1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2020 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bfd_boolean file_mips_opts_checked
= FALSE
;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
298 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
310 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static struct hash_control
*op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static struct hash_control
*mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static struct hash_control
*micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* Arrays of operands for each instruction. */
816 #define MAX_OPERANDS 6
817 struct mips_operand_array
819 const struct mips_operand
*operand
[MAX_OPERANDS
];
821 static struct mips_operand_array
*mips_operands
;
822 static struct mips_operand_array
*mips16_operands
;
823 static struct mips_operand_array
*micromips_operands
;
825 /* Nop instructions used by emit_nop. */
826 static struct mips_cl_insn nop_insn
;
827 static struct mips_cl_insn mips16_nop_insn
;
828 static struct mips_cl_insn micromips_nop16_insn
;
829 static struct mips_cl_insn micromips_nop32_insn
;
831 /* Sync instructions used by insert sync. */
832 static struct mips_cl_insn sync_insn
;
834 /* The appropriate nop for the current mode. */
835 #define NOP_INSN (mips_opts.mips16 \
837 : (mips_opts.micromips \
838 ? (mips_opts.insn32 \
839 ? µmips_nop32_insn \
840 : µmips_nop16_insn) \
843 /* The size of NOP_INSN in bytes. */
844 #define NOP_INSN_SIZE ((mips_opts.mips16 \
845 || (mips_opts.micromips && !mips_opts.insn32)) \
848 /* If this is set, it points to a frag holding nop instructions which
849 were inserted before the start of a noreorder section. If those
850 nops turn out to be unnecessary, the size of the frag can be
852 static fragS
*prev_nop_frag
;
854 /* The number of nop instructions we created in prev_nop_frag. */
855 static int prev_nop_frag_holds
;
857 /* The number of nop instructions that we know we need in
859 static int prev_nop_frag_required
;
861 /* The number of instructions we've seen since prev_nop_frag. */
862 static int prev_nop_frag_since
;
864 /* Relocations against symbols are sometimes done in two parts, with a HI
865 relocation and a LO relocation. Each relocation has only 16 bits of
866 space to store an addend. This means that in order for the linker to
867 handle carries correctly, it must be able to locate both the HI and
868 the LO relocation. This means that the relocations must appear in
869 order in the relocation table.
871 In order to implement this, we keep track of each unmatched HI
872 relocation. We then sort them so that they immediately precede the
873 corresponding LO relocation. */
878 struct mips_hi_fixup
*next
;
881 /* The section this fixup is in. */
885 /* The list of unmatched HI relocs. */
887 static struct mips_hi_fixup
*mips_hi_fixup_list
;
889 /* The frag containing the last explicit relocation operator.
890 Null if explicit relocations have not been used. */
892 static fragS
*prev_reloc_op_frag
;
894 /* Map mips16 register numbers to normal MIPS register numbers. */
896 static const unsigned int mips16_to_32_reg_map
[] =
898 16, 17, 2, 3, 4, 5, 6, 7
901 /* Map microMIPS register numbers to normal MIPS register numbers. */
903 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
905 /* The microMIPS registers with type h. */
906 static const unsigned int micromips_to_32_reg_h_map1
[] =
908 5, 5, 6, 4, 4, 4, 4, 4
910 static const unsigned int micromips_to_32_reg_h_map2
[] =
912 6, 7, 7, 21, 22, 5, 6, 7
915 /* The microMIPS registers with type m. */
916 static const unsigned int micromips_to_32_reg_m_map
[] =
918 0, 17, 2, 3, 16, 18, 19, 20
921 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
923 /* Classifies the kind of instructions we're interested in when
924 implementing -mfix-vr4120. */
925 enum fix_vr4120_class
933 NUM_FIX_VR4120_CLASSES
936 /* ...likewise -mfix-loongson2f-jump. */
937 static bfd_boolean mips_fix_loongson2f_jump
;
939 /* ...likewise -mfix-loongson2f-nop. */
940 static bfd_boolean mips_fix_loongson2f_nop
;
942 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
943 static bfd_boolean mips_fix_loongson2f
;
945 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
946 there must be at least one other instruction between an instruction
947 of type X and an instruction of type Y. */
948 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
950 /* True if -mfix-vr4120 is in force. */
951 static int mips_fix_vr4120
;
953 /* ...likewise -mfix-vr4130. */
954 static int mips_fix_vr4130
;
956 /* ...likewise -mfix-24k. */
957 static int mips_fix_24k
;
959 /* ...likewise -mfix-rm7000 */
960 static int mips_fix_rm7000
;
962 /* ...likewise -mfix-cn63xxp1 */
963 static bfd_boolean mips_fix_cn63xxp1
;
965 /* ...likewise -mfix-r5900 */
966 static bfd_boolean mips_fix_r5900
;
967 static bfd_boolean mips_fix_r5900_explicit
;
969 /* ...likewise -mfix-loongson3-llsc. */
970 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
972 /* We don't relax branches by default, since this causes us to expand
973 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
974 fail to compute the offset before expanding the macro to the most
975 efficient expansion. */
977 static int mips_relax_branch
;
979 /* TRUE if checks are suppressed for invalid branches between ISA modes.
980 Needed for broken assembly produced by some GCC versions and some
981 sloppy code out there, where branches to data labels are present. */
982 static bfd_boolean mips_ignore_branch_isa
;
984 /* The expansion of many macros depends on the type of symbol that
985 they refer to. For example, when generating position-dependent code,
986 a macro that refers to a symbol may have two different expansions,
987 one which uses GP-relative addresses and one which uses absolute
988 addresses. When generating SVR4-style PIC, a macro may have
989 different expansions for local and global symbols.
991 We handle these situations by generating both sequences and putting
992 them in variant frags. In position-dependent code, the first sequence
993 will be the GP-relative one and the second sequence will be the
994 absolute one. In SVR4 PIC, the first sequence will be for global
995 symbols and the second will be for local symbols.
997 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
998 SECOND are the lengths of the two sequences in bytes. These fields
999 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
1000 the subtype has the following flags:
1003 Set if generating PIC code.
1006 Set if it has been decided that we should use the second
1007 sequence instead of the first.
1010 Set in the first variant frag if the macro's second implementation
1011 is longer than its first. This refers to the macro as a whole,
1012 not an individual relaxation.
1015 Set in the first variant frag if the macro appeared in a .set nomacro
1016 block and if one alternative requires a warning but the other does not.
1019 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1022 RELAX_DELAY_SLOT_16BIT
1023 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1026 RELAX_DELAY_SLOT_SIZE_FIRST
1027 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1028 the macro is of the wrong size for the branch delay slot.
1030 RELAX_DELAY_SLOT_SIZE_SECOND
1031 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1032 the macro is of the wrong size for the branch delay slot.
1034 The frag's "opcode" points to the first fixup for relaxable code.
1036 Relaxable macros are generated using a sequence such as:
1038 relax_start (SYMBOL);
1039 ... generate first expansion ...
1041 ... generate second expansion ...
1044 The code and fixups for the unwanted alternative are discarded
1045 by md_convert_frag. */
1046 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1047 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1049 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1050 #define RELAX_SECOND(X) ((X) & 0xff)
1051 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1052 #define RELAX_USE_SECOND 0x20000
1053 #define RELAX_SECOND_LONGER 0x40000
1054 #define RELAX_NOMACRO 0x80000
1055 #define RELAX_DELAY_SLOT 0x100000
1056 #define RELAX_DELAY_SLOT_16BIT 0x200000
1057 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1058 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1060 /* Branch without likely bit. If label is out of range, we turn:
1062 beq reg1, reg2, label
1072 with the following opcode replacements:
1079 bltzal <-> bgezal (with jal label instead of j label)
1081 Even though keeping the delay slot instruction in the delay slot of
1082 the branch would be more efficient, it would be very tricky to do
1083 correctly, because we'd have to introduce a variable frag *after*
1084 the delay slot instruction, and expand that instead. Let's do it
1085 the easy way for now, even if the branch-not-taken case now costs
1086 one additional instruction. Out-of-range branches are not supposed
1087 to be common, anyway.
1089 Branch likely. If label is out of range, we turn:
1091 beql reg1, reg2, label
1092 delay slot (annulled if branch not taken)
1101 delay slot (executed only if branch taken)
1104 It would be possible to generate a shorter sequence by losing the
1105 likely bit, generating something like:
1110 delay slot (executed only if branch taken)
1122 bltzall -> bgezal (with jal label instead of j label)
1123 bgezall -> bltzal (ditto)
1126 but it's not clear that it would actually improve performance. */
1127 #define RELAX_BRANCH_ENCODE(at, pic, \
1128 uncond, likely, link, toofar) \
1129 ((relax_substateT) \
1132 | ((pic) ? 0x20 : 0) \
1133 | ((toofar) ? 0x40 : 0) \
1134 | ((link) ? 0x80 : 0) \
1135 | ((likely) ? 0x100 : 0) \
1136 | ((uncond) ? 0x200 : 0)))
1137 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1138 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1139 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1140 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1141 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1142 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1143 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1145 /* For mips16 code, we use an entirely different form of relaxation.
1146 mips16 supports two versions of most instructions which take
1147 immediate values: a small one which takes some small value, and a
1148 larger one which takes a 16 bit value. Since branches also follow
1149 this pattern, relaxing these values is required.
1151 We can assemble both mips16 and normal MIPS code in a single
1152 object. Therefore, we need to support this type of relaxation at
1153 the same time that we support the relaxation described above. We
1154 use the high bit of the subtype field to distinguish these cases.
1156 The information we store for this type of relaxation is the
1157 argument code found in the opcode file for this relocation, whether
1158 the user explicitly requested a small or extended form, and whether
1159 the relocation is in a jump or jal delay slot. That tells us the
1160 size of the value, and how it should be stored. We also store
1161 whether the fragment is considered to be extended or not. We also
1162 store whether this is known to be a branch to a different section,
1163 whether we have tried to relax this frag yet, and whether we have
1164 ever extended a PC relative fragment because of a shift count. */
1165 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1170 | ((e2) ? 0x100 : 0) \
1171 | ((pic) ? 0x200 : 0) \
1172 | ((sym32) ? 0x400 : 0) \
1173 | ((nomacro) ? 0x800 : 0) \
1174 | ((small) ? 0x1000 : 0) \
1175 | ((ext) ? 0x2000 : 0) \
1176 | ((dslot) ? 0x4000 : 0) \
1177 | ((jal_dslot) ? 0x8000 : 0))
1179 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1180 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1181 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1182 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1183 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1184 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1185 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1186 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1187 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1188 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1190 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1191 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1192 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1193 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1194 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1195 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1196 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1197 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1198 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1200 /* For microMIPS code, we use relaxation similar to one we use for
1201 MIPS16 code. Some instructions that take immediate values support
1202 two encodings: a small one which takes some small value, and a
1203 larger one which takes a 16 bit value. As some branches also follow
1204 this pattern, relaxing these values is required.
1206 We can assemble both microMIPS and normal MIPS code in a single
1207 object. Therefore, we need to support this type of relaxation at
1208 the same time that we support the relaxation described above. We
1209 use one of the high bits of the subtype field to distinguish these
1212 The information we store for this type of relaxation is the argument
1213 code found in the opcode file for this relocation, the register
1214 selected as the assembler temporary, whether in the 32-bit
1215 instruction mode, whether the branch is unconditional, whether it is
1216 compact, whether there is no delay-slot instruction available to fill
1217 in, whether it stores the link address implicitly in $ra, whether
1218 relaxation of out-of-range 32-bit branches to a sequence of
1219 instructions is enabled, and whether the displacement of a branch is
1220 too large to fit as an immediate argument of a 16-bit and a 32-bit
1221 branch, respectively. */
1222 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1223 uncond, compact, link, nods, \
1224 relax32, toofar16, toofar32) \
1227 | (((at) & 0x1f) << 8) \
1228 | ((insn32) ? 0x2000 : 0) \
1229 | ((pic) ? 0x4000 : 0) \
1230 | ((uncond) ? 0x8000 : 0) \
1231 | ((compact) ? 0x10000 : 0) \
1232 | ((link) ? 0x20000 : 0) \
1233 | ((nods) ? 0x40000 : 0) \
1234 | ((relax32) ? 0x80000 : 0) \
1235 | ((toofar16) ? 0x100000 : 0) \
1236 | ((toofar32) ? 0x200000 : 0))
1237 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1238 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1239 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1240 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1241 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1242 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1243 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1244 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1245 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1246 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1248 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1249 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1250 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1251 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1252 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1253 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1255 /* Sign-extend 16-bit value X. */
1256 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1258 /* Is the given value a sign-extended 32-bit value? */
1259 #define IS_SEXT_32BIT_NUM(x) \
1260 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1261 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1263 /* Is the given value a sign-extended 16-bit value? */
1264 #define IS_SEXT_16BIT_NUM(x) \
1265 (((x) &~ (offsetT) 0x7fff) == 0 \
1266 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1268 /* Is the given value a sign-extended 12-bit value? */
1269 #define IS_SEXT_12BIT_NUM(x) \
1270 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1272 /* Is the given value a sign-extended 9-bit value? */
1273 #define IS_SEXT_9BIT_NUM(x) \
1274 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1276 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1277 #define IS_ZEXT_32BIT_NUM(x) \
1278 (((x) &~ (offsetT) 0xffffffff) == 0 \
1279 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1281 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1283 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1284 (((STRUCT) >> (SHIFT)) & (MASK))
1286 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1287 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1289 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1290 : EXTRACT_BITS ((INSN).insn_opcode, \
1291 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1292 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1293 EXTRACT_BITS ((INSN).insn_opcode, \
1294 MIPS16OP_MASK_##FIELD, \
1295 MIPS16OP_SH_##FIELD)
1297 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1298 #define MIPS16_EXTEND (0xf000U << 16)
1300 /* Whether or not we are emitting a branch-likely macro. */
1301 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1303 /* Global variables used when generating relaxable macros. See the
1304 comment above RELAX_ENCODE for more details about how relaxation
1307 /* 0 if we're not emitting a relaxable macro.
1308 1 if we're emitting the first of the two relaxation alternatives.
1309 2 if we're emitting the second alternative. */
1312 /* The first relaxable fixup in the current frag. (In other words,
1313 the first fixup that refers to relaxable code.) */
1316 /* sizes[0] says how many bytes of the first alternative are stored in
1317 the current frag. Likewise sizes[1] for the second alternative. */
1318 unsigned int sizes
[2];
1320 /* The symbol on which the choice of sequence depends. */
1324 /* Global variables used to decide whether a macro needs a warning. */
1326 /* True if the macro is in a branch delay slot. */
1327 bfd_boolean delay_slot_p
;
1329 /* Set to the length in bytes required if the macro is in a delay slot
1330 that requires a specific length of instruction, otherwise zero. */
1331 unsigned int delay_slot_length
;
1333 /* For relaxable macros, sizes[0] is the length of the first alternative
1334 in bytes and sizes[1] is the length of the second alternative.
1335 For non-relaxable macros, both elements give the length of the
1337 unsigned int sizes
[2];
1339 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1340 instruction of the first alternative in bytes and first_insn_sizes[1]
1341 is the length of the first instruction of the second alternative.
1342 For non-relaxable macros, both elements give the length of the first
1343 instruction in bytes.
1345 Set to zero if we haven't yet seen the first instruction. */
1346 unsigned int first_insn_sizes
[2];
1348 /* For relaxable macros, insns[0] is the number of instructions for the
1349 first alternative and insns[1] is the number of instructions for the
1352 For non-relaxable macros, both elements give the number of
1353 instructions for the macro. */
1354 unsigned int insns
[2];
1356 /* The first variant frag for this macro. */
1358 } mips_macro_warning
;
1360 /* Prototypes for static functions. */
1362 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1364 static void append_insn
1365 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1366 bfd_boolean expansionp
);
1367 static void mips_no_prev_insn (void);
1368 static void macro_build (expressionS
*, const char *, const char *, ...);
1369 static void mips16_macro_build
1370 (expressionS
*, const char *, const char *, va_list *);
1371 static void load_register (int, expressionS
*, int);
1372 static void macro_start (void);
1373 static void macro_end (void);
1374 static void macro (struct mips_cl_insn
*ip
, char *str
);
1375 static void mips16_macro (struct mips_cl_insn
* ip
);
1376 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1377 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1378 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1379 static void mips16_immed
1380 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1381 unsigned int, unsigned long *);
1382 static size_t my_getSmallExpression
1383 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1384 static void my_getExpression (expressionS
*, char *);
1385 static void s_align (int);
1386 static void s_change_sec (int);
1387 static void s_change_section (int);
1388 static void s_cons (int);
1389 static void s_float_cons (int);
1390 static void s_mips_globl (int);
1391 static void s_option (int);
1392 static void s_mipsset (int);
1393 static void s_abicalls (int);
1394 static void s_cpload (int);
1395 static void s_cpsetup (int);
1396 static void s_cplocal (int);
1397 static void s_cprestore (int);
1398 static void s_cpreturn (int);
1399 static void s_dtprelword (int);
1400 static void s_dtpreldword (int);
1401 static void s_tprelword (int);
1402 static void s_tpreldword (int);
1403 static void s_gpvalue (int);
1404 static void s_gpword (int);
1405 static void s_gpdword (int);
1406 static void s_ehword (int);
1407 static void s_cpadd (int);
1408 static void s_insn (int);
1409 static void s_nan (int);
1410 static void s_module (int);
1411 static void s_mips_ent (int);
1412 static void s_mips_end (int);
1413 static void s_mips_frame (int);
1414 static void s_mips_mask (int reg_type
);
1415 static void s_mips_stab (int);
1416 static void s_mips_weakext (int);
1417 static void s_mips_file (int);
1418 static void s_mips_loc (int);
1419 static bfd_boolean
pic_need_relax (symbolS
*);
1420 static int relaxed_branch_length (fragS
*, asection
*, int);
1421 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1422 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1423 static void file_mips_check_options (void);
1425 /* Table and functions used to map between CPU/ISA names, and
1426 ISA levels, and CPU numbers. */
1428 struct mips_cpu_info
1430 const char *name
; /* CPU or ISA name. */
1431 int flags
; /* MIPS_CPU_* flags. */
1432 int ase
; /* Set of ASEs implemented by the CPU. */
1433 int isa
; /* ISA level. */
1434 int cpu
; /* CPU number (default CPU if ISA). */
1437 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1439 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1440 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1441 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1443 /* Command-line options. */
1444 const char *md_shortopts
= "O::g::G:";
1448 OPTION_MARCH
= OPTION_MD_BASE
,
1480 OPTION_NO_SMARTMIPS
,
1490 OPTION_NO_MICROMIPS
,
1505 OPTION_M7000_HILO_FIX
,
1506 OPTION_MNO_7000_HILO_FIX
,
1510 OPTION_NO_FIX_RM7000
,
1511 OPTION_FIX_LOONGSON3_LLSC
,
1512 OPTION_NO_FIX_LOONGSON3_LLSC
,
1513 OPTION_FIX_LOONGSON2F_JUMP
,
1514 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1515 OPTION_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_LOONGSON2F_NOP
,
1518 OPTION_NO_FIX_VR4120
,
1520 OPTION_NO_FIX_VR4130
,
1521 OPTION_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_CN63XXP1
,
1524 OPTION_NO_FIX_R5900
,
1531 OPTION_CONSTRUCT_FLOATS
,
1532 OPTION_NO_CONSTRUCT_FLOATS
,
1536 OPTION_RELAX_BRANCH
,
1537 OPTION_NO_RELAX_BRANCH
,
1538 OPTION_IGNORE_BRANCH_ISA
,
1539 OPTION_NO_IGNORE_BRANCH_ISA
,
1548 OPTION_SINGLE_FLOAT
,
1549 OPTION_DOUBLE_FLOAT
,
1562 OPTION_MVXWORKS_PIC
,
1565 OPTION_NO_ODD_SPREG
,
1568 OPTION_LOONGSON_MMI
,
1569 OPTION_NO_LOONGSON_MMI
,
1570 OPTION_LOONGSON_CAM
,
1571 OPTION_NO_LOONGSON_CAM
,
1572 OPTION_LOONGSON_EXT
,
1573 OPTION_NO_LOONGSON_EXT
,
1574 OPTION_LOONGSON_EXT2
,
1575 OPTION_NO_LOONGSON_EXT2
,
1579 struct option md_longopts
[] =
1581 /* Options which specify architecture. */
1582 {"march", required_argument
, NULL
, OPTION_MARCH
},
1583 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1584 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1585 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1586 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1587 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1588 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1589 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1590 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1591 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1592 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1593 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1594 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1595 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1596 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1597 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1598 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1599 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1601 /* Options which specify Application Specific Extensions (ASEs). */
1602 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1603 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1604 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1605 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1606 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1607 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1608 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1609 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1610 {"mmt", no_argument
, NULL
, OPTION_MT
},
1611 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1612 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1613 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1614 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1615 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1616 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1617 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1618 {"meva", no_argument
, NULL
, OPTION_EVA
},
1619 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1620 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1621 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1622 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1623 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1624 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1625 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1626 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1627 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1628 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1629 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1630 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1631 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1632 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1633 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1634 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1635 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1636 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1637 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1638 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1639 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1640 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1641 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1642 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1643 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1645 /* Old-style architecture options. Don't add more of these. */
1646 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1647 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1648 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1649 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1650 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1651 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1652 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1653 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1655 /* Options which enable bug fixes. */
1656 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1657 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1658 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1659 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1660 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1661 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1662 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1663 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1664 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1665 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1666 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1667 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1668 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1669 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1670 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1671 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1672 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1673 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1674 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1675 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1676 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1678 /* Miscellaneous options. */
1679 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1680 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1681 {"break", no_argument
, NULL
, OPTION_BREAK
},
1682 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1683 {"EB", no_argument
, NULL
, OPTION_EB
},
1684 {"EL", no_argument
, NULL
, OPTION_EL
},
1685 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1686 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1687 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1688 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1689 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1690 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1691 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1692 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1693 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1694 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1695 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1696 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1697 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1698 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1699 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1700 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1701 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1702 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1703 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1704 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1705 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1706 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1707 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1709 /* Strictly speaking this next option is ELF specific,
1710 but we allow it for other ports as well in order to
1711 make testing easier. */
1712 {"32", no_argument
, NULL
, OPTION_32
},
1714 /* ELF-specific options. */
1715 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1716 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1717 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1718 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1719 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1720 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1721 {"n32", no_argument
, NULL
, OPTION_N32
},
1722 {"64", no_argument
, NULL
, OPTION_64
},
1723 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1724 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1725 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1726 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1727 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1728 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1730 {NULL
, no_argument
, NULL
, 0}
1732 size_t md_longopts_size
= sizeof (md_longopts
);
1734 /* Information about either an Application Specific Extension or an
1735 optional architecture feature that, for simplicity, we treat in the
1736 same way as an ASE. */
1739 /* The name of the ASE, used in both the command-line and .set options. */
1742 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1743 and 64-bit architectures, the flags here refer to the subset that
1744 is available on both. */
1747 /* The ASE_* flag used for instructions that are available on 64-bit
1748 architectures but that are not included in FLAGS. */
1749 unsigned int flags64
;
1751 /* The command-line options that turn the ASE on and off. */
1755 /* The minimum required architecture revisions for MIPS32, MIPS64,
1756 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1759 int micromips32_rev
;
1760 int micromips64_rev
;
1762 /* The architecture where the ASE was removed or -1 if the extension has not
1767 /* A table of all supported ASEs. */
1768 static const struct mips_ase mips_ases
[] = {
1769 { "dsp", ASE_DSP
, ASE_DSP64
,
1770 OPTION_DSP
, OPTION_NO_DSP
,
1774 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1775 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1779 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1780 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1784 { "eva", ASE_EVA
, 0,
1785 OPTION_EVA
, OPTION_NO_EVA
,
1789 { "mcu", ASE_MCU
, 0,
1790 OPTION_MCU
, OPTION_NO_MCU
,
1794 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1795 { "mdmx", ASE_MDMX
, 0,
1796 OPTION_MDMX
, OPTION_NO_MDMX
,
1800 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1801 { "mips3d", ASE_MIPS3D
, 0,
1802 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1807 OPTION_MT
, OPTION_NO_MT
,
1811 { "smartmips", ASE_SMARTMIPS
, 0,
1812 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1816 { "virt", ASE_VIRT
, ASE_VIRT64
,
1817 OPTION_VIRT
, OPTION_NO_VIRT
,
1821 { "msa", ASE_MSA
, ASE_MSA64
,
1822 OPTION_MSA
, OPTION_NO_MSA
,
1826 { "xpa", ASE_XPA
, 0,
1827 OPTION_XPA
, OPTION_NO_XPA
,
1831 { "mips16e2", ASE_MIPS16E2
, 0,
1832 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1836 { "crc", ASE_CRC
, ASE_CRC64
,
1837 OPTION_CRC
, OPTION_NO_CRC
,
1841 { "ginv", ASE_GINV
, 0,
1842 OPTION_GINV
, OPTION_NO_GINV
,
1846 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1847 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1851 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1852 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1856 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1857 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1861 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1862 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1867 /* The set of ASEs that require -mfp64. */
1868 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1870 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1871 static const unsigned int mips_ase_groups
[] = {
1872 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1873 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1878 The following pseudo-ops from the Kane and Heinrich MIPS book
1879 should be defined here, but are currently unsupported: .alias,
1880 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1882 The following pseudo-ops from the Kane and Heinrich MIPS book are
1883 specific to the type of debugging information being generated, and
1884 should be defined by the object format: .aent, .begin, .bend,
1885 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1888 The following pseudo-ops from the Kane and Heinrich MIPS book are
1889 not MIPS CPU specific, but are also not specific to the object file
1890 format. This file is probably the best place to define them, but
1891 they are not currently supported: .asm0, .endr, .lab, .struct. */
1893 static const pseudo_typeS mips_pseudo_table
[] =
1895 /* MIPS specific pseudo-ops. */
1896 {"option", s_option
, 0},
1897 {"set", s_mipsset
, 0},
1898 {"rdata", s_change_sec
, 'r'},
1899 {"sdata", s_change_sec
, 's'},
1900 {"livereg", s_ignore
, 0},
1901 {"abicalls", s_abicalls
, 0},
1902 {"cpload", s_cpload
, 0},
1903 {"cpsetup", s_cpsetup
, 0},
1904 {"cplocal", s_cplocal
, 0},
1905 {"cprestore", s_cprestore
, 0},
1906 {"cpreturn", s_cpreturn
, 0},
1907 {"dtprelword", s_dtprelword
, 0},
1908 {"dtpreldword", s_dtpreldword
, 0},
1909 {"tprelword", s_tprelword
, 0},
1910 {"tpreldword", s_tpreldword
, 0},
1911 {"gpvalue", s_gpvalue
, 0},
1912 {"gpword", s_gpword
, 0},
1913 {"gpdword", s_gpdword
, 0},
1914 {"ehword", s_ehword
, 0},
1915 {"cpadd", s_cpadd
, 0},
1916 {"insn", s_insn
, 0},
1918 {"module", s_module
, 0},
1920 /* Relatively generic pseudo-ops that happen to be used on MIPS
1922 {"asciiz", stringer
, 8 + 1},
1923 {"bss", s_change_sec
, 'b'},
1925 {"half", s_cons
, 1},
1926 {"dword", s_cons
, 3},
1927 {"weakext", s_mips_weakext
, 0},
1928 {"origin", s_org
, 0},
1929 {"repeat", s_rept
, 0},
1931 /* For MIPS this is non-standard, but we define it for consistency. */
1932 {"sbss", s_change_sec
, 'B'},
1934 /* These pseudo-ops are defined in read.c, but must be overridden
1935 here for one reason or another. */
1936 {"align", s_align
, 0},
1937 {"byte", s_cons
, 0},
1938 {"data", s_change_sec
, 'd'},
1939 {"double", s_float_cons
, 'd'},
1940 {"float", s_float_cons
, 'f'},
1941 {"globl", s_mips_globl
, 0},
1942 {"global", s_mips_globl
, 0},
1943 {"hword", s_cons
, 1},
1945 {"long", s_cons
, 2},
1946 {"octa", s_cons
, 4},
1947 {"quad", s_cons
, 3},
1948 {"section", s_change_section
, 0},
1949 {"short", s_cons
, 1},
1950 {"single", s_float_cons
, 'f'},
1951 {"stabd", s_mips_stab
, 'd'},
1952 {"stabn", s_mips_stab
, 'n'},
1953 {"stabs", s_mips_stab
, 's'},
1954 {"text", s_change_sec
, 't'},
1955 {"word", s_cons
, 2},
1957 { "extern", ecoff_directive_extern
, 0},
1962 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1964 /* These pseudo-ops should be defined by the object file format.
1965 However, a.out doesn't support them, so we have versions here. */
1966 {"aent", s_mips_ent
, 1},
1967 {"bgnb", s_ignore
, 0},
1968 {"end", s_mips_end
, 0},
1969 {"endb", s_ignore
, 0},
1970 {"ent", s_mips_ent
, 0},
1971 {"file", s_mips_file
, 0},
1972 {"fmask", s_mips_mask
, 'F'},
1973 {"frame", s_mips_frame
, 0},
1974 {"loc", s_mips_loc
, 0},
1975 {"mask", s_mips_mask
, 'R'},
1976 {"verstamp", s_ignore
, 0},
1980 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1981 purpose of the `.dc.a' internal pseudo-op. */
1984 mips_address_bytes (void)
1986 file_mips_check_options ();
1987 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1990 extern void pop_insert (const pseudo_typeS
*);
1993 mips_pop_insert (void)
1995 pop_insert (mips_pseudo_table
);
1996 if (! ECOFF_DEBUGGING
)
1997 pop_insert (mips_nonecoff_pseudo_table
);
2000 /* Symbols labelling the current insn. */
2002 struct insn_label_list
2004 struct insn_label_list
*next
;
2008 static struct insn_label_list
*free_insn_labels
;
2009 #define label_list tc_segment_info_data.labels
2011 static void mips_clear_insn_labels (void);
2012 static void mips_mark_labels (void);
2013 static void mips_compressed_mark_labels (void);
2016 mips_clear_insn_labels (void)
2018 struct insn_label_list
**pl
;
2019 segment_info_type
*si
;
2023 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2026 si
= seg_info (now_seg
);
2027 *pl
= si
->label_list
;
2028 si
->label_list
= NULL
;
2032 /* Mark instruction labels in MIPS16/microMIPS mode. */
2035 mips_mark_labels (void)
2037 if (HAVE_CODE_COMPRESSION
)
2038 mips_compressed_mark_labels ();
2041 static char *expr_end
;
2043 /* An expression in a macro instruction. This is set by mips_ip and
2044 mips16_ip and when populated is always an O_constant. */
2046 static expressionS imm_expr
;
2048 /* The relocatable field in an instruction and the relocs associated
2049 with it. These variables are used for instructions like LUI and
2050 JAL as well as true offsets. They are also used for address
2051 operands in macros. */
2053 static expressionS offset_expr
;
2054 static bfd_reloc_code_real_type offset_reloc
[3]
2055 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2057 /* This is set to the resulting size of the instruction to be produced
2058 by mips16_ip if an explicit extension is used or by mips_ip if an
2059 explicit size is supplied. */
2061 static unsigned int forced_insn_length
;
2063 /* True if we are assembling an instruction. All dot symbols defined during
2064 this time should be treated as code labels. */
2066 static bfd_boolean mips_assembling_insn
;
2068 /* The pdr segment for per procedure frame/regmask info. Not used for
2071 static segT pdr_seg
;
2073 /* The default target format to use. */
2075 #if defined (TE_FreeBSD)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2077 #elif defined (TE_TMIPS)
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2080 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2084 mips_target_format (void)
2086 switch (OUTPUT_FLAVOR
)
2088 case bfd_target_elf_flavour
:
2090 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2091 return (target_big_endian
2092 ? "elf32-bigmips-vxworks"
2093 : "elf32-littlemips-vxworks");
2095 return (target_big_endian
2096 ? (HAVE_64BIT_OBJECTS
2097 ? ELF_TARGET ("elf64-", "big")
2099 ? ELF_TARGET ("elf32-n", "big")
2100 : ELF_TARGET ("elf32-", "big")))
2101 : (HAVE_64BIT_OBJECTS
2102 ? ELF_TARGET ("elf64-", "little")
2104 ? ELF_TARGET ("elf32-n", "little")
2105 : ELF_TARGET ("elf32-", "little"))));
2112 /* Return the ISA revision that is currently in use, or 0 if we are
2113 generating code for MIPS V or below. */
2118 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2121 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2124 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2127 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2130 /* microMIPS implies revision 2 or above. */
2131 if (mips_opts
.micromips
)
2134 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2140 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2143 mips_ase_mask (unsigned int flags
)
2147 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2148 if (flags
& mips_ase_groups
[i
])
2149 flags
|= mips_ase_groups
[i
];
2153 /* Check whether the current ISA supports ASE. Issue a warning if
2157 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2161 static unsigned int warned_isa
;
2162 static unsigned int warned_fp32
;
2164 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2165 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2167 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2168 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2169 && (warned_isa
& ase
->flags
) != ase
->flags
)
2171 warned_isa
|= ase
->flags
;
2172 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2173 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2175 as_warn (_("the %d-bit %s architecture does not support the"
2176 " `%s' extension"), size
, base
, ase
->name
);
2178 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2179 ase
->name
, base
, size
, min_rev
);
2181 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2182 && (warned_isa
& ase
->flags
) != ase
->flags
)
2184 warned_isa
|= ase
->flags
;
2185 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2186 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2187 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2188 ase
->name
, base
, size
, ase
->rem_rev
);
2191 if ((ase
->flags
& FP64_ASES
)
2192 && mips_opts
.fp
!= 64
2193 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2195 warned_fp32
|= ase
->flags
;
2196 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2200 /* Check all enabled ASEs to see whether they are supported by the
2201 chosen architecture. */
2204 mips_check_isa_supports_ases (void)
2206 unsigned int i
, mask
;
2208 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2210 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2211 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2212 mips_check_isa_supports_ase (&mips_ases
[i
]);
2216 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2217 that were affected. */
2220 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2221 bfd_boolean enabled_p
)
2225 mask
= mips_ase_mask (ase
->flags
);
2228 /* Clear combination ASE flags, which need to be recalculated based on
2229 updated regular ASE settings. */
2230 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
| ASE_EVA_R6
);
2233 opts
->ase
|= ase
->flags
;
2235 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2236 instructions which are only valid when both ASEs are enabled.
2237 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2238 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2240 opts
->ase
|= ASE_XPA_VIRT
;
2241 mask
|= ASE_XPA_VIRT
;
2243 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2245 opts
->ase
|= ASE_MIPS16E2_MT
;
2246 mask
|= ASE_MIPS16E2_MT
;
2249 /* The EVA Extension has instructions which are only valid when the R6 ISA
2250 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2252 if (((opts
->ase
& ASE_EVA
) != 0) && ISA_IS_R6 (opts
->isa
))
2254 opts
->ase
|= ASE_EVA_R6
;
2261 /* Return the ASE called NAME, or null if none. */
2263 static const struct mips_ase
*
2264 mips_lookup_ase (const char *name
)
2268 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2269 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2270 return &mips_ases
[i
];
2274 /* Return the length of a microMIPS instruction in bytes. If bits of
2275 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2276 otherwise it is a 32-bit instruction. */
2278 static inline unsigned int
2279 micromips_insn_length (const struct mips_opcode
*mo
)
2281 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2284 /* Return the length of MIPS16 instruction OPCODE. */
2286 static inline unsigned int
2287 mips16_opcode_length (unsigned long opcode
)
2289 return (opcode
>> 16) == 0 ? 2 : 4;
2292 /* Return the length of instruction INSN. */
2294 static inline unsigned int
2295 insn_length (const struct mips_cl_insn
*insn
)
2297 if (mips_opts
.micromips
)
2298 return micromips_insn_length (insn
->insn_mo
);
2299 else if (mips_opts
.mips16
)
2300 return mips16_opcode_length (insn
->insn_opcode
);
2305 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2308 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2313 insn
->insn_opcode
= mo
->match
;
2316 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2317 insn
->fixp
[i
] = NULL
;
2318 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2319 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2320 insn
->mips16_absolute_jump_p
= 0;
2321 insn
->complete_p
= 0;
2322 insn
->cleared_p
= 0;
2325 /* Get a list of all the operands in INSN. */
2327 static const struct mips_operand_array
*
2328 insn_operands (const struct mips_cl_insn
*insn
)
2330 if (insn
->insn_mo
>= &mips_opcodes
[0]
2331 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2332 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2334 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2335 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2336 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2338 if (insn
->insn_mo
>= µmips_opcodes
[0]
2339 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2340 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2345 /* Get a description of operand OPNO of INSN. */
2347 static const struct mips_operand
*
2348 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2350 const struct mips_operand_array
*operands
;
2352 operands
= insn_operands (insn
);
2353 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2355 return operands
->operand
[opno
];
2358 /* Install UVAL as the value of OPERAND in INSN. */
2361 insn_insert_operand (struct mips_cl_insn
*insn
,
2362 const struct mips_operand
*operand
, unsigned int uval
)
2364 if (mips_opts
.mips16
2365 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2366 && mips_opcode_32bit_p (insn
->insn_mo
))
2367 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2369 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2372 /* Extract the value of OPERAND from INSN. */
2374 static inline unsigned
2375 insn_extract_operand (const struct mips_cl_insn
*insn
,
2376 const struct mips_operand
*operand
)
2378 return mips_extract_operand (operand
, insn
->insn_opcode
);
2381 /* Record the current MIPS16/microMIPS mode in now_seg. */
2384 mips_record_compressed_mode (void)
2386 segment_info_type
*si
;
2388 si
= seg_info (now_seg
);
2389 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2390 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2391 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2392 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2395 /* Read a standard MIPS instruction from BUF. */
2397 static unsigned long
2398 read_insn (char *buf
)
2400 if (target_big_endian
)
2401 return bfd_getb32 ((bfd_byte
*) buf
);
2403 return bfd_getl32 ((bfd_byte
*) buf
);
2406 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2410 write_insn (char *buf
, unsigned int insn
)
2412 md_number_to_chars (buf
, insn
, 4);
2416 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2417 has length LENGTH. */
2419 static unsigned long
2420 read_compressed_insn (char *buf
, unsigned int length
)
2426 for (i
= 0; i
< length
; i
+= 2)
2429 if (target_big_endian
)
2430 insn
|= bfd_getb16 ((char *) buf
);
2432 insn
|= bfd_getl16 ((char *) buf
);
2438 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2439 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2442 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2446 for (i
= 0; i
< length
; i
+= 2)
2447 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2448 return buf
+ length
;
2451 /* Install INSN at the location specified by its "frag" and "where" fields. */
2454 install_insn (const struct mips_cl_insn
*insn
)
2456 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2457 if (HAVE_CODE_COMPRESSION
)
2458 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2460 write_insn (f
, insn
->insn_opcode
);
2461 mips_record_compressed_mode ();
2464 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2465 and install the opcode in the new location. */
2468 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2473 insn
->where
= where
;
2474 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2475 if (insn
->fixp
[i
] != NULL
)
2477 insn
->fixp
[i
]->fx_frag
= frag
;
2478 insn
->fixp
[i
]->fx_where
= where
;
2480 install_insn (insn
);
2483 /* Add INSN to the end of the output. */
2486 add_fixed_insn (struct mips_cl_insn
*insn
)
2488 char *f
= frag_more (insn_length (insn
));
2489 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2492 /* Start a variant frag and move INSN to the start of the variant part,
2493 marking it as fixed. The other arguments are as for frag_var. */
2496 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2497 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2499 frag_grow (max_chars
);
2500 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2502 frag_var (rs_machine_dependent
, max_chars
, var
,
2503 subtype
, symbol
, offset
, NULL
);
2506 /* Insert N copies of INSN into the history buffer, starting at
2507 position FIRST. Neither FIRST nor N need to be clipped. */
2510 insert_into_history (unsigned int first
, unsigned int n
,
2511 const struct mips_cl_insn
*insn
)
2513 if (mips_relax
.sequence
!= 2)
2517 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2519 history
[i
] = history
[i
- n
];
2525 /* Clear the error in insn_error. */
2528 clear_insn_error (void)
2530 memset (&insn_error
, 0, sizeof (insn_error
));
2533 /* Possibly record error message MSG for the current instruction.
2534 If the error is about a particular argument, ARGNUM is the 1-based
2535 number of that argument, otherwise it is 0. FORMAT is the format
2536 of MSG. Return true if MSG was used, false if the current message
2540 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2545 /* Give priority to errors against specific arguments, and to
2546 the first whole-instruction message. */
2552 /* Keep insn_error if it is against a later argument. */
2553 if (argnum
< insn_error
.min_argnum
)
2556 /* If both errors are against the same argument but are different,
2557 give up on reporting a specific error for this argument.
2558 See the comment about mips_insn_error for details. */
2559 if (argnum
== insn_error
.min_argnum
2561 && strcmp (insn_error
.msg
, msg
) != 0)
2564 insn_error
.min_argnum
+= 1;
2568 insn_error
.min_argnum
= argnum
;
2569 insn_error
.format
= format
;
2570 insn_error
.msg
= msg
;
2574 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2575 as for set_insn_error_format. */
2578 set_insn_error (int argnum
, const char *msg
)
2580 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2583 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2584 as for set_insn_error_format. */
2587 set_insn_error_i (int argnum
, const char *msg
, int i
)
2589 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2593 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2594 are as for set_insn_error_format. */
2597 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2599 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2601 insn_error
.u
.ss
[0] = s1
;
2602 insn_error
.u
.ss
[1] = s2
;
2606 /* Report the error in insn_error, which is against assembly code STR. */
2609 report_insn_error (const char *str
)
2611 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2613 switch (insn_error
.format
)
2620 as_bad (msg
, insn_error
.u
.i
, str
);
2624 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2628 free ((char *) msg
);
2631 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2632 the idea is to make it obvious at a glance that each errata is
2636 init_vr4120_conflicts (void)
2638 #define CONFLICT(FIRST, SECOND) \
2639 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2641 /* Errata 21 - [D]DIV[U] after [D]MACC */
2642 CONFLICT (MACC
, DIV
);
2643 CONFLICT (DMACC
, DIV
);
2645 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2646 CONFLICT (DMULT
, DMULT
);
2647 CONFLICT (DMULT
, DMACC
);
2648 CONFLICT (DMACC
, DMULT
);
2649 CONFLICT (DMACC
, DMACC
);
2651 /* Errata 24 - MT{LO,HI} after [D]MACC */
2652 CONFLICT (MACC
, MTHILO
);
2653 CONFLICT (DMACC
, MTHILO
);
2655 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2656 instruction is executed immediately after a MACC or DMACC
2657 instruction, the result of [either instruction] is incorrect." */
2658 CONFLICT (MACC
, MULT
);
2659 CONFLICT (MACC
, DMULT
);
2660 CONFLICT (DMACC
, MULT
);
2661 CONFLICT (DMACC
, DMULT
);
2663 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2664 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2665 DDIV or DDIVU instruction, the result of the MACC or
2666 DMACC instruction is incorrect.". */
2667 CONFLICT (DMULT
, MACC
);
2668 CONFLICT (DMULT
, DMACC
);
2669 CONFLICT (DIV
, MACC
);
2670 CONFLICT (DIV
, DMACC
);
2680 #define RNUM_MASK 0x00000ff
2681 #define RTYPE_MASK 0x0ffff00
2682 #define RTYPE_NUM 0x0000100
2683 #define RTYPE_FPU 0x0000200
2684 #define RTYPE_FCC 0x0000400
2685 #define RTYPE_VEC 0x0000800
2686 #define RTYPE_GP 0x0001000
2687 #define RTYPE_CP0 0x0002000
2688 #define RTYPE_PC 0x0004000
2689 #define RTYPE_ACC 0x0008000
2690 #define RTYPE_CCC 0x0010000
2691 #define RTYPE_VI 0x0020000
2692 #define RTYPE_VF 0x0040000
2693 #define RTYPE_R5900_I 0x0080000
2694 #define RTYPE_R5900_Q 0x0100000
2695 #define RTYPE_R5900_R 0x0200000
2696 #define RTYPE_R5900_ACC 0x0400000
2697 #define RTYPE_MSA 0x0800000
2698 #define RWARN 0x8000000
2700 #define GENERIC_REGISTER_NUMBERS \
2701 {"$0", RTYPE_NUM | 0}, \
2702 {"$1", RTYPE_NUM | 1}, \
2703 {"$2", RTYPE_NUM | 2}, \
2704 {"$3", RTYPE_NUM | 3}, \
2705 {"$4", RTYPE_NUM | 4}, \
2706 {"$5", RTYPE_NUM | 5}, \
2707 {"$6", RTYPE_NUM | 6}, \
2708 {"$7", RTYPE_NUM | 7}, \
2709 {"$8", RTYPE_NUM | 8}, \
2710 {"$9", RTYPE_NUM | 9}, \
2711 {"$10", RTYPE_NUM | 10}, \
2712 {"$11", RTYPE_NUM | 11}, \
2713 {"$12", RTYPE_NUM | 12}, \
2714 {"$13", RTYPE_NUM | 13}, \
2715 {"$14", RTYPE_NUM | 14}, \
2716 {"$15", RTYPE_NUM | 15}, \
2717 {"$16", RTYPE_NUM | 16}, \
2718 {"$17", RTYPE_NUM | 17}, \
2719 {"$18", RTYPE_NUM | 18}, \
2720 {"$19", RTYPE_NUM | 19}, \
2721 {"$20", RTYPE_NUM | 20}, \
2722 {"$21", RTYPE_NUM | 21}, \
2723 {"$22", RTYPE_NUM | 22}, \
2724 {"$23", RTYPE_NUM | 23}, \
2725 {"$24", RTYPE_NUM | 24}, \
2726 {"$25", RTYPE_NUM | 25}, \
2727 {"$26", RTYPE_NUM | 26}, \
2728 {"$27", RTYPE_NUM | 27}, \
2729 {"$28", RTYPE_NUM | 28}, \
2730 {"$29", RTYPE_NUM | 29}, \
2731 {"$30", RTYPE_NUM | 30}, \
2732 {"$31", RTYPE_NUM | 31}
2734 #define FPU_REGISTER_NAMES \
2735 {"$f0", RTYPE_FPU | 0}, \
2736 {"$f1", RTYPE_FPU | 1}, \
2737 {"$f2", RTYPE_FPU | 2}, \
2738 {"$f3", RTYPE_FPU | 3}, \
2739 {"$f4", RTYPE_FPU | 4}, \
2740 {"$f5", RTYPE_FPU | 5}, \
2741 {"$f6", RTYPE_FPU | 6}, \
2742 {"$f7", RTYPE_FPU | 7}, \
2743 {"$f8", RTYPE_FPU | 8}, \
2744 {"$f9", RTYPE_FPU | 9}, \
2745 {"$f10", RTYPE_FPU | 10}, \
2746 {"$f11", RTYPE_FPU | 11}, \
2747 {"$f12", RTYPE_FPU | 12}, \
2748 {"$f13", RTYPE_FPU | 13}, \
2749 {"$f14", RTYPE_FPU | 14}, \
2750 {"$f15", RTYPE_FPU | 15}, \
2751 {"$f16", RTYPE_FPU | 16}, \
2752 {"$f17", RTYPE_FPU | 17}, \
2753 {"$f18", RTYPE_FPU | 18}, \
2754 {"$f19", RTYPE_FPU | 19}, \
2755 {"$f20", RTYPE_FPU | 20}, \
2756 {"$f21", RTYPE_FPU | 21}, \
2757 {"$f22", RTYPE_FPU | 22}, \
2758 {"$f23", RTYPE_FPU | 23}, \
2759 {"$f24", RTYPE_FPU | 24}, \
2760 {"$f25", RTYPE_FPU | 25}, \
2761 {"$f26", RTYPE_FPU | 26}, \
2762 {"$f27", RTYPE_FPU | 27}, \
2763 {"$f28", RTYPE_FPU | 28}, \
2764 {"$f29", RTYPE_FPU | 29}, \
2765 {"$f30", RTYPE_FPU | 30}, \
2766 {"$f31", RTYPE_FPU | 31}
2768 #define FPU_CONDITION_CODE_NAMES \
2769 {"$fcc0", RTYPE_FCC | 0}, \
2770 {"$fcc1", RTYPE_FCC | 1}, \
2771 {"$fcc2", RTYPE_FCC | 2}, \
2772 {"$fcc3", RTYPE_FCC | 3}, \
2773 {"$fcc4", RTYPE_FCC | 4}, \
2774 {"$fcc5", RTYPE_FCC | 5}, \
2775 {"$fcc6", RTYPE_FCC | 6}, \
2776 {"$fcc7", RTYPE_FCC | 7}
2778 #define COPROC_CONDITION_CODE_NAMES \
2779 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2780 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2781 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2782 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2783 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2784 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2785 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2786 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2788 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2789 {"$a4", RTYPE_GP | 8}, \
2790 {"$a5", RTYPE_GP | 9}, \
2791 {"$a6", RTYPE_GP | 10}, \
2792 {"$a7", RTYPE_GP | 11}, \
2793 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2794 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2795 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2796 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2797 {"$t0", RTYPE_GP | 12}, \
2798 {"$t1", RTYPE_GP | 13}, \
2799 {"$t2", RTYPE_GP | 14}, \
2800 {"$t3", RTYPE_GP | 15}
2802 #define O32_SYMBOLIC_REGISTER_NAMES \
2803 {"$t0", RTYPE_GP | 8}, \
2804 {"$t1", RTYPE_GP | 9}, \
2805 {"$t2", RTYPE_GP | 10}, \
2806 {"$t3", RTYPE_GP | 11}, \
2807 {"$t4", RTYPE_GP | 12}, \
2808 {"$t5", RTYPE_GP | 13}, \
2809 {"$t6", RTYPE_GP | 14}, \
2810 {"$t7", RTYPE_GP | 15}, \
2811 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2812 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2813 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2814 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2816 /* Remaining symbolic register names. */
2817 #define SYMBOLIC_REGISTER_NAMES \
2818 {"$zero", RTYPE_GP | 0}, \
2819 {"$at", RTYPE_GP | 1}, \
2820 {"$AT", RTYPE_GP | 1}, \
2821 {"$v0", RTYPE_GP | 2}, \
2822 {"$v1", RTYPE_GP | 3}, \
2823 {"$a0", RTYPE_GP | 4}, \
2824 {"$a1", RTYPE_GP | 5}, \
2825 {"$a2", RTYPE_GP | 6}, \
2826 {"$a3", RTYPE_GP | 7}, \
2827 {"$s0", RTYPE_GP | 16}, \
2828 {"$s1", RTYPE_GP | 17}, \
2829 {"$s2", RTYPE_GP | 18}, \
2830 {"$s3", RTYPE_GP | 19}, \
2831 {"$s4", RTYPE_GP | 20}, \
2832 {"$s5", RTYPE_GP | 21}, \
2833 {"$s6", RTYPE_GP | 22}, \
2834 {"$s7", RTYPE_GP | 23}, \
2835 {"$t8", RTYPE_GP | 24}, \
2836 {"$t9", RTYPE_GP | 25}, \
2837 {"$k0", RTYPE_GP | 26}, \
2838 {"$kt0", RTYPE_GP | 26}, \
2839 {"$k1", RTYPE_GP | 27}, \
2840 {"$kt1", RTYPE_GP | 27}, \
2841 {"$gp", RTYPE_GP | 28}, \
2842 {"$sp", RTYPE_GP | 29}, \
2843 {"$s8", RTYPE_GP | 30}, \
2844 {"$fp", RTYPE_GP | 30}, \
2845 {"$ra", RTYPE_GP | 31}
2847 #define MIPS16_SPECIAL_REGISTER_NAMES \
2848 {"$pc", RTYPE_PC | 0}
2850 #define MDMX_VECTOR_REGISTER_NAMES \
2851 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2852 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2853 {"$v2", RTYPE_VEC | 2}, \
2854 {"$v3", RTYPE_VEC | 3}, \
2855 {"$v4", RTYPE_VEC | 4}, \
2856 {"$v5", RTYPE_VEC | 5}, \
2857 {"$v6", RTYPE_VEC | 6}, \
2858 {"$v7", RTYPE_VEC | 7}, \
2859 {"$v8", RTYPE_VEC | 8}, \
2860 {"$v9", RTYPE_VEC | 9}, \
2861 {"$v10", RTYPE_VEC | 10}, \
2862 {"$v11", RTYPE_VEC | 11}, \
2863 {"$v12", RTYPE_VEC | 12}, \
2864 {"$v13", RTYPE_VEC | 13}, \
2865 {"$v14", RTYPE_VEC | 14}, \
2866 {"$v15", RTYPE_VEC | 15}, \
2867 {"$v16", RTYPE_VEC | 16}, \
2868 {"$v17", RTYPE_VEC | 17}, \
2869 {"$v18", RTYPE_VEC | 18}, \
2870 {"$v19", RTYPE_VEC | 19}, \
2871 {"$v20", RTYPE_VEC | 20}, \
2872 {"$v21", RTYPE_VEC | 21}, \
2873 {"$v22", RTYPE_VEC | 22}, \
2874 {"$v23", RTYPE_VEC | 23}, \
2875 {"$v24", RTYPE_VEC | 24}, \
2876 {"$v25", RTYPE_VEC | 25}, \
2877 {"$v26", RTYPE_VEC | 26}, \
2878 {"$v27", RTYPE_VEC | 27}, \
2879 {"$v28", RTYPE_VEC | 28}, \
2880 {"$v29", RTYPE_VEC | 29}, \
2881 {"$v30", RTYPE_VEC | 30}, \
2882 {"$v31", RTYPE_VEC | 31}
2884 #define R5900_I_NAMES \
2885 {"$I", RTYPE_R5900_I | 0}
2887 #define R5900_Q_NAMES \
2888 {"$Q", RTYPE_R5900_Q | 0}
2890 #define R5900_R_NAMES \
2891 {"$R", RTYPE_R5900_R | 0}
2893 #define R5900_ACC_NAMES \
2894 {"$ACC", RTYPE_R5900_ACC | 0 }
2896 #define MIPS_DSP_ACCUMULATOR_NAMES \
2897 {"$ac0", RTYPE_ACC | 0}, \
2898 {"$ac1", RTYPE_ACC | 1}, \
2899 {"$ac2", RTYPE_ACC | 2}, \
2900 {"$ac3", RTYPE_ACC | 3}
2902 static const struct regname reg_names
[] = {
2903 GENERIC_REGISTER_NUMBERS
,
2905 FPU_CONDITION_CODE_NAMES
,
2906 COPROC_CONDITION_CODE_NAMES
,
2908 /* The $txx registers depends on the abi,
2909 these will be added later into the symbol table from
2910 one of the tables below once mips_abi is set after
2911 parsing of arguments from the command line. */
2912 SYMBOLIC_REGISTER_NAMES
,
2914 MIPS16_SPECIAL_REGISTER_NAMES
,
2915 MDMX_VECTOR_REGISTER_NAMES
,
2920 MIPS_DSP_ACCUMULATOR_NAMES
,
2924 static const struct regname reg_names_o32
[] = {
2925 O32_SYMBOLIC_REGISTER_NAMES
,
2929 static const struct regname reg_names_n32n64
[] = {
2930 N32N64_SYMBOLIC_REGISTER_NAMES
,
2934 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2935 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2936 of these register symbols, return the associated vector register,
2937 otherwise return SYMVAL itself. */
2940 mips_prefer_vec_regno (unsigned int symval
)
2942 if ((symval
& -2) == (RTYPE_GP
| 2))
2943 return RTYPE_VEC
| (symval
& 1);
2947 /* Return true if string [S, E) is a valid register name, storing its
2948 symbol value in *SYMVAL_PTR if so. */
2951 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2956 /* Terminate name. */
2960 /* Look up the name. */
2961 symbol
= symbol_find (s
);
2964 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2967 *symval_ptr
= S_GET_VALUE (symbol
);
2971 /* Return true if the string at *SPTR is a valid register name. Allow it
2972 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2975 When returning true, move *SPTR past the register, store the
2976 register's symbol value in *SYMVAL_PTR and the channel mask in
2977 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2978 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2979 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2982 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2983 unsigned int *channels_ptr
)
2987 unsigned int channels
, symval
, bit
;
2989 /* Find end of name. */
2991 if (is_name_beginner (*e
))
2993 while (is_part_of_name (*e
))
2997 if (!mips_parse_register_1 (s
, e
, &symval
))
3002 /* Eat characters from the end of the string that are valid
3003 channel suffixes. The preceding register must be $ACC or
3004 end with a digit, so there is no ambiguity. */
3007 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
3008 if (m
> s
&& m
[-1] == *q
)
3015 || !mips_parse_register_1 (s
, m
, &symval
)
3016 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3021 *symval_ptr
= symval
;
3023 *channels_ptr
= channels
;
3027 /* Check if SPTR points at a valid register specifier according to TYPES.
3028 If so, then return 1, advance S to consume the specifier and store
3029 the register's number in REGNOP, otherwise return 0. */
3032 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3036 if (mips_parse_register (s
, ®no
, NULL
))
3038 if (types
& RTYPE_VEC
)
3039 regno
= mips_prefer_vec_regno (regno
);
3048 as_warn (_("unrecognized register name `%s'"), *s
);
3053 return regno
<= RNUM_MASK
;
3056 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3057 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3060 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3065 for (i
= 0; i
< 4; i
++)
3066 if (*s
== "xyzw"[i
])
3068 *channels
|= 1 << (3 - i
);
3074 /* Token types for parsed operand lists. */
3075 enum mips_operand_token_type
{
3076 /* A plain register, e.g. $f2. */
3079 /* A 4-bit XYZW channel mask. */
3082 /* A constant vector index, e.g. [1]. */
3085 /* A register vector index, e.g. [$2]. */
3088 /* A continuous range of registers, e.g. $s0-$s4. */
3091 /* A (possibly relocated) expression. */
3094 /* A floating-point value. */
3097 /* A single character. This can be '(', ')' or ',', but '(' only appears
3101 /* A doubled character, either "--" or "++". */
3104 /* The end of the operand list. */
3108 /* A parsed operand token. */
3109 struct mips_operand_token
3111 /* The type of token. */
3112 enum mips_operand_token_type type
;
3115 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3118 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3119 unsigned int channels
;
3121 /* The integer value of an OT_INTEGER_INDEX. */
3124 /* The two register symbol values involved in an OT_REG_RANGE. */
3126 unsigned int regno1
;
3127 unsigned int regno2
;
3130 /* The value of an OT_INTEGER. The value is represented as an
3131 expression and the relocation operators that were applied to
3132 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3133 relocation operators were used. */
3136 bfd_reloc_code_real_type relocs
[3];
3139 /* The binary data for an OT_FLOAT constant, and the number of bytes
3142 unsigned char data
[8];
3146 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3151 /* An obstack used to construct lists of mips_operand_tokens. */
3152 static struct obstack mips_operand_tokens
;
3154 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3157 mips_add_token (struct mips_operand_token
*token
,
3158 enum mips_operand_token_type type
)
3161 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3164 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3165 and OT_REG tokens for them if so, and return a pointer to the first
3166 unconsumed character. Return null otherwise. */
3169 mips_parse_base_start (char *s
)
3171 struct mips_operand_token token
;
3172 unsigned int regno
, channels
;
3173 bfd_boolean decrement_p
;
3179 SKIP_SPACE_TABS (s
);
3181 /* Only match "--" as part of a base expression. In other contexts "--X"
3182 is a double negative. */
3183 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3187 SKIP_SPACE_TABS (s
);
3190 /* Allow a channel specifier because that leads to better error messages
3191 than treating something like "$vf0x++" as an expression. */
3192 if (!mips_parse_register (&s
, ®no
, &channels
))
3196 mips_add_token (&token
, OT_CHAR
);
3201 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3204 token
.u
.regno
= regno
;
3205 mips_add_token (&token
, OT_REG
);
3209 token
.u
.channels
= channels
;
3210 mips_add_token (&token
, OT_CHANNELS
);
3213 /* For consistency, only match "++" as part of base expressions too. */
3214 SKIP_SPACE_TABS (s
);
3215 if (s
[0] == '+' && s
[1] == '+')
3219 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3225 /* Parse one or more tokens from S. Return a pointer to the first
3226 unconsumed character on success. Return null if an error was found
3227 and store the error text in insn_error. FLOAT_FORMAT is as for
3228 mips_parse_arguments. */
3231 mips_parse_argument_token (char *s
, char float_format
)
3233 char *end
, *save_in
;
3235 unsigned int regno1
, regno2
, channels
;
3236 struct mips_operand_token token
;
3238 /* First look for "($reg", since we want to treat that as an
3239 OT_CHAR and OT_REG rather than an expression. */
3240 end
= mips_parse_base_start (s
);
3244 /* Handle other characters that end up as OT_CHARs. */
3245 if (*s
== ')' || *s
== ',')
3248 mips_add_token (&token
, OT_CHAR
);
3253 /* Handle tokens that start with a register. */
3254 if (mips_parse_register (&s
, ®no1
, &channels
))
3258 /* A register and a VU0 channel suffix. */
3259 token
.u
.regno
= regno1
;
3260 mips_add_token (&token
, OT_REG
);
3262 token
.u
.channels
= channels
;
3263 mips_add_token (&token
, OT_CHANNELS
);
3267 SKIP_SPACE_TABS (s
);
3270 /* A register range. */
3272 SKIP_SPACE_TABS (s
);
3273 if (!mips_parse_register (&s
, ®no2
, NULL
))
3275 set_insn_error (0, _("invalid register range"));
3279 token
.u
.reg_range
.regno1
= regno1
;
3280 token
.u
.reg_range
.regno2
= regno2
;
3281 mips_add_token (&token
, OT_REG_RANGE
);
3285 /* Add the register itself. */
3286 token
.u
.regno
= regno1
;
3287 mips_add_token (&token
, OT_REG
);
3289 /* Check for a vector index. */
3293 SKIP_SPACE_TABS (s
);
3294 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3295 mips_add_token (&token
, OT_REG_INDEX
);
3298 expressionS element
;
3300 my_getExpression (&element
, s
);
3301 if (element
.X_op
!= O_constant
)
3303 set_insn_error (0, _("vector element must be constant"));
3307 token
.u
.index
= element
.X_add_number
;
3308 mips_add_token (&token
, OT_INTEGER_INDEX
);
3310 SKIP_SPACE_TABS (s
);
3313 set_insn_error (0, _("missing `]'"));
3323 /* First try to treat expressions as floats. */
3324 save_in
= input_line_pointer
;
3325 input_line_pointer
= s
;
3326 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3327 &token
.u
.flt
.length
);
3328 end
= input_line_pointer
;
3329 input_line_pointer
= save_in
;
3332 set_insn_error (0, err
);
3337 mips_add_token (&token
, OT_FLOAT
);
3342 /* Treat everything else as an integer expression. */
3343 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3344 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3345 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3346 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3348 mips_add_token (&token
, OT_INTEGER
);
3352 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3353 if expressions should be treated as 32-bit floating-point constants,
3354 'd' if they should be treated as 64-bit floating-point constants,
3355 or 0 if they should be treated as integer expressions (the usual case).
3357 Return a list of tokens on success, otherwise return 0. The caller
3358 must obstack_free the list after use. */
3360 static struct mips_operand_token
*
3361 mips_parse_arguments (char *s
, char float_format
)
3363 struct mips_operand_token token
;
3365 SKIP_SPACE_TABS (s
);
3368 s
= mips_parse_argument_token (s
, float_format
);
3371 obstack_free (&mips_operand_tokens
,
3372 obstack_finish (&mips_operand_tokens
));
3375 SKIP_SPACE_TABS (s
);
3377 mips_add_token (&token
, OT_END
);
3378 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3381 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3382 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3385 is_opcode_valid (const struct mips_opcode
*mo
)
3387 int isa
= mips_opts
.isa
;
3388 int ase
= mips_opts
.ase
;
3392 if (ISA_HAS_64BIT_REGS (isa
))
3393 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3394 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3395 ase
|= mips_ases
[i
].flags64
;
3397 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3400 /* Check whether the instruction or macro requires single-precision or
3401 double-precision floating-point support. Note that this information is
3402 stored differently in the opcode table for insns and macros. */
3403 if (mo
->pinfo
== INSN_MACRO
)
3405 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3406 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3410 fp_s
= mo
->pinfo
& FP_S
;
3411 fp_d
= mo
->pinfo
& FP_D
;
3414 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3417 if (fp_s
&& mips_opts
.soft_float
)
3423 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3424 selected ISA and architecture. */
3427 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3429 int isa
= mips_opts
.isa
;
3430 int ase
= mips_opts
.ase
;
3433 if (ISA_HAS_64BIT_REGS (isa
))
3434 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3435 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3436 ase
|= mips_ases
[i
].flags64
;
3438 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3441 /* Return TRUE if the size of the microMIPS opcode MO matches one
3442 explicitly requested. Always TRUE in the standard MIPS mode.
3443 Use is_size_valid_16 for MIPS16 opcodes. */
3446 is_size_valid (const struct mips_opcode
*mo
)
3448 if (!mips_opts
.micromips
)
3451 if (mips_opts
.insn32
)
3453 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3455 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3458 if (!forced_insn_length
)
3460 if (mo
->pinfo
== INSN_MACRO
)
3462 return forced_insn_length
== micromips_insn_length (mo
);
3465 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3466 explicitly requested. */
3469 is_size_valid_16 (const struct mips_opcode
*mo
)
3471 if (!forced_insn_length
)
3473 if (mo
->pinfo
== INSN_MACRO
)
3475 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3477 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3482 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3483 of the preceding instruction. Always TRUE in the standard MIPS mode.
3485 We don't accept macros in 16-bit delay slots to avoid a case where
3486 a macro expansion fails because it relies on a preceding 32-bit real
3487 instruction to have matched and does not handle the operands correctly.
3488 The only macros that may expand to 16-bit instructions are JAL that
3489 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3490 and BGT (that likewise cannot be placed in a delay slot) that decay to
3491 a NOP. In all these cases the macros precede any corresponding real
3492 instruction definitions in the opcode table, so they will match in the
3493 second pass where the size of the delay slot is ignored and therefore
3494 produce correct code. */
3497 is_delay_slot_valid (const struct mips_opcode
*mo
)
3499 if (!mips_opts
.micromips
)
3502 if (mo
->pinfo
== INSN_MACRO
)
3503 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3504 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3505 && micromips_insn_length (mo
) != 4)
3507 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3508 && micromips_insn_length (mo
) != 2)
3514 /* For consistency checking, verify that all bits of OPCODE are specified
3515 either by the match/mask part of the instruction definition, or by the
3516 operand list. Also build up a list of operands in OPERANDS.
3518 INSN_BITS says which bits of the instruction are significant.
3519 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3520 provides the mips_operand description of each operand. DECODE_OPERAND
3521 is null for MIPS16 instructions. */
3524 validate_mips_insn (const struct mips_opcode
*opcode
,
3525 unsigned long insn_bits
,
3526 const struct mips_operand
*(*decode_operand
) (const char *),
3527 struct mips_operand_array
*operands
)
3530 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3531 const struct mips_operand
*operand
;
3533 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3534 if ((mask
& opcode
->match
) != opcode
->match
)
3536 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3537 opcode
->name
, opcode
->args
);
3542 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3543 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3544 for (s
= opcode
->args
; *s
; ++s
)
3557 if (!decode_operand
)
3558 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3560 operand
= decode_operand (s
);
3561 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3563 as_bad (_("internal: unknown operand type: %s %s"),
3564 opcode
->name
, opcode
->args
);
3567 gas_assert (opno
< MAX_OPERANDS
);
3568 operands
->operand
[opno
] = operand
;
3569 if (!decode_operand
&& operand
3570 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3571 && mips_opcode_32bit_p (opcode
))
3572 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3573 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3575 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3576 if (operand
->type
== OP_MDMX_IMM_REG
)
3577 /* Bit 5 is the format selector (OB vs QH). The opcode table
3578 has separate entries for each format. */
3579 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3580 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3581 used_bits
&= ~(mask
& 0x700);
3582 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3583 operand field that cannot be fully described with LSB/SIZE. */
3584 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3585 used_bits
&= ~0x6000;
3587 /* Skip prefix characters. */
3588 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3593 doubled
= used_bits
& mask
& insn_bits
;
3596 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3597 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3601 undefined
= ~used_bits
& insn_bits
;
3602 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3604 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3605 undefined
, opcode
->name
, opcode
->args
);
3608 used_bits
&= ~insn_bits
;
3611 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3612 used_bits
, opcode
->name
, opcode
->args
);
3618 /* The MIPS16 version of validate_mips_insn. */
3621 validate_mips16_insn (const struct mips_opcode
*opcode
,
3622 struct mips_operand_array
*operands
)
3624 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3626 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3629 /* The microMIPS version of validate_mips_insn. */
3632 validate_micromips_insn (const struct mips_opcode
*opc
,
3633 struct mips_operand_array
*operands
)
3635 unsigned long insn_bits
;
3636 unsigned long major
;
3637 unsigned int length
;
3639 if (opc
->pinfo
== INSN_MACRO
)
3640 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3643 length
= micromips_insn_length (opc
);
3644 if (length
!= 2 && length
!= 4)
3646 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3647 "%s %s"), length
, opc
->name
, opc
->args
);
3650 major
= opc
->match
>> (10 + 8 * (length
- 2));
3651 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3652 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3654 as_bad (_("internal error: bad microMIPS opcode "
3655 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3659 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3660 insn_bits
= 1 << 4 * length
;
3661 insn_bits
<<= 4 * length
;
3663 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3667 /* This function is called once, at assembler startup time. It should set up
3668 all the tables, etc. that the MD part of the assembler will need. */
3673 const char *retval
= NULL
;
3677 if (mips_pic
!= NO_PIC
)
3679 if (g_switch_seen
&& g_switch_value
!= 0)
3680 as_bad (_("-G may not be used in position-independent code"));
3683 else if (mips_abicalls
)
3685 if (g_switch_seen
&& g_switch_value
!= 0)
3686 as_bad (_("-G may not be used with abicalls"));
3690 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3691 as_warn (_("could not set architecture and machine"));
3693 op_hash
= hash_new ();
3695 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3696 for (i
= 0; i
< NUMOPCODES
;)
3698 const char *name
= mips_opcodes
[i
].name
;
3700 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
3703 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
3704 mips_opcodes
[i
].name
, retval
);
3705 /* Probably a memory allocation problem? Give up now. */
3706 as_fatal (_("broken assembler, no assembly attempted"));
3710 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3711 decode_mips_operand
, &mips_operands
[i
]))
3714 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3716 create_insn (&nop_insn
, mips_opcodes
+ i
);
3717 if (mips_fix_loongson2f_nop
)
3718 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3719 nop_insn
.fixed_p
= 1;
3722 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3723 create_insn (&sync_insn
, mips_opcodes
+ i
);
3727 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3730 mips16_op_hash
= hash_new ();
3731 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3732 bfd_mips16_num_opcodes
);
3735 while (i
< bfd_mips16_num_opcodes
)
3737 const char *name
= mips16_opcodes
[i
].name
;
3739 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
3741 as_fatal (_("internal: can't hash `%s': %s"),
3742 mips16_opcodes
[i
].name
, retval
);
3745 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3747 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3749 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3750 mips16_nop_insn
.fixed_p
= 1;
3754 while (i
< bfd_mips16_num_opcodes
3755 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3758 micromips_op_hash
= hash_new ();
3759 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3760 bfd_micromips_num_opcodes
);
3763 while (i
< bfd_micromips_num_opcodes
)
3765 const char *name
= micromips_opcodes
[i
].name
;
3767 retval
= hash_insert (micromips_op_hash
, name
,
3768 (void *) µmips_opcodes
[i
]);
3770 as_fatal (_("internal: can't hash `%s': %s"),
3771 micromips_opcodes
[i
].name
, retval
);
3774 struct mips_cl_insn
*micromips_nop_insn
;
3776 if (!validate_micromips_insn (µmips_opcodes
[i
],
3777 µmips_operands
[i
]))
3780 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3782 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3783 micromips_nop_insn
= µmips_nop16_insn
;
3784 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3785 micromips_nop_insn
= µmips_nop32_insn
;
3789 if (micromips_nop_insn
->insn_mo
== NULL
3790 && strcmp (name
, "nop") == 0)
3792 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3793 micromips_nop_insn
->fixed_p
= 1;
3797 while (++i
< bfd_micromips_num_opcodes
3798 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3802 as_fatal (_("broken assembler, no assembly attempted"));
3804 /* We add all the general register names to the symbol table. This
3805 helps us detect invalid uses of them. */
3806 for (i
= 0; reg_names
[i
].name
; i
++)
3807 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3808 reg_names
[i
].num
, /* & RNUM_MASK, */
3809 &zero_address_frag
));
3811 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3812 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3813 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
3814 &zero_address_frag
));
3816 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3817 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3818 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
3819 &zero_address_frag
));
3821 for (i
= 0; i
< 32; i
++)
3825 /* R5900 VU0 floating-point register. */
3826 sprintf (regname
, "$vf%d", i
);
3827 symbol_table_insert (symbol_new (regname
, reg_section
,
3828 RTYPE_VF
| i
, &zero_address_frag
));
3830 /* R5900 VU0 integer register. */
3831 sprintf (regname
, "$vi%d", i
);
3832 symbol_table_insert (symbol_new (regname
, reg_section
,
3833 RTYPE_VI
| i
, &zero_address_frag
));
3836 sprintf (regname
, "$w%d", i
);
3837 symbol_table_insert (symbol_new (regname
, reg_section
,
3838 RTYPE_MSA
| i
, &zero_address_frag
));
3841 obstack_init (&mips_operand_tokens
);
3843 mips_no_prev_insn ();
3846 mips_cprmask
[0] = 0;
3847 mips_cprmask
[1] = 0;
3848 mips_cprmask
[2] = 0;
3849 mips_cprmask
[3] = 0;
3851 /* set the default alignment for the text section (2**2) */
3852 record_alignment (text_section
, 2);
3854 bfd_set_gp_size (stdoutput
, g_switch_value
);
3856 /* On a native system other than VxWorks, sections must be aligned
3857 to 16 byte boundaries. When configured for an embedded ELF
3858 target, we don't bother. */
3859 if (strncmp (TARGET_OS
, "elf", 3) != 0
3860 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3862 bfd_set_section_alignment (text_section
, 4);
3863 bfd_set_section_alignment (data_section
, 4);
3864 bfd_set_section_alignment (bss_section
, 4);
3867 /* Create a .reginfo section for register masks and a .mdebug
3868 section for debugging information. */
3876 subseg
= now_subseg
;
3878 /* The ABI says this section should be loaded so that the
3879 running program can access it. However, we don't load it
3880 if we are configured for an embedded target. */
3881 flags
= SEC_READONLY
| SEC_DATA
;
3882 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3883 flags
|= SEC_ALLOC
| SEC_LOAD
;
3885 if (mips_abi
!= N64_ABI
)
3887 sec
= subseg_new (".reginfo", (subsegT
) 0);
3889 bfd_set_section_flags (sec
, flags
);
3890 bfd_set_section_alignment (sec
, HAVE_NEWABI
? 3 : 2);
3892 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3896 /* The 64-bit ABI uses a .MIPS.options section rather than
3897 .reginfo section. */
3898 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3899 bfd_set_section_flags (sec
, flags
);
3900 bfd_set_section_alignment (sec
, 3);
3902 /* Set up the option header. */
3904 Elf_Internal_Options opthdr
;
3907 opthdr
.kind
= ODK_REGINFO
;
3908 opthdr
.size
= (sizeof (Elf_External_Options
)
3909 + sizeof (Elf64_External_RegInfo
));
3912 f
= frag_more (sizeof (Elf_External_Options
));
3913 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3914 (Elf_External_Options
*) f
);
3916 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3920 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3921 bfd_set_section_flags (sec
,
3922 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3923 bfd_set_section_alignment (sec
, 3);
3924 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3926 if (ECOFF_DEBUGGING
)
3928 sec
= subseg_new (".mdebug", (subsegT
) 0);
3929 bfd_set_section_flags (sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
3930 bfd_set_section_alignment (sec
, 2);
3932 else if (mips_flag_pdr
)
3934 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3935 bfd_set_section_flags (pdr_seg
,
3936 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
3937 bfd_set_section_alignment (pdr_seg
, 2);
3940 subseg_set (seg
, subseg
);
3943 if (mips_fix_vr4120
)
3944 init_vr4120_conflicts ();
3948 fpabi_incompatible_with (int fpabi
, const char *what
)
3950 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3951 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3955 fpabi_requires (int fpabi
, const char *what
)
3957 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3958 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3961 /* Check -mabi and register sizes against the specified FP ABI. */
3963 check_fpabi (int fpabi
)
3967 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3968 if (file_mips_opts
.soft_float
)
3969 fpabi_incompatible_with (fpabi
, "softfloat");
3970 else if (file_mips_opts
.single_float
)
3971 fpabi_incompatible_with (fpabi
, "singlefloat");
3972 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3973 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3974 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3975 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3978 case Val_GNU_MIPS_ABI_FP_XX
:
3979 if (mips_abi
!= O32_ABI
)
3980 fpabi_requires (fpabi
, "-mabi=32");
3981 else if (file_mips_opts
.soft_float
)
3982 fpabi_incompatible_with (fpabi
, "softfloat");
3983 else if (file_mips_opts
.single_float
)
3984 fpabi_incompatible_with (fpabi
, "singlefloat");
3985 else if (file_mips_opts
.fp
!= 0)
3986 fpabi_requires (fpabi
, "fp=xx");
3989 case Val_GNU_MIPS_ABI_FP_64A
:
3990 case Val_GNU_MIPS_ABI_FP_64
:
3991 if (mips_abi
!= O32_ABI
)
3992 fpabi_requires (fpabi
, "-mabi=32");
3993 else if (file_mips_opts
.soft_float
)
3994 fpabi_incompatible_with (fpabi
, "softfloat");
3995 else if (file_mips_opts
.single_float
)
3996 fpabi_incompatible_with (fpabi
, "singlefloat");
3997 else if (file_mips_opts
.fp
!= 64)
3998 fpabi_requires (fpabi
, "fp=64");
3999 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
4000 fpabi_incompatible_with (fpabi
, "nooddspreg");
4001 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
4002 fpabi_requires (fpabi
, "nooddspreg");
4005 case Val_GNU_MIPS_ABI_FP_SINGLE
:
4006 if (file_mips_opts
.soft_float
)
4007 fpabi_incompatible_with (fpabi
, "softfloat");
4008 else if (!file_mips_opts
.single_float
)
4009 fpabi_requires (fpabi
, "singlefloat");
4012 case Val_GNU_MIPS_ABI_FP_SOFT
:
4013 if (!file_mips_opts
.soft_float
)
4014 fpabi_requires (fpabi
, "softfloat");
4017 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4018 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4019 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4022 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4023 /* Silently ignore compatibility value. */
4027 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4028 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4033 /* Perform consistency checks on the current options. */
4036 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4038 /* Check the size of integer registers agrees with the ABI and ISA. */
4039 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4040 as_bad (_("`gp=64' used with a 32-bit processor"));
4042 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4043 as_bad (_("`gp=32' used with a 64-bit ABI"));
4045 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4046 as_bad (_("`gp=64' used with a 32-bit ABI"));
4048 /* Check the size of the float registers agrees with the ABI and ISA. */
4052 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4053 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4054 else if (opts
->single_float
== 1)
4055 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4058 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4059 as_bad (_("`fp=64' used with a 32-bit fpu"));
4061 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4062 && !ISA_HAS_MXHC1 (opts
->isa
))
4063 as_warn (_("`fp=64' used with a 32-bit ABI"));
4067 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4068 as_warn (_("`fp=32' used with a 64-bit ABI"));
4069 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4070 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4073 as_bad (_("Unknown size of floating point registers"));
4077 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4078 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4080 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4081 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4082 else if (ISA_IS_R6 (opts
->isa
)
4083 && (opts
->micromips
== 1
4084 || opts
->mips16
== 1))
4085 as_fatal (_("`%s' cannot be used with `%s'"),
4086 opts
->micromips
? "micromips" : "mips16",
4087 mips_cpu_info_from_isa (opts
->isa
)->name
);
4089 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4090 as_fatal (_("branch relaxation is not supported in `%s'"),
4091 mips_cpu_info_from_isa (opts
->isa
)->name
);
4094 /* Perform consistency checks on the module level options exactly once.
4095 This is a deferred check that happens:
4096 at the first .set directive
4097 or, at the first pseudo op that generates code (inc .dc.a)
4098 or, at the first instruction
4102 file_mips_check_options (void)
4104 if (file_mips_opts_checked
)
4107 /* The following code determines the register size.
4108 Similar code was added to GCC 3.3 (see override_options() in
4109 config/mips/mips.c). The GAS and GCC code should be kept in sync
4110 as much as possible. */
4112 if (file_mips_opts
.gp
< 0)
4114 /* Infer the integer register size from the ABI and processor.
4115 Restrict ourselves to 32-bit registers if that's all the
4116 processor has, or if the ABI cannot handle 64-bit registers. */
4117 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4118 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4122 if (file_mips_opts
.fp
< 0)
4124 /* No user specified float register size.
4125 ??? GAS treats single-float processors as though they had 64-bit
4126 float registers (although it complains when double-precision
4127 instructions are used). As things stand, saying they have 32-bit
4128 registers would lead to spurious "register must be even" messages.
4129 So here we assume float registers are never smaller than the
4131 if (file_mips_opts
.gp
== 64)
4132 /* 64-bit integer registers implies 64-bit float registers. */
4133 file_mips_opts
.fp
= 64;
4134 else if ((file_mips_opts
.ase
& FP64_ASES
)
4135 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4136 /* Handle ASEs that require 64-bit float registers, if possible. */
4137 file_mips_opts
.fp
= 64;
4138 else if (ISA_IS_R6 (mips_opts
.isa
))
4139 /* R6 implies 64-bit float registers. */
4140 file_mips_opts
.fp
= 64;
4142 /* 32-bit float registers. */
4143 file_mips_opts
.fp
= 32;
4146 /* Disable operations on odd-numbered floating-point registers by default
4147 when using the FPXX ABI. */
4148 if (file_mips_opts
.oddspreg
< 0)
4150 if (file_mips_opts
.fp
== 0)
4151 file_mips_opts
.oddspreg
= 0;
4153 file_mips_opts
.oddspreg
= 1;
4156 /* End of GCC-shared inference code. */
4158 /* This flag is set when we have a 64-bit capable CPU but use only
4159 32-bit wide registers. Note that EABI does not use it. */
4160 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4161 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4162 || mips_abi
== O32_ABI
))
4165 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4166 as_bad (_("trap exception not supported at ISA 1"));
4168 /* If the selected architecture includes support for ASEs, enable
4169 generation of code for them. */
4170 if (file_mips_opts
.mips16
== -1)
4171 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4172 if (file_mips_opts
.micromips
== -1)
4173 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4176 if (mips_nan2008
== -1)
4177 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4178 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4179 as_fatal (_("`%s' does not support legacy NaN"),
4180 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4182 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4183 being selected implicitly. */
4184 if (file_mips_opts
.fp
!= 64)
4185 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4187 /* If the user didn't explicitly select or deselect a particular ASE,
4188 use the default setting for the CPU. */
4189 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4191 /* Set up the current options. These may change throughout assembly. */
4192 mips_opts
= file_mips_opts
;
4194 mips_check_isa_supports_ases ();
4195 mips_check_options (&file_mips_opts
, TRUE
);
4196 file_mips_opts_checked
= TRUE
;
4198 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4199 as_warn (_("could not set architecture and machine"));
4203 md_assemble (char *str
)
4205 struct mips_cl_insn insn
;
4206 bfd_reloc_code_real_type unused_reloc
[3]
4207 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4209 file_mips_check_options ();
4211 imm_expr
.X_op
= O_absent
;
4212 offset_expr
.X_op
= O_absent
;
4213 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4214 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4215 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4217 mips_mark_labels ();
4218 mips_assembling_insn
= TRUE
;
4219 clear_insn_error ();
4221 if (mips_opts
.mips16
)
4222 mips16_ip (str
, &insn
);
4225 mips_ip (str
, &insn
);
4226 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4227 str
, insn
.insn_opcode
));
4231 report_insn_error (str
);
4232 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4235 if (mips_opts
.mips16
)
4236 mips16_macro (&insn
);
4243 if (offset_expr
.X_op
!= O_absent
)
4244 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4246 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4249 mips_assembling_insn
= FALSE
;
4252 /* Convenience functions for abstracting away the differences between
4253 MIPS16 and non-MIPS16 relocations. */
4255 static inline bfd_boolean
4256 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4260 case BFD_RELOC_MIPS16_JMP
:
4261 case BFD_RELOC_MIPS16_GPREL
:
4262 case BFD_RELOC_MIPS16_GOT16
:
4263 case BFD_RELOC_MIPS16_CALL16
:
4264 case BFD_RELOC_MIPS16_HI16_S
:
4265 case BFD_RELOC_MIPS16_HI16
:
4266 case BFD_RELOC_MIPS16_LO16
:
4267 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4275 static inline bfd_boolean
4276 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4280 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4281 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4282 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4283 case BFD_RELOC_MICROMIPS_GPREL16
:
4284 case BFD_RELOC_MICROMIPS_JMP
:
4285 case BFD_RELOC_MICROMIPS_HI16
:
4286 case BFD_RELOC_MICROMIPS_HI16_S
:
4287 case BFD_RELOC_MICROMIPS_LO16
:
4288 case BFD_RELOC_MICROMIPS_LITERAL
:
4289 case BFD_RELOC_MICROMIPS_GOT16
:
4290 case BFD_RELOC_MICROMIPS_CALL16
:
4291 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4292 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4293 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4294 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4295 case BFD_RELOC_MICROMIPS_SUB
:
4296 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4297 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4298 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4299 case BFD_RELOC_MICROMIPS_HIGHEST
:
4300 case BFD_RELOC_MICROMIPS_HIGHER
:
4301 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4302 case BFD_RELOC_MICROMIPS_JALR
:
4310 static inline bfd_boolean
4311 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4313 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4316 static inline bfd_boolean
4317 b_reloc_p (bfd_reloc_code_real_type reloc
)
4319 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4320 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4321 || reloc
== BFD_RELOC_16_PCREL_S2
4322 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4323 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4324 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4325 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4328 static inline bfd_boolean
4329 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4331 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4332 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4335 static inline bfd_boolean
4336 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4338 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4339 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4342 static inline bfd_boolean
4343 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4345 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4346 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4349 static inline bfd_boolean
4350 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4352 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4355 static inline bfd_boolean
4356 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4358 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4359 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4362 /* Return true if RELOC is a PC-relative relocation that does not have
4363 full address range. */
4365 static inline bfd_boolean
4366 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4370 case BFD_RELOC_16_PCREL_S2
:
4371 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4372 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4373 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4374 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4375 case BFD_RELOC_MIPS_21_PCREL_S2
:
4376 case BFD_RELOC_MIPS_26_PCREL_S2
:
4377 case BFD_RELOC_MIPS_18_PCREL_S3
:
4378 case BFD_RELOC_MIPS_19_PCREL_S2
:
4381 case BFD_RELOC_32_PCREL
:
4382 case BFD_RELOC_HI16_S_PCREL
:
4383 case BFD_RELOC_LO16_PCREL
:
4384 return HAVE_64BIT_ADDRESSES
;
4391 /* Return true if the given relocation might need a matching %lo().
4392 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4393 need a matching %lo() when applied to local symbols. */
4395 static inline bfd_boolean
4396 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4398 return (HAVE_IN_PLACE_ADDENDS
4399 && (hi16_reloc_p (reloc
)
4400 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4401 all GOT16 relocations evaluate to "G". */
4402 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4405 /* Return the type of %lo() reloc needed by RELOC, given that
4406 reloc_needs_lo_p. */
4408 static inline bfd_reloc_code_real_type
4409 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4411 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4412 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4416 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4419 static inline bfd_boolean
4420 fixup_has_matching_lo_p (fixS
*fixp
)
4422 return (fixp
->fx_next
!= NULL
4423 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4424 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4425 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4428 /* Move all labels in LABELS to the current insertion point. TEXT_P
4429 says whether the labels refer to text or data. */
4432 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4434 struct insn_label_list
*l
;
4437 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4439 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4440 symbol_set_frag (l
->label
, frag_now
);
4441 val
= (valueT
) frag_now_fix ();
4442 /* MIPS16/microMIPS text labels are stored as odd.
4443 We just carry the ISA mode bit forward. */
4444 if (text_p
&& HAVE_CODE_COMPRESSION
)
4445 val
|= (S_GET_VALUE (l
->label
) & 0x1);
4446 S_SET_VALUE (l
->label
, val
);
4450 /* Move all labels in insn_labels to the current insertion point
4451 and treat them as text labels. */
4454 mips_move_text_labels (void)
4456 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4459 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4462 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4464 bfd_boolean linkonce
= FALSE
;
4465 segT symseg
= S_GET_SEGMENT (sym
);
4467 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4469 if ((bfd_section_flags (symseg
) & SEC_LINK_ONCE
))
4471 /* The GNU toolchain uses an extension for ELF: a section
4472 beginning with the magic string .gnu.linkonce is a
4473 linkonce section. */
4474 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4475 sizeof ".gnu.linkonce" - 1) == 0)
4481 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4482 linker to handle them specially, such as generating jalx instructions
4483 when needed. We also make them odd for the duration of the assembly,
4484 in order to generate the right sort of code. We will make them even
4485 in the adjust_symtab routine, while leaving them marked. This is
4486 convenient for the debugger and the disassembler. The linker knows
4487 to make them odd again. */
4490 mips_compressed_mark_label (symbolS
*label
)
4492 gas_assert (HAVE_CODE_COMPRESSION
);
4494 if (mips_opts
.mips16
)
4495 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4497 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4498 if ((S_GET_VALUE (label
) & 1) == 0
4499 /* Don't adjust the address if the label is global or weak, or
4500 in a link-once section, since we'll be emitting symbol reloc
4501 references to it which will be patched up by the linker, and
4502 the final value of the symbol may or may not be MIPS16/microMIPS. */
4503 && !S_IS_WEAK (label
)
4504 && !S_IS_EXTERNAL (label
)
4505 && !s_is_linkonce (label
, now_seg
))
4506 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4509 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4512 mips_compressed_mark_labels (void)
4514 struct insn_label_list
*l
;
4516 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4517 mips_compressed_mark_label (l
->label
);
4520 /* End the current frag. Make it a variant frag and record the
4524 relax_close_frag (void)
4526 mips_macro_warning
.first_frag
= frag_now
;
4527 frag_var (rs_machine_dependent
, 0, 0,
4528 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4529 mips_pic
!= NO_PIC
),
4530 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4532 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4533 mips_relax
.first_fixup
= 0;
4536 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4537 See the comment above RELAX_ENCODE for more details. */
4540 relax_start (symbolS
*symbol
)
4542 gas_assert (mips_relax
.sequence
== 0);
4543 mips_relax
.sequence
= 1;
4544 mips_relax
.symbol
= symbol
;
4547 /* Start generating the second version of a relaxable sequence.
4548 See the comment above RELAX_ENCODE for more details. */
4553 gas_assert (mips_relax
.sequence
== 1);
4554 mips_relax
.sequence
= 2;
4557 /* End the current relaxable sequence. */
4562 gas_assert (mips_relax
.sequence
== 2);
4563 relax_close_frag ();
4564 mips_relax
.sequence
= 0;
4567 /* Return true if IP is a delayed branch or jump. */
4569 static inline bfd_boolean
4570 delayed_branch_p (const struct mips_cl_insn
*ip
)
4572 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4573 | INSN_COND_BRANCH_DELAY
4574 | INSN_COND_BRANCH_LIKELY
)) != 0;
4577 /* Return true if IP is a compact branch or jump. */
4579 static inline bfd_boolean
4580 compact_branch_p (const struct mips_cl_insn
*ip
)
4582 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4583 | INSN2_COND_BRANCH
)) != 0;
4586 /* Return true if IP is an unconditional branch or jump. */
4588 static inline bfd_boolean
4589 uncond_branch_p (const struct mips_cl_insn
*ip
)
4591 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4592 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4595 /* Return true if IP is a branch-likely instruction. */
4597 static inline bfd_boolean
4598 branch_likely_p (const struct mips_cl_insn
*ip
)
4600 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4603 /* Return the type of nop that should be used to fill the delay slot
4604 of delayed branch IP. */
4606 static struct mips_cl_insn
*
4607 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4609 if (mips_opts
.micromips
4610 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4611 return µmips_nop32_insn
;
4615 /* Return a mask that has bit N set if OPCODE reads the register(s)
4619 insn_read_mask (const struct mips_opcode
*opcode
)
4621 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4624 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4628 insn_write_mask (const struct mips_opcode
*opcode
)
4630 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4633 /* Return a mask of the registers specified by operand OPERAND of INSN.
4634 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4638 operand_reg_mask (const struct mips_cl_insn
*insn
,
4639 const struct mips_operand
*operand
,
4640 unsigned int type_mask
)
4642 unsigned int uval
, vsel
;
4644 switch (operand
->type
)
4651 case OP_ADDIUSP_INT
:
4652 case OP_ENTRY_EXIT_LIST
:
4653 case OP_REPEAT_DEST_REG
:
4654 case OP_REPEAT_PREV_REG
:
4657 case OP_VU0_MATCH_SUFFIX
:
4665 case OP_OPTIONAL_REG
:
4667 const struct mips_reg_operand
*reg_op
;
4669 reg_op
= (const struct mips_reg_operand
*) operand
;
4670 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4672 uval
= insn_extract_operand (insn
, operand
);
4673 return 1 << mips_decode_reg_operand (reg_op
, uval
);
4678 const struct mips_reg_pair_operand
*pair_op
;
4680 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4681 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4683 uval
= insn_extract_operand (insn
, operand
);
4684 return (1 << pair_op
->reg1_map
[uval
]) | (1 << pair_op
->reg2_map
[uval
]);
4687 case OP_CLO_CLZ_DEST
:
4688 if (!(type_mask
& (1 << OP_REG_GP
)))
4690 uval
= insn_extract_operand (insn
, operand
);
4691 return (1 << (uval
& 31)) | (1 << (uval
>> 5));
4694 if (!(type_mask
& (1 << OP_REG_GP
)))
4696 uval
= insn_extract_operand (insn
, operand
);
4697 gas_assert ((uval
& 31) == (uval
>> 5));
4698 return 1 << (uval
& 31);
4701 case OP_NON_ZERO_REG
:
4702 if (!(type_mask
& (1 << OP_REG_GP
)))
4704 uval
= insn_extract_operand (insn
, operand
);
4705 return 1 << (uval
& 31);
4707 case OP_LWM_SWM_LIST
:
4710 case OP_SAVE_RESTORE_LIST
:
4713 case OP_MDMX_IMM_REG
:
4714 if (!(type_mask
& (1 << OP_REG_VEC
)))
4716 uval
= insn_extract_operand (insn
, operand
);
4718 if ((vsel
& 0x18) == 0x18)
4720 return 1 << (uval
& 31);
4723 if (!(type_mask
& (1 << OP_REG_GP
)))
4725 return 1 << insn_extract_operand (insn
, operand
);
4730 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4731 where bit N of OPNO_MASK is set if operand N should be included.
4732 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4736 insn_reg_mask (const struct mips_cl_insn
*insn
,
4737 unsigned int type_mask
, unsigned int opno_mask
)
4739 unsigned int opno
, reg_mask
;
4743 while (opno_mask
!= 0)
4746 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4753 /* Return the mask of core registers that IP reads. */
4756 gpr_read_mask (const struct mips_cl_insn
*ip
)
4758 unsigned long pinfo
, pinfo2
;
4761 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4762 pinfo
= ip
->insn_mo
->pinfo
;
4763 pinfo2
= ip
->insn_mo
->pinfo2
;
4764 if (pinfo
& INSN_UDI
)
4766 /* UDI instructions have traditionally been assumed to read RS
4768 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4769 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4771 if (pinfo
& INSN_READ_GPR_24
)
4773 if (pinfo2
& INSN2_READ_GPR_16
)
4775 if (pinfo2
& INSN2_READ_SP
)
4777 if (pinfo2
& INSN2_READ_GPR_31
)
4779 /* Don't include register 0. */
4783 /* Return the mask of core registers that IP writes. */
4786 gpr_write_mask (const struct mips_cl_insn
*ip
)
4788 unsigned long pinfo
, pinfo2
;
4791 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4792 pinfo
= ip
->insn_mo
->pinfo
;
4793 pinfo2
= ip
->insn_mo
->pinfo2
;
4794 if (pinfo
& INSN_WRITE_GPR_24
)
4796 if (pinfo
& INSN_WRITE_GPR_31
)
4798 if (pinfo
& INSN_UDI
)
4799 /* UDI instructions have traditionally been assumed to write to RD. */
4800 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4801 if (pinfo2
& INSN2_WRITE_SP
)
4803 /* Don't include register 0. */
4807 /* Return the mask of floating-point registers that IP reads. */
4810 fpr_read_mask (const struct mips_cl_insn
*ip
)
4812 unsigned long pinfo
;
4815 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4816 | (1 << OP_REG_MSA
)),
4817 insn_read_mask (ip
->insn_mo
));
4818 pinfo
= ip
->insn_mo
->pinfo
;
4819 /* Conservatively treat all operands to an FP_D instruction are doubles.
4820 (This is overly pessimistic for things like cvt.d.s.) */
4821 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4826 /* Return the mask of floating-point registers that IP writes. */
4829 fpr_write_mask (const struct mips_cl_insn
*ip
)
4831 unsigned long pinfo
;
4834 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4835 | (1 << OP_REG_MSA
)),
4836 insn_write_mask (ip
->insn_mo
));
4837 pinfo
= ip
->insn_mo
->pinfo
;
4838 /* Conservatively treat all operands to an FP_D instruction are doubles.
4839 (This is overly pessimistic for things like cvt.s.d.) */
4840 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4845 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4846 Check whether that is allowed. */
4849 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4851 const char *s
= insn
->name
;
4852 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4854 && mips_opts
.oddspreg
;
4856 if (insn
->pinfo
== INSN_MACRO
)
4857 /* Let a macro pass, we'll catch it later when it is expanded. */
4860 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4861 otherwise it depends on oddspreg. */
4862 if ((insn
->pinfo
& FP_S
)
4863 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4864 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4865 return FPR_SIZE
== 32 || oddspreg
;
4867 /* Allow odd registers for single-precision ops and double-precision if the
4868 floating-point registers are 64-bit wide. */
4869 switch (insn
->pinfo
& (FP_S
| FP_D
))
4875 return FPR_SIZE
== 64;
4880 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4881 s
= strchr (insn
->name
, '.');
4882 if (s
!= NULL
&& opnum
== 2)
4883 s
= strchr (s
+ 1, '.');
4884 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4887 return FPR_SIZE
== 64;
4890 /* Information about an instruction argument that we're trying to match. */
4891 struct mips_arg_info
4893 /* The instruction so far. */
4894 struct mips_cl_insn
*insn
;
4896 /* The first unconsumed operand token. */
4897 struct mips_operand_token
*token
;
4899 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4902 /* The 1-based argument number, for error reporting. This does not
4903 count elided optional registers, etc.. */
4906 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4907 unsigned int last_regno
;
4909 /* If the first operand was an OP_REG, this is the register that it
4910 specified, otherwise it is ILLEGAL_REG. */
4911 unsigned int dest_regno
;
4913 /* The value of the last OP_INT operand. Only used for OP_MSB,
4914 where it gives the lsb position. */
4915 unsigned int last_op_int
;
4917 /* If true, match routines should assume that no later instruction
4918 alternative matches and should therefore be as accommodating as
4919 possible. Match routines should not report errors if something
4920 is only invalid for !LAX_MATCH. */
4921 bfd_boolean lax_match
;
4923 /* True if a reference to the current AT register was seen. */
4924 bfd_boolean seen_at
;
4927 /* Record that the argument is out of range. */
4930 match_out_of_range (struct mips_arg_info
*arg
)
4932 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4935 /* Record that the argument isn't constant but needs to be. */
4938 match_not_constant (struct mips_arg_info
*arg
)
4940 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4944 /* Try to match an OT_CHAR token for character CH. Consume the token
4945 and return true on success, otherwise return false. */
4948 match_char (struct mips_arg_info
*arg
, char ch
)
4950 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4960 /* Try to get an expression from the next tokens in ARG. Consume the
4961 tokens and return true on success, storing the expression value in
4962 VALUE and relocation types in R. */
4965 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4966 bfd_reloc_code_real_type
*r
)
4968 /* If the next token is a '(' that was parsed as being part of a base
4969 expression, assume we have an elided offset. The later match will fail
4970 if this turns out to be wrong. */
4971 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4973 value
->X_op
= O_constant
;
4974 value
->X_add_number
= 0;
4975 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4979 /* Reject register-based expressions such as "0+$2" and "(($2))".
4980 For plain registers the default error seems more appropriate. */
4981 if (arg
->token
->type
== OT_INTEGER
4982 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4984 set_insn_error (arg
->argnum
, _("register value used as expression"));
4988 if (arg
->token
->type
== OT_INTEGER
)
4990 *value
= arg
->token
->u
.integer
.value
;
4991 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4997 (arg
->argnum
, _("operand %d must be an immediate expression"),
5002 /* Try to get a constant expression from the next tokens in ARG. Consume
5003 the tokens and return true on success, storing the constant value
5007 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
5010 bfd_reloc_code_real_type r
[3];
5012 if (!match_expression (arg
, &ex
, r
))
5015 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5016 *value
= ex
.X_add_number
;
5019 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5020 match_out_of_range (arg
);
5022 match_not_constant (arg
);
5028 /* Return the RTYPE_* flags for a register operand of type TYPE that
5029 appears in instruction OPCODE. */
5032 convert_reg_type (const struct mips_opcode
*opcode
,
5033 enum mips_reg_operand_type type
)
5038 return RTYPE_NUM
| RTYPE_GP
;
5041 /* Allow vector register names for MDMX if the instruction is a 64-bit
5042 FPR load, store or move (including moves to and from GPRs). */
5043 if ((mips_opts
.ase
& ASE_MDMX
)
5044 && (opcode
->pinfo
& FP_D
)
5045 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5046 | INSN_COPROC_MEMORY_DELAY
5049 | INSN_STORE_MEMORY
)))
5050 return RTYPE_FPU
| RTYPE_VEC
;
5054 if (opcode
->pinfo
& (FP_D
| FP_S
))
5055 return RTYPE_CCC
| RTYPE_FCC
;
5059 if (opcode
->membership
& INSN_5400
)
5061 return RTYPE_FPU
| RTYPE_VEC
;
5067 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5068 return RTYPE_NUM
| RTYPE_CP0
;
5075 return RTYPE_NUM
| RTYPE_VI
;
5078 return RTYPE_NUM
| RTYPE_VF
;
5080 case OP_REG_R5900_I
:
5081 return RTYPE_R5900_I
;
5083 case OP_REG_R5900_Q
:
5084 return RTYPE_R5900_Q
;
5086 case OP_REG_R5900_R
:
5087 return RTYPE_R5900_R
;
5089 case OP_REG_R5900_ACC
:
5090 return RTYPE_R5900_ACC
;
5095 case OP_REG_MSA_CTRL
:
5101 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5104 check_regno (struct mips_arg_info
*arg
,
5105 enum mips_reg_operand_type type
, unsigned int regno
)
5107 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5108 arg
->seen_at
= TRUE
;
5110 if (type
== OP_REG_FP
5112 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5114 /* This was a warning prior to introducing O32 FPXX and FP64 support
5115 so maintain a warning for FP32 but raise an error for the new
5118 as_warn (_("float register should be even, was %d"), regno
);
5120 as_bad (_("float register should be even, was %d"), regno
);
5123 if (type
== OP_REG_CCC
)
5128 name
= arg
->insn
->insn_mo
->name
;
5129 length
= strlen (name
);
5130 if ((regno
& 1) != 0
5131 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5132 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5133 as_warn (_("condition code register should be even for %s, was %d"),
5136 if ((regno
& 3) != 0
5137 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5138 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5143 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5144 a register of type TYPE. Return true on success, storing the register
5145 number in *REGNO and warning about any dubious uses. */
5148 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5149 unsigned int symval
, unsigned int *regno
)
5151 if (type
== OP_REG_VEC
)
5152 symval
= mips_prefer_vec_regno (symval
);
5153 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5156 *regno
= symval
& RNUM_MASK
;
5157 check_regno (arg
, type
, *regno
);
5161 /* Try to interpret the next token in ARG as a register of type TYPE.
5162 Consume the token and return true on success, storing the register
5163 number in *REGNO. Return false on failure. */
5166 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5167 unsigned int *regno
)
5169 if (arg
->token
->type
== OT_REG
5170 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5178 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5179 Consume the token and return true on success, storing the register numbers
5180 in *REGNO1 and *REGNO2. Return false on failure. */
5183 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5184 unsigned int *regno1
, unsigned int *regno2
)
5186 if (match_reg (arg
, type
, regno1
))
5191 if (arg
->token
->type
== OT_REG_RANGE
5192 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5193 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5194 && *regno1
<= *regno2
)
5202 /* OP_INT matcher. */
5205 match_int_operand (struct mips_arg_info
*arg
,
5206 const struct mips_operand
*operand_base
)
5208 const struct mips_int_operand
*operand
;
5210 int min_val
, max_val
, factor
;
5213 operand
= (const struct mips_int_operand
*) operand_base
;
5214 factor
= 1 << operand
->shift
;
5215 min_val
= mips_int_operand_min (operand
);
5216 max_val
= mips_int_operand_max (operand
);
5218 if (operand_base
->lsb
== 0
5219 && operand_base
->size
== 16
5220 && operand
->shift
== 0
5221 && operand
->bias
== 0
5222 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5224 /* The operand can be relocated. */
5225 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5228 if (offset_expr
.X_op
== O_big
)
5230 match_out_of_range (arg
);
5234 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5235 /* Relocation operators were used. Accept the argument and
5236 leave the relocation value in offset_expr and offset_relocs
5237 for the caller to process. */
5240 if (offset_expr
.X_op
!= O_constant
)
5242 /* Accept non-constant operands if no later alternative matches,
5243 leaving it for the caller to process. */
5244 if (!arg
->lax_match
)
5246 match_not_constant (arg
);
5249 offset_reloc
[0] = BFD_RELOC_LO16
;
5253 /* Clear the global state; we're going to install the operand
5255 sval
= offset_expr
.X_add_number
;
5256 offset_expr
.X_op
= O_absent
;
5258 /* For compatibility with older assemblers, we accept
5259 0x8000-0xffff as signed 16-bit numbers when only
5260 signed numbers are allowed. */
5263 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5264 if (!arg
->lax_match
&& sval
<= max_val
)
5266 match_out_of_range (arg
);
5273 if (!match_const_int (arg
, &sval
))
5277 arg
->last_op_int
= sval
;
5279 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5281 match_out_of_range (arg
);
5285 uval
= (unsigned int) sval
>> operand
->shift
;
5286 uval
-= operand
->bias
;
5288 /* Handle -mfix-cn63xxp1. */
5290 && mips_fix_cn63xxp1
5291 && !mips_opts
.micromips
5292 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5307 /* The rest must be changed to 28. */
5312 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5316 /* OP_MAPPED_INT matcher. */
5319 match_mapped_int_operand (struct mips_arg_info
*arg
,
5320 const struct mips_operand
*operand_base
)
5322 const struct mips_mapped_int_operand
*operand
;
5323 unsigned int uval
, num_vals
;
5326 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5327 if (!match_const_int (arg
, &sval
))
5330 num_vals
= 1 << operand_base
->size
;
5331 for (uval
= 0; uval
< num_vals
; uval
++)
5332 if (operand
->int_map
[uval
] == sval
)
5334 if (uval
== num_vals
)
5336 match_out_of_range (arg
);
5340 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5344 /* OP_MSB matcher. */
5347 match_msb_operand (struct mips_arg_info
*arg
,
5348 const struct mips_operand
*operand_base
)
5350 const struct mips_msb_operand
*operand
;
5351 int min_val
, max_val
, max_high
;
5352 offsetT size
, sval
, high
;
5354 operand
= (const struct mips_msb_operand
*) operand_base
;
5355 min_val
= operand
->bias
;
5356 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5357 max_high
= operand
->opsize
;
5359 if (!match_const_int (arg
, &size
))
5362 high
= size
+ arg
->last_op_int
;
5363 sval
= operand
->add_lsb
? high
: size
;
5365 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5367 match_out_of_range (arg
);
5370 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5374 /* OP_REG matcher. */
5377 match_reg_operand (struct mips_arg_info
*arg
,
5378 const struct mips_operand
*operand_base
)
5380 const struct mips_reg_operand
*operand
;
5381 unsigned int regno
, uval
, num_vals
;
5383 operand
= (const struct mips_reg_operand
*) operand_base
;
5384 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5387 if (operand
->reg_map
)
5389 num_vals
= 1 << operand
->root
.size
;
5390 for (uval
= 0; uval
< num_vals
; uval
++)
5391 if (operand
->reg_map
[uval
] == regno
)
5393 if (num_vals
== uval
)
5399 arg
->last_regno
= regno
;
5400 if (arg
->opnum
== 1)
5401 arg
->dest_regno
= regno
;
5402 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5406 /* OP_REG_PAIR matcher. */
5409 match_reg_pair_operand (struct mips_arg_info
*arg
,
5410 const struct mips_operand
*operand_base
)
5412 const struct mips_reg_pair_operand
*operand
;
5413 unsigned int regno1
, regno2
, uval
, num_vals
;
5415 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5416 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5417 || !match_char (arg
, ',')
5418 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5421 num_vals
= 1 << operand_base
->size
;
5422 for (uval
= 0; uval
< num_vals
; uval
++)
5423 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5425 if (uval
== num_vals
)
5428 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5432 /* OP_PCREL matcher. The caller chooses the relocation type. */
5435 match_pcrel_operand (struct mips_arg_info
*arg
)
5437 bfd_reloc_code_real_type r
[3];
5439 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5442 /* OP_PERF_REG matcher. */
5445 match_perf_reg_operand (struct mips_arg_info
*arg
,
5446 const struct mips_operand
*operand
)
5450 if (!match_const_int (arg
, &sval
))
5455 || (mips_opts
.arch
== CPU_R5900
5456 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5457 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5459 set_insn_error (arg
->argnum
, _("invalid performance register"));
5463 insn_insert_operand (arg
->insn
, operand
, sval
);
5467 /* OP_ADDIUSP matcher. */
5470 match_addiusp_operand (struct mips_arg_info
*arg
,
5471 const struct mips_operand
*operand
)
5476 if (!match_const_int (arg
, &sval
))
5481 match_out_of_range (arg
);
5486 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5488 match_out_of_range (arg
);
5492 uval
= (unsigned int) sval
;
5493 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5494 insn_insert_operand (arg
->insn
, operand
, uval
);
5498 /* OP_CLO_CLZ_DEST matcher. */
5501 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5502 const struct mips_operand
*operand
)
5506 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5509 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5513 /* OP_CHECK_PREV matcher. */
5516 match_check_prev_operand (struct mips_arg_info
*arg
,
5517 const struct mips_operand
*operand_base
)
5519 const struct mips_check_prev_operand
*operand
;
5522 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5524 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5527 if (!operand
->zero_ok
&& regno
== 0)
5530 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5531 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5532 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5534 arg
->last_regno
= regno
;
5535 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5542 /* OP_SAME_RS_RT matcher. */
5545 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5546 const struct mips_operand
*operand
)
5550 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5555 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5559 arg
->last_regno
= regno
;
5561 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5565 /* OP_LWM_SWM_LIST matcher. */
5568 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5569 const struct mips_operand
*operand
)
5571 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5572 struct mips_arg_info reset
;
5575 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5579 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5584 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5587 while (match_char (arg
, ',')
5588 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5591 if (operand
->size
== 2)
5593 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5599 and any permutations of these. */
5600 if ((reglist
& 0xfff1ffff) != 0x80010000)
5603 sregs
= (reglist
>> 17) & 7;
5608 /* The list must include at least one of ra and s0-sN,
5609 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5610 which are $23 and $30 respectively.) E.g.:
5618 and any permutations of these. */
5619 if ((reglist
& 0x3f00ffff) != 0)
5622 ra
= (reglist
>> 27) & 0x10;
5623 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5626 if ((sregs
& -sregs
) != sregs
)
5629 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5633 /* OP_ENTRY_EXIT_LIST matcher. */
5636 match_entry_exit_operand (struct mips_arg_info
*arg
,
5637 const struct mips_operand
*operand
)
5640 bfd_boolean is_exit
;
5642 /* The format is the same for both ENTRY and EXIT, but the constraints
5644 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5645 mask
= (is_exit
? 7 << 3 : 0);
5648 unsigned int regno1
, regno2
;
5649 bfd_boolean is_freg
;
5651 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5653 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5658 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5661 mask
|= (5 + regno2
) << 3;
5663 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5664 mask
|= (regno2
- 3) << 3;
5665 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5666 mask
|= (regno2
- 15) << 1;
5667 else if (regno1
== RA
&& regno2
== RA
)
5672 while (match_char (arg
, ','));
5674 insn_insert_operand (arg
->insn
, operand
, mask
);
5678 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5679 the argument register mask AMASK, the number of static registers
5680 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5681 respectively, and the frame size FRAME_SIZE. */
5684 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5685 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5686 unsigned int frame_size
)
5688 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5689 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5692 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5693 argument register mask AMASK, the number of static registers saved
5694 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5695 respectively, and the frame size FRAME_SIZE. */
5698 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5699 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5700 unsigned int frame_size
)
5704 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5705 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5706 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5707 | ((frame_size
& 0xf0) << 16));
5711 /* OP_SAVE_RESTORE_LIST matcher. */
5714 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5716 unsigned int opcode
, args
, statics
, sregs
;
5717 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5718 unsigned int arg_mask
, ra
, s0
, s1
;
5721 opcode
= arg
->insn
->insn_opcode
;
5723 num_frame_sizes
= 0;
5732 unsigned int regno1
, regno2
;
5734 if (arg
->token
->type
== OT_INTEGER
)
5736 /* Handle the frame size. */
5737 if (!match_const_int (arg
, &frame_size
))
5739 num_frame_sizes
+= 1;
5743 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5746 while (regno1
<= regno2
)
5748 if (regno1
>= 4 && regno1
<= 7)
5750 if (num_frame_sizes
== 0)
5752 args
|= 1 << (regno1
- 4);
5754 /* statics $a0-$a3 */
5755 statics
|= 1 << (regno1
- 4);
5757 else if (regno1
>= 16 && regno1
<= 23)
5759 sregs
|= 1 << (regno1
- 16);
5760 else if (regno1
== 30)
5763 else if (regno1
== 31)
5764 /* Add $ra to insn. */
5774 while (match_char (arg
, ','));
5776 /* Encode args/statics combination. */
5779 else if (args
== 0xf)
5780 /* All $a0-$a3 are args. */
5781 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5782 else if (statics
== 0xf)
5783 /* All $a0-$a3 are statics. */
5784 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5787 /* Count arg registers. */
5797 /* Count static registers. */
5799 while (statics
& 0x8)
5801 statics
= (statics
<< 1) & 0xf;
5807 /* Encode args/statics. */
5808 arg_mask
= (num_args
<< 2) | num_statics
;
5811 /* Encode $s0/$s1. */
5812 if (sregs
& (1 << 0)) /* $s0 */
5814 if (sregs
& (1 << 1)) /* $s1 */
5818 /* Encode $s2-$s8. */
5828 /* Encode frame size. */
5829 if (num_frame_sizes
== 0)
5831 set_insn_error (arg
->argnum
, _("missing frame size"));
5834 if (num_frame_sizes
> 1)
5836 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5839 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5841 set_insn_error (arg
->argnum
, _("invalid frame size"));
5846 /* Finally build the instruction. */
5847 if (mips_opts
.mips16
)
5848 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5850 else if (!mips_opts
.micromips
)
5851 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5856 arg
->insn
->insn_opcode
= opcode
;
5860 /* OP_MDMX_IMM_REG matcher. */
5863 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5864 const struct mips_operand
*operand
)
5866 unsigned int regno
, uval
;
5868 const struct mips_opcode
*opcode
;
5870 /* The mips_opcode records whether this is an octobyte or quadhalf
5871 instruction. Start out with that bit in place. */
5872 opcode
= arg
->insn
->insn_mo
;
5873 uval
= mips_extract_operand (operand
, opcode
->match
);
5874 is_qh
= (uval
!= 0);
5876 if (arg
->token
->type
== OT_REG
)
5878 if ((opcode
->membership
& INSN_5400
)
5879 && strcmp (opcode
->name
, "rzu.ob") == 0)
5881 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5886 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5890 /* Check whether this is a vector register or a broadcast of
5891 a single element. */
5892 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5894 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5896 set_insn_error (arg
->argnum
, _("invalid element selector"));
5899 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5904 /* A full vector. */
5905 if ((opcode
->membership
& INSN_5400
)
5906 && (strcmp (opcode
->name
, "sll.ob") == 0
5907 || strcmp (opcode
->name
, "srl.ob") == 0))
5909 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5915 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5917 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5925 if (!match_const_int (arg
, &sval
))
5927 if (sval
< 0 || sval
> 31)
5929 match_out_of_range (arg
);
5932 uval
|= (sval
& 31);
5934 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5936 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5938 insn_insert_operand (arg
->insn
, operand
, uval
);
5942 /* OP_IMM_INDEX matcher. */
5945 match_imm_index_operand (struct mips_arg_info
*arg
,
5946 const struct mips_operand
*operand
)
5948 unsigned int max_val
;
5950 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5953 max_val
= (1 << operand
->size
) - 1;
5954 if (arg
->token
->u
.index
> max_val
)
5956 match_out_of_range (arg
);
5959 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5964 /* OP_REG_INDEX matcher. */
5967 match_reg_index_operand (struct mips_arg_info
*arg
,
5968 const struct mips_operand
*operand
)
5972 if (arg
->token
->type
!= OT_REG_INDEX
)
5975 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5978 insn_insert_operand (arg
->insn
, operand
, regno
);
5983 /* OP_PC matcher. */
5986 match_pc_operand (struct mips_arg_info
*arg
)
5988 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5996 /* OP_REG28 matcher. */
5999 match_reg28_operand (struct mips_arg_info
*arg
)
6003 if (arg
->token
->type
== OT_REG
6004 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
6013 /* OP_NON_ZERO_REG matcher. */
6016 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6017 const struct mips_operand
*operand
)
6021 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6026 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6030 arg
->last_regno
= regno
;
6031 insn_insert_operand (arg
->insn
, operand
, regno
);
6035 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6036 register that we need to match. */
6039 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6043 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6046 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6047 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6048 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6050 Return the constant in IMM and OFFSET as follows:
6052 - If the constant should be loaded via memory, set IMM to O_absent and
6053 OFFSET to the memory address.
6055 - Otherwise, if the constant should be loaded into two 32-bit registers,
6056 set IMM to the O_constant to load into the high register and OFFSET
6057 to the corresponding value for the low register.
6059 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6061 These constants only appear as the last operand in an instruction,
6062 and every instruction that accepts them in any variant accepts them
6063 in all variants. This means we don't have to worry about backing out
6064 any changes if the instruction does not match. We just match
6065 unconditionally and report an error if the constant is invalid. */
6068 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6069 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6074 const char *newname
;
6075 unsigned char *data
;
6077 /* Where the constant is placed is based on how the MIPS assembler
6080 length == 4 && using_gprs -- immediate value only
6081 length == 8 && using_gprs -- .rdata or immediate value
6082 length == 4 && !using_gprs -- .lit4 or immediate value
6083 length == 8 && !using_gprs -- .lit8 or immediate value
6085 The .lit4 and .lit8 sections are only used if permitted by the
6087 if (arg
->token
->type
!= OT_FLOAT
)
6089 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6093 gas_assert (arg
->token
->u
.flt
.length
== length
);
6094 data
= arg
->token
->u
.flt
.data
;
6097 /* Handle 32-bit constants for which an immediate value is best. */
6100 || g_switch_value
< 4
6101 || (data
[0] == 0 && data
[1] == 0)
6102 || (data
[2] == 0 && data
[3] == 0)))
6104 imm
->X_op
= O_constant
;
6105 if (!target_big_endian
)
6106 imm
->X_add_number
= bfd_getl32 (data
);
6108 imm
->X_add_number
= bfd_getb32 (data
);
6109 offset
->X_op
= O_absent
;
6113 /* Handle 64-bit constants for which an immediate value is best. */
6115 && !mips_disable_float_construction
6116 /* Constants can only be constructed in GPRs and copied to FPRs if the
6117 GPRs are at least as wide as the FPRs or MTHC1 is available.
6118 Unlike most tests for 32-bit floating-point registers this check
6119 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6120 permit 64-bit moves without MXHC1.
6121 Force the constant into memory otherwise. */
6124 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6126 && ((data
[0] == 0 && data
[1] == 0)
6127 || (data
[2] == 0 && data
[3] == 0))
6128 && ((data
[4] == 0 && data
[5] == 0)
6129 || (data
[6] == 0 && data
[7] == 0)))
6131 /* The value is simple enough to load with a couple of instructions.
6132 If using 32-bit registers, set IMM to the high order 32 bits and
6133 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6135 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6137 imm
->X_op
= O_constant
;
6138 offset
->X_op
= O_constant
;
6139 if (!target_big_endian
)
6141 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6142 offset
->X_add_number
= bfd_getl32 (data
);
6146 imm
->X_add_number
= bfd_getb32 (data
);
6147 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6149 if (offset
->X_add_number
== 0)
6150 offset
->X_op
= O_absent
;
6154 imm
->X_op
= O_constant
;
6155 if (!target_big_endian
)
6156 imm
->X_add_number
= bfd_getl64 (data
);
6158 imm
->X_add_number
= bfd_getb64 (data
);
6159 offset
->X_op
= O_absent
;
6164 /* Switch to the right section. */
6166 subseg
= now_subseg
;
6169 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6174 if (using_gprs
|| g_switch_value
< 8)
6175 newname
= RDATA_SECTION_NAME
;
6180 new_seg
= subseg_new (newname
, (subsegT
) 0);
6181 bfd_set_section_flags (new_seg
,
6182 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6183 frag_align (length
== 4 ? 2 : 3, 0, 0);
6184 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6185 record_alignment (new_seg
, 4);
6187 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6189 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6191 /* Set the argument to the current address in the section. */
6192 imm
->X_op
= O_absent
;
6193 offset
->X_op
= O_symbol
;
6194 offset
->X_add_symbol
= symbol_temp_new_now ();
6195 offset
->X_add_number
= 0;
6197 /* Put the floating point number into the section. */
6198 p
= frag_more (length
);
6199 memcpy (p
, data
, length
);
6201 /* Switch back to the original section. */
6202 subseg_set (seg
, subseg
);
6206 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6210 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6211 const struct mips_operand
*operand
,
6212 bfd_boolean match_p
)
6216 /* The operand can be an XYZW mask or a single 2-bit channel index
6217 (with X being 0). */
6218 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6220 /* The suffix can be omitted when it is already part of the opcode. */
6221 if (arg
->token
->type
!= OT_CHANNELS
)
6224 uval
= arg
->token
->u
.channels
;
6225 if (operand
->size
== 2)
6227 /* Check that a single bit is set and convert it into a 2-bit index. */
6228 if ((uval
& -uval
) != uval
)
6230 uval
= 4 - ffs (uval
);
6233 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6238 insn_insert_operand (arg
->insn
, operand
, uval
);
6242 /* Try to match a token from ARG against OPERAND. Consume the token
6243 and return true on success, otherwise return false. */
6246 match_operand (struct mips_arg_info
*arg
,
6247 const struct mips_operand
*operand
)
6249 switch (operand
->type
)
6252 return match_int_operand (arg
, operand
);
6255 return match_mapped_int_operand (arg
, operand
);
6258 return match_msb_operand (arg
, operand
);
6261 case OP_OPTIONAL_REG
:
6262 return match_reg_operand (arg
, operand
);
6265 return match_reg_pair_operand (arg
, operand
);
6268 return match_pcrel_operand (arg
);
6271 return match_perf_reg_operand (arg
, operand
);
6273 case OP_ADDIUSP_INT
:
6274 return match_addiusp_operand (arg
, operand
);
6276 case OP_CLO_CLZ_DEST
:
6277 return match_clo_clz_dest_operand (arg
, operand
);
6279 case OP_LWM_SWM_LIST
:
6280 return match_lwm_swm_list_operand (arg
, operand
);
6282 case OP_ENTRY_EXIT_LIST
:
6283 return match_entry_exit_operand (arg
, operand
);
6285 case OP_SAVE_RESTORE_LIST
:
6286 return match_save_restore_list_operand (arg
);
6288 case OP_MDMX_IMM_REG
:
6289 return match_mdmx_imm_reg_operand (arg
, operand
);
6291 case OP_REPEAT_DEST_REG
:
6292 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6294 case OP_REPEAT_PREV_REG
:
6295 return match_tied_reg_operand (arg
, arg
->last_regno
);
6298 return match_pc_operand (arg
);
6301 return match_reg28_operand (arg
);
6304 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6306 case OP_VU0_MATCH_SUFFIX
:
6307 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6310 return match_imm_index_operand (arg
, operand
);
6313 return match_reg_index_operand (arg
, operand
);
6316 return match_same_rs_rt_operand (arg
, operand
);
6319 return match_check_prev_operand (arg
, operand
);
6321 case OP_NON_ZERO_REG
:
6322 return match_non_zero_reg_operand (arg
, operand
);
6327 /* ARG is the state after successfully matching an instruction.
6328 Issue any queued-up warnings. */
6331 check_completed_insn (struct mips_arg_info
*arg
)
6336 as_warn (_("used $at without \".set noat\""));
6338 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6342 /* Return true if modifying general-purpose register REG needs a delay. */
6345 reg_needs_delay (unsigned int reg
)
6347 unsigned long prev_pinfo
;
6349 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6350 if (!mips_opts
.noreorder
6351 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6352 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6353 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6359 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6360 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6361 by VR4120 errata. */
6364 classify_vr4120_insn (const char *name
)
6366 if (strncmp (name
, "macc", 4) == 0)
6367 return FIX_VR4120_MACC
;
6368 if (strncmp (name
, "dmacc", 5) == 0)
6369 return FIX_VR4120_DMACC
;
6370 if (strncmp (name
, "mult", 4) == 0)
6371 return FIX_VR4120_MULT
;
6372 if (strncmp (name
, "dmult", 5) == 0)
6373 return FIX_VR4120_DMULT
;
6374 if (strstr (name
, "div"))
6375 return FIX_VR4120_DIV
;
6376 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6377 return FIX_VR4120_MTHILO
;
6378 return NUM_FIX_VR4120_CLASSES
;
6381 #define INSN_ERET 0x42000018
6382 #define INSN_DERET 0x4200001f
6383 #define INSN_DMULT 0x1c
6384 #define INSN_DMULTU 0x1d
6386 /* Return the number of instructions that must separate INSN1 and INSN2,
6387 where INSN1 is the earlier instruction. Return the worst-case value
6388 for any INSN2 if INSN2 is null. */
6391 insns_between (const struct mips_cl_insn
*insn1
,
6392 const struct mips_cl_insn
*insn2
)
6394 unsigned long pinfo1
, pinfo2
;
6397 /* If INFO2 is null, pessimistically assume that all flags are set for
6398 the second instruction. */
6399 pinfo1
= insn1
->insn_mo
->pinfo
;
6400 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6402 /* For most targets, write-after-read dependencies on the HI and LO
6403 registers must be separated by at least two instructions. */
6404 if (!hilo_interlocks
)
6406 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6408 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6412 /* If we're working around r7000 errata, there must be two instructions
6413 between an mfhi or mflo and any instruction that uses the result. */
6414 if (mips_7000_hilo_fix
6415 && !mips_opts
.micromips
6416 && MF_HILO_INSN (pinfo1
)
6417 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6420 /* If we're working around 24K errata, one instruction is required
6421 if an ERET or DERET is followed by a branch instruction. */
6422 if (mips_fix_24k
&& !mips_opts
.micromips
)
6424 if (insn1
->insn_opcode
== INSN_ERET
6425 || insn1
->insn_opcode
== INSN_DERET
)
6428 || insn2
->insn_opcode
== INSN_ERET
6429 || insn2
->insn_opcode
== INSN_DERET
6430 || delayed_branch_p (insn2
))
6435 /* If we're working around PMC RM7000 errata, there must be three
6436 nops between a dmult and a load instruction. */
6437 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6439 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6440 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6442 if (pinfo2
& INSN_LOAD_MEMORY
)
6447 /* If working around VR4120 errata, check for combinations that need
6448 a single intervening instruction. */
6449 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6451 unsigned int class1
, class2
;
6453 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6454 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6458 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6459 if (vr4120_conflicts
[class1
] & (1 << class2
))
6464 if (!HAVE_CODE_COMPRESSION
)
6466 /* Check for GPR or coprocessor load delays. All such delays
6467 are on the RT register. */
6468 /* Itbl support may require additional care here. */
6469 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6470 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6472 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6476 /* Check for generic coprocessor hazards.
6478 This case is not handled very well. There is no special
6479 knowledge of CP0 handling, and the coprocessors other than
6480 the floating point unit are not distinguished at all. */
6481 /* Itbl support may require additional care here. FIXME!
6482 Need to modify this to include knowledge about
6483 user specified delays! */
6484 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6485 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6487 /* Handle cases where INSN1 writes to a known general coprocessor
6488 register. There must be a one instruction delay before INSN2
6489 if INSN2 reads that register, otherwise no delay is needed. */
6490 mask
= fpr_write_mask (insn1
);
6493 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6498 /* Read-after-write dependencies on the control registers
6499 require a two-instruction gap. */
6500 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6501 && (pinfo2
& INSN_READ_COND_CODE
))
6504 /* We don't know exactly what INSN1 does. If INSN2 is
6505 also a coprocessor instruction, assume there must be
6506 a one instruction gap. */
6507 if (pinfo2
& INSN_COP
)
6512 /* Check for read-after-write dependencies on the coprocessor
6513 control registers in cases where INSN1 does not need a general
6514 coprocessor delay. This means that INSN1 is a floating point
6515 comparison instruction. */
6516 /* Itbl support may require additional care here. */
6517 else if (!cop_interlocks
6518 && (pinfo1
& INSN_WRITE_COND_CODE
)
6519 && (pinfo2
& INSN_READ_COND_CODE
))
6523 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6524 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6526 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6527 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6528 || (insn2
&& delayed_branch_p (insn2
))))
6534 /* Return the number of nops that would be needed to work around the
6535 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6536 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6537 that are contained within the first IGNORE instructions of HIST. */
6540 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6541 const struct mips_cl_insn
*insn
)
6546 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6547 are not affected by the errata. */
6549 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6550 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6551 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6554 /* Search for the first MFLO or MFHI. */
6555 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6556 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6558 /* Extract the destination register. */
6559 mask
= gpr_write_mask (&hist
[i
]);
6561 /* No nops are needed if INSN reads that register. */
6562 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6565 /* ...or if any of the intervening instructions do. */
6566 for (j
= 0; j
< i
; j
++)
6567 if (gpr_read_mask (&hist
[j
]) & mask
)
6571 return MAX_VR4130_NOPS
- i
;
6576 #define BASE_REG_EQ(INSN1, INSN2) \
6577 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6578 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6580 /* Return the minimum alignment for this store instruction. */
6583 fix_24k_align_to (const struct mips_opcode
*mo
)
6585 if (strcmp (mo
->name
, "sh") == 0)
6588 if (strcmp (mo
->name
, "swc1") == 0
6589 || strcmp (mo
->name
, "swc2") == 0
6590 || strcmp (mo
->name
, "sw") == 0
6591 || strcmp (mo
->name
, "sc") == 0
6592 || strcmp (mo
->name
, "s.s") == 0)
6595 if (strcmp (mo
->name
, "sdc1") == 0
6596 || strcmp (mo
->name
, "sdc2") == 0
6597 || strcmp (mo
->name
, "s.d") == 0)
6604 struct fix_24k_store_info
6606 /* Immediate offset, if any, for this store instruction. */
6608 /* Alignment required by this store instruction. */
6610 /* True for register offsets. */
6611 int register_offset
;
6614 /* Comparison function used by qsort. */
6617 fix_24k_sort (const void *a
, const void *b
)
6619 const struct fix_24k_store_info
*pos1
= a
;
6620 const struct fix_24k_store_info
*pos2
= b
;
6622 return (pos1
->off
- pos2
->off
);
6625 /* INSN is a store instruction. Try to record the store information
6626 in STINFO. Return false if the information isn't known. */
6629 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6630 const struct mips_cl_insn
*insn
)
6632 /* The instruction must have a known offset. */
6633 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6636 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6637 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6641 /* Return the number of nops that would be needed to work around the 24k
6642 "lost data on stores during refill" errata if instruction INSN
6643 immediately followed the 2 instructions described by HIST.
6644 Ignore hazards that are contained within the first IGNORE
6645 instructions of HIST.
6647 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6648 for the data cache refills and store data. The following describes
6649 the scenario where the store data could be lost.
6651 * A data cache miss, due to either a load or a store, causing fill
6652 data to be supplied by the memory subsystem
6653 * The first three doublewords of fill data are returned and written
6655 * A sequence of four stores occurs in consecutive cycles around the
6656 final doubleword of the fill:
6660 * Zero, One or more instructions
6663 The four stores A-D must be to different doublewords of the line that
6664 is being filled. The fourth instruction in the sequence above permits
6665 the fill of the final doubleword to be transferred from the FSB into
6666 the cache. In the sequence above, the stores may be either integer
6667 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6668 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6669 different doublewords on the line. If the floating point unit is
6670 running in 1:2 mode, it is not possible to create the sequence above
6671 using only floating point store instructions.
6673 In this case, the cache line being filled is incorrectly marked
6674 invalid, thereby losing the data from any store to the line that
6675 occurs between the original miss and the completion of the five
6676 cycle sequence shown above.
6678 The workarounds are:
6680 * Run the data cache in write-through mode.
6681 * Insert a non-store instruction between
6682 Store A and Store B or Store B and Store C. */
6685 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6686 const struct mips_cl_insn
*insn
)
6688 struct fix_24k_store_info pos
[3];
6689 int align
, i
, base_offset
;
6694 /* If the previous instruction wasn't a store, there's nothing to
6696 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6699 /* If the instructions after the previous one are unknown, we have
6700 to assume the worst. */
6704 /* Check whether we are dealing with three consecutive stores. */
6705 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6706 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6709 /* If we don't know the relationship between the store addresses,
6710 assume the worst. */
6711 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6712 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6715 if (!fix_24k_record_store_info (&pos
[0], insn
)
6716 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6717 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6720 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6722 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6723 X bytes and such that the base register + X is known to be aligned
6726 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6730 align
= pos
[0].align_to
;
6731 base_offset
= pos
[0].off
;
6732 for (i
= 1; i
< 3; i
++)
6733 if (align
< pos
[i
].align_to
)
6735 align
= pos
[i
].align_to
;
6736 base_offset
= pos
[i
].off
;
6738 for (i
= 0; i
< 3; i
++)
6739 pos
[i
].off
-= base_offset
;
6742 pos
[0].off
&= ~align
+ 1;
6743 pos
[1].off
&= ~align
+ 1;
6744 pos
[2].off
&= ~align
+ 1;
6746 /* If any two stores write to the same chunk, they also write to the
6747 same doubleword. The offsets are still sorted at this point. */
6748 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6751 /* A range of at least 9 bytes is needed for the stores to be in
6752 non-overlapping doublewords. */
6753 if (pos
[2].off
- pos
[0].off
<= 8)
6756 if (pos
[2].off
- pos
[1].off
>= 24
6757 || pos
[1].off
- pos
[0].off
>= 24
6758 || pos
[2].off
- pos
[0].off
>= 32)
6764 /* Return the number of nops that would be needed if instruction INSN
6765 immediately followed the MAX_NOPS instructions given by HIST,
6766 where HIST[0] is the most recent instruction. Ignore hazards
6767 between INSN and the first IGNORE instructions in HIST.
6769 If INSN is null, return the worse-case number of nops for any
6773 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6774 const struct mips_cl_insn
*insn
)
6776 int i
, nops
, tmp_nops
;
6779 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6781 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6782 if (tmp_nops
> nops
)
6786 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6788 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6789 if (tmp_nops
> nops
)
6793 if (mips_fix_24k
&& !mips_opts
.micromips
)
6795 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6796 if (tmp_nops
> nops
)
6803 /* The variable arguments provide NUM_INSNS extra instructions that
6804 might be added to HIST. Return the largest number of nops that
6805 would be needed after the extended sequence, ignoring hazards
6806 in the first IGNORE instructions. */
6809 nops_for_sequence (int num_insns
, int ignore
,
6810 const struct mips_cl_insn
*hist
, ...)
6813 struct mips_cl_insn buffer
[MAX_NOPS
];
6814 struct mips_cl_insn
*cursor
;
6817 va_start (args
, hist
);
6818 cursor
= buffer
+ num_insns
;
6819 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6820 while (cursor
> buffer
)
6821 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6823 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6828 /* Like nops_for_insn, but if INSN is a branch, take into account the
6829 worst-case delay for the branch target. */
6832 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6833 const struct mips_cl_insn
*insn
)
6837 nops
= nops_for_insn (ignore
, hist
, insn
);
6838 if (delayed_branch_p (insn
))
6840 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6841 hist
, insn
, get_delay_slot_nop (insn
));
6842 if (tmp_nops
> nops
)
6845 else if (compact_branch_p (insn
))
6847 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6848 if (tmp_nops
> nops
)
6854 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6857 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6859 gas_assert (!HAVE_CODE_COMPRESSION
);
6860 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6861 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6864 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6865 jr target pc &= 'hffff_ffff_cfff_ffff. */
6868 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6870 gas_assert (!HAVE_CODE_COMPRESSION
);
6871 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6872 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6873 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6881 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6882 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6885 ep
.X_op
= O_constant
;
6886 ep
.X_add_number
= 0xcfff0000;
6887 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6888 ep
.X_add_number
= 0xffff;
6889 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6890 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6895 fix_loongson2f (struct mips_cl_insn
* ip
)
6897 if (mips_fix_loongson2f_nop
)
6898 fix_loongson2f_nop (ip
);
6900 if (mips_fix_loongson2f_jump
)
6901 fix_loongson2f_jump (ip
);
6904 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6907 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6909 gas_assert (!HAVE_CODE_COMPRESSION
);
6911 /* If is an local label and the insn is not sync,
6912 look forward that whether an branch between ll/sc jump to here
6913 if so, insert a sync. */
6914 if (seg_info (now_seg
)->label_list
6915 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6916 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6918 const char *label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6919 unsigned long lookback
= ARRAY_SIZE (history
);
6922 for (i
= 0; i
< lookback
; i
++)
6924 if (streq (history
[i
].insn_mo
->name
, "ll")
6925 || streq (history
[i
].insn_mo
->name
, "lld"))
6928 if (streq (history
[i
].insn_mo
->name
, "sc")
6929 || streq (history
[i
].insn_mo
->name
, "scd"))
6933 for (j
= i
+ 1; j
< lookback
; j
++)
6935 if (streq (history
[i
].insn_mo
->name
, "ll")
6936 || streq (history
[i
].insn_mo
->name
, "lld"))
6939 if (delayed_branch_p (&history
[j
]))
6941 if (streq (history
[j
].target
, label_name
))
6943 add_fixed_insn (&sync_insn
);
6944 insert_into_history (0, 1, &sync_insn
);
6953 /* If we find a sc, we look forward to look for an branch insn,
6954 and see whether it jump back and out of ll/sc. */
6955 else if (streq(ip
->insn_mo
->name
, "sc") || streq(ip
->insn_mo
->name
, "scd"))
6957 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6960 for (i
= 0; i
< lookback
; i
++)
6962 if (streq (history
[i
].insn_mo
->name
, "ll")
6963 || streq (history
[i
].insn_mo
->name
, "lld"))
6966 if (delayed_branch_p (&history
[i
]))
6970 for (j
= i
+ 1; j
< lookback
; j
++)
6972 if (streq (history
[j
].insn_mo
->name
, "ll")
6973 || streq (history
[i
].insn_mo
->name
, "lld"))
6977 for (; j
< lookback
; j
++)
6979 if (history
[j
].label
[0] != '\0'
6980 && streq (history
[j
].label
, history
[i
].target
)
6981 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
6983 add_fixed_insn (&sync_insn
);
6984 insert_into_history (++j
, 1, &sync_insn
);
6991 /* Skip if there is a sync before ll/lld. */
6992 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
6993 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
6994 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
6996 add_fixed_insn (&sync_insn
);
6997 insert_into_history (0, 1, &sync_insn
);
7001 /* IP is a branch that has a delay slot, and we need to fill it
7002 automatically. Return true if we can do that by swapping IP
7003 with the previous instruction.
7004 ADDRESS_EXPR is an operand of the instruction to be used with
7008 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7009 bfd_reloc_code_real_type
*reloc_type
)
7011 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7012 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7013 unsigned int fpr_read
, prev_fpr_write
;
7015 /* -O2 and above is required for this optimization. */
7016 if (mips_optimize
< 2)
7019 /* If we have seen .set volatile or .set nomove, don't optimize. */
7020 if (mips_opts
.nomove
)
7023 /* We can't swap if the previous instruction's position is fixed. */
7024 if (history
[0].fixed_p
)
7027 /* If the previous previous insn was in a .set noreorder, we can't
7028 swap. Actually, the MIPS assembler will swap in this situation.
7029 However, gcc configured -with-gnu-as will generate code like
7037 in which we can not swap the bne and INSN. If gcc is not configured
7038 -with-gnu-as, it does not output the .set pseudo-ops. */
7039 if (history
[1].noreorder_p
)
7042 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7043 This means that the previous instruction was a 4-byte one anyhow. */
7044 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7047 /* If the branch is itself the target of a branch, we can not swap.
7048 We cheat on this; all we check for is whether there is a label on
7049 this instruction. If there are any branches to anything other than
7050 a label, users must use .set noreorder. */
7051 if (seg_info (now_seg
)->label_list
)
7054 /* If the previous instruction is in a variant frag other than this
7055 branch's one, we cannot do the swap. This does not apply to
7056 MIPS16 code, which uses variant frags for different purposes. */
7057 if (!mips_opts
.mips16
7059 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7062 /* We do not swap with instructions that cannot architecturally
7063 be placed in a branch delay slot, such as SYNC or ERET. We
7064 also refrain from swapping with a trap instruction, since it
7065 complicates trap handlers to have the trap instruction be in
7067 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7068 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7071 /* Check for conflicts between the branch and the instructions
7072 before the candidate delay slot. */
7073 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7076 /* Check for conflicts between the swapped sequence and the
7077 target of the branch. */
7078 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7081 /* If the branch reads a register that the previous
7082 instruction sets, we can not swap. */
7083 gpr_read
= gpr_read_mask (ip
);
7084 prev_gpr_write
= gpr_write_mask (&history
[0]);
7085 if (gpr_read
& prev_gpr_write
)
7088 fpr_read
= fpr_read_mask (ip
);
7089 prev_fpr_write
= fpr_write_mask (&history
[0]);
7090 if (fpr_read
& prev_fpr_write
)
7093 /* If the branch writes a register that the previous
7094 instruction sets, we can not swap. */
7095 gpr_write
= gpr_write_mask (ip
);
7096 if (gpr_write
& prev_gpr_write
)
7099 /* If the branch writes a register that the previous
7100 instruction reads, we can not swap. */
7101 prev_gpr_read
= gpr_read_mask (&history
[0]);
7102 if (gpr_write
& prev_gpr_read
)
7105 /* If one instruction sets a condition code and the
7106 other one uses a condition code, we can not swap. */
7107 pinfo
= ip
->insn_mo
->pinfo
;
7108 if ((pinfo
& INSN_READ_COND_CODE
)
7109 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7111 if ((pinfo
& INSN_WRITE_COND_CODE
)
7112 && (prev_pinfo
& INSN_READ_COND_CODE
))
7115 /* If the previous instruction uses the PC, we can not swap. */
7116 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7117 if (prev_pinfo2
& INSN2_READ_PC
)
7120 /* If the previous instruction has an incorrect size for a fixed
7121 branch delay slot in microMIPS mode, we cannot swap. */
7122 pinfo2
= ip
->insn_mo
->pinfo2
;
7123 if (mips_opts
.micromips
7124 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7125 && insn_length (history
) != 2)
7127 if (mips_opts
.micromips
7128 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7129 && insn_length (history
) != 4)
7132 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7135 The short loop bug under certain conditions causes loops to execute
7136 only once or twice. We must ensure that the assembler never
7137 generates loops that satisfy all of the following conditions:
7139 - a loop consists of less than or equal to six instructions
7140 (including the branch delay slot);
7141 - a loop contains only one conditional branch instruction at the end
7143 - a loop does not contain any other branch or jump instructions;
7144 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7146 We need to do this because of a hardware bug in the R5900 chip. */
7148 /* Check if instruction has a parameter, ignore "j $31". */
7149 && (address_expr
!= NULL
)
7150 /* Parameter must be 16 bit. */
7151 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7152 /* Branch to same segment. */
7153 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7154 /* Branch to same code fragment. */
7155 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7156 /* Can only calculate branch offset if value is known. */
7157 && symbol_constant_p (address_expr
->X_add_symbol
)
7158 /* Check if branch is really conditional. */
7159 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7160 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7161 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7164 /* Check if loop is shorter than or equal to 6 instructions
7165 including branch and delay slot. */
7166 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7173 /* When the loop includes branches or jumps,
7174 it is not a short loop. */
7175 for (i
= 0; i
< (distance
/ 4); i
++)
7177 if ((history
[i
].cleared_p
)
7178 || delayed_branch_p (&history
[i
]))
7186 /* Insert nop after branch to fix short loop. */
7195 /* Decide how we should add IP to the instruction stream.
7196 ADDRESS_EXPR is an operand of the instruction to be used with
7199 static enum append_method
7200 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7201 bfd_reloc_code_real_type
*reloc_type
)
7203 /* The relaxed version of a macro sequence must be inherently
7205 if (mips_relax
.sequence
== 2)
7208 /* We must not dabble with instructions in a ".set noreorder" block. */
7209 if (mips_opts
.noreorder
)
7212 /* Otherwise, it's our responsibility to fill branch delay slots. */
7213 if (delayed_branch_p (ip
))
7215 if (!branch_likely_p (ip
)
7216 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7219 if (mips_opts
.mips16
7220 && ISA_SUPPORTS_MIPS16E
7221 && gpr_read_mask (ip
) != 0)
7222 return APPEND_ADD_COMPACT
;
7224 if (mips_opts
.micromips
7225 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7226 || (!forced_insn_length
7227 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7228 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7229 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7230 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7231 return APPEND_ADD_COMPACT
;
7233 return APPEND_ADD_WITH_NOP
;
7239 /* IP is an instruction whose opcode we have just changed, END points
7240 to the end of the opcode table processed. Point IP->insn_mo to the
7241 new opcode's definition. */
7244 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7246 const struct mips_opcode
*mo
;
7248 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7249 if (mo
->pinfo
!= INSN_MACRO
7250 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7258 /* IP is a MIPS16 instruction whose opcode we have just changed.
7259 Point IP->insn_mo to the new opcode's definition. */
7262 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7264 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7267 /* IP is a microMIPS instruction whose opcode we have just changed.
7268 Point IP->insn_mo to the new opcode's definition. */
7271 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7273 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7276 /* For microMIPS macros, we need to generate a local number label
7277 as the target of branches. */
7278 #define MICROMIPS_LABEL_CHAR '\037'
7279 static unsigned long micromips_target_label
;
7280 static char micromips_target_name
[32];
7283 micromips_label_name (void)
7285 char *p
= micromips_target_name
;
7286 char symbol_name_temporary
[24];
7294 l
= micromips_target_label
;
7295 #ifdef LOCAL_LABEL_PREFIX
7296 *p
++ = LOCAL_LABEL_PREFIX
;
7299 *p
++ = MICROMIPS_LABEL_CHAR
;
7302 symbol_name_temporary
[i
++] = l
% 10 + '0';
7307 *p
++ = symbol_name_temporary
[--i
];
7310 return micromips_target_name
;
7314 micromips_label_expr (expressionS
*label_expr
)
7316 label_expr
->X_op
= O_symbol
;
7317 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7318 label_expr
->X_add_number
= 0;
7322 micromips_label_inc (void)
7324 micromips_target_label
++;
7325 *micromips_target_name
= '\0';
7329 micromips_add_label (void)
7333 s
= colon (micromips_label_name ());
7334 micromips_label_inc ();
7335 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7338 /* If assembling microMIPS code, then return the microMIPS reloc
7339 corresponding to the requested one if any. Otherwise return
7340 the reloc unchanged. */
7342 static bfd_reloc_code_real_type
7343 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7345 static const bfd_reloc_code_real_type relocs
[][2] =
7347 /* Keep sorted incrementally by the left-hand key. */
7348 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7349 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7350 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7351 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7352 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7353 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7354 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7355 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7356 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7357 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7358 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7359 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7360 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7361 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7362 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7363 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7364 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7365 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7366 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7367 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7368 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7369 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7370 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7371 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7372 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7373 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7374 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7376 bfd_reloc_code_real_type r
;
7379 if (!mips_opts
.micromips
)
7381 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7387 return relocs
[i
][1];
7392 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7393 Return true on success, storing the resolved value in RESULT. */
7396 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7401 case BFD_RELOC_MIPS_HIGHEST
:
7402 case BFD_RELOC_MICROMIPS_HIGHEST
:
7403 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7406 case BFD_RELOC_MIPS_HIGHER
:
7407 case BFD_RELOC_MICROMIPS_HIGHER
:
7408 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7411 case BFD_RELOC_HI16_S
:
7412 case BFD_RELOC_HI16_S_PCREL
:
7413 case BFD_RELOC_MICROMIPS_HI16_S
:
7414 case BFD_RELOC_MIPS16_HI16_S
:
7415 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7418 case BFD_RELOC_HI16
:
7419 case BFD_RELOC_MICROMIPS_HI16
:
7420 case BFD_RELOC_MIPS16_HI16
:
7421 *result
= (operand
>> 16) & 0xffff;
7424 case BFD_RELOC_LO16
:
7425 case BFD_RELOC_LO16_PCREL
:
7426 case BFD_RELOC_MICROMIPS_LO16
:
7427 case BFD_RELOC_MIPS16_LO16
:
7428 *result
= operand
& 0xffff;
7431 case BFD_RELOC_UNUSED
:
7440 /* Output an instruction. IP is the instruction information.
7441 ADDRESS_EXPR is an operand of the instruction to be used with
7442 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7443 a macro expansion. */
7446 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7447 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7449 unsigned long prev_pinfo2
, pinfo
;
7450 bfd_boolean relaxed_branch
= FALSE
;
7451 enum append_method method
;
7452 bfd_boolean relax32
;
7455 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7456 fix_loongson2f (ip
);
7458 ip
->target
[0] = '\0';
7459 if (offset_expr
.X_op
== O_symbol
)
7460 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7461 ip
->label
[0] = '\0';
7462 if (seg_info (now_seg
)->label_list
)
7463 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7464 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7465 fix_loongson3_llsc (ip
);
7467 file_ase_mips16
|= mips_opts
.mips16
;
7468 file_ase_micromips
|= mips_opts
.micromips
;
7470 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7471 pinfo
= ip
->insn_mo
->pinfo
;
7473 /* Don't raise alarm about `nods' frags as they'll fill in the right
7474 kind of nop in relaxation if required. */
7475 if (mips_opts
.micromips
7477 && !(history
[0].frag
7478 && history
[0].frag
->fr_type
== rs_machine_dependent
7479 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7480 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7481 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7482 && micromips_insn_length (ip
->insn_mo
) != 2)
7483 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7484 && micromips_insn_length (ip
->insn_mo
) != 4)))
7485 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7486 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7488 if (address_expr
== NULL
)
7490 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7491 && reloc_type
[1] == BFD_RELOC_UNUSED
7492 && reloc_type
[2] == BFD_RELOC_UNUSED
7493 && address_expr
->X_op
== O_constant
)
7495 switch (*reloc_type
)
7497 case BFD_RELOC_MIPS_JMP
:
7501 /* Shift is 2, unusually, for microMIPS JALX. */
7502 shift
= (mips_opts
.micromips
7503 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7504 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7505 as_bad (_("jump to misaligned address (0x%lx)"),
7506 (unsigned long) address_expr
->X_add_number
);
7507 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7513 case BFD_RELOC_MIPS16_JMP
:
7514 if ((address_expr
->X_add_number
& 3) != 0)
7515 as_bad (_("jump to misaligned address (0x%lx)"),
7516 (unsigned long) address_expr
->X_add_number
);
7518 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7519 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7520 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7524 case BFD_RELOC_16_PCREL_S2
:
7528 shift
= mips_opts
.micromips
? 1 : 2;
7529 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7530 as_bad (_("branch to misaligned address (0x%lx)"),
7531 (unsigned long) address_expr
->X_add_number
);
7532 if (!mips_relax_branch
)
7534 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7535 & ~((1 << (shift
+ 16)) - 1))
7536 as_bad (_("branch address range overflow (0x%lx)"),
7537 (unsigned long) address_expr
->X_add_number
);
7538 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7544 case BFD_RELOC_MIPS_21_PCREL_S2
:
7549 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7550 as_bad (_("branch to misaligned address (0x%lx)"),
7551 (unsigned long) address_expr
->X_add_number
);
7552 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7553 & ~((1 << (shift
+ 21)) - 1))
7554 as_bad (_("branch address range overflow (0x%lx)"),
7555 (unsigned long) address_expr
->X_add_number
);
7556 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7561 case BFD_RELOC_MIPS_26_PCREL_S2
:
7566 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7567 as_bad (_("branch to misaligned address (0x%lx)"),
7568 (unsigned long) address_expr
->X_add_number
);
7569 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7570 & ~((1 << (shift
+ 26)) - 1))
7571 as_bad (_("branch address range overflow (0x%lx)"),
7572 (unsigned long) address_expr
->X_add_number
);
7573 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7582 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7585 ip
->insn_opcode
|= value
& 0xffff;
7593 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7595 /* There are a lot of optimizations we could do that we don't.
7596 In particular, we do not, in general, reorder instructions.
7597 If you use gcc with optimization, it will reorder
7598 instructions and generally do much more optimization then we
7599 do here; repeating all that work in the assembler would only
7600 benefit hand written assembly code, and does not seem worth
7602 int nops
= (mips_optimize
== 0
7603 ? nops_for_insn (0, history
, NULL
)
7604 : nops_for_insn_or_target (0, history
, ip
));
7608 unsigned long old_frag_offset
;
7611 old_frag
= frag_now
;
7612 old_frag_offset
= frag_now_fix ();
7614 for (i
= 0; i
< nops
; i
++)
7615 add_fixed_insn (NOP_INSN
);
7616 insert_into_history (0, nops
, NOP_INSN
);
7620 listing_prev_line ();
7621 /* We may be at the start of a variant frag. In case we
7622 are, make sure there is enough space for the frag
7623 after the frags created by listing_prev_line. The
7624 argument to frag_grow here must be at least as large
7625 as the argument to all other calls to frag_grow in
7626 this file. We don't have to worry about being in the
7627 middle of a variant frag, because the variants insert
7628 all needed nop instructions themselves. */
7632 mips_move_text_labels ();
7634 #ifndef NO_ECOFF_DEBUGGING
7635 if (ECOFF_DEBUGGING
)
7636 ecoff_fix_loc (old_frag
, old_frag_offset
);
7640 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7644 /* Work out how many nops in prev_nop_frag are needed by IP,
7645 ignoring hazards generated by the first prev_nop_frag_since
7647 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7648 gas_assert (nops
<= prev_nop_frag_holds
);
7650 /* Enforce NOPS as a minimum. */
7651 if (nops
> prev_nop_frag_required
)
7652 prev_nop_frag_required
= nops
;
7654 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7656 /* Settle for the current number of nops. Update the history
7657 accordingly (for the benefit of any future .set reorder code). */
7658 prev_nop_frag
= NULL
;
7659 insert_into_history (prev_nop_frag_since
,
7660 prev_nop_frag_holds
, NOP_INSN
);
7664 /* Allow this instruction to replace one of the nops that was
7665 tentatively added to prev_nop_frag. */
7666 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7667 prev_nop_frag_holds
--;
7668 prev_nop_frag_since
++;
7672 method
= get_append_method (ip
, address_expr
, reloc_type
);
7673 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7675 dwarf2_emit_insn (0);
7676 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7677 so "move" the instruction address accordingly.
7679 Also, it doesn't seem appropriate for the assembler to reorder .loc
7680 entries. If this instruction is a branch that we are going to swap
7681 with the previous instruction, the two instructions should be
7682 treated as a unit, and the debug information for both instructions
7683 should refer to the start of the branch sequence. Using the
7684 current position is certainly wrong when swapping a 32-bit branch
7685 and a 16-bit delay slot, since the current position would then be
7686 in the middle of a branch. */
7687 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7689 relax32
= (mips_relax_branch
7690 /* Don't try branch relaxation within .set nomacro, or within
7691 .set noat if we use $at for PIC computations. If it turns
7692 out that the branch was out-of-range, we'll get an error. */
7693 && !mips_opts
.warn_about_macros
7694 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7695 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7696 as they have no complementing branches. */
7697 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7699 if (!HAVE_CODE_COMPRESSION
7702 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7703 && delayed_branch_p (ip
))
7705 relaxed_branch
= TRUE
;
7706 add_relaxed_insn (ip
, (relaxed_branch_length
7708 uncond_branch_p (ip
) ? -1
7709 : branch_likely_p (ip
) ? 1
7712 (AT
, mips_pic
!= NO_PIC
,
7713 uncond_branch_p (ip
),
7714 branch_likely_p (ip
),
7715 pinfo
& INSN_WRITE_GPR_31
,
7717 address_expr
->X_add_symbol
,
7718 address_expr
->X_add_number
);
7719 *reloc_type
= BFD_RELOC_UNUSED
;
7721 else if (mips_opts
.micromips
7723 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7724 || *reloc_type
> BFD_RELOC_UNUSED
)
7725 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7726 /* Don't try branch relaxation when users specify
7727 16-bit/32-bit instructions. */
7728 && !forced_insn_length
)
7730 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7731 && *reloc_type
> BFD_RELOC_UNUSED
);
7732 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7733 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7734 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7735 int nods
= method
== APPEND_ADD_WITH_NOP
;
7736 int al
= pinfo
& INSN_WRITE_GPR_31
;
7737 int length32
= nods
? 8 : 4;
7739 gas_assert (address_expr
!= NULL
);
7740 gas_assert (!mips_relax
.sequence
);
7742 relaxed_branch
= TRUE
;
7744 method
= APPEND_ADD
;
7746 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7747 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7748 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7750 uncond
, compact
, al
, nods
,
7752 address_expr
->X_add_symbol
,
7753 address_expr
->X_add_number
);
7754 *reloc_type
= BFD_RELOC_UNUSED
;
7756 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7758 bfd_boolean require_unextended
;
7759 bfd_boolean require_extended
;
7763 if (forced_insn_length
!= 0)
7765 require_unextended
= forced_insn_length
== 2;
7766 require_extended
= forced_insn_length
== 4;
7770 require_unextended
= (mips_opts
.noautoextend
7771 && !mips_opcode_32bit_p (ip
->insn_mo
));
7772 require_extended
= 0;
7775 /* We need to set up a variant frag. */
7776 gas_assert (address_expr
!= NULL
);
7777 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7778 symbol created by `make_expr_symbol' may not get a necessary
7779 external relocation produced. */
7780 if (address_expr
->X_op
== O_symbol
)
7782 symbol
= address_expr
->X_add_symbol
;
7783 offset
= address_expr
->X_add_number
;
7787 symbol
= make_expr_symbol (address_expr
);
7788 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7791 add_relaxed_insn (ip
, 12, 0,
7793 (*reloc_type
- BFD_RELOC_UNUSED
,
7794 mips_opts
.ase
& ASE_MIPS16E2
,
7797 mips_opts
.warn_about_macros
,
7798 require_unextended
, require_extended
,
7799 delayed_branch_p (&history
[0]),
7800 history
[0].mips16_absolute_jump_p
),
7803 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7805 if (!delayed_branch_p (ip
))
7806 /* Make sure there is enough room to swap this instruction with
7807 a following jump instruction. */
7809 add_fixed_insn (ip
);
7813 if (mips_opts
.mips16
7814 && mips_opts
.noreorder
7815 && delayed_branch_p (&history
[0]))
7816 as_warn (_("extended instruction in delay slot"));
7818 if (mips_relax
.sequence
)
7820 /* If we've reached the end of this frag, turn it into a variant
7821 frag and record the information for the instructions we've
7823 if (frag_room () < 4)
7824 relax_close_frag ();
7825 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7828 if (mips_relax
.sequence
!= 2)
7830 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7831 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7832 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7833 mips_macro_warning
.insns
[0]++;
7835 if (mips_relax
.sequence
!= 1)
7837 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7838 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7839 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7840 mips_macro_warning
.insns
[1]++;
7843 if (mips_opts
.mips16
)
7846 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7848 add_fixed_insn (ip
);
7851 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7853 bfd_reloc_code_real_type final_type
[3];
7854 reloc_howto_type
*howto0
;
7855 reloc_howto_type
*howto
;
7858 /* Perform any necessary conversion to microMIPS relocations
7859 and find out how many relocations there actually are. */
7860 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7861 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7863 /* In a compound relocation, it is the final (outermost)
7864 operator that determines the relocated field. */
7865 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7870 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7871 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7872 bfd_get_reloc_size (howto
),
7874 howto0
&& howto0
->pc_relative
,
7876 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7877 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7879 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7880 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7881 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7883 /* These relocations can have an addend that won't fit in
7884 4 octets for 64bit assembly. */
7886 && ! howto
->partial_inplace
7887 && (reloc_type
[0] == BFD_RELOC_16
7888 || reloc_type
[0] == BFD_RELOC_32
7889 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7890 || reloc_type
[0] == BFD_RELOC_GPREL16
7891 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7892 || reloc_type
[0] == BFD_RELOC_GPREL32
7893 || reloc_type
[0] == BFD_RELOC_64
7894 || reloc_type
[0] == BFD_RELOC_CTOR
7895 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7896 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7897 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7898 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7899 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7900 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7901 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7902 || hi16_reloc_p (reloc_type
[0])
7903 || lo16_reloc_p (reloc_type
[0])))
7904 ip
->fixp
[0]->fx_no_overflow
= 1;
7906 /* These relocations can have an addend that won't fit in 2 octets. */
7907 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7908 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7909 ip
->fixp
[0]->fx_no_overflow
= 1;
7911 if (mips_relax
.sequence
)
7913 if (mips_relax
.first_fixup
== 0)
7914 mips_relax
.first_fixup
= ip
->fixp
[0];
7916 else if (reloc_needs_lo_p (*reloc_type
))
7918 struct mips_hi_fixup
*hi_fixup
;
7920 /* Reuse the last entry if it already has a matching %lo. */
7921 hi_fixup
= mips_hi_fixup_list
;
7923 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7925 hi_fixup
= XNEW (struct mips_hi_fixup
);
7926 hi_fixup
->next
= mips_hi_fixup_list
;
7927 mips_hi_fixup_list
= hi_fixup
;
7929 hi_fixup
->fixp
= ip
->fixp
[0];
7930 hi_fixup
->seg
= now_seg
;
7933 /* Add fixups for the second and third relocations, if given.
7934 Note that the ABI allows the second relocation to be
7935 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7936 moment we only use RSS_UNDEF, but we could add support
7937 for the others if it ever becomes necessary. */
7938 for (i
= 1; i
< 3; i
++)
7939 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7941 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7942 ip
->fixp
[0]->fx_size
, NULL
, 0,
7943 FALSE
, final_type
[i
]);
7945 /* Use fx_tcbit to mark compound relocs. */
7946 ip
->fixp
[0]->fx_tcbit
= 1;
7947 ip
->fixp
[i
]->fx_tcbit
= 1;
7951 /* Update the register mask information. */
7952 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7953 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7958 insert_into_history (0, 1, ip
);
7961 case APPEND_ADD_WITH_NOP
:
7963 struct mips_cl_insn
*nop
;
7965 insert_into_history (0, 1, ip
);
7966 nop
= get_delay_slot_nop (ip
);
7967 add_fixed_insn (nop
);
7968 insert_into_history (0, 1, nop
);
7969 if (mips_relax
.sequence
)
7970 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7974 case APPEND_ADD_COMPACT
:
7975 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7976 if (mips_opts
.mips16
)
7978 ip
->insn_opcode
|= 0x0080;
7979 find_altered_mips16_opcode (ip
);
7981 /* Convert microMIPS instructions. */
7982 else if (mips_opts
.micromips
)
7985 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
7986 ip
->insn_opcode
|= 0x0020;
7988 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
7989 ip
->insn_opcode
= 0x40e00000;
7990 /* beqz16->beqzc, bnez16->bnezc */
7991 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
7993 unsigned long regno
;
7995 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
7996 regno
&= MICROMIPSOP_MASK_MD
;
7997 regno
= micromips_to_32_reg_d_map
[regno
];
7998 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
7999 | (regno
<< MICROMIPSOP_SH_RS
)
8000 | 0x40a00000) ^ 0x00400000;
8002 /* beqz->beqzc, bnez->bnezc */
8003 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
8004 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
8005 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8006 | 0x40a00000) ^ 0x00400000;
8007 /* beq $0->beqzc, bne $0->bnezc */
8008 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8009 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8010 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8011 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8012 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8013 | 0x40a00000) ^ 0x00400000;
8016 find_altered_micromips_opcode (ip
);
8021 insert_into_history (0, 1, ip
);
8026 struct mips_cl_insn delay
= history
[0];
8028 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8030 /* Add the delay slot instruction to the end of the
8031 current frag and shrink the fixed part of the
8032 original frag. If the branch occupies the tail of
8033 the latter, move it backwards to cover the gap. */
8034 delay
.frag
->fr_fix
-= branch_disp
;
8035 if (delay
.frag
== ip
->frag
)
8036 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8037 add_fixed_insn (&delay
);
8041 /* If this is not a relaxed branch and we are in the
8042 same frag, then just swap the instructions. */
8043 move_insn (ip
, delay
.frag
, delay
.where
);
8044 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8048 insert_into_history (0, 1, &delay
);
8053 /* If we have just completed an unconditional branch, clear the history. */
8054 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8055 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8059 mips_no_prev_insn ();
8061 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8062 history
[i
].cleared_p
= 1;
8065 /* We need to emit a label at the end of branch-likely macros. */
8066 if (emit_branch_likely_macro
)
8068 emit_branch_likely_macro
= FALSE
;
8069 micromips_add_label ();
8072 /* We just output an insn, so the next one doesn't have a label. */
8073 mips_clear_insn_labels ();
8076 /* Forget that there was any previous instruction or label.
8077 When BRANCH is true, the branch history is also flushed. */
8080 mips_no_prev_insn (void)
8082 prev_nop_frag
= NULL
;
8083 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8084 mips_clear_insn_labels ();
8087 /* This function must be called before we emit something other than
8088 instructions. It is like mips_no_prev_insn except that it inserts
8089 any NOPS that might be needed by previous instructions. */
8092 mips_emit_delays (void)
8094 if (! mips_opts
.noreorder
)
8096 int nops
= nops_for_insn (0, history
, NULL
);
8100 add_fixed_insn (NOP_INSN
);
8101 mips_move_text_labels ();
8104 mips_no_prev_insn ();
8107 /* Start a (possibly nested) noreorder block. */
8110 start_noreorder (void)
8112 if (mips_opts
.noreorder
== 0)
8117 /* None of the instructions before the .set noreorder can be moved. */
8118 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8119 history
[i
].fixed_p
= 1;
8121 /* Insert any nops that might be needed between the .set noreorder
8122 block and the previous instructions. We will later remove any
8123 nops that turn out not to be needed. */
8124 nops
= nops_for_insn (0, history
, NULL
);
8127 if (mips_optimize
!= 0)
8129 /* Record the frag which holds the nop instructions, so
8130 that we can remove them if we don't need them. */
8131 frag_grow (nops
* NOP_INSN_SIZE
);
8132 prev_nop_frag
= frag_now
;
8133 prev_nop_frag_holds
= nops
;
8134 prev_nop_frag_required
= 0;
8135 prev_nop_frag_since
= 0;
8138 for (; nops
> 0; --nops
)
8139 add_fixed_insn (NOP_INSN
);
8141 /* Move on to a new frag, so that it is safe to simply
8142 decrease the size of prev_nop_frag. */
8143 frag_wane (frag_now
);
8145 mips_move_text_labels ();
8147 mips_mark_labels ();
8148 mips_clear_insn_labels ();
8150 mips_opts
.noreorder
++;
8151 mips_any_noreorder
= 1;
8154 /* End a nested noreorder block. */
8157 end_noreorder (void)
8159 mips_opts
.noreorder
--;
8160 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8162 /* Commit to inserting prev_nop_frag_required nops and go back to
8163 handling nop insertion the .set reorder way. */
8164 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8166 insert_into_history (prev_nop_frag_since
,
8167 prev_nop_frag_required
, NOP_INSN
);
8168 prev_nop_frag
= NULL
;
8172 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8173 higher bits unset. */
8176 normalize_constant_expr (expressionS
*ex
)
8178 if (ex
->X_op
== O_constant
8179 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8180 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8184 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8185 all higher bits unset. */
8188 normalize_address_expr (expressionS
*ex
)
8190 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8191 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8192 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8193 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8197 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8198 Return true if the match was successful.
8200 OPCODE_EXTRA is a value that should be ORed into the opcode
8201 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8202 there are more alternatives after OPCODE and SOFT_MATCH is
8203 as for mips_arg_info. */
8206 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8207 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8208 bfd_boolean lax_match
, bfd_boolean complete_p
)
8211 struct mips_arg_info arg
;
8212 const struct mips_operand
*operand
;
8215 imm_expr
.X_op
= O_absent
;
8216 offset_expr
.X_op
= O_absent
;
8217 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8218 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8219 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8221 create_insn (insn
, opcode
);
8222 /* When no opcode suffix is specified, assume ".xyzw". */
8223 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8224 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8226 insn
->insn_opcode
|= opcode_extra
;
8227 memset (&arg
, 0, sizeof (arg
));
8231 arg
.last_regno
= ILLEGAL_REG
;
8232 arg
.dest_regno
= ILLEGAL_REG
;
8233 arg
.lax_match
= lax_match
;
8234 for (args
= opcode
->args
;; ++args
)
8236 if (arg
.token
->type
== OT_END
)
8238 /* Handle unary instructions in which only one operand is given.
8239 The source is then the same as the destination. */
8240 if (arg
.opnum
== 1 && *args
== ',')
8242 operand
= (mips_opts
.micromips
8243 ? decode_micromips_operand (args
+ 1)
8244 : decode_mips_operand (args
+ 1));
8245 if (operand
&& mips_optional_operand_p (operand
))
8253 /* Treat elided base registers as $0. */
8254 if (strcmp (args
, "(b)") == 0)
8262 /* The register suffix is optional. */
8267 /* Fail the match if there were too few operands. */
8271 /* Successful match. */
8274 clear_insn_error ();
8275 if (arg
.dest_regno
== arg
.last_regno
8276 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8280 (0, _("source and destination must be different"));
8281 else if (arg
.last_regno
== 31)
8283 (0, _("a destination register must be supplied"));
8285 else if (arg
.last_regno
== 31
8286 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8287 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8288 set_insn_error (0, _("the source register must not be $31"));
8289 check_completed_insn (&arg
);
8293 /* Fail the match if the line has too many operands. */
8297 /* Handle characters that need to match exactly. */
8298 if (*args
== '(' || *args
== ')' || *args
== ',')
8300 if (match_char (&arg
, *args
))
8307 if (arg
.token
->type
== OT_DOUBLE_CHAR
8308 && arg
.token
->u
.ch
== *args
)
8316 /* Handle special macro operands. Work out the properties of
8325 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8329 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8338 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8342 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8346 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8352 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8354 imm_expr
.X_op
= O_constant
;
8356 normalize_constant_expr (&imm_expr
);
8360 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8362 /* Assume that the offset has been elided and that what
8363 we saw was a base register. The match will fail later
8364 if that assumption turns out to be wrong. */
8365 offset_expr
.X_op
= O_constant
;
8366 offset_expr
.X_add_number
= 0;
8370 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8372 normalize_address_expr (&offset_expr
);
8377 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8383 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8389 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8395 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8401 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8405 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8409 gas_assert (mips_opts
.micromips
);
8415 if (!forced_insn_length
)
8416 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8418 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8420 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8426 operand
= (mips_opts
.micromips
8427 ? decode_micromips_operand (args
)
8428 : decode_mips_operand (args
));
8432 /* Skip prefixes. */
8433 if (*args
== '+' || *args
== 'm' || *args
== '-')
8436 if (mips_optional_operand_p (operand
)
8438 && (arg
.token
[0].type
!= OT_REG
8439 || arg
.token
[1].type
== OT_END
))
8441 /* Assume that the register has been elided and is the
8442 same as the first operand. */
8447 if (!match_operand (&arg
, operand
))
8452 /* Like match_insn, but for MIPS16. */
8455 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8456 struct mips_operand_token
*tokens
)
8459 const struct mips_operand
*operand
;
8460 const struct mips_operand
*ext_operand
;
8461 bfd_boolean pcrel
= FALSE
;
8462 int required_insn_length
;
8463 struct mips_arg_info arg
;
8466 if (forced_insn_length
)
8467 required_insn_length
= forced_insn_length
;
8468 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8469 required_insn_length
= 2;
8471 required_insn_length
= 0;
8473 create_insn (insn
, opcode
);
8474 imm_expr
.X_op
= O_absent
;
8475 offset_expr
.X_op
= O_absent
;
8476 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8477 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8478 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8481 memset (&arg
, 0, sizeof (arg
));
8485 arg
.last_regno
= ILLEGAL_REG
;
8486 arg
.dest_regno
= ILLEGAL_REG
;
8488 for (args
= opcode
->args
;; ++args
)
8492 if (arg
.token
->type
== OT_END
)
8496 /* Handle unary instructions in which only one operand is given.
8497 The source is then the same as the destination. */
8498 if (arg
.opnum
== 1 && *args
== ',')
8500 operand
= decode_mips16_operand (args
[1], FALSE
);
8501 if (operand
&& mips_optional_operand_p (operand
))
8509 /* Fail the match if there were too few operands. */
8513 /* Successful match. Stuff the immediate value in now, if
8515 clear_insn_error ();
8516 if (opcode
->pinfo
== INSN_MACRO
)
8518 gas_assert (relax_char
== 0 || relax_char
== 'p');
8519 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8522 && offset_expr
.X_op
== O_constant
8524 && calculate_reloc (*offset_reloc
,
8525 offset_expr
.X_add_number
,
8528 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8529 required_insn_length
, &insn
->insn_opcode
);
8530 offset_expr
.X_op
= O_absent
;
8531 *offset_reloc
= BFD_RELOC_UNUSED
;
8533 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8535 if (required_insn_length
== 2)
8536 set_insn_error (0, _("invalid unextended operand value"));
8537 else if (!mips_opcode_32bit_p (opcode
))
8539 forced_insn_length
= 4;
8540 insn
->insn_opcode
|= MIPS16_EXTEND
;
8543 else if (relax_char
)
8544 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8546 check_completed_insn (&arg
);
8550 /* Fail the match if the line has too many operands. */
8554 /* Handle characters that need to match exactly. */
8555 if (*args
== '(' || *args
== ')' || *args
== ',')
8557 if (match_char (&arg
, *args
))
8577 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8579 imm_expr
.X_op
= O_constant
;
8581 normalize_constant_expr (&imm_expr
);
8586 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8590 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8594 if (operand
->type
== OP_PCREL
)
8598 ext_operand
= decode_mips16_operand (c
, TRUE
);
8599 if (operand
!= ext_operand
)
8601 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8603 offset_expr
.X_op
= O_constant
;
8604 offset_expr
.X_add_number
= 0;
8609 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8612 /* '8' is used for SLTI(U) and has traditionally not
8613 been allowed to take relocation operators. */
8614 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8615 && (ext_operand
->size
!= 16 || c
== '8'))
8617 match_not_constant (&arg
);
8621 if (offset_expr
.X_op
== O_big
)
8623 match_out_of_range (&arg
);
8632 if (mips_optional_operand_p (operand
)
8634 && (arg
.token
[0].type
!= OT_REG
8635 || arg
.token
[1].type
== OT_END
))
8637 /* Assume that the register has been elided and is the
8638 same as the first operand. */
8643 if (!match_operand (&arg
, operand
))
8648 /* Record that the current instruction is invalid for the current ISA. */
8651 match_invalid_for_isa (void)
8654 (0, _("opcode not supported on this processor: %s (%s)"),
8655 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8656 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8659 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8660 Return true if a definite match or failure was found, storing any match
8661 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8662 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8663 tried and failed to match under normal conditions and now want to try a
8664 more relaxed match. */
8667 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8668 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8669 int opcode_extra
, bfd_boolean lax_match
)
8671 const struct mips_opcode
*opcode
;
8672 const struct mips_opcode
*invalid_delay_slot
;
8673 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8675 /* Search for a match, ignoring alternatives that don't satisfy the
8676 current ISA or forced_length. */
8677 invalid_delay_slot
= 0;
8678 seen_valid_for_isa
= FALSE
;
8679 seen_valid_for_size
= FALSE
;
8683 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8684 if (is_opcode_valid (opcode
))
8686 seen_valid_for_isa
= TRUE
;
8687 if (is_size_valid (opcode
))
8689 bfd_boolean delay_slot_ok
;
8691 seen_valid_for_size
= TRUE
;
8692 delay_slot_ok
= is_delay_slot_valid (opcode
);
8693 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8694 lax_match
, delay_slot_ok
))
8698 if (!invalid_delay_slot
)
8699 invalid_delay_slot
= opcode
;
8708 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8710 /* If the only matches we found had the wrong length for the delay slot,
8711 pick the first such match. We'll issue an appropriate warning later. */
8712 if (invalid_delay_slot
)
8714 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8720 /* Handle the case where we didn't try to match an instruction because
8721 all the alternatives were incompatible with the current ISA. */
8722 if (!seen_valid_for_isa
)
8724 match_invalid_for_isa ();
8728 /* Handle the case where we didn't try to match an instruction because
8729 all the alternatives were of the wrong size. */
8730 if (!seen_valid_for_size
)
8732 if (mips_opts
.insn32
)
8733 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8736 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8737 8 * forced_insn_length
);
8744 /* Like match_insns, but for MIPS16. */
8747 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8748 struct mips_operand_token
*tokens
)
8750 const struct mips_opcode
*opcode
;
8751 bfd_boolean seen_valid_for_isa
;
8752 bfd_boolean seen_valid_for_size
;
8754 /* Search for a match, ignoring alternatives that don't satisfy the
8755 current ISA. There are no separate entries for extended forms so
8756 we deal with forced_length later. */
8757 seen_valid_for_isa
= FALSE
;
8758 seen_valid_for_size
= FALSE
;
8762 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8763 if (is_opcode_valid_16 (opcode
))
8765 seen_valid_for_isa
= TRUE
;
8766 if (is_size_valid_16 (opcode
))
8768 seen_valid_for_size
= TRUE
;
8769 if (match_mips16_insn (insn
, opcode
, tokens
))
8775 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8776 && strcmp (opcode
->name
, first
->name
) == 0);
8778 /* Handle the case where we didn't try to match an instruction because
8779 all the alternatives were incompatible with the current ISA. */
8780 if (!seen_valid_for_isa
)
8782 match_invalid_for_isa ();
8786 /* Handle the case where we didn't try to match an instruction because
8787 all the alternatives were of the wrong size. */
8788 if (!seen_valid_for_size
)
8790 if (forced_insn_length
== 2)
8792 (0, _("unrecognized unextended version of MIPS16 opcode"));
8795 (0, _("unrecognized extended version of MIPS16 opcode"));
8802 /* Set up global variables for the start of a new macro. */
8807 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8808 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8809 sizeof (mips_macro_warning
.first_insn_sizes
));
8810 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8811 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8812 && delayed_branch_p (&history
[0]));
8814 && history
[0].frag
->fr_type
== rs_machine_dependent
8815 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8816 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8817 mips_macro_warning
.delay_slot_length
= 0;
8819 switch (history
[0].insn_mo
->pinfo2
8820 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8822 case INSN2_BRANCH_DELAY_32BIT
:
8823 mips_macro_warning
.delay_slot_length
= 4;
8825 case INSN2_BRANCH_DELAY_16BIT
:
8826 mips_macro_warning
.delay_slot_length
= 2;
8829 mips_macro_warning
.delay_slot_length
= 0;
8832 mips_macro_warning
.first_frag
= NULL
;
8835 /* Given that a macro is longer than one instruction or of the wrong size,
8836 return the appropriate warning for it. Return null if no warning is
8837 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8838 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8839 and RELAX_NOMACRO. */
8842 macro_warning (relax_substateT subtype
)
8844 if (subtype
& RELAX_DELAY_SLOT
)
8845 return _("macro instruction expanded into multiple instructions"
8846 " in a branch delay slot");
8847 else if (subtype
& RELAX_NOMACRO
)
8848 return _("macro instruction expanded into multiple instructions");
8849 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8850 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8851 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8852 ? _("macro instruction expanded into a wrong size instruction"
8853 " in a 16-bit branch delay slot")
8854 : _("macro instruction expanded into a wrong size instruction"
8855 " in a 32-bit branch delay slot"));
8860 /* Finish up a macro. Emit warnings as appropriate. */
8865 /* Relaxation warning flags. */
8866 relax_substateT subtype
= 0;
8868 /* Check delay slot size requirements. */
8869 if (mips_macro_warning
.delay_slot_length
== 2)
8870 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8871 if (mips_macro_warning
.delay_slot_length
!= 0)
8873 if (mips_macro_warning
.delay_slot_length
8874 != mips_macro_warning
.first_insn_sizes
[0])
8875 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8876 if (mips_macro_warning
.delay_slot_length
8877 != mips_macro_warning
.first_insn_sizes
[1])
8878 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8881 /* Check instruction count requirements. */
8882 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8884 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8885 subtype
|= RELAX_SECOND_LONGER
;
8886 if (mips_opts
.warn_about_macros
)
8887 subtype
|= RELAX_NOMACRO
;
8888 if (mips_macro_warning
.delay_slot_p
)
8889 subtype
|= RELAX_DELAY_SLOT
;
8892 /* If both alternatives fail to fill a delay slot correctly,
8893 emit the warning now. */
8894 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8895 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8900 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8901 | RELAX_DELAY_SLOT_SIZE_FIRST
8902 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8903 msg
= macro_warning (s
);
8905 as_warn ("%s", msg
);
8909 /* If both implementations are longer than 1 instruction, then emit the
8911 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8916 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8917 msg
= macro_warning (s
);
8919 as_warn ("%s", msg
);
8923 /* If any flags still set, then one implementation might need a warning
8924 and the other either will need one of a different kind or none at all.
8925 Pass any remaining flags over to relaxation. */
8926 if (mips_macro_warning
.first_frag
!= NULL
)
8927 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8930 /* Instruction operand formats used in macros that vary between
8931 standard MIPS and microMIPS code. */
8933 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8934 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8935 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8936 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8937 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8938 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8939 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8940 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8942 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8943 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8944 : cop12_fmt[mips_opts.micromips])
8945 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8946 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8947 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8948 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8949 : mem12_fmt[mips_opts.micromips])
8950 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8951 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8952 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8954 /* Read a macro's relocation codes from *ARGS and store them in *R.
8955 The first argument in *ARGS will be either the code for a single
8956 relocation or -1 followed by the three codes that make up a
8957 composite relocation. */
8960 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8964 next
= va_arg (*args
, int);
8966 r
[0] = (bfd_reloc_code_real_type
) next
;
8969 for (i
= 0; i
< 3; i
++)
8970 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8971 /* This function is only used for 16-bit relocation fields.
8972 To make the macro code simpler, treat an unrelocated value
8973 in the same way as BFD_RELOC_LO16. */
8974 if (r
[0] == BFD_RELOC_UNUSED
)
8975 r
[0] = BFD_RELOC_LO16
;
8979 /* Build an instruction created by a macro expansion. This is passed
8980 a pointer to the count of instructions created so far, an
8981 expression, the name of the instruction to build, an operand format
8982 string, and corresponding arguments. */
8985 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
8987 const struct mips_opcode
*mo
= NULL
;
8988 bfd_reloc_code_real_type r
[3];
8989 const struct mips_opcode
*amo
;
8990 const struct mips_operand
*operand
;
8991 struct hash_control
*hash
;
8992 struct mips_cl_insn insn
;
8996 va_start (args
, fmt
);
8998 if (mips_opts
.mips16
)
9000 mips16_macro_build (ep
, name
, fmt
, &args
);
9005 r
[0] = BFD_RELOC_UNUSED
;
9006 r
[1] = BFD_RELOC_UNUSED
;
9007 r
[2] = BFD_RELOC_UNUSED
;
9008 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9009 amo
= (struct mips_opcode
*) hash_find (hash
, name
);
9011 gas_assert (strcmp (name
, amo
->name
) == 0);
9015 /* Search until we get a match for NAME. It is assumed here that
9016 macros will never generate MDMX, MIPS-3D, or MT instructions.
9017 We try to match an instruction that fulfills the branch delay
9018 slot instruction length requirement (if any) of the previous
9019 instruction. While doing this we record the first instruction
9020 seen that matches all the other conditions and use it anyway
9021 if the requirement cannot be met; we will issue an appropriate
9022 warning later on. */
9023 if (strcmp (fmt
, amo
->args
) == 0
9024 && amo
->pinfo
!= INSN_MACRO
9025 && is_opcode_valid (amo
)
9026 && is_size_valid (amo
))
9028 if (is_delay_slot_valid (amo
))
9038 gas_assert (amo
->name
);
9040 while (strcmp (name
, amo
->name
) == 0);
9043 create_insn (&insn
, mo
);
9056 macro_read_relocs (&args
, r
);
9057 gas_assert (*r
== BFD_RELOC_GPREL16
9058 || *r
== BFD_RELOC_MIPS_HIGHER
9059 || *r
== BFD_RELOC_HI16_S
9060 || *r
== BFD_RELOC_LO16
9061 || *r
== BFD_RELOC_MIPS_GOT_OFST
9062 || (mips_opts
.micromips
9063 && (*r
== BFD_RELOC_16
9064 || *r
== BFD_RELOC_MIPS_GOT16
9065 || *r
== BFD_RELOC_MIPS_CALL16
9066 || *r
== BFD_RELOC_MIPS_GOT_HI16
9067 || *r
== BFD_RELOC_MIPS_GOT_LO16
9068 || *r
== BFD_RELOC_MIPS_CALL_HI16
9069 || *r
== BFD_RELOC_MIPS_CALL_LO16
9070 || *r
== BFD_RELOC_MIPS_SUB
9071 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9072 || *r
== BFD_RELOC_MIPS_HIGHEST
9073 || *r
== BFD_RELOC_MIPS_GOT_DISP
9074 || *r
== BFD_RELOC_MIPS_TLS_GD
9075 || *r
== BFD_RELOC_MIPS_TLS_LDM
9076 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9077 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9078 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9079 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9080 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9084 macro_read_relocs (&args
, r
);
9088 macro_read_relocs (&args
, r
);
9089 gas_assert (ep
!= NULL
9090 && (ep
->X_op
== O_constant
9091 || (ep
->X_op
== O_symbol
9092 && (*r
== BFD_RELOC_MIPS_HIGHEST
9093 || *r
== BFD_RELOC_HI16_S
9094 || *r
== BFD_RELOC_HI16
9095 || *r
== BFD_RELOC_GPREL16
9096 || *r
== BFD_RELOC_MIPS_GOT_HI16
9097 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9101 gas_assert (ep
!= NULL
);
9104 * This allows macro() to pass an immediate expression for
9105 * creating short branches without creating a symbol.
9107 * We don't allow branch relaxation for these branches, as
9108 * they should only appear in ".set nomacro" anyway.
9110 if (ep
->X_op
== O_constant
)
9112 /* For microMIPS we always use relocations for branches.
9113 So we should not resolve immediate values. */
9114 gas_assert (!mips_opts
.micromips
);
9116 if ((ep
->X_add_number
& 3) != 0)
9117 as_bad (_("branch to misaligned address (0x%lx)"),
9118 (unsigned long) ep
->X_add_number
);
9119 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9120 as_bad (_("branch address range overflow (0x%lx)"),
9121 (unsigned long) ep
->X_add_number
);
9122 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9126 *r
= BFD_RELOC_16_PCREL_S2
;
9130 gas_assert (ep
!= NULL
);
9131 *r
= BFD_RELOC_MIPS_JMP
;
9135 operand
= (mips_opts
.micromips
9136 ? decode_micromips_operand (fmt
)
9137 : decode_mips_operand (fmt
));
9141 uval
= va_arg (args
, int);
9142 if (operand
->type
== OP_CLO_CLZ_DEST
)
9143 uval
|= (uval
<< 5);
9144 insn_insert_operand (&insn
, operand
, uval
);
9146 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9152 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9154 append_insn (&insn
, ep
, r
, TRUE
);
9158 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9161 struct mips_opcode
*mo
;
9162 struct mips_cl_insn insn
;
9163 const struct mips_operand
*operand
;
9164 bfd_reloc_code_real_type r
[3]
9165 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9167 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
9169 gas_assert (strcmp (name
, mo
->name
) == 0);
9171 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9174 gas_assert (mo
->name
);
9175 gas_assert (strcmp (name
, mo
->name
) == 0);
9178 create_insn (&insn
, mo
);
9215 gas_assert (ep
!= NULL
);
9217 if (ep
->X_op
!= O_constant
)
9218 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9219 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9221 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9223 *r
= BFD_RELOC_UNUSED
;
9229 operand
= decode_mips16_operand (c
, FALSE
);
9233 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9238 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9240 append_insn (&insn
, ep
, r
, TRUE
);
9244 * Generate a "jalr" instruction with a relocation hint to the called
9245 * function. This occurs in NewABI PIC code.
9248 macro_build_jalr (expressionS
*ep
, int cprestore
)
9250 static const bfd_reloc_code_real_type jalr_relocs
[2]
9251 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9252 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9256 if (MIPS_JALR_HINT_P (ep
))
9261 if (mips_opts
.micromips
)
9263 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9264 ? "jalr" : "jalrs");
9265 if (MIPS_JALR_HINT_P (ep
)
9267 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9268 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9270 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9273 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9274 if (MIPS_JALR_HINT_P (ep
))
9275 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9279 * Generate a "lui" instruction.
9282 macro_build_lui (expressionS
*ep
, int regnum
)
9284 gas_assert (! mips_opts
.mips16
);
9286 if (ep
->X_op
!= O_constant
)
9288 gas_assert (ep
->X_op
== O_symbol
);
9289 /* _gp_disp is a special case, used from s_cpload.
9290 __gnu_local_gp is used if mips_no_shared. */
9291 gas_assert (mips_pic
== NO_PIC
9293 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9294 || (! mips_in_shared
9295 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9296 "__gnu_local_gp") == 0));
9299 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9302 /* Generate a sequence of instructions to do a load or store from a constant
9303 offset off of a base register (breg) into/from a target register (treg),
9304 using AT if necessary. */
9306 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9307 int treg
, int breg
, int dbl
)
9309 gas_assert (ep
->X_op
== O_constant
);
9311 /* Sign-extending 32-bit constants makes their handling easier. */
9313 normalize_constant_expr (ep
);
9315 /* Right now, this routine can only handle signed 32-bit constants. */
9316 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9317 as_warn (_("operand overflow"));
9319 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9321 /* Signed 16-bit offset will fit in the op. Easy! */
9322 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9326 /* 32-bit offset, need multiple instructions and AT, like:
9327 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9328 addu $tempreg,$tempreg,$breg
9329 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9330 to handle the complete offset. */
9331 macro_build_lui (ep
, AT
);
9332 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9333 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9336 as_bad (_("macro used $at after \".set noat\""));
9341 * Generates code to set the $at register to true (one)
9342 * if reg is less than the immediate expression.
9345 set_at (int reg
, int unsignedp
)
9347 if (imm_expr
.X_add_number
>= -0x8000
9348 && imm_expr
.X_add_number
< 0x8000)
9349 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9350 AT
, reg
, BFD_RELOC_LO16
);
9353 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9354 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9358 /* Count the leading zeroes by performing a binary chop. This is a
9359 bulky bit of source, but performance is a LOT better for the
9360 majority of values than a simple loop to count the bits:
9361 for (lcnt = 0; (lcnt < 32); lcnt++)
9362 if ((v) & (1 << (31 - lcnt)))
9364 However it is not code size friendly, and the gain will drop a bit
9365 on certain cached systems.
9367 #define COUNT_TOP_ZEROES(v) \
9368 (((v) & ~0xffff) == 0 \
9369 ? ((v) & ~0xff) == 0 \
9370 ? ((v) & ~0xf) == 0 \
9371 ? ((v) & ~0x3) == 0 \
9372 ? ((v) & ~0x1) == 0 \
9377 : ((v) & ~0x7) == 0 \
9380 : ((v) & ~0x3f) == 0 \
9381 ? ((v) & ~0x1f) == 0 \
9384 : ((v) & ~0x7f) == 0 \
9387 : ((v) & ~0xfff) == 0 \
9388 ? ((v) & ~0x3ff) == 0 \
9389 ? ((v) & ~0x1ff) == 0 \
9392 : ((v) & ~0x7ff) == 0 \
9395 : ((v) & ~0x3fff) == 0 \
9396 ? ((v) & ~0x1fff) == 0 \
9399 : ((v) & ~0x7fff) == 0 \
9402 : ((v) & ~0xffffff) == 0 \
9403 ? ((v) & ~0xfffff) == 0 \
9404 ? ((v) & ~0x3ffff) == 0 \
9405 ? ((v) & ~0x1ffff) == 0 \
9408 : ((v) & ~0x7ffff) == 0 \
9411 : ((v) & ~0x3fffff) == 0 \
9412 ? ((v) & ~0x1fffff) == 0 \
9415 : ((v) & ~0x7fffff) == 0 \
9418 : ((v) & ~0xfffffff) == 0 \
9419 ? ((v) & ~0x3ffffff) == 0 \
9420 ? ((v) & ~0x1ffffff) == 0 \
9423 : ((v) & ~0x7ffffff) == 0 \
9426 : ((v) & ~0x3fffffff) == 0 \
9427 ? ((v) & ~0x1fffffff) == 0 \
9430 : ((v) & ~0x7fffffff) == 0 \
9435 * This routine generates the least number of instructions necessary to load
9436 * an absolute expression value into a register.
9439 load_register (int reg
, expressionS
*ep
, int dbl
)
9442 expressionS hi32
, lo32
;
9444 if (ep
->X_op
!= O_big
)
9446 gas_assert (ep
->X_op
== O_constant
);
9448 /* Sign-extending 32-bit constants makes their handling easier. */
9450 normalize_constant_expr (ep
);
9452 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9454 /* We can handle 16 bit signed values with an addiu to
9455 $zero. No need to ever use daddiu here, since $zero and
9456 the result are always correct in 32 bit mode. */
9457 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9460 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9462 /* We can handle 16 bit unsigned values with an ori to
9464 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9467 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9469 /* 32 bit values require an lui. */
9470 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9471 if ((ep
->X_add_number
& 0xffff) != 0)
9472 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9477 /* The value is larger than 32 bits. */
9479 if (!dbl
|| GPR_SIZE
== 32)
9483 sprintf_vma (value
, ep
->X_add_number
);
9484 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9485 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9489 if (ep
->X_op
!= O_big
)
9492 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9493 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9494 hi32
.X_add_number
&= 0xffffffff;
9496 lo32
.X_add_number
&= 0xffffffff;
9500 gas_assert (ep
->X_add_number
> 2);
9501 if (ep
->X_add_number
== 3)
9502 generic_bignum
[3] = 0;
9503 else if (ep
->X_add_number
> 4)
9504 as_bad (_("number larger than 64 bits"));
9505 lo32
.X_op
= O_constant
;
9506 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9507 hi32
.X_op
= O_constant
;
9508 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9511 if (hi32
.X_add_number
== 0)
9516 unsigned long hi
, lo
;
9518 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9520 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9522 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9525 if (lo32
.X_add_number
& 0x80000000)
9527 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9528 if (lo32
.X_add_number
& 0xffff)
9529 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9534 /* Check for 16bit shifted constant. We know that hi32 is
9535 non-zero, so start the mask on the first bit of the hi32
9540 unsigned long himask
, lomask
;
9544 himask
= 0xffff >> (32 - shift
);
9545 lomask
= (0xffff << shift
) & 0xffffffff;
9549 himask
= 0xffff << (shift
- 32);
9552 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9553 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9557 tmp
.X_op
= O_constant
;
9559 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9560 | (lo32
.X_add_number
>> shift
));
9562 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9563 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9564 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9565 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9570 while (shift
<= (64 - 16));
9572 /* Find the bit number of the lowest one bit, and store the
9573 shifted value in hi/lo. */
9574 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9575 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9579 while ((lo
& 1) == 0)
9584 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
9590 while ((hi
& 1) == 0)
9599 /* Optimize if the shifted value is a (power of 2) - 1. */
9600 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9601 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9603 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9608 /* This instruction will set the register to be all
9610 tmp
.X_op
= O_constant
;
9611 tmp
.X_add_number
= (offsetT
) -1;
9612 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9616 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9617 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9619 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9620 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9625 /* Sign extend hi32 before calling load_register, because we can
9626 generally get better code when we load a sign extended value. */
9627 if ((hi32
.X_add_number
& 0x80000000) != 0)
9628 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9629 load_register (reg
, &hi32
, 0);
9632 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9636 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9644 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9646 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9647 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9653 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9657 mid16
.X_add_number
>>= 16;
9658 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9659 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9662 if ((lo32
.X_add_number
& 0xffff) != 0)
9663 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9667 load_delay_nop (void)
9669 if (!gpr_interlocks
)
9670 macro_build (NULL
, "nop", "");
9673 /* Load an address into a register. */
9676 load_address (int reg
, expressionS
*ep
, int *used_at
)
9678 if (ep
->X_op
!= O_constant
9679 && ep
->X_op
!= O_symbol
)
9681 as_bad (_("expression too complex"));
9682 ep
->X_op
= O_constant
;
9685 if (ep
->X_op
== O_constant
)
9687 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9691 if (mips_pic
== NO_PIC
)
9693 /* If this is a reference to a GP relative symbol, we want
9694 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9696 lui $reg,<sym> (BFD_RELOC_HI16_S)
9697 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9698 If we have an addend, we always use the latter form.
9700 With 64bit address space and a usable $at we want
9701 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9702 lui $at,<sym> (BFD_RELOC_HI16_S)
9703 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9704 daddiu $at,<sym> (BFD_RELOC_LO16)
9708 If $at is already in use, we use a path which is suboptimal
9709 on superscalar processors.
9710 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9711 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9713 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9715 daddiu $reg,<sym> (BFD_RELOC_LO16)
9717 For GP relative symbols in 64bit address space we can use
9718 the same sequence as in 32bit address space. */
9719 if (HAVE_64BIT_SYMBOLS
)
9721 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9722 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9724 relax_start (ep
->X_add_symbol
);
9725 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9726 mips_gp_register
, BFD_RELOC_GPREL16
);
9730 if (*used_at
== 0 && mips_opts
.at
)
9732 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9733 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9734 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9735 BFD_RELOC_MIPS_HIGHER
);
9736 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9737 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9738 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9743 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9744 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9745 BFD_RELOC_MIPS_HIGHER
);
9746 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9747 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9748 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9749 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9752 if (mips_relax
.sequence
)
9757 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9758 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9760 relax_start (ep
->X_add_symbol
);
9761 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9762 mips_gp_register
, BFD_RELOC_GPREL16
);
9765 macro_build_lui (ep
, reg
);
9766 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9767 reg
, reg
, BFD_RELOC_LO16
);
9768 if (mips_relax
.sequence
)
9772 else if (!mips_big_got
)
9776 /* If this is a reference to an external symbol, we want
9777 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9779 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9781 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9782 If there is a constant, it must be added in after.
9784 If we have NewABI, we want
9785 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9786 unless we're referencing a global symbol with a non-zero
9787 offset, in which case cst must be added separately. */
9790 if (ep
->X_add_number
)
9792 ex
.X_add_number
= ep
->X_add_number
;
9793 ep
->X_add_number
= 0;
9794 relax_start (ep
->X_add_symbol
);
9795 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9796 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9797 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9798 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9799 ex
.X_op
= O_constant
;
9800 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9801 reg
, reg
, BFD_RELOC_LO16
);
9802 ep
->X_add_number
= ex
.X_add_number
;
9805 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9806 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9807 if (mips_relax
.sequence
)
9812 ex
.X_add_number
= ep
->X_add_number
;
9813 ep
->X_add_number
= 0;
9814 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9815 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9817 relax_start (ep
->X_add_symbol
);
9819 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9823 if (ex
.X_add_number
!= 0)
9825 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9826 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9827 ex
.X_op
= O_constant
;
9828 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9829 reg
, reg
, BFD_RELOC_LO16
);
9833 else if (mips_big_got
)
9837 /* This is the large GOT case. If this is a reference to an
9838 external symbol, we want
9839 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9841 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9843 Otherwise, for a reference to a local symbol in old ABI, we want
9844 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9846 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9847 If there is a constant, it must be added in after.
9849 In the NewABI, for local symbols, with or without offsets, we want:
9850 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9851 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9855 ex
.X_add_number
= ep
->X_add_number
;
9856 ep
->X_add_number
= 0;
9857 relax_start (ep
->X_add_symbol
);
9858 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9859 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9860 reg
, reg
, mips_gp_register
);
9861 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9862 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9863 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9864 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9865 else if (ex
.X_add_number
)
9867 ex
.X_op
= O_constant
;
9868 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9872 ep
->X_add_number
= ex
.X_add_number
;
9874 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9875 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9876 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9877 BFD_RELOC_MIPS_GOT_OFST
);
9882 ex
.X_add_number
= ep
->X_add_number
;
9883 ep
->X_add_number
= 0;
9884 relax_start (ep
->X_add_symbol
);
9885 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9886 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9887 reg
, reg
, mips_gp_register
);
9888 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9889 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9891 if (reg_needs_delay (mips_gp_register
))
9893 /* We need a nop before loading from $gp. This special
9894 check is required because the lui which starts the main
9895 instruction stream does not refer to $gp, and so will not
9896 insert the nop which may be required. */
9897 macro_build (NULL
, "nop", "");
9899 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9900 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9902 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9906 if (ex
.X_add_number
!= 0)
9908 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9909 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9910 ex
.X_op
= O_constant
;
9911 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9919 if (!mips_opts
.at
&& *used_at
== 1)
9920 as_bad (_("macro used $at after \".set noat\""));
9923 /* Move the contents of register SOURCE into register DEST. */
9926 move_register (int dest
, int source
)
9928 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9929 instruction specifically requires a 32-bit one. */
9930 if (mips_opts
.micromips
9931 && !mips_opts
.insn32
9932 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9933 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9935 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9938 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9939 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9940 The two alternatives are:
9942 Global symbol Local symbol
9943 ------------- ------------
9944 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9946 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9948 load_got_offset emits the first instruction and add_got_offset
9949 emits the second for a 16-bit offset or add_got_offset_hilo emits
9950 a sequence to add a 32-bit offset using a scratch register. */
9953 load_got_offset (int dest
, expressionS
*local
)
9958 global
.X_add_number
= 0;
9960 relax_start (local
->X_add_symbol
);
9961 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9962 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9964 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9965 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9970 add_got_offset (int dest
, expressionS
*local
)
9974 global
.X_op
= O_constant
;
9975 global
.X_op_symbol
= NULL
;
9976 global
.X_add_symbol
= NULL
;
9977 global
.X_add_number
= local
->X_add_number
;
9979 relax_start (local
->X_add_symbol
);
9980 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
9981 dest
, dest
, BFD_RELOC_LO16
);
9983 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
9988 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
9991 int hold_mips_optimize
;
9993 global
.X_op
= O_constant
;
9994 global
.X_op_symbol
= NULL
;
9995 global
.X_add_symbol
= NULL
;
9996 global
.X_add_number
= local
->X_add_number
;
9998 relax_start (local
->X_add_symbol
);
9999 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
10001 /* Set mips_optimize around the lui instruction to avoid
10002 inserting an unnecessary nop after the lw. */
10003 hold_mips_optimize
= mips_optimize
;
10005 macro_build_lui (&global
, tmp
);
10006 mips_optimize
= hold_mips_optimize
;
10007 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10010 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10013 /* Emit a sequence of instructions to emulate a branch likely operation.
10014 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10015 is its complementing branch with the original condition negated.
10016 CALL is set if the original branch specified the link operation.
10017 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10019 Code like this is produced in the noreorder mode:
10024 delay slot (executed only if branch taken)
10027 or, if CALL is set:
10032 delay slot (executed only if branch taken)
10035 In the reorder mode the delay slot would be filled with a nop anyway,
10036 so code produced is simply:
10041 This function is used when producing code for the microMIPS ASE that
10042 does not implement branch likely instructions in hardware. */
10045 macro_build_branch_likely (const char *br
, const char *brneg
,
10046 int call
, expressionS
*ep
, const char *fmt
,
10047 unsigned int sreg
, unsigned int treg
)
10049 int noreorder
= mips_opts
.noreorder
;
10052 gas_assert (mips_opts
.micromips
);
10053 start_noreorder ();
10056 micromips_label_expr (&expr1
);
10057 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10058 macro_build (NULL
, "nop", "");
10059 macro_build (ep
, call
? "bal" : "b", "p");
10061 /* Set to true so that append_insn adds a label. */
10062 emit_branch_likely_macro
= TRUE
;
10066 macro_build (ep
, br
, fmt
, sreg
, treg
);
10067 macro_build (NULL
, "nop", "");
10072 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10073 the condition code tested. EP specifies the branch target. */
10076 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10078 const int call
= 0;
10103 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10106 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10107 the register tested. EP specifies the branch target. */
10110 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10112 const char *brneg
= NULL
;
10122 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10126 gas_assert (mips_opts
.micromips
);
10127 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10135 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10142 br
= mips_opts
.micromips
? "blez" : "blezl";
10149 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10153 gas_assert (mips_opts
.micromips
);
10154 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10161 if (mips_opts
.micromips
&& brneg
)
10162 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10164 macro_build (ep
, br
, "s,p", sreg
);
10167 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10168 TREG as the registers tested. EP specifies the branch target. */
10171 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10172 unsigned int sreg
, unsigned int treg
)
10174 const char *brneg
= NULL
;
10175 const int call
= 0;
10186 br
= mips_opts
.micromips
? "beq" : "beql";
10195 br
= mips_opts
.micromips
? "bne" : "bnel";
10201 if (mips_opts
.micromips
&& brneg
)
10202 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10204 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10207 /* Return the high part that should be loaded in order to make the low
10208 part of VALUE accessible using an offset of OFFBITS bits. */
10211 offset_high_part (offsetT value
, unsigned int offbits
)
10218 bias
= 1 << (offbits
- 1);
10219 low_mask
= bias
* 2 - 1;
10220 return (value
+ bias
) & ~low_mask
;
10223 /* Return true if the value stored in offset_expr and offset_reloc
10224 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10225 amount that the caller wants to add without inducing overflow
10226 and ALIGN is the known alignment of the value in bytes. */
10229 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10233 /* Accept any relocation operator if overflow isn't a concern. */
10234 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10237 /* These relocations are guaranteed not to overflow in correct links. */
10238 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10239 || gprel16_reloc_p (*offset_reloc
))
10242 if (offset_expr
.X_op
== O_constant
10243 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10244 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10251 * This routine implements the seemingly endless macro or synthesized
10252 * instructions and addressing modes in the mips assembly language. Many
10253 * of these macros are simple and are similar to each other. These could
10254 * probably be handled by some kind of table or grammar approach instead of
10255 * this verbose method. Others are not simple macros but are more like
10256 * optimizing code generation.
10257 * One interesting optimization is when several store macros appear
10258 * consecutively that would load AT with the upper half of the same address.
10259 * The ensuing load upper instructions are omitted. This implies some kind
10260 * of global optimization. We currently only optimize within a single macro.
10261 * For many of the load and store macros if the address is specified as a
10262 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10263 * first load register 'at' with zero and use it as the base register. The
10264 * mips assembler simply uses register $zero. Just one tiny optimization
10268 macro (struct mips_cl_insn
*ip
, char *str
)
10270 const struct mips_operand_array
*operands
;
10271 unsigned int breg
, i
;
10272 unsigned int tempreg
;
10275 expressionS label_expr
;
10290 int ll_sc_paired
= 0;
10291 bfd_boolean large_offset
;
10293 int hold_mips_optimize
;
10294 unsigned int align
;
10295 unsigned int op
[MAX_OPERANDS
];
10297 gas_assert (! mips_opts
.mips16
);
10299 operands
= insn_operands (ip
);
10300 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10301 if (operands
->operand
[i
])
10302 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10306 mask
= ip
->insn_mo
->mask
;
10308 label_expr
.X_op
= O_constant
;
10309 label_expr
.X_op_symbol
= NULL
;
10310 label_expr
.X_add_symbol
= NULL
;
10311 label_expr
.X_add_number
= 0;
10313 expr1
.X_op
= O_constant
;
10314 expr1
.X_op_symbol
= NULL
;
10315 expr1
.X_add_symbol
= NULL
;
10316 expr1
.X_add_number
= 1;
10323 /* Fall through. */
10331 start_noreorder ();
10333 if (mips_opts
.micromips
)
10334 micromips_label_expr (&label_expr
);
10336 label_expr
.X_add_number
= 8;
10337 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10338 if (op
[0] == op
[1])
10339 macro_build (NULL
, "nop", "");
10341 move_register (op
[0], op
[1]);
10342 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10343 if (mips_opts
.micromips
)
10344 micromips_add_label ();
10352 if (ISA_IS_R6 (mips_opts
.isa
))
10364 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
10366 if (imm_expr
.X_add_number
>= -0x200
10367 && imm_expr
.X_add_number
< 0x200
10368 && !ISA_IS_R6 (mips_opts
.isa
))
10370 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10371 (int) imm_expr
.X_add_number
);
10380 if (imm_expr
.X_add_number
>= -0x8000
10381 && imm_expr
.X_add_number
< 0x8000)
10383 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10388 load_register (AT
, &imm_expr
, dbl
);
10389 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10408 if (imm_expr
.X_add_number
>= 0
10409 && imm_expr
.X_add_number
< 0x10000)
10411 if (mask
!= M_NOR_I
)
10412 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10415 macro_build (&imm_expr
, "ori", "t,r,i",
10416 op
[0], op
[1], BFD_RELOC_LO16
);
10417 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10423 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10424 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10428 switch (imm_expr
.X_add_number
)
10431 macro_build (NULL
, "nop", "");
10434 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10438 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10439 (int) imm_expr
.X_add_number
);
10442 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10443 (unsigned long) imm_expr
.X_add_number
);
10452 gas_assert (mips_opts
.micromips
);
10453 macro_build_branch_ccl (mask
, &offset_expr
,
10454 EXTRACT_OPERAND (1, BCC
, *ip
));
10461 if (imm_expr
.X_add_number
== 0)
10467 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10469 /* Fall through. */
10472 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10477 /* Fall through. */
10480 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10481 else if (op
[0] == 0)
10482 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10486 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10487 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10488 &offset_expr
, AT
, ZERO
);
10498 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10503 /* Fall through. */
10505 /* Check for > max integer. */
10506 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10509 /* Result is always false. */
10511 macro_build (NULL
, "nop", "");
10513 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10516 ++imm_expr
.X_add_number
;
10517 /* Fall through. */
10520 if (mask
== M_BGEL_I
)
10522 if (imm_expr
.X_add_number
== 0)
10524 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10525 &offset_expr
, op
[0]);
10528 if (imm_expr
.X_add_number
== 1)
10530 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10531 &offset_expr
, op
[0]);
10534 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10537 /* Result is always true. */
10538 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10539 macro_build (&offset_expr
, "b", "p");
10544 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10545 &offset_expr
, AT
, ZERO
);
10550 /* Fall through. */
10554 else if (op
[0] == 0)
10555 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10556 &offset_expr
, ZERO
, op
[1]);
10560 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10561 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10562 &offset_expr
, AT
, ZERO
);
10568 /* Fall through. */
10572 && imm_expr
.X_add_number
== -1))
10574 ++imm_expr
.X_add_number
;
10575 /* Fall through. */
10578 if (mask
== M_BGEUL_I
)
10580 if (imm_expr
.X_add_number
== 0)
10582 else if (imm_expr
.X_add_number
== 1)
10583 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10584 &offset_expr
, op
[0], ZERO
);
10589 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10590 &offset_expr
, AT
, ZERO
);
10596 /* Fall through. */
10599 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10600 else if (op
[0] == 0)
10601 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10605 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10606 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10607 &offset_expr
, AT
, ZERO
);
10613 /* Fall through. */
10616 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10617 &offset_expr
, op
[0], ZERO
);
10618 else if (op
[0] == 0)
10623 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10624 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10625 &offset_expr
, AT
, ZERO
);
10631 /* Fall through. */
10634 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10635 else if (op
[0] == 0)
10636 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10640 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10641 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10642 &offset_expr
, AT
, ZERO
);
10648 /* Fall through. */
10650 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10652 ++imm_expr
.X_add_number
;
10653 /* Fall through. */
10656 if (mask
== M_BLTL_I
)
10658 if (imm_expr
.X_add_number
== 0)
10659 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10660 else if (imm_expr
.X_add_number
== 1)
10661 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10666 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10667 &offset_expr
, AT
, ZERO
);
10673 /* Fall through. */
10676 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10677 &offset_expr
, op
[0], ZERO
);
10678 else if (op
[0] == 0)
10683 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10684 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10685 &offset_expr
, AT
, ZERO
);
10691 /* Fall through. */
10695 && imm_expr
.X_add_number
== -1))
10697 ++imm_expr
.X_add_number
;
10698 /* Fall through. */
10701 if (mask
== M_BLTUL_I
)
10703 if (imm_expr
.X_add_number
== 0)
10705 else if (imm_expr
.X_add_number
== 1)
10706 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10707 &offset_expr
, op
[0], ZERO
);
10712 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10713 &offset_expr
, AT
, ZERO
);
10719 /* Fall through. */
10722 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10723 else if (op
[0] == 0)
10724 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10728 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10729 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10730 &offset_expr
, AT
, ZERO
);
10736 /* Fall through. */
10740 else if (op
[0] == 0)
10741 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10742 &offset_expr
, ZERO
, op
[1]);
10746 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10747 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10748 &offset_expr
, AT
, ZERO
);
10754 /* Fall through. */
10760 /* Fall through. */
10766 as_warn (_("divide by zero"));
10768 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10770 macro_build (NULL
, "break", BRK_FMT
, 7);
10774 start_noreorder ();
10777 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10778 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10782 if (mips_opts
.micromips
)
10783 micromips_label_expr (&label_expr
);
10785 label_expr
.X_add_number
= 8;
10786 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10787 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10788 macro_build (NULL
, "break", BRK_FMT
, 7);
10789 if (mips_opts
.micromips
)
10790 micromips_add_label ();
10792 expr1
.X_add_number
= -1;
10794 load_register (AT
, &expr1
, dbl
);
10795 if (mips_opts
.micromips
)
10796 micromips_label_expr (&label_expr
);
10798 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10799 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10802 expr1
.X_add_number
= 1;
10803 load_register (AT
, &expr1
, dbl
);
10804 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10808 expr1
.X_add_number
= 0x80000000;
10809 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10813 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10814 /* We want to close the noreorder block as soon as possible, so
10815 that later insns are available for delay slot filling. */
10820 if (mips_opts
.micromips
)
10821 micromips_label_expr (&label_expr
);
10823 label_expr
.X_add_number
= 8;
10824 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10825 macro_build (NULL
, "nop", "");
10827 /* We want to close the noreorder block as soon as possible, so
10828 that later insns are available for delay slot filling. */
10831 macro_build (NULL
, "break", BRK_FMT
, 6);
10833 if (mips_opts
.micromips
)
10834 micromips_add_label ();
10835 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10874 if (imm_expr
.X_add_number
== 0)
10876 as_warn (_("divide by zero"));
10878 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10880 macro_build (NULL
, "break", BRK_FMT
, 7);
10883 if (imm_expr
.X_add_number
== 1)
10885 if (strcmp (s2
, "mflo") == 0)
10886 move_register (op
[0], op
[1]);
10888 move_register (op
[0], ZERO
);
10891 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10893 if (strcmp (s2
, "mflo") == 0)
10894 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10896 move_register (op
[0], ZERO
);
10901 load_register (AT
, &imm_expr
, dbl
);
10902 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10903 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10922 start_noreorder ();
10925 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10926 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10927 /* We want to close the noreorder block as soon as possible, so
10928 that later insns are available for delay slot filling. */
10933 if (mips_opts
.micromips
)
10934 micromips_label_expr (&label_expr
);
10936 label_expr
.X_add_number
= 8;
10937 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10938 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10940 /* We want to close the noreorder block as soon as possible, so
10941 that later insns are available for delay slot filling. */
10943 macro_build (NULL
, "break", BRK_FMT
, 7);
10944 if (mips_opts
.micromips
)
10945 micromips_add_label ();
10947 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10952 /* Fall through. */
10958 /* Fall through. */
10961 /* Load the address of a symbol into a register. If breg is not
10962 zero, we then add a base register to it. */
10965 if (dbl
&& GPR_SIZE
== 32)
10966 as_warn (_("dla used to load 32-bit register; recommend using la "
10969 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10970 as_warn (_("la used to load 64-bit address; recommend using dla "
10973 if (small_offset_p (0, align
, 16))
10975 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
10976 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
10980 if (mips_opts
.at
&& (op
[0] == breg
))
10988 if (offset_expr
.X_op
!= O_symbol
10989 && offset_expr
.X_op
!= O_constant
)
10991 as_bad (_("expression too complex"));
10992 offset_expr
.X_op
= O_constant
;
10995 if (offset_expr
.X_op
== O_constant
)
10996 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
10997 else if (mips_pic
== NO_PIC
)
10999 /* If this is a reference to a GP relative symbol, we want
11000 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11002 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11003 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11004 If we have a constant, we need two instructions anyhow,
11005 so we may as well always use the latter form.
11007 With 64bit address space and a usable $at we want
11008 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11009 lui $at,<sym> (BFD_RELOC_HI16_S)
11010 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11011 daddiu $at,<sym> (BFD_RELOC_LO16)
11013 daddu $tempreg,$tempreg,$at
11015 If $at is already in use, we use a path which is suboptimal
11016 on superscalar processors.
11017 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11018 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11020 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11022 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11024 For GP relative symbols in 64bit address space we can use
11025 the same sequence as in 32bit address space. */
11026 if (HAVE_64BIT_SYMBOLS
)
11028 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11029 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11031 relax_start (offset_expr
.X_add_symbol
);
11032 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11033 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11037 if (used_at
== 0 && mips_opts
.at
)
11039 macro_build (&offset_expr
, "lui", LUI_FMT
,
11040 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11041 macro_build (&offset_expr
, "lui", LUI_FMT
,
11042 AT
, BFD_RELOC_HI16_S
);
11043 macro_build (&offset_expr
, "daddiu", "t,r,j",
11044 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11045 macro_build (&offset_expr
, "daddiu", "t,r,j",
11046 AT
, AT
, BFD_RELOC_LO16
);
11047 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11048 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11053 macro_build (&offset_expr
, "lui", LUI_FMT
,
11054 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11055 macro_build (&offset_expr
, "daddiu", "t,r,j",
11056 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11057 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11058 macro_build (&offset_expr
, "daddiu", "t,r,j",
11059 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11060 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11061 macro_build (&offset_expr
, "daddiu", "t,r,j",
11062 tempreg
, tempreg
, BFD_RELOC_LO16
);
11065 if (mips_relax
.sequence
)
11070 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11071 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11073 relax_start (offset_expr
.X_add_symbol
);
11074 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11075 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11078 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11079 as_bad (_("offset too large"));
11080 macro_build_lui (&offset_expr
, tempreg
);
11081 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11082 tempreg
, tempreg
, BFD_RELOC_LO16
);
11083 if (mips_relax
.sequence
)
11087 else if (!mips_big_got
&& !HAVE_NEWABI
)
11089 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11091 /* If this is a reference to an external symbol, and there
11092 is no constant, we want
11093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11094 or for lca or if tempreg is PIC_CALL_REG
11095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11096 For a local symbol, we want
11097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11099 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11101 If we have a small constant, and this is a reference to
11102 an external symbol, we want
11103 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11105 addiu $tempreg,$tempreg,<constant>
11106 For a local symbol, we want the same instruction
11107 sequence, but we output a BFD_RELOC_LO16 reloc on the
11110 If we have a large constant, and this is a reference to
11111 an external symbol, we want
11112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11113 lui $at,<hiconstant>
11114 addiu $at,$at,<loconstant>
11115 addu $tempreg,$tempreg,$at
11116 For a local symbol, we want the same instruction
11117 sequence, but we output a BFD_RELOC_LO16 reloc on the
11121 if (offset_expr
.X_add_number
== 0)
11123 if (mips_pic
== SVR4_PIC
11125 && (call
|| tempreg
== PIC_CALL_REG
))
11126 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11128 relax_start (offset_expr
.X_add_symbol
);
11129 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11130 lw_reloc_type
, mips_gp_register
);
11133 /* We're going to put in an addu instruction using
11134 tempreg, so we may as well insert the nop right
11139 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11140 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11142 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11143 tempreg
, tempreg
, BFD_RELOC_LO16
);
11145 /* FIXME: If breg == 0, and the next instruction uses
11146 $tempreg, then if this variant case is used an extra
11147 nop will be generated. */
11149 else if (offset_expr
.X_add_number
>= -0x8000
11150 && offset_expr
.X_add_number
< 0x8000)
11152 load_got_offset (tempreg
, &offset_expr
);
11154 add_got_offset (tempreg
, &offset_expr
);
11158 expr1
.X_add_number
= offset_expr
.X_add_number
;
11159 offset_expr
.X_add_number
=
11160 SEXT_16BIT (offset_expr
.X_add_number
);
11161 load_got_offset (tempreg
, &offset_expr
);
11162 offset_expr
.X_add_number
= expr1
.X_add_number
;
11163 /* If we are going to add in a base register, and the
11164 target register and the base register are the same,
11165 then we are using AT as a temporary register. Since
11166 we want to load the constant into AT, we add our
11167 current AT (from the global offset table) and the
11168 register into the register now, and pretend we were
11169 not using a base register. */
11173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11178 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11182 else if (!mips_big_got
&& HAVE_NEWABI
)
11184 int add_breg_early
= 0;
11186 /* If this is a reference to an external, and there is no
11187 constant, or local symbol (*), with or without a
11189 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11190 or for lca or if tempreg is PIC_CALL_REG
11191 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11193 If we have a small constant, and this is a reference to
11194 an external symbol, we want
11195 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11196 addiu $tempreg,$tempreg,<constant>
11198 If we have a large constant, and this is a reference to
11199 an external symbol, we want
11200 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11201 lui $at,<hiconstant>
11202 addiu $at,$at,<loconstant>
11203 addu $tempreg,$tempreg,$at
11205 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11206 local symbols, even though it introduces an additional
11209 if (offset_expr
.X_add_number
)
11211 expr1
.X_add_number
= offset_expr
.X_add_number
;
11212 offset_expr
.X_add_number
= 0;
11214 relax_start (offset_expr
.X_add_symbol
);
11215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11216 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11218 if (expr1
.X_add_number
>= -0x8000
11219 && expr1
.X_add_number
< 0x8000)
11221 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11222 tempreg
, tempreg
, BFD_RELOC_LO16
);
11224 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11228 /* If we are going to add in a base register, and the
11229 target register and the base register are the same,
11230 then we are using AT as a temporary register. Since
11231 we want to load the constant into AT, we add our
11232 current AT (from the global offset table) and the
11233 register into the register now, and pretend we were
11234 not using a base register. */
11239 gas_assert (tempreg
== AT
);
11240 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11243 add_breg_early
= 1;
11246 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11247 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11253 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11256 offset_expr
.X_add_number
= expr1
.X_add_number
;
11258 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11259 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11260 if (add_breg_early
)
11262 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11263 op
[0], tempreg
, breg
);
11269 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11271 relax_start (offset_expr
.X_add_symbol
);
11272 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11273 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11275 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11276 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11281 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11282 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11285 else if (mips_big_got
&& !HAVE_NEWABI
)
11288 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11289 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11290 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11292 /* This is the large GOT case. If this is a reference to an
11293 external symbol, and there is no constant, we want
11294 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11295 addu $tempreg,$tempreg,$gp
11296 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11297 or for lca or if tempreg is PIC_CALL_REG
11298 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11299 addu $tempreg,$tempreg,$gp
11300 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11301 For a local symbol, we want
11302 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11304 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11306 If we have a small constant, and this is a reference to
11307 an external symbol, we want
11308 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11309 addu $tempreg,$tempreg,$gp
11310 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11312 addiu $tempreg,$tempreg,<constant>
11313 For a local symbol, we want
11314 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11316 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11318 If we have a large constant, and this is a reference to
11319 an external symbol, we want
11320 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11321 addu $tempreg,$tempreg,$gp
11322 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11323 lui $at,<hiconstant>
11324 addiu $at,$at,<loconstant>
11325 addu $tempreg,$tempreg,$at
11326 For a local symbol, we want
11327 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11328 lui $at,<hiconstant>
11329 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11330 addu $tempreg,$tempreg,$at
11333 expr1
.X_add_number
= offset_expr
.X_add_number
;
11334 offset_expr
.X_add_number
= 0;
11335 relax_start (offset_expr
.X_add_symbol
);
11336 gpdelay
= reg_needs_delay (mips_gp_register
);
11337 if (expr1
.X_add_number
== 0 && breg
== 0
11338 && (call
|| tempreg
== PIC_CALL_REG
))
11340 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11341 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11343 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11344 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11345 tempreg
, tempreg
, mips_gp_register
);
11346 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11347 tempreg
, lw_reloc_type
, tempreg
);
11348 if (expr1
.X_add_number
== 0)
11352 /* We're going to put in an addu instruction using
11353 tempreg, so we may as well insert the nop right
11358 else if (expr1
.X_add_number
>= -0x8000
11359 && expr1
.X_add_number
< 0x8000)
11362 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11363 tempreg
, tempreg
, BFD_RELOC_LO16
);
11369 /* If we are going to add in a base register, and the
11370 target register and the base register are the same,
11371 then we are using AT as a temporary register. Since
11372 we want to load the constant into AT, we add our
11373 current AT (from the global offset table) and the
11374 register into the register now, and pretend we were
11375 not using a base register. */
11380 gas_assert (tempreg
== AT
);
11382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11387 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11388 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11392 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11397 /* This is needed because this instruction uses $gp, but
11398 the first instruction on the main stream does not. */
11399 macro_build (NULL
, "nop", "");
11402 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11403 local_reloc_type
, mips_gp_register
);
11404 if (expr1
.X_add_number
>= -0x8000
11405 && expr1
.X_add_number
< 0x8000)
11408 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11409 tempreg
, tempreg
, BFD_RELOC_LO16
);
11410 /* FIXME: If add_number is 0, and there was no base
11411 register, the external symbol case ended with a load,
11412 so if the symbol turns out to not be external, and
11413 the next instruction uses tempreg, an unnecessary nop
11414 will be inserted. */
11420 /* We must add in the base register now, as in the
11421 external symbol case. */
11422 gas_assert (tempreg
== AT
);
11424 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11427 /* We set breg to 0 because we have arranged to add
11428 it in in both cases. */
11432 macro_build_lui (&expr1
, AT
);
11433 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11434 AT
, AT
, BFD_RELOC_LO16
);
11435 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11436 tempreg
, tempreg
, AT
);
11441 else if (mips_big_got
&& HAVE_NEWABI
)
11443 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11444 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11445 int add_breg_early
= 0;
11447 /* This is the large GOT case. If this is a reference to an
11448 external symbol, and there is no constant, we want
11449 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11450 add $tempreg,$tempreg,$gp
11451 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11452 or for lca or if tempreg is PIC_CALL_REG
11453 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11454 add $tempreg,$tempreg,$gp
11455 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11457 If we have a small constant, and this is a reference to
11458 an external symbol, we want
11459 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11460 add $tempreg,$tempreg,$gp
11461 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11462 addi $tempreg,$tempreg,<constant>
11464 If we have a large constant, and this is a reference to
11465 an external symbol, we want
11466 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11467 addu $tempreg,$tempreg,$gp
11468 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11469 lui $at,<hiconstant>
11470 addi $at,$at,<loconstant>
11471 add $tempreg,$tempreg,$at
11473 If we have NewABI, and we know it's a local symbol, we want
11474 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11475 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11476 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11478 relax_start (offset_expr
.X_add_symbol
);
11480 expr1
.X_add_number
= offset_expr
.X_add_number
;
11481 offset_expr
.X_add_number
= 0;
11483 if (expr1
.X_add_number
== 0 && breg
== 0
11484 && (call
|| tempreg
== PIC_CALL_REG
))
11486 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11487 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11489 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11490 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11491 tempreg
, tempreg
, mips_gp_register
);
11492 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11493 tempreg
, lw_reloc_type
, tempreg
);
11495 if (expr1
.X_add_number
== 0)
11497 else if (expr1
.X_add_number
>= -0x8000
11498 && expr1
.X_add_number
< 0x8000)
11500 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11501 tempreg
, tempreg
, BFD_RELOC_LO16
);
11503 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11507 /* If we are going to add in a base register, and the
11508 target register and the base register are the same,
11509 then we are using AT as a temporary register. Since
11510 we want to load the constant into AT, we add our
11511 current AT (from the global offset table) and the
11512 register into the register now, and pretend we were
11513 not using a base register. */
11518 gas_assert (tempreg
== AT
);
11519 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11522 add_breg_early
= 1;
11525 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11526 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11531 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11534 offset_expr
.X_add_number
= expr1
.X_add_number
;
11535 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11536 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11537 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11538 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11539 if (add_breg_early
)
11541 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11542 op
[0], tempreg
, breg
);
11552 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11556 gas_assert (!mips_opts
.micromips
);
11557 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11561 gas_assert (!mips_opts
.micromips
);
11562 macro_build (NULL
, "c2", "C", 0x02);
11566 gas_assert (!mips_opts
.micromips
);
11567 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11571 gas_assert (!mips_opts
.micromips
);
11572 macro_build (NULL
, "c2", "C", 3);
11576 gas_assert (!mips_opts
.micromips
);
11577 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11581 /* The j instruction may not be used in PIC code, since it
11582 requires an absolute address. We convert it to a b
11584 if (mips_pic
== NO_PIC
)
11585 macro_build (&offset_expr
, "j", "a");
11587 macro_build (&offset_expr
, "b", "p");
11590 /* The jal instructions must be handled as macros because when
11591 generating PIC code they expand to multi-instruction
11592 sequences. Normally they are simple instructions. */
11596 /* Fall through. */
11598 gas_assert (mips_opts
.micromips
);
11599 if (mips_opts
.insn32
)
11601 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11609 /* Fall through. */
11612 if (mips_pic
== NO_PIC
)
11614 s
= jals
? "jalrs" : "jalr";
11615 if (mips_opts
.micromips
11616 && !mips_opts
.insn32
11618 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11619 macro_build (NULL
, s
, "mj", op
[1]);
11621 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11625 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11626 && mips_cprestore_offset
>= 0);
11628 if (op
[1] != PIC_CALL_REG
)
11629 as_warn (_("MIPS PIC call to register other than $25"));
11631 s
= ((mips_opts
.micromips
11632 && !mips_opts
.insn32
11633 && (!mips_opts
.noreorder
|| cprestore
))
11634 ? "jalrs" : "jalr");
11635 if (mips_opts
.micromips
11636 && !mips_opts
.insn32
11638 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11639 macro_build (NULL
, s
, "mj", op
[1]);
11641 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11642 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11644 if (mips_cprestore_offset
< 0)
11645 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11648 if (!mips_frame_reg_valid
)
11650 as_warn (_("no .frame pseudo-op used in PIC code"));
11651 /* Quiet this warning. */
11652 mips_frame_reg_valid
= 1;
11654 if (!mips_cprestore_valid
)
11656 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11657 /* Quiet this warning. */
11658 mips_cprestore_valid
= 1;
11660 if (mips_opts
.noreorder
)
11661 macro_build (NULL
, "nop", "");
11662 expr1
.X_add_number
= mips_cprestore_offset
;
11663 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11666 HAVE_64BIT_ADDRESSES
);
11674 gas_assert (mips_opts
.micromips
);
11675 if (mips_opts
.insn32
)
11677 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11681 /* Fall through. */
11683 if (mips_pic
== NO_PIC
)
11684 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11685 else if (mips_pic
== SVR4_PIC
)
11687 /* If this is a reference to an external symbol, and we are
11688 using a small GOT, we want
11689 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11693 lw $gp,cprestore($sp)
11694 The cprestore value is set using the .cprestore
11695 pseudo-op. If we are using a big GOT, we want
11696 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11698 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11702 lw $gp,cprestore($sp)
11703 If the symbol is not external, we want
11704 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11706 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11709 lw $gp,cprestore($sp)
11711 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11712 sequences above, minus nops, unless the symbol is local,
11713 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11719 relax_start (offset_expr
.X_add_symbol
);
11720 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11721 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11724 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11725 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11731 relax_start (offset_expr
.X_add_symbol
);
11732 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11733 BFD_RELOC_MIPS_CALL_HI16
);
11734 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11735 PIC_CALL_REG
, mips_gp_register
);
11736 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11737 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11740 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11741 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11743 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11744 PIC_CALL_REG
, PIC_CALL_REG
,
11745 BFD_RELOC_MIPS_GOT_OFST
);
11749 macro_build_jalr (&offset_expr
, 0);
11753 relax_start (offset_expr
.X_add_symbol
);
11756 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11757 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11766 gpdelay
= reg_needs_delay (mips_gp_register
);
11767 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11768 BFD_RELOC_MIPS_CALL_HI16
);
11769 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11770 PIC_CALL_REG
, mips_gp_register
);
11771 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11772 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11777 macro_build (NULL
, "nop", "");
11779 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11780 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11783 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11784 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11786 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11788 if (mips_cprestore_offset
< 0)
11789 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11792 if (!mips_frame_reg_valid
)
11794 as_warn (_("no .frame pseudo-op used in PIC code"));
11795 /* Quiet this warning. */
11796 mips_frame_reg_valid
= 1;
11798 if (!mips_cprestore_valid
)
11800 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11801 /* Quiet this warning. */
11802 mips_cprestore_valid
= 1;
11804 if (mips_opts
.noreorder
)
11805 macro_build (NULL
, "nop", "");
11806 expr1
.X_add_number
= mips_cprestore_offset
;
11807 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11810 HAVE_64BIT_ADDRESSES
);
11814 else if (mips_pic
== VXWORKS_PIC
)
11815 as_bad (_("non-PIC jump used in PIC library"));
11922 gas_assert (!mips_opts
.micromips
);
11925 /* Itbl support may require additional care here. */
11931 /* Itbl support may require additional care here. */
11937 offbits
= (mips_opts
.micromips
? 12
11938 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11940 /* Itbl support may require additional care here. */
11944 gas_assert (!mips_opts
.micromips
);
11947 /* Itbl support may require additional care here. */
11953 offbits
= (mips_opts
.micromips
? 12 : 16);
11958 offbits
= (mips_opts
.micromips
? 12 : 16);
11963 /* Itbl support may require additional care here. */
11969 offbits
= (mips_opts
.micromips
? 12
11970 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11972 /* Itbl support may require additional care here. */
11978 /* Itbl support may require additional care here. */
11984 /* Itbl support may require additional care here. */
11990 offbits
= (mips_opts
.micromips
? 12 : 16);
11995 offbits
= (mips_opts
.micromips
? 12 : 16);
12000 offbits
= (mips_opts
.micromips
? 12
12001 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12007 offbits
= (mips_opts
.micromips
? 12
12008 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12014 offbits
= (mips_opts
.micromips
? 12 : 16);
12017 gas_assert (mips_opts
.micromips
);
12024 gas_assert (mips_opts
.micromips
);
12033 s
= ip
->insn_mo
->name
;
12039 gas_assert (mips_opts
.micromips
);
12045 gas_assert (mips_opts
.micromips
);
12052 /* Try to use one the the load registers to compute the base address.
12053 We don't want to use $0 as tempreg. */
12056 if ((op
[0] == ZERO
&& op
[3] == op
[1])
12057 || (op
[1] == ZERO
&& op
[3] == op
[0])
12058 || (op
[0] == ZERO
&& op
[1] == ZERO
))
12060 else if (op
[0] != op
[3] && op
[0] != ZERO
)
12067 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12070 tempreg
= op
[0] + lp
;
12087 gas_assert (!mips_opts
.micromips
);
12090 /* Itbl support may require additional care here. */
12096 /* Itbl support may require additional care here. */
12102 offbits
= (mips_opts
.micromips
? 12
12103 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12105 /* Itbl support may require additional care here. */
12109 gas_assert (!mips_opts
.micromips
);
12112 /* Itbl support may require additional care here. */
12118 offbits
= (mips_opts
.micromips
? 12 : 16);
12123 offbits
= (mips_opts
.micromips
? 12 : 16);
12128 offbits
= (mips_opts
.micromips
? 12
12129 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12135 offbits
= (mips_opts
.micromips
? 12
12136 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12142 s
= ip
->insn_mo
->name
;
12149 fmt
= (mips_opts
.micromips
? "k,~(b)"
12150 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12152 offbits
= (mips_opts
.micromips
? 12
12153 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12163 fmt
= (mips_opts
.micromips
? "k,~(b)"
12164 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12166 offbits
= (mips_opts
.micromips
? 12
12167 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12179 /* Itbl support may require additional care here. */
12184 offbits
= (mips_opts
.micromips
? 12
12185 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12187 /* Itbl support may require additional care here. */
12193 /* Itbl support may require additional care here. */
12197 gas_assert (!mips_opts
.micromips
);
12200 /* Itbl support may require additional care here. */
12206 offbits
= (mips_opts
.micromips
? 12 : 16);
12211 offbits
= (mips_opts
.micromips
? 12 : 16);
12214 gas_assert (mips_opts
.micromips
);
12220 gas_assert (mips_opts
.micromips
);
12226 gas_assert (mips_opts
.micromips
);
12232 gas_assert (mips_opts
.micromips
);
12240 breg
= ll_sc_paired
? op
[3] : op
[2];
12241 if (small_offset_p (0, align
, 16))
12243 /* The first case exists for M_LD_AB and M_SD_AB, which are
12244 macros for o32 but which should act like normal instructions
12247 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12248 offset_reloc
[1], offset_reloc
[2], breg
);
12249 else if (small_offset_p (0, align
, offbits
))
12254 macro_build (NULL
, s
, fmt
, op
[0], op
[1], breg
);
12256 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12259 macro_build (NULL
, s
, fmt
, op
[0],
12260 (int) offset_expr
.X_add_number
, breg
);
12266 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12267 tempreg
, breg
, -1, offset_reloc
[0],
12268 offset_reloc
[1], offset_reloc
[2]);
12272 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12274 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12277 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12285 if (offset_expr
.X_op
!= O_constant
12286 && offset_expr
.X_op
!= O_symbol
)
12288 as_bad (_("expression too complex"));
12289 offset_expr
.X_op
= O_constant
;
12292 if (HAVE_32BIT_ADDRESSES
12293 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12297 sprintf_vma (value
, offset_expr
.X_add_number
);
12298 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12301 /* A constant expression in PIC code can be handled just as it
12302 is in non PIC code. */
12303 if (offset_expr
.X_op
== O_constant
)
12305 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12306 offbits
== 0 ? 16 : offbits
);
12307 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12309 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12311 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12312 tempreg
, tempreg
, breg
);
12315 if (offset_expr
.X_add_number
!= 0)
12316 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12317 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12319 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12321 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12323 else if (offbits
== 16)
12324 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12326 macro_build (NULL
, s
, fmt
, op
[0],
12327 (int) offset_expr
.X_add_number
, tempreg
);
12329 else if (offbits
!= 16)
12331 /* The offset field is too narrow to be used for a low-part
12332 relocation, so load the whole address into the auxiliary
12334 load_address (tempreg
, &offset_expr
, &used_at
);
12336 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12337 tempreg
, tempreg
, breg
);
12341 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12343 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12346 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12348 else if (mips_pic
== NO_PIC
)
12350 /* If this is a reference to a GP relative symbol, and there
12351 is no base register, we want
12352 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12353 Otherwise, if there is no base register, we want
12354 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12355 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12356 If we have a constant, we need two instructions anyhow,
12357 so we always use the latter form.
12359 If we have a base register, and this is a reference to a
12360 GP relative symbol, we want
12361 addu $tempreg,$breg,$gp
12362 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12364 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12365 addu $tempreg,$tempreg,$breg
12366 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12367 With a constant we always use the latter case.
12369 With 64bit address space and no base register and $at usable,
12371 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12372 lui $at,<sym> (BFD_RELOC_HI16_S)
12373 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12376 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12377 If we have a base register, we want
12378 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12379 lui $at,<sym> (BFD_RELOC_HI16_S)
12380 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12384 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12386 Without $at we can't generate the optimal path for superscalar
12387 processors here since this would require two temporary registers.
12388 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12389 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12391 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12393 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12394 If we have a base register, we want
12395 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12396 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12398 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12400 daddu $tempreg,$tempreg,$breg
12401 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12403 For GP relative symbols in 64bit address space we can use
12404 the same sequence as in 32bit address space. */
12405 if (HAVE_64BIT_SYMBOLS
)
12407 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12408 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12410 relax_start (offset_expr
.X_add_symbol
);
12413 macro_build (&offset_expr
, s
, fmt
, op
[0],
12414 BFD_RELOC_GPREL16
, mips_gp_register
);
12418 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12419 tempreg
, breg
, mips_gp_register
);
12420 macro_build (&offset_expr
, s
, fmt
, op
[0],
12421 BFD_RELOC_GPREL16
, tempreg
);
12426 if (used_at
== 0 && mips_opts
.at
)
12428 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12429 BFD_RELOC_MIPS_HIGHEST
);
12430 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12432 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12433 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12435 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12436 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12437 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12438 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12444 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12445 BFD_RELOC_MIPS_HIGHEST
);
12446 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12447 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12448 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12449 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12450 tempreg
, BFD_RELOC_HI16_S
);
12451 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12453 macro_build (NULL
, "daddu", "d,v,t",
12454 tempreg
, tempreg
, breg
);
12455 macro_build (&offset_expr
, s
, fmt
, op
[0],
12456 BFD_RELOC_LO16
, tempreg
);
12459 if (mips_relax
.sequence
)
12466 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12467 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12469 relax_start (offset_expr
.X_add_symbol
);
12470 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12474 macro_build_lui (&offset_expr
, tempreg
);
12475 macro_build (&offset_expr
, s
, fmt
, op
[0],
12476 BFD_RELOC_LO16
, tempreg
);
12477 if (mips_relax
.sequence
)
12482 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12483 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12485 relax_start (offset_expr
.X_add_symbol
);
12486 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12487 tempreg
, breg
, mips_gp_register
);
12488 macro_build (&offset_expr
, s
, fmt
, op
[0],
12489 BFD_RELOC_GPREL16
, tempreg
);
12492 macro_build_lui (&offset_expr
, tempreg
);
12493 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12494 tempreg
, tempreg
, breg
);
12495 macro_build (&offset_expr
, s
, fmt
, op
[0],
12496 BFD_RELOC_LO16
, tempreg
);
12497 if (mips_relax
.sequence
)
12501 else if (!mips_big_got
)
12503 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12505 /* If this is a reference to an external symbol, we want
12506 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12508 <op> op[0],0($tempreg)
12510 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12512 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12513 <op> op[0],0($tempreg)
12515 For NewABI, we want
12516 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12517 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12519 If there is a base register, we add it to $tempreg before
12520 the <op>. If there is a constant, we stick it in the
12521 <op> instruction. We don't handle constants larger than
12522 16 bits, because we have no way to load the upper 16 bits
12523 (actually, we could handle them for the subset of cases
12524 in which we are not using $at). */
12525 gas_assert (offset_expr
.X_op
== O_symbol
);
12528 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12529 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12531 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12532 tempreg
, tempreg
, breg
);
12533 macro_build (&offset_expr
, s
, fmt
, op
[0],
12534 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12537 expr1
.X_add_number
= offset_expr
.X_add_number
;
12538 offset_expr
.X_add_number
= 0;
12539 if (expr1
.X_add_number
< -0x8000
12540 || expr1
.X_add_number
>= 0x8000)
12541 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12542 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12543 lw_reloc_type
, mips_gp_register
);
12545 relax_start (offset_expr
.X_add_symbol
);
12547 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12548 tempreg
, BFD_RELOC_LO16
);
12551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12552 tempreg
, tempreg
, breg
);
12553 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12555 else if (mips_big_got
&& !HAVE_NEWABI
)
12559 /* If this is a reference to an external symbol, we want
12560 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12561 addu $tempreg,$tempreg,$gp
12562 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12563 <op> op[0],0($tempreg)
12565 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12567 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12568 <op> op[0],0($tempreg)
12569 If there is a base register, we add it to $tempreg before
12570 the <op>. If there is a constant, we stick it in the
12571 <op> instruction. We don't handle constants larger than
12572 16 bits, because we have no way to load the upper 16 bits
12573 (actually, we could handle them for the subset of cases
12574 in which we are not using $at). */
12575 gas_assert (offset_expr
.X_op
== O_symbol
);
12576 expr1
.X_add_number
= offset_expr
.X_add_number
;
12577 offset_expr
.X_add_number
= 0;
12578 if (expr1
.X_add_number
< -0x8000
12579 || expr1
.X_add_number
>= 0x8000)
12580 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12581 gpdelay
= reg_needs_delay (mips_gp_register
);
12582 relax_start (offset_expr
.X_add_symbol
);
12583 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12584 BFD_RELOC_MIPS_GOT_HI16
);
12585 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12587 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12588 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12591 macro_build (NULL
, "nop", "");
12592 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12593 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12595 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12596 tempreg
, BFD_RELOC_LO16
);
12600 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12601 tempreg
, tempreg
, breg
);
12602 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12604 else if (mips_big_got
&& HAVE_NEWABI
)
12606 /* If this is a reference to an external symbol, we want
12607 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12608 add $tempreg,$tempreg,$gp
12609 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12610 <op> op[0],<ofst>($tempreg)
12611 Otherwise, for local symbols, we want:
12612 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12613 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12614 gas_assert (offset_expr
.X_op
== O_symbol
);
12615 expr1
.X_add_number
= offset_expr
.X_add_number
;
12616 offset_expr
.X_add_number
= 0;
12617 if (expr1
.X_add_number
< -0x8000
12618 || expr1
.X_add_number
>= 0x8000)
12619 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12620 relax_start (offset_expr
.X_add_symbol
);
12621 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12622 BFD_RELOC_MIPS_GOT_HI16
);
12623 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12625 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12626 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12628 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12629 tempreg
, tempreg
, breg
);
12630 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12633 offset_expr
.X_add_number
= expr1
.X_add_number
;
12634 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12635 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12637 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12638 tempreg
, tempreg
, breg
);
12639 macro_build (&offset_expr
, s
, fmt
, op
[0],
12640 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12649 gas_assert (mips_opts
.micromips
);
12650 gas_assert (mips_opts
.insn32
);
12651 start_noreorder ();
12652 macro_build (NULL
, "jr", "s", RA
);
12653 expr1
.X_add_number
= op
[0] << 2;
12654 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12659 gas_assert (mips_opts
.micromips
);
12660 gas_assert (mips_opts
.insn32
);
12661 macro_build (NULL
, "jr", "s", op
[0]);
12662 if (mips_opts
.noreorder
)
12663 macro_build (NULL
, "nop", "");
12668 load_register (op
[0], &imm_expr
, 0);
12672 load_register (op
[0], &imm_expr
, 1);
12676 if (imm_expr
.X_op
== O_constant
)
12679 load_register (AT
, &imm_expr
, 0);
12680 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12685 gas_assert (imm_expr
.X_op
== O_absent
12686 && offset_expr
.X_op
== O_symbol
12687 && strcmp (segment_name (S_GET_SEGMENT
12688 (offset_expr
.X_add_symbol
)),
12690 && offset_expr
.X_add_number
== 0);
12691 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12692 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12697 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12698 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12699 order 32 bits of the value and the low order 32 bits are either
12700 zero or in OFFSET_EXPR. */
12701 if (imm_expr
.X_op
== O_constant
)
12703 if (GPR_SIZE
== 64)
12704 load_register (op
[0], &imm_expr
, 1);
12709 if (target_big_endian
)
12721 load_register (hreg
, &imm_expr
, 0);
12724 if (offset_expr
.X_op
== O_absent
)
12725 move_register (lreg
, 0);
12728 gas_assert (offset_expr
.X_op
== O_constant
);
12729 load_register (lreg
, &offset_expr
, 0);
12735 gas_assert (imm_expr
.X_op
== O_absent
);
12737 /* We know that sym is in the .rdata section. First we get the
12738 upper 16 bits of the address. */
12739 if (mips_pic
== NO_PIC
)
12741 macro_build_lui (&offset_expr
, AT
);
12746 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12747 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12751 /* Now we load the register(s). */
12752 if (GPR_SIZE
== 64)
12755 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12756 BFD_RELOC_LO16
, AT
);
12761 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12762 BFD_RELOC_LO16
, AT
);
12765 /* FIXME: How in the world do we deal with the possible
12767 offset_expr
.X_add_number
+= 4;
12768 macro_build (&offset_expr
, "lw", "t,o(b)",
12769 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12775 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12776 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12777 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12778 the value and the low order 32 bits are either zero or in
12780 if (imm_expr
.X_op
== O_constant
)
12783 if (((FPR_SIZE
== 64 && GPR_SIZE
== 64)
12784 || !ISA_HAS_MXHC1 (mips_opts
.isa
))
12785 && imm_expr
.X_add_number
!= 0)
12789 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12791 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12792 macro_build (NULL
, "dmtc1", "t,S", tempreg
, op
[0]);
12795 if (!ISA_HAS_MXHC1 (mips_opts
.isa
))
12797 if (FPR_SIZE
!= 32)
12798 as_bad (_("Unable to generate `%s' compliant code "
12800 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12802 macro_build (NULL
, "mtc1", "t,G", tempreg
, op
[0] + 1);
12804 if (offset_expr
.X_op
== O_absent
)
12805 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12808 gas_assert (offset_expr
.X_op
== O_constant
);
12809 load_register (AT
, &offset_expr
, 0);
12810 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12812 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12814 if (imm_expr
.X_add_number
!= 0)
12818 load_register (AT
, &imm_expr
, 0);
12820 macro_build (NULL
, "mthc1", "t,G", tempreg
, op
[0]);
12826 gas_assert (imm_expr
.X_op
== O_absent
12827 && offset_expr
.X_op
== O_symbol
12828 && offset_expr
.X_add_number
== 0);
12829 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12830 if (strcmp (s
, ".lit8") == 0)
12832 op
[2] = mips_gp_register
;
12833 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12834 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12835 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12839 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12841 if (mips_pic
!= NO_PIC
)
12842 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12843 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12846 /* FIXME: This won't work for a 64 bit address. */
12847 macro_build_lui (&offset_expr
, AT
);
12851 offset_reloc
[0] = BFD_RELOC_LO16
;
12852 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12853 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12856 /* Fall through. */
12859 /* The MIPS assembler seems to check for X_add_number not
12860 being double aligned and generating:
12863 addiu at,at,%lo(foo+1)
12866 But, the resulting address is the same after relocation so why
12867 generate the extra instruction? */
12868 /* Itbl support may require additional care here. */
12871 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12880 gas_assert (!mips_opts
.micromips
);
12881 /* Itbl support may require additional care here. */
12884 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12904 if (GPR_SIZE
== 64)
12914 if (GPR_SIZE
== 64)
12922 /* Even on a big endian machine $fn comes before $fn+1. We have
12923 to adjust when loading from memory. We set coproc if we must
12924 load $fn+1 first. */
12925 /* Itbl support may require additional care here. */
12926 if (!target_big_endian
)
12930 if (small_offset_p (0, align
, 16))
12933 if (!small_offset_p (4, align
, 16))
12935 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12936 -1, offset_reloc
[0], offset_reloc
[1],
12938 expr1
.X_add_number
= 0;
12942 offset_reloc
[0] = BFD_RELOC_LO16
;
12943 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12944 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12946 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12948 ep
->X_add_number
+= 4;
12949 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12950 offset_reloc
[1], offset_reloc
[2], breg
);
12951 ep
->X_add_number
-= 4;
12952 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12953 offset_reloc
[1], offset_reloc
[2], breg
);
12957 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12958 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12960 ep
->X_add_number
+= 4;
12961 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12962 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12968 if (offset_expr
.X_op
!= O_symbol
12969 && offset_expr
.X_op
!= O_constant
)
12971 as_bad (_("expression too complex"));
12972 offset_expr
.X_op
= O_constant
;
12975 if (HAVE_32BIT_ADDRESSES
12976 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12980 sprintf_vma (value
, offset_expr
.X_add_number
);
12981 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12984 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
12986 /* If this is a reference to a GP relative symbol, we want
12987 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12988 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
12989 If we have a base register, we use this
12991 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
12992 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
12993 If this is not a GP relative symbol, we want
12994 lui $at,<sym> (BFD_RELOC_HI16_S)
12995 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
12996 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
12997 If there is a base register, we add it to $at after the
12998 lui instruction. If there is a constant, we always use
13000 if (offset_expr
.X_op
== O_symbol
13001 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
13002 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
13004 relax_start (offset_expr
.X_add_symbol
);
13007 tempreg
= mips_gp_register
;
13011 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13012 AT
, breg
, mips_gp_register
);
13017 /* Itbl support may require additional care here. */
13018 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13019 BFD_RELOC_GPREL16
, tempreg
);
13020 offset_expr
.X_add_number
+= 4;
13022 /* Set mips_optimize to 2 to avoid inserting an
13024 hold_mips_optimize
= mips_optimize
;
13026 /* Itbl support may require additional care here. */
13027 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13028 BFD_RELOC_GPREL16
, tempreg
);
13029 mips_optimize
= hold_mips_optimize
;
13033 offset_expr
.X_add_number
-= 4;
13036 if (offset_high_part (offset_expr
.X_add_number
, 16)
13037 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
13039 load_address (AT
, &offset_expr
, &used_at
);
13040 offset_expr
.X_op
= O_constant
;
13041 offset_expr
.X_add_number
= 0;
13044 macro_build_lui (&offset_expr
, AT
);
13046 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13047 /* Itbl support may require additional care here. */
13048 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13049 BFD_RELOC_LO16
, AT
);
13050 /* FIXME: How do we handle overflow here? */
13051 offset_expr
.X_add_number
+= 4;
13052 /* Itbl support may require additional care here. */
13053 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13054 BFD_RELOC_LO16
, AT
);
13055 if (mips_relax
.sequence
)
13058 else if (!mips_big_got
)
13060 /* If this is a reference to an external symbol, we want
13061 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13064 <op> op[0]+1,4($at)
13066 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13068 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13069 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13070 If there is a base register we add it to $at before the
13071 lwc1 instructions. If there is a constant we include it
13072 in the lwc1 instructions. */
13074 expr1
.X_add_number
= offset_expr
.X_add_number
;
13075 if (expr1
.X_add_number
< -0x8000
13076 || expr1
.X_add_number
>= 0x8000 - 4)
13077 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13078 load_got_offset (AT
, &offset_expr
);
13081 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13083 /* Set mips_optimize to 2 to avoid inserting an undesired
13085 hold_mips_optimize
= mips_optimize
;
13088 /* Itbl support may require additional care here. */
13089 relax_start (offset_expr
.X_add_symbol
);
13090 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13091 BFD_RELOC_LO16
, AT
);
13092 expr1
.X_add_number
+= 4;
13093 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13094 BFD_RELOC_LO16
, AT
);
13096 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13097 BFD_RELOC_LO16
, AT
);
13098 offset_expr
.X_add_number
+= 4;
13099 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13100 BFD_RELOC_LO16
, AT
);
13103 mips_optimize
= hold_mips_optimize
;
13105 else if (mips_big_got
)
13109 /* If this is a reference to an external symbol, we want
13110 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13112 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13115 <op> op[0]+1,4($at)
13117 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13119 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13120 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13121 If there is a base register we add it to $at before the
13122 lwc1 instructions. If there is a constant we include it
13123 in the lwc1 instructions. */
13125 expr1
.X_add_number
= offset_expr
.X_add_number
;
13126 offset_expr
.X_add_number
= 0;
13127 if (expr1
.X_add_number
< -0x8000
13128 || expr1
.X_add_number
>= 0x8000 - 4)
13129 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13130 gpdelay
= reg_needs_delay (mips_gp_register
);
13131 relax_start (offset_expr
.X_add_symbol
);
13132 macro_build (&offset_expr
, "lui", LUI_FMT
,
13133 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13134 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13135 AT
, AT
, mips_gp_register
);
13136 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13137 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13140 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13141 /* Itbl support may require additional care here. */
13142 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13143 BFD_RELOC_LO16
, AT
);
13144 expr1
.X_add_number
+= 4;
13146 /* Set mips_optimize to 2 to avoid inserting an undesired
13148 hold_mips_optimize
= mips_optimize
;
13150 /* Itbl support may require additional care here. */
13151 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13152 BFD_RELOC_LO16
, AT
);
13153 mips_optimize
= hold_mips_optimize
;
13154 expr1
.X_add_number
-= 4;
13157 offset_expr
.X_add_number
= expr1
.X_add_number
;
13159 macro_build (NULL
, "nop", "");
13160 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13161 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13164 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13165 /* Itbl support may require additional care here. */
13166 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13167 BFD_RELOC_LO16
, AT
);
13168 offset_expr
.X_add_number
+= 4;
13170 /* Set mips_optimize to 2 to avoid inserting an undesired
13172 hold_mips_optimize
= mips_optimize
;
13174 /* Itbl support may require additional care here. */
13175 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13176 BFD_RELOC_LO16
, AT
);
13177 mips_optimize
= hold_mips_optimize
;
13191 gas_assert (!mips_opts
.micromips
);
13196 /* New code added to support COPZ instructions.
13197 This code builds table entries out of the macros in mip_opcodes.
13198 R4000 uses interlocks to handle coproc delays.
13199 Other chips (like the R3000) require nops to be inserted for delays.
13201 FIXME: Currently, we require that the user handle delays.
13202 In order to fill delay slots for non-interlocked chips,
13203 we must have a way to specify delays based on the coprocessor.
13204 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13205 What are the side-effects of the cop instruction?
13206 What cache support might we have and what are its effects?
13207 Both coprocessor & memory require delays. how long???
13208 What registers are read/set/modified?
13210 If an itbl is provided to interpret cop instructions,
13211 this knowledge can be encoded in the itbl spec. */
13225 gas_assert (!mips_opts
.micromips
);
13226 /* For now we just do C (same as Cz). The parameter will be
13227 stored in insn_opcode by mips_ip. */
13228 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13232 move_register (op
[0], op
[1]);
13236 gas_assert (mips_opts
.micromips
);
13237 gas_assert (mips_opts
.insn32
);
13238 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13239 micromips_to_32_reg_m_map
[op
[1]]);
13240 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13241 micromips_to_32_reg_n_map
[op
[2]]);
13246 /* Fall through. */
13248 if (mips_opts
.arch
== CPU_R5900
)
13249 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13253 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13254 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13260 /* Fall through. */
13262 /* The MIPS assembler some times generates shifts and adds. I'm
13263 not trying to be that fancy. GCC should do this for us
13266 load_register (AT
, &imm_expr
, dbl
);
13267 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13268 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13273 /* Fall through. */
13280 /* Fall through. */
13283 start_noreorder ();
13286 load_register (AT
, &imm_expr
, dbl
);
13287 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13288 op
[1], imm
? AT
: op
[2]);
13289 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13290 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13291 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13293 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13296 if (mips_opts
.micromips
)
13297 micromips_label_expr (&label_expr
);
13299 label_expr
.X_add_number
= 8;
13300 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13301 macro_build (NULL
, "nop", "");
13302 macro_build (NULL
, "break", BRK_FMT
, 6);
13303 if (mips_opts
.micromips
)
13304 micromips_add_label ();
13307 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13312 /* Fall through. */
13319 /* Fall through. */
13322 start_noreorder ();
13325 load_register (AT
, &imm_expr
, dbl
);
13326 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13327 op
[1], imm
? AT
: op
[2]);
13328 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13329 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13331 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13334 if (mips_opts
.micromips
)
13335 micromips_label_expr (&label_expr
);
13337 label_expr
.X_add_number
= 8;
13338 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13339 macro_build (NULL
, "nop", "");
13340 macro_build (NULL
, "break", BRK_FMT
, 6);
13341 if (mips_opts
.micromips
)
13342 micromips_add_label ();
13348 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13350 if (op
[0] == op
[1])
13357 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13358 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13362 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13363 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13364 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13365 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13369 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13371 if (op
[0] == op
[1])
13378 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13379 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13383 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13384 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13385 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13386 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13395 rot
= imm_expr
.X_add_number
& 0x3f;
13396 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13398 rot
= (64 - rot
) & 0x3f;
13400 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13402 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13407 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13410 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13411 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13414 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13415 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13416 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13424 rot
= imm_expr
.X_add_number
& 0x1f;
13425 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13427 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13428 (32 - rot
) & 0x1f);
13433 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13437 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13438 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13439 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13444 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13446 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13450 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13451 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13452 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13453 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13457 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13459 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13463 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13464 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13465 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13466 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13475 rot
= imm_expr
.X_add_number
& 0x3f;
13476 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13479 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13481 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13486 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13489 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13490 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13493 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13494 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13495 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13503 rot
= imm_expr
.X_add_number
& 0x1f;
13504 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13506 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13511 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13515 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13516 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13517 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13523 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13524 else if (op
[2] == 0)
13525 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13528 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13529 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13534 if (imm_expr
.X_add_number
== 0)
13536 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13541 as_warn (_("instruction %s: result is always false"),
13542 ip
->insn_mo
->name
);
13543 move_register (op
[0], 0);
13546 if (CPU_HAS_SEQ (mips_opts
.arch
)
13547 && -512 <= imm_expr
.X_add_number
13548 && imm_expr
.X_add_number
< 512)
13550 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13551 (int) imm_expr
.X_add_number
);
13554 if (imm_expr
.X_add_number
>= 0
13555 && imm_expr
.X_add_number
< 0x10000)
13556 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13557 else if (imm_expr
.X_add_number
> -0x8000
13558 && imm_expr
.X_add_number
< 0)
13560 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13561 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13562 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13564 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13567 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13568 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13573 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13574 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13577 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13580 case M_SGE
: /* X >= Y <==> not (X < Y) */
13586 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13587 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13590 case M_SGE_I
: /* X >= I <==> not (X < I). */
13592 if (imm_expr
.X_add_number
>= -0x8000
13593 && imm_expr
.X_add_number
< 0x8000)
13594 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13595 op
[0], op
[1], BFD_RELOC_LO16
);
13598 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13599 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13603 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13606 case M_SGT
: /* X > Y <==> Y < X. */
13612 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13615 case M_SGT_I
: /* X > I <==> I < X. */
13622 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13623 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13626 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13632 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13633 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13636 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13643 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13644 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13645 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13649 if (imm_expr
.X_add_number
>= -0x8000
13650 && imm_expr
.X_add_number
< 0x8000)
13652 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13657 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13658 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13662 if (imm_expr
.X_add_number
>= -0x8000
13663 && imm_expr
.X_add_number
< 0x8000)
13665 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13670 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13671 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13676 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13677 else if (op
[2] == 0)
13678 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13681 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13682 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13687 if (imm_expr
.X_add_number
== 0)
13689 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13694 as_warn (_("instruction %s: result is always true"),
13695 ip
->insn_mo
->name
);
13696 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13697 op
[0], 0, BFD_RELOC_LO16
);
13700 if (CPU_HAS_SEQ (mips_opts
.arch
)
13701 && -512 <= imm_expr
.X_add_number
13702 && imm_expr
.X_add_number
< 512)
13704 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13705 (int) imm_expr
.X_add_number
);
13708 if (imm_expr
.X_add_number
>= 0
13709 && imm_expr
.X_add_number
< 0x10000)
13711 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13714 else if (imm_expr
.X_add_number
> -0x8000
13715 && imm_expr
.X_add_number
< 0)
13717 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13718 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13719 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13721 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13724 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13725 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13730 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13731 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13734 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13740 if (ISA_IS_R6 (mips_opts
.isa
))
13752 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
13754 if (imm_expr
.X_add_number
> -0x200
13755 && imm_expr
.X_add_number
<= 0x200
13756 && !ISA_IS_R6 (mips_opts
.isa
))
13758 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13759 (int) -imm_expr
.X_add_number
);
13768 if (imm_expr
.X_add_number
> -0x8000
13769 && imm_expr
.X_add_number
<= 0x8000)
13771 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13772 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13777 load_register (AT
, &imm_expr
, dbl
);
13778 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13800 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13801 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13806 gas_assert (!mips_opts
.micromips
);
13807 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13811 * Is the double cfc1 instruction a bug in the mips assembler;
13812 * or is there a reason for it?
13814 start_noreorder ();
13815 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13816 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13817 macro_build (NULL
, "nop", "");
13818 expr1
.X_add_number
= 3;
13819 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13820 expr1
.X_add_number
= 2;
13821 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13822 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13823 macro_build (NULL
, "nop", "");
13824 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13826 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13827 macro_build (NULL
, "nop", "");
13844 offbits
= (mips_opts
.micromips
? 12 : 16);
13850 offbits
= (mips_opts
.micromips
? 12 : 16);
13862 offbits
= (mips_opts
.micromips
? 12 : 16);
13869 offbits
= (mips_opts
.micromips
? 12 : 16);
13875 large_offset
= !small_offset_p (off
, align
, offbits
);
13877 expr1
.X_add_number
= 0;
13882 if (small_offset_p (0, align
, 16))
13883 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13884 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13887 load_address (tempreg
, ep
, &used_at
);
13889 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13890 tempreg
, tempreg
, breg
);
13892 offset_reloc
[0] = BFD_RELOC_LO16
;
13893 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13894 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13899 else if (!ust
&& op
[0] == breg
)
13910 if (!target_big_endian
)
13911 ep
->X_add_number
+= off
;
13913 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13915 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13916 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13918 if (!target_big_endian
)
13919 ep
->X_add_number
-= off
;
13921 ep
->X_add_number
+= off
;
13923 macro_build (NULL
, s2
, "t,~(b)",
13924 tempreg
, (int) ep
->X_add_number
, breg
);
13926 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13927 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13929 /* If necessary, move the result in tempreg to the final destination. */
13930 if (!ust
&& op
[0] != tempreg
)
13932 /* Protect second load's delay slot. */
13934 move_register (op
[0], tempreg
);
13940 if (target_big_endian
== ust
)
13941 ep
->X_add_number
+= off
;
13942 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13943 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13944 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13946 /* For halfword transfers we need a temporary register to shuffle
13947 bytes. Unfortunately for M_USH_A we have none available before
13948 the next store as AT holds the base address. We deal with this
13949 case by clobbering TREG and then restoring it as with ULH. */
13950 tempreg
= ust
== large_offset
? op
[0] : AT
;
13952 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13954 if (target_big_endian
== ust
)
13955 ep
->X_add_number
-= off
;
13957 ep
->X_add_number
+= off
;
13958 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13959 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13961 /* For M_USH_A re-retrieve the LSB. */
13962 if (ust
&& large_offset
)
13964 if (target_big_endian
)
13965 ep
->X_add_number
+= off
;
13967 ep
->X_add_number
-= off
;
13968 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13969 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13971 /* For ULH and M_USH_A OR the LSB in. */
13972 if (!ust
|| large_offset
)
13974 tempreg
= !large_offset
? AT
: op
[0];
13975 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
13976 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13981 /* FIXME: Check if this is one of the itbl macros, since they
13982 are added dynamically. */
13983 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
13986 if (!mips_opts
.at
&& used_at
)
13987 as_bad (_("macro used $at after \".set noat\""));
13990 /* Implement macros in mips16 mode. */
13993 mips16_macro (struct mips_cl_insn
*ip
)
13995 const struct mips_operand_array
*operands
;
14000 const char *s
, *s2
, *s3
;
14001 unsigned int op
[MAX_OPERANDS
];
14004 mask
= ip
->insn_mo
->mask
;
14006 operands
= insn_operands (ip
);
14007 for (i
= 0; i
< MAX_OPERANDS
; i
++)
14008 if (operands
->operand
[i
])
14009 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
14013 expr1
.X_op
= O_constant
;
14014 expr1
.X_op_symbol
= NULL
;
14015 expr1
.X_add_symbol
= NULL
;
14016 expr1
.X_add_number
= 1;
14027 /* Fall through. */
14033 /* Fall through. */
14037 start_noreorder ();
14038 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
14039 expr1
.X_add_number
= 2;
14040 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14041 macro_build (NULL
, "break", "6", 7);
14043 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14044 since that causes an overflow. We should do that as well,
14045 but I don't see how to do the comparisons without a temporary
14048 macro_build (NULL
, s
, "x", op
[0]);
14067 start_noreorder ();
14068 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
14069 expr1
.X_add_number
= 2;
14070 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14071 macro_build (NULL
, "break", "6", 7);
14073 macro_build (NULL
, s2
, "x", op
[0]);
14078 /* Fall through. */
14080 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
14081 macro_build (NULL
, "mflo", "x", op
[0]);
14089 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14090 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14094 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14095 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14099 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14100 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14122 goto do_reverse_branch
;
14126 goto do_reverse_branch
;
14138 goto do_reverse_branch
;
14149 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14150 macro_build (&offset_expr
, s2
, "p");
14177 goto do_addone_branch_i
;
14182 goto do_addone_branch_i
;
14197 goto do_addone_branch_i
;
14203 do_addone_branch_i
:
14204 ++imm_expr
.X_add_number
;
14207 macro_build (&imm_expr
, s
, s3
, op
[0]);
14208 macro_build (&offset_expr
, s2
, "p");
14212 expr1
.X_add_number
= 0;
14213 macro_build (&expr1
, "slti", "x,8", op
[1]);
14214 if (op
[0] != op
[1])
14215 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14216 expr1
.X_add_number
= 2;
14217 macro_build (&expr1
, "bteqz", "p");
14218 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14223 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14224 opcode bits in *OPCODE_EXTRA. */
14226 static struct mips_opcode
*
14227 mips_lookup_insn (struct hash_control
*hash
, const char *start
,
14228 ssize_t length
, unsigned int *opcode_extra
)
14230 char *name
, *dot
, *p
;
14231 unsigned int mask
, suffix
;
14233 struct mips_opcode
*insn
;
14235 /* Make a copy of the instruction so that we can fiddle with it. */
14236 name
= xstrndup (start
, length
);
14238 /* Look up the instruction as-is. */
14239 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14243 dot
= strchr (name
, '.');
14246 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14247 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14248 if (*p
== 0 && mask
!= 0)
14251 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14253 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14255 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14261 if (mips_opts
.micromips
)
14263 /* See if there's an instruction size override suffix,
14264 either `16' or `32', at the end of the mnemonic proper,
14265 that defines the operation, i.e. before the first `.'
14266 character if any. Strip it and retry. */
14267 opend
= dot
!= NULL
? dot
- name
: length
;
14268 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14270 else if (opend
>= 2 && name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14276 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14277 insn
= (struct mips_opcode
*) hash_find (hash
, name
);
14280 forced_insn_length
= suffix
;
14292 /* Assemble an instruction into its binary format. If the instruction
14293 is a macro, set imm_expr and offset_expr to the values associated
14294 with "I" and "A" operands respectively. Otherwise store the value
14295 of the relocatable field (if any) in offset_expr. In both cases
14296 set offset_reloc to the relocation operators applied to offset_expr. */
14299 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14301 const struct mips_opcode
*first
, *past
;
14302 struct hash_control
*hash
;
14305 struct mips_operand_token
*tokens
;
14306 unsigned int opcode_extra
;
14308 if (mips_opts
.micromips
)
14310 hash
= micromips_op_hash
;
14311 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14316 past
= &mips_opcodes
[NUMOPCODES
];
14318 forced_insn_length
= 0;
14321 /* We first try to match an instruction up to a space or to the end. */
14322 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14325 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14328 set_insn_error (0, _("unrecognized opcode"));
14332 if (strcmp (first
->name
, "li.s") == 0)
14334 else if (strcmp (first
->name
, "li.d") == 0)
14338 tokens
= mips_parse_arguments (str
+ end
, format
);
14342 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14343 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14344 set_insn_error (0, _("invalid operands"));
14346 obstack_free (&mips_operand_tokens
, tokens
);
14349 /* As for mips_ip, but used when assembling MIPS16 code.
14350 Also set forced_insn_length to the resulting instruction size in
14351 bytes if the user explicitly requested a small or extended instruction. */
14354 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14357 struct mips_opcode
*first
;
14358 struct mips_operand_token
*tokens
;
14361 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14383 else if (*s
== 'e')
14390 else if (*s
++ == ' ')
14392 set_insn_error (0, _("unrecognized opcode"));
14395 forced_insn_length
= l
;
14398 first
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
);
14403 set_insn_error (0, _("unrecognized opcode"));
14407 tokens
= mips_parse_arguments (s
, 0);
14411 if (!match_mips16_insns (insn
, first
, tokens
))
14412 set_insn_error (0, _("invalid operands"));
14414 obstack_free (&mips_operand_tokens
, tokens
);
14417 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14418 NBITS is the number of significant bits in VAL. */
14420 static unsigned long
14421 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14426 val
&= (1U << nbits
) - 1;
14427 if (nbits
== 16 || nbits
== 9)
14429 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14432 else if (nbits
== 15)
14434 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14437 else if (nbits
== 6)
14439 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14442 return (extval
<< 16) | val
;
14445 /* Like decode_mips16_operand, but require the operand to be defined and
14446 require it to be an integer. */
14448 static const struct mips_int_operand
*
14449 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14451 const struct mips_operand
*operand
;
14453 operand
= decode_mips16_operand (type
, extended_p
);
14454 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14456 return (const struct mips_int_operand
*) operand
;
14459 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14462 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14463 bfd_reloc_code_real_type reloc
, offsetT sval
)
14465 int min_val
, max_val
;
14467 min_val
= mips_int_operand_min (operand
);
14468 max_val
= mips_int_operand_max (operand
);
14469 if (reloc
!= BFD_RELOC_UNUSED
)
14472 sval
= SEXT_16BIT (sval
);
14477 return (sval
>= min_val
14479 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14482 /* Install immediate value VAL into MIPS16 instruction *INSN,
14483 extending it if necessary. The instruction in *INSN may
14484 already be extended.
14486 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14487 if none. In the former case, VAL is a 16-bit number with no
14488 defined signedness.
14490 TYPE is the type of the immediate field. USER_INSN_LENGTH
14491 is the length that the user requested, or 0 if none. */
14494 mips16_immed (const char *file
, unsigned int line
, int type
,
14495 bfd_reloc_code_real_type reloc
, offsetT val
,
14496 unsigned int user_insn_length
, unsigned long *insn
)
14498 const struct mips_int_operand
*operand
;
14499 unsigned int uval
, length
;
14501 operand
= mips16_immed_operand (type
, FALSE
);
14502 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14504 /* We need an extended instruction. */
14505 if (user_insn_length
== 2)
14506 as_bad_where (file
, line
, _("invalid unextended operand value"));
14508 *insn
|= MIPS16_EXTEND
;
14510 else if (user_insn_length
== 4)
14512 /* The operand doesn't force an unextended instruction to be extended.
14513 Warn if the user wanted an extended instruction anyway. */
14514 *insn
|= MIPS16_EXTEND
;
14515 as_warn_where (file
, line
,
14516 _("extended operand requested but not required"));
14519 length
= mips16_opcode_length (*insn
);
14522 operand
= mips16_immed_operand (type
, TRUE
);
14523 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14524 as_bad_where (file
, line
,
14525 _("operand value out of range for instruction"));
14527 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14528 if (length
== 2 || operand
->root
.lsb
!= 0)
14529 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14531 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14534 struct percent_op_match
14537 bfd_reloc_code_real_type reloc
;
14540 static const struct percent_op_match mips_percent_op
[] =
14542 {"%lo", BFD_RELOC_LO16
},
14543 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14544 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14545 {"%call16", BFD_RELOC_MIPS_CALL16
},
14546 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14547 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14548 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14549 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14550 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14551 {"%got", BFD_RELOC_MIPS_GOT16
},
14552 {"%gp_rel", BFD_RELOC_GPREL16
},
14553 {"%gprel", BFD_RELOC_GPREL16
},
14554 {"%half", BFD_RELOC_16
},
14555 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14556 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14557 {"%neg", BFD_RELOC_MIPS_SUB
},
14558 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14559 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14560 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14561 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14562 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14563 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14564 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14565 {"%hi", BFD_RELOC_HI16_S
},
14566 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14567 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14570 static const struct percent_op_match mips16_percent_op
[] =
14572 {"%lo", BFD_RELOC_MIPS16_LO16
},
14573 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14574 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14575 {"%got", BFD_RELOC_MIPS16_GOT16
},
14576 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14577 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14578 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14579 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14580 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14581 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14582 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14583 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14584 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14588 /* Return true if *STR points to a relocation operator. When returning true,
14589 move *STR over the operator and store its relocation code in *RELOC.
14590 Leave both *STR and *RELOC alone when returning false. */
14593 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14595 const struct percent_op_match
*percent_op
;
14598 if (mips_opts
.mips16
)
14600 percent_op
= mips16_percent_op
;
14601 limit
= ARRAY_SIZE (mips16_percent_op
);
14605 percent_op
= mips_percent_op
;
14606 limit
= ARRAY_SIZE (mips_percent_op
);
14609 for (i
= 0; i
< limit
; i
++)
14610 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14612 int len
= strlen (percent_op
[i
].str
);
14614 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14617 *str
+= strlen (percent_op
[i
].str
);
14618 *reloc
= percent_op
[i
].reloc
;
14620 /* Check whether the output BFD supports this relocation.
14621 If not, issue an error and fall back on something safe. */
14622 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14624 as_bad (_("relocation %s isn't supported by the current ABI"),
14625 percent_op
[i
].str
);
14626 *reloc
= BFD_RELOC_UNUSED
;
14634 /* Parse string STR as a 16-bit relocatable operand. Store the
14635 expression in *EP and the relocations in the array starting
14636 at RELOC. Return the number of relocation operators used.
14638 On exit, EXPR_END points to the first character after the expression. */
14641 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14644 bfd_reloc_code_real_type reversed_reloc
[3];
14645 size_t reloc_index
, i
;
14646 int crux_depth
, str_depth
;
14649 /* Search for the start of the main expression, recoding relocations
14650 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14651 of the main expression and with CRUX_DEPTH containing the number
14652 of open brackets at that point. */
14659 crux_depth
= str_depth
;
14661 /* Skip over whitespace and brackets, keeping count of the number
14663 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14668 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14669 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14671 my_getExpression (ep
, crux
);
14674 /* Match every open bracket. */
14675 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14679 if (crux_depth
> 0)
14680 as_bad (_("unclosed '('"));
14684 if (reloc_index
!= 0)
14686 prev_reloc_op_frag
= frag_now
;
14687 for (i
= 0; i
< reloc_index
; i
++)
14688 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14691 return reloc_index
;
14695 my_getExpression (expressionS
*ep
, char *str
)
14699 save_in
= input_line_pointer
;
14700 input_line_pointer
= str
;
14702 expr_end
= input_line_pointer
;
14703 input_line_pointer
= save_in
;
14707 md_atof (int type
, char *litP
, int *sizeP
)
14709 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14713 md_number_to_chars (char *buf
, valueT val
, int n
)
14715 if (target_big_endian
)
14716 number_to_chars_bigendian (buf
, val
, n
);
14718 number_to_chars_littleendian (buf
, val
, n
);
14721 static int support_64bit_objects(void)
14723 const char **list
, **l
;
14726 list
= bfd_target_list ();
14727 for (l
= list
; *l
!= NULL
; l
++)
14728 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14729 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14731 yes
= (*l
!= NULL
);
14736 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14737 NEW_VALUE. Warn if another value was already specified. Note:
14738 we have to defer parsing the -march and -mtune arguments in order
14739 to handle 'from-abi' correctly, since the ABI might be specified
14740 in a later argument. */
14743 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14745 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14746 as_warn (_("a different %s was already specified, is now %s"),
14747 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14750 *string_ptr
= new_value
;
14754 md_parse_option (int c
, const char *arg
)
14758 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14759 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14761 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14762 c
== mips_ases
[i
].option_on
);
14768 case OPTION_CONSTRUCT_FLOATS
:
14769 mips_disable_float_construction
= 0;
14772 case OPTION_NO_CONSTRUCT_FLOATS
:
14773 mips_disable_float_construction
= 1;
14785 target_big_endian
= 1;
14789 target_big_endian
= 0;
14795 else if (arg
[0] == '0')
14797 else if (arg
[0] == '1')
14807 mips_debug
= atoi (arg
);
14811 file_mips_opts
.isa
= ISA_MIPS1
;
14815 file_mips_opts
.isa
= ISA_MIPS2
;
14819 file_mips_opts
.isa
= ISA_MIPS3
;
14823 file_mips_opts
.isa
= ISA_MIPS4
;
14827 file_mips_opts
.isa
= ISA_MIPS5
;
14830 case OPTION_MIPS32
:
14831 file_mips_opts
.isa
= ISA_MIPS32
;
14834 case OPTION_MIPS32R2
:
14835 file_mips_opts
.isa
= ISA_MIPS32R2
;
14838 case OPTION_MIPS32R3
:
14839 file_mips_opts
.isa
= ISA_MIPS32R3
;
14842 case OPTION_MIPS32R5
:
14843 file_mips_opts
.isa
= ISA_MIPS32R5
;
14846 case OPTION_MIPS32R6
:
14847 file_mips_opts
.isa
= ISA_MIPS32R6
;
14850 case OPTION_MIPS64R2
:
14851 file_mips_opts
.isa
= ISA_MIPS64R2
;
14854 case OPTION_MIPS64R3
:
14855 file_mips_opts
.isa
= ISA_MIPS64R3
;
14858 case OPTION_MIPS64R5
:
14859 file_mips_opts
.isa
= ISA_MIPS64R5
;
14862 case OPTION_MIPS64R6
:
14863 file_mips_opts
.isa
= ISA_MIPS64R6
;
14866 case OPTION_MIPS64
:
14867 file_mips_opts
.isa
= ISA_MIPS64
;
14871 mips_set_option_string (&mips_tune_string
, arg
);
14875 mips_set_option_string (&mips_arch_string
, arg
);
14879 mips_set_option_string (&mips_arch_string
, "4650");
14880 mips_set_option_string (&mips_tune_string
, "4650");
14883 case OPTION_NO_M4650
:
14887 mips_set_option_string (&mips_arch_string
, "4010");
14888 mips_set_option_string (&mips_tune_string
, "4010");
14891 case OPTION_NO_M4010
:
14895 mips_set_option_string (&mips_arch_string
, "4100");
14896 mips_set_option_string (&mips_tune_string
, "4100");
14899 case OPTION_NO_M4100
:
14903 mips_set_option_string (&mips_arch_string
, "3900");
14904 mips_set_option_string (&mips_tune_string
, "3900");
14907 case OPTION_NO_M3900
:
14910 case OPTION_MICROMIPS
:
14911 if (file_mips_opts
.mips16
== 1)
14913 as_bad (_("-mmicromips cannot be used with -mips16"));
14916 file_mips_opts
.micromips
= 1;
14917 mips_no_prev_insn ();
14920 case OPTION_NO_MICROMIPS
:
14921 file_mips_opts
.micromips
= 0;
14922 mips_no_prev_insn ();
14925 case OPTION_MIPS16
:
14926 if (file_mips_opts
.micromips
== 1)
14928 as_bad (_("-mips16 cannot be used with -micromips"));
14931 file_mips_opts
.mips16
= 1;
14932 mips_no_prev_insn ();
14935 case OPTION_NO_MIPS16
:
14936 file_mips_opts
.mips16
= 0;
14937 mips_no_prev_insn ();
14940 case OPTION_FIX_24K
:
14944 case OPTION_NO_FIX_24K
:
14948 case OPTION_FIX_RM7000
:
14949 mips_fix_rm7000
= 1;
14952 case OPTION_NO_FIX_RM7000
:
14953 mips_fix_rm7000
= 0;
14956 case OPTION_FIX_LOONGSON3_LLSC
:
14957 mips_fix_loongson3_llsc
= TRUE
;
14960 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14961 mips_fix_loongson3_llsc
= FALSE
;
14964 case OPTION_FIX_LOONGSON2F_JUMP
:
14965 mips_fix_loongson2f_jump
= TRUE
;
14968 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14969 mips_fix_loongson2f_jump
= FALSE
;
14972 case OPTION_FIX_LOONGSON2F_NOP
:
14973 mips_fix_loongson2f_nop
= TRUE
;
14976 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14977 mips_fix_loongson2f_nop
= FALSE
;
14980 case OPTION_FIX_VR4120
:
14981 mips_fix_vr4120
= 1;
14984 case OPTION_NO_FIX_VR4120
:
14985 mips_fix_vr4120
= 0;
14988 case OPTION_FIX_VR4130
:
14989 mips_fix_vr4130
= 1;
14992 case OPTION_NO_FIX_VR4130
:
14993 mips_fix_vr4130
= 0;
14996 case OPTION_FIX_CN63XXP1
:
14997 mips_fix_cn63xxp1
= TRUE
;
15000 case OPTION_NO_FIX_CN63XXP1
:
15001 mips_fix_cn63xxp1
= FALSE
;
15004 case OPTION_FIX_R5900
:
15005 mips_fix_r5900
= TRUE
;
15006 mips_fix_r5900_explicit
= TRUE
;
15009 case OPTION_NO_FIX_R5900
:
15010 mips_fix_r5900
= FALSE
;
15011 mips_fix_r5900_explicit
= TRUE
;
15014 case OPTION_RELAX_BRANCH
:
15015 mips_relax_branch
= 1;
15018 case OPTION_NO_RELAX_BRANCH
:
15019 mips_relax_branch
= 0;
15022 case OPTION_IGNORE_BRANCH_ISA
:
15023 mips_ignore_branch_isa
= TRUE
;
15026 case OPTION_NO_IGNORE_BRANCH_ISA
:
15027 mips_ignore_branch_isa
= FALSE
;
15030 case OPTION_INSN32
:
15031 file_mips_opts
.insn32
= TRUE
;
15034 case OPTION_NO_INSN32
:
15035 file_mips_opts
.insn32
= FALSE
;
15038 case OPTION_MSHARED
:
15039 mips_in_shared
= TRUE
;
15042 case OPTION_MNO_SHARED
:
15043 mips_in_shared
= FALSE
;
15046 case OPTION_MSYM32
:
15047 file_mips_opts
.sym32
= TRUE
;
15050 case OPTION_MNO_SYM32
:
15051 file_mips_opts
.sym32
= FALSE
;
15054 /* When generating ELF code, we permit -KPIC and -call_shared to
15055 select SVR4_PIC, and -non_shared to select no PIC. This is
15056 intended to be compatible with Irix 5. */
15057 case OPTION_CALL_SHARED
:
15058 mips_pic
= SVR4_PIC
;
15059 mips_abicalls
= TRUE
;
15062 case OPTION_CALL_NONPIC
:
15064 mips_abicalls
= TRUE
;
15067 case OPTION_NON_SHARED
:
15069 mips_abicalls
= FALSE
;
15072 /* The -xgot option tells the assembler to use 32 bit offsets
15073 when accessing the got in SVR4_PIC mode. It is for Irix
15080 g_switch_value
= atoi (arg
);
15084 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15087 mips_abi
= O32_ABI
;
15091 mips_abi
= N32_ABI
;
15095 mips_abi
= N64_ABI
;
15096 if (!support_64bit_objects())
15097 as_fatal (_("no compiled in support for 64 bit object file format"));
15101 file_mips_opts
.gp
= 32;
15105 file_mips_opts
.gp
= 64;
15109 file_mips_opts
.fp
= 32;
15113 file_mips_opts
.fp
= 0;
15117 file_mips_opts
.fp
= 64;
15120 case OPTION_ODD_SPREG
:
15121 file_mips_opts
.oddspreg
= 1;
15124 case OPTION_NO_ODD_SPREG
:
15125 file_mips_opts
.oddspreg
= 0;
15128 case OPTION_SINGLE_FLOAT
:
15129 file_mips_opts
.single_float
= 1;
15132 case OPTION_DOUBLE_FLOAT
:
15133 file_mips_opts
.single_float
= 0;
15136 case OPTION_SOFT_FLOAT
:
15137 file_mips_opts
.soft_float
= 1;
15140 case OPTION_HARD_FLOAT
:
15141 file_mips_opts
.soft_float
= 0;
15145 if (strcmp (arg
, "32") == 0)
15146 mips_abi
= O32_ABI
;
15147 else if (strcmp (arg
, "o64") == 0)
15148 mips_abi
= O64_ABI
;
15149 else if (strcmp (arg
, "n32") == 0)
15150 mips_abi
= N32_ABI
;
15151 else if (strcmp (arg
, "64") == 0)
15153 mips_abi
= N64_ABI
;
15154 if (! support_64bit_objects())
15155 as_fatal (_("no compiled in support for 64 bit object file "
15158 else if (strcmp (arg
, "eabi") == 0)
15159 mips_abi
= EABI_ABI
;
15162 as_fatal (_("invalid abi -mabi=%s"), arg
);
15167 case OPTION_M7000_HILO_FIX
:
15168 mips_7000_hilo_fix
= TRUE
;
15171 case OPTION_MNO_7000_HILO_FIX
:
15172 mips_7000_hilo_fix
= FALSE
;
15175 case OPTION_MDEBUG
:
15176 mips_flag_mdebug
= TRUE
;
15179 case OPTION_NO_MDEBUG
:
15180 mips_flag_mdebug
= FALSE
;
15184 mips_flag_pdr
= TRUE
;
15187 case OPTION_NO_PDR
:
15188 mips_flag_pdr
= FALSE
;
15191 case OPTION_MVXWORKS_PIC
:
15192 mips_pic
= VXWORKS_PIC
;
15196 if (strcmp (arg
, "2008") == 0)
15198 else if (strcmp (arg
, "legacy") == 0)
15202 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15211 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15216 /* Set up globals to tune for the ISA or processor described by INFO. */
15219 mips_set_tune (const struct mips_cpu_info
*info
)
15222 mips_tune
= info
->cpu
;
15227 mips_after_parse_args (void)
15229 const struct mips_cpu_info
*arch_info
= 0;
15230 const struct mips_cpu_info
*tune_info
= 0;
15232 /* GP relative stuff not working for PE. */
15233 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15235 if (g_switch_seen
&& g_switch_value
!= 0)
15236 as_bad (_("-G not supported in this configuration"));
15237 g_switch_value
= 0;
15240 if (mips_abi
== NO_ABI
)
15241 mips_abi
= MIPS_DEFAULT_ABI
;
15243 /* The following code determines the architecture.
15244 Similar code was added to GCC 3.3 (see override_options() in
15245 config/mips/mips.c). The GAS and GCC code should be kept in sync
15246 as much as possible. */
15248 if (mips_arch_string
!= 0)
15249 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15251 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15253 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15254 ISA level specified by -mipsN, while arch_info->isa contains
15255 the -march selection (if any). */
15256 if (arch_info
!= 0)
15258 /* -march takes precedence over -mipsN, since it is more descriptive.
15259 There's no harm in specifying both as long as the ISA levels
15261 if (file_mips_opts
.isa
!= arch_info
->isa
)
15262 as_bad (_("-%s conflicts with the other architecture options,"
15263 " which imply -%s"),
15264 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15265 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15268 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15271 if (arch_info
== 0)
15273 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15274 gas_assert (arch_info
);
15277 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15278 as_bad (_("-march=%s is not compatible with the selected ABI"),
15281 file_mips_opts
.arch
= arch_info
->cpu
;
15282 file_mips_opts
.isa
= arch_info
->isa
;
15283 file_mips_opts
.init_ase
= arch_info
->ase
;
15285 /* The EVA Extension has instructions which are only valid when the R6 ISA
15286 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15288 if (((file_mips_opts
.ase
& ASE_EVA
) != 0) && ISA_IS_R6 (file_mips_opts
.isa
))
15289 file_mips_opts
.ase
|= ASE_EVA_R6
;
15291 /* Set up initial mips_opts state. */
15292 mips_opts
= file_mips_opts
;
15294 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15295 if (!mips_fix_r5900_explicit
)
15296 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15298 /* The register size inference code is now placed in
15299 file_mips_check_options. */
15301 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15303 if (mips_tune_string
!= 0)
15304 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15306 if (tune_info
== 0)
15307 mips_set_tune (arch_info
);
15309 mips_set_tune (tune_info
);
15311 if (mips_flag_mdebug
< 0)
15312 mips_flag_mdebug
= 0;
15316 mips_init_after_args (void)
15318 /* Initialize opcodes. */
15319 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15320 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15324 md_pcrel_from (fixS
*fixP
)
15326 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15328 switch (fixP
->fx_r_type
)
15330 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15331 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15332 /* Return the address of the delay slot. */
15335 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15336 case BFD_RELOC_MICROMIPS_JMP
:
15337 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15338 case BFD_RELOC_16_PCREL_S2
:
15339 case BFD_RELOC_MIPS_21_PCREL_S2
:
15340 case BFD_RELOC_MIPS_26_PCREL_S2
:
15341 case BFD_RELOC_MIPS_JMP
:
15342 /* Return the address of the delay slot. */
15345 case BFD_RELOC_MIPS_18_PCREL_S3
:
15346 /* Return the aligned address of the doubleword containing
15347 the instruction. */
15355 /* This is called before the symbol table is processed. In order to
15356 work with gcc when using mips-tfile, we must keep all local labels.
15357 However, in other cases, we want to discard them. If we were
15358 called with -g, but we didn't see any debugging information, it may
15359 mean that gcc is smuggling debugging information through to
15360 mips-tfile, in which case we must generate all local labels. */
15363 mips_frob_file_before_adjust (void)
15365 #ifndef NO_ECOFF_DEBUGGING
15366 if (ECOFF_DEBUGGING
15368 && ! ecoff_debugging_seen
)
15369 flag_keep_locals
= 1;
15373 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15374 the corresponding LO16 reloc. This is called before md_apply_fix and
15375 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15376 relocation operators.
15378 For our purposes, a %lo() expression matches a %got() or %hi()
15381 (a) it refers to the same symbol; and
15382 (b) the offset applied in the %lo() expression is no lower than
15383 the offset applied in the %got() or %hi().
15385 (b) allows us to cope with code like:
15388 lh $4,%lo(foo+2)($4)
15390 ...which is legal on RELA targets, and has a well-defined behaviour
15391 if the user knows that adding 2 to "foo" will not induce a carry to
15394 When several %lo()s match a particular %got() or %hi(), we use the
15395 following rules to distinguish them:
15397 (1) %lo()s with smaller offsets are a better match than %lo()s with
15400 (2) %lo()s with no matching %got() or %hi() are better than those
15401 that already have a matching %got() or %hi().
15403 (3) later %lo()s are better than earlier %lo()s.
15405 These rules are applied in order.
15407 (1) means, among other things, that %lo()s with identical offsets are
15408 chosen if they exist.
15410 (2) means that we won't associate several high-part relocations with
15411 the same low-part relocation unless there's no alternative. Having
15412 several high parts for the same low part is a GNU extension; this rule
15413 allows careful users to avoid it.
15415 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15416 with the last high-part relocation being at the front of the list.
15417 It therefore makes sense to choose the last matching low-part
15418 relocation, all other things being equal. It's also easier
15419 to code that way. */
15422 mips_frob_file (void)
15424 struct mips_hi_fixup
*l
;
15425 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15427 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15429 segment_info_type
*seginfo
;
15430 bfd_boolean matched_lo_p
;
15431 fixS
**hi_pos
, **lo_pos
, **pos
;
15433 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15435 /* If a GOT16 relocation turns out to be against a global symbol,
15436 there isn't supposed to be a matching LO. Ignore %gots against
15437 constants; we'll report an error for those later. */
15438 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15439 && !(l
->fixp
->fx_addsy
15440 && pic_need_relax (l
->fixp
->fx_addsy
)))
15443 /* Check quickly whether the next fixup happens to be a matching %lo. */
15444 if (fixup_has_matching_lo_p (l
->fixp
))
15447 seginfo
= seg_info (l
->seg
);
15449 /* Set HI_POS to the position of this relocation in the chain.
15450 Set LO_POS to the position of the chosen low-part relocation.
15451 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15452 relocation that matches an immediately-preceding high-part
15456 matched_lo_p
= FALSE
;
15457 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15459 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15461 if (*pos
== l
->fixp
)
15464 if ((*pos
)->fx_r_type
== looking_for_rtype
15465 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15466 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15468 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15470 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15473 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15474 && fixup_has_matching_lo_p (*pos
));
15477 /* If we found a match, remove the high-part relocation from its
15478 current position and insert it before the low-part relocation.
15479 Make the offsets match so that fixup_has_matching_lo_p()
15482 We don't warn about unmatched high-part relocations since some
15483 versions of gcc have been known to emit dead "lui ...%hi(...)"
15485 if (lo_pos
!= NULL
)
15487 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15488 if (l
->fixp
->fx_next
!= *lo_pos
)
15490 *hi_pos
= l
->fixp
->fx_next
;
15491 l
->fixp
->fx_next
= *lo_pos
;
15499 mips_force_relocation (fixS
*fixp
)
15501 if (generic_force_reloc (fixp
))
15504 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15505 so that the linker relaxation can update targets. */
15506 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15507 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15508 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15511 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15512 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15513 microMIPS symbols so that we can do cross-mode branch diagnostics
15514 and BAL to JALX conversion by the linker. */
15515 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15516 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15517 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15519 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15522 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15523 if (ISA_IS_R6 (file_mips_opts
.isa
)
15524 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15525 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15526 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15527 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15528 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15529 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15530 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15536 /* Implement TC_FORCE_RELOCATION_ABS. */
15539 mips_force_relocation_abs (fixS
*fixp
)
15541 if (generic_force_reloc (fixp
))
15544 /* These relocations do not have enough bits in the in-place addend
15545 to hold an arbitrary absolute section's offset. */
15546 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15552 /* Read the instruction associated with RELOC from BUF. */
15554 static unsigned int
15555 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15557 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15558 return read_compressed_insn (buf
, 4);
15560 return read_insn (buf
);
15563 /* Write instruction INSN to BUF, given that it has been relocated
15567 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15568 unsigned long insn
)
15570 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15571 write_compressed_insn (buf
, insn
, 4);
15573 write_insn (buf
, insn
);
15576 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15577 to a symbol in another ISA mode, which cannot be converted to JALX. */
15580 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15582 unsigned long opcode
;
15586 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15589 other
= S_GET_OTHER (fixP
->fx_addsy
);
15590 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15591 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15592 switch (fixP
->fx_r_type
)
15594 case BFD_RELOC_MIPS_JMP
:
15595 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15596 case BFD_RELOC_MICROMIPS_JMP
:
15597 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15603 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15604 jump to a symbol in the same ISA mode. */
15607 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15609 unsigned long opcode
;
15613 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15616 other
= S_GET_OTHER (fixP
->fx_addsy
);
15617 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15618 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15619 switch (fixP
->fx_r_type
)
15621 case BFD_RELOC_MIPS_JMP
:
15622 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15623 case BFD_RELOC_MIPS16_JMP
:
15624 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15625 case BFD_RELOC_MICROMIPS_JMP
:
15626 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15632 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15633 to a symbol whose value plus addend is not aligned according to the
15634 ultimate (after linker relaxation) jump instruction's immediate field
15635 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15636 regular MIPS code, to (1 << 2). */
15639 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15641 bfd_boolean micro_to_mips_p
;
15645 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15648 other
= S_GET_OTHER (fixP
->fx_addsy
);
15649 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15650 val
+= fixP
->fx_offset
;
15651 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15652 && !ELF_ST_IS_MICROMIPS (other
));
15653 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15654 != ELF_ST_IS_COMPRESSED (other
));
15657 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15658 to a symbol whose annotation indicates another ISA mode. For absolute
15659 symbols check the ISA bit instead.
15661 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15662 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15663 MIPS symbols and associated with BAL instructions as these instructions
15664 may be converted to JALX by the linker. */
15667 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15669 bfd_boolean absolute_p
;
15670 unsigned long opcode
;
15676 if (mips_ignore_branch_isa
)
15679 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15682 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15683 absolute_p
= bfd_is_abs_section (symsec
);
15685 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15686 other
= S_GET_OTHER (fixP
->fx_addsy
);
15688 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15689 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15690 switch (fixP
->fx_r_type
)
15692 case BFD_RELOC_16_PCREL_S2
:
15693 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15694 && opcode
!= 0x0411);
15695 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15696 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15697 && opcode
!= 0x4060);
15698 case BFD_RELOC_MIPS_21_PCREL_S2
:
15699 case BFD_RELOC_MIPS_26_PCREL_S2
:
15700 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15701 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15702 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15703 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15704 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15705 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15711 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15712 branch instruction pointed to by FIXP is not aligned according to the
15713 branch instruction's immediate field requirement. We need the addend
15714 to preserve the ISA bit and also the sum must not have bit 2 set. We
15715 must explicitly OR in the ISA bit from symbol annotation as the bit
15716 won't be set in the symbol's value then. */
15719 fix_bad_misaligned_branch_p (fixS
*fixP
)
15721 bfd_boolean absolute_p
;
15728 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15731 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15732 absolute_p
= bfd_is_abs_section (symsec
);
15734 val
= S_GET_VALUE (fixP
->fx_addsy
);
15735 other
= S_GET_OTHER (fixP
->fx_addsy
);
15736 off
= fixP
->fx_offset
;
15738 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15739 val
|= ELF_ST_IS_COMPRESSED (other
);
15741 return (val
& 0x3) != isa_bit
;
15744 /* Calculate the relocation target by masking off ISA mode bit before
15745 combining symbol and addend. */
15748 fix_bad_misaligned_address (fixS
*fixP
)
15753 gas_assert (fixP
!= NULL
&& fixP
->fx_addsy
!= NULL
);
15754 val
= S_GET_VALUE (fixP
->fx_addsy
);
15755 off
= fixP
->fx_offset
;
15756 isa_mode
= (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP
->fx_addsy
))
15759 return ((val
& ~isa_mode
) + off
);
15762 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15763 and its calculated value VAL. */
15766 fix_validate_branch (fixS
*fixP
, valueT val
)
15768 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15770 _("branch to misaligned address (0x%lx)"),
15771 (long) (val
+ md_pcrel_from (fixP
)));
15772 else if (fix_bad_cross_mode_branch_p (fixP
))
15773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15774 _("branch to a symbol in another ISA mode"));
15775 else if (fix_bad_misaligned_branch_p (fixP
))
15776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15777 _("branch to misaligned address (0x%lx)"),
15778 (long) fix_bad_misaligned_address (fixP
));
15779 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15780 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15781 _("cannot encode misaligned addend "
15782 "in the relocatable field (0x%lx)"),
15783 (long) fixP
->fx_offset
);
15786 /* Apply a fixup to the object file. */
15789 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15792 unsigned long insn
;
15793 reloc_howto_type
*howto
;
15795 if (fixP
->fx_pcrel
)
15796 switch (fixP
->fx_r_type
)
15798 case BFD_RELOC_16_PCREL_S2
:
15799 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15800 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15801 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15802 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15803 case BFD_RELOC_32_PCREL
:
15804 case BFD_RELOC_MIPS_21_PCREL_S2
:
15805 case BFD_RELOC_MIPS_26_PCREL_S2
:
15806 case BFD_RELOC_MIPS_18_PCREL_S3
:
15807 case BFD_RELOC_MIPS_19_PCREL_S2
:
15808 case BFD_RELOC_HI16_S_PCREL
:
15809 case BFD_RELOC_LO16_PCREL
:
15813 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15818 _("PC-relative reference to a different section"));
15822 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15823 that have no MIPS ELF equivalent. */
15824 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15826 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15831 gas_assert (fixP
->fx_size
== 2
15832 || fixP
->fx_size
== 4
15833 || fixP
->fx_r_type
== BFD_RELOC_8
15834 || fixP
->fx_r_type
== BFD_RELOC_16
15835 || fixP
->fx_r_type
== BFD_RELOC_64
15836 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15837 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15838 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15839 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15840 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15841 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15842 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15844 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15846 /* Don't treat parts of a composite relocation as done. There are two
15849 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15850 should nevertheless be emitted if the first part is.
15852 (2) In normal usage, composite relocations are never assembly-time
15853 constants. The easiest way of dealing with the pathological
15854 exceptions is to generate a relocation against STN_UNDEF and
15855 leave everything up to the linker. */
15856 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15859 switch (fixP
->fx_r_type
)
15861 case BFD_RELOC_MIPS_TLS_GD
:
15862 case BFD_RELOC_MIPS_TLS_LDM
:
15863 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15864 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15865 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15866 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15867 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15868 case BFD_RELOC_MIPS_TLS_TPREL32
:
15869 case BFD_RELOC_MIPS_TLS_TPREL64
:
15870 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15871 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15872 case BFD_RELOC_MICROMIPS_TLS_GD
:
15873 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15874 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15875 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15876 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15877 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15878 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15879 case BFD_RELOC_MIPS16_TLS_GD
:
15880 case BFD_RELOC_MIPS16_TLS_LDM
:
15881 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15882 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15883 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15884 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15885 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15886 if (fixP
->fx_addsy
)
15887 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15890 _("TLS relocation against a constant"));
15893 case BFD_RELOC_MIPS_JMP
:
15894 case BFD_RELOC_MIPS16_JMP
:
15895 case BFD_RELOC_MICROMIPS_JMP
:
15899 gas_assert (!fixP
->fx_done
);
15901 /* Shift is 2, unusually, for microMIPS JALX. */
15902 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15903 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15908 if (fix_bad_cross_mode_jump_p (fixP
))
15909 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15910 _("jump to a symbol in another ISA mode"));
15911 else if (fix_bad_same_mode_jalx_p (fixP
))
15912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15913 _("JALX to a symbol in the same ISA mode"));
15914 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15915 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15916 _("jump to misaligned address (0x%lx)"),
15917 (long) fix_bad_misaligned_address (fixP
));
15918 else if (HAVE_IN_PLACE_ADDENDS
15919 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15921 _("cannot encode misaligned addend "
15922 "in the relocatable field (0x%lx)"),
15923 (long) fixP
->fx_offset
);
15925 /* Fall through. */
15927 case BFD_RELOC_MIPS_SHIFT5
:
15928 case BFD_RELOC_MIPS_SHIFT6
:
15929 case BFD_RELOC_MIPS_GOT_DISP
:
15930 case BFD_RELOC_MIPS_GOT_PAGE
:
15931 case BFD_RELOC_MIPS_GOT_OFST
:
15932 case BFD_RELOC_MIPS_SUB
:
15933 case BFD_RELOC_MIPS_INSERT_A
:
15934 case BFD_RELOC_MIPS_INSERT_B
:
15935 case BFD_RELOC_MIPS_DELETE
:
15936 case BFD_RELOC_MIPS_HIGHEST
:
15937 case BFD_RELOC_MIPS_HIGHER
:
15938 case BFD_RELOC_MIPS_SCN_DISP
:
15939 case BFD_RELOC_MIPS_REL16
:
15940 case BFD_RELOC_MIPS_RELGOT
:
15941 case BFD_RELOC_MIPS_JALR
:
15942 case BFD_RELOC_HI16
:
15943 case BFD_RELOC_HI16_S
:
15944 case BFD_RELOC_LO16
:
15945 case BFD_RELOC_GPREL16
:
15946 case BFD_RELOC_MIPS_LITERAL
:
15947 case BFD_RELOC_MIPS_CALL16
:
15948 case BFD_RELOC_MIPS_GOT16
:
15949 case BFD_RELOC_GPREL32
:
15950 case BFD_RELOC_MIPS_GOT_HI16
:
15951 case BFD_RELOC_MIPS_GOT_LO16
:
15952 case BFD_RELOC_MIPS_CALL_HI16
:
15953 case BFD_RELOC_MIPS_CALL_LO16
:
15954 case BFD_RELOC_HI16_S_PCREL
:
15955 case BFD_RELOC_LO16_PCREL
:
15956 case BFD_RELOC_MIPS16_GPREL
:
15957 case BFD_RELOC_MIPS16_GOT16
:
15958 case BFD_RELOC_MIPS16_CALL16
:
15959 case BFD_RELOC_MIPS16_HI16
:
15960 case BFD_RELOC_MIPS16_HI16_S
:
15961 case BFD_RELOC_MIPS16_LO16
:
15962 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15963 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15964 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15965 case BFD_RELOC_MICROMIPS_SUB
:
15966 case BFD_RELOC_MICROMIPS_HIGHEST
:
15967 case BFD_RELOC_MICROMIPS_HIGHER
:
15968 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15969 case BFD_RELOC_MICROMIPS_JALR
:
15970 case BFD_RELOC_MICROMIPS_HI16
:
15971 case BFD_RELOC_MICROMIPS_HI16_S
:
15972 case BFD_RELOC_MICROMIPS_LO16
:
15973 case BFD_RELOC_MICROMIPS_GPREL16
:
15974 case BFD_RELOC_MICROMIPS_LITERAL
:
15975 case BFD_RELOC_MICROMIPS_CALL16
:
15976 case BFD_RELOC_MICROMIPS_GOT16
:
15977 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15978 case BFD_RELOC_MICROMIPS_GOT_LO16
:
15979 case BFD_RELOC_MICROMIPS_CALL_HI16
:
15980 case BFD_RELOC_MICROMIPS_CALL_LO16
:
15981 case BFD_RELOC_MIPS_EH
:
15986 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
15988 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
15989 if (mips16_reloc_p (fixP
->fx_r_type
))
15990 insn
|= mips16_immed_extend (value
, 16);
15992 insn
|= (value
& 0xffff);
15993 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
15996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15997 _("unsupported constant in relocation"));
16002 /* This is handled like BFD_RELOC_32, but we output a sign
16003 extended value if we are only 32 bits. */
16006 if (8 <= sizeof (valueT
))
16007 md_number_to_chars (buf
, *valP
, 8);
16012 if ((*valP
& 0x80000000) != 0)
16016 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16017 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16022 case BFD_RELOC_RVA
:
16024 case BFD_RELOC_32_PCREL
:
16027 /* If we are deleting this reloc entry, we must fill in the
16028 value now. This can happen if we have a .word which is not
16029 resolved when it appears but is later defined. */
16031 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16034 case BFD_RELOC_MIPS_21_PCREL_S2
:
16035 fix_validate_branch (fixP
, *valP
);
16036 if (!fixP
->fx_done
)
16039 if (*valP
+ 0x400000 <= 0x7fffff)
16041 insn
= read_insn (buf
);
16042 insn
|= (*valP
>> 2) & 0x1fffff;
16043 write_insn (buf
, insn
);
16046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16047 _("branch out of range"));
16050 case BFD_RELOC_MIPS_26_PCREL_S2
:
16051 fix_validate_branch (fixP
, *valP
);
16052 if (!fixP
->fx_done
)
16055 if (*valP
+ 0x8000000 <= 0xfffffff)
16057 insn
= read_insn (buf
);
16058 insn
|= (*valP
>> 2) & 0x3ffffff;
16059 write_insn (buf
, insn
);
16062 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16063 _("branch out of range"));
16066 case BFD_RELOC_MIPS_18_PCREL_S3
:
16067 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
16068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16069 _("PC-relative access using misaligned symbol (%lx)"),
16070 (long) S_GET_VALUE (fixP
->fx_addsy
));
16071 if ((fixP
->fx_offset
& 0x7) != 0)
16072 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16073 _("PC-relative access using misaligned offset (%lx)"),
16074 (long) fixP
->fx_offset
);
16075 if (!fixP
->fx_done
)
16078 if (*valP
+ 0x100000 <= 0x1fffff)
16080 insn
= read_insn (buf
);
16081 insn
|= (*valP
>> 3) & 0x3ffff;
16082 write_insn (buf
, insn
);
16085 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16086 _("PC-relative access out of range"));
16089 case BFD_RELOC_MIPS_19_PCREL_S2
:
16090 if ((*valP
& 0x3) != 0)
16091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16092 _("PC-relative access to misaligned address (%lx)"),
16094 if (!fixP
->fx_done
)
16097 if (*valP
+ 0x100000 <= 0x1fffff)
16099 insn
= read_insn (buf
);
16100 insn
|= (*valP
>> 2) & 0x7ffff;
16101 write_insn (buf
, insn
);
16104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16105 _("PC-relative access out of range"));
16108 case BFD_RELOC_16_PCREL_S2
:
16109 fix_validate_branch (fixP
, *valP
);
16111 /* We need to save the bits in the instruction since fixup_segment()
16112 might be deleting the relocation entry (i.e., a branch within
16113 the current segment). */
16114 if (! fixP
->fx_done
)
16117 /* Update old instruction data. */
16118 insn
= read_insn (buf
);
16120 if (*valP
+ 0x20000 <= 0x3ffff)
16122 insn
|= (*valP
>> 2) & 0xffff;
16123 write_insn (buf
, insn
);
16125 else if (fixP
->fx_tcbit2
16127 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16128 && (fixP
->fx_frag
->fr_address
16129 < text_section
->vma
+ bfd_section_size (text_section
))
16130 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16131 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16132 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16134 /* The branch offset is too large. If this is an
16135 unconditional branch, and we are not generating PIC code,
16136 we can convert it to an absolute jump instruction. */
16137 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16138 insn
= 0x0c000000; /* jal */
16140 insn
= 0x08000000; /* j */
16141 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16143 fixP
->fx_addsy
= section_symbol (text_section
);
16144 *valP
+= md_pcrel_from (fixP
);
16145 write_insn (buf
, insn
);
16149 /* If we got here, we have branch-relaxation disabled,
16150 and there's nothing we can do to fix this instruction
16151 without turning it into a longer sequence. */
16152 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16153 _("branch out of range"));
16157 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16158 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16159 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16160 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16161 gas_assert (!fixP
->fx_done
);
16162 if (fix_bad_cross_mode_branch_p (fixP
))
16163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16164 _("branch to a symbol in another ISA mode"));
16165 else if (fixP
->fx_addsy
16166 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16167 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16168 && (fixP
->fx_offset
& 0x1) != 0)
16169 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16170 _("branch to misaligned address (0x%lx)"),
16171 (long) fix_bad_misaligned_address (fixP
));
16172 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16174 _("cannot encode misaligned addend "
16175 "in the relocatable field (0x%lx)"),
16176 (long) fixP
->fx_offset
);
16179 case BFD_RELOC_VTABLE_INHERIT
:
16182 && !S_IS_DEFINED (fixP
->fx_addsy
)
16183 && !S_IS_WEAK (fixP
->fx_addsy
))
16184 S_SET_WEAK (fixP
->fx_addsy
);
16187 case BFD_RELOC_NONE
:
16188 case BFD_RELOC_VTABLE_ENTRY
:
16196 /* Remember value for tc_gen_reloc. */
16197 fixP
->fx_addnumber
= *valP
;
16207 c
= get_symbol_name (&name
);
16208 p
= (symbolS
*) symbol_find_or_make (name
);
16209 (void) restore_line_pointer (c
);
16213 /* Align the current frag to a given power of two. If a particular
16214 fill byte should be used, FILL points to an integer that contains
16215 that byte, otherwise FILL is null.
16217 This function used to have the comment:
16219 The MIPS assembler also automatically adjusts any preceding label.
16221 The implementation therefore applied the adjustment to a maximum of
16222 one label. However, other label adjustments are applied to batches
16223 of labels, and adjusting just one caused problems when new labels
16224 were added for the sake of debugging or unwind information.
16225 We therefore adjust all preceding labels (given as LABELS) instead. */
16228 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16230 mips_emit_delays ();
16231 mips_record_compressed_mode ();
16232 if (fill
== NULL
&& subseg_text_p (now_seg
))
16233 frag_align_code (to
, 0);
16235 frag_align (to
, fill
? *fill
: 0, 0);
16236 record_alignment (now_seg
, to
);
16237 mips_move_labels (labels
, subseg_text_p (now_seg
));
16240 /* Align to a given power of two. .align 0 turns off the automatic
16241 alignment used by the data creating pseudo-ops. */
16244 s_align (int x ATTRIBUTE_UNUSED
)
16246 int temp
, fill_value
, *fill_ptr
;
16247 long max_alignment
= 28;
16249 /* o Note that the assembler pulls down any immediately preceding label
16250 to the aligned address.
16251 o It's not documented but auto alignment is reinstated by
16252 a .align pseudo instruction.
16253 o Note also that after auto alignment is turned off the mips assembler
16254 issues an error on attempt to assemble an improperly aligned data item.
16257 temp
= get_absolute_expression ();
16258 if (temp
> max_alignment
)
16259 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16262 as_warn (_("alignment negative, 0 assumed"));
16265 if (*input_line_pointer
== ',')
16267 ++input_line_pointer
;
16268 fill_value
= get_absolute_expression ();
16269 fill_ptr
= &fill_value
;
16275 segment_info_type
*si
= seg_info (now_seg
);
16276 struct insn_label_list
*l
= si
->label_list
;
16277 /* Auto alignment should be switched on by next section change. */
16279 mips_align (temp
, fill_ptr
, l
);
16286 demand_empty_rest_of_line ();
16290 s_change_sec (int sec
)
16294 /* The ELF backend needs to know that we are changing sections, so
16295 that .previous works correctly. We could do something like check
16296 for an obj_section_change_hook macro, but that might be confusing
16297 as it would not be appropriate to use it in the section changing
16298 functions in read.c, since obj-elf.c intercepts those. FIXME:
16299 This should be cleaner, somehow. */
16300 obj_elf_section_change_hook ();
16302 mips_emit_delays ();
16313 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16314 demand_empty_rest_of_line ();
16318 seg
= subseg_new (RDATA_SECTION_NAME
,
16319 (subsegT
) get_absolute_expression ());
16320 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
16321 | SEC_RELOC
| SEC_DATA
));
16322 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16323 record_alignment (seg
, 4);
16324 demand_empty_rest_of_line ();
16328 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16329 bfd_set_section_flags (seg
,
16330 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
16331 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16332 record_alignment (seg
, 4);
16333 demand_empty_rest_of_line ();
16337 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16338 bfd_set_section_flags (seg
, SEC_ALLOC
);
16339 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16340 record_alignment (seg
, 4);
16341 demand_empty_rest_of_line ();
16349 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16352 char *section_name
;
16357 int section_entry_size
;
16358 int section_alignment
;
16360 saved_ilp
= input_line_pointer
;
16361 endc
= get_symbol_name (§ion_name
);
16362 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16364 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16366 /* Do we have .section Name<,"flags">? */
16367 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16369 /* Just after name is now '\0'. */
16370 (void) restore_line_pointer (endc
);
16371 input_line_pointer
= saved_ilp
;
16372 obj_elf_section (ignore
);
16376 section_name
= xstrdup (section_name
);
16377 c
= restore_line_pointer (endc
);
16379 input_line_pointer
++;
16381 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16383 section_type
= get_absolute_expression ();
16387 if (*input_line_pointer
++ == ',')
16388 section_flag
= get_absolute_expression ();
16392 if (*input_line_pointer
++ == ',')
16393 section_entry_size
= get_absolute_expression ();
16395 section_entry_size
= 0;
16397 if (*input_line_pointer
++ == ',')
16398 section_alignment
= get_absolute_expression ();
16400 section_alignment
= 0;
16402 /* FIXME: really ignore? */
16403 (void) section_alignment
;
16405 /* When using the generic form of .section (as implemented by obj-elf.c),
16406 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16407 traditionally had to fall back on the more common @progbits instead.
16409 There's nothing really harmful in this, since bfd will correct
16410 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16411 means that, for backwards compatibility, the special_section entries
16412 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16414 Even so, we shouldn't force users of the MIPS .section syntax to
16415 incorrectly label the sections as SHT_PROGBITS. The best compromise
16416 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16417 generic type-checking code. */
16418 if (section_type
== SHT_MIPS_DWARF
)
16419 section_type
= SHT_PROGBITS
;
16421 obj_elf_change_section (section_name
, section_type
, section_flag
,
16422 section_entry_size
, 0, 0, 0);
16424 if (now_seg
->name
!= section_name
)
16425 free (section_name
);
16429 mips_enable_auto_align (void)
16435 s_cons (int log_size
)
16437 segment_info_type
*si
= seg_info (now_seg
);
16438 struct insn_label_list
*l
= si
->label_list
;
16440 mips_emit_delays ();
16441 if (log_size
> 0 && auto_align
)
16442 mips_align (log_size
, 0, l
);
16443 cons (1 << log_size
);
16444 mips_clear_insn_labels ();
16448 s_float_cons (int type
)
16450 segment_info_type
*si
= seg_info (now_seg
);
16451 struct insn_label_list
*l
= si
->label_list
;
16453 mips_emit_delays ();
16458 mips_align (3, 0, l
);
16460 mips_align (2, 0, l
);
16464 mips_clear_insn_labels ();
16467 /* Handle .globl. We need to override it because on Irix 5 you are
16470 where foo is an undefined symbol, to mean that foo should be
16471 considered to be the address of a function. */
16474 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16482 c
= get_symbol_name (&name
);
16483 symbolP
= symbol_find_or_make (name
);
16484 S_SET_EXTERNAL (symbolP
);
16486 *input_line_pointer
= c
;
16487 SKIP_WHITESPACE_AFTER_NAME ();
16489 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16490 && (*input_line_pointer
!= ','))
16495 c
= get_symbol_name (&secname
);
16496 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16498 as_bad (_("%s: no such section"), secname
);
16499 (void) restore_line_pointer (c
);
16501 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16502 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
16505 c
= *input_line_pointer
;
16508 input_line_pointer
++;
16509 SKIP_WHITESPACE ();
16510 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16516 demand_empty_rest_of_line ();
16520 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16521 any undefined non-function symbol to STT_OBJECT. We try to be
16522 compatible, since newer Irix 5 and 6 linkers care. */
16525 mips_frob_symbol (symbolS
*symp ATTRIBUTE_UNUSED
)
16527 /* This late in assembly we can set BSF_OBJECT indiscriminately
16528 and let elf.c:swap_out_syms sort out the symbol type. */
16529 flagword
*flags
= &symbol_get_bfdsym (symp
)->flags
;
16530 if ((*flags
& (BSF_GLOBAL
| BSF_WEAK
)) != 0
16531 || !S_IS_DEFINED (symp
))
16532 *flags
|= BSF_OBJECT
;
16537 s_option (int x ATTRIBUTE_UNUSED
)
16542 c
= get_symbol_name (&opt
);
16546 /* FIXME: What does this mean? */
16548 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16552 i
= atoi (opt
+ 3);
16553 if (i
!= 0 && i
!= 2)
16554 as_bad (_(".option pic%d not supported"), i
);
16555 else if (mips_pic
== VXWORKS_PIC
)
16556 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16561 mips_pic
= SVR4_PIC
;
16562 mips_abicalls
= TRUE
;
16565 if (mips_pic
== SVR4_PIC
)
16567 if (g_switch_seen
&& g_switch_value
!= 0)
16568 as_warn (_("-G may not be used with SVR4 PIC code"));
16569 g_switch_value
= 0;
16570 bfd_set_gp_size (stdoutput
, 0);
16574 as_warn (_("unrecognized option \"%s\""), opt
);
16576 (void) restore_line_pointer (c
);
16577 demand_empty_rest_of_line ();
16580 /* This structure is used to hold a stack of .set values. */
16582 struct mips_option_stack
16584 struct mips_option_stack
*next
;
16585 struct mips_set_options options
;
16588 static struct mips_option_stack
*mips_opts_stack
;
16590 /* Return status for .set/.module option handling. */
16592 enum code_option_type
16594 /* Unrecognized option. */
16595 OPTION_TYPE_BAD
= -1,
16597 /* Ordinary option. */
16598 OPTION_TYPE_NORMAL
,
16600 /* ISA changing option. */
16604 /* Handle common .set/.module options. Return status indicating option
16607 static enum code_option_type
16608 parse_code_option (char * name
)
16610 bfd_boolean isa_set
= FALSE
;
16611 const struct mips_ase
*ase
;
16613 if (strncmp (name
, "at=", 3) == 0)
16615 char *s
= name
+ 3;
16617 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16618 as_bad (_("unrecognized register name `%s'"), s
);
16620 else if (strcmp (name
, "at") == 0)
16621 mips_opts
.at
= ATREG
;
16622 else if (strcmp (name
, "noat") == 0)
16623 mips_opts
.at
= ZERO
;
16624 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16625 mips_opts
.nomove
= 0;
16626 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16627 mips_opts
.nomove
= 1;
16628 else if (strcmp (name
, "bopt") == 0)
16629 mips_opts
.nobopt
= 0;
16630 else if (strcmp (name
, "nobopt") == 0)
16631 mips_opts
.nobopt
= 1;
16632 else if (strcmp (name
, "gp=32") == 0)
16634 else if (strcmp (name
, "gp=64") == 0)
16636 else if (strcmp (name
, "fp=32") == 0)
16638 else if (strcmp (name
, "fp=xx") == 0)
16640 else if (strcmp (name
, "fp=64") == 0)
16642 else if (strcmp (name
, "softfloat") == 0)
16643 mips_opts
.soft_float
= 1;
16644 else if (strcmp (name
, "hardfloat") == 0)
16645 mips_opts
.soft_float
= 0;
16646 else if (strcmp (name
, "singlefloat") == 0)
16647 mips_opts
.single_float
= 1;
16648 else if (strcmp (name
, "doublefloat") == 0)
16649 mips_opts
.single_float
= 0;
16650 else if (strcmp (name
, "nooddspreg") == 0)
16651 mips_opts
.oddspreg
= 0;
16652 else if (strcmp (name
, "oddspreg") == 0)
16653 mips_opts
.oddspreg
= 1;
16654 else if (strcmp (name
, "mips16") == 0
16655 || strcmp (name
, "MIPS-16") == 0)
16656 mips_opts
.mips16
= 1;
16657 else if (strcmp (name
, "nomips16") == 0
16658 || strcmp (name
, "noMIPS-16") == 0)
16659 mips_opts
.mips16
= 0;
16660 else if (strcmp (name
, "micromips") == 0)
16661 mips_opts
.micromips
= 1;
16662 else if (strcmp (name
, "nomicromips") == 0)
16663 mips_opts
.micromips
= 0;
16664 else if (name
[0] == 'n'
16666 && (ase
= mips_lookup_ase (name
+ 2)))
16667 mips_set_ase (ase
, &mips_opts
, FALSE
);
16668 else if ((ase
= mips_lookup_ase (name
)))
16669 mips_set_ase (ase
, &mips_opts
, TRUE
);
16670 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16672 /* Permit the user to change the ISA and architecture on the fly.
16673 Needless to say, misuse can cause serious problems. */
16674 if (strncmp (name
, "arch=", 5) == 0)
16676 const struct mips_cpu_info
*p
;
16678 p
= mips_parse_cpu ("internal use", name
+ 5);
16680 as_bad (_("unknown architecture %s"), name
+ 5);
16683 mips_opts
.arch
= p
->cpu
;
16684 mips_opts
.isa
= p
->isa
;
16686 mips_opts
.init_ase
= p
->ase
;
16689 else if (strncmp (name
, "mips", 4) == 0)
16691 const struct mips_cpu_info
*p
;
16693 p
= mips_parse_cpu ("internal use", name
);
16695 as_bad (_("unknown ISA level %s"), name
+ 4);
16698 mips_opts
.arch
= p
->cpu
;
16699 mips_opts
.isa
= p
->isa
;
16701 mips_opts
.init_ase
= p
->ase
;
16705 as_bad (_("unknown ISA or architecture %s"), name
);
16707 else if (strcmp (name
, "autoextend") == 0)
16708 mips_opts
.noautoextend
= 0;
16709 else if (strcmp (name
, "noautoextend") == 0)
16710 mips_opts
.noautoextend
= 1;
16711 else if (strcmp (name
, "insn32") == 0)
16712 mips_opts
.insn32
= TRUE
;
16713 else if (strcmp (name
, "noinsn32") == 0)
16714 mips_opts
.insn32
= FALSE
;
16715 else if (strcmp (name
, "sym32") == 0)
16716 mips_opts
.sym32
= TRUE
;
16717 else if (strcmp (name
, "nosym32") == 0)
16718 mips_opts
.sym32
= FALSE
;
16720 return OPTION_TYPE_BAD
;
16722 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16725 /* Handle the .set pseudo-op. */
16728 s_mipsset (int x ATTRIBUTE_UNUSED
)
16730 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16731 char *name
= input_line_pointer
, ch
;
16733 file_mips_check_options ();
16735 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16736 ++input_line_pointer
;
16737 ch
= *input_line_pointer
;
16738 *input_line_pointer
= '\0';
16740 if (strchr (name
, ','))
16742 /* Generic ".set" directive; use the generic handler. */
16743 *input_line_pointer
= ch
;
16744 input_line_pointer
= name
;
16749 if (strcmp (name
, "reorder") == 0)
16751 if (mips_opts
.noreorder
)
16754 else if (strcmp (name
, "noreorder") == 0)
16756 if (!mips_opts
.noreorder
)
16757 start_noreorder ();
16759 else if (strcmp (name
, "macro") == 0)
16760 mips_opts
.warn_about_macros
= 0;
16761 else if (strcmp (name
, "nomacro") == 0)
16763 if (mips_opts
.noreorder
== 0)
16764 as_bad (_("`noreorder' must be set before `nomacro'"));
16765 mips_opts
.warn_about_macros
= 1;
16767 else if (strcmp (name
, "gp=default") == 0)
16768 mips_opts
.gp
= file_mips_opts
.gp
;
16769 else if (strcmp (name
, "fp=default") == 0)
16770 mips_opts
.fp
= file_mips_opts
.fp
;
16771 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16773 mips_opts
.isa
= file_mips_opts
.isa
;
16774 mips_opts
.arch
= file_mips_opts
.arch
;
16775 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16776 mips_opts
.gp
= file_mips_opts
.gp
;
16777 mips_opts
.fp
= file_mips_opts
.fp
;
16779 else if (strcmp (name
, "push") == 0)
16781 struct mips_option_stack
*s
;
16783 s
= XNEW (struct mips_option_stack
);
16784 s
->next
= mips_opts_stack
;
16785 s
->options
= mips_opts
;
16786 mips_opts_stack
= s
;
16788 else if (strcmp (name
, "pop") == 0)
16790 struct mips_option_stack
*s
;
16792 s
= mips_opts_stack
;
16794 as_bad (_(".set pop with no .set push"));
16797 /* If we're changing the reorder mode we need to handle
16798 delay slots correctly. */
16799 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16800 start_noreorder ();
16801 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16804 mips_opts
= s
->options
;
16805 mips_opts_stack
= s
->next
;
16811 type
= parse_code_option (name
);
16812 if (type
== OPTION_TYPE_BAD
)
16813 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16816 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16817 registers based on what is supported by the arch/cpu. */
16818 if (type
== OPTION_TYPE_ISA
)
16820 switch (mips_opts
.isa
)
16825 /* MIPS I cannot support FPXX. */
16827 /* fall-through. */
16834 if (mips_opts
.fp
!= 0)
16850 if (mips_opts
.fp
!= 0)
16852 if (mips_opts
.arch
== CPU_R5900
)
16859 as_bad (_("unknown ISA level %s"), name
+ 4);
16864 mips_check_options (&mips_opts
, FALSE
);
16866 mips_check_isa_supports_ases ();
16867 *input_line_pointer
= ch
;
16868 demand_empty_rest_of_line ();
16871 /* Handle the .module pseudo-op. */
16874 s_module (int ignore ATTRIBUTE_UNUSED
)
16876 char *name
= input_line_pointer
, ch
;
16878 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16879 ++input_line_pointer
;
16880 ch
= *input_line_pointer
;
16881 *input_line_pointer
= '\0';
16883 if (!file_mips_opts_checked
)
16885 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16886 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16888 /* Update module level settings from mips_opts. */
16889 file_mips_opts
= mips_opts
;
16892 as_bad (_(".module is not permitted after generating code"));
16894 *input_line_pointer
= ch
;
16895 demand_empty_rest_of_line ();
16898 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16899 .option pic2. It means to generate SVR4 PIC calls. */
16902 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16904 mips_pic
= SVR4_PIC
;
16905 mips_abicalls
= TRUE
;
16907 if (g_switch_seen
&& g_switch_value
!= 0)
16908 as_warn (_("-G may not be used with SVR4 PIC code"));
16909 g_switch_value
= 0;
16911 bfd_set_gp_size (stdoutput
, 0);
16912 demand_empty_rest_of_line ();
16915 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16916 PIC code. It sets the $gp register for the function based on the
16917 function address, which is in the register named in the argument.
16918 This uses a relocation against _gp_disp, which is handled specially
16919 by the linker. The result is:
16920 lui $gp,%hi(_gp_disp)
16921 addiu $gp,$gp,%lo(_gp_disp)
16922 addu $gp,$gp,.cpload argument
16923 The .cpload argument is normally $25 == $t9.
16925 The -mno-shared option changes this to:
16926 lui $gp,%hi(__gnu_local_gp)
16927 addiu $gp,$gp,%lo(__gnu_local_gp)
16928 and the argument is ignored. This saves an instruction, but the
16929 resulting code is not position independent; it uses an absolute
16930 address for __gnu_local_gp. Thus code assembled with -mno-shared
16931 can go into an ordinary executable, but not into a shared library. */
16934 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16940 file_mips_check_options ();
16942 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16943 .cpload is ignored. */
16944 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16950 if (mips_opts
.mips16
)
16952 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16953 ignore_rest_of_line ();
16957 /* .cpload should be in a .set noreorder section. */
16958 if (mips_opts
.noreorder
== 0)
16959 as_warn (_(".cpload not in noreorder section"));
16961 reg
= tc_get_register (0);
16963 /* If we need to produce a 64-bit address, we are better off using
16964 the default instruction sequence. */
16965 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16967 ex
.X_op
= O_symbol
;
16968 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16970 ex
.X_op_symbol
= NULL
;
16971 ex
.X_add_number
= 0;
16973 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16974 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16976 mips_mark_labels ();
16977 mips_assembling_insn
= TRUE
;
16980 macro_build_lui (&ex
, mips_gp_register
);
16981 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
16982 mips_gp_register
, BFD_RELOC_LO16
);
16984 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
16985 mips_gp_register
, reg
);
16988 mips_assembling_insn
= FALSE
;
16989 demand_empty_rest_of_line ();
16992 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
16993 .cpsetup $reg1, offset|$reg2, label
16995 If offset is given, this results in:
16996 sd $gp, offset($sp)
16997 lui $gp, %hi(%neg(%gp_rel(label)))
16998 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
16999 daddu $gp, $gp, $reg1
17001 If $reg2 is given, this results in:
17003 lui $gp, %hi(%neg(%gp_rel(label)))
17004 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17005 daddu $gp, $gp, $reg1
17006 $reg1 is normally $25 == $t9.
17008 The -mno-shared option replaces the last three instructions with
17010 addiu $gp,$gp,%lo(_gp) */
17013 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17015 expressionS ex_off
;
17016 expressionS ex_sym
;
17019 file_mips_check_options ();
17021 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17022 We also need NewABI support. */
17023 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17029 if (mips_opts
.mips16
)
17031 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17032 ignore_rest_of_line ();
17036 reg1
= tc_get_register (0);
17037 SKIP_WHITESPACE ();
17038 if (*input_line_pointer
!= ',')
17040 as_bad (_("missing argument separator ',' for .cpsetup"));
17044 ++input_line_pointer
;
17045 SKIP_WHITESPACE ();
17046 if (*input_line_pointer
== '$')
17048 mips_cpreturn_register
= tc_get_register (0);
17049 mips_cpreturn_offset
= -1;
17053 mips_cpreturn_offset
= get_absolute_expression ();
17054 mips_cpreturn_register
= -1;
17056 SKIP_WHITESPACE ();
17057 if (*input_line_pointer
!= ',')
17059 as_bad (_("missing argument separator ',' for .cpsetup"));
17063 ++input_line_pointer
;
17064 SKIP_WHITESPACE ();
17065 expression (&ex_sym
);
17067 mips_mark_labels ();
17068 mips_assembling_insn
= TRUE
;
17071 if (mips_cpreturn_register
== -1)
17073 ex_off
.X_op
= O_constant
;
17074 ex_off
.X_add_symbol
= NULL
;
17075 ex_off
.X_op_symbol
= NULL
;
17076 ex_off
.X_add_number
= mips_cpreturn_offset
;
17078 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17079 BFD_RELOC_LO16
, SP
);
17082 move_register (mips_cpreturn_register
, mips_gp_register
);
17084 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17086 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17087 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17090 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17091 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17092 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17094 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17095 mips_gp_register
, reg1
);
17101 ex
.X_op
= O_symbol
;
17102 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17103 ex
.X_op_symbol
= NULL
;
17104 ex
.X_add_number
= 0;
17106 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17107 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17109 macro_build_lui (&ex
, mips_gp_register
);
17110 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17111 mips_gp_register
, BFD_RELOC_LO16
);
17116 mips_assembling_insn
= FALSE
;
17117 demand_empty_rest_of_line ();
17121 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17123 file_mips_check_options ();
17125 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17126 .cplocal is ignored. */
17127 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17133 if (mips_opts
.mips16
)
17135 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17136 ignore_rest_of_line ();
17140 mips_gp_register
= tc_get_register (0);
17141 demand_empty_rest_of_line ();
17144 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17145 offset from $sp. The offset is remembered, and after making a PIC
17146 call $gp is restored from that location. */
17149 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17153 file_mips_check_options ();
17155 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17156 .cprestore is ignored. */
17157 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17163 if (mips_opts
.mips16
)
17165 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17166 ignore_rest_of_line ();
17170 mips_cprestore_offset
= get_absolute_expression ();
17171 mips_cprestore_valid
= 1;
17173 ex
.X_op
= O_constant
;
17174 ex
.X_add_symbol
= NULL
;
17175 ex
.X_op_symbol
= NULL
;
17176 ex
.X_add_number
= mips_cprestore_offset
;
17178 mips_mark_labels ();
17179 mips_assembling_insn
= TRUE
;
17182 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17183 SP
, HAVE_64BIT_ADDRESSES
);
17186 mips_assembling_insn
= FALSE
;
17187 demand_empty_rest_of_line ();
17190 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17191 was given in the preceding .cpsetup, it results in:
17192 ld $gp, offset($sp)
17194 If a register $reg2 was given there, it results in:
17195 or $gp, $reg2, $0 */
17198 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17202 file_mips_check_options ();
17204 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17205 We also need NewABI support. */
17206 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17212 if (mips_opts
.mips16
)
17214 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17215 ignore_rest_of_line ();
17219 mips_mark_labels ();
17220 mips_assembling_insn
= TRUE
;
17223 if (mips_cpreturn_register
== -1)
17225 ex
.X_op
= O_constant
;
17226 ex
.X_add_symbol
= NULL
;
17227 ex
.X_op_symbol
= NULL
;
17228 ex
.X_add_number
= mips_cpreturn_offset
;
17230 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17233 move_register (mips_gp_register
, mips_cpreturn_register
);
17237 mips_assembling_insn
= FALSE
;
17238 demand_empty_rest_of_line ();
17241 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17242 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17243 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17244 debug information or MIPS16 TLS. */
17247 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17248 bfd_reloc_code_real_type rtype
)
17255 if (ex
.X_op
!= O_symbol
)
17257 as_bad (_("unsupported use of %s"), dirstr
);
17258 ignore_rest_of_line ();
17261 p
= frag_more (bytes
);
17262 md_number_to_chars (p
, 0, bytes
);
17263 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17264 demand_empty_rest_of_line ();
17265 mips_clear_insn_labels ();
17268 /* Handle .dtprelword. */
17271 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17273 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17276 /* Handle .dtpreldword. */
17279 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17281 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17284 /* Handle .tprelword. */
17287 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17289 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17292 /* Handle .tpreldword. */
17295 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17297 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17300 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17301 code. It sets the offset to use in gp_rel relocations. */
17304 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17306 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17307 We also need NewABI support. */
17308 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17314 mips_gprel_offset
= get_absolute_expression ();
17316 demand_empty_rest_of_line ();
17319 /* Handle the .gpword pseudo-op. This is used when generating PIC
17320 code. It generates a 32 bit GP relative reloc. */
17323 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17325 segment_info_type
*si
;
17326 struct insn_label_list
*l
;
17330 /* When not generating PIC code, this is treated as .word. */
17331 if (mips_pic
!= SVR4_PIC
)
17337 si
= seg_info (now_seg
);
17338 l
= si
->label_list
;
17339 mips_emit_delays ();
17341 mips_align (2, 0, l
);
17344 mips_clear_insn_labels ();
17346 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17348 as_bad (_("unsupported use of .gpword"));
17349 ignore_rest_of_line ();
17353 md_number_to_chars (p
, 0, 4);
17354 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17355 BFD_RELOC_GPREL32
);
17357 demand_empty_rest_of_line ();
17361 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17363 segment_info_type
*si
;
17364 struct insn_label_list
*l
;
17368 /* When not generating PIC code, this is treated as .dword. */
17369 if (mips_pic
!= SVR4_PIC
)
17375 si
= seg_info (now_seg
);
17376 l
= si
->label_list
;
17377 mips_emit_delays ();
17379 mips_align (3, 0, l
);
17382 mips_clear_insn_labels ();
17384 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17386 as_bad (_("unsupported use of .gpdword"));
17387 ignore_rest_of_line ();
17391 md_number_to_chars (p
, 0, 8);
17392 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17393 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17395 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17396 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17397 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17399 demand_empty_rest_of_line ();
17402 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17403 tables. It generates a R_MIPS_EH reloc. */
17406 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17411 mips_emit_delays ();
17414 mips_clear_insn_labels ();
17416 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17418 as_bad (_("unsupported use of .ehword"));
17419 ignore_rest_of_line ();
17423 md_number_to_chars (p
, 0, 4);
17424 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17425 BFD_RELOC_32_PCREL
);
17427 demand_empty_rest_of_line ();
17430 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17431 tables in SVR4 PIC code. */
17434 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17438 file_mips_check_options ();
17440 /* This is ignored when not generating SVR4 PIC code. */
17441 if (mips_pic
!= SVR4_PIC
)
17447 mips_mark_labels ();
17448 mips_assembling_insn
= TRUE
;
17450 /* Add $gp to the register named as an argument. */
17452 reg
= tc_get_register (0);
17453 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17456 mips_assembling_insn
= FALSE
;
17457 demand_empty_rest_of_line ();
17460 /* Handle the .insn pseudo-op. This marks instruction labels in
17461 mips16/micromips mode. This permits the linker to handle them specially,
17462 such as generating jalx instructions when needed. We also make
17463 them odd for the duration of the assembly, in order to generate the
17464 right sort of code. We will make them even in the adjust_symtab
17465 routine, while leaving them marked. This is convenient for the
17466 debugger and the disassembler. The linker knows to make them odd
17470 s_insn (int ignore ATTRIBUTE_UNUSED
)
17472 file_mips_check_options ();
17473 file_ase_mips16
|= mips_opts
.mips16
;
17474 file_ase_micromips
|= mips_opts
.micromips
;
17476 mips_mark_labels ();
17478 demand_empty_rest_of_line ();
17481 /* Handle the .nan pseudo-op. */
17484 s_nan (int ignore ATTRIBUTE_UNUSED
)
17486 static const char str_legacy
[] = "legacy";
17487 static const char str_2008
[] = "2008";
17490 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17492 if (i
== sizeof (str_2008
) - 1
17493 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17495 else if (i
== sizeof (str_legacy
) - 1
17496 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17498 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17501 as_bad (_("`%s' does not support legacy NaN"),
17502 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17505 as_bad (_("bad .nan directive"));
17507 input_line_pointer
+= i
;
17508 demand_empty_rest_of_line ();
17511 /* Handle a .stab[snd] directive. Ideally these directives would be
17512 implemented in a transparent way, so that removing them would not
17513 have any effect on the generated instructions. However, s_stab
17514 internally changes the section, so in practice we need to decide
17515 now whether the preceding label marks compressed code. We do not
17516 support changing the compression mode of a label after a .stab*
17517 directive, such as in:
17523 so the current mode wins. */
17526 s_mips_stab (int type
)
17528 file_mips_check_options ();
17529 mips_mark_labels ();
17533 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17536 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17543 c
= get_symbol_name (&name
);
17544 symbolP
= symbol_find_or_make (name
);
17545 S_SET_WEAK (symbolP
);
17546 *input_line_pointer
= c
;
17548 SKIP_WHITESPACE_AFTER_NAME ();
17550 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17552 if (S_IS_DEFINED (symbolP
))
17554 as_bad (_("ignoring attempt to redefine symbol %s"),
17555 S_GET_NAME (symbolP
));
17556 ignore_rest_of_line ();
17560 if (*input_line_pointer
== ',')
17562 ++input_line_pointer
;
17563 SKIP_WHITESPACE ();
17567 if (exp
.X_op
!= O_symbol
)
17569 as_bad (_("bad .weakext directive"));
17570 ignore_rest_of_line ();
17573 symbol_set_value_expression (symbolP
, &exp
);
17576 demand_empty_rest_of_line ();
17579 /* Parse a register string into a number. Called from the ECOFF code
17580 to parse .frame. The argument is non-zero if this is the frame
17581 register, so that we can record it in mips_frame_reg. */
17584 tc_get_register (int frame
)
17588 SKIP_WHITESPACE ();
17589 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17593 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17594 mips_frame_reg_valid
= 1;
17595 mips_cprestore_valid
= 0;
17601 md_section_align (asection
*seg
, valueT addr
)
17603 int align
= bfd_section_alignment (seg
);
17605 /* We don't need to align ELF sections to the full alignment.
17606 However, Irix 5 may prefer that we align them at least to a 16
17607 byte boundary. We don't bother to align the sections if we
17608 are targeted for an embedded system. */
17609 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17614 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17617 /* Utility routine, called from above as well. If called while the
17618 input file is still being read, it's only an approximation. (For
17619 example, a symbol may later become defined which appeared to be
17620 undefined earlier.) */
17623 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17628 if (g_switch_value
> 0)
17630 const char *symname
;
17633 /* Find out whether this symbol can be referenced off the $gp
17634 register. It can be if it is smaller than the -G size or if
17635 it is in the .sdata or .sbss section. Certain symbols can
17636 not be referenced off the $gp, although it appears as though
17638 symname
= S_GET_NAME (sym
);
17639 if (symname
!= (const char *) NULL
17640 && (strcmp (symname
, "eprol") == 0
17641 || strcmp (symname
, "etext") == 0
17642 || strcmp (symname
, "_gp") == 0
17643 || strcmp (symname
, "edata") == 0
17644 || strcmp (symname
, "_fbss") == 0
17645 || strcmp (symname
, "_fdata") == 0
17646 || strcmp (symname
, "_ftext") == 0
17647 || strcmp (symname
, "end") == 0
17648 || strcmp (symname
, "_gp_disp") == 0))
17650 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17652 #ifndef NO_ECOFF_DEBUGGING
17653 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17654 && (symbol_get_obj (sym
)->ecoff_extern_size
17655 <= g_switch_value
))
17657 /* We must defer this decision until after the whole
17658 file has been read, since there might be a .extern
17659 after the first use of this symbol. */
17660 || (before_relaxing
17661 #ifndef NO_ECOFF_DEBUGGING
17662 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17664 && S_GET_VALUE (sym
) == 0)
17665 || (S_GET_VALUE (sym
) != 0
17666 && S_GET_VALUE (sym
) <= g_switch_value
)))
17670 const char *segname
;
17672 segname
= segment_name (S_GET_SEGMENT (sym
));
17673 gas_assert (strcmp (segname
, ".lit8") != 0
17674 && strcmp (segname
, ".lit4") != 0);
17675 change
= (strcmp (segname
, ".sdata") != 0
17676 && strcmp (segname
, ".sbss") != 0
17677 && strncmp (segname
, ".sdata.", 7) != 0
17678 && strncmp (segname
, ".sbss.", 6) != 0
17679 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17680 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17685 /* We are not optimizing for the $gp register. */
17690 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17693 pic_need_relax (symbolS
*sym
)
17697 /* Handle the case of a symbol equated to another symbol. */
17698 while (symbol_equated_reloc_p (sym
))
17702 /* It's possible to get a loop here in a badly written program. */
17703 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17709 if (symbol_section_p (sym
))
17712 symsec
= S_GET_SEGMENT (sym
);
17714 /* This must duplicate the test in adjust_reloc_syms. */
17715 return (!bfd_is_und_section (symsec
)
17716 && !bfd_is_abs_section (symsec
)
17717 && !bfd_is_com_section (symsec
)
17718 /* A global or weak symbol is treated as external. */
17719 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17722 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17723 convert a section-relative value VAL to the equivalent PC-relative
17727 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17728 offsetT val
, long stretch
)
17733 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17735 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17737 /* If the relax_marker of the symbol fragment differs from the
17738 relax_marker of this fragment, we have not yet adjusted the
17739 symbol fragment fr_address. We want to add in STRETCH in
17740 order to get a better estimate of the address. This
17741 particularly matters because of the shift bits. */
17742 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17746 /* Adjust stretch for any alignment frag. Note that if have
17747 been expanding the earlier code, the symbol may be
17748 defined in what appears to be an earlier frag. FIXME:
17749 This doesn't handle the fr_subtype field, which specifies
17750 a maximum number of bytes to skip when doing an
17752 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17754 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17757 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17759 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17768 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17770 /* The base address rules are complicated. The base address of
17771 a branch is the following instruction. The base address of a
17772 PC relative load or add is the instruction itself, but if it
17773 is in a delay slot (in which case it can not be extended) use
17774 the address of the instruction whose delay slot it is in. */
17775 if (pcrel_op
->include_isa_bit
)
17779 /* If we are currently assuming that this frag should be
17780 extended, then the current address is two bytes higher. */
17781 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17784 /* Ignore the low bit in the target, since it will be set
17785 for a text label. */
17788 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17790 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17793 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17798 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17799 extended opcode. SEC is the section the frag is in. */
17802 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17804 const struct mips_int_operand
*operand
;
17809 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17811 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17814 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17815 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17816 operand
= mips16_immed_operand (type
, FALSE
);
17817 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17818 || (operand
->root
.type
== OP_PCREL
17820 : !bfd_is_abs_section (symsec
)))
17823 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17825 if (operand
->root
.type
== OP_PCREL
)
17827 const struct mips_pcrel_operand
*pcrel_op
;
17830 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17833 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17834 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17836 /* If any of the shifted bits are set, we must use an extended
17837 opcode. If the address depends on the size of this
17838 instruction, this can lead to a loop, so we arrange to always
17839 use an extended opcode. */
17840 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17842 fragp
->fr_subtype
=
17843 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17847 /* If we are about to mark a frag as extended because the value
17848 is precisely the next value above maxtiny, then there is a
17849 chance of an infinite loop as in the following code:
17854 In this case when the la is extended, foo is 0x3fc bytes
17855 away, so the la can be shrunk, but then foo is 0x400 away, so
17856 the la must be extended. To avoid this loop, we mark the
17857 frag as extended if it was small, and is about to become
17858 extended with the next value above maxtiny. */
17859 maxtiny
= mips_int_operand_max (operand
);
17860 if (val
== maxtiny
+ (1 << operand
->shift
)
17861 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17863 fragp
->fr_subtype
=
17864 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17869 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17872 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17873 macro expansion. SEC is the section the frag is in. We only
17874 support PC-relative instructions (LA, DLA, LW, LD) here, in
17875 non-PIC code using 32-bit addressing. */
17878 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17880 const struct mips_pcrel_operand
*pcrel_op
;
17881 const struct mips_int_operand
*operand
;
17886 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17888 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17890 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17893 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17899 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17900 if (bfd_is_abs_section (symsec
))
17902 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17904 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17907 operand
= mips16_immed_operand (type
, TRUE
);
17908 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17909 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17910 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17912 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17919 /* Compute the length of a branch sequence, and adjust the
17920 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17921 worst-case length is computed, with UPDATE being used to indicate
17922 whether an unconditional (-1), branch-likely (+1) or regular (0)
17923 branch is to be computed. */
17925 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17927 bfd_boolean toofar
;
17931 && S_IS_DEFINED (fragp
->fr_symbol
)
17932 && !S_IS_WEAK (fragp
->fr_symbol
)
17933 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17938 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17940 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17944 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17947 /* If the symbol is not defined or it's in a different segment,
17948 we emit the long sequence. */
17951 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17953 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17954 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17955 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17956 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17957 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17963 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17966 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17968 /* Additional space for PIC loading of target address. */
17970 if (mips_opts
.isa
== ISA_MIPS1
)
17971 /* Additional space for $at-stabilizing nop. */
17975 /* If branch is conditional. */
17976 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
17983 /* Get a FRAG's branch instruction delay slot size, either from the
17984 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
17985 or SHORT_INSN_SIZE otherwise. */
17988 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
17990 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17993 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
17995 return short_insn_size
;
17998 /* Compute the length of a branch sequence, and adjust the
17999 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18000 worst-case length is computed, with UPDATE being used to indicate
18001 whether an unconditional (-1), or regular (0) branch is to be
18005 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18007 bfd_boolean insn32
= TRUE
;
18008 bfd_boolean nods
= TRUE
;
18009 bfd_boolean pic
= TRUE
;
18010 bfd_boolean al
= TRUE
;
18011 int short_insn_size
;
18012 bfd_boolean toofar
;
18017 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18018 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18019 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18020 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18022 short_insn_size
= insn32
? 4 : 2;
18025 && S_IS_DEFINED (fragp
->fr_symbol
)
18026 && !S_IS_WEAK (fragp
->fr_symbol
)
18027 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18032 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18033 /* Ignore the low bit in the target, since it will be set
18034 for a text label. */
18035 if ((val
& 1) != 0)
18038 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18042 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18045 /* If the symbol is not defined or it's in a different segment,
18046 we emit the long sequence. */
18049 if (fragp
&& update
18050 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18051 fragp
->fr_subtype
= (toofar
18052 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18053 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18058 bfd_boolean compact_known
= fragp
!= NULL
;
18059 bfd_boolean compact
= FALSE
;
18060 bfd_boolean uncond
;
18064 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18065 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18068 uncond
= update
< 0;
18070 /* If label is out of range, we turn branch <br>:
18072 <br> label # 4 bytes
18079 # compact && (!PIC || insn32)
18082 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
18083 length
+= short_insn_size
;
18085 /* If assembling PIC code, we further turn:
18091 lw/ld at, %got(label)(gp) # 4 bytes
18092 d/addiu at, %lo(label) # 4 bytes
18093 jr/c at # 2/4 bytes
18096 length
+= 4 + short_insn_size
;
18098 /* Add an extra nop if the jump has no compact form and we need
18099 to fill the delay slot. */
18100 if ((!pic
|| al
) && nods
)
18102 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
18103 : short_insn_size
);
18105 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18107 <brneg> 0f # 4 bytes
18108 nop # 2/4 bytes if !compact
18111 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
18115 /* Add an extra nop to fill the delay slot. */
18116 gas_assert (fragp
);
18117 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18123 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18124 bit accordingly. */
18127 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18129 bfd_boolean toofar
;
18132 && S_IS_DEFINED (fragp
->fr_symbol
)
18133 && !S_IS_WEAK (fragp
->fr_symbol
)
18134 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18140 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18141 /* Ignore the low bit in the target, since it will be set
18142 for a text label. */
18143 if ((val
& 1) != 0)
18146 /* Assume this is a 2-byte branch. */
18147 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18149 /* We try to avoid the infinite loop by not adding 2 more bytes for
18154 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18156 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18157 else if (type
== 'E')
18158 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18163 /* If the symbol is not defined or it's in a different segment,
18164 we emit a normal 32-bit branch. */
18167 if (fragp
&& update
18168 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18170 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18171 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18179 /* Estimate the size of a frag before relaxing. Unless this is the
18180 mips16, we are not really relaxing here, and the final size is
18181 encoded in the subtype information. For the mips16, we have to
18182 decide whether we are using an extended opcode or not. */
18185 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18189 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18192 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18194 return fragp
->fr_var
;
18197 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18199 /* We don't want to modify the EXTENDED bit here; it might get us
18200 into infinite loops. We change it only in mips_relax_frag(). */
18201 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18202 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18204 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18207 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18211 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18212 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18213 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18214 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18215 fragp
->fr_var
= length
;
18220 if (mips_pic
== VXWORKS_PIC
)
18221 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18223 else if (RELAX_PIC (fragp
->fr_subtype
))
18224 change
= pic_need_relax (fragp
->fr_symbol
);
18226 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18230 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18231 return -RELAX_FIRST (fragp
->fr_subtype
);
18234 return -RELAX_SECOND (fragp
->fr_subtype
);
18237 /* This is called to see whether a reloc against a defined symbol
18238 should be converted into a reloc against a section. */
18241 mips_fix_adjustable (fixS
*fixp
)
18243 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18244 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18247 if (fixp
->fx_addsy
== NULL
)
18250 /* Allow relocs used for EH tables. */
18251 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18254 /* If symbol SYM is in a mergeable section, relocations of the form
18255 SYM + 0 can usually be made section-relative. The mergeable data
18256 is then identified by the section offset rather than by the symbol.
18258 However, if we're generating REL LO16 relocations, the offset is split
18259 between the LO16 and partnering high part relocation. The linker will
18260 need to recalculate the complete offset in order to correctly identify
18263 The linker has traditionally not looked for the partnering high part
18264 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18265 placed anywhere. Rather than break backwards compatibility by changing
18266 this, it seems better not to force the issue, and instead keep the
18267 original symbol. This will work with either linker behavior. */
18268 if ((lo16_reloc_p (fixp
->fx_r_type
)
18269 || reloc_needs_lo_p (fixp
->fx_r_type
))
18270 && HAVE_IN_PLACE_ADDENDS
18271 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18274 /* There is no place to store an in-place offset for JALR relocations. */
18275 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18278 /* Likewise an in-range offset of limited PC-relative relocations may
18279 overflow the in-place relocatable field if recalculated against the
18280 start address of the symbol's containing section.
18282 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18283 section relative to allow linker relaxations to be performed later on. */
18284 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18285 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18288 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18289 to a floating-point stub. The same is true for non-R_MIPS16_26
18290 relocations against MIPS16 functions; in this case, the stub becomes
18291 the function's canonical address.
18293 Floating-point stubs are stored in unique .mips16.call.* or
18294 .mips16.fn.* sections. If a stub T for function F is in section S,
18295 the first relocation in section S must be against F; this is how the
18296 linker determines the target function. All relocations that might
18297 resolve to T must also be against F. We therefore have the following
18298 restrictions, which are given in an intentionally-redundant way:
18300 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18303 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18304 if that stub might be used.
18306 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18309 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18310 that stub might be used.
18312 There is a further restriction:
18314 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18315 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18316 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18317 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18318 against MIPS16 or microMIPS symbols because we need to keep the
18319 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18320 detection and JAL or BAL to JALX instruction conversion in the
18323 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18324 against a MIPS16 symbol. We deal with (5) by additionally leaving
18325 alone any jump and branch relocations against a microMIPS symbol.
18327 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18328 relocation against some symbol R, no relocation against R may be
18329 reduced. (Note that this deals with (2) as well as (1) because
18330 relocations against global symbols will never be reduced on ELF
18331 targets.) This approach is a little simpler than trying to detect
18332 stub sections, and gives the "all or nothing" per-symbol consistency
18333 that we have for MIPS16 symbols. */
18334 if (fixp
->fx_subsy
== NULL
18335 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18336 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18337 && (jmp_reloc_p (fixp
->fx_r_type
)
18338 || b_reloc_p (fixp
->fx_r_type
)))
18339 || *symbol_get_tc (fixp
->fx_addsy
)))
18345 /* Translate internal representation of relocation info to BFD target
18349 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18351 static arelent
*retval
[4];
18353 bfd_reloc_code_real_type code
;
18355 memset (retval
, 0, sizeof(retval
));
18356 reloc
= retval
[0] = XCNEW (arelent
);
18357 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18358 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18359 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18361 if (fixp
->fx_pcrel
)
18363 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18364 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18365 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18366 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18367 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18368 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18369 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18370 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18371 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18372 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18373 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18374 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18376 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18377 Relocations want only the symbol offset. */
18378 switch (fixp
->fx_r_type
)
18380 case BFD_RELOC_MIPS_18_PCREL_S3
:
18381 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18384 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18388 else if (HAVE_IN_PLACE_ADDENDS
18389 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18390 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18391 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18393 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18394 addend accordingly. */
18395 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18398 reloc
->addend
= fixp
->fx_addnumber
;
18400 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18401 entry to be used in the relocation's section offset. */
18402 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18404 reloc
->address
= reloc
->addend
;
18408 code
= fixp
->fx_r_type
;
18410 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18411 if (reloc
->howto
== NULL
)
18413 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18414 _("cannot represent %s relocation in this object file"
18416 bfd_get_reloc_code_name (code
));
18423 /* Relax a machine dependent frag. This returns the amount by which
18424 the current size of the frag should change. */
18427 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18429 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18431 offsetT old_var
= fragp
->fr_var
;
18433 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18435 return fragp
->fr_var
- old_var
;
18438 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18440 offsetT old_var
= fragp
->fr_var
;
18441 offsetT new_var
= 4;
18443 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18444 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18445 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18446 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18447 fragp
->fr_var
= new_var
;
18449 return new_var
- old_var
;
18452 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18455 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18457 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18459 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18460 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18462 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18464 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18470 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18472 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18474 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18475 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18476 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18478 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18480 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18488 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18490 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18492 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18493 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18494 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18498 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18499 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18506 /* Convert a machine dependent frag. */
18509 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18511 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18514 unsigned long insn
;
18517 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18518 insn
= read_insn (buf
);
18520 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18522 /* We generate a fixup instead of applying it right now
18523 because, if there are linker relaxations, we're going to
18524 need the relocations. */
18525 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18526 fragp
->fr_symbol
, fragp
->fr_offset
,
18527 TRUE
, BFD_RELOC_16_PCREL_S2
);
18528 fixp
->fx_file
= fragp
->fr_file
;
18529 fixp
->fx_line
= fragp
->fr_line
;
18531 buf
= write_insn (buf
, insn
);
18537 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18538 _("relaxed out-of-range branch into a jump"));
18540 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18543 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18545 /* Reverse the branch. */
18546 switch ((insn
>> 28) & 0xf)
18549 if ((insn
& 0xff000000) == 0x47000000
18550 || (insn
& 0xff600000) == 0x45600000)
18552 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18553 reversed by tweaking bit 23. */
18554 insn
^= 0x00800000;
18558 /* bc[0-3][tf]l? instructions can have the condition
18559 reversed by tweaking a single TF bit, and their
18560 opcodes all have 0x4???????. */
18561 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18562 insn
^= 0x00010000;
18567 /* bltz 0x04000000 bgez 0x04010000
18568 bltzal 0x04100000 bgezal 0x04110000 */
18569 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18570 insn
^= 0x00010000;
18574 /* beq 0x10000000 bne 0x14000000
18575 blez 0x18000000 bgtz 0x1c000000 */
18576 insn
^= 0x04000000;
18584 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18586 /* Clear the and-link bit. */
18587 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18589 /* bltzal 0x04100000 bgezal 0x04110000
18590 bltzall 0x04120000 bgezall 0x04130000 */
18591 insn
&= ~0x00100000;
18594 /* Branch over the branch (if the branch was likely) or the
18595 full jump (not likely case). Compute the offset from the
18596 current instruction to branch to. */
18597 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18601 /* How many bytes in instructions we've already emitted? */
18602 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18603 /* How many bytes in instructions from here to the end? */
18604 i
= fragp
->fr_var
- i
;
18606 /* Convert to instruction count. */
18608 /* Branch counts from the next instruction. */
18611 /* Branch over the jump. */
18612 buf
= write_insn (buf
, insn
);
18615 buf
= write_insn (buf
, 0);
18617 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18619 /* beql $0, $0, 2f */
18621 /* Compute the PC offset from the current instruction to
18622 the end of the variable frag. */
18623 /* How many bytes in instructions we've already emitted? */
18624 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18625 /* How many bytes in instructions from here to the end? */
18626 i
= fragp
->fr_var
- i
;
18627 /* Convert to instruction count. */
18629 /* Don't decrement i, because we want to branch over the
18633 buf
= write_insn (buf
, insn
);
18634 buf
= write_insn (buf
, 0);
18638 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18641 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18642 ? 0x0c000000 : 0x08000000);
18644 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18645 fragp
->fr_symbol
, fragp
->fr_offset
,
18646 FALSE
, BFD_RELOC_MIPS_JMP
);
18647 fixp
->fx_file
= fragp
->fr_file
;
18648 fixp
->fx_line
= fragp
->fr_line
;
18650 buf
= write_insn (buf
, insn
);
18654 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18656 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18657 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18658 insn
|= at
<< OP_SH_RT
;
18660 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18661 fragp
->fr_symbol
, fragp
->fr_offset
,
18662 FALSE
, BFD_RELOC_MIPS_GOT16
);
18663 fixp
->fx_file
= fragp
->fr_file
;
18664 fixp
->fx_line
= fragp
->fr_line
;
18666 buf
= write_insn (buf
, insn
);
18668 if (mips_opts
.isa
== ISA_MIPS1
)
18670 buf
= write_insn (buf
, 0);
18672 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18673 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18674 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18676 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18677 fragp
->fr_symbol
, fragp
->fr_offset
,
18678 FALSE
, BFD_RELOC_LO16
);
18679 fixp
->fx_file
= fragp
->fr_file
;
18680 fixp
->fx_line
= fragp
->fr_line
;
18682 buf
= write_insn (buf
, insn
);
18685 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18689 insn
|= at
<< OP_SH_RS
;
18691 buf
= write_insn (buf
, insn
);
18695 fragp
->fr_fix
+= fragp
->fr_var
;
18696 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18700 /* Relax microMIPS branches. */
18701 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18703 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18704 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18705 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18706 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18707 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18708 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18709 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18710 bfd_boolean short_ds
;
18711 unsigned long insn
;
18714 fragp
->fr_fix
+= fragp
->fr_var
;
18716 /* Handle 16-bit branches that fit or are forced to fit. */
18717 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18719 /* We generate a fixup instead of applying it right now,
18720 because if there is linker relaxation, we're going to
18721 need the relocations. */
18725 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18726 fragp
->fr_symbol
, fragp
->fr_offset
,
18727 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18730 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18731 fragp
->fr_symbol
, fragp
->fr_offset
,
18732 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18738 fixp
->fx_file
= fragp
->fr_file
;
18739 fixp
->fx_line
= fragp
->fr_line
;
18741 /* These relocations can have an addend that won't fit in
18743 fixp
->fx_no_overflow
= 1;
18748 /* Handle 32-bit branches that fit or are forced to fit. */
18749 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18750 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18752 /* We generate a fixup instead of applying it right now,
18753 because if there is linker relaxation, we're going to
18754 need the relocations. */
18755 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18756 fragp
->fr_symbol
, fragp
->fr_offset
,
18757 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18758 fixp
->fx_file
= fragp
->fr_file
;
18759 fixp
->fx_line
= fragp
->fr_line
;
18763 insn
= read_compressed_insn (buf
, 4);
18768 /* Check the short-delay-slot bit. */
18769 if (!al
|| (insn
& 0x02000000) != 0)
18770 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18772 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18775 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18780 /* Relax 16-bit branches to 32-bit branches. */
18783 insn
= read_compressed_insn (buf
, 2);
18785 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18786 insn
= 0x94000000; /* beq */
18787 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18789 unsigned long regno
;
18791 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18792 regno
= micromips_to_32_reg_d_map
[regno
];
18793 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18794 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18799 /* Nothing else to do, just write it out. */
18800 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18801 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18803 buf
= write_compressed_insn (buf
, insn
, 4);
18805 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18806 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18811 insn
= read_compressed_insn (buf
, 4);
18813 /* Relax 32-bit branches to a sequence of instructions. */
18814 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18815 _("relaxed out-of-range branch into a jump"));
18817 /* Set the short-delay-slot bit. */
18818 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18820 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18824 /* Reverse the branch. */
18825 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18826 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18827 insn
^= 0x20000000;
18828 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18829 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18830 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18831 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18832 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18833 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18834 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18835 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18836 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18837 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18838 insn
^= 0x00400000;
18839 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18840 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18841 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18842 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18843 insn
^= 0x00200000;
18844 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18846 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18848 insn
^= 0x00800000;
18854 /* Clear the and-link and short-delay-slot bits. */
18855 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18857 /* bltzal 0x40200000 bgezal 0x40600000 */
18858 /* bltzals 0x42200000 bgezals 0x42600000 */
18859 insn
&= ~0x02200000;
18862 /* Make a label at the end for use with the branch. */
18863 l
= symbol_new (micromips_label_name (), asec
, fragp
->fr_fix
, fragp
);
18864 micromips_label_inc ();
18865 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18868 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18869 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18870 fixp
->fx_file
= fragp
->fr_file
;
18871 fixp
->fx_line
= fragp
->fr_line
;
18873 /* Branch over the jump. */
18874 buf
= write_compressed_insn (buf
, insn
, 4);
18880 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18882 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18888 unsigned long jal
= (short_ds
|| nods
18889 ? 0x74000000 : 0xf4000000); /* jal/s */
18891 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18892 insn
= al
? jal
: 0xd4000000;
18894 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18895 fragp
->fr_symbol
, fragp
->fr_offset
,
18896 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18897 fixp
->fx_file
= fragp
->fr_file
;
18898 fixp
->fx_line
= fragp
->fr_line
;
18900 buf
= write_compressed_insn (buf
, insn
, 4);
18902 if (compact
|| nods
)
18906 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18908 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18913 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18915 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18916 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18917 insn
|= at
<< MICROMIPSOP_SH_RT
;
18919 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18920 fragp
->fr_symbol
, fragp
->fr_offset
,
18921 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18922 fixp
->fx_file
= fragp
->fr_file
;
18923 fixp
->fx_line
= fragp
->fr_line
;
18925 buf
= write_compressed_insn (buf
, insn
, 4);
18927 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18928 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18929 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18931 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18932 fragp
->fr_symbol
, fragp
->fr_offset
,
18933 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18934 fixp
->fx_file
= fragp
->fr_file
;
18935 fixp
->fx_line
= fragp
->fr_line
;
18937 buf
= write_compressed_insn (buf
, insn
, 4);
18942 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18943 insn
|= at
<< MICROMIPSOP_SH_RS
;
18945 buf
= write_compressed_insn (buf
, insn
, 4);
18947 if (compact
|| nods
)
18949 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18953 /* jr/jrc/jalr/jalrs $at */
18954 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18955 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18957 insn
= al
? jalr
: jr
;
18958 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18960 buf
= write_compressed_insn (buf
, insn
, 2);
18965 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18967 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18972 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18976 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18979 const struct mips_int_operand
*operand
;
18982 unsigned int user_length
;
18983 bfd_boolean need_reloc
;
18984 unsigned long insn
;
18989 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
18990 operand
= mips16_immed_operand (type
, FALSE
);
18992 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
18993 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
18994 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
18996 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
18997 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
18998 || (operand
->root
.type
== OP_PCREL
&& !mac
19000 : !bfd_is_abs_section (symsec
)));
19002 if (operand
->root
.type
== OP_PCREL
&& !mac
)
19004 const struct mips_pcrel_operand
*pcrel_op
;
19006 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
19008 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
19010 if (!mips_ignore_branch_isa
19011 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
19012 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19013 _("branch to a symbol in another ISA mode"));
19014 else if ((fragp
->fr_offset
& 0x1) != 0)
19015 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19016 _("branch to misaligned address (0x%lx)"),
19017 (long) (resolve_symbol_value (fragp
->fr_symbol
)
19018 + (fragp
->fr_offset
& ~1)));
19021 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
19023 /* Make sure the section winds up with the alignment we have
19025 if (operand
->shift
> 0)
19026 record_alignment (asec
, operand
->shift
);
19029 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
19030 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
19033 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19034 _("macro instruction expanded into multiple "
19035 "instructions in a branch delay slot"));
19037 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19038 _("extended instruction in a branch delay slot"));
19040 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
19041 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19042 _("macro instruction expanded into multiple "
19045 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19047 insn
= read_compressed_insn (buf
, 2);
19049 insn
|= MIPS16_EXTEND
;
19051 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
19053 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
19065 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
19066 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
19068 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
19074 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
19076 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19077 fragp
->fr_symbol
, fragp
->fr_offset
,
19078 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
19079 fixp
->fx_file
= fragp
->fr_file
;
19080 fixp
->fx_line
= fragp
->fr_line
;
19082 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
19083 fragp
->fr_symbol
, fragp
->fr_offset
,
19084 FALSE
, BFD_RELOC_MIPS16_LO16
);
19085 fixp
->fx_file
= fragp
->fr_file
;
19086 fixp
->fx_line
= fragp
->fr_line
;
19091 switch (insn
& 0xf800)
19093 case 0x0800: /* ADDIU */
19094 reg
= (insn
>> 8) & 0x7;
19095 op
= 0xf0004800 | (reg
<< 8);
19097 case 0xb000: /* LW */
19098 reg
= (insn
>> 8) & 0x7;
19099 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
19101 case 0xf800: /* I64 */
19102 reg
= (insn
>> 5) & 0x7;
19103 switch (insn
& 0x0700)
19105 case 0x0400: /* LD */
19106 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
19108 case 0x0600: /* DADDIU */
19109 op
= 0xf000fd00 | (reg
<< 5);
19119 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19120 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19121 buf
= write_compressed_insn (buf
, new, 4);
19124 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19125 buf
= write_compressed_insn (buf
, new, 4);
19127 op
|= mips16_immed_extend (val
, 16);
19128 buf
= write_compressed_insn (buf
, op
, 4);
19130 fragp
->fr_fix
+= e2
? 8 : 12;
19134 unsigned int length
= ext
? 4 : 2;
19138 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19145 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19150 if (mac
|| reloc
== BFD_RELOC_NONE
)
19151 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19152 _("unsupported relocation"));
19155 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19156 fragp
->fr_symbol
, fragp
->fr_offset
,
19158 fixp
->fx_file
= fragp
->fr_file
;
19159 fixp
->fx_line
= fragp
->fr_line
;
19162 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19163 _("invalid unextended operand value"));
19166 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19167 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19169 gas_assert (mips16_opcode_length (insn
) == length
);
19170 write_compressed_insn (buf
, insn
, length
);
19171 fragp
->fr_fix
+= length
;
19176 relax_substateT subtype
= fragp
->fr_subtype
;
19177 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19178 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19179 unsigned int first
, second
;
19182 first
= RELAX_FIRST (subtype
);
19183 second
= RELAX_SECOND (subtype
);
19184 fixp
= (fixS
*) fragp
->fr_opcode
;
19186 /* If the delay slot chosen does not match the size of the instruction,
19187 then emit a warning. */
19188 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19189 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19194 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19195 | RELAX_DELAY_SLOT_SIZE_FIRST
19196 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19197 msg
= macro_warning (s
);
19199 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19203 /* Possibly emit a warning if we've chosen the longer option. */
19204 if (use_second
== second_longer
)
19210 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19211 msg
= macro_warning (s
);
19213 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19217 /* Go through all the fixups for the first sequence. Disable them
19218 (by marking them as done) if we're going to use the second
19219 sequence instead. */
19221 && fixp
->fx_frag
== fragp
19222 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19224 if (subtype
& RELAX_USE_SECOND
)
19226 fixp
= fixp
->fx_next
;
19229 /* Go through the fixups for the second sequence. Disable them if
19230 we're going to use the first sequence, otherwise adjust their
19231 addresses to account for the relaxation. */
19232 while (fixp
&& fixp
->fx_frag
== fragp
)
19234 if (subtype
& RELAX_USE_SECOND
)
19235 fixp
->fx_where
-= first
;
19238 fixp
= fixp
->fx_next
;
19241 /* Now modify the frag contents. */
19242 if (subtype
& RELAX_USE_SECOND
)
19246 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19247 memmove (start
, start
+ first
, second
);
19248 fragp
->fr_fix
-= first
;
19251 fragp
->fr_fix
-= second
;
19255 /* This function is called after the relocs have been generated.
19256 We've been storing mips16 text labels as odd. Here we convert them
19257 back to even for the convenience of the debugger. */
19260 mips_frob_file_after_relocs (void)
19263 unsigned int count
, i
;
19265 syms
= bfd_get_outsymbols (stdoutput
);
19266 count
= bfd_get_symcount (stdoutput
);
19267 for (i
= 0; i
< count
; i
++, syms
++)
19268 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19269 && ((*syms
)->value
& 1) != 0)
19271 (*syms
)->value
&= ~1;
19272 /* If the symbol has an odd size, it was probably computed
19273 incorrectly, so adjust that as well. */
19274 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19275 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19279 /* This function is called whenever a label is defined, including fake
19280 labels instantiated off the dot special symbol. It is used when
19281 handling branch delays; if a branch has a label, we assume we cannot
19282 move it. This also bumps the value of the symbol by 1 in compressed
19286 mips_record_label (symbolS
*sym
)
19288 segment_info_type
*si
= seg_info (now_seg
);
19289 struct insn_label_list
*l
;
19291 if (free_insn_labels
== NULL
)
19292 l
= XNEW (struct insn_label_list
);
19295 l
= free_insn_labels
;
19296 free_insn_labels
= l
->next
;
19300 l
->next
= si
->label_list
;
19301 si
->label_list
= l
;
19304 /* This function is called as tc_frob_label() whenever a label is defined
19305 and adds a DWARF-2 record we only want for true labels. */
19308 mips_define_label (symbolS
*sym
)
19310 mips_record_label (sym
);
19311 dwarf2_emit_label (sym
);
19314 /* This function is called by tc_new_dot_label whenever a new dot symbol
19318 mips_add_dot_label (symbolS
*sym
)
19320 mips_record_label (sym
);
19321 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19322 mips_compressed_mark_label (sym
);
19325 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19326 static unsigned int
19327 mips_convert_ase_flags (int ase
)
19329 unsigned int ext_ases
= 0;
19332 ext_ases
|= AFL_ASE_DSP
;
19333 if (ase
& ASE_DSPR2
)
19334 ext_ases
|= AFL_ASE_DSPR2
;
19335 if (ase
& ASE_DSPR3
)
19336 ext_ases
|= AFL_ASE_DSPR3
;
19338 ext_ases
|= AFL_ASE_EVA
;
19340 ext_ases
|= AFL_ASE_MCU
;
19341 if (ase
& ASE_MDMX
)
19342 ext_ases
|= AFL_ASE_MDMX
;
19343 if (ase
& ASE_MIPS3D
)
19344 ext_ases
|= AFL_ASE_MIPS3D
;
19346 ext_ases
|= AFL_ASE_MT
;
19347 if (ase
& ASE_SMARTMIPS
)
19348 ext_ases
|= AFL_ASE_SMARTMIPS
;
19349 if (ase
& ASE_VIRT
)
19350 ext_ases
|= AFL_ASE_VIRT
;
19352 ext_ases
|= AFL_ASE_MSA
;
19354 ext_ases
|= AFL_ASE_XPA
;
19355 if (ase
& ASE_MIPS16E2
)
19356 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19358 ext_ases
|= AFL_ASE_CRC
;
19359 if (ase
& ASE_GINV
)
19360 ext_ases
|= AFL_ASE_GINV
;
19361 if (ase
& ASE_LOONGSON_MMI
)
19362 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19363 if (ase
& ASE_LOONGSON_CAM
)
19364 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19365 if (ase
& ASE_LOONGSON_EXT
)
19366 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19367 if (ase
& ASE_LOONGSON_EXT2
)
19368 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19372 /* Some special processing for a MIPS ELF file. */
19375 mips_elf_final_processing (void)
19378 Elf_Internal_ABIFlags_v0 flags
;
19382 switch (file_mips_opts
.isa
)
19385 flags
.isa_level
= 1;
19388 flags
.isa_level
= 2;
19391 flags
.isa_level
= 3;
19394 flags
.isa_level
= 4;
19397 flags
.isa_level
= 5;
19400 flags
.isa_level
= 32;
19404 flags
.isa_level
= 32;
19408 flags
.isa_level
= 32;
19412 flags
.isa_level
= 32;
19416 flags
.isa_level
= 32;
19420 flags
.isa_level
= 64;
19424 flags
.isa_level
= 64;
19428 flags
.isa_level
= 64;
19432 flags
.isa_level
= 64;
19436 flags
.isa_level
= 64;
19441 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19442 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19443 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19444 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19446 flags
.cpr2_size
= AFL_REG_NONE
;
19447 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19448 Tag_GNU_MIPS_ABI_FP
);
19449 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19450 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19451 if (file_ase_mips16
)
19452 flags
.ases
|= AFL_ASE_MIPS16
;
19453 if (file_ase_micromips
)
19454 flags
.ases
|= AFL_ASE_MICROMIPS
;
19456 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19457 || file_mips_opts
.fp
== 64)
19458 && file_mips_opts
.oddspreg
)
19459 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19462 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19463 ((Elf_External_ABIFlags_v0
*)
19466 /* Write out the register information. */
19467 if (mips_abi
!= N64_ABI
)
19471 s
.ri_gprmask
= mips_gprmask
;
19472 s
.ri_cprmask
[0] = mips_cprmask
[0];
19473 s
.ri_cprmask
[1] = mips_cprmask
[1];
19474 s
.ri_cprmask
[2] = mips_cprmask
[2];
19475 s
.ri_cprmask
[3] = mips_cprmask
[3];
19476 /* The gp_value field is set by the MIPS ELF backend. */
19478 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19479 ((Elf32_External_RegInfo
*)
19480 mips_regmask_frag
));
19484 Elf64_Internal_RegInfo s
;
19486 s
.ri_gprmask
= mips_gprmask
;
19488 s
.ri_cprmask
[0] = mips_cprmask
[0];
19489 s
.ri_cprmask
[1] = mips_cprmask
[1];
19490 s
.ri_cprmask
[2] = mips_cprmask
[2];
19491 s
.ri_cprmask
[3] = mips_cprmask
[3];
19492 /* The gp_value field is set by the MIPS ELF backend. */
19494 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19495 ((Elf64_External_RegInfo
*)
19496 mips_regmask_frag
));
19499 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19500 sort of BFD interface for this. */
19501 if (mips_any_noreorder
)
19502 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19503 if (mips_pic
!= NO_PIC
)
19505 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19506 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19509 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19511 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19512 defined at present; this might need to change in future. */
19513 if (file_ase_mips16
)
19514 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19515 if (file_ase_micromips
)
19516 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19517 if (file_mips_opts
.ase
& ASE_MDMX
)
19518 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19520 /* Set the MIPS ELF ABI flags. */
19521 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19522 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19523 else if (mips_abi
== O64_ABI
)
19524 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19525 else if (mips_abi
== EABI_ABI
)
19527 if (file_mips_opts
.gp
== 64)
19528 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19530 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19533 /* Nothing to do for N32_ABI or N64_ABI. */
19535 if (mips_32bitmode
)
19536 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19538 if (mips_nan2008
== 1)
19539 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19541 /* 32 bit code with 64 bit FP registers. */
19542 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19543 Tag_GNU_MIPS_ABI_FP
);
19544 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19545 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19548 typedef struct proc
{
19550 symbolS
*func_end_sym
;
19551 unsigned long reg_mask
;
19552 unsigned long reg_offset
;
19553 unsigned long fpreg_mask
;
19554 unsigned long fpreg_offset
;
19555 unsigned long frame_offset
;
19556 unsigned long frame_reg
;
19557 unsigned long pc_reg
;
19560 static procS cur_proc
;
19561 static procS
*cur_proc_ptr
;
19562 static int numprocs
;
19564 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19565 as "2", and a normal nop as "0". */
19567 #define NOP_OPCODE_MIPS 0
19568 #define NOP_OPCODE_MIPS16 1
19569 #define NOP_OPCODE_MICROMIPS 2
19572 mips_nop_opcode (void)
19574 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19575 return NOP_OPCODE_MICROMIPS
;
19576 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19577 return NOP_OPCODE_MIPS16
;
19579 return NOP_OPCODE_MIPS
;
19582 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19583 32-bit microMIPS NOPs here (if applicable). */
19586 mips_handle_align (fragS
*fragp
)
19590 int bytes
, size
, excess
;
19593 if (fragp
->fr_type
!= rs_align_code
)
19596 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19598 switch (nop_opcode
)
19600 case NOP_OPCODE_MICROMIPS
:
19601 opcode
= micromips_nop32_insn
.insn_opcode
;
19604 case NOP_OPCODE_MIPS16
:
19605 opcode
= mips16_nop_insn
.insn_opcode
;
19608 case NOP_OPCODE_MIPS
:
19610 opcode
= nop_insn
.insn_opcode
;
19615 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19616 excess
= bytes
% size
;
19618 /* Handle the leading part if we're not inserting a whole number of
19619 instructions, and make it the end of the fixed part of the frag.
19620 Try to fit in a short microMIPS NOP if applicable and possible,
19621 and use zeroes otherwise. */
19622 gas_assert (excess
< 4);
19623 fragp
->fr_fix
+= excess
;
19628 /* Fall through. */
19630 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19632 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19636 /* Fall through. */
19639 /* Fall through. */
19644 md_number_to_chars (p
, opcode
, size
);
19645 fragp
->fr_var
= size
;
19654 if (*input_line_pointer
== '-')
19656 ++input_line_pointer
;
19659 if (!ISDIGIT (*input_line_pointer
))
19660 as_bad (_("expected simple number"));
19661 if (input_line_pointer
[0] == '0')
19663 if (input_line_pointer
[1] == 'x')
19665 input_line_pointer
+= 2;
19666 while (ISXDIGIT (*input_line_pointer
))
19669 val
|= hex_value (*input_line_pointer
++);
19671 return negative
? -val
: val
;
19675 ++input_line_pointer
;
19676 while (ISDIGIT (*input_line_pointer
))
19679 val
|= *input_line_pointer
++ - '0';
19681 return negative
? -val
: val
;
19684 if (!ISDIGIT (*input_line_pointer
))
19686 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19687 *input_line_pointer
, *input_line_pointer
);
19688 as_warn (_("invalid number"));
19691 while (ISDIGIT (*input_line_pointer
))
19694 val
+= *input_line_pointer
++ - '0';
19696 return negative
? -val
: val
;
19699 /* The .file directive; just like the usual .file directive, but there
19700 is an initial number which is the ECOFF file index. In the non-ECOFF
19701 case .file implies DWARF-2. */
19704 s_mips_file (int x ATTRIBUTE_UNUSED
)
19706 static int first_file_directive
= 0;
19708 if (ECOFF_DEBUGGING
)
19717 filename
= dwarf2_directive_filename ();
19719 /* Versions of GCC up to 3.1 start files with a ".file"
19720 directive even for stabs output. Make sure that this
19721 ".file" is handled. Note that you need a version of GCC
19722 after 3.1 in order to support DWARF-2 on MIPS. */
19723 if (filename
!= NULL
&& ! first_file_directive
)
19725 (void) new_logical_line (filename
, -1);
19726 s_app_file_string (filename
, 0);
19728 first_file_directive
= 1;
19732 /* The .loc directive, implying DWARF-2. */
19735 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19737 if (!ECOFF_DEBUGGING
)
19738 dwarf2_directive_loc (0);
19741 /* The .end directive. */
19744 s_mips_end (int x ATTRIBUTE_UNUSED
)
19748 /* Following functions need their own .frame and .cprestore directives. */
19749 mips_frame_reg_valid
= 0;
19750 mips_cprestore_valid
= 0;
19752 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19755 demand_empty_rest_of_line ();
19760 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19761 as_warn (_(".end not in text section"));
19765 as_warn (_(".end directive without a preceding .ent directive"));
19766 demand_empty_rest_of_line ();
19772 gas_assert (S_GET_NAME (p
));
19773 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19774 as_warn (_(".end symbol does not match .ent symbol"));
19776 if (debug_type
== DEBUG_STABS
)
19777 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19781 as_warn (_(".end directive missing or unknown symbol"));
19783 /* Create an expression to calculate the size of the function. */
19784 if (p
&& cur_proc_ptr
)
19786 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19787 expressionS
*exp
= XNEW (expressionS
);
19790 exp
->X_op
= O_subtract
;
19791 exp
->X_add_symbol
= symbol_temp_new_now ();
19792 exp
->X_op_symbol
= p
;
19793 exp
->X_add_number
= 0;
19795 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19798 #ifdef md_flush_pending_output
19799 md_flush_pending_output ();
19802 /* Generate a .pdr section. */
19803 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19805 segT saved_seg
= now_seg
;
19806 subsegT saved_subseg
= now_subseg
;
19810 gas_assert (pdr_seg
);
19811 subseg_set (pdr_seg
, 0);
19813 /* Write the symbol. */
19814 exp
.X_op
= O_symbol
;
19815 exp
.X_add_symbol
= p
;
19816 exp
.X_add_number
= 0;
19817 emit_expr (&exp
, 4);
19819 fragp
= frag_more (7 * 4);
19821 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19822 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19823 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19824 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19825 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19826 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19827 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19829 subseg_set (saved_seg
, saved_subseg
);
19832 cur_proc_ptr
= NULL
;
19835 /* The .aent and .ent directives. */
19838 s_mips_ent (int aent
)
19842 symbolP
= get_symbol ();
19843 if (*input_line_pointer
== ',')
19844 ++input_line_pointer
;
19845 SKIP_WHITESPACE ();
19846 if (ISDIGIT (*input_line_pointer
)
19847 || *input_line_pointer
== '-')
19850 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19851 as_warn (_(".ent or .aent not in text section"));
19853 if (!aent
&& cur_proc_ptr
)
19854 as_warn (_("missing .end"));
19858 /* This function needs its own .frame and .cprestore directives. */
19859 mips_frame_reg_valid
= 0;
19860 mips_cprestore_valid
= 0;
19862 cur_proc_ptr
= &cur_proc
;
19863 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19865 cur_proc_ptr
->func_sym
= symbolP
;
19869 if (debug_type
== DEBUG_STABS
)
19870 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19871 S_GET_NAME (symbolP
));
19874 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19876 demand_empty_rest_of_line ();
19879 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19880 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19881 s_mips_frame is used so that we can set the PDR information correctly.
19882 We can't use the ecoff routines because they make reference to the ecoff
19883 symbol table (in the mdebug section). */
19886 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19888 if (ECOFF_DEBUGGING
)
19894 if (cur_proc_ptr
== (procS
*) NULL
)
19896 as_warn (_(".frame outside of .ent"));
19897 demand_empty_rest_of_line ();
19901 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19903 SKIP_WHITESPACE ();
19904 if (*input_line_pointer
++ != ','
19905 || get_absolute_expression_and_terminator (&val
) != ',')
19907 as_warn (_("bad .frame directive"));
19908 --input_line_pointer
;
19909 demand_empty_rest_of_line ();
19913 cur_proc_ptr
->frame_offset
= val
;
19914 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19916 demand_empty_rest_of_line ();
19920 /* The .fmask and .mask directives. If the mdebug section is present
19921 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19922 embedded targets, s_mips_mask is used so that we can set the PDR
19923 information correctly. We can't use the ecoff routines because they
19924 make reference to the ecoff symbol table (in the mdebug section). */
19927 s_mips_mask (int reg_type
)
19929 if (ECOFF_DEBUGGING
)
19930 s_ignore (reg_type
);
19935 if (cur_proc_ptr
== (procS
*) NULL
)
19937 as_warn (_(".mask/.fmask outside of .ent"));
19938 demand_empty_rest_of_line ();
19942 if (get_absolute_expression_and_terminator (&mask
) != ',')
19944 as_warn (_("bad .mask/.fmask directive"));
19945 --input_line_pointer
;
19946 demand_empty_rest_of_line ();
19950 off
= get_absolute_expression ();
19952 if (reg_type
== 'F')
19954 cur_proc_ptr
->fpreg_mask
= mask
;
19955 cur_proc_ptr
->fpreg_offset
= off
;
19959 cur_proc_ptr
->reg_mask
= mask
;
19960 cur_proc_ptr
->reg_offset
= off
;
19963 demand_empty_rest_of_line ();
19967 /* A table describing all the processors gas knows about. Names are
19968 matched in the order listed.
19970 To ease comparison, please keep this table in the same order as
19971 gcc's mips_cpu_info_table[]. */
19972 static const struct mips_cpu_info mips_cpu_info_table
[] =
19974 /* Entries for generic ISAs. */
19975 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19976 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19977 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19978 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
19979 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
19980 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
19981 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
19982 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
19983 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
19984 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
19985 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
19986 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
19987 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
19988 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
19989 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
19992 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19993 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
19994 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
19997 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
20000 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
20001 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
20002 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
20003 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
20004 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20005 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20006 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
20007 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
20008 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
20009 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
20010 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
20011 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
20012 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
20013 /* ST Microelectronics Loongson 2E and 2F cores. */
20014 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
20015 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
20018 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
20019 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
20020 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
20021 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
20022 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
20023 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
20024 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
20025 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
20026 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
20027 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
20028 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
20029 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
20030 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
20031 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
20032 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
20035 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20036 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20037 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20038 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
20040 /* MIPS 32 Release 2 */
20041 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20042 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20043 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20044 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20045 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20046 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20047 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20048 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20049 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20050 ISA_MIPS32R2
, CPU_MIPS32R2
},
20051 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20052 ISA_MIPS32R2
, CPU_MIPS32R2
},
20053 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20054 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20055 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20056 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20057 /* Deprecated forms of the above. */
20058 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20059 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20060 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20061 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20062 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20063 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20064 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20065 /* Deprecated forms of the above. */
20066 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20067 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20068 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20069 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20070 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20071 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20072 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20073 /* Deprecated forms of the above. */
20074 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20075 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20076 /* 34Kn is a 34kc without DSP. */
20077 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20078 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20079 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20080 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20081 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20082 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20083 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20084 /* Deprecated forms of the above. */
20085 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20086 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20087 /* 1004K cores are multiprocessor versions of the 34K. */
20088 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20089 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20090 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20091 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20092 /* interaptiv is the new name for 1004kf. */
20093 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20094 { "interaptiv-mr2", 0,
20095 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
20096 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
20097 /* M5100 family. */
20098 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20099 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20100 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20101 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20104 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20105 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20106 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20107 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20109 /* Broadcom SB-1 CPU core. */
20110 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20111 /* Broadcom SB-1A CPU core. */
20112 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20114 /* MIPS 64 Release 2. */
20115 /* Loongson CPU core. */
20116 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20117 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20118 ISA_MIPS64R2
, CPU_GS464
},
20119 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20120 ISA_MIPS64R2
, CPU_GS464
},
20121 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20122 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20123 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20124 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20126 /* Cavium Networks Octeon CPU core. */
20127 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20128 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20129 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20130 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20133 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20136 XLP is mostly like XLR, with the prominent exception that it is
20137 MIPS64R2 rather than MIPS64. */
20138 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20140 /* MIPS 64 Release 6. */
20141 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20142 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20143 ISA_MIPS64R6
, CPU_MIPS64R6
},
20144 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20147 { NULL
, 0, 0, 0, 0 }
20151 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20152 with a final "000" replaced by "k". Ignore case.
20154 Note: this function is shared between GCC and GAS. */
20157 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20159 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20160 given
++, canonical
++;
20162 return ((*given
== 0 && *canonical
== 0)
20163 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20167 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20168 CPU name. We've traditionally allowed a lot of variation here.
20170 Note: this function is shared between GCC and GAS. */
20173 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20175 /* First see if the name matches exactly, or with a final "000"
20176 turned into "k". */
20177 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20180 /* If not, try comparing based on numerical designation alone.
20181 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20182 if (TOLOWER (*given
) == 'r')
20184 if (!ISDIGIT (*given
))
20187 /* Skip over some well-known prefixes in the canonical name,
20188 hoping to find a number there too. */
20189 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20191 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20193 else if (TOLOWER (canonical
[0]) == 'r')
20196 return mips_strict_matching_cpu_name_p (canonical
, given
);
20200 /* Parse an option that takes the name of a processor as its argument.
20201 OPTION is the name of the option and CPU_STRING is the argument.
20202 Return the corresponding processor enumeration if the CPU_STRING is
20203 recognized, otherwise report an error and return null.
20205 A similar function exists in GCC. */
20207 static const struct mips_cpu_info
*
20208 mips_parse_cpu (const char *option
, const char *cpu_string
)
20210 const struct mips_cpu_info
*p
;
20212 /* 'from-abi' selects the most compatible architecture for the given
20213 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20214 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20215 version. Look first at the -mgp options, if given, otherwise base
20216 the choice on MIPS_DEFAULT_64BIT.
20218 Treat NO_ABI like the EABIs. One reason to do this is that the
20219 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20220 architecture. This code picks MIPS I for 'mips' and MIPS III for
20221 'mips64', just as we did in the days before 'from-abi'. */
20222 if (strcasecmp (cpu_string
, "from-abi") == 0)
20224 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20225 return mips_cpu_info_from_isa (ISA_MIPS1
);
20227 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20228 return mips_cpu_info_from_isa (ISA_MIPS3
);
20230 if (file_mips_opts
.gp
>= 0)
20231 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20232 ? ISA_MIPS1
: ISA_MIPS3
);
20234 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20239 /* 'default' has traditionally been a no-op. Probably not very useful. */
20240 if (strcasecmp (cpu_string
, "default") == 0)
20243 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20244 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20247 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20251 /* Return the canonical processor information for ISA (a member of the
20252 ISA_MIPS* enumeration). */
20254 static const struct mips_cpu_info
*
20255 mips_cpu_info_from_isa (int isa
)
20259 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20260 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20261 && isa
== mips_cpu_info_table
[i
].isa
)
20262 return (&mips_cpu_info_table
[i
]);
20267 static const struct mips_cpu_info
*
20268 mips_cpu_info_from_arch (int arch
)
20272 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20273 if (arch
== mips_cpu_info_table
[i
].cpu
)
20274 return (&mips_cpu_info_table
[i
]);
20280 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20284 fprintf (stream
, "%24s", "");
20289 fprintf (stream
, ", ");
20293 if (*col_p
+ strlen (string
) > 72)
20295 fprintf (stream
, "\n%24s", "");
20299 fprintf (stream
, "%s", string
);
20300 *col_p
+= strlen (string
);
20306 md_show_usage (FILE *stream
)
20311 fprintf (stream
, _("\
20313 -EB generate big endian output\n\
20314 -EL generate little endian output\n\
20315 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20316 -G NUM allow referencing objects up to NUM bytes\n\
20317 implicitly with the gp register [default 8]\n"));
20318 fprintf (stream
, _("\
20319 -mips1 generate MIPS ISA I instructions\n\
20320 -mips2 generate MIPS ISA II instructions\n\
20321 -mips3 generate MIPS ISA III instructions\n\
20322 -mips4 generate MIPS ISA IV instructions\n\
20323 -mips5 generate MIPS ISA V instructions\n\
20324 -mips32 generate MIPS32 ISA instructions\n\
20325 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20326 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20327 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20328 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20329 -mips64 generate MIPS64 ISA instructions\n\
20330 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20331 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20332 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20333 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20334 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20338 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20339 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20340 show (stream
, "from-abi", &column
, &first
);
20341 fputc ('\n', stream
);
20343 fprintf (stream
, _("\
20344 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20345 -no-mCPU don't generate code specific to CPU.\n\
20346 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20350 show (stream
, "3900", &column
, &first
);
20351 show (stream
, "4010", &column
, &first
);
20352 show (stream
, "4100", &column
, &first
);
20353 show (stream
, "4650", &column
, &first
);
20354 fputc ('\n', stream
);
20356 fprintf (stream
, _("\
20357 -mips16 generate mips16 instructions\n\
20358 -no-mips16 do not generate mips16 instructions\n"));
20359 fprintf (stream
, _("\
20360 -mmips16e2 generate MIPS16e2 instructions\n\
20361 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20362 fprintf (stream
, _("\
20363 -mmicromips generate microMIPS instructions\n\
20364 -mno-micromips do not generate microMIPS instructions\n"));
20365 fprintf (stream
, _("\
20366 -msmartmips generate smartmips instructions\n\
20367 -mno-smartmips do not generate smartmips instructions\n"));
20368 fprintf (stream
, _("\
20369 -mdsp generate DSP instructions\n\
20370 -mno-dsp do not generate DSP instructions\n"));
20371 fprintf (stream
, _("\
20372 -mdspr2 generate DSP R2 instructions\n\
20373 -mno-dspr2 do not generate DSP R2 instructions\n"));
20374 fprintf (stream
, _("\
20375 -mdspr3 generate DSP R3 instructions\n\
20376 -mno-dspr3 do not generate DSP R3 instructions\n"));
20377 fprintf (stream
, _("\
20378 -mmt generate MT instructions\n\
20379 -mno-mt do not generate MT instructions\n"));
20380 fprintf (stream
, _("\
20381 -mmcu generate MCU instructions\n\
20382 -mno-mcu do not generate MCU instructions\n"));
20383 fprintf (stream
, _("\
20384 -mmsa generate MSA instructions\n\
20385 -mno-msa do not generate MSA instructions\n"));
20386 fprintf (stream
, _("\
20387 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20388 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20389 fprintf (stream
, _("\
20390 -mvirt generate Virtualization instructions\n\
20391 -mno-virt do not generate Virtualization instructions\n"));
20392 fprintf (stream
, _("\
20393 -mcrc generate CRC instructions\n\
20394 -mno-crc do not generate CRC instructions\n"));
20395 fprintf (stream
, _("\
20396 -mginv generate Global INValidate (GINV) instructions\n\
20397 -mno-ginv do not generate Global INValidate instructions\n"));
20398 fprintf (stream
, _("\
20399 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20400 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20401 fprintf (stream
, _("\
20402 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20403 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20404 fprintf (stream
, _("\
20405 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20406 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20407 fprintf (stream
, _("\
20408 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20409 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20410 fprintf (stream
, _("\
20411 -minsn32 only generate 32-bit microMIPS instructions\n\
20412 -mno-insn32 generate all microMIPS instructions\n"));
20413 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20414 fprintf (stream
, _("\
20415 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20416 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20418 fprintf (stream
, _("\
20419 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20420 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20422 fprintf (stream
, _("\
20423 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20424 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20425 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20426 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20427 -mfix-vr4120 work around certain VR4120 errata\n\
20428 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20429 -mfix-24k insert a nop after ERET and DERET instructions\n\
20430 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20431 -mfix-r5900 work around R5900 short loop errata\n\
20432 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20433 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20434 -msym32 assume all symbols have 32-bit values\n\
20435 -O0 do not remove unneeded NOPs, do not swap branches\n\
20436 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20437 -O2 remove unneeded NOPs and swap branches\n\
20438 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20439 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20440 fprintf (stream
, _("\
20441 -mhard-float allow floating-point instructions\n\
20442 -msoft-float do not allow floating-point instructions\n\
20443 -msingle-float only allow 32-bit floating-point operations\n\
20444 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20445 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20446 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20447 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20448 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20449 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20453 show (stream
, "legacy", &column
, &first
);
20454 show (stream
, "2008", &column
, &first
);
20456 fputc ('\n', stream
);
20458 fprintf (stream
, _("\
20459 -KPIC, -call_shared generate SVR4 position independent code\n\
20460 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20461 -mvxworks-pic generate VxWorks position independent code\n\
20462 -non_shared do not generate code that can operate with DSOs\n\
20463 -xgot assume a 32 bit GOT\n\
20464 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20465 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20466 position dependent (non shared) code\n\
20467 -mabi=ABI create ABI conformant object file for:\n"));
20471 show (stream
, "32", &column
, &first
);
20472 show (stream
, "o64", &column
, &first
);
20473 show (stream
, "n32", &column
, &first
);
20474 show (stream
, "64", &column
, &first
);
20475 show (stream
, "eabi", &column
, &first
);
20477 fputc ('\n', stream
);
20479 fprintf (stream
, _("\
20480 -32 create o32 ABI object file%s\n"),
20481 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20482 fprintf (stream
, _("\
20483 -n32 create n32 ABI object file%s\n"),
20484 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20485 fprintf (stream
, _("\
20486 -64 create 64 ABI object file%s\n"),
20487 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20492 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20494 if (HAVE_64BIT_SYMBOLS
)
20495 return dwarf2_format_64bit_irix
;
20497 return dwarf2_format_32bit
;
20502 mips_dwarf2_addr_size (void)
20504 if (HAVE_64BIT_OBJECTS
)
20510 /* Standard calling conventions leave the CFA at SP on entry. */
20512 mips_cfi_frame_initial_instructions (void)
20514 cfi_add_CFA_def_cfa_register (SP
);
20518 tc_mips_regname_to_dw2regnum (char *regname
)
20520 unsigned int regnum
= -1;
20523 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20529 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20530 Given a symbolic attribute NAME, return the proper integer value.
20531 Returns -1 if the attribute is not known. */
20534 mips_convert_symbolic_attribute (const char *name
)
20536 static const struct
20541 attribute_table
[] =
20543 #define T(tag) {#tag, tag}
20544 T (Tag_GNU_MIPS_ABI_FP
),
20545 T (Tag_GNU_MIPS_ABI_MSA
),
20553 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20554 if (streq (name
, attribute_table
[i
].name
))
20555 return attribute_table
[i
].tag
;
20563 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20565 mips_emit_delays ();
20567 as_warn (_("missing .end at end of assembly"));
20569 /* Just in case no code was emitted, do the consistency check. */
20570 file_mips_check_options ();
20572 /* Set a floating-point ABI if the user did not. */
20573 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20575 /* Perform consistency checks on the floating-point ABI. */
20576 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20577 Tag_GNU_MIPS_ABI_FP
);
20578 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20579 check_fpabi (fpabi
);
20583 /* Soft-float gets precedence over single-float, the two options should
20584 not be used together so this should not matter. */
20585 if (file_mips_opts
.soft_float
== 1)
20586 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20587 /* Single-float gets precedence over all double_float cases. */
20588 else if (file_mips_opts
.single_float
== 1)
20589 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20592 switch (file_mips_opts
.fp
)
20595 if (file_mips_opts
.gp
== 32)
20596 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20599 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20602 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20603 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20604 else if (file_mips_opts
.gp
== 32)
20605 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20607 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20612 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20613 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20617 /* Returns the relocation type required for a particular CFI encoding. */
20619 bfd_reloc_code_real_type
20620 mips_cfi_reloc_for_encoding (int encoding
)
20622 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20623 return BFD_RELOC_32_PCREL
;
20624 else return BFD_RELOC_NONE
;