1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float
;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float
;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32
= -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32
= -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float
= 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float
= 0;
265 static struct mips_set_options mips_opts
=
267 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
272 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask
;
279 unsigned long mips_cprmask
[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa
= ISA_UNKNOWN
;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d
;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx
;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips
;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp
;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2
;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt
;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch
= CPU_UNKNOWN
;
333 static const char *mips_arch_string
;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune
= CPU_UNKNOWN
;
338 static const char *mips_tune_string
;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode
= 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_RM7000 \
476 || mips_opts.arch == CPU_VR5500 \
479 /* Whether the processor uses hardware interlocks to protect reads
480 from the GPRs after they are loaded from memory, and thus does not
481 require nops to be inserted. This applies to instructions marked
482 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
484 #define gpr_interlocks \
485 (mips_opts.isa != ISA_MIPS1 \
486 || mips_opts.arch == CPU_R3900)
488 /* Whether the processor uses hardware interlocks to avoid delays
489 required by coprocessor instructions, and thus does not require
490 nops to be inserted. This applies to instructions marked
491 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
492 between instructions marked INSN_WRITE_COND_CODE and ones marked
493 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
494 levels I, II, and III. */
495 /* Itbl support may require additional care here. */
496 #define cop_interlocks \
497 ((mips_opts.isa != ISA_MIPS1 \
498 && mips_opts.isa != ISA_MIPS2 \
499 && mips_opts.isa != ISA_MIPS3) \
500 || mips_opts.arch == CPU_R4300 \
503 /* Whether the processor uses hardware interlocks to protect reads
504 from coprocessor registers after they are loaded from memory, and
505 thus does not require nops to be inserted. This applies to
506 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
507 requires at MIPS ISA level I. */
508 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
510 /* Is this a mfhi or mflo instruction? */
511 #define MF_HILO_INSN(PINFO) \
512 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
514 /* Returns true for a (non floating-point) coprocessor instruction. Reading
515 or writing the condition code is only possible on the coprocessors and
516 these insns are not marked with INSN_COP. Thus for these insns use the
517 condition-code flags unless this is the floating-point coprocessor. */
518 #define COP_INSN(PINFO) \
519 (PINFO != INSN_MACRO \
520 && (((PINFO) & INSN_COP) \
521 || ((PINFO) & (INSN_READ_COND_CODE | INSN_WRITE_COND_CODE) \
522 && ((PINFO) & (FP_S | FP_D)) == 0)))
524 /* MIPS PIC level. */
526 enum mips_pic_level mips_pic
;
528 /* 1 if we should generate 32 bit offsets from the $gp register in
529 SVR4_PIC mode. Currently has no meaning in other modes. */
530 static int mips_big_got
= 0;
532 /* 1 if trap instructions should used for overflow rather than break
534 static int mips_trap
= 0;
536 /* 1 if double width floating point constants should not be constructed
537 by assembling two single width halves into two single width floating
538 point registers which just happen to alias the double width destination
539 register. On some architectures this aliasing can be disabled by a bit
540 in the status register, and the setting of this bit cannot be determined
541 automatically at assemble time. */
542 static int mips_disable_float_construction
;
544 /* Non-zero if any .set noreorder directives were used. */
546 static int mips_any_noreorder
;
548 /* Non-zero if nops should be inserted when the register referenced in
549 an mfhi/mflo instruction is read in the next two instructions. */
550 static int mips_7000_hilo_fix
;
552 /* The size of objects in the small data section. */
553 static unsigned int g_switch_value
= 8;
554 /* Whether the -G option was used. */
555 static int g_switch_seen
= 0;
560 /* If we can determine in advance that GP optimization won't be
561 possible, we can skip the relaxation stuff that tries to produce
562 GP-relative references. This makes delay slot optimization work
565 This function can only provide a guess, but it seems to work for
566 gcc output. It needs to guess right for gcc, otherwise gcc
567 will put what it thinks is a GP-relative instruction in a branch
570 I don't know if a fix is needed for the SVR4_PIC mode. I've only
571 fixed it for the non-PIC mode. KR 95/04/07 */
572 static int nopic_need_relax (symbolS
*, int);
574 /* handle of the OPCODE hash table */
575 static struct hash_control
*op_hash
= NULL
;
577 /* The opcode hash table we use for the mips16. */
578 static struct hash_control
*mips16_op_hash
= NULL
;
580 /* This array holds the chars that always start a comment. If the
581 pre-processor is disabled, these aren't very useful */
582 const char comment_chars
[] = "#";
584 /* This array holds the chars that only start a comment at the beginning of
585 a line. If the line seems to have the form '# 123 filename'
586 .line and .file directives will appear in the pre-processed output */
587 /* Note that input_file.c hand checks for '#' at the beginning of the
588 first line of the input file. This is because the compiler outputs
589 #NO_APP at the beginning of its output. */
590 /* Also note that C style comments are always supported. */
591 const char line_comment_chars
[] = "#";
593 /* This array holds machine specific line separator characters. */
594 const char line_separator_chars
[] = ";";
596 /* Chars that can be used to separate mant from exp in floating point nums */
597 const char EXP_CHARS
[] = "eE";
599 /* Chars that mean this number is a floating point constant */
602 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
604 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
605 changed in read.c . Ideally it shouldn't have to know about it at all,
606 but nothing is ideal around here.
609 static char *insn_error
;
611 static int auto_align
= 1;
613 /* When outputting SVR4 PIC code, the assembler needs to know the
614 offset in the stack frame from which to restore the $gp register.
615 This is set by the .cprestore pseudo-op, and saved in this
617 static offsetT mips_cprestore_offset
= -1;
619 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
620 more optimizations, it can use a register value instead of a memory-saved
621 offset and even an other register than $gp as global pointer. */
622 static offsetT mips_cpreturn_offset
= -1;
623 static int mips_cpreturn_register
= -1;
624 static int mips_gp_register
= GP
;
625 static int mips_gprel_offset
= 0;
627 /* Whether mips_cprestore_offset has been set in the current function
628 (or whether it has already been warned about, if not). */
629 static int mips_cprestore_valid
= 0;
631 /* This is the register which holds the stack frame, as set by the
632 .frame pseudo-op. This is needed to implement .cprestore. */
633 static int mips_frame_reg
= SP
;
635 /* Whether mips_frame_reg has been set in the current function
636 (or whether it has already been warned about, if not). */
637 static int mips_frame_reg_valid
= 0;
639 /* To output NOP instructions correctly, we need to keep information
640 about the previous two instructions. */
642 /* Whether we are optimizing. The default value of 2 means to remove
643 unneeded NOPs and swap branch instructions when possible. A value
644 of 1 means to not swap branches. A value of 0 means to always
646 static int mips_optimize
= 2;
648 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
649 equivalent to seeing no -g option at all. */
650 static int mips_debug
= 0;
652 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
653 #define MAX_VR4130_NOPS 4
655 /* The maximum number of NOPs needed to fill delay slots. */
656 #define MAX_DELAY_NOPS 2
658 /* The maximum number of NOPs needed for any purpose. */
661 /* A list of previous instructions, with index 0 being the most recent.
662 We need to look back MAX_NOPS instructions when filling delay slots
663 or working around processor errata. We need to look back one
664 instruction further if we're thinking about using history[0] to
665 fill a branch delay slot. */
666 static struct mips_cl_insn history
[1 + MAX_NOPS
];
668 /* Nop instructions used by emit_nop. */
669 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
671 /* The appropriate nop for the current mode. */
672 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
674 /* If this is set, it points to a frag holding nop instructions which
675 were inserted before the start of a noreorder section. If those
676 nops turn out to be unnecessary, the size of the frag can be
678 static fragS
*prev_nop_frag
;
680 /* The number of nop instructions we created in prev_nop_frag. */
681 static int prev_nop_frag_holds
;
683 /* The number of nop instructions that we know we need in
685 static int prev_nop_frag_required
;
687 /* The number of instructions we've seen since prev_nop_frag. */
688 static int prev_nop_frag_since
;
690 /* For ECOFF and ELF, relocations against symbols are done in two
691 parts, with a HI relocation and a LO relocation. Each relocation
692 has only 16 bits of space to store an addend. This means that in
693 order for the linker to handle carries correctly, it must be able
694 to locate both the HI and the LO relocation. This means that the
695 relocations must appear in order in the relocation table.
697 In order to implement this, we keep track of each unmatched HI
698 relocation. We then sort them so that they immediately precede the
699 corresponding LO relocation. */
704 struct mips_hi_fixup
*next
;
707 /* The section this fixup is in. */
711 /* The list of unmatched HI relocs. */
713 static struct mips_hi_fixup
*mips_hi_fixup_list
;
715 /* The frag containing the last explicit relocation operator.
716 Null if explicit relocations have not been used. */
718 static fragS
*prev_reloc_op_frag
;
720 /* Map normal MIPS register numbers to mips16 register numbers. */
722 #define X ILLEGAL_REG
723 static const int mips32_to_16_reg_map
[] =
725 X
, X
, 2, 3, 4, 5, 6, 7,
726 X
, X
, X
, X
, X
, X
, X
, X
,
727 0, 1, X
, X
, X
, X
, X
, X
,
728 X
, X
, X
, X
, X
, X
, X
, X
732 /* Map mips16 register numbers to normal MIPS register numbers. */
734 static const unsigned int mips16_to_32_reg_map
[] =
736 16, 17, 2, 3, 4, 5, 6, 7
739 /* Classifies the kind of instructions we're interested in when
740 implementing -mfix-vr4120. */
741 enum fix_vr4120_class
{
748 NUM_FIX_VR4120_CLASSES
751 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
752 there must be at least one other instruction between an instruction
753 of type X and an instruction of type Y. */
754 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
756 /* True if -mfix-vr4120 is in force. */
757 static int mips_fix_vr4120
;
759 /* ...likewise -mfix-vr4130. */
760 static int mips_fix_vr4130
;
762 /* We don't relax branches by default, since this causes us to expand
763 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
764 fail to compute the offset before expanding the macro to the most
765 efficient expansion. */
767 static int mips_relax_branch
;
769 /* The expansion of many macros depends on the type of symbol that
770 they refer to. For example, when generating position-dependent code,
771 a macro that refers to a symbol may have two different expansions,
772 one which uses GP-relative addresses and one which uses absolute
773 addresses. When generating SVR4-style PIC, a macro may have
774 different expansions for local and global symbols.
776 We handle these situations by generating both sequences and putting
777 them in variant frags. In position-dependent code, the first sequence
778 will be the GP-relative one and the second sequence will be the
779 absolute one. In SVR4 PIC, the first sequence will be for global
780 symbols and the second will be for local symbols.
782 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
783 SECOND are the lengths of the two sequences in bytes. These fields
784 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
785 the subtype has the following flags:
788 Set if it has been decided that we should use the second
789 sequence instead of the first.
792 Set in the first variant frag if the macro's second implementation
793 is longer than its first. This refers to the macro as a whole,
794 not an individual relaxation.
797 Set in the first variant frag if the macro appeared in a .set nomacro
798 block and if one alternative requires a warning but the other does not.
801 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
804 The frag's "opcode" points to the first fixup for relaxable code.
806 Relaxable macros are generated using a sequence such as:
808 relax_start (SYMBOL);
809 ... generate first expansion ...
811 ... generate second expansion ...
814 The code and fixups for the unwanted alternative are discarded
815 by md_convert_frag. */
816 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
818 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
819 #define RELAX_SECOND(X) ((X) & 0xff)
820 #define RELAX_USE_SECOND 0x10000
821 #define RELAX_SECOND_LONGER 0x20000
822 #define RELAX_NOMACRO 0x40000
823 #define RELAX_DELAY_SLOT 0x80000
825 /* Branch without likely bit. If label is out of range, we turn:
827 beq reg1, reg2, label
837 with the following opcode replacements:
844 bltzal <-> bgezal (with jal label instead of j label)
846 Even though keeping the delay slot instruction in the delay slot of
847 the branch would be more efficient, it would be very tricky to do
848 correctly, because we'd have to introduce a variable frag *after*
849 the delay slot instruction, and expand that instead. Let's do it
850 the easy way for now, even if the branch-not-taken case now costs
851 one additional instruction. Out-of-range branches are not supposed
852 to be common, anyway.
854 Branch likely. If label is out of range, we turn:
856 beql reg1, reg2, label
857 delay slot (annulled if branch not taken)
866 delay slot (executed only if branch taken)
869 It would be possible to generate a shorter sequence by losing the
870 likely bit, generating something like:
875 delay slot (executed only if branch taken)
887 bltzall -> bgezal (with jal label instead of j label)
888 bgezall -> bltzal (ditto)
891 but it's not clear that it would actually improve performance. */
892 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
895 | ((toofar) ? 1 : 0) \
897 | ((likely) ? 4 : 0) \
898 | ((uncond) ? 8 : 0)))
899 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
900 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
901 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
902 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
903 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
905 /* For mips16 code, we use an entirely different form of relaxation.
906 mips16 supports two versions of most instructions which take
907 immediate values: a small one which takes some small value, and a
908 larger one which takes a 16 bit value. Since branches also follow
909 this pattern, relaxing these values is required.
911 We can assemble both mips16 and normal MIPS code in a single
912 object. Therefore, we need to support this type of relaxation at
913 the same time that we support the relaxation described above. We
914 use the high bit of the subtype field to distinguish these cases.
916 The information we store for this type of relaxation is the
917 argument code found in the opcode file for this relocation, whether
918 the user explicitly requested a small or extended form, and whether
919 the relocation is in a jump or jal delay slot. That tells us the
920 size of the value, and how it should be stored. We also store
921 whether the fragment is considered to be extended or not. We also
922 store whether this is known to be a branch to a different section,
923 whether we have tried to relax this frag yet, and whether we have
924 ever extended a PC relative fragment because of a shift count. */
925 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
928 | ((small) ? 0x100 : 0) \
929 | ((ext) ? 0x200 : 0) \
930 | ((dslot) ? 0x400 : 0) \
931 | ((jal_dslot) ? 0x800 : 0))
932 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
933 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
934 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
935 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
936 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
937 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
938 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
939 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
940 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
941 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
942 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
943 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
945 /* Is the given value a sign-extended 32-bit value? */
946 #define IS_SEXT_32BIT_NUM(x) \
947 (((x) &~ (offsetT) 0x7fffffff) == 0 \
948 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
950 /* Is the given value a sign-extended 16-bit value? */
951 #define IS_SEXT_16BIT_NUM(x) \
952 (((x) &~ (offsetT) 0x7fff) == 0 \
953 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
955 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
956 #define IS_ZEXT_32BIT_NUM(x) \
957 (((x) &~ (offsetT) 0xffffffff) == 0 \
958 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
960 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
961 VALUE << SHIFT. VALUE is evaluated exactly once. */
962 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
963 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
964 | (((VALUE) & (MASK)) << (SHIFT)))
966 /* Extract bits MASK << SHIFT from STRUCT and shift them right
968 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
969 (((STRUCT) >> (SHIFT)) & (MASK))
971 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
972 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
974 include/opcode/mips.h specifies operand fields using the macros
975 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
976 with "MIPS16OP" instead of "OP". */
977 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
978 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
979 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
980 INSERT_BITS ((INSN).insn_opcode, VALUE, \
981 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
983 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
984 #define EXTRACT_OPERAND(FIELD, INSN) \
985 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
986 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
987 EXTRACT_BITS ((INSN).insn_opcode, \
988 MIPS16OP_MASK_##FIELD, \
991 /* Global variables used when generating relaxable macros. See the
992 comment above RELAX_ENCODE for more details about how relaxation
995 /* 0 if we're not emitting a relaxable macro.
996 1 if we're emitting the first of the two relaxation alternatives.
997 2 if we're emitting the second alternative. */
1000 /* The first relaxable fixup in the current frag. (In other words,
1001 the first fixup that refers to relaxable code.) */
1004 /* sizes[0] says how many bytes of the first alternative are stored in
1005 the current frag. Likewise sizes[1] for the second alternative. */
1006 unsigned int sizes
[2];
1008 /* The symbol on which the choice of sequence depends. */
1012 /* Global variables used to decide whether a macro needs a warning. */
1014 /* True if the macro is in a branch delay slot. */
1015 bfd_boolean delay_slot_p
;
1017 /* For relaxable macros, sizes[0] is the length of the first alternative
1018 in bytes and sizes[1] is the length of the second alternative.
1019 For non-relaxable macros, both elements give the length of the
1021 unsigned int sizes
[2];
1023 /* The first variant frag for this macro. */
1025 } mips_macro_warning
;
1027 /* Prototypes for static functions. */
1029 #define internalError() \
1030 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1032 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1034 static void append_insn
1035 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
1036 static void mips_no_prev_insn (void);
1037 static void mips16_macro_build
1038 (expressionS
*, const char *, const char *, va_list);
1039 static void load_register (int, expressionS
*, int);
1040 static void macro_start (void);
1041 static void macro_end (void);
1042 static void macro (struct mips_cl_insn
* ip
);
1043 static void mips16_macro (struct mips_cl_insn
* ip
);
1044 #ifdef LOSING_COMPILER
1045 static void macro2 (struct mips_cl_insn
* ip
);
1047 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1048 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1049 static void mips16_immed
1050 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1051 unsigned long *, bfd_boolean
*, unsigned short *);
1052 static size_t my_getSmallExpression
1053 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1054 static void my_getExpression (expressionS
*, char *);
1055 static void s_align (int);
1056 static void s_change_sec (int);
1057 static void s_change_section (int);
1058 static void s_cons (int);
1059 static void s_float_cons (int);
1060 static void s_mips_globl (int);
1061 static void s_option (int);
1062 static void s_mipsset (int);
1063 static void s_abicalls (int);
1064 static void s_cpload (int);
1065 static void s_cpsetup (int);
1066 static void s_cplocal (int);
1067 static void s_cprestore (int);
1068 static void s_cpreturn (int);
1069 static void s_dtprelword (int);
1070 static void s_dtpreldword (int);
1071 static void s_gpvalue (int);
1072 static void s_gpword (int);
1073 static void s_gpdword (int);
1074 static void s_cpadd (int);
1075 static void s_insn (int);
1076 static void md_obj_begin (void);
1077 static void md_obj_end (void);
1078 static void s_mips_ent (int);
1079 static void s_mips_end (int);
1080 static void s_mips_frame (int);
1081 static void s_mips_mask (int reg_type
);
1082 static void s_mips_stab (int);
1083 static void s_mips_weakext (int);
1084 static void s_mips_file (int);
1085 static void s_mips_loc (int);
1086 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1087 static int relaxed_branch_length (fragS
*, asection
*, int);
1088 static int validate_mips_insn (const struct mips_opcode
*);
1090 /* Table and functions used to map between CPU/ISA names, and
1091 ISA levels, and CPU numbers. */
1093 struct mips_cpu_info
1095 const char *name
; /* CPU or ISA name. */
1096 int flags
; /* ASEs available, or ISA flag. */
1097 int isa
; /* ISA level. */
1098 int cpu
; /* CPU number (default CPU if ISA). */
1101 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1102 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1103 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1104 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1105 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1106 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1107 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1109 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1110 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1111 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1115 The following pseudo-ops from the Kane and Heinrich MIPS book
1116 should be defined here, but are currently unsupported: .alias,
1117 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1119 The following pseudo-ops from the Kane and Heinrich MIPS book are
1120 specific to the type of debugging information being generated, and
1121 should be defined by the object format: .aent, .begin, .bend,
1122 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1125 The following pseudo-ops from the Kane and Heinrich MIPS book are
1126 not MIPS CPU specific, but are also not specific to the object file
1127 format. This file is probably the best place to define them, but
1128 they are not currently supported: .asm0, .endr, .lab, .struct. */
1130 static const pseudo_typeS mips_pseudo_table
[] =
1132 /* MIPS specific pseudo-ops. */
1133 {"option", s_option
, 0},
1134 {"set", s_mipsset
, 0},
1135 {"rdata", s_change_sec
, 'r'},
1136 {"sdata", s_change_sec
, 's'},
1137 {"livereg", s_ignore
, 0},
1138 {"abicalls", s_abicalls
, 0},
1139 {"cpload", s_cpload
, 0},
1140 {"cpsetup", s_cpsetup
, 0},
1141 {"cplocal", s_cplocal
, 0},
1142 {"cprestore", s_cprestore
, 0},
1143 {"cpreturn", s_cpreturn
, 0},
1144 {"dtprelword", s_dtprelword
, 0},
1145 {"dtpreldword", s_dtpreldword
, 0},
1146 {"gpvalue", s_gpvalue
, 0},
1147 {"gpword", s_gpword
, 0},
1148 {"gpdword", s_gpdword
, 0},
1149 {"cpadd", s_cpadd
, 0},
1150 {"insn", s_insn
, 0},
1152 /* Relatively generic pseudo-ops that happen to be used on MIPS
1154 {"asciiz", stringer
, 8 + 1},
1155 {"bss", s_change_sec
, 'b'},
1157 {"half", s_cons
, 1},
1158 {"dword", s_cons
, 3},
1159 {"weakext", s_mips_weakext
, 0},
1160 {"origin", s_org
, 0},
1161 {"repeat", s_rept
, 0},
1163 /* These pseudo-ops are defined in read.c, but must be overridden
1164 here for one reason or another. */
1165 {"align", s_align
, 0},
1166 {"byte", s_cons
, 0},
1167 {"data", s_change_sec
, 'd'},
1168 {"double", s_float_cons
, 'd'},
1169 {"float", s_float_cons
, 'f'},
1170 {"globl", s_mips_globl
, 0},
1171 {"global", s_mips_globl
, 0},
1172 {"hword", s_cons
, 1},
1174 {"long", s_cons
, 2},
1175 {"octa", s_cons
, 4},
1176 {"quad", s_cons
, 3},
1177 {"section", s_change_section
, 0},
1178 {"short", s_cons
, 1},
1179 {"single", s_float_cons
, 'f'},
1180 {"stabn", s_mips_stab
, 'n'},
1181 {"text", s_change_sec
, 't'},
1182 {"word", s_cons
, 2},
1184 { "extern", ecoff_directive_extern
, 0},
1189 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1191 /* These pseudo-ops should be defined by the object file format.
1192 However, a.out doesn't support them, so we have versions here. */
1193 {"aent", s_mips_ent
, 1},
1194 {"bgnb", s_ignore
, 0},
1195 {"end", s_mips_end
, 0},
1196 {"endb", s_ignore
, 0},
1197 {"ent", s_mips_ent
, 0},
1198 {"file", s_mips_file
, 0},
1199 {"fmask", s_mips_mask
, 'F'},
1200 {"frame", s_mips_frame
, 0},
1201 {"loc", s_mips_loc
, 0},
1202 {"mask", s_mips_mask
, 'R'},
1203 {"verstamp", s_ignore
, 0},
1207 extern void pop_insert (const pseudo_typeS
*);
1210 mips_pop_insert (void)
1212 pop_insert (mips_pseudo_table
);
1213 if (! ECOFF_DEBUGGING
)
1214 pop_insert (mips_nonecoff_pseudo_table
);
1217 /* Symbols labelling the current insn. */
1219 struct insn_label_list
1221 struct insn_label_list
*next
;
1225 static struct insn_label_list
*free_insn_labels
;
1226 #define label_list tc_segment_info_data.labels
1228 static void mips_clear_insn_labels (void);
1231 mips_clear_insn_labels (void)
1233 register struct insn_label_list
**pl
;
1234 segment_info_type
*si
;
1238 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1241 si
= seg_info (now_seg
);
1242 *pl
= si
->label_list
;
1243 si
->label_list
= NULL
;
1248 static char *expr_end
;
1250 /* Expressions which appear in instructions. These are set by
1253 static expressionS imm_expr
;
1254 static expressionS imm2_expr
;
1255 static expressionS offset_expr
;
1257 /* Relocs associated with imm_expr and offset_expr. */
1259 static bfd_reloc_code_real_type imm_reloc
[3]
1260 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1261 static bfd_reloc_code_real_type offset_reloc
[3]
1262 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1264 /* These are set by mips16_ip if an explicit extension is used. */
1266 static bfd_boolean mips16_small
, mips16_ext
;
1269 /* The pdr segment for per procedure frame/regmask info. Not used for
1272 static segT pdr_seg
;
1275 /* The default target format to use. */
1278 mips_target_format (void)
1280 switch (OUTPUT_FLAVOR
)
1282 case bfd_target_ecoff_flavour
:
1283 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1284 case bfd_target_coff_flavour
:
1286 case bfd_target_elf_flavour
:
1288 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1289 return (target_big_endian
1290 ? "elf32-bigmips-vxworks"
1291 : "elf32-littlemips-vxworks");
1294 /* This is traditional mips. */
1295 return (target_big_endian
1296 ? (HAVE_64BIT_OBJECTS
1297 ? "elf64-tradbigmips"
1299 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1300 : (HAVE_64BIT_OBJECTS
1301 ? "elf64-tradlittlemips"
1303 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1305 return (target_big_endian
1306 ? (HAVE_64BIT_OBJECTS
1309 ? "elf32-nbigmips" : "elf32-bigmips"))
1310 : (HAVE_64BIT_OBJECTS
1311 ? "elf64-littlemips"
1313 ? "elf32-nlittlemips" : "elf32-littlemips")));
1321 /* Return the length of instruction INSN. */
1323 static inline unsigned int
1324 insn_length (const struct mips_cl_insn
*insn
)
1326 if (!mips_opts
.mips16
)
1328 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1331 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1334 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1339 insn
->use_extend
= FALSE
;
1341 insn
->insn_opcode
= mo
->match
;
1344 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1345 insn
->fixp
[i
] = NULL
;
1346 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1347 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1348 insn
->mips16_absolute_jump_p
= 0;
1351 /* Record the current MIPS16 mode in now_seg. */
1354 mips_record_mips16_mode (void)
1356 segment_info_type
*si
;
1358 si
= seg_info (now_seg
);
1359 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1360 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1363 /* Install INSN at the location specified by its "frag" and "where" fields. */
1366 install_insn (const struct mips_cl_insn
*insn
)
1368 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1369 if (!mips_opts
.mips16
)
1370 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1371 else if (insn
->mips16_absolute_jump_p
)
1373 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1374 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1378 if (insn
->use_extend
)
1380 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1383 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1385 mips_record_mips16_mode ();
1388 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1389 and install the opcode in the new location. */
1392 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1397 insn
->where
= where
;
1398 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1399 if (insn
->fixp
[i
] != NULL
)
1401 insn
->fixp
[i
]->fx_frag
= frag
;
1402 insn
->fixp
[i
]->fx_where
= where
;
1404 install_insn (insn
);
1407 /* Add INSN to the end of the output. */
1410 add_fixed_insn (struct mips_cl_insn
*insn
)
1412 char *f
= frag_more (insn_length (insn
));
1413 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1416 /* Start a variant frag and move INSN to the start of the variant part,
1417 marking it as fixed. The other arguments are as for frag_var. */
1420 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1421 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1423 frag_grow (max_chars
);
1424 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1426 frag_var (rs_machine_dependent
, max_chars
, var
,
1427 subtype
, symbol
, offset
, NULL
);
1430 /* Insert N copies of INSN into the history buffer, starting at
1431 position FIRST. Neither FIRST nor N need to be clipped. */
1434 insert_into_history (unsigned int first
, unsigned int n
,
1435 const struct mips_cl_insn
*insn
)
1437 if (mips_relax
.sequence
!= 2)
1441 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1443 history
[i
] = history
[i
- n
];
1449 /* Emit a nop instruction, recording it in the history buffer. */
1454 add_fixed_insn (NOP_INSN
);
1455 insert_into_history (0, 1, NOP_INSN
);
1458 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1459 the idea is to make it obvious at a glance that each errata is
1463 init_vr4120_conflicts (void)
1465 #define CONFLICT(FIRST, SECOND) \
1466 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1468 /* Errata 21 - [D]DIV[U] after [D]MACC */
1469 CONFLICT (MACC
, DIV
);
1470 CONFLICT (DMACC
, DIV
);
1472 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1473 CONFLICT (DMULT
, DMULT
);
1474 CONFLICT (DMULT
, DMACC
);
1475 CONFLICT (DMACC
, DMULT
);
1476 CONFLICT (DMACC
, DMACC
);
1478 /* Errata 24 - MT{LO,HI} after [D]MACC */
1479 CONFLICT (MACC
, MTHILO
);
1480 CONFLICT (DMACC
, MTHILO
);
1482 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1483 instruction is executed immediately after a MACC or DMACC
1484 instruction, the result of [either instruction] is incorrect." */
1485 CONFLICT (MACC
, MULT
);
1486 CONFLICT (MACC
, DMULT
);
1487 CONFLICT (DMACC
, MULT
);
1488 CONFLICT (DMACC
, DMULT
);
1490 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1491 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1492 DDIV or DDIVU instruction, the result of the MACC or
1493 DMACC instruction is incorrect.". */
1494 CONFLICT (DMULT
, MACC
);
1495 CONFLICT (DMULT
, DMACC
);
1496 CONFLICT (DIV
, MACC
);
1497 CONFLICT (DIV
, DMACC
);
1507 #define RTYPE_MASK 0x1ff00
1508 #define RTYPE_NUM 0x00100
1509 #define RTYPE_FPU 0x00200
1510 #define RTYPE_FCC 0x00400
1511 #define RTYPE_VEC 0x00800
1512 #define RTYPE_GP 0x01000
1513 #define RTYPE_CP0 0x02000
1514 #define RTYPE_PC 0x04000
1515 #define RTYPE_ACC 0x08000
1516 #define RTYPE_CCC 0x10000
1517 #define RNUM_MASK 0x000ff
1518 #define RWARN 0x80000
1520 #define GENERIC_REGISTER_NUMBERS \
1521 {"$0", RTYPE_NUM | 0}, \
1522 {"$1", RTYPE_NUM | 1}, \
1523 {"$2", RTYPE_NUM | 2}, \
1524 {"$3", RTYPE_NUM | 3}, \
1525 {"$4", RTYPE_NUM | 4}, \
1526 {"$5", RTYPE_NUM | 5}, \
1527 {"$6", RTYPE_NUM | 6}, \
1528 {"$7", RTYPE_NUM | 7}, \
1529 {"$8", RTYPE_NUM | 8}, \
1530 {"$9", RTYPE_NUM | 9}, \
1531 {"$10", RTYPE_NUM | 10}, \
1532 {"$11", RTYPE_NUM | 11}, \
1533 {"$12", RTYPE_NUM | 12}, \
1534 {"$13", RTYPE_NUM | 13}, \
1535 {"$14", RTYPE_NUM | 14}, \
1536 {"$15", RTYPE_NUM | 15}, \
1537 {"$16", RTYPE_NUM | 16}, \
1538 {"$17", RTYPE_NUM | 17}, \
1539 {"$18", RTYPE_NUM | 18}, \
1540 {"$19", RTYPE_NUM | 19}, \
1541 {"$20", RTYPE_NUM | 20}, \
1542 {"$21", RTYPE_NUM | 21}, \
1543 {"$22", RTYPE_NUM | 22}, \
1544 {"$23", RTYPE_NUM | 23}, \
1545 {"$24", RTYPE_NUM | 24}, \
1546 {"$25", RTYPE_NUM | 25}, \
1547 {"$26", RTYPE_NUM | 26}, \
1548 {"$27", RTYPE_NUM | 27}, \
1549 {"$28", RTYPE_NUM | 28}, \
1550 {"$29", RTYPE_NUM | 29}, \
1551 {"$30", RTYPE_NUM | 30}, \
1552 {"$31", RTYPE_NUM | 31}
1554 #define FPU_REGISTER_NAMES \
1555 {"$f0", RTYPE_FPU | 0}, \
1556 {"$f1", RTYPE_FPU | 1}, \
1557 {"$f2", RTYPE_FPU | 2}, \
1558 {"$f3", RTYPE_FPU | 3}, \
1559 {"$f4", RTYPE_FPU | 4}, \
1560 {"$f5", RTYPE_FPU | 5}, \
1561 {"$f6", RTYPE_FPU | 6}, \
1562 {"$f7", RTYPE_FPU | 7}, \
1563 {"$f8", RTYPE_FPU | 8}, \
1564 {"$f9", RTYPE_FPU | 9}, \
1565 {"$f10", RTYPE_FPU | 10}, \
1566 {"$f11", RTYPE_FPU | 11}, \
1567 {"$f12", RTYPE_FPU | 12}, \
1568 {"$f13", RTYPE_FPU | 13}, \
1569 {"$f14", RTYPE_FPU | 14}, \
1570 {"$f15", RTYPE_FPU | 15}, \
1571 {"$f16", RTYPE_FPU | 16}, \
1572 {"$f17", RTYPE_FPU | 17}, \
1573 {"$f18", RTYPE_FPU | 18}, \
1574 {"$f19", RTYPE_FPU | 19}, \
1575 {"$f20", RTYPE_FPU | 20}, \
1576 {"$f21", RTYPE_FPU | 21}, \
1577 {"$f22", RTYPE_FPU | 22}, \
1578 {"$f23", RTYPE_FPU | 23}, \
1579 {"$f24", RTYPE_FPU | 24}, \
1580 {"$f25", RTYPE_FPU | 25}, \
1581 {"$f26", RTYPE_FPU | 26}, \
1582 {"$f27", RTYPE_FPU | 27}, \
1583 {"$f28", RTYPE_FPU | 28}, \
1584 {"$f29", RTYPE_FPU | 29}, \
1585 {"$f30", RTYPE_FPU | 30}, \
1586 {"$f31", RTYPE_FPU | 31}
1588 #define FPU_CONDITION_CODE_NAMES \
1589 {"$fcc0", RTYPE_FCC | 0}, \
1590 {"$fcc1", RTYPE_FCC | 1}, \
1591 {"$fcc2", RTYPE_FCC | 2}, \
1592 {"$fcc3", RTYPE_FCC | 3}, \
1593 {"$fcc4", RTYPE_FCC | 4}, \
1594 {"$fcc5", RTYPE_FCC | 5}, \
1595 {"$fcc6", RTYPE_FCC | 6}, \
1596 {"$fcc7", RTYPE_FCC | 7}
1598 #define COPROC_CONDITION_CODE_NAMES \
1599 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1600 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1601 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1602 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1603 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1604 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1605 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1606 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1608 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1609 {"$a4", RTYPE_GP | 8}, \
1610 {"$a5", RTYPE_GP | 9}, \
1611 {"$a6", RTYPE_GP | 10}, \
1612 {"$a7", RTYPE_GP | 11}, \
1613 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1614 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1615 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1616 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1617 {"$t0", RTYPE_GP | 12}, \
1618 {"$t1", RTYPE_GP | 13}, \
1619 {"$t2", RTYPE_GP | 14}, \
1620 {"$t3", RTYPE_GP | 15}
1622 #define O32_SYMBOLIC_REGISTER_NAMES \
1623 {"$t0", RTYPE_GP | 8}, \
1624 {"$t1", RTYPE_GP | 9}, \
1625 {"$t2", RTYPE_GP | 10}, \
1626 {"$t3", RTYPE_GP | 11}, \
1627 {"$t4", RTYPE_GP | 12}, \
1628 {"$t5", RTYPE_GP | 13}, \
1629 {"$t6", RTYPE_GP | 14}, \
1630 {"$t7", RTYPE_GP | 15}, \
1631 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1632 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1633 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1634 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1636 /* Remaining symbolic register names */
1637 #define SYMBOLIC_REGISTER_NAMES \
1638 {"$zero", RTYPE_GP | 0}, \
1639 {"$at", RTYPE_GP | 1}, \
1640 {"$AT", RTYPE_GP | 1}, \
1641 {"$v0", RTYPE_GP | 2}, \
1642 {"$v1", RTYPE_GP | 3}, \
1643 {"$a0", RTYPE_GP | 4}, \
1644 {"$a1", RTYPE_GP | 5}, \
1645 {"$a2", RTYPE_GP | 6}, \
1646 {"$a3", RTYPE_GP | 7}, \
1647 {"$s0", RTYPE_GP | 16}, \
1648 {"$s1", RTYPE_GP | 17}, \
1649 {"$s2", RTYPE_GP | 18}, \
1650 {"$s3", RTYPE_GP | 19}, \
1651 {"$s4", RTYPE_GP | 20}, \
1652 {"$s5", RTYPE_GP | 21}, \
1653 {"$s6", RTYPE_GP | 22}, \
1654 {"$s7", RTYPE_GP | 23}, \
1655 {"$t8", RTYPE_GP | 24}, \
1656 {"$t9", RTYPE_GP | 25}, \
1657 {"$k0", RTYPE_GP | 26}, \
1658 {"$kt0", RTYPE_GP | 26}, \
1659 {"$k1", RTYPE_GP | 27}, \
1660 {"$kt1", RTYPE_GP | 27}, \
1661 {"$gp", RTYPE_GP | 28}, \
1662 {"$sp", RTYPE_GP | 29}, \
1663 {"$s8", RTYPE_GP | 30}, \
1664 {"$fp", RTYPE_GP | 30}, \
1665 {"$ra", RTYPE_GP | 31}
1667 #define MIPS16_SPECIAL_REGISTER_NAMES \
1668 {"$pc", RTYPE_PC | 0}
1670 #define MDMX_VECTOR_REGISTER_NAMES \
1671 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1672 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1673 {"$v2", RTYPE_VEC | 2}, \
1674 {"$v3", RTYPE_VEC | 3}, \
1675 {"$v4", RTYPE_VEC | 4}, \
1676 {"$v5", RTYPE_VEC | 5}, \
1677 {"$v6", RTYPE_VEC | 6}, \
1678 {"$v7", RTYPE_VEC | 7}, \
1679 {"$v8", RTYPE_VEC | 8}, \
1680 {"$v9", RTYPE_VEC | 9}, \
1681 {"$v10", RTYPE_VEC | 10}, \
1682 {"$v11", RTYPE_VEC | 11}, \
1683 {"$v12", RTYPE_VEC | 12}, \
1684 {"$v13", RTYPE_VEC | 13}, \
1685 {"$v14", RTYPE_VEC | 14}, \
1686 {"$v15", RTYPE_VEC | 15}, \
1687 {"$v16", RTYPE_VEC | 16}, \
1688 {"$v17", RTYPE_VEC | 17}, \
1689 {"$v18", RTYPE_VEC | 18}, \
1690 {"$v19", RTYPE_VEC | 19}, \
1691 {"$v20", RTYPE_VEC | 20}, \
1692 {"$v21", RTYPE_VEC | 21}, \
1693 {"$v22", RTYPE_VEC | 22}, \
1694 {"$v23", RTYPE_VEC | 23}, \
1695 {"$v24", RTYPE_VEC | 24}, \
1696 {"$v25", RTYPE_VEC | 25}, \
1697 {"$v26", RTYPE_VEC | 26}, \
1698 {"$v27", RTYPE_VEC | 27}, \
1699 {"$v28", RTYPE_VEC | 28}, \
1700 {"$v29", RTYPE_VEC | 29}, \
1701 {"$v30", RTYPE_VEC | 30}, \
1702 {"$v31", RTYPE_VEC | 31}
1704 #define MIPS_DSP_ACCUMULATOR_NAMES \
1705 {"$ac0", RTYPE_ACC | 0}, \
1706 {"$ac1", RTYPE_ACC | 1}, \
1707 {"$ac2", RTYPE_ACC | 2}, \
1708 {"$ac3", RTYPE_ACC | 3}
1710 static const struct regname reg_names
[] = {
1711 GENERIC_REGISTER_NUMBERS
,
1713 FPU_CONDITION_CODE_NAMES
,
1714 COPROC_CONDITION_CODE_NAMES
,
1716 /* The $txx registers depends on the abi,
1717 these will be added later into the symbol table from
1718 one of the tables below once mips_abi is set after
1719 parsing of arguments from the command line. */
1720 SYMBOLIC_REGISTER_NAMES
,
1722 MIPS16_SPECIAL_REGISTER_NAMES
,
1723 MDMX_VECTOR_REGISTER_NAMES
,
1724 MIPS_DSP_ACCUMULATOR_NAMES
,
1728 static const struct regname reg_names_o32
[] = {
1729 O32_SYMBOLIC_REGISTER_NAMES
,
1733 static const struct regname reg_names_n32n64
[] = {
1734 N32N64_SYMBOLIC_REGISTER_NAMES
,
1739 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1746 /* Find end of name. */
1748 if (is_name_beginner (*e
))
1750 while (is_part_of_name (*e
))
1753 /* Terminate name. */
1757 /* Look for a register symbol. */
1758 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1760 int r
= S_GET_VALUE (symbolP
);
1762 reg
= r
& RNUM_MASK
;
1763 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1764 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1765 reg
= (r
& RNUM_MASK
) - 2;
1767 /* Else see if this is a register defined in an itbl entry. */
1768 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1775 if (itbl_get_reg_val (n
, &r
))
1776 reg
= r
& RNUM_MASK
;
1779 /* Advance to next token if a register was recognised. */
1782 else if (types
& RWARN
)
1783 as_warn ("Unrecognized register name `%s'", *s
);
1791 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1792 architecture. If EXPANSIONP is TRUE then this check is done while
1793 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1796 is_opcode_valid (const struct mips_opcode
*mo
, bfd_boolean expansionp
)
1798 int isa
= mips_opts
.isa
;
1801 if (mips_opts
.ase_mdmx
)
1803 if (mips_opts
.ase_dsp
)
1805 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1807 if (mips_opts
.ase_dspr2
)
1809 if (mips_opts
.ase_mt
)
1811 if (mips_opts
.ase_mips3d
)
1813 if (mips_opts
.ase_smartmips
)
1814 isa
|= INSN_SMARTMIPS
;
1816 /* For user code we don't check for mips_opts.mips16 since we want
1817 to allow jalx if -mips16 was specified on the command line. */
1818 if (expansionp
? mips_opts
.mips16
: file_ase_mips16
)
1821 /* Don't accept instructions based on the ISA if the CPU does not implement
1822 all the coprocessor insns. */
1823 if (NO_ISA_COP (mips_opts
.arch
)
1824 && COP_INSN (mo
->pinfo
))
1827 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1830 /* Check whether the instruction or macro requires single-precision or
1831 double-precision floating-point support. Note that this information is
1832 stored differently in the opcode table for insns and macros. */
1833 if (mo
->pinfo
== INSN_MACRO
)
1835 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1836 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1840 fp_s
= mo
->pinfo
& FP_S
;
1841 fp_d
= mo
->pinfo
& FP_D
;
1844 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1847 if (fp_s
&& mips_opts
.soft_float
)
1853 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1854 selected ISA and architecture. */
1857 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1859 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1862 /* This function is called once, at assembler startup time. It should set up
1863 all the tables, etc. that the MD part of the assembler will need. */
1868 const char *retval
= NULL
;
1872 if (mips_pic
!= NO_PIC
)
1874 if (g_switch_seen
&& g_switch_value
!= 0)
1875 as_bad (_("-G may not be used in position-independent code"));
1879 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1880 as_warn (_("Could not set architecture and machine"));
1882 op_hash
= hash_new ();
1884 for (i
= 0; i
< NUMOPCODES
;)
1886 const char *name
= mips_opcodes
[i
].name
;
1888 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1891 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1892 mips_opcodes
[i
].name
, retval
);
1893 /* Probably a memory allocation problem? Give up now. */
1894 as_fatal (_("Broken assembler. No assembly attempted."));
1898 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1900 if (!validate_mips_insn (&mips_opcodes
[i
]))
1902 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1904 create_insn (&nop_insn
, mips_opcodes
+ i
);
1905 nop_insn
.fixed_p
= 1;
1910 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1913 mips16_op_hash
= hash_new ();
1916 while (i
< bfd_mips16_num_opcodes
)
1918 const char *name
= mips16_opcodes
[i
].name
;
1920 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1922 as_fatal (_("internal: can't hash `%s': %s"),
1923 mips16_opcodes
[i
].name
, retval
);
1926 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1927 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1928 != mips16_opcodes
[i
].match
))
1930 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1931 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1934 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1936 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1937 mips16_nop_insn
.fixed_p
= 1;
1941 while (i
< bfd_mips16_num_opcodes
1942 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1946 as_fatal (_("Broken assembler. No assembly attempted."));
1948 /* We add all the general register names to the symbol table. This
1949 helps us detect invalid uses of them. */
1950 for (i
= 0; reg_names
[i
].name
; i
++)
1951 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1952 reg_names
[i
].num
, // & RNUM_MASK,
1953 &zero_address_frag
));
1955 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1956 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1957 reg_names_n32n64
[i
].num
, // & RNUM_MASK,
1958 &zero_address_frag
));
1960 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1961 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1962 reg_names_o32
[i
].num
, // & RNUM_MASK,
1963 &zero_address_frag
));
1965 mips_no_prev_insn ();
1968 mips_cprmask
[0] = 0;
1969 mips_cprmask
[1] = 0;
1970 mips_cprmask
[2] = 0;
1971 mips_cprmask
[3] = 0;
1973 /* set the default alignment for the text section (2**2) */
1974 record_alignment (text_section
, 2);
1976 bfd_set_gp_size (stdoutput
, g_switch_value
);
1981 /* On a native system other than VxWorks, sections must be aligned
1982 to 16 byte boundaries. When configured for an embedded ELF
1983 target, we don't bother. */
1984 if (strncmp (TARGET_OS
, "elf", 3) != 0
1985 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
1987 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1988 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1989 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1992 /* Create a .reginfo section for register masks and a .mdebug
1993 section for debugging information. */
2001 subseg
= now_subseg
;
2003 /* The ABI says this section should be loaded so that the
2004 running program can access it. However, we don't load it
2005 if we are configured for an embedded target */
2006 flags
= SEC_READONLY
| SEC_DATA
;
2007 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2008 flags
|= SEC_ALLOC
| SEC_LOAD
;
2010 if (mips_abi
!= N64_ABI
)
2012 sec
= subseg_new (".reginfo", (subsegT
) 0);
2014 bfd_set_section_flags (stdoutput
, sec
, flags
);
2015 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2017 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2021 /* The 64-bit ABI uses a .MIPS.options section rather than
2022 .reginfo section. */
2023 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2024 bfd_set_section_flags (stdoutput
, sec
, flags
);
2025 bfd_set_section_alignment (stdoutput
, sec
, 3);
2027 /* Set up the option header. */
2029 Elf_Internal_Options opthdr
;
2032 opthdr
.kind
= ODK_REGINFO
;
2033 opthdr
.size
= (sizeof (Elf_External_Options
)
2034 + sizeof (Elf64_External_RegInfo
));
2037 f
= frag_more (sizeof (Elf_External_Options
));
2038 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2039 (Elf_External_Options
*) f
);
2041 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2045 if (ECOFF_DEBUGGING
)
2047 sec
= subseg_new (".mdebug", (subsegT
) 0);
2048 (void) bfd_set_section_flags (stdoutput
, sec
,
2049 SEC_HAS_CONTENTS
| SEC_READONLY
);
2050 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2052 else if (mips_flag_pdr
)
2054 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2055 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2056 SEC_READONLY
| SEC_RELOC
2058 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2061 subseg_set (seg
, subseg
);
2064 #endif /* OBJ_ELF */
2066 if (! ECOFF_DEBUGGING
)
2069 if (mips_fix_vr4120
)
2070 init_vr4120_conflicts ();
2076 if (! ECOFF_DEBUGGING
)
2081 md_assemble (char *str
)
2083 struct mips_cl_insn insn
;
2084 bfd_reloc_code_real_type unused_reloc
[3]
2085 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2087 imm_expr
.X_op
= O_absent
;
2088 imm2_expr
.X_op
= O_absent
;
2089 offset_expr
.X_op
= O_absent
;
2090 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2091 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2092 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2093 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2094 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2095 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2097 if (mips_opts
.mips16
)
2098 mips16_ip (str
, &insn
);
2101 mips_ip (str
, &insn
);
2102 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2103 str
, insn
.insn_opcode
));
2108 as_bad ("%s `%s'", insn_error
, str
);
2112 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2115 if (mips_opts
.mips16
)
2116 mips16_macro (&insn
);
2123 if (imm_expr
.X_op
!= O_absent
)
2124 append_insn (&insn
, &imm_expr
, imm_reloc
);
2125 else if (offset_expr
.X_op
!= O_absent
)
2126 append_insn (&insn
, &offset_expr
, offset_reloc
);
2128 append_insn (&insn
, NULL
, unused_reloc
);
2132 /* Return true if the given relocation might need a matching %lo().
2133 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2134 need a matching %lo() when applied to local symbols. */
2136 static inline bfd_boolean
2137 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2139 return (HAVE_IN_PLACE_ADDENDS
2140 && (reloc
== BFD_RELOC_HI16_S
2141 || reloc
== BFD_RELOC_MIPS16_HI16_S
2142 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2143 all GOT16 relocations evaluate to "G". */
2144 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
2147 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2150 static inline bfd_boolean
2151 fixup_has_matching_lo_p (fixS
*fixp
)
2153 return (fixp
->fx_next
!= NULL
2154 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
2155 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
2156 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2157 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2160 /* See whether instruction IP reads register REG. CLASS is the type
2164 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2165 enum mips_regclass
class)
2167 if (class == MIPS16_REG
)
2169 assert (mips_opts
.mips16
);
2170 reg
= mips16_to_32_reg_map
[reg
];
2171 class = MIPS_GR_REG
;
2174 /* Don't report on general register ZERO, since it never changes. */
2175 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2178 if (class == MIPS_FP_REG
)
2180 assert (! mips_opts
.mips16
);
2181 /* If we are called with either $f0 or $f1, we must check $f0.
2182 This is not optimal, because it will introduce an unnecessary
2183 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2184 need to distinguish reading both $f0 and $f1 or just one of
2185 them. Note that we don't have to check the other way,
2186 because there is no instruction that sets both $f0 and $f1
2187 and requires a delay. */
2188 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2189 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2190 == (reg
&~ (unsigned) 1)))
2192 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2193 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2194 == (reg
&~ (unsigned) 1)))
2197 else if (! mips_opts
.mips16
)
2199 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2200 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2202 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2203 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2208 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2209 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2211 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2212 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2214 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2215 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2218 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2220 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2222 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2224 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2225 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2232 /* This function returns true if modifying a register requires a
2236 reg_needs_delay (unsigned int reg
)
2238 unsigned long prev_pinfo
;
2240 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2241 if (! mips_opts
.noreorder
2242 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2243 && ! gpr_interlocks
)
2244 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2245 && ! cop_interlocks
)))
2247 /* A load from a coprocessor or from memory. All load delays
2248 delay the use of general register rt for one instruction. */
2249 /* Itbl support may require additional care here. */
2250 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2251 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2258 /* Move all labels in insn_labels to the current insertion point. */
2261 mips_move_labels (void)
2263 segment_info_type
*si
= seg_info (now_seg
);
2264 struct insn_label_list
*l
;
2267 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2269 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2270 symbol_set_frag (l
->label
, frag_now
);
2271 val
= (valueT
) frag_now_fix ();
2272 /* mips16 text labels are stored as odd. */
2273 if (mips_opts
.mips16
)
2275 S_SET_VALUE (l
->label
, val
);
2280 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2282 bfd_boolean linkonce
= FALSE
;
2283 segT symseg
= S_GET_SEGMENT (sym
);
2285 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2287 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2290 /* The GNU toolchain uses an extension for ELF: a section
2291 beginning with the magic string .gnu.linkonce is a
2292 linkonce section. */
2293 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2294 sizeof ".gnu.linkonce" - 1) == 0)
2301 /* Mark instruction labels in mips16 mode. This permits the linker to
2302 handle them specially, such as generating jalx instructions when
2303 needed. We also make them odd for the duration of the assembly, in
2304 order to generate the right sort of code. We will make them even
2305 in the adjust_symtab routine, while leaving them marked. This is
2306 convenient for the debugger and the disassembler. The linker knows
2307 to make them odd again. */
2310 mips16_mark_labels (void)
2312 segment_info_type
*si
= seg_info (now_seg
);
2313 struct insn_label_list
*l
;
2315 if (!mips_opts
.mips16
)
2318 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2320 symbolS
*label
= l
->label
;
2322 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2324 S_SET_OTHER (label
, STO_MIPS16
);
2326 if ((S_GET_VALUE (label
) & 1) == 0
2327 /* Don't adjust the address if the label is global or weak, or
2328 in a link-once section, since we'll be emitting symbol reloc
2329 references to it which will be patched up by the linker, and
2330 the final value of the symbol may or may not be MIPS16. */
2331 && ! S_IS_WEAK (label
)
2332 && ! S_IS_EXTERNAL (label
)
2333 && ! s_is_linkonce (label
, now_seg
))
2334 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2338 /* End the current frag. Make it a variant frag and record the
2342 relax_close_frag (void)
2344 mips_macro_warning
.first_frag
= frag_now
;
2345 frag_var (rs_machine_dependent
, 0, 0,
2346 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2347 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2349 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2350 mips_relax
.first_fixup
= 0;
2353 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2354 See the comment above RELAX_ENCODE for more details. */
2357 relax_start (symbolS
*symbol
)
2359 assert (mips_relax
.sequence
== 0);
2360 mips_relax
.sequence
= 1;
2361 mips_relax
.symbol
= symbol
;
2364 /* Start generating the second version of a relaxable sequence.
2365 See the comment above RELAX_ENCODE for more details. */
2370 assert (mips_relax
.sequence
== 1);
2371 mips_relax
.sequence
= 2;
2374 /* End the current relaxable sequence. */
2379 assert (mips_relax
.sequence
== 2);
2380 relax_close_frag ();
2381 mips_relax
.sequence
= 0;
2384 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2385 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2386 by VR4120 errata. */
2389 classify_vr4120_insn (const char *name
)
2391 if (strncmp (name
, "macc", 4) == 0)
2392 return FIX_VR4120_MACC
;
2393 if (strncmp (name
, "dmacc", 5) == 0)
2394 return FIX_VR4120_DMACC
;
2395 if (strncmp (name
, "mult", 4) == 0)
2396 return FIX_VR4120_MULT
;
2397 if (strncmp (name
, "dmult", 5) == 0)
2398 return FIX_VR4120_DMULT
;
2399 if (strstr (name
, "div"))
2400 return FIX_VR4120_DIV
;
2401 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2402 return FIX_VR4120_MTHILO
;
2403 return NUM_FIX_VR4120_CLASSES
;
2406 /* Return the number of instructions that must separate INSN1 and INSN2,
2407 where INSN1 is the earlier instruction. Return the worst-case value
2408 for any INSN2 if INSN2 is null. */
2411 insns_between (const struct mips_cl_insn
*insn1
,
2412 const struct mips_cl_insn
*insn2
)
2414 unsigned long pinfo1
, pinfo2
;
2416 /* This function needs to know which pinfo flags are set for INSN2
2417 and which registers INSN2 uses. The former is stored in PINFO2 and
2418 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2419 will have every flag set and INSN2_USES_REG will always return true. */
2420 pinfo1
= insn1
->insn_mo
->pinfo
;
2421 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2423 #define INSN2_USES_REG(REG, CLASS) \
2424 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2426 /* For most targets, write-after-read dependencies on the HI and LO
2427 registers must be separated by at least two instructions. */
2428 if (!hilo_interlocks
)
2430 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2432 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2436 /* If we're working around r7000 errata, there must be two instructions
2437 between an mfhi or mflo and any instruction that uses the result. */
2438 if (mips_7000_hilo_fix
2439 && MF_HILO_INSN (pinfo1
)
2440 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2443 /* If working around VR4120 errata, check for combinations that need
2444 a single intervening instruction. */
2445 if (mips_fix_vr4120
)
2447 unsigned int class1
, class2
;
2449 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2450 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2454 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2455 if (vr4120_conflicts
[class1
] & (1 << class2
))
2460 if (!mips_opts
.mips16
)
2462 /* Check for GPR or coprocessor load delays. All such delays
2463 are on the RT register. */
2464 /* Itbl support may require additional care here. */
2465 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2466 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2468 know (pinfo1
& INSN_WRITE_GPR_T
);
2469 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2473 /* Check for generic coprocessor hazards.
2475 This case is not handled very well. There is no special
2476 knowledge of CP0 handling, and the coprocessors other than
2477 the floating point unit are not distinguished at all. */
2478 /* Itbl support may require additional care here. FIXME!
2479 Need to modify this to include knowledge about
2480 user specified delays! */
2481 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2482 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2484 /* Handle cases where INSN1 writes to a known general coprocessor
2485 register. There must be a one instruction delay before INSN2
2486 if INSN2 reads that register, otherwise no delay is needed. */
2487 if (pinfo1
& INSN_WRITE_FPR_T
)
2489 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2492 else if (pinfo1
& INSN_WRITE_FPR_S
)
2494 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2499 /* Read-after-write dependencies on the control registers
2500 require a two-instruction gap. */
2501 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2502 && (pinfo2
& INSN_READ_COND_CODE
))
2505 /* We don't know exactly what INSN1 does. If INSN2 is
2506 also a coprocessor instruction, assume there must be
2507 a one instruction gap. */
2508 if (pinfo2
& INSN_COP
)
2513 /* Check for read-after-write dependencies on the coprocessor
2514 control registers in cases where INSN1 does not need a general
2515 coprocessor delay. This means that INSN1 is a floating point
2516 comparison instruction. */
2517 /* Itbl support may require additional care here. */
2518 else if (!cop_interlocks
2519 && (pinfo1
& INSN_WRITE_COND_CODE
)
2520 && (pinfo2
& INSN_READ_COND_CODE
))
2524 #undef INSN2_USES_REG
2529 /* Return the number of nops that would be needed to work around the
2530 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2531 the MAX_VR4130_NOPS instructions described by HISTORY. */
2534 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2535 const struct mips_cl_insn
*insn
)
2539 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2540 are not affected by the errata. */
2542 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2543 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2544 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2547 /* Search for the first MFLO or MFHI. */
2548 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2549 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2551 /* Extract the destination register. */
2552 if (mips_opts
.mips16
)
2553 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2555 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2557 /* No nops are needed if INSN reads that register. */
2558 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2561 /* ...or if any of the intervening instructions do. */
2562 for (j
= 0; j
< i
; j
++)
2563 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2566 return MAX_VR4130_NOPS
- i
;
2571 /* Return the number of nops that would be needed if instruction INSN
2572 immediately followed the MAX_NOPS instructions given by HISTORY,
2573 where HISTORY[0] is the most recent instruction. If INSN is null,
2574 return the worse-case number of nops for any instruction. */
2577 nops_for_insn (const struct mips_cl_insn
*history
,
2578 const struct mips_cl_insn
*insn
)
2580 int i
, nops
, tmp_nops
;
2583 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2584 if (!history
[i
].noreorder_p
)
2586 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2587 if (tmp_nops
> nops
)
2591 if (mips_fix_vr4130
)
2593 tmp_nops
= nops_for_vr4130 (history
, insn
);
2594 if (tmp_nops
> nops
)
2601 /* The variable arguments provide NUM_INSNS extra instructions that
2602 might be added to HISTORY. Return the largest number of nops that
2603 would be needed after the extended sequence. */
2606 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2609 struct mips_cl_insn buffer
[MAX_NOPS
];
2610 struct mips_cl_insn
*cursor
;
2613 va_start (args
, history
);
2614 cursor
= buffer
+ num_insns
;
2615 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2616 while (cursor
> buffer
)
2617 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2619 nops
= nops_for_insn (buffer
, NULL
);
2624 /* Like nops_for_insn, but if INSN is a branch, take into account the
2625 worst-case delay for the branch target. */
2628 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2629 const struct mips_cl_insn
*insn
)
2633 nops
= nops_for_insn (history
, insn
);
2634 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2635 | INSN_COND_BRANCH_DELAY
2636 | INSN_COND_BRANCH_LIKELY
))
2638 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2639 if (tmp_nops
> nops
)
2642 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2644 tmp_nops
= nops_for_sequence (1, history
, insn
);
2645 if (tmp_nops
> nops
)
2651 /* Output an instruction. IP is the instruction information.
2652 ADDRESS_EXPR is an operand of the instruction to be used with
2656 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2657 bfd_reloc_code_real_type
*reloc_type
)
2659 unsigned long prev_pinfo
, pinfo
;
2660 relax_stateT prev_insn_frag_type
= 0;
2661 bfd_boolean relaxed_branch
= FALSE
;
2662 segment_info_type
*si
= seg_info (now_seg
);
2664 /* Mark instruction labels in mips16 mode. */
2665 mips16_mark_labels ();
2667 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2668 pinfo
= ip
->insn_mo
->pinfo
;
2670 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2672 /* There are a lot of optimizations we could do that we don't.
2673 In particular, we do not, in general, reorder instructions.
2674 If you use gcc with optimization, it will reorder
2675 instructions and generally do much more optimization then we
2676 do here; repeating all that work in the assembler would only
2677 benefit hand written assembly code, and does not seem worth
2679 int nops
= (mips_optimize
== 0
2680 ? nops_for_insn (history
, NULL
)
2681 : nops_for_insn_or_target (history
, ip
));
2685 unsigned long old_frag_offset
;
2688 old_frag
= frag_now
;
2689 old_frag_offset
= frag_now_fix ();
2691 for (i
= 0; i
< nops
; i
++)
2696 listing_prev_line ();
2697 /* We may be at the start of a variant frag. In case we
2698 are, make sure there is enough space for the frag
2699 after the frags created by listing_prev_line. The
2700 argument to frag_grow here must be at least as large
2701 as the argument to all other calls to frag_grow in
2702 this file. We don't have to worry about being in the
2703 middle of a variant frag, because the variants insert
2704 all needed nop instructions themselves. */
2708 mips_move_labels ();
2710 #ifndef NO_ECOFF_DEBUGGING
2711 if (ECOFF_DEBUGGING
)
2712 ecoff_fix_loc (old_frag
, old_frag_offset
);
2716 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2718 /* Work out how many nops in prev_nop_frag are needed by IP. */
2719 int nops
= nops_for_insn_or_target (history
, ip
);
2720 assert (nops
<= prev_nop_frag_holds
);
2722 /* Enforce NOPS as a minimum. */
2723 if (nops
> prev_nop_frag_required
)
2724 prev_nop_frag_required
= nops
;
2726 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2728 /* Settle for the current number of nops. Update the history
2729 accordingly (for the benefit of any future .set reorder code). */
2730 prev_nop_frag
= NULL
;
2731 insert_into_history (prev_nop_frag_since
,
2732 prev_nop_frag_holds
, NOP_INSN
);
2736 /* Allow this instruction to replace one of the nops that was
2737 tentatively added to prev_nop_frag. */
2738 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2739 prev_nop_frag_holds
--;
2740 prev_nop_frag_since
++;
2745 /* The value passed to dwarf2_emit_insn is the distance between
2746 the beginning of the current instruction and the address that
2747 should be recorded in the debug tables. For MIPS16 debug info
2748 we want to use ISA-encoded addresses, so we pass -1 for an
2749 address higher by one than the current. */
2750 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2753 /* Record the frag type before frag_var. */
2754 if (history
[0].frag
)
2755 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2758 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2759 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2760 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2761 && mips_relax_branch
2762 /* Don't try branch relaxation within .set nomacro, or within
2763 .set noat if we use $at for PIC computations. If it turns
2764 out that the branch was out-of-range, we'll get an error. */
2765 && !mips_opts
.warn_about_macros
2766 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2767 && !mips_opts
.mips16
)
2769 relaxed_branch
= TRUE
;
2770 add_relaxed_insn (ip
, (relaxed_branch_length
2772 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2773 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2776 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2777 pinfo
& INSN_COND_BRANCH_LIKELY
,
2778 pinfo
& INSN_WRITE_GPR_31
,
2780 address_expr
->X_add_symbol
,
2781 address_expr
->X_add_number
);
2782 *reloc_type
= BFD_RELOC_UNUSED
;
2784 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2786 /* We need to set up a variant frag. */
2787 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2788 add_relaxed_insn (ip
, 4, 0,
2790 (*reloc_type
- BFD_RELOC_UNUSED
,
2791 mips16_small
, mips16_ext
,
2792 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2793 history
[0].mips16_absolute_jump_p
),
2794 make_expr_symbol (address_expr
), 0);
2796 else if (mips_opts
.mips16
2798 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2800 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2801 /* Make sure there is enough room to swap this instruction with
2802 a following jump instruction. */
2804 add_fixed_insn (ip
);
2808 if (mips_opts
.mips16
2809 && mips_opts
.noreorder
2810 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2811 as_warn (_("extended instruction in delay slot"));
2813 if (mips_relax
.sequence
)
2815 /* If we've reached the end of this frag, turn it into a variant
2816 frag and record the information for the instructions we've
2818 if (frag_room () < 4)
2819 relax_close_frag ();
2820 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2823 if (mips_relax
.sequence
!= 2)
2824 mips_macro_warning
.sizes
[0] += 4;
2825 if (mips_relax
.sequence
!= 1)
2826 mips_macro_warning
.sizes
[1] += 4;
2828 if (mips_opts
.mips16
)
2831 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2833 add_fixed_insn (ip
);
2836 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2838 if (address_expr
->X_op
== O_constant
)
2842 switch (*reloc_type
)
2845 ip
->insn_opcode
|= address_expr
->X_add_number
;
2848 case BFD_RELOC_MIPS_HIGHEST
:
2849 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2850 ip
->insn_opcode
|= tmp
& 0xffff;
2853 case BFD_RELOC_MIPS_HIGHER
:
2854 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2855 ip
->insn_opcode
|= tmp
& 0xffff;
2858 case BFD_RELOC_HI16_S
:
2859 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2860 ip
->insn_opcode
|= tmp
& 0xffff;
2863 case BFD_RELOC_HI16
:
2864 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2867 case BFD_RELOC_UNUSED
:
2868 case BFD_RELOC_LO16
:
2869 case BFD_RELOC_MIPS_GOT_DISP
:
2870 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2873 case BFD_RELOC_MIPS_JMP
:
2874 if ((address_expr
->X_add_number
& 3) != 0)
2875 as_bad (_("jump to misaligned address (0x%lx)"),
2876 (unsigned long) address_expr
->X_add_number
);
2877 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2880 case BFD_RELOC_MIPS16_JMP
:
2881 if ((address_expr
->X_add_number
& 3) != 0)
2882 as_bad (_("jump to misaligned address (0x%lx)"),
2883 (unsigned long) address_expr
->X_add_number
);
2885 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2886 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2887 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2890 case BFD_RELOC_16_PCREL_S2
:
2891 if ((address_expr
->X_add_number
& 3) != 0)
2892 as_bad (_("branch to misaligned address (0x%lx)"),
2893 (unsigned long) address_expr
->X_add_number
);
2894 if (mips_relax_branch
)
2896 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2897 as_bad (_("branch address range overflow (0x%lx)"),
2898 (unsigned long) address_expr
->X_add_number
);
2899 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2906 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2909 reloc_howto_type
*howto
;
2912 /* In a compound relocation, it is the final (outermost)
2913 operator that determines the relocated field. */
2914 for (i
= 1; i
< 3; i
++)
2915 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2918 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2919 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2920 bfd_get_reloc_size (howto
),
2922 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2925 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2926 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2927 && ip
->fixp
[0]->fx_addsy
)
2928 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2930 /* These relocations can have an addend that won't fit in
2931 4 octets for 64bit assembly. */
2933 && ! howto
->partial_inplace
2934 && (reloc_type
[0] == BFD_RELOC_16
2935 || reloc_type
[0] == BFD_RELOC_32
2936 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2937 || reloc_type
[0] == BFD_RELOC_HI16_S
2938 || reloc_type
[0] == BFD_RELOC_LO16
2939 || reloc_type
[0] == BFD_RELOC_GPREL16
2940 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2941 || reloc_type
[0] == BFD_RELOC_GPREL32
2942 || reloc_type
[0] == BFD_RELOC_64
2943 || reloc_type
[0] == BFD_RELOC_CTOR
2944 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2945 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2946 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2947 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2948 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2949 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2950 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2951 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2952 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2953 ip
->fixp
[0]->fx_no_overflow
= 1;
2955 if (mips_relax
.sequence
)
2957 if (mips_relax
.first_fixup
== 0)
2958 mips_relax
.first_fixup
= ip
->fixp
[0];
2960 else if (reloc_needs_lo_p (*reloc_type
))
2962 struct mips_hi_fixup
*hi_fixup
;
2964 /* Reuse the last entry if it already has a matching %lo. */
2965 hi_fixup
= mips_hi_fixup_list
;
2967 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2969 hi_fixup
= ((struct mips_hi_fixup
*)
2970 xmalloc (sizeof (struct mips_hi_fixup
)));
2971 hi_fixup
->next
= mips_hi_fixup_list
;
2972 mips_hi_fixup_list
= hi_fixup
;
2974 hi_fixup
->fixp
= ip
->fixp
[0];
2975 hi_fixup
->seg
= now_seg
;
2978 /* Add fixups for the second and third relocations, if given.
2979 Note that the ABI allows the second relocation to be
2980 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2981 moment we only use RSS_UNDEF, but we could add support
2982 for the others if it ever becomes necessary. */
2983 for (i
= 1; i
< 3; i
++)
2984 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2986 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2987 ip
->fixp
[0]->fx_size
, NULL
, 0,
2988 FALSE
, reloc_type
[i
]);
2990 /* Use fx_tcbit to mark compound relocs. */
2991 ip
->fixp
[0]->fx_tcbit
= 1;
2992 ip
->fixp
[i
]->fx_tcbit
= 1;
2998 /* Update the register mask information. */
2999 if (! mips_opts
.mips16
)
3001 if (pinfo
& INSN_WRITE_GPR_D
)
3002 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3003 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3004 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3005 if (pinfo
& INSN_READ_GPR_S
)
3006 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3007 if (pinfo
& INSN_WRITE_GPR_31
)
3008 mips_gprmask
|= 1 << RA
;
3009 if (pinfo
& INSN_WRITE_FPR_D
)
3010 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3011 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3012 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3013 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3014 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3015 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3016 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3017 if (pinfo
& INSN_COP
)
3019 /* We don't keep enough information to sort these cases out.
3020 The itbl support does keep this information however, although
3021 we currently don't support itbl fprmats as part of the cop
3022 instruction. May want to add this support in the future. */
3024 /* Never set the bit for $0, which is always zero. */
3025 mips_gprmask
&= ~1 << 0;
3029 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3030 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3031 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3032 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3033 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3034 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3035 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3036 mips_gprmask
|= 1 << TREG
;
3037 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3038 mips_gprmask
|= 1 << SP
;
3039 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3040 mips_gprmask
|= 1 << RA
;
3041 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3042 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3043 if (pinfo
& MIPS16_INSN_READ_Z
)
3044 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3045 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3046 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3049 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3051 /* Filling the branch delay slot is more complex. We try to
3052 switch the branch with the previous instruction, which we can
3053 do if the previous instruction does not set up a condition
3054 that the branch tests and if the branch is not itself the
3055 target of any branch. */
3056 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3057 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3059 if (mips_optimize
< 2
3060 /* If we have seen .set volatile or .set nomove, don't
3062 || mips_opts
.nomove
!= 0
3063 /* We can't swap if the previous instruction's position
3065 || history
[0].fixed_p
3066 /* If the previous previous insn was in a .set
3067 noreorder, we can't swap. Actually, the MIPS
3068 assembler will swap in this situation. However, gcc
3069 configured -with-gnu-as will generate code like
3075 in which we can not swap the bne and INSN. If gcc is
3076 not configured -with-gnu-as, it does not output the
3078 || history
[1].noreorder_p
3079 /* If the branch is itself the target of a branch, we
3080 can not swap. We cheat on this; all we check for is
3081 whether there is a label on this instruction. If
3082 there are any branches to anything other than a
3083 label, users must use .set noreorder. */
3084 || si
->label_list
!= NULL
3085 /* If the previous instruction is in a variant frag
3086 other than this branch's one, we cannot do the swap.
3087 This does not apply to the mips16, which uses variant
3088 frags for different purposes. */
3089 || (! mips_opts
.mips16
3090 && prev_insn_frag_type
== rs_machine_dependent
)
3091 /* Check for conflicts between the branch and the instructions
3092 before the candidate delay slot. */
3093 || nops_for_insn (history
+ 1, ip
) > 0
3094 /* Check for conflicts between the swapped sequence and the
3095 target of the branch. */
3096 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3097 /* We do not swap with a trap instruction, since it
3098 complicates trap handlers to have the trap
3099 instruction be in a delay slot. */
3100 || (prev_pinfo
& INSN_TRAP
)
3101 /* If the branch reads a register that the previous
3102 instruction sets, we can not swap. */
3103 || (! mips_opts
.mips16
3104 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3105 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3107 || (! mips_opts
.mips16
3108 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3109 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3111 || (mips_opts
.mips16
3112 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3114 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3116 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3118 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3120 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3122 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3124 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3125 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3126 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3127 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3128 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3129 && insn_uses_reg (ip
,
3130 MIPS16OP_EXTRACT_REG32R
3131 (history
[0].insn_opcode
),
3133 /* If the branch writes a register that the previous
3134 instruction sets, we can not swap (we know that
3135 branches write only to RD or to $31). */
3136 || (! mips_opts
.mips16
3137 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3138 && (((pinfo
& INSN_WRITE_GPR_D
)
3139 && (EXTRACT_OPERAND (RT
, history
[0])
3140 == EXTRACT_OPERAND (RD
, *ip
)))
3141 || ((pinfo
& INSN_WRITE_GPR_31
)
3142 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3143 || (! mips_opts
.mips16
3144 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3145 && (((pinfo
& INSN_WRITE_GPR_D
)
3146 && (EXTRACT_OPERAND (RD
, history
[0])
3147 == EXTRACT_OPERAND (RD
, *ip
)))
3148 || ((pinfo
& INSN_WRITE_GPR_31
)
3149 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3150 || (mips_opts
.mips16
3151 && (pinfo
& MIPS16_INSN_WRITE_31
)
3152 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3153 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3154 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3156 /* If the branch writes a register that the previous
3157 instruction reads, we can not swap (we know that
3158 branches only write to RD or to $31). */
3159 || (! mips_opts
.mips16
3160 && (pinfo
& INSN_WRITE_GPR_D
)
3161 && insn_uses_reg (&history
[0],
3162 EXTRACT_OPERAND (RD
, *ip
),
3164 || (! mips_opts
.mips16
3165 && (pinfo
& INSN_WRITE_GPR_31
)
3166 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3167 || (mips_opts
.mips16
3168 && (pinfo
& MIPS16_INSN_WRITE_31
)
3169 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3170 /* If one instruction sets a condition code and the
3171 other one uses a condition code, we can not swap. */
3172 || ((pinfo
& INSN_READ_COND_CODE
)
3173 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3174 || ((pinfo
& INSN_WRITE_COND_CODE
)
3175 && (prev_pinfo
& INSN_READ_COND_CODE
))
3176 /* If the previous instruction uses the PC, we can not
3178 || (mips_opts
.mips16
3179 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3180 /* If the previous instruction had a fixup in mips16
3181 mode, we can not swap. This normally means that the
3182 previous instruction was a 4 byte branch anyhow. */
3183 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3184 /* If the previous instruction is a sync, sync.l, or
3185 sync.p, we can not swap. */
3186 || (prev_pinfo
& INSN_SYNC
))
3188 if (mips_opts
.mips16
3189 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3190 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3191 && ISA_SUPPORTS_MIPS16E
)
3193 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3194 ip
->insn_opcode
|= 0x0080;
3196 insert_into_history (0, 1, ip
);
3200 /* We could do even better for unconditional branches to
3201 portions of this object file; we could pick up the
3202 instruction at the destination, put it in the delay
3203 slot, and bump the destination address. */
3204 insert_into_history (0, 1, ip
);
3208 if (mips_relax
.sequence
)
3209 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3213 /* It looks like we can actually do the swap. */
3214 struct mips_cl_insn delay
= history
[0];
3215 if (mips_opts
.mips16
)
3217 know (delay
.frag
== ip
->frag
);
3218 move_insn (ip
, delay
.frag
, delay
.where
);
3219 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3221 else if (relaxed_branch
)
3223 /* Add the delay slot instruction to the end of the
3224 current frag and shrink the fixed part of the
3225 original frag. If the branch occupies the tail of
3226 the latter, move it backwards to cover the gap. */
3227 delay
.frag
->fr_fix
-= 4;
3228 if (delay
.frag
== ip
->frag
)
3229 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3230 add_fixed_insn (&delay
);
3234 move_insn (&delay
, ip
->frag
, ip
->where
);
3235 move_insn (ip
, history
[0].frag
, history
[0].where
);
3239 insert_into_history (0, 1, &delay
);
3242 /* If that was an unconditional branch, forget the previous
3243 insn information. */
3244 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3245 mips_no_prev_insn ();
3247 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3249 /* We don't yet optimize a branch likely. What we should do
3250 is look at the target, copy the instruction found there
3251 into the delay slot, and increment the branch to jump to
3252 the next instruction. */
3253 insert_into_history (0, 1, ip
);
3257 insert_into_history (0, 1, ip
);
3260 insert_into_history (0, 1, ip
);
3262 /* We just output an insn, so the next one doesn't have a label. */
3263 mips_clear_insn_labels ();
3266 /* Forget that there was any previous instruction or label. */
3269 mips_no_prev_insn (void)
3271 prev_nop_frag
= NULL
;
3272 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3273 mips_clear_insn_labels ();
3276 /* This function must be called before we emit something other than
3277 instructions. It is like mips_no_prev_insn except that it inserts
3278 any NOPS that might be needed by previous instructions. */
3281 mips_emit_delays (void)
3283 if (! mips_opts
.noreorder
)
3285 int nops
= nops_for_insn (history
, NULL
);
3289 add_fixed_insn (NOP_INSN
);
3290 mips_move_labels ();
3293 mips_no_prev_insn ();
3296 /* Start a (possibly nested) noreorder block. */
3299 start_noreorder (void)
3301 if (mips_opts
.noreorder
== 0)
3306 /* None of the instructions before the .set noreorder can be moved. */
3307 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3308 history
[i
].fixed_p
= 1;
3310 /* Insert any nops that might be needed between the .set noreorder
3311 block and the previous instructions. We will later remove any
3312 nops that turn out not to be needed. */
3313 nops
= nops_for_insn (history
, NULL
);
3316 if (mips_optimize
!= 0)
3318 /* Record the frag which holds the nop instructions, so
3319 that we can remove them if we don't need them. */
3320 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3321 prev_nop_frag
= frag_now
;
3322 prev_nop_frag_holds
= nops
;
3323 prev_nop_frag_required
= 0;
3324 prev_nop_frag_since
= 0;
3327 for (; nops
> 0; --nops
)
3328 add_fixed_insn (NOP_INSN
);
3330 /* Move on to a new frag, so that it is safe to simply
3331 decrease the size of prev_nop_frag. */
3332 frag_wane (frag_now
);
3334 mips_move_labels ();
3336 mips16_mark_labels ();
3337 mips_clear_insn_labels ();
3339 mips_opts
.noreorder
++;
3340 mips_any_noreorder
= 1;
3343 /* End a nested noreorder block. */
3346 end_noreorder (void)
3348 mips_opts
.noreorder
--;
3349 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3351 /* Commit to inserting prev_nop_frag_required nops and go back to
3352 handling nop insertion the .set reorder way. */
3353 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3354 * (mips_opts
.mips16
? 2 : 4));
3355 insert_into_history (prev_nop_frag_since
,
3356 prev_nop_frag_required
, NOP_INSN
);
3357 prev_nop_frag
= NULL
;
3361 /* Set up global variables for the start of a new macro. */
3366 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3367 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3368 && (history
[0].insn_mo
->pinfo
3369 & (INSN_UNCOND_BRANCH_DELAY
3370 | INSN_COND_BRANCH_DELAY
3371 | INSN_COND_BRANCH_LIKELY
)) != 0);
3374 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3375 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3376 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3379 macro_warning (relax_substateT subtype
)
3381 if (subtype
& RELAX_DELAY_SLOT
)
3382 return _("Macro instruction expanded into multiple instructions"
3383 " in a branch delay slot");
3384 else if (subtype
& RELAX_NOMACRO
)
3385 return _("Macro instruction expanded into multiple instructions");
3390 /* Finish up a macro. Emit warnings as appropriate. */
3395 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3397 relax_substateT subtype
;
3399 /* Set up the relaxation warning flags. */
3401 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3402 subtype
|= RELAX_SECOND_LONGER
;
3403 if (mips_opts
.warn_about_macros
)
3404 subtype
|= RELAX_NOMACRO
;
3405 if (mips_macro_warning
.delay_slot_p
)
3406 subtype
|= RELAX_DELAY_SLOT
;
3408 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3410 /* Either the macro has a single implementation or both
3411 implementations are longer than 4 bytes. Emit the
3413 const char *msg
= macro_warning (subtype
);
3419 /* One implementation might need a warning but the other
3420 definitely doesn't. */
3421 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3426 /* Read a macro's relocation codes from *ARGS and store them in *R.
3427 The first argument in *ARGS will be either the code for a single
3428 relocation or -1 followed by the three codes that make up a
3429 composite relocation. */
3432 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3436 next
= va_arg (*args
, int);
3438 r
[0] = (bfd_reloc_code_real_type
) next
;
3440 for (i
= 0; i
< 3; i
++)
3441 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3444 /* Build an instruction created by a macro expansion. This is passed
3445 a pointer to the count of instructions created so far, an
3446 expression, the name of the instruction to build, an operand format
3447 string, and corresponding arguments. */
3450 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3452 const struct mips_opcode
*mo
;
3453 struct mips_cl_insn insn
;
3454 bfd_reloc_code_real_type r
[3];
3457 va_start (args
, fmt
);
3459 if (mips_opts
.mips16
)
3461 mips16_macro_build (ep
, name
, fmt
, args
);
3466 r
[0] = BFD_RELOC_UNUSED
;
3467 r
[1] = BFD_RELOC_UNUSED
;
3468 r
[2] = BFD_RELOC_UNUSED
;
3469 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3471 assert (strcmp (name
, mo
->name
) == 0);
3475 /* Search until we get a match for NAME. It is assumed here that
3476 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3477 if (strcmp (fmt
, mo
->args
) == 0
3478 && mo
->pinfo
!= INSN_MACRO
3479 && is_opcode_valid (mo
, TRUE
))
3484 assert (strcmp (name
, mo
->name
) == 0);
3487 create_insn (&insn
, mo
);
3505 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3510 /* Note that in the macro case, these arguments are already
3511 in MSB form. (When handling the instruction in the
3512 non-macro case, these arguments are sizes from which
3513 MSB values must be calculated.) */
3514 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3520 /* Note that in the macro case, these arguments are already
3521 in MSBD form. (When handling the instruction in the
3522 non-macro case, these arguments are sizes from which
3523 MSBD values must be calculated.) */
3524 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3528 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3537 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3543 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3547 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3552 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3558 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3563 int tmp
= va_arg (args
, int);
3565 INSERT_OPERAND (RT
, insn
, tmp
);
3566 INSERT_OPERAND (RD
, insn
, tmp
);
3572 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3579 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3583 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3587 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3591 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3595 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3602 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3608 macro_read_relocs (&args
, r
);
3609 assert (*r
== BFD_RELOC_GPREL16
3610 || *r
== BFD_RELOC_MIPS_LITERAL
3611 || *r
== BFD_RELOC_MIPS_HIGHER
3612 || *r
== BFD_RELOC_HI16_S
3613 || *r
== BFD_RELOC_LO16
3614 || *r
== BFD_RELOC_MIPS_GOT16
3615 || *r
== BFD_RELOC_MIPS_CALL16
3616 || *r
== BFD_RELOC_MIPS_GOT_DISP
3617 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3618 || *r
== BFD_RELOC_MIPS_GOT_OFST
3619 || *r
== BFD_RELOC_MIPS_GOT_LO16
3620 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3624 macro_read_relocs (&args
, r
);
3626 && (ep
->X_op
== O_constant
3627 || (ep
->X_op
== O_symbol
3628 && (*r
== BFD_RELOC_MIPS_HIGHEST
3629 || *r
== BFD_RELOC_HI16_S
3630 || *r
== BFD_RELOC_HI16
3631 || *r
== BFD_RELOC_GPREL16
3632 || *r
== BFD_RELOC_MIPS_GOT_HI16
3633 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3637 assert (ep
!= NULL
);
3640 * This allows macro() to pass an immediate expression for
3641 * creating short branches without creating a symbol.
3643 * We don't allow branch relaxation for these branches, as
3644 * they should only appear in ".set nomacro" anyway.
3646 if (ep
->X_op
== O_constant
)
3648 if ((ep
->X_add_number
& 3) != 0)
3649 as_bad (_("branch to misaligned address (0x%lx)"),
3650 (unsigned long) ep
->X_add_number
);
3651 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3652 as_bad (_("branch address range overflow (0x%lx)"),
3653 (unsigned long) ep
->X_add_number
);
3654 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3658 *r
= BFD_RELOC_16_PCREL_S2
;
3662 assert (ep
!= NULL
);
3663 *r
= BFD_RELOC_MIPS_JMP
;
3667 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3671 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3680 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3682 append_insn (&insn
, ep
, r
);
3686 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3689 struct mips_opcode
*mo
;
3690 struct mips_cl_insn insn
;
3691 bfd_reloc_code_real_type r
[3]
3692 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3694 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3696 assert (strcmp (name
, mo
->name
) == 0);
3698 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3702 assert (strcmp (name
, mo
->name
) == 0);
3705 create_insn (&insn
, mo
);
3723 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3728 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3732 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3736 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3746 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3753 regno
= va_arg (args
, int);
3754 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3755 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3776 assert (ep
!= NULL
);
3778 if (ep
->X_op
!= O_constant
)
3779 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3782 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3783 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3786 *r
= BFD_RELOC_UNUSED
;
3792 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3799 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3801 append_insn (&insn
, ep
, r
);
3805 * Sign-extend 32-bit mode constants that have bit 31 set and all
3806 * higher bits unset.
3809 normalize_constant_expr (expressionS
*ex
)
3811 if (ex
->X_op
== O_constant
3812 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3813 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3818 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3819 * all higher bits unset.
3822 normalize_address_expr (expressionS
*ex
)
3824 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3825 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3826 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3827 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3832 * Generate a "jalr" instruction with a relocation hint to the called
3833 * function. This occurs in NewABI PIC code.
3836 macro_build_jalr (expressionS
*ep
)
3845 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3847 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3848 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3852 * Generate a "lui" instruction.
3855 macro_build_lui (expressionS
*ep
, int regnum
)
3857 expressionS high_expr
;
3858 const struct mips_opcode
*mo
;
3859 struct mips_cl_insn insn
;
3860 bfd_reloc_code_real_type r
[3]
3861 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3862 const char *name
= "lui";
3863 const char *fmt
= "t,u";
3865 assert (! mips_opts
.mips16
);
3869 if (high_expr
.X_op
== O_constant
)
3871 /* We can compute the instruction now without a relocation entry. */
3872 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3874 *r
= BFD_RELOC_UNUSED
;
3878 assert (ep
->X_op
== O_symbol
);
3879 /* _gp_disp is a special case, used from s_cpload.
3880 __gnu_local_gp is used if mips_no_shared. */
3881 assert (mips_pic
== NO_PIC
3883 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3884 || (! mips_in_shared
3885 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3886 "__gnu_local_gp") == 0));
3887 *r
= BFD_RELOC_HI16_S
;
3890 mo
= hash_find (op_hash
, name
);
3891 assert (strcmp (name
, mo
->name
) == 0);
3892 assert (strcmp (fmt
, mo
->args
) == 0);
3893 create_insn (&insn
, mo
);
3895 insn
.insn_opcode
= insn
.insn_mo
->match
;
3896 INSERT_OPERAND (RT
, insn
, regnum
);
3897 if (*r
== BFD_RELOC_UNUSED
)
3899 insn
.insn_opcode
|= high_expr
.X_add_number
;
3900 append_insn (&insn
, NULL
, r
);
3903 append_insn (&insn
, &high_expr
, r
);
3906 /* Generate a sequence of instructions to do a load or store from a constant
3907 offset off of a base register (breg) into/from a target register (treg),
3908 using AT if necessary. */
3910 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3911 int treg
, int breg
, int dbl
)
3913 assert (ep
->X_op
== O_constant
);
3915 /* Sign-extending 32-bit constants makes their handling easier. */
3917 normalize_constant_expr (ep
);
3919 /* Right now, this routine can only handle signed 32-bit constants. */
3920 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3921 as_warn (_("operand overflow"));
3923 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3925 /* Signed 16-bit offset will fit in the op. Easy! */
3926 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3930 /* 32-bit offset, need multiple instructions and AT, like:
3931 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3932 addu $tempreg,$tempreg,$breg
3933 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3934 to handle the complete offset. */
3935 macro_build_lui (ep
, AT
);
3936 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3937 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3940 as_bad (_("Macro used $at after \".set noat\""));
3945 * Generates code to set the $at register to true (one)
3946 * if reg is less than the immediate expression.
3949 set_at (int reg
, int unsignedp
)
3951 if (imm_expr
.X_op
== O_constant
3952 && imm_expr
.X_add_number
>= -0x8000
3953 && imm_expr
.X_add_number
< 0x8000)
3954 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3955 AT
, reg
, BFD_RELOC_LO16
);
3958 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3959 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3963 /* Warn if an expression is not a constant. */
3966 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3968 if (ex
->X_op
== O_big
)
3969 as_bad (_("unsupported large constant"));
3970 else if (ex
->X_op
!= O_constant
)
3971 as_bad (_("Instruction %s requires absolute expression"),
3974 if (HAVE_32BIT_GPRS
)
3975 normalize_constant_expr (ex
);
3978 /* Count the leading zeroes by performing a binary chop. This is a
3979 bulky bit of source, but performance is a LOT better for the
3980 majority of values than a simple loop to count the bits:
3981 for (lcnt = 0; (lcnt < 32); lcnt++)
3982 if ((v) & (1 << (31 - lcnt)))
3984 However it is not code size friendly, and the gain will drop a bit
3985 on certain cached systems.
3987 #define COUNT_TOP_ZEROES(v) \
3988 (((v) & ~0xffff) == 0 \
3989 ? ((v) & ~0xff) == 0 \
3990 ? ((v) & ~0xf) == 0 \
3991 ? ((v) & ~0x3) == 0 \
3992 ? ((v) & ~0x1) == 0 \
3997 : ((v) & ~0x7) == 0 \
4000 : ((v) & ~0x3f) == 0 \
4001 ? ((v) & ~0x1f) == 0 \
4004 : ((v) & ~0x7f) == 0 \
4007 : ((v) & ~0xfff) == 0 \
4008 ? ((v) & ~0x3ff) == 0 \
4009 ? ((v) & ~0x1ff) == 0 \
4012 : ((v) & ~0x7ff) == 0 \
4015 : ((v) & ~0x3fff) == 0 \
4016 ? ((v) & ~0x1fff) == 0 \
4019 : ((v) & ~0x7fff) == 0 \
4022 : ((v) & ~0xffffff) == 0 \
4023 ? ((v) & ~0xfffff) == 0 \
4024 ? ((v) & ~0x3ffff) == 0 \
4025 ? ((v) & ~0x1ffff) == 0 \
4028 : ((v) & ~0x7ffff) == 0 \
4031 : ((v) & ~0x3fffff) == 0 \
4032 ? ((v) & ~0x1fffff) == 0 \
4035 : ((v) & ~0x7fffff) == 0 \
4038 : ((v) & ~0xfffffff) == 0 \
4039 ? ((v) & ~0x3ffffff) == 0 \
4040 ? ((v) & ~0x1ffffff) == 0 \
4043 : ((v) & ~0x7ffffff) == 0 \
4046 : ((v) & ~0x3fffffff) == 0 \
4047 ? ((v) & ~0x1fffffff) == 0 \
4050 : ((v) & ~0x7fffffff) == 0 \
4055 * This routine generates the least number of instructions necessary to load
4056 * an absolute expression value into a register.
4059 load_register (int reg
, expressionS
*ep
, int dbl
)
4062 expressionS hi32
, lo32
;
4064 if (ep
->X_op
!= O_big
)
4066 assert (ep
->X_op
== O_constant
);
4068 /* Sign-extending 32-bit constants makes their handling easier. */
4070 normalize_constant_expr (ep
);
4072 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4074 /* We can handle 16 bit signed values with an addiu to
4075 $zero. No need to ever use daddiu here, since $zero and
4076 the result are always correct in 32 bit mode. */
4077 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4080 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4082 /* We can handle 16 bit unsigned values with an ori to
4084 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4087 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4089 /* 32 bit values require an lui. */
4090 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4091 if ((ep
->X_add_number
& 0xffff) != 0)
4092 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4097 /* The value is larger than 32 bits. */
4099 if (!dbl
|| HAVE_32BIT_GPRS
)
4103 sprintf_vma (value
, ep
->X_add_number
);
4104 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4105 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4109 if (ep
->X_op
!= O_big
)
4112 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4113 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4114 hi32
.X_add_number
&= 0xffffffff;
4116 lo32
.X_add_number
&= 0xffffffff;
4120 assert (ep
->X_add_number
> 2);
4121 if (ep
->X_add_number
== 3)
4122 generic_bignum
[3] = 0;
4123 else if (ep
->X_add_number
> 4)
4124 as_bad (_("Number larger than 64 bits"));
4125 lo32
.X_op
= O_constant
;
4126 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4127 hi32
.X_op
= O_constant
;
4128 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4131 if (hi32
.X_add_number
== 0)
4136 unsigned long hi
, lo
;
4138 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4140 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4142 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4145 if (lo32
.X_add_number
& 0x80000000)
4147 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4148 if (lo32
.X_add_number
& 0xffff)
4149 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4154 /* Check for 16bit shifted constant. We know that hi32 is
4155 non-zero, so start the mask on the first bit of the hi32
4160 unsigned long himask
, lomask
;
4164 himask
= 0xffff >> (32 - shift
);
4165 lomask
= (0xffff << shift
) & 0xffffffff;
4169 himask
= 0xffff << (shift
- 32);
4172 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4173 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4177 tmp
.X_op
= O_constant
;
4179 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4180 | (lo32
.X_add_number
>> shift
));
4182 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4183 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4184 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4185 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4190 while (shift
<= (64 - 16));
4192 /* Find the bit number of the lowest one bit, and store the
4193 shifted value in hi/lo. */
4194 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4195 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4199 while ((lo
& 1) == 0)
4204 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4210 while ((hi
& 1) == 0)
4219 /* Optimize if the shifted value is a (power of 2) - 1. */
4220 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4221 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4223 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4228 /* This instruction will set the register to be all
4230 tmp
.X_op
= O_constant
;
4231 tmp
.X_add_number
= (offsetT
) -1;
4232 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4236 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4237 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4239 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4240 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4245 /* Sign extend hi32 before calling load_register, because we can
4246 generally get better code when we load a sign extended value. */
4247 if ((hi32
.X_add_number
& 0x80000000) != 0)
4248 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4249 load_register (reg
, &hi32
, 0);
4252 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4256 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4264 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4266 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4267 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4273 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4277 mid16
.X_add_number
>>= 16;
4278 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4279 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4282 if ((lo32
.X_add_number
& 0xffff) != 0)
4283 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4287 load_delay_nop (void)
4289 if (!gpr_interlocks
)
4290 macro_build (NULL
, "nop", "");
4293 /* Load an address into a register. */
4296 load_address (int reg
, expressionS
*ep
, int *used_at
)
4298 if (ep
->X_op
!= O_constant
4299 && ep
->X_op
!= O_symbol
)
4301 as_bad (_("expression too complex"));
4302 ep
->X_op
= O_constant
;
4305 if (ep
->X_op
== O_constant
)
4307 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4311 if (mips_pic
== NO_PIC
)
4313 /* If this is a reference to a GP relative symbol, we want
4314 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4316 lui $reg,<sym> (BFD_RELOC_HI16_S)
4317 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4318 If we have an addend, we always use the latter form.
4320 With 64bit address space and a usable $at we want
4321 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4322 lui $at,<sym> (BFD_RELOC_HI16_S)
4323 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4324 daddiu $at,<sym> (BFD_RELOC_LO16)
4328 If $at is already in use, we use a path which is suboptimal
4329 on superscalar processors.
4330 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4331 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4333 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4335 daddiu $reg,<sym> (BFD_RELOC_LO16)
4337 For GP relative symbols in 64bit address space we can use
4338 the same sequence as in 32bit address space. */
4339 if (HAVE_64BIT_SYMBOLS
)
4341 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4342 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4344 relax_start (ep
->X_add_symbol
);
4345 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4346 mips_gp_register
, BFD_RELOC_GPREL16
);
4350 if (*used_at
== 0 && mips_opts
.at
)
4352 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4353 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4354 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4355 BFD_RELOC_MIPS_HIGHER
);
4356 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4357 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4358 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4363 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4364 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4365 BFD_RELOC_MIPS_HIGHER
);
4366 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4367 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4368 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4369 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4372 if (mips_relax
.sequence
)
4377 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4378 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4380 relax_start (ep
->X_add_symbol
);
4381 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4382 mips_gp_register
, BFD_RELOC_GPREL16
);
4385 macro_build_lui (ep
, reg
);
4386 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4387 reg
, reg
, BFD_RELOC_LO16
);
4388 if (mips_relax
.sequence
)
4392 else if (!mips_big_got
)
4396 /* If this is a reference to an external symbol, we want
4397 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4399 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4401 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4402 If there is a constant, it must be added in after.
4404 If we have NewABI, we want
4405 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4406 unless we're referencing a global symbol with a non-zero
4407 offset, in which case cst must be added separately. */
4410 if (ep
->X_add_number
)
4412 ex
.X_add_number
= ep
->X_add_number
;
4413 ep
->X_add_number
= 0;
4414 relax_start (ep
->X_add_symbol
);
4415 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4416 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4417 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4418 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4419 ex
.X_op
= O_constant
;
4420 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4421 reg
, reg
, BFD_RELOC_LO16
);
4422 ep
->X_add_number
= ex
.X_add_number
;
4425 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4426 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4427 if (mips_relax
.sequence
)
4432 ex
.X_add_number
= ep
->X_add_number
;
4433 ep
->X_add_number
= 0;
4434 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4435 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4437 relax_start (ep
->X_add_symbol
);
4439 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4443 if (ex
.X_add_number
!= 0)
4445 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4446 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4447 ex
.X_op
= O_constant
;
4448 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4449 reg
, reg
, BFD_RELOC_LO16
);
4453 else if (mips_big_got
)
4457 /* This is the large GOT case. If this is a reference to an
4458 external symbol, we want
4459 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4461 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4463 Otherwise, for a reference to a local symbol in old ABI, we want
4464 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4466 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4467 If there is a constant, it must be added in after.
4469 In the NewABI, for local symbols, with or without offsets, we want:
4470 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4471 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4475 ex
.X_add_number
= ep
->X_add_number
;
4476 ep
->X_add_number
= 0;
4477 relax_start (ep
->X_add_symbol
);
4478 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4479 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4480 reg
, reg
, mips_gp_register
);
4481 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4482 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4483 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4484 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4485 else if (ex
.X_add_number
)
4487 ex
.X_op
= O_constant
;
4488 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4492 ep
->X_add_number
= ex
.X_add_number
;
4494 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4495 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4496 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4497 BFD_RELOC_MIPS_GOT_OFST
);
4502 ex
.X_add_number
= ep
->X_add_number
;
4503 ep
->X_add_number
= 0;
4504 relax_start (ep
->X_add_symbol
);
4505 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4506 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4507 reg
, reg
, mips_gp_register
);
4508 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4509 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4511 if (reg_needs_delay (mips_gp_register
))
4513 /* We need a nop before loading from $gp. This special
4514 check is required because the lui which starts the main
4515 instruction stream does not refer to $gp, and so will not
4516 insert the nop which may be required. */
4517 macro_build (NULL
, "nop", "");
4519 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4520 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4522 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4526 if (ex
.X_add_number
!= 0)
4528 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4529 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4530 ex
.X_op
= O_constant
;
4531 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4539 if (!mips_opts
.at
&& *used_at
== 1)
4540 as_bad (_("Macro used $at after \".set noat\""));
4543 /* Move the contents of register SOURCE into register DEST. */
4546 move_register (int dest
, int source
)
4548 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4552 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4553 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4554 The two alternatives are:
4556 Global symbol Local sybmol
4557 ------------- ------------
4558 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4560 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4562 load_got_offset emits the first instruction and add_got_offset
4563 emits the second for a 16-bit offset or add_got_offset_hilo emits
4564 a sequence to add a 32-bit offset using a scratch register. */
4567 load_got_offset (int dest
, expressionS
*local
)
4572 global
.X_add_number
= 0;
4574 relax_start (local
->X_add_symbol
);
4575 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4576 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4578 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4579 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4584 add_got_offset (int dest
, expressionS
*local
)
4588 global
.X_op
= O_constant
;
4589 global
.X_op_symbol
= NULL
;
4590 global
.X_add_symbol
= NULL
;
4591 global
.X_add_number
= local
->X_add_number
;
4593 relax_start (local
->X_add_symbol
);
4594 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4595 dest
, dest
, BFD_RELOC_LO16
);
4597 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4602 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4605 int hold_mips_optimize
;
4607 global
.X_op
= O_constant
;
4608 global
.X_op_symbol
= NULL
;
4609 global
.X_add_symbol
= NULL
;
4610 global
.X_add_number
= local
->X_add_number
;
4612 relax_start (local
->X_add_symbol
);
4613 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4615 /* Set mips_optimize around the lui instruction to avoid
4616 inserting an unnecessary nop after the lw. */
4617 hold_mips_optimize
= mips_optimize
;
4619 macro_build_lui (&global
, tmp
);
4620 mips_optimize
= hold_mips_optimize
;
4621 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4624 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4629 * This routine implements the seemingly endless macro or synthesized
4630 * instructions and addressing modes in the mips assembly language. Many
4631 * of these macros are simple and are similar to each other. These could
4632 * probably be handled by some kind of table or grammar approach instead of
4633 * this verbose method. Others are not simple macros but are more like
4634 * optimizing code generation.
4635 * One interesting optimization is when several store macros appear
4636 * consecutively that would load AT with the upper half of the same address.
4637 * The ensuing load upper instructions are ommited. This implies some kind
4638 * of global optimization. We currently only optimize within a single macro.
4639 * For many of the load and store macros if the address is specified as a
4640 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4641 * first load register 'at' with zero and use it as the base register. The
4642 * mips assembler simply uses register $zero. Just one tiny optimization
4646 macro (struct mips_cl_insn
*ip
)
4648 unsigned int treg
, sreg
, dreg
, breg
;
4649 unsigned int tempreg
;
4664 bfd_reloc_code_real_type r
;
4665 int hold_mips_optimize
;
4667 assert (! mips_opts
.mips16
);
4669 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4670 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4671 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4672 mask
= ip
->insn_mo
->mask
;
4674 expr1
.X_op
= O_constant
;
4675 expr1
.X_op_symbol
= NULL
;
4676 expr1
.X_add_symbol
= NULL
;
4677 expr1
.X_add_number
= 1;
4691 expr1
.X_add_number
= 8;
4692 macro_build (&expr1
, "bgez", "s,p", sreg
);
4694 macro_build (NULL
, "nop", "", 0);
4696 move_register (dreg
, sreg
);
4697 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4720 if (imm_expr
.X_op
== O_constant
4721 && imm_expr
.X_add_number
>= -0x8000
4722 && imm_expr
.X_add_number
< 0x8000)
4724 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4728 load_register (AT
, &imm_expr
, dbl
);
4729 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4748 if (imm_expr
.X_op
== O_constant
4749 && imm_expr
.X_add_number
>= 0
4750 && imm_expr
.X_add_number
< 0x10000)
4752 if (mask
!= M_NOR_I
)
4753 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4756 macro_build (&imm_expr
, "ori", "t,r,i",
4757 treg
, sreg
, BFD_RELOC_LO16
);
4758 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4764 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4765 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4769 switch (imm_expr
.X_add_number
)
4772 macro_build (NULL
, "nop", "");
4775 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4778 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4779 (int)imm_expr
.X_add_number
);
4798 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4800 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4804 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4805 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4813 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4818 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4822 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4823 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4829 /* check for > max integer */
4830 maxnum
= 0x7fffffff;
4831 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4838 if (imm_expr
.X_op
== O_constant
4839 && imm_expr
.X_add_number
>= maxnum
4840 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4843 /* result is always false */
4845 macro_build (NULL
, "nop", "", 0);
4847 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4850 if (imm_expr
.X_op
!= O_constant
)
4851 as_bad (_("Unsupported large constant"));
4852 ++imm_expr
.X_add_number
;
4856 if (mask
== M_BGEL_I
)
4858 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4860 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4863 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4865 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4868 maxnum
= 0x7fffffff;
4869 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4876 maxnum
= - maxnum
- 1;
4877 if (imm_expr
.X_op
== O_constant
4878 && imm_expr
.X_add_number
<= maxnum
4879 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4882 /* result is always true */
4883 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4884 macro_build (&offset_expr
, "b", "p");
4889 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4899 macro_build (&offset_expr
, likely
? "beql" : "beq",
4904 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4905 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4913 && imm_expr
.X_op
== O_constant
4914 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4916 if (imm_expr
.X_op
!= O_constant
)
4917 as_bad (_("Unsupported large constant"));
4918 ++imm_expr
.X_add_number
;
4922 if (mask
== M_BGEUL_I
)
4924 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4926 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4928 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4934 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4942 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4947 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4951 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4952 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4960 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4967 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4968 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4976 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4981 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4985 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4986 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4992 maxnum
= 0x7fffffff;
4993 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5000 if (imm_expr
.X_op
== O_constant
5001 && imm_expr
.X_add_number
>= maxnum
5002 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5004 if (imm_expr
.X_op
!= O_constant
)
5005 as_bad (_("Unsupported large constant"));
5006 ++imm_expr
.X_add_number
;
5010 if (mask
== M_BLTL_I
)
5012 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5014 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5017 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5019 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5024 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5032 macro_build (&offset_expr
, likely
? "beql" : "beq",
5039 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5040 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5048 && imm_expr
.X_op
== O_constant
5049 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5051 if (imm_expr
.X_op
!= O_constant
)
5052 as_bad (_("Unsupported large constant"));
5053 ++imm_expr
.X_add_number
;
5057 if (mask
== M_BLTUL_I
)
5059 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5061 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5063 macro_build (&offset_expr
, likely
? "beql" : "beq",
5069 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5077 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5082 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5086 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5087 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5097 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5102 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5103 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5111 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5113 as_bad (_("Unsupported large constant"));
5118 pos
= (unsigned long) imm_expr
.X_add_number
;
5119 size
= (unsigned long) imm2_expr
.X_add_number
;
5124 as_bad (_("Improper position (%lu)"), pos
);
5127 if (size
== 0 || size
> 64
5128 || (pos
+ size
- 1) > 63)
5130 as_bad (_("Improper extract size (%lu, position %lu)"),
5135 if (size
<= 32 && pos
< 32)
5140 else if (size
<= 32)
5150 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5159 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5161 as_bad (_("Unsupported large constant"));
5166 pos
= (unsigned long) imm_expr
.X_add_number
;
5167 size
= (unsigned long) imm2_expr
.X_add_number
;
5172 as_bad (_("Improper position (%lu)"), pos
);
5175 if (size
== 0 || size
> 64
5176 || (pos
+ size
- 1) > 63)
5178 as_bad (_("Improper insert size (%lu, position %lu)"),
5183 if (pos
< 32 && (pos
+ size
- 1) < 32)
5198 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5215 as_warn (_("Divide by zero."));
5217 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5219 macro_build (NULL
, "break", "c", 7);
5226 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5227 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5231 expr1
.X_add_number
= 8;
5232 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5233 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5234 macro_build (NULL
, "break", "c", 7);
5236 expr1
.X_add_number
= -1;
5238 load_register (AT
, &expr1
, dbl
);
5239 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5240 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5243 expr1
.X_add_number
= 1;
5244 load_register (AT
, &expr1
, dbl
);
5245 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5249 expr1
.X_add_number
= 0x80000000;
5250 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5254 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5255 /* We want to close the noreorder block as soon as possible, so
5256 that later insns are available for delay slot filling. */
5261 expr1
.X_add_number
= 8;
5262 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5263 macro_build (NULL
, "nop", "", 0);
5265 /* We want to close the noreorder block as soon as possible, so
5266 that later insns are available for delay slot filling. */
5269 macro_build (NULL
, "break", "c", 6);
5271 macro_build (NULL
, s
, "d", dreg
);
5310 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5312 as_warn (_("Divide by zero."));
5314 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5316 macro_build (NULL
, "break", "c", 7);
5319 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5321 if (strcmp (s2
, "mflo") == 0)
5322 move_register (dreg
, sreg
);
5324 move_register (dreg
, 0);
5327 if (imm_expr
.X_op
== O_constant
5328 && imm_expr
.X_add_number
== -1
5329 && s
[strlen (s
) - 1] != 'u')
5331 if (strcmp (s2
, "mflo") == 0)
5333 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5336 move_register (dreg
, 0);
5341 load_register (AT
, &imm_expr
, dbl
);
5342 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5343 macro_build (NULL
, s2
, "d", dreg
);
5365 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5366 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5367 /* We want to close the noreorder block as soon as possible, so
5368 that later insns are available for delay slot filling. */
5373 expr1
.X_add_number
= 8;
5374 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5375 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5377 /* We want to close the noreorder block as soon as possible, so
5378 that later insns are available for delay slot filling. */
5380 macro_build (NULL
, "break", "c", 7);
5382 macro_build (NULL
, s2
, "d", dreg
);
5394 /* Load the address of a symbol into a register. If breg is not
5395 zero, we then add a base register to it. */
5397 if (dbl
&& HAVE_32BIT_GPRS
)
5398 as_warn (_("dla used to load 32-bit register"));
5400 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5401 as_warn (_("la used to load 64-bit address"));
5403 if (offset_expr
.X_op
== O_constant
5404 && offset_expr
.X_add_number
>= -0x8000
5405 && offset_expr
.X_add_number
< 0x8000)
5407 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5408 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5412 if (mips_opts
.at
&& (treg
== breg
))
5422 if (offset_expr
.X_op
!= O_symbol
5423 && offset_expr
.X_op
!= O_constant
)
5425 as_bad (_("expression too complex"));
5426 offset_expr
.X_op
= O_constant
;
5429 if (offset_expr
.X_op
== O_constant
)
5430 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5431 else if (mips_pic
== NO_PIC
)
5433 /* If this is a reference to a GP relative symbol, we want
5434 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5436 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5437 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5438 If we have a constant, we need two instructions anyhow,
5439 so we may as well always use the latter form.
5441 With 64bit address space and a usable $at we want
5442 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5443 lui $at,<sym> (BFD_RELOC_HI16_S)
5444 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5445 daddiu $at,<sym> (BFD_RELOC_LO16)
5447 daddu $tempreg,$tempreg,$at
5449 If $at is already in use, we use a path which is suboptimal
5450 on superscalar processors.
5451 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5452 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5454 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5456 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5458 For GP relative symbols in 64bit address space we can use
5459 the same sequence as in 32bit address space. */
5460 if (HAVE_64BIT_SYMBOLS
)
5462 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5463 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5465 relax_start (offset_expr
.X_add_symbol
);
5466 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5467 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5471 if (used_at
== 0 && mips_opts
.at
)
5473 macro_build (&offset_expr
, "lui", "t,u",
5474 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5475 macro_build (&offset_expr
, "lui", "t,u",
5476 AT
, BFD_RELOC_HI16_S
);
5477 macro_build (&offset_expr
, "daddiu", "t,r,j",
5478 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5479 macro_build (&offset_expr
, "daddiu", "t,r,j",
5480 AT
, AT
, BFD_RELOC_LO16
);
5481 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5482 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5487 macro_build (&offset_expr
, "lui", "t,u",
5488 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5489 macro_build (&offset_expr
, "daddiu", "t,r,j",
5490 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5491 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5492 macro_build (&offset_expr
, "daddiu", "t,r,j",
5493 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5494 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5495 macro_build (&offset_expr
, "daddiu", "t,r,j",
5496 tempreg
, tempreg
, BFD_RELOC_LO16
);
5499 if (mips_relax
.sequence
)
5504 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5505 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5507 relax_start (offset_expr
.X_add_symbol
);
5508 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5509 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5512 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5513 as_bad (_("offset too large"));
5514 macro_build_lui (&offset_expr
, tempreg
);
5515 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5516 tempreg
, tempreg
, BFD_RELOC_LO16
);
5517 if (mips_relax
.sequence
)
5521 else if (!mips_big_got
&& !HAVE_NEWABI
)
5523 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5525 /* If this is a reference to an external symbol, and there
5526 is no constant, we want
5527 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5528 or for lca or if tempreg is PIC_CALL_REG
5529 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5530 For a local symbol, we want
5531 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5533 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5535 If we have a small constant, and this is a reference to
5536 an external symbol, we want
5537 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5539 addiu $tempreg,$tempreg,<constant>
5540 For a local symbol, we want the same instruction
5541 sequence, but we output a BFD_RELOC_LO16 reloc on the
5544 If we have a large constant, and this is a reference to
5545 an external symbol, we want
5546 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5547 lui $at,<hiconstant>
5548 addiu $at,$at,<loconstant>
5549 addu $tempreg,$tempreg,$at
5550 For a local symbol, we want the same instruction
5551 sequence, but we output a BFD_RELOC_LO16 reloc on the
5555 if (offset_expr
.X_add_number
== 0)
5557 if (mips_pic
== SVR4_PIC
5559 && (call
|| tempreg
== PIC_CALL_REG
))
5560 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5562 relax_start (offset_expr
.X_add_symbol
);
5563 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5564 lw_reloc_type
, mips_gp_register
);
5567 /* We're going to put in an addu instruction using
5568 tempreg, so we may as well insert the nop right
5573 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5574 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5576 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5577 tempreg
, tempreg
, BFD_RELOC_LO16
);
5579 /* FIXME: If breg == 0, and the next instruction uses
5580 $tempreg, then if this variant case is used an extra
5581 nop will be generated. */
5583 else if (offset_expr
.X_add_number
>= -0x8000
5584 && offset_expr
.X_add_number
< 0x8000)
5586 load_got_offset (tempreg
, &offset_expr
);
5588 add_got_offset (tempreg
, &offset_expr
);
5592 expr1
.X_add_number
= offset_expr
.X_add_number
;
5593 offset_expr
.X_add_number
=
5594 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5595 load_got_offset (tempreg
, &offset_expr
);
5596 offset_expr
.X_add_number
= expr1
.X_add_number
;
5597 /* If we are going to add in a base register, and the
5598 target register and the base register are the same,
5599 then we are using AT as a temporary register. Since
5600 we want to load the constant into AT, we add our
5601 current AT (from the global offset table) and the
5602 register into the register now, and pretend we were
5603 not using a base register. */
5607 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5612 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5616 else if (!mips_big_got
&& HAVE_NEWABI
)
5618 int add_breg_early
= 0;
5620 /* If this is a reference to an external, and there is no
5621 constant, or local symbol (*), with or without a
5623 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5624 or for lca or if tempreg is PIC_CALL_REG
5625 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5627 If we have a small constant, and this is a reference to
5628 an external symbol, we want
5629 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5630 addiu $tempreg,$tempreg,<constant>
5632 If we have a large constant, and this is a reference to
5633 an external symbol, we want
5634 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5635 lui $at,<hiconstant>
5636 addiu $at,$at,<loconstant>
5637 addu $tempreg,$tempreg,$at
5639 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5640 local symbols, even though it introduces an additional
5643 if (offset_expr
.X_add_number
)
5645 expr1
.X_add_number
= offset_expr
.X_add_number
;
5646 offset_expr
.X_add_number
= 0;
5648 relax_start (offset_expr
.X_add_symbol
);
5649 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5650 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5652 if (expr1
.X_add_number
>= -0x8000
5653 && expr1
.X_add_number
< 0x8000)
5655 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5656 tempreg
, tempreg
, BFD_RELOC_LO16
);
5658 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5662 /* If we are going to add in a base register, and the
5663 target register and the base register are the same,
5664 then we are using AT as a temporary register. Since
5665 we want to load the constant into AT, we add our
5666 current AT (from the global offset table) and the
5667 register into the register now, and pretend we were
5668 not using a base register. */
5673 assert (tempreg
== AT
);
5674 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5680 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5687 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5690 offset_expr
.X_add_number
= expr1
.X_add_number
;
5692 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5693 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5696 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5697 treg
, tempreg
, breg
);
5703 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5705 relax_start (offset_expr
.X_add_symbol
);
5706 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5707 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5709 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5710 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5715 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5716 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5719 else if (mips_big_got
&& !HAVE_NEWABI
)
5722 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5723 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5724 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5726 /* This is the large GOT case. If this is a reference to an
5727 external symbol, and there is no constant, we want
5728 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5729 addu $tempreg,$tempreg,$gp
5730 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5731 or for lca or if tempreg is PIC_CALL_REG
5732 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5733 addu $tempreg,$tempreg,$gp
5734 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5735 For a local symbol, we want
5736 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5738 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5740 If we have a small constant, and this is a reference to
5741 an external symbol, we want
5742 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5743 addu $tempreg,$tempreg,$gp
5744 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5746 addiu $tempreg,$tempreg,<constant>
5747 For a local symbol, we want
5748 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5750 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5752 If we have a large constant, and this is a reference to
5753 an external symbol, we want
5754 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5755 addu $tempreg,$tempreg,$gp
5756 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5757 lui $at,<hiconstant>
5758 addiu $at,$at,<loconstant>
5759 addu $tempreg,$tempreg,$at
5760 For a local symbol, we want
5761 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5762 lui $at,<hiconstant>
5763 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5764 addu $tempreg,$tempreg,$at
5767 expr1
.X_add_number
= offset_expr
.X_add_number
;
5768 offset_expr
.X_add_number
= 0;
5769 relax_start (offset_expr
.X_add_symbol
);
5770 gpdelay
= reg_needs_delay (mips_gp_register
);
5771 if (expr1
.X_add_number
== 0 && breg
== 0
5772 && (call
|| tempreg
== PIC_CALL_REG
))
5774 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5775 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5777 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5778 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5779 tempreg
, tempreg
, mips_gp_register
);
5780 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5781 tempreg
, lw_reloc_type
, tempreg
);
5782 if (expr1
.X_add_number
== 0)
5786 /* We're going to put in an addu instruction using
5787 tempreg, so we may as well insert the nop right
5792 else if (expr1
.X_add_number
>= -0x8000
5793 && expr1
.X_add_number
< 0x8000)
5796 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5797 tempreg
, tempreg
, BFD_RELOC_LO16
);
5803 /* If we are going to add in a base register, and the
5804 target register and the base register are the same,
5805 then we are using AT as a temporary register. Since
5806 we want to load the constant into AT, we add our
5807 current AT (from the global offset table) and the
5808 register into the register now, and pretend we were
5809 not using a base register. */
5814 assert (tempreg
== AT
);
5816 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5821 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5822 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5826 offset_expr
.X_add_number
=
5827 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5832 /* This is needed because this instruction uses $gp, but
5833 the first instruction on the main stream does not. */
5834 macro_build (NULL
, "nop", "");
5837 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5838 local_reloc_type
, mips_gp_register
);
5839 if (expr1
.X_add_number
>= -0x8000
5840 && expr1
.X_add_number
< 0x8000)
5843 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5844 tempreg
, tempreg
, BFD_RELOC_LO16
);
5845 /* FIXME: If add_number is 0, and there was no base
5846 register, the external symbol case ended with a load,
5847 so if the symbol turns out to not be external, and
5848 the next instruction uses tempreg, an unnecessary nop
5849 will be inserted. */
5855 /* We must add in the base register now, as in the
5856 external symbol case. */
5857 assert (tempreg
== AT
);
5859 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5862 /* We set breg to 0 because we have arranged to add
5863 it in in both cases. */
5867 macro_build_lui (&expr1
, AT
);
5868 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5869 AT
, AT
, BFD_RELOC_LO16
);
5870 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5871 tempreg
, tempreg
, AT
);
5876 else if (mips_big_got
&& HAVE_NEWABI
)
5878 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5879 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5880 int add_breg_early
= 0;
5882 /* This is the large GOT case. If this is a reference to an
5883 external symbol, and there is no constant, we want
5884 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5885 add $tempreg,$tempreg,$gp
5886 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5887 or for lca or if tempreg is PIC_CALL_REG
5888 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5889 add $tempreg,$tempreg,$gp
5890 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5892 If we have a small constant, and this is a reference to
5893 an external symbol, we want
5894 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5895 add $tempreg,$tempreg,$gp
5896 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5897 addi $tempreg,$tempreg,<constant>
5899 If we have a large constant, and this is a reference to
5900 an external symbol, we want
5901 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5902 addu $tempreg,$tempreg,$gp
5903 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5904 lui $at,<hiconstant>
5905 addi $at,$at,<loconstant>
5906 add $tempreg,$tempreg,$at
5908 If we have NewABI, and we know it's a local symbol, we want
5909 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5910 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5911 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5913 relax_start (offset_expr
.X_add_symbol
);
5915 expr1
.X_add_number
= offset_expr
.X_add_number
;
5916 offset_expr
.X_add_number
= 0;
5918 if (expr1
.X_add_number
== 0 && breg
== 0
5919 && (call
|| tempreg
== PIC_CALL_REG
))
5921 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5922 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5924 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5926 tempreg
, tempreg
, mips_gp_register
);
5927 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5928 tempreg
, lw_reloc_type
, tempreg
);
5930 if (expr1
.X_add_number
== 0)
5932 else if (expr1
.X_add_number
>= -0x8000
5933 && expr1
.X_add_number
< 0x8000)
5935 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5936 tempreg
, tempreg
, BFD_RELOC_LO16
);
5938 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5942 /* If we are going to add in a base register, and the
5943 target register and the base register are the same,
5944 then we are using AT as a temporary register. Since
5945 we want to load the constant into AT, we add our
5946 current AT (from the global offset table) and the
5947 register into the register now, and pretend we were
5948 not using a base register. */
5953 assert (tempreg
== AT
);
5954 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5960 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5961 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5966 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5969 offset_expr
.X_add_number
= expr1
.X_add_number
;
5970 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5971 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5972 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5973 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5976 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5977 treg
, tempreg
, breg
);
5987 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5991 /* The j instruction may not be used in PIC code, since it
5992 requires an absolute address. We convert it to a b
5994 if (mips_pic
== NO_PIC
)
5995 macro_build (&offset_expr
, "j", "a");
5997 macro_build (&offset_expr
, "b", "p");
6000 /* The jal instructions must be handled as macros because when
6001 generating PIC code they expand to multi-instruction
6002 sequences. Normally they are simple instructions. */
6007 if (mips_pic
== NO_PIC
)
6008 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6011 if (sreg
!= PIC_CALL_REG
)
6012 as_warn (_("MIPS PIC call to register other than $25"));
6014 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6015 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6017 if (mips_cprestore_offset
< 0)
6018 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6021 if (! mips_frame_reg_valid
)
6023 as_warn (_("No .frame pseudo-op used in PIC code"));
6024 /* Quiet this warning. */
6025 mips_frame_reg_valid
= 1;
6027 if (! mips_cprestore_valid
)
6029 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6030 /* Quiet this warning. */
6031 mips_cprestore_valid
= 1;
6033 expr1
.X_add_number
= mips_cprestore_offset
;
6034 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6037 HAVE_64BIT_ADDRESSES
);
6045 if (mips_pic
== NO_PIC
)
6046 macro_build (&offset_expr
, "jal", "a");
6047 else if (mips_pic
== SVR4_PIC
)
6049 /* If this is a reference to an external symbol, and we are
6050 using a small GOT, we want
6051 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6055 lw $gp,cprestore($sp)
6056 The cprestore value is set using the .cprestore
6057 pseudo-op. If we are using a big GOT, we want
6058 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6060 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6064 lw $gp,cprestore($sp)
6065 If the symbol is not external, we want
6066 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6068 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6071 lw $gp,cprestore($sp)
6073 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6074 sequences above, minus nops, unless the symbol is local,
6075 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6081 relax_start (offset_expr
.X_add_symbol
);
6082 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6083 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6086 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6087 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6093 relax_start (offset_expr
.X_add_symbol
);
6094 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6095 BFD_RELOC_MIPS_CALL_HI16
);
6096 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6097 PIC_CALL_REG
, mips_gp_register
);
6098 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6099 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6102 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6103 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6105 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6106 PIC_CALL_REG
, PIC_CALL_REG
,
6107 BFD_RELOC_MIPS_GOT_OFST
);
6111 macro_build_jalr (&offset_expr
);
6115 relax_start (offset_expr
.X_add_symbol
);
6118 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6119 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6128 gpdelay
= reg_needs_delay (mips_gp_register
);
6129 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6130 BFD_RELOC_MIPS_CALL_HI16
);
6131 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6132 PIC_CALL_REG
, mips_gp_register
);
6133 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6134 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6139 macro_build (NULL
, "nop", "");
6141 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6142 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6145 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6146 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6148 macro_build_jalr (&offset_expr
);
6150 if (mips_cprestore_offset
< 0)
6151 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6154 if (! mips_frame_reg_valid
)
6156 as_warn (_("No .frame pseudo-op used in PIC code"));
6157 /* Quiet this warning. */
6158 mips_frame_reg_valid
= 1;
6160 if (! mips_cprestore_valid
)
6162 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6163 /* Quiet this warning. */
6164 mips_cprestore_valid
= 1;
6166 if (mips_opts
.noreorder
)
6167 macro_build (NULL
, "nop", "");
6168 expr1
.X_add_number
= mips_cprestore_offset
;
6169 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6172 HAVE_64BIT_ADDRESSES
);
6176 else if (mips_pic
== VXWORKS_PIC
)
6177 as_bad (_("Non-PIC jump used in PIC library"));
6200 /* Itbl support may require additional care here. */
6205 /* Itbl support may require additional care here. */
6210 /* Itbl support may require additional care here. */
6215 /* Itbl support may require additional care here. */
6228 /* Itbl support may require additional care here. */
6233 /* Itbl support may require additional care here. */
6238 /* Itbl support may require additional care here. */
6258 if (breg
== treg
|| coproc
|| lr
)
6279 /* Itbl support may require additional care here. */
6284 /* Itbl support may require additional care here. */
6289 /* Itbl support may require additional care here. */
6294 /* Itbl support may require additional care here. */
6315 /* Itbl support may require additional care here. */
6319 /* Itbl support may require additional care here. */
6324 /* Itbl support may require additional care here. */
6337 && NO_ISA_COP (mips_opts
.arch
)
6338 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6340 as_bad (_("opcode not supported on this processor: %s"),
6341 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6345 /* Itbl support may require additional care here. */
6346 if (mask
== M_LWC1_AB
6347 || mask
== M_SWC1_AB
6348 || mask
== M_LDC1_AB
6349 || mask
== M_SDC1_AB
6353 else if (mask
== M_CACHE_AB
)
6360 if (offset_expr
.X_op
!= O_constant
6361 && offset_expr
.X_op
!= O_symbol
)
6363 as_bad (_("expression too complex"));
6364 offset_expr
.X_op
= O_constant
;
6367 if (HAVE_32BIT_ADDRESSES
6368 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6372 sprintf_vma (value
, offset_expr
.X_add_number
);
6373 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6376 /* A constant expression in PIC code can be handled just as it
6377 is in non PIC code. */
6378 if (offset_expr
.X_op
== O_constant
)
6380 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6381 & ~(bfd_vma
) 0xffff);
6382 normalize_address_expr (&expr1
);
6383 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6385 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6386 tempreg
, tempreg
, breg
);
6387 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6389 else if (mips_pic
== NO_PIC
)
6391 /* If this is a reference to a GP relative symbol, and there
6392 is no base register, we want
6393 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6394 Otherwise, if there is no base register, we want
6395 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6396 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6397 If we have a constant, we need two instructions anyhow,
6398 so we always use the latter form.
6400 If we have a base register, and this is a reference to a
6401 GP relative symbol, we want
6402 addu $tempreg,$breg,$gp
6403 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6405 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6406 addu $tempreg,$tempreg,$breg
6407 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6408 With a constant we always use the latter case.
6410 With 64bit address space and no base register and $at usable,
6412 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6413 lui $at,<sym> (BFD_RELOC_HI16_S)
6414 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6417 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6418 If we have a base register, we want
6419 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6420 lui $at,<sym> (BFD_RELOC_HI16_S)
6421 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6425 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6427 Without $at we can't generate the optimal path for superscalar
6428 processors here since this would require two temporary registers.
6429 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6430 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6432 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6434 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6435 If we have a base register, we want
6436 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6437 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6439 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6441 daddu $tempreg,$tempreg,$breg
6442 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6444 For GP relative symbols in 64bit address space we can use
6445 the same sequence as in 32bit address space. */
6446 if (HAVE_64BIT_SYMBOLS
)
6448 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6449 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6451 relax_start (offset_expr
.X_add_symbol
);
6454 macro_build (&offset_expr
, s
, fmt
, treg
,
6455 BFD_RELOC_GPREL16
, mips_gp_register
);
6459 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6460 tempreg
, breg
, mips_gp_register
);
6461 macro_build (&offset_expr
, s
, fmt
, treg
,
6462 BFD_RELOC_GPREL16
, tempreg
);
6467 if (used_at
== 0 && mips_opts
.at
)
6469 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6470 BFD_RELOC_MIPS_HIGHEST
);
6471 macro_build (&offset_expr
, "lui", "t,u", AT
,
6473 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6474 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6476 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6477 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6478 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6479 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6485 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6486 BFD_RELOC_MIPS_HIGHEST
);
6487 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6488 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6489 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6490 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6491 tempreg
, BFD_RELOC_HI16_S
);
6492 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6494 macro_build (NULL
, "daddu", "d,v,t",
6495 tempreg
, tempreg
, breg
);
6496 macro_build (&offset_expr
, s
, fmt
, treg
,
6497 BFD_RELOC_LO16
, tempreg
);
6500 if (mips_relax
.sequence
)
6507 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6508 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6510 relax_start (offset_expr
.X_add_symbol
);
6511 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6515 macro_build_lui (&offset_expr
, tempreg
);
6516 macro_build (&offset_expr
, s
, fmt
, treg
,
6517 BFD_RELOC_LO16
, tempreg
);
6518 if (mips_relax
.sequence
)
6523 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6524 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6526 relax_start (offset_expr
.X_add_symbol
);
6527 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6528 tempreg
, breg
, mips_gp_register
);
6529 macro_build (&offset_expr
, s
, fmt
, treg
,
6530 BFD_RELOC_GPREL16
, tempreg
);
6533 macro_build_lui (&offset_expr
, tempreg
);
6534 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6535 tempreg
, tempreg
, breg
);
6536 macro_build (&offset_expr
, s
, fmt
, treg
,
6537 BFD_RELOC_LO16
, tempreg
);
6538 if (mips_relax
.sequence
)
6542 else if (!mips_big_got
)
6544 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6546 /* If this is a reference to an external symbol, we want
6547 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6549 <op> $treg,0($tempreg)
6551 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6553 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6554 <op> $treg,0($tempreg)
6557 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6558 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6560 If there is a base register, we add it to $tempreg before
6561 the <op>. If there is a constant, we stick it in the
6562 <op> instruction. We don't handle constants larger than
6563 16 bits, because we have no way to load the upper 16 bits
6564 (actually, we could handle them for the subset of cases
6565 in which we are not using $at). */
6566 assert (offset_expr
.X_op
== O_symbol
);
6569 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6570 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6572 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6573 tempreg
, tempreg
, breg
);
6574 macro_build (&offset_expr
, s
, fmt
, treg
,
6575 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6578 expr1
.X_add_number
= offset_expr
.X_add_number
;
6579 offset_expr
.X_add_number
= 0;
6580 if (expr1
.X_add_number
< -0x8000
6581 || expr1
.X_add_number
>= 0x8000)
6582 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6583 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6584 lw_reloc_type
, mips_gp_register
);
6586 relax_start (offset_expr
.X_add_symbol
);
6588 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6589 tempreg
, BFD_RELOC_LO16
);
6592 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6593 tempreg
, tempreg
, breg
);
6594 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6596 else if (mips_big_got
&& !HAVE_NEWABI
)
6600 /* If this is a reference to an external symbol, we want
6601 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6602 addu $tempreg,$tempreg,$gp
6603 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6604 <op> $treg,0($tempreg)
6606 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6608 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6609 <op> $treg,0($tempreg)
6610 If there is a base register, we add it to $tempreg before
6611 the <op>. If there is a constant, we stick it in the
6612 <op> instruction. We don't handle constants larger than
6613 16 bits, because we have no way to load the upper 16 bits
6614 (actually, we could handle them for the subset of cases
6615 in which we are not using $at). */
6616 assert (offset_expr
.X_op
== O_symbol
);
6617 expr1
.X_add_number
= offset_expr
.X_add_number
;
6618 offset_expr
.X_add_number
= 0;
6619 if (expr1
.X_add_number
< -0x8000
6620 || expr1
.X_add_number
>= 0x8000)
6621 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6622 gpdelay
= reg_needs_delay (mips_gp_register
);
6623 relax_start (offset_expr
.X_add_symbol
);
6624 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6625 BFD_RELOC_MIPS_GOT_HI16
);
6626 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6628 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6629 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6632 macro_build (NULL
, "nop", "");
6633 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6634 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6636 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6637 tempreg
, BFD_RELOC_LO16
);
6641 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6642 tempreg
, tempreg
, breg
);
6643 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6645 else if (mips_big_got
&& HAVE_NEWABI
)
6647 /* If this is a reference to an external symbol, we want
6648 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6649 add $tempreg,$tempreg,$gp
6650 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6651 <op> $treg,<ofst>($tempreg)
6652 Otherwise, for local symbols, we want:
6653 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6654 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6655 assert (offset_expr
.X_op
== O_symbol
);
6656 expr1
.X_add_number
= offset_expr
.X_add_number
;
6657 offset_expr
.X_add_number
= 0;
6658 if (expr1
.X_add_number
< -0x8000
6659 || expr1
.X_add_number
>= 0x8000)
6660 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6661 relax_start (offset_expr
.X_add_symbol
);
6662 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6663 BFD_RELOC_MIPS_GOT_HI16
);
6664 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6666 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6667 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6669 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6670 tempreg
, tempreg
, breg
);
6671 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6674 offset_expr
.X_add_number
= expr1
.X_add_number
;
6675 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6676 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6678 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6679 tempreg
, tempreg
, breg
);
6680 macro_build (&offset_expr
, s
, fmt
, treg
,
6681 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6691 load_register (treg
, &imm_expr
, 0);
6695 load_register (treg
, &imm_expr
, 1);
6699 if (imm_expr
.X_op
== O_constant
)
6702 load_register (AT
, &imm_expr
, 0);
6703 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6708 assert (offset_expr
.X_op
== O_symbol
6709 && strcmp (segment_name (S_GET_SEGMENT
6710 (offset_expr
.X_add_symbol
)),
6712 && offset_expr
.X_add_number
== 0);
6713 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6714 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6719 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6720 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6721 order 32 bits of the value and the low order 32 bits are either
6722 zero or in OFFSET_EXPR. */
6723 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6725 if (HAVE_64BIT_GPRS
)
6726 load_register (treg
, &imm_expr
, 1);
6731 if (target_big_endian
)
6743 load_register (hreg
, &imm_expr
, 0);
6746 if (offset_expr
.X_op
== O_absent
)
6747 move_register (lreg
, 0);
6750 assert (offset_expr
.X_op
== O_constant
);
6751 load_register (lreg
, &offset_expr
, 0);
6758 /* We know that sym is in the .rdata section. First we get the
6759 upper 16 bits of the address. */
6760 if (mips_pic
== NO_PIC
)
6762 macro_build_lui (&offset_expr
, AT
);
6767 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6768 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6772 /* Now we load the register(s). */
6773 if (HAVE_64BIT_GPRS
)
6776 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6781 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6784 /* FIXME: How in the world do we deal with the possible
6786 offset_expr
.X_add_number
+= 4;
6787 macro_build (&offset_expr
, "lw", "t,o(b)",
6788 treg
+ 1, BFD_RELOC_LO16
, AT
);
6794 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6795 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6796 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6797 the value and the low order 32 bits are either zero or in
6799 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6802 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6803 if (HAVE_64BIT_FPRS
)
6805 assert (HAVE_64BIT_GPRS
);
6806 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6810 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6811 if (offset_expr
.X_op
== O_absent
)
6812 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6815 assert (offset_expr
.X_op
== O_constant
);
6816 load_register (AT
, &offset_expr
, 0);
6817 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6823 assert (offset_expr
.X_op
== O_symbol
6824 && offset_expr
.X_add_number
== 0);
6825 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6826 if (strcmp (s
, ".lit8") == 0)
6828 if (mips_opts
.isa
!= ISA_MIPS1
)
6830 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6831 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6834 breg
= mips_gp_register
;
6835 r
= BFD_RELOC_MIPS_LITERAL
;
6840 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6842 if (mips_pic
!= NO_PIC
)
6843 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6844 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6847 /* FIXME: This won't work for a 64 bit address. */
6848 macro_build_lui (&offset_expr
, AT
);
6851 if (mips_opts
.isa
!= ISA_MIPS1
)
6853 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6854 treg
, BFD_RELOC_LO16
, AT
);
6863 /* Even on a big endian machine $fn comes before $fn+1. We have
6864 to adjust when loading from memory. */
6867 assert (mips_opts
.isa
== ISA_MIPS1
);
6868 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6869 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6870 /* FIXME: A possible overflow which I don't know how to deal
6872 offset_expr
.X_add_number
+= 4;
6873 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6874 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6879 * The MIPS assembler seems to check for X_add_number not
6880 * being double aligned and generating:
6883 * addiu at,at,%lo(foo+1)
6886 * But, the resulting address is the same after relocation so why
6887 * generate the extra instruction?
6889 /* Itbl support may require additional care here. */
6891 if (mips_opts
.isa
!= ISA_MIPS1
)
6902 if (mips_opts
.isa
!= ISA_MIPS1
)
6910 /* Itbl support may require additional care here. */
6915 if (HAVE_64BIT_GPRS
)
6926 if (HAVE_64BIT_GPRS
)
6936 if (offset_expr
.X_op
!= O_symbol
6937 && offset_expr
.X_op
!= O_constant
)
6939 as_bad (_("expression too complex"));
6940 offset_expr
.X_op
= O_constant
;
6943 if (HAVE_32BIT_ADDRESSES
6944 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6948 sprintf_vma (value
, offset_expr
.X_add_number
);
6949 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6952 /* Even on a big endian machine $fn comes before $fn+1. We have
6953 to adjust when loading from memory. We set coproc if we must
6954 load $fn+1 first. */
6955 /* Itbl support may require additional care here. */
6956 if (! target_big_endian
)
6959 if (mips_pic
== NO_PIC
6960 || offset_expr
.X_op
== O_constant
)
6962 /* If this is a reference to a GP relative symbol, we want
6963 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6964 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6965 If we have a base register, we use this
6967 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6968 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6969 If this is not a GP relative symbol, we want
6970 lui $at,<sym> (BFD_RELOC_HI16_S)
6971 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6972 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6973 If there is a base register, we add it to $at after the
6974 lui instruction. If there is a constant, we always use
6976 if (offset_expr
.X_op
== O_symbol
6977 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6978 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6980 relax_start (offset_expr
.X_add_symbol
);
6983 tempreg
= mips_gp_register
;
6987 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6988 AT
, breg
, mips_gp_register
);
6993 /* Itbl support may require additional care here. */
6994 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6995 BFD_RELOC_GPREL16
, tempreg
);
6996 offset_expr
.X_add_number
+= 4;
6998 /* Set mips_optimize to 2 to avoid inserting an
7000 hold_mips_optimize
= mips_optimize
;
7002 /* Itbl support may require additional care here. */
7003 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7004 BFD_RELOC_GPREL16
, tempreg
);
7005 mips_optimize
= hold_mips_optimize
;
7009 /* We just generated two relocs. When tc_gen_reloc
7010 handles this case, it will skip the first reloc and
7011 handle the second. The second reloc already has an
7012 extra addend of 4, which we added above. We must
7013 subtract it out, and then subtract another 4 to make
7014 the first reloc come out right. The second reloc
7015 will come out right because we are going to add 4 to
7016 offset_expr when we build its instruction below.
7018 If we have a symbol, then we don't want to include
7019 the offset, because it will wind up being included
7020 when we generate the reloc. */
7022 if (offset_expr
.X_op
== O_constant
)
7023 offset_expr
.X_add_number
-= 8;
7026 offset_expr
.X_add_number
= -4;
7027 offset_expr
.X_op
= O_constant
;
7031 macro_build_lui (&offset_expr
, AT
);
7033 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7034 /* Itbl support may require additional care here. */
7035 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7036 BFD_RELOC_LO16
, AT
);
7037 /* FIXME: How do we handle overflow here? */
7038 offset_expr
.X_add_number
+= 4;
7039 /* Itbl support may require additional care here. */
7040 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7041 BFD_RELOC_LO16
, AT
);
7042 if (mips_relax
.sequence
)
7045 else if (!mips_big_got
)
7047 /* If this is a reference to an external symbol, we want
7048 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7053 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7055 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7056 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7057 If there is a base register we add it to $at before the
7058 lwc1 instructions. If there is a constant we include it
7059 in the lwc1 instructions. */
7061 expr1
.X_add_number
= offset_expr
.X_add_number
;
7062 if (expr1
.X_add_number
< -0x8000
7063 || expr1
.X_add_number
>= 0x8000 - 4)
7064 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7065 load_got_offset (AT
, &offset_expr
);
7068 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7070 /* Set mips_optimize to 2 to avoid inserting an undesired
7072 hold_mips_optimize
= mips_optimize
;
7075 /* Itbl support may require additional care here. */
7076 relax_start (offset_expr
.X_add_symbol
);
7077 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7078 BFD_RELOC_LO16
, AT
);
7079 expr1
.X_add_number
+= 4;
7080 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7081 BFD_RELOC_LO16
, AT
);
7083 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7084 BFD_RELOC_LO16
, AT
);
7085 offset_expr
.X_add_number
+= 4;
7086 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7087 BFD_RELOC_LO16
, AT
);
7090 mips_optimize
= hold_mips_optimize
;
7092 else if (mips_big_got
)
7096 /* If this is a reference to an external symbol, we want
7097 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7099 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7104 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7106 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7107 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7108 If there is a base register we add it to $at before the
7109 lwc1 instructions. If there is a constant we include it
7110 in the lwc1 instructions. */
7112 expr1
.X_add_number
= offset_expr
.X_add_number
;
7113 offset_expr
.X_add_number
= 0;
7114 if (expr1
.X_add_number
< -0x8000
7115 || expr1
.X_add_number
>= 0x8000 - 4)
7116 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7117 gpdelay
= reg_needs_delay (mips_gp_register
);
7118 relax_start (offset_expr
.X_add_symbol
);
7119 macro_build (&offset_expr
, "lui", "t,u",
7120 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7121 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7122 AT
, AT
, mips_gp_register
);
7123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7124 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7127 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7128 /* Itbl support may require additional care here. */
7129 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7130 BFD_RELOC_LO16
, AT
);
7131 expr1
.X_add_number
+= 4;
7133 /* Set mips_optimize to 2 to avoid inserting an undesired
7135 hold_mips_optimize
= mips_optimize
;
7137 /* Itbl support may require additional care here. */
7138 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7139 BFD_RELOC_LO16
, AT
);
7140 mips_optimize
= hold_mips_optimize
;
7141 expr1
.X_add_number
-= 4;
7144 offset_expr
.X_add_number
= expr1
.X_add_number
;
7146 macro_build (NULL
, "nop", "");
7147 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7148 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7151 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7152 /* Itbl support may require additional care here. */
7153 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7154 BFD_RELOC_LO16
, AT
);
7155 offset_expr
.X_add_number
+= 4;
7157 /* Set mips_optimize to 2 to avoid inserting an undesired
7159 hold_mips_optimize
= mips_optimize
;
7161 /* Itbl support may require additional care here. */
7162 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7163 BFD_RELOC_LO16
, AT
);
7164 mips_optimize
= hold_mips_optimize
;
7178 assert (HAVE_32BIT_ADDRESSES
);
7179 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7180 offset_expr
.X_add_number
+= 4;
7181 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7184 /* New code added to support COPZ instructions.
7185 This code builds table entries out of the macros in mip_opcodes.
7186 R4000 uses interlocks to handle coproc delays.
7187 Other chips (like the R3000) require nops to be inserted for delays.
7189 FIXME: Currently, we require that the user handle delays.
7190 In order to fill delay slots for non-interlocked chips,
7191 we must have a way to specify delays based on the coprocessor.
7192 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7193 What are the side-effects of the cop instruction?
7194 What cache support might we have and what are its effects?
7195 Both coprocessor & memory require delays. how long???
7196 What registers are read/set/modified?
7198 If an itbl is provided to interpret cop instructions,
7199 this knowledge can be encoded in the itbl spec. */
7213 if (NO_ISA_COP (mips_opts
.arch
)
7214 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7216 as_bad (_("opcode not supported on this processor: %s"),
7217 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7221 /* For now we just do C (same as Cz). The parameter will be
7222 stored in insn_opcode by mips_ip. */
7223 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7227 move_register (dreg
, sreg
);
7230 #ifdef LOSING_COMPILER
7232 /* Try and see if this is a new itbl instruction.
7233 This code builds table entries out of the macros in mip_opcodes.
7234 FIXME: For now we just assemble the expression and pass it's
7235 value along as a 32-bit immediate.
7236 We may want to have the assembler assemble this value,
7237 so that we gain the assembler's knowledge of delay slots,
7239 Would it be more efficient to use mask (id) here? */
7240 if (itbl_have_entries
7241 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7243 s
= ip
->insn_mo
->name
;
7245 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7246 macro_build (&immed_expr
, s
, "C");
7252 if (!mips_opts
.at
&& used_at
)
7253 as_bad (_("Macro used $at after \".set noat\""));
7257 macro2 (struct mips_cl_insn
*ip
)
7259 unsigned int treg
, sreg
, dreg
, breg
;
7260 unsigned int tempreg
;
7274 bfd_reloc_code_real_type r
;
7276 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7277 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7278 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7279 mask
= ip
->insn_mo
->mask
;
7281 expr1
.X_op
= O_constant
;
7282 expr1
.X_op_symbol
= NULL
;
7283 expr1
.X_add_symbol
= NULL
;
7284 expr1
.X_add_number
= 1;
7288 #endif /* LOSING_COMPILER */
7293 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7294 macro_build (NULL
, "mflo", "d", dreg
);
7300 /* The MIPS assembler some times generates shifts and adds. I'm
7301 not trying to be that fancy. GCC should do this for us
7304 load_register (AT
, &imm_expr
, dbl
);
7305 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7306 macro_build (NULL
, "mflo", "d", dreg
);
7322 load_register (AT
, &imm_expr
, dbl
);
7323 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7324 macro_build (NULL
, "mflo", "d", dreg
);
7325 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7326 macro_build (NULL
, "mfhi", "d", AT
);
7328 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7331 expr1
.X_add_number
= 8;
7332 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7333 macro_build (NULL
, "nop", "", 0);
7334 macro_build (NULL
, "break", "c", 6);
7337 macro_build (NULL
, "mflo", "d", dreg
);
7353 load_register (AT
, &imm_expr
, dbl
);
7354 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7355 sreg
, imm
? AT
: treg
);
7356 macro_build (NULL
, "mfhi", "d", AT
);
7357 macro_build (NULL
, "mflo", "d", dreg
);
7359 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7362 expr1
.X_add_number
= 8;
7363 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7364 macro_build (NULL
, "nop", "", 0);
7365 macro_build (NULL
, "break", "c", 6);
7371 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7382 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7383 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7387 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7388 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7389 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7390 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7394 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7405 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7406 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7410 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7411 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7412 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7413 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7421 if (imm_expr
.X_op
!= O_constant
)
7422 as_bad (_("Improper rotate count"));
7423 rot
= imm_expr
.X_add_number
& 0x3f;
7424 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7426 rot
= (64 - rot
) & 0x3f;
7428 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7430 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7435 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7438 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7439 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7442 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7443 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7444 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7452 if (imm_expr
.X_op
!= O_constant
)
7453 as_bad (_("Improper rotate count"));
7454 rot
= imm_expr
.X_add_number
& 0x1f;
7455 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7457 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7462 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7466 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7467 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7468 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7473 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7475 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7479 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7480 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7481 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7482 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7486 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7488 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7492 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7493 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7494 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7495 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7503 if (imm_expr
.X_op
!= O_constant
)
7504 as_bad (_("Improper rotate count"));
7505 rot
= imm_expr
.X_add_number
& 0x3f;
7506 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7509 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7511 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7516 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7519 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7520 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7523 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7524 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7525 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7533 if (imm_expr
.X_op
!= O_constant
)
7534 as_bad (_("Improper rotate count"));
7535 rot
= imm_expr
.X_add_number
& 0x1f;
7536 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7538 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7543 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7547 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7548 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7549 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7554 assert (mips_opts
.isa
== ISA_MIPS1
);
7555 /* Even on a big endian machine $fn comes before $fn+1. We have
7556 to adjust when storing to memory. */
7557 macro_build (&offset_expr
, "swc1", "T,o(b)",
7558 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7559 offset_expr
.X_add_number
+= 4;
7560 macro_build (&offset_expr
, "swc1", "T,o(b)",
7561 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7566 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7568 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7571 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7572 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7577 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7579 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7584 as_warn (_("Instruction %s: result is always false"),
7586 move_register (dreg
, 0);
7589 if (CPU_HAS_SEQ (mips_opts
.arch
)
7590 && -512 <= imm_expr
.X_add_number
7591 && imm_expr
.X_add_number
< 512)
7593 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7594 imm_expr
.X_add_number
);
7597 if (imm_expr
.X_op
== O_constant
7598 && imm_expr
.X_add_number
>= 0
7599 && imm_expr
.X_add_number
< 0x10000)
7601 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7603 else if (imm_expr
.X_op
== O_constant
7604 && imm_expr
.X_add_number
> -0x8000
7605 && imm_expr
.X_add_number
< 0)
7607 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7608 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7609 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7611 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7614 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7615 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7620 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7621 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7624 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7627 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7633 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7634 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7637 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7639 if (imm_expr
.X_op
== O_constant
7640 && imm_expr
.X_add_number
>= -0x8000
7641 && imm_expr
.X_add_number
< 0x8000)
7643 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7644 dreg
, sreg
, BFD_RELOC_LO16
);
7648 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7649 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7653 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7656 case M_SGT
: /* sreg > treg <==> treg < sreg */
7662 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7665 case M_SGT_I
: /* sreg > I <==> I < sreg */
7672 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7673 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7676 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7682 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7683 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7686 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7693 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7694 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7695 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7699 if (imm_expr
.X_op
== O_constant
7700 && imm_expr
.X_add_number
>= -0x8000
7701 && imm_expr
.X_add_number
< 0x8000)
7703 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7707 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7708 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7712 if (imm_expr
.X_op
== O_constant
7713 && imm_expr
.X_add_number
>= -0x8000
7714 && imm_expr
.X_add_number
< 0x8000)
7716 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7721 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7722 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7727 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7729 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7732 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7733 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7738 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7740 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7745 as_warn (_("Instruction %s: result is always true"),
7747 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7748 dreg
, 0, BFD_RELOC_LO16
);
7751 if (CPU_HAS_SEQ (mips_opts
.arch
)
7752 && -512 <= imm_expr
.X_add_number
7753 && imm_expr
.X_add_number
< 512)
7755 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7756 imm_expr
.X_add_number
);
7759 if (imm_expr
.X_op
== O_constant
7760 && imm_expr
.X_add_number
>= 0
7761 && imm_expr
.X_add_number
< 0x10000)
7763 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7765 else if (imm_expr
.X_op
== O_constant
7766 && imm_expr
.X_add_number
> -0x8000
7767 && imm_expr
.X_add_number
< 0)
7769 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7770 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7771 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7773 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7776 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7777 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7782 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7783 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7786 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7792 if (imm_expr
.X_op
== O_constant
7793 && imm_expr
.X_add_number
> -0x8000
7794 && imm_expr
.X_add_number
<= 0x8000)
7796 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7797 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7798 dreg
, sreg
, BFD_RELOC_LO16
);
7802 load_register (AT
, &imm_expr
, dbl
);
7803 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7809 if (imm_expr
.X_op
== O_constant
7810 && imm_expr
.X_add_number
> -0x8000
7811 && imm_expr
.X_add_number
<= 0x8000)
7813 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7814 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7815 dreg
, sreg
, BFD_RELOC_LO16
);
7819 load_register (AT
, &imm_expr
, dbl
);
7820 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7842 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7843 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7848 assert (mips_opts
.isa
== ISA_MIPS1
);
7850 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7851 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7854 * Is the double cfc1 instruction a bug in the mips assembler;
7855 * or is there a reason for it?
7858 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7859 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7860 macro_build (NULL
, "nop", "");
7861 expr1
.X_add_number
= 3;
7862 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7863 expr1
.X_add_number
= 2;
7864 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7865 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7866 macro_build (NULL
, "nop", "");
7867 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7869 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7870 macro_build (NULL
, "nop", "");
7881 if (offset_expr
.X_add_number
>= 0x7fff)
7882 as_bad (_("operand overflow"));
7883 if (! target_big_endian
)
7884 ++offset_expr
.X_add_number
;
7885 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7886 if (! target_big_endian
)
7887 --offset_expr
.X_add_number
;
7889 ++offset_expr
.X_add_number
;
7890 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7891 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7892 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7905 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7906 as_bad (_("operand overflow"));
7914 if (! target_big_endian
)
7915 offset_expr
.X_add_number
+= off
;
7916 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7917 if (! target_big_endian
)
7918 offset_expr
.X_add_number
-= off
;
7920 offset_expr
.X_add_number
+= off
;
7921 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7923 /* If necessary, move the result in tempreg the final destination. */
7924 if (treg
== tempreg
)
7926 /* Protect second load's delay slot. */
7928 move_register (treg
, tempreg
);
7942 load_address (AT
, &offset_expr
, &used_at
);
7944 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7945 if (! target_big_endian
)
7946 expr1
.X_add_number
= off
;
7948 expr1
.X_add_number
= 0;
7949 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7950 if (! target_big_endian
)
7951 expr1
.X_add_number
= 0;
7953 expr1
.X_add_number
= off
;
7954 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7960 load_address (AT
, &offset_expr
, &used_at
);
7962 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7963 if (target_big_endian
)
7964 expr1
.X_add_number
= 0;
7965 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7966 treg
, BFD_RELOC_LO16
, AT
);
7967 if (target_big_endian
)
7968 expr1
.X_add_number
= 1;
7970 expr1
.X_add_number
= 0;
7971 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7972 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7973 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7978 if (offset_expr
.X_add_number
>= 0x7fff)
7979 as_bad (_("operand overflow"));
7980 if (target_big_endian
)
7981 ++offset_expr
.X_add_number
;
7982 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7983 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7984 if (target_big_endian
)
7985 --offset_expr
.X_add_number
;
7987 ++offset_expr
.X_add_number
;
7988 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8001 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8002 as_bad (_("operand overflow"));
8003 if (! target_big_endian
)
8004 offset_expr
.X_add_number
+= off
;
8005 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8006 if (! target_big_endian
)
8007 offset_expr
.X_add_number
-= off
;
8009 offset_expr
.X_add_number
+= off
;
8010 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8024 load_address (AT
, &offset_expr
, &used_at
);
8026 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8027 if (! target_big_endian
)
8028 expr1
.X_add_number
= off
;
8030 expr1
.X_add_number
= 0;
8031 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8032 if (! target_big_endian
)
8033 expr1
.X_add_number
= 0;
8035 expr1
.X_add_number
= off
;
8036 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8041 load_address (AT
, &offset_expr
, &used_at
);
8043 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8044 if (! target_big_endian
)
8045 expr1
.X_add_number
= 0;
8046 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8047 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8048 if (! target_big_endian
)
8049 expr1
.X_add_number
= 1;
8051 expr1
.X_add_number
= 0;
8052 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8053 if (! target_big_endian
)
8054 expr1
.X_add_number
= 0;
8056 expr1
.X_add_number
= 1;
8057 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8058 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8059 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8063 /* FIXME: Check if this is one of the itbl macros, since they
8064 are added dynamically. */
8065 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8068 if (!mips_opts
.at
&& used_at
)
8069 as_bad (_("Macro used $at after \".set noat\""));
8072 /* Implement macros in mips16 mode. */
8075 mips16_macro (struct mips_cl_insn
*ip
)
8078 int xreg
, yreg
, zreg
, tmp
;
8081 const char *s
, *s2
, *s3
;
8083 mask
= ip
->insn_mo
->mask
;
8085 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8086 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8087 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8089 expr1
.X_op
= O_constant
;
8090 expr1
.X_op_symbol
= NULL
;
8091 expr1
.X_add_symbol
= NULL
;
8092 expr1
.X_add_number
= 1;
8112 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8113 expr1
.X_add_number
= 2;
8114 macro_build (&expr1
, "bnez", "x,p", yreg
);
8115 macro_build (NULL
, "break", "6", 7);
8117 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8118 since that causes an overflow. We should do that as well,
8119 but I don't see how to do the comparisons without a temporary
8122 macro_build (NULL
, s
, "x", zreg
);
8142 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8143 expr1
.X_add_number
= 2;
8144 macro_build (&expr1
, "bnez", "x,p", yreg
);
8145 macro_build (NULL
, "break", "6", 7);
8147 macro_build (NULL
, s2
, "x", zreg
);
8153 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8154 macro_build (NULL
, "mflo", "x", zreg
);
8162 if (imm_expr
.X_op
!= O_constant
)
8163 as_bad (_("Unsupported large constant"));
8164 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8165 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8169 if (imm_expr
.X_op
!= O_constant
)
8170 as_bad (_("Unsupported large constant"));
8171 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8172 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8176 if (imm_expr
.X_op
!= O_constant
)
8177 as_bad (_("Unsupported large constant"));
8178 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8179 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8201 goto do_reverse_branch
;
8205 goto do_reverse_branch
;
8217 goto do_reverse_branch
;
8228 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8229 macro_build (&offset_expr
, s2
, "p");
8256 goto do_addone_branch_i
;
8261 goto do_addone_branch_i
;
8276 goto do_addone_branch_i
;
8283 if (imm_expr
.X_op
!= O_constant
)
8284 as_bad (_("Unsupported large constant"));
8285 ++imm_expr
.X_add_number
;
8288 macro_build (&imm_expr
, s
, s3
, xreg
);
8289 macro_build (&offset_expr
, s2
, "p");
8293 expr1
.X_add_number
= 0;
8294 macro_build (&expr1
, "slti", "x,8", yreg
);
8296 move_register (xreg
, yreg
);
8297 expr1
.X_add_number
= 2;
8298 macro_build (&expr1
, "bteqz", "p");
8299 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8303 /* For consistency checking, verify that all bits are specified either
8304 by the match/mask part of the instruction definition, or by the
8307 validate_mips_insn (const struct mips_opcode
*opc
)
8309 const char *p
= opc
->args
;
8311 unsigned long used_bits
= opc
->mask
;
8313 if ((used_bits
& opc
->match
) != opc
->match
)
8315 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8316 opc
->name
, opc
->args
);
8319 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8329 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8330 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8331 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8332 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8333 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8334 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8335 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8336 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8337 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8338 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8339 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8340 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8341 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8343 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8344 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8345 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8346 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8347 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8348 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8349 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8350 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8351 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8352 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8355 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8356 c
, opc
->name
, opc
->args
);
8360 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8361 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8363 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8364 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8365 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8366 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8368 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8369 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8371 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8372 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8374 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8375 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8376 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8377 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8378 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8379 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8380 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8381 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8382 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8383 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8384 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8385 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8386 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8387 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8388 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8389 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8390 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8392 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8393 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8394 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8395 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8397 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8398 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8399 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8400 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8401 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8402 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8403 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8404 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8405 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8408 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8409 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8410 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8411 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8412 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8415 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8416 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8417 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8418 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8419 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8420 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8421 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8422 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8423 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8424 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8425 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8426 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8427 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8428 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8429 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8430 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8431 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8433 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8434 c
, opc
->name
, opc
->args
);
8438 if (used_bits
!= 0xffffffff)
8440 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8441 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8447 /* UDI immediates. */
8455 static const struct mips_immed mips_immed
[] = {
8456 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8457 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8458 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8459 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8463 /* Check whether an odd floating-point register is allowed. */
8465 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8467 const char *s
= insn
->name
;
8469 if (insn
->pinfo
== INSN_MACRO
)
8470 /* Let a macro pass, we'll catch it later when it is expanded. */
8473 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8475 /* Allow odd registers for single-precision ops. */
8476 switch (insn
->pinfo
& (FP_S
| FP_D
))
8480 return 1; /* both single precision - ok */
8482 return 0; /* both double precision - fail */
8487 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8488 s
= strchr (insn
->name
, '.');
8490 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8491 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8494 /* Single-precision coprocessor loads and moves are OK too. */
8495 if ((insn
->pinfo
& FP_S
)
8496 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8497 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8503 /* This routine assembles an instruction into its binary format. As a
8504 side effect, it sets one of the global variables imm_reloc or
8505 offset_reloc to the type of relocation to do if one of the operands
8506 is an address expression. */
8509 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8514 struct mips_opcode
*insn
;
8517 unsigned int lastregno
= 0;
8518 unsigned int lastpos
= 0;
8519 unsigned int limlo
, limhi
;
8522 offsetT min_range
, max_range
;
8528 /* If the instruction contains a '.', we first try to match an instruction
8529 including the '.'. Then we try again without the '.'. */
8531 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8534 /* If we stopped on whitespace, then replace the whitespace with null for
8535 the call to hash_find. Save the character we replaced just in case we
8536 have to re-parse the instruction. */
8543 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8545 /* If we didn't find the instruction in the opcode table, try again, but
8546 this time with just the instruction up to, but not including the
8550 /* Restore the character we overwrite above (if any). */
8554 /* Scan up to the first '.' or whitespace. */
8556 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8560 /* If we did not find a '.', then we can quit now. */
8563 insn_error
= "unrecognized opcode";
8567 /* Lookup the instruction in the hash table. */
8569 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8571 insn_error
= "unrecognized opcode";
8581 assert (strcmp (insn
->name
, str
) == 0);
8583 ok
= is_opcode_valid (insn
, FALSE
);
8586 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8587 && strcmp (insn
->name
, insn
[1].name
) == 0)
8596 static char buf
[100];
8598 _("opcode not supported on this processor: %s (%s)"),
8599 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8600 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8609 create_insn (ip
, insn
);
8612 for (args
= insn
->args
;; ++args
)
8616 s
+= strspn (s
, " \t");
8620 case '\0': /* end of args */
8625 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8626 my_getExpression (&imm_expr
, s
);
8627 check_absolute_expr (ip
, &imm_expr
);
8628 if ((unsigned long) imm_expr
.X_add_number
!= 1
8629 && (unsigned long) imm_expr
.X_add_number
!= 3)
8631 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8632 (unsigned long) imm_expr
.X_add_number
);
8634 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8635 imm_expr
.X_op
= O_absent
;
8639 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8640 my_getExpression (&imm_expr
, s
);
8641 check_absolute_expr (ip
, &imm_expr
);
8642 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8644 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8645 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8647 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8648 imm_expr
.X_op
= O_absent
;
8652 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8653 my_getExpression (&imm_expr
, s
);
8654 check_absolute_expr (ip
, &imm_expr
);
8655 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8657 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8658 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8660 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8661 imm_expr
.X_op
= O_absent
;
8665 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8666 my_getExpression (&imm_expr
, s
);
8667 check_absolute_expr (ip
, &imm_expr
);
8668 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8670 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8671 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8673 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8674 imm_expr
.X_op
= O_absent
;
8678 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8679 my_getExpression (&imm_expr
, s
);
8680 check_absolute_expr (ip
, &imm_expr
);
8681 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8683 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8684 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8686 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8687 imm_expr
.X_op
= O_absent
;
8691 case '7': /* four dsp accumulators in bits 11,12 */
8692 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8693 s
[3] >= '0' && s
[3] <= '3')
8697 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8701 as_bad (_("Invalid dsp acc register"));
8704 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8705 my_getExpression (&imm_expr
, s
);
8706 check_absolute_expr (ip
, &imm_expr
);
8707 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8709 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8711 (unsigned long) imm_expr
.X_add_number
);
8713 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8714 imm_expr
.X_op
= O_absent
;
8718 case '9': /* four dsp accumulators in bits 21,22 */
8719 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8720 s
[3] >= '0' && s
[3] <= '3')
8724 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8728 as_bad (_("Invalid dsp acc register"));
8731 case '0': /* dsp 6-bit signed immediate in bit 20 */
8732 my_getExpression (&imm_expr
, s
);
8733 check_absolute_expr (ip
, &imm_expr
);
8734 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8735 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8736 if (imm_expr
.X_add_number
< min_range
||
8737 imm_expr
.X_add_number
> max_range
)
8739 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8740 (long) min_range
, (long) max_range
,
8741 (long) imm_expr
.X_add_number
);
8743 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8744 imm_expr
.X_op
= O_absent
;
8748 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8749 my_getExpression (&imm_expr
, s
);
8750 check_absolute_expr (ip
, &imm_expr
);
8751 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8753 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8755 (unsigned long) imm_expr
.X_add_number
);
8757 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8758 imm_expr
.X_op
= O_absent
;
8762 case ':': /* dsp 7-bit signed immediate in bit 19 */
8763 my_getExpression (&imm_expr
, s
);
8764 check_absolute_expr (ip
, &imm_expr
);
8765 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8766 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8767 if (imm_expr
.X_add_number
< min_range
||
8768 imm_expr
.X_add_number
> max_range
)
8770 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8771 (long) min_range
, (long) max_range
,
8772 (long) imm_expr
.X_add_number
);
8774 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8775 imm_expr
.X_op
= O_absent
;
8779 case '@': /* dsp 10-bit signed immediate in bit 16 */
8780 my_getExpression (&imm_expr
, s
);
8781 check_absolute_expr (ip
, &imm_expr
);
8782 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8783 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8784 if (imm_expr
.X_add_number
< min_range
||
8785 imm_expr
.X_add_number
> max_range
)
8787 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8788 (long) min_range
, (long) max_range
,
8789 (long) imm_expr
.X_add_number
);
8791 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8792 imm_expr
.X_op
= O_absent
;
8796 case '!': /* MT usermode flag bit. */
8797 my_getExpression (&imm_expr
, s
);
8798 check_absolute_expr (ip
, &imm_expr
);
8799 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8800 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8801 (unsigned long) imm_expr
.X_add_number
);
8802 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8803 imm_expr
.X_op
= O_absent
;
8807 case '$': /* MT load high flag bit. */
8808 my_getExpression (&imm_expr
, s
);
8809 check_absolute_expr (ip
, &imm_expr
);
8810 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8811 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8812 (unsigned long) imm_expr
.X_add_number
);
8813 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8814 imm_expr
.X_op
= O_absent
;
8818 case '*': /* four dsp accumulators in bits 18,19 */
8819 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8820 s
[3] >= '0' && s
[3] <= '3')
8824 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8828 as_bad (_("Invalid dsp/smartmips acc register"));
8831 case '&': /* four dsp accumulators in bits 13,14 */
8832 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8833 s
[3] >= '0' && s
[3] <= '3')
8837 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8841 as_bad (_("Invalid dsp/smartmips acc register"));
8853 INSERT_OPERAND (RS
, *ip
, lastregno
);
8857 INSERT_OPERAND (RT
, *ip
, lastregno
);
8861 INSERT_OPERAND (FT
, *ip
, lastregno
);
8865 INSERT_OPERAND (FS
, *ip
, lastregno
);
8871 /* Handle optional base register.
8872 Either the base register is omitted or
8873 we must have a left paren. */
8874 /* This is dependent on the next operand specifier
8875 is a base register specification. */
8876 assert (args
[1] == 'b' || args
[1] == '5'
8877 || args
[1] == '-' || args
[1] == '4');
8881 case ')': /* these must match exactly */
8888 case '+': /* Opcode extension character. */
8891 case '1': /* UDI immediates. */
8896 const struct mips_immed
*imm
= mips_immed
;
8898 while (imm
->type
&& imm
->type
!= *args
)
8902 my_getExpression (&imm_expr
, s
);
8903 check_absolute_expr (ip
, &imm_expr
);
8904 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8906 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8907 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8908 (unsigned long) imm_expr
.X_add_number
,
8909 (unsigned long) imm_expr
.X_add_number
);
8910 imm_expr
.X_add_number
&= imm
->mask
;
8912 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8914 imm_expr
.X_op
= O_absent
;
8919 case 'A': /* ins/ext position, becomes LSB. */
8928 my_getExpression (&imm_expr
, s
);
8929 check_absolute_expr (ip
, &imm_expr
);
8930 if ((unsigned long) imm_expr
.X_add_number
< limlo
8931 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8933 as_bad (_("Improper position (%lu)"),
8934 (unsigned long) imm_expr
.X_add_number
);
8935 imm_expr
.X_add_number
= limlo
;
8937 lastpos
= imm_expr
.X_add_number
;
8938 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8939 imm_expr
.X_op
= O_absent
;
8943 case 'B': /* ins size, becomes MSB. */
8952 my_getExpression (&imm_expr
, s
);
8953 check_absolute_expr (ip
, &imm_expr
);
8954 /* Check for negative input so that small negative numbers
8955 will not succeed incorrectly. The checks against
8956 (pos+size) transitively check "size" itself,
8957 assuming that "pos" is reasonable. */
8958 if ((long) imm_expr
.X_add_number
< 0
8959 || ((unsigned long) imm_expr
.X_add_number
8961 || ((unsigned long) imm_expr
.X_add_number
8964 as_bad (_("Improper insert size (%lu, position %lu)"),
8965 (unsigned long) imm_expr
.X_add_number
,
8966 (unsigned long) lastpos
);
8967 imm_expr
.X_add_number
= limlo
- lastpos
;
8969 INSERT_OPERAND (INSMSB
, *ip
,
8970 lastpos
+ imm_expr
.X_add_number
- 1);
8971 imm_expr
.X_op
= O_absent
;
8975 case 'C': /* ext size, becomes MSBD. */
8988 my_getExpression (&imm_expr
, s
);
8989 check_absolute_expr (ip
, &imm_expr
);
8990 /* Check for negative input so that small negative numbers
8991 will not succeed incorrectly. The checks against
8992 (pos+size) transitively check "size" itself,
8993 assuming that "pos" is reasonable. */
8994 if ((long) imm_expr
.X_add_number
< 0
8995 || ((unsigned long) imm_expr
.X_add_number
8997 || ((unsigned long) imm_expr
.X_add_number
9000 as_bad (_("Improper extract size (%lu, position %lu)"),
9001 (unsigned long) imm_expr
.X_add_number
,
9002 (unsigned long) lastpos
);
9003 imm_expr
.X_add_number
= limlo
- lastpos
;
9005 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9006 imm_expr
.X_op
= O_absent
;
9011 /* +D is for disassembly only; never match. */
9015 /* "+I" is like "I", except that imm2_expr is used. */
9016 my_getExpression (&imm2_expr
, s
);
9017 if (imm2_expr
.X_op
!= O_big
9018 && imm2_expr
.X_op
!= O_constant
)
9019 insn_error
= _("absolute expression required");
9020 if (HAVE_32BIT_GPRS
)
9021 normalize_constant_expr (&imm2_expr
);
9025 case 'T': /* Coprocessor register. */
9026 /* +T is for disassembly only; never match. */
9029 case 't': /* Coprocessor register number. */
9030 if (s
[0] == '$' && ISDIGIT (s
[1]))
9040 while (ISDIGIT (*s
));
9042 as_bad (_("Invalid register number (%d)"), regno
);
9045 INSERT_OPERAND (RT
, *ip
, regno
);
9050 as_bad (_("Invalid coprocessor 0 register number"));
9054 /* bbit[01] and bbit[01]32 bit index. Give error if index
9055 is not in the valid range. */
9056 my_getExpression (&imm_expr
, s
);
9057 check_absolute_expr (ip
, &imm_expr
);
9058 if ((unsigned) imm_expr
.X_add_number
> 31)
9060 as_bad (_("Improper bit index (%lu)"),
9061 (unsigned long) imm_expr
.X_add_number
);
9062 imm_expr
.X_add_number
= 0;
9064 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9065 imm_expr
.X_op
= O_absent
;
9070 /* bbit[01] bit index when bbit is used but we generate
9071 bbit[01]32 because the index is over 32. Move to the
9072 next candidate if index is not in the valid range. */
9073 my_getExpression (&imm_expr
, s
);
9074 check_absolute_expr (ip
, &imm_expr
);
9075 if ((unsigned) imm_expr
.X_add_number
< 32
9076 || (unsigned) imm_expr
.X_add_number
> 63)
9078 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9079 imm_expr
.X_op
= O_absent
;
9084 /* cins, cins32, exts and exts32 position field. Give error
9085 if it's not in the valid range. */
9086 my_getExpression (&imm_expr
, s
);
9087 check_absolute_expr (ip
, &imm_expr
);
9088 if ((unsigned) imm_expr
.X_add_number
> 31)
9090 as_bad (_("Improper position (%lu)"),
9091 (unsigned long) imm_expr
.X_add_number
);
9092 imm_expr
.X_add_number
= 0;
9094 /* Make the pos explicit to simplify +S. */
9095 lastpos
= imm_expr
.X_add_number
+ 32;
9096 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9097 imm_expr
.X_op
= O_absent
;
9102 /* cins, cins32, exts and exts32 position field. Move to
9103 the next candidate if it's not in the valid range. */
9104 my_getExpression (&imm_expr
, s
);
9105 check_absolute_expr (ip
, &imm_expr
);
9106 if ((unsigned) imm_expr
.X_add_number
< 32
9107 || (unsigned) imm_expr
.X_add_number
> 63)
9109 lastpos
= imm_expr
.X_add_number
;
9110 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9111 imm_expr
.X_op
= O_absent
;
9116 /* cins and exts length-minus-one field. */
9117 my_getExpression (&imm_expr
, s
);
9118 check_absolute_expr (ip
, &imm_expr
);
9119 if ((unsigned long) imm_expr
.X_add_number
> 31)
9121 as_bad (_("Improper size (%lu)"),
9122 (unsigned long) imm_expr
.X_add_number
);
9123 imm_expr
.X_add_number
= 0;
9125 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9126 imm_expr
.X_op
= O_absent
;
9131 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9132 length-minus-one field. */
9133 my_getExpression (&imm_expr
, s
);
9134 check_absolute_expr (ip
, &imm_expr
);
9135 if ((long) imm_expr
.X_add_number
< 0
9136 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9138 as_bad (_("Improper size (%lu)"),
9139 (unsigned long) imm_expr
.X_add_number
);
9140 imm_expr
.X_add_number
= 0;
9142 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9143 imm_expr
.X_op
= O_absent
;
9148 /* seqi/snei immediate field. */
9149 my_getExpression (&imm_expr
, s
);
9150 check_absolute_expr (ip
, &imm_expr
);
9151 if ((long) imm_expr
.X_add_number
< -512
9152 || (long) imm_expr
.X_add_number
>= 512)
9154 as_bad (_("Improper immediate (%ld)"),
9155 (long) imm_expr
.X_add_number
);
9156 imm_expr
.X_add_number
= 0;
9158 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9159 imm_expr
.X_op
= O_absent
;
9164 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9165 *args
, insn
->name
, insn
->args
);
9166 /* Further processing is fruitless. */
9171 case '<': /* must be at least one digit */
9173 * According to the manual, if the shift amount is greater
9174 * than 31 or less than 0, then the shift amount should be
9175 * mod 32. In reality the mips assembler issues an error.
9176 * We issue a warning and mask out all but the low 5 bits.
9178 my_getExpression (&imm_expr
, s
);
9179 check_absolute_expr (ip
, &imm_expr
);
9180 if ((unsigned long) imm_expr
.X_add_number
> 31)
9181 as_warn (_("Improper shift amount (%lu)"),
9182 (unsigned long) imm_expr
.X_add_number
);
9183 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9184 imm_expr
.X_op
= O_absent
;
9188 case '>': /* shift amount minus 32 */
9189 my_getExpression (&imm_expr
, s
);
9190 check_absolute_expr (ip
, &imm_expr
);
9191 if ((unsigned long) imm_expr
.X_add_number
< 32
9192 || (unsigned long) imm_expr
.X_add_number
> 63)
9194 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9195 imm_expr
.X_op
= O_absent
;
9199 case 'k': /* cache code */
9200 case 'h': /* prefx code */
9201 my_getExpression (&imm_expr
, s
);
9202 check_absolute_expr (ip
, &imm_expr
);
9203 if ((unsigned long) imm_expr
.X_add_number
> 31)
9204 as_warn (_("Invalid value for `%s' (%lu)"),
9206 (unsigned long) imm_expr
.X_add_number
);
9208 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9210 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9211 imm_expr
.X_op
= O_absent
;
9215 case 'c': /* break code */
9216 my_getExpression (&imm_expr
, s
);
9217 check_absolute_expr (ip
, &imm_expr
);
9218 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9219 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9221 (unsigned long) imm_expr
.X_add_number
);
9222 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9223 imm_expr
.X_op
= O_absent
;
9227 case 'q': /* lower break code */
9228 my_getExpression (&imm_expr
, s
);
9229 check_absolute_expr (ip
, &imm_expr
);
9230 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9231 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9233 (unsigned long) imm_expr
.X_add_number
);
9234 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9235 imm_expr
.X_op
= O_absent
;
9239 case 'B': /* 20-bit syscall/break code. */
9240 my_getExpression (&imm_expr
, s
);
9241 check_absolute_expr (ip
, &imm_expr
);
9242 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9243 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9245 (unsigned long) imm_expr
.X_add_number
);
9246 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9247 imm_expr
.X_op
= O_absent
;
9251 case 'C': /* Coprocessor code */
9252 my_getExpression (&imm_expr
, s
);
9253 check_absolute_expr (ip
, &imm_expr
);
9254 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9256 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9257 (unsigned long) imm_expr
.X_add_number
);
9258 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9260 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9261 imm_expr
.X_op
= O_absent
;
9265 case 'J': /* 19-bit wait code. */
9266 my_getExpression (&imm_expr
, s
);
9267 check_absolute_expr (ip
, &imm_expr
);
9268 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9270 as_warn (_("Illegal 19-bit code (%lu)"),
9271 (unsigned long) imm_expr
.X_add_number
);
9272 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9274 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9275 imm_expr
.X_op
= O_absent
;
9279 case 'P': /* Performance register. */
9280 my_getExpression (&imm_expr
, s
);
9281 check_absolute_expr (ip
, &imm_expr
);
9282 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9283 as_warn (_("Invalid performance register (%lu)"),
9284 (unsigned long) imm_expr
.X_add_number
);
9285 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9286 imm_expr
.X_op
= O_absent
;
9290 case 'G': /* Coprocessor destination register. */
9291 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9292 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9294 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9295 INSERT_OPERAND (RD
, *ip
, regno
);
9304 case 'b': /* base register */
9305 case 'd': /* destination register */
9306 case 's': /* source register */
9307 case 't': /* target register */
9308 case 'r': /* both target and source */
9309 case 'v': /* both dest and source */
9310 case 'w': /* both dest and target */
9311 case 'E': /* coprocessor target register */
9312 case 'K': /* 'rdhwr' destination register */
9313 case 'x': /* ignore register name */
9314 case 'z': /* must be zero register */
9315 case 'U': /* destination register (clo/clz). */
9316 case 'g': /* coprocessor destination register */
9318 if (*args
== 'E' || *args
== 'K')
9319 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9322 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9323 if (regno
== AT
&& mips_opts
.at
)
9325 if (mips_opts
.at
== ATREG
)
9326 as_warn (_("used $at without \".set noat\""));
9328 as_warn (_("used $%u with \".set at=$%u\""),
9329 regno
, mips_opts
.at
);
9339 if (c
== 'r' || c
== 'v' || c
== 'w')
9346 /* 'z' only matches $0. */
9347 if (c
== 'z' && regno
!= 0)
9350 if (c
== 's' && !strcmp (ip
->insn_mo
->name
, "jalr"))
9352 if (regno
== lastregno
)
9354 insn_error
= _("source and destinationations must be different");
9357 if (regno
== 31 && lastregno
== 0)
9359 insn_error
= _("a destination register must be supplied");
9363 /* Now that we have assembled one operand, we use the args string
9364 * to figure out where it goes in the instruction. */
9371 INSERT_OPERAND (RS
, *ip
, regno
);
9377 INSERT_OPERAND (RD
, *ip
, regno
);
9380 INSERT_OPERAND (RD
, *ip
, regno
);
9381 INSERT_OPERAND (RT
, *ip
, regno
);
9386 INSERT_OPERAND (RT
, *ip
, regno
);
9389 /* This case exists because on the r3000 trunc
9390 expands into a macro which requires a gp
9391 register. On the r6000 or r4000 it is
9392 assembled into a single instruction which
9393 ignores the register. Thus the insn version
9394 is MIPS_ISA2 and uses 'x', and the macro
9395 version is MIPS_ISA1 and uses 't'. */
9398 /* This case is for the div instruction, which
9399 acts differently if the destination argument
9400 is $0. This only matches $0, and is checked
9401 outside the switch. */
9404 /* Itbl operand; not yet implemented. FIXME ?? */
9406 /* What about all other operands like 'i', which
9407 can be specified in the opcode table? */
9416 INSERT_OPERAND (RS
, *ip
, lastregno
);
9419 INSERT_OPERAND (RT
, *ip
, lastregno
);
9424 case 'O': /* MDMX alignment immediate constant. */
9425 my_getExpression (&imm_expr
, s
);
9426 check_absolute_expr (ip
, &imm_expr
);
9427 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9428 as_warn ("Improper align amount (%ld), using low bits",
9429 (long) imm_expr
.X_add_number
);
9430 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9431 imm_expr
.X_op
= O_absent
;
9435 case 'Q': /* MDMX vector, element sel, or const. */
9438 /* MDMX Immediate. */
9439 my_getExpression (&imm_expr
, s
);
9440 check_absolute_expr (ip
, &imm_expr
);
9441 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9442 as_warn (_("Invalid MDMX Immediate (%ld)"),
9443 (long) imm_expr
.X_add_number
);
9444 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9445 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9446 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9448 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9449 imm_expr
.X_op
= O_absent
;
9453 /* Not MDMX Immediate. Fall through. */
9454 case 'X': /* MDMX destination register. */
9455 case 'Y': /* MDMX source register. */
9456 case 'Z': /* MDMX target register. */
9458 case 'D': /* floating point destination register */
9459 case 'S': /* floating point source register */
9460 case 'T': /* floating point target register */
9461 case 'R': /* floating point source register */
9466 || (mips_opts
.ase_mdmx
9467 && (ip
->insn_mo
->pinfo
& FP_D
)
9468 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9469 | INSN_COPROC_MEMORY_DELAY
9470 | INSN_LOAD_COPROC_DELAY
9471 | INSN_LOAD_MEMORY_DELAY
9472 | INSN_STORE_MEMORY
))))
9475 if (reg_lookup (&s
, rtype
, ®no
))
9477 if ((regno
& 1) != 0
9479 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9480 as_warn (_("Float register should be even, was %d"),
9488 if (c
== 'V' || c
== 'W')
9499 INSERT_OPERAND (FD
, *ip
, regno
);
9504 INSERT_OPERAND (FS
, *ip
, regno
);
9507 /* This is like 'Z', but also needs to fix the MDMX
9508 vector/scalar select bits. Note that the
9509 scalar immediate case is handled above. */
9512 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9513 int max_el
= (is_qh
? 3 : 7);
9515 my_getExpression(&imm_expr
, s
);
9516 check_absolute_expr (ip
, &imm_expr
);
9518 if (imm_expr
.X_add_number
> max_el
)
9519 as_bad(_("Bad element selector %ld"),
9520 (long) imm_expr
.X_add_number
);
9521 imm_expr
.X_add_number
&= max_el
;
9522 ip
->insn_opcode
|= (imm_expr
.X_add_number
9525 imm_expr
.X_op
= O_absent
;
9527 as_warn(_("Expecting ']' found '%s'"), s
);
9533 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9534 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9537 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9544 INSERT_OPERAND (FT
, *ip
, regno
);
9547 INSERT_OPERAND (FR
, *ip
, regno
);
9557 INSERT_OPERAND (FS
, *ip
, lastregno
);
9560 INSERT_OPERAND (FT
, *ip
, lastregno
);
9566 my_getExpression (&imm_expr
, s
);
9567 if (imm_expr
.X_op
!= O_big
9568 && imm_expr
.X_op
!= O_constant
)
9569 insn_error
= _("absolute expression required");
9570 if (HAVE_32BIT_GPRS
)
9571 normalize_constant_expr (&imm_expr
);
9576 my_getExpression (&offset_expr
, s
);
9577 normalize_address_expr (&offset_expr
);
9578 *imm_reloc
= BFD_RELOC_32
;
9591 unsigned char temp
[8];
9593 unsigned int length
;
9598 /* These only appear as the last operand in an
9599 instruction, and every instruction that accepts
9600 them in any variant accepts them in all variants.
9601 This means we don't have to worry about backing out
9602 any changes if the instruction does not match.
9604 The difference between them is the size of the
9605 floating point constant and where it goes. For 'F'
9606 and 'L' the constant is 64 bits; for 'f' and 'l' it
9607 is 32 bits. Where the constant is placed is based
9608 on how the MIPS assembler does things:
9611 f -- immediate value
9614 The .lit4 and .lit8 sections are only used if
9615 permitted by the -G argument.
9617 The code below needs to know whether the target register
9618 is 32 or 64 bits wide. It relies on the fact 'f' and
9619 'F' are used with GPR-based instructions and 'l' and
9620 'L' are used with FPR-based instructions. */
9622 f64
= *args
== 'F' || *args
== 'L';
9623 using_gprs
= *args
== 'F' || *args
== 'f';
9625 save_in
= input_line_pointer
;
9626 input_line_pointer
= s
;
9627 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9629 s
= input_line_pointer
;
9630 input_line_pointer
= save_in
;
9631 if (err
!= NULL
&& *err
!= '\0')
9633 as_bad (_("Bad floating point constant: %s"), err
);
9634 memset (temp
, '\0', sizeof temp
);
9635 length
= f64
? 8 : 4;
9638 assert (length
== (unsigned) (f64
? 8 : 4));
9642 && (g_switch_value
< 4
9643 || (temp
[0] == 0 && temp
[1] == 0)
9644 || (temp
[2] == 0 && temp
[3] == 0))))
9646 imm_expr
.X_op
= O_constant
;
9647 if (! target_big_endian
)
9648 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9650 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9653 && ! mips_disable_float_construction
9654 /* Constants can only be constructed in GPRs and
9655 copied to FPRs if the GPRs are at least as wide
9656 as the FPRs. Force the constant into memory if
9657 we are using 64-bit FPRs but the GPRs are only
9660 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9661 && ((temp
[0] == 0 && temp
[1] == 0)
9662 || (temp
[2] == 0 && temp
[3] == 0))
9663 && ((temp
[4] == 0 && temp
[5] == 0)
9664 || (temp
[6] == 0 && temp
[7] == 0)))
9666 /* The value is simple enough to load with a couple of
9667 instructions. If using 32-bit registers, set
9668 imm_expr to the high order 32 bits and offset_expr to
9669 the low order 32 bits. Otherwise, set imm_expr to
9670 the entire 64 bit constant. */
9671 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9673 imm_expr
.X_op
= O_constant
;
9674 offset_expr
.X_op
= O_constant
;
9675 if (! target_big_endian
)
9677 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9678 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9682 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9683 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9685 if (offset_expr
.X_add_number
== 0)
9686 offset_expr
.X_op
= O_absent
;
9688 else if (sizeof (imm_expr
.X_add_number
) > 4)
9690 imm_expr
.X_op
= O_constant
;
9691 if (! target_big_endian
)
9692 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9694 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9698 imm_expr
.X_op
= O_big
;
9699 imm_expr
.X_add_number
= 4;
9700 if (! target_big_endian
)
9702 generic_bignum
[0] = bfd_getl16 (temp
);
9703 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9704 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9705 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9709 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9710 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9711 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9712 generic_bignum
[3] = bfd_getb16 (temp
);
9718 const char *newname
;
9721 /* Switch to the right section. */
9723 subseg
= now_subseg
;
9726 default: /* unused default case avoids warnings. */
9728 newname
= RDATA_SECTION_NAME
;
9729 if (g_switch_value
>= 8)
9733 newname
= RDATA_SECTION_NAME
;
9736 assert (g_switch_value
>= 4);
9740 new_seg
= subseg_new (newname
, (subsegT
) 0);
9742 bfd_set_section_flags (stdoutput
, new_seg
,
9747 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9748 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
9749 record_alignment (new_seg
, 4);
9751 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9753 as_bad (_("Can't use floating point insn in this section"));
9755 /* Set the argument to the current address in the
9757 offset_expr
.X_op
= O_symbol
;
9758 offset_expr
.X_add_symbol
=
9759 symbol_new ("L0\001", now_seg
,
9760 (valueT
) frag_now_fix (), frag_now
);
9761 offset_expr
.X_add_number
= 0;
9763 /* Put the floating point number into the section. */
9764 p
= frag_more ((int) length
);
9765 memcpy (p
, temp
, length
);
9767 /* Switch back to the original section. */
9768 subseg_set (seg
, subseg
);
9773 case 'i': /* 16 bit unsigned immediate */
9774 case 'j': /* 16 bit signed immediate */
9775 *imm_reloc
= BFD_RELOC_LO16
;
9776 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9779 offsetT minval
, maxval
;
9781 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9782 && strcmp (insn
->name
, insn
[1].name
) == 0);
9784 /* If the expression was written as an unsigned number,
9785 only treat it as signed if there are no more
9789 && sizeof (imm_expr
.X_add_number
) <= 4
9790 && imm_expr
.X_op
== O_constant
9791 && imm_expr
.X_add_number
< 0
9792 && imm_expr
.X_unsigned
9796 /* For compatibility with older assemblers, we accept
9797 0x8000-0xffff as signed 16-bit numbers when only
9798 signed numbers are allowed. */
9800 minval
= 0, maxval
= 0xffff;
9802 minval
= -0x8000, maxval
= 0x7fff;
9804 minval
= -0x8000, maxval
= 0xffff;
9806 if (imm_expr
.X_op
!= O_constant
9807 || imm_expr
.X_add_number
< minval
9808 || imm_expr
.X_add_number
> maxval
)
9812 if (imm_expr
.X_op
== O_constant
9813 || imm_expr
.X_op
== O_big
)
9814 as_bad (_("expression out of range"));
9820 case 'o': /* 16 bit offset */
9821 /* Check whether there is only a single bracketed expression
9822 left. If so, it must be the base register and the
9823 constant must be zero. */
9824 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9826 offset_expr
.X_op
= O_constant
;
9827 offset_expr
.X_add_number
= 0;
9831 /* If this value won't fit into a 16 bit offset, then go
9832 find a macro that will generate the 32 bit offset
9834 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9835 && (offset_expr
.X_op
!= O_constant
9836 || offset_expr
.X_add_number
>= 0x8000
9837 || offset_expr
.X_add_number
< -0x8000))
9843 case 'p': /* pc relative offset */
9844 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9845 my_getExpression (&offset_expr
, s
);
9849 case 'u': /* upper 16 bits */
9850 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9851 && imm_expr
.X_op
== O_constant
9852 && (imm_expr
.X_add_number
< 0
9853 || imm_expr
.X_add_number
>= 0x10000))
9854 as_bad (_("lui expression not in range 0..65535"));
9858 case 'a': /* 26 bit address */
9859 my_getExpression (&offset_expr
, s
);
9861 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9864 case 'N': /* 3 bit branch condition code */
9865 case 'M': /* 3 bit compare condition code */
9867 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9869 if (!reg_lookup (&s
, rtype
, ®no
))
9871 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9872 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9873 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9874 && (regno
& 1) != 0)
9875 as_warn(_("Condition code register should be even for %s, was %d"),
9877 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9878 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9879 && (regno
& 3) != 0)
9880 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9883 INSERT_OPERAND (BCC
, *ip
, regno
);
9885 INSERT_OPERAND (CCC
, *ip
, regno
);
9889 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9900 while (ISDIGIT (*s
));
9903 c
= 8; /* Invalid sel value. */
9906 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9907 ip
->insn_opcode
|= c
;
9911 /* Must be at least one digit. */
9912 my_getExpression (&imm_expr
, s
);
9913 check_absolute_expr (ip
, &imm_expr
);
9915 if ((unsigned long) imm_expr
.X_add_number
9916 > (unsigned long) OP_MASK_VECBYTE
)
9918 as_bad (_("bad byte vector index (%ld)"),
9919 (long) imm_expr
.X_add_number
);
9920 imm_expr
.X_add_number
= 0;
9923 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9924 imm_expr
.X_op
= O_absent
;
9929 my_getExpression (&imm_expr
, s
);
9930 check_absolute_expr (ip
, &imm_expr
);
9932 if ((unsigned long) imm_expr
.X_add_number
9933 > (unsigned long) OP_MASK_VECALIGN
)
9935 as_bad (_("bad byte vector index (%ld)"),
9936 (long) imm_expr
.X_add_number
);
9937 imm_expr
.X_add_number
= 0;
9940 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9941 imm_expr
.X_op
= O_absent
;
9946 as_bad (_("bad char = '%c'\n"), *args
);
9951 /* Args don't match. */
9952 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9953 !strcmp (insn
->name
, insn
[1].name
))
9957 insn_error
= _("illegal operands");
9962 insn_error
= _("illegal operands");
9967 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9969 /* This routine assembles an instruction into its binary format when
9970 assembling for the mips16. As a side effect, it sets one of the
9971 global variables imm_reloc or offset_reloc to the type of
9972 relocation to do if one of the operands is an address expression.
9973 It also sets mips16_small and mips16_ext if the user explicitly
9974 requested a small or extended instruction. */
9977 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9981 struct mips_opcode
*insn
;
9984 unsigned int lastregno
= 0;
9990 mips16_small
= FALSE
;
9993 for (s
= str
; ISLOWER (*s
); ++s
)
10005 if (s
[1] == 't' && s
[2] == ' ')
10008 mips16_small
= TRUE
;
10012 else if (s
[1] == 'e' && s
[2] == ' ')
10019 /* Fall through. */
10021 insn_error
= _("unknown opcode");
10025 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10026 mips16_small
= TRUE
;
10028 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10030 insn_error
= _("unrecognized opcode");
10039 assert (strcmp (insn
->name
, str
) == 0);
10041 ok
= is_opcode_valid_16 (insn
);
10044 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10045 && strcmp (insn
->name
, insn
[1].name
) == 0)
10054 static char buf
[100];
10056 _("opcode not supported on this processor: %s (%s)"),
10057 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10058 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10065 create_insn (ip
, insn
);
10066 imm_expr
.X_op
= O_absent
;
10067 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10068 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10069 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10070 imm2_expr
.X_op
= O_absent
;
10071 offset_expr
.X_op
= O_absent
;
10072 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10073 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10074 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10075 for (args
= insn
->args
; 1; ++args
)
10082 /* In this switch statement we call break if we did not find
10083 a match, continue if we did find a match, or return if we
10092 /* Stuff the immediate value in now, if we can. */
10093 if (imm_expr
.X_op
== O_constant
10094 && *imm_reloc
> BFD_RELOC_UNUSED
10095 && insn
->pinfo
!= INSN_MACRO
)
10099 switch (*offset_reloc
)
10101 case BFD_RELOC_MIPS16_HI16_S
:
10102 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10105 case BFD_RELOC_MIPS16_HI16
:
10106 tmp
= imm_expr
.X_add_number
>> 16;
10109 case BFD_RELOC_MIPS16_LO16
:
10110 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10114 case BFD_RELOC_UNUSED
:
10115 tmp
= imm_expr
.X_add_number
;
10121 *offset_reloc
= BFD_RELOC_UNUSED
;
10123 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10124 tmp
, TRUE
, mips16_small
,
10125 mips16_ext
, &ip
->insn_opcode
,
10126 &ip
->use_extend
, &ip
->extend
);
10127 imm_expr
.X_op
= O_absent
;
10128 *imm_reloc
= BFD_RELOC_UNUSED
;
10142 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10145 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10161 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10163 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10167 /* Fall through. */
10178 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10180 if (c
== 'v' || c
== 'w')
10183 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10185 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10196 if (c
== 'v' || c
== 'w')
10198 regno
= mips16_to_32_reg_map
[lastregno
];
10212 regno
= mips32_to_16_reg_map
[regno
];
10217 regno
= ILLEGAL_REG
;
10222 regno
= ILLEGAL_REG
;
10227 regno
= ILLEGAL_REG
;
10232 if (regno
== AT
&& mips_opts
.at
)
10234 if (mips_opts
.at
== ATREG
)
10235 as_warn (_("used $at without \".set noat\""));
10237 as_warn (_("used $%u with \".set at=$%u\""),
10238 regno
, mips_opts
.at
);
10246 if (regno
== ILLEGAL_REG
)
10253 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10257 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10260 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10263 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10269 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10272 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10273 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10283 if (strncmp (s
, "$pc", 3) == 0)
10300 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10303 if (imm_expr
.X_op
!= O_constant
)
10306 ip
->use_extend
= TRUE
;
10311 /* We need to relax this instruction. */
10312 *offset_reloc
= *imm_reloc
;
10313 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10318 *imm_reloc
= BFD_RELOC_UNUSED
;
10319 /* Fall through. */
10326 my_getExpression (&imm_expr
, s
);
10327 if (imm_expr
.X_op
== O_register
)
10329 /* What we thought was an expression turned out to
10332 if (s
[0] == '(' && args
[1] == '(')
10334 /* It looks like the expression was omitted
10335 before a register indirection, which means
10336 that the expression is implicitly zero. We
10337 still set up imm_expr, so that we handle
10338 explicit extensions correctly. */
10339 imm_expr
.X_op
= O_constant
;
10340 imm_expr
.X_add_number
= 0;
10341 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10348 /* We need to relax this instruction. */
10349 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10358 /* We use offset_reloc rather than imm_reloc for the PC
10359 relative operands. This lets macros with both
10360 immediate and address operands work correctly. */
10361 my_getExpression (&offset_expr
, s
);
10363 if (offset_expr
.X_op
== O_register
)
10366 /* We need to relax this instruction. */
10367 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10371 case '6': /* break code */
10372 my_getExpression (&imm_expr
, s
);
10373 check_absolute_expr (ip
, &imm_expr
);
10374 if ((unsigned long) imm_expr
.X_add_number
> 63)
10375 as_warn (_("Invalid value for `%s' (%lu)"),
10377 (unsigned long) imm_expr
.X_add_number
);
10378 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10379 imm_expr
.X_op
= O_absent
;
10383 case 'a': /* 26 bit address */
10384 my_getExpression (&offset_expr
, s
);
10386 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10387 ip
->insn_opcode
<<= 16;
10390 case 'l': /* register list for entry macro */
10391 case 'L': /* register list for exit macro */
10401 unsigned int freg
, reg1
, reg2
;
10403 while (*s
== ' ' || *s
== ',')
10405 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10407 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10411 as_bad (_("can't parse register list"));
10421 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10422 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10424 as_bad (_("invalid register list"));
10428 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10430 mask
&= ~ (7 << 3);
10433 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10435 mask
&= ~ (7 << 3);
10438 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10439 mask
|= (reg2
- 3) << 3;
10440 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10441 mask
|= (reg2
- 15) << 1;
10442 else if (reg1
== RA
&& reg2
== RA
)
10446 as_bad (_("invalid register list"));
10450 /* The mask is filled in in the opcode table for the
10451 benefit of the disassembler. We remove it before
10452 applying the actual mask. */
10453 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10454 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10458 case 'm': /* Register list for save insn. */
10459 case 'M': /* Register list for restore insn. */
10462 int framesz
= 0, seen_framesz
= 0;
10463 int args
= 0, statics
= 0, sregs
= 0;
10467 unsigned int reg1
, reg2
;
10469 SKIP_SPACE_TABS (s
);
10472 SKIP_SPACE_TABS (s
);
10474 my_getExpression (&imm_expr
, s
);
10475 if (imm_expr
.X_op
== O_constant
)
10477 /* Handle the frame size. */
10480 as_bad (_("more than one frame size in list"));
10484 framesz
= imm_expr
.X_add_number
;
10485 imm_expr
.X_op
= O_absent
;
10490 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10492 as_bad (_("can't parse register list"));
10504 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10507 as_bad (_("can't parse register list"));
10512 while (reg1
<= reg2
)
10514 if (reg1
>= 4 && reg1
<= 7)
10518 args
|= 1 << (reg1
- 4);
10520 /* statics $a0-$a3 */
10521 statics
|= 1 << (reg1
- 4);
10523 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10526 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10528 else if (reg1
== 31)
10530 /* Add $ra to insn. */
10535 as_bad (_("unexpected register in list"));
10543 /* Encode args/statics combination. */
10544 if (args
& statics
)
10545 as_bad (_("arg/static registers overlap"));
10546 else if (args
== 0xf)
10547 /* All $a0-$a3 are args. */
10548 opcode
|= MIPS16_ALL_ARGS
<< 16;
10549 else if (statics
== 0xf)
10550 /* All $a0-$a3 are statics. */
10551 opcode
|= MIPS16_ALL_STATICS
<< 16;
10554 int narg
= 0, nstat
= 0;
10556 /* Count arg registers. */
10563 as_bad (_("invalid arg register list"));
10565 /* Count static registers. */
10566 while (statics
& 0x8)
10568 statics
= (statics
<< 1) & 0xf;
10572 as_bad (_("invalid static register list"));
10574 /* Encode args/statics. */
10575 opcode
|= ((narg
<< 2) | nstat
) << 16;
10578 /* Encode $s0/$s1. */
10579 if (sregs
& (1 << 0)) /* $s0 */
10581 if (sregs
& (1 << 1)) /* $s1 */
10587 /* Count regs $s2-$s8. */
10595 as_bad (_("invalid static register list"));
10596 /* Encode $s2-$s8. */
10597 opcode
|= nsreg
<< 24;
10600 /* Encode frame size. */
10602 as_bad (_("missing frame size"));
10603 else if ((framesz
& 7) != 0 || framesz
< 0
10604 || framesz
> 0xff * 8)
10605 as_bad (_("invalid frame size"));
10606 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10609 opcode
|= (((framesz
& 0xf0) << 16)
10610 | (framesz
& 0x0f));
10613 /* Finally build the instruction. */
10614 if ((opcode
>> 16) != 0 || framesz
== 0)
10616 ip
->use_extend
= TRUE
;
10617 ip
->extend
= opcode
>> 16;
10619 ip
->insn_opcode
|= opcode
& 0x7f;
10623 case 'e': /* extend code */
10624 my_getExpression (&imm_expr
, s
);
10625 check_absolute_expr (ip
, &imm_expr
);
10626 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10628 as_warn (_("Invalid value for `%s' (%lu)"),
10630 (unsigned long) imm_expr
.X_add_number
);
10631 imm_expr
.X_add_number
&= 0x7ff;
10633 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10634 imm_expr
.X_op
= O_absent
;
10644 /* Args don't match. */
10645 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10646 strcmp (insn
->name
, insn
[1].name
) == 0)
10653 insn_error
= _("illegal operands");
10659 /* This structure holds information we know about a mips16 immediate
10662 struct mips16_immed_operand
10664 /* The type code used in the argument string in the opcode table. */
10666 /* The number of bits in the short form of the opcode. */
10668 /* The number of bits in the extended form of the opcode. */
10670 /* The amount by which the short form is shifted when it is used;
10671 for example, the sw instruction has a shift count of 2. */
10673 /* The amount by which the short form is shifted when it is stored
10674 into the instruction code. */
10676 /* Non-zero if the short form is unsigned. */
10678 /* Non-zero if the extended form is unsigned. */
10680 /* Non-zero if the value is PC relative. */
10684 /* The mips16 immediate operand types. */
10686 static const struct mips16_immed_operand mips16_immed_operands
[] =
10688 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10689 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10690 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10691 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10692 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10693 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10694 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10695 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10696 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10697 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10698 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10699 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10700 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10701 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10702 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10703 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10704 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10705 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10706 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10707 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10708 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10711 #define MIPS16_NUM_IMMED \
10712 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10714 /* Handle a mips16 instruction with an immediate value. This or's the
10715 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10716 whether an extended value is needed; if one is needed, it sets
10717 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10718 If SMALL is true, an unextended opcode was explicitly requested.
10719 If EXT is true, an extended opcode was explicitly requested. If
10720 WARN is true, warn if EXT does not match reality. */
10723 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10724 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10725 unsigned long *insn
, bfd_boolean
*use_extend
,
10726 unsigned short *extend
)
10728 const struct mips16_immed_operand
*op
;
10729 int mintiny
, maxtiny
;
10730 bfd_boolean needext
;
10732 op
= mips16_immed_operands
;
10733 while (op
->type
!= type
)
10736 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10741 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10744 maxtiny
= 1 << op
->nbits
;
10749 maxtiny
= (1 << op
->nbits
) - 1;
10754 mintiny
= - (1 << (op
->nbits
- 1));
10755 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10758 /* Branch offsets have an implicit 0 in the lowest bit. */
10759 if (type
== 'p' || type
== 'q')
10762 if ((val
& ((1 << op
->shift
) - 1)) != 0
10763 || val
< (mintiny
<< op
->shift
)
10764 || val
> (maxtiny
<< op
->shift
))
10769 if (warn
&& ext
&& ! needext
)
10770 as_warn_where (file
, line
,
10771 _("extended operand requested but not required"));
10772 if (small
&& needext
)
10773 as_bad_where (file
, line
, _("invalid unextended operand value"));
10775 if (small
|| (! ext
&& ! needext
))
10779 *use_extend
= FALSE
;
10780 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10781 insnval
<<= op
->op_shift
;
10786 long minext
, maxext
;
10792 maxext
= (1 << op
->extbits
) - 1;
10796 minext
= - (1 << (op
->extbits
- 1));
10797 maxext
= (1 << (op
->extbits
- 1)) - 1;
10799 if (val
< minext
|| val
> maxext
)
10800 as_bad_where (file
, line
,
10801 _("operand value out of range for instruction"));
10803 *use_extend
= TRUE
;
10804 if (op
->extbits
== 16)
10806 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10809 else if (op
->extbits
== 15)
10811 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10816 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10820 *extend
= (unsigned short) extval
;
10825 struct percent_op_match
10828 bfd_reloc_code_real_type reloc
;
10831 static const struct percent_op_match mips_percent_op
[] =
10833 {"%lo", BFD_RELOC_LO16
},
10835 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10836 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10837 {"%call16", BFD_RELOC_MIPS_CALL16
},
10838 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10839 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10840 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10841 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10842 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10843 {"%got", BFD_RELOC_MIPS_GOT16
},
10844 {"%gp_rel", BFD_RELOC_GPREL16
},
10845 {"%half", BFD_RELOC_16
},
10846 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10847 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10848 {"%neg", BFD_RELOC_MIPS_SUB
},
10849 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10850 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10851 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10852 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10853 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10854 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10855 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10857 {"%hi", BFD_RELOC_HI16_S
}
10860 static const struct percent_op_match mips16_percent_op
[] =
10862 {"%lo", BFD_RELOC_MIPS16_LO16
},
10863 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10864 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10868 /* Return true if *STR points to a relocation operator. When returning true,
10869 move *STR over the operator and store its relocation code in *RELOC.
10870 Leave both *STR and *RELOC alone when returning false. */
10873 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10875 const struct percent_op_match
*percent_op
;
10878 if (mips_opts
.mips16
)
10880 percent_op
= mips16_percent_op
;
10881 limit
= ARRAY_SIZE (mips16_percent_op
);
10885 percent_op
= mips_percent_op
;
10886 limit
= ARRAY_SIZE (mips_percent_op
);
10889 for (i
= 0; i
< limit
; i
++)
10890 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10892 int len
= strlen (percent_op
[i
].str
);
10894 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10897 *str
+= strlen (percent_op
[i
].str
);
10898 *reloc
= percent_op
[i
].reloc
;
10900 /* Check whether the output BFD supports this relocation.
10901 If not, issue an error and fall back on something safe. */
10902 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10904 as_bad ("relocation %s isn't supported by the current ABI",
10905 percent_op
[i
].str
);
10906 *reloc
= BFD_RELOC_UNUSED
;
10914 /* Parse string STR as a 16-bit relocatable operand. Store the
10915 expression in *EP and the relocations in the array starting
10916 at RELOC. Return the number of relocation operators used.
10918 On exit, EXPR_END points to the first character after the expression. */
10921 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10924 bfd_reloc_code_real_type reversed_reloc
[3];
10925 size_t reloc_index
, i
;
10926 int crux_depth
, str_depth
;
10929 /* Search for the start of the main expression, recoding relocations
10930 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10931 of the main expression and with CRUX_DEPTH containing the number
10932 of open brackets at that point. */
10939 crux_depth
= str_depth
;
10941 /* Skip over whitespace and brackets, keeping count of the number
10943 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10948 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10949 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10951 my_getExpression (ep
, crux
);
10954 /* Match every open bracket. */
10955 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10959 if (crux_depth
> 0)
10960 as_bad ("unclosed '('");
10964 if (reloc_index
!= 0)
10966 prev_reloc_op_frag
= frag_now
;
10967 for (i
= 0; i
< reloc_index
; i
++)
10968 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10971 return reloc_index
;
10975 my_getExpression (expressionS
*ep
, char *str
)
10980 save_in
= input_line_pointer
;
10981 input_line_pointer
= str
;
10983 expr_end
= input_line_pointer
;
10984 input_line_pointer
= save_in
;
10986 /* If we are in mips16 mode, and this is an expression based on `.',
10987 then we bump the value of the symbol by 1 since that is how other
10988 text symbols are handled. We don't bother to handle complex
10989 expressions, just `.' plus or minus a constant. */
10990 if (mips_opts
.mips16
10991 && ep
->X_op
== O_symbol
10992 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10993 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10994 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10995 && symbol_constant_p (ep
->X_add_symbol
)
10996 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10997 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
11001 md_atof (int type
, char *litP
, int *sizeP
)
11003 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11007 md_number_to_chars (char *buf
, valueT val
, int n
)
11009 if (target_big_endian
)
11010 number_to_chars_bigendian (buf
, val
, n
);
11012 number_to_chars_littleendian (buf
, val
, n
);
11016 static int support_64bit_objects(void)
11018 const char **list
, **l
;
11021 list
= bfd_target_list ();
11022 for (l
= list
; *l
!= NULL
; l
++)
11024 /* This is traditional mips */
11025 if (strcmp (*l
, "elf64-tradbigmips") == 0
11026 || strcmp (*l
, "elf64-tradlittlemips") == 0)
11028 if (strcmp (*l
, "elf64-bigmips") == 0
11029 || strcmp (*l
, "elf64-littlemips") == 0)
11032 yes
= (*l
!= NULL
);
11036 #endif /* OBJ_ELF */
11038 const char *md_shortopts
= "O::g::G:";
11040 struct option md_longopts
[] =
11042 /* Options which specify architecture. */
11043 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
11044 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
11045 {"march", required_argument
, NULL
, OPTION_MARCH
},
11046 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
11047 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11048 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
11049 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11050 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11051 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
11052 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11053 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
11054 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11055 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
11056 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11057 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
11058 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11059 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
11060 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11061 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
11062 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11063 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
11064 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11065 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
11066 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11068 /* Options which specify Application Specific Extensions (ASEs). */
11069 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
11070 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
11071 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11072 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
11073 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11074 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
11075 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11076 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
11077 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11078 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
11079 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11080 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
11081 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11082 #define OPTION_DSP (OPTION_ASE_BASE + 6)
11083 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11084 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
11085 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11086 #define OPTION_MT (OPTION_ASE_BASE + 8)
11087 {"mmt", no_argument
, NULL
, OPTION_MT
},
11088 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
11089 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11090 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
11091 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11092 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
11093 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11094 #define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
11095 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11096 #define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
11097 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11099 /* Old-style architecture options. Don't add more of these. */
11100 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
11101 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
11102 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11103 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
11104 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11105 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
11106 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11107 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
11108 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11109 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
11110 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11111 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
11112 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11113 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
11114 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11115 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
11116 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11118 /* Options which enable bug fixes. */
11119 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
11120 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
11121 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11122 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
11123 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11124 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11125 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
11126 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
11127 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11128 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11129 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
11130 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
11131 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11132 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11134 /* Miscellaneous options. */
11135 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
11136 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
11137 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11138 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11139 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
11140 {"break", no_argument
, NULL
, OPTION_BREAK
},
11141 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11142 #define OPTION_EB (OPTION_MISC_BASE + 2)
11143 {"EB", no_argument
, NULL
, OPTION_EB
},
11144 #define OPTION_EL (OPTION_MISC_BASE + 3)
11145 {"EL", no_argument
, NULL
, OPTION_EL
},
11146 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
11147 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11148 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
11149 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11150 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
11151 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11152 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
11153 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11154 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
11155 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11156 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
11157 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11158 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
11159 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
11160 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11161 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11162 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
11163 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
11164 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11165 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11166 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
11167 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
11168 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11169 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11170 #define OPTION_SOFT_FLOAT (OPTION_MISC_BASE + 16)
11171 #define OPTION_HARD_FLOAT (OPTION_MISC_BASE + 17)
11172 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11173 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11174 #define OPTION_SINGLE_FLOAT (OPTION_MISC_BASE + 18)
11175 #define OPTION_DOUBLE_FLOAT (OPTION_MISC_BASE + 19)
11176 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11177 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11179 /* ELF-specific options. */
11181 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 20)
11182 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
11183 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11184 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11185 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
11186 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11187 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
11188 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11189 #define OPTION_MABI (OPTION_ELF_BASE + 3)
11190 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11191 #define OPTION_32 (OPTION_ELF_BASE + 4)
11192 {"32", no_argument
, NULL
, OPTION_32
},
11193 #define OPTION_N32 (OPTION_ELF_BASE + 5)
11194 {"n32", no_argument
, NULL
, OPTION_N32
},
11195 #define OPTION_64 (OPTION_ELF_BASE + 6)
11196 {"64", no_argument
, NULL
, OPTION_64
},
11197 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
11198 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11199 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
11200 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11201 #define OPTION_PDR (OPTION_ELF_BASE + 9)
11202 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11203 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
11204 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11205 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
11206 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11207 #endif /* OBJ_ELF */
11209 {NULL
, no_argument
, NULL
, 0}
11211 size_t md_longopts_size
= sizeof (md_longopts
);
11213 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11214 NEW_VALUE. Warn if another value was already specified. Note:
11215 we have to defer parsing the -march and -mtune arguments in order
11216 to handle 'from-abi' correctly, since the ABI might be specified
11217 in a later argument. */
11220 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11222 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11223 as_warn (_("A different %s was already specified, is now %s"),
11224 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11227 *string_ptr
= new_value
;
11231 md_parse_option (int c
, char *arg
)
11235 case OPTION_CONSTRUCT_FLOATS
:
11236 mips_disable_float_construction
= 0;
11239 case OPTION_NO_CONSTRUCT_FLOATS
:
11240 mips_disable_float_construction
= 1;
11252 target_big_endian
= 1;
11256 target_big_endian
= 0;
11262 else if (arg
[0] == '0')
11264 else if (arg
[0] == '1')
11274 mips_debug
= atoi (arg
);
11278 file_mips_isa
= ISA_MIPS1
;
11282 file_mips_isa
= ISA_MIPS2
;
11286 file_mips_isa
= ISA_MIPS3
;
11290 file_mips_isa
= ISA_MIPS4
;
11294 file_mips_isa
= ISA_MIPS5
;
11297 case OPTION_MIPS32
:
11298 file_mips_isa
= ISA_MIPS32
;
11301 case OPTION_MIPS32R2
:
11302 file_mips_isa
= ISA_MIPS32R2
;
11305 case OPTION_MIPS64R2
:
11306 file_mips_isa
= ISA_MIPS64R2
;
11309 case OPTION_MIPS64
:
11310 file_mips_isa
= ISA_MIPS64
;
11314 mips_set_option_string (&mips_tune_string
, arg
);
11318 mips_set_option_string (&mips_arch_string
, arg
);
11322 mips_set_option_string (&mips_arch_string
, "4650");
11323 mips_set_option_string (&mips_tune_string
, "4650");
11326 case OPTION_NO_M4650
:
11330 mips_set_option_string (&mips_arch_string
, "4010");
11331 mips_set_option_string (&mips_tune_string
, "4010");
11334 case OPTION_NO_M4010
:
11338 mips_set_option_string (&mips_arch_string
, "4100");
11339 mips_set_option_string (&mips_tune_string
, "4100");
11342 case OPTION_NO_M4100
:
11346 mips_set_option_string (&mips_arch_string
, "3900");
11347 mips_set_option_string (&mips_tune_string
, "3900");
11350 case OPTION_NO_M3900
:
11354 mips_opts
.ase_mdmx
= 1;
11357 case OPTION_NO_MDMX
:
11358 mips_opts
.ase_mdmx
= 0;
11362 mips_opts
.ase_dsp
= 1;
11363 mips_opts
.ase_dspr2
= 0;
11366 case OPTION_NO_DSP
:
11367 mips_opts
.ase_dsp
= 0;
11368 mips_opts
.ase_dspr2
= 0;
11372 mips_opts
.ase_dspr2
= 1;
11373 mips_opts
.ase_dsp
= 1;
11376 case OPTION_NO_DSPR2
:
11377 mips_opts
.ase_dspr2
= 0;
11378 mips_opts
.ase_dsp
= 0;
11382 mips_opts
.ase_mt
= 1;
11386 mips_opts
.ase_mt
= 0;
11389 case OPTION_MIPS16
:
11390 mips_opts
.mips16
= 1;
11391 mips_no_prev_insn ();
11394 case OPTION_NO_MIPS16
:
11395 mips_opts
.mips16
= 0;
11396 mips_no_prev_insn ();
11399 case OPTION_MIPS3D
:
11400 mips_opts
.ase_mips3d
= 1;
11403 case OPTION_NO_MIPS3D
:
11404 mips_opts
.ase_mips3d
= 0;
11407 case OPTION_SMARTMIPS
:
11408 mips_opts
.ase_smartmips
= 1;
11411 case OPTION_NO_SMARTMIPS
:
11412 mips_opts
.ase_smartmips
= 0;
11415 case OPTION_FIX_VR4120
:
11416 mips_fix_vr4120
= 1;
11419 case OPTION_NO_FIX_VR4120
:
11420 mips_fix_vr4120
= 0;
11423 case OPTION_FIX_VR4130
:
11424 mips_fix_vr4130
= 1;
11427 case OPTION_NO_FIX_VR4130
:
11428 mips_fix_vr4130
= 0;
11431 case OPTION_RELAX_BRANCH
:
11432 mips_relax_branch
= 1;
11435 case OPTION_NO_RELAX_BRANCH
:
11436 mips_relax_branch
= 0;
11439 case OPTION_MSHARED
:
11440 mips_in_shared
= TRUE
;
11443 case OPTION_MNO_SHARED
:
11444 mips_in_shared
= FALSE
;
11447 case OPTION_MSYM32
:
11448 mips_opts
.sym32
= TRUE
;
11451 case OPTION_MNO_SYM32
:
11452 mips_opts
.sym32
= FALSE
;
11456 /* When generating ELF code, we permit -KPIC and -call_shared to
11457 select SVR4_PIC, and -non_shared to select no PIC. This is
11458 intended to be compatible with Irix 5. */
11459 case OPTION_CALL_SHARED
:
11462 as_bad (_("-call_shared is supported only for ELF format"));
11465 mips_pic
= SVR4_PIC
;
11466 mips_abicalls
= TRUE
;
11469 case OPTION_NON_SHARED
:
11472 as_bad (_("-non_shared is supported only for ELF format"));
11476 mips_abicalls
= FALSE
;
11479 /* The -xgot option tells the assembler to use 32 bit offsets
11480 when accessing the got in SVR4_PIC mode. It is for Irix
11485 #endif /* OBJ_ELF */
11488 g_switch_value
= atoi (arg
);
11493 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11498 as_bad (_("-32 is supported for ELF format only"));
11501 mips_abi
= O32_ABI
;
11507 as_bad (_("-n32 is supported for ELF format only"));
11510 mips_abi
= N32_ABI
;
11516 as_bad (_("-64 is supported for ELF format only"));
11519 mips_abi
= N64_ABI
;
11520 if (!support_64bit_objects())
11521 as_fatal (_("No compiled in support for 64 bit object file format"));
11523 #endif /* OBJ_ELF */
11526 file_mips_gp32
= 1;
11530 file_mips_gp32
= 0;
11534 file_mips_fp32
= 1;
11538 file_mips_fp32
= 0;
11541 case OPTION_SINGLE_FLOAT
:
11542 file_mips_single_float
= 1;
11545 case OPTION_DOUBLE_FLOAT
:
11546 file_mips_single_float
= 0;
11549 case OPTION_SOFT_FLOAT
:
11550 file_mips_soft_float
= 1;
11553 case OPTION_HARD_FLOAT
:
11554 file_mips_soft_float
= 0;
11561 as_bad (_("-mabi is supported for ELF format only"));
11564 if (strcmp (arg
, "32") == 0)
11565 mips_abi
= O32_ABI
;
11566 else if (strcmp (arg
, "o64") == 0)
11567 mips_abi
= O64_ABI
;
11568 else if (strcmp (arg
, "n32") == 0)
11569 mips_abi
= N32_ABI
;
11570 else if (strcmp (arg
, "64") == 0)
11572 mips_abi
= N64_ABI
;
11573 if (! support_64bit_objects())
11574 as_fatal (_("No compiled in support for 64 bit object file "
11577 else if (strcmp (arg
, "eabi") == 0)
11578 mips_abi
= EABI_ABI
;
11581 as_fatal (_("invalid abi -mabi=%s"), arg
);
11585 #endif /* OBJ_ELF */
11587 case OPTION_M7000_HILO_FIX
:
11588 mips_7000_hilo_fix
= TRUE
;
11591 case OPTION_MNO_7000_HILO_FIX
:
11592 mips_7000_hilo_fix
= FALSE
;
11596 case OPTION_MDEBUG
:
11597 mips_flag_mdebug
= TRUE
;
11600 case OPTION_NO_MDEBUG
:
11601 mips_flag_mdebug
= FALSE
;
11605 mips_flag_pdr
= TRUE
;
11608 case OPTION_NO_PDR
:
11609 mips_flag_pdr
= FALSE
;
11612 case OPTION_MVXWORKS_PIC
:
11613 mips_pic
= VXWORKS_PIC
;
11615 #endif /* OBJ_ELF */
11624 /* Set up globals to generate code for the ISA or processor
11625 described by INFO. */
11628 mips_set_architecture (const struct mips_cpu_info
*info
)
11632 file_mips_arch
= info
->cpu
;
11633 mips_opts
.arch
= info
->cpu
;
11634 mips_opts
.isa
= info
->isa
;
11639 /* Likewise for tuning. */
11642 mips_set_tune (const struct mips_cpu_info
*info
)
11645 mips_tune
= info
->cpu
;
11650 mips_after_parse_args (void)
11652 const struct mips_cpu_info
*arch_info
= 0;
11653 const struct mips_cpu_info
*tune_info
= 0;
11655 /* GP relative stuff not working for PE */
11656 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11658 if (g_switch_seen
&& g_switch_value
!= 0)
11659 as_bad (_("-G not supported in this configuration."));
11660 g_switch_value
= 0;
11663 if (mips_abi
== NO_ABI
)
11664 mips_abi
= MIPS_DEFAULT_ABI
;
11666 /* The following code determines the architecture and register size.
11667 Similar code was added to GCC 3.3 (see override_options() in
11668 config/mips/mips.c). The GAS and GCC code should be kept in sync
11669 as much as possible. */
11671 if (mips_arch_string
!= 0)
11672 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11674 if (file_mips_isa
!= ISA_UNKNOWN
)
11676 /* Handle -mipsN. At this point, file_mips_isa contains the
11677 ISA level specified by -mipsN, while arch_info->isa contains
11678 the -march selection (if any). */
11679 if (arch_info
!= 0)
11681 /* -march takes precedence over -mipsN, since it is more descriptive.
11682 There's no harm in specifying both as long as the ISA levels
11684 if (file_mips_isa
!= arch_info
->isa
)
11685 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11686 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11687 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11690 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11693 if (arch_info
== 0)
11694 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11696 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11697 as_bad ("-march=%s is not compatible with the selected ABI",
11700 mips_set_architecture (arch_info
);
11702 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11703 if (mips_tune_string
!= 0)
11704 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11706 if (tune_info
== 0)
11707 mips_set_tune (arch_info
);
11709 mips_set_tune (tune_info
);
11711 if (file_mips_gp32
>= 0)
11713 /* The user specified the size of the integer registers. Make sure
11714 it agrees with the ABI and ISA. */
11715 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11716 as_bad (_("-mgp64 used with a 32-bit processor"));
11717 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11718 as_bad (_("-mgp32 used with a 64-bit ABI"));
11719 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11720 as_bad (_("-mgp64 used with a 32-bit ABI"));
11724 /* Infer the integer register size from the ABI and processor.
11725 Restrict ourselves to 32-bit registers if that's all the
11726 processor has, or if the ABI cannot handle 64-bit registers. */
11727 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11728 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11731 switch (file_mips_fp32
)
11735 /* No user specified float register size.
11736 ??? GAS treats single-float processors as though they had 64-bit
11737 float registers (although it complains when double-precision
11738 instructions are used). As things stand, saying they have 32-bit
11739 registers would lead to spurious "register must be even" messages.
11740 So here we assume float registers are never smaller than the
11742 if (file_mips_gp32
== 0)
11743 /* 64-bit integer registers implies 64-bit float registers. */
11744 file_mips_fp32
= 0;
11745 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11746 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11747 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11748 file_mips_fp32
= 0;
11750 /* 32-bit float registers. */
11751 file_mips_fp32
= 1;
11754 /* The user specified the size of the float registers. Check if it
11755 agrees with the ABI and ISA. */
11757 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11758 as_bad (_("-mfp64 used with a 32-bit fpu"));
11759 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11760 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11761 as_warn (_("-mfp64 used with a 32-bit ABI"));
11764 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11765 as_warn (_("-mfp32 used with a 64-bit ABI"));
11769 /* End of GCC-shared inference code. */
11771 /* This flag is set when we have a 64-bit capable CPU but use only
11772 32-bit wide registers. Note that EABI does not use it. */
11773 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11774 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11775 || mips_abi
== O32_ABI
))
11776 mips_32bitmode
= 1;
11778 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11779 as_bad (_("trap exception not supported at ISA 1"));
11781 /* If the selected architecture includes support for ASEs, enable
11782 generation of code for them. */
11783 if (mips_opts
.mips16
== -1)
11784 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11785 if (mips_opts
.ase_mips3d
== -1)
11786 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11787 && file_mips_fp32
== 0) ? 1 : 0;
11788 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11789 as_bad (_("-mfp32 used with -mips3d"));
11791 if (mips_opts
.ase_mdmx
== -1)
11792 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11793 && file_mips_fp32
== 0) ? 1 : 0;
11794 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11795 as_bad (_("-mfp32 used with -mdmx"));
11797 if (mips_opts
.ase_smartmips
== -1)
11798 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11799 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11800 as_warn ("%s ISA does not support SmartMIPS",
11801 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11803 if (mips_opts
.ase_dsp
== -1)
11804 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11805 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11806 as_warn ("%s ISA does not support DSP ASE",
11807 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11809 if (mips_opts
.ase_dspr2
== -1)
11811 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11812 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11814 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11815 as_warn ("%s ISA does not support DSP R2 ASE",
11816 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11818 if (mips_opts
.ase_mt
== -1)
11819 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11820 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11821 as_warn ("%s ISA does not support MT ASE",
11822 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11824 file_mips_isa
= mips_opts
.isa
;
11825 file_ase_mips16
= mips_opts
.mips16
;
11826 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11827 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11828 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11829 file_ase_dsp
= mips_opts
.ase_dsp
;
11830 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11831 file_ase_mt
= mips_opts
.ase_mt
;
11832 mips_opts
.gp32
= file_mips_gp32
;
11833 mips_opts
.fp32
= file_mips_fp32
;
11834 mips_opts
.soft_float
= file_mips_soft_float
;
11835 mips_opts
.single_float
= file_mips_single_float
;
11837 if (mips_flag_mdebug
< 0)
11839 #ifdef OBJ_MAYBE_ECOFF
11840 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11841 mips_flag_mdebug
= 1;
11843 #endif /* OBJ_MAYBE_ECOFF */
11844 mips_flag_mdebug
= 0;
11849 mips_init_after_args (void)
11851 /* initialize opcodes */
11852 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11853 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11857 md_pcrel_from (fixS
*fixP
)
11859 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11860 switch (fixP
->fx_r_type
)
11862 case BFD_RELOC_16_PCREL_S2
:
11863 case BFD_RELOC_MIPS_JMP
:
11864 /* Return the address of the delay slot. */
11867 /* We have no relocation type for PC relative MIPS16 instructions. */
11868 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11870 _("PC relative MIPS16 instruction references a different section"));
11875 /* This is called before the symbol table is processed. In order to
11876 work with gcc when using mips-tfile, we must keep all local labels.
11877 However, in other cases, we want to discard them. If we were
11878 called with -g, but we didn't see any debugging information, it may
11879 mean that gcc is smuggling debugging information through to
11880 mips-tfile, in which case we must generate all local labels. */
11883 mips_frob_file_before_adjust (void)
11885 #ifndef NO_ECOFF_DEBUGGING
11886 if (ECOFF_DEBUGGING
11888 && ! ecoff_debugging_seen
)
11889 flag_keep_locals
= 1;
11893 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11894 the corresponding LO16 reloc. This is called before md_apply_fix and
11895 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11896 relocation operators.
11898 For our purposes, a %lo() expression matches a %got() or %hi()
11901 (a) it refers to the same symbol; and
11902 (b) the offset applied in the %lo() expression is no lower than
11903 the offset applied in the %got() or %hi().
11905 (b) allows us to cope with code like:
11908 lh $4,%lo(foo+2)($4)
11910 ...which is legal on RELA targets, and has a well-defined behaviour
11911 if the user knows that adding 2 to "foo" will not induce a carry to
11914 When several %lo()s match a particular %got() or %hi(), we use the
11915 following rules to distinguish them:
11917 (1) %lo()s with smaller offsets are a better match than %lo()s with
11920 (2) %lo()s with no matching %got() or %hi() are better than those
11921 that already have a matching %got() or %hi().
11923 (3) later %lo()s are better than earlier %lo()s.
11925 These rules are applied in order.
11927 (1) means, among other things, that %lo()s with identical offsets are
11928 chosen if they exist.
11930 (2) means that we won't associate several high-part relocations with
11931 the same low-part relocation unless there's no alternative. Having
11932 several high parts for the same low part is a GNU extension; this rule
11933 allows careful users to avoid it.
11935 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11936 with the last high-part relocation being at the front of the list.
11937 It therefore makes sense to choose the last matching low-part
11938 relocation, all other things being equal. It's also easier
11939 to code that way. */
11942 mips_frob_file (void)
11944 struct mips_hi_fixup
*l
;
11945 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
11947 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11949 segment_info_type
*seginfo
;
11950 bfd_boolean matched_lo_p
;
11951 fixS
**hi_pos
, **lo_pos
, **pos
;
11953 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11955 /* If a GOT16 relocation turns out to be against a global symbol,
11956 there isn't supposed to be a matching LO. */
11957 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11958 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11961 /* Check quickly whether the next fixup happens to be a matching %lo. */
11962 if (fixup_has_matching_lo_p (l
->fixp
))
11965 seginfo
= seg_info (l
->seg
);
11967 /* Set HI_POS to the position of this relocation in the chain.
11968 Set LO_POS to the position of the chosen low-part relocation.
11969 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11970 relocation that matches an immediately-preceding high-part
11974 matched_lo_p
= FALSE
;
11976 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS16_HI16
11977 || l
->fixp
->fx_r_type
== BFD_RELOC_MIPS16_HI16_S
)
11978 looking_for_rtype
= BFD_RELOC_MIPS16_LO16
;
11980 looking_for_rtype
= BFD_RELOC_LO16
;
11982 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11984 if (*pos
== l
->fixp
)
11987 if ((*pos
)->fx_r_type
== looking_for_rtype
11988 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11989 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11991 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11993 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11996 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11997 && fixup_has_matching_lo_p (*pos
));
12000 /* If we found a match, remove the high-part relocation from its
12001 current position and insert it before the low-part relocation.
12002 Make the offsets match so that fixup_has_matching_lo_p()
12005 We don't warn about unmatched high-part relocations since some
12006 versions of gcc have been known to emit dead "lui ...%hi(...)"
12008 if (lo_pos
!= NULL
)
12010 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12011 if (l
->fixp
->fx_next
!= *lo_pos
)
12013 *hi_pos
= l
->fixp
->fx_next
;
12014 l
->fixp
->fx_next
= *lo_pos
;
12021 /* We may have combined relocations without symbols in the N32/N64 ABI.
12022 We have to prevent gas from dropping them. */
12025 mips_force_relocation (fixS
*fixp
)
12027 if (generic_force_reloc (fixp
))
12031 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12032 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12033 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
12034 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
12040 /* Apply a fixup to the object file. */
12043 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12047 reloc_howto_type
*howto
;
12049 /* We ignore generic BFD relocations we don't know about. */
12050 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12054 assert (fixP
->fx_size
== 4
12055 || fixP
->fx_r_type
== BFD_RELOC_16
12056 || fixP
->fx_r_type
== BFD_RELOC_64
12057 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12058 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12059 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12060 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12061 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12063 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12065 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12067 /* Don't treat parts of a composite relocation as done. There are two
12070 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12071 should nevertheless be emitted if the first part is.
12073 (2) In normal usage, composite relocations are never assembly-time
12074 constants. The easiest way of dealing with the pathological
12075 exceptions is to generate a relocation against STN_UNDEF and
12076 leave everything up to the linker. */
12077 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12080 switch (fixP
->fx_r_type
)
12082 case BFD_RELOC_MIPS_TLS_GD
:
12083 case BFD_RELOC_MIPS_TLS_LDM
:
12084 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12085 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12086 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12087 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12088 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12089 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12090 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12091 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12094 case BFD_RELOC_MIPS_JMP
:
12095 case BFD_RELOC_MIPS_SHIFT5
:
12096 case BFD_RELOC_MIPS_SHIFT6
:
12097 case BFD_RELOC_MIPS_GOT_DISP
:
12098 case BFD_RELOC_MIPS_GOT_PAGE
:
12099 case BFD_RELOC_MIPS_GOT_OFST
:
12100 case BFD_RELOC_MIPS_SUB
:
12101 case BFD_RELOC_MIPS_INSERT_A
:
12102 case BFD_RELOC_MIPS_INSERT_B
:
12103 case BFD_RELOC_MIPS_DELETE
:
12104 case BFD_RELOC_MIPS_HIGHEST
:
12105 case BFD_RELOC_MIPS_HIGHER
:
12106 case BFD_RELOC_MIPS_SCN_DISP
:
12107 case BFD_RELOC_MIPS_REL16
:
12108 case BFD_RELOC_MIPS_RELGOT
:
12109 case BFD_RELOC_MIPS_JALR
:
12110 case BFD_RELOC_HI16
:
12111 case BFD_RELOC_HI16_S
:
12112 case BFD_RELOC_GPREL16
:
12113 case BFD_RELOC_MIPS_LITERAL
:
12114 case BFD_RELOC_MIPS_CALL16
:
12115 case BFD_RELOC_MIPS_GOT16
:
12116 case BFD_RELOC_GPREL32
:
12117 case BFD_RELOC_MIPS_GOT_HI16
:
12118 case BFD_RELOC_MIPS_GOT_LO16
:
12119 case BFD_RELOC_MIPS_CALL_HI16
:
12120 case BFD_RELOC_MIPS_CALL_LO16
:
12121 case BFD_RELOC_MIPS16_GPREL
:
12122 case BFD_RELOC_MIPS16_HI16
:
12123 case BFD_RELOC_MIPS16_HI16_S
:
12124 case BFD_RELOC_MIPS16_JMP
:
12125 /* Nothing needed to do. The value comes from the reloc entry. */
12129 /* This is handled like BFD_RELOC_32, but we output a sign
12130 extended value if we are only 32 bits. */
12133 if (8 <= sizeof (valueT
))
12134 md_number_to_chars ((char *) buf
, *valP
, 8);
12139 if ((*valP
& 0x80000000) != 0)
12143 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12145 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12151 case BFD_RELOC_RVA
:
12154 /* If we are deleting this reloc entry, we must fill in the
12155 value now. This can happen if we have a .word which is not
12156 resolved when it appears but is later defined. */
12158 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12161 case BFD_RELOC_LO16
:
12162 case BFD_RELOC_MIPS16_LO16
:
12163 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12164 may be safe to remove, but if so it's not obvious. */
12165 /* When handling an embedded PIC switch statement, we can wind
12166 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12169 if (*valP
+ 0x8000 > 0xffff)
12170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12171 _("relocation overflow"));
12172 if (target_big_endian
)
12174 md_number_to_chars ((char *) buf
, *valP
, 2);
12178 case BFD_RELOC_16_PCREL_S2
:
12179 if ((*valP
& 0x3) != 0)
12180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12181 _("Branch to misaligned address (%lx)"), (long) *valP
);
12183 /* We need to save the bits in the instruction since fixup_segment()
12184 might be deleting the relocation entry (i.e., a branch within
12185 the current segment). */
12186 if (! fixP
->fx_done
)
12189 /* Update old instruction data. */
12190 if (target_big_endian
)
12191 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12193 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12195 if (*valP
+ 0x20000 <= 0x3ffff)
12197 insn
|= (*valP
>> 2) & 0xffff;
12198 md_number_to_chars ((char *) buf
, insn
, 4);
12200 else if (mips_pic
== NO_PIC
12202 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12203 && (fixP
->fx_frag
->fr_address
12204 < text_section
->vma
+ bfd_get_section_size (text_section
))
12205 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12206 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12207 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12209 /* The branch offset is too large. If this is an
12210 unconditional branch, and we are not generating PIC code,
12211 we can convert it to an absolute jump instruction. */
12212 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12213 insn
= 0x0c000000; /* jal */
12215 insn
= 0x08000000; /* j */
12216 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12218 fixP
->fx_addsy
= section_symbol (text_section
);
12219 *valP
+= md_pcrel_from (fixP
);
12220 md_number_to_chars ((char *) buf
, insn
, 4);
12224 /* If we got here, we have branch-relaxation disabled,
12225 and there's nothing we can do to fix this instruction
12226 without turning it into a longer sequence. */
12227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12228 _("Branch out of range"));
12232 case BFD_RELOC_VTABLE_INHERIT
:
12235 && !S_IS_DEFINED (fixP
->fx_addsy
)
12236 && !S_IS_WEAK (fixP
->fx_addsy
))
12237 S_SET_WEAK (fixP
->fx_addsy
);
12240 case BFD_RELOC_VTABLE_ENTRY
:
12248 /* Remember value for tc_gen_reloc. */
12249 fixP
->fx_addnumber
= *valP
;
12259 name
= input_line_pointer
;
12260 c
= get_symbol_end ();
12261 p
= (symbolS
*) symbol_find_or_make (name
);
12262 *input_line_pointer
= c
;
12266 /* Align the current frag to a given power of two. If a particular
12267 fill byte should be used, FILL points to an integer that contains
12268 that byte, otherwise FILL is null.
12270 The MIPS assembler also automatically adjusts any preceding
12274 mips_align (int to
, int *fill
, symbolS
*label
)
12276 mips_emit_delays ();
12277 mips_record_mips16_mode ();
12278 if (fill
== NULL
&& subseg_text_p (now_seg
))
12279 frag_align_code (to
, 0);
12281 frag_align (to
, fill
? *fill
: 0, 0);
12282 record_alignment (now_seg
, to
);
12285 assert (S_GET_SEGMENT (label
) == now_seg
);
12286 symbol_set_frag (label
, frag_now
);
12287 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12291 /* Align to a given power of two. .align 0 turns off the automatic
12292 alignment used by the data creating pseudo-ops. */
12295 s_align (int x ATTRIBUTE_UNUSED
)
12297 int temp
, fill_value
, *fill_ptr
;
12298 long max_alignment
= 28;
12300 /* o Note that the assembler pulls down any immediately preceding label
12301 to the aligned address.
12302 o It's not documented but auto alignment is reinstated by
12303 a .align pseudo instruction.
12304 o Note also that after auto alignment is turned off the mips assembler
12305 issues an error on attempt to assemble an improperly aligned data item.
12308 temp
= get_absolute_expression ();
12309 if (temp
> max_alignment
)
12310 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12313 as_warn (_("Alignment negative: 0 assumed."));
12316 if (*input_line_pointer
== ',')
12318 ++input_line_pointer
;
12319 fill_value
= get_absolute_expression ();
12320 fill_ptr
= &fill_value
;
12326 segment_info_type
*si
= seg_info (now_seg
);
12327 struct insn_label_list
*l
= si
->label_list
;
12328 /* Auto alignment should be switched on by next section change. */
12330 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12337 demand_empty_rest_of_line ();
12341 s_change_sec (int sec
)
12346 /* The ELF backend needs to know that we are changing sections, so
12347 that .previous works correctly. We could do something like check
12348 for an obj_section_change_hook macro, but that might be confusing
12349 as it would not be appropriate to use it in the section changing
12350 functions in read.c, since obj-elf.c intercepts those. FIXME:
12351 This should be cleaner, somehow. */
12353 obj_elf_section_change_hook ();
12356 mips_emit_delays ();
12366 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12367 demand_empty_rest_of_line ();
12371 seg
= subseg_new (RDATA_SECTION_NAME
,
12372 (subsegT
) get_absolute_expression ());
12375 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12376 | SEC_READONLY
| SEC_RELOC
12378 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12379 record_alignment (seg
, 4);
12381 demand_empty_rest_of_line ();
12385 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12388 bfd_set_section_flags (stdoutput
, seg
,
12389 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12390 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12391 record_alignment (seg
, 4);
12393 demand_empty_rest_of_line ();
12401 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12404 char *section_name
;
12409 int section_entry_size
;
12410 int section_alignment
;
12415 section_name
= input_line_pointer
;
12416 c
= get_symbol_end ();
12418 next_c
= *(input_line_pointer
+ 1);
12420 /* Do we have .section Name<,"flags">? */
12421 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12423 /* just after name is now '\0'. */
12424 *input_line_pointer
= c
;
12425 input_line_pointer
= section_name
;
12426 obj_elf_section (ignore
);
12429 input_line_pointer
++;
12431 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12433 section_type
= get_absolute_expression ();
12436 if (*input_line_pointer
++ == ',')
12437 section_flag
= get_absolute_expression ();
12440 if (*input_line_pointer
++ == ',')
12441 section_entry_size
= get_absolute_expression ();
12443 section_entry_size
= 0;
12444 if (*input_line_pointer
++ == ',')
12445 section_alignment
= get_absolute_expression ();
12447 section_alignment
= 0;
12449 section_name
= xstrdup (section_name
);
12451 /* When using the generic form of .section (as implemented by obj-elf.c),
12452 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12453 traditionally had to fall back on the more common @progbits instead.
12455 There's nothing really harmful in this, since bfd will correct
12456 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12457 means that, for backwards compatibility, the special_section entries
12458 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12460 Even so, we shouldn't force users of the MIPS .section syntax to
12461 incorrectly label the sections as SHT_PROGBITS. The best compromise
12462 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12463 generic type-checking code. */
12464 if (section_type
== SHT_MIPS_DWARF
)
12465 section_type
= SHT_PROGBITS
;
12467 obj_elf_change_section (section_name
, section_type
, section_flag
,
12468 section_entry_size
, 0, 0, 0);
12470 if (now_seg
->name
!= section_name
)
12471 free (section_name
);
12472 #endif /* OBJ_ELF */
12476 mips_enable_auto_align (void)
12482 s_cons (int log_size
)
12484 segment_info_type
*si
= seg_info (now_seg
);
12485 struct insn_label_list
*l
= si
->label_list
;
12488 label
= l
!= NULL
? l
->label
: NULL
;
12489 mips_emit_delays ();
12490 if (log_size
> 0 && auto_align
)
12491 mips_align (log_size
, 0, label
);
12492 mips_clear_insn_labels ();
12493 cons (1 << log_size
);
12497 s_float_cons (int type
)
12499 segment_info_type
*si
= seg_info (now_seg
);
12500 struct insn_label_list
*l
= si
->label_list
;
12503 label
= l
!= NULL
? l
->label
: NULL
;
12505 mips_emit_delays ();
12510 mips_align (3, 0, label
);
12512 mips_align (2, 0, label
);
12515 mips_clear_insn_labels ();
12520 /* Handle .globl. We need to override it because on Irix 5 you are
12523 where foo is an undefined symbol, to mean that foo should be
12524 considered to be the address of a function. */
12527 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12536 name
= input_line_pointer
;
12537 c
= get_symbol_end ();
12538 symbolP
= symbol_find_or_make (name
);
12539 S_SET_EXTERNAL (symbolP
);
12541 *input_line_pointer
= c
;
12542 SKIP_WHITESPACE ();
12544 /* On Irix 5, every global symbol that is not explicitly labelled as
12545 being a function is apparently labelled as being an object. */
12548 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12549 && (*input_line_pointer
!= ','))
12554 secname
= input_line_pointer
;
12555 c
= get_symbol_end ();
12556 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12558 as_bad (_("%s: no such section"), secname
);
12559 *input_line_pointer
= c
;
12561 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12562 flag
= BSF_FUNCTION
;
12565 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12567 c
= *input_line_pointer
;
12570 input_line_pointer
++;
12571 SKIP_WHITESPACE ();
12572 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12578 demand_empty_rest_of_line ();
12582 s_option (int x ATTRIBUTE_UNUSED
)
12587 opt
= input_line_pointer
;
12588 c
= get_symbol_end ();
12592 /* FIXME: What does this mean? */
12594 else if (strncmp (opt
, "pic", 3) == 0)
12598 i
= atoi (opt
+ 3);
12603 mips_pic
= SVR4_PIC
;
12604 mips_abicalls
= TRUE
;
12607 as_bad (_(".option pic%d not supported"), i
);
12609 if (mips_pic
== SVR4_PIC
)
12611 if (g_switch_seen
&& g_switch_value
!= 0)
12612 as_warn (_("-G may not be used with SVR4 PIC code"));
12613 g_switch_value
= 0;
12614 bfd_set_gp_size (stdoutput
, 0);
12618 as_warn (_("Unrecognized option \"%s\""), opt
);
12620 *input_line_pointer
= c
;
12621 demand_empty_rest_of_line ();
12624 /* This structure is used to hold a stack of .set values. */
12626 struct mips_option_stack
12628 struct mips_option_stack
*next
;
12629 struct mips_set_options options
;
12632 static struct mips_option_stack
*mips_opts_stack
;
12634 /* Handle the .set pseudo-op. */
12637 s_mipsset (int x ATTRIBUTE_UNUSED
)
12639 char *name
= input_line_pointer
, ch
;
12641 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12642 ++input_line_pointer
;
12643 ch
= *input_line_pointer
;
12644 *input_line_pointer
= '\0';
12646 if (strcmp (name
, "reorder") == 0)
12648 if (mips_opts
.noreorder
)
12651 else if (strcmp (name
, "noreorder") == 0)
12653 if (!mips_opts
.noreorder
)
12654 start_noreorder ();
12656 else if (strncmp (name
, "at=", 3) == 0)
12658 char *s
= name
+ 3;
12660 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12661 as_bad (_("Unrecognized register name `%s'"), s
);
12663 else if (strcmp (name
, "at") == 0)
12665 mips_opts
.at
= ATREG
;
12667 else if (strcmp (name
, "noat") == 0)
12669 mips_opts
.at
= ZERO
;
12671 else if (strcmp (name
, "macro") == 0)
12673 mips_opts
.warn_about_macros
= 0;
12675 else if (strcmp (name
, "nomacro") == 0)
12677 if (mips_opts
.noreorder
== 0)
12678 as_bad (_("`noreorder' must be set before `nomacro'"));
12679 mips_opts
.warn_about_macros
= 1;
12681 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12683 mips_opts
.nomove
= 0;
12685 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12687 mips_opts
.nomove
= 1;
12689 else if (strcmp (name
, "bopt") == 0)
12691 mips_opts
.nobopt
= 0;
12693 else if (strcmp (name
, "nobopt") == 0)
12695 mips_opts
.nobopt
= 1;
12697 else if (strcmp (name
, "gp=default") == 0)
12698 mips_opts
.gp32
= file_mips_gp32
;
12699 else if (strcmp (name
, "gp=32") == 0)
12700 mips_opts
.gp32
= 1;
12701 else if (strcmp (name
, "gp=64") == 0)
12703 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12704 as_warn ("%s isa does not support 64-bit registers",
12705 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12706 mips_opts
.gp32
= 0;
12708 else if (strcmp (name
, "fp=default") == 0)
12709 mips_opts
.fp32
= file_mips_fp32
;
12710 else if (strcmp (name
, "fp=32") == 0)
12711 mips_opts
.fp32
= 1;
12712 else if (strcmp (name
, "fp=64") == 0)
12714 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12715 as_warn ("%s isa does not support 64-bit floating point registers",
12716 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12717 mips_opts
.fp32
= 0;
12719 else if (strcmp (name
, "softfloat") == 0)
12720 mips_opts
.soft_float
= 1;
12721 else if (strcmp (name
, "hardfloat") == 0)
12722 mips_opts
.soft_float
= 0;
12723 else if (strcmp (name
, "singlefloat") == 0)
12724 mips_opts
.single_float
= 1;
12725 else if (strcmp (name
, "doublefloat") == 0)
12726 mips_opts
.single_float
= 0;
12727 else if (strcmp (name
, "mips16") == 0
12728 || strcmp (name
, "MIPS-16") == 0)
12729 mips_opts
.mips16
= 1;
12730 else if (strcmp (name
, "nomips16") == 0
12731 || strcmp (name
, "noMIPS-16") == 0)
12732 mips_opts
.mips16
= 0;
12733 else if (strcmp (name
, "smartmips") == 0)
12735 if (!ISA_SUPPORTS_SMARTMIPS
)
12736 as_warn ("%s ISA does not support SmartMIPS ASE",
12737 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12738 mips_opts
.ase_smartmips
= 1;
12740 else if (strcmp (name
, "nosmartmips") == 0)
12741 mips_opts
.ase_smartmips
= 0;
12742 else if (strcmp (name
, "mips3d") == 0)
12743 mips_opts
.ase_mips3d
= 1;
12744 else if (strcmp (name
, "nomips3d") == 0)
12745 mips_opts
.ase_mips3d
= 0;
12746 else if (strcmp (name
, "mdmx") == 0)
12747 mips_opts
.ase_mdmx
= 1;
12748 else if (strcmp (name
, "nomdmx") == 0)
12749 mips_opts
.ase_mdmx
= 0;
12750 else if (strcmp (name
, "dsp") == 0)
12752 if (!ISA_SUPPORTS_DSP_ASE
)
12753 as_warn ("%s ISA does not support DSP ASE",
12754 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12755 mips_opts
.ase_dsp
= 1;
12756 mips_opts
.ase_dspr2
= 0;
12758 else if (strcmp (name
, "nodsp") == 0)
12760 mips_opts
.ase_dsp
= 0;
12761 mips_opts
.ase_dspr2
= 0;
12763 else if (strcmp (name
, "dspr2") == 0)
12765 if (!ISA_SUPPORTS_DSPR2_ASE
)
12766 as_warn ("%s ISA does not support DSP R2 ASE",
12767 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12768 mips_opts
.ase_dspr2
= 1;
12769 mips_opts
.ase_dsp
= 1;
12771 else if (strcmp (name
, "nodspr2") == 0)
12773 mips_opts
.ase_dspr2
= 0;
12774 mips_opts
.ase_dsp
= 0;
12776 else if (strcmp (name
, "mt") == 0)
12778 if (!ISA_SUPPORTS_MT_ASE
)
12779 as_warn ("%s ISA does not support MT ASE",
12780 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12781 mips_opts
.ase_mt
= 1;
12783 else if (strcmp (name
, "nomt") == 0)
12784 mips_opts
.ase_mt
= 0;
12785 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12789 /* Permit the user to change the ISA and architecture on the fly.
12790 Needless to say, misuse can cause serious problems. */
12791 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12794 mips_opts
.isa
= file_mips_isa
;
12795 mips_opts
.arch
= file_mips_arch
;
12797 else if (strncmp (name
, "arch=", 5) == 0)
12799 const struct mips_cpu_info
*p
;
12801 p
= mips_parse_cpu("internal use", name
+ 5);
12803 as_bad (_("unknown architecture %s"), name
+ 5);
12806 mips_opts
.arch
= p
->cpu
;
12807 mips_opts
.isa
= p
->isa
;
12810 else if (strncmp (name
, "mips", 4) == 0)
12812 const struct mips_cpu_info
*p
;
12814 p
= mips_parse_cpu("internal use", name
);
12816 as_bad (_("unknown ISA level %s"), name
+ 4);
12819 mips_opts
.arch
= p
->cpu
;
12820 mips_opts
.isa
= p
->isa
;
12824 as_bad (_("unknown ISA or architecture %s"), name
);
12826 switch (mips_opts
.isa
)
12834 mips_opts
.gp32
= 1;
12835 mips_opts
.fp32
= 1;
12842 mips_opts
.gp32
= 0;
12843 mips_opts
.fp32
= 0;
12846 as_bad (_("unknown ISA level %s"), name
+ 4);
12851 mips_opts
.gp32
= file_mips_gp32
;
12852 mips_opts
.fp32
= file_mips_fp32
;
12855 else if (strcmp (name
, "autoextend") == 0)
12856 mips_opts
.noautoextend
= 0;
12857 else if (strcmp (name
, "noautoextend") == 0)
12858 mips_opts
.noautoextend
= 1;
12859 else if (strcmp (name
, "push") == 0)
12861 struct mips_option_stack
*s
;
12863 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12864 s
->next
= mips_opts_stack
;
12865 s
->options
= mips_opts
;
12866 mips_opts_stack
= s
;
12868 else if (strcmp (name
, "pop") == 0)
12870 struct mips_option_stack
*s
;
12872 s
= mips_opts_stack
;
12874 as_bad (_(".set pop with no .set push"));
12877 /* If we're changing the reorder mode we need to handle
12878 delay slots correctly. */
12879 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12880 start_noreorder ();
12881 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12884 mips_opts
= s
->options
;
12885 mips_opts_stack
= s
->next
;
12889 else if (strcmp (name
, "sym32") == 0)
12890 mips_opts
.sym32
= TRUE
;
12891 else if (strcmp (name
, "nosym32") == 0)
12892 mips_opts
.sym32
= FALSE
;
12893 else if (strchr (name
, ','))
12895 /* Generic ".set" directive; use the generic handler. */
12896 *input_line_pointer
= ch
;
12897 input_line_pointer
= name
;
12903 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12905 *input_line_pointer
= ch
;
12906 demand_empty_rest_of_line ();
12909 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12910 .option pic2. It means to generate SVR4 PIC calls. */
12913 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12915 mips_pic
= SVR4_PIC
;
12916 mips_abicalls
= TRUE
;
12918 if (g_switch_seen
&& g_switch_value
!= 0)
12919 as_warn (_("-G may not be used with SVR4 PIC code"));
12920 g_switch_value
= 0;
12922 bfd_set_gp_size (stdoutput
, 0);
12923 demand_empty_rest_of_line ();
12926 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12927 PIC code. It sets the $gp register for the function based on the
12928 function address, which is in the register named in the argument.
12929 This uses a relocation against _gp_disp, which is handled specially
12930 by the linker. The result is:
12931 lui $gp,%hi(_gp_disp)
12932 addiu $gp,$gp,%lo(_gp_disp)
12933 addu $gp,$gp,.cpload argument
12934 The .cpload argument is normally $25 == $t9.
12936 The -mno-shared option changes this to:
12937 lui $gp,%hi(__gnu_local_gp)
12938 addiu $gp,$gp,%lo(__gnu_local_gp)
12939 and the argument is ignored. This saves an instruction, but the
12940 resulting code is not position independent; it uses an absolute
12941 address for __gnu_local_gp. Thus code assembled with -mno-shared
12942 can go into an ordinary executable, but not into a shared library. */
12945 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12951 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12952 .cpload is ignored. */
12953 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12959 /* .cpload should be in a .set noreorder section. */
12960 if (mips_opts
.noreorder
== 0)
12961 as_warn (_(".cpload not in noreorder section"));
12963 reg
= tc_get_register (0);
12965 /* If we need to produce a 64-bit address, we are better off using
12966 the default instruction sequence. */
12967 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12969 ex
.X_op
= O_symbol
;
12970 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12972 ex
.X_op_symbol
= NULL
;
12973 ex
.X_add_number
= 0;
12975 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12976 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12979 macro_build_lui (&ex
, mips_gp_register
);
12980 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12981 mips_gp_register
, BFD_RELOC_LO16
);
12983 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12984 mips_gp_register
, reg
);
12987 demand_empty_rest_of_line ();
12990 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12991 .cpsetup $reg1, offset|$reg2, label
12993 If offset is given, this results in:
12994 sd $gp, offset($sp)
12995 lui $gp, %hi(%neg(%gp_rel(label)))
12996 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12997 daddu $gp, $gp, $reg1
12999 If $reg2 is given, this results in:
13000 daddu $reg2, $gp, $0
13001 lui $gp, %hi(%neg(%gp_rel(label)))
13002 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13003 daddu $gp, $gp, $reg1
13004 $reg1 is normally $25 == $t9.
13006 The -mno-shared option replaces the last three instructions with
13008 addiu $gp,$gp,%lo(_gp) */
13011 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13013 expressionS ex_off
;
13014 expressionS ex_sym
;
13017 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13018 We also need NewABI support. */
13019 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13025 reg1
= tc_get_register (0);
13026 SKIP_WHITESPACE ();
13027 if (*input_line_pointer
!= ',')
13029 as_bad (_("missing argument separator ',' for .cpsetup"));
13033 ++input_line_pointer
;
13034 SKIP_WHITESPACE ();
13035 if (*input_line_pointer
== '$')
13037 mips_cpreturn_register
= tc_get_register (0);
13038 mips_cpreturn_offset
= -1;
13042 mips_cpreturn_offset
= get_absolute_expression ();
13043 mips_cpreturn_register
= -1;
13045 SKIP_WHITESPACE ();
13046 if (*input_line_pointer
!= ',')
13048 as_bad (_("missing argument separator ',' for .cpsetup"));
13052 ++input_line_pointer
;
13053 SKIP_WHITESPACE ();
13054 expression (&ex_sym
);
13057 if (mips_cpreturn_register
== -1)
13059 ex_off
.X_op
= O_constant
;
13060 ex_off
.X_add_symbol
= NULL
;
13061 ex_off
.X_op_symbol
= NULL
;
13062 ex_off
.X_add_number
= mips_cpreturn_offset
;
13064 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13065 BFD_RELOC_LO16
, SP
);
13068 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13069 mips_gp_register
, 0);
13071 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13073 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13074 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13077 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13078 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13079 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13081 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13082 mips_gp_register
, reg1
);
13088 ex
.X_op
= O_symbol
;
13089 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13090 ex
.X_op_symbol
= NULL
;
13091 ex
.X_add_number
= 0;
13093 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13094 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13096 macro_build_lui (&ex
, mips_gp_register
);
13097 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13098 mips_gp_register
, BFD_RELOC_LO16
);
13103 demand_empty_rest_of_line ();
13107 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13109 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13110 .cplocal is ignored. */
13111 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13117 mips_gp_register
= tc_get_register (0);
13118 demand_empty_rest_of_line ();
13121 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13122 offset from $sp. The offset is remembered, and after making a PIC
13123 call $gp is restored from that location. */
13126 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13130 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13131 .cprestore is ignored. */
13132 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13138 mips_cprestore_offset
= get_absolute_expression ();
13139 mips_cprestore_valid
= 1;
13141 ex
.X_op
= O_constant
;
13142 ex
.X_add_symbol
= NULL
;
13143 ex
.X_op_symbol
= NULL
;
13144 ex
.X_add_number
= mips_cprestore_offset
;
13147 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13148 SP
, HAVE_64BIT_ADDRESSES
);
13151 demand_empty_rest_of_line ();
13154 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13155 was given in the preceding .cpsetup, it results in:
13156 ld $gp, offset($sp)
13158 If a register $reg2 was given there, it results in:
13159 daddu $gp, $reg2, $0 */
13162 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13166 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13167 We also need NewABI support. */
13168 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13175 if (mips_cpreturn_register
== -1)
13177 ex
.X_op
= O_constant
;
13178 ex
.X_add_symbol
= NULL
;
13179 ex
.X_op_symbol
= NULL
;
13180 ex
.X_add_number
= mips_cpreturn_offset
;
13182 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13185 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13186 mips_cpreturn_register
, 0);
13189 demand_empty_rest_of_line ();
13192 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13193 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13194 use in DWARF debug information. */
13197 s_dtprel_internal (size_t bytes
)
13204 if (ex
.X_op
!= O_symbol
)
13206 as_bad (_("Unsupported use of %s"), (bytes
== 8
13209 ignore_rest_of_line ();
13212 p
= frag_more (bytes
);
13213 md_number_to_chars (p
, 0, bytes
);
13214 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13216 ? BFD_RELOC_MIPS_TLS_DTPREL64
13217 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13219 demand_empty_rest_of_line ();
13222 /* Handle .dtprelword. */
13225 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13227 s_dtprel_internal (4);
13230 /* Handle .dtpreldword. */
13233 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13235 s_dtprel_internal (8);
13238 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13239 code. It sets the offset to use in gp_rel relocations. */
13242 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13244 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13245 We also need NewABI support. */
13246 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13252 mips_gprel_offset
= get_absolute_expression ();
13254 demand_empty_rest_of_line ();
13257 /* Handle the .gpword pseudo-op. This is used when generating PIC
13258 code. It generates a 32 bit GP relative reloc. */
13261 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13263 segment_info_type
*si
;
13264 struct insn_label_list
*l
;
13269 /* When not generating PIC code, this is treated as .word. */
13270 if (mips_pic
!= SVR4_PIC
)
13276 si
= seg_info (now_seg
);
13277 l
= si
->label_list
;
13278 label
= l
!= NULL
? l
->label
: NULL
;
13279 mips_emit_delays ();
13281 mips_align (2, 0, label
);
13282 mips_clear_insn_labels ();
13286 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13288 as_bad (_("Unsupported use of .gpword"));
13289 ignore_rest_of_line ();
13293 md_number_to_chars (p
, 0, 4);
13294 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13295 BFD_RELOC_GPREL32
);
13297 demand_empty_rest_of_line ();
13301 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13303 segment_info_type
*si
;
13304 struct insn_label_list
*l
;
13309 /* When not generating PIC code, this is treated as .dword. */
13310 if (mips_pic
!= SVR4_PIC
)
13316 si
= seg_info (now_seg
);
13317 l
= si
->label_list
;
13318 label
= l
!= NULL
? l
->label
: NULL
;
13319 mips_emit_delays ();
13321 mips_align (3, 0, label
);
13322 mips_clear_insn_labels ();
13326 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13328 as_bad (_("Unsupported use of .gpdword"));
13329 ignore_rest_of_line ();
13333 md_number_to_chars (p
, 0, 8);
13334 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13335 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13337 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13338 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13339 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13341 demand_empty_rest_of_line ();
13344 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13345 tables in SVR4 PIC code. */
13348 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13352 /* This is ignored when not generating SVR4 PIC code. */
13353 if (mips_pic
!= SVR4_PIC
)
13359 /* Add $gp to the register named as an argument. */
13361 reg
= tc_get_register (0);
13362 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13365 demand_empty_rest_of_line ();
13368 /* Handle the .insn pseudo-op. This marks instruction labels in
13369 mips16 mode. This permits the linker to handle them specially,
13370 such as generating jalx instructions when needed. We also make
13371 them odd for the duration of the assembly, in order to generate the
13372 right sort of code. We will make them even in the adjust_symtab
13373 routine, while leaving them marked. This is convenient for the
13374 debugger and the disassembler. The linker knows to make them odd
13378 s_insn (int ignore ATTRIBUTE_UNUSED
)
13380 mips16_mark_labels ();
13382 demand_empty_rest_of_line ();
13385 /* Handle a .stabn directive. We need these in order to mark a label
13386 as being a mips16 text label correctly. Sometimes the compiler
13387 will emit a label, followed by a .stabn, and then switch sections.
13388 If the label and .stabn are in mips16 mode, then the label is
13389 really a mips16 text label. */
13392 s_mips_stab (int type
)
13395 mips16_mark_labels ();
13400 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13403 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13410 name
= input_line_pointer
;
13411 c
= get_symbol_end ();
13412 symbolP
= symbol_find_or_make (name
);
13413 S_SET_WEAK (symbolP
);
13414 *input_line_pointer
= c
;
13416 SKIP_WHITESPACE ();
13418 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13420 if (S_IS_DEFINED (symbolP
))
13422 as_bad ("ignoring attempt to redefine symbol %s",
13423 S_GET_NAME (symbolP
));
13424 ignore_rest_of_line ();
13428 if (*input_line_pointer
== ',')
13430 ++input_line_pointer
;
13431 SKIP_WHITESPACE ();
13435 if (exp
.X_op
!= O_symbol
)
13437 as_bad ("bad .weakext directive");
13438 ignore_rest_of_line ();
13441 symbol_set_value_expression (symbolP
, &exp
);
13444 demand_empty_rest_of_line ();
13447 /* Parse a register string into a number. Called from the ECOFF code
13448 to parse .frame. The argument is non-zero if this is the frame
13449 register, so that we can record it in mips_frame_reg. */
13452 tc_get_register (int frame
)
13456 SKIP_WHITESPACE ();
13457 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13461 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13462 mips_frame_reg_valid
= 1;
13463 mips_cprestore_valid
= 0;
13469 md_section_align (asection
*seg
, valueT addr
)
13471 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13475 /* We don't need to align ELF sections to the full alignment.
13476 However, Irix 5 may prefer that we align them at least to a 16
13477 byte boundary. We don't bother to align the sections if we
13478 are targeted for an embedded system. */
13479 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13485 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13488 /* Utility routine, called from above as well. If called while the
13489 input file is still being read, it's only an approximation. (For
13490 example, a symbol may later become defined which appeared to be
13491 undefined earlier.) */
13494 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13499 if (g_switch_value
> 0)
13501 const char *symname
;
13504 /* Find out whether this symbol can be referenced off the $gp
13505 register. It can be if it is smaller than the -G size or if
13506 it is in the .sdata or .sbss section. Certain symbols can
13507 not be referenced off the $gp, although it appears as though
13509 symname
= S_GET_NAME (sym
);
13510 if (symname
!= (const char *) NULL
13511 && (strcmp (symname
, "eprol") == 0
13512 || strcmp (symname
, "etext") == 0
13513 || strcmp (symname
, "_gp") == 0
13514 || strcmp (symname
, "edata") == 0
13515 || strcmp (symname
, "_fbss") == 0
13516 || strcmp (symname
, "_fdata") == 0
13517 || strcmp (symname
, "_ftext") == 0
13518 || strcmp (symname
, "end") == 0
13519 || strcmp (symname
, "_gp_disp") == 0))
13521 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13523 #ifndef NO_ECOFF_DEBUGGING
13524 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13525 && (symbol_get_obj (sym
)->ecoff_extern_size
13526 <= g_switch_value
))
13528 /* We must defer this decision until after the whole
13529 file has been read, since there might be a .extern
13530 after the first use of this symbol. */
13531 || (before_relaxing
13532 #ifndef NO_ECOFF_DEBUGGING
13533 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13535 && S_GET_VALUE (sym
) == 0)
13536 || (S_GET_VALUE (sym
) != 0
13537 && S_GET_VALUE (sym
) <= g_switch_value
)))
13541 const char *segname
;
13543 segname
= segment_name (S_GET_SEGMENT (sym
));
13544 assert (strcmp (segname
, ".lit8") != 0
13545 && strcmp (segname
, ".lit4") != 0);
13546 change
= (strcmp (segname
, ".sdata") != 0
13547 && strcmp (segname
, ".sbss") != 0
13548 && strncmp (segname
, ".sdata.", 7) != 0
13549 && strncmp (segname
, ".sbss.", 6) != 0
13550 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13551 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13556 /* We are not optimizing for the $gp register. */
13561 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13564 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13568 /* Handle the case of a symbol equated to another symbol. */
13569 while (symbol_equated_reloc_p (sym
))
13573 /* It's possible to get a loop here in a badly written program. */
13574 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13580 if (symbol_section_p (sym
))
13583 symsec
= S_GET_SEGMENT (sym
);
13585 /* This must duplicate the test in adjust_reloc_syms. */
13586 return (symsec
!= &bfd_und_section
13587 && symsec
!= &bfd_abs_section
13588 && !bfd_is_com_section (symsec
)
13589 && !s_is_linkonce (sym
, segtype
)
13591 /* A global or weak symbol is treated as external. */
13592 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13598 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13599 extended opcode. SEC is the section the frag is in. */
13602 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13605 const struct mips16_immed_operand
*op
;
13607 int mintiny
, maxtiny
;
13611 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13613 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13616 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13617 op
= mips16_immed_operands
;
13618 while (op
->type
!= type
)
13621 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13626 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13629 maxtiny
= 1 << op
->nbits
;
13634 maxtiny
= (1 << op
->nbits
) - 1;
13639 mintiny
= - (1 << (op
->nbits
- 1));
13640 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13643 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13644 val
= S_GET_VALUE (fragp
->fr_symbol
);
13645 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13651 /* We won't have the section when we are called from
13652 mips_relax_frag. However, we will always have been called
13653 from md_estimate_size_before_relax first. If this is a
13654 branch to a different section, we mark it as such. If SEC is
13655 NULL, and the frag is not marked, then it must be a branch to
13656 the same section. */
13659 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13664 /* Must have been called from md_estimate_size_before_relax. */
13667 fragp
->fr_subtype
=
13668 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13670 /* FIXME: We should support this, and let the linker
13671 catch branches and loads that are out of range. */
13672 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13673 _("unsupported PC relative reference to different section"));
13677 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13678 /* Assume non-extended on the first relaxation pass.
13679 The address we have calculated will be bogus if this is
13680 a forward branch to another frag, as the forward frag
13681 will have fr_address == 0. */
13685 /* In this case, we know for sure that the symbol fragment is in
13686 the same section. If the relax_marker of the symbol fragment
13687 differs from the relax_marker of this fragment, we have not
13688 yet adjusted the symbol fragment fr_address. We want to add
13689 in STRETCH in order to get a better estimate of the address.
13690 This particularly matters because of the shift bits. */
13692 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13696 /* Adjust stretch for any alignment frag. Note that if have
13697 been expanding the earlier code, the symbol may be
13698 defined in what appears to be an earlier frag. FIXME:
13699 This doesn't handle the fr_subtype field, which specifies
13700 a maximum number of bytes to skip when doing an
13702 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13704 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13707 stretch
= - ((- stretch
)
13708 & ~ ((1 << (int) f
->fr_offset
) - 1));
13710 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13719 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13721 /* The base address rules are complicated. The base address of
13722 a branch is the following instruction. The base address of a
13723 PC relative load or add is the instruction itself, but if it
13724 is in a delay slot (in which case it can not be extended) use
13725 the address of the instruction whose delay slot it is in. */
13726 if (type
== 'p' || type
== 'q')
13730 /* If we are currently assuming that this frag should be
13731 extended, then, the current address is two bytes
13733 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13736 /* Ignore the low bit in the target, since it will be set
13737 for a text label. */
13738 if ((val
& 1) != 0)
13741 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13743 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13746 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13748 /* Branch offsets have an implicit 0 in the lowest bit. */
13749 if (type
== 'p' || type
== 'q')
13752 /* If any of the shifted bits are set, we must use an extended
13753 opcode. If the address depends on the size of this
13754 instruction, this can lead to a loop, so we arrange to always
13755 use an extended opcode. We only check this when we are in
13756 the main relaxation loop, when SEC is NULL. */
13757 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13759 fragp
->fr_subtype
=
13760 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13764 /* If we are about to mark a frag as extended because the value
13765 is precisely maxtiny + 1, then there is a chance of an
13766 infinite loop as in the following code:
13771 In this case when the la is extended, foo is 0x3fc bytes
13772 away, so the la can be shrunk, but then foo is 0x400 away, so
13773 the la must be extended. To avoid this loop, we mark the
13774 frag as extended if it was small, and is about to become
13775 extended with a value of maxtiny + 1. */
13776 if (val
== ((maxtiny
+ 1) << op
->shift
)
13777 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13780 fragp
->fr_subtype
=
13781 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13785 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13786 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13788 if ((val
& ((1 << op
->shift
) - 1)) != 0
13789 || val
< (mintiny
<< op
->shift
)
13790 || val
> (maxtiny
<< op
->shift
))
13796 /* Compute the length of a branch sequence, and adjust the
13797 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13798 worst-case length is computed, with UPDATE being used to indicate
13799 whether an unconditional (-1), branch-likely (+1) or regular (0)
13800 branch is to be computed. */
13802 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13804 bfd_boolean toofar
;
13808 && S_IS_DEFINED (fragp
->fr_symbol
)
13809 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13814 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13816 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13820 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13823 /* If the symbol is not defined or it's in a different segment,
13824 assume the user knows what's going on and emit a short
13830 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13832 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13833 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13834 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13840 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13843 if (mips_pic
!= NO_PIC
)
13845 /* Additional space for PIC loading of target address. */
13847 if (mips_opts
.isa
== ISA_MIPS1
)
13848 /* Additional space for $at-stabilizing nop. */
13852 /* If branch is conditional. */
13853 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13860 /* Estimate the size of a frag before relaxing. Unless this is the
13861 mips16, we are not really relaxing here, and the final size is
13862 encoded in the subtype information. For the mips16, we have to
13863 decide whether we are using an extended opcode or not. */
13866 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13870 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13873 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13875 return fragp
->fr_var
;
13878 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13879 /* We don't want to modify the EXTENDED bit here; it might get us
13880 into infinite loops. We change it only in mips_relax_frag(). */
13881 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13883 if (mips_pic
== NO_PIC
)
13884 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13885 else if (mips_pic
== SVR4_PIC
)
13886 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13887 else if (mips_pic
== VXWORKS_PIC
)
13888 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13895 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13896 return -RELAX_FIRST (fragp
->fr_subtype
);
13899 return -RELAX_SECOND (fragp
->fr_subtype
);
13902 /* This is called to see whether a reloc against a defined symbol
13903 should be converted into a reloc against a section. */
13906 mips_fix_adjustable (fixS
*fixp
)
13908 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13909 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13912 if (fixp
->fx_addsy
== NULL
)
13915 /* If symbol SYM is in a mergeable section, relocations of the form
13916 SYM + 0 can usually be made section-relative. The mergeable data
13917 is then identified by the section offset rather than by the symbol.
13919 However, if we're generating REL LO16 relocations, the offset is split
13920 between the LO16 and parterning high part relocation. The linker will
13921 need to recalculate the complete offset in order to correctly identify
13924 The linker has traditionally not looked for the parterning high part
13925 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13926 placed anywhere. Rather than break backwards compatibility by changing
13927 this, it seems better not to force the issue, and instead keep the
13928 original symbol. This will work with either linker behavior. */
13929 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13930 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13931 || reloc_needs_lo_p (fixp
->fx_r_type
))
13932 && HAVE_IN_PLACE_ADDENDS
13933 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13937 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
13938 to a floating-point stub. The same is true for non-R_MIPS16_26
13939 relocations against MIPS16 functions; in this case, the stub becomes
13940 the function's canonical address.
13942 Floating-point stubs are stored in unique .mips16.call.* or
13943 .mips16.fn.* sections. If a stub T for function F is in section S,
13944 the first relocation in section S must be against F; this is how the
13945 linker determines the target function. All relocations that might
13946 resolve to T must also be against F. We therefore have the following
13947 restrictions, which are given in an intentionally-redundant way:
13949 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
13952 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
13953 if that stub might be used.
13955 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
13958 4. We cannot reduce a stub's relocations against MIPS16 symbols if
13959 that stub might be used.
13961 There is a further restriction:
13963 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
13964 on targets with in-place addends; the relocation field cannot
13965 encode the low bit.
13967 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
13968 against a MIPS16 symbol.
13970 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
13971 relocation against some symbol R, no relocation against R may be
13972 reduced. (Note that this deals with (2) as well as (1) because
13973 relocations against global symbols will never be reduced on ELF
13974 targets.) This approach is a little simpler than trying to detect
13975 stub sections, and gives the "all or nothing" per-symbol consistency
13976 that we have for MIPS16 symbols. */
13978 && fixp
->fx_subsy
== NULL
13979 && (S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13980 || *symbol_get_tc (fixp
->fx_addsy
)))
13987 /* Translate internal representation of relocation info to BFD target
13991 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13993 static arelent
*retval
[4];
13995 bfd_reloc_code_real_type code
;
13997 memset (retval
, 0, sizeof(retval
));
13998 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13999 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14000 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14001 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14003 if (fixp
->fx_pcrel
)
14005 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14007 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14008 Relocations want only the symbol offset. */
14009 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14012 /* A gruesome hack which is a result of the gruesome gas
14013 reloc handling. What's worse, for COFF (as opposed to
14014 ECOFF), we might need yet another copy of reloc->address.
14015 See bfd_install_relocation. */
14016 reloc
->addend
+= reloc
->address
;
14020 reloc
->addend
= fixp
->fx_addnumber
;
14022 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14023 entry to be used in the relocation's section offset. */
14024 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14026 reloc
->address
= reloc
->addend
;
14030 code
= fixp
->fx_r_type
;
14032 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14033 if (reloc
->howto
== NULL
)
14035 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14036 _("Can not represent %s relocation in this object file format"),
14037 bfd_get_reloc_code_name (code
));
14044 /* Relax a machine dependent frag. This returns the amount by which
14045 the current size of the frag should change. */
14048 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14050 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14052 offsetT old_var
= fragp
->fr_var
;
14054 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14056 return fragp
->fr_var
- old_var
;
14059 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14062 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14064 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14066 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14071 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14073 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14080 /* Convert a machine dependent frag. */
14083 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14085 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14088 unsigned long insn
;
14092 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14094 if (target_big_endian
)
14095 insn
= bfd_getb32 (buf
);
14097 insn
= bfd_getl32 (buf
);
14099 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14101 /* We generate a fixup instead of applying it right now
14102 because, if there are linker relaxations, we're going to
14103 need the relocations. */
14104 exp
.X_op
= O_symbol
;
14105 exp
.X_add_symbol
= fragp
->fr_symbol
;
14106 exp
.X_add_number
= fragp
->fr_offset
;
14108 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14109 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14110 fixp
->fx_file
= fragp
->fr_file
;
14111 fixp
->fx_line
= fragp
->fr_line
;
14113 md_number_to_chars ((char *) buf
, insn
, 4);
14120 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14121 _("relaxed out-of-range branch into a jump"));
14123 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14126 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14128 /* Reverse the branch. */
14129 switch ((insn
>> 28) & 0xf)
14132 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14133 have the condition reversed by tweaking a single
14134 bit, and their opcodes all have 0x4???????. */
14135 assert ((insn
& 0xf1000000) == 0x41000000);
14136 insn
^= 0x00010000;
14140 /* bltz 0x04000000 bgez 0x04010000
14141 bltzal 0x04100000 bgezal 0x04110000 */
14142 assert ((insn
& 0xfc0e0000) == 0x04000000);
14143 insn
^= 0x00010000;
14147 /* beq 0x10000000 bne 0x14000000
14148 blez 0x18000000 bgtz 0x1c000000 */
14149 insn
^= 0x04000000;
14157 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14159 /* Clear the and-link bit. */
14160 assert ((insn
& 0xfc1c0000) == 0x04100000);
14162 /* bltzal 0x04100000 bgezal 0x04110000
14163 bltzall 0x04120000 bgezall 0x04130000 */
14164 insn
&= ~0x00100000;
14167 /* Branch over the branch (if the branch was likely) or the
14168 full jump (not likely case). Compute the offset from the
14169 current instruction to branch to. */
14170 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14174 /* How many bytes in instructions we've already emitted? */
14175 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14176 /* How many bytes in instructions from here to the end? */
14177 i
= fragp
->fr_var
- i
;
14179 /* Convert to instruction count. */
14181 /* Branch counts from the next instruction. */
14184 /* Branch over the jump. */
14185 md_number_to_chars ((char *) buf
, insn
, 4);
14189 md_number_to_chars ((char *) buf
, 0, 4);
14192 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14194 /* beql $0, $0, 2f */
14196 /* Compute the PC offset from the current instruction to
14197 the end of the variable frag. */
14198 /* How many bytes in instructions we've already emitted? */
14199 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14200 /* How many bytes in instructions from here to the end? */
14201 i
= fragp
->fr_var
- i
;
14202 /* Convert to instruction count. */
14204 /* Don't decrement i, because we want to branch over the
14208 md_number_to_chars ((char *) buf
, insn
, 4);
14211 md_number_to_chars ((char *) buf
, 0, 4);
14216 if (mips_pic
== NO_PIC
)
14219 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14220 ? 0x0c000000 : 0x08000000);
14221 exp
.X_op
= O_symbol
;
14222 exp
.X_add_symbol
= fragp
->fr_symbol
;
14223 exp
.X_add_number
= fragp
->fr_offset
;
14225 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14226 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14227 fixp
->fx_file
= fragp
->fr_file
;
14228 fixp
->fx_line
= fragp
->fr_line
;
14230 md_number_to_chars ((char *) buf
, insn
, 4);
14235 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14236 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14237 exp
.X_op
= O_symbol
;
14238 exp
.X_add_symbol
= fragp
->fr_symbol
;
14239 exp
.X_add_number
= fragp
->fr_offset
;
14241 if (fragp
->fr_offset
)
14243 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14244 exp
.X_add_number
= 0;
14247 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14248 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14249 fixp
->fx_file
= fragp
->fr_file
;
14250 fixp
->fx_line
= fragp
->fr_line
;
14252 md_number_to_chars ((char *) buf
, insn
, 4);
14255 if (mips_opts
.isa
== ISA_MIPS1
)
14258 md_number_to_chars ((char *) buf
, 0, 4);
14262 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14263 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14265 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14266 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14267 fixp
->fx_file
= fragp
->fr_file
;
14268 fixp
->fx_line
= fragp
->fr_line
;
14270 md_number_to_chars ((char *) buf
, insn
, 4);
14274 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14279 md_number_to_chars ((char *) buf
, insn
, 4);
14284 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14285 + fragp
->fr_fix
+ fragp
->fr_var
);
14287 fragp
->fr_fix
+= fragp
->fr_var
;
14292 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14295 const struct mips16_immed_operand
*op
;
14296 bfd_boolean small
, ext
;
14299 unsigned long insn
;
14300 bfd_boolean use_extend
;
14301 unsigned short extend
;
14303 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14304 op
= mips16_immed_operands
;
14305 while (op
->type
!= type
)
14308 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14319 resolve_symbol_value (fragp
->fr_symbol
);
14320 val
= S_GET_VALUE (fragp
->fr_symbol
);
14325 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14327 /* The rules for the base address of a PC relative reloc are
14328 complicated; see mips16_extended_frag. */
14329 if (type
== 'p' || type
== 'q')
14334 /* Ignore the low bit in the target, since it will be
14335 set for a text label. */
14336 if ((val
& 1) != 0)
14339 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14341 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14344 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14347 /* Make sure the section winds up with the alignment we have
14350 record_alignment (asec
, op
->shift
);
14354 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14355 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14356 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14357 _("extended instruction in delay slot"));
14359 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14361 if (target_big_endian
)
14362 insn
= bfd_getb16 (buf
);
14364 insn
= bfd_getl16 (buf
);
14366 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14367 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14368 small
, ext
, &insn
, &use_extend
, &extend
);
14372 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14373 fragp
->fr_fix
+= 2;
14377 md_number_to_chars ((char *) buf
, insn
, 2);
14378 fragp
->fr_fix
+= 2;
14386 first
= RELAX_FIRST (fragp
->fr_subtype
);
14387 second
= RELAX_SECOND (fragp
->fr_subtype
);
14388 fixp
= (fixS
*) fragp
->fr_opcode
;
14390 /* Possibly emit a warning if we've chosen the longer option. */
14391 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14392 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14394 const char *msg
= macro_warning (fragp
->fr_subtype
);
14396 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14399 /* Go through all the fixups for the first sequence. Disable them
14400 (by marking them as done) if we're going to use the second
14401 sequence instead. */
14403 && fixp
->fx_frag
== fragp
14404 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14406 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14408 fixp
= fixp
->fx_next
;
14411 /* Go through the fixups for the second sequence. Disable them if
14412 we're going to use the first sequence, otherwise adjust their
14413 addresses to account for the relaxation. */
14414 while (fixp
&& fixp
->fx_frag
== fragp
)
14416 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14417 fixp
->fx_where
-= first
;
14420 fixp
= fixp
->fx_next
;
14423 /* Now modify the frag contents. */
14424 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14428 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14429 memmove (start
, start
+ first
, second
);
14430 fragp
->fr_fix
-= first
;
14433 fragp
->fr_fix
-= second
;
14439 /* This function is called after the relocs have been generated.
14440 We've been storing mips16 text labels as odd. Here we convert them
14441 back to even for the convenience of the debugger. */
14444 mips_frob_file_after_relocs (void)
14447 unsigned int count
, i
;
14452 syms
= bfd_get_outsymbols (stdoutput
);
14453 count
= bfd_get_symcount (stdoutput
);
14454 for (i
= 0; i
< count
; i
++, syms
++)
14456 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
14457 && ((*syms
)->value
& 1) != 0)
14459 (*syms
)->value
&= ~1;
14460 /* If the symbol has an odd size, it was probably computed
14461 incorrectly, so adjust that as well. */
14462 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14463 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14470 /* This function is called whenever a label is defined. It is used
14471 when handling branch delays; if a branch has a label, we assume we
14472 can not move it. */
14475 mips_define_label (symbolS
*sym
)
14477 segment_info_type
*si
= seg_info (now_seg
);
14478 struct insn_label_list
*l
;
14480 if (free_insn_labels
== NULL
)
14481 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14484 l
= free_insn_labels
;
14485 free_insn_labels
= l
->next
;
14489 l
->next
= si
->label_list
;
14490 si
->label_list
= l
;
14493 dwarf2_emit_label (sym
);
14497 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14499 /* Some special processing for a MIPS ELF file. */
14502 mips_elf_final_processing (void)
14504 /* Write out the register information. */
14505 if (mips_abi
!= N64_ABI
)
14509 s
.ri_gprmask
= mips_gprmask
;
14510 s
.ri_cprmask
[0] = mips_cprmask
[0];
14511 s
.ri_cprmask
[1] = mips_cprmask
[1];
14512 s
.ri_cprmask
[2] = mips_cprmask
[2];
14513 s
.ri_cprmask
[3] = mips_cprmask
[3];
14514 /* The gp_value field is set by the MIPS ELF backend. */
14516 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14517 ((Elf32_External_RegInfo
*)
14518 mips_regmask_frag
));
14522 Elf64_Internal_RegInfo s
;
14524 s
.ri_gprmask
= mips_gprmask
;
14526 s
.ri_cprmask
[0] = mips_cprmask
[0];
14527 s
.ri_cprmask
[1] = mips_cprmask
[1];
14528 s
.ri_cprmask
[2] = mips_cprmask
[2];
14529 s
.ri_cprmask
[3] = mips_cprmask
[3];
14530 /* The gp_value field is set by the MIPS ELF backend. */
14532 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14533 ((Elf64_External_RegInfo
*)
14534 mips_regmask_frag
));
14537 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14538 sort of BFD interface for this. */
14539 if (mips_any_noreorder
)
14540 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14541 if (mips_pic
!= NO_PIC
)
14543 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14544 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14547 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14549 /* Set MIPS ELF flags for ASEs. */
14550 /* We may need to define a new flag for DSP ASE, and set this flag when
14551 file_ase_dsp is true. */
14552 /* Same for DSP R2. */
14553 /* We may need to define a new flag for MT ASE, and set this flag when
14554 file_ase_mt is true. */
14555 if (file_ase_mips16
)
14556 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14557 #if 0 /* XXX FIXME */
14558 if (file_ase_mips3d
)
14559 elf_elfheader (stdoutput
)->e_flags
|= ???;
14562 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14564 /* Set the MIPS ELF ABI flags. */
14565 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14566 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14567 else if (mips_abi
== O64_ABI
)
14568 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14569 else if (mips_abi
== EABI_ABI
)
14571 if (!file_mips_gp32
)
14572 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14574 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14576 else if (mips_abi
== N32_ABI
)
14577 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14579 /* Nothing to do for N64_ABI. */
14581 if (mips_32bitmode
)
14582 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14584 #if 0 /* XXX FIXME */
14585 /* 32 bit code with 64 bit FP registers. */
14586 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14587 elf_elfheader (stdoutput
)->e_flags
|= ???;
14591 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14593 typedef struct proc
{
14595 symbolS
*func_end_sym
;
14596 unsigned long reg_mask
;
14597 unsigned long reg_offset
;
14598 unsigned long fpreg_mask
;
14599 unsigned long fpreg_offset
;
14600 unsigned long frame_offset
;
14601 unsigned long frame_reg
;
14602 unsigned long pc_reg
;
14605 static procS cur_proc
;
14606 static procS
*cur_proc_ptr
;
14607 static int numprocs
;
14609 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14613 mips_nop_opcode (void)
14615 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14618 /* Fill in an rs_align_code fragment. This only needs to do something
14619 for MIPS16 code, where 0 is not a nop. */
14622 mips_handle_align (fragS
*fragp
)
14626 if (fragp
->fr_type
!= rs_align_code
)
14629 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14634 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14640 md_number_to_chars (p
, mips16_nop_insn
.insn_opcode
, 2);
14646 md_obj_begin (void)
14653 /* Check for premature end, nesting errors, etc. */
14655 as_warn (_("missing .end at end of assembly"));
14664 if (*input_line_pointer
== '-')
14666 ++input_line_pointer
;
14669 if (!ISDIGIT (*input_line_pointer
))
14670 as_bad (_("expected simple number"));
14671 if (input_line_pointer
[0] == '0')
14673 if (input_line_pointer
[1] == 'x')
14675 input_line_pointer
+= 2;
14676 while (ISXDIGIT (*input_line_pointer
))
14679 val
|= hex_value (*input_line_pointer
++);
14681 return negative
? -val
: val
;
14685 ++input_line_pointer
;
14686 while (ISDIGIT (*input_line_pointer
))
14689 val
|= *input_line_pointer
++ - '0';
14691 return negative
? -val
: val
;
14694 if (!ISDIGIT (*input_line_pointer
))
14696 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14697 *input_line_pointer
, *input_line_pointer
);
14698 as_warn (_("invalid number"));
14701 while (ISDIGIT (*input_line_pointer
))
14704 val
+= *input_line_pointer
++ - '0';
14706 return negative
? -val
: val
;
14709 /* The .file directive; just like the usual .file directive, but there
14710 is an initial number which is the ECOFF file index. In the non-ECOFF
14711 case .file implies DWARF-2. */
14714 s_mips_file (int x ATTRIBUTE_UNUSED
)
14716 static int first_file_directive
= 0;
14718 if (ECOFF_DEBUGGING
)
14727 filename
= dwarf2_directive_file (0);
14729 /* Versions of GCC up to 3.1 start files with a ".file"
14730 directive even for stabs output. Make sure that this
14731 ".file" is handled. Note that you need a version of GCC
14732 after 3.1 in order to support DWARF-2 on MIPS. */
14733 if (filename
!= NULL
&& ! first_file_directive
)
14735 (void) new_logical_line (filename
, -1);
14736 s_app_file_string (filename
, 0);
14738 first_file_directive
= 1;
14742 /* The .loc directive, implying DWARF-2. */
14745 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14747 if (!ECOFF_DEBUGGING
)
14748 dwarf2_directive_loc (0);
14751 /* The .end directive. */
14754 s_mips_end (int x ATTRIBUTE_UNUSED
)
14758 /* Following functions need their own .frame and .cprestore directives. */
14759 mips_frame_reg_valid
= 0;
14760 mips_cprestore_valid
= 0;
14762 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14765 demand_empty_rest_of_line ();
14770 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14771 as_warn (_(".end not in text section"));
14775 as_warn (_(".end directive without a preceding .ent directive."));
14776 demand_empty_rest_of_line ();
14782 assert (S_GET_NAME (p
));
14783 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14784 as_warn (_(".end symbol does not match .ent symbol."));
14786 if (debug_type
== DEBUG_STABS
)
14787 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14791 as_warn (_(".end directive missing or unknown symbol"));
14794 /* Create an expression to calculate the size of the function. */
14795 if (p
&& cur_proc_ptr
)
14797 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14798 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14801 exp
->X_op
= O_subtract
;
14802 exp
->X_add_symbol
= symbol_temp_new_now ();
14803 exp
->X_op_symbol
= p
;
14804 exp
->X_add_number
= 0;
14806 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14809 /* Generate a .pdr section. */
14810 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14812 segT saved_seg
= now_seg
;
14813 subsegT saved_subseg
= now_subseg
;
14818 dot
= frag_now_fix ();
14820 #ifdef md_flush_pending_output
14821 md_flush_pending_output ();
14825 subseg_set (pdr_seg
, 0);
14827 /* Write the symbol. */
14828 exp
.X_op
= O_symbol
;
14829 exp
.X_add_symbol
= p
;
14830 exp
.X_add_number
= 0;
14831 emit_expr (&exp
, 4);
14833 fragp
= frag_more (7 * 4);
14835 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14836 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14837 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14838 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14839 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14840 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14841 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14843 subseg_set (saved_seg
, saved_subseg
);
14845 #endif /* OBJ_ELF */
14847 cur_proc_ptr
= NULL
;
14850 /* The .aent and .ent directives. */
14853 s_mips_ent (int aent
)
14857 symbolP
= get_symbol ();
14858 if (*input_line_pointer
== ',')
14859 ++input_line_pointer
;
14860 SKIP_WHITESPACE ();
14861 if (ISDIGIT (*input_line_pointer
)
14862 || *input_line_pointer
== '-')
14865 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14866 as_warn (_(".ent or .aent not in text section."));
14868 if (!aent
&& cur_proc_ptr
)
14869 as_warn (_("missing .end"));
14873 /* This function needs its own .frame and .cprestore directives. */
14874 mips_frame_reg_valid
= 0;
14875 mips_cprestore_valid
= 0;
14877 cur_proc_ptr
= &cur_proc
;
14878 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14880 cur_proc_ptr
->func_sym
= symbolP
;
14882 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14886 if (debug_type
== DEBUG_STABS
)
14887 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14888 S_GET_NAME (symbolP
));
14891 demand_empty_rest_of_line ();
14894 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14895 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14896 s_mips_frame is used so that we can set the PDR information correctly.
14897 We can't use the ecoff routines because they make reference to the ecoff
14898 symbol table (in the mdebug section). */
14901 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14904 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14908 if (cur_proc_ptr
== (procS
*) NULL
)
14910 as_warn (_(".frame outside of .ent"));
14911 demand_empty_rest_of_line ();
14915 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14917 SKIP_WHITESPACE ();
14918 if (*input_line_pointer
++ != ','
14919 || get_absolute_expression_and_terminator (&val
) != ',')
14921 as_warn (_("Bad .frame directive"));
14922 --input_line_pointer
;
14923 demand_empty_rest_of_line ();
14927 cur_proc_ptr
->frame_offset
= val
;
14928 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14930 demand_empty_rest_of_line ();
14933 #endif /* OBJ_ELF */
14937 /* The .fmask and .mask directives. If the mdebug section is present
14938 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14939 embedded targets, s_mips_mask is used so that we can set the PDR
14940 information correctly. We can't use the ecoff routines because they
14941 make reference to the ecoff symbol table (in the mdebug section). */
14944 s_mips_mask (int reg_type
)
14947 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14951 if (cur_proc_ptr
== (procS
*) NULL
)
14953 as_warn (_(".mask/.fmask outside of .ent"));
14954 demand_empty_rest_of_line ();
14958 if (get_absolute_expression_and_terminator (&mask
) != ',')
14960 as_warn (_("Bad .mask/.fmask directive"));
14961 --input_line_pointer
;
14962 demand_empty_rest_of_line ();
14966 off
= get_absolute_expression ();
14968 if (reg_type
== 'F')
14970 cur_proc_ptr
->fpreg_mask
= mask
;
14971 cur_proc_ptr
->fpreg_offset
= off
;
14975 cur_proc_ptr
->reg_mask
= mask
;
14976 cur_proc_ptr
->reg_offset
= off
;
14979 demand_empty_rest_of_line ();
14982 #endif /* OBJ_ELF */
14983 s_ignore (reg_type
);
14986 /* A table describing all the processors gas knows about. Names are
14987 matched in the order listed.
14989 To ease comparison, please keep this table in the same order as
14990 gcc's mips_cpu_info_table[]. */
14991 static const struct mips_cpu_info mips_cpu_info_table
[] =
14993 /* Entries for generic ISAs */
14994 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
14995 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
14996 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
14997 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
14998 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
14999 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15000 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15001 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15002 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15005 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15006 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15007 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15010 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15013 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15014 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15015 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15016 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15017 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15018 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15019 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15020 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15021 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15022 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15023 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15024 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15025 /* ST Microelectronics Loongson 2E and 2F cores */
15026 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15027 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15030 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15031 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15032 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15033 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15034 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15035 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15036 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15037 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15038 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15039 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15040 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15041 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15042 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15045 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15046 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15047 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15048 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15050 /* MIPS 32 Release 2 */
15051 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15052 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15053 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15054 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15055 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15056 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15057 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15058 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15059 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15060 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15061 /* Deprecated forms of the above. */
15062 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15063 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15064 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15065 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15066 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15067 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15068 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15069 /* Deprecated forms of the above. */
15070 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15071 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15072 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15073 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15074 ISA_MIPS32R2
, CPU_MIPS32R2
},
15075 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15076 ISA_MIPS32R2
, CPU_MIPS32R2
},
15077 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15078 ISA_MIPS32R2
, CPU_MIPS32R2
},
15079 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15080 ISA_MIPS32R2
, CPU_MIPS32R2
},
15081 /* Deprecated forms of the above. */
15082 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15083 ISA_MIPS32R2
, CPU_MIPS32R2
},
15084 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15085 ISA_MIPS32R2
, CPU_MIPS32R2
},
15086 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15087 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15088 ISA_MIPS32R2
, CPU_MIPS32R2
},
15089 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15090 ISA_MIPS32R2
, CPU_MIPS32R2
},
15091 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15092 ISA_MIPS32R2
, CPU_MIPS32R2
},
15093 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15094 ISA_MIPS32R2
, CPU_MIPS32R2
},
15095 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15096 ISA_MIPS32R2
, CPU_MIPS32R2
},
15097 /* Deprecated forms of the above. */
15098 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15099 ISA_MIPS32R2
, CPU_MIPS32R2
},
15100 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15101 ISA_MIPS32R2
, CPU_MIPS32R2
},
15104 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15105 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15106 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15107 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15109 /* MIPS 64 Release 2 */
15111 /* Broadcom SB-1 CPU core */
15112 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15113 ISA_MIPS64
, CPU_SB1
},
15114 /* Broadcom SB-1A CPU core */
15115 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15116 ISA_MIPS64
, CPU_SB1
},
15118 /* Cavium Networks Octeon CPU core */
15119 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15126 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15127 with a final "000" replaced by "k". Ignore case.
15129 Note: this function is shared between GCC and GAS. */
15132 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15134 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15135 given
++, canonical
++;
15137 return ((*given
== 0 && *canonical
== 0)
15138 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15142 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15143 CPU name. We've traditionally allowed a lot of variation here.
15145 Note: this function is shared between GCC and GAS. */
15148 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15150 /* First see if the name matches exactly, or with a final "000"
15151 turned into "k". */
15152 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15155 /* If not, try comparing based on numerical designation alone.
15156 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15157 if (TOLOWER (*given
) == 'r')
15159 if (!ISDIGIT (*given
))
15162 /* Skip over some well-known prefixes in the canonical name,
15163 hoping to find a number there too. */
15164 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15166 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15168 else if (TOLOWER (canonical
[0]) == 'r')
15171 return mips_strict_matching_cpu_name_p (canonical
, given
);
15175 /* Parse an option that takes the name of a processor as its argument.
15176 OPTION is the name of the option and CPU_STRING is the argument.
15177 Return the corresponding processor enumeration if the CPU_STRING is
15178 recognized, otherwise report an error and return null.
15180 A similar function exists in GCC. */
15182 static const struct mips_cpu_info
*
15183 mips_parse_cpu (const char *option
, const char *cpu_string
)
15185 const struct mips_cpu_info
*p
;
15187 /* 'from-abi' selects the most compatible architecture for the given
15188 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15189 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15190 version. Look first at the -mgp options, if given, otherwise base
15191 the choice on MIPS_DEFAULT_64BIT.
15193 Treat NO_ABI like the EABIs. One reason to do this is that the
15194 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15195 architecture. This code picks MIPS I for 'mips' and MIPS III for
15196 'mips64', just as we did in the days before 'from-abi'. */
15197 if (strcasecmp (cpu_string
, "from-abi") == 0)
15199 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15200 return mips_cpu_info_from_isa (ISA_MIPS1
);
15202 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15203 return mips_cpu_info_from_isa (ISA_MIPS3
);
15205 if (file_mips_gp32
>= 0)
15206 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15208 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15213 /* 'default' has traditionally been a no-op. Probably not very useful. */
15214 if (strcasecmp (cpu_string
, "default") == 0)
15217 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15218 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15221 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
15225 /* Return the canonical processor information for ISA (a member of the
15226 ISA_MIPS* enumeration). */
15228 static const struct mips_cpu_info
*
15229 mips_cpu_info_from_isa (int isa
)
15233 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15234 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15235 && isa
== mips_cpu_info_table
[i
].isa
)
15236 return (&mips_cpu_info_table
[i
]);
15241 static const struct mips_cpu_info
*
15242 mips_cpu_info_from_arch (int arch
)
15246 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15247 if (arch
== mips_cpu_info_table
[i
].cpu
)
15248 return (&mips_cpu_info_table
[i
]);
15254 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15258 fprintf (stream
, "%24s", "");
15263 fprintf (stream
, ", ");
15267 if (*col_p
+ strlen (string
) > 72)
15269 fprintf (stream
, "\n%24s", "");
15273 fprintf (stream
, "%s", string
);
15274 *col_p
+= strlen (string
);
15280 md_show_usage (FILE *stream
)
15285 fprintf (stream
, _("\
15287 -EB generate big endian output\n\
15288 -EL generate little endian output\n\
15289 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15290 -G NUM allow referencing objects up to NUM bytes\n\
15291 implicitly with the gp register [default 8]\n"));
15292 fprintf (stream
, _("\
15293 -mips1 generate MIPS ISA I instructions\n\
15294 -mips2 generate MIPS ISA II instructions\n\
15295 -mips3 generate MIPS ISA III instructions\n\
15296 -mips4 generate MIPS ISA IV instructions\n\
15297 -mips5 generate MIPS ISA V instructions\n\
15298 -mips32 generate MIPS32 ISA instructions\n\
15299 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15300 -mips64 generate MIPS64 ISA instructions\n\
15301 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15302 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15306 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15307 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15308 show (stream
, "from-abi", &column
, &first
);
15309 fputc ('\n', stream
);
15311 fprintf (stream
, _("\
15312 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15313 -no-mCPU don't generate code specific to CPU.\n\
15314 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15318 show (stream
, "3900", &column
, &first
);
15319 show (stream
, "4010", &column
, &first
);
15320 show (stream
, "4100", &column
, &first
);
15321 show (stream
, "4650", &column
, &first
);
15322 fputc ('\n', stream
);
15324 fprintf (stream
, _("\
15325 -mips16 generate mips16 instructions\n\
15326 -no-mips16 do not generate mips16 instructions\n"));
15327 fprintf (stream
, _("\
15328 -msmartmips generate smartmips instructions\n\
15329 -mno-smartmips do not generate smartmips instructions\n"));
15330 fprintf (stream
, _("\
15331 -mdsp generate DSP instructions\n\
15332 -mno-dsp do not generate DSP instructions\n"));
15333 fprintf (stream
, _("\
15334 -mdspr2 generate DSP R2 instructions\n\
15335 -mno-dspr2 do not generate DSP R2 instructions\n"));
15336 fprintf (stream
, _("\
15337 -mmt generate MT instructions\n\
15338 -mno-mt do not generate MT instructions\n"));
15339 fprintf (stream
, _("\
15340 -mfix-vr4120 work around certain VR4120 errata\n\
15341 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15342 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15343 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15344 -msym32 assume all symbols have 32-bit values\n\
15345 -O0 remove unneeded NOPs, do not swap branches\n\
15346 -O remove unneeded NOPs and swap branches\n\
15347 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15348 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15349 fprintf (stream
, _("\
15350 -mhard-float allow floating-point instructions\n\
15351 -msoft-float do not allow floating-point instructions\n\
15352 -msingle-float only allow 32-bit floating-point operations\n\
15353 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15354 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15357 fprintf (stream
, _("\
15358 -KPIC, -call_shared generate SVR4 position independent code\n\
15359 -mvxworks-pic generate VxWorks position independent code\n\
15360 -non_shared do not generate position independent code\n\
15361 -xgot assume a 32 bit GOT\n\
15362 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15363 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15364 position dependent (non shared) code\n\
15365 -mabi=ABI create ABI conformant object file for:\n"));
15369 show (stream
, "32", &column
, &first
);
15370 show (stream
, "o64", &column
, &first
);
15371 show (stream
, "n32", &column
, &first
);
15372 show (stream
, "64", &column
, &first
);
15373 show (stream
, "eabi", &column
, &first
);
15375 fputc ('\n', stream
);
15377 fprintf (stream
, _("\
15378 -32 create o32 ABI object file (default)\n\
15379 -n32 create n32 ABI object file\n\
15380 -64 create 64 ABI object file\n"));
15385 mips_dwarf2_format (void)
15387 if (HAVE_64BIT_SYMBOLS
)
15390 return dwarf2_format_64bit_irix
;
15392 return dwarf2_format_64bit
;
15396 return dwarf2_format_32bit
;
15400 mips_dwarf2_addr_size (void)
15402 if (HAVE_64BIT_SYMBOLS
)
15408 /* Standard calling conventions leave the CFA at SP on entry. */
15410 mips_cfi_frame_initial_instructions (void)
15412 cfi_add_CFA_def_cfa_register (SP
);
15416 tc_mips_regname_to_dw2regnum (char *regname
)
15418 unsigned int regnum
= -1;
15421 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))