1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* Whether or not we have code which can be put into a shared
141 static bfd_boolean mips_in_shared
= TRUE
;
143 /* This is the set of options which may be modified by the .set
144 pseudo-op. We use a struct so that .set push and .set pop are more
147 struct mips_set_options
149 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
150 if it has not been initialized. Changed by `.set mipsN', and the
151 -mipsN command line option, and the default CPU. */
153 /* Enabled Application Specific Extensions (ASEs). These are set to -1
154 if they have not been initialized. Changed by `.set <asename>', by
155 command line options, and based on the default architecture. */
158 /* Whether we are assembling for the mips16 processor. 0 if we are
159 not, 1 if we are, and -1 if the value has not been initialized.
160 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
161 -nomips16 command line options, and the default CPU. */
163 /* Non-zero if we should not reorder instructions. Changed by `.set
164 reorder' and `.set noreorder'. */
166 /* Non-zero if we should not permit the $at ($1) register to be used
167 in instructions. Changed by `.set at' and `.set noat'. */
169 /* Non-zero if we should warn when a macro instruction expands into
170 more than one machine instruction. Changed by `.set nomacro' and
172 int warn_about_macros
;
173 /* Non-zero if we should not move instructions. Changed by `.set
174 move', `.set volatile', `.set nomove', and `.set novolatile'. */
176 /* Non-zero if we should not optimize branches by moving the target
177 of the branch into the delay slot. Actually, we don't perform
178 this optimization anyhow. Changed by `.set bopt' and `.set
181 /* Non-zero if we should not autoextend mips16 instructions.
182 Changed by `.set autoextend' and `.set noautoextend'. */
184 /* Restrict general purpose registers and floating point registers
185 to 32 bit. This is initially determined when -mgp32 or -mfp32
186 is passed but can changed if the assembler code uses .set mipsN. */
189 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
190 command line option, and the default CPU. */
194 /* True if -mgp32 was passed. */
195 static int file_mips_gp32
= -1;
197 /* True if -mfp32 was passed. */
198 static int file_mips_fp32
= -1;
200 /* This is the struct we use to hold the current set of options. Note
201 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
202 -1 to indicate that they have not been initialized. */
204 static struct mips_set_options mips_opts
=
206 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
209 /* These variables are filled in with the masks of registers used.
210 The object format code reads them and puts them in the appropriate
212 unsigned long mips_gprmask
;
213 unsigned long mips_cprmask
[4];
215 /* MIPS ISA we are using for this output file. */
216 static int file_mips_isa
= ISA_UNKNOWN
;
218 /* True if -mips16 was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips16
;
222 /* True if -mips3d was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mips3d
;
226 /* True if -mdmx was passed or implied by arguments passed on the
227 command line (e.g., by -march). */
228 static int file_ase_mdmx
;
230 /* The argument of the -march= flag. The architecture we are assembling. */
231 static int file_mips_arch
= CPU_UNKNOWN
;
232 static const char *mips_arch_string
;
234 /* The argument of the -mtune= flag. The architecture for which we
236 static int mips_tune
= CPU_UNKNOWN
;
237 static const char *mips_tune_string
;
239 /* True when generating 32-bit code for a 64-bit processor. */
240 static int mips_32bitmode
= 0;
242 /* True if the given ABI requires 32-bit registers. */
243 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
245 /* Likewise 64-bit registers. */
246 #define ABI_NEEDS_64BIT_REGS(ABI) \
248 || (ABI) == N64_ABI \
251 /* Return true if ISA supports 64 bit gp register instructions. */
252 #define ISA_HAS_64BIT_REGS(ISA) ( \
254 || (ISA) == ISA_MIPS4 \
255 || (ISA) == ISA_MIPS5 \
256 || (ISA) == ISA_MIPS64 \
257 || (ISA) == ISA_MIPS64R2 \
260 /* Return true if ISA supports 64-bit right rotate (dror et al.)
262 #define ISA_HAS_DROR(ISA) ( \
263 (ISA) == ISA_MIPS64R2 \
266 /* Return true if ISA supports 32-bit right rotate (ror et al.)
268 #define ISA_HAS_ROR(ISA) ( \
269 (ISA) == ISA_MIPS32R2 \
270 || (ISA) == ISA_MIPS64R2 \
273 #define HAVE_32BIT_GPRS \
274 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
276 #define HAVE_32BIT_FPRS \
277 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
279 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
280 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
282 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
284 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
286 /* True if relocations are stored in-place. */
287 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
289 /* We can only have 64bit addresses if the object file format supports it. */
290 #define HAVE_32BIT_ADDRESSES \
292 || (bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS)) \
295 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
297 /* Addresses are loaded in different ways, depending on the address size
298 in use. The n32 ABI Documentation also mandates the use of additions
299 with overflow checking, but existing implementations don't follow it. */
300 #define ADDRESS_ADD_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
303 #define ADDRESS_ADDI_INSN \
304 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
306 #define ADDRESS_LOAD_INSN \
307 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
309 #define ADDRESS_STORE_INSN \
310 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
312 /* Return true if the given CPU supports the MIPS16 ASE. */
313 #define CPU_HAS_MIPS16(cpu) \
314 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
315 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
317 /* Return true if the given CPU supports the MIPS3D ASE. */
318 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
321 /* Return true if the given CPU supports the MDMX ASE. */
322 #define CPU_HAS_MDMX(cpu) (FALSE \
325 /* True if CPU has a dror instruction. */
326 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
328 /* True if CPU has a ror instruction. */
329 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
331 /* True if mflo and mfhi can be immediately followed by instructions
332 which write to the HI and LO registers.
334 According to MIPS specifications, MIPS ISAs I, II, and III need
335 (at least) two instructions between the reads of HI/LO and
336 instructions which write them, and later ISAs do not. Contradicting
337 the MIPS specifications, some MIPS IV processor user manuals (e.g.
338 the UM for the NEC Vr5000) document needing the instructions between
339 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
340 MIPS64 and later ISAs to have the interlocks, plus any specific
341 earlier-ISA CPUs for which CPU documentation declares that the
342 instructions are really interlocked. */
343 #define hilo_interlocks \
344 (mips_opts.isa == ISA_MIPS32 \
345 || mips_opts.isa == ISA_MIPS32R2 \
346 || mips_opts.isa == ISA_MIPS64 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.arch == CPU_R4010 \
349 || mips_opts.arch == CPU_R10000 \
350 || mips_opts.arch == CPU_R12000 \
351 || mips_opts.arch == CPU_RM7000 \
352 || mips_opts.arch == CPU_VR5500 \
355 /* Whether the processor uses hardware interlocks to protect reads
356 from the GPRs after they are loaded from memory, and thus does not
357 require nops to be inserted. This applies to instructions marked
358 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
360 #define gpr_interlocks \
361 (mips_opts.isa != ISA_MIPS1 \
362 || mips_opts.arch == CPU_R3900)
364 /* Whether the processor uses hardware interlocks to avoid delays
365 required by coprocessor instructions, and thus does not require
366 nops to be inserted. This applies to instructions marked
367 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
368 between instructions marked INSN_WRITE_COND_CODE and ones marked
369 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
370 levels I, II, and III. */
371 /* Itbl support may require additional care here. */
372 #define cop_interlocks \
373 ((mips_opts.isa != ISA_MIPS1 \
374 && mips_opts.isa != ISA_MIPS2 \
375 && mips_opts.isa != ISA_MIPS3) \
376 || mips_opts.arch == CPU_R4300 \
379 /* Whether the processor uses hardware interlocks to protect reads
380 from coprocessor registers after they are loaded from memory, and
381 thus does not require nops to be inserted. This applies to
382 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
383 requires at MIPS ISA level I. */
384 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
386 /* Is this a mfhi or mflo instruction? */
387 #define MF_HILO_INSN(PINFO) \
388 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
390 /* MIPS PIC level. */
392 enum mips_pic_level mips_pic
;
394 /* 1 if we should generate 32 bit offsets from the $gp register in
395 SVR4_PIC mode. Currently has no meaning in other modes. */
396 static int mips_big_got
= 0;
398 /* 1 if trap instructions should used for overflow rather than break
400 static int mips_trap
= 0;
402 /* 1 if double width floating point constants should not be constructed
403 by assembling two single width halves into two single width floating
404 point registers which just happen to alias the double width destination
405 register. On some architectures this aliasing can be disabled by a bit
406 in the status register, and the setting of this bit cannot be determined
407 automatically at assemble time. */
408 static int mips_disable_float_construction
;
410 /* Non-zero if any .set noreorder directives were used. */
412 static int mips_any_noreorder
;
414 /* Non-zero if nops should be inserted when the register referenced in
415 an mfhi/mflo instruction is read in the next two instructions. */
416 static int mips_7000_hilo_fix
;
418 /* The size of the small data section. */
419 static unsigned int g_switch_value
= 8;
420 /* Whether the -G option was used. */
421 static int g_switch_seen
= 0;
426 /* If we can determine in advance that GP optimization won't be
427 possible, we can skip the relaxation stuff that tries to produce
428 GP-relative references. This makes delay slot optimization work
431 This function can only provide a guess, but it seems to work for
432 gcc output. It needs to guess right for gcc, otherwise gcc
433 will put what it thinks is a GP-relative instruction in a branch
436 I don't know if a fix is needed for the SVR4_PIC mode. I've only
437 fixed it for the non-PIC mode. KR 95/04/07 */
438 static int nopic_need_relax (symbolS
*, int);
440 /* handle of the OPCODE hash table */
441 static struct hash_control
*op_hash
= NULL
;
443 /* The opcode hash table we use for the mips16. */
444 static struct hash_control
*mips16_op_hash
= NULL
;
446 /* This array holds the chars that always start a comment. If the
447 pre-processor is disabled, these aren't very useful */
448 const char comment_chars
[] = "#";
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output */
453 /* Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output. */
456 /* Also note that C style comments are always supported. */
457 const char line_comment_chars
[] = "#";
459 /* This array holds machine specific line separator characters. */
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point nums */
463 const char EXP_CHARS
[] = "eE";
465 /* Chars that mean this number is a floating point constant */
468 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
470 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
471 changed in read.c . Ideally it shouldn't have to know about it at all,
472 but nothing is ideal around here.
475 static char *insn_error
;
477 static int auto_align
= 1;
479 /* When outputting SVR4 PIC code, the assembler needs to know the
480 offset in the stack frame from which to restore the $gp register.
481 This is set by the .cprestore pseudo-op, and saved in this
483 static offsetT mips_cprestore_offset
= -1;
485 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
486 more optimizations, it can use a register value instead of a memory-saved
487 offset and even an other register than $gp as global pointer. */
488 static offsetT mips_cpreturn_offset
= -1;
489 static int mips_cpreturn_register
= -1;
490 static int mips_gp_register
= GP
;
491 static int mips_gprel_offset
= 0;
493 /* Whether mips_cprestore_offset has been set in the current function
494 (or whether it has already been warned about, if not). */
495 static int mips_cprestore_valid
= 0;
497 /* This is the register which holds the stack frame, as set by the
498 .frame pseudo-op. This is needed to implement .cprestore. */
499 static int mips_frame_reg
= SP
;
501 /* Whether mips_frame_reg has been set in the current function
502 (or whether it has already been warned about, if not). */
503 static int mips_frame_reg_valid
= 0;
505 /* To output NOP instructions correctly, we need to keep information
506 about the previous two instructions. */
508 /* Whether we are optimizing. The default value of 2 means to remove
509 unneeded NOPs and swap branch instructions when possible. A value
510 of 1 means to not swap branches. A value of 0 means to always
512 static int mips_optimize
= 2;
514 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
515 equivalent to seeing no -g option at all. */
516 static int mips_debug
= 0;
518 /* The previous instruction. */
519 static struct mips_cl_insn prev_insn
;
521 /* The instruction before prev_insn. */
522 static struct mips_cl_insn prev_prev_insn
;
524 /* If we don't want information for prev_insn or prev_prev_insn, we
525 point the insn_mo field at this dummy integer. */
526 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0, 0 };
528 /* Non-zero if prev_insn is valid. */
529 static int prev_insn_valid
;
531 /* The frag for the previous instruction. */
532 static struct frag
*prev_insn_frag
;
534 /* The offset into prev_insn_frag for the previous instruction. */
535 static long prev_insn_where
;
537 /* The reloc type for the previous instruction, if any. */
538 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
540 /* The reloc for the previous instruction, if any. */
541 static fixS
*prev_insn_fixp
[3];
543 /* Non-zero if the previous instruction was in a delay slot. */
544 static int prev_insn_is_delay_slot
;
546 /* Non-zero if the previous instruction was in a .set noreorder. */
547 static int prev_insn_unreordered
;
549 /* Non-zero if the previous instruction uses an extend opcode (if
551 static int prev_insn_extended
;
553 /* Non-zero if the previous previous instruction was in a .set
555 static int prev_prev_insn_unreordered
;
557 /* If this is set, it points to a frag holding nop instructions which
558 were inserted before the start of a noreorder section. If those
559 nops turn out to be unnecessary, the size of the frag can be
561 static fragS
*prev_nop_frag
;
563 /* The number of nop instructions we created in prev_nop_frag. */
564 static int prev_nop_frag_holds
;
566 /* The number of nop instructions that we know we need in
568 static int prev_nop_frag_required
;
570 /* The number of instructions we've seen since prev_nop_frag. */
571 static int prev_nop_frag_since
;
573 /* For ECOFF and ELF, relocations against symbols are done in two
574 parts, with a HI relocation and a LO relocation. Each relocation
575 has only 16 bits of space to store an addend. This means that in
576 order for the linker to handle carries correctly, it must be able
577 to locate both the HI and the LO relocation. This means that the
578 relocations must appear in order in the relocation table.
580 In order to implement this, we keep track of each unmatched HI
581 relocation. We then sort them so that they immediately precede the
582 corresponding LO relocation. */
587 struct mips_hi_fixup
*next
;
590 /* The section this fixup is in. */
594 /* The list of unmatched HI relocs. */
596 static struct mips_hi_fixup
*mips_hi_fixup_list
;
598 /* The frag containing the last explicit relocation operator.
599 Null if explicit relocations have not been used. */
601 static fragS
*prev_reloc_op_frag
;
603 /* Map normal MIPS register numbers to mips16 register numbers. */
605 #define X ILLEGAL_REG
606 static const int mips32_to_16_reg_map
[] =
608 X
, X
, 2, 3, 4, 5, 6, 7,
609 X
, X
, X
, X
, X
, X
, X
, X
,
610 0, 1, X
, X
, X
, X
, X
, X
,
611 X
, X
, X
, X
, X
, X
, X
, X
615 /* Map mips16 register numbers to normal MIPS register numbers. */
617 static const unsigned int mips16_to_32_reg_map
[] =
619 16, 17, 2, 3, 4, 5, 6, 7
622 static int mips_fix_vr4120
;
624 /* We don't relax branches by default, since this causes us to expand
625 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
626 fail to compute the offset before expanding the macro to the most
627 efficient expansion. */
629 static int mips_relax_branch
;
631 /* The expansion of many macros depends on the type of symbol that
632 they refer to. For example, when generating position-dependent code,
633 a macro that refers to a symbol may have two different expansions,
634 one which uses GP-relative addresses and one which uses absolute
635 addresses. When generating SVR4-style PIC, a macro may have
636 different expansions for local and global symbols.
638 We handle these situations by generating both sequences and putting
639 them in variant frags. In position-dependent code, the first sequence
640 will be the GP-relative one and the second sequence will be the
641 absolute one. In SVR4 PIC, the first sequence will be for global
642 symbols and the second will be for local symbols.
644 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
645 SECOND are the lengths of the two sequences in bytes. These fields
646 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
647 the subtype has the following flags:
650 Set if it has been decided that we should use the second
651 sequence instead of the first.
654 Set in the first variant frag if the macro's second implementation
655 is longer than its first. This refers to the macro as a whole,
656 not an individual relaxation.
659 Set in the first variant frag if the macro appeared in a .set nomacro
660 block and if one alternative requires a warning but the other does not.
663 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
666 The frag's "opcode" points to the first fixup for relaxable code.
668 Relaxable macros are generated using a sequence such as:
670 relax_start (SYMBOL);
671 ... generate first expansion ...
673 ... generate second expansion ...
676 The code and fixups for the unwanted alternative are discarded
677 by md_convert_frag. */
678 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
680 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
681 #define RELAX_SECOND(X) ((X) & 0xff)
682 #define RELAX_USE_SECOND 0x10000
683 #define RELAX_SECOND_LONGER 0x20000
684 #define RELAX_NOMACRO 0x40000
685 #define RELAX_DELAY_SLOT 0x80000
687 /* Branch without likely bit. If label is out of range, we turn:
689 beq reg1, reg2, label
699 with the following opcode replacements:
706 bltzal <-> bgezal (with jal label instead of j label)
708 Even though keeping the delay slot instruction in the delay slot of
709 the branch would be more efficient, it would be very tricky to do
710 correctly, because we'd have to introduce a variable frag *after*
711 the delay slot instruction, and expand that instead. Let's do it
712 the easy way for now, even if the branch-not-taken case now costs
713 one additional instruction. Out-of-range branches are not supposed
714 to be common, anyway.
716 Branch likely. If label is out of range, we turn:
718 beql reg1, reg2, label
719 delay slot (annulled if branch not taken)
728 delay slot (executed only if branch taken)
731 It would be possible to generate a shorter sequence by losing the
732 likely bit, generating something like:
737 delay slot (executed only if branch taken)
749 bltzall -> bgezal (with jal label instead of j label)
750 bgezall -> bltzal (ditto)
753 but it's not clear that it would actually improve performance. */
754 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
757 | ((toofar) ? 1 : 0) \
759 | ((likely) ? 4 : 0) \
760 | ((uncond) ? 8 : 0)))
761 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
762 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
763 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
764 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
765 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
767 /* For mips16 code, we use an entirely different form of relaxation.
768 mips16 supports two versions of most instructions which take
769 immediate values: a small one which takes some small value, and a
770 larger one which takes a 16 bit value. Since branches also follow
771 this pattern, relaxing these values is required.
773 We can assemble both mips16 and normal MIPS code in a single
774 object. Therefore, we need to support this type of relaxation at
775 the same time that we support the relaxation described above. We
776 use the high bit of the subtype field to distinguish these cases.
778 The information we store for this type of relaxation is the
779 argument code found in the opcode file for this relocation, whether
780 the user explicitly requested a small or extended form, and whether
781 the relocation is in a jump or jal delay slot. That tells us the
782 size of the value, and how it should be stored. We also store
783 whether the fragment is considered to be extended or not. We also
784 store whether this is known to be a branch to a different section,
785 whether we have tried to relax this frag yet, and whether we have
786 ever extended a PC relative fragment because of a shift count. */
787 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
790 | ((small) ? 0x100 : 0) \
791 | ((ext) ? 0x200 : 0) \
792 | ((dslot) ? 0x400 : 0) \
793 | ((jal_dslot) ? 0x800 : 0))
794 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
795 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
796 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
797 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
798 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
799 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
800 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
801 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
802 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
803 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
804 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
805 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
807 /* Is the given value a sign-extended 32-bit value? */
808 #define IS_SEXT_32BIT_NUM(x) \
809 (((x) &~ (offsetT) 0x7fffffff) == 0 \
810 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
812 /* Is the given value a sign-extended 16-bit value? */
813 #define IS_SEXT_16BIT_NUM(x) \
814 (((x) &~ (offsetT) 0x7fff) == 0 \
815 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
818 /* Global variables used when generating relaxable macros. See the
819 comment above RELAX_ENCODE for more details about how relaxation
822 /* 0 if we're not emitting a relaxable macro.
823 1 if we're emitting the first of the two relaxation alternatives.
824 2 if we're emitting the second alternative. */
827 /* The first relaxable fixup in the current frag. (In other words,
828 the first fixup that refers to relaxable code.) */
831 /* sizes[0] says how many bytes of the first alternative are stored in
832 the current frag. Likewise sizes[1] for the second alternative. */
833 unsigned int sizes
[2];
835 /* The symbol on which the choice of sequence depends. */
839 /* Global variables used to decide whether a macro needs a warning. */
841 /* True if the macro is in a branch delay slot. */
842 bfd_boolean delay_slot_p
;
844 /* For relaxable macros, sizes[0] is the length of the first alternative
845 in bytes and sizes[1] is the length of the second alternative.
846 For non-relaxable macros, both elements give the length of the
848 unsigned int sizes
[2];
850 /* The first variant frag for this macro. */
852 } mips_macro_warning
;
854 /* Prototypes for static functions. */
856 #define internalError() \
857 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
859 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
861 static void append_insn
862 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
863 static void mips_no_prev_insn (int);
864 static void mips16_macro_build
865 (expressionS
*, const char *, const char *, va_list);
866 static void load_register (int, expressionS
*, int);
867 static void macro_start (void);
868 static void macro_end (void);
869 static void macro (struct mips_cl_insn
* ip
);
870 static void mips16_macro (struct mips_cl_insn
* ip
);
871 #ifdef LOSING_COMPILER
872 static void macro2 (struct mips_cl_insn
* ip
);
874 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
875 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
876 static void mips16_immed
877 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
878 unsigned long *, bfd_boolean
*, unsigned short *);
879 static size_t my_getSmallExpression
880 (expressionS
*, bfd_reloc_code_real_type
*, char *);
881 static void my_getExpression (expressionS
*, char *);
882 static void s_align (int);
883 static void s_change_sec (int);
884 static void s_change_section (int);
885 static void s_cons (int);
886 static void s_float_cons (int);
887 static void s_mips_globl (int);
888 static void s_option (int);
889 static void s_mipsset (int);
890 static void s_abicalls (int);
891 static void s_cpload (int);
892 static void s_cpsetup (int);
893 static void s_cplocal (int);
894 static void s_cprestore (int);
895 static void s_cpreturn (int);
896 static void s_gpvalue (int);
897 static void s_gpword (int);
898 static void s_gpdword (int);
899 static void s_cpadd (int);
900 static void s_insn (int);
901 static void md_obj_begin (void);
902 static void md_obj_end (void);
903 static void s_mips_ent (int);
904 static void s_mips_end (int);
905 static void s_mips_frame (int);
906 static void s_mips_mask (int reg_type
);
907 static void s_mips_stab (int);
908 static void s_mips_weakext (int);
909 static void s_mips_file (int);
910 static void s_mips_loc (int);
911 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
912 static int relaxed_branch_length (fragS
*, asection
*, int);
913 static int validate_mips_insn (const struct mips_opcode
*);
915 /* Table and functions used to map between CPU/ISA names, and
916 ISA levels, and CPU numbers. */
920 const char *name
; /* CPU or ISA name. */
921 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
922 int isa
; /* ISA level. */
923 int cpu
; /* CPU number (default CPU if ISA). */
926 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
927 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
928 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
932 The following pseudo-ops from the Kane and Heinrich MIPS book
933 should be defined here, but are currently unsupported: .alias,
934 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
936 The following pseudo-ops from the Kane and Heinrich MIPS book are
937 specific to the type of debugging information being generated, and
938 should be defined by the object format: .aent, .begin, .bend,
939 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
942 The following pseudo-ops from the Kane and Heinrich MIPS book are
943 not MIPS CPU specific, but are also not specific to the object file
944 format. This file is probably the best place to define them, but
945 they are not currently supported: .asm0, .endr, .lab, .repeat,
948 static const pseudo_typeS mips_pseudo_table
[] =
950 /* MIPS specific pseudo-ops. */
951 {"option", s_option
, 0},
952 {"set", s_mipsset
, 0},
953 {"rdata", s_change_sec
, 'r'},
954 {"sdata", s_change_sec
, 's'},
955 {"livereg", s_ignore
, 0},
956 {"abicalls", s_abicalls
, 0},
957 {"cpload", s_cpload
, 0},
958 {"cpsetup", s_cpsetup
, 0},
959 {"cplocal", s_cplocal
, 0},
960 {"cprestore", s_cprestore
, 0},
961 {"cpreturn", s_cpreturn
, 0},
962 {"gpvalue", s_gpvalue
, 0},
963 {"gpword", s_gpword
, 0},
964 {"gpdword", s_gpdword
, 0},
965 {"cpadd", s_cpadd
, 0},
968 /* Relatively generic pseudo-ops that happen to be used on MIPS
970 {"asciiz", stringer
, 1},
971 {"bss", s_change_sec
, 'b'},
974 {"dword", s_cons
, 3},
975 {"weakext", s_mips_weakext
, 0},
977 /* These pseudo-ops are defined in read.c, but must be overridden
978 here for one reason or another. */
979 {"align", s_align
, 0},
981 {"data", s_change_sec
, 'd'},
982 {"double", s_float_cons
, 'd'},
983 {"float", s_float_cons
, 'f'},
984 {"globl", s_mips_globl
, 0},
985 {"global", s_mips_globl
, 0},
986 {"hword", s_cons
, 1},
991 {"section", s_change_section
, 0},
992 {"short", s_cons
, 1},
993 {"single", s_float_cons
, 'f'},
994 {"stabn", s_mips_stab
, 'n'},
995 {"text", s_change_sec
, 't'},
998 { "extern", ecoff_directive_extern
, 0},
1003 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1005 /* These pseudo-ops should be defined by the object file format.
1006 However, a.out doesn't support them, so we have versions here. */
1007 {"aent", s_mips_ent
, 1},
1008 {"bgnb", s_ignore
, 0},
1009 {"end", s_mips_end
, 0},
1010 {"endb", s_ignore
, 0},
1011 {"ent", s_mips_ent
, 0},
1012 {"file", s_mips_file
, 0},
1013 {"fmask", s_mips_mask
, 'F'},
1014 {"frame", s_mips_frame
, 0},
1015 {"loc", s_mips_loc
, 0},
1016 {"mask", s_mips_mask
, 'R'},
1017 {"verstamp", s_ignore
, 0},
1021 extern void pop_insert (const pseudo_typeS
*);
1024 mips_pop_insert (void)
1026 pop_insert (mips_pseudo_table
);
1027 if (! ECOFF_DEBUGGING
)
1028 pop_insert (mips_nonecoff_pseudo_table
);
1031 /* Symbols labelling the current insn. */
1033 struct insn_label_list
1035 struct insn_label_list
*next
;
1039 static struct insn_label_list
*insn_labels
;
1040 static struct insn_label_list
*free_insn_labels
;
1042 static void mips_clear_insn_labels (void);
1045 mips_clear_insn_labels (void)
1047 register struct insn_label_list
**pl
;
1049 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1055 static char *expr_end
;
1057 /* Expressions which appear in instructions. These are set by
1060 static expressionS imm_expr
;
1061 static expressionS imm2_expr
;
1062 static expressionS offset_expr
;
1064 /* Relocs associated with imm_expr and offset_expr. */
1066 static bfd_reloc_code_real_type imm_reloc
[3]
1067 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1068 static bfd_reloc_code_real_type offset_reloc
[3]
1069 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1071 /* These are set by mips16_ip if an explicit extension is used. */
1073 static bfd_boolean mips16_small
, mips16_ext
;
1076 /* The pdr segment for per procedure frame/regmask info. Not used for
1079 static segT pdr_seg
;
1082 /* The default target format to use. */
1085 mips_target_format (void)
1087 switch (OUTPUT_FLAVOR
)
1089 case bfd_target_ecoff_flavour
:
1090 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1091 case bfd_target_coff_flavour
:
1093 case bfd_target_elf_flavour
:
1095 /* This is traditional mips. */
1096 return (target_big_endian
1097 ? (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradbigmips"
1100 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1101 : (HAVE_64BIT_OBJECTS
1102 ? "elf64-tradlittlemips"
1104 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1106 return (target_big_endian
1107 ? (HAVE_64BIT_OBJECTS
1110 ? "elf32-nbigmips" : "elf32-bigmips"))
1111 : (HAVE_64BIT_OBJECTS
1112 ? "elf64-littlemips"
1114 ? "elf32-nlittlemips" : "elf32-littlemips")));
1122 /* This function is called once, at assembler startup time. It should
1123 set up all the tables, etc. that the MD part of the assembler will need. */
1128 register const char *retval
= NULL
;
1132 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1133 as_warn (_("Could not set architecture and machine"));
1135 op_hash
= hash_new ();
1137 for (i
= 0; i
< NUMOPCODES
;)
1139 const char *name
= mips_opcodes
[i
].name
;
1141 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1144 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1145 mips_opcodes
[i
].name
, retval
);
1146 /* Probably a memory allocation problem? Give up now. */
1147 as_fatal (_("Broken assembler. No assembly attempted."));
1151 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1153 if (!validate_mips_insn (&mips_opcodes
[i
]))
1158 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1161 mips16_op_hash
= hash_new ();
1164 while (i
< bfd_mips16_num_opcodes
)
1166 const char *name
= mips16_opcodes
[i
].name
;
1168 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1170 as_fatal (_("internal: can't hash `%s': %s"),
1171 mips16_opcodes
[i
].name
, retval
);
1174 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1175 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1176 != mips16_opcodes
[i
].match
))
1178 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1179 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1184 while (i
< bfd_mips16_num_opcodes
1185 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1189 as_fatal (_("Broken assembler. No assembly attempted."));
1191 /* We add all the general register names to the symbol table. This
1192 helps us detect invalid uses of them. */
1193 for (i
= 0; i
< 32; i
++)
1197 sprintf (buf
, "$%d", i
);
1198 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1199 &zero_address_frag
));
1201 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1202 &zero_address_frag
));
1203 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1204 &zero_address_frag
));
1205 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1206 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1218 &zero_address_frag
));
1220 /* If we don't add these register names to the symbol table, they
1221 may end up being added as regular symbols by operand(), and then
1222 make it to the object file as undefined in case they're not
1223 regarded as local symbols. They're local in o32, since `$' is a
1224 local symbol prefix, but not in n32 or n64. */
1225 for (i
= 0; i
< 8; i
++)
1229 sprintf (buf
, "$fcc%i", i
);
1230 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1231 &zero_address_frag
));
1234 mips_no_prev_insn (FALSE
);
1237 mips_cprmask
[0] = 0;
1238 mips_cprmask
[1] = 0;
1239 mips_cprmask
[2] = 0;
1240 mips_cprmask
[3] = 0;
1242 /* set the default alignment for the text section (2**2) */
1243 record_alignment (text_section
, 2);
1245 bfd_set_gp_size (stdoutput
, g_switch_value
);
1247 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1249 /* On a native system, sections must be aligned to 16 byte
1250 boundaries. When configured for an embedded ELF target, we
1252 if (strcmp (TARGET_OS
, "elf") != 0)
1254 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1255 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1256 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1259 /* Create a .reginfo section for register masks and a .mdebug
1260 section for debugging information. */
1268 subseg
= now_subseg
;
1270 /* The ABI says this section should be loaded so that the
1271 running program can access it. However, we don't load it
1272 if we are configured for an embedded target */
1273 flags
= SEC_READONLY
| SEC_DATA
;
1274 if (strcmp (TARGET_OS
, "elf") != 0)
1275 flags
|= SEC_ALLOC
| SEC_LOAD
;
1277 if (mips_abi
!= N64_ABI
)
1279 sec
= subseg_new (".reginfo", (subsegT
) 0);
1281 bfd_set_section_flags (stdoutput
, sec
, flags
);
1282 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1285 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1290 /* The 64-bit ABI uses a .MIPS.options section rather than
1291 .reginfo section. */
1292 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1293 bfd_set_section_flags (stdoutput
, sec
, flags
);
1294 bfd_set_section_alignment (stdoutput
, sec
, 3);
1297 /* Set up the option header. */
1299 Elf_Internal_Options opthdr
;
1302 opthdr
.kind
= ODK_REGINFO
;
1303 opthdr
.size
= (sizeof (Elf_External_Options
)
1304 + sizeof (Elf64_External_RegInfo
));
1307 f
= frag_more (sizeof (Elf_External_Options
));
1308 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1309 (Elf_External_Options
*) f
);
1311 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1316 if (ECOFF_DEBUGGING
)
1318 sec
= subseg_new (".mdebug", (subsegT
) 0);
1319 (void) bfd_set_section_flags (stdoutput
, sec
,
1320 SEC_HAS_CONTENTS
| SEC_READONLY
);
1321 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1324 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1326 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1327 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1328 SEC_READONLY
| SEC_RELOC
1330 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1334 subseg_set (seg
, subseg
);
1338 if (! ECOFF_DEBUGGING
)
1345 if (! ECOFF_DEBUGGING
)
1350 md_assemble (char *str
)
1352 struct mips_cl_insn insn
;
1353 bfd_reloc_code_real_type unused_reloc
[3]
1354 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1356 imm_expr
.X_op
= O_absent
;
1357 imm2_expr
.X_op
= O_absent
;
1358 offset_expr
.X_op
= O_absent
;
1359 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1360 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1361 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1362 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1364 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1366 if (mips_opts
.mips16
)
1367 mips16_ip (str
, &insn
);
1370 mips_ip (str
, &insn
);
1371 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1372 str
, insn
.insn_opcode
));
1377 as_bad ("%s `%s'", insn_error
, str
);
1381 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1384 if (mips_opts
.mips16
)
1385 mips16_macro (&insn
);
1392 if (imm_expr
.X_op
!= O_absent
)
1393 append_insn (&insn
, &imm_expr
, imm_reloc
);
1394 else if (offset_expr
.X_op
!= O_absent
)
1395 append_insn (&insn
, &offset_expr
, offset_reloc
);
1397 append_insn (&insn
, NULL
, unused_reloc
);
1401 /* Return true if the given relocation might need a matching %lo().
1402 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1403 applied to local symbols. */
1405 static inline bfd_boolean
1406 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1408 return (HAVE_IN_PLACE_ADDENDS
1409 && (reloc
== BFD_RELOC_HI16_S
1410 || reloc
== BFD_RELOC_MIPS_GOT16
1411 || reloc
== BFD_RELOC_MIPS16_HI16_S
));
1414 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1417 static inline bfd_boolean
1418 fixup_has_matching_lo_p (fixS
*fixp
)
1420 return (fixp
->fx_next
!= NULL
1421 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1422 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
1423 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1424 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1427 /* See whether instruction IP reads register REG. CLASS is the type
1431 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1432 enum mips_regclass
class)
1434 if (class == MIPS16_REG
)
1436 assert (mips_opts
.mips16
);
1437 reg
= mips16_to_32_reg_map
[reg
];
1438 class = MIPS_GR_REG
;
1441 /* Don't report on general register ZERO, since it never changes. */
1442 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1445 if (class == MIPS_FP_REG
)
1447 assert (! mips_opts
.mips16
);
1448 /* If we are called with either $f0 or $f1, we must check $f0.
1449 This is not optimal, because it will introduce an unnecessary
1450 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1451 need to distinguish reading both $f0 and $f1 or just one of
1452 them. Note that we don't have to check the other way,
1453 because there is no instruction that sets both $f0 and $f1
1454 and requires a delay. */
1455 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1456 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1457 == (reg
&~ (unsigned) 1)))
1459 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1460 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1461 == (reg
&~ (unsigned) 1)))
1464 else if (! mips_opts
.mips16
)
1466 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1467 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1469 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1470 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1475 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1476 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1477 & MIPS16OP_MASK_RX
)]
1480 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1481 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1482 & MIPS16OP_MASK_RY
)]
1485 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1486 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1487 & MIPS16OP_MASK_MOVE32Z
)]
1490 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1494 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1496 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1497 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1498 & MIPS16OP_MASK_REGR32
) == reg
)
1505 /* This function returns true if modifying a register requires a
1509 reg_needs_delay (unsigned int reg
)
1511 unsigned long prev_pinfo
;
1513 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1514 if (! mips_opts
.noreorder
1515 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1516 && ! gpr_interlocks
)
1517 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1518 && ! cop_interlocks
)))
1520 /* A load from a coprocessor or from memory. All load delays
1521 delay the use of general register rt for one instruction. */
1522 /* Itbl support may require additional care here. */
1523 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1524 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1531 /* Mark instruction labels in mips16 mode. This permits the linker to
1532 handle them specially, such as generating jalx instructions when
1533 needed. We also make them odd for the duration of the assembly, in
1534 order to generate the right sort of code. We will make them even
1535 in the adjust_symtab routine, while leaving them marked. This is
1536 convenient for the debugger and the disassembler. The linker knows
1537 to make them odd again. */
1540 mips16_mark_labels (void)
1542 if (mips_opts
.mips16
)
1544 struct insn_label_list
*l
;
1547 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1550 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1551 S_SET_OTHER (l
->label
, STO_MIPS16
);
1553 val
= S_GET_VALUE (l
->label
);
1555 S_SET_VALUE (l
->label
, val
+ 1);
1560 /* End the current frag. Make it a variant frag and record the
1564 relax_close_frag (void)
1566 mips_macro_warning
.first_frag
= frag_now
;
1567 frag_var (rs_machine_dependent
, 0, 0,
1568 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1569 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1571 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1572 mips_relax
.first_fixup
= 0;
1575 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1576 See the comment above RELAX_ENCODE for more details. */
1579 relax_start (symbolS
*symbol
)
1581 assert (mips_relax
.sequence
== 0);
1582 mips_relax
.sequence
= 1;
1583 mips_relax
.symbol
= symbol
;
1586 /* Start generating the second version of a relaxable sequence.
1587 See the comment above RELAX_ENCODE for more details. */
1592 assert (mips_relax
.sequence
== 1);
1593 mips_relax
.sequence
= 2;
1596 /* End the current relaxable sequence. */
1601 assert (mips_relax
.sequence
== 2);
1602 relax_close_frag ();
1603 mips_relax
.sequence
= 0;
1606 /* Output an instruction. IP is the instruction information.
1607 ADDRESS_EXPR is an operand of the instruction to be used with
1611 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1612 bfd_reloc_code_real_type
*reloc_type
)
1614 register unsigned long prev_pinfo
, pinfo
;
1618 relax_stateT prev_insn_frag_type
= 0;
1619 bfd_boolean relaxed_branch
= FALSE
;
1620 bfd_boolean force_new_frag
= FALSE
;
1622 /* Mark instruction labels in mips16 mode. */
1623 mips16_mark_labels ();
1625 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1626 pinfo
= ip
->insn_mo
->pinfo
;
1628 if (mips_relax
.sequence
!= 2
1629 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1633 /* If the previous insn required any delay slots, see if we need
1634 to insert a NOP or two. There are eight kinds of possible
1635 hazards, of which an instruction can have at most one type.
1636 (1) a load from memory delay
1637 (2) a load from a coprocessor delay
1638 (3) an unconditional branch delay
1639 (4) a conditional branch delay
1640 (5) a move to coprocessor register delay
1641 (6) a load coprocessor register from memory delay
1642 (7) a coprocessor condition code delay
1643 (8) a HI/LO special register delay
1645 There are a lot of optimizations we could do that we don't.
1646 In particular, we do not, in general, reorder instructions.
1647 If you use gcc with optimization, it will reorder
1648 instructions and generally do much more optimization then we
1649 do here; repeating all that work in the assembler would only
1650 benefit hand written assembly code, and does not seem worth
1653 /* This is how a NOP is emitted. */
1654 #define emit_nop() \
1656 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1657 : md_number_to_chars (frag_more (4), 0, 4))
1659 /* The previous insn might require a delay slot, depending upon
1660 the contents of the current insn. */
1661 if (! mips_opts
.mips16
1662 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1663 && ! gpr_interlocks
)
1664 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1665 && ! cop_interlocks
)))
1667 /* A load from a coprocessor or from memory. All load
1668 delays delay the use of general register rt for one
1670 /* Itbl support may require additional care here. */
1671 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1672 if (mips_optimize
== 0
1673 || insn_uses_reg (ip
,
1674 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1679 else if (! mips_opts
.mips16
1680 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1681 && ! cop_interlocks
)
1682 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1683 && ! cop_mem_interlocks
)))
1685 /* A generic coprocessor delay. The previous instruction
1686 modified a coprocessor general or control register. If
1687 it modified a control register, we need to avoid any
1688 coprocessor instruction (this is probably not always
1689 required, but it sometimes is). If it modified a general
1690 register, we avoid using that register.
1692 This case is not handled very well. There is no special
1693 knowledge of CP0 handling, and the coprocessors other
1694 than the floating point unit are not distinguished at
1696 /* Itbl support may require additional care here. FIXME!
1697 Need to modify this to include knowledge about
1698 user specified delays! */
1699 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1701 if (mips_optimize
== 0
1702 || insn_uses_reg (ip
,
1703 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1708 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1710 if (mips_optimize
== 0
1711 || insn_uses_reg (ip
,
1712 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1719 /* We don't know exactly what the previous instruction
1720 does. If the current instruction uses a coprocessor
1721 register, we must insert a NOP. If previous
1722 instruction may set the condition codes, and the
1723 current instruction uses them, we must insert two
1725 /* Itbl support may require additional care here. */
1726 if (mips_optimize
== 0
1727 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1728 && (pinfo
& INSN_READ_COND_CODE
)))
1730 else if (pinfo
& INSN_COP
)
1734 else if (! mips_opts
.mips16
1735 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1736 && ! cop_interlocks
)
1738 /* The previous instruction sets the coprocessor condition
1739 codes, but does not require a general coprocessor delay
1740 (this means it is a floating point comparison
1741 instruction). If this instruction uses the condition
1742 codes, we need to insert a single NOP. */
1743 /* Itbl support may require additional care here. */
1744 if (mips_optimize
== 0
1745 || (pinfo
& INSN_READ_COND_CODE
))
1749 /* If we're fixing up mfhi/mflo for the r7000 and the
1750 previous insn was an mfhi/mflo and the current insn
1751 reads the register that the mfhi/mflo wrote to, then
1754 else if (mips_7000_hilo_fix
1755 && MF_HILO_INSN (prev_pinfo
)
1756 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1763 /* If we're fixing up mfhi/mflo for the r7000 and the
1764 2nd previous insn was an mfhi/mflo and the current insn
1765 reads the register that the mfhi/mflo wrote to, then
1768 else if (mips_7000_hilo_fix
1769 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1770 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1778 else if (prev_pinfo
& INSN_READ_LO
)
1780 /* The previous instruction reads the LO register; if the
1781 current instruction writes to the LO register, we must
1782 insert two NOPS. Some newer processors have interlocks.
1783 Also the tx39's multiply instructions can be executed
1784 immediately after a read from HI/LO (without the delay),
1785 though the tx39's divide insns still do require the
1787 if (! (hilo_interlocks
1788 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1789 && (mips_optimize
== 0
1790 || (pinfo
& INSN_WRITE_LO
)))
1792 /* Most mips16 branch insns don't have a delay slot.
1793 If a read from LO is immediately followed by a branch
1794 to a write to LO we have a read followed by a write
1795 less than 2 insns away. We assume the target of
1796 a branch might be a write to LO, and insert a nop
1797 between a read and an immediately following branch. */
1798 else if (mips_opts
.mips16
1799 && (mips_optimize
== 0
1800 || (pinfo
& MIPS16_INSN_BRANCH
)))
1803 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1805 /* The previous instruction reads the HI register; if the
1806 current instruction writes to the HI register, we must
1807 insert a NOP. Some newer processors have interlocks.
1808 Also the note tx39's multiply above. */
1809 if (! (hilo_interlocks
1810 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1811 && (mips_optimize
== 0
1812 || (pinfo
& INSN_WRITE_HI
)))
1814 /* Most mips16 branch insns don't have a delay slot.
1815 If a read from HI is immediately followed by a branch
1816 to a write to HI we have a read followed by a write
1817 less than 2 insns away. We assume the target of
1818 a branch might be a write to HI, and insert a nop
1819 between a read and an immediately following branch. */
1820 else if (mips_opts
.mips16
1821 && (mips_optimize
== 0
1822 || (pinfo
& MIPS16_INSN_BRANCH
)))
1826 /* If the previous instruction was in a noreorder section, then
1827 we don't want to insert the nop after all. */
1828 /* Itbl support may require additional care here. */
1829 if (prev_insn_unreordered
)
1832 /* There are two cases which require two intervening
1833 instructions: 1) setting the condition codes using a move to
1834 coprocessor instruction which requires a general coprocessor
1835 delay and then reading the condition codes 2) reading the HI
1836 or LO register and then writing to it (except on processors
1837 which have interlocks). If we are not already emitting a NOP
1838 instruction, we must check for these cases compared to the
1839 instruction previous to the previous instruction. */
1840 if ((! mips_opts
.mips16
1841 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1842 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1843 && (pinfo
& INSN_READ_COND_CODE
)
1844 && ! cop_interlocks
)
1845 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1846 && (pinfo
& INSN_WRITE_LO
)
1847 && ! (hilo_interlocks
1848 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1849 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1850 && (pinfo
& INSN_WRITE_HI
)
1851 && ! (hilo_interlocks
1852 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1857 if (prev_prev_insn_unreordered
)
1860 if (prev_prev_nop
&& nops
== 0)
1863 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1865 /* We're out of bits in pinfo, so we must resort to string
1866 ops here. Shortcuts are selected based on opcodes being
1867 limited to the VR4120 instruction set. */
1869 const char *pn
= prev_insn
.insn_mo
->name
;
1870 const char *tn
= ip
->insn_mo
->name
;
1871 if (strncmp (pn
, "macc", 4) == 0
1872 || strncmp (pn
, "dmacc", 5) == 0)
1874 /* Errata 21 - [D]DIV[U] after [D]MACC */
1875 if (strstr (tn
, "div"))
1878 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1879 instruction is executed immediately after a MACC or
1880 DMACC instruction, the result of [either instruction]
1882 if (strncmp (tn
, "mult", 4) == 0
1883 || strncmp (tn
, "dmult", 5) == 0)
1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1887 Applies on top of VR4181A MD(1) errata. */
1888 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1891 /* Errata 24 - MT{LO,HI} after [D]MACC */
1892 if (strcmp (tn
, "mtlo") == 0
1893 || strcmp (tn
, "mthi") == 0)
1896 else if (strncmp (pn
, "dmult", 5) == 0
1897 && (strncmp (tn
, "dmult", 5) == 0
1898 || strncmp (tn
, "dmacc", 5) == 0))
1900 /* Here is the rest of errata 23. */
1903 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1904 && (strncmp (tn
, "macc", 4) == 0
1905 || strncmp (tn
, "dmacc", 5) == 0))
1907 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1908 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1909 DDIV or DDIVU instruction, the result of the MACC or
1910 DMACC instruction is incorrect.". This partly overlaps
1911 the workaround for errata 23. */
1914 if (nops
< min_nops
)
1918 /* If we are being given a nop instruction, don't bother with
1919 one of the nops we would otherwise output. This will only
1920 happen when a nop instruction is used with mips_optimize set
1923 && ! mips_opts
.noreorder
1924 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1927 /* Now emit the right number of NOP instructions. */
1928 if (nops
> 0 && ! mips_opts
.noreorder
)
1931 unsigned long old_frag_offset
;
1933 struct insn_label_list
*l
;
1935 old_frag
= frag_now
;
1936 old_frag_offset
= frag_now_fix ();
1938 for (i
= 0; i
< nops
; i
++)
1943 listing_prev_line ();
1944 /* We may be at the start of a variant frag. In case we
1945 are, make sure there is enough space for the frag
1946 after the frags created by listing_prev_line. The
1947 argument to frag_grow here must be at least as large
1948 as the argument to all other calls to frag_grow in
1949 this file. We don't have to worry about being in the
1950 middle of a variant frag, because the variants insert
1951 all needed nop instructions themselves. */
1955 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1959 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1960 symbol_set_frag (l
->label
, frag_now
);
1961 val
= (valueT
) frag_now_fix ();
1962 /* mips16 text labels are stored as odd. */
1963 if (mips_opts
.mips16
)
1965 S_SET_VALUE (l
->label
, val
);
1968 #ifndef NO_ECOFF_DEBUGGING
1969 if (ECOFF_DEBUGGING
)
1970 ecoff_fix_loc (old_frag
, old_frag_offset
);
1973 else if (prev_nop_frag
!= NULL
)
1975 /* We have a frag holding nops we may be able to remove. If
1976 we don't need any nops, we can decrease the size of
1977 prev_nop_frag by the size of one instruction. If we do
1978 need some nops, we count them in prev_nops_required. */
1979 if (prev_nop_frag_since
== 0)
1983 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1984 --prev_nop_frag_holds
;
1987 prev_nop_frag_required
+= nops
;
1991 if (prev_prev_nop
== 0)
1993 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1994 --prev_nop_frag_holds
;
1997 ++prev_nop_frag_required
;
2000 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
2001 prev_nop_frag
= NULL
;
2003 ++prev_nop_frag_since
;
2005 /* Sanity check: by the time we reach the second instruction
2006 after prev_nop_frag, we should have used up all the nops
2007 one way or another. */
2008 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2012 /* Record the frag type before frag_var. */
2014 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2017 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2018 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2019 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2020 && mips_relax_branch
2021 /* Don't try branch relaxation within .set nomacro, or within
2022 .set noat if we use $at for PIC computations. If it turns
2023 out that the branch was out-of-range, we'll get an error. */
2024 && !mips_opts
.warn_about_macros
2025 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2026 && !mips_opts
.mips16
)
2028 relaxed_branch
= TRUE
;
2029 f
= frag_var (rs_machine_dependent
,
2030 relaxed_branch_length
2032 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2033 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2035 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2036 pinfo
& INSN_COND_BRANCH_LIKELY
,
2037 pinfo
& INSN_WRITE_GPR_31
,
2039 address_expr
->X_add_symbol
,
2040 address_expr
->X_add_number
,
2042 *reloc_type
= BFD_RELOC_UNUSED
;
2044 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2046 /* We need to set up a variant frag. */
2047 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2048 f
= frag_var (rs_machine_dependent
, 4, 0,
2049 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2050 mips16_small
, mips16_ext
,
2052 & INSN_UNCOND_BRANCH_DELAY
),
2053 (*prev_insn_reloc_type
2054 == BFD_RELOC_MIPS16_JMP
)),
2055 make_expr_symbol (address_expr
), 0, NULL
);
2057 else if (mips_opts
.mips16
2059 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2061 /* Make sure there is enough room to swap this instruction with
2062 a following jump instruction. */
2068 if (mips_opts
.mips16
2069 && mips_opts
.noreorder
2070 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2071 as_warn (_("extended instruction in delay slot"));
2073 if (mips_relax
.sequence
)
2075 /* If we've reached the end of this frag, turn it into a variant
2076 frag and record the information for the instructions we've
2078 if (frag_room () < 4)
2079 relax_close_frag ();
2080 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2083 if (mips_relax
.sequence
!= 2)
2084 mips_macro_warning
.sizes
[0] += 4;
2085 if (mips_relax
.sequence
!= 1)
2086 mips_macro_warning
.sizes
[1] += 4;
2091 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2092 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2094 if (address_expr
->X_op
== O_constant
)
2098 switch (*reloc_type
)
2101 ip
->insn_opcode
|= address_expr
->X_add_number
;
2104 case BFD_RELOC_MIPS_HIGHEST
:
2105 tmp
= (address_expr
->X_add_number
2106 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2108 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2111 case BFD_RELOC_MIPS_HIGHER
:
2112 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2113 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2116 case BFD_RELOC_HI16_S
:
2117 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2121 case BFD_RELOC_HI16
:
2122 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2125 case BFD_RELOC_UNUSED
:
2126 case BFD_RELOC_LO16
:
2127 case BFD_RELOC_MIPS_GOT_DISP
:
2128 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2131 case BFD_RELOC_MIPS_JMP
:
2132 if ((address_expr
->X_add_number
& 3) != 0)
2133 as_bad (_("jump to misaligned address (0x%lx)"),
2134 (unsigned long) address_expr
->X_add_number
);
2135 if (address_expr
->X_add_number
& ~0xfffffff)
2136 as_bad (_("jump address range overflow (0x%lx)"),
2137 (unsigned long) address_expr
->X_add_number
);
2138 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2141 case BFD_RELOC_MIPS16_JMP
:
2142 if ((address_expr
->X_add_number
& 3) != 0)
2143 as_bad (_("jump to misaligned address (0x%lx)"),
2144 (unsigned long) address_expr
->X_add_number
);
2145 if (address_expr
->X_add_number
& ~0xfffffff)
2146 as_bad (_("jump address range overflow (0x%lx)"),
2147 (unsigned long) address_expr
->X_add_number
);
2149 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2150 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2151 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2154 case BFD_RELOC_16_PCREL_S2
:
2161 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2164 reloc_howto_type
*howto
;
2167 /* In a compound relocation, it is the final (outermost)
2168 operator that determines the relocated field. */
2169 for (i
= 1; i
< 3; i
++)
2170 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2173 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2174 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2175 bfd_get_reloc_size(howto
),
2177 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2180 /* These relocations can have an addend that won't fit in
2181 4 octets for 64bit assembly. */
2183 && ! howto
->partial_inplace
2184 && (reloc_type
[0] == BFD_RELOC_16
2185 || reloc_type
[0] == BFD_RELOC_32
2186 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2187 || reloc_type
[0] == BFD_RELOC_HI16_S
2188 || reloc_type
[0] == BFD_RELOC_LO16
2189 || reloc_type
[0] == BFD_RELOC_GPREL16
2190 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2191 || reloc_type
[0] == BFD_RELOC_GPREL32
2192 || reloc_type
[0] == BFD_RELOC_64
2193 || reloc_type
[0] == BFD_RELOC_CTOR
2194 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2195 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2196 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2197 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2198 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2199 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2200 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2201 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2202 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2203 fixp
[0]->fx_no_overflow
= 1;
2205 if (mips_relax
.sequence
)
2207 if (mips_relax
.first_fixup
== 0)
2208 mips_relax
.first_fixup
= fixp
[0];
2210 else if (reloc_needs_lo_p (*reloc_type
))
2212 struct mips_hi_fixup
*hi_fixup
;
2214 /* Reuse the last entry if it already has a matching %lo. */
2215 hi_fixup
= mips_hi_fixup_list
;
2217 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2219 hi_fixup
= ((struct mips_hi_fixup
*)
2220 xmalloc (sizeof (struct mips_hi_fixup
)));
2221 hi_fixup
->next
= mips_hi_fixup_list
;
2222 mips_hi_fixup_list
= hi_fixup
;
2224 hi_fixup
->fixp
= fixp
[0];
2225 hi_fixup
->seg
= now_seg
;
2228 /* Add fixups for the second and third relocations, if given.
2229 Note that the ABI allows the second relocation to be
2230 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2231 moment we only use RSS_UNDEF, but we could add support
2232 for the others if it ever becomes necessary. */
2233 for (i
= 1; i
< 3; i
++)
2234 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2236 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2237 fixp
[0]->fx_size
, NULL
, 0,
2238 FALSE
, reloc_type
[i
]);
2240 /* Use fx_tcbit to mark compound relocs. */
2241 fixp
[0]->fx_tcbit
= 1;
2242 fixp
[i
]->fx_tcbit
= 1;
2247 if (! mips_opts
.mips16
)
2249 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2251 dwarf2_emit_insn (4);
2254 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2256 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2257 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2259 /* The value passed to dwarf2_emit_insn is the distance between
2260 the end of the current instruction and the address that should
2261 be recorded in the debug tables. Since we want to use ISA-encoded
2262 addresses in MIPS16 debug info, the value is one byte less than
2263 the real instruction length. */
2264 dwarf2_emit_insn (3);
2271 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2274 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2276 dwarf2_emit_insn (ip
->use_extend
? 3 : 1);
2280 /* Update the register mask information. */
2281 if (! mips_opts
.mips16
)
2283 if (pinfo
& INSN_WRITE_GPR_D
)
2284 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2285 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2286 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2287 if (pinfo
& INSN_READ_GPR_S
)
2288 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2289 if (pinfo
& INSN_WRITE_GPR_31
)
2290 mips_gprmask
|= 1 << RA
;
2291 if (pinfo
& INSN_WRITE_FPR_D
)
2292 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2293 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2294 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2295 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2296 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2297 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2298 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2299 if (pinfo
& INSN_COP
)
2301 /* We don't keep enough information to sort these cases out.
2302 The itbl support does keep this information however, although
2303 we currently don't support itbl fprmats as part of the cop
2304 instruction. May want to add this support in the future. */
2306 /* Never set the bit for $0, which is always zero. */
2307 mips_gprmask
&= ~1 << 0;
2311 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2312 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2313 & MIPS16OP_MASK_RX
);
2314 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2315 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2316 & MIPS16OP_MASK_RY
);
2317 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2318 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2319 & MIPS16OP_MASK_RZ
);
2320 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2321 mips_gprmask
|= 1 << TREG
;
2322 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2323 mips_gprmask
|= 1 << SP
;
2324 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2325 mips_gprmask
|= 1 << RA
;
2326 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2327 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2328 if (pinfo
& MIPS16_INSN_READ_Z
)
2329 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2330 & MIPS16OP_MASK_MOVE32Z
);
2331 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2332 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2333 & MIPS16OP_MASK_REGR32
);
2336 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2338 /* Filling the branch delay slot is more complex. We try to
2339 switch the branch with the previous instruction, which we can
2340 do if the previous instruction does not set up a condition
2341 that the branch tests and if the branch is not itself the
2342 target of any branch. */
2343 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2344 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2346 if (mips_optimize
< 2
2347 /* If we have seen .set volatile or .set nomove, don't
2349 || mips_opts
.nomove
!= 0
2350 /* If we had to emit any NOP instructions, then we
2351 already know we can not swap. */
2353 /* If we don't even know the previous insn, we can not
2355 || ! prev_insn_valid
2356 /* If the previous insn is already in a branch delay
2357 slot, then we can not swap. */
2358 || prev_insn_is_delay_slot
2359 /* If the previous previous insn was in a .set
2360 noreorder, we can't swap. Actually, the MIPS
2361 assembler will swap in this situation. However, gcc
2362 configured -with-gnu-as will generate code like
2368 in which we can not swap the bne and INSN. If gcc is
2369 not configured -with-gnu-as, it does not output the
2370 .set pseudo-ops. We don't have to check
2371 prev_insn_unreordered, because prev_insn_valid will
2372 be 0 in that case. We don't want to use
2373 prev_prev_insn_valid, because we do want to be able
2374 to swap at the start of a function. */
2375 || prev_prev_insn_unreordered
2376 /* If the branch is itself the target of a branch, we
2377 can not swap. We cheat on this; all we check for is
2378 whether there is a label on this instruction. If
2379 there are any branches to anything other than a
2380 label, users must use .set noreorder. */
2381 || insn_labels
!= NULL
2382 /* If the previous instruction is in a variant frag
2383 other than this branch's one, we cannot do the swap.
2384 This does not apply to the mips16, which uses variant
2385 frags for different purposes. */
2386 || (! mips_opts
.mips16
2387 && prev_insn_frag_type
== rs_machine_dependent
)
2388 /* If the branch reads the condition codes, we don't
2389 even try to swap, because in the sequence
2394 we can not swap, and I don't feel like handling that
2396 || (! mips_opts
.mips16
2397 && (pinfo
& INSN_READ_COND_CODE
)
2398 && ! cop_interlocks
)
2399 /* We can not swap with an instruction that requires a
2400 delay slot, because the target of the branch might
2401 interfere with that instruction. */
2402 || (! mips_opts
.mips16
2404 /* Itbl support may require additional care here. */
2405 & (INSN_LOAD_COPROC_DELAY
2406 | INSN_COPROC_MOVE_DELAY
2407 | INSN_WRITE_COND_CODE
))
2408 && ! cop_interlocks
)
2409 || (! (hilo_interlocks
2410 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2414 || (! mips_opts
.mips16
2415 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2416 && ! gpr_interlocks
)
2417 || (! mips_opts
.mips16
2418 /* Itbl support may require additional care here. */
2419 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2420 && ! cop_mem_interlocks
)
2421 /* We can not swap with a branch instruction. */
2423 & (INSN_UNCOND_BRANCH_DELAY
2424 | INSN_COND_BRANCH_DELAY
2425 | INSN_COND_BRANCH_LIKELY
))
2426 /* We do not swap with a trap instruction, since it
2427 complicates trap handlers to have the trap
2428 instruction be in a delay slot. */
2429 || (prev_pinfo
& INSN_TRAP
)
2430 /* If the branch reads a register that the previous
2431 instruction sets, we can not swap. */
2432 || (! mips_opts
.mips16
2433 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2434 && insn_uses_reg (ip
,
2435 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2438 || (! mips_opts
.mips16
2439 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2440 && insn_uses_reg (ip
,
2441 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2444 || (mips_opts
.mips16
2445 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2446 && insn_uses_reg (ip
,
2447 ((prev_insn
.insn_opcode
2449 & MIPS16OP_MASK_RX
),
2451 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2452 && insn_uses_reg (ip
,
2453 ((prev_insn
.insn_opcode
2455 & MIPS16OP_MASK_RY
),
2457 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2458 && insn_uses_reg (ip
,
2459 ((prev_insn
.insn_opcode
2461 & MIPS16OP_MASK_RZ
),
2463 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2464 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2465 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2466 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2467 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2468 && insn_uses_reg (ip
,
2469 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2472 /* If the branch writes a register that the previous
2473 instruction sets, we can not swap (we know that
2474 branches write only to RD or to $31). */
2475 || (! mips_opts
.mips16
2476 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2477 && (((pinfo
& INSN_WRITE_GPR_D
)
2478 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2479 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2480 || ((pinfo
& INSN_WRITE_GPR_31
)
2481 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2484 || (! mips_opts
.mips16
2485 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2486 && (((pinfo
& INSN_WRITE_GPR_D
)
2487 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2488 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2489 || ((pinfo
& INSN_WRITE_GPR_31
)
2490 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2493 || (mips_opts
.mips16
2494 && (pinfo
& MIPS16_INSN_WRITE_31
)
2495 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2496 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2497 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2499 /* If the branch writes a register that the previous
2500 instruction reads, we can not swap (we know that
2501 branches only write to RD or to $31). */
2502 || (! mips_opts
.mips16
2503 && (pinfo
& INSN_WRITE_GPR_D
)
2504 && insn_uses_reg (&prev_insn
,
2505 ((ip
->insn_opcode
>> OP_SH_RD
)
2508 || (! mips_opts
.mips16
2509 && (pinfo
& INSN_WRITE_GPR_31
)
2510 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2511 || (mips_opts
.mips16
2512 && (pinfo
& MIPS16_INSN_WRITE_31
)
2513 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2514 /* If the previous previous instruction has a load
2515 delay, and sets a register that the branch reads, we
2517 || (! mips_opts
.mips16
2518 /* Itbl support may require additional care here. */
2519 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2520 && ! cop_interlocks
)
2521 || ((prev_prev_insn
.insn_mo
->pinfo
2522 & INSN_LOAD_MEMORY_DELAY
)
2523 && ! gpr_interlocks
))
2524 && insn_uses_reg (ip
,
2525 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2528 /* If one instruction sets a condition code and the
2529 other one uses a condition code, we can not swap. */
2530 || ((pinfo
& INSN_READ_COND_CODE
)
2531 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2532 || ((pinfo
& INSN_WRITE_COND_CODE
)
2533 && (prev_pinfo
& INSN_READ_COND_CODE
))
2534 /* If the previous instruction uses the PC, we can not
2536 || (mips_opts
.mips16
2537 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2538 /* If the previous instruction was extended, we can not
2540 || (mips_opts
.mips16
&& prev_insn_extended
)
2541 /* If the previous instruction had a fixup in mips16
2542 mode, we can not swap. This normally means that the
2543 previous instruction was a 4 byte branch anyhow. */
2544 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2545 /* If the previous instruction is a sync, sync.l, or
2546 sync.p, we can not swap. */
2547 || (prev_pinfo
& INSN_SYNC
))
2549 /* We could do even better for unconditional branches to
2550 portions of this object file; we could pick up the
2551 instruction at the destination, put it in the delay
2552 slot, and bump the destination address. */
2554 if (mips_relax
.sequence
)
2555 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2556 /* Update the previous insn information. */
2557 prev_prev_insn
= *ip
;
2558 prev_insn
.insn_mo
= &dummy_opcode
;
2562 /* It looks like we can actually do the swap. */
2563 if (! mips_opts
.mips16
)
2568 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2569 if (!relaxed_branch
)
2571 /* If this is not a relaxed branch, then just
2572 swap the instructions. */
2573 memcpy (temp
, prev_f
, 4);
2574 memcpy (prev_f
, f
, 4);
2575 memcpy (f
, temp
, 4);
2579 /* If this is a relaxed branch, then we move the
2580 instruction to be placed in the delay slot to
2581 the current frag, shrinking the fixed part of
2582 the originating frag. If the branch occupies
2583 the tail of the latter, we move it backwards,
2584 into the space freed by the moved instruction. */
2586 memcpy (f
, prev_f
, 4);
2587 prev_insn_frag
->fr_fix
-= 4;
2588 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2589 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2592 if (prev_insn_fixp
[0])
2594 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2595 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2597 if (prev_insn_fixp
[1])
2599 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2600 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2602 if (prev_insn_fixp
[2])
2604 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2605 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2607 if (prev_insn_fixp
[0] && HAVE_NEWABI
2608 && prev_insn_frag
!= frag_now
2609 && (prev_insn_fixp
[0]->fx_r_type
2610 == BFD_RELOC_MIPS_GOT_DISP
2611 || (prev_insn_fixp
[0]->fx_r_type
2612 == BFD_RELOC_MIPS_CALL16
)))
2614 /* To avoid confusion in tc_gen_reloc, we must
2615 ensure that this does not become a variant
2617 force_new_frag
= TRUE
;
2620 if (!relaxed_branch
)
2624 fixp
[0]->fx_frag
= prev_insn_frag
;
2625 fixp
[0]->fx_where
= prev_insn_where
;
2629 fixp
[1]->fx_frag
= prev_insn_frag
;
2630 fixp
[1]->fx_where
= prev_insn_where
;
2634 fixp
[2]->fx_frag
= prev_insn_frag
;
2635 fixp
[2]->fx_where
= prev_insn_where
;
2638 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2641 fixp
[0]->fx_where
-= 4;
2643 fixp
[1]->fx_where
-= 4;
2645 fixp
[2]->fx_where
-= 4;
2653 assert (prev_insn_fixp
[0] == NULL
);
2654 assert (prev_insn_fixp
[1] == NULL
);
2655 assert (prev_insn_fixp
[2] == NULL
);
2656 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2657 memcpy (temp
, prev_f
, 2);
2658 memcpy (prev_f
, f
, 2);
2659 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2661 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2662 memcpy (f
, temp
, 2);
2666 memcpy (f
, f
+ 2, 2);
2667 memcpy (f
+ 2, temp
, 2);
2671 fixp
[0]->fx_frag
= prev_insn_frag
;
2672 fixp
[0]->fx_where
= prev_insn_where
;
2676 fixp
[1]->fx_frag
= prev_insn_frag
;
2677 fixp
[1]->fx_where
= prev_insn_where
;
2681 fixp
[2]->fx_frag
= prev_insn_frag
;
2682 fixp
[2]->fx_where
= prev_insn_where
;
2686 /* Update the previous insn information; leave prev_insn
2688 prev_prev_insn
= *ip
;
2690 prev_insn_is_delay_slot
= 1;
2692 /* If that was an unconditional branch, forget the previous
2693 insn information. */
2694 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2696 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2697 prev_insn
.insn_mo
= &dummy_opcode
;
2700 prev_insn_fixp
[0] = NULL
;
2701 prev_insn_fixp
[1] = NULL
;
2702 prev_insn_fixp
[2] = NULL
;
2703 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2704 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2705 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2706 prev_insn_extended
= 0;
2708 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2710 /* We don't yet optimize a branch likely. What we should do
2711 is look at the target, copy the instruction found there
2712 into the delay slot, and increment the branch to jump to
2713 the next instruction. */
2715 /* Update the previous insn information. */
2716 prev_prev_insn
= *ip
;
2717 prev_insn
.insn_mo
= &dummy_opcode
;
2718 prev_insn_fixp
[0] = NULL
;
2719 prev_insn_fixp
[1] = NULL
;
2720 prev_insn_fixp
[2] = NULL
;
2721 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2722 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2723 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2724 prev_insn_extended
= 0;
2725 prev_insn_is_delay_slot
= 1;
2729 /* Update the previous insn information. */
2731 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2733 prev_prev_insn
= prev_insn
;
2736 /* Any time we see a branch, we always fill the delay slot
2737 immediately; since this insn is not a branch, we know it
2738 is not in a delay slot. */
2739 prev_insn_is_delay_slot
= 0;
2741 prev_insn_fixp
[0] = fixp
[0];
2742 prev_insn_fixp
[1] = fixp
[1];
2743 prev_insn_fixp
[2] = fixp
[2];
2744 prev_insn_reloc_type
[0] = reloc_type
[0];
2745 prev_insn_reloc_type
[1] = reloc_type
[1];
2746 prev_insn_reloc_type
[2] = reloc_type
[2];
2747 if (mips_opts
.mips16
)
2748 prev_insn_extended
= (ip
->use_extend
2749 || *reloc_type
> BFD_RELOC_UNUSED
);
2752 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2753 prev_insn_unreordered
= 0;
2754 prev_insn_frag
= frag_now
;
2755 prev_insn_where
= f
- frag_now
->fr_literal
;
2756 prev_insn_valid
= 1;
2758 else if (mips_relax
.sequence
!= 2)
2760 /* We need to record a bit of information even when we are not
2761 reordering, in order to determine the base address for mips16
2762 PC relative relocs. */
2763 prev_prev_insn
= prev_insn
;
2765 prev_insn_reloc_type
[0] = reloc_type
[0];
2766 prev_insn_reloc_type
[1] = reloc_type
[1];
2767 prev_insn_reloc_type
[2] = reloc_type
[2];
2768 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2769 prev_insn_unreordered
= 1;
2772 /* We just output an insn, so the next one doesn't have a label. */
2773 mips_clear_insn_labels ();
2776 /* This function forgets that there was any previous instruction or
2777 label. If PRESERVE is non-zero, it remembers enough information to
2778 know whether nops are needed before a noreorder section. */
2781 mips_no_prev_insn (int preserve
)
2785 prev_insn
.insn_mo
= &dummy_opcode
;
2786 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2787 prev_nop_frag
= NULL
;
2788 prev_nop_frag_holds
= 0;
2789 prev_nop_frag_required
= 0;
2790 prev_nop_frag_since
= 0;
2792 prev_insn_valid
= 0;
2793 prev_insn_is_delay_slot
= 0;
2794 prev_insn_unreordered
= 0;
2795 prev_insn_extended
= 0;
2796 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2797 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2798 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2799 prev_prev_insn_unreordered
= 0;
2800 mips_clear_insn_labels ();
2803 /* This function must be called whenever we turn on noreorder or emit
2804 something other than instructions. It inserts any NOPS which might
2805 be needed by the previous instruction, and clears the information
2806 kept for the previous instructions. The INSNS parameter is true if
2807 instructions are to follow. */
2810 mips_emit_delays (bfd_boolean insns
)
2812 if (! mips_opts
.noreorder
)
2817 if ((! mips_opts
.mips16
2818 && ((prev_insn
.insn_mo
->pinfo
2819 & (INSN_LOAD_COPROC_DELAY
2820 | INSN_COPROC_MOVE_DELAY
2821 | INSN_WRITE_COND_CODE
))
2822 && ! cop_interlocks
))
2823 || (! hilo_interlocks
2824 && (prev_insn
.insn_mo
->pinfo
2827 || (! mips_opts
.mips16
2828 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2829 && ! gpr_interlocks
)
2830 || (! mips_opts
.mips16
2831 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2832 && ! cop_mem_interlocks
))
2834 /* Itbl support may require additional care here. */
2836 if ((! mips_opts
.mips16
2837 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2838 && ! cop_interlocks
))
2839 || (! hilo_interlocks
2840 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2841 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2844 if (prev_insn_unreordered
)
2847 else if ((! mips_opts
.mips16
2848 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2849 && ! cop_interlocks
))
2850 || (! hilo_interlocks
2851 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2852 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2854 /* Itbl support may require additional care here. */
2855 if (! prev_prev_insn_unreordered
)
2859 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2862 const char *pn
= prev_insn
.insn_mo
->name
;
2863 if (strncmp (pn
, "macc", 4) == 0
2864 || strncmp (pn
, "dmacc", 5) == 0
2865 || strncmp (pn
, "dmult", 5) == 0
2866 || strstr (pn
, "div"))
2868 if (nops
< min_nops
)
2874 struct insn_label_list
*l
;
2878 /* Record the frag which holds the nop instructions, so
2879 that we can remove them if we don't need them. */
2880 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2881 prev_nop_frag
= frag_now
;
2882 prev_nop_frag_holds
= nops
;
2883 prev_nop_frag_required
= 0;
2884 prev_nop_frag_since
= 0;
2887 for (; nops
> 0; --nops
)
2892 /* Move on to a new frag, so that it is safe to simply
2893 decrease the size of prev_nop_frag. */
2894 frag_wane (frag_now
);
2898 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2902 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2903 symbol_set_frag (l
->label
, frag_now
);
2904 val
= (valueT
) frag_now_fix ();
2905 /* mips16 text labels are stored as odd. */
2906 if (mips_opts
.mips16
)
2908 S_SET_VALUE (l
->label
, val
);
2913 /* Mark instruction labels in mips16 mode. */
2915 mips16_mark_labels ();
2917 mips_no_prev_insn (insns
);
2920 /* Set up global variables for the start of a new macro. */
2925 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2926 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2927 && (prev_insn
.insn_mo
->pinfo
2928 & (INSN_UNCOND_BRANCH_DELAY
2929 | INSN_COND_BRANCH_DELAY
2930 | INSN_COND_BRANCH_LIKELY
)) != 0);
2933 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2934 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2935 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2938 macro_warning (relax_substateT subtype
)
2940 if (subtype
& RELAX_DELAY_SLOT
)
2941 return _("Macro instruction expanded into multiple instructions"
2942 " in a branch delay slot");
2943 else if (subtype
& RELAX_NOMACRO
)
2944 return _("Macro instruction expanded into multiple instructions");
2949 /* Finish up a macro. Emit warnings as appropriate. */
2954 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2956 relax_substateT subtype
;
2958 /* Set up the relaxation warning flags. */
2960 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2961 subtype
|= RELAX_SECOND_LONGER
;
2962 if (mips_opts
.warn_about_macros
)
2963 subtype
|= RELAX_NOMACRO
;
2964 if (mips_macro_warning
.delay_slot_p
)
2965 subtype
|= RELAX_DELAY_SLOT
;
2967 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2969 /* Either the macro has a single implementation or both
2970 implementations are longer than 4 bytes. Emit the
2972 const char *msg
= macro_warning (subtype
);
2978 /* One implementation might need a warning but the other
2979 definitely doesn't. */
2980 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2985 /* Read a macro's relocation codes from *ARGS and store them in *R.
2986 The first argument in *ARGS will be either the code for a single
2987 relocation or -1 followed by the three codes that make up a
2988 composite relocation. */
2991 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2995 next
= va_arg (*args
, int);
2997 r
[0] = (bfd_reloc_code_real_type
) next
;
2999 for (i
= 0; i
< 3; i
++)
3000 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3003 /* Build an instruction created by a macro expansion. This is passed
3004 a pointer to the count of instructions created so far, an
3005 expression, the name of the instruction to build, an operand format
3006 string, and corresponding arguments. */
3009 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3011 struct mips_cl_insn insn
;
3012 bfd_reloc_code_real_type r
[3];
3015 va_start (args
, fmt
);
3017 if (mips_opts
.mips16
)
3019 mips16_macro_build (ep
, name
, fmt
, args
);
3024 r
[0] = BFD_RELOC_UNUSED
;
3025 r
[1] = BFD_RELOC_UNUSED
;
3026 r
[2] = BFD_RELOC_UNUSED
;
3027 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3028 assert (insn
.insn_mo
);
3029 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3031 /* Search until we get a match for NAME. */
3034 /* It is assumed here that macros will never generate
3035 MDMX or MIPS-3D instructions. */
3036 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3037 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3038 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3040 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3042 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3046 assert (insn
.insn_mo
->name
);
3047 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3050 insn
.insn_opcode
= insn
.insn_mo
->match
;
3068 insn
.insn_opcode
|= (va_arg (args
, int)
3069 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3074 /* Note that in the macro case, these arguments are already
3075 in MSB form. (When handling the instruction in the
3076 non-macro case, these arguments are sizes from which
3077 MSB values must be calculated.) */
3078 insn
.insn_opcode
|= (va_arg (args
, int)
3079 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3085 /* Note that in the macro case, these arguments are already
3086 in MSBD form. (When handling the instruction in the
3087 non-macro case, these arguments are sizes from which
3088 MSBD values must be calculated.) */
3089 insn
.insn_opcode
|= (va_arg (args
, int)
3090 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3101 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3105 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3110 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3116 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3121 int tmp
= va_arg (args
, int);
3123 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3124 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3130 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3137 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3141 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3145 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3149 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3153 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3160 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3166 macro_read_relocs (&args
, r
);
3167 assert (*r
== BFD_RELOC_GPREL16
3168 || *r
== BFD_RELOC_MIPS_LITERAL
3169 || *r
== BFD_RELOC_MIPS_HIGHER
3170 || *r
== BFD_RELOC_HI16_S
3171 || *r
== BFD_RELOC_LO16
3172 || *r
== BFD_RELOC_MIPS_GOT16
3173 || *r
== BFD_RELOC_MIPS_CALL16
3174 || *r
== BFD_RELOC_MIPS_GOT_DISP
3175 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3176 || *r
== BFD_RELOC_MIPS_GOT_OFST
3177 || *r
== BFD_RELOC_MIPS_GOT_LO16
3178 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3182 macro_read_relocs (&args
, r
);
3184 && (ep
->X_op
== O_constant
3185 || (ep
->X_op
== O_symbol
3186 && (*r
== BFD_RELOC_MIPS_HIGHEST
3187 || *r
== BFD_RELOC_HI16_S
3188 || *r
== BFD_RELOC_HI16
3189 || *r
== BFD_RELOC_GPREL16
3190 || *r
== BFD_RELOC_MIPS_GOT_HI16
3191 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3195 assert (ep
!= NULL
);
3197 * This allows macro() to pass an immediate expression for
3198 * creating short branches without creating a symbol.
3199 * Note that the expression still might come from the assembly
3200 * input, in which case the value is not checked for range nor
3201 * is a relocation entry generated (yuck).
3203 if (ep
->X_op
== O_constant
)
3205 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3209 *r
= BFD_RELOC_16_PCREL_S2
;
3213 assert (ep
!= NULL
);
3214 *r
= BFD_RELOC_MIPS_JMP
;
3218 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3227 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3229 append_insn (&insn
, ep
, r
);
3233 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3236 struct mips_cl_insn insn
;
3237 bfd_reloc_code_real_type r
[3]
3238 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3240 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3241 assert (insn
.insn_mo
);
3242 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3244 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3245 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3248 assert (insn
.insn_mo
->name
);
3249 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3252 insn
.insn_opcode
= insn
.insn_mo
->match
;
3253 insn
.use_extend
= FALSE
;
3272 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3277 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3281 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3285 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3295 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3302 regno
= va_arg (args
, int);
3303 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3304 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3325 assert (ep
!= NULL
);
3327 if (ep
->X_op
!= O_constant
)
3328 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3331 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3332 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3335 *r
= BFD_RELOC_UNUSED
;
3341 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3348 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3350 append_insn (&insn
, ep
, r
);
3354 * Generate a "jalr" instruction with a relocation hint to the called
3355 * function. This occurs in NewABI PIC code.
3358 macro_build_jalr (expressionS
*ep
)
3367 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3369 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3370 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3374 * Generate a "lui" instruction.
3377 macro_build_lui (expressionS
*ep
, int regnum
)
3379 expressionS high_expr
;
3380 struct mips_cl_insn insn
;
3381 bfd_reloc_code_real_type r
[3]
3382 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3383 const char *name
= "lui";
3384 const char *fmt
= "t,u";
3386 assert (! mips_opts
.mips16
);
3390 if (high_expr
.X_op
== O_constant
)
3392 /* we can compute the instruction now without a relocation entry */
3393 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3395 *r
= BFD_RELOC_UNUSED
;
3399 assert (ep
->X_op
== O_symbol
);
3400 /* _gp_disp is a special case, used from s_cpload. _gp is used
3401 if mips_no_shared. */
3402 assert (mips_pic
== NO_PIC
3404 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3405 || (! mips_in_shared
3406 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp") == 0));
3407 *r
= BFD_RELOC_HI16_S
;
3410 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3411 assert (insn
.insn_mo
);
3412 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3413 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3415 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3416 if (*r
== BFD_RELOC_UNUSED
)
3418 insn
.insn_opcode
|= high_expr
.X_add_number
;
3419 append_insn (&insn
, NULL
, r
);
3422 append_insn (&insn
, &high_expr
, r
);
3425 /* Generate a sequence of instructions to do a load or store from a constant
3426 offset off of a base register (breg) into/from a target register (treg),
3427 using AT if necessary. */
3429 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3430 int treg
, int breg
, int dbl
)
3432 assert (ep
->X_op
== O_constant
);
3434 /* Sign-extending 32-bit constants makes their handling easier. */
3435 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3436 == ~((bfd_vma
) 0x7fffffff)))
3438 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3439 as_bad (_("constant too large"));
3441 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3445 /* Right now, this routine can only handle signed 32-bit constants. */
3446 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3447 as_warn (_("operand overflow"));
3449 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3451 /* Signed 16-bit offset will fit in the op. Easy! */
3452 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3456 /* 32-bit offset, need multiple instructions and AT, like:
3457 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3458 addu $tempreg,$tempreg,$breg
3459 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3460 to handle the complete offset. */
3461 macro_build_lui (ep
, AT
);
3462 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3463 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3466 as_warn (_("Macro used $at after \".set noat\""));
3471 * Generates code to set the $at register to true (one)
3472 * if reg is less than the immediate expression.
3475 set_at (int reg
, int unsignedp
)
3477 if (imm_expr
.X_op
== O_constant
3478 && imm_expr
.X_add_number
>= -0x8000
3479 && imm_expr
.X_add_number
< 0x8000)
3480 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3481 AT
, reg
, BFD_RELOC_LO16
);
3484 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3485 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3490 normalize_constant_expr (expressionS
*ex
)
3492 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3493 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3497 /* Warn if an expression is not a constant. */
3500 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3502 if (ex
->X_op
== O_big
)
3503 as_bad (_("unsupported large constant"));
3504 else if (ex
->X_op
!= O_constant
)
3505 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3507 normalize_constant_expr (ex
);
3510 /* Count the leading zeroes by performing a binary chop. This is a
3511 bulky bit of source, but performance is a LOT better for the
3512 majority of values than a simple loop to count the bits:
3513 for (lcnt = 0; (lcnt < 32); lcnt++)
3514 if ((v) & (1 << (31 - lcnt)))
3516 However it is not code size friendly, and the gain will drop a bit
3517 on certain cached systems.
3519 #define COUNT_TOP_ZEROES(v) \
3520 (((v) & ~0xffff) == 0 \
3521 ? ((v) & ~0xff) == 0 \
3522 ? ((v) & ~0xf) == 0 \
3523 ? ((v) & ~0x3) == 0 \
3524 ? ((v) & ~0x1) == 0 \
3529 : ((v) & ~0x7) == 0 \
3532 : ((v) & ~0x3f) == 0 \
3533 ? ((v) & ~0x1f) == 0 \
3536 : ((v) & ~0x7f) == 0 \
3539 : ((v) & ~0xfff) == 0 \
3540 ? ((v) & ~0x3ff) == 0 \
3541 ? ((v) & ~0x1ff) == 0 \
3544 : ((v) & ~0x7ff) == 0 \
3547 : ((v) & ~0x3fff) == 0 \
3548 ? ((v) & ~0x1fff) == 0 \
3551 : ((v) & ~0x7fff) == 0 \
3554 : ((v) & ~0xffffff) == 0 \
3555 ? ((v) & ~0xfffff) == 0 \
3556 ? ((v) & ~0x3ffff) == 0 \
3557 ? ((v) & ~0x1ffff) == 0 \
3560 : ((v) & ~0x7ffff) == 0 \
3563 : ((v) & ~0x3fffff) == 0 \
3564 ? ((v) & ~0x1fffff) == 0 \
3567 : ((v) & ~0x7fffff) == 0 \
3570 : ((v) & ~0xfffffff) == 0 \
3571 ? ((v) & ~0x3ffffff) == 0 \
3572 ? ((v) & ~0x1ffffff) == 0 \
3575 : ((v) & ~0x7ffffff) == 0 \
3578 : ((v) & ~0x3fffffff) == 0 \
3579 ? ((v) & ~0x1fffffff) == 0 \
3582 : ((v) & ~0x7fffffff) == 0 \
3587 * This routine generates the least number of instructions necessary to load
3588 * an absolute expression value into a register.
3591 load_register (int reg
, expressionS
*ep
, int dbl
)
3594 expressionS hi32
, lo32
;
3596 if (ep
->X_op
!= O_big
)
3598 assert (ep
->X_op
== O_constant
);
3600 /* Sign-extending 32-bit constants makes their handling easier. */
3601 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3602 == ~((bfd_vma
) 0x7fffffff)))
3604 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3605 as_bad (_("constant too large"));
3607 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3611 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3613 /* We can handle 16 bit signed values with an addiu to
3614 $zero. No need to ever use daddiu here, since $zero and
3615 the result are always correct in 32 bit mode. */
3616 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3619 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3621 /* We can handle 16 bit unsigned values with an ori to
3623 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3626 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3628 /* 32 bit values require an lui. */
3629 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3630 if ((ep
->X_add_number
& 0xffff) != 0)
3631 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3636 /* The value is larger than 32 bits. */
3638 if (HAVE_32BIT_GPRS
)
3640 as_bad (_("Number (0x%lx) larger than 32 bits"),
3641 (unsigned long) ep
->X_add_number
);
3642 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3646 if (ep
->X_op
!= O_big
)
3649 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3650 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3651 hi32
.X_add_number
&= 0xffffffff;
3653 lo32
.X_add_number
&= 0xffffffff;
3657 assert (ep
->X_add_number
> 2);
3658 if (ep
->X_add_number
== 3)
3659 generic_bignum
[3] = 0;
3660 else if (ep
->X_add_number
> 4)
3661 as_bad (_("Number larger than 64 bits"));
3662 lo32
.X_op
= O_constant
;
3663 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3664 hi32
.X_op
= O_constant
;
3665 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3668 if (hi32
.X_add_number
== 0)
3673 unsigned long hi
, lo
;
3675 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3677 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3679 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3682 if (lo32
.X_add_number
& 0x80000000)
3684 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3685 if (lo32
.X_add_number
& 0xffff)
3686 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3691 /* Check for 16bit shifted constant. We know that hi32 is
3692 non-zero, so start the mask on the first bit of the hi32
3697 unsigned long himask
, lomask
;
3701 himask
= 0xffff >> (32 - shift
);
3702 lomask
= (0xffff << shift
) & 0xffffffff;
3706 himask
= 0xffff << (shift
- 32);
3709 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3710 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3714 tmp
.X_op
= O_constant
;
3716 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3717 | (lo32
.X_add_number
>> shift
));
3719 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3720 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3721 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3722 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3727 while (shift
<= (64 - 16));
3729 /* Find the bit number of the lowest one bit, and store the
3730 shifted value in hi/lo. */
3731 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3732 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3736 while ((lo
& 1) == 0)
3741 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3747 while ((hi
& 1) == 0)
3756 /* Optimize if the shifted value is a (power of 2) - 1. */
3757 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3758 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3760 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3765 /* This instruction will set the register to be all
3767 tmp
.X_op
= O_constant
;
3768 tmp
.X_add_number
= (offsetT
) -1;
3769 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3773 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3774 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3776 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3777 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3782 /* Sign extend hi32 before calling load_register, because we can
3783 generally get better code when we load a sign extended value. */
3784 if ((hi32
.X_add_number
& 0x80000000) != 0)
3785 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3786 load_register (reg
, &hi32
, 0);
3789 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3793 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3801 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3803 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3804 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3810 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3814 mid16
.X_add_number
>>= 16;
3815 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3816 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3819 if ((lo32
.X_add_number
& 0xffff) != 0)
3820 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3824 load_delay_nop (void)
3826 if (!gpr_interlocks
)
3827 macro_build (NULL
, "nop", "");
3830 /* Load an address into a register. */
3833 load_address (int reg
, expressionS
*ep
, int *used_at
)
3835 if (ep
->X_op
!= O_constant
3836 && ep
->X_op
!= O_symbol
)
3838 as_bad (_("expression too complex"));
3839 ep
->X_op
= O_constant
;
3842 if (ep
->X_op
== O_constant
)
3844 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3848 if (mips_pic
== NO_PIC
)
3850 /* If this is a reference to a GP relative symbol, we want
3851 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3853 lui $reg,<sym> (BFD_RELOC_HI16_S)
3854 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3855 If we have an addend, we always use the latter form.
3857 With 64bit address space and a usable $at we want
3858 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3859 lui $at,<sym> (BFD_RELOC_HI16_S)
3860 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3861 daddiu $at,<sym> (BFD_RELOC_LO16)
3865 If $at is already in use, we use a path which is suboptimal
3866 on superscalar processors.
3867 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3868 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3870 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3872 daddiu $reg,<sym> (BFD_RELOC_LO16)
3874 if (HAVE_64BIT_ADDRESSES
)
3876 /* ??? We don't provide a GP-relative alternative for these macros.
3877 It used not to be possible with the original relaxation code,
3878 but it could be done now. */
3880 if (*used_at
== 0 && !mips_opts
.noat
)
3882 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3883 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3884 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3885 BFD_RELOC_MIPS_HIGHER
);
3886 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3887 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3888 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3893 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3894 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3895 BFD_RELOC_MIPS_HIGHER
);
3896 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3897 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3898 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3899 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3904 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3905 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3907 relax_start (ep
->X_add_symbol
);
3908 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3909 mips_gp_register
, BFD_RELOC_GPREL16
);
3912 macro_build_lui (ep
, reg
);
3913 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3914 reg
, reg
, BFD_RELOC_LO16
);
3915 if (mips_relax
.sequence
)
3919 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3923 /* If this is a reference to an external symbol, we want
3924 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3926 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3928 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3929 If there is a constant, it must be added in after.
3931 If we have NewABI, we want
3932 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3933 unless we're referencing a global symbol with a non-zero
3934 offset, in which case cst must be added separately. */
3937 if (ep
->X_add_number
)
3939 ex
.X_add_number
= ep
->X_add_number
;
3940 ep
->X_add_number
= 0;
3941 relax_start (ep
->X_add_symbol
);
3942 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3943 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3944 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3945 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3946 ex
.X_op
= O_constant
;
3947 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3948 reg
, reg
, BFD_RELOC_LO16
);
3949 ep
->X_add_number
= ex
.X_add_number
;
3952 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3953 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3954 if (mips_relax
.sequence
)
3959 ex
.X_add_number
= ep
->X_add_number
;
3960 ep
->X_add_number
= 0;
3961 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3962 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3964 relax_start (ep
->X_add_symbol
);
3966 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3970 if (ex
.X_add_number
!= 0)
3972 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3973 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3974 ex
.X_op
= O_constant
;
3975 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3976 reg
, reg
, BFD_RELOC_LO16
);
3980 else if (mips_pic
== SVR4_PIC
)
3984 /* This is the large GOT case. If this is a reference to an
3985 external symbol, we want
3986 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3988 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3990 Otherwise, for a reference to a local symbol in old ABI, we want
3991 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3993 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3994 If there is a constant, it must be added in after.
3996 In the NewABI, for local symbols, with or without offsets, we want:
3997 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3998 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4002 ex
.X_add_number
= ep
->X_add_number
;
4003 ep
->X_add_number
= 0;
4004 relax_start (ep
->X_add_symbol
);
4005 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4006 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4007 reg
, reg
, mips_gp_register
);
4008 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4009 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4010 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4011 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4012 else if (ex
.X_add_number
)
4014 ex
.X_op
= O_constant
;
4015 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4019 ep
->X_add_number
= ex
.X_add_number
;
4021 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4022 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4023 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4024 BFD_RELOC_MIPS_GOT_OFST
);
4029 ex
.X_add_number
= ep
->X_add_number
;
4030 ep
->X_add_number
= 0;
4031 relax_start (ep
->X_add_symbol
);
4032 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4033 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4034 reg
, reg
, mips_gp_register
);
4035 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4036 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4038 if (reg_needs_delay (mips_gp_register
))
4040 /* We need a nop before loading from $gp. This special
4041 check is required because the lui which starts the main
4042 instruction stream does not refer to $gp, and so will not
4043 insert the nop which may be required. */
4044 macro_build (NULL
, "nop", "");
4046 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4047 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4049 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4053 if (ex
.X_add_number
!= 0)
4055 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4056 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4057 ex
.X_op
= O_constant
;
4058 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4067 /* Move the contents of register SOURCE into register DEST. */
4070 move_register (int dest
, int source
)
4072 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4076 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4077 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4078 The two alternatives are:
4080 Global symbol Local sybmol
4081 ------------- ------------
4082 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4084 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4086 load_got_offset emits the first instruction and add_got_offset
4087 emits the second for a 16-bit offset or add_got_offset_hilo emits
4088 a sequence to add a 32-bit offset using a scratch register. */
4091 load_got_offset (int dest
, expressionS
*local
)
4096 global
.X_add_number
= 0;
4098 relax_start (local
->X_add_symbol
);
4099 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4100 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4102 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4103 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4108 add_got_offset (int dest
, expressionS
*local
)
4112 global
.X_op
= O_constant
;
4113 global
.X_op_symbol
= NULL
;
4114 global
.X_add_symbol
= NULL
;
4115 global
.X_add_number
= local
->X_add_number
;
4117 relax_start (local
->X_add_symbol
);
4118 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4119 dest
, dest
, BFD_RELOC_LO16
);
4121 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4126 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4129 int hold_mips_optimize
;
4131 global
.X_op
= O_constant
;
4132 global
.X_op_symbol
= NULL
;
4133 global
.X_add_symbol
= NULL
;
4134 global
.X_add_number
= local
->X_add_number
;
4136 relax_start (local
->X_add_symbol
);
4137 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4139 /* Set mips_optimize around the lui instruction to avoid
4140 inserting an unnecessary nop after the lw. */
4141 hold_mips_optimize
= mips_optimize
;
4143 macro_build_lui (&global
, tmp
);
4144 mips_optimize
= hold_mips_optimize
;
4145 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4148 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4153 * This routine implements the seemingly endless macro or synthesized
4154 * instructions and addressing modes in the mips assembly language. Many
4155 * of these macros are simple and are similar to each other. These could
4156 * probably be handled by some kind of table or grammar approach instead of
4157 * this verbose method. Others are not simple macros but are more like
4158 * optimizing code generation.
4159 * One interesting optimization is when several store macros appear
4160 * consecutively that would load AT with the upper half of the same address.
4161 * The ensuing load upper instructions are ommited. This implies some kind
4162 * of global optimization. We currently only optimize within a single macro.
4163 * For many of the load and store macros if the address is specified as a
4164 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4165 * first load register 'at' with zero and use it as the base register. The
4166 * mips assembler simply uses register $zero. Just one tiny optimization
4170 macro (struct mips_cl_insn
*ip
)
4172 register int treg
, sreg
, dreg
, breg
;
4188 bfd_reloc_code_real_type r
;
4189 int hold_mips_optimize
;
4191 assert (! mips_opts
.mips16
);
4193 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4194 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4195 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4196 mask
= ip
->insn_mo
->mask
;
4198 expr1
.X_op
= O_constant
;
4199 expr1
.X_op_symbol
= NULL
;
4200 expr1
.X_add_symbol
= NULL
;
4201 expr1
.X_add_number
= 1;
4213 mips_emit_delays (TRUE
);
4214 ++mips_opts
.noreorder
;
4215 mips_any_noreorder
= 1;
4217 expr1
.X_add_number
= 8;
4218 macro_build (&expr1
, "bgez", "s,p", sreg
);
4220 macro_build (NULL
, "nop", "", 0);
4222 move_register (dreg
, sreg
);
4223 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4225 --mips_opts
.noreorder
;
4246 if (imm_expr
.X_op
== O_constant
4247 && imm_expr
.X_add_number
>= -0x8000
4248 && imm_expr
.X_add_number
< 0x8000)
4250 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4253 load_register (AT
, &imm_expr
, dbl
);
4254 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4273 if (imm_expr
.X_op
== O_constant
4274 && imm_expr
.X_add_number
>= 0
4275 && imm_expr
.X_add_number
< 0x10000)
4277 if (mask
!= M_NOR_I
)
4278 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4281 macro_build (&imm_expr
, "ori", "t,r,i",
4282 treg
, sreg
, BFD_RELOC_LO16
);
4283 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4288 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4289 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4306 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4308 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4311 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4312 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4320 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4325 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4328 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4329 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4335 /* check for > max integer */
4336 maxnum
= 0x7fffffff;
4337 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4344 if (imm_expr
.X_op
== O_constant
4345 && imm_expr
.X_add_number
>= maxnum
4346 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4349 /* result is always false */
4351 macro_build (NULL
, "nop", "", 0);
4353 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4356 if (imm_expr
.X_op
!= O_constant
)
4357 as_bad (_("Unsupported large constant"));
4358 ++imm_expr
.X_add_number
;
4362 if (mask
== M_BGEL_I
)
4364 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4366 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4369 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4371 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4374 maxnum
= 0x7fffffff;
4375 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4382 maxnum
= - maxnum
- 1;
4383 if (imm_expr
.X_op
== O_constant
4384 && imm_expr
.X_add_number
<= maxnum
4385 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4388 /* result is always true */
4389 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4390 macro_build (&offset_expr
, "b", "p");
4394 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4404 macro_build (&offset_expr
, likely
? "beql" : "beq",
4408 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4409 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4417 && imm_expr
.X_op
== O_constant
4418 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4420 if (imm_expr
.X_op
!= O_constant
)
4421 as_bad (_("Unsupported large constant"));
4422 ++imm_expr
.X_add_number
;
4426 if (mask
== M_BGEUL_I
)
4428 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4430 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4432 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4437 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4445 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4450 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4453 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4454 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4462 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4468 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4469 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4477 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4482 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4485 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4486 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4492 maxnum
= 0x7fffffff;
4493 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4500 if (imm_expr
.X_op
== O_constant
4501 && imm_expr
.X_add_number
>= maxnum
4502 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4504 if (imm_expr
.X_op
!= O_constant
)
4505 as_bad (_("Unsupported large constant"));
4506 ++imm_expr
.X_add_number
;
4510 if (mask
== M_BLTL_I
)
4512 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4514 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4517 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4519 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4523 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4531 macro_build (&offset_expr
, likely
? "beql" : "beq",
4537 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4538 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4546 && imm_expr
.X_op
== O_constant
4547 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4549 if (imm_expr
.X_op
!= O_constant
)
4550 as_bad (_("Unsupported large constant"));
4551 ++imm_expr
.X_add_number
;
4555 if (mask
== M_BLTUL_I
)
4557 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4559 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4561 macro_build (&offset_expr
, likely
? "beql" : "beq",
4566 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4574 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4579 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4582 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4583 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4593 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4597 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4598 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4606 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4608 as_bad (_("Unsupported large constant"));
4613 pos
= (unsigned long) imm_expr
.X_add_number
;
4614 size
= (unsigned long) imm2_expr
.X_add_number
;
4619 as_bad (_("Improper position (%lu)"), pos
);
4622 if (size
== 0 || size
> 64
4623 || (pos
+ size
- 1) > 63)
4625 as_bad (_("Improper extract size (%lu, position %lu)"),
4630 if (size
<= 32 && pos
< 32)
4635 else if (size
<= 32)
4645 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4654 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4656 as_bad (_("Unsupported large constant"));
4661 pos
= (unsigned long) imm_expr
.X_add_number
;
4662 size
= (unsigned long) imm2_expr
.X_add_number
;
4667 as_bad (_("Improper position (%lu)"), pos
);
4670 if (size
== 0 || size
> 64
4671 || (pos
+ size
- 1) > 63)
4673 as_bad (_("Improper insert size (%lu, position %lu)"),
4678 if (pos
< 32 && (pos
+ size
- 1) < 32)
4693 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4710 as_warn (_("Divide by zero."));
4712 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4714 macro_build (NULL
, "break", "c", 7);
4718 mips_emit_delays (TRUE
);
4719 ++mips_opts
.noreorder
;
4720 mips_any_noreorder
= 1;
4723 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4724 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4728 expr1
.X_add_number
= 8;
4729 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4730 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4731 macro_build (NULL
, "break", "c", 7);
4733 expr1
.X_add_number
= -1;
4734 load_register (AT
, &expr1
, dbl
);
4735 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4736 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4739 expr1
.X_add_number
= 1;
4740 load_register (AT
, &expr1
, dbl
);
4741 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4745 expr1
.X_add_number
= 0x80000000;
4746 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4750 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4751 /* We want to close the noreorder block as soon as possible, so
4752 that later insns are available for delay slot filling. */
4753 --mips_opts
.noreorder
;
4757 expr1
.X_add_number
= 8;
4758 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4759 macro_build (NULL
, "nop", "", 0);
4761 /* We want to close the noreorder block as soon as possible, so
4762 that later insns are available for delay slot filling. */
4763 --mips_opts
.noreorder
;
4765 macro_build (NULL
, "break", "c", 6);
4767 macro_build (NULL
, s
, "d", dreg
);
4806 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4808 as_warn (_("Divide by zero."));
4810 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4812 macro_build (NULL
, "break", "c", 7);
4815 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4817 if (strcmp (s2
, "mflo") == 0)
4818 move_register (dreg
, sreg
);
4820 move_register (dreg
, 0);
4823 if (imm_expr
.X_op
== O_constant
4824 && imm_expr
.X_add_number
== -1
4825 && s
[strlen (s
) - 1] != 'u')
4827 if (strcmp (s2
, "mflo") == 0)
4829 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4832 move_register (dreg
, 0);
4836 load_register (AT
, &imm_expr
, dbl
);
4837 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4838 macro_build (NULL
, s2
, "d", dreg
);
4857 mips_emit_delays (TRUE
);
4858 ++mips_opts
.noreorder
;
4859 mips_any_noreorder
= 1;
4862 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4863 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4864 /* We want to close the noreorder block as soon as possible, so
4865 that later insns are available for delay slot filling. */
4866 --mips_opts
.noreorder
;
4870 expr1
.X_add_number
= 8;
4871 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4872 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4874 /* We want to close the noreorder block as soon as possible, so
4875 that later insns are available for delay slot filling. */
4876 --mips_opts
.noreorder
;
4877 macro_build (NULL
, "break", "c", 7);
4879 macro_build (NULL
, s2
, "d", dreg
);
4891 /* Load the address of a symbol into a register. If breg is not
4892 zero, we then add a base register to it. */
4894 if (dbl
&& HAVE_32BIT_GPRS
)
4895 as_warn (_("dla used to load 32-bit register"));
4897 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4898 as_warn (_("la used to load 64-bit address"));
4900 if (offset_expr
.X_op
== O_constant
4901 && offset_expr
.X_add_number
>= -0x8000
4902 && offset_expr
.X_add_number
< 0x8000)
4904 macro_build (&offset_expr
,
4905 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4906 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4910 if (!mips_opts
.noat
&& (treg
== breg
))
4920 if (offset_expr
.X_op
!= O_symbol
4921 && offset_expr
.X_op
!= O_constant
)
4923 as_bad (_("expression too complex"));
4924 offset_expr
.X_op
= O_constant
;
4927 if (offset_expr
.X_op
== O_constant
)
4928 load_register (tempreg
, &offset_expr
,
4930 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4931 : HAVE_64BIT_ADDRESSES
));
4932 else if (mips_pic
== NO_PIC
)
4934 /* If this is a reference to a GP relative symbol, we want
4935 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4937 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4938 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4939 If we have a constant, we need two instructions anyhow,
4940 so we may as well always use the latter form.
4942 With 64bit address space and a usable $at we want
4943 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4944 lui $at,<sym> (BFD_RELOC_HI16_S)
4945 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4946 daddiu $at,<sym> (BFD_RELOC_LO16)
4948 daddu $tempreg,$tempreg,$at
4950 If $at is already in use, we use a path which is suboptimal
4951 on superscalar processors.
4952 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4953 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4955 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4957 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4959 if (HAVE_64BIT_ADDRESSES
)
4961 /* ??? We don't provide a GP-relative alternative for
4962 these macros. It used not to be possible with the
4963 original relaxation code, but it could be done now. */
4965 if (used_at
== 0 && !mips_opts
.noat
)
4967 macro_build (&offset_expr
, "lui", "t,u",
4968 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4969 macro_build (&offset_expr
, "lui", "t,u",
4970 AT
, BFD_RELOC_HI16_S
);
4971 macro_build (&offset_expr
, "daddiu", "t,r,j",
4972 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4973 macro_build (&offset_expr
, "daddiu", "t,r,j",
4974 AT
, AT
, BFD_RELOC_LO16
);
4975 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4976 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4981 macro_build (&offset_expr
, "lui", "t,u",
4982 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4983 macro_build (&offset_expr
, "daddiu", "t,r,j",
4984 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4985 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4986 macro_build (&offset_expr
, "daddiu", "t,r,j",
4987 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4988 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4989 macro_build (&offset_expr
, "daddiu", "t,r,j",
4990 tempreg
, tempreg
, BFD_RELOC_LO16
);
4995 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4996 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4998 relax_start (offset_expr
.X_add_symbol
);
4999 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5000 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5003 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5004 as_bad (_("offset too large"));
5005 macro_build_lui (&offset_expr
, tempreg
);
5006 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5007 tempreg
, tempreg
, BFD_RELOC_LO16
);
5008 if (mips_relax
.sequence
)
5012 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5014 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5016 /* If this is a reference to an external symbol, and there
5017 is no constant, we want
5018 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5019 or for lca or if tempreg is PIC_CALL_REG
5020 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5021 For a local symbol, we want
5022 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5024 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5026 If we have a small constant, and this is a reference to
5027 an external symbol, we want
5028 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5030 addiu $tempreg,$tempreg,<constant>
5031 For a local symbol, we want the same instruction
5032 sequence, but we output a BFD_RELOC_LO16 reloc on the
5035 If we have a large constant, and this is a reference to
5036 an external symbol, we want
5037 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5038 lui $at,<hiconstant>
5039 addiu $at,$at,<loconstant>
5040 addu $tempreg,$tempreg,$at
5041 For a local symbol, we want the same instruction
5042 sequence, but we output a BFD_RELOC_LO16 reloc on the
5046 if (offset_expr
.X_add_number
== 0)
5048 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5049 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5051 relax_start (offset_expr
.X_add_symbol
);
5052 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5053 lw_reloc_type
, mips_gp_register
);
5056 /* We're going to put in an addu instruction using
5057 tempreg, so we may as well insert the nop right
5062 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5063 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5065 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5066 tempreg
, tempreg
, BFD_RELOC_LO16
);
5068 /* FIXME: If breg == 0, and the next instruction uses
5069 $tempreg, then if this variant case is used an extra
5070 nop will be generated. */
5072 else if (offset_expr
.X_add_number
>= -0x8000
5073 && offset_expr
.X_add_number
< 0x8000)
5075 load_got_offset (tempreg
, &offset_expr
);
5077 add_got_offset (tempreg
, &offset_expr
);
5081 expr1
.X_add_number
= offset_expr
.X_add_number
;
5082 offset_expr
.X_add_number
=
5083 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5084 load_got_offset (tempreg
, &offset_expr
);
5085 offset_expr
.X_add_number
= expr1
.X_add_number
;
5086 /* If we are going to add in a base register, and the
5087 target register and the base register are the same,
5088 then we are using AT as a temporary register. Since
5089 we want to load the constant into AT, we add our
5090 current AT (from the global offset table) and the
5091 register into the register now, and pretend we were
5092 not using a base register. */
5096 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5101 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5105 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5107 int add_breg_early
= 0;
5109 /* If this is a reference to an external, and there is no
5110 constant, or local symbol (*), with or without a
5112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5113 or for lca or if tempreg is PIC_CALL_REG
5114 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5116 If we have a small constant, and this is a reference to
5117 an external symbol, we want
5118 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5119 addiu $tempreg,$tempreg,<constant>
5121 If we have a large constant, and this is a reference to
5122 an external symbol, we want
5123 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5124 lui $at,<hiconstant>
5125 addiu $at,$at,<loconstant>
5126 addu $tempreg,$tempreg,$at
5128 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5129 local symbols, even though it introduces an additional
5132 if (offset_expr
.X_add_number
)
5134 expr1
.X_add_number
= offset_expr
.X_add_number
;
5135 offset_expr
.X_add_number
= 0;
5137 relax_start (offset_expr
.X_add_symbol
);
5138 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5139 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5141 if (expr1
.X_add_number
>= -0x8000
5142 && expr1
.X_add_number
< 0x8000)
5144 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5145 tempreg
, tempreg
, BFD_RELOC_LO16
);
5147 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5151 /* If we are going to add in a base register, and the
5152 target register and the base register are the same,
5153 then we are using AT as a temporary register. Since
5154 we want to load the constant into AT, we add our
5155 current AT (from the global offset table) and the
5156 register into the register now, and pretend we were
5157 not using a base register. */
5162 assert (tempreg
== AT
);
5163 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5169 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5170 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5176 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5179 offset_expr
.X_add_number
= expr1
.X_add_number
;
5181 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5182 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5185 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5186 treg
, tempreg
, breg
);
5192 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5194 relax_start (offset_expr
.X_add_symbol
);
5195 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5196 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5198 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5199 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5204 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5205 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5208 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5211 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5212 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5213 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5215 /* This is the large GOT case. If this is a reference to an
5216 external symbol, and there is no constant, we want
5217 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5218 addu $tempreg,$tempreg,$gp
5219 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5220 or for lca or if tempreg is PIC_CALL_REG
5221 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5222 addu $tempreg,$tempreg,$gp
5223 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5224 For a local symbol, we want
5225 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5227 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5229 If we have a small constant, and this is a reference to
5230 an external symbol, we want
5231 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5232 addu $tempreg,$tempreg,$gp
5233 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5235 addiu $tempreg,$tempreg,<constant>
5236 For a local symbol, we want
5237 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5239 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5241 If we have a large constant, and this is a reference to
5242 an external symbol, we want
5243 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5244 addu $tempreg,$tempreg,$gp
5245 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5246 lui $at,<hiconstant>
5247 addiu $at,$at,<loconstant>
5248 addu $tempreg,$tempreg,$at
5249 For a local symbol, we want
5250 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5251 lui $at,<hiconstant>
5252 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5253 addu $tempreg,$tempreg,$at
5256 expr1
.X_add_number
= offset_expr
.X_add_number
;
5257 offset_expr
.X_add_number
= 0;
5258 relax_start (offset_expr
.X_add_symbol
);
5259 gpdelay
= reg_needs_delay (mips_gp_register
);
5260 if (expr1
.X_add_number
== 0 && breg
== 0
5261 && (call
|| tempreg
== PIC_CALL_REG
))
5263 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5264 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5266 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5267 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5268 tempreg
, tempreg
, mips_gp_register
);
5269 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5270 tempreg
, lw_reloc_type
, tempreg
);
5271 if (expr1
.X_add_number
== 0)
5275 /* We're going to put in an addu instruction using
5276 tempreg, so we may as well insert the nop right
5281 else if (expr1
.X_add_number
>= -0x8000
5282 && expr1
.X_add_number
< 0x8000)
5285 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5286 tempreg
, tempreg
, BFD_RELOC_LO16
);
5292 /* If we are going to add in a base register, and the
5293 target register and the base register are the same,
5294 then we are using AT as a temporary register. Since
5295 we want to load the constant into AT, we add our
5296 current AT (from the global offset table) and the
5297 register into the register now, and pretend we were
5298 not using a base register. */
5303 assert (tempreg
== AT
);
5305 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5310 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5311 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5315 offset_expr
.X_add_number
=
5316 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5321 /* This is needed because this instruction uses $gp, but
5322 the first instruction on the main stream does not. */
5323 macro_build (NULL
, "nop", "");
5326 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5327 local_reloc_type
, mips_gp_register
);
5328 if (expr1
.X_add_number
>= -0x8000
5329 && expr1
.X_add_number
< 0x8000)
5332 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5333 tempreg
, tempreg
, BFD_RELOC_LO16
);
5334 /* FIXME: If add_number is 0, and there was no base
5335 register, the external symbol case ended with a load,
5336 so if the symbol turns out to not be external, and
5337 the next instruction uses tempreg, an unnecessary nop
5338 will be inserted. */
5344 /* We must add in the base register now, as in the
5345 external symbol case. */
5346 assert (tempreg
== AT
);
5348 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5351 /* We set breg to 0 because we have arranged to add
5352 it in in both cases. */
5356 macro_build_lui (&expr1
, AT
);
5357 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5358 AT
, AT
, BFD_RELOC_LO16
);
5359 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5360 tempreg
, tempreg
, AT
);
5364 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5366 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5367 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5368 int add_breg_early
= 0;
5370 /* This is the large GOT case. If this is a reference to an
5371 external symbol, and there is no constant, we want
5372 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5373 add $tempreg,$tempreg,$gp
5374 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5375 or for lca or if tempreg is PIC_CALL_REG
5376 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5377 add $tempreg,$tempreg,$gp
5378 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5380 If we have a small constant, and this is a reference to
5381 an external symbol, we want
5382 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5383 add $tempreg,$tempreg,$gp
5384 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5385 addi $tempreg,$tempreg,<constant>
5387 If we have a large constant, and this is a reference to
5388 an external symbol, we want
5389 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5390 addu $tempreg,$tempreg,$gp
5391 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5392 lui $at,<hiconstant>
5393 addi $at,$at,<loconstant>
5394 add $tempreg,$tempreg,$at
5396 If we have NewABI, and we know it's a local symbol, we want
5397 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5398 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5399 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5401 relax_start (offset_expr
.X_add_symbol
);
5403 expr1
.X_add_number
= offset_expr
.X_add_number
;
5404 offset_expr
.X_add_number
= 0;
5406 if (expr1
.X_add_number
== 0 && breg
== 0
5407 && (call
|| tempreg
== PIC_CALL_REG
))
5409 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5410 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5412 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5414 tempreg
, tempreg
, mips_gp_register
);
5415 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5416 tempreg
, lw_reloc_type
, tempreg
);
5418 if (expr1
.X_add_number
== 0)
5420 else if (expr1
.X_add_number
>= -0x8000
5421 && expr1
.X_add_number
< 0x8000)
5423 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5424 tempreg
, tempreg
, BFD_RELOC_LO16
);
5426 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5430 /* If we are going to add in a base register, and the
5431 target register and the base register are the same,
5432 then we are using AT as a temporary register. Since
5433 we want to load the constant into AT, we add our
5434 current AT (from the global offset table) and the
5435 register into the register now, and pretend we were
5436 not using a base register. */
5441 assert (tempreg
== AT
);
5442 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5448 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5449 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5454 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5457 offset_expr
.X_add_number
= expr1
.X_add_number
;
5458 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5459 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5460 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5461 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5464 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5465 treg
, tempreg
, breg
);
5478 if (mips_pic
== NO_PIC
)
5479 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5481 s
= ADDRESS_ADD_INSN
;
5483 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5492 /* The j instruction may not be used in PIC code, since it
5493 requires an absolute address. We convert it to a b
5495 if (mips_pic
== NO_PIC
)
5496 macro_build (&offset_expr
, "j", "a");
5498 macro_build (&offset_expr
, "b", "p");
5501 /* The jal instructions must be handled as macros because when
5502 generating PIC code they expand to multi-instruction
5503 sequences. Normally they are simple instructions. */
5508 if (mips_pic
== NO_PIC
)
5509 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5510 else if (mips_pic
== SVR4_PIC
)
5512 if (sreg
!= PIC_CALL_REG
)
5513 as_warn (_("MIPS PIC call to register other than $25"));
5515 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5518 if (mips_cprestore_offset
< 0)
5519 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5522 if (! mips_frame_reg_valid
)
5524 as_warn (_("No .frame pseudo-op used in PIC code"));
5525 /* Quiet this warning. */
5526 mips_frame_reg_valid
= 1;
5528 if (! mips_cprestore_valid
)
5530 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5531 /* Quiet this warning. */
5532 mips_cprestore_valid
= 1;
5534 expr1
.X_add_number
= mips_cprestore_offset
;
5535 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5538 HAVE_64BIT_ADDRESSES
);
5548 if (mips_pic
== NO_PIC
)
5549 macro_build (&offset_expr
, "jal", "a");
5550 else if (mips_pic
== SVR4_PIC
)
5552 /* If this is a reference to an external symbol, and we are
5553 using a small GOT, we want
5554 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5558 lw $gp,cprestore($sp)
5559 The cprestore value is set using the .cprestore
5560 pseudo-op. If we are using a big GOT, we want
5561 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5563 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5567 lw $gp,cprestore($sp)
5568 If the symbol is not external, we want
5569 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5571 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5574 lw $gp,cprestore($sp)
5576 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5577 sequences above, minus nops, unless the symbol is local,
5578 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5584 relax_start (offset_expr
.X_add_symbol
);
5585 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5586 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5589 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5590 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5596 relax_start (offset_expr
.X_add_symbol
);
5597 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5598 BFD_RELOC_MIPS_CALL_HI16
);
5599 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5600 PIC_CALL_REG
, mips_gp_register
);
5601 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5602 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5606 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5608 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5609 PIC_CALL_REG
, PIC_CALL_REG
,
5610 BFD_RELOC_MIPS_GOT_OFST
);
5614 macro_build_jalr (&offset_expr
);
5618 relax_start (offset_expr
.X_add_symbol
);
5621 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5622 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5631 gpdelay
= reg_needs_delay (mips_gp_register
);
5632 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5633 BFD_RELOC_MIPS_CALL_HI16
);
5634 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5635 PIC_CALL_REG
, mips_gp_register
);
5636 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5637 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5642 macro_build (NULL
, "nop", "");
5644 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5645 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5648 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5649 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5651 macro_build_jalr (&offset_expr
);
5653 if (mips_cprestore_offset
< 0)
5654 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5657 if (! mips_frame_reg_valid
)
5659 as_warn (_("No .frame pseudo-op used in PIC code"));
5660 /* Quiet this warning. */
5661 mips_frame_reg_valid
= 1;
5663 if (! mips_cprestore_valid
)
5665 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5666 /* Quiet this warning. */
5667 mips_cprestore_valid
= 1;
5669 if (mips_opts
.noreorder
)
5670 macro_build (NULL
, "nop", "");
5671 expr1
.X_add_number
= mips_cprestore_offset
;
5672 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5675 HAVE_64BIT_ADDRESSES
);
5701 /* Itbl support may require additional care here. */
5706 /* Itbl support may require additional care here. */
5711 /* Itbl support may require additional care here. */
5716 /* Itbl support may require additional care here. */
5728 if (mips_opts
.arch
== CPU_R4650
)
5730 as_bad (_("opcode not supported on this processor"));
5734 /* Itbl support may require additional care here. */
5739 /* Itbl support may require additional care here. */
5744 /* Itbl support may require additional care here. */
5764 /* XXX Why don't we try to use AT for all expansions? */
5765 if (!mips_opts
.noat
&& (breg
== treg
|| coproc
|| lr
))
5770 else if (breg
== treg
5771 && (offset_expr
.X_op
!= O_constant
5772 || (offset_expr
.X_add_number
> 0x7fff
5773 || offset_expr
.X_add_number
< -0x8000)))
5775 as_bad(_("load expansion needs $at register"));
5794 /* Itbl support may require additional care here. */
5799 /* Itbl support may require additional care here. */
5804 /* Itbl support may require additional care here. */
5809 /* Itbl support may require additional care here. */
5825 if (mips_opts
.arch
== CPU_R4650
)
5827 as_bad (_("opcode not supported on this processor"));
5832 /* Itbl support may require additional care here. */
5836 /* Itbl support may require additional care here. */
5841 /* Itbl support may require additional care here. */
5850 if (!mips_opts
.noat
)
5855 else if (breg
== treg
5856 && (offset_expr
.X_op
!= O_constant
5857 || (offset_expr
.X_add_number
> 0x7fff
5858 || offset_expr
.X_add_number
< -0x8000)))
5860 as_bad(_("store expansion needs $at register"));
5868 /* Itbl support may require additional care here. */
5869 if (mask
== M_LWC1_AB
5870 || mask
== M_SWC1_AB
5871 || mask
== M_LDC1_AB
5872 || mask
== M_SDC1_AB
5881 /* Sign-extending 32-bit constants makes their handling easier.
5882 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5884 if ((! HAVE_64BIT_ADDRESSES
5885 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5886 && (offset_expr
.X_op
== O_constant
)
5887 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5888 == ~((bfd_vma
) 0x7fffffff)))
5890 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5891 as_bad (_("constant too large"));
5893 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5894 ^ 0x80000000) - 0x80000000);
5897 if (offset_expr
.X_op
!= O_constant
5898 && offset_expr
.X_op
!= O_symbol
)
5900 as_bad (_("expression too complex"));
5901 offset_expr
.X_op
= O_constant
;
5904 /* A constant expression in PIC code can be handled just as it
5905 is in non PIC code. */
5906 if (mips_pic
== NO_PIC
5907 || offset_expr
.X_op
== O_constant
)
5909 /* If this is a reference to a GP relative symbol, and there
5910 is no base register, we want
5911 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5912 Otherwise, if there is no base register, we want
5913 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5914 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5915 If we have a constant, we need two instructions anyhow,
5916 so we always use the latter form.
5918 If we have a base register, and this is a reference to a
5919 GP relative symbol, we want
5920 addu $tempreg,$breg,$gp
5921 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5923 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5924 addu $tempreg,$tempreg,$breg
5925 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5926 With a constant we always use the latter case.
5928 With 64bit address space and no base register and $at usable,
5930 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5931 lui $at,<sym> (BFD_RELOC_HI16_S)
5932 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5935 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5936 If we have a base register, we want
5937 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5938 lui $at,<sym> (BFD_RELOC_HI16_S)
5939 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5943 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5945 Without $at we can't generate the optimal path for superscalar
5946 processors here since this would require two temporary registers.
5947 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5948 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5950 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5952 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5953 If we have a base register, we want
5954 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5955 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5957 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5959 daddu $tempreg,$tempreg,$breg
5960 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5962 If we have 64-bit addresses, as an optimization, for
5963 addresses which are 32-bit constants (e.g. kseg0/kseg1
5964 addresses) we fall back to the 32-bit address generation
5965 mechanism since it is more efficient. Note that due to
5966 the signed offset used by memory operations, the 32-bit
5967 range is shifted down by 32768 here. This code should
5968 probably attempt to generate 64-bit constants more
5969 efficiently in general.
5971 As an extension for architectures with 64-bit registers,
5972 we don't truncate 64-bit addresses given as literal
5973 constants down to 32 bits, to support existing practice
5974 in the mips64 Linux (the kernel), that compiles source
5975 files with -mabi=64, assembling them as o32 or n32 (with
5976 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5977 the whole kernel is loaded into a memory region that is
5978 addressable with sign-extended 32-bit addresses, it is
5979 wasteful to compute the upper 32 bits of every
5980 non-literal address, that takes more space and time.
5981 Some day this should probably be implemented as an
5982 assembler option, such that the kernel doesn't have to
5983 use such ugly hacks, even though it will still have to
5984 end up converting the binary to ELF32 for a number of
5985 platforms whose boot loaders don't support ELF64
5987 if ((HAVE_64BIT_ADDRESSES
5988 && ! (offset_expr
.X_op
== O_constant
5989 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5991 && offset_expr
.X_op
== O_constant
5992 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5994 /* ??? We don't provide a GP-relative alternative for
5995 these macros. It used not to be possible with the
5996 original relaxation code, but it could be done now. */
5998 if (used_at
== 0 && !mips_opts
.noat
)
6000 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6001 BFD_RELOC_MIPS_HIGHEST
);
6002 macro_build (&offset_expr
, "lui", "t,u", AT
,
6004 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6005 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6007 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6008 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6009 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6010 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6016 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6017 BFD_RELOC_MIPS_HIGHEST
);
6018 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6019 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6020 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6021 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6022 tempreg
, BFD_RELOC_HI16_S
);
6023 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6025 macro_build (NULL
, "daddu", "d,v,t",
6026 tempreg
, tempreg
, breg
);
6027 macro_build (&offset_expr
, s
, fmt
, treg
,
6028 BFD_RELOC_LO16
, tempreg
);
6037 if (offset_expr
.X_op
== O_constant
6038 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6039 as_bad (_("load/store address overflow (max 32 bits)"));
6043 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6044 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6046 relax_start (offset_expr
.X_add_symbol
);
6047 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6051 macro_build_lui (&offset_expr
, tempreg
);
6052 macro_build (&offset_expr
, s
, fmt
, treg
,
6053 BFD_RELOC_LO16
, tempreg
);
6054 if (mips_relax
.sequence
)
6059 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6060 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6062 relax_start (offset_expr
.X_add_symbol
);
6063 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6064 tempreg
, breg
, mips_gp_register
);
6065 macro_build (&offset_expr
, s
, fmt
, treg
,
6066 BFD_RELOC_GPREL16
, tempreg
);
6069 macro_build_lui (&offset_expr
, tempreg
);
6070 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6071 tempreg
, tempreg
, breg
);
6072 macro_build (&offset_expr
, s
, fmt
, treg
,
6073 BFD_RELOC_LO16
, tempreg
);
6074 if (mips_relax
.sequence
)
6078 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6080 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6082 /* If this is a reference to an external symbol, we want
6083 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6085 <op> $treg,0($tempreg)
6087 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6089 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6090 <op> $treg,0($tempreg)
6093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6094 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6096 If there is a base register, we add it to $tempreg before
6097 the <op>. If there is a constant, we stick it in the
6098 <op> instruction. We don't handle constants larger than
6099 16 bits, because we have no way to load the upper 16 bits
6100 (actually, we could handle them for the subset of cases
6101 in which we are not using $at). */
6102 assert (offset_expr
.X_op
== O_symbol
);
6105 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6106 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6108 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6109 tempreg
, tempreg
, breg
);
6110 macro_build (&offset_expr
, s
, fmt
, treg
,
6111 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6118 expr1
.X_add_number
= offset_expr
.X_add_number
;
6119 offset_expr
.X_add_number
= 0;
6120 if (expr1
.X_add_number
< -0x8000
6121 || expr1
.X_add_number
>= 0x8000)
6122 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6123 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6124 lw_reloc_type
, mips_gp_register
);
6126 relax_start (offset_expr
.X_add_symbol
);
6128 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6129 tempreg
, BFD_RELOC_LO16
);
6132 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6133 tempreg
, tempreg
, breg
);
6134 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6136 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6140 /* If this is a reference to an external symbol, we want
6141 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6142 addu $tempreg,$tempreg,$gp
6143 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6144 <op> $treg,0($tempreg)
6146 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6148 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6149 <op> $treg,0($tempreg)
6150 If there is a base register, we add it to $tempreg before
6151 the <op>. If there is a constant, we stick it in the
6152 <op> instruction. We don't handle constants larger than
6153 16 bits, because we have no way to load the upper 16 bits
6154 (actually, we could handle them for the subset of cases
6155 in which we are not using $at). */
6156 assert (offset_expr
.X_op
== O_symbol
);
6157 expr1
.X_add_number
= offset_expr
.X_add_number
;
6158 offset_expr
.X_add_number
= 0;
6159 if (expr1
.X_add_number
< -0x8000
6160 || expr1
.X_add_number
>= 0x8000)
6161 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6162 gpdelay
= reg_needs_delay (mips_gp_register
);
6163 relax_start (offset_expr
.X_add_symbol
);
6164 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6165 BFD_RELOC_MIPS_GOT_HI16
);
6166 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6168 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6169 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6172 macro_build (NULL
, "nop", "");
6173 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6174 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6176 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6177 tempreg
, BFD_RELOC_LO16
);
6181 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6182 tempreg
, tempreg
, breg
);
6183 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6185 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6187 /* If this is a reference to an external symbol, we want
6188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6189 add $tempreg,$tempreg,$gp
6190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6191 <op> $treg,<ofst>($tempreg)
6192 Otherwise, for local symbols, we want:
6193 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6194 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6195 assert (offset_expr
.X_op
== O_symbol
);
6196 expr1
.X_add_number
= offset_expr
.X_add_number
;
6197 offset_expr
.X_add_number
= 0;
6198 if (expr1
.X_add_number
< -0x8000
6199 || expr1
.X_add_number
>= 0x8000)
6200 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6201 relax_start (offset_expr
.X_add_symbol
);
6202 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6203 BFD_RELOC_MIPS_GOT_HI16
);
6204 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6206 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6207 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6209 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6210 tempreg
, tempreg
, breg
);
6211 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6214 offset_expr
.X_add_number
= expr1
.X_add_number
;
6215 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6216 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6218 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6219 tempreg
, tempreg
, breg
);
6220 macro_build (&offset_expr
, s
, fmt
, treg
,
6221 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6234 load_register (treg
, &imm_expr
, 0);
6238 load_register (treg
, &imm_expr
, 1);
6242 if (imm_expr
.X_op
== O_constant
)
6244 load_register (AT
, &imm_expr
, 0);
6245 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6250 assert (offset_expr
.X_op
== O_symbol
6251 && strcmp (segment_name (S_GET_SEGMENT
6252 (offset_expr
.X_add_symbol
)),
6254 && offset_expr
.X_add_number
== 0);
6255 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6256 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6261 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6262 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6263 order 32 bits of the value and the low order 32 bits are either
6264 zero or in OFFSET_EXPR. */
6265 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6267 if (HAVE_64BIT_GPRS
)
6268 load_register (treg
, &imm_expr
, 1);
6273 if (target_big_endian
)
6285 load_register (hreg
, &imm_expr
, 0);
6288 if (offset_expr
.X_op
== O_absent
)
6289 move_register (lreg
, 0);
6292 assert (offset_expr
.X_op
== O_constant
);
6293 load_register (lreg
, &offset_expr
, 0);
6300 /* We know that sym is in the .rdata section. First we get the
6301 upper 16 bits of the address. */
6302 if (mips_pic
== NO_PIC
)
6304 macro_build_lui (&offset_expr
, AT
);
6306 else if (mips_pic
== SVR4_PIC
)
6308 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6309 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6314 /* Now we load the register(s). */
6315 if (HAVE_64BIT_GPRS
)
6316 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6319 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6322 /* FIXME: How in the world do we deal with the possible
6324 offset_expr
.X_add_number
+= 4;
6325 macro_build (&offset_expr
, "lw", "t,o(b)",
6326 treg
+ 1, BFD_RELOC_LO16
, AT
);
6332 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6333 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6334 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6335 the value and the low order 32 bits are either zero or in
6337 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6339 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6340 if (HAVE_64BIT_FPRS
)
6342 assert (HAVE_64BIT_GPRS
);
6343 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6347 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6348 if (offset_expr
.X_op
== O_absent
)
6349 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6352 assert (offset_expr
.X_op
== O_constant
);
6353 load_register (AT
, &offset_expr
, 0);
6354 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6360 assert (offset_expr
.X_op
== O_symbol
6361 && offset_expr
.X_add_number
== 0);
6362 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6363 if (strcmp (s
, ".lit8") == 0)
6365 if (mips_opts
.isa
!= ISA_MIPS1
)
6367 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6368 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6371 breg
= mips_gp_register
;
6372 r
= BFD_RELOC_MIPS_LITERAL
;
6377 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6378 if (mips_pic
== SVR4_PIC
)
6379 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6380 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6383 /* FIXME: This won't work for a 64 bit address. */
6384 macro_build_lui (&offset_expr
, AT
);
6387 if (mips_opts
.isa
!= ISA_MIPS1
)
6389 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6390 treg
, BFD_RELOC_LO16
, AT
);
6399 if (mips_opts
.arch
== CPU_R4650
)
6401 as_bad (_("opcode not supported on this processor"));
6404 /* Even on a big endian machine $fn comes before $fn+1. We have
6405 to adjust when loading from memory. */
6408 assert (mips_opts
.isa
== ISA_MIPS1
);
6409 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6410 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6411 /* FIXME: A possible overflow which I don't know how to deal
6413 offset_expr
.X_add_number
+= 4;
6414 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6415 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6423 * The MIPS assembler seems to check for X_add_number not
6424 * being double aligned and generating:
6427 * addiu at,at,%lo(foo+1)
6430 * But, the resulting address is the same after relocation so why
6431 * generate the extra instruction?
6433 if (mips_opts
.arch
== CPU_R4650
)
6435 as_bad (_("opcode not supported on this processor"));
6438 /* Itbl support may require additional care here. */
6440 if (mips_opts
.isa
!= ISA_MIPS1
)
6451 if (mips_opts
.arch
== CPU_R4650
)
6453 as_bad (_("opcode not supported on this processor"));
6457 if (mips_opts
.isa
!= ISA_MIPS1
)
6465 /* Itbl support may require additional care here. */
6470 if (HAVE_64BIT_GPRS
)
6481 if (HAVE_64BIT_GPRS
)
6491 if (offset_expr
.X_op
!= O_symbol
6492 && offset_expr
.X_op
!= O_constant
)
6494 as_bad (_("expression too complex"));
6495 offset_expr
.X_op
= O_constant
;
6498 /* Even on a big endian machine $fn comes before $fn+1. We have
6499 to adjust when loading from memory. We set coproc if we must
6500 load $fn+1 first. */
6501 /* Itbl support may require additional care here. */
6502 if (! target_big_endian
)
6505 if (mips_pic
== NO_PIC
6506 || offset_expr
.X_op
== O_constant
)
6508 /* If this is a reference to a GP relative symbol, we want
6509 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6510 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6511 If we have a base register, we use this
6513 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6514 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6515 If this is not a GP relative symbol, we want
6516 lui $at,<sym> (BFD_RELOC_HI16_S)
6517 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6518 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6519 If there is a base register, we add it to $at after the
6520 lui instruction. If there is a constant, we always use
6522 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6523 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6527 relax_start (offset_expr
.X_add_symbol
);
6530 tempreg
= mips_gp_register
;
6534 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6535 AT
, breg
, mips_gp_register
);
6540 /* Itbl support may require additional care here. */
6541 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6542 BFD_RELOC_GPREL16
, tempreg
);
6543 offset_expr
.X_add_number
+= 4;
6545 /* Set mips_optimize to 2 to avoid inserting an
6547 hold_mips_optimize
= mips_optimize
;
6549 /* Itbl support may require additional care here. */
6550 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6551 BFD_RELOC_GPREL16
, tempreg
);
6552 mips_optimize
= hold_mips_optimize
;
6556 /* We just generated two relocs. When tc_gen_reloc
6557 handles this case, it will skip the first reloc and
6558 handle the second. The second reloc already has an
6559 extra addend of 4, which we added above. We must
6560 subtract it out, and then subtract another 4 to make
6561 the first reloc come out right. The second reloc
6562 will come out right because we are going to add 4 to
6563 offset_expr when we build its instruction below.
6565 If we have a symbol, then we don't want to include
6566 the offset, because it will wind up being included
6567 when we generate the reloc. */
6569 if (offset_expr
.X_op
== O_constant
)
6570 offset_expr
.X_add_number
-= 8;
6573 offset_expr
.X_add_number
= -4;
6574 offset_expr
.X_op
= O_constant
;
6577 macro_build_lui (&offset_expr
, AT
);
6579 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6580 /* Itbl support may require additional care here. */
6581 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6582 BFD_RELOC_LO16
, AT
);
6583 /* FIXME: How do we handle overflow here? */
6584 offset_expr
.X_add_number
+= 4;
6585 /* Itbl support may require additional care here. */
6586 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6587 BFD_RELOC_LO16
, AT
);
6588 if (mips_relax
.sequence
)
6591 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6593 /* If this is a reference to an external symbol, we want
6594 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6599 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6601 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6602 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6603 If there is a base register we add it to $at before the
6604 lwc1 instructions. If there is a constant we include it
6605 in the lwc1 instructions. */
6607 expr1
.X_add_number
= offset_expr
.X_add_number
;
6608 if (expr1
.X_add_number
< -0x8000
6609 || expr1
.X_add_number
>= 0x8000 - 4)
6610 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6611 load_got_offset (AT
, &offset_expr
);
6614 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6616 /* Set mips_optimize to 2 to avoid inserting an undesired
6618 hold_mips_optimize
= mips_optimize
;
6621 /* Itbl support may require additional care here. */
6622 relax_start (offset_expr
.X_add_symbol
);
6623 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6624 BFD_RELOC_LO16
, AT
);
6625 expr1
.X_add_number
+= 4;
6626 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6627 BFD_RELOC_LO16
, AT
);
6629 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6630 BFD_RELOC_LO16
, AT
);
6631 offset_expr
.X_add_number
+= 4;
6632 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6633 BFD_RELOC_LO16
, AT
);
6636 mips_optimize
= hold_mips_optimize
;
6638 else if (mips_pic
== SVR4_PIC
)
6642 /* If this is a reference to an external symbol, we want
6643 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6645 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6650 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6652 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6653 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6654 If there is a base register we add it to $at before the
6655 lwc1 instructions. If there is a constant we include it
6656 in the lwc1 instructions. */
6658 expr1
.X_add_number
= offset_expr
.X_add_number
;
6659 offset_expr
.X_add_number
= 0;
6660 if (expr1
.X_add_number
< -0x8000
6661 || expr1
.X_add_number
>= 0x8000 - 4)
6662 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6663 gpdelay
= reg_needs_delay (mips_gp_register
);
6664 relax_start (offset_expr
.X_add_symbol
);
6665 macro_build (&offset_expr
, "lui", "t,u",
6666 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6667 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6668 AT
, AT
, mips_gp_register
);
6669 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6670 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6673 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6674 /* Itbl support may require additional care here. */
6675 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6676 BFD_RELOC_LO16
, AT
);
6677 expr1
.X_add_number
+= 4;
6679 /* Set mips_optimize to 2 to avoid inserting an undesired
6681 hold_mips_optimize
= mips_optimize
;
6683 /* Itbl support may require additional care here. */
6684 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6685 BFD_RELOC_LO16
, AT
);
6686 mips_optimize
= hold_mips_optimize
;
6687 expr1
.X_add_number
-= 4;
6690 offset_expr
.X_add_number
= expr1
.X_add_number
;
6692 macro_build (NULL
, "nop", "");
6693 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6694 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6697 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6698 /* Itbl support may require additional care here. */
6699 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6700 BFD_RELOC_LO16
, AT
);
6701 offset_expr
.X_add_number
+= 4;
6703 /* Set mips_optimize to 2 to avoid inserting an undesired
6705 hold_mips_optimize
= mips_optimize
;
6707 /* Itbl support may require additional care here. */
6708 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6709 BFD_RELOC_LO16
, AT
);
6710 mips_optimize
= hold_mips_optimize
;
6727 assert (HAVE_32BIT_ADDRESSES
);
6728 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6729 offset_expr
.X_add_number
+= 4;
6730 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6733 /* New code added to support COPZ instructions.
6734 This code builds table entries out of the macros in mip_opcodes.
6735 R4000 uses interlocks to handle coproc delays.
6736 Other chips (like the R3000) require nops to be inserted for delays.
6738 FIXME: Currently, we require that the user handle delays.
6739 In order to fill delay slots for non-interlocked chips,
6740 we must have a way to specify delays based on the coprocessor.
6741 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6742 What are the side-effects of the cop instruction?
6743 What cache support might we have and what are its effects?
6744 Both coprocessor & memory require delays. how long???
6745 What registers are read/set/modified?
6747 If an itbl is provided to interpret cop instructions,
6748 this knowledge can be encoded in the itbl spec. */
6762 /* For now we just do C (same as Cz). The parameter will be
6763 stored in insn_opcode by mips_ip. */
6764 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6768 move_register (dreg
, sreg
);
6771 #ifdef LOSING_COMPILER
6773 /* Try and see if this is a new itbl instruction.
6774 This code builds table entries out of the macros in mip_opcodes.
6775 FIXME: For now we just assemble the expression and pass it's
6776 value along as a 32-bit immediate.
6777 We may want to have the assembler assemble this value,
6778 so that we gain the assembler's knowledge of delay slots,
6780 Would it be more efficient to use mask (id) here? */
6781 if (itbl_have_entries
6782 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6784 s
= ip
->insn_mo
->name
;
6786 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6787 macro_build (&immed_expr
, s
, "C");
6794 as_warn (_("Macro used $at after \".set noat\""));
6798 macro2 (struct mips_cl_insn
*ip
)
6800 register int treg
, sreg
, dreg
, breg
;
6815 bfd_reloc_code_real_type r
;
6817 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6818 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6819 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6820 mask
= ip
->insn_mo
->mask
;
6822 expr1
.X_op
= O_constant
;
6823 expr1
.X_op_symbol
= NULL
;
6824 expr1
.X_add_symbol
= NULL
;
6825 expr1
.X_add_number
= 1;
6829 #endif /* LOSING_COMPILER */
6834 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6835 macro_build (NULL
, "mflo", "d", dreg
);
6841 /* The MIPS assembler some times generates shifts and adds. I'm
6842 not trying to be that fancy. GCC should do this for us
6844 load_register (AT
, &imm_expr
, dbl
);
6845 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6846 macro_build (NULL
, "mflo", "d", dreg
);
6859 mips_emit_delays (TRUE
);
6860 ++mips_opts
.noreorder
;
6861 mips_any_noreorder
= 1;
6863 load_register (AT
, &imm_expr
, dbl
);
6864 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6865 macro_build (NULL
, "mflo", "d", dreg
);
6866 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6867 macro_build (NULL
, "mfhi", "d", AT
);
6869 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6872 expr1
.X_add_number
= 8;
6873 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6874 macro_build (NULL
, "nop", "", 0);
6875 macro_build (NULL
, "break", "c", 6);
6877 --mips_opts
.noreorder
;
6878 macro_build (NULL
, "mflo", "d", dreg
);
6891 mips_emit_delays (TRUE
);
6892 ++mips_opts
.noreorder
;
6893 mips_any_noreorder
= 1;
6895 load_register (AT
, &imm_expr
, dbl
);
6896 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6897 sreg
, imm
? AT
: treg
);
6898 macro_build (NULL
, "mfhi", "d", AT
);
6899 macro_build (NULL
, "mflo", "d", dreg
);
6901 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6904 expr1
.X_add_number
= 8;
6905 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6906 macro_build (NULL
, "nop", "", 0);
6907 macro_build (NULL
, "break", "c", 6);
6909 --mips_opts
.noreorder
;
6913 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6924 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6925 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6930 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6931 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6932 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6933 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6937 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6948 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6949 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6954 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6955 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6956 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6957 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6965 if (imm_expr
.X_op
!= O_constant
)
6966 as_bad (_("Improper rotate count"));
6967 rot
= imm_expr
.X_add_number
& 0x3f;
6968 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6970 rot
= (64 - rot
) & 0x3f;
6972 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6974 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6979 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6982 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6983 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6985 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6986 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6987 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6995 if (imm_expr
.X_op
!= O_constant
)
6996 as_bad (_("Improper rotate count"));
6997 rot
= imm_expr
.X_add_number
& 0x1f;
6998 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7000 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7005 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7008 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7009 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7010 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7015 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7017 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7020 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7021 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7022 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7023 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7027 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7029 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7032 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7033 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7034 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7035 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7043 if (imm_expr
.X_op
!= O_constant
)
7044 as_bad (_("Improper rotate count"));
7045 rot
= imm_expr
.X_add_number
& 0x3f;
7046 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7049 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7051 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7056 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7059 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7060 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7062 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7063 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7064 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7072 if (imm_expr
.X_op
!= O_constant
)
7073 as_bad (_("Improper rotate count"));
7074 rot
= imm_expr
.X_add_number
& 0x1f;
7075 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7077 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7082 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7085 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7086 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7087 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7092 if (mips_opts
.arch
== CPU_R4650
)
7094 as_bad (_("opcode not supported on this processor"));
7097 assert (mips_opts
.isa
== ISA_MIPS1
);
7098 /* Even on a big endian machine $fn comes before $fn+1. We have
7099 to adjust when storing to memory. */
7100 macro_build (&offset_expr
, "swc1", "T,o(b)",
7101 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7102 offset_expr
.X_add_number
+= 4;
7103 macro_build (&offset_expr
, "swc1", "T,o(b)",
7104 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7109 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7111 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7114 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7115 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7120 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7122 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7127 as_warn (_("Instruction %s: result is always false"),
7129 move_register (dreg
, 0);
7132 if (imm_expr
.X_op
== O_constant
7133 && imm_expr
.X_add_number
>= 0
7134 && imm_expr
.X_add_number
< 0x10000)
7136 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7138 else if (imm_expr
.X_op
== O_constant
7139 && imm_expr
.X_add_number
> -0x8000
7140 && imm_expr
.X_add_number
< 0)
7142 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7143 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7144 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7148 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7149 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7152 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7157 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7163 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7164 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7167 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7169 if (imm_expr
.X_op
== O_constant
7170 && imm_expr
.X_add_number
>= -0x8000
7171 && imm_expr
.X_add_number
< 0x8000)
7173 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7174 dreg
, sreg
, BFD_RELOC_LO16
);
7178 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7179 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7183 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7188 case M_SGT
: /* sreg > treg <==> treg < sreg */
7194 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7197 case M_SGT_I
: /* sreg > I <==> I < sreg */
7203 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7204 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7207 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7213 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7214 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7217 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7223 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7224 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7225 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7229 if (imm_expr
.X_op
== O_constant
7230 && imm_expr
.X_add_number
>= -0x8000
7231 && imm_expr
.X_add_number
< 0x8000)
7233 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7236 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7237 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7241 if (imm_expr
.X_op
== O_constant
7242 && imm_expr
.X_add_number
>= -0x8000
7243 && imm_expr
.X_add_number
< 0x8000)
7245 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7249 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7250 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7255 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7257 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7260 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7261 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7266 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7268 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7273 as_warn (_("Instruction %s: result is always true"),
7275 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7276 dreg
, 0, BFD_RELOC_LO16
);
7279 if (imm_expr
.X_op
== O_constant
7280 && imm_expr
.X_add_number
>= 0
7281 && imm_expr
.X_add_number
< 0x10000)
7283 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7285 else if (imm_expr
.X_op
== O_constant
7286 && imm_expr
.X_add_number
> -0x8000
7287 && imm_expr
.X_add_number
< 0)
7289 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7290 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7291 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7295 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7296 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7299 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7307 if (imm_expr
.X_op
== O_constant
7308 && imm_expr
.X_add_number
> -0x8000
7309 && imm_expr
.X_add_number
<= 0x8000)
7311 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7312 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7313 dreg
, sreg
, BFD_RELOC_LO16
);
7316 load_register (AT
, &imm_expr
, dbl
);
7317 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7323 if (imm_expr
.X_op
== O_constant
7324 && imm_expr
.X_add_number
> -0x8000
7325 && imm_expr
.X_add_number
<= 0x8000)
7327 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7328 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7329 dreg
, sreg
, BFD_RELOC_LO16
);
7332 load_register (AT
, &imm_expr
, dbl
);
7333 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7354 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7355 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7360 assert (mips_opts
.isa
== ISA_MIPS1
);
7361 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7362 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7365 * Is the double cfc1 instruction a bug in the mips assembler;
7366 * or is there a reason for it?
7368 mips_emit_delays (TRUE
);
7369 ++mips_opts
.noreorder
;
7370 mips_any_noreorder
= 1;
7371 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7372 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7373 macro_build (NULL
, "nop", "");
7374 expr1
.X_add_number
= 3;
7375 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7376 expr1
.X_add_number
= 2;
7377 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7378 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7379 macro_build (NULL
, "nop", "");
7380 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7382 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7383 macro_build (NULL
, "nop", "");
7384 --mips_opts
.noreorder
;
7393 if (offset_expr
.X_add_number
>= 0x7fff)
7394 as_bad (_("operand overflow"));
7395 if (! target_big_endian
)
7396 ++offset_expr
.X_add_number
;
7397 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7398 if (! target_big_endian
)
7399 --offset_expr
.X_add_number
;
7401 ++offset_expr
.X_add_number
;
7402 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7403 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7404 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7417 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7418 as_bad (_("operand overflow"));
7423 if (! target_big_endian
)
7424 offset_expr
.X_add_number
+= off
;
7425 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7426 if (! target_big_endian
)
7427 offset_expr
.X_add_number
-= off
;
7429 offset_expr
.X_add_number
+= off
;
7430 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7432 /* If necessary, move the result in tempreg the final destination. */
7433 if (treg
== tempreg
)
7435 /* Protect second load's delay slot. */
7437 move_register (treg
, tempreg
);
7451 load_address (AT
, &offset_expr
, &used_at
);
7453 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7454 if (! target_big_endian
)
7455 expr1
.X_add_number
= off
;
7457 expr1
.X_add_number
= 0;
7458 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7459 if (! target_big_endian
)
7460 expr1
.X_add_number
= 0;
7462 expr1
.X_add_number
= off
;
7463 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7469 load_address (AT
, &offset_expr
, &used_at
);
7471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7472 if (target_big_endian
)
7473 expr1
.X_add_number
= 0;
7474 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7475 treg
, BFD_RELOC_LO16
, AT
);
7476 if (target_big_endian
)
7477 expr1
.X_add_number
= 1;
7479 expr1
.X_add_number
= 0;
7480 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7481 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7482 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7486 if (offset_expr
.X_add_number
>= 0x7fff)
7487 as_bad (_("operand overflow"));
7488 if (target_big_endian
)
7489 ++offset_expr
.X_add_number
;
7490 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7491 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7492 if (target_big_endian
)
7493 --offset_expr
.X_add_number
;
7495 ++offset_expr
.X_add_number
;
7496 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7509 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7510 as_bad (_("operand overflow"));
7511 if (! target_big_endian
)
7512 offset_expr
.X_add_number
+= off
;
7513 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7514 if (! target_big_endian
)
7515 offset_expr
.X_add_number
-= off
;
7517 offset_expr
.X_add_number
+= off
;
7518 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7532 load_address (AT
, &offset_expr
, &used_at
);
7534 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7535 if (! target_big_endian
)
7536 expr1
.X_add_number
= off
;
7538 expr1
.X_add_number
= 0;
7539 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7540 if (! target_big_endian
)
7541 expr1
.X_add_number
= 0;
7543 expr1
.X_add_number
= off
;
7544 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7549 load_address (AT
, &offset_expr
, &used_at
);
7551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7552 if (! target_big_endian
)
7553 expr1
.X_add_number
= 0;
7554 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7555 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7556 if (! target_big_endian
)
7557 expr1
.X_add_number
= 1;
7559 expr1
.X_add_number
= 0;
7560 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7561 if (! target_big_endian
)
7562 expr1
.X_add_number
= 0;
7564 expr1
.X_add_number
= 1;
7565 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7566 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7567 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7571 /* FIXME: Check if this is one of the itbl macros, since they
7572 are added dynamically. */
7573 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7577 as_warn (_("Macro used $at after \".set noat\""));
7580 /* Implement macros in mips16 mode. */
7583 mips16_macro (struct mips_cl_insn
*ip
)
7586 int xreg
, yreg
, zreg
, tmp
;
7589 const char *s
, *s2
, *s3
;
7591 mask
= ip
->insn_mo
->mask
;
7593 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7594 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7595 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7597 expr1
.X_op
= O_constant
;
7598 expr1
.X_op_symbol
= NULL
;
7599 expr1
.X_add_symbol
= NULL
;
7600 expr1
.X_add_number
= 1;
7619 mips_emit_delays (TRUE
);
7620 ++mips_opts
.noreorder
;
7621 mips_any_noreorder
= 1;
7622 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7623 expr1
.X_add_number
= 2;
7624 macro_build (&expr1
, "bnez", "x,p", yreg
);
7625 macro_build (NULL
, "break", "6", 7);
7627 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7628 since that causes an overflow. We should do that as well,
7629 but I don't see how to do the comparisons without a temporary
7631 --mips_opts
.noreorder
;
7632 macro_build (NULL
, s
, "x", zreg
);
7651 mips_emit_delays (TRUE
);
7652 ++mips_opts
.noreorder
;
7653 mips_any_noreorder
= 1;
7654 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7655 expr1
.X_add_number
= 2;
7656 macro_build (&expr1
, "bnez", "x,p", yreg
);
7657 macro_build (NULL
, "break", "6", 7);
7658 --mips_opts
.noreorder
;
7659 macro_build (NULL
, s2
, "x", zreg
);
7665 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7666 macro_build (NULL
, "mflo", "x", zreg
);
7674 if (imm_expr
.X_op
!= O_constant
)
7675 as_bad (_("Unsupported large constant"));
7676 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7677 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7681 if (imm_expr
.X_op
!= O_constant
)
7682 as_bad (_("Unsupported large constant"));
7683 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7684 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7688 if (imm_expr
.X_op
!= O_constant
)
7689 as_bad (_("Unsupported large constant"));
7690 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7691 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7713 goto do_reverse_branch
;
7717 goto do_reverse_branch
;
7729 goto do_reverse_branch
;
7740 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7741 macro_build (&offset_expr
, s2
, "p");
7768 goto do_addone_branch_i
;
7773 goto do_addone_branch_i
;
7788 goto do_addone_branch_i
;
7795 if (imm_expr
.X_op
!= O_constant
)
7796 as_bad (_("Unsupported large constant"));
7797 ++imm_expr
.X_add_number
;
7800 macro_build (&imm_expr
, s
, s3
, xreg
);
7801 macro_build (&offset_expr
, s2
, "p");
7805 expr1
.X_add_number
= 0;
7806 macro_build (&expr1
, "slti", "x,8", yreg
);
7808 move_register (xreg
, yreg
);
7809 expr1
.X_add_number
= 2;
7810 macro_build (&expr1
, "bteqz", "p");
7811 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7815 /* For consistency checking, verify that all bits are specified either
7816 by the match/mask part of the instruction definition, or by the
7819 validate_mips_insn (const struct mips_opcode
*opc
)
7821 const char *p
= opc
->args
;
7823 unsigned long used_bits
= opc
->mask
;
7825 if ((used_bits
& opc
->match
) != opc
->match
)
7827 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7828 opc
->name
, opc
->args
);
7831 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7841 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7842 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7843 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7844 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7845 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7846 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7847 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7848 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7849 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7852 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7853 c
, opc
->name
, opc
->args
);
7857 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7858 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7860 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7861 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7862 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7863 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7865 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7866 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7868 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7869 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7871 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7872 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7873 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7874 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7875 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7876 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7877 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7878 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7879 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7880 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7881 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7882 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7883 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7884 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7885 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7886 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7887 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7889 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7890 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7891 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7892 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7894 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7895 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7896 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7897 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7898 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7899 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7900 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7901 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7902 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7905 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7906 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7907 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7908 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7909 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7913 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7914 c
, opc
->name
, opc
->args
);
7918 if (used_bits
!= 0xffffffff)
7920 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7921 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7927 /* This routine assembles an instruction into its binary format. As a
7928 side effect, it sets one of the global variables imm_reloc or
7929 offset_reloc to the type of relocation to do if one of the operands
7930 is an address expression. */
7933 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7938 struct mips_opcode
*insn
;
7941 unsigned int lastregno
= 0;
7942 unsigned int lastpos
= 0;
7943 unsigned int limlo
, limhi
;
7949 /* If the instruction contains a '.', we first try to match an instruction
7950 including the '.'. Then we try again without the '.'. */
7952 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7955 /* If we stopped on whitespace, then replace the whitespace with null for
7956 the call to hash_find. Save the character we replaced just in case we
7957 have to re-parse the instruction. */
7964 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7966 /* If we didn't find the instruction in the opcode table, try again, but
7967 this time with just the instruction up to, but not including the
7971 /* Restore the character we overwrite above (if any). */
7975 /* Scan up to the first '.' or whitespace. */
7977 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7981 /* If we did not find a '.', then we can quit now. */
7984 insn_error
= "unrecognized opcode";
7988 /* Lookup the instruction in the hash table. */
7990 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7992 insn_error
= "unrecognized opcode";
8002 assert (strcmp (insn
->name
, str
) == 0);
8004 if (OPCODE_IS_MEMBER (insn
,
8006 | (file_ase_mips16
? INSN_MIPS16
: 0)
8007 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8008 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8014 if (insn
->pinfo
!= INSN_MACRO
)
8016 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8022 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8023 && strcmp (insn
->name
, insn
[1].name
) == 0)
8032 static char buf
[100];
8034 _("opcode not supported on this processor: %s (%s)"),
8035 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8036 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8046 ip
->insn_opcode
= insn
->match
;
8048 for (args
= insn
->args
;; ++args
)
8052 s
+= strspn (s
, " \t");
8056 case '\0': /* end of args */
8069 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8073 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8077 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8081 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8087 /* Handle optional base register.
8088 Either the base register is omitted or
8089 we must have a left paren. */
8090 /* This is dependent on the next operand specifier
8091 is a base register specification. */
8092 assert (args
[1] == 'b' || args
[1] == '5'
8093 || args
[1] == '-' || args
[1] == '4');
8097 case ')': /* these must match exactly */
8104 case '+': /* Opcode extension character. */
8107 case 'A': /* ins/ext position, becomes LSB. */
8116 my_getExpression (&imm_expr
, s
);
8117 check_absolute_expr (ip
, &imm_expr
);
8118 if ((unsigned long) imm_expr
.X_add_number
< limlo
8119 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8121 as_bad (_("Improper position (%lu)"),
8122 (unsigned long) imm_expr
.X_add_number
);
8123 imm_expr
.X_add_number
= limlo
;
8125 lastpos
= imm_expr
.X_add_number
;
8126 ip
->insn_opcode
|= (imm_expr
.X_add_number
8127 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8128 imm_expr
.X_op
= O_absent
;
8132 case 'B': /* ins size, becomes MSB. */
8141 my_getExpression (&imm_expr
, s
);
8142 check_absolute_expr (ip
, &imm_expr
);
8143 /* Check for negative input so that small negative numbers
8144 will not succeed incorrectly. The checks against
8145 (pos+size) transitively check "size" itself,
8146 assuming that "pos" is reasonable. */
8147 if ((long) imm_expr
.X_add_number
< 0
8148 || ((unsigned long) imm_expr
.X_add_number
8150 || ((unsigned long) imm_expr
.X_add_number
8153 as_bad (_("Improper insert size (%lu, position %lu)"),
8154 (unsigned long) imm_expr
.X_add_number
,
8155 (unsigned long) lastpos
);
8156 imm_expr
.X_add_number
= limlo
- lastpos
;
8158 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8159 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8160 imm_expr
.X_op
= O_absent
;
8164 case 'C': /* ext size, becomes MSBD. */
8177 my_getExpression (&imm_expr
, s
);
8178 check_absolute_expr (ip
, &imm_expr
);
8179 /* Check for negative input so that small negative numbers
8180 will not succeed incorrectly. The checks against
8181 (pos+size) transitively check "size" itself,
8182 assuming that "pos" is reasonable. */
8183 if ((long) imm_expr
.X_add_number
< 0
8184 || ((unsigned long) imm_expr
.X_add_number
8186 || ((unsigned long) imm_expr
.X_add_number
8189 as_bad (_("Improper extract size (%lu, position %lu)"),
8190 (unsigned long) imm_expr
.X_add_number
,
8191 (unsigned long) lastpos
);
8192 imm_expr
.X_add_number
= limlo
- lastpos
;
8194 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8195 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8196 imm_expr
.X_op
= O_absent
;
8201 /* +D is for disassembly only; never match. */
8205 /* "+I" is like "I", except that imm2_expr is used. */
8206 my_getExpression (&imm2_expr
, s
);
8207 if (imm2_expr
.X_op
!= O_big
8208 && imm2_expr
.X_op
!= O_constant
)
8209 insn_error
= _("absolute expression required");
8210 normalize_constant_expr (&imm2_expr
);
8215 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8216 *args
, insn
->name
, insn
->args
);
8217 /* Further processing is fruitless. */
8222 case '<': /* must be at least one digit */
8224 * According to the manual, if the shift amount is greater
8225 * than 31 or less than 0, then the shift amount should be
8226 * mod 32. In reality the mips assembler issues an error.
8227 * We issue a warning and mask out all but the low 5 bits.
8229 my_getExpression (&imm_expr
, s
);
8230 check_absolute_expr (ip
, &imm_expr
);
8231 if ((unsigned long) imm_expr
.X_add_number
> 31)
8233 as_warn (_("Improper shift amount (%lu)"),
8234 (unsigned long) imm_expr
.X_add_number
);
8235 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8237 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8238 imm_expr
.X_op
= O_absent
;
8242 case '>': /* shift amount minus 32 */
8243 my_getExpression (&imm_expr
, s
);
8244 check_absolute_expr (ip
, &imm_expr
);
8245 if ((unsigned long) imm_expr
.X_add_number
< 32
8246 || (unsigned long) imm_expr
.X_add_number
> 63)
8248 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8249 imm_expr
.X_op
= O_absent
;
8253 case 'k': /* cache code */
8254 case 'h': /* prefx code */
8255 my_getExpression (&imm_expr
, s
);
8256 check_absolute_expr (ip
, &imm_expr
);
8257 if ((unsigned long) imm_expr
.X_add_number
> 31)
8259 as_warn (_("Invalid value for `%s' (%lu)"),
8261 (unsigned long) imm_expr
.X_add_number
);
8262 imm_expr
.X_add_number
&= 0x1f;
8265 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8267 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8268 imm_expr
.X_op
= O_absent
;
8272 case 'c': /* break code */
8273 my_getExpression (&imm_expr
, s
);
8274 check_absolute_expr (ip
, &imm_expr
);
8275 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8277 as_warn (_("Illegal break code (%lu)"),
8278 (unsigned long) imm_expr
.X_add_number
);
8279 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8281 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8282 imm_expr
.X_op
= O_absent
;
8286 case 'q': /* lower break code */
8287 my_getExpression (&imm_expr
, s
);
8288 check_absolute_expr (ip
, &imm_expr
);
8289 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8291 as_warn (_("Illegal lower break code (%lu)"),
8292 (unsigned long) imm_expr
.X_add_number
);
8293 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8295 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8296 imm_expr
.X_op
= O_absent
;
8300 case 'B': /* 20-bit syscall/break code. */
8301 my_getExpression (&imm_expr
, s
);
8302 check_absolute_expr (ip
, &imm_expr
);
8303 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8304 as_warn (_("Illegal 20-bit code (%lu)"),
8305 (unsigned long) imm_expr
.X_add_number
);
8306 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8307 imm_expr
.X_op
= O_absent
;
8311 case 'C': /* Coprocessor code */
8312 my_getExpression (&imm_expr
, s
);
8313 check_absolute_expr (ip
, &imm_expr
);
8314 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8316 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8317 (unsigned long) imm_expr
.X_add_number
);
8318 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8320 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8321 imm_expr
.X_op
= O_absent
;
8325 case 'J': /* 19-bit wait code. */
8326 my_getExpression (&imm_expr
, s
);
8327 check_absolute_expr (ip
, &imm_expr
);
8328 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8329 as_warn (_("Illegal 19-bit code (%lu)"),
8330 (unsigned long) imm_expr
.X_add_number
);
8331 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8332 imm_expr
.X_op
= O_absent
;
8336 case 'P': /* Performance register */
8337 my_getExpression (&imm_expr
, s
);
8338 check_absolute_expr (ip
, &imm_expr
);
8339 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8341 as_warn (_("Invalid performance register (%lu)"),
8342 (unsigned long) imm_expr
.X_add_number
);
8343 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8345 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8346 imm_expr
.X_op
= O_absent
;
8350 case 'b': /* base register */
8351 case 'd': /* destination register */
8352 case 's': /* source register */
8353 case 't': /* target register */
8354 case 'r': /* both target and source */
8355 case 'v': /* both dest and source */
8356 case 'w': /* both dest and target */
8357 case 'E': /* coprocessor target register */
8358 case 'G': /* coprocessor destination register */
8359 case 'K': /* 'rdhwr' destination register */
8360 case 'x': /* ignore register name */
8361 case 'z': /* must be zero register */
8362 case 'U': /* destination register (clo/clz). */
8377 while (ISDIGIT (*s
));
8379 as_bad (_("Invalid register number (%d)"), regno
);
8381 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8385 if (s
[1] == 'r' && s
[2] == 'a')
8390 else if (s
[1] == 'f' && s
[2] == 'p')
8395 else if (s
[1] == 's' && s
[2] == 'p')
8400 else if (s
[1] == 'g' && s
[2] == 'p')
8405 else if (s
[1] == 'a' && s
[2] == 't')
8410 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8415 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8420 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8425 else if (itbl_have_entries
)
8430 p
= s
+ 1; /* advance past '$' */
8431 n
= itbl_get_field (&p
); /* n is name */
8433 /* See if this is a register defined in an
8435 if (itbl_get_reg_val (n
, &r
))
8437 /* Get_field advances to the start of
8438 the next field, so we need to back
8439 rack to the end of the last field. */
8443 s
= strchr (s
, '\0');
8457 as_warn (_("Used $at without \".set noat\""));
8463 if (c
== 'r' || c
== 'v' || c
== 'w')
8470 /* 'z' only matches $0. */
8471 if (c
== 'z' && regno
!= 0)
8474 /* Now that we have assembled one operand, we use the args string
8475 * to figure out where it goes in the instruction. */
8482 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8487 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8490 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8491 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8496 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8499 /* This case exists because on the r3000 trunc
8500 expands into a macro which requires a gp
8501 register. On the r6000 or r4000 it is
8502 assembled into a single instruction which
8503 ignores the register. Thus the insn version
8504 is MIPS_ISA2 and uses 'x', and the macro
8505 version is MIPS_ISA1 and uses 't'. */
8508 /* This case is for the div instruction, which
8509 acts differently if the destination argument
8510 is $0. This only matches $0, and is checked
8511 outside the switch. */
8514 /* Itbl operand; not yet implemented. FIXME ?? */
8516 /* What about all other operands like 'i', which
8517 can be specified in the opcode table? */
8527 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8530 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8535 case 'O': /* MDMX alignment immediate constant. */
8536 my_getExpression (&imm_expr
, s
);
8537 check_absolute_expr (ip
, &imm_expr
);
8538 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8540 as_warn ("Improper align amount (%ld), using low bits",
8541 (long) imm_expr
.X_add_number
);
8542 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8544 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8545 imm_expr
.X_op
= O_absent
;
8549 case 'Q': /* MDMX vector, element sel, or const. */
8552 /* MDMX Immediate. */
8553 my_getExpression (&imm_expr
, s
);
8554 check_absolute_expr (ip
, &imm_expr
);
8555 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8557 as_warn (_("Invalid MDMX Immediate (%ld)"),
8558 (long) imm_expr
.X_add_number
);
8559 imm_expr
.X_add_number
&= OP_MASK_FT
;
8561 imm_expr
.X_add_number
&= OP_MASK_FT
;
8562 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8563 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8565 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8566 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8567 imm_expr
.X_op
= O_absent
;
8571 /* Not MDMX Immediate. Fall through. */
8572 case 'X': /* MDMX destination register. */
8573 case 'Y': /* MDMX source register. */
8574 case 'Z': /* MDMX target register. */
8576 case 'D': /* floating point destination register */
8577 case 'S': /* floating point source register */
8578 case 'T': /* floating point target register */
8579 case 'R': /* floating point source register */
8583 /* Accept $fN for FP and MDMX register numbers, and in
8584 addition accept $vN for MDMX register numbers. */
8585 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8586 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8597 while (ISDIGIT (*s
));
8600 as_bad (_("Invalid float register number (%d)"), regno
);
8602 if ((regno
& 1) != 0
8604 && ! (strcmp (str
, "mtc1") == 0
8605 || strcmp (str
, "mfc1") == 0
8606 || strcmp (str
, "lwc1") == 0
8607 || strcmp (str
, "swc1") == 0
8608 || strcmp (str
, "l.s") == 0
8609 || strcmp (str
, "s.s") == 0))
8610 as_warn (_("Float register should be even, was %d"),
8618 if (c
== 'V' || c
== 'W')
8629 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8634 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8637 /* This is like 'Z', but also needs to fix the MDMX
8638 vector/scalar select bits. Note that the
8639 scalar immediate case is handled above. */
8642 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8643 int max_el
= (is_qh
? 3 : 7);
8645 my_getExpression(&imm_expr
, s
);
8646 check_absolute_expr (ip
, &imm_expr
);
8648 if (imm_expr
.X_add_number
> max_el
)
8649 as_bad(_("Bad element selector %ld"),
8650 (long) imm_expr
.X_add_number
);
8651 imm_expr
.X_add_number
&= max_el
;
8652 ip
->insn_opcode
|= (imm_expr
.X_add_number
8655 imm_expr
.X_op
= O_absent
;
8657 as_warn(_("Expecting ']' found '%s'"), s
);
8663 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8664 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8667 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8674 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8677 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8687 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8690 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8696 my_getExpression (&imm_expr
, s
);
8697 if (imm_expr
.X_op
!= O_big
8698 && imm_expr
.X_op
!= O_constant
)
8699 insn_error
= _("absolute expression required");
8700 normalize_constant_expr (&imm_expr
);
8705 my_getExpression (&offset_expr
, s
);
8706 *imm_reloc
= BFD_RELOC_32
;
8719 unsigned char temp
[8];
8721 unsigned int length
;
8726 /* These only appear as the last operand in an
8727 instruction, and every instruction that accepts
8728 them in any variant accepts them in all variants.
8729 This means we don't have to worry about backing out
8730 any changes if the instruction does not match.
8732 The difference between them is the size of the
8733 floating point constant and where it goes. For 'F'
8734 and 'L' the constant is 64 bits; for 'f' and 'l' it
8735 is 32 bits. Where the constant is placed is based
8736 on how the MIPS assembler does things:
8739 f -- immediate value
8742 The .lit4 and .lit8 sections are only used if
8743 permitted by the -G argument.
8745 The code below needs to know whether the target register
8746 is 32 or 64 bits wide. It relies on the fact 'f' and
8747 'F' are used with GPR-based instructions and 'l' and
8748 'L' are used with FPR-based instructions. */
8750 f64
= *args
== 'F' || *args
== 'L';
8751 using_gprs
= *args
== 'F' || *args
== 'f';
8753 save_in
= input_line_pointer
;
8754 input_line_pointer
= s
;
8755 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8757 s
= input_line_pointer
;
8758 input_line_pointer
= save_in
;
8759 if (err
!= NULL
&& *err
!= '\0')
8761 as_bad (_("Bad floating point constant: %s"), err
);
8762 memset (temp
, '\0', sizeof temp
);
8763 length
= f64
? 8 : 4;
8766 assert (length
== (unsigned) (f64
? 8 : 4));
8770 && (g_switch_value
< 4
8771 || (temp
[0] == 0 && temp
[1] == 0)
8772 || (temp
[2] == 0 && temp
[3] == 0))))
8774 imm_expr
.X_op
= O_constant
;
8775 if (! target_big_endian
)
8776 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8778 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8781 && ! mips_disable_float_construction
8782 /* Constants can only be constructed in GPRs and
8783 copied to FPRs if the GPRs are at least as wide
8784 as the FPRs. Force the constant into memory if
8785 we are using 64-bit FPRs but the GPRs are only
8788 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8789 && ((temp
[0] == 0 && temp
[1] == 0)
8790 || (temp
[2] == 0 && temp
[3] == 0))
8791 && ((temp
[4] == 0 && temp
[5] == 0)
8792 || (temp
[6] == 0 && temp
[7] == 0)))
8794 /* The value is simple enough to load with a couple of
8795 instructions. If using 32-bit registers, set
8796 imm_expr to the high order 32 bits and offset_expr to
8797 the low order 32 bits. Otherwise, set imm_expr to
8798 the entire 64 bit constant. */
8799 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8801 imm_expr
.X_op
= O_constant
;
8802 offset_expr
.X_op
= O_constant
;
8803 if (! target_big_endian
)
8805 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8806 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8810 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8811 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8813 if (offset_expr
.X_add_number
== 0)
8814 offset_expr
.X_op
= O_absent
;
8816 else if (sizeof (imm_expr
.X_add_number
) > 4)
8818 imm_expr
.X_op
= O_constant
;
8819 if (! target_big_endian
)
8820 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8822 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8826 imm_expr
.X_op
= O_big
;
8827 imm_expr
.X_add_number
= 4;
8828 if (! target_big_endian
)
8830 generic_bignum
[0] = bfd_getl16 (temp
);
8831 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8832 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8833 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8837 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8838 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8839 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8840 generic_bignum
[3] = bfd_getb16 (temp
);
8846 const char *newname
;
8849 /* Switch to the right section. */
8851 subseg
= now_subseg
;
8854 default: /* unused default case avoids warnings. */
8856 newname
= RDATA_SECTION_NAME
;
8857 if (g_switch_value
>= 8)
8861 newname
= RDATA_SECTION_NAME
;
8864 assert (g_switch_value
>= 4);
8868 new_seg
= subseg_new (newname
, (subsegT
) 0);
8869 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8870 bfd_set_section_flags (stdoutput
, new_seg
,
8875 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8876 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8877 && strcmp (TARGET_OS
, "elf") != 0)
8878 record_alignment (new_seg
, 4);
8880 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8882 as_bad (_("Can't use floating point insn in this section"));
8884 /* Set the argument to the current address in the
8886 offset_expr
.X_op
= O_symbol
;
8887 offset_expr
.X_add_symbol
=
8888 symbol_new ("L0\001", now_seg
,
8889 (valueT
) frag_now_fix (), frag_now
);
8890 offset_expr
.X_add_number
= 0;
8892 /* Put the floating point number into the section. */
8893 p
= frag_more ((int) length
);
8894 memcpy (p
, temp
, length
);
8896 /* Switch back to the original section. */
8897 subseg_set (seg
, subseg
);
8902 case 'i': /* 16 bit unsigned immediate */
8903 case 'j': /* 16 bit signed immediate */
8904 *imm_reloc
= BFD_RELOC_LO16
;
8905 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8908 offsetT minval
, maxval
;
8910 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8911 && strcmp (insn
->name
, insn
[1].name
) == 0);
8913 /* If the expression was written as an unsigned number,
8914 only treat it as signed if there are no more
8918 && sizeof (imm_expr
.X_add_number
) <= 4
8919 && imm_expr
.X_op
== O_constant
8920 && imm_expr
.X_add_number
< 0
8921 && imm_expr
.X_unsigned
8925 /* For compatibility with older assemblers, we accept
8926 0x8000-0xffff as signed 16-bit numbers when only
8927 signed numbers are allowed. */
8929 minval
= 0, maxval
= 0xffff;
8931 minval
= -0x8000, maxval
= 0x7fff;
8933 minval
= -0x8000, maxval
= 0xffff;
8935 if (imm_expr
.X_op
!= O_constant
8936 || imm_expr
.X_add_number
< minval
8937 || imm_expr
.X_add_number
> maxval
)
8941 if (imm_expr
.X_op
== O_constant
8942 || imm_expr
.X_op
== O_big
)
8943 as_bad (_("expression out of range"));
8949 case 'o': /* 16 bit offset */
8950 /* Check whether there is only a single bracketed expression
8951 left. If so, it must be the base register and the
8952 constant must be zero. */
8953 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8955 offset_expr
.X_op
= O_constant
;
8956 offset_expr
.X_add_number
= 0;
8960 /* If this value won't fit into a 16 bit offset, then go
8961 find a macro that will generate the 32 bit offset
8963 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8964 && (offset_expr
.X_op
!= O_constant
8965 || offset_expr
.X_add_number
>= 0x8000
8966 || offset_expr
.X_add_number
< -0x8000))
8972 case 'p': /* pc relative offset */
8973 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8974 my_getExpression (&offset_expr
, s
);
8978 case 'u': /* upper 16 bits */
8979 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8980 && imm_expr
.X_op
== O_constant
8981 && (imm_expr
.X_add_number
< 0
8982 || imm_expr
.X_add_number
>= 0x10000))
8983 as_bad (_("lui expression not in range 0..65535"));
8987 case 'a': /* 26 bit address */
8988 my_getExpression (&offset_expr
, s
);
8990 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8993 case 'N': /* 3 bit branch condition code */
8994 case 'M': /* 3 bit compare condition code */
8995 if (strncmp (s
, "$fcc", 4) != 0)
9005 while (ISDIGIT (*s
));
9007 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9008 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9009 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9010 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9011 && (regno
& 1) != 0)
9012 as_warn(_("Condition code register should be even for %s, was %d"),
9014 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9015 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9016 && (regno
& 3) != 0)
9017 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9020 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9022 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9026 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9037 while (ISDIGIT (*s
));
9040 c
= 8; /* Invalid sel value. */
9043 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9044 ip
->insn_opcode
|= c
;
9048 /* Must be at least one digit. */
9049 my_getExpression (&imm_expr
, s
);
9050 check_absolute_expr (ip
, &imm_expr
);
9052 if ((unsigned long) imm_expr
.X_add_number
9053 > (unsigned long) OP_MASK_VECBYTE
)
9055 as_bad (_("bad byte vector index (%ld)"),
9056 (long) imm_expr
.X_add_number
);
9057 imm_expr
.X_add_number
= 0;
9060 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9061 imm_expr
.X_op
= O_absent
;
9066 my_getExpression (&imm_expr
, s
);
9067 check_absolute_expr (ip
, &imm_expr
);
9069 if ((unsigned long) imm_expr
.X_add_number
9070 > (unsigned long) OP_MASK_VECALIGN
)
9072 as_bad (_("bad byte vector index (%ld)"),
9073 (long) imm_expr
.X_add_number
);
9074 imm_expr
.X_add_number
= 0;
9077 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9078 imm_expr
.X_op
= O_absent
;
9083 as_bad (_("bad char = '%c'\n"), *args
);
9088 /* Args don't match. */
9089 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9090 !strcmp (insn
->name
, insn
[1].name
))
9094 insn_error
= _("illegal operands");
9099 insn_error
= _("illegal operands");
9104 /* This routine assembles an instruction into its binary format when
9105 assembling for the mips16. As a side effect, it sets one of the
9106 global variables imm_reloc or offset_reloc to the type of
9107 relocation to do if one of the operands is an address expression.
9108 It also sets mips16_small and mips16_ext if the user explicitly
9109 requested a small or extended instruction. */
9112 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9116 struct mips_opcode
*insn
;
9119 unsigned int lastregno
= 0;
9125 mips16_small
= FALSE
;
9128 for (s
= str
; ISLOWER (*s
); ++s
)
9140 if (s
[1] == 't' && s
[2] == ' ')
9143 mips16_small
= TRUE
;
9147 else if (s
[1] == 'e' && s
[2] == ' ')
9156 insn_error
= _("unknown opcode");
9160 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9161 mips16_small
= TRUE
;
9163 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9165 insn_error
= _("unrecognized opcode");
9172 assert (strcmp (insn
->name
, str
) == 0);
9175 ip
->insn_opcode
= insn
->match
;
9176 ip
->use_extend
= FALSE
;
9177 imm_expr
.X_op
= O_absent
;
9178 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9179 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9180 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9181 imm2_expr
.X_op
= O_absent
;
9182 offset_expr
.X_op
= O_absent
;
9183 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9184 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9185 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9186 for (args
= insn
->args
; 1; ++args
)
9193 /* In this switch statement we call break if we did not find
9194 a match, continue if we did find a match, or return if we
9203 /* Stuff the immediate value in now, if we can. */
9204 if (imm_expr
.X_op
== O_constant
9205 && *imm_reloc
> BFD_RELOC_UNUSED
9206 && insn
->pinfo
!= INSN_MACRO
)
9210 switch (*offset_reloc
)
9212 case BFD_RELOC_MIPS16_HI16_S
:
9213 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9216 case BFD_RELOC_MIPS16_HI16
:
9217 tmp
= imm_expr
.X_add_number
>> 16;
9220 case BFD_RELOC_MIPS16_LO16
:
9221 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9225 case BFD_RELOC_UNUSED
:
9226 tmp
= imm_expr
.X_add_number
;
9232 *offset_reloc
= BFD_RELOC_UNUSED
;
9234 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9235 tmp
, TRUE
, mips16_small
,
9236 mips16_ext
, &ip
->insn_opcode
,
9237 &ip
->use_extend
, &ip
->extend
);
9238 imm_expr
.X_op
= O_absent
;
9239 *imm_reloc
= BFD_RELOC_UNUSED
;
9253 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9256 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9272 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9274 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9301 while (ISDIGIT (*s
));
9304 as_bad (_("invalid register number (%d)"), regno
);
9310 if (s
[1] == 'r' && s
[2] == 'a')
9315 else if (s
[1] == 'f' && s
[2] == 'p')
9320 else if (s
[1] == 's' && s
[2] == 'p')
9325 else if (s
[1] == 'g' && s
[2] == 'p')
9330 else if (s
[1] == 'a' && s
[2] == 't')
9335 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9340 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9345 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9358 if (c
== 'v' || c
== 'w')
9360 regno
= mips16_to_32_reg_map
[lastregno
];
9374 regno
= mips32_to_16_reg_map
[regno
];
9379 regno
= ILLEGAL_REG
;
9384 regno
= ILLEGAL_REG
;
9389 regno
= ILLEGAL_REG
;
9394 if (regno
== AT
&& ! mips_opts
.noat
)
9395 as_warn (_("used $at without \".set noat\""));
9402 if (regno
== ILLEGAL_REG
)
9409 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9413 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9416 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9419 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9425 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9428 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9429 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9439 if (strncmp (s
, "$pc", 3) == 0)
9456 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9459 if (imm_expr
.X_op
!= O_constant
)
9462 ip
->use_extend
= TRUE
;
9467 /* We need to relax this instruction. */
9468 *offset_reloc
= *imm_reloc
;
9469 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9474 *imm_reloc
= BFD_RELOC_UNUSED
;
9482 my_getExpression (&imm_expr
, s
);
9483 if (imm_expr
.X_op
== O_register
)
9485 /* What we thought was an expression turned out to
9488 if (s
[0] == '(' && args
[1] == '(')
9490 /* It looks like the expression was omitted
9491 before a register indirection, which means
9492 that the expression is implicitly zero. We
9493 still set up imm_expr, so that we handle
9494 explicit extensions correctly. */
9495 imm_expr
.X_op
= O_constant
;
9496 imm_expr
.X_add_number
= 0;
9497 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9504 /* We need to relax this instruction. */
9505 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9514 /* We use offset_reloc rather than imm_reloc for the PC
9515 relative operands. This lets macros with both
9516 immediate and address operands work correctly. */
9517 my_getExpression (&offset_expr
, s
);
9519 if (offset_expr
.X_op
== O_register
)
9522 /* We need to relax this instruction. */
9523 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9527 case '6': /* break code */
9528 my_getExpression (&imm_expr
, s
);
9529 check_absolute_expr (ip
, &imm_expr
);
9530 if ((unsigned long) imm_expr
.X_add_number
> 63)
9532 as_warn (_("Invalid value for `%s' (%lu)"),
9534 (unsigned long) imm_expr
.X_add_number
);
9535 imm_expr
.X_add_number
&= 0x3f;
9537 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9538 imm_expr
.X_op
= O_absent
;
9542 case 'a': /* 26 bit address */
9543 my_getExpression (&offset_expr
, s
);
9545 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9546 ip
->insn_opcode
<<= 16;
9549 case 'l': /* register list for entry macro */
9550 case 'L': /* register list for exit macro */
9560 int freg
, reg1
, reg2
;
9562 while (*s
== ' ' || *s
== ',')
9566 as_bad (_("can't parse register list"));
9578 while (ISDIGIT (*s
))
9600 as_bad (_("invalid register list"));
9605 while (ISDIGIT (*s
))
9612 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9617 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9622 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9623 mask
|= (reg2
- 3) << 3;
9624 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9625 mask
|= (reg2
- 15) << 1;
9626 else if (reg1
== RA
&& reg2
== RA
)
9630 as_bad (_("invalid register list"));
9634 /* The mask is filled in in the opcode table for the
9635 benefit of the disassembler. We remove it before
9636 applying the actual mask. */
9637 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9638 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9642 case 'e': /* extend code */
9643 my_getExpression (&imm_expr
, s
);
9644 check_absolute_expr (ip
, &imm_expr
);
9645 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9647 as_warn (_("Invalid value for `%s' (%lu)"),
9649 (unsigned long) imm_expr
.X_add_number
);
9650 imm_expr
.X_add_number
&= 0x7ff;
9652 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9653 imm_expr
.X_op
= O_absent
;
9663 /* Args don't match. */
9664 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9665 strcmp (insn
->name
, insn
[1].name
) == 0)
9672 insn_error
= _("illegal operands");
9678 /* This structure holds information we know about a mips16 immediate
9681 struct mips16_immed_operand
9683 /* The type code used in the argument string in the opcode table. */
9685 /* The number of bits in the short form of the opcode. */
9687 /* The number of bits in the extended form of the opcode. */
9689 /* The amount by which the short form is shifted when it is used;
9690 for example, the sw instruction has a shift count of 2. */
9692 /* The amount by which the short form is shifted when it is stored
9693 into the instruction code. */
9695 /* Non-zero if the short form is unsigned. */
9697 /* Non-zero if the extended form is unsigned. */
9699 /* Non-zero if the value is PC relative. */
9703 /* The mips16 immediate operand types. */
9705 static const struct mips16_immed_operand mips16_immed_operands
[] =
9707 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9708 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9709 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9710 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9711 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9712 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9713 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9714 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9715 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9716 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9717 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9718 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9719 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9720 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9721 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9722 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9723 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9724 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9725 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9726 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9727 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9730 #define MIPS16_NUM_IMMED \
9731 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9733 /* Handle a mips16 instruction with an immediate value. This or's the
9734 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9735 whether an extended value is needed; if one is needed, it sets
9736 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9737 If SMALL is true, an unextended opcode was explicitly requested.
9738 If EXT is true, an extended opcode was explicitly requested. If
9739 WARN is true, warn if EXT does not match reality. */
9742 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9743 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9744 unsigned long *insn
, bfd_boolean
*use_extend
,
9745 unsigned short *extend
)
9747 register const struct mips16_immed_operand
*op
;
9748 int mintiny
, maxtiny
;
9749 bfd_boolean needext
;
9751 op
= mips16_immed_operands
;
9752 while (op
->type
!= type
)
9755 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9760 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9763 maxtiny
= 1 << op
->nbits
;
9768 maxtiny
= (1 << op
->nbits
) - 1;
9773 mintiny
= - (1 << (op
->nbits
- 1));
9774 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9777 /* Branch offsets have an implicit 0 in the lowest bit. */
9778 if (type
== 'p' || type
== 'q')
9781 if ((val
& ((1 << op
->shift
) - 1)) != 0
9782 || val
< (mintiny
<< op
->shift
)
9783 || val
> (maxtiny
<< op
->shift
))
9788 if (warn
&& ext
&& ! needext
)
9789 as_warn_where (file
, line
,
9790 _("extended operand requested but not required"));
9791 if (small
&& needext
)
9792 as_bad_where (file
, line
, _("invalid unextended operand value"));
9794 if (small
|| (! ext
&& ! needext
))
9798 *use_extend
= FALSE
;
9799 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9800 insnval
<<= op
->op_shift
;
9805 long minext
, maxext
;
9811 maxext
= (1 << op
->extbits
) - 1;
9815 minext
= - (1 << (op
->extbits
- 1));
9816 maxext
= (1 << (op
->extbits
- 1)) - 1;
9818 if (val
< minext
|| val
> maxext
)
9819 as_bad_where (file
, line
,
9820 _("operand value out of range for instruction"));
9823 if (op
->extbits
== 16)
9825 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9828 else if (op
->extbits
== 15)
9830 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9835 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9839 *extend
= (unsigned short) extval
;
9844 struct percent_op_match
9847 bfd_reloc_code_real_type reloc
;
9850 static const struct percent_op_match mips_percent_op
[] =
9852 {"%lo", BFD_RELOC_LO16
},
9854 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9855 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9856 {"%call16", BFD_RELOC_MIPS_CALL16
},
9857 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9858 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9859 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9860 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9861 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9862 {"%got", BFD_RELOC_MIPS_GOT16
},
9863 {"%gp_rel", BFD_RELOC_GPREL16
},
9864 {"%half", BFD_RELOC_16
},
9865 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9866 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9867 {"%neg", BFD_RELOC_MIPS_SUB
},
9869 {"%hi", BFD_RELOC_HI16_S
}
9872 static const struct percent_op_match mips16_percent_op
[] =
9874 {"%lo", BFD_RELOC_MIPS16_LO16
},
9875 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
9876 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
9880 /* Return true if *STR points to a relocation operator. When returning true,
9881 move *STR over the operator and store its relocation code in *RELOC.
9882 Leave both *STR and *RELOC alone when returning false. */
9885 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9887 const struct percent_op_match
*percent_op
;
9890 if (mips_opts
.mips16
)
9892 percent_op
= mips16_percent_op
;
9893 limit
= ARRAY_SIZE (mips16_percent_op
);
9897 percent_op
= mips_percent_op
;
9898 limit
= ARRAY_SIZE (mips_percent_op
);
9901 for (i
= 0; i
< limit
; i
++)
9902 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9904 *str
+= strlen (percent_op
[i
].str
);
9905 *reloc
= percent_op
[i
].reloc
;
9907 /* Check whether the output BFD supports this relocation.
9908 If not, issue an error and fall back on something safe. */
9909 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9911 as_bad ("relocation %s isn't supported by the current ABI",
9913 *reloc
= BFD_RELOC_UNUSED
;
9921 /* Parse string STR as a 16-bit relocatable operand. Store the
9922 expression in *EP and the relocations in the array starting
9923 at RELOC. Return the number of relocation operators used.
9925 On exit, EXPR_END points to the first character after the expression. */
9928 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9931 bfd_reloc_code_real_type reversed_reloc
[3];
9932 size_t reloc_index
, i
;
9933 int crux_depth
, str_depth
;
9936 /* Search for the start of the main expression, recoding relocations
9937 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9938 of the main expression and with CRUX_DEPTH containing the number
9939 of open brackets at that point. */
9946 crux_depth
= str_depth
;
9948 /* Skip over whitespace and brackets, keeping count of the number
9950 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9955 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9956 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9958 my_getExpression (ep
, crux
);
9961 /* Match every open bracket. */
9962 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9967 as_bad ("unclosed '('");
9971 if (reloc_index
!= 0)
9973 prev_reloc_op_frag
= frag_now
;
9974 for (i
= 0; i
< reloc_index
; i
++)
9975 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9982 my_getExpression (expressionS
*ep
, char *str
)
9987 save_in
= input_line_pointer
;
9988 input_line_pointer
= str
;
9990 expr_end
= input_line_pointer
;
9991 input_line_pointer
= save_in
;
9993 /* If we are in mips16 mode, and this is an expression based on `.',
9994 then we bump the value of the symbol by 1 since that is how other
9995 text symbols are handled. We don't bother to handle complex
9996 expressions, just `.' plus or minus a constant. */
9997 if (mips_opts
.mips16
9998 && ep
->X_op
== O_symbol
9999 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10000 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10001 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10002 && symbol_constant_p (ep
->X_add_symbol
)
10003 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10004 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10007 /* Turn a string in input_line_pointer into a floating point constant
10008 of type TYPE, and store the appropriate bytes in *LITP. The number
10009 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10010 returned, or NULL on OK. */
10013 md_atof (int type
, char *litP
, int *sizeP
)
10016 LITTLENUM_TYPE words
[4];
10032 return _("bad call to md_atof");
10035 t
= atof_ieee (input_line_pointer
, type
, words
);
10037 input_line_pointer
= t
;
10041 if (! target_big_endian
)
10043 for (i
= prec
- 1; i
>= 0; i
--)
10045 md_number_to_chars (litP
, words
[i
], 2);
10051 for (i
= 0; i
< prec
; i
++)
10053 md_number_to_chars (litP
, words
[i
], 2);
10062 md_number_to_chars (char *buf
, valueT val
, int n
)
10064 if (target_big_endian
)
10065 number_to_chars_bigendian (buf
, val
, n
);
10067 number_to_chars_littleendian (buf
, val
, n
);
10071 static int support_64bit_objects(void)
10073 const char **list
, **l
;
10076 list
= bfd_target_list ();
10077 for (l
= list
; *l
!= NULL
; l
++)
10079 /* This is traditional mips */
10080 if (strcmp (*l
, "elf64-tradbigmips") == 0
10081 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10083 if (strcmp (*l
, "elf64-bigmips") == 0
10084 || strcmp (*l
, "elf64-littlemips") == 0)
10087 yes
= (*l
!= NULL
);
10091 #endif /* OBJ_ELF */
10093 const char *md_shortopts
= "O::g::G:";
10095 struct option md_longopts
[] =
10097 /* Options which specify architecture. */
10098 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10099 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10100 {"march", required_argument
, NULL
, OPTION_MARCH
},
10101 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10102 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10103 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10104 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10105 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10106 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10107 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10108 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10109 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10110 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10111 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10112 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10113 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10114 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10115 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10116 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10117 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10118 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10119 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10120 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10121 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10123 /* Options which specify Application Specific Extensions (ASEs). */
10124 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10125 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10126 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10127 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10128 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10129 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10130 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10131 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10132 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10133 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10134 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10135 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10136 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10138 /* Old-style architecture options. Don't add more of these. */
10139 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10140 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10141 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10142 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10143 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10144 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10145 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10146 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10147 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10148 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10149 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10150 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10151 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10152 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10153 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10154 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10155 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10157 /* Options which enable bug fixes. */
10158 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10159 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10160 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10161 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10162 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10163 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10164 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10165 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10166 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10167 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10169 /* Miscellaneous options. */
10170 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10171 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10172 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10173 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10174 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10175 {"break", no_argument
, NULL
, OPTION_BREAK
},
10176 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10177 #define OPTION_EB (OPTION_MISC_BASE + 2)
10178 {"EB", no_argument
, NULL
, OPTION_EB
},
10179 #define OPTION_EL (OPTION_MISC_BASE + 3)
10180 {"EL", no_argument
, NULL
, OPTION_EL
},
10181 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10182 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10183 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10184 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10185 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10186 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10187 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10188 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10189 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10190 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10191 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10192 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10193 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10194 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10195 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10196 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10197 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10198 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10199 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10200 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10202 /* ELF-specific options. */
10204 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14)
10205 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10206 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10207 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10208 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10209 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10210 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10211 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10212 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10213 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10214 #define OPTION_32 (OPTION_ELF_BASE + 4)
10215 {"32", no_argument
, NULL
, OPTION_32
},
10216 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10217 {"n32", no_argument
, NULL
, OPTION_N32
},
10218 #define OPTION_64 (OPTION_ELF_BASE + 6)
10219 {"64", no_argument
, NULL
, OPTION_64
},
10220 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10221 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10222 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10223 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10224 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10225 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10226 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10227 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10228 #endif /* OBJ_ELF */
10230 {NULL
, no_argument
, NULL
, 0}
10232 size_t md_longopts_size
= sizeof (md_longopts
);
10234 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10235 NEW_VALUE. Warn if another value was already specified. Note:
10236 we have to defer parsing the -march and -mtune arguments in order
10237 to handle 'from-abi' correctly, since the ABI might be specified
10238 in a later argument. */
10241 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10243 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10244 as_warn (_("A different %s was already specified, is now %s"),
10245 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10248 *string_ptr
= new_value
;
10252 md_parse_option (int c
, char *arg
)
10256 case OPTION_CONSTRUCT_FLOATS
:
10257 mips_disable_float_construction
= 0;
10260 case OPTION_NO_CONSTRUCT_FLOATS
:
10261 mips_disable_float_construction
= 1;
10273 target_big_endian
= 1;
10277 target_big_endian
= 0;
10281 if (arg
&& arg
[1] == '0')
10291 mips_debug
= atoi (arg
);
10292 /* When the MIPS assembler sees -g or -g2, it does not do
10293 optimizations which limit full symbolic debugging. We take
10294 that to be equivalent to -O0. */
10295 if (mips_debug
== 2)
10300 file_mips_isa
= ISA_MIPS1
;
10304 file_mips_isa
= ISA_MIPS2
;
10308 file_mips_isa
= ISA_MIPS3
;
10312 file_mips_isa
= ISA_MIPS4
;
10316 file_mips_isa
= ISA_MIPS5
;
10319 case OPTION_MIPS32
:
10320 file_mips_isa
= ISA_MIPS32
;
10323 case OPTION_MIPS32R2
:
10324 file_mips_isa
= ISA_MIPS32R2
;
10327 case OPTION_MIPS64R2
:
10328 file_mips_isa
= ISA_MIPS64R2
;
10331 case OPTION_MIPS64
:
10332 file_mips_isa
= ISA_MIPS64
;
10336 mips_set_option_string (&mips_tune_string
, arg
);
10340 mips_set_option_string (&mips_arch_string
, arg
);
10344 mips_set_option_string (&mips_arch_string
, "4650");
10345 mips_set_option_string (&mips_tune_string
, "4650");
10348 case OPTION_NO_M4650
:
10352 mips_set_option_string (&mips_arch_string
, "4010");
10353 mips_set_option_string (&mips_tune_string
, "4010");
10356 case OPTION_NO_M4010
:
10360 mips_set_option_string (&mips_arch_string
, "4100");
10361 mips_set_option_string (&mips_tune_string
, "4100");
10364 case OPTION_NO_M4100
:
10368 mips_set_option_string (&mips_arch_string
, "3900");
10369 mips_set_option_string (&mips_tune_string
, "3900");
10372 case OPTION_NO_M3900
:
10376 mips_opts
.ase_mdmx
= 1;
10379 case OPTION_NO_MDMX
:
10380 mips_opts
.ase_mdmx
= 0;
10383 case OPTION_MIPS16
:
10384 mips_opts
.mips16
= 1;
10385 mips_no_prev_insn (FALSE
);
10388 case OPTION_NO_MIPS16
:
10389 mips_opts
.mips16
= 0;
10390 mips_no_prev_insn (FALSE
);
10393 case OPTION_MIPS3D
:
10394 mips_opts
.ase_mips3d
= 1;
10397 case OPTION_NO_MIPS3D
:
10398 mips_opts
.ase_mips3d
= 0;
10401 case OPTION_FIX_VR4120
:
10402 mips_fix_vr4120
= 1;
10405 case OPTION_NO_FIX_VR4120
:
10406 mips_fix_vr4120
= 0;
10409 case OPTION_RELAX_BRANCH
:
10410 mips_relax_branch
= 1;
10413 case OPTION_NO_RELAX_BRANCH
:
10414 mips_relax_branch
= 0;
10417 case OPTION_MSHARED
:
10418 mips_in_shared
= TRUE
;
10421 case OPTION_MNO_SHARED
:
10422 mips_in_shared
= FALSE
;
10426 /* When generating ELF code, we permit -KPIC and -call_shared to
10427 select SVR4_PIC, and -non_shared to select no PIC. This is
10428 intended to be compatible with Irix 5. */
10429 case OPTION_CALL_SHARED
:
10430 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10432 as_bad (_("-call_shared is supported only for ELF format"));
10435 mips_pic
= SVR4_PIC
;
10436 mips_abicalls
= TRUE
;
10437 if (g_switch_seen
&& g_switch_value
!= 0)
10439 as_bad (_("-G may not be used with SVR4 PIC code"));
10442 g_switch_value
= 0;
10445 case OPTION_NON_SHARED
:
10446 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10448 as_bad (_("-non_shared is supported only for ELF format"));
10452 mips_abicalls
= FALSE
;
10455 /* The -xgot option tells the assembler to use 32 offsets when
10456 accessing the got in SVR4_PIC mode. It is for Irix
10461 #endif /* OBJ_ELF */
10464 if (mips_pic
== SVR4_PIC
)
10466 as_bad (_("-G may not be used with SVR4 PIC code"));
10470 g_switch_value
= atoi (arg
);
10475 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10478 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10480 as_bad (_("-32 is supported for ELF format only"));
10483 mips_abi
= O32_ABI
;
10487 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10489 as_bad (_("-n32 is supported for ELF format only"));
10492 mips_abi
= N32_ABI
;
10496 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10498 as_bad (_("-64 is supported for ELF format only"));
10501 mips_abi
= N64_ABI
;
10502 if (! support_64bit_objects())
10503 as_fatal (_("No compiled in support for 64 bit object file format"));
10505 #endif /* OBJ_ELF */
10508 file_mips_gp32
= 1;
10512 file_mips_gp32
= 0;
10516 file_mips_fp32
= 1;
10520 file_mips_fp32
= 0;
10525 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10527 as_bad (_("-mabi is supported for ELF format only"));
10530 if (strcmp (arg
, "32") == 0)
10531 mips_abi
= O32_ABI
;
10532 else if (strcmp (arg
, "o64") == 0)
10533 mips_abi
= O64_ABI
;
10534 else if (strcmp (arg
, "n32") == 0)
10535 mips_abi
= N32_ABI
;
10536 else if (strcmp (arg
, "64") == 0)
10538 mips_abi
= N64_ABI
;
10539 if (! support_64bit_objects())
10540 as_fatal (_("No compiled in support for 64 bit object file "
10543 else if (strcmp (arg
, "eabi") == 0)
10544 mips_abi
= EABI_ABI
;
10547 as_fatal (_("invalid abi -mabi=%s"), arg
);
10551 #endif /* OBJ_ELF */
10553 case OPTION_M7000_HILO_FIX
:
10554 mips_7000_hilo_fix
= TRUE
;
10557 case OPTION_MNO_7000_HILO_FIX
:
10558 mips_7000_hilo_fix
= FALSE
;
10562 case OPTION_MDEBUG
:
10563 mips_flag_mdebug
= TRUE
;
10566 case OPTION_NO_MDEBUG
:
10567 mips_flag_mdebug
= FALSE
;
10571 mips_flag_pdr
= TRUE
;
10574 case OPTION_NO_PDR
:
10575 mips_flag_pdr
= FALSE
;
10577 #endif /* OBJ_ELF */
10586 /* Set up globals to generate code for the ISA or processor
10587 described by INFO. */
10590 mips_set_architecture (const struct mips_cpu_info
*info
)
10594 file_mips_arch
= info
->cpu
;
10595 mips_opts
.arch
= info
->cpu
;
10596 mips_opts
.isa
= info
->isa
;
10601 /* Likewise for tuning. */
10604 mips_set_tune (const struct mips_cpu_info
*info
)
10607 mips_tune
= info
->cpu
;
10612 mips_after_parse_args (void)
10614 const struct mips_cpu_info
*arch_info
= 0;
10615 const struct mips_cpu_info
*tune_info
= 0;
10617 /* GP relative stuff not working for PE */
10618 if (strncmp (TARGET_OS
, "pe", 2) == 0
10619 && g_switch_value
!= 0)
10622 as_bad (_("-G not supported in this configuration."));
10623 g_switch_value
= 0;
10626 if (mips_abi
== NO_ABI
)
10627 mips_abi
= MIPS_DEFAULT_ABI
;
10629 /* The following code determines the architecture and register size.
10630 Similar code was added to GCC 3.3 (see override_options() in
10631 config/mips/mips.c). The GAS and GCC code should be kept in sync
10632 as much as possible. */
10634 if (mips_arch_string
!= 0)
10635 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10637 if (file_mips_isa
!= ISA_UNKNOWN
)
10639 /* Handle -mipsN. At this point, file_mips_isa contains the
10640 ISA level specified by -mipsN, while arch_info->isa contains
10641 the -march selection (if any). */
10642 if (arch_info
!= 0)
10644 /* -march takes precedence over -mipsN, since it is more descriptive.
10645 There's no harm in specifying both as long as the ISA levels
10647 if (file_mips_isa
!= arch_info
->isa
)
10648 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10649 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10650 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10653 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10656 if (arch_info
== 0)
10657 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10659 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10660 as_bad ("-march=%s is not compatible with the selected ABI",
10663 mips_set_architecture (arch_info
);
10665 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10666 if (mips_tune_string
!= 0)
10667 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10669 if (tune_info
== 0)
10670 mips_set_tune (arch_info
);
10672 mips_set_tune (tune_info
);
10674 if (file_mips_gp32
>= 0)
10676 /* The user specified the size of the integer registers. Make sure
10677 it agrees with the ABI and ISA. */
10678 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10679 as_bad (_("-mgp64 used with a 32-bit processor"));
10680 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10681 as_bad (_("-mgp32 used with a 64-bit ABI"));
10682 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10683 as_bad (_("-mgp64 used with a 32-bit ABI"));
10687 /* Infer the integer register size from the ABI and processor.
10688 Restrict ourselves to 32-bit registers if that's all the
10689 processor has, or if the ABI cannot handle 64-bit registers. */
10690 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10691 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10694 /* ??? GAS treats single-float processors as though they had 64-bit
10695 float registers (although it complains when double-precision
10696 instructions are used). As things stand, saying they have 32-bit
10697 registers would lead to spurious "register must be even" messages.
10698 So here we assume float registers are always the same size as
10699 integer ones, unless the user says otherwise. */
10700 if (file_mips_fp32
< 0)
10701 file_mips_fp32
= file_mips_gp32
;
10703 /* End of GCC-shared inference code. */
10705 /* This flag is set when we have a 64-bit capable CPU but use only
10706 32-bit wide registers. Note that EABI does not use it. */
10707 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10708 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10709 || mips_abi
== O32_ABI
))
10710 mips_32bitmode
= 1;
10712 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10713 as_bad (_("trap exception not supported at ISA 1"));
10715 /* If the selected architecture includes support for ASEs, enable
10716 generation of code for them. */
10717 if (mips_opts
.mips16
== -1)
10718 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10719 if (mips_opts
.ase_mips3d
== -1)
10720 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10721 if (mips_opts
.ase_mdmx
== -1)
10722 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10724 file_mips_isa
= mips_opts
.isa
;
10725 file_ase_mips16
= mips_opts
.mips16
;
10726 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10727 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10728 mips_opts
.gp32
= file_mips_gp32
;
10729 mips_opts
.fp32
= file_mips_fp32
;
10731 if (mips_flag_mdebug
< 0)
10733 #ifdef OBJ_MAYBE_ECOFF
10734 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10735 mips_flag_mdebug
= 1;
10737 #endif /* OBJ_MAYBE_ECOFF */
10738 mips_flag_mdebug
= 0;
10743 mips_init_after_args (void)
10745 /* initialize opcodes */
10746 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10747 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10751 md_pcrel_from (fixS
*fixP
)
10753 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10754 switch (fixP
->fx_r_type
)
10756 case BFD_RELOC_16_PCREL_S2
:
10757 case BFD_RELOC_MIPS_JMP
:
10758 /* Return the address of the delay slot. */
10765 /* This is called before the symbol table is processed. In order to
10766 work with gcc when using mips-tfile, we must keep all local labels.
10767 However, in other cases, we want to discard them. If we were
10768 called with -g, but we didn't see any debugging information, it may
10769 mean that gcc is smuggling debugging information through to
10770 mips-tfile, in which case we must generate all local labels. */
10773 mips_frob_file_before_adjust (void)
10775 #ifndef NO_ECOFF_DEBUGGING
10776 if (ECOFF_DEBUGGING
10778 && ! ecoff_debugging_seen
)
10779 flag_keep_locals
= 1;
10783 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10784 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10785 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10786 relocation operators.
10788 For our purposes, a %lo() expression matches a %got() or %hi()
10791 (a) it refers to the same symbol; and
10792 (b) the offset applied in the %lo() expression is no lower than
10793 the offset applied in the %got() or %hi().
10795 (b) allows us to cope with code like:
10798 lh $4,%lo(foo+2)($4)
10800 ...which is legal on RELA targets, and has a well-defined behaviour
10801 if the user knows that adding 2 to "foo" will not induce a carry to
10804 When several %lo()s match a particular %got() or %hi(), we use the
10805 following rules to distinguish them:
10807 (1) %lo()s with smaller offsets are a better match than %lo()s with
10810 (2) %lo()s with no matching %got() or %hi() are better than those
10811 that already have a matching %got() or %hi().
10813 (3) later %lo()s are better than earlier %lo()s.
10815 These rules are applied in order.
10817 (1) means, among other things, that %lo()s with identical offsets are
10818 chosen if they exist.
10820 (2) means that we won't associate several high-part relocations with
10821 the same low-part relocation unless there's no alternative. Having
10822 several high parts for the same low part is a GNU extension; this rule
10823 allows careful users to avoid it.
10825 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10826 with the last high-part relocation being at the front of the list.
10827 It therefore makes sense to choose the last matching low-part
10828 relocation, all other things being equal. It's also easier
10829 to code that way. */
10832 mips_frob_file (void)
10834 struct mips_hi_fixup
*l
;
10836 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10838 segment_info_type
*seginfo
;
10839 bfd_boolean matched_lo_p
;
10840 fixS
**hi_pos
, **lo_pos
, **pos
;
10842 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10844 /* If a GOT16 relocation turns out to be against a global symbol,
10845 there isn't supposed to be a matching LO. */
10846 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10847 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10850 /* Check quickly whether the next fixup happens to be a matching %lo. */
10851 if (fixup_has_matching_lo_p (l
->fixp
))
10854 seginfo
= seg_info (l
->seg
);
10856 /* Set HI_POS to the position of this relocation in the chain.
10857 Set LO_POS to the position of the chosen low-part relocation.
10858 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10859 relocation that matches an immediately-preceding high-part
10863 matched_lo_p
= FALSE
;
10864 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10866 if (*pos
== l
->fixp
)
10869 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10870 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10871 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10873 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10875 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10878 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10879 && fixup_has_matching_lo_p (*pos
));
10882 /* If we found a match, remove the high-part relocation from its
10883 current position and insert it before the low-part relocation.
10884 Make the offsets match so that fixup_has_matching_lo_p()
10887 We don't warn about unmatched high-part relocations since some
10888 versions of gcc have been known to emit dead "lui ...%hi(...)"
10890 if (lo_pos
!= NULL
)
10892 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10893 if (l
->fixp
->fx_next
!= *lo_pos
)
10895 *hi_pos
= l
->fixp
->fx_next
;
10896 l
->fixp
->fx_next
= *lo_pos
;
10903 /* We may have combined relocations without symbols in the N32/N64 ABI.
10904 We have to prevent gas from dropping them. */
10907 mips_force_relocation (fixS
*fixp
)
10909 if (generic_force_reloc (fixp
))
10913 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10914 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10915 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10916 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10922 /* This hook is called before a fix is simplified. We don't really
10923 decide whether to skip a fix here. Rather, we turn global symbols
10924 used as branch targets into local symbols, such that they undergo
10925 simplification. We can only do this if the symbol is defined and
10926 it is in the same section as the branch. If this doesn't hold, we
10927 emit a better error message than just saying the relocation is not
10928 valid for the selected object format.
10930 FIXP is the fix-up we're going to try to simplify, SEG is the
10931 segment in which the fix up occurs. The return value should be
10932 non-zero to indicate the fix-up is valid for further
10933 simplifications. */
10936 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10938 /* There's a lot of discussion on whether it should be possible to
10939 use R_MIPS_PC16 to represent branch relocations. The outcome
10940 seems to be that it can, but gas/bfd are very broken in creating
10941 RELA relocations for this, so for now we only accept branches to
10942 symbols in the same section. Anything else is of dubious value,
10943 since there's no guarantee that at link time the symbol would be
10944 in range. Even for branches to local symbols this is arguably
10945 wrong, since it we assume the symbol is not going to be
10946 overridden, which should be possible per ELF library semantics,
10947 but then, there isn't a dynamic relocation that could be used to
10948 this effect, and the target would likely be out of range as well.
10950 Unfortunately, it seems that there is too much code out there
10951 that relies on branches to symbols that are global to be resolved
10952 as if they were local, like the IRIX tools do, so we do it as
10953 well, but with a warning so that people are reminded to fix their
10954 code. If we ever get back to using R_MIPS_PC16 for branch
10955 targets, this entire block should go away (and probably the
10956 whole function). */
10958 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10959 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10960 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10961 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10964 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10967 _("Cannot branch to undefined symbol."));
10968 /* Avoid any further errors about this fixup. */
10971 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10974 _("Cannot branch to symbol in another section."));
10977 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10979 symbolS
*sym
= fixP
->fx_addsy
;
10981 if (mips_pic
== SVR4_PIC
)
10982 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10983 _("Pretending global symbol used as branch target is local."));
10985 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10986 S_GET_SEGMENT (sym
),
10988 symbol_get_frag (sym
));
10989 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10990 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10991 assert (symbol_resolved_p (sym
));
10992 symbol_mark_resolved (fixP
->fx_addsy
);
10999 /* Apply a fixup to the object file. */
11002 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11006 reloc_howto_type
*howto
;
11008 /* We ignore generic BFD relocations we don't know about. */
11009 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11013 assert (fixP
->fx_size
== 4
11014 || fixP
->fx_r_type
== BFD_RELOC_16
11015 || fixP
->fx_r_type
== BFD_RELOC_64
11016 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11017 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11018 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11019 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11021 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11023 assert (! fixP
->fx_pcrel
);
11025 /* Don't treat parts of a composite relocation as done. There are two
11028 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11029 should nevertheless be emitted if the first part is.
11031 (2) In normal usage, composite relocations are never assembly-time
11032 constants. The easiest way of dealing with the pathological
11033 exceptions is to generate a relocation against STN_UNDEF and
11034 leave everything up to the linker. */
11035 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
11038 switch (fixP
->fx_r_type
)
11040 case BFD_RELOC_MIPS_JMP
:
11041 case BFD_RELOC_MIPS_SHIFT5
:
11042 case BFD_RELOC_MIPS_SHIFT6
:
11043 case BFD_RELOC_MIPS_GOT_DISP
:
11044 case BFD_RELOC_MIPS_GOT_PAGE
:
11045 case BFD_RELOC_MIPS_GOT_OFST
:
11046 case BFD_RELOC_MIPS_SUB
:
11047 case BFD_RELOC_MIPS_INSERT_A
:
11048 case BFD_RELOC_MIPS_INSERT_B
:
11049 case BFD_RELOC_MIPS_DELETE
:
11050 case BFD_RELOC_MIPS_HIGHEST
:
11051 case BFD_RELOC_MIPS_HIGHER
:
11052 case BFD_RELOC_MIPS_SCN_DISP
:
11053 case BFD_RELOC_MIPS_REL16
:
11054 case BFD_RELOC_MIPS_RELGOT
:
11055 case BFD_RELOC_MIPS_JALR
:
11056 case BFD_RELOC_HI16
:
11057 case BFD_RELOC_HI16_S
:
11058 case BFD_RELOC_GPREL16
:
11059 case BFD_RELOC_MIPS_LITERAL
:
11060 case BFD_RELOC_MIPS_CALL16
:
11061 case BFD_RELOC_MIPS_GOT16
:
11062 case BFD_RELOC_GPREL32
:
11063 case BFD_RELOC_MIPS_GOT_HI16
:
11064 case BFD_RELOC_MIPS_GOT_LO16
:
11065 case BFD_RELOC_MIPS_CALL_HI16
:
11066 case BFD_RELOC_MIPS_CALL_LO16
:
11067 case BFD_RELOC_MIPS16_GPREL
:
11068 case BFD_RELOC_MIPS16_HI16
:
11069 case BFD_RELOC_MIPS16_HI16_S
:
11070 assert (! fixP
->fx_pcrel
);
11071 /* Nothing needed to do. The value comes from the reloc entry */
11074 case BFD_RELOC_MIPS16_JMP
:
11075 /* We currently always generate a reloc against a symbol, which
11076 means that we don't want an addend even if the symbol is
11082 /* This is handled like BFD_RELOC_32, but we output a sign
11083 extended value if we are only 32 bits. */
11086 if (8 <= sizeof (valueT
))
11087 md_number_to_chars (buf
, *valP
, 8);
11092 if ((*valP
& 0x80000000) != 0)
11096 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11098 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11104 case BFD_RELOC_RVA
:
11106 /* If we are deleting this reloc entry, we must fill in the
11107 value now. This can happen if we have a .word which is not
11108 resolved when it appears but is later defined. */
11110 md_number_to_chars (buf
, *valP
, 4);
11114 /* If we are deleting this reloc entry, we must fill in the
11117 md_number_to_chars (buf
, *valP
, 2);
11120 case BFD_RELOC_LO16
:
11121 case BFD_RELOC_MIPS16_LO16
:
11122 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11123 may be safe to remove, but if so it's not obvious. */
11124 /* When handling an embedded PIC switch statement, we can wind
11125 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11128 if (*valP
+ 0x8000 > 0xffff)
11129 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11130 _("relocation overflow"));
11131 if (target_big_endian
)
11133 md_number_to_chars (buf
, *valP
, 2);
11137 case BFD_RELOC_16_PCREL_S2
:
11138 if ((*valP
& 0x3) != 0)
11139 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11140 _("Branch to odd address (%lx)"), (long) *valP
);
11143 * We need to save the bits in the instruction since fixup_segment()
11144 * might be deleting the relocation entry (i.e., a branch within
11145 * the current segment).
11147 if (! fixP
->fx_done
)
11150 /* update old instruction data */
11151 if (target_big_endian
)
11152 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11154 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11156 if (*valP
+ 0x20000 <= 0x3ffff)
11158 insn
|= (*valP
>> 2) & 0xffff;
11159 md_number_to_chars (buf
, insn
, 4);
11161 else if (mips_pic
== NO_PIC
11163 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11164 && (fixP
->fx_frag
->fr_address
11165 < text_section
->vma
+ bfd_get_section_size (text_section
))
11166 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11167 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11168 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11170 /* The branch offset is too large. If this is an
11171 unconditional branch, and we are not generating PIC code,
11172 we can convert it to an absolute jump instruction. */
11173 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11174 insn
= 0x0c000000; /* jal */
11176 insn
= 0x08000000; /* j */
11177 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11179 fixP
->fx_addsy
= section_symbol (text_section
);
11180 *valP
+= md_pcrel_from (fixP
);
11181 md_number_to_chars (buf
, insn
, 4);
11185 /* If we got here, we have branch-relaxation disabled,
11186 and there's nothing we can do to fix this instruction
11187 without turning it into a longer sequence. */
11188 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11189 _("Branch out of range"));
11193 case BFD_RELOC_VTABLE_INHERIT
:
11196 && !S_IS_DEFINED (fixP
->fx_addsy
)
11197 && !S_IS_WEAK (fixP
->fx_addsy
))
11198 S_SET_WEAK (fixP
->fx_addsy
);
11201 case BFD_RELOC_VTABLE_ENTRY
:
11209 /* Remember value for tc_gen_reloc. */
11210 fixP
->fx_addnumber
= *valP
;
11220 name
= input_line_pointer
;
11221 c
= get_symbol_end ();
11222 p
= (symbolS
*) symbol_find_or_make (name
);
11223 *input_line_pointer
= c
;
11227 /* Align the current frag to a given power of two. The MIPS assembler
11228 also automatically adjusts any preceding label. */
11231 mips_align (int to
, int fill
, symbolS
*label
)
11233 mips_emit_delays (FALSE
);
11234 frag_align (to
, fill
, 0);
11235 record_alignment (now_seg
, to
);
11238 assert (S_GET_SEGMENT (label
) == now_seg
);
11239 symbol_set_frag (label
, frag_now
);
11240 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11244 /* Align to a given power of two. .align 0 turns off the automatic
11245 alignment used by the data creating pseudo-ops. */
11248 s_align (int x ATTRIBUTE_UNUSED
)
11251 register long temp_fill
;
11252 long max_alignment
= 15;
11256 o Note that the assembler pulls down any immediately preceding label
11257 to the aligned address.
11258 o It's not documented but auto alignment is reinstated by
11259 a .align pseudo instruction.
11260 o Note also that after auto alignment is turned off the mips assembler
11261 issues an error on attempt to assemble an improperly aligned data item.
11266 temp
= get_absolute_expression ();
11267 if (temp
> max_alignment
)
11268 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11271 as_warn (_("Alignment negative: 0 assumed."));
11274 if (*input_line_pointer
== ',')
11276 ++input_line_pointer
;
11277 temp_fill
= get_absolute_expression ();
11284 mips_align (temp
, (int) temp_fill
,
11285 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11292 demand_empty_rest_of_line ();
11296 mips_flush_pending_output (void)
11298 mips_emit_delays (FALSE
);
11299 mips_clear_insn_labels ();
11303 s_change_sec (int sec
)
11308 /* The ELF backend needs to know that we are changing sections, so
11309 that .previous works correctly. We could do something like check
11310 for an obj_section_change_hook macro, but that might be confusing
11311 as it would not be appropriate to use it in the section changing
11312 functions in read.c, since obj-elf.c intercepts those. FIXME:
11313 This should be cleaner, somehow. */
11314 obj_elf_section_change_hook ();
11317 mips_emit_delays (FALSE
);
11327 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11328 demand_empty_rest_of_line ();
11332 seg
= subseg_new (RDATA_SECTION_NAME
,
11333 (subsegT
) get_absolute_expression ());
11334 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11336 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11337 | SEC_READONLY
| SEC_RELOC
11339 if (strcmp (TARGET_OS
, "elf") != 0)
11340 record_alignment (seg
, 4);
11342 demand_empty_rest_of_line ();
11346 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11347 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11349 bfd_set_section_flags (stdoutput
, seg
,
11350 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11351 if (strcmp (TARGET_OS
, "elf") != 0)
11352 record_alignment (seg
, 4);
11354 demand_empty_rest_of_line ();
11362 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11365 char *section_name
;
11370 int section_entry_size
;
11371 int section_alignment
;
11373 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11376 section_name
= input_line_pointer
;
11377 c
= get_symbol_end ();
11379 next_c
= *(input_line_pointer
+ 1);
11381 /* Do we have .section Name<,"flags">? */
11382 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11384 /* just after name is now '\0'. */
11385 *input_line_pointer
= c
;
11386 input_line_pointer
= section_name
;
11387 obj_elf_section (ignore
);
11390 input_line_pointer
++;
11392 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11394 section_type
= get_absolute_expression ();
11397 if (*input_line_pointer
++ == ',')
11398 section_flag
= get_absolute_expression ();
11401 if (*input_line_pointer
++ == ',')
11402 section_entry_size
= get_absolute_expression ();
11404 section_entry_size
= 0;
11405 if (*input_line_pointer
++ == ',')
11406 section_alignment
= get_absolute_expression ();
11408 section_alignment
= 0;
11410 section_name
= xstrdup (section_name
);
11412 /* When using the generic form of .section (as implemented by obj-elf.c),
11413 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11414 traditionally had to fall back on the more common @progbits instead.
11416 There's nothing really harmful in this, since bfd will correct
11417 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11418 means that, for backwards compatibiltiy, the special_section entries
11419 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11421 Even so, we shouldn't force users of the MIPS .section syntax to
11422 incorrectly label the sections as SHT_PROGBITS. The best compromise
11423 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11424 generic type-checking code. */
11425 if (section_type
== SHT_MIPS_DWARF
)
11426 section_type
= SHT_PROGBITS
;
11428 obj_elf_change_section (section_name
, section_type
, section_flag
,
11429 section_entry_size
, 0, 0, 0);
11431 if (now_seg
->name
!= section_name
)
11432 free (section_name
);
11433 #endif /* OBJ_ELF */
11437 mips_enable_auto_align (void)
11443 s_cons (int log_size
)
11447 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11448 mips_emit_delays (FALSE
);
11449 if (log_size
> 0 && auto_align
)
11450 mips_align (log_size
, 0, label
);
11451 mips_clear_insn_labels ();
11452 cons (1 << log_size
);
11456 s_float_cons (int type
)
11460 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11462 mips_emit_delays (FALSE
);
11467 mips_align (3, 0, label
);
11469 mips_align (2, 0, label
);
11472 mips_clear_insn_labels ();
11477 /* Handle .globl. We need to override it because on Irix 5 you are
11480 where foo is an undefined symbol, to mean that foo should be
11481 considered to be the address of a function. */
11484 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11491 name
= input_line_pointer
;
11492 c
= get_symbol_end ();
11493 symbolP
= symbol_find_or_make (name
);
11494 *input_line_pointer
= c
;
11495 SKIP_WHITESPACE ();
11497 /* On Irix 5, every global symbol that is not explicitly labelled as
11498 being a function is apparently labelled as being an object. */
11501 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11506 secname
= input_line_pointer
;
11507 c
= get_symbol_end ();
11508 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11510 as_bad (_("%s: no such section"), secname
);
11511 *input_line_pointer
= c
;
11513 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11514 flag
= BSF_FUNCTION
;
11517 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11519 S_SET_EXTERNAL (symbolP
);
11520 demand_empty_rest_of_line ();
11524 s_option (int x ATTRIBUTE_UNUSED
)
11529 opt
= input_line_pointer
;
11530 c
= get_symbol_end ();
11534 /* FIXME: What does this mean? */
11536 else if (strncmp (opt
, "pic", 3) == 0)
11540 i
= atoi (opt
+ 3);
11545 mips_pic
= SVR4_PIC
;
11546 mips_abicalls
= TRUE
;
11549 as_bad (_(".option pic%d not supported"), i
);
11551 if (mips_pic
== SVR4_PIC
)
11553 if (g_switch_seen
&& g_switch_value
!= 0)
11554 as_warn (_("-G may not be used with SVR4 PIC code"));
11555 g_switch_value
= 0;
11556 bfd_set_gp_size (stdoutput
, 0);
11560 as_warn (_("Unrecognized option \"%s\""), opt
);
11562 *input_line_pointer
= c
;
11563 demand_empty_rest_of_line ();
11566 /* This structure is used to hold a stack of .set values. */
11568 struct mips_option_stack
11570 struct mips_option_stack
*next
;
11571 struct mips_set_options options
;
11574 static struct mips_option_stack
*mips_opts_stack
;
11576 /* Handle the .set pseudo-op. */
11579 s_mipsset (int x ATTRIBUTE_UNUSED
)
11581 char *name
= input_line_pointer
, ch
;
11583 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11584 ++input_line_pointer
;
11585 ch
= *input_line_pointer
;
11586 *input_line_pointer
= '\0';
11588 if (strcmp (name
, "reorder") == 0)
11590 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11592 /* If we still have pending nops, we can discard them. The
11593 usual nop handling will insert any that are still
11595 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11596 * (mips_opts
.mips16
? 2 : 4));
11597 prev_nop_frag
= NULL
;
11599 mips_opts
.noreorder
= 0;
11601 else if (strcmp (name
, "noreorder") == 0)
11603 mips_emit_delays (TRUE
);
11604 mips_opts
.noreorder
= 1;
11605 mips_any_noreorder
= 1;
11607 else if (strcmp (name
, "at") == 0)
11609 mips_opts
.noat
= 0;
11611 else if (strcmp (name
, "noat") == 0)
11613 mips_opts
.noat
= 1;
11615 else if (strcmp (name
, "macro") == 0)
11617 mips_opts
.warn_about_macros
= 0;
11619 else if (strcmp (name
, "nomacro") == 0)
11621 if (mips_opts
.noreorder
== 0)
11622 as_bad (_("`noreorder' must be set before `nomacro'"));
11623 mips_opts
.warn_about_macros
= 1;
11625 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11627 mips_opts
.nomove
= 0;
11629 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11631 mips_opts
.nomove
= 1;
11633 else if (strcmp (name
, "bopt") == 0)
11635 mips_opts
.nobopt
= 0;
11637 else if (strcmp (name
, "nobopt") == 0)
11639 mips_opts
.nobopt
= 1;
11641 else if (strcmp (name
, "mips16") == 0
11642 || strcmp (name
, "MIPS-16") == 0)
11643 mips_opts
.mips16
= 1;
11644 else if (strcmp (name
, "nomips16") == 0
11645 || strcmp (name
, "noMIPS-16") == 0)
11646 mips_opts
.mips16
= 0;
11647 else if (strcmp (name
, "mips3d") == 0)
11648 mips_opts
.ase_mips3d
= 1;
11649 else if (strcmp (name
, "nomips3d") == 0)
11650 mips_opts
.ase_mips3d
= 0;
11651 else if (strcmp (name
, "mdmx") == 0)
11652 mips_opts
.ase_mdmx
= 1;
11653 else if (strcmp (name
, "nomdmx") == 0)
11654 mips_opts
.ase_mdmx
= 0;
11655 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11659 /* Permit the user to change the ISA and architecture on the fly.
11660 Needless to say, misuse can cause serious problems. */
11661 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11664 mips_opts
.isa
= file_mips_isa
;
11665 mips_opts
.arch
= file_mips_arch
;
11667 else if (strncmp (name
, "arch=", 5) == 0)
11669 const struct mips_cpu_info
*p
;
11671 p
= mips_parse_cpu("internal use", name
+ 5);
11673 as_bad (_("unknown architecture %s"), name
+ 5);
11676 mips_opts
.arch
= p
->cpu
;
11677 mips_opts
.isa
= p
->isa
;
11680 else if (strncmp (name
, "mips", 4) == 0)
11682 const struct mips_cpu_info
*p
;
11684 p
= mips_parse_cpu("internal use", name
);
11686 as_bad (_("unknown ISA level %s"), name
+ 4);
11689 mips_opts
.arch
= p
->cpu
;
11690 mips_opts
.isa
= p
->isa
;
11694 as_bad (_("unknown ISA or architecture %s"), name
);
11696 switch (mips_opts
.isa
)
11704 mips_opts
.gp32
= 1;
11705 mips_opts
.fp32
= 1;
11712 mips_opts
.gp32
= 0;
11713 mips_opts
.fp32
= 0;
11716 as_bad (_("unknown ISA level %s"), name
+ 4);
11721 mips_opts
.gp32
= file_mips_gp32
;
11722 mips_opts
.fp32
= file_mips_fp32
;
11725 else if (strcmp (name
, "autoextend") == 0)
11726 mips_opts
.noautoextend
= 0;
11727 else if (strcmp (name
, "noautoextend") == 0)
11728 mips_opts
.noautoextend
= 1;
11729 else if (strcmp (name
, "push") == 0)
11731 struct mips_option_stack
*s
;
11733 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11734 s
->next
= mips_opts_stack
;
11735 s
->options
= mips_opts
;
11736 mips_opts_stack
= s
;
11738 else if (strcmp (name
, "pop") == 0)
11740 struct mips_option_stack
*s
;
11742 s
= mips_opts_stack
;
11744 as_bad (_(".set pop with no .set push"));
11747 /* If we're changing the reorder mode we need to handle
11748 delay slots correctly. */
11749 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11750 mips_emit_delays (TRUE
);
11751 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11753 if (prev_nop_frag
!= NULL
)
11755 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11756 * (mips_opts
.mips16
? 2 : 4));
11757 prev_nop_frag
= NULL
;
11761 mips_opts
= s
->options
;
11762 mips_opts_stack
= s
->next
;
11768 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11770 *input_line_pointer
= ch
;
11771 demand_empty_rest_of_line ();
11774 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11775 .option pic2. It means to generate SVR4 PIC calls. */
11778 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11780 mips_pic
= SVR4_PIC
;
11781 mips_abicalls
= TRUE
;
11783 if (g_switch_seen
&& g_switch_value
!= 0)
11784 as_warn (_("-G may not be used with SVR4 PIC code"));
11785 g_switch_value
= 0;
11787 bfd_set_gp_size (stdoutput
, 0);
11788 demand_empty_rest_of_line ();
11791 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11792 PIC code. It sets the $gp register for the function based on the
11793 function address, which is in the register named in the argument.
11794 This uses a relocation against _gp_disp, which is handled specially
11795 by the linker. The result is:
11796 lui $gp,%hi(_gp_disp)
11797 addiu $gp,$gp,%lo(_gp_disp)
11798 addu $gp,$gp,.cpload argument
11799 The .cpload argument is normally $25 == $t9.
11801 The -mno-shared option changes this to:
11803 addiu $gp,$gp,%lo(_gp)
11804 and the argument is ignored. This saves an instruction, but the
11805 resulting code is not position independent; it uses an absolute
11806 address for _gp. Thus code assembled with -mno-shared can go into
11807 an ordinary executable, but not into a shared library. */
11810 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11816 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11817 .cpload is ignored. */
11818 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11824 /* .cpload should be in a .set noreorder section. */
11825 if (mips_opts
.noreorder
== 0)
11826 as_warn (_(".cpload not in noreorder section"));
11828 reg
= tc_get_register (0);
11830 /* If we need to produce a 64-bit address, we are better off using
11831 the default instruction sequence. */
11832 in_shared
= mips_in_shared
|| HAVE_64BIT_ADDRESSES
;
11834 ex
.X_op
= O_symbol
;
11835 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" : "_gp");
11836 ex
.X_op_symbol
= NULL
;
11837 ex
.X_add_number
= 0;
11839 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11840 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11843 macro_build_lui (&ex
, mips_gp_register
);
11844 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11845 mips_gp_register
, BFD_RELOC_LO16
);
11847 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11848 mips_gp_register
, reg
);
11851 demand_empty_rest_of_line ();
11854 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11855 .cpsetup $reg1, offset|$reg2, label
11857 If offset is given, this results in:
11858 sd $gp, offset($sp)
11859 lui $gp, %hi(%neg(%gp_rel(label)))
11860 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11861 daddu $gp, $gp, $reg1
11863 If $reg2 is given, this results in:
11864 daddu $reg2, $gp, $0
11865 lui $gp, %hi(%neg(%gp_rel(label)))
11866 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11867 daddu $gp, $gp, $reg1
11868 $reg1 is normally $25 == $t9.
11870 The -mno-shared option replaces the last three instructions with
11872 addiu $gp,$gp,%lo(_gp)
11876 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11878 expressionS ex_off
;
11879 expressionS ex_sym
;
11882 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11883 We also need NewABI support. */
11884 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11890 reg1
= tc_get_register (0);
11891 SKIP_WHITESPACE ();
11892 if (*input_line_pointer
!= ',')
11894 as_bad (_("missing argument separator ',' for .cpsetup"));
11898 ++input_line_pointer
;
11899 SKIP_WHITESPACE ();
11900 if (*input_line_pointer
== '$')
11902 mips_cpreturn_register
= tc_get_register (0);
11903 mips_cpreturn_offset
= -1;
11907 mips_cpreturn_offset
= get_absolute_expression ();
11908 mips_cpreturn_register
= -1;
11910 SKIP_WHITESPACE ();
11911 if (*input_line_pointer
!= ',')
11913 as_bad (_("missing argument separator ',' for .cpsetup"));
11917 ++input_line_pointer
;
11918 SKIP_WHITESPACE ();
11919 expression (&ex_sym
);
11922 if (mips_cpreturn_register
== -1)
11924 ex_off
.X_op
= O_constant
;
11925 ex_off
.X_add_symbol
= NULL
;
11926 ex_off
.X_op_symbol
= NULL
;
11927 ex_off
.X_add_number
= mips_cpreturn_offset
;
11929 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11930 BFD_RELOC_LO16
, SP
);
11933 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11934 mips_gp_register
, 0);
11936 if (mips_in_shared
|| HAVE_64BIT_ADDRESSES
)
11938 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11939 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11942 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11943 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11944 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11946 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11947 mips_gp_register
, reg1
);
11953 ex
.X_op
= O_symbol
;
11954 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11955 ex
.X_op_symbol
= NULL
;
11956 ex
.X_add_number
= 0;
11958 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11959 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11961 macro_build_lui (&ex
, mips_gp_register
);
11962 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11963 mips_gp_register
, BFD_RELOC_LO16
);
11968 demand_empty_rest_of_line ();
11972 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11974 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11975 .cplocal is ignored. */
11976 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11982 mips_gp_register
= tc_get_register (0);
11983 demand_empty_rest_of_line ();
11986 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11987 offset from $sp. The offset is remembered, and after making a PIC
11988 call $gp is restored from that location. */
11991 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
11995 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11996 .cprestore is ignored. */
11997 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12003 mips_cprestore_offset
= get_absolute_expression ();
12004 mips_cprestore_valid
= 1;
12006 ex
.X_op
= O_constant
;
12007 ex
.X_add_symbol
= NULL
;
12008 ex
.X_op_symbol
= NULL
;
12009 ex
.X_add_number
= mips_cprestore_offset
;
12012 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12013 SP
, HAVE_64BIT_ADDRESSES
);
12016 demand_empty_rest_of_line ();
12019 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12020 was given in the preceding .cpsetup, it results in:
12021 ld $gp, offset($sp)
12023 If a register $reg2 was given there, it results in:
12024 daddu $gp, $reg2, $0
12027 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12031 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12032 We also need NewABI support. */
12033 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12040 if (mips_cpreturn_register
== -1)
12042 ex
.X_op
= O_constant
;
12043 ex
.X_add_symbol
= NULL
;
12044 ex
.X_op_symbol
= NULL
;
12045 ex
.X_add_number
= mips_cpreturn_offset
;
12047 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12050 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12051 mips_cpreturn_register
, 0);
12054 demand_empty_rest_of_line ();
12057 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12058 code. It sets the offset to use in gp_rel relocations. */
12061 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12063 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12064 We also need NewABI support. */
12065 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12071 mips_gprel_offset
= get_absolute_expression ();
12073 demand_empty_rest_of_line ();
12076 /* Handle the .gpword pseudo-op. This is used when generating PIC
12077 code. It generates a 32 bit GP relative reloc. */
12080 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12086 /* When not generating PIC code, this is treated as .word. */
12087 if (mips_pic
!= SVR4_PIC
)
12093 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12094 mips_emit_delays (TRUE
);
12096 mips_align (2, 0, label
);
12097 mips_clear_insn_labels ();
12101 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12103 as_bad (_("Unsupported use of .gpword"));
12104 ignore_rest_of_line ();
12108 md_number_to_chars (p
, 0, 4);
12109 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12110 BFD_RELOC_GPREL32
);
12112 demand_empty_rest_of_line ();
12116 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12122 /* When not generating PIC code, this is treated as .dword. */
12123 if (mips_pic
!= SVR4_PIC
)
12129 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12130 mips_emit_delays (TRUE
);
12132 mips_align (3, 0, label
);
12133 mips_clear_insn_labels ();
12137 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12139 as_bad (_("Unsupported use of .gpdword"));
12140 ignore_rest_of_line ();
12144 md_number_to_chars (p
, 0, 8);
12145 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12146 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12148 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12149 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12150 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12152 demand_empty_rest_of_line ();
12155 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12156 tables in SVR4 PIC code. */
12159 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12163 /* This is ignored when not generating SVR4 PIC code. */
12164 if (mips_pic
!= SVR4_PIC
)
12170 /* Add $gp to the register named as an argument. */
12172 reg
= tc_get_register (0);
12173 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12176 demand_empty_rest_of_line ();
12179 /* Handle the .insn pseudo-op. This marks instruction labels in
12180 mips16 mode. This permits the linker to handle them specially,
12181 such as generating jalx instructions when needed. We also make
12182 them odd for the duration of the assembly, in order to generate the
12183 right sort of code. We will make them even in the adjust_symtab
12184 routine, while leaving them marked. This is convenient for the
12185 debugger and the disassembler. The linker knows to make them odd
12189 s_insn (int ignore ATTRIBUTE_UNUSED
)
12191 mips16_mark_labels ();
12193 demand_empty_rest_of_line ();
12196 /* Handle a .stabn directive. We need these in order to mark a label
12197 as being a mips16 text label correctly. Sometimes the compiler
12198 will emit a label, followed by a .stabn, and then switch sections.
12199 If the label and .stabn are in mips16 mode, then the label is
12200 really a mips16 text label. */
12203 s_mips_stab (int type
)
12206 mips16_mark_labels ();
12211 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12215 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12222 name
= input_line_pointer
;
12223 c
= get_symbol_end ();
12224 symbolP
= symbol_find_or_make (name
);
12225 S_SET_WEAK (symbolP
);
12226 *input_line_pointer
= c
;
12228 SKIP_WHITESPACE ();
12230 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12232 if (S_IS_DEFINED (symbolP
))
12234 as_bad ("ignoring attempt to redefine symbol %s",
12235 S_GET_NAME (symbolP
));
12236 ignore_rest_of_line ();
12240 if (*input_line_pointer
== ',')
12242 ++input_line_pointer
;
12243 SKIP_WHITESPACE ();
12247 if (exp
.X_op
!= O_symbol
)
12249 as_bad ("bad .weakext directive");
12250 ignore_rest_of_line ();
12253 symbol_set_value_expression (symbolP
, &exp
);
12256 demand_empty_rest_of_line ();
12259 /* Parse a register string into a number. Called from the ECOFF code
12260 to parse .frame. The argument is non-zero if this is the frame
12261 register, so that we can record it in mips_frame_reg. */
12264 tc_get_register (int frame
)
12268 SKIP_WHITESPACE ();
12269 if (*input_line_pointer
++ != '$')
12271 as_warn (_("expected `$'"));
12274 else if (ISDIGIT (*input_line_pointer
))
12276 reg
= get_absolute_expression ();
12277 if (reg
< 0 || reg
>= 32)
12279 as_warn (_("Bad register number"));
12285 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12288 input_line_pointer
+= 2;
12290 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12293 input_line_pointer
+= 2;
12295 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12298 input_line_pointer
+= 2;
12300 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12303 input_line_pointer
+= 2;
12305 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12308 input_line_pointer
+= 2;
12310 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12313 input_line_pointer
+= 3;
12315 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12318 input_line_pointer
+= 3;
12320 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12323 input_line_pointer
+= 4;
12327 as_warn (_("Unrecognized register name"));
12329 while (ISALNUM(*input_line_pointer
))
12330 input_line_pointer
++;
12335 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12336 mips_frame_reg_valid
= 1;
12337 mips_cprestore_valid
= 0;
12343 md_section_align (asection
*seg
, valueT addr
)
12345 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12348 /* We don't need to align ELF sections to the full alignment.
12349 However, Irix 5 may prefer that we align them at least to a 16
12350 byte boundary. We don't bother to align the sections if we are
12351 targeted for an embedded system. */
12352 if (strcmp (TARGET_OS
, "elf") == 0)
12358 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12361 /* Utility routine, called from above as well. If called while the
12362 input file is still being read, it's only an approximation. (For
12363 example, a symbol may later become defined which appeared to be
12364 undefined earlier.) */
12367 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12372 if (g_switch_value
> 0)
12374 const char *symname
;
12377 /* Find out whether this symbol can be referenced off the $gp
12378 register. It can be if it is smaller than the -G size or if
12379 it is in the .sdata or .sbss section. Certain symbols can
12380 not be referenced off the $gp, although it appears as though
12382 symname
= S_GET_NAME (sym
);
12383 if (symname
!= (const char *) NULL
12384 && (strcmp (symname
, "eprol") == 0
12385 || strcmp (symname
, "etext") == 0
12386 || strcmp (symname
, "_gp") == 0
12387 || strcmp (symname
, "edata") == 0
12388 || strcmp (symname
, "_fbss") == 0
12389 || strcmp (symname
, "_fdata") == 0
12390 || strcmp (symname
, "_ftext") == 0
12391 || strcmp (symname
, "end") == 0
12392 || strcmp (symname
, "_gp_disp") == 0))
12394 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12396 #ifndef NO_ECOFF_DEBUGGING
12397 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12398 && (symbol_get_obj (sym
)->ecoff_extern_size
12399 <= g_switch_value
))
12401 /* We must defer this decision until after the whole
12402 file has been read, since there might be a .extern
12403 after the first use of this symbol. */
12404 || (before_relaxing
12405 #ifndef NO_ECOFF_DEBUGGING
12406 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12408 && S_GET_VALUE (sym
) == 0)
12409 || (S_GET_VALUE (sym
) != 0
12410 && S_GET_VALUE (sym
) <= g_switch_value
)))
12414 const char *segname
;
12416 segname
= segment_name (S_GET_SEGMENT (sym
));
12417 assert (strcmp (segname
, ".lit8") != 0
12418 && strcmp (segname
, ".lit4") != 0);
12419 change
= (strcmp (segname
, ".sdata") != 0
12420 && strcmp (segname
, ".sbss") != 0
12421 && strncmp (segname
, ".sdata.", 7) != 0
12422 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12427 /* We are not optimizing for the $gp register. */
12432 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12435 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12438 bfd_boolean linkonce
;
12440 /* Handle the case of a symbol equated to another symbol. */
12441 while (symbol_equated_reloc_p (sym
))
12445 /* It's possible to get a loop here in a badly written
12447 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12453 symsec
= S_GET_SEGMENT (sym
);
12455 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12457 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12459 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12463 /* The GNU toolchain uses an extension for ELF: a section
12464 beginning with the magic string .gnu.linkonce is a linkonce
12466 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12467 sizeof ".gnu.linkonce" - 1) == 0)
12471 /* This must duplicate the test in adjust_reloc_syms. */
12472 return (symsec
!= &bfd_und_section
12473 && symsec
!= &bfd_abs_section
12474 && ! bfd_is_com_section (symsec
)
12477 /* A global or weak symbol is treated as external. */
12478 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12479 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12485 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12486 extended opcode. SEC is the section the frag is in. */
12489 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12492 register const struct mips16_immed_operand
*op
;
12494 int mintiny
, maxtiny
;
12498 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12500 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12503 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12504 op
= mips16_immed_operands
;
12505 while (op
->type
!= type
)
12508 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12513 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12516 maxtiny
= 1 << op
->nbits
;
12521 maxtiny
= (1 << op
->nbits
) - 1;
12526 mintiny
= - (1 << (op
->nbits
- 1));
12527 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12530 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12531 val
= S_GET_VALUE (fragp
->fr_symbol
);
12532 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12538 /* We won't have the section when we are called from
12539 mips_relax_frag. However, we will always have been called
12540 from md_estimate_size_before_relax first. If this is a
12541 branch to a different section, we mark it as such. If SEC is
12542 NULL, and the frag is not marked, then it must be a branch to
12543 the same section. */
12546 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12551 /* Must have been called from md_estimate_size_before_relax. */
12554 fragp
->fr_subtype
=
12555 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12557 /* FIXME: We should support this, and let the linker
12558 catch branches and loads that are out of range. */
12559 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12560 _("unsupported PC relative reference to different section"));
12564 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12565 /* Assume non-extended on the first relaxation pass.
12566 The address we have calculated will be bogus if this is
12567 a forward branch to another frag, as the forward frag
12568 will have fr_address == 0. */
12572 /* In this case, we know for sure that the symbol fragment is in
12573 the same section. If the relax_marker of the symbol fragment
12574 differs from the relax_marker of this fragment, we have not
12575 yet adjusted the symbol fragment fr_address. We want to add
12576 in STRETCH in order to get a better estimate of the address.
12577 This particularly matters because of the shift bits. */
12579 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12583 /* Adjust stretch for any alignment frag. Note that if have
12584 been expanding the earlier code, the symbol may be
12585 defined in what appears to be an earlier frag. FIXME:
12586 This doesn't handle the fr_subtype field, which specifies
12587 a maximum number of bytes to skip when doing an
12589 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12591 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12594 stretch
= - ((- stretch
)
12595 & ~ ((1 << (int) f
->fr_offset
) - 1));
12597 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12606 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12608 /* The base address rules are complicated. The base address of
12609 a branch is the following instruction. The base address of a
12610 PC relative load or add is the instruction itself, but if it
12611 is in a delay slot (in which case it can not be extended) use
12612 the address of the instruction whose delay slot it is in. */
12613 if (type
== 'p' || type
== 'q')
12617 /* If we are currently assuming that this frag should be
12618 extended, then, the current address is two bytes
12620 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12623 /* Ignore the low bit in the target, since it will be set
12624 for a text label. */
12625 if ((val
& 1) != 0)
12628 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12630 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12633 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12635 /* Branch offsets have an implicit 0 in the lowest bit. */
12636 if (type
== 'p' || type
== 'q')
12639 /* If any of the shifted bits are set, we must use an extended
12640 opcode. If the address depends on the size of this
12641 instruction, this can lead to a loop, so we arrange to always
12642 use an extended opcode. We only check this when we are in
12643 the main relaxation loop, when SEC is NULL. */
12644 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12646 fragp
->fr_subtype
=
12647 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12651 /* If we are about to mark a frag as extended because the value
12652 is precisely maxtiny + 1, then there is a chance of an
12653 infinite loop as in the following code:
12658 In this case when the la is extended, foo is 0x3fc bytes
12659 away, so the la can be shrunk, but then foo is 0x400 away, so
12660 the la must be extended. To avoid this loop, we mark the
12661 frag as extended if it was small, and is about to become
12662 extended with a value of maxtiny + 1. */
12663 if (val
== ((maxtiny
+ 1) << op
->shift
)
12664 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12667 fragp
->fr_subtype
=
12668 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12672 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12673 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12675 if ((val
& ((1 << op
->shift
) - 1)) != 0
12676 || val
< (mintiny
<< op
->shift
)
12677 || val
> (maxtiny
<< op
->shift
))
12683 /* Compute the length of a branch sequence, and adjust the
12684 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12685 worst-case length is computed, with UPDATE being used to indicate
12686 whether an unconditional (-1), branch-likely (+1) or regular (0)
12687 branch is to be computed. */
12689 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12691 bfd_boolean toofar
;
12695 && S_IS_DEFINED (fragp
->fr_symbol
)
12696 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12701 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12703 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12707 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12710 /* If the symbol is not defined or it's in a different segment,
12711 assume the user knows what's going on and emit a short
12717 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12719 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12720 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12721 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12727 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12730 if (mips_pic
!= NO_PIC
)
12732 /* Additional space for PIC loading of target address. */
12734 if (mips_opts
.isa
== ISA_MIPS1
)
12735 /* Additional space for $at-stabilizing nop. */
12739 /* If branch is conditional. */
12740 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12747 /* Estimate the size of a frag before relaxing. Unless this is the
12748 mips16, we are not really relaxing here, and the final size is
12749 encoded in the subtype information. For the mips16, we have to
12750 decide whether we are using an extended opcode or not. */
12753 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12757 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12760 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12762 return fragp
->fr_var
;
12765 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12766 /* We don't want to modify the EXTENDED bit here; it might get us
12767 into infinite loops. We change it only in mips_relax_frag(). */
12768 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12770 if (mips_pic
== NO_PIC
)
12771 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12772 else if (mips_pic
== SVR4_PIC
)
12773 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12779 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12780 return -RELAX_FIRST (fragp
->fr_subtype
);
12783 return -RELAX_SECOND (fragp
->fr_subtype
);
12786 /* This is called to see whether a reloc against a defined symbol
12787 should be converted into a reloc against a section. */
12790 mips_fix_adjustable (fixS
*fixp
)
12792 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12793 about the format of the offset in the .o file. */
12794 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12797 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12798 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12801 if (fixp
->fx_addsy
== NULL
)
12804 /* If symbol SYM is in a mergeable section, relocations of the form
12805 SYM + 0 can usually be made section-relative. The mergeable data
12806 is then identified by the section offset rather than by the symbol.
12808 However, if we're generating REL LO16 relocations, the offset is split
12809 between the LO16 and parterning high part relocation. The linker will
12810 need to recalculate the complete offset in order to correctly identify
12813 The linker has traditionally not looked for the parterning high part
12814 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12815 placed anywhere. Rather than break backwards compatibility by changing
12816 this, it seems better not to force the issue, and instead keep the
12817 original symbol. This will work with either linker behavior. */
12818 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12819 && HAVE_IN_PLACE_ADDENDS
12820 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12824 /* Don't adjust relocations against mips16 symbols, so that the linker
12825 can find them if it needs to set up a stub. */
12826 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12827 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12828 && fixp
->fx_subsy
== NULL
)
12835 /* Translate internal representation of relocation info to BFD target
12839 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12841 static arelent
*retval
[4];
12843 bfd_reloc_code_real_type code
;
12845 memset (retval
, 0, sizeof(retval
));
12846 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12847 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12848 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12849 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12851 assert (! fixp
->fx_pcrel
);
12852 reloc
->addend
= fixp
->fx_addnumber
;
12854 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12855 entry to be used in the relocation's section offset. */
12856 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12858 reloc
->address
= reloc
->addend
;
12862 code
= fixp
->fx_r_type
;
12864 /* To support a PC relative reloc, we used a Cygnus extension.
12865 We check for that here to make sure that we don't let such a
12866 reloc escape normally. (FIXME: This was formerly used by
12867 embedded-PIC support, but is now used by branch handling in
12868 general. That probably should be fixed.) */
12869 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12870 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12871 && code
== BFD_RELOC_16_PCREL_S2
)
12872 reloc
->howto
= NULL
;
12874 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12876 if (reloc
->howto
== NULL
)
12878 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12879 _("Can not represent %s relocation in this object file format"),
12880 bfd_get_reloc_code_name (code
));
12887 /* Relax a machine dependent frag. This returns the amount by which
12888 the current size of the frag should change. */
12891 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12893 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12895 offsetT old_var
= fragp
->fr_var
;
12897 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12899 return fragp
->fr_var
- old_var
;
12902 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12905 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12907 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12909 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12914 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12916 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12923 /* Convert a machine dependent frag. */
12926 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12928 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12931 unsigned long insn
;
12935 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12937 if (target_big_endian
)
12938 insn
= bfd_getb32 (buf
);
12940 insn
= bfd_getl32 (buf
);
12942 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12944 /* We generate a fixup instead of applying it right now
12945 because, if there are linker relaxations, we're going to
12946 need the relocations. */
12947 exp
.X_op
= O_symbol
;
12948 exp
.X_add_symbol
= fragp
->fr_symbol
;
12949 exp
.X_add_number
= fragp
->fr_offset
;
12951 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12953 BFD_RELOC_16_PCREL_S2
);
12954 fixp
->fx_file
= fragp
->fr_file
;
12955 fixp
->fx_line
= fragp
->fr_line
;
12957 md_number_to_chars (buf
, insn
, 4);
12964 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12965 _("relaxed out-of-range branch into a jump"));
12967 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12970 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12972 /* Reverse the branch. */
12973 switch ((insn
>> 28) & 0xf)
12976 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12977 have the condition reversed by tweaking a single
12978 bit, and their opcodes all have 0x4???????. */
12979 assert ((insn
& 0xf1000000) == 0x41000000);
12980 insn
^= 0x00010000;
12984 /* bltz 0x04000000 bgez 0x04010000
12985 bltzal 0x04100000 bgezal 0x04110000 */
12986 assert ((insn
& 0xfc0e0000) == 0x04000000);
12987 insn
^= 0x00010000;
12991 /* beq 0x10000000 bne 0x14000000
12992 blez 0x18000000 bgtz 0x1c000000 */
12993 insn
^= 0x04000000;
13001 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13003 /* Clear the and-link bit. */
13004 assert ((insn
& 0xfc1c0000) == 0x04100000);
13006 /* bltzal 0x04100000 bgezal 0x04110000
13007 bltzall 0x04120000 bgezall 0x04130000 */
13008 insn
&= ~0x00100000;
13011 /* Branch over the branch (if the branch was likely) or the
13012 full jump (not likely case). Compute the offset from the
13013 current instruction to branch to. */
13014 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13018 /* How many bytes in instructions we've already emitted? */
13019 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13020 /* How many bytes in instructions from here to the end? */
13021 i
= fragp
->fr_var
- i
;
13023 /* Convert to instruction count. */
13025 /* Branch counts from the next instruction. */
13028 /* Branch over the jump. */
13029 md_number_to_chars (buf
, insn
, 4);
13033 md_number_to_chars (buf
, 0, 4);
13036 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13038 /* beql $0, $0, 2f */
13040 /* Compute the PC offset from the current instruction to
13041 the end of the variable frag. */
13042 /* How many bytes in instructions we've already emitted? */
13043 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13044 /* How many bytes in instructions from here to the end? */
13045 i
= fragp
->fr_var
- i
;
13046 /* Convert to instruction count. */
13048 /* Don't decrement i, because we want to branch over the
13052 md_number_to_chars (buf
, insn
, 4);
13055 md_number_to_chars (buf
, 0, 4);
13060 if (mips_pic
== NO_PIC
)
13063 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13064 ? 0x0c000000 : 0x08000000);
13065 exp
.X_op
= O_symbol
;
13066 exp
.X_add_symbol
= fragp
->fr_symbol
;
13067 exp
.X_add_number
= fragp
->fr_offset
;
13069 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13070 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13071 fixp
->fx_file
= fragp
->fr_file
;
13072 fixp
->fx_line
= fragp
->fr_line
;
13074 md_number_to_chars (buf
, insn
, 4);
13079 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13080 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13081 exp
.X_op
= O_symbol
;
13082 exp
.X_add_symbol
= fragp
->fr_symbol
;
13083 exp
.X_add_number
= fragp
->fr_offset
;
13085 if (fragp
->fr_offset
)
13087 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13088 exp
.X_add_number
= 0;
13091 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13092 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13093 fixp
->fx_file
= fragp
->fr_file
;
13094 fixp
->fx_line
= fragp
->fr_line
;
13096 md_number_to_chars (buf
, insn
, 4);
13099 if (mips_opts
.isa
== ISA_MIPS1
)
13102 md_number_to_chars (buf
, 0, 4);
13106 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13107 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13109 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13110 4, &exp
, 0, BFD_RELOC_LO16
);
13111 fixp
->fx_file
= fragp
->fr_file
;
13112 fixp
->fx_line
= fragp
->fr_line
;
13114 md_number_to_chars (buf
, insn
, 4);
13118 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13123 md_number_to_chars (buf
, insn
, 4);
13128 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13129 + fragp
->fr_fix
+ fragp
->fr_var
);
13131 fragp
->fr_fix
+= fragp
->fr_var
;
13136 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13139 register const struct mips16_immed_operand
*op
;
13140 bfd_boolean small
, ext
;
13143 unsigned long insn
;
13144 bfd_boolean use_extend
;
13145 unsigned short extend
;
13147 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13148 op
= mips16_immed_operands
;
13149 while (op
->type
!= type
)
13152 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13163 resolve_symbol_value (fragp
->fr_symbol
);
13164 val
= S_GET_VALUE (fragp
->fr_symbol
);
13169 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13171 /* The rules for the base address of a PC relative reloc are
13172 complicated; see mips16_extended_frag. */
13173 if (type
== 'p' || type
== 'q')
13178 /* Ignore the low bit in the target, since it will be
13179 set for a text label. */
13180 if ((val
& 1) != 0)
13183 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13185 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13188 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13191 /* Make sure the section winds up with the alignment we have
13194 record_alignment (asec
, op
->shift
);
13198 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13199 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13200 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13201 _("extended instruction in delay slot"));
13203 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13205 if (target_big_endian
)
13206 insn
= bfd_getb16 (buf
);
13208 insn
= bfd_getl16 (buf
);
13210 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13211 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13212 small
, ext
, &insn
, &use_extend
, &extend
);
13216 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13217 fragp
->fr_fix
+= 2;
13221 md_number_to_chars (buf
, insn
, 2);
13222 fragp
->fr_fix
+= 2;
13230 first
= RELAX_FIRST (fragp
->fr_subtype
);
13231 second
= RELAX_SECOND (fragp
->fr_subtype
);
13232 fixp
= (fixS
*) fragp
->fr_opcode
;
13234 /* Possibly emit a warning if we've chosen the longer option. */
13235 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13236 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13238 const char *msg
= macro_warning (fragp
->fr_subtype
);
13240 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13243 /* Go through all the fixups for the first sequence. Disable them
13244 (by marking them as done) if we're going to use the second
13245 sequence instead. */
13247 && fixp
->fx_frag
== fragp
13248 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13250 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13252 fixp
= fixp
->fx_next
;
13255 /* Go through the fixups for the second sequence. Disable them if
13256 we're going to use the first sequence, otherwise adjust their
13257 addresses to account for the relaxation. */
13258 while (fixp
&& fixp
->fx_frag
== fragp
)
13260 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13261 fixp
->fx_where
-= first
;
13264 fixp
= fixp
->fx_next
;
13267 /* Now modify the frag contents. */
13268 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13272 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13273 memmove (start
, start
+ first
, second
);
13274 fragp
->fr_fix
-= first
;
13277 fragp
->fr_fix
-= second
;
13283 /* This function is called after the relocs have been generated.
13284 We've been storing mips16 text labels as odd. Here we convert them
13285 back to even for the convenience of the debugger. */
13288 mips_frob_file_after_relocs (void)
13291 unsigned int count
, i
;
13293 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13296 syms
= bfd_get_outsymbols (stdoutput
);
13297 count
= bfd_get_symcount (stdoutput
);
13298 for (i
= 0; i
< count
; i
++, syms
++)
13300 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13301 && ((*syms
)->value
& 1) != 0)
13303 (*syms
)->value
&= ~1;
13304 /* If the symbol has an odd size, it was probably computed
13305 incorrectly, so adjust that as well. */
13306 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13307 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13314 /* This function is called whenever a label is defined. It is used
13315 when handling branch delays; if a branch has a label, we assume we
13316 can not move it. */
13319 mips_define_label (symbolS
*sym
)
13321 struct insn_label_list
*l
;
13323 if (free_insn_labels
== NULL
)
13324 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13327 l
= free_insn_labels
;
13328 free_insn_labels
= l
->next
;
13332 l
->next
= insn_labels
;
13336 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13338 /* Some special processing for a MIPS ELF file. */
13341 mips_elf_final_processing (void)
13343 /* Write out the register information. */
13344 if (mips_abi
!= N64_ABI
)
13348 s
.ri_gprmask
= mips_gprmask
;
13349 s
.ri_cprmask
[0] = mips_cprmask
[0];
13350 s
.ri_cprmask
[1] = mips_cprmask
[1];
13351 s
.ri_cprmask
[2] = mips_cprmask
[2];
13352 s
.ri_cprmask
[3] = mips_cprmask
[3];
13353 /* The gp_value field is set by the MIPS ELF backend. */
13355 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13356 ((Elf32_External_RegInfo
*)
13357 mips_regmask_frag
));
13361 Elf64_Internal_RegInfo s
;
13363 s
.ri_gprmask
= mips_gprmask
;
13365 s
.ri_cprmask
[0] = mips_cprmask
[0];
13366 s
.ri_cprmask
[1] = mips_cprmask
[1];
13367 s
.ri_cprmask
[2] = mips_cprmask
[2];
13368 s
.ri_cprmask
[3] = mips_cprmask
[3];
13369 /* The gp_value field is set by the MIPS ELF backend. */
13371 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13372 ((Elf64_External_RegInfo
*)
13373 mips_regmask_frag
));
13376 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13377 sort of BFD interface for this. */
13378 if (mips_any_noreorder
)
13379 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13380 if (mips_pic
!= NO_PIC
)
13382 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13383 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13386 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13388 /* Set MIPS ELF flags for ASEs. */
13389 if (file_ase_mips16
)
13390 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13391 #if 0 /* XXX FIXME */
13392 if (file_ase_mips3d
)
13393 elf_elfheader (stdoutput
)->e_flags
|= ???;
13396 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13398 /* Set the MIPS ELF ABI flags. */
13399 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13400 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13401 else if (mips_abi
== O64_ABI
)
13402 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13403 else if (mips_abi
== EABI_ABI
)
13405 if (!file_mips_gp32
)
13406 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13408 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13410 else if (mips_abi
== N32_ABI
)
13411 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13413 /* Nothing to do for N64_ABI. */
13415 if (mips_32bitmode
)
13416 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13419 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13421 typedef struct proc
{
13423 unsigned long reg_mask
;
13424 unsigned long reg_offset
;
13425 unsigned long fpreg_mask
;
13426 unsigned long fpreg_offset
;
13427 unsigned long frame_offset
;
13428 unsigned long frame_reg
;
13429 unsigned long pc_reg
;
13432 static procS cur_proc
;
13433 static procS
*cur_proc_ptr
;
13434 static int numprocs
;
13436 /* Fill in an rs_align_code fragment. */
13439 mips_handle_align (fragS
*fragp
)
13441 if (fragp
->fr_type
!= rs_align_code
)
13444 if (mips_opts
.mips16
)
13446 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13447 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13452 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13453 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13461 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13465 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13469 md_obj_begin (void)
13476 /* check for premature end, nesting errors, etc */
13478 as_warn (_("missing .end at end of assembly"));
13487 if (*input_line_pointer
== '-')
13489 ++input_line_pointer
;
13492 if (!ISDIGIT (*input_line_pointer
))
13493 as_bad (_("expected simple number"));
13494 if (input_line_pointer
[0] == '0')
13496 if (input_line_pointer
[1] == 'x')
13498 input_line_pointer
+= 2;
13499 while (ISXDIGIT (*input_line_pointer
))
13502 val
|= hex_value (*input_line_pointer
++);
13504 return negative
? -val
: val
;
13508 ++input_line_pointer
;
13509 while (ISDIGIT (*input_line_pointer
))
13512 val
|= *input_line_pointer
++ - '0';
13514 return negative
? -val
: val
;
13517 if (!ISDIGIT (*input_line_pointer
))
13519 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13520 *input_line_pointer
, *input_line_pointer
);
13521 as_warn (_("invalid number"));
13524 while (ISDIGIT (*input_line_pointer
))
13527 val
+= *input_line_pointer
++ - '0';
13529 return negative
? -val
: val
;
13532 /* The .file directive; just like the usual .file directive, but there
13533 is an initial number which is the ECOFF file index. In the non-ECOFF
13534 case .file implies DWARF-2. */
13537 s_mips_file (int x ATTRIBUTE_UNUSED
)
13539 static int first_file_directive
= 0;
13541 if (ECOFF_DEBUGGING
)
13550 filename
= dwarf2_directive_file (0);
13552 /* Versions of GCC up to 3.1 start files with a ".file"
13553 directive even for stabs output. Make sure that this
13554 ".file" is handled. Note that you need a version of GCC
13555 after 3.1 in order to support DWARF-2 on MIPS. */
13556 if (filename
!= NULL
&& ! first_file_directive
)
13558 (void) new_logical_line (filename
, -1);
13559 s_app_file_string (filename
, 0);
13561 first_file_directive
= 1;
13565 /* The .loc directive, implying DWARF-2. */
13568 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13570 if (!ECOFF_DEBUGGING
)
13571 dwarf2_directive_loc (0);
13574 /* The .end directive. */
13577 s_mips_end (int x ATTRIBUTE_UNUSED
)
13581 /* Following functions need their own .frame and .cprestore directives. */
13582 mips_frame_reg_valid
= 0;
13583 mips_cprestore_valid
= 0;
13585 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13588 demand_empty_rest_of_line ();
13593 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13594 as_warn (_(".end not in text section"));
13598 as_warn (_(".end directive without a preceding .ent directive."));
13599 demand_empty_rest_of_line ();
13605 assert (S_GET_NAME (p
));
13606 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13607 as_warn (_(".end symbol does not match .ent symbol."));
13609 if (debug_type
== DEBUG_STABS
)
13610 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13614 as_warn (_(".end directive missing or unknown symbol"));
13617 /* Generate a .pdr section. */
13618 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13621 segT saved_seg
= now_seg
;
13622 subsegT saved_subseg
= now_subseg
;
13627 dot
= frag_now_fix ();
13629 #ifdef md_flush_pending_output
13630 md_flush_pending_output ();
13634 subseg_set (pdr_seg
, 0);
13636 /* Write the symbol. */
13637 exp
.X_op
= O_symbol
;
13638 exp
.X_add_symbol
= p
;
13639 exp
.X_add_number
= 0;
13640 emit_expr (&exp
, 4);
13642 fragp
= frag_more (7 * 4);
13644 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13645 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13646 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13647 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13648 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13649 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13650 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13652 subseg_set (saved_seg
, saved_subseg
);
13654 #endif /* OBJ_ELF */
13656 cur_proc_ptr
= NULL
;
13659 /* The .aent and .ent directives. */
13662 s_mips_ent (int aent
)
13666 symbolP
= get_symbol ();
13667 if (*input_line_pointer
== ',')
13668 ++input_line_pointer
;
13669 SKIP_WHITESPACE ();
13670 if (ISDIGIT (*input_line_pointer
)
13671 || *input_line_pointer
== '-')
13674 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13675 as_warn (_(".ent or .aent not in text section."));
13677 if (!aent
&& cur_proc_ptr
)
13678 as_warn (_("missing .end"));
13682 /* This function needs its own .frame and .cprestore directives. */
13683 mips_frame_reg_valid
= 0;
13684 mips_cprestore_valid
= 0;
13686 cur_proc_ptr
= &cur_proc
;
13687 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13689 cur_proc_ptr
->isym
= symbolP
;
13691 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13695 if (debug_type
== DEBUG_STABS
)
13696 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13697 S_GET_NAME (symbolP
));
13700 demand_empty_rest_of_line ();
13703 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13704 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13705 s_mips_frame is used so that we can set the PDR information correctly.
13706 We can't use the ecoff routines because they make reference to the ecoff
13707 symbol table (in the mdebug section). */
13710 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13713 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13717 if (cur_proc_ptr
== (procS
*) NULL
)
13719 as_warn (_(".frame outside of .ent"));
13720 demand_empty_rest_of_line ();
13724 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13726 SKIP_WHITESPACE ();
13727 if (*input_line_pointer
++ != ','
13728 || get_absolute_expression_and_terminator (&val
) != ',')
13730 as_warn (_("Bad .frame directive"));
13731 --input_line_pointer
;
13732 demand_empty_rest_of_line ();
13736 cur_proc_ptr
->frame_offset
= val
;
13737 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13739 demand_empty_rest_of_line ();
13742 #endif /* OBJ_ELF */
13746 /* The .fmask and .mask directives. If the mdebug section is present
13747 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13748 embedded targets, s_mips_mask is used so that we can set the PDR
13749 information correctly. We can't use the ecoff routines because they
13750 make reference to the ecoff symbol table (in the mdebug section). */
13753 s_mips_mask (int reg_type
)
13756 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13760 if (cur_proc_ptr
== (procS
*) NULL
)
13762 as_warn (_(".mask/.fmask outside of .ent"));
13763 demand_empty_rest_of_line ();
13767 if (get_absolute_expression_and_terminator (&mask
) != ',')
13769 as_warn (_("Bad .mask/.fmask directive"));
13770 --input_line_pointer
;
13771 demand_empty_rest_of_line ();
13775 off
= get_absolute_expression ();
13777 if (reg_type
== 'F')
13779 cur_proc_ptr
->fpreg_mask
= mask
;
13780 cur_proc_ptr
->fpreg_offset
= off
;
13784 cur_proc_ptr
->reg_mask
= mask
;
13785 cur_proc_ptr
->reg_offset
= off
;
13788 demand_empty_rest_of_line ();
13791 #endif /* OBJ_ELF */
13792 s_ignore (reg_type
);
13795 /* A table describing all the processors gas knows about. Names are
13796 matched in the order listed.
13798 To ease comparison, please keep this table in the same order as
13799 gcc's mips_cpu_info_table[]. */
13800 static const struct mips_cpu_info mips_cpu_info_table
[] =
13802 /* Entries for generic ISAs */
13803 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13804 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13805 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13806 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13807 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13808 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13809 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13810 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13811 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13814 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13815 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13816 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13819 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13822 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13823 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13824 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13825 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13826 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13827 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13828 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13829 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13830 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13831 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13832 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13833 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13836 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13837 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13838 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13839 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13840 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13841 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13842 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13843 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13844 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13845 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13846 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13847 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13848 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13851 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13852 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13853 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13856 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13857 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13859 /* Broadcom SB-1 CPU core */
13860 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13867 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13868 with a final "000" replaced by "k". Ignore case.
13870 Note: this function is shared between GCC and GAS. */
13873 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13875 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13876 given
++, canonical
++;
13878 return ((*given
== 0 && *canonical
== 0)
13879 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13883 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13884 CPU name. We've traditionally allowed a lot of variation here.
13886 Note: this function is shared between GCC and GAS. */
13889 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13891 /* First see if the name matches exactly, or with a final "000"
13892 turned into "k". */
13893 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13896 /* If not, try comparing based on numerical designation alone.
13897 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13898 if (TOLOWER (*given
) == 'r')
13900 if (!ISDIGIT (*given
))
13903 /* Skip over some well-known prefixes in the canonical name,
13904 hoping to find a number there too. */
13905 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13907 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13909 else if (TOLOWER (canonical
[0]) == 'r')
13912 return mips_strict_matching_cpu_name_p (canonical
, given
);
13916 /* Parse an option that takes the name of a processor as its argument.
13917 OPTION is the name of the option and CPU_STRING is the argument.
13918 Return the corresponding processor enumeration if the CPU_STRING is
13919 recognized, otherwise report an error and return null.
13921 A similar function exists in GCC. */
13923 static const struct mips_cpu_info
*
13924 mips_parse_cpu (const char *option
, const char *cpu_string
)
13926 const struct mips_cpu_info
*p
;
13928 /* 'from-abi' selects the most compatible architecture for the given
13929 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13930 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13931 version. Look first at the -mgp options, if given, otherwise base
13932 the choice on MIPS_DEFAULT_64BIT.
13934 Treat NO_ABI like the EABIs. One reason to do this is that the
13935 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13936 architecture. This code picks MIPS I for 'mips' and MIPS III for
13937 'mips64', just as we did in the days before 'from-abi'. */
13938 if (strcasecmp (cpu_string
, "from-abi") == 0)
13940 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13941 return mips_cpu_info_from_isa (ISA_MIPS1
);
13943 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13944 return mips_cpu_info_from_isa (ISA_MIPS3
);
13946 if (file_mips_gp32
>= 0)
13947 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13949 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13954 /* 'default' has traditionally been a no-op. Probably not very useful. */
13955 if (strcasecmp (cpu_string
, "default") == 0)
13958 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
13959 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
13962 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
13966 /* Return the canonical processor information for ISA (a member of the
13967 ISA_MIPS* enumeration). */
13969 static const struct mips_cpu_info
*
13970 mips_cpu_info_from_isa (int isa
)
13974 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13975 if (mips_cpu_info_table
[i
].is_isa
13976 && isa
== mips_cpu_info_table
[i
].isa
)
13977 return (&mips_cpu_info_table
[i
]);
13982 static const struct mips_cpu_info
*
13983 mips_cpu_info_from_arch (int arch
)
13987 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13988 if (arch
== mips_cpu_info_table
[i
].cpu
)
13989 return (&mips_cpu_info_table
[i
]);
13995 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
13999 fprintf (stream
, "%24s", "");
14004 fprintf (stream
, ", ");
14008 if (*col_p
+ strlen (string
) > 72)
14010 fprintf (stream
, "\n%24s", "");
14014 fprintf (stream
, "%s", string
);
14015 *col_p
+= strlen (string
);
14021 md_show_usage (FILE *stream
)
14026 fprintf (stream
, _("\
14028 -EB generate big endian output\n\
14029 -EL generate little endian output\n\
14030 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14031 -G NUM allow referencing objects up to NUM bytes\n\
14032 implicitly with the gp register [default 8]\n"));
14033 fprintf (stream
, _("\
14034 -mips1 generate MIPS ISA I instructions\n\
14035 -mips2 generate MIPS ISA II instructions\n\
14036 -mips3 generate MIPS ISA III instructions\n\
14037 -mips4 generate MIPS ISA IV instructions\n\
14038 -mips5 generate MIPS ISA V instructions\n\
14039 -mips32 generate MIPS32 ISA instructions\n\
14040 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14041 -mips64 generate MIPS64 ISA instructions\n\
14042 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14043 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14047 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14048 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14049 show (stream
, "from-abi", &column
, &first
);
14050 fputc ('\n', stream
);
14052 fprintf (stream
, _("\
14053 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14054 -no-mCPU don't generate code specific to CPU.\n\
14055 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14059 show (stream
, "3900", &column
, &first
);
14060 show (stream
, "4010", &column
, &first
);
14061 show (stream
, "4100", &column
, &first
);
14062 show (stream
, "4650", &column
, &first
);
14063 fputc ('\n', stream
);
14065 fprintf (stream
, _("\
14066 -mips16 generate mips16 instructions\n\
14067 -no-mips16 do not generate mips16 instructions\n"));
14068 fprintf (stream
, _("\
14069 -mfix-vr4120 work around certain VR4120 errata\n\
14070 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14071 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14072 -O0 remove unneeded NOPs, do not swap branches\n\
14073 -O remove unneeded NOPs and swap branches\n\
14074 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14075 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14076 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14078 fprintf (stream
, _("\
14079 -KPIC, -call_shared generate SVR4 position independent code\n\
14080 -non_shared do not generate position independent code\n\
14081 -xgot assume a 32 bit GOT\n\
14082 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14083 -mabi=ABI create ABI conformant object file for:\n"));
14087 show (stream
, "32", &column
, &first
);
14088 show (stream
, "o64", &column
, &first
);
14089 show (stream
, "n32", &column
, &first
);
14090 show (stream
, "64", &column
, &first
);
14091 show (stream
, "eabi", &column
, &first
);
14093 fputc ('\n', stream
);
14095 fprintf (stream
, _("\
14096 -32 create o32 ABI object file (default)\n\
14097 -n32 create n32 ABI object file\n\
14098 -64 create 64 ABI object file\n"));
14103 mips_dwarf2_format (void)
14105 if (mips_abi
== N64_ABI
)
14108 return dwarf2_format_64bit_irix
;
14110 return dwarf2_format_64bit
;
14114 return dwarf2_format_32bit
;
14118 mips_dwarf2_addr_size (void)
14120 if (mips_abi
== N64_ABI
)