1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 #include "opcode/mips.h"
43 #define DBG(x) printf x
49 /* Clean up namespace so we can include obj-elf.h too. */
50 static int mips_output_flavor
PARAMS ((void));
51 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
52 #undef OBJ_PROCESS_STAB
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
115 mips_target_format ()
117 switch (OUTPUT_FLAVOR
)
119 case bfd_target_aout_flavour
:
120 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
121 case bfd_target_ecoff_flavour
:
122 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
123 case bfd_target_coff_flavour
:
125 case bfd_target_elf_flavour
:
127 /* This is traditional mips */
128 return (target_big_endian
129 ? "elf32-tradbigmips" : "elf32-tradlittlemips");
131 return (target_big_endian
132 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
133 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
141 /* The name of the readonly data section. */
142 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
144 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
146 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
148 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
152 /* This is the set of options which may be modified by the .set
153 pseudo-op. We use a struct so that .set push and .set pop are more
156 struct mips_set_options
{
157 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
158 if it has not been initialized. Changed by `.set mipsN', and the
159 -mipsN command line option, and the default CPU. */
161 /* Whether we are assembling for the mips16 processor. 0 if we are
162 not, 1 if we are, and -1 if the value has not been initialized.
163 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
164 -nomips16 command line options, and the default CPU. */
166 /* Non-zero if we should not reorder instructions. Changed by `.set
167 reorder' and `.set noreorder'. */
169 /* Non-zero if we should not permit the $at ($1) register to be used
170 in instructions. Changed by `.set at' and `.set noat'. */
172 /* Non-zero if we should warn when a macro instruction expands into
173 more than one machine instruction. Changed by `.set nomacro' and
175 int warn_about_macros
;
176 /* Non-zero if we should not move instructions. Changed by `.set
177 move', `.set volatile', `.set nomove', and `.set novolatile'. */
179 /* Non-zero if we should not optimize branches by moving the target
180 of the branch into the delay slot. Actually, we don't perform
181 this optimization anyhow. Changed by `.set bopt' and `.set
184 /* Non-zero if we should not autoextend mips16 instructions.
185 Changed by `.set autoextend' and `.set noautoextend'. */
189 /* This is the struct we use to hold the current set of options. Note
190 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
191 -1 to indicate that they have not been initialized. */
193 static struct mips_set_options mips_opts
= {
194 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0
197 /* These variables are filled in with the masks of registers used.
198 The object format code reads them and puts them in the appropriate
200 unsigned long mips_gprmask
;
201 unsigned long mips_cprmask
[4];
203 /* MIPS ISA we are using for this output file. */
204 static int file_mips_isa
= ISA_UNKNOWN
;
206 /* The CPU type we are using for this output file. */
207 static int mips_cpu
= CPU_UNKNOWN
;
209 /* The argument of the -mabi= flag. */
210 static char *mips_abi_string
= 0;
212 /* Wether we should mark the file EABI64 or EABI32. */
213 static int mips_eabi64
= 0;
215 /* If they asked for mips1 or mips2 and a cpu that is
216 mips3 or greater, then mark the object file 32BITMODE. */
217 static int mips_32bitmode
= 0;
219 /* True if -mgp32 was passed. */
220 static int mips_gp32
= 0;
222 /* Some ISA's have delay slots for instructions which read or write
223 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
224 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
225 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
226 delay slot in this ISA. The uses of this macro assume that any
227 ISA that has delay slots for one of these, has them for all. They
228 also assume that ISAs which don't have delays for these insns, don't
229 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
230 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
232 || (ISA) == ISA_MIPS2 \
233 || (ISA) == ISA_MIPS3 \
236 /* Return true if ISA supports 64 bit gp register instructions. */
237 #define ISA_HAS_64BIT_REGS(ISA) ( \
239 || (ISA) == ISA_MIPS4 \
240 || (ISA) == ISA_MIPS5 \
241 || (ISA) == ISA_MIPS32 \
244 /* Whether the processor uses hardware interlocks to protect
245 reads from the HI and LO registers, and thus does not
246 require nops to be inserted.
248 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
249 -mcpu=FOO schedules for FOO, but still produces code that meets the
250 requirements of MIPS ISA I. For example, it won't generate any
251 FOO-specific instructions, and it will still assume that any
252 scheduling hazards described in MIPS ISA I are there, even if FOO
253 has interlocks. -mFOO gives GCC permission to generate code that
254 will only run on a FOO; it will generate FOO-specific instructions,
255 and assume interlocks provided by a FOO.
257 However, GAS currently doesn't make this distinction; before Jan 28
258 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
259 assumptions. The GCC driver passes these flags through to GAS, so
260 if GAS actually does anything that doesn't meet MIPS ISA I with
261 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
263 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
264 which seems senseless --- why generate code which will only run on
265 a FOO, but schedule for something else?
267 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
269 -- Jim Blandy <jimb@cygnus.com> */
271 #define hilo_interlocks (mips_cpu == CPU_R4010 \
274 /* Whether the processor uses hardware interlocks to protect reads
275 from the GPRs, and thus does not require nops to be inserted. */
276 #define gpr_interlocks \
277 (mips_opts.isa != ISA_MIPS1 \
278 || mips_cpu == CPU_R3900)
280 /* As with other "interlocks" this is used by hardware that has FP
281 (co-processor) interlocks. */
282 /* Itbl support may require additional care here. */
283 #define cop_interlocks (mips_cpu == CPU_R4300 \
286 /* Is this a mfhi or mflo instruction? */
287 #define MF_HILO_INSN(PINFO) \
288 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
290 /* MIPS PIC level. */
292 enum mips_pic_level
{
293 /* Do not generate PIC code. */
296 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
297 not sure what it is supposed to do. */
300 /* Generate PIC code as in the SVR4 MIPS ABI. */
303 /* Generate PIC code without using a global offset table: the data
304 segment has a maximum size of 64K, all data references are off
305 the $gp register, and all text references are PC relative. This
306 is used on some embedded systems. */
310 static enum mips_pic_level mips_pic
;
312 /* 1 if we should generate 32 bit offsets from the GP register in
313 SVR4_PIC mode. Currently has no meaning in other modes. */
314 static int mips_big_got
;
316 /* 1 if trap instructions should used for overflow rather than break
318 static int mips_trap
;
320 /* 1 if double width floating point constants should not be constructed
321 by a assembling two single width halves into two single width floating
322 point registers which just happen to alias the double width destination
323 register. On some architectures this aliasing can be disabled by a bit
324 in the status register, and the setting of this bit cannot be determined
325 automatically at assemble time. */
326 static int mips_disable_float_construction
;
328 /* Non-zero if any .set noreorder directives were used. */
330 static int mips_any_noreorder
;
332 /* Non-zero if nops should be inserted when the register referenced in
333 an mfhi/mflo instruction is read in the next two instructions. */
334 static int mips_7000_hilo_fix
;
336 /* The size of the small data section. */
337 static unsigned int g_switch_value
= 8;
338 /* Whether the -G option was used. */
339 static int g_switch_seen
= 0;
344 /* If we can determine in advance that GP optimization won't be
345 possible, we can skip the relaxation stuff that tries to produce
346 GP-relative references. This makes delay slot optimization work
349 This function can only provide a guess, but it seems to work for
350 gcc output. It needs to guess right for gcc, otherwise gcc
351 will put what it thinks is a GP-relative instruction in a branch
354 I don't know if a fix is needed for the SVR4_PIC mode. I've only
355 fixed it for the non-PIC mode. KR 95/04/07 */
356 static int nopic_need_relax
PARAMS ((symbolS
*, int));
358 /* handle of the OPCODE hash table */
359 static struct hash_control
*op_hash
= NULL
;
361 /* The opcode hash table we use for the mips16. */
362 static struct hash_control
*mips16_op_hash
= NULL
;
364 /* This array holds the chars that always start a comment. If the
365 pre-processor is disabled, these aren't very useful */
366 const char comment_chars
[] = "#";
368 /* This array holds the chars that only start a comment at the beginning of
369 a line. If the line seems to have the form '# 123 filename'
370 .line and .file directives will appear in the pre-processed output */
371 /* Note that input_file.c hand checks for '#' at the beginning of the
372 first line of the input file. This is because the compiler outputs
373 #NO_APP at the beginning of its output. */
374 /* Also note that C style comments are always supported. */
375 const char line_comment_chars
[] = "#";
377 /* This array holds machine specific line separator characters. */
378 const char line_separator_chars
[] = ";";
380 /* Chars that can be used to separate mant from exp in floating point nums */
381 const char EXP_CHARS
[] = "eE";
383 /* Chars that mean this number is a floating point constant */
386 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
388 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
389 changed in read.c . Ideally it shouldn't have to know about it at all,
390 but nothing is ideal around here.
393 static char *insn_error
;
395 static int auto_align
= 1;
397 /* When outputting SVR4 PIC code, the assembler needs to know the
398 offset in the stack frame from which to restore the $gp register.
399 This is set by the .cprestore pseudo-op, and saved in this
401 static offsetT mips_cprestore_offset
= -1;
403 /* This is the register which holds the stack frame, as set by the
404 .frame pseudo-op. This is needed to implement .cprestore. */
405 static int mips_frame_reg
= SP
;
407 /* To output NOP instructions correctly, we need to keep information
408 about the previous two instructions. */
410 /* Whether we are optimizing. The default value of 2 means to remove
411 unneeded NOPs and swap branch instructions when possible. A value
412 of 1 means to not swap branches. A value of 0 means to always
414 static int mips_optimize
= 2;
416 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
417 equivalent to seeing no -g option at all. */
418 static int mips_debug
= 0;
420 /* The previous instruction. */
421 static struct mips_cl_insn prev_insn
;
423 /* The instruction before prev_insn. */
424 static struct mips_cl_insn prev_prev_insn
;
426 /* If we don't want information for prev_insn or prev_prev_insn, we
427 point the insn_mo field at this dummy integer. */
428 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
430 /* Non-zero if prev_insn is valid. */
431 static int prev_insn_valid
;
433 /* The frag for the previous instruction. */
434 static struct frag
*prev_insn_frag
;
436 /* The offset into prev_insn_frag for the previous instruction. */
437 static long prev_insn_where
;
439 /* The reloc type for the previous instruction, if any. */
440 static bfd_reloc_code_real_type prev_insn_reloc_type
;
442 /* The reloc for the previous instruction, if any. */
443 static fixS
*prev_insn_fixp
;
445 /* Non-zero if the previous instruction was in a delay slot. */
446 static int prev_insn_is_delay_slot
;
448 /* Non-zero if the previous instruction was in a .set noreorder. */
449 static int prev_insn_unreordered
;
451 /* Non-zero if the previous instruction uses an extend opcode (if
453 static int prev_insn_extended
;
455 /* Non-zero if the previous previous instruction was in a .set
457 static int prev_prev_insn_unreordered
;
459 /* If this is set, it points to a frag holding nop instructions which
460 were inserted before the start of a noreorder section. If those
461 nops turn out to be unnecessary, the size of the frag can be
463 static fragS
*prev_nop_frag
;
465 /* The number of nop instructions we created in prev_nop_frag. */
466 static int prev_nop_frag_holds
;
468 /* The number of nop instructions that we know we need in
470 static int prev_nop_frag_required
;
472 /* The number of instructions we've seen since prev_nop_frag. */
473 static int prev_nop_frag_since
;
475 /* For ECOFF and ELF, relocations against symbols are done in two
476 parts, with a HI relocation and a LO relocation. Each relocation
477 has only 16 bits of space to store an addend. This means that in
478 order for the linker to handle carries correctly, it must be able
479 to locate both the HI and the LO relocation. This means that the
480 relocations must appear in order in the relocation table.
482 In order to implement this, we keep track of each unmatched HI
483 relocation. We then sort them so that they immediately precede the
484 corresponding LO relocation. */
486 struct mips_hi_fixup
{
488 struct mips_hi_fixup
*next
;
491 /* The section this fixup is in. */
495 /* The list of unmatched HI relocs. */
497 static struct mips_hi_fixup
*mips_hi_fixup_list
;
499 /* Map normal MIPS register numbers to mips16 register numbers. */
501 #define X ILLEGAL_REG
502 static const int mips32_to_16_reg_map
[] = {
503 X
, X
, 2, 3, 4, 5, 6, 7,
504 X
, X
, X
, X
, X
, X
, X
, X
,
505 0, 1, X
, X
, X
, X
, X
, X
,
506 X
, X
, X
, X
, X
, X
, X
, X
510 /* Map mips16 register numbers to normal MIPS register numbers. */
512 static const unsigned int mips16_to_32_reg_map
[] = {
513 16, 17, 2, 3, 4, 5, 6, 7
516 /* Since the MIPS does not have multiple forms of PC relative
517 instructions, we do not have to do relaxing as is done on other
518 platforms. However, we do have to handle GP relative addressing
519 correctly, which turns out to be a similar problem.
521 Every macro that refers to a symbol can occur in (at least) two
522 forms, one with GP relative addressing and one without. For
523 example, loading a global variable into a register generally uses
524 a macro instruction like this:
526 If i can be addressed off the GP register (this is true if it is in
527 the .sbss or .sdata section, or if it is known to be smaller than
528 the -G argument) this will generate the following instruction:
530 This instruction will use a GPREL reloc. If i can not be addressed
531 off the GP register, the following instruction sequence will be used:
534 In this case the first instruction will have a HI16 reloc, and the
535 second reloc will have a LO16 reloc. Both relocs will be against
538 The issue here is that we may not know whether i is GP addressable
539 until after we see the instruction that uses it. Therefore, we
540 want to be able to choose the final instruction sequence only at
541 the end of the assembly. This is similar to the way other
542 platforms choose the size of a PC relative instruction only at the
545 When generating position independent code we do not use GP
546 addressing in quite the same way, but the issue still arises as
547 external symbols and local symbols must be handled differently.
549 We handle these issues by actually generating both possible
550 instruction sequences. The longer one is put in a frag_var with
551 type rs_machine_dependent. We encode what to do with the frag in
552 the subtype field. We encode (1) the number of existing bytes to
553 replace, (2) the number of new bytes to use, (3) the offset from
554 the start of the existing bytes to the first reloc we must generate
555 (that is, the offset is applied from the start of the existing
556 bytes after they are replaced by the new bytes, if any), (4) the
557 offset from the start of the existing bytes to the second reloc,
558 (5) whether a third reloc is needed (the third reloc is always four
559 bytes after the second reloc), and (6) whether to warn if this
560 variant is used (this is sometimes needed if .set nomacro or .set
561 noat is in effect). All these numbers are reasonably small.
563 Generating two instruction sequences must be handled carefully to
564 ensure that delay slots are handled correctly. Fortunately, there
565 are a limited number of cases. When the second instruction
566 sequence is generated, append_insn is directed to maintain the
567 existing delay slot information, so it continues to apply to any
568 code after the second instruction sequence. This means that the
569 second instruction sequence must not impose any requirements not
570 required by the first instruction sequence.
572 These variant frags are then handled in functions called by the
573 machine independent code. md_estimate_size_before_relax returns
574 the final size of the frag. md_convert_frag sets up the final form
575 of the frag. tc_gen_reloc adjust the first reloc and adds a second
577 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
581 | (((reloc1) + 64) << 9) \
582 | (((reloc2) + 64) << 2) \
583 | ((reloc3) ? (1 << 1) : 0) \
585 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
586 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
587 #define RELAX_RELOC1(i) ((bfd_vma) (((i) >> 9) & 0x7f) - 64)
588 #define RELAX_RELOC2(i) ((bfd_vma) (((i) >> 2) & 0x7f) - 64)
589 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
590 #define RELAX_WARN(i) ((i) & 1)
592 /* For mips16 code, we use an entirely different form of relaxation.
593 mips16 supports two versions of most instructions which take
594 immediate values: a small one which takes some small value, and a
595 larger one which takes a 16 bit value. Since branches also follow
596 this pattern, relaxing these values is required.
598 We can assemble both mips16 and normal MIPS code in a single
599 object. Therefore, we need to support this type of relaxation at
600 the same time that we support the relaxation described above. We
601 use the high bit of the subtype field to distinguish these cases.
603 The information we store for this type of relaxation is the
604 argument code found in the opcode file for this relocation, whether
605 the user explicitly requested a small or extended form, and whether
606 the relocation is in a jump or jal delay slot. That tells us the
607 size of the value, and how it should be stored. We also store
608 whether the fragment is considered to be extended or not. We also
609 store whether this is known to be a branch to a different section,
610 whether we have tried to relax this frag yet, and whether we have
611 ever extended a PC relative fragment because of a shift count. */
612 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
615 | ((small) ? 0x100 : 0) \
616 | ((ext) ? 0x200 : 0) \
617 | ((dslot) ? 0x400 : 0) \
618 | ((jal_dslot) ? 0x800 : 0))
619 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
620 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
621 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
622 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
623 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
624 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
625 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
626 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
627 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
628 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
629 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
630 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
632 /* Prototypes for static functions. */
635 #define internalError() \
636 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
638 #define internalError() as_fatal (_("MIPS internal Error"));
641 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
643 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
644 unsigned int reg
, enum mips_regclass
class));
645 static int reg_needs_delay
PARAMS ((unsigned int));
646 static void mips16_mark_labels
PARAMS ((void));
647 static void append_insn
PARAMS ((char *place
,
648 struct mips_cl_insn
* ip
,
650 bfd_reloc_code_real_type r
,
652 static void mips_no_prev_insn
PARAMS ((int));
653 static void mips_emit_delays
PARAMS ((boolean
));
655 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
656 const char *name
, const char *fmt
,
659 static void macro_build ();
661 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
662 const char *, const char *,
664 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
665 expressionS
* ep
, int regnum
));
666 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
667 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
669 static void load_register
PARAMS ((int *, int, expressionS
*, int));
670 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
671 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
672 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
673 #ifdef LOSING_COMPILER
674 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
676 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
677 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
678 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
679 boolean
, boolean
, unsigned long *,
680 boolean
*, unsigned short *));
681 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
682 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
683 static symbolS
*get_symbol
PARAMS ((void));
684 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
685 static void s_align
PARAMS ((int));
686 static void s_change_sec
PARAMS ((int));
687 static void s_cons
PARAMS ((int));
688 static void s_float_cons
PARAMS ((int));
689 static void s_mips_globl
PARAMS ((int));
690 static void s_option
PARAMS ((int));
691 static void s_mipsset
PARAMS ((int));
692 static void s_abicalls
PARAMS ((int));
693 static void s_cpload
PARAMS ((int));
694 static void s_cprestore
PARAMS ((int));
695 static void s_gpword
PARAMS ((int));
696 static void s_cpadd
PARAMS ((int));
697 static void s_insn
PARAMS ((int));
698 static void md_obj_begin
PARAMS ((void));
699 static void md_obj_end
PARAMS ((void));
700 static long get_number
PARAMS ((void));
701 static void s_mips_ent
PARAMS ((int));
702 static void s_mips_end
PARAMS ((int));
703 static void s_mips_frame
PARAMS ((int));
704 static void s_mips_mask
PARAMS ((int));
705 static void s_mips_stab
PARAMS ((int));
706 static void s_mips_weakext
PARAMS ((int));
707 static void s_file
PARAMS ((int));
708 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
709 static const char *mips_isa_to_str
PARAMS ((int));
710 static const char *mips_cpu_to_str
PARAMS ((int));
711 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
713 /* Table and functions used to map between CPU/ISA names, and
714 ISA levels, and CPU numbers. */
716 struct mips_cpu_info
{
717 const char *name
; /* CPU or ISA name. */
718 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
719 int isa
; /* ISA level. */
720 int cpu
; /* CPU number (default CPU if ISA). */
723 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
724 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
725 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
729 The following pseudo-ops from the Kane and Heinrich MIPS book
730 should be defined here, but are currently unsupported: .alias,
731 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
733 The following pseudo-ops from the Kane and Heinrich MIPS book are
734 specific to the type of debugging information being generated, and
735 should be defined by the object format: .aent, .begin, .bend,
736 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
739 The following pseudo-ops from the Kane and Heinrich MIPS book are
740 not MIPS CPU specific, but are also not specific to the object file
741 format. This file is probably the best place to define them, but
742 they are not currently supported: .asm0, .endr, .lab, .repeat,
745 static const pseudo_typeS mips_pseudo_table
[] = {
746 /* MIPS specific pseudo-ops. */
747 {"option", s_option
, 0},
748 {"set", s_mipsset
, 0},
749 {"rdata", s_change_sec
, 'r'},
750 {"sdata", s_change_sec
, 's'},
751 {"livereg", s_ignore
, 0},
752 {"abicalls", s_abicalls
, 0},
753 {"cpload", s_cpload
, 0},
754 {"cprestore", s_cprestore
, 0},
755 {"gpword", s_gpword
, 0},
756 {"cpadd", s_cpadd
, 0},
759 /* Relatively generic pseudo-ops that happen to be used on MIPS
761 {"asciiz", stringer
, 1},
762 {"bss", s_change_sec
, 'b'},
765 {"dword", s_cons
, 3},
766 {"weakext", s_mips_weakext
, 0},
768 /* These pseudo-ops are defined in read.c, but must be overridden
769 here for one reason or another. */
770 {"align", s_align
, 0},
772 {"data", s_change_sec
, 'd'},
773 {"double", s_float_cons
, 'd'},
774 {"float", s_float_cons
, 'f'},
775 {"globl", s_mips_globl
, 0},
776 {"global", s_mips_globl
, 0},
777 {"hword", s_cons
, 1},
782 {"short", s_cons
, 1},
783 {"single", s_float_cons
, 'f'},
784 {"stabn", s_mips_stab
, 'n'},
785 {"text", s_change_sec
, 't'},
790 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
791 /* These pseudo-ops should be defined by the object file format.
792 However, a.out doesn't support them, so we have versions here. */
793 {"aent", s_mips_ent
, 1},
794 {"bgnb", s_ignore
, 0},
795 {"end", s_mips_end
, 0},
796 {"endb", s_ignore
, 0},
797 {"ent", s_mips_ent
, 0},
799 {"fmask", s_mips_mask
, 'F'},
800 {"frame", s_mips_frame
, 0},
801 {"loc", s_ignore
, 0},
802 {"mask", s_mips_mask
, 'R'},
803 {"verstamp", s_ignore
, 0},
807 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
812 pop_insert (mips_pseudo_table
);
813 if (! ECOFF_DEBUGGING
)
814 pop_insert (mips_nonecoff_pseudo_table
);
817 /* Symbols labelling the current insn. */
819 struct insn_label_list
{
820 struct insn_label_list
*next
;
824 static struct insn_label_list
*insn_labels
;
825 static struct insn_label_list
*free_insn_labels
;
827 static void mips_clear_insn_labels
PARAMS ((void));
830 mips_clear_insn_labels ()
832 register struct insn_label_list
**pl
;
834 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
840 static char *expr_end
;
842 /* Expressions which appear in instructions. These are set by
845 static expressionS imm_expr
;
846 static expressionS offset_expr
;
848 /* Relocs associated with imm_expr and offset_expr. */
850 static bfd_reloc_code_real_type imm_reloc
;
851 static bfd_reloc_code_real_type offset_reloc
;
853 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
855 static boolean imm_unmatched_hi
;
857 /* These are set by mips16_ip if an explicit extension is used. */
859 static boolean mips16_small
, mips16_ext
;
861 #ifdef MIPS_STABS_ELF
862 /* The pdr segment for per procedure frame/regmask info */
868 mips_isa_to_str (isa
)
871 const struct mips_cpu_info
*ci
;
874 ci
= mips_cpu_info_from_isa (isa
);
878 sprintf (s
, "ISA#%d", isa
);
883 mips_cpu_to_str (cpu
)
886 const struct mips_cpu_info
*ci
;
889 ci
= mips_cpu_info_from_cpu (cpu
);
893 sprintf (s
, "CPU#%d", cpu
);
897 /* This function is called once, at assembler startup time. It should
898 set up all the tables, etc. that the MD part of the assembler will need. */
903 register const char *retval
= NULL
;
908 int mips_isa_from_cpu
;
909 int target_cpu_had_mips16
= 0;
910 const struct mips_cpu_info
*ci
;
912 /* GP relative stuff not working for PE */
913 if (strncmp (TARGET_OS
, "pe", 2) == 0
914 && g_switch_value
!= 0)
917 as_bad (_("-G not supported in this configuration."));
922 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
924 a
= xmalloc (sizeof TARGET_CPU
);
925 strcpy (a
, TARGET_CPU
);
926 a
[(sizeof TARGET_CPU
) - 3] = '\0';
930 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
932 target_cpu_had_mips16
= 1;
933 cpu
+= sizeof "mips16" - 1;
936 if (mips_opts
.mips16
< 0)
937 mips_opts
.mips16
= target_cpu_had_mips16
;
939 /* At this point, mips_cpu will either be CPU_UNKNOWN if no CPU was
940 specified on the command line, or some other value if one was.
941 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
942 the command line, or will be set otherwise if one was. */
943 if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
945 /* We have it all. There's nothing to do. */
947 else if (mips_cpu
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
949 /* We have CPU, we need ISA. */
950 ci
= mips_cpu_info_from_cpu (mips_cpu
);
952 mips_opts
.isa
= ci
->isa
;
954 else if (mips_cpu
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
956 /* We have ISA, we need default CPU. */
957 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
963 /* We need to set both ISA and CPU from target cpu. */
964 ci
= mips_cpu_info_from_name (cpu
);
966 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
968 mips_opts
.isa
= ci
->isa
;
972 ci
= mips_cpu_info_from_cpu (mips_cpu
);
974 mips_isa_from_cpu
= ci
->isa
;
976 /* End of TARGET_CPU processing, get rid of malloced memory
985 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
986 as_bad (_("trap exception not supported at ISA 1"));
988 /* Set the EABI kind based on the ISA before the user gets
989 to change the ISA with directives. This isn't really
990 the best, but then neither is basing the abi on the isa. */
991 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
993 && 0 == strcmp (mips_abi_string
, "eabi"))
996 /* If they asked for mips1 or mips2 and a cpu that is
997 mips3 or greater, then mark the object file 32BITMODE. */
998 if (mips_isa_from_cpu
!= ISA_UNKNOWN
999 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1000 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1003 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
))
1004 as_warn (_("Could not set architecture and machine"));
1006 file_mips_isa
= mips_opts
.isa
;
1008 op_hash
= hash_new ();
1010 for (i
= 0; i
< NUMOPCODES
;)
1012 const char *name
= mips_opcodes
[i
].name
;
1014 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1017 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1018 mips_opcodes
[i
].name
, retval
);
1019 /* Probably a memory allocation problem? Give up now. */
1020 as_fatal (_("Broken assembler. No assembly attempted."));
1024 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1026 if (!validate_mips_insn (&mips_opcodes
[i
]))
1031 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1034 mips16_op_hash
= hash_new ();
1037 while (i
< bfd_mips16_num_opcodes
)
1039 const char *name
= mips16_opcodes
[i
].name
;
1041 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1043 as_fatal (_("internal: can't hash `%s': %s"),
1044 mips16_opcodes
[i
].name
, retval
);
1047 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1048 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1049 != mips16_opcodes
[i
].match
))
1051 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1052 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1057 while (i
< bfd_mips16_num_opcodes
1058 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1062 as_fatal (_("Broken assembler. No assembly attempted."));
1064 /* We add all the general register names to the symbol table. This
1065 helps us detect invalid uses of them. */
1066 for (i
= 0; i
< 32; i
++)
1070 sprintf (buf
, "$%d", i
);
1071 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1072 &zero_address_frag
));
1074 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1075 &zero_address_frag
));
1076 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1077 &zero_address_frag
));
1078 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1079 &zero_address_frag
));
1080 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1081 &zero_address_frag
));
1082 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1083 &zero_address_frag
));
1084 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1085 &zero_address_frag
));
1086 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1087 &zero_address_frag
));
1089 mips_no_prev_insn (false);
1092 mips_cprmask
[0] = 0;
1093 mips_cprmask
[1] = 0;
1094 mips_cprmask
[2] = 0;
1095 mips_cprmask
[3] = 0;
1097 /* set the default alignment for the text section (2**2) */
1098 record_alignment (text_section
, 2);
1100 if (USE_GLOBAL_POINTER_OPT
)
1101 bfd_set_gp_size (stdoutput
, g_switch_value
);
1103 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1105 /* On a native system, sections must be aligned to 16 byte
1106 boundaries. When configured for an embedded ELF target, we
1108 if (strcmp (TARGET_OS
, "elf") != 0)
1110 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1111 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1112 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1115 /* Create a .reginfo section for register masks and a .mdebug
1116 section for debugging information. */
1124 subseg
= now_subseg
;
1126 /* The ABI says this section should be loaded so that the
1127 running program can access it. However, we don't load it
1128 if we are configured for an embedded target */
1129 flags
= SEC_READONLY
| SEC_DATA
;
1130 if (strcmp (TARGET_OS
, "elf") != 0)
1131 flags
|= SEC_ALLOC
| SEC_LOAD
;
1135 sec
= subseg_new (".reginfo", (subsegT
) 0);
1137 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1138 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1141 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1146 /* The 64-bit ABI uses a .MIPS.options section rather than
1147 .reginfo section. */
1148 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1149 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1150 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1153 /* Set up the option header. */
1155 Elf_Internal_Options opthdr
;
1158 opthdr
.kind
= ODK_REGINFO
;
1159 opthdr
.size
= (sizeof (Elf_External_Options
)
1160 + sizeof (Elf64_External_RegInfo
));
1163 f
= frag_more (sizeof (Elf_External_Options
));
1164 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1165 (Elf_External_Options
*) f
);
1167 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1172 if (ECOFF_DEBUGGING
)
1174 sec
= subseg_new (".mdebug", (subsegT
) 0);
1175 (void) bfd_set_section_flags (stdoutput
, sec
,
1176 SEC_HAS_CONTENTS
| SEC_READONLY
);
1177 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1180 #ifdef MIPS_STABS_ELF
1181 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1182 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1183 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1184 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1187 subseg_set (seg
, subseg
);
1191 if (! ECOFF_DEBUGGING
)
1198 if (! ECOFF_DEBUGGING
)
1206 struct mips_cl_insn insn
;
1208 imm_expr
.X_op
= O_absent
;
1209 imm_reloc
= BFD_RELOC_UNUSED
;
1210 imm_unmatched_hi
= false;
1211 offset_expr
.X_op
= O_absent
;
1212 offset_reloc
= BFD_RELOC_UNUSED
;
1214 if (mips_opts
.mips16
)
1215 mips16_ip (str
, &insn
);
1218 mips_ip (str
, &insn
);
1219 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1220 str
, insn
.insn_opcode
));
1225 as_bad ("%s `%s'", insn_error
, str
);
1229 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1231 if (mips_opts
.mips16
)
1232 mips16_macro (&insn
);
1238 if (imm_expr
.X_op
!= O_absent
)
1239 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1241 else if (offset_expr
.X_op
!= O_absent
)
1242 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1244 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1248 /* See whether instruction IP reads register REG. CLASS is the type
1252 insn_uses_reg (ip
, reg
, class)
1253 struct mips_cl_insn
*ip
;
1255 enum mips_regclass
class;
1257 if (class == MIPS16_REG
)
1259 assert (mips_opts
.mips16
);
1260 reg
= mips16_to_32_reg_map
[reg
];
1261 class = MIPS_GR_REG
;
1264 /* Don't report on general register 0, since it never changes. */
1265 if (class == MIPS_GR_REG
&& reg
== 0)
1268 if (class == MIPS_FP_REG
)
1270 assert (! mips_opts
.mips16
);
1271 /* If we are called with either $f0 or $f1, we must check $f0.
1272 This is not optimal, because it will introduce an unnecessary
1273 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1274 need to distinguish reading both $f0 and $f1 or just one of
1275 them. Note that we don't have to check the other way,
1276 because there is no instruction that sets both $f0 and $f1
1277 and requires a delay. */
1278 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1279 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1280 == (reg
&~ (unsigned) 1)))
1282 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1283 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1284 == (reg
&~ (unsigned) 1)))
1287 else if (! mips_opts
.mips16
)
1289 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1290 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1292 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1293 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1298 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1299 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1300 & MIPS16OP_MASK_RX
)]
1303 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1304 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1305 & MIPS16OP_MASK_RY
)]
1308 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1309 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1310 & MIPS16OP_MASK_MOVE32Z
)]
1313 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1315 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1317 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1319 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1320 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1321 & MIPS16OP_MASK_REGR32
) == reg
)
1328 /* This function returns true if modifying a register requires a
1332 reg_needs_delay (reg
)
1335 unsigned long prev_pinfo
;
1337 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1338 if (! mips_opts
.noreorder
1339 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1340 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1341 || (! gpr_interlocks
1342 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1344 /* A load from a coprocessor or from memory. All load
1345 delays delay the use of general register rt for one
1346 instruction on the r3000. The r6000 and r4000 use
1348 /* Itbl support may require additional care here. */
1349 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1350 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1357 /* Mark instruction labels in mips16 mode. This permits the linker to
1358 handle them specially, such as generating jalx instructions when
1359 needed. We also make them odd for the duration of the assembly, in
1360 order to generate the right sort of code. We will make them even
1361 in the adjust_symtab routine, while leaving them marked. This is
1362 convenient for the debugger and the disassembler. The linker knows
1363 to make them odd again. */
1366 mips16_mark_labels ()
1368 if (mips_opts
.mips16
)
1370 struct insn_label_list
*l
;
1372 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1375 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1376 S_SET_OTHER (l
->label
, STO_MIPS16
);
1378 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1379 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1384 /* Output an instruction. PLACE is where to put the instruction; if
1385 it is NULL, this uses frag_more to get room. IP is the instruction
1386 information. ADDRESS_EXPR is an operand of the instruction to be
1387 used with RELOC_TYPE. */
1390 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1392 struct mips_cl_insn
*ip
;
1393 expressionS
*address_expr
;
1394 bfd_reloc_code_real_type reloc_type
;
1395 boolean unmatched_hi
;
1397 register unsigned long prev_pinfo
, pinfo
;
1402 /* Mark instruction labels in mips16 mode. */
1403 if (mips_opts
.mips16
)
1404 mips16_mark_labels ();
1406 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1407 pinfo
= ip
->insn_mo
->pinfo
;
1409 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1413 /* If the previous insn required any delay slots, see if we need
1414 to insert a NOP or two. There are eight kinds of possible
1415 hazards, of which an instruction can have at most one type.
1416 (1) a load from memory delay
1417 (2) a load from a coprocessor delay
1418 (3) an unconditional branch delay
1419 (4) a conditional branch delay
1420 (5) a move to coprocessor register delay
1421 (6) a load coprocessor register from memory delay
1422 (7) a coprocessor condition code delay
1423 (8) a HI/LO special register delay
1425 There are a lot of optimizations we could do that we don't.
1426 In particular, we do not, in general, reorder instructions.
1427 If you use gcc with optimization, it will reorder
1428 instructions and generally do much more optimization then we
1429 do here; repeating all that work in the assembler would only
1430 benefit hand written assembly code, and does not seem worth
1433 /* This is how a NOP is emitted. */
1434 #define emit_nop() \
1436 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1437 : md_number_to_chars (frag_more (4), 0, 4))
1439 /* The previous insn might require a delay slot, depending upon
1440 the contents of the current insn. */
1441 if (! mips_opts
.mips16
1442 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1443 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1444 && ! cop_interlocks
)
1445 || (! gpr_interlocks
1446 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1448 /* A load from a coprocessor or from memory. All load
1449 delays delay the use of general register rt for one
1450 instruction on the r3000. The r6000 and r4000 use
1452 /* Itbl support may require additional care here. */
1453 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1454 if (mips_optimize
== 0
1455 || insn_uses_reg (ip
,
1456 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1461 else if (! mips_opts
.mips16
1462 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1463 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1464 && ! cop_interlocks
)
1465 || (mips_opts
.isa
== ISA_MIPS1
1466 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1468 /* A generic coprocessor delay. The previous instruction
1469 modified a coprocessor general or control register. If
1470 it modified a control register, we need to avoid any
1471 coprocessor instruction (this is probably not always
1472 required, but it sometimes is). If it modified a general
1473 register, we avoid using that register.
1475 On the r6000 and r4000 loading a coprocessor register
1476 from memory is interlocked, and does not require a delay.
1478 This case is not handled very well. There is no special
1479 knowledge of CP0 handling, and the coprocessors other
1480 than the floating point unit are not distinguished at
1482 /* Itbl support may require additional care here. FIXME!
1483 Need to modify this to include knowledge about
1484 user specified delays! */
1485 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1487 if (mips_optimize
== 0
1488 || insn_uses_reg (ip
,
1489 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1494 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1496 if (mips_optimize
== 0
1497 || insn_uses_reg (ip
,
1498 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1505 /* We don't know exactly what the previous instruction
1506 does. If the current instruction uses a coprocessor
1507 register, we must insert a NOP. If previous
1508 instruction may set the condition codes, and the
1509 current instruction uses them, we must insert two
1511 /* Itbl support may require additional care here. */
1512 if (mips_optimize
== 0
1513 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1514 && (pinfo
& INSN_READ_COND_CODE
)))
1516 else if (pinfo
& INSN_COP
)
1520 else if (! mips_opts
.mips16
1521 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1522 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1523 && ! cop_interlocks
)
1525 /* The previous instruction sets the coprocessor condition
1526 codes, but does not require a general coprocessor delay
1527 (this means it is a floating point comparison
1528 instruction). If this instruction uses the condition
1529 codes, we need to insert a single NOP. */
1530 /* Itbl support may require additional care here. */
1531 if (mips_optimize
== 0
1532 || (pinfo
& INSN_READ_COND_CODE
))
1536 /* If we're fixing up mfhi/mflo for the r7000 and the
1537 previous insn was an mfhi/mflo and the current insn
1538 reads the register that the mfhi/mflo wrote to, then
1541 else if (mips_7000_hilo_fix
1542 && MF_HILO_INSN (prev_pinfo
)
1543 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1551 /* If we're fixing up mfhi/mflo for the r7000 and the
1552 2nd previous insn was an mfhi/mflo and the current insn
1553 reads the register that the mfhi/mflo wrote to, then
1556 else if (mips_7000_hilo_fix
1557 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1558 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1566 else if (prev_pinfo
& INSN_READ_LO
)
1568 /* The previous instruction reads the LO register; if the
1569 current instruction writes to the LO register, we must
1570 insert two NOPS. Some newer processors have interlocks.
1571 Also the tx39's multiply instructions can be exectuted
1572 immediatly after a read from HI/LO (without the delay),
1573 though the tx39's divide insns still do require the
1575 if (! (hilo_interlocks
1576 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1577 && (mips_optimize
== 0
1578 || (pinfo
& INSN_WRITE_LO
)))
1580 /* Most mips16 branch insns don't have a delay slot.
1581 If a read from LO is immediately followed by a branch
1582 to a write to LO we have a read followed by a write
1583 less than 2 insns away. We assume the target of
1584 a branch might be a write to LO, and insert a nop
1585 between a read and an immediately following branch. */
1586 else if (mips_opts
.mips16
1587 && (mips_optimize
== 0
1588 || (pinfo
& MIPS16_INSN_BRANCH
)))
1591 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1593 /* The previous instruction reads the HI register; if the
1594 current instruction writes to the HI register, we must
1595 insert a NOP. Some newer processors have interlocks.
1596 Also the note tx39's multiply above. */
1597 if (! (hilo_interlocks
1598 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1599 && (mips_optimize
== 0
1600 || (pinfo
& INSN_WRITE_HI
)))
1602 /* Most mips16 branch insns don't have a delay slot.
1603 If a read from HI is immediately followed by a branch
1604 to a write to HI we have a read followed by a write
1605 less than 2 insns away. We assume the target of
1606 a branch might be a write to HI, and insert a nop
1607 between a read and an immediately following branch. */
1608 else if (mips_opts
.mips16
1609 && (mips_optimize
== 0
1610 || (pinfo
& MIPS16_INSN_BRANCH
)))
1614 /* If the previous instruction was in a noreorder section, then
1615 we don't want to insert the nop after all. */
1616 /* Itbl support may require additional care here. */
1617 if (prev_insn_unreordered
)
1620 /* There are two cases which require two intervening
1621 instructions: 1) setting the condition codes using a move to
1622 coprocessor instruction which requires a general coprocessor
1623 delay and then reading the condition codes 2) reading the HI
1624 or LO register and then writing to it (except on processors
1625 which have interlocks). If we are not already emitting a NOP
1626 instruction, we must check for these cases compared to the
1627 instruction previous to the previous instruction. */
1628 if ((! mips_opts
.mips16
1629 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1630 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1631 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1632 && (pinfo
& INSN_READ_COND_CODE
)
1633 && ! cop_interlocks
)
1634 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1635 && (pinfo
& INSN_WRITE_LO
)
1636 && ! (hilo_interlocks
1637 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1638 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1639 && (pinfo
& INSN_WRITE_HI
)
1640 && ! (hilo_interlocks
1641 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1646 if (prev_prev_insn_unreordered
)
1649 if (prev_prev_nop
&& nops
== 0)
1652 /* If we are being given a nop instruction, don't bother with
1653 one of the nops we would otherwise output. This will only
1654 happen when a nop instruction is used with mips_optimize set
1657 && ! mips_opts
.noreorder
1658 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1661 /* Now emit the right number of NOP instructions. */
1662 if (nops
> 0 && ! mips_opts
.noreorder
)
1665 unsigned long old_frag_offset
;
1667 struct insn_label_list
*l
;
1669 old_frag
= frag_now
;
1670 old_frag_offset
= frag_now_fix ();
1672 for (i
= 0; i
< nops
; i
++)
1677 listing_prev_line ();
1678 /* We may be at the start of a variant frag. In case we
1679 are, make sure there is enough space for the frag
1680 after the frags created by listing_prev_line. The
1681 argument to frag_grow here must be at least as large
1682 as the argument to all other calls to frag_grow in
1683 this file. We don't have to worry about being in the
1684 middle of a variant frag, because the variants insert
1685 all needed nop instructions themselves. */
1689 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1691 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1692 symbol_set_frag (l
->label
, frag_now
);
1693 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1694 /* mips16 text labels are stored as odd. */
1695 if (mips_opts
.mips16
)
1696 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1699 #ifndef NO_ECOFF_DEBUGGING
1700 if (ECOFF_DEBUGGING
)
1701 ecoff_fix_loc (old_frag
, old_frag_offset
);
1704 else if (prev_nop_frag
!= NULL
)
1706 /* We have a frag holding nops we may be able to remove. If
1707 we don't need any nops, we can decrease the size of
1708 prev_nop_frag by the size of one instruction. If we do
1709 need some nops, we count them in prev_nops_required. */
1710 if (prev_nop_frag_since
== 0)
1714 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1715 --prev_nop_frag_holds
;
1718 prev_nop_frag_required
+= nops
;
1722 if (prev_prev_nop
== 0)
1724 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1725 --prev_nop_frag_holds
;
1728 ++prev_nop_frag_required
;
1731 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1732 prev_nop_frag
= NULL
;
1734 ++prev_nop_frag_since
;
1736 /* Sanity check: by the time we reach the second instruction
1737 after prev_nop_frag, we should have used up all the nops
1738 one way or another. */
1739 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1743 if (reloc_type
> BFD_RELOC_UNUSED
)
1745 /* We need to set up a variant frag. */
1746 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1747 f
= frag_var (rs_machine_dependent
, 4, 0,
1748 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1749 mips16_small
, mips16_ext
,
1751 & INSN_UNCOND_BRANCH_DELAY
),
1752 (prev_insn_reloc_type
1753 == BFD_RELOC_MIPS16_JMP
)),
1754 make_expr_symbol (address_expr
), (offsetT
) 0,
1757 else if (place
!= NULL
)
1759 else if (mips_opts
.mips16
1761 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1763 /* Make sure there is enough room to swap this instruction with
1764 a following jump instruction. */
1770 if (mips_opts
.mips16
1771 && mips_opts
.noreorder
1772 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1773 as_warn (_("extended instruction in delay slot"));
1779 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1781 if (address_expr
->X_op
== O_constant
)
1786 ip
->insn_opcode
|= address_expr
->X_add_number
;
1789 case BFD_RELOC_LO16
:
1790 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1793 case BFD_RELOC_MIPS_JMP
:
1794 if ((address_expr
->X_add_number
& 3) != 0)
1795 as_bad (_("jump to misaligned address (0x%lx)"),
1796 (unsigned long) address_expr
->X_add_number
);
1797 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1800 case BFD_RELOC_MIPS16_JMP
:
1801 if ((address_expr
->X_add_number
& 3) != 0)
1802 as_bad (_("jump to misaligned address (0x%lx)"),
1803 (unsigned long) address_expr
->X_add_number
);
1805 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1806 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1807 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1810 case BFD_RELOC_16_PCREL_S2
:
1820 /* Don't generate a reloc if we are writing into a variant
1824 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1826 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1830 struct mips_hi_fixup
*hi_fixup
;
1832 assert (reloc_type
== BFD_RELOC_HI16_S
);
1833 hi_fixup
= ((struct mips_hi_fixup
*)
1834 xmalloc (sizeof (struct mips_hi_fixup
)));
1835 hi_fixup
->fixp
= fixp
;
1836 hi_fixup
->seg
= now_seg
;
1837 hi_fixup
->next
= mips_hi_fixup_list
;
1838 mips_hi_fixup_list
= hi_fixup
;
1844 if (! mips_opts
.mips16
)
1845 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1846 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1848 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1849 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1855 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1858 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1861 /* Update the register mask information. */
1862 if (! mips_opts
.mips16
)
1864 if (pinfo
& INSN_WRITE_GPR_D
)
1865 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1866 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1867 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1868 if (pinfo
& INSN_READ_GPR_S
)
1869 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1870 if (pinfo
& INSN_WRITE_GPR_31
)
1871 mips_gprmask
|= 1 << 31;
1872 if (pinfo
& INSN_WRITE_FPR_D
)
1873 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1874 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1875 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1876 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1877 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1878 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1879 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1880 if (pinfo
& INSN_COP
)
1882 /* We don't keep enough information to sort these cases out.
1883 The itbl support does keep this information however, although
1884 we currently don't support itbl fprmats as part of the cop
1885 instruction. May want to add this support in the future. */
1887 /* Never set the bit for $0, which is always zero. */
1888 mips_gprmask
&= ~1 << 0;
1892 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1893 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1894 & MIPS16OP_MASK_RX
);
1895 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1896 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1897 & MIPS16OP_MASK_RY
);
1898 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1899 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1900 & MIPS16OP_MASK_RZ
);
1901 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1902 mips_gprmask
|= 1 << TREG
;
1903 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1904 mips_gprmask
|= 1 << SP
;
1905 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1906 mips_gprmask
|= 1 << RA
;
1907 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1908 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1909 if (pinfo
& MIPS16_INSN_READ_Z
)
1910 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1911 & MIPS16OP_MASK_MOVE32Z
);
1912 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1913 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1914 & MIPS16OP_MASK_REGR32
);
1917 if (place
== NULL
&& ! mips_opts
.noreorder
)
1919 /* Filling the branch delay slot is more complex. We try to
1920 switch the branch with the previous instruction, which we can
1921 do if the previous instruction does not set up a condition
1922 that the branch tests and if the branch is not itself the
1923 target of any branch. */
1924 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1925 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1927 if (mips_optimize
< 2
1928 /* If we have seen .set volatile or .set nomove, don't
1930 || mips_opts
.nomove
!= 0
1931 /* If we had to emit any NOP instructions, then we
1932 already know we can not swap. */
1934 /* If we don't even know the previous insn, we can not
1936 || ! prev_insn_valid
1937 /* If the previous insn is already in a branch delay
1938 slot, then we can not swap. */
1939 || prev_insn_is_delay_slot
1940 /* If the previous previous insn was in a .set
1941 noreorder, we can't swap. Actually, the MIPS
1942 assembler will swap in this situation. However, gcc
1943 configured -with-gnu-as will generate code like
1949 in which we can not swap the bne and INSN. If gcc is
1950 not configured -with-gnu-as, it does not output the
1951 .set pseudo-ops. We don't have to check
1952 prev_insn_unreordered, because prev_insn_valid will
1953 be 0 in that case. We don't want to use
1954 prev_prev_insn_valid, because we do want to be able
1955 to swap at the start of a function. */
1956 || prev_prev_insn_unreordered
1957 /* If the branch is itself the target of a branch, we
1958 can not swap. We cheat on this; all we check for is
1959 whether there is a label on this instruction. If
1960 there are any branches to anything other than a
1961 label, users must use .set noreorder. */
1962 || insn_labels
!= NULL
1963 /* If the previous instruction is in a variant frag, we
1964 can not do the swap. This does not apply to the
1965 mips16, which uses variant frags for different
1967 || (! mips_opts
.mips16
1968 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1969 /* If the branch reads the condition codes, we don't
1970 even try to swap, because in the sequence
1975 we can not swap, and I don't feel like handling that
1977 || (! mips_opts
.mips16
1978 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1979 && (pinfo
& INSN_READ_COND_CODE
))
1980 /* We can not swap with an instruction that requires a
1981 delay slot, becase the target of the branch might
1982 interfere with that instruction. */
1983 || (! mips_opts
.mips16
1984 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1986 /* Itbl support may require additional care here. */
1987 & (INSN_LOAD_COPROC_DELAY
1988 | INSN_COPROC_MOVE_DELAY
1989 | INSN_WRITE_COND_CODE
)))
1990 || (! (hilo_interlocks
1991 || (mips_cpu
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1995 || (! mips_opts
.mips16
1997 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1998 || (! mips_opts
.mips16
1999 && mips_opts
.isa
== ISA_MIPS1
2000 /* Itbl support may require additional care here. */
2001 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2002 /* We can not swap with a branch instruction. */
2004 & (INSN_UNCOND_BRANCH_DELAY
2005 | INSN_COND_BRANCH_DELAY
2006 | INSN_COND_BRANCH_LIKELY
))
2007 /* We do not swap with a trap instruction, since it
2008 complicates trap handlers to have the trap
2009 instruction be in a delay slot. */
2010 || (prev_pinfo
& INSN_TRAP
)
2011 /* If the branch reads a register that the previous
2012 instruction sets, we can not swap. */
2013 || (! mips_opts
.mips16
2014 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2015 && insn_uses_reg (ip
,
2016 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2019 || (! mips_opts
.mips16
2020 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2021 && insn_uses_reg (ip
,
2022 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2025 || (mips_opts
.mips16
2026 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2027 && insn_uses_reg (ip
,
2028 ((prev_insn
.insn_opcode
2030 & MIPS16OP_MASK_RX
),
2032 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2033 && insn_uses_reg (ip
,
2034 ((prev_insn
.insn_opcode
2036 & MIPS16OP_MASK_RY
),
2038 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2039 && insn_uses_reg (ip
,
2040 ((prev_insn
.insn_opcode
2042 & MIPS16OP_MASK_RZ
),
2044 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2045 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2046 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2047 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2048 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2049 && insn_uses_reg (ip
,
2050 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2053 /* If the branch writes a register that the previous
2054 instruction sets, we can not swap (we know that
2055 branches write only to RD or to $31). */
2056 || (! mips_opts
.mips16
2057 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2058 && (((pinfo
& INSN_WRITE_GPR_D
)
2059 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2060 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2061 || ((pinfo
& INSN_WRITE_GPR_31
)
2062 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2065 || (! mips_opts
.mips16
2066 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2067 && (((pinfo
& INSN_WRITE_GPR_D
)
2068 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2069 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2070 || ((pinfo
& INSN_WRITE_GPR_31
)
2071 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2074 || (mips_opts
.mips16
2075 && (pinfo
& MIPS16_INSN_WRITE_31
)
2076 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2077 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2078 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2080 /* If the branch writes a register that the previous
2081 instruction reads, we can not swap (we know that
2082 branches only write to RD or to $31). */
2083 || (! mips_opts
.mips16
2084 && (pinfo
& INSN_WRITE_GPR_D
)
2085 && insn_uses_reg (&prev_insn
,
2086 ((ip
->insn_opcode
>> OP_SH_RD
)
2089 || (! mips_opts
.mips16
2090 && (pinfo
& INSN_WRITE_GPR_31
)
2091 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2092 || (mips_opts
.mips16
2093 && (pinfo
& MIPS16_INSN_WRITE_31
)
2094 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2095 /* If we are generating embedded PIC code, the branch
2096 might be expanded into a sequence which uses $at, so
2097 we can't swap with an instruction which reads it. */
2098 || (mips_pic
== EMBEDDED_PIC
2099 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2100 /* If the previous previous instruction has a load
2101 delay, and sets a register that the branch reads, we
2103 || (! mips_opts
.mips16
2104 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2105 /* Itbl support may require additional care here. */
2106 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2107 || (! gpr_interlocks
2108 && (prev_prev_insn
.insn_mo
->pinfo
2109 & INSN_LOAD_MEMORY_DELAY
)))
2110 && insn_uses_reg (ip
,
2111 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2114 /* If one instruction sets a condition code and the
2115 other one uses a condition code, we can not swap. */
2116 || ((pinfo
& INSN_READ_COND_CODE
)
2117 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2118 || ((pinfo
& INSN_WRITE_COND_CODE
)
2119 && (prev_pinfo
& INSN_READ_COND_CODE
))
2120 /* If the previous instruction uses the PC, we can not
2122 || (mips_opts
.mips16
2123 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2124 /* If the previous instruction was extended, we can not
2126 || (mips_opts
.mips16
&& prev_insn_extended
)
2127 /* If the previous instruction had a fixup in mips16
2128 mode, we can not swap. This normally means that the
2129 previous instruction was a 4 byte branch anyhow. */
2130 || (mips_opts
.mips16
&& prev_insn_fixp
)
2131 /* If the previous instruction is a sync, sync.l, or
2132 sync.p, we can not swap. */
2133 || (prev_pinfo
& INSN_SYNC
))
2135 /* We could do even better for unconditional branches to
2136 portions of this object file; we could pick up the
2137 instruction at the destination, put it in the delay
2138 slot, and bump the destination address. */
2140 /* Update the previous insn information. */
2141 prev_prev_insn
= *ip
;
2142 prev_insn
.insn_mo
= &dummy_opcode
;
2146 /* It looks like we can actually do the swap. */
2147 if (! mips_opts
.mips16
)
2152 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2153 memcpy (temp
, prev_f
, 4);
2154 memcpy (prev_f
, f
, 4);
2155 memcpy (f
, temp
, 4);
2158 prev_insn_fixp
->fx_frag
= frag_now
;
2159 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2163 fixp
->fx_frag
= prev_insn_frag
;
2164 fixp
->fx_where
= prev_insn_where
;
2172 assert (prev_insn_fixp
== NULL
);
2173 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2174 memcpy (temp
, prev_f
, 2);
2175 memcpy (prev_f
, f
, 2);
2176 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2178 assert (reloc_type
== BFD_RELOC_UNUSED
);
2179 memcpy (f
, temp
, 2);
2183 memcpy (f
, f
+ 2, 2);
2184 memcpy (f
+ 2, temp
, 2);
2188 fixp
->fx_frag
= prev_insn_frag
;
2189 fixp
->fx_where
= prev_insn_where
;
2193 /* Update the previous insn information; leave prev_insn
2195 prev_prev_insn
= *ip
;
2197 prev_insn_is_delay_slot
= 1;
2199 /* If that was an unconditional branch, forget the previous
2200 insn information. */
2201 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2203 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2204 prev_insn
.insn_mo
= &dummy_opcode
;
2207 prev_insn_fixp
= NULL
;
2208 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2209 prev_insn_extended
= 0;
2211 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2213 /* We don't yet optimize a branch likely. What we should do
2214 is look at the target, copy the instruction found there
2215 into the delay slot, and increment the branch to jump to
2216 the next instruction. */
2218 /* Update the previous insn information. */
2219 prev_prev_insn
= *ip
;
2220 prev_insn
.insn_mo
= &dummy_opcode
;
2221 prev_insn_fixp
= NULL
;
2222 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2223 prev_insn_extended
= 0;
2227 /* Update the previous insn information. */
2229 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2231 prev_prev_insn
= prev_insn
;
2234 /* Any time we see a branch, we always fill the delay slot
2235 immediately; since this insn is not a branch, we know it
2236 is not in a delay slot. */
2237 prev_insn_is_delay_slot
= 0;
2239 prev_insn_fixp
= fixp
;
2240 prev_insn_reloc_type
= reloc_type
;
2241 if (mips_opts
.mips16
)
2242 prev_insn_extended
= (ip
->use_extend
2243 || reloc_type
> BFD_RELOC_UNUSED
);
2246 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2247 prev_insn_unreordered
= 0;
2248 prev_insn_frag
= frag_now
;
2249 prev_insn_where
= f
- frag_now
->fr_literal
;
2250 prev_insn_valid
= 1;
2252 else if (place
== NULL
)
2254 /* We need to record a bit of information even when we are not
2255 reordering, in order to determine the base address for mips16
2256 PC relative relocs. */
2257 prev_prev_insn
= prev_insn
;
2259 prev_insn_reloc_type
= reloc_type
;
2260 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2261 prev_insn_unreordered
= 1;
2264 /* We just output an insn, so the next one doesn't have a label. */
2265 mips_clear_insn_labels ();
2267 /* We must ensure that a fixup associated with an unmatched %hi
2268 reloc does not become a variant frag. Otherwise, the
2269 rearrangement of %hi relocs in frob_file may confuse
2273 frag_wane (frag_now
);
2278 /* This function forgets that there was any previous instruction or
2279 label. If PRESERVE is non-zero, it remembers enough information to
2280 know whether nops are needed before a noreorder section. */
2283 mips_no_prev_insn (preserve
)
2288 prev_insn
.insn_mo
= &dummy_opcode
;
2289 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2290 prev_nop_frag
= NULL
;
2291 prev_nop_frag_holds
= 0;
2292 prev_nop_frag_required
= 0;
2293 prev_nop_frag_since
= 0;
2295 prev_insn_valid
= 0;
2296 prev_insn_is_delay_slot
= 0;
2297 prev_insn_unreordered
= 0;
2298 prev_insn_extended
= 0;
2299 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2300 prev_prev_insn_unreordered
= 0;
2301 mips_clear_insn_labels ();
2304 /* This function must be called whenever we turn on noreorder or emit
2305 something other than instructions. It inserts any NOPS which might
2306 be needed by the previous instruction, and clears the information
2307 kept for the previous instructions. The INSNS parameter is true if
2308 instructions are to follow. */
2311 mips_emit_delays (insns
)
2314 if (! mips_opts
.noreorder
)
2319 if ((! mips_opts
.mips16
2320 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2321 && (! cop_interlocks
2322 && (prev_insn
.insn_mo
->pinfo
2323 & (INSN_LOAD_COPROC_DELAY
2324 | INSN_COPROC_MOVE_DELAY
2325 | INSN_WRITE_COND_CODE
))))
2326 || (! hilo_interlocks
2327 && (prev_insn
.insn_mo
->pinfo
2330 || (! mips_opts
.mips16
2332 && (prev_insn
.insn_mo
->pinfo
2333 & INSN_LOAD_MEMORY_DELAY
))
2334 || (! mips_opts
.mips16
2335 && mips_opts
.isa
== ISA_MIPS1
2336 && (prev_insn
.insn_mo
->pinfo
2337 & INSN_COPROC_MEMORY_DELAY
)))
2339 /* Itbl support may require additional care here. */
2341 if ((! mips_opts
.mips16
2342 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2343 && (! cop_interlocks
2344 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2345 || (! hilo_interlocks
2346 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2347 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2350 if (prev_insn_unreordered
)
2353 else if ((! mips_opts
.mips16
2354 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2355 && (! cop_interlocks
2356 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2357 || (! hilo_interlocks
2358 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2359 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2361 /* Itbl support may require additional care here. */
2362 if (! prev_prev_insn_unreordered
)
2368 struct insn_label_list
*l
;
2372 /* Record the frag which holds the nop instructions, so
2373 that we can remove them if we don't need them. */
2374 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2375 prev_nop_frag
= frag_now
;
2376 prev_nop_frag_holds
= nops
;
2377 prev_nop_frag_required
= 0;
2378 prev_nop_frag_since
= 0;
2381 for (; nops
> 0; --nops
)
2386 /* Move on to a new frag, so that it is safe to simply
2387 decrease the size of prev_nop_frag. */
2388 frag_wane (frag_now
);
2392 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2394 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2395 symbol_set_frag (l
->label
, frag_now
);
2396 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2397 /* mips16 text labels are stored as odd. */
2398 if (mips_opts
.mips16
)
2399 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2404 /* Mark instruction labels in mips16 mode. */
2405 if (mips_opts
.mips16
&& insns
)
2406 mips16_mark_labels ();
2408 mips_no_prev_insn (insns
);
2411 /* Build an instruction created by a macro expansion. This is passed
2412 a pointer to the count of instructions created so far, an
2413 expression, the name of the instruction to build, an operand format
2414 string, and corresponding arguments. */
2418 macro_build (char *place
,
2426 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2435 struct mips_cl_insn insn
;
2436 bfd_reloc_code_real_type r
;
2440 va_start (args
, fmt
);
2446 * If the macro is about to expand into a second instruction,
2447 * print a warning if needed. We need to pass ip as a parameter
2448 * to generate a better warning message here...
2450 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2451 as_warn (_("Macro instruction expanded into multiple instructions"));
2454 *counter
+= 1; /* bump instruction counter */
2456 if (mips_opts
.mips16
)
2458 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2463 r
= BFD_RELOC_UNUSED
;
2464 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2465 assert (insn
.insn_mo
);
2466 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2468 /* Search until we get a match for NAME. */
2471 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2472 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2473 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2475 && (mips_cpu
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2479 assert (insn
.insn_mo
->name
);
2480 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2483 insn
.insn_opcode
= insn
.insn_mo
->match
;
2499 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2505 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2510 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2515 int tmp
= va_arg (args
, int);
2517 insn
.insn_opcode
|= tmp
<< 16;
2518 insn
.insn_opcode
|= tmp
<< 11;
2524 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2531 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2535 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2539 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2543 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2547 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2554 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2560 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2561 assert (r
== BFD_RELOC_MIPS_GPREL
2562 || r
== BFD_RELOC_MIPS_LITERAL
2563 || r
== BFD_RELOC_LO16
2564 || r
== BFD_RELOC_MIPS_GOT16
2565 || r
== BFD_RELOC_MIPS_CALL16
2566 || r
== BFD_RELOC_MIPS_GOT_LO16
2567 || r
== BFD_RELOC_MIPS_CALL_LO16
2568 || (ep
->X_op
== O_subtract
2569 && r
== BFD_RELOC_PCREL_LO16
));
2573 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2575 && (ep
->X_op
== O_constant
2576 || (ep
->X_op
== O_symbol
2577 && (r
== BFD_RELOC_HI16_S
2578 || r
== BFD_RELOC_HI16
2579 || r
== BFD_RELOC_MIPS_GOT_HI16
2580 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2581 || (ep
->X_op
== O_subtract
2582 && r
== BFD_RELOC_PCREL_HI16_S
)));
2583 if (ep
->X_op
== O_constant
)
2585 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2587 r
= BFD_RELOC_UNUSED
;
2592 assert (ep
!= NULL
);
2594 * This allows macro() to pass an immediate expression for
2595 * creating short branches without creating a symbol.
2596 * Note that the expression still might come from the assembly
2597 * input, in which case the value is not checked for range nor
2598 * is a relocation entry generated (yuck).
2600 if (ep
->X_op
== O_constant
)
2602 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2606 r
= BFD_RELOC_16_PCREL_S2
;
2610 assert (ep
!= NULL
);
2611 r
= BFD_RELOC_MIPS_JMP
;
2615 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2624 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2626 append_insn (place
, &insn
, ep
, r
, false);
2630 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2632 int *counter ATTRIBUTE_UNUSED
;
2638 struct mips_cl_insn insn
;
2639 bfd_reloc_code_real_type r
;
2641 r
= BFD_RELOC_UNUSED
;
2642 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2643 assert (insn
.insn_mo
);
2644 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2646 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2647 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2650 assert (insn
.insn_mo
->name
);
2651 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2654 insn
.insn_opcode
= insn
.insn_mo
->match
;
2655 insn
.use_extend
= false;
2674 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2679 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2683 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2687 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2697 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2704 regno
= va_arg (args
, int);
2705 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2706 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2727 assert (ep
!= NULL
);
2729 if (ep
->X_op
!= O_constant
)
2730 r
= BFD_RELOC_UNUSED
+ c
;
2733 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2734 false, false, &insn
.insn_opcode
,
2735 &insn
.use_extend
, &insn
.extend
);
2737 r
= BFD_RELOC_UNUSED
;
2743 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2750 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2752 append_insn (place
, &insn
, ep
, r
, false);
2756 * Generate a "lui" instruction.
2759 macro_build_lui (place
, counter
, ep
, regnum
)
2765 expressionS high_expr
;
2766 struct mips_cl_insn insn
;
2767 bfd_reloc_code_real_type r
;
2768 CONST
char *name
= "lui";
2769 CONST
char *fmt
= "t,u";
2771 assert (! mips_opts
.mips16
);
2777 high_expr
.X_op
= O_constant
;
2778 high_expr
.X_add_number
= ep
->X_add_number
;
2781 if (high_expr
.X_op
== O_constant
)
2783 /* we can compute the instruction now without a relocation entry */
2784 if (high_expr
.X_add_number
& 0x8000)
2785 high_expr
.X_add_number
+= 0x10000;
2786 high_expr
.X_add_number
=
2787 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2788 r
= BFD_RELOC_UNUSED
;
2792 assert (ep
->X_op
== O_symbol
);
2793 /* _gp_disp is a special case, used from s_cpload. */
2794 assert (mips_pic
== NO_PIC
2795 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2796 r
= BFD_RELOC_HI16_S
;
2800 * If the macro is about to expand into a second instruction,
2801 * print a warning if needed. We need to pass ip as a parameter
2802 * to generate a better warning message here...
2804 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2805 as_warn (_("Macro instruction expanded into multiple instructions"));
2808 *counter
+= 1; /* bump instruction counter */
2810 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2811 assert (insn
.insn_mo
);
2812 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2813 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2815 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2816 if (r
== BFD_RELOC_UNUSED
)
2818 insn
.insn_opcode
|= high_expr
.X_add_number
;
2819 append_insn (place
, &insn
, NULL
, r
, false);
2822 append_insn (place
, &insn
, &high_expr
, r
, false);
2826 * Generates code to set the $at register to true (one)
2827 * if reg is less than the immediate expression.
2830 set_at (counter
, reg
, unsignedp
)
2835 if (imm_expr
.X_op
== O_constant
2836 && imm_expr
.X_add_number
>= -0x8000
2837 && imm_expr
.X_add_number
< 0x8000)
2838 macro_build ((char *) NULL
, counter
, &imm_expr
,
2839 unsignedp
? "sltiu" : "slti",
2840 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2843 load_register (counter
, AT
, &imm_expr
, 0);
2844 macro_build ((char *) NULL
, counter
, NULL
,
2845 unsignedp
? "sltu" : "slt",
2846 "d,v,t", AT
, reg
, AT
);
2850 /* Warn if an expression is not a constant. */
2853 check_absolute_expr (ip
, ex
)
2854 struct mips_cl_insn
*ip
;
2857 if (ex
->X_op
== O_big
)
2858 as_bad (_("unsupported large constant"));
2859 else if (ex
->X_op
!= O_constant
)
2860 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2863 /* Count the leading zeroes by performing a binary chop. This is a
2864 bulky bit of source, but performance is a LOT better for the
2865 majority of values than a simple loop to count the bits:
2866 for (lcnt = 0; (lcnt < 32); lcnt++)
2867 if ((v) & (1 << (31 - lcnt)))
2869 However it is not code size friendly, and the gain will drop a bit
2870 on certain cached systems.
2872 #define COUNT_TOP_ZEROES(v) \
2873 (((v) & ~0xffff) == 0 \
2874 ? ((v) & ~0xff) == 0 \
2875 ? ((v) & ~0xf) == 0 \
2876 ? ((v) & ~0x3) == 0 \
2877 ? ((v) & ~0x1) == 0 \
2882 : ((v) & ~0x7) == 0 \
2885 : ((v) & ~0x3f) == 0 \
2886 ? ((v) & ~0x1f) == 0 \
2889 : ((v) & ~0x7f) == 0 \
2892 : ((v) & ~0xfff) == 0 \
2893 ? ((v) & ~0x3ff) == 0 \
2894 ? ((v) & ~0x1ff) == 0 \
2897 : ((v) & ~0x7ff) == 0 \
2900 : ((v) & ~0x3fff) == 0 \
2901 ? ((v) & ~0x1fff) == 0 \
2904 : ((v) & ~0x7fff) == 0 \
2907 : ((v) & ~0xffffff) == 0 \
2908 ? ((v) & ~0xfffff) == 0 \
2909 ? ((v) & ~0x3ffff) == 0 \
2910 ? ((v) & ~0x1ffff) == 0 \
2913 : ((v) & ~0x7ffff) == 0 \
2916 : ((v) & ~0x3fffff) == 0 \
2917 ? ((v) & ~0x1fffff) == 0 \
2920 : ((v) & ~0x7fffff) == 0 \
2923 : ((v) & ~0xfffffff) == 0 \
2924 ? ((v) & ~0x3ffffff) == 0 \
2925 ? ((v) & ~0x1ffffff) == 0 \
2928 : ((v) & ~0x7ffffff) == 0 \
2931 : ((v) & ~0x3fffffff) == 0 \
2932 ? ((v) & ~0x1fffffff) == 0 \
2935 : ((v) & ~0x7fffffff) == 0 \
2940 * This routine generates the least number of instructions neccessary to load
2941 * an absolute expression value into a register.
2944 load_register (counter
, reg
, ep
, dbl
)
2951 expressionS hi32
, lo32
;
2953 if (ep
->X_op
!= O_big
)
2955 assert (ep
->X_op
== O_constant
);
2956 if (ep
->X_add_number
< 0x8000
2957 && (ep
->X_add_number
>= 0
2958 || (ep
->X_add_number
>= -0x8000
2961 || sizeof (ep
->X_add_number
) > 4))))
2963 /* We can handle 16 bit signed values with an addiu to
2964 $zero. No need to ever use daddiu here, since $zero and
2965 the result are always correct in 32 bit mode. */
2966 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2967 (int) BFD_RELOC_LO16
);
2970 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2972 /* We can handle 16 bit unsigned values with an ori to
2974 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2975 (int) BFD_RELOC_LO16
);
2978 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2979 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2980 == ~ (offsetT
) 0x7fffffff))
2983 || sizeof (ep
->X_add_number
) > 4
2984 || (ep
->X_add_number
& 0x80000000) == 0))
2985 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
2986 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2987 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
2989 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2990 == ~ (offsetT
) 0xffffffff)))
2992 /* 32 bit values require an lui. */
2993 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2994 (int) BFD_RELOC_HI16
);
2995 if ((ep
->X_add_number
& 0xffff) != 0)
2996 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2997 (int) BFD_RELOC_LO16
);
3002 /* The value is larger than 32 bits. */
3004 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3006 as_bad (_("Number larger than 32 bits"));
3007 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3008 (int) BFD_RELOC_LO16
);
3012 if (ep
->X_op
!= O_big
)
3015 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3016 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3017 hi32
.X_add_number
&= 0xffffffff;
3019 lo32
.X_add_number
&= 0xffffffff;
3023 assert (ep
->X_add_number
> 2);
3024 if (ep
->X_add_number
== 3)
3025 generic_bignum
[3] = 0;
3026 else if (ep
->X_add_number
> 4)
3027 as_bad (_("Number larger than 64 bits"));
3028 lo32
.X_op
= O_constant
;
3029 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3030 hi32
.X_op
= O_constant
;
3031 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3034 if (hi32
.X_add_number
== 0)
3039 unsigned long hi
, lo
;
3041 if (hi32
.X_add_number
== 0xffffffff)
3043 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3045 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3046 reg
, 0, (int) BFD_RELOC_LO16
);
3049 if (lo32
.X_add_number
& 0x80000000)
3051 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3052 (int) BFD_RELOC_HI16
);
3053 if (lo32
.X_add_number
& 0xffff)
3054 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3055 reg
, reg
, (int) BFD_RELOC_LO16
);
3060 /* Check for 16bit shifted constant. We know that hi32 is
3061 non-zero, so start the mask on the first bit of the hi32
3066 unsigned long himask
, lomask
;
3070 himask
= 0xffff >> (32 - shift
);
3071 lomask
= (0xffff << shift
) & 0xffffffff;
3075 himask
= 0xffff << (shift
- 32);
3078 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3079 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3083 tmp
.X_op
= O_constant
;
3085 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3086 | (lo32
.X_add_number
>> shift
));
3088 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3089 macro_build ((char *) NULL
, counter
, &tmp
,
3090 "ori", "t,r,i", reg
, 0,
3091 (int) BFD_RELOC_LO16
);
3092 macro_build ((char *) NULL
, counter
, NULL
,
3093 (shift
>= 32) ? "dsll32" : "dsll",
3095 (shift
>= 32) ? shift
- 32 : shift
);
3100 while (shift
<= (64 - 16));
3102 /* Find the bit number of the lowest one bit, and store the
3103 shifted value in hi/lo. */
3104 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3105 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3109 while ((lo
& 1) == 0)
3114 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3120 while ((hi
& 1) == 0)
3129 /* Optimize if the shifted value is a (power of 2) - 1. */
3130 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3131 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3133 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3138 /* This instruction will set the register to be all
3140 tmp
.X_op
= O_constant
;
3141 tmp
.X_add_number
= (offsetT
) -1;
3142 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3143 reg
, 0, (int) BFD_RELOC_LO16
);
3147 macro_build ((char *) NULL
, counter
, NULL
,
3148 (bit
>= 32) ? "dsll32" : "dsll",
3150 (bit
>= 32) ? bit
- 32 : bit
);
3152 macro_build ((char *) NULL
, counter
, NULL
,
3153 (shift
>= 32) ? "dsrl32" : "dsrl",
3155 (shift
>= 32) ? shift
- 32 : shift
);
3160 /* Sign extend hi32 before calling load_register, because we can
3161 generally get better code when we load a sign extended value. */
3162 if ((hi32
.X_add_number
& 0x80000000) != 0)
3163 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3164 load_register (counter
, reg
, &hi32
, 0);
3167 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3171 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3180 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3182 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3183 (int) BFD_RELOC_HI16
);
3184 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3191 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3196 mid16
.X_add_number
>>= 16;
3197 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3198 freg
, (int) BFD_RELOC_LO16
);
3199 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3203 if ((lo32
.X_add_number
& 0xffff) != 0)
3204 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3205 (int) BFD_RELOC_LO16
);
3208 /* Load an address into a register. */
3211 load_address (counter
, reg
, ep
)
3218 if (ep
->X_op
!= O_constant
3219 && ep
->X_op
!= O_symbol
)
3221 as_bad (_("expression too complex"));
3222 ep
->X_op
= O_constant
;
3225 if (ep
->X_op
== O_constant
)
3227 load_register (counter
, reg
, ep
, 0);
3231 if (mips_pic
== NO_PIC
)
3233 /* If this is a reference to a GP relative symbol, we want
3234 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3236 lui $reg,<sym> (BFD_RELOC_HI16_S)
3237 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3238 If we have an addend, we always use the latter form. */
3239 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3240 || nopic_need_relax (ep
->X_add_symbol
, 1))
3245 macro_build ((char *) NULL
, counter
, ep
,
3246 ((bfd_arch_bits_per_address (stdoutput
) == 32
3247 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3248 ? "addiu" : "daddiu"),
3249 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3250 p
= frag_var (rs_machine_dependent
, 8, 0,
3251 RELAX_ENCODE (4, 8, 0, 4, 0,
3252 mips_opts
.warn_about_macros
),
3253 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3255 macro_build_lui (p
, counter
, ep
, reg
);
3258 macro_build (p
, counter
, ep
,
3259 ((bfd_arch_bits_per_address (stdoutput
) == 32
3260 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3261 ? "addiu" : "daddiu"),
3262 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3264 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3268 /* If this is a reference to an external symbol, we want
3269 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3271 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3273 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3274 If there is a constant, it must be added in after. */
3275 ex
.X_add_number
= ep
->X_add_number
;
3276 ep
->X_add_number
= 0;
3278 macro_build ((char *) NULL
, counter
, ep
,
3279 ((bfd_arch_bits_per_address (stdoutput
) == 32
3280 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3282 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3283 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3284 p
= frag_var (rs_machine_dependent
, 4, 0,
3285 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3286 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3287 macro_build (p
, counter
, ep
,
3288 ((bfd_arch_bits_per_address (stdoutput
) == 32
3289 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3290 ? "addiu" : "daddiu"),
3291 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3292 if (ex
.X_add_number
!= 0)
3294 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3295 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3296 ex
.X_op
= O_constant
;
3297 macro_build ((char *) NULL
, counter
, &ex
,
3298 ((bfd_arch_bits_per_address (stdoutput
) == 32
3299 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3300 ? "addiu" : "daddiu"),
3301 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3304 else if (mips_pic
== SVR4_PIC
)
3309 /* This is the large GOT case. If this is a reference to an
3310 external symbol, we want
3311 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3313 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3314 Otherwise, for a reference to a local symbol, we want
3315 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3317 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3318 If there is a constant, it must be added in after. */
3319 ex
.X_add_number
= ep
->X_add_number
;
3320 ep
->X_add_number
= 0;
3321 if (reg_needs_delay (GP
))
3326 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3327 (int) BFD_RELOC_MIPS_GOT_HI16
);
3328 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3329 ((bfd_arch_bits_per_address (stdoutput
) == 32
3330 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3331 ? "addu" : "daddu"),
3332 "d,v,t", reg
, reg
, GP
);
3333 macro_build ((char *) NULL
, counter
, ep
,
3334 ((bfd_arch_bits_per_address (stdoutput
) == 32
3335 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3337 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3338 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3339 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3340 mips_opts
.warn_about_macros
),
3341 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3344 /* We need a nop before loading from $gp. This special
3345 check is required because the lui which starts the main
3346 instruction stream does not refer to $gp, and so will not
3347 insert the nop which may be required. */
3348 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3351 macro_build (p
, counter
, ep
,
3352 ((bfd_arch_bits_per_address (stdoutput
) == 32
3353 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3355 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3357 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3359 macro_build (p
, counter
, ep
,
3360 ((bfd_arch_bits_per_address (stdoutput
) == 32
3361 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3362 ? "addiu" : "daddiu"),
3363 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3364 if (ex
.X_add_number
!= 0)
3366 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3367 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3368 ex
.X_op
= O_constant
;
3369 macro_build ((char *) NULL
, counter
, &ex
,
3370 ((bfd_arch_bits_per_address (stdoutput
) == 32
3371 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3372 ? "addiu" : "daddiu"),
3373 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3376 else if (mips_pic
== EMBEDDED_PIC
)
3379 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3381 macro_build ((char *) NULL
, counter
, ep
,
3382 ((bfd_arch_bits_per_address (stdoutput
) == 32
3383 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3384 ? "addiu" : "daddiu"),
3385 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3393 * This routine implements the seemingly endless macro or synthesized
3394 * instructions and addressing modes in the mips assembly language. Many
3395 * of these macros are simple and are similar to each other. These could
3396 * probably be handled by some kind of table or grammer aproach instead of
3397 * this verbose method. Others are not simple macros but are more like
3398 * optimizing code generation.
3399 * One interesting optimization is when several store macros appear
3400 * consecutivly that would load AT with the upper half of the same address.
3401 * The ensuing load upper instructions are ommited. This implies some kind
3402 * of global optimization. We currently only optimize within a single macro.
3403 * For many of the load and store macros if the address is specified as a
3404 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3405 * first load register 'at' with zero and use it as the base register. The
3406 * mips assembler simply uses register $zero. Just one tiny optimization
3411 struct mips_cl_insn
*ip
;
3413 register int treg
, sreg
, dreg
, breg
;
3429 bfd_reloc_code_real_type r
;
3431 int hold_mips_optimize
;
3433 assert (! mips_opts
.mips16
);
3435 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3436 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3437 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3438 mask
= ip
->insn_mo
->mask
;
3440 expr1
.X_op
= O_constant
;
3441 expr1
.X_op_symbol
= NULL
;
3442 expr1
.X_add_symbol
= NULL
;
3443 expr1
.X_add_number
= 1;
3455 mips_emit_delays (true);
3456 ++mips_opts
.noreorder
;
3457 mips_any_noreorder
= 1;
3459 expr1
.X_add_number
= 8;
3460 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3462 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3464 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3465 macro_build ((char *) NULL
, &icnt
, NULL
,
3466 dbl
? "dsub" : "sub",
3467 "d,v,t", dreg
, 0, sreg
);
3469 --mips_opts
.noreorder
;
3490 if (imm_expr
.X_op
== O_constant
3491 && imm_expr
.X_add_number
>= -0x8000
3492 && imm_expr
.X_add_number
< 0x8000)
3494 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3495 (int) BFD_RELOC_LO16
);
3498 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3499 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3518 if (imm_expr
.X_op
== O_constant
3519 && imm_expr
.X_add_number
>= 0
3520 && imm_expr
.X_add_number
< 0x10000)
3522 if (mask
!= M_NOR_I
)
3523 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3524 sreg
, (int) BFD_RELOC_LO16
);
3527 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3528 treg
, sreg
, (int) BFD_RELOC_LO16
);
3529 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3535 load_register (&icnt
, AT
, &imm_expr
, 0);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3553 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3555 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3559 load_register (&icnt
, AT
, &imm_expr
, 0);
3560 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3568 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3569 likely
? "bgezl" : "bgez",
3575 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3576 likely
? "blezl" : "blez",
3580 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3581 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3582 likely
? "beql" : "beq",
3589 /* check for > max integer */
3590 maxnum
= 0x7fffffff;
3591 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3598 if (imm_expr
.X_op
== O_constant
3599 && imm_expr
.X_add_number
>= maxnum
3600 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3603 /* result is always false */
3606 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3607 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3611 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3612 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3617 if (imm_expr
.X_op
!= O_constant
)
3618 as_bad (_("Unsupported large constant"));
3619 imm_expr
.X_add_number
++;
3623 if (mask
== M_BGEL_I
)
3625 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3627 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3628 likely
? "bgezl" : "bgez",
3632 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3634 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3635 likely
? "bgtzl" : "bgtz",
3639 maxnum
= 0x7fffffff;
3640 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3647 maxnum
= - maxnum
- 1;
3648 if (imm_expr
.X_op
== O_constant
3649 && imm_expr
.X_add_number
<= maxnum
3650 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3653 /* result is always true */
3654 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3655 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3658 set_at (&icnt
, sreg
, 0);
3659 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3660 likely
? "beql" : "beq",
3671 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3672 likely
? "beql" : "beq",
3676 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3678 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3679 likely
? "beql" : "beq",
3687 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3688 && imm_expr
.X_op
== O_constant
3689 && imm_expr
.X_add_number
== 0xffffffff))
3691 if (imm_expr
.X_op
!= O_constant
)
3692 as_bad (_("Unsupported large constant"));
3693 imm_expr
.X_add_number
++;
3697 if (mask
== M_BGEUL_I
)
3699 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3701 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3703 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3704 likely
? "bnel" : "bne",
3708 set_at (&icnt
, sreg
, 1);
3709 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3710 likely
? "beql" : "beq",
3719 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3720 likely
? "bgtzl" : "bgtz",
3726 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3727 likely
? "bltzl" : "bltz",
3731 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3732 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3733 likely
? "bnel" : "bne",
3742 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3743 likely
? "bnel" : "bne",
3749 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3752 likely
? "bnel" : "bne",
3761 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3762 likely
? "blezl" : "blez",
3768 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3769 likely
? "bgezl" : "bgez",
3773 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3774 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3775 likely
? "beql" : "beq",
3782 maxnum
= 0x7fffffff;
3783 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3790 if (imm_expr
.X_op
== O_constant
3791 && imm_expr
.X_add_number
>= maxnum
3792 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3794 if (imm_expr
.X_op
!= O_constant
)
3795 as_bad (_("Unsupported large constant"));
3796 imm_expr
.X_add_number
++;
3800 if (mask
== M_BLTL_I
)
3802 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3804 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3805 likely
? "bltzl" : "bltz",
3809 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3812 likely
? "blezl" : "blez",
3816 set_at (&icnt
, sreg
, 0);
3817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3818 likely
? "bnel" : "bne",
3827 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3828 likely
? "beql" : "beq",
3834 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3836 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3837 likely
? "beql" : "beq",
3845 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3846 && imm_expr
.X_op
== O_constant
3847 && imm_expr
.X_add_number
== 0xffffffff))
3849 if (imm_expr
.X_op
!= O_constant
)
3850 as_bad (_("Unsupported large constant"));
3851 imm_expr
.X_add_number
++;
3855 if (mask
== M_BLTUL_I
)
3857 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3859 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3861 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3862 likely
? "beql" : "beq",
3866 set_at (&icnt
, sreg
, 1);
3867 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3868 likely
? "bnel" : "bne",
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3878 likely
? "bltzl" : "bltz",
3884 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3885 likely
? "bgtzl" : "bgtz",
3889 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3890 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3891 likely
? "bnel" : "bne",
3902 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3903 likely
? "bnel" : "bne",
3907 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3909 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3910 likely
? "bnel" : "bne",
3926 as_warn (_("Divide by zero."));
3928 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3930 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3934 mips_emit_delays (true);
3935 ++mips_opts
.noreorder
;
3936 mips_any_noreorder
= 1;
3939 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3940 macro_build ((char *) NULL
, &icnt
, NULL
,
3941 dbl
? "ddiv" : "div",
3942 "z,s,t", sreg
, treg
);
3946 expr1
.X_add_number
= 8;
3947 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3948 macro_build ((char *) NULL
, &icnt
, NULL
,
3949 dbl
? "ddiv" : "div",
3950 "z,s,t", sreg
, treg
);
3951 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3953 expr1
.X_add_number
= -1;
3954 macro_build ((char *) NULL
, &icnt
, &expr1
,
3955 dbl
? "daddiu" : "addiu",
3956 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3957 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3958 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3961 expr1
.X_add_number
= 1;
3962 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3963 (int) BFD_RELOC_LO16
);
3964 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3969 expr1
.X_add_number
= 0x80000000;
3970 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3971 (int) BFD_RELOC_HI16
);
3975 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3976 /* We want to close the noreorder block as soon as possible, so
3977 that later insns are available for delay slot filling. */
3978 --mips_opts
.noreorder
;
3982 expr1
.X_add_number
= 8;
3983 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3984 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3986 /* We want to close the noreorder block as soon as possible, so
3987 that later insns are available for delay slot filling. */
3988 --mips_opts
.noreorder
;
3990 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3992 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4031 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4033 as_warn (_("Divide by zero."));
4035 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4037 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4040 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4042 if (strcmp (s2
, "mflo") == 0)
4043 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4046 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4049 if (imm_expr
.X_op
== O_constant
4050 && imm_expr
.X_add_number
== -1
4051 && s
[strlen (s
) - 1] != 'u')
4053 if (strcmp (s2
, "mflo") == 0)
4056 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4059 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4063 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4067 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4068 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4069 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4088 mips_emit_delays (true);
4089 ++mips_opts
.noreorder
;
4090 mips_any_noreorder
= 1;
4093 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4094 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4095 /* We want to close the noreorder block as soon as possible, so
4096 that later insns are available for delay slot filling. */
4097 --mips_opts
.noreorder
;
4101 expr1
.X_add_number
= 8;
4102 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4103 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4105 /* We want to close the noreorder block as soon as possible, so
4106 that later insns are available for delay slot filling. */
4107 --mips_opts
.noreorder
;
4108 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4110 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4116 /* Load the address of a symbol into a register. If breg is not
4117 zero, we then add a base register to it. */
4119 /* When generating embedded PIC code, we permit expressions of
4122 where bar is an address in the current section. These are used
4123 when getting the addresses of functions. We don't permit
4124 X_add_number to be non-zero, because if the symbol is
4125 external the relaxing code needs to know that any addend is
4126 purely the offset to X_op_symbol. */
4127 if (mips_pic
== EMBEDDED_PIC
4128 && offset_expr
.X_op
== O_subtract
4129 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4130 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4131 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4133 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4137 && (offset_expr
.X_add_number
== 0
4138 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4140 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4141 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4142 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4143 ((bfd_arch_bits_per_address (stdoutput
) == 32
4144 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4145 ? "addiu" : "daddiu"),
4146 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4150 if (offset_expr
.X_op
!= O_symbol
4151 && offset_expr
.X_op
!= O_constant
)
4153 as_bad (_("expression too complex"));
4154 offset_expr
.X_op
= O_constant
;
4168 if (offset_expr
.X_op
== O_constant
)
4169 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4170 else if (mips_pic
== NO_PIC
)
4172 /* If this is a reference to an GP relative symbol, we want
4173 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4175 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4176 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4177 If we have a constant, we need two instructions anyhow,
4178 so we may as well always use the latter form. */
4179 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4180 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4185 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4186 ((bfd_arch_bits_per_address (stdoutput
) == 32
4187 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4188 ? "addiu" : "daddiu"),
4189 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4190 p
= frag_var (rs_machine_dependent
, 8, 0,
4191 RELAX_ENCODE (4, 8, 0, 4, 0,
4192 mips_opts
.warn_about_macros
),
4193 offset_expr
.X_add_symbol
, (offsetT
) 0,
4196 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4199 macro_build (p
, &icnt
, &offset_expr
,
4200 ((bfd_arch_bits_per_address (stdoutput
) == 32
4201 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4202 ? "addiu" : "daddiu"),
4203 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4205 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4207 /* If this is a reference to an external symbol, and there
4208 is no constant, we want
4209 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4210 For a local symbol, we want
4211 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4213 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4215 If we have a small constant, and this is a reference to
4216 an external symbol, we want
4217 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4219 addiu $tempreg,$tempreg,<constant>
4220 For a local symbol, we want the same instruction
4221 sequence, but we output a BFD_RELOC_LO16 reloc on the
4224 If we have a large constant, and this is a reference to
4225 an external symbol, we want
4226 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4227 lui $at,<hiconstant>
4228 addiu $at,$at,<loconstant>
4229 addu $tempreg,$tempreg,$at
4230 For a local symbol, we want the same instruction
4231 sequence, but we output a BFD_RELOC_LO16 reloc on the
4232 addiu instruction. */
4233 expr1
.X_add_number
= offset_expr
.X_add_number
;
4234 offset_expr
.X_add_number
= 0;
4236 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4238 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4239 if (expr1
.X_add_number
== 0)
4247 /* We're going to put in an addu instruction using
4248 tempreg, so we may as well insert the nop right
4250 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4254 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4255 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4257 ? mips_opts
.warn_about_macros
4259 offset_expr
.X_add_symbol
, (offsetT
) 0,
4263 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4266 macro_build (p
, &icnt
, &expr1
,
4267 ((bfd_arch_bits_per_address (stdoutput
) == 32
4268 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4269 ? "addiu" : "daddiu"),
4270 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4271 /* FIXME: If breg == 0, and the next instruction uses
4272 $tempreg, then if this variant case is used an extra
4273 nop will be generated. */
4275 else if (expr1
.X_add_number
>= -0x8000
4276 && expr1
.X_add_number
< 0x8000)
4278 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4280 macro_build ((char *) NULL
, &icnt
, &expr1
,
4281 ((bfd_arch_bits_per_address (stdoutput
) == 32
4282 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4283 ? "addiu" : "daddiu"),
4284 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4285 (void) frag_var (rs_machine_dependent
, 0, 0,
4286 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4287 offset_expr
.X_add_symbol
, (offsetT
) 0,
4294 /* If we are going to add in a base register, and the
4295 target register and the base register are the same,
4296 then we are using AT as a temporary register. Since
4297 we want to load the constant into AT, we add our
4298 current AT (from the global offset table) and the
4299 register into the register now, and pretend we were
4300 not using a base register. */
4305 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4308 ((bfd_arch_bits_per_address (stdoutput
) == 32
4309 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4310 ? "addu" : "daddu"),
4311 "d,v,t", treg
, AT
, breg
);
4317 /* Set mips_optimize around the lui instruction to avoid
4318 inserting an unnecessary nop after the lw. */
4319 hold_mips_optimize
= mips_optimize
;
4321 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4322 mips_optimize
= hold_mips_optimize
;
4324 macro_build ((char *) NULL
, &icnt
, &expr1
,
4325 ((bfd_arch_bits_per_address (stdoutput
) == 32
4326 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4327 ? "addiu" : "daddiu"),
4328 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4329 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4330 ((bfd_arch_bits_per_address (stdoutput
) == 32
4331 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4332 ? "addu" : "daddu"),
4333 "d,v,t", tempreg
, tempreg
, AT
);
4334 (void) frag_var (rs_machine_dependent
, 0, 0,
4335 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4336 offset_expr
.X_add_symbol
, (offsetT
) 0,
4341 else if (mips_pic
== SVR4_PIC
)
4345 /* This is the large GOT case. If this is a reference to an
4346 external symbol, and there is no constant, we want
4347 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4348 addu $tempreg,$tempreg,$gp
4349 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4350 For a local symbol, we want
4351 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4353 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4355 If we have a small constant, and this is a reference to
4356 an external symbol, we want
4357 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4358 addu $tempreg,$tempreg,$gp
4359 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4361 addiu $tempreg,$tempreg,<constant>
4362 For a local symbol, we want
4363 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4365 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4367 If we have a large constant, and this is a reference to
4368 an external symbol, we want
4369 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4370 addu $tempreg,$tempreg,$gp
4371 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4372 lui $at,<hiconstant>
4373 addiu $at,$at,<loconstant>
4374 addu $tempreg,$tempreg,$at
4375 For a local symbol, we want
4376 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4377 lui $at,<hiconstant>
4378 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4379 addu $tempreg,$tempreg,$at
4381 expr1
.X_add_number
= offset_expr
.X_add_number
;
4382 offset_expr
.X_add_number
= 0;
4384 if (reg_needs_delay (GP
))
4388 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4389 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4390 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4391 ((bfd_arch_bits_per_address (stdoutput
) == 32
4392 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4393 ? "addu" : "daddu"),
4394 "d,v,t", tempreg
, tempreg
, GP
);
4395 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4397 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4399 if (expr1
.X_add_number
== 0)
4407 /* We're going to put in an addu instruction using
4408 tempreg, so we may as well insert the nop right
4410 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4415 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4416 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4419 ? mips_opts
.warn_about_macros
4421 offset_expr
.X_add_symbol
, (offsetT
) 0,
4424 else if (expr1
.X_add_number
>= -0x8000
4425 && expr1
.X_add_number
< 0x8000)
4427 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4429 macro_build ((char *) NULL
, &icnt
, &expr1
,
4430 ((bfd_arch_bits_per_address (stdoutput
) == 32
4431 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4432 ? "addiu" : "daddiu"),
4433 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4435 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4436 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4438 ? mips_opts
.warn_about_macros
4440 offset_expr
.X_add_symbol
, (offsetT
) 0,
4447 /* If we are going to add in a base register, and the
4448 target register and the base register are the same,
4449 then we are using AT as a temporary register. Since
4450 we want to load the constant into AT, we add our
4451 current AT (from the global offset table) and the
4452 register into the register now, and pretend we were
4453 not using a base register. */
4461 assert (tempreg
== AT
);
4462 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4464 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4465 ((bfd_arch_bits_per_address (stdoutput
) == 32
4466 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4467 ? "addu" : "daddu"),
4468 "d,v,t", treg
, AT
, breg
);
4473 /* Set mips_optimize around the lui instruction to avoid
4474 inserting an unnecessary nop after the lw. */
4475 hold_mips_optimize
= mips_optimize
;
4477 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4478 mips_optimize
= hold_mips_optimize
;
4480 macro_build ((char *) NULL
, &icnt
, &expr1
,
4481 ((bfd_arch_bits_per_address (stdoutput
) == 32
4482 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4483 ? "addiu" : "daddiu"),
4484 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4486 ((bfd_arch_bits_per_address (stdoutput
) == 32
4487 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4488 ? "addu" : "daddu"),
4489 "d,v,t", dreg
, dreg
, AT
);
4491 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4492 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4495 ? mips_opts
.warn_about_macros
4497 offset_expr
.X_add_symbol
, (offsetT
) 0,
4505 /* This is needed because this instruction uses $gp, but
4506 the first instruction on the main stream does not. */
4507 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4510 macro_build (p
, &icnt
, &offset_expr
,
4512 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4514 if (expr1
.X_add_number
>= -0x8000
4515 && expr1
.X_add_number
< 0x8000)
4517 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4519 macro_build (p
, &icnt
, &expr1
,
4520 ((bfd_arch_bits_per_address (stdoutput
) == 32
4521 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4522 ? "addiu" : "daddiu"),
4523 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4524 /* FIXME: If add_number is 0, and there was no base
4525 register, the external symbol case ended with a load,
4526 so if the symbol turns out to not be external, and
4527 the next instruction uses tempreg, an unnecessary nop
4528 will be inserted. */
4534 /* We must add in the base register now, as in the
4535 external symbol case. */
4536 assert (tempreg
== AT
);
4537 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4539 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4540 ((bfd_arch_bits_per_address (stdoutput
) == 32
4541 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4542 ? "addu" : "daddu"),
4543 "d,v,t", treg
, AT
, breg
);
4546 /* We set breg to 0 because we have arranged to add
4547 it in in both cases. */
4551 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4553 macro_build (p
, &icnt
, &expr1
,
4554 ((bfd_arch_bits_per_address (stdoutput
) == 32
4555 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4556 ? "addiu" : "daddiu"),
4557 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4559 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4560 ((bfd_arch_bits_per_address (stdoutput
) == 32
4561 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4562 ? "addu" : "daddu"),
4563 "d,v,t", tempreg
, tempreg
, AT
);
4567 else if (mips_pic
== EMBEDDED_PIC
)
4570 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4572 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4573 ((bfd_arch_bits_per_address (stdoutput
) == 32
4574 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4575 ? "addiu" : "daddiu"),
4576 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4583 ((bfd_arch_bits_per_address (stdoutput
) == 32
4584 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4585 ? "addu" : "daddu"),
4586 "d,v,t", treg
, tempreg
, breg
);
4594 /* The j instruction may not be used in PIC code, since it
4595 requires an absolute address. We convert it to a b
4597 if (mips_pic
== NO_PIC
)
4598 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4600 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4603 /* The jal instructions must be handled as macros because when
4604 generating PIC code they expand to multi-instruction
4605 sequences. Normally they are simple instructions. */
4610 if (mips_pic
== NO_PIC
4611 || mips_pic
== EMBEDDED_PIC
)
4612 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4614 else if (mips_pic
== SVR4_PIC
)
4616 if (sreg
!= PIC_CALL_REG
)
4617 as_warn (_("MIPS PIC call to register other than $25"));
4619 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4621 if (mips_cprestore_offset
< 0)
4622 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4625 expr1
.X_add_number
= mips_cprestore_offset
;
4626 macro_build ((char *) NULL
, &icnt
, &expr1
,
4627 ((bfd_arch_bits_per_address (stdoutput
) == 32
4628 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4630 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4639 if (mips_pic
== NO_PIC
)
4640 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4641 else if (mips_pic
== SVR4_PIC
)
4643 /* If this is a reference to an external symbol, and we are
4644 using a small GOT, we want
4645 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4649 lw $gp,cprestore($sp)
4650 The cprestore value is set using the .cprestore
4651 pseudo-op. If we are using a big GOT, we want
4652 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4654 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4658 lw $gp,cprestore($sp)
4659 If the symbol is not external, we want
4660 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4662 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4665 lw $gp,cprestore($sp) */
4669 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4670 ((bfd_arch_bits_per_address (stdoutput
) == 32
4671 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4673 "t,o(b)", PIC_CALL_REG
,
4674 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4677 p
= frag_var (rs_machine_dependent
, 4, 0,
4678 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4679 offset_expr
.X_add_symbol
, (offsetT
) 0,
4686 if (reg_needs_delay (GP
))
4690 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4691 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4693 ((bfd_arch_bits_per_address (stdoutput
) == 32
4694 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4695 ? "addu" : "daddu"),
4696 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4697 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4698 ((bfd_arch_bits_per_address (stdoutput
) == 32
4699 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4701 "t,o(b)", PIC_CALL_REG
,
4702 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4703 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4705 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4706 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4708 offset_expr
.X_add_symbol
, (offsetT
) 0,
4712 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4715 macro_build (p
, &icnt
, &offset_expr
,
4716 ((bfd_arch_bits_per_address (stdoutput
) == 32
4717 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4719 "t,o(b)", PIC_CALL_REG
,
4720 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4722 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4725 macro_build (p
, &icnt
, &offset_expr
,
4726 ((bfd_arch_bits_per_address (stdoutput
) == 32
4727 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4728 ? "addiu" : "daddiu"),
4729 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4730 (int) BFD_RELOC_LO16
);
4731 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4732 "jalr", "s", PIC_CALL_REG
);
4733 if (mips_cprestore_offset
< 0)
4734 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4737 if (mips_opts
.noreorder
)
4738 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4740 expr1
.X_add_number
= mips_cprestore_offset
;
4741 macro_build ((char *) NULL
, &icnt
, &expr1
,
4742 ((bfd_arch_bits_per_address (stdoutput
) == 32
4743 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4745 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4749 else if (mips_pic
== EMBEDDED_PIC
)
4751 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4752 /* The linker may expand the call to a longer sequence which
4753 uses $at, so we must break rather than return. */
4778 /* Itbl support may require additional care here. */
4783 /* Itbl support may require additional care here. */
4788 /* Itbl support may require additional care here. */
4793 /* Itbl support may require additional care here. */
4805 if (mips_cpu
== CPU_R4650
)
4807 as_bad (_("opcode not supported on this processor"));
4811 /* Itbl support may require additional care here. */
4816 /* Itbl support may require additional care here. */
4821 /* Itbl support may require additional care here. */
4841 if (breg
== treg
|| coproc
|| lr
)
4863 /* Itbl support may require additional care here. */
4868 /* Itbl support may require additional care here. */
4873 /* Itbl support may require additional care here. */
4878 /* Itbl support may require additional care here. */
4894 if (mips_cpu
== CPU_R4650
)
4896 as_bad (_("opcode not supported on this processor"));
4901 /* Itbl support may require additional care here. */
4905 /* Itbl support may require additional care here. */
4910 /* Itbl support may require additional care here. */
4922 /* Itbl support may require additional care here. */
4923 if (mask
== M_LWC1_AB
4924 || mask
== M_SWC1_AB
4925 || mask
== M_LDC1_AB
4926 || mask
== M_SDC1_AB
4935 if (offset_expr
.X_op
!= O_constant
4936 && offset_expr
.X_op
!= O_symbol
)
4938 as_bad (_("expression too complex"));
4939 offset_expr
.X_op
= O_constant
;
4942 /* A constant expression in PIC code can be handled just as it
4943 is in non PIC code. */
4944 if (mips_pic
== NO_PIC
4945 || offset_expr
.X_op
== O_constant
)
4947 /* If this is a reference to a GP relative symbol, and there
4948 is no base register, we want
4949 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4950 Otherwise, if there is no base register, we want
4951 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4952 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4953 If we have a constant, we need two instructions anyhow,
4954 so we always use the latter form.
4956 If we have a base register, and this is a reference to a
4957 GP relative symbol, we want
4958 addu $tempreg,$breg,$gp
4959 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4961 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4962 addu $tempreg,$tempreg,$breg
4963 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4964 With a constant we always use the latter case. */
4967 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4968 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4973 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4974 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4975 p
= frag_var (rs_machine_dependent
, 8, 0,
4976 RELAX_ENCODE (4, 8, 0, 4, 0,
4977 (mips_opts
.warn_about_macros
4979 && mips_opts
.noat
))),
4980 offset_expr
.X_add_symbol
, (offsetT
) 0,
4984 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4987 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4988 (int) BFD_RELOC_LO16
, tempreg
);
4992 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4993 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4999 ((bfd_arch_bits_per_address (stdoutput
) == 32
5000 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5001 ? "addu" : "daddu"),
5002 "d,v,t", tempreg
, breg
, GP
);
5003 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5004 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5005 p
= frag_var (rs_machine_dependent
, 12, 0,
5006 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5007 offset_expr
.X_add_symbol
, (offsetT
) 0,
5010 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5013 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5014 ((bfd_arch_bits_per_address (stdoutput
) == 32
5015 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5016 ? "addu" : "daddu"),
5017 "d,v,t", tempreg
, tempreg
, breg
);
5020 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5021 (int) BFD_RELOC_LO16
, tempreg
);
5024 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5026 /* If this is a reference to an external symbol, we want
5027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5029 <op> $treg,0($tempreg)
5031 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5033 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5034 <op> $treg,0($tempreg)
5035 If there is a base register, we add it to $tempreg before
5036 the <op>. If there is a constant, we stick it in the
5037 <op> instruction. We don't handle constants larger than
5038 16 bits, because we have no way to load the upper 16 bits
5039 (actually, we could handle them for the subset of cases
5040 in which we are not using $at). */
5041 assert (offset_expr
.X_op
== O_symbol
);
5042 expr1
.X_add_number
= offset_expr
.X_add_number
;
5043 offset_expr
.X_add_number
= 0;
5044 if (expr1
.X_add_number
< -0x8000
5045 || expr1
.X_add_number
>= 0x8000)
5046 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5048 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5049 ((bfd_arch_bits_per_address (stdoutput
) == 32
5050 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5052 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5053 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5054 p
= frag_var (rs_machine_dependent
, 4, 0,
5055 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5056 offset_expr
.X_add_symbol
, (offsetT
) 0,
5058 macro_build (p
, &icnt
, &offset_expr
,
5059 ((bfd_arch_bits_per_address (stdoutput
) == 32
5060 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5061 ? "addiu" : "daddiu"),
5062 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5064 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5065 ((bfd_arch_bits_per_address (stdoutput
) == 32
5066 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5067 ? "addu" : "daddu"),
5068 "d,v,t", tempreg
, tempreg
, breg
);
5069 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5070 (int) BFD_RELOC_LO16
, tempreg
);
5072 else if (mips_pic
== SVR4_PIC
)
5076 /* If this is a reference to an external symbol, we want
5077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5078 addu $tempreg,$tempreg,$gp
5079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5080 <op> $treg,0($tempreg)
5082 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5084 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5085 <op> $treg,0($tempreg)
5086 If there is a base register, we add it to $tempreg before
5087 the <op>. If there is a constant, we stick it in the
5088 <op> instruction. We don't handle constants larger than
5089 16 bits, because we have no way to load the upper 16 bits
5090 (actually, we could handle them for the subset of cases
5091 in which we are not using $at). */
5092 assert (offset_expr
.X_op
== O_symbol
);
5093 expr1
.X_add_number
= offset_expr
.X_add_number
;
5094 offset_expr
.X_add_number
= 0;
5095 if (expr1
.X_add_number
< -0x8000
5096 || expr1
.X_add_number
>= 0x8000)
5097 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5098 if (reg_needs_delay (GP
))
5103 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5104 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5105 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5106 ((bfd_arch_bits_per_address (stdoutput
) == 32
5107 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5108 ? "addu" : "daddu"),
5109 "d,v,t", tempreg
, tempreg
, GP
);
5110 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5111 ((bfd_arch_bits_per_address (stdoutput
) == 32
5112 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5114 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5116 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5117 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5118 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5121 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5124 macro_build (p
, &icnt
, &offset_expr
,
5125 ((bfd_arch_bits_per_address (stdoutput
) == 32
5126 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5128 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5130 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5132 macro_build (p
, &icnt
, &offset_expr
,
5133 ((bfd_arch_bits_per_address (stdoutput
) == 32
5134 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5135 ? "addiu" : "daddiu"),
5136 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5139 ((bfd_arch_bits_per_address (stdoutput
) == 32
5140 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5141 ? "addu" : "daddu"),
5142 "d,v,t", tempreg
, tempreg
, breg
);
5143 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5144 (int) BFD_RELOC_LO16
, tempreg
);
5146 else if (mips_pic
== EMBEDDED_PIC
)
5148 /* If there is no base register, we want
5149 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5150 If there is a base register, we want
5151 addu $tempreg,$breg,$gp
5152 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5154 assert (offset_expr
.X_op
== O_symbol
);
5157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5158 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5163 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5164 ((bfd_arch_bits_per_address (stdoutput
) == 32
5165 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5166 ? "addu" : "daddu"),
5167 "d,v,t", tempreg
, breg
, GP
);
5168 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5169 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5182 load_register (&icnt
, treg
, &imm_expr
, 0);
5186 load_register (&icnt
, treg
, &imm_expr
, 1);
5190 if (imm_expr
.X_op
== O_constant
)
5192 load_register (&icnt
, AT
, &imm_expr
, 0);
5193 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5194 "mtc1", "t,G", AT
, treg
);
5199 assert (offset_expr
.X_op
== O_symbol
5200 && strcmp (segment_name (S_GET_SEGMENT
5201 (offset_expr
.X_add_symbol
)),
5203 && offset_expr
.X_add_number
== 0);
5204 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5205 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5210 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5211 the entire value, and in mips1 mode it is the high order 32
5212 bits of the value and the low order 32 bits are either zero
5213 or in offset_expr. */
5214 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5216 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5217 load_register (&icnt
, treg
, &imm_expr
, 1);
5222 if (target_big_endian
)
5234 load_register (&icnt
, hreg
, &imm_expr
, 0);
5237 if (offset_expr
.X_op
== O_absent
)
5238 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5242 assert (offset_expr
.X_op
== O_constant
);
5243 load_register (&icnt
, lreg
, &offset_expr
, 0);
5250 /* We know that sym is in the .rdata section. First we get the
5251 upper 16 bits of the address. */
5252 if (mips_pic
== NO_PIC
)
5254 /* FIXME: This won't work for a 64 bit address. */
5255 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5257 else if (mips_pic
== SVR4_PIC
)
5259 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5260 ((bfd_arch_bits_per_address (stdoutput
) == 32
5261 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5263 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5265 else if (mips_pic
== EMBEDDED_PIC
)
5267 /* For embedded PIC we pick up the entire address off $gp in
5268 a single instruction. */
5269 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5270 ((bfd_arch_bits_per_address (stdoutput
) == 32
5271 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5272 ? "addiu" : "daddiu"),
5273 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5274 offset_expr
.X_op
= O_constant
;
5275 offset_expr
.X_add_number
= 0;
5280 /* Now we load the register(s). */
5281 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5283 treg
, (int) BFD_RELOC_LO16
, AT
);
5286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5287 treg
, (int) BFD_RELOC_LO16
, AT
);
5290 /* FIXME: How in the world do we deal with the possible
5292 offset_expr
.X_add_number
+= 4;
5293 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5294 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5298 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5299 does not become a variant frag. */
5300 frag_wane (frag_now
);
5306 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5307 the entire value, and in mips1 mode it is the high order 32
5308 bits of the value and the low order 32 bits are either zero
5309 or in offset_expr. */
5310 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5312 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5313 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5315 "dmtc1", "t,S", AT
, treg
);
5318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5319 "mtc1", "t,G", AT
, treg
+ 1);
5320 if (offset_expr
.X_op
== O_absent
)
5321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5322 "mtc1", "t,G", 0, treg
);
5325 assert (offset_expr
.X_op
== O_constant
);
5326 load_register (&icnt
, AT
, &offset_expr
, 0);
5327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5328 "mtc1", "t,G", AT
, treg
);
5334 assert (offset_expr
.X_op
== O_symbol
5335 && offset_expr
.X_add_number
== 0);
5336 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5337 if (strcmp (s
, ".lit8") == 0)
5339 if (mips_opts
.isa
!= ISA_MIPS1
)
5341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5342 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5346 r
= BFD_RELOC_MIPS_LITERAL
;
5351 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5352 if (mips_pic
== SVR4_PIC
)
5353 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5354 ((bfd_arch_bits_per_address (stdoutput
) == 32
5355 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5357 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5360 /* FIXME: This won't work for a 64 bit address. */
5361 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5364 if (mips_opts
.isa
!= ISA_MIPS1
)
5366 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5367 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5369 /* To avoid confusion in tc_gen_reloc, we must ensure
5370 that this does not become a variant frag. */
5371 frag_wane (frag_now
);
5382 if (mips_cpu
== CPU_R4650
)
5384 as_bad (_("opcode not supported on this processor"));
5387 /* Even on a big endian machine $fn comes before $fn+1. We have
5388 to adjust when loading from memory. */
5391 assert (mips_opts
.isa
== ISA_MIPS1
);
5392 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5393 target_big_endian
? treg
+ 1 : treg
,
5395 /* FIXME: A possible overflow which I don't know how to deal
5397 offset_expr
.X_add_number
+= 4;
5398 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5399 target_big_endian
? treg
: treg
+ 1,
5402 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5403 does not become a variant frag. */
5404 frag_wane (frag_now
);
5413 * The MIPS assembler seems to check for X_add_number not
5414 * being double aligned and generating:
5417 * addiu at,at,%lo(foo+1)
5420 * But, the resulting address is the same after relocation so why
5421 * generate the extra instruction?
5423 if (mips_cpu
== CPU_R4650
)
5425 as_bad (_("opcode not supported on this processor"));
5428 /* Itbl support may require additional care here. */
5430 if (mips_opts
.isa
!= ISA_MIPS1
)
5441 if (mips_cpu
== CPU_R4650
)
5443 as_bad (_("opcode not supported on this processor"));
5447 if (mips_opts
.isa
!= ISA_MIPS1
)
5455 /* Itbl support may require additional care here. */
5460 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5471 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5481 if (offset_expr
.X_op
!= O_symbol
5482 && offset_expr
.X_op
!= O_constant
)
5484 as_bad (_("expression too complex"));
5485 offset_expr
.X_op
= O_constant
;
5488 /* Even on a big endian machine $fn comes before $fn+1. We have
5489 to adjust when loading from memory. We set coproc if we must
5490 load $fn+1 first. */
5491 /* Itbl support may require additional care here. */
5492 if (! target_big_endian
)
5495 if (mips_pic
== NO_PIC
5496 || offset_expr
.X_op
== O_constant
)
5498 /* If this is a reference to a GP relative symbol, we want
5499 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5500 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5501 If we have a base register, we use this
5503 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5504 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5505 If this is not a GP relative symbol, we want
5506 lui $at,<sym> (BFD_RELOC_HI16_S)
5507 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5508 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5509 If there is a base register, we add it to $at after the
5510 lui instruction. If there is a constant, we always use
5512 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5513 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5532 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5533 ((bfd_arch_bits_per_address (stdoutput
) == 32
5534 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5535 ? "addu" : "daddu"),
5536 "d,v,t", AT
, breg
, GP
);
5542 /* Itbl support may require additional care here. */
5543 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5544 coproc
? treg
+ 1 : treg
,
5545 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5546 offset_expr
.X_add_number
+= 4;
5548 /* Set mips_optimize to 2 to avoid inserting an
5550 hold_mips_optimize
= mips_optimize
;
5552 /* Itbl support may require additional care here. */
5553 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5554 coproc
? treg
: treg
+ 1,
5555 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5556 mips_optimize
= hold_mips_optimize
;
5558 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5559 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5560 used_at
&& mips_opts
.noat
),
5561 offset_expr
.X_add_symbol
, (offsetT
) 0,
5564 /* We just generated two relocs. When tc_gen_reloc
5565 handles this case, it will skip the first reloc and
5566 handle the second. The second reloc already has an
5567 extra addend of 4, which we added above. We must
5568 subtract it out, and then subtract another 4 to make
5569 the first reloc come out right. The second reloc
5570 will come out right because we are going to add 4 to
5571 offset_expr when we build its instruction below.
5573 If we have a symbol, then we don't want to include
5574 the offset, because it will wind up being included
5575 when we generate the reloc. */
5577 if (offset_expr
.X_op
== O_constant
)
5578 offset_expr
.X_add_number
-= 8;
5581 offset_expr
.X_add_number
= -4;
5582 offset_expr
.X_op
= O_constant
;
5585 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5590 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5591 ((bfd_arch_bits_per_address (stdoutput
) == 32
5592 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5593 ? "addu" : "daddu"),
5594 "d,v,t", AT
, breg
, AT
);
5598 /* Itbl support may require additional care here. */
5599 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5600 coproc
? treg
+ 1 : treg
,
5601 (int) BFD_RELOC_LO16
, AT
);
5604 /* FIXME: How do we handle overflow here? */
5605 offset_expr
.X_add_number
+= 4;
5606 /* Itbl support may require additional care here. */
5607 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5608 coproc
? treg
: treg
+ 1,
5609 (int) BFD_RELOC_LO16
, AT
);
5611 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5615 /* If this is a reference to an external symbol, we want
5616 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5621 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5623 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5624 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5625 If there is a base register we add it to $at before the
5626 lwc1 instructions. If there is a constant we include it
5627 in the lwc1 instructions. */
5629 expr1
.X_add_number
= offset_expr
.X_add_number
;
5630 offset_expr
.X_add_number
= 0;
5631 if (expr1
.X_add_number
< -0x8000
5632 || expr1
.X_add_number
>= 0x8000 - 4)
5633 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5638 frag_grow (24 + off
);
5639 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5640 ((bfd_arch_bits_per_address (stdoutput
) == 32
5641 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5643 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5647 ((bfd_arch_bits_per_address (stdoutput
) == 32
5648 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5649 ? "addu" : "daddu"),
5650 "d,v,t", AT
, breg
, AT
);
5651 /* Itbl support may require additional care here. */
5652 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5653 coproc
? treg
+ 1 : treg
,
5654 (int) BFD_RELOC_LO16
, AT
);
5655 expr1
.X_add_number
+= 4;
5657 /* Set mips_optimize to 2 to avoid inserting an undesired
5659 hold_mips_optimize
= mips_optimize
;
5661 /* Itbl support may require additional care here. */
5662 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5663 coproc
? treg
: treg
+ 1,
5664 (int) BFD_RELOC_LO16
, AT
);
5665 mips_optimize
= hold_mips_optimize
;
5667 (void) frag_var (rs_machine_dependent
, 0, 0,
5668 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5669 offset_expr
.X_add_symbol
, (offsetT
) 0,
5672 else if (mips_pic
== SVR4_PIC
)
5676 /* If this is a reference to an external symbol, we want
5677 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5679 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5684 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5686 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5687 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5688 If there is a base register we add it to $at before the
5689 lwc1 instructions. If there is a constant we include it
5690 in the lwc1 instructions. */
5692 expr1
.X_add_number
= offset_expr
.X_add_number
;
5693 offset_expr
.X_add_number
= 0;
5694 if (expr1
.X_add_number
< -0x8000
5695 || expr1
.X_add_number
>= 0x8000 - 4)
5696 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5697 if (reg_needs_delay (GP
))
5706 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5707 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5708 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5709 ((bfd_arch_bits_per_address (stdoutput
) == 32
5710 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5711 ? "addu" : "daddu"),
5712 "d,v,t", AT
, AT
, GP
);
5713 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5714 ((bfd_arch_bits_per_address (stdoutput
) == 32
5715 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5717 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5718 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5720 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5721 ((bfd_arch_bits_per_address (stdoutput
) == 32
5722 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5723 ? "addu" : "daddu"),
5724 "d,v,t", AT
, breg
, AT
);
5725 /* Itbl support may require additional care here. */
5726 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5727 coproc
? treg
+ 1 : treg
,
5728 (int) BFD_RELOC_LO16
, AT
);
5729 expr1
.X_add_number
+= 4;
5731 /* Set mips_optimize to 2 to avoid inserting an undesired
5733 hold_mips_optimize
= mips_optimize
;
5735 /* Itbl support may require additional care here. */
5736 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5737 coproc
? treg
: treg
+ 1,
5738 (int) BFD_RELOC_LO16
, AT
);
5739 mips_optimize
= hold_mips_optimize
;
5740 expr1
.X_add_number
-= 4;
5742 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5743 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5744 8 + gpdel
+ off
, 1, 0),
5745 offset_expr
.X_add_symbol
, (offsetT
) 0,
5749 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5752 macro_build (p
, &icnt
, &offset_expr
,
5753 ((bfd_arch_bits_per_address (stdoutput
) == 32
5754 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5756 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5758 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5762 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5763 ((bfd_arch_bits_per_address (stdoutput
) == 32
5764 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5765 ? "addu" : "daddu"),
5766 "d,v,t", AT
, breg
, AT
);
5769 /* Itbl support may require additional care here. */
5770 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5771 coproc
? treg
+ 1 : treg
,
5772 (int) BFD_RELOC_LO16
, AT
);
5774 expr1
.X_add_number
+= 4;
5776 /* Set mips_optimize to 2 to avoid inserting an undesired
5778 hold_mips_optimize
= mips_optimize
;
5780 /* Itbl support may require additional care here. */
5781 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5782 coproc
? treg
: treg
+ 1,
5783 (int) BFD_RELOC_LO16
, AT
);
5784 mips_optimize
= hold_mips_optimize
;
5786 else if (mips_pic
== EMBEDDED_PIC
)
5788 /* If there is no base register, we use
5789 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5790 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5791 If we have a base register, we use
5793 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5794 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5804 ((bfd_arch_bits_per_address (stdoutput
) == 32
5805 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5806 ? "addu" : "daddu"),
5807 "d,v,t", AT
, breg
, GP
);
5812 /* Itbl support may require additional care here. */
5813 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5814 coproc
? treg
+ 1 : treg
,
5815 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5816 offset_expr
.X_add_number
+= 4;
5817 /* Itbl support may require additional care here. */
5818 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5819 coproc
? treg
: treg
+ 1,
5820 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5836 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5837 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5838 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5839 (int) BFD_RELOC_LO16
, breg
);
5840 offset_expr
.X_add_number
+= 4;
5841 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5842 (int) BFD_RELOC_LO16
, breg
);
5845 /* New code added to support COPZ instructions.
5846 This code builds table entries out of the macros in mip_opcodes.
5847 R4000 uses interlocks to handle coproc delays.
5848 Other chips (like the R3000) require nops to be inserted for delays.
5850 FIXME: Currently, we require that the user handle delays.
5851 In order to fill delay slots for non-interlocked chips,
5852 we must have a way to specify delays based on the coprocessor.
5853 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5854 What are the side-effects of the cop instruction?
5855 What cache support might we have and what are its effects?
5856 Both coprocessor & memory require delays. how long???
5857 What registers are read/set/modified?
5859 If an itbl is provided to interpret cop instructions,
5860 this knowledge can be encoded in the itbl spec. */
5874 /* For now we just do C (same as Cz). The parameter will be
5875 stored in insn_opcode by mips_ip. */
5876 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5880 #ifdef LOSING_COMPILER
5882 /* Try and see if this is a new itbl instruction.
5883 This code builds table entries out of the macros in mip_opcodes.
5884 FIXME: For now we just assemble the expression and pass it's
5885 value along as a 32-bit immediate.
5886 We may want to have the assembler assemble this value,
5887 so that we gain the assembler's knowledge of delay slots,
5889 Would it be more efficient to use mask (id) here? */
5890 if (itbl_have_entries
5891 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5893 s
= ip
->insn_mo
->name
;
5895 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5896 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5903 as_warn (_("Macro used $at after \".set noat\""));
5908 struct mips_cl_insn
*ip
;
5910 register int treg
, sreg
, dreg
, breg
;
5926 bfd_reloc_code_real_type r
;
5929 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5930 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5931 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5932 mask
= ip
->insn_mo
->mask
;
5934 expr1
.X_op
= O_constant
;
5935 expr1
.X_op_symbol
= NULL
;
5936 expr1
.X_add_symbol
= NULL
;
5937 expr1
.X_add_number
= 1;
5941 #endif /* LOSING_COMPILER */
5946 macro_build ((char *) NULL
, &icnt
, NULL
,
5947 dbl
? "dmultu" : "multu",
5949 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5955 /* The MIPS assembler some times generates shifts and adds. I'm
5956 not trying to be that fancy. GCC should do this for us
5958 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5959 macro_build ((char *) NULL
, &icnt
, NULL
,
5960 dbl
? "dmult" : "mult",
5962 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5975 mips_emit_delays (true);
5976 ++mips_opts
.noreorder
;
5977 mips_any_noreorder
= 1;
5979 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5980 macro_build ((char *) NULL
, &icnt
, NULL
,
5981 dbl
? "dmult" : "mult",
5982 "s,t", sreg
, imm
? AT
: treg
);
5983 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5984 macro_build ((char *) NULL
, &icnt
, NULL
,
5985 dbl
? "dsra32" : "sra",
5986 "d,w,<", dreg
, dreg
, 31);
5987 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5989 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5992 expr1
.X_add_number
= 8;
5993 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5994 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5997 --mips_opts
.noreorder
;
5998 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6011 mips_emit_delays (true);
6012 ++mips_opts
.noreorder
;
6013 mips_any_noreorder
= 1;
6015 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6016 macro_build ((char *) NULL
, &icnt
, NULL
,
6017 dbl
? "dmultu" : "multu",
6018 "s,t", sreg
, imm
? AT
: treg
);
6019 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6020 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6022 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6025 expr1
.X_add_number
= 8;
6026 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6028 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6030 --mips_opts
.noreorder
;
6034 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6035 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6036 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6038 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6042 if (imm_expr
.X_op
!= O_constant
)
6043 as_bad (_("rotate count too large"));
6044 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6045 (int) (imm_expr
.X_add_number
& 0x1f));
6046 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6047 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6048 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6052 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6053 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6054 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6056 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6060 if (imm_expr
.X_op
!= O_constant
)
6061 as_bad (_("rotate count too large"));
6062 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6063 (int) (imm_expr
.X_add_number
& 0x1f));
6064 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6065 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6066 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6070 if (mips_cpu
== CPU_R4650
)
6072 as_bad (_("opcode not supported on this processor"));
6075 assert (mips_opts
.isa
== ISA_MIPS1
);
6076 /* Even on a big endian machine $fn comes before $fn+1. We have
6077 to adjust when storing to memory. */
6078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6079 target_big_endian
? treg
+ 1 : treg
,
6080 (int) BFD_RELOC_LO16
, breg
);
6081 offset_expr
.X_add_number
+= 4;
6082 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6083 target_big_endian
? treg
: treg
+ 1,
6084 (int) BFD_RELOC_LO16
, breg
);
6089 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6090 treg
, (int) BFD_RELOC_LO16
);
6092 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6093 sreg
, (int) BFD_RELOC_LO16
);
6096 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6098 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6099 dreg
, (int) BFD_RELOC_LO16
);
6104 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6106 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6107 sreg
, (int) BFD_RELOC_LO16
);
6112 as_warn (_("Instruction %s: result is always false"),
6114 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6117 if (imm_expr
.X_op
== O_constant
6118 && imm_expr
.X_add_number
>= 0
6119 && imm_expr
.X_add_number
< 0x10000)
6121 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6122 sreg
, (int) BFD_RELOC_LO16
);
6125 else if (imm_expr
.X_op
== O_constant
6126 && imm_expr
.X_add_number
> -0x8000
6127 && imm_expr
.X_add_number
< 0)
6129 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6130 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6131 ((bfd_arch_bits_per_address (stdoutput
) == 32
6132 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6133 ? "addiu" : "daddiu"),
6134 "t,r,j", dreg
, sreg
,
6135 (int) BFD_RELOC_LO16
);
6140 load_register (&icnt
, AT
, &imm_expr
, 0);
6141 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6145 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6146 (int) BFD_RELOC_LO16
);
6151 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6157 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6158 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6159 (int) BFD_RELOC_LO16
);
6162 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6164 if (imm_expr
.X_op
== O_constant
6165 && imm_expr
.X_add_number
>= -0x8000
6166 && imm_expr
.X_add_number
< 0x8000)
6168 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6169 mask
== M_SGE_I
? "slti" : "sltiu",
6170 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6175 load_register (&icnt
, AT
, &imm_expr
, 0);
6176 macro_build ((char *) NULL
, &icnt
, NULL
,
6177 mask
== M_SGE_I
? "slt" : "sltu",
6178 "d,v,t", dreg
, sreg
, AT
);
6181 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6182 (int) BFD_RELOC_LO16
);
6187 case M_SGT
: /* sreg > treg <==> treg < sreg */
6193 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6196 case M_SGT_I
: /* sreg > I <==> I < sreg */
6202 load_register (&icnt
, AT
, &imm_expr
, 0);
6203 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6206 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6212 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6213 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6214 (int) BFD_RELOC_LO16
);
6217 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6223 load_register (&icnt
, AT
, &imm_expr
, 0);
6224 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6225 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6226 (int) BFD_RELOC_LO16
);
6230 if (imm_expr
.X_op
== O_constant
6231 && imm_expr
.X_add_number
>= -0x8000
6232 && imm_expr
.X_add_number
< 0x8000)
6234 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6235 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6238 load_register (&icnt
, AT
, &imm_expr
, 0);
6239 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6243 if (imm_expr
.X_op
== O_constant
6244 && imm_expr
.X_add_number
>= -0x8000
6245 && imm_expr
.X_add_number
< 0x8000)
6247 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6248 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6251 load_register (&icnt
, AT
, &imm_expr
, 0);
6252 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6258 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6261 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6265 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6267 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6273 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6275 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6281 as_warn (_("Instruction %s: result is always true"),
6283 macro_build ((char *) NULL
, &icnt
, &expr1
,
6284 ((bfd_arch_bits_per_address (stdoutput
) == 32
6285 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6286 ? "addiu" : "daddiu"),
6287 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6290 if (imm_expr
.X_op
== O_constant
6291 && imm_expr
.X_add_number
>= 0
6292 && imm_expr
.X_add_number
< 0x10000)
6294 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6295 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6298 else if (imm_expr
.X_op
== O_constant
6299 && imm_expr
.X_add_number
> -0x8000
6300 && imm_expr
.X_add_number
< 0)
6302 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6303 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6304 ((bfd_arch_bits_per_address (stdoutput
) == 32
6305 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6306 ? "addiu" : "daddiu"),
6307 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6312 load_register (&icnt
, AT
, &imm_expr
, 0);
6313 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6317 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6325 if (imm_expr
.X_op
== O_constant
6326 && imm_expr
.X_add_number
> -0x8000
6327 && imm_expr
.X_add_number
<= 0x8000)
6329 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6330 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6331 dbl
? "daddi" : "addi",
6332 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6335 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6336 macro_build ((char *) NULL
, &icnt
, NULL
,
6337 dbl
? "dsub" : "sub",
6338 "d,v,t", dreg
, sreg
, AT
);
6344 if (imm_expr
.X_op
== O_constant
6345 && imm_expr
.X_add_number
> -0x8000
6346 && imm_expr
.X_add_number
<= 0x8000)
6348 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6349 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6350 dbl
? "daddiu" : "addiu",
6351 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6354 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6355 macro_build ((char *) NULL
, &icnt
, NULL
,
6356 dbl
? "dsubu" : "subu",
6357 "d,v,t", dreg
, sreg
, AT
);
6378 load_register (&icnt
, AT
, &imm_expr
, 0);
6379 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6384 assert (mips_opts
.isa
== ISA_MIPS1
);
6385 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6386 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6389 * Is the double cfc1 instruction a bug in the mips assembler;
6390 * or is there a reason for it?
6392 mips_emit_delays (true);
6393 ++mips_opts
.noreorder
;
6394 mips_any_noreorder
= 1;
6395 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6396 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6397 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6398 expr1
.X_add_number
= 3;
6399 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6400 (int) BFD_RELOC_LO16
);
6401 expr1
.X_add_number
= 2;
6402 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6403 (int) BFD_RELOC_LO16
);
6404 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6405 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6406 macro_build ((char *) NULL
, &icnt
, NULL
,
6407 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6408 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6409 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6410 --mips_opts
.noreorder
;
6419 if (offset_expr
.X_add_number
>= 0x7fff)
6420 as_bad (_("operand overflow"));
6421 /* avoid load delay */
6422 if (! target_big_endian
)
6423 offset_expr
.X_add_number
+= 1;
6424 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6425 (int) BFD_RELOC_LO16
, breg
);
6426 if (! target_big_endian
)
6427 offset_expr
.X_add_number
-= 1;
6429 offset_expr
.X_add_number
+= 1;
6430 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6431 (int) BFD_RELOC_LO16
, breg
);
6432 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6433 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6446 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6447 as_bad (_("operand overflow"));
6448 if (! target_big_endian
)
6449 offset_expr
.X_add_number
+= off
;
6450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6451 (int) BFD_RELOC_LO16
, breg
);
6452 if (! target_big_endian
)
6453 offset_expr
.X_add_number
-= off
;
6455 offset_expr
.X_add_number
+= off
;
6456 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6457 (int) BFD_RELOC_LO16
, breg
);
6470 load_address (&icnt
, AT
, &offset_expr
);
6472 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6473 ((bfd_arch_bits_per_address (stdoutput
) == 32
6474 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6475 ? "addu" : "daddu"),
6476 "d,v,t", AT
, AT
, breg
);
6477 if (! target_big_endian
)
6478 expr1
.X_add_number
= off
;
6480 expr1
.X_add_number
= 0;
6481 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6482 (int) BFD_RELOC_LO16
, AT
);
6483 if (! target_big_endian
)
6484 expr1
.X_add_number
= 0;
6486 expr1
.X_add_number
= off
;
6487 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6488 (int) BFD_RELOC_LO16
, AT
);
6493 load_address (&icnt
, AT
, &offset_expr
);
6495 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6496 ((bfd_arch_bits_per_address (stdoutput
) == 32
6497 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6498 ? "addu" : "daddu"),
6499 "d,v,t", AT
, AT
, breg
);
6500 if (target_big_endian
)
6501 expr1
.X_add_number
= 0;
6502 macro_build ((char *) NULL
, &icnt
, &expr1
,
6503 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6504 (int) BFD_RELOC_LO16
, AT
);
6505 if (target_big_endian
)
6506 expr1
.X_add_number
= 1;
6508 expr1
.X_add_number
= 0;
6509 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6510 (int) BFD_RELOC_LO16
, AT
);
6511 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6513 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6518 if (offset_expr
.X_add_number
>= 0x7fff)
6519 as_bad (_("operand overflow"));
6520 if (target_big_endian
)
6521 offset_expr
.X_add_number
+= 1;
6522 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6523 (int) BFD_RELOC_LO16
, breg
);
6524 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6525 if (target_big_endian
)
6526 offset_expr
.X_add_number
-= 1;
6528 offset_expr
.X_add_number
+= 1;
6529 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6530 (int) BFD_RELOC_LO16
, breg
);
6543 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6544 as_bad (_("operand overflow"));
6545 if (! target_big_endian
)
6546 offset_expr
.X_add_number
+= off
;
6547 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6548 (int) BFD_RELOC_LO16
, breg
);
6549 if (! target_big_endian
)
6550 offset_expr
.X_add_number
-= off
;
6552 offset_expr
.X_add_number
+= off
;
6553 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6554 (int) BFD_RELOC_LO16
, breg
);
6567 load_address (&icnt
, AT
, &offset_expr
);
6569 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6570 ((bfd_arch_bits_per_address (stdoutput
) == 32
6571 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6572 ? "addu" : "daddu"),
6573 "d,v,t", AT
, AT
, breg
);
6574 if (! target_big_endian
)
6575 expr1
.X_add_number
= off
;
6577 expr1
.X_add_number
= 0;
6578 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6579 (int) BFD_RELOC_LO16
, AT
);
6580 if (! target_big_endian
)
6581 expr1
.X_add_number
= 0;
6583 expr1
.X_add_number
= off
;
6584 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6585 (int) BFD_RELOC_LO16
, AT
);
6589 load_address (&icnt
, AT
, &offset_expr
);
6591 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6592 ((bfd_arch_bits_per_address (stdoutput
) == 32
6593 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6594 ? "addu" : "daddu"),
6595 "d,v,t", AT
, AT
, breg
);
6596 if (! target_big_endian
)
6597 expr1
.X_add_number
= 0;
6598 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6599 (int) BFD_RELOC_LO16
, AT
);
6600 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6602 if (! target_big_endian
)
6603 expr1
.X_add_number
= 1;
6605 expr1
.X_add_number
= 0;
6606 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6607 (int) BFD_RELOC_LO16
, AT
);
6608 if (! target_big_endian
)
6609 expr1
.X_add_number
= 0;
6611 expr1
.X_add_number
= 1;
6612 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6613 (int) BFD_RELOC_LO16
, AT
);
6614 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6616 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6621 /* FIXME: Check if this is one of the itbl macros, since they
6622 are added dynamically. */
6623 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6627 as_warn (_("Macro used $at after \".set noat\""));
6630 /* Implement macros in mips16 mode. */
6634 struct mips_cl_insn
*ip
;
6637 int xreg
, yreg
, zreg
, tmp
;
6641 const char *s
, *s2
, *s3
;
6643 mask
= ip
->insn_mo
->mask
;
6645 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6646 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6647 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6651 expr1
.X_op
= O_constant
;
6652 expr1
.X_op_symbol
= NULL
;
6653 expr1
.X_add_symbol
= NULL
;
6654 expr1
.X_add_number
= 1;
6673 mips_emit_delays (true);
6674 ++mips_opts
.noreorder
;
6675 mips_any_noreorder
= 1;
6676 macro_build ((char *) NULL
, &icnt
, NULL
,
6677 dbl
? "ddiv" : "div",
6678 "0,x,y", xreg
, yreg
);
6679 expr1
.X_add_number
= 2;
6680 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6681 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6683 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6684 since that causes an overflow. We should do that as well,
6685 but I don't see how to do the comparisons without a temporary
6687 --mips_opts
.noreorder
;
6688 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6707 mips_emit_delays (true);
6708 ++mips_opts
.noreorder
;
6709 mips_any_noreorder
= 1;
6710 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6711 expr1
.X_add_number
= 2;
6712 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6713 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6714 --mips_opts
.noreorder
;
6715 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6721 macro_build ((char *) NULL
, &icnt
, NULL
,
6722 dbl
? "dmultu" : "multu",
6724 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6732 if (imm_expr
.X_op
!= O_constant
)
6733 as_bad (_("Unsupported large constant"));
6734 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6735 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6736 dbl
? "daddiu" : "addiu",
6737 "y,x,4", yreg
, xreg
);
6741 if (imm_expr
.X_op
!= O_constant
)
6742 as_bad (_("Unsupported large constant"));
6743 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6744 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6749 if (imm_expr
.X_op
!= O_constant
)
6750 as_bad (_("Unsupported large constant"));
6751 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6752 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6775 goto do_reverse_branch
;
6779 goto do_reverse_branch
;
6791 goto do_reverse_branch
;
6802 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6804 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6831 goto do_addone_branch_i
;
6836 goto do_addone_branch_i
;
6851 goto do_addone_branch_i
;
6858 if (imm_expr
.X_op
!= O_constant
)
6859 as_bad (_("Unsupported large constant"));
6860 ++imm_expr
.X_add_number
;
6863 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6864 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6868 expr1
.X_add_number
= 0;
6869 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6871 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6872 "move", "y,X", xreg
, yreg
);
6873 expr1
.X_add_number
= 2;
6874 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6876 "neg", "x,w", xreg
, xreg
);
6880 /* For consistency checking, verify that all bits are specified either
6881 by the match/mask part of the instruction definition, or by the
6884 validate_mips_insn (opc
)
6885 const struct mips_opcode
*opc
;
6887 const char *p
= opc
->args
;
6889 unsigned long used_bits
= opc
->mask
;
6891 if ((used_bits
& opc
->match
) != opc
->match
)
6893 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6894 opc
->name
, opc
->args
);
6897 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6904 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6905 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6907 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
6908 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6909 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6910 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6912 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6913 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
6915 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
6917 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6918 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6919 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6920 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6921 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6922 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6923 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6924 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6925 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6926 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6927 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6929 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6930 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6931 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6932 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6934 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6935 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6936 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6937 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6938 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6939 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6940 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6941 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6942 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6945 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6946 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
6947 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6949 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6950 c
, opc
->name
, opc
->args
);
6954 if (used_bits
!= 0xffffffff)
6956 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6957 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6963 /* This routine assembles an instruction into its binary format. As a
6964 side effect, it sets one of the global variables imm_reloc or
6965 offset_reloc to the type of relocation to do if one of the operands
6966 is an address expression. */
6971 struct mips_cl_insn
*ip
;
6976 struct mips_opcode
*insn
;
6979 unsigned int lastregno
= 0;
6982 int full_opcode_match
= 1;
6986 /* If the instruction contains a '.', we first try to match an instruction
6987 including the '.'. Then we try again without the '.'. */
6989 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
6992 /* If we stopped on whitespace, then replace the whitespace with null for
6993 the call to hash_find. Save the character we replaced just in case we
6994 have to re-parse the instruction. */
6995 if (isspace ((unsigned char) *s
))
7001 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7003 /* If we didn't find the instruction in the opcode table, try again, but
7004 this time with just the instruction up to, but not including the
7008 /* Restore the character we overwrite above (if any). */
7012 /* Scan up to the first '.' or whitespace. */
7013 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7016 /* If we did not find a '.', then we can quit now. */
7019 insn_error
= "unrecognized opcode";
7023 /* Lookup the instruction in the hash table. */
7025 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7027 insn_error
= "unrecognized opcode";
7031 full_opcode_match
= 0;
7039 assert (strcmp (insn
->name
, str
) == 0);
7041 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7046 if (insn
->pinfo
!= INSN_MACRO
)
7048 if (mips_cpu
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7054 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7055 && strcmp (insn
->name
, insn
[1].name
) == 0)
7062 static char buf
[100];
7064 _("opcode not supported on this processor: %s (%s)"),
7065 mips_cpu_to_str (mips_cpu
),
7066 mips_isa_to_str (mips_opts
.isa
));
7074 ip
->insn_opcode
= insn
->match
;
7075 for (args
= insn
->args
;; ++args
)
7081 case '\0': /* end of args */
7094 ip
->insn_opcode
|= lastregno
<< 21;
7099 ip
->insn_opcode
|= lastregno
<< 16;
7103 ip
->insn_opcode
|= lastregno
<< 11;
7109 /* Handle optional base register.
7110 Either the base register is omitted or
7111 we must have a left paren. */
7112 /* This is dependent on the next operand specifier
7113 is a base register specification. */
7114 assert (args
[1] == 'b' || args
[1] == '5'
7115 || args
[1] == '-' || args
[1] == '4');
7119 case ')': /* these must match exactly */
7124 case '<': /* must be at least one digit */
7126 * According to the manual, if the shift amount is greater
7127 * than 31 or less than 0 the the shift amount should be
7128 * mod 32. In reality the mips assembler issues an error.
7129 * We issue a warning and mask out all but the low 5 bits.
7131 my_getExpression (&imm_expr
, s
);
7132 check_absolute_expr (ip
, &imm_expr
);
7133 if ((unsigned long) imm_expr
.X_add_number
> 31)
7135 as_warn (_("Improper shift amount (%ld)"),
7136 (long) imm_expr
.X_add_number
);
7137 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7139 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7140 imm_expr
.X_op
= O_absent
;
7144 case '>': /* shift amount minus 32 */
7145 my_getExpression (&imm_expr
, s
);
7146 check_absolute_expr (ip
, &imm_expr
);
7147 if ((unsigned long) imm_expr
.X_add_number
< 32
7148 || (unsigned long) imm_expr
.X_add_number
> 63)
7150 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7151 imm_expr
.X_op
= O_absent
;
7155 case 'k': /* cache code */
7156 case 'h': /* prefx code */
7157 my_getExpression (&imm_expr
, s
);
7158 check_absolute_expr (ip
, &imm_expr
);
7159 if ((unsigned long) imm_expr
.X_add_number
> 31)
7161 as_warn (_("Invalid value for `%s' (%lu)"),
7163 (unsigned long) imm_expr
.X_add_number
);
7164 imm_expr
.X_add_number
&= 0x1f;
7167 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7169 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7170 imm_expr
.X_op
= O_absent
;
7174 case 'c': /* break code */
7175 my_getExpression (&imm_expr
, s
);
7176 check_absolute_expr (ip
, &imm_expr
);
7177 if ((unsigned) imm_expr
.X_add_number
> 1023)
7179 as_warn (_("Illegal break code (%ld)"),
7180 (long) imm_expr
.X_add_number
);
7181 imm_expr
.X_add_number
&= 0x3ff;
7183 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7184 imm_expr
.X_op
= O_absent
;
7188 case 'q': /* lower break code */
7189 my_getExpression (&imm_expr
, s
);
7190 check_absolute_expr (ip
, &imm_expr
);
7191 if ((unsigned) imm_expr
.X_add_number
> 1023)
7193 as_warn (_("Illegal lower break code (%ld)"),
7194 (long) imm_expr
.X_add_number
);
7195 imm_expr
.X_add_number
&= 0x3ff;
7197 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7198 imm_expr
.X_op
= O_absent
;
7202 case 'B': /* 20-bit syscall/break code. */
7203 my_getExpression (&imm_expr
, s
);
7204 check_absolute_expr (ip
, &imm_expr
);
7205 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7206 as_warn (_("Illegal 20-bit code (%ld)"),
7207 (long) imm_expr
.X_add_number
);
7208 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7209 imm_expr
.X_op
= O_absent
;
7213 case 'C': /* Coprocessor code */
7214 my_getExpression (&imm_expr
, s
);
7215 check_absolute_expr (ip
, &imm_expr
);
7216 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7218 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7219 (long) imm_expr
.X_add_number
);
7220 imm_expr
.X_add_number
&= ((1<<25) - 1);
7222 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7223 imm_expr
.X_op
= O_absent
;
7227 case 'J': /* 19-bit wait code. */
7228 my_getExpression (&imm_expr
, s
);
7229 check_absolute_expr (ip
, &imm_expr
);
7230 if ((unsigned) imm_expr
.X_add_number
> 0x7ffff)
7231 as_warn (_("Illegal 19-bit code (%ld)"),
7232 (long) imm_expr
.X_add_number
);
7233 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7234 imm_expr
.X_op
= O_absent
;
7238 case 'P': /* Performance register */
7239 my_getExpression (&imm_expr
, s
);
7240 check_absolute_expr (ip
, &imm_expr
);
7241 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7243 as_warn (_("Invalidate performance regster (%ld)"),
7244 (long) imm_expr
.X_add_number
);
7245 imm_expr
.X_add_number
&= 1;
7247 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7248 imm_expr
.X_op
= O_absent
;
7252 case 'b': /* base register */
7253 case 'd': /* destination register */
7254 case 's': /* source register */
7255 case 't': /* target register */
7256 case 'r': /* both target and source */
7257 case 'v': /* both dest and source */
7258 case 'w': /* both dest and target */
7259 case 'E': /* coprocessor target register */
7260 case 'G': /* coprocessor destination register */
7261 case 'x': /* ignore register name */
7262 case 'z': /* must be zero register */
7263 case 'U': /* destination register (clo/clz). */
7268 if (isdigit ((unsigned char) s
[1]))
7278 while (isdigit ((unsigned char) *s
));
7280 as_bad (_("Invalid register number (%d)"), regno
);
7282 else if (*args
== 'E' || *args
== 'G')
7286 if (s
[1] == 'f' && s
[2] == 'p')
7291 else if (s
[1] == 's' && s
[2] == 'p')
7296 else if (s
[1] == 'g' && s
[2] == 'p')
7301 else if (s
[1] == 'a' && s
[2] == 't')
7306 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7311 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7316 else if (itbl_have_entries
)
7321 p
= s
+ 1; /* advance past '$' */
7322 n
= itbl_get_field (&p
); /* n is name */
7324 /* See if this is a register defined in an
7326 if (itbl_get_reg_val (n
, &r
))
7328 /* Get_field advances to the start of
7329 the next field, so we need to back
7330 rack to the end of the last field. */
7334 s
= strchr (s
, '\0');
7347 as_warn (_("Used $at without \".set noat\""));
7353 if (c
== 'r' || c
== 'v' || c
== 'w')
7360 /* 'z' only matches $0. */
7361 if (c
== 'z' && regno
!= 0)
7364 /* Now that we have assembled one operand, we use the args string
7365 * to figure out where it goes in the instruction. */
7372 ip
->insn_opcode
|= regno
<< 21;
7376 ip
->insn_opcode
|= regno
<< 11;
7379 ip
->insn_opcode
|= regno
<< 11;
7380 ip
->insn_opcode
|= regno
<< 16;
7385 ip
->insn_opcode
|= regno
<< 16;
7388 /* This case exists because on the r3000 trunc
7389 expands into a macro which requires a gp
7390 register. On the r6000 or r4000 it is
7391 assembled into a single instruction which
7392 ignores the register. Thus the insn version
7393 is MIPS_ISA2 and uses 'x', and the macro
7394 version is MIPS_ISA1 and uses 't'. */
7397 /* This case is for the div instruction, which
7398 acts differently if the destination argument
7399 is $0. This only matches $0, and is checked
7400 outside the switch. */
7403 /* Itbl operand; not yet implemented. FIXME ?? */
7405 /* What about all other operands like 'i', which
7406 can be specified in the opcode table? */
7416 ip
->insn_opcode
|= lastregno
<< 21;
7419 ip
->insn_opcode
|= lastregno
<< 16;
7424 case 'D': /* floating point destination register */
7425 case 'S': /* floating point source register */
7426 case 'T': /* floating point target register */
7427 case 'R': /* floating point source register */
7431 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7441 while (isdigit ((unsigned char) *s
));
7444 as_bad (_("Invalid float register number (%d)"), regno
);
7446 if ((regno
& 1) != 0
7447 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7448 && ! (strcmp (str
, "mtc1") == 0
7449 || strcmp (str
, "mfc1") == 0
7450 || strcmp (str
, "lwc1") == 0
7451 || strcmp (str
, "swc1") == 0
7452 || strcmp (str
, "l.s") == 0
7453 || strcmp (str
, "s.s") == 0))
7454 as_warn (_("Float register should be even, was %d"),
7462 if (c
== 'V' || c
== 'W')
7472 ip
->insn_opcode
|= regno
<< 6;
7476 ip
->insn_opcode
|= regno
<< 11;
7480 ip
->insn_opcode
|= regno
<< 16;
7483 ip
->insn_opcode
|= regno
<< 21;
7493 ip
->insn_opcode
|= lastregno
<< 11;
7496 ip
->insn_opcode
|= lastregno
<< 16;
7502 my_getExpression (&imm_expr
, s
);
7503 if (imm_expr
.X_op
!= O_big
7504 && imm_expr
.X_op
!= O_constant
)
7505 insn_error
= _("absolute expression required");
7510 my_getExpression (&offset_expr
, s
);
7511 imm_reloc
= BFD_RELOC_32
;
7523 unsigned char temp
[8];
7525 unsigned int length
;
7530 /* These only appear as the last operand in an
7531 instruction, and every instruction that accepts
7532 them in any variant accepts them in all variants.
7533 This means we don't have to worry about backing out
7534 any changes if the instruction does not match.
7536 The difference between them is the size of the
7537 floating point constant and where it goes. For 'F'
7538 and 'L' the constant is 64 bits; for 'f' and 'l' it
7539 is 32 bits. Where the constant is placed is based
7540 on how the MIPS assembler does things:
7543 f -- immediate value
7546 The .lit4 and .lit8 sections are only used if
7547 permitted by the -G argument.
7549 When generating embedded PIC code, we use the
7550 .lit8 section but not the .lit4 section (we can do
7551 .lit4 inline easily; we need to put .lit8
7552 somewhere in the data segment, and using .lit8
7553 permits the linker to eventually combine identical
7556 f64
= *args
== 'F' || *args
== 'L';
7558 save_in
= input_line_pointer
;
7559 input_line_pointer
= s
;
7560 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7562 s
= input_line_pointer
;
7563 input_line_pointer
= save_in
;
7564 if (err
!= NULL
&& *err
!= '\0')
7566 as_bad (_("Bad floating point constant: %s"), err
);
7567 memset (temp
, '\0', sizeof temp
);
7568 length
= f64
? 8 : 4;
7571 assert (length
== (unsigned) (f64
? 8 : 4));
7575 && (! USE_GLOBAL_POINTER_OPT
7576 || mips_pic
== EMBEDDED_PIC
7577 || g_switch_value
< 4
7578 || (temp
[0] == 0 && temp
[1] == 0)
7579 || (temp
[2] == 0 && temp
[3] == 0))))
7581 imm_expr
.X_op
= O_constant
;
7582 if (! target_big_endian
)
7583 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7585 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7588 && ! mips_disable_float_construction
7589 && ((temp
[0] == 0 && temp
[1] == 0)
7590 || (temp
[2] == 0 && temp
[3] == 0))
7591 && ((temp
[4] == 0 && temp
[5] == 0)
7592 || (temp
[6] == 0 && temp
[7] == 0)))
7594 /* The value is simple enough to load with a
7595 couple of instructions. In mips1 mode, set
7596 imm_expr to the high order 32 bits and
7597 offset_expr to the low order 32 bits.
7598 Otherwise, set imm_expr to the entire 64 bit
7600 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7602 imm_expr
.X_op
= O_constant
;
7603 offset_expr
.X_op
= O_constant
;
7604 if (! target_big_endian
)
7606 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7607 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7611 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7612 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7614 if (offset_expr
.X_add_number
== 0)
7615 offset_expr
.X_op
= O_absent
;
7617 else if (sizeof (imm_expr
.X_add_number
) > 4)
7619 imm_expr
.X_op
= O_constant
;
7620 if (! target_big_endian
)
7621 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7623 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7627 imm_expr
.X_op
= O_big
;
7628 imm_expr
.X_add_number
= 4;
7629 if (! target_big_endian
)
7631 generic_bignum
[0] = bfd_getl16 (temp
);
7632 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7633 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7634 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7638 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7639 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7640 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7641 generic_bignum
[3] = bfd_getb16 (temp
);
7647 const char *newname
;
7650 /* Switch to the right section. */
7652 subseg
= now_subseg
;
7655 default: /* unused default case avoids warnings. */
7657 newname
= RDATA_SECTION_NAME
;
7658 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7659 || mips_pic
== EMBEDDED_PIC
)
7663 if (mips_pic
== EMBEDDED_PIC
)
7666 newname
= RDATA_SECTION_NAME
;
7669 assert (!USE_GLOBAL_POINTER_OPT
7670 || g_switch_value
>= 4);
7674 new_seg
= subseg_new (newname
, (subsegT
) 0);
7675 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7676 bfd_set_section_flags (stdoutput
, new_seg
,
7681 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7682 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7683 && strcmp (TARGET_OS
, "elf") != 0)
7684 record_alignment (new_seg
, 4);
7686 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7688 as_bad (_("Can't use floating point insn in this section"));
7690 /* Set the argument to the current address in the
7692 offset_expr
.X_op
= O_symbol
;
7693 offset_expr
.X_add_symbol
=
7694 symbol_new ("L0\001", now_seg
,
7695 (valueT
) frag_now_fix (), frag_now
);
7696 offset_expr
.X_add_number
= 0;
7698 /* Put the floating point number into the section. */
7699 p
= frag_more ((int) length
);
7700 memcpy (p
, temp
, length
);
7702 /* Switch back to the original section. */
7703 subseg_set (seg
, subseg
);
7708 case 'i': /* 16 bit unsigned immediate */
7709 case 'j': /* 16 bit signed immediate */
7710 imm_reloc
= BFD_RELOC_LO16
;
7711 c
= my_getSmallExpression (&imm_expr
, s
);
7716 if (imm_expr
.X_op
== O_constant
)
7717 imm_expr
.X_add_number
=
7718 (imm_expr
.X_add_number
>> 16) & 0xffff;
7721 imm_reloc
= BFD_RELOC_HI16_S
;
7722 imm_unmatched_hi
= true;
7725 imm_reloc
= BFD_RELOC_HI16
;
7727 else if (imm_expr
.X_op
== O_constant
)
7728 imm_expr
.X_add_number
&= 0xffff;
7732 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7733 || ((imm_expr
.X_add_number
< 0
7734 || imm_expr
.X_add_number
>= 0x10000)
7735 && imm_expr
.X_op
== O_constant
))
7737 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7738 !strcmp (insn
->name
, insn
[1].name
))
7740 if (imm_expr
.X_op
== O_constant
7741 || imm_expr
.X_op
== O_big
)
7742 as_bad (_("16 bit expression not in range 0..65535"));
7750 /* The upper bound should be 0x8000, but
7751 unfortunately the MIPS assembler accepts numbers
7752 from 0x8000 to 0xffff and sign extends them, and
7753 we want to be compatible. We only permit this
7754 extended range for an instruction which does not
7755 provide any further alternates, since those
7756 alternates may handle other cases. People should
7757 use the numbers they mean, rather than relying on
7758 a mysterious sign extension. */
7759 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7760 strcmp (insn
->name
, insn
[1].name
) == 0);
7765 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7766 || ((imm_expr
.X_add_number
< -0x8000
7767 || imm_expr
.X_add_number
>= max
)
7768 && imm_expr
.X_op
== O_constant
)
7770 && imm_expr
.X_add_number
< 0
7771 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7772 && imm_expr
.X_unsigned
7773 && sizeof (imm_expr
.X_add_number
) <= 4))
7777 if (imm_expr
.X_op
== O_constant
7778 || imm_expr
.X_op
== O_big
)
7779 as_bad (_("16 bit expression not in range -32768..32767"));
7785 case 'o': /* 16 bit offset */
7786 c
= my_getSmallExpression (&offset_expr
, s
);
7788 /* If this value won't fit into a 16 bit offset, then go
7789 find a macro that will generate the 32 bit offset
7790 code pattern. As a special hack, we accept the
7791 difference of two local symbols as a constant. This
7792 is required to suppose embedded PIC switches, which
7793 use an instruction which looks like
7794 lw $4,$L12-$LS12($4)
7795 The problem with handling this in a more general
7796 fashion is that the macro function doesn't expect to
7797 see anything which can be handled in a single
7798 constant instruction. */
7800 && (offset_expr
.X_op
!= O_constant
7801 || offset_expr
.X_add_number
>= 0x8000
7802 || offset_expr
.X_add_number
< -0x8000)
7803 && (mips_pic
!= EMBEDDED_PIC
7804 || offset_expr
.X_op
!= O_subtract
7805 || (S_GET_SEGMENT (offset_expr
.X_add_symbol
)
7806 != S_GET_SEGMENT (offset_expr
.X_op_symbol
))))
7809 if (c
== 'h' || c
== 'H')
7811 if (offset_expr
.X_op
!= O_constant
)
7813 offset_expr
.X_add_number
=
7814 (offset_expr
.X_add_number
>> 16) & 0xffff;
7816 offset_reloc
= BFD_RELOC_LO16
;
7820 case 'p': /* pc relative offset */
7821 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7822 my_getExpression (&offset_expr
, s
);
7826 case 'u': /* upper 16 bits */
7827 c
= my_getSmallExpression (&imm_expr
, s
);
7828 imm_reloc
= BFD_RELOC_LO16
;
7833 if (imm_expr
.X_op
== O_constant
)
7834 imm_expr
.X_add_number
=
7835 (imm_expr
.X_add_number
>> 16) & 0xffff;
7838 imm_reloc
= BFD_RELOC_HI16_S
;
7839 imm_unmatched_hi
= true;
7842 imm_reloc
= BFD_RELOC_HI16
;
7844 else if (imm_expr
.X_op
== O_constant
)
7845 imm_expr
.X_add_number
&= 0xffff;
7847 if (imm_expr
.X_op
== O_constant
7848 && (imm_expr
.X_add_number
< 0
7849 || imm_expr
.X_add_number
>= 0x10000))
7850 as_bad (_("lui expression not in range 0..65535"));
7854 case 'a': /* 26 bit address */
7855 my_getExpression (&offset_expr
, s
);
7857 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7860 case 'N': /* 3 bit branch condition code */
7861 case 'M': /* 3 bit compare condition code */
7862 if (strncmp (s
, "$fcc", 4) != 0)
7872 while (isdigit ((unsigned char) *s
));
7874 as_bad (_("invalid condition code register $fcc%d"), regno
);
7876 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7878 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7882 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
7884 if (isdigit ((unsigned char) *s
))
7893 while (isdigit ((unsigned char) *s
));
7896 c
= 8; /* Invalid sel value. */
7899 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
7900 ip
->insn_opcode
|= c
;
7904 as_bad (_("bad char = '%c'\n"), *args
);
7909 /* Args don't match. */
7910 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7911 !strcmp (insn
->name
, insn
[1].name
))
7917 insn_error
= _("illegal operands");
7922 /* This routine assembles an instruction into its binary format when
7923 assembling for the mips16. As a side effect, it sets one of the
7924 global variables imm_reloc or offset_reloc to the type of
7925 relocation to do if one of the operands is an address expression.
7926 It also sets mips16_small and mips16_ext if the user explicitly
7927 requested a small or extended instruction. */
7932 struct mips_cl_insn
*ip
;
7936 struct mips_opcode
*insn
;
7939 unsigned int lastregno
= 0;
7944 mips16_small
= false;
7947 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7959 if (s
[1] == 't' && s
[2] == ' ')
7962 mips16_small
= true;
7966 else if (s
[1] == 'e' && s
[2] == ' ')
7975 insn_error
= _("unknown opcode");
7979 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7980 mips16_small
= true;
7982 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7984 insn_error
= _("unrecognized opcode");
7991 assert (strcmp (insn
->name
, str
) == 0);
7994 ip
->insn_opcode
= insn
->match
;
7995 ip
->use_extend
= false;
7996 imm_expr
.X_op
= O_absent
;
7997 imm_reloc
= BFD_RELOC_UNUSED
;
7998 offset_expr
.X_op
= O_absent
;
7999 offset_reloc
= BFD_RELOC_UNUSED
;
8000 for (args
= insn
->args
; 1; ++args
)
8007 /* In this switch statement we call break if we did not find
8008 a match, continue if we did find a match, or return if we
8017 /* Stuff the immediate value in now, if we can. */
8018 if (imm_expr
.X_op
== O_constant
8019 && imm_reloc
> BFD_RELOC_UNUSED
8020 && insn
->pinfo
!= INSN_MACRO
)
8022 mips16_immed ((char *) NULL
, 0,
8023 imm_reloc
- BFD_RELOC_UNUSED
,
8024 imm_expr
.X_add_number
, true, mips16_small
,
8025 mips16_ext
, &ip
->insn_opcode
,
8026 &ip
->use_extend
, &ip
->extend
);
8027 imm_expr
.X_op
= O_absent
;
8028 imm_reloc
= BFD_RELOC_UNUSED
;
8042 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8045 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8061 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8063 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8080 if (isdigit ((unsigned char) s
[1]))
8090 while (isdigit ((unsigned char) *s
));
8093 as_bad (_("invalid register number (%d)"), regno
);
8099 if (s
[1] == 'f' && s
[2] == 'p')
8104 else if (s
[1] == 's' && s
[2] == 'p')
8109 else if (s
[1] == 'g' && s
[2] == 'p')
8114 else if (s
[1] == 'a' && s
[2] == 't')
8119 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8124 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8137 if (c
== 'v' || c
== 'w')
8139 regno
= mips16_to_32_reg_map
[lastregno
];
8153 regno
= mips32_to_16_reg_map
[regno
];
8158 regno
= ILLEGAL_REG
;
8163 regno
= ILLEGAL_REG
;
8168 regno
= ILLEGAL_REG
;
8173 if (regno
== AT
&& ! mips_opts
.noat
)
8174 as_warn (_("used $at without \".set noat\""));
8181 if (regno
== ILLEGAL_REG
)
8188 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8192 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8195 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8198 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8204 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8207 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8208 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8218 if (strncmp (s
, "$pc", 3) == 0)
8242 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8244 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8245 and generate the appropriate reloc. If the text
8246 inside %gprel is not a symbol name with an
8247 optional offset, then we generate a normal reloc
8248 and will probably fail later. */
8249 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8250 if (imm_expr
.X_op
== O_symbol
)
8253 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8255 ip
->use_extend
= true;
8262 /* Just pick up a normal expression. */
8263 my_getExpression (&imm_expr
, s
);
8266 if (imm_expr
.X_op
== O_register
)
8268 /* What we thought was an expression turned out to
8271 if (s
[0] == '(' && args
[1] == '(')
8273 /* It looks like the expression was omitted
8274 before a register indirection, which means
8275 that the expression is implicitly zero. We
8276 still set up imm_expr, so that we handle
8277 explicit extensions correctly. */
8278 imm_expr
.X_op
= O_constant
;
8279 imm_expr
.X_add_number
= 0;
8280 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8287 /* We need to relax this instruction. */
8288 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8297 /* We use offset_reloc rather than imm_reloc for the PC
8298 relative operands. This lets macros with both
8299 immediate and address operands work correctly. */
8300 my_getExpression (&offset_expr
, s
);
8302 if (offset_expr
.X_op
== O_register
)
8305 /* We need to relax this instruction. */
8306 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8310 case '6': /* break code */
8311 my_getExpression (&imm_expr
, s
);
8312 check_absolute_expr (ip
, &imm_expr
);
8313 if ((unsigned long) imm_expr
.X_add_number
> 63)
8315 as_warn (_("Invalid value for `%s' (%lu)"),
8317 (unsigned long) imm_expr
.X_add_number
);
8318 imm_expr
.X_add_number
&= 0x3f;
8320 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8321 imm_expr
.X_op
= O_absent
;
8325 case 'a': /* 26 bit address */
8326 my_getExpression (&offset_expr
, s
);
8328 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8329 ip
->insn_opcode
<<= 16;
8332 case 'l': /* register list for entry macro */
8333 case 'L': /* register list for exit macro */
8343 int freg
, reg1
, reg2
;
8345 while (*s
== ' ' || *s
== ',')
8349 as_bad (_("can't parse register list"));
8361 while (isdigit ((unsigned char) *s
))
8383 as_bad (_("invalid register list"));
8388 while (isdigit ((unsigned char) *s
))
8395 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8400 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8405 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8406 mask
|= (reg2
- 3) << 3;
8407 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8408 mask
|= (reg2
- 15) << 1;
8409 else if (reg1
== 31 && reg2
== 31)
8413 as_bad (_("invalid register list"));
8417 /* The mask is filled in in the opcode table for the
8418 benefit of the disassembler. We remove it before
8419 applying the actual mask. */
8420 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8421 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8425 case 'e': /* extend code */
8426 my_getExpression (&imm_expr
, s
);
8427 check_absolute_expr (ip
, &imm_expr
);
8428 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8430 as_warn (_("Invalid value for `%s' (%lu)"),
8432 (unsigned long) imm_expr
.X_add_number
);
8433 imm_expr
.X_add_number
&= 0x7ff;
8435 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8436 imm_expr
.X_op
= O_absent
;
8446 /* Args don't match. */
8447 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8448 strcmp (insn
->name
, insn
[1].name
) == 0)
8455 insn_error
= _("illegal operands");
8461 /* This structure holds information we know about a mips16 immediate
8464 struct mips16_immed_operand
{
8465 /* The type code used in the argument string in the opcode table. */
8467 /* The number of bits in the short form of the opcode. */
8469 /* The number of bits in the extended form of the opcode. */
8471 /* The amount by which the short form is shifted when it is used;
8472 for example, the sw instruction has a shift count of 2. */
8474 /* The amount by which the short form is shifted when it is stored
8475 into the instruction code. */
8477 /* Non-zero if the short form is unsigned. */
8479 /* Non-zero if the extended form is unsigned. */
8481 /* Non-zero if the value is PC relative. */
8485 /* The mips16 immediate operand types. */
8487 static const struct mips16_immed_operand mips16_immed_operands
[] =
8489 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8490 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8491 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8492 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8493 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8494 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8495 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8496 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8497 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8498 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8499 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8500 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8501 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8502 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8503 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8504 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8505 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8506 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8507 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8508 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8509 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8512 #define MIPS16_NUM_IMMED \
8513 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8515 /* Handle a mips16 instruction with an immediate value. This or's the
8516 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8517 whether an extended value is needed; if one is needed, it sets
8518 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8519 If SMALL is true, an unextended opcode was explicitly requested.
8520 If EXT is true, an extended opcode was explicitly requested. If
8521 WARN is true, warn if EXT does not match reality. */
8524 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8533 unsigned long *insn
;
8534 boolean
*use_extend
;
8535 unsigned short *extend
;
8537 register const struct mips16_immed_operand
*op
;
8538 int mintiny
, maxtiny
;
8541 op
= mips16_immed_operands
;
8542 while (op
->type
!= type
)
8545 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8550 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8553 maxtiny
= 1 << op
->nbits
;
8558 maxtiny
= (1 << op
->nbits
) - 1;
8563 mintiny
= - (1 << (op
->nbits
- 1));
8564 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8567 /* Branch offsets have an implicit 0 in the lowest bit. */
8568 if (type
== 'p' || type
== 'q')
8571 if ((val
& ((1 << op
->shift
) - 1)) != 0
8572 || val
< (mintiny
<< op
->shift
)
8573 || val
> (maxtiny
<< op
->shift
))
8578 if (warn
&& ext
&& ! needext
)
8579 as_warn_where (file
, line
,
8580 _("extended operand requested but not required"));
8581 if (small
&& needext
)
8582 as_bad_where (file
, line
, _("invalid unextended operand value"));
8584 if (small
|| (! ext
&& ! needext
))
8588 *use_extend
= false;
8589 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8590 insnval
<<= op
->op_shift
;
8595 long minext
, maxext
;
8601 maxext
= (1 << op
->extbits
) - 1;
8605 minext
= - (1 << (op
->extbits
- 1));
8606 maxext
= (1 << (op
->extbits
- 1)) - 1;
8608 if (val
< minext
|| val
> maxext
)
8609 as_bad_where (file
, line
,
8610 _("operand value out of range for instruction"));
8613 if (op
->extbits
== 16)
8615 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8618 else if (op
->extbits
== 15)
8620 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8625 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8629 *extend
= (unsigned short) extval
;
8638 my_getSmallExpression (ep
, str
)
8649 ((str
[1] == 'h' && str
[2] == 'i')
8650 || (str
[1] == 'H' && str
[2] == 'I')
8651 || (str
[1] == 'l' && str
[2] == 'o'))
8663 * A small expression may be followed by a base register.
8664 * Scan to the end of this operand, and then back over a possible
8665 * base register. Then scan the small expression up to that
8666 * point. (Based on code in sparc.c...)
8668 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8670 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8672 if (isdigit ((unsigned char) sp
[-2]))
8674 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8676 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8682 else if (sp
- 5 >= str
8685 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8686 || (sp
[-3] == 's' && sp
[-2] == 'p')
8687 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8688 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8694 /* no expression means zero offset */
8697 /* %xx(reg) is an error */
8698 ep
->X_op
= O_absent
;
8703 ep
->X_op
= O_constant
;
8706 ep
->X_add_symbol
= NULL
;
8707 ep
->X_op_symbol
= NULL
;
8708 ep
->X_add_number
= 0;
8713 my_getExpression (ep
, str
);
8720 my_getExpression (ep
, str
);
8721 return c
; /* => %hi or %lo encountered */
8725 my_getExpression (ep
, str
)
8731 save_in
= input_line_pointer
;
8732 input_line_pointer
= str
;
8734 expr_end
= input_line_pointer
;
8735 input_line_pointer
= save_in
;
8737 /* If we are in mips16 mode, and this is an expression based on `.',
8738 then we bump the value of the symbol by 1 since that is how other
8739 text symbols are handled. We don't bother to handle complex
8740 expressions, just `.' plus or minus a constant. */
8741 if (mips_opts
.mips16
8742 && ep
->X_op
== O_symbol
8743 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8744 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8745 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8746 && symbol_constant_p (ep
->X_add_symbol
)
8747 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8748 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8751 /* Turn a string in input_line_pointer into a floating point constant
8752 of type TYPE, and store the appropriate bytes in *LITP. The number
8753 of LITTLENUMS emitted is stored in *SIZEP. An error message is
8754 returned, or NULL on OK. */
8757 md_atof (type
, litP
, sizeP
)
8763 LITTLENUM_TYPE words
[4];
8779 return _("bad call to md_atof");
8782 t
= atof_ieee (input_line_pointer
, type
, words
);
8784 input_line_pointer
= t
;
8788 if (! target_big_endian
)
8790 for (i
= prec
- 1; i
>= 0; i
--)
8792 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8798 for (i
= 0; i
< prec
; i
++)
8800 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8809 md_number_to_chars (buf
, val
, n
)
8814 if (target_big_endian
)
8815 number_to_chars_bigendian (buf
, val
, n
);
8817 number_to_chars_littleendian (buf
, val
, n
);
8820 CONST
char *md_shortopts
= "O::g::G:";
8822 struct option md_longopts
[] = {
8823 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8824 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8825 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8826 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8827 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8828 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8829 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8830 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8831 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8832 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8833 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8834 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8835 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8836 #define OPTION_TRAP (OPTION_MD_BASE + 7)
8837 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8838 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8839 #define OPTION_BREAK (OPTION_MD_BASE + 8)
8840 {"break", no_argument
, NULL
, OPTION_BREAK
},
8841 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8842 #define OPTION_EB (OPTION_MD_BASE + 9)
8843 {"EB", no_argument
, NULL
, OPTION_EB
},
8844 #define OPTION_EL (OPTION_MD_BASE + 10)
8845 {"EL", no_argument
, NULL
, OPTION_EL
},
8846 #define OPTION_M4650 (OPTION_MD_BASE + 11)
8847 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8848 #define OPTION_NO_M4650 (OPTION_MD_BASE + 12)
8849 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8850 #define OPTION_M4010 (OPTION_MD_BASE + 13)
8851 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8852 #define OPTION_NO_M4010 (OPTION_MD_BASE + 14)
8853 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8854 #define OPTION_M4100 (OPTION_MD_BASE + 15)
8855 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8856 #define OPTION_NO_M4100 (OPTION_MD_BASE + 16)
8857 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8858 #define OPTION_MIPS16 (OPTION_MD_BASE + 17)
8859 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8860 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 18)
8861 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8862 #define OPTION_M3900 (OPTION_MD_BASE + 19)
8863 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8864 #define OPTION_NO_M3900 (OPTION_MD_BASE + 20)
8865 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8866 #define OPTION_MABI (OPTION_MD_BASE + 21)
8867 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8868 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 22)
8869 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8870 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 23)
8871 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8872 #define OPTION_GP32 (OPTION_MD_BASE + 24)
8873 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8874 #define OPTION_GP64 (OPTION_MD_BASE + 25)
8875 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8876 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 26)
8877 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
8878 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 27)
8879 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
8880 #define OPTION_MIPS32 (OPTION_MD_BASE + 28)
8881 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
8882 #define OPTION_MIPS5 (OPTION_MD_BASE + 29)
8883 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
8884 #define OPTION_MIPS64 (OPTION_MD_BASE + 30)
8885 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
8887 #define OPTION_ELF_BASE (OPTION_MD_BASE + 35)
8888 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
8889 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
8890 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
8891 #define OPTION_32 (OPTION_ELF_BASE + 3)
8892 #define OPTION_64 (OPTION_ELF_BASE + 4)
8893 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8894 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8895 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8896 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8897 {"32", no_argument
, NULL
, OPTION_32
},
8898 {"64", no_argument
, NULL
, OPTION_64
},
8901 {NULL
, no_argument
, NULL
, 0}
8903 size_t md_longopts_size
= sizeof (md_longopts
);
8906 md_parse_option (c
, arg
)
8912 case OPTION_CONSTRUCT_FLOATS
:
8913 mips_disable_float_construction
= 0;
8916 case OPTION_NO_CONSTRUCT_FLOATS
:
8917 mips_disable_float_construction
= 1;
8929 target_big_endian
= 1;
8933 target_big_endian
= 0;
8937 if (arg
&& arg
[1] == '0')
8947 mips_debug
= atoi (arg
);
8948 /* When the MIPS assembler sees -g or -g2, it does not do
8949 optimizations which limit full symbolic debugging. We take
8950 that to be equivalent to -O0. */
8951 if (mips_debug
== 2)
8956 mips_opts
.isa
= ISA_MIPS1
;
8960 mips_opts
.isa
= ISA_MIPS2
;
8964 mips_opts
.isa
= ISA_MIPS3
;
8968 mips_opts
.isa
= ISA_MIPS4
;
8972 mips_opts
.isa
= ISA_MIPS5
;
8976 mips_opts
.isa
= ISA_MIPS32
;
8980 mips_opts
.isa
= ISA_MIPS64
;
8985 /* Identify the processor type. */
8986 if (strcasecmp (arg
, "default") == 0)
8987 mips_cpu
= CPU_UNKNOWN
;
8990 const struct mips_cpu_info
*ci
;
8992 ci
= mips_cpu_info_from_name (arg
);
8993 if (ci
== NULL
|| ci
->is_isa
)
8994 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9002 mips_cpu
= CPU_R4650
;
9005 case OPTION_NO_M4650
:
9009 mips_cpu
= CPU_R4010
;
9012 case OPTION_NO_M4010
:
9016 mips_cpu
= CPU_VR4100
;
9019 case OPTION_NO_M4100
:
9023 mips_cpu
= CPU_R3900
;
9026 case OPTION_NO_M3900
:
9030 mips_opts
.mips16
= 1;
9031 mips_no_prev_insn (false);
9034 case OPTION_NO_MIPS16
:
9035 mips_opts
.mips16
= 0;
9036 mips_no_prev_insn (false);
9039 case OPTION_MEMBEDDED_PIC
:
9040 mips_pic
= EMBEDDED_PIC
;
9041 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9043 as_bad (_("-G may not be used with embedded PIC code"));
9046 g_switch_value
= 0x7fffffff;
9049 /* When generating ELF code, we permit -KPIC and -call_shared to
9050 select SVR4_PIC, and -non_shared to select no PIC. This is
9051 intended to be compatible with Irix 5. */
9052 case OPTION_CALL_SHARED
:
9053 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9055 as_bad (_("-call_shared is supported only for ELF format"));
9058 mips_pic
= SVR4_PIC
;
9059 if (g_switch_seen
&& g_switch_value
!= 0)
9061 as_bad (_("-G may not be used with SVR4 PIC code"));
9067 case OPTION_NON_SHARED
:
9068 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9070 as_bad (_("-non_shared is supported only for ELF format"));
9076 /* The -xgot option tells the assembler to use 32 offsets when
9077 accessing the got in SVR4_PIC mode. It is for Irix
9084 if (! USE_GLOBAL_POINTER_OPT
)
9086 as_bad (_("-G is not supported for this configuration"));
9089 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9091 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9095 g_switch_value
= atoi (arg
);
9099 /* The -32 and -64 options tell the assembler to output the 32
9100 bit or the 64 bit MIPS ELF format. */
9107 const char **list
, **l
;
9109 list
= bfd_target_list ();
9110 for (l
= list
; *l
!= NULL
; l
++)
9111 if (strcmp (*l
, "elf64-bigmips") == 0
9112 || strcmp (*l
, "elf64-littlemips") == 0)
9115 as_fatal (_("No compiled in support for 64 bit object file format"));
9125 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9126 flag in object files because to do so would make it
9127 impossible to link with libraries compiled without "-gp32".
9128 This is unnecessarily restrictive.
9130 We could solve this problem by adding "-gp32" multilibs to
9131 gcc, but to set this flag before gcc is built with such
9132 multilibs will break too many systems. */
9148 if (strcmp (arg
, "32") == 0
9149 || strcmp (arg
, "n32") == 0
9150 || strcmp (arg
, "64") == 0
9151 || strcmp (arg
, "o64") == 0
9152 || strcmp (arg
, "eabi") == 0)
9153 mips_abi_string
= arg
;
9156 case OPTION_M7000_HILO_FIX
:
9157 mips_7000_hilo_fix
= true;
9160 case OPTION_NO_M7000_HILO_FIX
:
9161 mips_7000_hilo_fix
= false;
9172 show (stream
, string
, col_p
, first_p
)
9180 fprintf (stream
, "%24s", "");
9185 fprintf (stream
, ", ");
9189 if (*col_p
+ strlen (string
) > 72)
9191 fprintf (stream
, "\n%24s", "");
9195 fprintf (stream
, "%s", string
);
9196 *col_p
+= strlen (string
);
9202 md_show_usage (stream
)
9207 fprintf (stream
, _("\
9209 -membedded-pic generate embedded position independent code\n\
9210 -EB generate big endian output\n\
9211 -EL generate little endian output\n\
9212 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9213 -G NUM allow referencing objects up to NUM bytes\n\
9214 implicitly with the gp register [default 8]\n"));
9215 fprintf (stream
, _("\
9216 -mips1 generate MIPS ISA I instructions\n\
9217 -mips2 generate MIPS ISA II instructions\n\
9218 -mips3 generate MIPS ISA III instructions\n\
9219 -mips4 generate MIPS ISA IV instructions\n\
9220 -mips5 generate MIPS ISA V instructions\n\
9221 -mips32 generate MIPS32 ISA instructions\n\
9222 -mips64 generate MIPS64 ISA instructions\n\
9223 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9227 show (stream
, "2000", &column
, &first
);
9228 show (stream
, "3000", &column
, &first
);
9229 show (stream
, "3900", &column
, &first
);
9230 show (stream
, "4000", &column
, &first
);
9231 show (stream
, "4010", &column
, &first
);
9232 show (stream
, "4100", &column
, &first
);
9233 show (stream
, "4111", &column
, &first
);
9234 show (stream
, "4300", &column
, &first
);
9235 show (stream
, "4400", &column
, &first
);
9236 show (stream
, "4600", &column
, &first
);
9237 show (stream
, "4650", &column
, &first
);
9238 show (stream
, "5000", &column
, &first
);
9239 show (stream
, "6000", &column
, &first
);
9240 show (stream
, "8000", &column
, &first
);
9241 show (stream
, "10000", &column
, &first
);
9242 show (stream
, "mips32-4k", &column
, &first
);
9243 show (stream
, "sb-1", &column
, &first
);
9244 fputc ('\n', stream
);
9246 fprintf (stream
, _("\
9247 -mCPU equivalent to -mcpu=CPU.\n\
9248 -no-mCPU don't generate code specific to CPU.\n\
9249 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9253 show (stream
, "3900", &column
, &first
);
9254 show (stream
, "4010", &column
, &first
);
9255 show (stream
, "4100", &column
, &first
);
9256 show (stream
, "4650", &column
, &first
);
9257 fputc ('\n', stream
);
9259 fprintf (stream
, _("\
9260 -mips16 generate mips16 instructions\n\
9261 -no-mips16 do not generate mips16 instructions\n"));
9262 fprintf (stream
, _("\
9263 -O0 remove unneeded NOPs, do not swap branches\n\
9264 -O remove unneeded NOPs and swap branches\n\
9265 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
9266 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9267 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9269 fprintf (stream
, _("\
9270 -KPIC, -call_shared generate SVR4 position independent code\n\
9271 -non_shared do not generate position independent code\n\
9272 -xgot assume a 32 bit GOT\n\
9273 -32 create 32 bit object file (default)\n\
9274 -64 create 64 bit object file\n"));
9279 mips_init_after_args ()
9281 /* initialize opcodes */
9282 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9283 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9287 md_pcrel_from (fixP
)
9290 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9291 && fixP
->fx_addsy
!= (symbolS
*) NULL
9292 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9294 /* This makes a branch to an undefined symbol be a branch to the
9295 current location. */
9299 /* return the address of the delay slot */
9300 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9303 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9304 reloc for a cons. We could use the definition there, except that
9305 we want to handle 64 bit relocs specially. */
9308 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9309 fragS
*frag ATTRIBUTE_UNUSED
;
9311 unsigned int nbytes
;
9315 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9317 if (nbytes
== 8 && ! mips_64
)
9319 if (target_big_endian
)
9325 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9326 as_bad (_("Unsupported reloc size %d"), nbytes
);
9328 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9331 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9334 /* This is called before the symbol table is processed. In order to
9335 work with gcc when using mips-tfile, we must keep all local labels.
9336 However, in other cases, we want to discard them. If we were
9337 called with -g, but we didn't see any debugging information, it may
9338 mean that gcc is smuggling debugging information through to
9339 mips-tfile, in which case we must generate all local labels. */
9342 mips_frob_file_before_adjust ()
9344 #ifndef NO_ECOFF_DEBUGGING
9347 && ! ecoff_debugging_seen
)
9348 flag_keep_locals
= 1;
9352 /* Sort any unmatched HI16_S relocs so that they immediately precede
9353 the corresponding LO reloc. This is called before md_apply_fix and
9354 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9355 explicit use of the %hi modifier. */
9360 struct mips_hi_fixup
*l
;
9362 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9364 segment_info_type
*seginfo
;
9367 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9369 /* Check quickly whether the next fixup happens to be a matching
9371 if (l
->fixp
->fx_next
!= NULL
9372 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9373 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9374 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9377 /* Look through the fixups for this segment for a matching %lo.
9378 When we find one, move the %hi just in front of it. We do
9379 this in two passes. In the first pass, we try to find a
9380 unique %lo. In the second pass, we permit multiple %hi
9381 relocs for a single %lo (this is a GNU extension). */
9382 seginfo
= seg_info (l
->seg
);
9383 for (pass
= 0; pass
< 2; pass
++)
9388 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9390 /* Check whether this is a %lo fixup which matches l->fixp. */
9391 if (f
->fx_r_type
== BFD_RELOC_LO16
9392 && f
->fx_addsy
== l
->fixp
->fx_addsy
9393 && f
->fx_offset
== l
->fixp
->fx_offset
9396 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9397 || prev
->fx_addsy
!= f
->fx_addsy
9398 || prev
->fx_offset
!= f
->fx_offset
))
9402 /* Move l->fixp before f. */
9403 for (pf
= &seginfo
->fix_root
;
9405 pf
= &(*pf
)->fx_next
)
9406 assert (*pf
!= NULL
);
9408 *pf
= l
->fixp
->fx_next
;
9410 l
->fixp
->fx_next
= f
;
9412 seginfo
->fix_root
= l
->fixp
;
9414 prev
->fx_next
= l
->fixp
;
9425 #if 0 /* GCC code motion plus incomplete dead code elimination
9426 can leave a %hi without a %lo. */
9428 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9429 _("Unmatched %%hi reloc"));
9435 /* When generating embedded PIC code we need to use a special
9436 relocation to represent the difference of two symbols in the .text
9437 section (switch tables use a difference of this sort). See
9438 include/coff/mips.h for details. This macro checks whether this
9439 fixup requires the special reloc. */
9440 #define SWITCH_TABLE(fixp) \
9441 ((fixp)->fx_r_type == BFD_RELOC_32 \
9442 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9443 && (fixp)->fx_addsy != NULL \
9444 && (fixp)->fx_subsy != NULL \
9445 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9446 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9448 /* When generating embedded PIC code we must keep all PC relative
9449 relocations, in case the linker has to relax a call. We also need
9450 to keep relocations for switch table entries. */
9453 mips_force_relocation (fixp
)
9456 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9457 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9460 return (mips_pic
== EMBEDDED_PIC
9462 || SWITCH_TABLE (fixp
)
9463 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9464 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9467 /* Apply a fixup to the object file. */
9470 md_apply_fix (fixP
, valueP
)
9477 assert (fixP
->fx_size
== 4
9478 || fixP
->fx_r_type
== BFD_RELOC_16
9479 || fixP
->fx_r_type
== BFD_RELOC_64
9480 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9481 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9485 /* If we aren't adjusting this fixup to be against the section
9486 symbol, we need to adjust the value. */
9488 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9490 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9491 || S_IS_WEAK (fixP
->fx_addsy
)
9492 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9493 && (((bfd_get_section_flags (stdoutput
,
9494 S_GET_SEGMENT (fixP
->fx_addsy
))
9495 & SEC_LINK_ONCE
) != 0)
9496 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9498 sizeof (".gnu.linkonce") - 1))))
9501 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9502 if (value
!= 0 && ! fixP
->fx_pcrel
)
9504 /* In this case, the bfd_install_relocation routine will
9505 incorrectly add the symbol value back in. We just want
9506 the addend to appear in the object file.
9507 FIXME: If this makes VALUE zero, we're toast. */
9508 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9512 /* This code was generated using trial and error and so is
9513 fragile and not trustworthy. If you change it, you should
9514 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9516 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9518 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9520 /* BFD's REL handling, for MIPS, is _very_ weird.
9521 This gives the right results, but it can't possibly
9522 be the way things are supposed to work. */
9523 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9524 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9525 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9530 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9532 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9535 switch (fixP
->fx_r_type
)
9537 case BFD_RELOC_MIPS_JMP
:
9538 case BFD_RELOC_HI16
:
9539 case BFD_RELOC_HI16_S
:
9540 case BFD_RELOC_MIPS_GPREL
:
9541 case BFD_RELOC_MIPS_LITERAL
:
9542 case BFD_RELOC_MIPS_CALL16
:
9543 case BFD_RELOC_MIPS_GOT16
:
9544 case BFD_RELOC_MIPS_GPREL32
:
9545 case BFD_RELOC_MIPS_GOT_HI16
:
9546 case BFD_RELOC_MIPS_GOT_LO16
:
9547 case BFD_RELOC_MIPS_CALL_HI16
:
9548 case BFD_RELOC_MIPS_CALL_LO16
:
9549 case BFD_RELOC_MIPS16_GPREL
:
9551 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9552 _("Invalid PC relative reloc"));
9553 /* Nothing needed to do. The value comes from the reloc entry */
9556 case BFD_RELOC_MIPS16_JMP
:
9557 /* We currently always generate a reloc against a symbol, which
9558 means that we don't want an addend even if the symbol is
9560 fixP
->fx_addnumber
= 0;
9563 case BFD_RELOC_PCREL_HI16_S
:
9564 /* The addend for this is tricky if it is internal, so we just
9565 do everything here rather than in bfd_install_relocation. */
9566 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9571 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9573 /* For an external symbol adjust by the address to make it
9574 pcrel_offset. We use the address of the RELLO reloc
9575 which follows this one. */
9576 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9577 + fixP
->fx_next
->fx_where
);
9582 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9583 if (target_big_endian
)
9585 md_number_to_chars (buf
, value
, 2);
9588 case BFD_RELOC_PCREL_LO16
:
9589 /* The addend for this is tricky if it is internal, so we just
9590 do everything here rather than in bfd_install_relocation. */
9591 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9596 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9597 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9598 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9599 if (target_big_endian
)
9601 md_number_to_chars (buf
, value
, 2);
9605 /* This is handled like BFD_RELOC_32, but we output a sign
9606 extended value if we are only 32 bits. */
9608 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9610 if (8 <= sizeof (valueT
))
9611 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9618 w1
= w2
= fixP
->fx_where
;
9619 if (target_big_endian
)
9623 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9624 if ((value
& 0x80000000) != 0)
9628 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9635 /* If we are deleting this reloc entry, we must fill in the
9636 value now. This can happen if we have a .word which is not
9637 resolved when it appears but is later defined. We also need
9638 to fill in the value if this is an embedded PIC switch table
9641 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9642 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9647 /* If we are deleting this reloc entry, we must fill in the
9649 assert (fixP
->fx_size
== 2);
9651 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9655 case BFD_RELOC_LO16
:
9656 /* When handling an embedded PIC switch statement, we can wind
9657 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9660 if (value
< -0x8000 || value
> 0x7fff)
9661 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9662 _("relocation overflow"));
9663 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9664 if (target_big_endian
)
9666 md_number_to_chars (buf
, value
, 2);
9670 case BFD_RELOC_16_PCREL_S2
:
9672 * We need to save the bits in the instruction since fixup_segment()
9673 * might be deleting the relocation entry (i.e., a branch within
9674 * the current segment).
9676 if ((value
& 0x3) != 0)
9677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9678 _("Branch to odd address (%lx)"), value
);
9680 if (!fixP
->fx_done
&& value
!= 0)
9682 /* If 'value' is zero, the remaining reloc code won't actually
9683 do the store, so it must be done here. This is probably
9686 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9690 /* update old instruction data */
9691 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9692 if (target_big_endian
)
9693 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9695 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9697 if (value
>= -0x8000 && value
< 0x8000)
9698 insn
|= value
& 0xffff;
9701 /* The branch offset is too large. If this is an
9702 unconditional branch, and we are not generating PIC code,
9703 we can convert it to an absolute jump instruction. */
9704 if (mips_pic
== NO_PIC
9706 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9707 && (fixP
->fx_frag
->fr_address
9708 < text_section
->vma
+ text_section
->_raw_size
)
9709 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9710 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9711 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9713 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9714 insn
= 0x0c000000; /* jal */
9716 insn
= 0x08000000; /* j */
9717 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9719 fixP
->fx_addsy
= section_symbol (text_section
);
9720 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9724 /* FIXME. It would be possible in principle to handle
9725 conditional branches which overflow. They could be
9726 transformed into a branch around a jump. This would
9727 require setting up variant frags for each different
9728 branch type. The native MIPS assembler attempts to
9729 handle these cases, but it appears to do it
9731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9732 _("Branch out of range"));
9736 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9739 case BFD_RELOC_VTABLE_INHERIT
:
9742 && !S_IS_DEFINED (fixP
->fx_addsy
)
9743 && !S_IS_WEAK (fixP
->fx_addsy
))
9744 S_SET_WEAK (fixP
->fx_addsy
);
9747 case BFD_RELOC_VTABLE_ENTRY
:
9763 const struct mips_opcode
*p
;
9764 int treg
, sreg
, dreg
, shamt
;
9769 for (i
= 0; i
< NUMOPCODES
; ++i
)
9771 p
= &mips_opcodes
[i
];
9772 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9774 printf ("%08lx %s\t", oc
, p
->name
);
9775 treg
= (oc
>> 16) & 0x1f;
9776 sreg
= (oc
>> 21) & 0x1f;
9777 dreg
= (oc
>> 11) & 0x1f;
9778 shamt
= (oc
>> 6) & 0x1f;
9780 for (args
= p
->args
;; ++args
)
9791 printf ("%c", *args
);
9795 assert (treg
== sreg
);
9796 printf ("$%d,$%d", treg
, sreg
);
9801 printf ("$%d", dreg
);
9806 printf ("$%d", treg
);
9810 printf ("0x%x", treg
);
9815 printf ("$%d", sreg
);
9819 printf ("0x%08lx", oc
& 0x1ffffff);
9831 printf ("$%d", shamt
);
9842 printf (_("%08lx UNDEFINED\n"), oc
);
9853 name
= input_line_pointer
;
9854 c
= get_symbol_end ();
9855 p
= (symbolS
*) symbol_find_or_make (name
);
9856 *input_line_pointer
= c
;
9860 /* Align the current frag to a given power of two. The MIPS assembler
9861 also automatically adjusts any preceding label. */
9864 mips_align (to
, fill
, label
)
9869 mips_emit_delays (false);
9870 frag_align (to
, fill
, 0);
9871 record_alignment (now_seg
, to
);
9874 assert (S_GET_SEGMENT (label
) == now_seg
);
9875 symbol_set_frag (label
, frag_now
);
9876 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9880 /* Align to a given power of two. .align 0 turns off the automatic
9881 alignment used by the data creating pseudo-ops. */
9885 int x ATTRIBUTE_UNUSED
;
9888 register long temp_fill
;
9889 long max_alignment
= 15;
9893 o Note that the assembler pulls down any immediately preceeding label
9894 to the aligned address.
9895 o It's not documented but auto alignment is reinstated by
9896 a .align pseudo instruction.
9897 o Note also that after auto alignment is turned off the mips assembler
9898 issues an error on attempt to assemble an improperly aligned data item.
9903 temp
= get_absolute_expression ();
9904 if (temp
> max_alignment
)
9905 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9908 as_warn (_("Alignment negative: 0 assumed."));
9911 if (*input_line_pointer
== ',')
9913 input_line_pointer
++;
9914 temp_fill
= get_absolute_expression ();
9921 mips_align (temp
, (int) temp_fill
,
9922 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9929 demand_empty_rest_of_line ();
9933 mips_flush_pending_output ()
9935 mips_emit_delays (false);
9936 mips_clear_insn_labels ();
9945 /* When generating embedded PIC code, we only use the .text, .lit8,
9946 .sdata and .sbss sections. We change the .data and .rdata
9947 pseudo-ops to use .sdata. */
9948 if (mips_pic
== EMBEDDED_PIC
9949 && (sec
== 'd' || sec
== 'r'))
9953 /* The ELF backend needs to know that we are changing sections, so
9954 that .previous works correctly. We could do something like check
9955 for a obj_section_change_hook macro, but that might be confusing
9956 as it would not be appropriate to use it in the section changing
9957 functions in read.c, since obj-elf.c intercepts those. FIXME:
9958 This should be cleaner, somehow. */
9959 obj_elf_section_change_hook ();
9962 mips_emit_delays (false);
9972 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9973 demand_empty_rest_of_line ();
9977 if (USE_GLOBAL_POINTER_OPT
)
9979 seg
= subseg_new (RDATA_SECTION_NAME
,
9980 (subsegT
) get_absolute_expression ());
9981 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9983 bfd_set_section_flags (stdoutput
, seg
,
9989 if (strcmp (TARGET_OS
, "elf") != 0)
9990 record_alignment (seg
, 4);
9992 demand_empty_rest_of_line ();
9996 as_bad (_("No read only data section in this object file format"));
9997 demand_empty_rest_of_line ();
10003 if (USE_GLOBAL_POINTER_OPT
)
10005 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10006 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10008 bfd_set_section_flags (stdoutput
, seg
,
10009 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10011 if (strcmp (TARGET_OS
, "elf") != 0)
10012 record_alignment (seg
, 4);
10014 demand_empty_rest_of_line ();
10019 as_bad (_("Global pointers not supported; recompile -G 0"));
10020 demand_empty_rest_of_line ();
10029 mips_enable_auto_align ()
10040 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10041 mips_emit_delays (false);
10042 if (log_size
> 0 && auto_align
)
10043 mips_align (log_size
, 0, label
);
10044 mips_clear_insn_labels ();
10045 cons (1 << log_size
);
10049 s_float_cons (type
)
10054 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10056 mips_emit_delays (false);
10061 mips_align (3, 0, label
);
10063 mips_align (2, 0, label
);
10066 mips_clear_insn_labels ();
10071 /* Handle .globl. We need to override it because on Irix 5 you are
10074 where foo is an undefined symbol, to mean that foo should be
10075 considered to be the address of a function. */
10079 int x ATTRIBUTE_UNUSED
;
10086 name
= input_line_pointer
;
10087 c
= get_symbol_end ();
10088 symbolP
= symbol_find_or_make (name
);
10089 *input_line_pointer
= c
;
10090 SKIP_WHITESPACE ();
10092 /* On Irix 5, every global symbol that is not explicitly labelled as
10093 being a function is apparently labelled as being an object. */
10096 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10101 secname
= input_line_pointer
;
10102 c
= get_symbol_end ();
10103 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10105 as_bad (_("%s: no such section"), secname
);
10106 *input_line_pointer
= c
;
10108 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10109 flag
= BSF_FUNCTION
;
10112 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10114 S_SET_EXTERNAL (symbolP
);
10115 demand_empty_rest_of_line ();
10120 int x ATTRIBUTE_UNUSED
;
10125 opt
= input_line_pointer
;
10126 c
= get_symbol_end ();
10130 /* FIXME: What does this mean? */
10132 else if (strncmp (opt
, "pic", 3) == 0)
10136 i
= atoi (opt
+ 3);
10140 mips_pic
= SVR4_PIC
;
10142 as_bad (_(".option pic%d not supported"), i
);
10144 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10146 if (g_switch_seen
&& g_switch_value
!= 0)
10147 as_warn (_("-G may not be used with SVR4 PIC code"));
10148 g_switch_value
= 0;
10149 bfd_set_gp_size (stdoutput
, 0);
10153 as_warn (_("Unrecognized option \"%s\""), opt
);
10155 *input_line_pointer
= c
;
10156 demand_empty_rest_of_line ();
10159 /* This structure is used to hold a stack of .set values. */
10161 struct mips_option_stack
{
10162 struct mips_option_stack
*next
;
10163 struct mips_set_options options
;
10166 static struct mips_option_stack
*mips_opts_stack
;
10168 /* Handle the .set pseudo-op. */
10172 int x ATTRIBUTE_UNUSED
;
10174 char *name
= input_line_pointer
, ch
;
10176 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10177 input_line_pointer
++;
10178 ch
= *input_line_pointer
;
10179 *input_line_pointer
= '\0';
10181 if (strcmp (name
, "reorder") == 0)
10183 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10185 /* If we still have pending nops, we can discard them. The
10186 usual nop handling will insert any that are still
10188 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10189 * (mips_opts
.mips16
? 2 : 4));
10190 prev_nop_frag
= NULL
;
10192 mips_opts
.noreorder
= 0;
10194 else if (strcmp (name
, "noreorder") == 0)
10196 mips_emit_delays (true);
10197 mips_opts
.noreorder
= 1;
10198 mips_any_noreorder
= 1;
10200 else if (strcmp (name
, "at") == 0)
10202 mips_opts
.noat
= 0;
10204 else if (strcmp (name
, "noat") == 0)
10206 mips_opts
.noat
= 1;
10208 else if (strcmp (name
, "macro") == 0)
10210 mips_opts
.warn_about_macros
= 0;
10212 else if (strcmp (name
, "nomacro") == 0)
10214 if (mips_opts
.noreorder
== 0)
10215 as_bad (_("`noreorder' must be set before `nomacro'"));
10216 mips_opts
.warn_about_macros
= 1;
10218 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10220 mips_opts
.nomove
= 0;
10222 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10224 mips_opts
.nomove
= 1;
10226 else if (strcmp (name
, "bopt") == 0)
10228 mips_opts
.nobopt
= 0;
10230 else if (strcmp (name
, "nobopt") == 0)
10232 mips_opts
.nobopt
= 1;
10234 else if (strcmp (name
, "mips16") == 0
10235 || strcmp (name
, "MIPS-16") == 0)
10236 mips_opts
.mips16
= 1;
10237 else if (strcmp (name
, "nomips16") == 0
10238 || strcmp (name
, "noMIPS-16") == 0)
10239 mips_opts
.mips16
= 0;
10240 else if (strncmp (name
, "mips", 4) == 0)
10244 /* Permit the user to change the ISA on the fly. Needless to
10245 say, misuse can cause serious problems. */
10246 isa
= atoi (name
+ 4);
10249 case 0: mips_opts
.isa
= file_mips_isa
; break;
10250 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
10251 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
10252 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
10253 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
10254 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
10255 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
10256 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
10257 default: as_bad (_("unknown ISA level")); break;
10260 else if (strcmp (name
, "autoextend") == 0)
10261 mips_opts
.noautoextend
= 0;
10262 else if (strcmp (name
, "noautoextend") == 0)
10263 mips_opts
.noautoextend
= 1;
10264 else if (strcmp (name
, "push") == 0)
10266 struct mips_option_stack
*s
;
10268 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10269 s
->next
= mips_opts_stack
;
10270 s
->options
= mips_opts
;
10271 mips_opts_stack
= s
;
10273 else if (strcmp (name
, "pop") == 0)
10275 struct mips_option_stack
*s
;
10277 s
= mips_opts_stack
;
10279 as_bad (_(".set pop with no .set push"));
10282 /* If we're changing the reorder mode we need to handle
10283 delay slots correctly. */
10284 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10285 mips_emit_delays (true);
10286 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10288 if (prev_nop_frag
!= NULL
)
10290 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10291 * (mips_opts
.mips16
? 2 : 4));
10292 prev_nop_frag
= NULL
;
10296 mips_opts
= s
->options
;
10297 mips_opts_stack
= s
->next
;
10303 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10305 *input_line_pointer
= ch
;
10306 demand_empty_rest_of_line ();
10309 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10310 .option pic2. It means to generate SVR4 PIC calls. */
10313 s_abicalls (ignore
)
10314 int ignore ATTRIBUTE_UNUSED
;
10316 mips_pic
= SVR4_PIC
;
10317 if (USE_GLOBAL_POINTER_OPT
)
10319 if (g_switch_seen
&& g_switch_value
!= 0)
10320 as_warn (_("-G may not be used with SVR4 PIC code"));
10321 g_switch_value
= 0;
10323 bfd_set_gp_size (stdoutput
, 0);
10324 demand_empty_rest_of_line ();
10327 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10328 PIC code. It sets the $gp register for the function based on the
10329 function address, which is in the register named in the argument.
10330 This uses a relocation against _gp_disp, which is handled specially
10331 by the linker. The result is:
10332 lui $gp,%hi(_gp_disp)
10333 addiu $gp,$gp,%lo(_gp_disp)
10334 addu $gp,$gp,.cpload argument
10335 The .cpload argument is normally $25 == $t9. */
10339 int ignore ATTRIBUTE_UNUSED
;
10344 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10345 if (mips_pic
!= SVR4_PIC
)
10351 /* .cpload should be a in .set noreorder section. */
10352 if (mips_opts
.noreorder
== 0)
10353 as_warn (_(".cpload not in noreorder section"));
10355 ex
.X_op
= O_symbol
;
10356 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10357 ex
.X_op_symbol
= NULL
;
10358 ex
.X_add_number
= 0;
10360 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10361 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10363 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10364 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10365 (int) BFD_RELOC_LO16
);
10367 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10368 GP
, GP
, tc_get_register (0));
10370 demand_empty_rest_of_line ();
10373 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10374 offset from $sp. The offset is remembered, and after making a PIC
10375 call $gp is restored from that location. */
10378 s_cprestore (ignore
)
10379 int ignore ATTRIBUTE_UNUSED
;
10384 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10385 if (mips_pic
!= SVR4_PIC
)
10391 mips_cprestore_offset
= get_absolute_expression ();
10393 ex
.X_op
= O_constant
;
10394 ex
.X_add_symbol
= NULL
;
10395 ex
.X_op_symbol
= NULL
;
10396 ex
.X_add_number
= mips_cprestore_offset
;
10398 macro_build ((char *) NULL
, &icnt
, &ex
,
10399 ((bfd_arch_bits_per_address (stdoutput
) == 32
10400 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10402 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10404 demand_empty_rest_of_line ();
10407 /* Handle the .gpword pseudo-op. This is used when generating PIC
10408 code. It generates a 32 bit GP relative reloc. */
10412 int ignore ATTRIBUTE_UNUSED
;
10418 /* When not generating PIC code, this is treated as .word. */
10419 if (mips_pic
!= SVR4_PIC
)
10425 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10426 mips_emit_delays (true);
10428 mips_align (2, 0, label
);
10429 mips_clear_insn_labels ();
10433 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10435 as_bad (_("Unsupported use of .gpword"));
10436 ignore_rest_of_line ();
10440 md_number_to_chars (p
, (valueT
) 0, 4);
10441 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10442 BFD_RELOC_MIPS_GPREL32
);
10444 demand_empty_rest_of_line ();
10447 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10448 tables in SVR4 PIC code. */
10452 int ignore ATTRIBUTE_UNUSED
;
10457 /* This is ignored when not generating SVR4 PIC code. */
10458 if (mips_pic
!= SVR4_PIC
)
10464 /* Add $gp to the register named as an argument. */
10465 reg
= tc_get_register (0);
10466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10467 ((bfd_arch_bits_per_address (stdoutput
) == 32
10468 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10469 ? "addu" : "daddu"),
10470 "d,v,t", reg
, reg
, GP
);
10472 demand_empty_rest_of_line ();
10475 /* Handle the .insn pseudo-op. This marks instruction labels in
10476 mips16 mode. This permits the linker to handle them specially,
10477 such as generating jalx instructions when needed. We also make
10478 them odd for the duration of the assembly, in order to generate the
10479 right sort of code. We will make them even in the adjust_symtab
10480 routine, while leaving them marked. This is convenient for the
10481 debugger and the disassembler. The linker knows to make them odd
10486 int ignore ATTRIBUTE_UNUSED
;
10488 if (mips_opts
.mips16
)
10489 mips16_mark_labels ();
10491 demand_empty_rest_of_line ();
10494 /* Handle a .stabn directive. We need these in order to mark a label
10495 as being a mips16 text label correctly. Sometimes the compiler
10496 will emit a label, followed by a .stabn, and then switch sections.
10497 If the label and .stabn are in mips16 mode, then the label is
10498 really a mips16 text label. */
10504 if (type
== 'n' && mips_opts
.mips16
)
10505 mips16_mark_labels ();
10510 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10514 s_mips_weakext (ignore
)
10515 int ignore ATTRIBUTE_UNUSED
;
10522 name
= input_line_pointer
;
10523 c
= get_symbol_end ();
10524 symbolP
= symbol_find_or_make (name
);
10525 S_SET_WEAK (symbolP
);
10526 *input_line_pointer
= c
;
10528 SKIP_WHITESPACE ();
10530 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10532 if (S_IS_DEFINED (symbolP
))
10534 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10535 S_GET_NAME (symbolP
));
10536 ignore_rest_of_line ();
10540 if (*input_line_pointer
== ',')
10542 ++input_line_pointer
;
10543 SKIP_WHITESPACE ();
10547 if (exp
.X_op
!= O_symbol
)
10549 as_bad ("bad .weakext directive");
10550 ignore_rest_of_line();
10553 symbol_set_value_expression (symbolP
, &exp
);
10556 demand_empty_rest_of_line ();
10559 /* Parse a register string into a number. Called from the ECOFF code
10560 to parse .frame. The argument is non-zero if this is the frame
10561 register, so that we can record it in mips_frame_reg. */
10564 tc_get_register (frame
)
10569 SKIP_WHITESPACE ();
10570 if (*input_line_pointer
++ != '$')
10572 as_warn (_("expected `$'"));
10575 else if (isdigit ((unsigned char) *input_line_pointer
))
10577 reg
= get_absolute_expression ();
10578 if (reg
< 0 || reg
>= 32)
10580 as_warn (_("Bad register number"));
10586 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10588 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10590 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10592 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10596 as_warn (_("Unrecognized register name"));
10599 input_line_pointer
+= 2;
10602 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10607 md_section_align (seg
, addr
)
10611 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10614 /* We don't need to align ELF sections to the full alignment.
10615 However, Irix 5 may prefer that we align them at least to a 16
10616 byte boundary. We don't bother to align the sections if we are
10617 targeted for an embedded system. */
10618 if (strcmp (TARGET_OS
, "elf") == 0)
10624 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10627 /* Utility routine, called from above as well. If called while the
10628 input file is still being read, it's only an approximation. (For
10629 example, a symbol may later become defined which appeared to be
10630 undefined earlier.) */
10633 nopic_need_relax (sym
, before_relaxing
)
10635 int before_relaxing
;
10640 if (USE_GLOBAL_POINTER_OPT
)
10642 const char *symname
;
10645 /* Find out whether this symbol can be referenced off the GP
10646 register. It can be if it is smaller than the -G size or if
10647 it is in the .sdata or .sbss section. Certain symbols can
10648 not be referenced off the GP, although it appears as though
10650 symname
= S_GET_NAME (sym
);
10651 if (symname
!= (const char *) NULL
10652 && (strcmp (symname
, "eprol") == 0
10653 || strcmp (symname
, "etext") == 0
10654 || strcmp (symname
, "_gp") == 0
10655 || strcmp (symname
, "edata") == 0
10656 || strcmp (symname
, "_fbss") == 0
10657 || strcmp (symname
, "_fdata") == 0
10658 || strcmp (symname
, "_ftext") == 0
10659 || strcmp (symname
, "end") == 0
10660 || strcmp (symname
, "_gp_disp") == 0))
10662 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10664 #ifndef NO_ECOFF_DEBUGGING
10665 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10666 && (symbol_get_obj (sym
)->ecoff_extern_size
10667 <= g_switch_value
))
10669 /* We must defer this decision until after the whole
10670 file has been read, since there might be a .extern
10671 after the first use of this symbol. */
10672 || (before_relaxing
10673 #ifndef NO_ECOFF_DEBUGGING
10674 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10676 && S_GET_VALUE (sym
) == 0)
10677 || (S_GET_VALUE (sym
) != 0
10678 && S_GET_VALUE (sym
) <= g_switch_value
)))
10682 const char *segname
;
10684 segname
= segment_name (S_GET_SEGMENT (sym
));
10685 assert (strcmp (segname
, ".lit8") != 0
10686 && strcmp (segname
, ".lit4") != 0);
10687 change
= (strcmp (segname
, ".sdata") != 0
10688 && strcmp (segname
, ".sbss") != 0
10689 && strncmp (segname
, ".sdata.", 7) != 0
10690 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10695 /* We are not optimizing for the GP register. */
10699 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10700 extended opcode. SEC is the section the frag is in. */
10703 mips16_extended_frag (fragp
, sec
, stretch
)
10709 register const struct mips16_immed_operand
*op
;
10711 int mintiny
, maxtiny
;
10714 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10716 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10719 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10720 op
= mips16_immed_operands
;
10721 while (op
->type
!= type
)
10724 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10729 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10732 maxtiny
= 1 << op
->nbits
;
10737 maxtiny
= (1 << op
->nbits
) - 1;
10742 mintiny
= - (1 << (op
->nbits
- 1));
10743 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10746 /* We can't always call S_GET_VALUE here, because we don't want to
10747 lock in a particular frag address. */
10748 if (symbol_constant_p (fragp
->fr_symbol
))
10750 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10751 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10752 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10754 else if (symbol_equated_p (fragp
->fr_symbol
)
10755 && (symbol_constant_p
10756 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10760 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10761 val
= (S_GET_VALUE (eqsym
)
10762 + symbol_get_frag (eqsym
)->fr_address
10763 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10764 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10765 symsec
= S_GET_SEGMENT (eqsym
);
10774 /* We won't have the section when we are called from
10775 mips_relax_frag. However, we will always have been called
10776 from md_estimate_size_before_relax first. If this is a
10777 branch to a different section, we mark it as such. If SEC is
10778 NULL, and the frag is not marked, then it must be a branch to
10779 the same section. */
10782 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10789 fragp
->fr_subtype
=
10790 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10792 /* FIXME: We should support this, and let the linker
10793 catch branches and loads that are out of range. */
10794 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10795 _("unsupported PC relative reference to different section"));
10801 /* In this case, we know for sure that the symbol fragment is in
10802 the same section. If the fr_address of the symbol fragment
10803 is greater then the address of this fragment we want to add
10804 in STRETCH in order to get a better estimate of the address.
10805 This particularly matters because of the shift bits. */
10807 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10808 >= fragp
->fr_address
))
10812 /* Adjust stretch for any alignment frag. Note that if have
10813 been expanding the earlier code, the symbol may be
10814 defined in what appears to be an earlier frag. FIXME:
10815 This doesn't handle the fr_subtype field, which specifies
10816 a maximum number of bytes to skip when doing an
10819 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10822 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10825 stretch
= - ((- stretch
)
10826 & ~ ((1 << (int) f
->fr_offset
) - 1));
10828 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10837 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10839 /* The base address rules are complicated. The base address of
10840 a branch is the following instruction. The base address of a
10841 PC relative load or add is the instruction itself, but if it
10842 is in a delay slot (in which case it can not be extended) use
10843 the address of the instruction whose delay slot it is in. */
10844 if (type
== 'p' || type
== 'q')
10848 /* If we are currently assuming that this frag should be
10849 extended, then, the current address is two bytes
10851 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10854 /* Ignore the low bit in the target, since it will be set
10855 for a text label. */
10856 if ((val
& 1) != 0)
10859 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10861 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10864 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10866 /* Branch offsets have an implicit 0 in the lowest bit. */
10867 if (type
== 'p' || type
== 'q')
10870 /* If any of the shifted bits are set, we must use an extended
10871 opcode. If the address depends on the size of this
10872 instruction, this can lead to a loop, so we arrange to always
10873 use an extended opcode. We only check this when we are in
10874 the main relaxation loop, when SEC is NULL. */
10875 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10877 fragp
->fr_subtype
=
10878 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10882 /* If we are about to mark a frag as extended because the value
10883 is precisely maxtiny + 1, then there is a chance of an
10884 infinite loop as in the following code:
10889 In this case when the la is extended, foo is 0x3fc bytes
10890 away, so the la can be shrunk, but then foo is 0x400 away, so
10891 the la must be extended. To avoid this loop, we mark the
10892 frag as extended if it was small, and is about to become
10893 extended with a value of maxtiny + 1. */
10894 if (val
== ((maxtiny
+ 1) << op
->shift
)
10895 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10898 fragp
->fr_subtype
=
10899 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10903 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10904 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10906 if ((val
& ((1 << op
->shift
) - 1)) != 0
10907 || val
< (mintiny
<< op
->shift
)
10908 || val
> (maxtiny
<< op
->shift
))
10914 /* Estimate the size of a frag before relaxing. Unless this is the
10915 mips16, we are not really relaxing here, and the final size is
10916 encoded in the subtype information. For the mips16, we have to
10917 decide whether we are using an extended opcode or not. */
10920 md_estimate_size_before_relax (fragp
, segtype
)
10925 boolean linkonce
= false;
10927 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10929 if (mips16_extended_frag (fragp
, segtype
, 0))
10931 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10936 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10941 if (mips_pic
== NO_PIC
)
10943 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10945 else if (mips_pic
== SVR4_PIC
)
10950 sym
= fragp
->fr_symbol
;
10952 /* Handle the case of a symbol equated to another symbol. */
10953 while (symbol_equated_p (sym
)
10954 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10958 /* It's possible to get a loop here in a badly written
10960 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
10966 symsec
= S_GET_SEGMENT (sym
);
10968 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
10969 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
10971 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
10975 /* The GNU toolchain uses an extension for ELF: a section
10976 beginning with the magic string .gnu.linkonce is a linkonce
10978 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
10979 sizeof ".gnu.linkonce" - 1) == 0)
10983 /* This must duplicate the test in adjust_reloc_syms. */
10984 change
= (symsec
!= &bfd_und_section
10985 && symsec
!= &bfd_abs_section
10986 && ! bfd_is_com_section (symsec
)
10989 /* A weak symbol is treated as external. */
10990 && ! S_IS_WEAK (sym
)
10999 /* Record the offset to the first reloc in the fr_opcode field.
11000 This lets md_convert_frag and tc_gen_reloc know that the code
11001 must be expanded. */
11002 fragp
->fr_opcode
= (fragp
->fr_literal
11004 - RELAX_OLD (fragp
->fr_subtype
)
11005 + RELAX_RELOC1 (fragp
->fr_subtype
));
11006 /* FIXME: This really needs as_warn_where. */
11007 if (RELAX_WARN (fragp
->fr_subtype
))
11008 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11014 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11017 /* This is called to see whether a reloc against a defined symbol
11018 should be converted into a reloc against a section. Don't adjust
11019 MIPS16 jump relocations, so we don't have to worry about the format
11020 of the offset in the .o file. Don't adjust relocations against
11021 mips16 symbols, so that the linker can find them if it needs to set
11025 mips_fix_adjustable (fixp
)
11028 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11030 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11031 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11033 if (fixp
->fx_addsy
== NULL
)
11036 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11037 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11038 && fixp
->fx_subsy
== NULL
)
11044 /* Translate internal representation of relocation info to BFD target
11048 tc_gen_reloc (section
, fixp
)
11049 asection
*section ATTRIBUTE_UNUSED
;
11052 static arelent
*retval
[4];
11054 bfd_reloc_code_real_type code
;
11056 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11059 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11060 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11061 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11063 if (mips_pic
== EMBEDDED_PIC
11064 && SWITCH_TABLE (fixp
))
11066 /* For a switch table entry we use a special reloc. The addend
11067 is actually the difference between the reloc address and the
11069 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11070 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11071 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11072 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11074 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11075 reloc
->addend
= fixp
->fx_addnumber
;
11076 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11078 /* We use a special addend for an internal RELLO reloc. */
11079 if (symbol_section_p (fixp
->fx_addsy
))
11080 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11082 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11084 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11086 assert (fixp
->fx_next
!= NULL
11087 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11088 /* We use a special addend for an internal RELHI reloc. The
11089 reloc is relative to the RELLO; adjust the addend
11091 if (symbol_section_p (fixp
->fx_addsy
))
11092 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11093 + fixp
->fx_next
->fx_where
11094 - S_GET_VALUE (fixp
->fx_subsy
));
11096 reloc
->addend
= (fixp
->fx_addnumber
11097 + fixp
->fx_next
->fx_frag
->fr_address
11098 + fixp
->fx_next
->fx_where
);
11102 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11103 /* A gruesome hack which is a result of the gruesome gas reloc
11105 reloc
->addend
= reloc
->address
;
11107 reloc
->addend
= -reloc
->address
;
11110 /* If this is a variant frag, we may need to adjust the existing
11111 reloc and generate a new one. */
11112 if (fixp
->fx_frag
->fr_opcode
!= NULL
11113 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11114 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11115 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11116 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11117 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11118 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11119 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11123 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11125 /* If this is not the last reloc in this frag, then we have two
11126 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11127 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11128 the second one handle all of them. */
11129 if (fixp
->fx_next
!= NULL
11130 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11132 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11133 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11134 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11135 && (fixp
->fx_next
->fx_r_type
11136 == BFD_RELOC_MIPS_GOT_LO16
))
11137 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11138 && (fixp
->fx_next
->fx_r_type
11139 == BFD_RELOC_MIPS_CALL_LO16
)));
11144 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11145 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11146 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11148 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11149 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11150 reloc2
->address
= (reloc
->address
11151 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11152 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11153 reloc2
->addend
= fixp
->fx_addnumber
;
11154 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11155 assert (reloc2
->howto
!= NULL
);
11157 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11161 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11164 reloc3
->address
+= 4;
11167 if (mips_pic
== NO_PIC
)
11169 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11170 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11172 else if (mips_pic
== SVR4_PIC
)
11174 switch (fixp
->fx_r_type
)
11178 case BFD_RELOC_MIPS_GOT16
:
11180 case BFD_RELOC_MIPS_CALL16
:
11181 case BFD_RELOC_MIPS_GOT_LO16
:
11182 case BFD_RELOC_MIPS_CALL_LO16
:
11183 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11191 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11192 to be used in the relocation's section offset. */
11193 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11195 reloc
->address
= reloc
->addend
;
11199 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11200 fixup_segment converted a non-PC relative reloc into a PC
11201 relative reloc. In such a case, we need to convert the reloc
11203 code
= fixp
->fx_r_type
;
11204 if (fixp
->fx_pcrel
)
11209 code
= BFD_RELOC_8_PCREL
;
11212 code
= BFD_RELOC_16_PCREL
;
11215 code
= BFD_RELOC_32_PCREL
;
11218 code
= BFD_RELOC_64_PCREL
;
11220 case BFD_RELOC_8_PCREL
:
11221 case BFD_RELOC_16_PCREL
:
11222 case BFD_RELOC_32_PCREL
:
11223 case BFD_RELOC_64_PCREL
:
11224 case BFD_RELOC_16_PCREL_S2
:
11225 case BFD_RELOC_PCREL_HI16_S
:
11226 case BFD_RELOC_PCREL_LO16
:
11229 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11230 _("Cannot make %s relocation PC relative"),
11231 bfd_get_reloc_code_name (code
));
11235 /* To support a PC relative reloc when generating embedded PIC code
11236 for ECOFF, we use a Cygnus extension. We check for that here to
11237 make sure that we don't let such a reloc escape normally. */
11238 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11239 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11240 && code
== BFD_RELOC_16_PCREL_S2
11241 && mips_pic
!= EMBEDDED_PIC
)
11242 reloc
->howto
= NULL
;
11244 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11246 if (reloc
->howto
== NULL
)
11248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11249 _("Can not represent %s relocation in this object file format"),
11250 bfd_get_reloc_code_name (code
));
11257 /* Relax a machine dependent frag. This returns the amount by which
11258 the current size of the frag should change. */
11261 mips_relax_frag (fragp
, stretch
)
11265 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11268 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11270 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11272 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11277 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11279 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11286 /* Convert a machine dependent frag. */
11289 md_convert_frag (abfd
, asec
, fragp
)
11290 bfd
*abfd ATTRIBUTE_UNUSED
;
11297 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11300 register const struct mips16_immed_operand
*op
;
11301 boolean small
, ext
;
11304 unsigned long insn
;
11305 boolean use_extend
;
11306 unsigned short extend
;
11308 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11309 op
= mips16_immed_operands
;
11310 while (op
->type
!= type
)
11313 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11324 resolve_symbol_value (fragp
->fr_symbol
, 1);
11325 val
= S_GET_VALUE (fragp
->fr_symbol
);
11330 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11332 /* The rules for the base address of a PC relative reloc are
11333 complicated; see mips16_extended_frag. */
11334 if (type
== 'p' || type
== 'q')
11339 /* Ignore the low bit in the target, since it will be
11340 set for a text label. */
11341 if ((val
& 1) != 0)
11344 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11346 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11349 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11352 /* Make sure the section winds up with the alignment we have
11355 record_alignment (asec
, op
->shift
);
11359 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11360 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11361 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11362 _("extended instruction in delay slot"));
11364 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11366 if (target_big_endian
)
11367 insn
= bfd_getb16 (buf
);
11369 insn
= bfd_getl16 (buf
);
11371 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11372 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11373 small
, ext
, &insn
, &use_extend
, &extend
);
11377 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11378 fragp
->fr_fix
+= 2;
11382 md_number_to_chars (buf
, insn
, 2);
11383 fragp
->fr_fix
+= 2;
11388 if (fragp
->fr_opcode
== NULL
)
11391 old
= RELAX_OLD (fragp
->fr_subtype
);
11392 new = RELAX_NEW (fragp
->fr_subtype
);
11393 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11396 memcpy (fixptr
- old
, fixptr
, new);
11398 fragp
->fr_fix
+= new - old
;
11404 /* This function is called after the relocs have been generated.
11405 We've been storing mips16 text labels as odd. Here we convert them
11406 back to even for the convenience of the debugger. */
11409 mips_frob_file_after_relocs ()
11412 unsigned int count
, i
;
11414 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11417 syms
= bfd_get_outsymbols (stdoutput
);
11418 count
= bfd_get_symcount (stdoutput
);
11419 for (i
= 0; i
< count
; i
++, syms
++)
11421 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11422 && ((*syms
)->value
& 1) != 0)
11424 (*syms
)->value
&= ~1;
11425 /* If the symbol has an odd size, it was probably computed
11426 incorrectly, so adjust that as well. */
11427 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11428 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11435 /* This function is called whenever a label is defined. It is used
11436 when handling branch delays; if a branch has a label, we assume we
11437 can not move it. */
11440 mips_define_label (sym
)
11443 struct insn_label_list
*l
;
11445 if (free_insn_labels
== NULL
)
11446 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11449 l
= free_insn_labels
;
11450 free_insn_labels
= l
->next
;
11454 l
->next
= insn_labels
;
11458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11460 /* Some special processing for a MIPS ELF file. */
11463 mips_elf_final_processing ()
11465 /* Write out the register information. */
11470 s
.ri_gprmask
= mips_gprmask
;
11471 s
.ri_cprmask
[0] = mips_cprmask
[0];
11472 s
.ri_cprmask
[1] = mips_cprmask
[1];
11473 s
.ri_cprmask
[2] = mips_cprmask
[2];
11474 s
.ri_cprmask
[3] = mips_cprmask
[3];
11475 /* The gp_value field is set by the MIPS ELF backend. */
11477 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11478 ((Elf32_External_RegInfo
*)
11479 mips_regmask_frag
));
11483 Elf64_Internal_RegInfo s
;
11485 s
.ri_gprmask
= mips_gprmask
;
11487 s
.ri_cprmask
[0] = mips_cprmask
[0];
11488 s
.ri_cprmask
[1] = mips_cprmask
[1];
11489 s
.ri_cprmask
[2] = mips_cprmask
[2];
11490 s
.ri_cprmask
[3] = mips_cprmask
[3];
11491 /* The gp_value field is set by the MIPS ELF backend. */
11493 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11494 ((Elf64_External_RegInfo
*)
11495 mips_regmask_frag
));
11498 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11499 sort of BFD interface for this. */
11500 if (mips_any_noreorder
)
11501 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11502 if (mips_pic
!= NO_PIC
)
11503 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11505 /* Set the MIPS ELF ABI flags. */
11506 if (mips_abi_string
== 0)
11508 else if (strcmp (mips_abi_string
, "32") == 0)
11509 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11510 else if (strcmp (mips_abi_string
, "o64") == 0)
11511 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11512 else if (strcmp (mips_abi_string
, "eabi") == 0)
11515 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11517 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11520 if (mips_32bitmode
)
11521 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11524 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11526 typedef struct proc
{
11528 unsigned long reg_mask
;
11529 unsigned long reg_offset
;
11530 unsigned long fpreg_mask
;
11531 unsigned long fpreg_offset
;
11532 unsigned long frame_offset
;
11533 unsigned long frame_reg
;
11534 unsigned long pc_reg
;
11537 static procS cur_proc
;
11538 static procS
*cur_proc_ptr
;
11539 static int numprocs
;
11541 /* When we align code in the .text section of mips16, use the correct two
11542 byte nop pattern of 0x6500 (move $0,$0) */
11545 mips_do_align (n
, fill
, len
, max
)
11548 int len ATTRIBUTE_UNUSED
;
11552 && subseg_text_p (now_seg
)
11554 && mips_opts
.mips16
)
11556 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11557 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11559 frag_align (1, 0, 0);
11561 if (target_big_endian
)
11562 frag_align_pattern (n
, be_nop
, 2, max
);
11564 frag_align_pattern (n
, le_nop
, 2, max
);
11579 /* check for premature end, nesting errors, etc */
11581 as_warn (_("missing `.end' at end of assembly"));
11590 if (*input_line_pointer
== '-')
11592 ++input_line_pointer
;
11595 if (!isdigit ((unsigned char) *input_line_pointer
))
11596 as_bad (_("Expected simple number."));
11597 if (input_line_pointer
[0] == '0')
11599 if (input_line_pointer
[1] == 'x')
11601 input_line_pointer
+= 2;
11602 while (isxdigit ((unsigned char) *input_line_pointer
))
11605 val
|= hex_value (*input_line_pointer
++);
11607 return negative
? -val
: val
;
11611 ++input_line_pointer
;
11612 while (isdigit ((unsigned char) *input_line_pointer
))
11615 val
|= *input_line_pointer
++ - '0';
11617 return negative
? -val
: val
;
11620 if (!isdigit ((unsigned char) *input_line_pointer
))
11622 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11623 *input_line_pointer
, *input_line_pointer
);
11624 as_warn (_("Invalid number"));
11627 while (isdigit ((unsigned char) *input_line_pointer
))
11630 val
+= *input_line_pointer
++ - '0';
11632 return negative
? -val
: val
;
11635 /* The .file directive; just like the usual .file directive, but there
11636 is an initial number which is the ECOFF file index. */
11640 int x ATTRIBUTE_UNUSED
;
11644 line
= get_number ();
11648 /* The .end directive. */
11652 int x ATTRIBUTE_UNUSED
;
11657 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11660 demand_empty_rest_of_line ();
11665 #ifdef BFD_ASSEMBLER
11666 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11671 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11678 as_warn (_(".end not in text section"));
11682 as_warn (_(".end directive without a preceding .ent directive."));
11683 demand_empty_rest_of_line ();
11689 assert (S_GET_NAME (p
));
11690 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11691 as_warn (_(".end symbol does not match .ent symbol."));
11694 as_warn (_(".end directive missing or unknown symbol"));
11696 #ifdef MIPS_STABS_ELF
11698 segT saved_seg
= now_seg
;
11699 subsegT saved_subseg
= now_subseg
;
11700 fragS
*saved_frag
= frag_now
;
11706 dot
= frag_now_fix ();
11708 #ifdef md_flush_pending_output
11709 md_flush_pending_output ();
11713 subseg_set (pdr_seg
, 0);
11715 /* Write the symbol. */
11716 exp
.X_op
= O_symbol
;
11717 exp
.X_add_symbol
= p
;
11718 exp
.X_add_number
= 0;
11719 emit_expr (&exp
, 4);
11721 fragp
= frag_more (7 * 4);
11723 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11724 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11725 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11726 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11727 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11728 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11729 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11731 subseg_set (saved_seg
, saved_subseg
);
11735 cur_proc_ptr
= NULL
;
11738 /* The .aent and .ent directives. */
11748 symbolP
= get_symbol ();
11749 if (*input_line_pointer
== ',')
11750 input_line_pointer
++;
11751 SKIP_WHITESPACE ();
11752 if (isdigit ((unsigned char) *input_line_pointer
)
11753 || *input_line_pointer
== '-')
11754 number
= get_number ();
11756 #ifdef BFD_ASSEMBLER
11757 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11762 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11769 as_warn (_(".ent or .aent not in text section."));
11771 if (!aent
&& cur_proc_ptr
)
11772 as_warn (_("missing `.end'"));
11776 cur_proc_ptr
= &cur_proc
;
11777 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11779 cur_proc_ptr
->isym
= symbolP
;
11781 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11786 demand_empty_rest_of_line ();
11789 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11790 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11791 s_mips_frame is used so that we can set the PDR information correctly.
11792 We can't use the ecoff routines because they make reference to the ecoff
11793 symbol table (in the mdebug section). */
11796 s_mips_frame (ignore
)
11799 #ifdef MIPS_STABS_ELF
11803 if (cur_proc_ptr
== (procS
*) NULL
)
11805 as_warn (_(".frame outside of .ent"));
11806 demand_empty_rest_of_line ();
11810 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11812 SKIP_WHITESPACE ();
11813 if (*input_line_pointer
++ != ','
11814 || get_absolute_expression_and_terminator (&val
) != ',')
11816 as_warn (_("Bad .frame directive"));
11817 --input_line_pointer
;
11818 demand_empty_rest_of_line ();
11822 cur_proc_ptr
->frame_offset
= val
;
11823 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11825 demand_empty_rest_of_line ();
11828 #endif /* MIPS_STABS_ELF */
11831 /* The .fmask and .mask directives. If the mdebug section is present
11832 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11833 embedded targets, s_mips_mask is used so that we can set the PDR
11834 information correctly. We can't use the ecoff routines because they
11835 make reference to the ecoff symbol table (in the mdebug section). */
11838 s_mips_mask (reg_type
)
11841 #ifdef MIPS_STABS_ELF
11844 if (cur_proc_ptr
== (procS
*) NULL
)
11846 as_warn (_(".mask/.fmask outside of .ent"));
11847 demand_empty_rest_of_line ();
11851 if (get_absolute_expression_and_terminator (&mask
) != ',')
11853 as_warn (_("Bad .mask/.fmask directive"));
11854 --input_line_pointer
;
11855 demand_empty_rest_of_line ();
11859 off
= get_absolute_expression ();
11861 if (reg_type
== 'F')
11863 cur_proc_ptr
->fpreg_mask
= mask
;
11864 cur_proc_ptr
->fpreg_offset
= off
;
11868 cur_proc_ptr
->reg_mask
= mask
;
11869 cur_proc_ptr
->reg_offset
= off
;
11872 demand_empty_rest_of_line ();
11874 s_ignore (reg_type
);
11875 #endif /* MIPS_STABS_ELF */
11878 /* The .loc directive. */
11889 assert (now_seg
== text_section
);
11891 lineno
= get_number ();
11892 addroff
= frag_now_fix ();
11894 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11895 S_SET_TYPE (symbolP
, N_SLINE
);
11896 S_SET_OTHER (symbolP
, 0);
11897 S_SET_DESC (symbolP
, lineno
);
11898 symbolP
->sy_segment
= now_seg
;
11902 /* CPU name/ISA/number mapping table.
11904 Entries are grouped by type. The first matching CPU or ISA entry
11905 gets chosen by CPU or ISA, so it should be the 'canonical' name
11906 for that type. Entries after that within the type are sorted
11909 Case is ignored in comparison, so put the canonical entry in the
11910 appropriate case but everything else in lower case to ease eye pain. */
11911 static const struct mips_cpu_info mips_cpu_info_table
[] = {
11913 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
11914 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
11917 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
11920 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
11923 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
11926 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
11927 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
11930 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
11931 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
11934 /* XXX for now, MIPS64 -> MIPS3 because of history */
11935 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
}, /* XXX! */
11938 { "MIPS64", 1, ISA_MIPS64
, CPU_MIPS64
},
11940 { "mips64isa", 1, ISA_MIPS64
, CPU_MIPS64
},
11941 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
11944 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
11945 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
11946 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
11947 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
11950 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
11951 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
11952 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
11953 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
11956 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
11957 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
11958 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
11961 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
11962 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
11963 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
11964 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
11967 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
11968 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
11971 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
11972 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
11975 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
11976 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
11977 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
11978 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
11981 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
11982 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
11985 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
11986 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
11987 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
11988 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
11991 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
11992 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
11993 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
11994 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
11997 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
11998 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
11999 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
12000 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
12003 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12004 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12005 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12006 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
12009 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
12010 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
12011 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
12012 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
12015 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
12016 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
12017 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
12018 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
12021 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
12022 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
12023 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
12024 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
12025 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
12026 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
12027 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
12028 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
12029 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
12030 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
12031 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
12032 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
12034 /* MIPS32 4K CPU */
12035 { "MIPS32-4K", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12036 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12037 { "4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12038 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12039 { "mips32-4kc", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12040 { "mips32-4km", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12041 { "mips32-4kp", 0, ISA_MIPS32
, CPU_MIPS32_4K
, },
12043 /* SiByte SB-1 CPU */
12044 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
12045 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
12046 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
12047 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
12050 { NULL
, 0, 0, 0, },
12053 static const struct mips_cpu_info
*
12054 mips_cpu_info_from_name (name
)
12059 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12060 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
12061 return (&mips_cpu_info_table
[i
]);
12066 static const struct mips_cpu_info
*
12067 mips_cpu_info_from_isa (isa
)
12072 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12073 if (mips_cpu_info_table
[i
].is_isa
12074 && isa
== mips_cpu_info_table
[i
].isa
)
12075 return (&mips_cpu_info_table
[i
]);
12080 static const struct mips_cpu_info
*
12081 mips_cpu_info_from_cpu (cpu
)
12086 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
12087 if (!mips_cpu_info_table
[i
].is_isa
12088 && cpu
== mips_cpu_info_table
[i
].cpu
)
12089 return (&mips_cpu_info_table
[i
]);