1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-vr4320 */
207 /* Whether NEC vr4320 instructions are permitted. */
208 static int mips_4320
= -1;
210 /* end-sanitize-vr4320 */
211 /* start-sanitize-vr5400 */
212 /* Whether NEC vr5400 instructions are permitted. */
213 static int mips_5400
= -1;
215 /* end-sanitize-vr5400 */
216 /* start-sanitize-r5900 */
217 /* Whether Toshiba r5900 instructions are permitted. */
218 static int mips_5900
= -1;
220 /* end-sanitize-r5900 */
221 /* Whether Toshiba r3900 instructions are permitted. */
222 static int mips_3900
= -1;
224 /* start-sanitize-tx49 */
225 /* Whether Toshiba r4900 instructions are permitted. */
226 static int mips_4900
= -1;
228 /* end-sanitize-tx49 */
229 /* start-sanitize-tx19 */
230 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
231 The tx19 related options and configuration bits are handled by
233 /* end-sanitize-tx19 */
235 /* Whether the processor uses hardware interlocks to protect
236 reads from the HI and LO registers, and thus does not
237 require nops to be inserted. */
238 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \
239 /* start-sanitize-tx49 */ \
240 || mips_cpu == 4900 || mips_4900 \
241 /* end-sanitize-tx49 */ \
242 /* start-sanitize-vr4320 */ \
243 || mips_cpu == 4320 \
244 /* end-sanitize-vr4320 */ \
245 /* start-sanitize-vr5400 */ \
246 || mips_cpu == 5400 \
247 /* end-sanitize-vr5400 */ \
250 /* Whether the processor uses hardware interlocks to protect reads
251 from the GPRs, and thus does not require nops to be inserted. */
252 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
253 /* start-sanitize-vr5400 */
254 #undef gpr_interlocks
255 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900 || mips_5400)
256 /* end-sanitize-vr5400 */
259 /* As with other "interlocks" this is used by hardware that has FP
260 (co-processor) interlocks. */
261 /* Itbl support may require additional care here. */
262 #define cop_interlocks (mips_cpu == 4300 \
263 /* start-sanitize-vr4320 */ \
264 || mips_cpu == 4320 \
265 /* end-sanitize-vr4320 */ \
266 /* start-sanitize-vr5400 */ \
267 || mips_cpu == 5400 \
268 /* end-sanitize-vr5400 */ \
271 /* MIPS PIC level. */
275 /* Do not generate PIC code. */
278 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
279 not sure what it is supposed to do. */
282 /* Generate PIC code as in the SVR4 MIPS ABI. */
285 /* Generate PIC code without using a global offset table: the data
286 segment has a maximum size of 64K, all data references are off
287 the $gp register, and all text references are PC relative. This
288 is used on some embedded systems. */
292 static enum mips_pic_level mips_pic
;
294 /* 1 if we should generate 32 bit offsets from the GP register in
295 SVR4_PIC mode. Currently has no meaning in other modes. */
296 static int mips_big_got
;
298 /* 1 if trap instructions should used for overflow rather than break
300 static int mips_trap
;
302 /* Non-zero if any .set noreorder directives were used. */
304 static int mips_any_noreorder
;
306 /* The size of the small data section. */
307 static int g_switch_value
= 8;
308 /* Whether the -G option was used. */
309 static int g_switch_seen
= 0;
314 /* If we can determine in advance that GP optimization won't be
315 possible, we can skip the relaxation stuff that tries to produce
316 GP-relative references. This makes delay slot optimization work
319 This function can only provide a guess, but it seems to work for
320 gcc output. If it guesses wrong, the only loss should be in
321 efficiency; it shouldn't introduce any bugs.
323 I don't know if a fix is needed for the SVR4_PIC mode. I've only
324 fixed it for the non-PIC mode. KR 95/04/07 */
325 static int nopic_need_relax
PARAMS ((symbolS
*, int));
327 /* handle of the OPCODE hash table */
328 static struct hash_control
*op_hash
= NULL
;
330 /* The opcode hash table we use for the mips16. */
331 static struct hash_control
*mips16_op_hash
= NULL
;
333 /* This array holds the chars that always start a comment. If the
334 pre-processor is disabled, these aren't very useful */
335 const char comment_chars
[] = "#";
337 /* This array holds the chars that only start a comment at the beginning of
338 a line. If the line seems to have the form '# 123 filename'
339 .line and .file directives will appear in the pre-processed output */
340 /* Note that input_file.c hand checks for '#' at the beginning of the
341 first line of the input file. This is because the compiler outputs
342 #NO_APP at the beginning of its output. */
343 /* Also note that C style comments are always supported. */
344 const char line_comment_chars
[] = "#";
346 /* This array holds machine specific line separator characters. */
347 const char line_separator_chars
[] = "";
349 /* Chars that can be used to separate mant from exp in floating point nums */
350 const char EXP_CHARS
[] = "eE";
352 /* Chars that mean this number is a floating point constant */
355 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
357 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
358 changed in read.c . Ideally it shouldn't have to know about it at all,
359 but nothing is ideal around here.
362 static char *insn_error
;
364 static int auto_align
= 1;
366 /* When outputting SVR4 PIC code, the assembler needs to know the
367 offset in the stack frame from which to restore the $gp register.
368 This is set by the .cprestore pseudo-op, and saved in this
370 static offsetT mips_cprestore_offset
= -1;
372 /* This is the register which holds the stack frame, as set by the
373 .frame pseudo-op. This is needed to implement .cprestore. */
374 static int mips_frame_reg
= SP
;
376 /* To output NOP instructions correctly, we need to keep information
377 about the previous two instructions. */
379 /* Whether we are optimizing. The default value of 2 means to remove
380 unneeded NOPs and swap branch instructions when possible. A value
381 of 1 means to not swap branches. A value of 0 means to always
383 static int mips_optimize
= 2;
385 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
386 equivalent to seeing no -g option at all. */
387 static int mips_debug
= 0;
389 /* The previous instruction. */
390 static struct mips_cl_insn prev_insn
;
392 /* The instruction before prev_insn. */
393 static struct mips_cl_insn prev_prev_insn
;
395 /* If we don't want information for prev_insn or prev_prev_insn, we
396 point the insn_mo field at this dummy integer. */
397 static const struct mips_opcode dummy_opcode
= { 0 };
399 /* Non-zero if prev_insn is valid. */
400 static int prev_insn_valid
;
402 /* The frag for the previous instruction. */
403 static struct frag
*prev_insn_frag
;
405 /* The offset into prev_insn_frag for the previous instruction. */
406 static long prev_insn_where
;
408 /* The reloc type for the previous instruction, if any. */
409 static bfd_reloc_code_real_type prev_insn_reloc_type
;
411 /* The reloc for the previous instruction, if any. */
412 static fixS
*prev_insn_fixp
;
414 /* Non-zero if the previous instruction was in a delay slot. */
415 static int prev_insn_is_delay_slot
;
417 /* Non-zero if the previous instruction was in a .set noreorder. */
418 static int prev_insn_unreordered
;
420 /* Non-zero if the previous instruction uses an extend opcode (if
422 static int prev_insn_extended
;
424 /* Non-zero if the previous previous instruction was in a .set
426 static int prev_prev_insn_unreordered
;
428 /* If this is set, it points to a frag holding nop instructions which
429 were inserted before the start of a noreorder section. If those
430 nops turn out to be unnecessary, the size of the frag can be
432 static fragS
*prev_nop_frag
;
434 /* The number of nop instructions we created in prev_nop_frag. */
435 static int prev_nop_frag_holds
;
437 /* The number of nop instructions that we know we need in
439 static int prev_nop_frag_required
;
441 /* The number of instructions we've seen since prev_nop_frag. */
442 static int prev_nop_frag_since
;
444 /* For ECOFF and ELF, relocations against symbols are done in two
445 parts, with a HI relocation and a LO relocation. Each relocation
446 has only 16 bits of space to store an addend. This means that in
447 order for the linker to handle carries correctly, it must be able
448 to locate both the HI and the LO relocation. This means that the
449 relocations must appear in order in the relocation table.
451 In order to implement this, we keep track of each unmatched HI
452 relocation. We then sort them so that they immediately precede the
453 corresponding LO relocation. */
458 struct mips_hi_fixup
*next
;
461 /* The section this fixup is in. */
465 /* The list of unmatched HI relocs. */
467 static struct mips_hi_fixup
*mips_hi_fixup_list
;
469 /* Map normal MIPS register numbers to mips16 register numbers. */
471 #define X ILLEGAL_REG
472 static const int mips32_to_16_reg_map
[] =
474 X
, X
, 2, 3, 4, 5, 6, 7,
475 X
, X
, X
, X
, X
, X
, X
, X
,
476 0, 1, X
, X
, X
, X
, X
, X
,
477 X
, X
, X
, X
, X
, X
, X
, X
481 /* Map mips16 register numbers to normal MIPS register numbers. */
483 static const int mips16_to_32_reg_map
[] =
485 16, 17, 2, 3, 4, 5, 6, 7
488 /* Since the MIPS does not have multiple forms of PC relative
489 instructions, we do not have to do relaxing as is done on other
490 platforms. However, we do have to handle GP relative addressing
491 correctly, which turns out to be a similar problem.
493 Every macro that refers to a symbol can occur in (at least) two
494 forms, one with GP relative addressing and one without. For
495 example, loading a global variable into a register generally uses
496 a macro instruction like this:
498 If i can be addressed off the GP register (this is true if it is in
499 the .sbss or .sdata section, or if it is known to be smaller than
500 the -G argument) this will generate the following instruction:
502 This instruction will use a GPREL reloc. If i can not be addressed
503 off the GP register, the following instruction sequence will be used:
506 In this case the first instruction will have a HI16 reloc, and the
507 second reloc will have a LO16 reloc. Both relocs will be against
510 The issue here is that we may not know whether i is GP addressable
511 until after we see the instruction that uses it. Therefore, we
512 want to be able to choose the final instruction sequence only at
513 the end of the assembly. This is similar to the way other
514 platforms choose the size of a PC relative instruction only at the
517 When generating position independent code we do not use GP
518 addressing in quite the same way, but the issue still arises as
519 external symbols and local symbols must be handled differently.
521 We handle these issues by actually generating both possible
522 instruction sequences. The longer one is put in a frag_var with
523 type rs_machine_dependent. We encode what to do with the frag in
524 the subtype field. We encode (1) the number of existing bytes to
525 replace, (2) the number of new bytes to use, (3) the offset from
526 the start of the existing bytes to the first reloc we must generate
527 (that is, the offset is applied from the start of the existing
528 bytes after they are replaced by the new bytes, if any), (4) the
529 offset from the start of the existing bytes to the second reloc,
530 (5) whether a third reloc is needed (the third reloc is always four
531 bytes after the second reloc), and (6) whether to warn if this
532 variant is used (this is sometimes needed if .set nomacro or .set
533 noat is in effect). All these numbers are reasonably small.
535 Generating two instruction sequences must be handled carefully to
536 ensure that delay slots are handled correctly. Fortunately, there
537 are a limited number of cases. When the second instruction
538 sequence is generated, append_insn is directed to maintain the
539 existing delay slot information, so it continues to apply to any
540 code after the second instruction sequence. This means that the
541 second instruction sequence must not impose any requirements not
542 required by the first instruction sequence.
544 These variant frags are then handled in functions called by the
545 machine independent code. md_estimate_size_before_relax returns
546 the final size of the frag. md_convert_frag sets up the final form
547 of the frag. tc_gen_reloc adjust the first reloc and adds a second
549 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
553 | (((reloc1) + 64) << 9) \
554 | (((reloc2) + 64) << 2) \
555 | ((reloc3) ? (1 << 1) : 0) \
557 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
558 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
559 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
560 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
561 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
562 #define RELAX_WARN(i) ((i) & 1)
564 /* For mips16 code, we use an entirely different form of relaxation.
565 mips16 supports two versions of most instructions which take
566 immediate values: a small one which takes some small value, and a
567 larger one which takes a 16 bit value. Since branches also follow
568 this pattern, relaxing these values is required.
570 We can assemble both mips16 and normal MIPS code in a single
571 object. Therefore, we need to support this type of relaxation at
572 the same time that we support the relaxation described above. We
573 use the high bit of the subtype field to distinguish these cases.
575 The information we store for this type of relaxation is the
576 argument code found in the opcode file for this relocation, whether
577 the user explicitly requested a small or extended form, and whether
578 the relocation is in a jump or jal delay slot. That tells us the
579 size of the value, and how it should be stored. We also store
580 whether the fragment is considered to be extended or not. We also
581 store whether this is known to be a branch to a different section,
582 whether we have tried to relax this frag yet, and whether we have
583 ever extended a PC relative fragment because of a shift count. */
584 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
587 | ((small) ? 0x100 : 0) \
588 | ((ext) ? 0x200 : 0) \
589 | ((dslot) ? 0x400 : 0) \
590 | ((jal_dslot) ? 0x800 : 0))
591 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
592 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
593 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
594 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
595 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
596 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
597 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
598 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
599 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
600 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
601 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
602 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
604 /* Prototypes for static functions. */
607 #define internalError() \
608 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
610 #define internalError() as_fatal ("MIPS internal Error");
613 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
615 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
616 unsigned int reg
, enum mips_regclass
class));
617 static int reg_needs_delay
PARAMS ((int));
618 static void mips16_mark_labels
PARAMS ((void));
619 static void append_insn
PARAMS ((char *place
,
620 struct mips_cl_insn
* ip
,
622 bfd_reloc_code_real_type r
,
624 static void mips_no_prev_insn
PARAMS ((int));
625 static void mips_emit_delays
PARAMS ((boolean
));
627 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
628 const char *name
, const char *fmt
,
631 static void macro_build ();
633 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
634 const char *, const char *,
636 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
637 expressionS
* ep
, int regnum
));
638 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
639 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
641 static void load_register
PARAMS ((int *, int, expressionS
*, int));
642 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
643 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
644 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
645 #ifdef LOSING_COMPILER
646 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
648 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
649 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
650 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
651 boolean
, boolean
, unsigned long *,
652 boolean
*, unsigned short *));
653 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
654 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
655 static symbolS
*get_symbol
PARAMS ((void));
656 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
657 static void s_align
PARAMS ((int));
658 static void s_change_sec
PARAMS ((int));
659 static void s_cons
PARAMS ((int));
660 static void s_float_cons
PARAMS ((int));
661 static void s_mips_globl
PARAMS ((int));
662 static void s_option
PARAMS ((int));
663 static void s_mipsset
PARAMS ((int));
664 static void s_abicalls
PARAMS ((int));
665 static void s_cpload
PARAMS ((int));
666 static void s_cprestore
PARAMS ((int));
667 static void s_gpword
PARAMS ((int));
668 static void s_cpadd
PARAMS ((int));
669 static void s_insn
PARAMS ((int));
670 static void md_obj_begin
PARAMS ((void));
671 static void md_obj_end
PARAMS ((void));
672 static long get_number
PARAMS ((void));
673 static void s_ent
PARAMS ((int));
674 static void s_mipsend
PARAMS ((int));
675 static void s_file
PARAMS ((int));
676 static void s_mips_stab
PARAMS ((int));
677 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
679 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
683 The following pseudo-ops from the Kane and Heinrich MIPS book
684 should be defined here, but are currently unsupported: .alias,
685 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
687 The following pseudo-ops from the Kane and Heinrich MIPS book are
688 specific to the type of debugging information being generated, and
689 should be defined by the object format: .aent, .begin, .bend,
690 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
693 The following pseudo-ops from the Kane and Heinrich MIPS book are
694 not MIPS CPU specific, but are also not specific to the object file
695 format. This file is probably the best place to define them, but
696 they are not currently supported: .asm0, .endr, .lab, .repeat,
697 .struct, .weakext. */
699 static const pseudo_typeS mips_pseudo_table
[] =
701 /* MIPS specific pseudo-ops. */
702 {"option", s_option
, 0},
703 {"set", s_mipsset
, 0},
704 {"rdata", s_change_sec
, 'r'},
705 {"sdata", s_change_sec
, 's'},
706 {"livereg", s_ignore
, 0},
707 {"abicalls", s_abicalls
, 0},
708 {"cpload", s_cpload
, 0},
709 {"cprestore", s_cprestore
, 0},
710 {"gpword", s_gpword
, 0},
711 {"cpadd", s_cpadd
, 0},
714 /* Relatively generic pseudo-ops that happen to be used on MIPS
716 {"asciiz", stringer
, 1},
717 {"bss", s_change_sec
, 'b'},
720 {"dword", s_cons
, 3},
722 /* These pseudo-ops are defined in read.c, but must be overridden
723 here for one reason or another. */
724 {"align", s_align
, 0},
726 {"data", s_change_sec
, 'd'},
727 {"double", s_float_cons
, 'd'},
728 {"float", s_float_cons
, 'f'},
729 {"globl", s_mips_globl
, 0},
730 {"global", s_mips_globl
, 0},
731 {"hword", s_cons
, 1},
736 {"short", s_cons
, 1},
737 {"single", s_float_cons
, 'f'},
738 {"stabn", s_mips_stab
, 'n'},
739 {"text", s_change_sec
, 't'},
744 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
745 /* These pseudo-ops should be defined by the object file format.
746 However, a.out doesn't support them, so we have versions here. */
748 {"bgnb", s_ignore
, 0},
749 {"end", s_mipsend
, 0},
750 {"endb", s_ignore
, 0},
753 {"fmask", s_ignore
, 'F'},
754 {"frame", s_ignore
, 0},
755 {"loc", s_ignore
, 0},
756 {"mask", s_ignore
, 'R'},
757 {"verstamp", s_ignore
, 0},
761 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
766 pop_insert (mips_pseudo_table
);
767 if (! ECOFF_DEBUGGING
)
768 pop_insert (mips_nonecoff_pseudo_table
);
771 /* Symbols labelling the current insn. */
773 struct insn_label_list
775 struct insn_label_list
*next
;
779 static struct insn_label_list
*insn_labels
;
780 static struct insn_label_list
*free_insn_labels
;
782 static void mips_clear_insn_labels
PARAMS ((void));
785 mips_clear_insn_labels ()
787 register struct insn_label_list
**pl
;
789 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
795 static char *expr_end
;
797 /* Expressions which appear in instructions. These are set by
800 static expressionS imm_expr
;
801 static expressionS offset_expr
;
803 /* Relocs associated with imm_expr and offset_expr. */
805 static bfd_reloc_code_real_type imm_reloc
;
806 static bfd_reloc_code_real_type offset_reloc
;
808 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
810 static boolean imm_unmatched_hi
;
812 /* These are set by mips16_ip if an explicit extension is used. */
814 static boolean mips16_small
, mips16_ext
;
817 * This function is called once, at assembler startup time. It should
818 * set up all the tables, etc. that the MD part of the assembler will need.
824 register const char *retval
= NULL
;
825 register unsigned int i
= 0;
831 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
833 a
= xmalloc (sizeof TARGET_CPU
);
834 strcpy (a
, TARGET_CPU
);
835 a
[(sizeof TARGET_CPU
) - 3] = '\0';
841 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
842 just the generic 'mips', in which case set mips_cpu based
843 on the given ISA, if any. */
845 if (strcmp (cpu
, "mips") == 0)
847 if (mips_opts
.isa
< 0)
850 else if (mips_opts
.isa
== 2)
853 else if (mips_opts
.isa
== 3)
856 else if (mips_opts
.isa
== 4)
863 else if (strcmp (cpu
, "r3900") == 0
864 || strcmp (cpu
, "mipstx39") == 0
865 /* start-sanitize-tx19 */
866 || strcmp (cpu
, "r1900") == 0
867 || strcmp (cpu
, "mipstx19") == 0
868 /* end-sanitize-tx19 */
872 else if (strcmp (cpu
, "r6000") == 0
873 || strcmp (cpu
, "mips2") == 0)
876 else if (strcmp (cpu
, "mips64") == 0
877 || strcmp (cpu
, "r4000") == 0
878 || strcmp (cpu
, "mips3") == 0)
881 else if (strcmp (cpu
, "r4400") == 0)
884 else if (strcmp (cpu
, "mips64orion") == 0
885 || strcmp (cpu
, "r4600") == 0)
888 else if (strcmp (cpu
, "r4650") == 0)
891 else if (strcmp (cpu
, "mips64vr4300") == 0)
894 /* start-sanitize-vr4320 */
895 else if (strcmp (cpu
, "r4320") == 0
896 || strcmp (cpu
, "mips64vr4320") == 0)
899 /* end-sanitize-vr4320 */
900 else if (strcmp (cpu
, "mips64vr4100") == 0)
903 else if (strcmp (cpu
, "r4010") == 0)
906 /* start-sanitize-tx49 */
907 else if (strcmp (cpu
, "mips64tx49") == 0)
909 /* end-sanitize-tx49 */
911 else if (strcmp (cpu
, "r5000") == 0
912 || strcmp (cpu
, "mips64vr5000") == 0)
915 /* start-sanitize-vr5400 */
916 else if (strcmp (cpu
, "r5400") == 0
917 || strcmp (cpu
, "mips64vr5400") == 0)
919 /* end-sanitize-vr5400 */
921 /* start-sanitize-r5900 */
922 else if (strcmp (cpu
, "r5900") == 0
923 || strcmp (cpu
, "mips64r5900") == 0)
925 /* end-sanitize-r5900 */
927 else if (strcmp (cpu
, "r8000") == 0
928 || strcmp (cpu
, "mips4") == 0)
931 else if (strcmp (cpu
, "r10000") == 0)
934 else if (strcmp (cpu
, "mips16") == 0)
935 mips_cpu
= 0; /* FIXME */
941 if (mips_opts
.isa
== -1)
947 else if (mips_cpu
== 6000
951 else if (mips_cpu
== 4000
955 /* start-sanitize-vr4320 */
957 /* end-sanitize-vr4320 */
959 /* start-sanitize-tx49 */
961 /* end-sanitize-tx49 */
962 /* start-sanitize-r5900 */
964 /* end-sanitize-r5900 */
968 else if (mips_cpu
== 5000
969 /* start-sanitize-vr5400 */
971 /* end-sanitize-vr5400 */
973 || mips_cpu
== 10000)
980 if (mips_opts
.mips16
< 0)
982 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
983 mips_opts
.mips16
= 1;
985 mips_opts
.mips16
= 0;
989 mips_4650
= (mips_cpu
== 4650);
992 mips_4010
= (mips_cpu
== 4010);
995 mips_4100
= (mips_cpu
== 4100);
997 /* start-sanitize-vr4320 */
999 mips_4320
= (mips_cpu
== 4320);
1001 /* end-sanitize-vr4320 */
1002 /* start-sanitize-vr5400 */
1004 mips_5400
= (mips_cpu
== 5400);
1005 /* end-sanitize-vr5400 */
1007 /* start-sanitize-r5900 */
1009 mips_5900
= (mips_cpu
== 5900);
1010 /* end-sanitize-r5900 */
1013 mips_3900
= (mips_cpu
== 3900);
1015 /* start-sanitize-tx49 */
1017 mips_4900
= (mips_cpu
== 4900);
1019 /* end-sanitize-tx49 */
1021 /* End of TARGET_CPU processing, get rid of malloced memory
1030 if (mips_opts
.isa
< 2 && mips_trap
)
1031 as_bad ("trap exception not supported at ISA 1");
1033 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1035 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1039 switch (mips_opts
.isa
)
1042 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1045 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1048 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1051 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1057 as_warn ("Could not set architecture and machine");
1059 file_mips_isa
= mips_opts
.isa
;
1061 op_hash
= hash_new ();
1063 for (i
= 0; i
< NUMOPCODES
;)
1065 const char *name
= mips_opcodes
[i
].name
;
1067 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1070 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
1071 mips_opcodes
[i
].name
, retval
);
1072 /* Probably a memory allocation problem? Give up now. */
1073 as_fatal ("Broken assembler. No assembly attempted.");
1077 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1079 if (!validate_mips_insn (&mips_opcodes
[i
]))
1084 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1087 mips16_op_hash
= hash_new ();
1090 while (i
< bfd_mips16_num_opcodes
)
1092 const char *name
= mips16_opcodes
[i
].name
;
1094 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1096 as_fatal ("internal: can't hash `%s': %s",
1097 mips16_opcodes
[i
].name
, retval
);
1100 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1101 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1102 != mips16_opcodes
[i
].match
))
1104 fprintf (stderr
, "internal error: bad mips16 opcode: %s %s\n",
1105 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1110 while (i
< bfd_mips16_num_opcodes
1111 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1115 as_fatal ("Broken assembler. No assembly attempted.");
1117 /* We add all the general register names to the symbol table. This
1118 helps us detect invalid uses of them. */
1119 for (i
= 0; i
< 32; i
++)
1123 sprintf (buf
, "$%d", i
);
1124 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1125 &zero_address_frag
));
1127 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1128 &zero_address_frag
));
1129 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1130 &zero_address_frag
));
1131 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1132 &zero_address_frag
));
1133 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1134 &zero_address_frag
));
1135 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1136 &zero_address_frag
));
1137 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1138 &zero_address_frag
));
1139 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1140 &zero_address_frag
));
1142 mips_no_prev_insn (false);
1145 mips_cprmask
[0] = 0;
1146 mips_cprmask
[1] = 0;
1147 mips_cprmask
[2] = 0;
1148 mips_cprmask
[3] = 0;
1150 /* set the default alignment for the text section (2**2) */
1151 record_alignment (text_section
, 2);
1153 if (USE_GLOBAL_POINTER_OPT
)
1154 bfd_set_gp_size (stdoutput
, g_switch_value
);
1156 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1158 /* On a native system, sections must be aligned to 16 byte
1159 boundaries. When configured for an embedded ELF target, we
1161 if (strcmp (TARGET_OS
, "elf") != 0)
1163 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1164 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1165 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1168 /* Create a .reginfo section for register masks and a .mdebug
1169 section for debugging information. */
1177 subseg
= now_subseg
;
1179 /* The ABI says this section should be loaded so that the
1180 running program can access it. However, we don't load it
1181 if we are configured for an embedded target */
1182 flags
= SEC_READONLY
| SEC_DATA
;
1183 if (strcmp (TARGET_OS
, "elf") != 0)
1184 flags
|= SEC_ALLOC
| SEC_LOAD
;
1188 sec
= subseg_new (".reginfo", (subsegT
) 0);
1191 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1192 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1195 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1200 /* The 64-bit ABI uses a .MIPS.options section rather than
1201 .reginfo section. */
1202 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1203 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1204 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1207 /* Set up the option header. */
1209 Elf_Internal_Options opthdr
;
1212 opthdr
.kind
= ODK_REGINFO
;
1213 opthdr
.size
= (sizeof (Elf_External_Options
)
1214 + sizeof (Elf64_External_RegInfo
));
1217 f
= frag_more (sizeof (Elf_External_Options
));
1218 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1219 (Elf_External_Options
*) f
);
1221 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1226 if (ECOFF_DEBUGGING
)
1228 sec
= subseg_new (".mdebug", (subsegT
) 0);
1229 (void) bfd_set_section_flags (stdoutput
, sec
,
1230 SEC_HAS_CONTENTS
| SEC_READONLY
);
1231 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1234 subseg_set (seg
, subseg
);
1238 if (! ECOFF_DEBUGGING
)
1245 if (! ECOFF_DEBUGGING
)
1253 struct mips_cl_insn insn
;
1255 imm_expr
.X_op
= O_absent
;
1256 imm_reloc
= BFD_RELOC_UNUSED
;
1257 imm_unmatched_hi
= false;
1258 offset_expr
.X_op
= O_absent
;
1259 offset_reloc
= BFD_RELOC_UNUSED
;
1261 if (mips_opts
.mips16
)
1262 mips16_ip (str
, &insn
);
1265 mips_ip (str
, &insn
);
1266 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1267 str
, insn
.insn_opcode
));
1272 as_bad ("%s `%s'", insn_error
, str
);
1276 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1278 if (mips_opts
.mips16
)
1279 mips16_macro (&insn
);
1285 if (imm_expr
.X_op
!= O_absent
)
1286 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1288 else if (offset_expr
.X_op
!= O_absent
)
1289 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1291 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1295 /* See whether instruction IP reads register REG. CLASS is the type
1299 insn_uses_reg (ip
, reg
, class)
1300 struct mips_cl_insn
*ip
;
1302 enum mips_regclass
class;
1304 if (class == MIPS16_REG
)
1306 assert (mips_opts
.mips16
);
1307 reg
= mips16_to_32_reg_map
[reg
];
1308 class = MIPS_GR_REG
;
1311 /* Don't report on general register 0, since it never changes. */
1312 if (class == MIPS_GR_REG
&& reg
== 0)
1315 if (class == MIPS_FP_REG
)
1317 assert (! mips_opts
.mips16
);
1318 /* If we are called with either $f0 or $f1, we must check $f0.
1319 This is not optimal, because it will introduce an unnecessary
1320 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1321 need to distinguish reading both $f0 and $f1 or just one of
1322 them. Note that we don't have to check the other way,
1323 because there is no instruction that sets both $f0 and $f1
1324 and requires a delay. */
1325 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1326 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1327 == (reg
&~ (unsigned) 1)))
1329 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1330 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1331 == (reg
&~ (unsigned) 1)))
1334 else if (! mips_opts
.mips16
)
1336 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1337 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1339 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1340 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1345 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1346 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1347 & MIPS16OP_MASK_RX
)]
1350 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1351 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1352 & MIPS16OP_MASK_RY
)]
1355 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1356 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1357 & MIPS16OP_MASK_MOVE32Z
)]
1360 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1362 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1364 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1366 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1367 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1368 & MIPS16OP_MASK_REGR32
) == reg
)
1375 /* This function returns true if modifying a register requires a
1379 reg_needs_delay (reg
)
1382 unsigned long prev_pinfo
;
1384 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1385 if (! mips_opts
.noreorder
1386 && mips_opts
.isa
< 4
1387 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1388 || (! gpr_interlocks
1389 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1391 /* A load from a coprocessor or from memory. All load
1392 delays delay the use of general register rt for one
1393 instruction on the r3000. The r6000 and r4000 use
1395 /* Itbl support may require additional care here. */
1396 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1397 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1404 /* Mark instruction labels in mips16 mode. This permits the linker to
1405 handle them specially, such as generating jalx instructions when
1406 needed. We also make them odd for the duration of the assembly, in
1407 order to generate the right sort of code. We will make them even
1408 in the adjust_symtab routine, while leaving them marked. This is
1409 convenient for the debugger and the disassembler. The linker knows
1410 to make them odd again. */
1413 mips16_mark_labels ()
1415 if (mips_opts
.mips16
)
1417 struct insn_label_list
*l
;
1419 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1422 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1423 S_SET_OTHER (l
->label
, STO_MIPS16
);
1425 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1426 ++l
->label
->sy_value
.X_add_number
;
1431 /* Output an instruction. PLACE is where to put the instruction; if
1432 it is NULL, this uses frag_more to get room. IP is the instruction
1433 information. ADDRESS_EXPR is an operand of the instruction to be
1434 used with RELOC_TYPE. */
1437 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1439 struct mips_cl_insn
*ip
;
1440 expressionS
*address_expr
;
1441 bfd_reloc_code_real_type reloc_type
;
1442 boolean unmatched_hi
;
1444 register unsigned long prev_pinfo
, pinfo
;
1449 /* Mark instruction labels in mips16 mode. */
1450 if (mips_opts
.mips16
)
1451 mips16_mark_labels ();
1453 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1454 pinfo
= ip
->insn_mo
->pinfo
;
1456 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1460 /* If the previous insn required any delay slots, see if we need
1461 to insert a NOP or two. There are eight kinds of possible
1462 hazards, of which an instruction can have at most one type.
1463 (1) a load from memory delay
1464 (2) a load from a coprocessor delay
1465 (3) an unconditional branch delay
1466 (4) a conditional branch delay
1467 (5) a move to coprocessor register delay
1468 (6) a load coprocessor register from memory delay
1469 (7) a coprocessor condition code delay
1470 (8) a HI/LO special register delay
1472 There are a lot of optimizations we could do that we don't.
1473 In particular, we do not, in general, reorder instructions.
1474 If you use gcc with optimization, it will reorder
1475 instructions and generally do much more optimization then we
1476 do here; repeating all that work in the assembler would only
1477 benefit hand written assembly code, and does not seem worth
1480 /* This is how a NOP is emitted. */
1481 #define emit_nop() \
1483 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1484 : md_number_to_chars (frag_more (4), 0, 4))
1486 /* The previous insn might require a delay slot, depending upon
1487 the contents of the current insn. */
1488 if (! mips_opts
.mips16
1489 && mips_opts
.isa
< 4
1490 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1491 && ! cop_interlocks
)
1492 || (! gpr_interlocks
1493 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1495 /* A load from a coprocessor or from memory. All load
1496 delays delay the use of general register rt for one
1497 instruction on the r3000. The r6000 and r4000 use
1499 /* Itbl support may require additional care here. */
1500 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1501 if (mips_optimize
== 0
1502 || insn_uses_reg (ip
,
1503 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1508 else if (! mips_opts
.mips16
1509 && mips_opts
.isa
< 4
1510 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1511 && ! cop_interlocks
)
1512 || (mips_opts
.isa
< 2
1513 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1515 /* A generic coprocessor delay. The previous instruction
1516 modified a coprocessor general or control register. If
1517 it modified a control register, we need to avoid any
1518 coprocessor instruction (this is probably not always
1519 required, but it sometimes is). If it modified a general
1520 register, we avoid using that register.
1522 On the r6000 and r4000 loading a coprocessor register
1523 from memory is interlocked, and does not require a delay.
1525 This case is not handled very well. There is no special
1526 knowledge of CP0 handling, and the coprocessors other
1527 than the floating point unit are not distinguished at
1529 /* Itbl support may require additional care here. FIXME!
1530 Need to modify this to include knowledge about
1531 user specified delays! */
1532 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1534 if (mips_optimize
== 0
1535 || insn_uses_reg (ip
,
1536 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1541 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1543 if (mips_optimize
== 0
1544 || insn_uses_reg (ip
,
1545 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1552 /* We don't know exactly what the previous instruction
1553 does. If the current instruction uses a coprocessor
1554 register, we must insert a NOP. If previous
1555 instruction may set the condition codes, and the
1556 current instruction uses them, we must insert two
1558 /* Itbl support may require additional care here. */
1559 if (mips_optimize
== 0
1560 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1561 && (pinfo
& INSN_READ_COND_CODE
)))
1563 else if (pinfo
& INSN_COP
)
1567 else if (! mips_opts
.mips16
1568 && mips_opts
.isa
< 4
1569 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1570 && ! cop_interlocks
)
1572 /* The previous instruction sets the coprocessor condition
1573 codes, but does not require a general coprocessor delay
1574 (this means it is a floating point comparison
1575 instruction). If this instruction uses the condition
1576 codes, we need to insert a single NOP. */
1577 /* Itbl support may require additional care here. */
1578 if (mips_optimize
== 0
1579 || (pinfo
& INSN_READ_COND_CODE
))
1582 else if (prev_pinfo
& INSN_READ_LO
)
1584 /* The previous instruction reads the LO register; if the
1585 current instruction writes to the LO register, we must
1586 insert two NOPS. Some newer processors have interlocks. */
1587 if (! hilo_interlocks
1588 && (mips_optimize
== 0
1589 || (pinfo
& INSN_WRITE_LO
)))
1592 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1594 /* The previous instruction reads the HI register; if the
1595 current instruction writes to the HI register, we must
1596 insert a NOP. Some newer processors have interlocks. */
1597 if (! hilo_interlocks
1598 && (mips_optimize
== 0
1599 || (pinfo
& INSN_WRITE_HI
)))
1603 /* If the previous instruction was in a noreorder section, then
1604 we don't want to insert the nop after all. */
1605 /* Itbl support may require additional care here. */
1606 if (prev_insn_unreordered
)
1609 /* There are two cases which require two intervening
1610 instructions: 1) setting the condition codes using a move to
1611 coprocessor instruction which requires a general coprocessor
1612 delay and then reading the condition codes 2) reading the HI
1613 or LO register and then writing to it (except on processors
1614 which have interlocks). If we are not already emitting a NOP
1615 instruction, we must check for these cases compared to the
1616 instruction previous to the previous instruction. */
1617 if ((! mips_opts
.mips16
1618 && mips_opts
.isa
< 4
1619 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1620 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1621 && (pinfo
& INSN_READ_COND_CODE
)
1622 && ! cop_interlocks
)
1623 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1624 && (pinfo
& INSN_WRITE_LO
)
1625 && ! hilo_interlocks
)
1626 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1627 && (pinfo
& INSN_WRITE_HI
)
1628 && ! hilo_interlocks
))
1633 if (prev_prev_insn_unreordered
)
1636 if (prev_prev_nop
&& nops
== 0)
1639 /* If we are being given a nop instruction, don't bother with
1640 one of the nops we would otherwise output. This will only
1641 happen when a nop instruction is used with mips_optimize set
1644 && ! mips_opts
.noreorder
1645 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1648 /* Now emit the right number of NOP instructions. */
1649 if (nops
> 0 && ! mips_opts
.noreorder
)
1652 unsigned long old_frag_offset
;
1654 struct insn_label_list
*l
;
1656 old_frag
= frag_now
;
1657 old_frag_offset
= frag_now_fix ();
1659 for (i
= 0; i
< nops
; i
++)
1664 listing_prev_line ();
1665 /* We may be at the start of a variant frag. In case we
1666 are, make sure there is enough space for the frag
1667 after the frags created by listing_prev_line. The
1668 argument to frag_grow here must be at least as large
1669 as the argument to all other calls to frag_grow in
1670 this file. We don't have to worry about being in the
1671 middle of a variant frag, because the variants insert
1672 all needed nop instructions themselves. */
1676 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1678 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1679 l
->label
->sy_frag
= frag_now
;
1680 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1681 /* mips16 text labels are stored as odd. */
1682 if (mips_opts
.mips16
)
1683 ++l
->label
->sy_value
.X_add_number
;
1686 #ifndef NO_ECOFF_DEBUGGING
1687 if (ECOFF_DEBUGGING
)
1688 ecoff_fix_loc (old_frag
, old_frag_offset
);
1691 else if (prev_nop_frag
!= NULL
)
1693 /* We have a frag holding nops we may be able to remove. If
1694 we don't need any nops, we can decrease the size of
1695 prev_nop_frag by the size of one instruction. If we do
1696 need some nops, we count them in prev_nops_required. */
1697 if (prev_nop_frag_since
== 0)
1701 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1702 --prev_nop_frag_holds
;
1705 prev_nop_frag_required
+= nops
;
1709 if (prev_prev_nop
== 0)
1711 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1712 --prev_nop_frag_holds
;
1715 ++prev_nop_frag_required
;
1718 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1719 prev_nop_frag
= NULL
;
1721 ++prev_nop_frag_since
;
1723 /* Sanity check: by the time we reach the second instruction
1724 after prev_nop_frag, we should have used up all the nops
1725 one way or another. */
1726 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1730 if (reloc_type
> BFD_RELOC_UNUSED
)
1732 /* We need to set up a variant frag. */
1733 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1734 f
= frag_var (rs_machine_dependent
, 4, 0,
1735 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1736 mips16_small
, mips16_ext
,
1738 & INSN_UNCOND_BRANCH_DELAY
),
1739 (prev_insn_reloc_type
1740 == BFD_RELOC_MIPS16_JMP
)),
1741 make_expr_symbol (address_expr
), (offsetT
) 0,
1744 else if (place
!= NULL
)
1746 else if (mips_opts
.mips16
1748 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1750 /* Make sure there is enough room to swap this instruction with
1751 a following jump instruction. */
1757 if (mips_opts
.mips16
1758 && mips_opts
.noreorder
1759 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1760 as_warn ("extended instruction in delay slot");
1766 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1768 if (address_expr
->X_op
== O_constant
)
1773 ip
->insn_opcode
|= address_expr
->X_add_number
;
1776 case BFD_RELOC_LO16
:
1777 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1780 case BFD_RELOC_MIPS_JMP
:
1781 if ((address_expr
->X_add_number
& 3) != 0)
1782 as_bad ("jump to misaligned address (0x%lx)",
1783 (unsigned long) address_expr
->X_add_number
);
1784 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1787 case BFD_RELOC_MIPS16_JMP
:
1788 if ((address_expr
->X_add_number
& 3) != 0)
1789 as_bad ("jump to misaligned address (0x%lx)",
1790 (unsigned long) address_expr
->X_add_number
);
1792 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1793 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1794 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1797 /* start-sanitize-r5900
1798 case BFD_RELOC_MIPS15_S3:
1799 ip->insn_opcode |= ((imm_expr.X_add_number & 0x7fff) >> 3) << 6;
1801 /* end-sanitize-r5900
1803 case BFD_RELOC_16_PCREL_S2:
1813 /* Don't generate a reloc if we are writing into a variant
1817 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1819 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1823 struct mips_hi_fixup
*hi_fixup
;
1825 assert (reloc_type
== BFD_RELOC_HI16_S
);
1826 hi_fixup
= ((struct mips_hi_fixup
*)
1827 xmalloc (sizeof (struct mips_hi_fixup
)));
1828 hi_fixup
->fixp
= fixp
;
1829 hi_fixup
->seg
= now_seg
;
1830 hi_fixup
->next
= mips_hi_fixup_list
;
1831 mips_hi_fixup_list
= hi_fixup
;
1837 if (! mips_opts
.mips16
)
1838 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1839 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1841 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1842 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1848 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1851 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1854 /* Update the register mask information. */
1855 if (! mips_opts
.mips16
)
1857 if (pinfo
& INSN_WRITE_GPR_D
)
1858 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1859 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1860 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1861 if (pinfo
& INSN_READ_GPR_S
)
1862 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1863 if (pinfo
& INSN_WRITE_GPR_31
)
1864 mips_gprmask
|= 1 << 31;
1865 if (pinfo
& INSN_WRITE_FPR_D
)
1866 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1867 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1868 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1869 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1870 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1871 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1872 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1873 if (pinfo
& INSN_COP
)
1875 /* We don't keep enough information to sort these cases out.
1876 The itbl support does keep this information however, although
1877 we currently don't support itbl fprmats as part of the cop
1878 instruction. May want to add this support in the future. */
1880 /* Never set the bit for $0, which is always zero. */
1881 mips_gprmask
&=~ 1 << 0;
1885 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1886 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1887 & MIPS16OP_MASK_RX
);
1888 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1889 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1890 & MIPS16OP_MASK_RY
);
1891 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1892 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1893 & MIPS16OP_MASK_RZ
);
1894 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1895 mips_gprmask
|= 1 << TREG
;
1896 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1897 mips_gprmask
|= 1 << SP
;
1898 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1899 mips_gprmask
|= 1 << RA
;
1900 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1901 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1902 if (pinfo
& MIPS16_INSN_READ_Z
)
1903 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1904 & MIPS16OP_MASK_MOVE32Z
);
1905 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1906 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1907 & MIPS16OP_MASK_REGR32
);
1910 if (place
== NULL
&& ! mips_opts
.noreorder
)
1912 /* Filling the branch delay slot is more complex. We try to
1913 switch the branch with the previous instruction, which we can
1914 do if the previous instruction does not set up a condition
1915 that the branch tests and if the branch is not itself the
1916 target of any branch. */
1917 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1918 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1920 if (mips_optimize
< 2
1921 /* If we have seen .set volatile or .set nomove, don't
1923 || mips_opts
.nomove
!= 0
1924 /* If we had to emit any NOP instructions, then we
1925 already know we can not swap. */
1927 /* If we don't even know the previous insn, we can not
1929 || ! prev_insn_valid
1930 /* If the previous insn is already in a branch delay
1931 slot, then we can not swap. */
1932 || prev_insn_is_delay_slot
1933 /* If the previous previous insn was in a .set
1934 noreorder, we can't swap. Actually, the MIPS
1935 assembler will swap in this situation. However, gcc
1936 configured -with-gnu-as will generate code like
1942 in which we can not swap the bne and INSN. If gcc is
1943 not configured -with-gnu-as, it does not output the
1944 .set pseudo-ops. We don't have to check
1945 prev_insn_unreordered, because prev_insn_valid will
1946 be 0 in that case. We don't want to use
1947 prev_prev_insn_valid, because we do want to be able
1948 to swap at the start of a function. */
1949 || prev_prev_insn_unreordered
1950 /* If the branch is itself the target of a branch, we
1951 can not swap. We cheat on this; all we check for is
1952 whether there is a label on this instruction. If
1953 there are any branches to anything other than a
1954 label, users must use .set noreorder. */
1955 || insn_labels
!= NULL
1956 /* If the previous instruction is in a variant frag, we
1957 can not do the swap. This does not apply to the
1958 mips16, which uses variant frags for different
1960 || (! mips_opts
.mips16
1961 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1962 /* If the branch reads the condition codes, we don't
1963 even try to swap, because in the sequence
1968 we can not swap, and I don't feel like handling that
1970 || (! mips_opts
.mips16
1971 && mips_opts
.isa
< 4
1972 && (pinfo
& INSN_READ_COND_CODE
))
1973 /* We can not swap with an instruction that requires a
1974 delay slot, becase the target of the branch might
1975 interfere with that instruction. */
1976 || (! mips_opts
.mips16
1977 && mips_opts
.isa
< 4
1979 /* Itbl support may require additional care here. */
1980 & (INSN_LOAD_COPROC_DELAY
1981 | INSN_COPROC_MOVE_DELAY
1982 | INSN_WRITE_COND_CODE
)))
1983 || (! hilo_interlocks
1987 || (! mips_opts
.mips16
1989 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1990 || (! mips_opts
.mips16
1991 && mips_opts
.isa
< 2
1992 /* Itbl support may require additional care here. */
1993 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1994 /* We can not swap with a branch instruction. */
1996 & (INSN_UNCOND_BRANCH_DELAY
1997 | INSN_COND_BRANCH_DELAY
1998 | INSN_COND_BRANCH_LIKELY
))
1999 /* We do not swap with a trap instruction, since it
2000 complicates trap handlers to have the trap
2001 instruction be in a delay slot. */
2002 || (prev_pinfo
& INSN_TRAP
)
2003 /* If the branch reads a register that the previous
2004 instruction sets, we can not swap. */
2005 || (! mips_opts
.mips16
2006 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2007 && insn_uses_reg (ip
,
2008 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2011 || (! mips_opts
.mips16
2012 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2013 && insn_uses_reg (ip
,
2014 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2017 || (mips_opts
.mips16
2018 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2019 && insn_uses_reg (ip
,
2020 ((prev_insn
.insn_opcode
2022 & MIPS16OP_MASK_RX
),
2024 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2025 && insn_uses_reg (ip
,
2026 ((prev_insn
.insn_opcode
2028 & MIPS16OP_MASK_RY
),
2030 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2031 && insn_uses_reg (ip
,
2032 ((prev_insn
.insn_opcode
2034 & MIPS16OP_MASK_RZ
),
2036 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2037 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2038 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2039 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2040 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2041 && insn_uses_reg (ip
,
2042 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2045 /* If the branch writes a register that the previous
2046 instruction sets, we can not swap (we know that
2047 branches write only to RD or to $31). */
2048 || (! mips_opts
.mips16
2049 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2050 && (((pinfo
& INSN_WRITE_GPR_D
)
2051 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2052 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2053 || ((pinfo
& INSN_WRITE_GPR_31
)
2054 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2057 || (! mips_opts
.mips16
2058 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2059 && (((pinfo
& INSN_WRITE_GPR_D
)
2060 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2061 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2062 || ((pinfo
& INSN_WRITE_GPR_31
)
2063 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2066 || (mips_opts
.mips16
2067 && (pinfo
& MIPS16_INSN_WRITE_31
)
2068 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2069 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2070 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2072 /* If the branch writes a register that the previous
2073 instruction reads, we can not swap (we know that
2074 branches only write to RD or to $31). */
2075 || (! mips_opts
.mips16
2076 && (pinfo
& INSN_WRITE_GPR_D
)
2077 && insn_uses_reg (&prev_insn
,
2078 ((ip
->insn_opcode
>> OP_SH_RD
)
2081 || (! mips_opts
.mips16
2082 && (pinfo
& INSN_WRITE_GPR_31
)
2083 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2084 || (mips_opts
.mips16
2085 && (pinfo
& MIPS16_INSN_WRITE_31
)
2086 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2087 /* If we are generating embedded PIC code, the branch
2088 might be expanded into a sequence which uses $at, so
2089 we can't swap with an instruction which reads it. */
2090 || (mips_pic
== EMBEDDED_PIC
2091 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2092 /* If the previous previous instruction has a load
2093 delay, and sets a register that the branch reads, we
2095 || (! mips_opts
.mips16
2096 && mips_opts
.isa
< 4
2097 /* Itbl support may require additional care here. */
2098 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2099 || (! gpr_interlocks
2100 && (prev_prev_insn
.insn_mo
->pinfo
2101 & INSN_LOAD_MEMORY_DELAY
)))
2102 && insn_uses_reg (ip
,
2103 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2106 /* If one instruction sets a condition code and the
2107 other one uses a condition code, we can not swap. */
2108 || ((pinfo
& INSN_READ_COND_CODE
)
2109 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2110 || ((pinfo
& INSN_WRITE_COND_CODE
)
2111 && (prev_pinfo
& INSN_READ_COND_CODE
))
2112 /* If the previous instruction uses the PC, we can not
2114 || (mips_opts
.mips16
2115 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2116 /* If the previous instruction was extended, we can not
2118 || (mips_opts
.mips16
&& prev_insn_extended
)
2119 /* If the previous instruction had a fixup in mips16
2120 mode, we can not swap. This normally means that the
2121 previous instruction was a 4 byte branch anyhow. */
2122 || (mips_opts
.mips16
&& prev_insn_fixp
))
2124 /* We could do even better for unconditional branches to
2125 portions of this object file; we could pick up the
2126 instruction at the destination, put it in the delay
2127 slot, and bump the destination address. */
2129 /* Update the previous insn information. */
2130 prev_prev_insn
= *ip
;
2131 prev_insn
.insn_mo
= &dummy_opcode
;
2135 /* It looks like we can actually do the swap. */
2136 if (! mips_opts
.mips16
)
2141 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2142 memcpy (temp
, prev_f
, 4);
2143 memcpy (prev_f
, f
, 4);
2144 memcpy (f
, temp
, 4);
2147 prev_insn_fixp
->fx_frag
= frag_now
;
2148 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2152 fixp
->fx_frag
= prev_insn_frag
;
2153 fixp
->fx_where
= prev_insn_where
;
2161 assert (prev_insn_fixp
== NULL
);
2162 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2163 memcpy (temp
, prev_f
, 2);
2164 memcpy (prev_f
, f
, 2);
2165 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2167 assert (reloc_type
== BFD_RELOC_UNUSED
);
2168 memcpy (f
, temp
, 2);
2172 memcpy (f
, f
+ 2, 2);
2173 memcpy (f
+ 2, temp
, 2);
2177 fixp
->fx_frag
= prev_insn_frag
;
2178 fixp
->fx_where
= prev_insn_where
;
2182 /* Update the previous insn information; leave prev_insn
2184 prev_prev_insn
= *ip
;
2186 prev_insn_is_delay_slot
= 1;
2188 /* If that was an unconditional branch, forget the previous
2189 insn information. */
2190 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2192 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2193 prev_insn
.insn_mo
= &dummy_opcode
;
2196 prev_insn_fixp
= NULL
;
2197 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2198 prev_insn_extended
= 0;
2200 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2202 /* We don't yet optimize a branch likely. What we should do
2203 is look at the target, copy the instruction found there
2204 into the delay slot, and increment the branch to jump to
2205 the next instruction. */
2207 /* Update the previous insn information. */
2208 prev_prev_insn
= *ip
;
2209 prev_insn
.insn_mo
= &dummy_opcode
;
2210 prev_insn_fixp
= NULL
;
2211 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2212 prev_insn_extended
= 0;
2216 /* Update the previous insn information. */
2218 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2220 prev_prev_insn
= prev_insn
;
2223 /* Any time we see a branch, we always fill the delay slot
2224 immediately; since this insn is not a branch, we know it
2225 is not in a delay slot. */
2226 prev_insn_is_delay_slot
= 0;
2228 prev_insn_fixp
= fixp
;
2229 prev_insn_reloc_type
= reloc_type
;
2230 if (mips_opts
.mips16
)
2231 prev_insn_extended
= (ip
->use_extend
2232 || reloc_type
> BFD_RELOC_UNUSED
);
2235 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2236 prev_insn_unreordered
= 0;
2237 prev_insn_frag
= frag_now
;
2238 prev_insn_where
= f
- frag_now
->fr_literal
;
2239 prev_insn_valid
= 1;
2241 else if (place
== NULL
)
2243 /* We need to record a bit of information even when we are not
2244 reordering, in order to determine the base address for mips16
2245 PC relative relocs. */
2246 prev_prev_insn
= prev_insn
;
2248 prev_insn_reloc_type
= reloc_type
;
2249 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2250 prev_insn_unreordered
= 1;
2253 /* We just output an insn, so the next one doesn't have a label. */
2254 mips_clear_insn_labels ();
2256 /* We must ensure that a fixup associated with an unmatched %hi
2257 reloc does not become a variant frag. Otherwise, the
2258 rearrangement of %hi relocs in frob_file may confuse
2262 frag_wane (frag_now
);
2267 /* This function forgets that there was any previous instruction or
2268 label. If PRESERVE is non-zero, it remembers enough information to
2269 know whether nops are needed before a noreorder section. */
2272 mips_no_prev_insn (preserve
)
2277 prev_insn
.insn_mo
= &dummy_opcode
;
2278 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2279 prev_nop_frag
= NULL
;
2280 prev_nop_frag_holds
= 0;
2281 prev_nop_frag_required
= 0;
2282 prev_nop_frag_since
= 0;
2284 prev_insn_valid
= 0;
2285 prev_insn_is_delay_slot
= 0;
2286 prev_insn_unreordered
= 0;
2287 prev_insn_extended
= 0;
2288 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2289 prev_prev_insn_unreordered
= 0;
2290 mips_clear_insn_labels ();
2293 /* This function must be called whenever we turn on noreorder or emit
2294 something other than instructions. It inserts any NOPS which might
2295 be needed by the previous instruction, and clears the information
2296 kept for the previous instructions. The INSNS parameter is true if
2297 instructions are to follow. */
2300 mips_emit_delays (insns
)
2303 if (! mips_opts
.noreorder
)
2308 if ((! mips_opts
.mips16
2309 && mips_opts
.isa
< 4
2310 && (! cop_interlocks
2311 && (prev_insn
.insn_mo
->pinfo
2312 & (INSN_LOAD_COPROC_DELAY
2313 | INSN_COPROC_MOVE_DELAY
2314 | INSN_WRITE_COND_CODE
))))
2315 || (! hilo_interlocks
2316 && (prev_insn
.insn_mo
->pinfo
2319 || (! mips_opts
.mips16
2321 && (prev_insn
.insn_mo
->pinfo
2322 & INSN_LOAD_MEMORY_DELAY
))
2323 || (! mips_opts
.mips16
2324 && mips_opts
.isa
< 2
2325 && (prev_insn
.insn_mo
->pinfo
2326 & INSN_COPROC_MEMORY_DELAY
)))
2328 /* Itbl support may require additional care here. */
2330 if ((! mips_opts
.mips16
2331 && mips_opts
.isa
< 4
2332 && (! cop_interlocks
2333 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2334 || (! hilo_interlocks
2335 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2336 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2339 if (prev_insn_unreordered
)
2342 else if ((! mips_opts
.mips16
2343 && mips_opts
.isa
< 4
2344 && (! cop_interlocks
2345 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2346 || (! hilo_interlocks
2347 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2348 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2350 /* Itbl support may require additional care here. */
2351 if (! prev_prev_insn_unreordered
)
2357 struct insn_label_list
*l
;
2361 /* Record the frag which holds the nop instructions, so
2362 that we can remove them if we don't need them. */
2363 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2364 prev_nop_frag
= frag_now
;
2365 prev_nop_frag_holds
= nops
;
2366 prev_nop_frag_required
= 0;
2367 prev_nop_frag_since
= 0;
2370 for (; nops
> 0; --nops
)
2375 /* Move on to a new frag, so that it is safe to simply
2376 decrease the size of prev_nop_frag. */
2377 frag_wane (frag_now
);
2381 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2383 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2384 l
->label
->sy_frag
= frag_now
;
2385 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2386 /* mips16 text labels are stored as odd. */
2387 if (mips_opts
.mips16
)
2388 ++l
->label
->sy_value
.X_add_number
;
2393 /* Mark instruction labels in mips16 mode. */
2394 if (mips_opts
.mips16
&& insns
)
2395 mips16_mark_labels ();
2397 mips_no_prev_insn (insns
);
2400 /* Build an instruction created by a macro expansion. This is passed
2401 a pointer to the count of instructions created so far, an
2402 expression, the name of the instruction to build, an operand format
2403 string, and corresponding arguments. */
2407 macro_build (char *place
,
2415 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2424 struct mips_cl_insn insn
;
2425 bfd_reloc_code_real_type r
;
2430 va_start (args
, fmt
);
2436 * If the macro is about to expand into a second instruction,
2437 * print a warning if needed. We need to pass ip as a parameter
2438 * to generate a better warning message here...
2440 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2441 as_warn ("Macro instruction expanded into multiple instructions");
2444 *counter
+= 1; /* bump instruction counter */
2446 if (mips_opts
.mips16
)
2448 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2453 r
= BFD_RELOC_UNUSED
;
2454 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2455 assert (insn
.insn_mo
);
2456 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2458 /* Search until we get a match for NAME. */
2461 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2463 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2465 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2467 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2472 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2473 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2474 && (insn_isa
<= mips_opts
.isa
2476 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2478 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2480 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2481 /* start-sanitize-vr4320 */
2483 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2484 /* end-sanitize-vr4320 */
2485 /* start-sanitize-tx49 */
2487 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2488 /* end-sanitize-tx49 */
2489 /* start-sanitize-r5900 */
2491 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2492 /* end-sanitize-r5900 */
2493 /* start-sanitize-vr5400 */
2495 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2496 /* end-sanitize-vr5400 */
2498 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2499 /* start-sanitize-r5900 */
2500 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2501 /* end-sanitize-r5900 */
2502 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2506 assert (insn
.insn_mo
->name
);
2507 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2510 insn
.insn_opcode
= insn
.insn_mo
->match
;
2526 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2532 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2537 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2542 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2549 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2553 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2557 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2564 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2570 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2571 assert (r
== BFD_RELOC_MIPS_GPREL
2572 || r
== BFD_RELOC_MIPS_LITERAL
2573 || r
== BFD_RELOC_LO16
2574 || r
== BFD_RELOC_MIPS_GOT16
2575 || r
== BFD_RELOC_MIPS_CALL16
2576 || r
== BFD_RELOC_MIPS_GOT_LO16
2577 || r
== BFD_RELOC_MIPS_CALL_LO16
2578 || (ep
->X_op
== O_subtract
2579 && now_seg
== text_section
2580 && r
== BFD_RELOC_PCREL_LO16
));
2584 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2586 && (ep
->X_op
== O_constant
2587 || (ep
->X_op
== O_symbol
2588 && (r
== BFD_RELOC_HI16_S
2589 || r
== BFD_RELOC_HI16
2590 || r
== BFD_RELOC_MIPS_GOT_HI16
2591 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2592 || (ep
->X_op
== O_subtract
2593 && now_seg
== text_section
2594 && r
== BFD_RELOC_PCREL_HI16_S
)));
2595 if (ep
->X_op
== O_constant
)
2597 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2599 r
= BFD_RELOC_UNUSED
;
2604 assert (ep
!= NULL
);
2606 * This allows macro() to pass an immediate expression for
2607 * creating short branches without creating a symbol.
2608 * Note that the expression still might come from the assembly
2609 * input, in which case the value is not checked for range nor
2610 * is a relocation entry generated (yuck).
2612 if (ep
->X_op
== O_constant
)
2614 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2618 r
= BFD_RELOC_16_PCREL_S2
;
2622 assert (ep
!= NULL
);
2623 r
= BFD_RELOC_MIPS_JMP
;
2627 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2636 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2638 append_insn (place
, &insn
, ep
, r
, false);
2642 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2650 struct mips_cl_insn insn
;
2651 bfd_reloc_code_real_type r
;
2653 r
= BFD_RELOC_UNUSED
;
2654 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2655 assert (insn
.insn_mo
);
2656 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2658 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2659 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2662 assert (insn
.insn_mo
->name
);
2663 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2666 insn
.insn_opcode
= insn
.insn_mo
->match
;
2667 insn
.use_extend
= false;
2686 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2691 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2695 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2699 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2709 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2716 regno
= va_arg (args
, int);
2717 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2718 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2739 assert (ep
!= NULL
);
2741 if (ep
->X_op
!= O_constant
)
2742 r
= BFD_RELOC_UNUSED
+ c
;
2745 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2746 false, false, &insn
.insn_opcode
,
2747 &insn
.use_extend
, &insn
.extend
);
2749 r
= BFD_RELOC_UNUSED
;
2755 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2762 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2764 append_insn (place
, &insn
, ep
, r
, false);
2768 * Generate a "lui" instruction.
2771 macro_build_lui (place
, counter
, ep
, regnum
)
2777 expressionS high_expr
;
2778 struct mips_cl_insn insn
;
2779 bfd_reloc_code_real_type r
;
2780 CONST
char *name
= "lui";
2781 CONST
char *fmt
= "t,u";
2783 assert (! mips_opts
.mips16
);
2789 high_expr
.X_op
= O_constant
;
2790 high_expr
.X_add_number
= ep
->X_add_number
;
2793 if (high_expr
.X_op
== O_constant
)
2795 /* we can compute the instruction now without a relocation entry */
2796 if (high_expr
.X_add_number
& 0x8000)
2797 high_expr
.X_add_number
+= 0x10000;
2798 high_expr
.X_add_number
=
2799 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2800 r
= BFD_RELOC_UNUSED
;
2804 assert (ep
->X_op
== O_symbol
);
2805 /* _gp_disp is a special case, used from s_cpload. */
2806 assert (mips_pic
== NO_PIC
2807 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2808 r
= BFD_RELOC_HI16_S
;
2812 * If the macro is about to expand into a second instruction,
2813 * print a warning if needed. We need to pass ip as a parameter
2814 * to generate a better warning message here...
2816 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2817 as_warn ("Macro instruction expanded into multiple instructions");
2820 *counter
+= 1; /* bump instruction counter */
2822 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2823 assert (insn
.insn_mo
);
2824 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2825 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2827 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2828 if (r
== BFD_RELOC_UNUSED
)
2830 insn
.insn_opcode
|= high_expr
.X_add_number
;
2831 append_insn (place
, &insn
, NULL
, r
, false);
2834 append_insn (place
, &insn
, &high_expr
, r
, false);
2838 * Generates code to set the $at register to true (one)
2839 * if reg is less than the immediate expression.
2842 set_at (counter
, reg
, unsignedp
)
2847 if (imm_expr
.X_op
== O_constant
2848 && imm_expr
.X_add_number
>= -0x8000
2849 && imm_expr
.X_add_number
< 0x8000)
2850 macro_build ((char *) NULL
, counter
, &imm_expr
,
2851 unsignedp
? "sltiu" : "slti",
2852 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2855 load_register (counter
, AT
, &imm_expr
, 0);
2856 macro_build ((char *) NULL
, counter
, NULL
,
2857 unsignedp
? "sltu" : "slt",
2858 "d,v,t", AT
, reg
, AT
);
2862 /* Warn if an expression is not a constant. */
2865 check_absolute_expr (ip
, ex
)
2866 struct mips_cl_insn
*ip
;
2869 if (ex
->X_op
== O_big
)
2870 as_bad ("unsupported large constant");
2871 else if (ex
->X_op
!= O_constant
)
2872 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2875 /* Count the leading zeroes by performing a binary chop. This is a
2876 bulky bit of source, but performance is a LOT better for the
2877 majority of values than a simple loop to count the bits:
2878 for (lcnt = 0; (lcnt < 32); lcnt++)
2879 if ((v) & (1 << (31 - lcnt)))
2881 However it is not code size friendly, and the gain will drop a bit
2882 on certain cached systems.
2884 #define COUNT_TOP_ZEROES(v) \
2885 (((v) & ~0xffff) == 0 \
2886 ? ((v) & ~0xff) == 0 \
2887 ? ((v) & ~0xf) == 0 \
2888 ? ((v) & ~0x3) == 0 \
2889 ? ((v) & ~0x1) == 0 \
2894 : ((v) & ~0x7) == 0 \
2897 : ((v) & ~0x3f) == 0 \
2898 ? ((v) & ~0x1f) == 0 \
2901 : ((v) & ~0x7f) == 0 \
2904 : ((v) & ~0xfff) == 0 \
2905 ? ((v) & ~0x3ff) == 0 \
2906 ? ((v) & ~0x1ff) == 0 \
2909 : ((v) & ~0x7ff) == 0 \
2912 : ((v) & ~0x3fff) == 0 \
2913 ? ((v) & ~0x1fff) == 0 \
2916 : ((v) & ~0x7fff) == 0 \
2919 : ((v) & ~0xffffff) == 0 \
2920 ? ((v) & ~0xfffff) == 0 \
2921 ? ((v) & ~0x3ffff) == 0 \
2922 ? ((v) & ~0x1ffff) == 0 \
2925 : ((v) & ~0x7ffff) == 0 \
2928 : ((v) & ~0x3fffff) == 0 \
2929 ? ((v) & ~0x1fffff) == 0 \
2932 : ((v) & ~0x7fffff) == 0 \
2935 : ((v) & ~0xfffffff) == 0 \
2936 ? ((v) & ~0x3ffffff) == 0 \
2937 ? ((v) & ~0x1ffffff) == 0 \
2940 : ((v) & ~0x7ffffff) == 0 \
2943 : ((v) & ~0x3fffffff) == 0 \
2944 ? ((v) & ~0x1fffffff) == 0 \
2947 : ((v) & ~0x7fffffff) == 0 \
2952 * This routine generates the least number of instructions neccessary to load
2953 * an absolute expression value into a register.
2956 load_register (counter
, reg
, ep
, dbl
)
2963 expressionS hi32
, lo32
;
2965 if (ep
->X_op
!= O_big
)
2967 assert (ep
->X_op
== O_constant
);
2968 if (ep
->X_add_number
< 0x8000
2969 && (ep
->X_add_number
>= 0
2970 || (ep
->X_add_number
>= -0x8000
2973 || sizeof (ep
->X_add_number
) > 4))))
2975 /* We can handle 16 bit signed values with an addiu to
2976 $zero. No need to ever use daddiu here, since $zero and
2977 the result are always correct in 32 bit mode. */
2978 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2979 (int) BFD_RELOC_LO16
);
2982 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2984 /* We can handle 16 bit unsigned values with an ori to
2986 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2987 (int) BFD_RELOC_LO16
);
2990 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2991 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2992 == ~ (offsetT
) 0x7fffffff))
2995 || sizeof (ep
->X_add_number
) > 4
2996 || (ep
->X_add_number
& 0x80000000) == 0))
2997 || ((mips_opts
.isa
< 3 || ! dbl
)
2998 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2999 || (mips_opts
.isa
< 3
3001 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3002 == ~ (offsetT
) 0xffffffff)))
3004 /* 32 bit values require an lui. */
3005 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3006 (int) BFD_RELOC_HI16
);
3007 if ((ep
->X_add_number
& 0xffff) != 0)
3008 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3009 (int) BFD_RELOC_LO16
);
3014 /* The value is larger than 32 bits. */
3016 if (mips_opts
.isa
< 3)
3018 as_bad ("Number larger than 32 bits");
3019 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3020 (int) BFD_RELOC_LO16
);
3024 if (ep
->X_op
!= O_big
)
3027 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3028 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3029 hi32
.X_add_number
&= 0xffffffff;
3031 lo32
.X_add_number
&= 0xffffffff;
3035 assert (ep
->X_add_number
> 2);
3036 if (ep
->X_add_number
== 3)
3037 generic_bignum
[3] = 0;
3038 else if (ep
->X_add_number
> 4)
3039 as_bad ("Number larger than 64 bits");
3040 lo32
.X_op
= O_constant
;
3041 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3042 hi32
.X_op
= O_constant
;
3043 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3046 if (hi32
.X_add_number
== 0)
3051 unsigned long hi
, lo
;
3053 if (hi32
.X_add_number
== 0xffffffff)
3055 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3057 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3058 reg
, 0, (int) BFD_RELOC_LO16
);
3061 if (lo32
.X_add_number
& 0x80000000)
3063 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3064 (int) BFD_RELOC_HI16
);
3065 if (lo32
.X_add_number
& 0xffff)
3066 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3067 reg
, reg
, (int) BFD_RELOC_LO16
);
3072 /* Check for 16bit shifted constant. We know that hi32 is
3073 non-zero, so start the mask on the first bit of the hi32
3078 unsigned long himask
, lomask
;
3082 himask
= 0xffff >> (32 - shift
);
3083 lomask
= (0xffff << shift
) & 0xffffffff;
3087 himask
= 0xffff << (shift
- 32);
3090 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3091 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3095 tmp
.X_op
= O_constant
;
3097 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3098 | (lo32
.X_add_number
>> shift
));
3100 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3101 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3102 (int) BFD_RELOC_LO16
);
3103 macro_build ((char *) NULL
, counter
, NULL
,
3104 (shift
>= 32) ? "dsll32" : "dsll",
3106 (shift
>= 32) ? shift
- 32 : shift
);
3110 } while (shift
<= (64 - 16));
3112 /* Find the bit number of the lowest one bit, and store the
3113 shifted value in hi/lo. */
3114 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3115 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3119 while ((lo
& 1) == 0)
3124 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3130 while ((hi
& 1) == 0)
3139 /* Optimize if the shifted value is a (power of 2) - 1. */
3140 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3141 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3143 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3148 /* This instruction will set the register to be all
3150 tmp
.X_op
= O_constant
;
3151 tmp
.X_add_number
= (offsetT
) -1;
3152 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3153 reg
, 0, (int) BFD_RELOC_LO16
);
3157 macro_build ((char *) NULL
, counter
, NULL
,
3158 (bit
>= 32) ? "dsll32" : "dsll",
3160 (bit
>= 32) ? bit
- 32 : bit
);
3162 macro_build ((char *) NULL
, counter
, NULL
,
3163 (shift
>= 32) ? "dsrl32" : "dsrl",
3165 (shift
>= 32) ? shift
- 32 : shift
);
3170 /* Sign extend hi32 before calling load_register, because we can
3171 generally get better code when we load a sign extended value. */
3172 if ((hi32
.X_add_number
& 0x80000000) != 0)
3173 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3174 load_register (counter
, reg
, &hi32
, 0);
3177 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3181 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3190 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3192 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3193 (int) BFD_RELOC_HI16
);
3194 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3201 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3206 mid16
.X_add_number
>>= 16;
3207 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3208 freg
, (int) BFD_RELOC_LO16
);
3209 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3213 if ((lo32
.X_add_number
& 0xffff) != 0)
3214 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3215 (int) BFD_RELOC_LO16
);
3218 /* Load an address into a register. */
3221 load_address (counter
, reg
, ep
)
3228 if (ep
->X_op
!= O_constant
3229 && ep
->X_op
!= O_symbol
)
3231 as_bad ("expression too complex");
3232 ep
->X_op
= O_constant
;
3235 if (ep
->X_op
== O_constant
)
3237 load_register (counter
, reg
, ep
, 0);
3241 if (mips_pic
== NO_PIC
)
3243 /* If this is a reference to a GP relative symbol, we want
3244 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3246 lui $reg,<sym> (BFD_RELOC_HI16_S)
3247 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3248 If we have an addend, we always use the latter form. */
3249 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3250 || nopic_need_relax (ep
->X_add_symbol
, 1))
3255 macro_build ((char *) NULL
, counter
, ep
,
3256 ((bfd_arch_bits_per_address (stdoutput
) == 32
3257 || mips_opts
.isa
< 3)
3258 ? "addiu" : "daddiu"),
3259 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3260 p
= frag_var (rs_machine_dependent
, 8, 0,
3261 RELAX_ENCODE (4, 8, 0, 4, 0,
3262 mips_opts
.warn_about_macros
),
3263 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3265 macro_build_lui (p
, counter
, ep
, reg
);
3268 macro_build (p
, counter
, ep
,
3269 ((bfd_arch_bits_per_address (stdoutput
) == 32
3270 || mips_opts
.isa
< 3)
3271 ? "addiu" : "daddiu"),
3272 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3274 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3278 /* If this is a reference to an external symbol, we want
3279 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3281 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3283 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3284 If there is a constant, it must be added in after. */
3285 ex
.X_add_number
= ep
->X_add_number
;
3286 ep
->X_add_number
= 0;
3288 macro_build ((char *) NULL
, counter
, ep
,
3289 ((bfd_arch_bits_per_address (stdoutput
) == 32
3290 || mips_opts
.isa
< 3)
3292 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3293 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3294 p
= frag_var (rs_machine_dependent
, 4, 0,
3295 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3296 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3297 macro_build (p
, counter
, ep
,
3298 ((bfd_arch_bits_per_address (stdoutput
) == 32
3299 || mips_opts
.isa
< 3)
3300 ? "addiu" : "daddiu"),
3301 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3302 if (ex
.X_add_number
!= 0)
3304 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3305 as_bad ("PIC code offset overflow (max 16 signed bits)");
3306 ex
.X_op
= O_constant
;
3307 macro_build ((char *) NULL
, counter
, &ex
,
3308 ((bfd_arch_bits_per_address (stdoutput
) == 32
3309 || mips_opts
.isa
< 3)
3310 ? "addiu" : "daddiu"),
3311 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3314 else if (mips_pic
== SVR4_PIC
)
3319 /* This is the large GOT case. If this is a reference to an
3320 external symbol, we want
3321 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3323 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3324 Otherwise, for a reference to a local symbol, we want
3325 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3327 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3328 If there is a constant, it must be added in after. */
3329 ex
.X_add_number
= ep
->X_add_number
;
3330 ep
->X_add_number
= 0;
3331 if (reg_needs_delay (GP
))
3336 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3337 (int) BFD_RELOC_MIPS_GOT_HI16
);
3338 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3339 ((bfd_arch_bits_per_address (stdoutput
) == 32
3340 || mips_opts
.isa
< 3)
3341 ? "addu" : "daddu"),
3342 "d,v,t", reg
, reg
, GP
);
3343 macro_build ((char *) NULL
, counter
, ep
,
3344 ((bfd_arch_bits_per_address (stdoutput
) == 32
3345 || mips_opts
.isa
< 3)
3347 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3348 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3349 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3350 mips_opts
.warn_about_macros
),
3351 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3354 /* We need a nop before loading from $gp. This special
3355 check is required because the lui which starts the main
3356 instruction stream does not refer to $gp, and so will not
3357 insert the nop which may be required. */
3358 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3361 macro_build (p
, counter
, ep
,
3362 ((bfd_arch_bits_per_address (stdoutput
) == 32
3363 || mips_opts
.isa
< 3)
3365 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3367 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3369 macro_build (p
, counter
, ep
,
3370 ((bfd_arch_bits_per_address (stdoutput
) == 32
3371 || mips_opts
.isa
< 3)
3372 ? "addiu" : "daddiu"),
3373 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3374 if (ex
.X_add_number
!= 0)
3376 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3377 as_bad ("PIC code offset overflow (max 16 signed bits)");
3378 ex
.X_op
= O_constant
;
3379 macro_build ((char *) NULL
, counter
, &ex
,
3380 ((bfd_arch_bits_per_address (stdoutput
) == 32
3381 || mips_opts
.isa
< 3)
3382 ? "addiu" : "daddiu"),
3383 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3386 else if (mips_pic
== EMBEDDED_PIC
)
3389 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3391 macro_build ((char *) NULL
, counter
, ep
,
3392 ((bfd_arch_bits_per_address (stdoutput
) == 32
3393 || mips_opts
.isa
< 3)
3394 ? "addiu" : "daddiu"),
3395 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3403 * This routine implements the seemingly endless macro or synthesized
3404 * instructions and addressing modes in the mips assembly language. Many
3405 * of these macros are simple and are similar to each other. These could
3406 * probably be handled by some kind of table or grammer aproach instead of
3407 * this verbose method. Others are not simple macros but are more like
3408 * optimizing code generation.
3409 * One interesting optimization is when several store macros appear
3410 * consecutivly that would load AT with the upper half of the same address.
3411 * The ensuing load upper instructions are ommited. This implies some kind
3412 * of global optimization. We currently only optimize within a single macro.
3413 * For many of the load and store macros if the address is specified as a
3414 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3415 * first load register 'at' with zero and use it as the base register. The
3416 * mips assembler simply uses register $zero. Just one tiny optimization
3421 struct mips_cl_insn
*ip
;
3423 register int treg
, sreg
, dreg
, breg
;
3438 bfd_reloc_code_real_type r
;
3440 int hold_mips_optimize
;
3442 assert (! mips_opts
.mips16
);
3444 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3445 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3446 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3447 mask
= ip
->insn_mo
->mask
;
3449 expr1
.X_op
= O_constant
;
3450 expr1
.X_op_symbol
= NULL
;
3451 expr1
.X_add_symbol
= NULL
;
3452 expr1
.X_add_number
= 1;
3464 mips_emit_delays (true);
3465 ++mips_opts
.noreorder
;
3466 mips_any_noreorder
= 1;
3468 expr1
.X_add_number
= 8;
3469 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3471 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3473 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3474 macro_build ((char *) NULL
, &icnt
, NULL
,
3475 dbl
? "dsub" : "sub",
3476 "d,v,t", dreg
, 0, sreg
);
3478 --mips_opts
.noreorder
;
3499 if (imm_expr
.X_op
== O_constant
3500 && imm_expr
.X_add_number
>= -0x8000
3501 && imm_expr
.X_add_number
< 0x8000)
3503 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3504 (int) BFD_RELOC_LO16
);
3507 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3508 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3527 if (imm_expr
.X_op
== O_constant
3528 && imm_expr
.X_add_number
>= 0
3529 && imm_expr
.X_add_number
< 0x10000)
3531 if (mask
!= M_NOR_I
)
3532 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3533 sreg
, (int) BFD_RELOC_LO16
);
3536 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3537 treg
, sreg
, (int) BFD_RELOC_LO16
);
3538 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3544 load_register (&icnt
, AT
, &imm_expr
, 0);
3545 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3562 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3564 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3568 load_register (&icnt
, AT
, &imm_expr
, 0);
3569 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3577 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3578 likely
? "bgezl" : "bgez",
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3585 likely
? "blezl" : "blez",
3589 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3591 likely
? "beql" : "beq",
3598 /* check for > max integer */
3599 maxnum
= 0x7fffffff;
3600 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3607 if (imm_expr
.X_op
== O_constant
3608 && imm_expr
.X_add_number
>= maxnum
3609 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3612 /* result is always false */
3615 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3616 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3620 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3621 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3626 if (imm_expr
.X_op
!= O_constant
)
3627 as_bad ("Unsupported large constant");
3628 imm_expr
.X_add_number
++;
3632 if (mask
== M_BGEL_I
)
3634 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3636 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3637 likely
? "bgezl" : "bgez",
3641 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3643 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3644 likely
? "bgtzl" : "bgtz",
3648 maxnum
= 0x7fffffff;
3649 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3656 maxnum
= - maxnum
- 1;
3657 if (imm_expr
.X_op
== O_constant
3658 && imm_expr
.X_add_number
<= maxnum
3659 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3662 /* result is always true */
3663 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3664 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3667 set_at (&icnt
, sreg
, 0);
3668 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3669 likely
? "beql" : "beq",
3680 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3681 likely
? "beql" : "beq",
3685 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3687 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3688 likely
? "beql" : "beq",
3696 || (mips_opts
.isa
< 3
3697 && imm_expr
.X_op
== O_constant
3698 && imm_expr
.X_add_number
== 0xffffffff))
3700 if (imm_expr
.X_op
!= O_constant
)
3701 as_bad ("Unsupported large constant");
3702 imm_expr
.X_add_number
++;
3706 if (mask
== M_BGEUL_I
)
3708 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3710 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3712 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3713 likely
? "bnel" : "bne",
3717 set_at (&icnt
, sreg
, 1);
3718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3719 likely
? "beql" : "beq",
3728 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3729 likely
? "bgtzl" : "bgtz",
3735 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3736 likely
? "bltzl" : "bltz",
3740 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3741 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3742 likely
? "bnel" : "bne",
3751 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3752 likely
? "bnel" : "bne",
3758 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3760 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3761 likely
? "bnel" : "bne",
3770 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3771 likely
? "blezl" : "blez",
3777 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3778 likely
? "bgezl" : "bgez",
3782 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3783 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3784 likely
? "beql" : "beq",
3791 maxnum
= 0x7fffffff;
3792 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3799 if (imm_expr
.X_op
== O_constant
3800 && imm_expr
.X_add_number
>= maxnum
3801 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3803 if (imm_expr
.X_op
!= O_constant
)
3804 as_bad ("Unsupported large constant");
3805 imm_expr
.X_add_number
++;
3809 if (mask
== M_BLTL_I
)
3811 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3813 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3814 likely
? "bltzl" : "bltz",
3818 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3820 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3821 likely
? "blezl" : "blez",
3825 set_at (&icnt
, sreg
, 0);
3826 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3827 likely
? "bnel" : "bne",
3836 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3837 likely
? "beql" : "beq",
3843 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3845 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3846 likely
? "beql" : "beq",
3854 || (mips_opts
.isa
< 3
3855 && imm_expr
.X_op
== O_constant
3856 && imm_expr
.X_add_number
== 0xffffffff))
3858 if (imm_expr
.X_op
!= O_constant
)
3859 as_bad ("Unsupported large constant");
3860 imm_expr
.X_add_number
++;
3864 if (mask
== M_BLTUL_I
)
3866 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3868 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3871 likely
? "beql" : "beq",
3875 set_at (&icnt
, sreg
, 1);
3876 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3877 likely
? "bnel" : "bne",
3886 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3887 likely
? "bltzl" : "bltz",
3893 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3894 likely
? "bgtzl" : "bgtz",
3898 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3899 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3900 likely
? "bnel" : "bne",
3911 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3912 likely
? "bnel" : "bne",
3916 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3918 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3919 likely
? "bnel" : "bne",
3935 as_warn ("Divide by zero.");
3937 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3939 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3943 mips_emit_delays (true);
3944 ++mips_opts
.noreorder
;
3945 mips_any_noreorder
= 1;
3948 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3949 macro_build ((char *) NULL
, &icnt
, NULL
,
3950 dbl
? "ddiv" : "div",
3951 "z,s,t", sreg
, treg
);
3955 expr1
.X_add_number
= 8;
3956 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3957 macro_build ((char *) NULL
, &icnt
, NULL
,
3958 dbl
? "ddiv" : "div",
3959 "z,s,t", sreg
, treg
);
3960 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3962 expr1
.X_add_number
= -1;
3963 macro_build ((char *) NULL
, &icnt
, &expr1
,
3964 dbl
? "daddiu" : "addiu",
3965 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3966 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3967 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3970 expr1
.X_add_number
= 1;
3971 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3972 (int) BFD_RELOC_LO16
);
3973 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3978 expr1
.X_add_number
= 0x80000000;
3979 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3980 (int) BFD_RELOC_HI16
);
3983 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3986 expr1
.X_add_number
= 8;
3987 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3988 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3989 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3991 --mips_opts
.noreorder
;
3992 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4031 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4033 as_warn ("Divide by zero.");
4035 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4037 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4040 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4042 if (strcmp (s2
, "mflo") == 0)
4043 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4046 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4049 if (imm_expr
.X_op
== O_constant
4050 && imm_expr
.X_add_number
== -1
4051 && s
[strlen (s
) - 1] != 'u')
4053 if (strcmp (s2
, "mflo") == 0)
4056 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4059 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4063 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4067 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4068 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4069 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4088 mips_emit_delays (true);
4089 ++mips_opts
.noreorder
;
4090 mips_any_noreorder
= 1;
4093 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4094 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4098 expr1
.X_add_number
= 8;
4099 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4100 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4101 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4103 --mips_opts
.noreorder
;
4104 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4110 /* Load the address of a symbol into a register. If breg is not
4111 zero, we then add a base register to it. */
4113 /* When generating embedded PIC code, we permit expressions of
4116 where bar is an address in the .text section. These are used
4117 when getting the addresses of functions. We don't permit
4118 X_add_number to be non-zero, because if the symbol is
4119 external the relaxing code needs to know that any addend is
4120 purely the offset to X_op_symbol. */
4121 if (mips_pic
== EMBEDDED_PIC
4122 && offset_expr
.X_op
== O_subtract
4123 && now_seg
== text_section
4124 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4125 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4126 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4127 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4128 ->sy_value
.X_add_symbol
)
4131 && offset_expr
.X_add_number
== 0)
4133 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4134 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4136 ((bfd_arch_bits_per_address (stdoutput
) == 32
4137 || mips_opts
.isa
< 3)
4138 ? "addiu" : "daddiu"),
4139 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4143 if (offset_expr
.X_op
!= O_symbol
4144 && offset_expr
.X_op
!= O_constant
)
4146 as_bad ("expression too complex");
4147 offset_expr
.X_op
= O_constant
;
4161 if (offset_expr
.X_op
== O_constant
)
4162 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4163 else if (mips_pic
== NO_PIC
)
4165 /* If this is a reference to an GP relative symbol, we want
4166 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4168 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4169 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4170 If we have a constant, we need two instructions anyhow,
4171 so we may as well always use the latter form. */
4172 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4173 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4179 ((bfd_arch_bits_per_address (stdoutput
) == 32
4180 || mips_opts
.isa
< 3)
4181 ? "addiu" : "daddiu"),
4182 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4183 p
= frag_var (rs_machine_dependent
, 8, 0,
4184 RELAX_ENCODE (4, 8, 0, 4, 0,
4185 mips_opts
.warn_about_macros
),
4186 offset_expr
.X_add_symbol
, (offsetT
) 0,
4189 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4192 macro_build (p
, &icnt
, &offset_expr
,
4193 ((bfd_arch_bits_per_address (stdoutput
) == 32
4194 || mips_opts
.isa
< 3)
4195 ? "addiu" : "daddiu"),
4196 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4198 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4200 /* If this is a reference to an external symbol, and there
4201 is no constant, we want
4202 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4203 For a local symbol, we want
4204 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4206 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4208 If we have a small constant, and this is a reference to
4209 an external symbol, we want
4210 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4212 addiu $tempreg,$tempreg,<constant>
4213 For a local symbol, we want the same instruction
4214 sequence, but we output a BFD_RELOC_LO16 reloc on the
4217 If we have a large constant, and this is a reference to
4218 an external symbol, we want
4219 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4220 lui $at,<hiconstant>
4221 addiu $at,$at,<loconstant>
4222 addu $tempreg,$tempreg,$at
4223 For a local symbol, we want the same instruction
4224 sequence, but we output a BFD_RELOC_LO16 reloc on the
4225 addiu instruction. */
4226 expr1
.X_add_number
= offset_expr
.X_add_number
;
4227 offset_expr
.X_add_number
= 0;
4229 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4231 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4232 if (expr1
.X_add_number
== 0)
4240 /* We're going to put in an addu instruction using
4241 tempreg, so we may as well insert the nop right
4243 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4247 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4248 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4250 ? mips_opts
.warn_about_macros
4252 offset_expr
.X_add_symbol
, (offsetT
) 0,
4256 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4259 macro_build (p
, &icnt
, &expr1
,
4260 ((bfd_arch_bits_per_address (stdoutput
) == 32
4261 || mips_opts
.isa
< 3)
4262 ? "addiu" : "daddiu"),
4263 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4264 /* FIXME: If breg == 0, and the next instruction uses
4265 $tempreg, then if this variant case is used an extra
4266 nop will be generated. */
4268 else if (expr1
.X_add_number
>= -0x8000
4269 && expr1
.X_add_number
< 0x8000)
4271 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4273 macro_build ((char *) NULL
, &icnt
, &expr1
,
4274 ((bfd_arch_bits_per_address (stdoutput
) == 32
4275 || mips_opts
.isa
< 3)
4276 ? "addiu" : "daddiu"),
4277 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4278 (void) frag_var (rs_machine_dependent
, 0, 0,
4279 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4280 offset_expr
.X_add_symbol
, (offsetT
) 0,
4287 /* If we are going to add in a base register, and the
4288 target register and the base register are the same,
4289 then we are using AT as a temporary register. Since
4290 we want to load the constant into AT, we add our
4291 current AT (from the global offset table) and the
4292 register into the register now, and pretend we were
4293 not using a base register. */
4298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4300 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4301 ((bfd_arch_bits_per_address (stdoutput
) == 32
4302 || mips_opts
.isa
< 3)
4303 ? "addu" : "daddu"),
4304 "d,v,t", treg
, AT
, breg
);
4310 /* Set mips_optimize around the lui instruction to avoid
4311 inserting an unnecessary nop after the lw. */
4312 hold_mips_optimize
= mips_optimize
;
4314 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4315 mips_optimize
= hold_mips_optimize
;
4317 macro_build ((char *) NULL
, &icnt
, &expr1
,
4318 ((bfd_arch_bits_per_address (stdoutput
) == 32
4319 || mips_opts
.isa
< 3)
4320 ? "addiu" : "daddiu"),
4321 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4322 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4323 ((bfd_arch_bits_per_address (stdoutput
) == 32
4324 || mips_opts
.isa
< 3)
4325 ? "addu" : "daddu"),
4326 "d,v,t", tempreg
, tempreg
, AT
);
4327 (void) frag_var (rs_machine_dependent
, 0, 0,
4328 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4329 offset_expr
.X_add_symbol
, (offsetT
) 0,
4334 else if (mips_pic
== SVR4_PIC
)
4338 /* This is the large GOT case. If this is a reference to an
4339 external symbol, and there is no constant, we want
4340 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4341 addu $tempreg,$tempreg,$gp
4342 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4343 For a local symbol, we want
4344 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4346 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4348 If we have a small constant, and this is a reference to
4349 an external symbol, we want
4350 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4351 addu $tempreg,$tempreg,$gp
4352 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4354 addiu $tempreg,$tempreg,<constant>
4355 For a local symbol, we want
4356 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4358 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4360 If we have a large constant, and this is a reference to
4361 an external symbol, we want
4362 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4363 addu $tempreg,$tempreg,$gp
4364 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4365 lui $at,<hiconstant>
4366 addiu $at,$at,<loconstant>
4367 addu $tempreg,$tempreg,$at
4368 For a local symbol, we want
4369 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4370 lui $at,<hiconstant>
4371 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4372 addu $tempreg,$tempreg,$at
4374 expr1
.X_add_number
= offset_expr
.X_add_number
;
4375 offset_expr
.X_add_number
= 0;
4377 if (reg_needs_delay (GP
))
4381 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4382 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4383 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4384 ((bfd_arch_bits_per_address (stdoutput
) == 32
4385 || mips_opts
.isa
< 3)
4386 ? "addu" : "daddu"),
4387 "d,v,t", tempreg
, tempreg
, GP
);
4388 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4390 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4392 if (expr1
.X_add_number
== 0)
4400 /* We're going to put in an addu instruction using
4401 tempreg, so we may as well insert the nop right
4403 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4408 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4409 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4412 ? mips_opts
.warn_about_macros
4414 offset_expr
.X_add_symbol
, (offsetT
) 0,
4417 else if (expr1
.X_add_number
>= -0x8000
4418 && expr1
.X_add_number
< 0x8000)
4420 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4422 macro_build ((char *) NULL
, &icnt
, &expr1
,
4423 ((bfd_arch_bits_per_address (stdoutput
) == 32
4424 || mips_opts
.isa
< 3)
4425 ? "addiu" : "daddiu"),
4426 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4428 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4429 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4431 ? mips_opts
.warn_about_macros
4433 offset_expr
.X_add_symbol
, (offsetT
) 0,
4440 /* If we are going to add in a base register, and the
4441 target register and the base register are the same,
4442 then we are using AT as a temporary register. Since
4443 we want to load the constant into AT, we add our
4444 current AT (from the global offset table) and the
4445 register into the register now, and pretend we were
4446 not using a base register. */
4454 assert (tempreg
== AT
);
4455 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4458 ((bfd_arch_bits_per_address (stdoutput
) == 32
4459 || mips_opts
.isa
< 3)
4460 ? "addu" : "daddu"),
4461 "d,v,t", treg
, AT
, breg
);
4466 /* Set mips_optimize around the lui instruction to avoid
4467 inserting an unnecessary nop after the lw. */
4468 hold_mips_optimize
= mips_optimize
;
4470 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4471 mips_optimize
= hold_mips_optimize
;
4473 macro_build ((char *) NULL
, &icnt
, &expr1
,
4474 ((bfd_arch_bits_per_address (stdoutput
) == 32
4475 || mips_opts
.isa
< 3)
4476 ? "addiu" : "daddiu"),
4477 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4478 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4479 ((bfd_arch_bits_per_address (stdoutput
) == 32
4480 || mips_opts
.isa
< 3)
4481 ? "addu" : "daddu"),
4482 "d,v,t", dreg
, dreg
, AT
);
4484 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4485 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4488 ? mips_opts
.warn_about_macros
4490 offset_expr
.X_add_symbol
, (offsetT
) 0,
4498 /* This is needed because this instruction uses $gp, but
4499 the first instruction on the main stream does not. */
4500 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4503 macro_build (p
, &icnt
, &offset_expr
,
4505 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4507 if (expr1
.X_add_number
>= -0x8000
4508 && expr1
.X_add_number
< 0x8000)
4510 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4512 macro_build (p
, &icnt
, &expr1
,
4513 ((bfd_arch_bits_per_address (stdoutput
) == 32
4514 || mips_opts
.isa
< 3)
4515 ? "addiu" : "daddiu"),
4516 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4517 /* FIXME: If add_number is 0, and there was no base
4518 register, the external symbol case ended with a load,
4519 so if the symbol turns out to not be external, and
4520 the next instruction uses tempreg, an unnecessary nop
4521 will be inserted. */
4527 /* We must add in the base register now, as in the
4528 external symbol case. */
4529 assert (tempreg
== AT
);
4530 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4532 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4533 ((bfd_arch_bits_per_address (stdoutput
) == 32
4534 || mips_opts
.isa
< 3)
4535 ? "addu" : "daddu"),
4536 "d,v,t", treg
, AT
, breg
);
4539 /* We set breg to 0 because we have arranged to add
4540 it in in both cases. */
4544 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4546 macro_build (p
, &icnt
, &expr1
,
4547 ((bfd_arch_bits_per_address (stdoutput
) == 32
4548 || mips_opts
.isa
< 3)
4549 ? "addiu" : "daddiu"),
4550 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4552 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4553 ((bfd_arch_bits_per_address (stdoutput
) == 32
4554 || mips_opts
.isa
< 3)
4555 ? "addu" : "daddu"),
4556 "d,v,t", tempreg
, tempreg
, AT
);
4560 else if (mips_pic
== EMBEDDED_PIC
)
4563 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4565 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4566 ((bfd_arch_bits_per_address (stdoutput
) == 32
4567 || mips_opts
.isa
< 3)
4568 ? "addiu" : "daddiu"),
4569 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4576 ((bfd_arch_bits_per_address (stdoutput
) == 32
4577 || mips_opts
.isa
< 3)
4578 ? "addu" : "daddu"),
4579 "d,v,t", treg
, tempreg
, breg
);
4587 /* The j instruction may not be used in PIC code, since it
4588 requires an absolute address. We convert it to a b
4590 if (mips_pic
== NO_PIC
)
4591 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4596 /* The jal instructions must be handled as macros because when
4597 generating PIC code they expand to multi-instruction
4598 sequences. Normally they are simple instructions. */
4603 if (mips_pic
== NO_PIC
4604 || mips_pic
== EMBEDDED_PIC
)
4605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4607 else if (mips_pic
== SVR4_PIC
)
4609 if (sreg
!= PIC_CALL_REG
)
4610 as_warn ("MIPS PIC call to register other than $25");
4612 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4614 if (mips_cprestore_offset
< 0)
4615 as_warn ("No .cprestore pseudo-op used in PIC code");
4618 expr1
.X_add_number
= mips_cprestore_offset
;
4619 macro_build ((char *) NULL
, &icnt
, &expr1
,
4620 ((bfd_arch_bits_per_address (stdoutput
) == 32
4621 || mips_opts
.isa
< 3)
4623 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4632 if (mips_pic
== NO_PIC
)
4633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4634 else if (mips_pic
== SVR4_PIC
)
4636 /* If this is a reference to an external symbol, and we are
4637 using a small GOT, we want
4638 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4642 lw $gp,cprestore($sp)
4643 The cprestore value is set using the .cprestore
4644 pseudo-op. If we are using a big GOT, we want
4645 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4647 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4651 lw $gp,cprestore($sp)
4652 If the symbol is not external, we want
4653 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4655 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4658 lw $gp,cprestore($sp) */
4662 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4663 ((bfd_arch_bits_per_address (stdoutput
) == 32
4664 || mips_opts
.isa
< 3)
4666 "t,o(b)", PIC_CALL_REG
,
4667 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4668 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4670 p
= frag_var (rs_machine_dependent
, 4, 0,
4671 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4672 offset_expr
.X_add_symbol
, (offsetT
) 0,
4679 if (reg_needs_delay (GP
))
4683 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4684 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4685 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4686 ((bfd_arch_bits_per_address (stdoutput
) == 32
4687 || mips_opts
.isa
< 3)
4688 ? "addu" : "daddu"),
4689 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4690 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4691 ((bfd_arch_bits_per_address (stdoutput
) == 32
4692 || mips_opts
.isa
< 3)
4694 "t,o(b)", PIC_CALL_REG
,
4695 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4698 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4699 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4701 offset_expr
.X_add_symbol
, (offsetT
) 0,
4705 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4708 macro_build (p
, &icnt
, &offset_expr
,
4709 ((bfd_arch_bits_per_address (stdoutput
) == 32
4710 || mips_opts
.isa
< 3)
4712 "t,o(b)", PIC_CALL_REG
,
4713 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4715 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4718 macro_build (p
, &icnt
, &offset_expr
,
4719 ((bfd_arch_bits_per_address (stdoutput
) == 32
4720 || mips_opts
.isa
< 3)
4721 ? "addiu" : "daddiu"),
4722 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4723 (int) BFD_RELOC_LO16
);
4724 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4725 "jalr", "s", PIC_CALL_REG
);
4726 if (mips_cprestore_offset
< 0)
4727 as_warn ("No .cprestore pseudo-op used in PIC code");
4730 if (mips_opts
.noreorder
)
4731 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4733 expr1
.X_add_number
= mips_cprestore_offset
;
4734 macro_build ((char *) NULL
, &icnt
, &expr1
,
4735 ((bfd_arch_bits_per_address (stdoutput
) == 32
4736 || mips_opts
.isa
< 3)
4738 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4742 else if (mips_pic
== EMBEDDED_PIC
)
4744 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4745 /* The linker may expand the call to a longer sequence which
4746 uses $at, so we must break rather than return. */
4771 /* Itbl support may require additional care here. */
4776 /* Itbl support may require additional care here. */
4781 /* Itbl support may require additional care here. */
4786 /* Itbl support may require additional care here. */
4800 as_bad ("opcode not supported on this processor");
4804 /* Itbl support may require additional care here. */
4809 /* Itbl support may require additional care here. */
4814 /* Itbl support may require additional care here. */
4834 if (breg
== treg
|| coproc
|| lr
)
4856 /* Itbl support may require additional care here. */
4861 /* Itbl support may require additional care here. */
4866 /* Itbl support may require additional care here. */
4871 /* Itbl support may require additional care here. */
4889 as_bad ("opcode not supported on this processor");
4894 /* Itbl support may require additional care here. */
4898 /* Itbl support may require additional care here. */
4903 /* Itbl support may require additional care here. */
4915 /* Itbl support may require additional care here. */
4916 if (mask
== M_LWC1_AB
4917 || mask
== M_SWC1_AB
4918 || mask
== M_LDC1_AB
4919 || mask
== M_SDC1_AB
4928 if (offset_expr
.X_op
!= O_constant
4929 && offset_expr
.X_op
!= O_symbol
)
4931 as_bad ("expression too complex");
4932 offset_expr
.X_op
= O_constant
;
4935 /* A constant expression in PIC code can be handled just as it
4936 is in non PIC code. */
4937 if (mips_pic
== NO_PIC
4938 || offset_expr
.X_op
== O_constant
)
4940 /* If this is a reference to a GP relative symbol, and there
4941 is no base register, we want
4942 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4943 Otherwise, if there is no base register, we want
4944 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4945 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4946 If we have a constant, we need two instructions anyhow,
4947 so we always use the latter form.
4949 If we have a base register, and this is a reference to a
4950 GP relative symbol, we want
4951 addu $tempreg,$breg,$gp
4952 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4954 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4955 addu $tempreg,$tempreg,$breg
4956 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4957 With a constant we always use the latter case. */
4960 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4961 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4966 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4967 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4968 p
= frag_var (rs_machine_dependent
, 8, 0,
4969 RELAX_ENCODE (4, 8, 0, 4, 0,
4970 (mips_opts
.warn_about_macros
4972 && mips_opts
.noat
))),
4973 offset_expr
.X_add_symbol
, (offsetT
) 0,
4977 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4980 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4981 (int) BFD_RELOC_LO16
, tempreg
);
4985 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4986 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4991 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4992 ((bfd_arch_bits_per_address (stdoutput
) == 32
4993 || mips_opts
.isa
< 3)
4994 ? "addu" : "daddu"),
4995 "d,v,t", tempreg
, breg
, GP
);
4996 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4997 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4998 p
= frag_var (rs_machine_dependent
, 12, 0,
4999 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5000 offset_expr
.X_add_symbol
, (offsetT
) 0,
5003 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5006 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5007 ((bfd_arch_bits_per_address (stdoutput
) == 32
5008 || mips_opts
.isa
< 3)
5009 ? "addu" : "daddu"),
5010 "d,v,t", tempreg
, tempreg
, breg
);
5013 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5014 (int) BFD_RELOC_LO16
, tempreg
);
5017 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5019 /* If this is a reference to an external symbol, we want
5020 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5022 <op> $treg,0($tempreg)
5024 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5026 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5027 <op> $treg,0($tempreg)
5028 If there is a base register, we add it to $tempreg before
5029 the <op>. If there is a constant, we stick it in the
5030 <op> instruction. We don't handle constants larger than
5031 16 bits, because we have no way to load the upper 16 bits
5032 (actually, we could handle them for the subset of cases
5033 in which we are not using $at). */
5034 assert (offset_expr
.X_op
== O_symbol
);
5035 expr1
.X_add_number
= offset_expr
.X_add_number
;
5036 offset_expr
.X_add_number
= 0;
5037 if (expr1
.X_add_number
< -0x8000
5038 || expr1
.X_add_number
>= 0x8000)
5039 as_bad ("PIC code offset overflow (max 16 signed bits)");
5041 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5042 ((bfd_arch_bits_per_address (stdoutput
) == 32
5043 || mips_opts
.isa
< 3)
5045 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5046 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5047 p
= frag_var (rs_machine_dependent
, 4, 0,
5048 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5049 offset_expr
.X_add_symbol
, (offsetT
) 0,
5051 macro_build (p
, &icnt
, &offset_expr
,
5052 ((bfd_arch_bits_per_address (stdoutput
) == 32
5053 || mips_opts
.isa
< 3)
5054 ? "addiu" : "daddiu"),
5055 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5057 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5058 ((bfd_arch_bits_per_address (stdoutput
) == 32
5059 || mips_opts
.isa
< 3)
5060 ? "addu" : "daddu"),
5061 "d,v,t", tempreg
, tempreg
, breg
);
5062 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5063 (int) BFD_RELOC_LO16
, tempreg
);
5065 else if (mips_pic
== SVR4_PIC
)
5069 /* If this is a reference to an external symbol, we want
5070 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5071 addu $tempreg,$tempreg,$gp
5072 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5073 <op> $treg,0($tempreg)
5075 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5077 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5078 <op> $treg,0($tempreg)
5079 If there is a base register, we add it to $tempreg before
5080 the <op>. If there is a constant, we stick it in the
5081 <op> instruction. We don't handle constants larger than
5082 16 bits, because we have no way to load the upper 16 bits
5083 (actually, we could handle them for the subset of cases
5084 in which we are not using $at). */
5085 assert (offset_expr
.X_op
== O_symbol
);
5086 expr1
.X_add_number
= offset_expr
.X_add_number
;
5087 offset_expr
.X_add_number
= 0;
5088 if (expr1
.X_add_number
< -0x8000
5089 || expr1
.X_add_number
>= 0x8000)
5090 as_bad ("PIC code offset overflow (max 16 signed bits)");
5091 if (reg_needs_delay (GP
))
5096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5097 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5098 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5099 ((bfd_arch_bits_per_address (stdoutput
) == 32
5100 || mips_opts
.isa
< 3)
5101 ? "addu" : "daddu"),
5102 "d,v,t", tempreg
, tempreg
, GP
);
5103 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5104 ((bfd_arch_bits_per_address (stdoutput
) == 32
5105 || mips_opts
.isa
< 3)
5107 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5109 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5110 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5111 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5114 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5117 macro_build (p
, &icnt
, &offset_expr
,
5118 ((bfd_arch_bits_per_address (stdoutput
) == 32
5119 || mips_opts
.isa
< 3)
5121 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5123 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5125 macro_build (p
, &icnt
, &offset_expr
,
5126 ((bfd_arch_bits_per_address (stdoutput
) == 32
5127 || mips_opts
.isa
< 3)
5128 ? "addiu" : "daddiu"),
5129 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5132 ((bfd_arch_bits_per_address (stdoutput
) == 32
5133 || mips_opts
.isa
< 3)
5134 ? "addu" : "daddu"),
5135 "d,v,t", tempreg
, tempreg
, breg
);
5136 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5137 (int) BFD_RELOC_LO16
, tempreg
);
5139 else if (mips_pic
== EMBEDDED_PIC
)
5141 /* If there is no base register, we want
5142 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5143 If there is a base register, we want
5144 addu $tempreg,$breg,$gp
5145 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5147 assert (offset_expr
.X_op
== O_symbol
);
5150 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5151 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5157 ((bfd_arch_bits_per_address (stdoutput
) == 32
5158 || mips_opts
.isa
< 3)
5159 ? "addu" : "daddu"),
5160 "d,v,t", tempreg
, breg
, GP
);
5161 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5162 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5175 load_register (&icnt
, treg
, &imm_expr
, 0);
5179 load_register (&icnt
, treg
, &imm_expr
, 1);
5183 if (imm_expr
.X_op
== O_constant
)
5185 load_register (&icnt
, AT
, &imm_expr
, 0);
5186 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5187 "mtc1", "t,G", AT
, treg
);
5192 assert (offset_expr
.X_op
== O_symbol
5193 && strcmp (segment_name (S_GET_SEGMENT
5194 (offset_expr
.X_add_symbol
)),
5196 && offset_expr
.X_add_number
== 0);
5197 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5198 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5203 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5204 the entire value, and in mips1 mode it is the high order 32
5205 bits of the value and the low order 32 bits are either zero
5206 or in offset_expr. */
5207 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5209 if (mips_opts
.isa
>= 3)
5210 load_register (&icnt
, treg
, &imm_expr
, 1);
5215 if (target_big_endian
)
5227 load_register (&icnt
, hreg
, &imm_expr
, 0);
5230 if (offset_expr
.X_op
== O_absent
)
5231 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5235 assert (offset_expr
.X_op
== O_constant
);
5236 load_register (&icnt
, lreg
, &offset_expr
, 0);
5243 /* We know that sym is in the .rdata section. First we get the
5244 upper 16 bits of the address. */
5245 if (mips_pic
== NO_PIC
)
5247 /* FIXME: This won't work for a 64 bit address. */
5248 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5250 else if (mips_pic
== SVR4_PIC
)
5252 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5253 ((bfd_arch_bits_per_address (stdoutput
) == 32
5254 || mips_opts
.isa
< 3)
5256 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5258 else if (mips_pic
== EMBEDDED_PIC
)
5260 /* For embedded PIC we pick up the entire address off $gp in
5261 a single instruction. */
5262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5263 ((bfd_arch_bits_per_address (stdoutput
) == 32
5264 || mips_opts
.isa
< 3)
5265 ? "addiu" : "daddiu"),
5266 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5267 offset_expr
.X_op
= O_constant
;
5268 offset_expr
.X_add_number
= 0;
5273 /* Now we load the register(s). */
5274 if (mips_opts
.isa
>= 3)
5275 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5276 treg
, (int) BFD_RELOC_LO16
, AT
);
5279 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5280 treg
, (int) BFD_RELOC_LO16
, AT
);
5283 /* FIXME: How in the world do we deal with the possible
5285 offset_expr
.X_add_number
+= 4;
5286 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5287 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5291 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5292 does not become a variant frag. */
5293 frag_wane (frag_now
);
5299 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5300 the entire value, and in mips1 mode it is the high order 32
5301 bits of the value and the low order 32 bits are either zero
5302 or in offset_expr. */
5303 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5305 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5306 if (mips_opts
.isa
>= 3)
5307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5308 "dmtc1", "t,S", AT
, treg
);
5311 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5312 "mtc1", "t,G", AT
, treg
+ 1);
5313 if (offset_expr
.X_op
== O_absent
)
5314 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5315 "mtc1", "t,G", 0, treg
);
5318 assert (offset_expr
.X_op
== O_constant
);
5319 load_register (&icnt
, AT
, &offset_expr
, 0);
5320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5321 "mtc1", "t,G", AT
, treg
);
5327 assert (offset_expr
.X_op
== O_symbol
5328 && offset_expr
.X_add_number
== 0);
5329 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5330 if (strcmp (s
, ".lit8") == 0)
5332 if (mips_opts
.isa
>= 2)
5334 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5335 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5339 r
= BFD_RELOC_MIPS_LITERAL
;
5344 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5345 if (mips_pic
== SVR4_PIC
)
5346 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5347 ((bfd_arch_bits_per_address (stdoutput
) == 32
5348 || mips_opts
.isa
< 3)
5350 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5353 /* FIXME: This won't work for a 64 bit address. */
5354 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5357 if (mips_opts
.isa
>= 2)
5359 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5360 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5362 /* To avoid confusion in tc_gen_reloc, we must ensure
5363 that this does not become a variant frag. */
5364 frag_wane (frag_now
);
5377 as_bad ("opcode not supported on this processor");
5380 /* Even on a big endian machine $fn comes before $fn+1. We have
5381 to adjust when loading from memory. */
5384 assert (mips_opts
.isa
< 2);
5385 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5386 target_big_endian
? treg
+ 1 : treg
,
5388 /* FIXME: A possible overflow which I don't know how to deal
5390 offset_expr
.X_add_number
+= 4;
5391 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5392 target_big_endian
? treg
: treg
+ 1,
5395 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5396 does not become a variant frag. */
5397 frag_wane (frag_now
);
5406 * The MIPS assembler seems to check for X_add_number not
5407 * being double aligned and generating:
5410 * addiu at,at,%lo(foo+1)
5413 * But, the resulting address is the same after relocation so why
5414 * generate the extra instruction?
5418 as_bad ("opcode not supported on this processor");
5421 /* Itbl support may require additional care here. */
5423 if (mips_opts
.isa
>= 2)
5436 as_bad ("opcode not supported on this processor");
5440 if (mips_opts
.isa
>= 2)
5448 /* Itbl support may require additional care here. */
5453 if (mips_opts
.isa
>= 3)
5464 if (mips_opts
.isa
>= 3)
5474 if (offset_expr
.X_op
!= O_symbol
5475 && offset_expr
.X_op
!= O_constant
)
5477 as_bad ("expression too complex");
5478 offset_expr
.X_op
= O_constant
;
5481 /* Even on a big endian machine $fn comes before $fn+1. We have
5482 to adjust when loading from memory. We set coproc if we must
5483 load $fn+1 first. */
5484 /* Itbl support may require additional care here. */
5485 if (! target_big_endian
)
5488 if (mips_pic
== NO_PIC
5489 || offset_expr
.X_op
== O_constant
)
5491 /* If this is a reference to a GP relative symbol, we want
5492 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5493 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5494 If we have a base register, we use this
5496 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5497 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5498 If this is not a GP relative symbol, we want
5499 lui $at,<sym> (BFD_RELOC_HI16_S)
5500 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5501 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5502 If there is a base register, we add it to $at after the
5503 lui instruction. If there is a constant, we always use
5505 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5506 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5526 ((bfd_arch_bits_per_address (stdoutput
) == 32
5527 || mips_opts
.isa
< 3)
5528 ? "addu" : "daddu"),
5529 "d,v,t", AT
, breg
, GP
);
5535 /* Itbl support may require additional care here. */
5536 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5537 coproc
? treg
+ 1 : treg
,
5538 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5539 offset_expr
.X_add_number
+= 4;
5541 /* Set mips_optimize to 2 to avoid inserting an
5543 hold_mips_optimize
= mips_optimize
;
5545 /* Itbl support may require additional care here. */
5546 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5547 coproc
? treg
: treg
+ 1,
5548 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5549 mips_optimize
= hold_mips_optimize
;
5551 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5552 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5553 used_at
&& mips_opts
.noat
),
5554 offset_expr
.X_add_symbol
, (offsetT
) 0,
5557 /* We just generated two relocs. When tc_gen_reloc
5558 handles this case, it will skip the first reloc and
5559 handle the second. The second reloc already has an
5560 extra addend of 4, which we added above. We must
5561 subtract it out, and then subtract another 4 to make
5562 the first reloc come out right. The second reloc
5563 will come out right because we are going to add 4 to
5564 offset_expr when we build its instruction below.
5566 If we have a symbol, then we don't want to include
5567 the offset, because it will wind up being included
5568 when we generate the reloc. */
5570 if (offset_expr
.X_op
== O_constant
)
5571 offset_expr
.X_add_number
-= 8;
5574 offset_expr
.X_add_number
= -4;
5575 offset_expr
.X_op
= O_constant
;
5578 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5583 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5584 ((bfd_arch_bits_per_address (stdoutput
) == 32
5585 || mips_opts
.isa
< 3)
5586 ? "addu" : "daddu"),
5587 "d,v,t", AT
, breg
, AT
);
5591 /* Itbl support may require additional care here. */
5592 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5593 coproc
? treg
+ 1 : treg
,
5594 (int) BFD_RELOC_LO16
, AT
);
5597 /* FIXME: How do we handle overflow here? */
5598 offset_expr
.X_add_number
+= 4;
5599 /* Itbl support may require additional care here. */
5600 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5601 coproc
? treg
: treg
+ 1,
5602 (int) BFD_RELOC_LO16
, AT
);
5604 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5608 /* If this is a reference to an external symbol, we want
5609 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5614 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5616 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5617 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5618 If there is a base register we add it to $at before the
5619 lwc1 instructions. If there is a constant we include it
5620 in the lwc1 instructions. */
5622 expr1
.X_add_number
= offset_expr
.X_add_number
;
5623 offset_expr
.X_add_number
= 0;
5624 if (expr1
.X_add_number
< -0x8000
5625 || expr1
.X_add_number
>= 0x8000 - 4)
5626 as_bad ("PIC code offset overflow (max 16 signed bits)");
5631 frag_grow (24 + off
);
5632 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5633 ((bfd_arch_bits_per_address (stdoutput
) == 32
5634 || mips_opts
.isa
< 3)
5636 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5637 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5639 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5640 ((bfd_arch_bits_per_address (stdoutput
) == 32
5641 || mips_opts
.isa
< 3)
5642 ? "addu" : "daddu"),
5643 "d,v,t", AT
, breg
, AT
);
5644 /* Itbl support may require additional care here. */
5645 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5646 coproc
? treg
+ 1 : treg
,
5647 (int) BFD_RELOC_LO16
, AT
);
5648 expr1
.X_add_number
+= 4;
5650 /* Set mips_optimize to 2 to avoid inserting an undesired
5652 hold_mips_optimize
= mips_optimize
;
5654 /* Itbl support may require additional care here. */
5655 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5656 coproc
? treg
: treg
+ 1,
5657 (int) BFD_RELOC_LO16
, AT
);
5658 mips_optimize
= hold_mips_optimize
;
5660 (void) frag_var (rs_machine_dependent
, 0, 0,
5661 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5662 offset_expr
.X_add_symbol
, (offsetT
) 0,
5665 else if (mips_pic
== SVR4_PIC
)
5669 /* If this is a reference to an external symbol, we want
5670 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5672 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5677 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5679 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5680 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5681 If there is a base register we add it to $at before the
5682 lwc1 instructions. If there is a constant we include it
5683 in the lwc1 instructions. */
5685 expr1
.X_add_number
= offset_expr
.X_add_number
;
5686 offset_expr
.X_add_number
= 0;
5687 if (expr1
.X_add_number
< -0x8000
5688 || expr1
.X_add_number
>= 0x8000 - 4)
5689 as_bad ("PIC code offset overflow (max 16 signed bits)");
5690 if (reg_needs_delay (GP
))
5699 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5700 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5701 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5702 ((bfd_arch_bits_per_address (stdoutput
) == 32
5703 || mips_opts
.isa
< 3)
5704 ? "addu" : "daddu"),
5705 "d,v,t", AT
, AT
, GP
);
5706 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5707 ((bfd_arch_bits_per_address (stdoutput
) == 32
5708 || mips_opts
.isa
< 3)
5710 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5711 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5714 ((bfd_arch_bits_per_address (stdoutput
) == 32
5715 || mips_opts
.isa
< 3)
5716 ? "addu" : "daddu"),
5717 "d,v,t", AT
, breg
, AT
);
5718 /* Itbl support may require additional care here. */
5719 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5720 coproc
? treg
+ 1 : treg
,
5721 (int) BFD_RELOC_LO16
, AT
);
5722 expr1
.X_add_number
+= 4;
5724 /* Set mips_optimize to 2 to avoid inserting an undesired
5726 hold_mips_optimize
= mips_optimize
;
5728 /* Itbl support may require additional care here. */
5729 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5730 coproc
? treg
: treg
+ 1,
5731 (int) BFD_RELOC_LO16
, AT
);
5732 mips_optimize
= hold_mips_optimize
;
5733 expr1
.X_add_number
-= 4;
5735 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5736 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5737 8 + gpdel
+ off
, 1, 0),
5738 offset_expr
.X_add_symbol
, (offsetT
) 0,
5742 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5745 macro_build (p
, &icnt
, &offset_expr
,
5746 ((bfd_arch_bits_per_address (stdoutput
) == 32
5747 || mips_opts
.isa
< 3)
5749 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5751 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5755 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5756 ((bfd_arch_bits_per_address (stdoutput
) == 32
5757 || mips_opts
.isa
< 3)
5758 ? "addu" : "daddu"),
5759 "d,v,t", AT
, breg
, AT
);
5762 /* Itbl support may require additional care here. */
5763 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5764 coproc
? treg
+ 1 : treg
,
5765 (int) BFD_RELOC_LO16
, AT
);
5767 expr1
.X_add_number
+= 4;
5769 /* Set mips_optimize to 2 to avoid inserting an undesired
5771 hold_mips_optimize
= mips_optimize
;
5773 /* Itbl support may require additional care here. */
5774 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5775 coproc
? treg
: treg
+ 1,
5776 (int) BFD_RELOC_LO16
, AT
);
5777 mips_optimize
= hold_mips_optimize
;
5779 else if (mips_pic
== EMBEDDED_PIC
)
5781 /* If there is no base register, we use
5782 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5783 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5784 If we have a base register, we use
5786 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5787 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5796 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5797 ((bfd_arch_bits_per_address (stdoutput
) == 32
5798 || mips_opts
.isa
< 3)
5799 ? "addu" : "daddu"),
5800 "d,v,t", AT
, breg
, GP
);
5805 /* Itbl support may require additional care here. */
5806 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5807 coproc
? treg
+ 1 : treg
,
5808 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5809 offset_expr
.X_add_number
+= 4;
5810 /* Itbl support may require additional care here. */
5811 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5812 coproc
? treg
: treg
+ 1,
5813 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5829 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
5830 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5831 (int) BFD_RELOC_LO16
, breg
);
5832 offset_expr
.X_add_number
+= 4;
5833 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5834 (int) BFD_RELOC_LO16
, breg
);
5837 /* New code added to support COPZ instructions.
5838 This code builds table entries out of the macros in mip_opcodes.
5839 R4000 uses interlocks to handle coproc delays.
5840 Other chips (like the R3000) require nops to be inserted for delays.
5842 FIXME: Currently, we require that the user handle delays.
5843 In order to fill delay slots for non-interlocked chips,
5844 we must have a way to specify delays based on the coprocessor.
5845 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5846 What are the side-effects of the cop instruction?
5847 What cache support might we have and what are its effects?
5848 Both coprocessor & memory require delays. how long???
5849 What registers are read/set/modified?
5851 If an itbl is provided to interpret cop instructions,
5852 this knowledge can be encoded in the itbl spec. */
5866 /* For now we just do C (same as Cz). The parameter will be
5867 stored in insn_opcode by mips_ip. */
5868 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5872 #ifdef LOSING_COMPILER
5874 /* Try and see if this is a new itbl instruction.
5875 This code builds table entries out of the macros in mip_opcodes.
5876 FIXME: For now we just assemble the expression and pass it's
5877 value along as a 32-bit immediate.
5878 We may want to have the assembler assemble this value,
5879 so that we gain the assembler's knowledge of delay slots,
5881 Would it be more efficient to use mask (id) here? */
5882 if (itbl_have_entries
5883 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5885 s
= ip
->insn_mo
->name
;
5887 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5888 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5895 as_warn ("Macro used $at after \".set noat\"");
5900 struct mips_cl_insn
*ip
;
5902 register int treg
, sreg
, dreg
, breg
;
5917 bfd_reloc_code_real_type r
;
5920 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5921 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5922 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5923 mask
= ip
->insn_mo
->mask
;
5925 expr1
.X_op
= O_constant
;
5926 expr1
.X_op_symbol
= NULL
;
5927 expr1
.X_add_symbol
= NULL
;
5928 expr1
.X_add_number
= 1;
5932 #endif /* LOSING_COMPILER */
5937 macro_build ((char *) NULL
, &icnt
, NULL
,
5938 dbl
? "dmultu" : "multu",
5940 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5946 /* The MIPS assembler some times generates shifts and adds. I'm
5947 not trying to be that fancy. GCC should do this for us
5949 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5950 macro_build ((char *) NULL
, &icnt
, NULL
,
5951 dbl
? "dmult" : "mult",
5953 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5959 mips_emit_delays (true);
5960 ++mips_opts
.noreorder
;
5961 mips_any_noreorder
= 1;
5962 macro_build ((char *) NULL
, &icnt
, NULL
,
5963 dbl
? "dmult" : "mult",
5965 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5966 macro_build ((char *) NULL
, &icnt
, NULL
,
5967 dbl
? "dsra32" : "sra",
5968 "d,w,<", dreg
, dreg
, 31);
5969 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5971 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5974 expr1
.X_add_number
= 8;
5975 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5976 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5977 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5979 --mips_opts
.noreorder
;
5980 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5986 mips_emit_delays (true);
5987 ++mips_opts
.noreorder
;
5988 mips_any_noreorder
= 1;
5989 macro_build ((char *) NULL
, &icnt
, NULL
,
5990 dbl
? "dmultu" : "multu",
5992 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5993 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5998 expr1
.X_add_number
= 8;
5999 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6000 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6003 --mips_opts
.noreorder
;
6007 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6008 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6009 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6011 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6015 if (imm_expr
.X_op
!= O_constant
)
6016 as_bad ("rotate count too large");
6017 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6018 (int) (imm_expr
.X_add_number
& 0x1f));
6019 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6020 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6021 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6025 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6026 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6029 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6033 if (imm_expr
.X_op
!= O_constant
)
6034 as_bad ("rotate count too large");
6035 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6036 (int) (imm_expr
.X_add_number
& 0x1f));
6037 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6038 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6039 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6045 as_bad ("opcode not supported on this processor");
6048 assert (mips_opts
.isa
< 2);
6049 /* Even on a big endian machine $fn comes before $fn+1. We have
6050 to adjust when storing to memory. */
6051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6052 target_big_endian
? treg
+ 1 : treg
,
6053 (int) BFD_RELOC_LO16
, breg
);
6054 offset_expr
.X_add_number
+= 4;
6055 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6056 target_big_endian
? treg
: treg
+ 1,
6057 (int) BFD_RELOC_LO16
, breg
);
6062 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6063 treg
, (int) BFD_RELOC_LO16
);
6065 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6066 sreg
, (int) BFD_RELOC_LO16
);
6069 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6071 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6072 dreg
, (int) BFD_RELOC_LO16
);
6077 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6079 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6080 sreg
, (int) BFD_RELOC_LO16
);
6085 as_warn ("Instruction %s: result is always false",
6087 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6090 if (imm_expr
.X_op
== O_constant
6091 && imm_expr
.X_add_number
>= 0
6092 && imm_expr
.X_add_number
< 0x10000)
6094 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6095 sreg
, (int) BFD_RELOC_LO16
);
6098 else if (imm_expr
.X_op
== O_constant
6099 && imm_expr
.X_add_number
> -0x8000
6100 && imm_expr
.X_add_number
< 0)
6102 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6103 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6104 ((bfd_arch_bits_per_address (stdoutput
) == 32
6105 || mips_opts
.isa
< 3)
6106 ? "addiu" : "daddiu"),
6107 "t,r,j", dreg
, sreg
,
6108 (int) BFD_RELOC_LO16
);
6113 load_register (&icnt
, AT
, &imm_expr
, 0);
6114 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6118 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6119 (int) BFD_RELOC_LO16
);
6124 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6130 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6131 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6132 (int) BFD_RELOC_LO16
);
6135 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6137 if (imm_expr
.X_op
== O_constant
6138 && imm_expr
.X_add_number
>= -0x8000
6139 && imm_expr
.X_add_number
< 0x8000)
6141 macro_build ((char *) NULL
, &icnt
, &expr1
,
6142 mask
== M_SGE_I
? "slti" : "sltiu",
6143 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6148 load_register (&icnt
, AT
, &imm_expr
, 0);
6149 macro_build ((char *) NULL
, &icnt
, NULL
,
6150 mask
== M_SGE_I
? "slt" : "sltu",
6151 "d,v,t", dreg
, sreg
, AT
);
6154 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6155 (int) BFD_RELOC_LO16
);
6160 case M_SGT
: /* sreg > treg <==> treg < sreg */
6166 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6169 case M_SGT_I
: /* sreg > I <==> I < sreg */
6175 load_register (&icnt
, AT
, &imm_expr
, 0);
6176 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6179 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6185 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6186 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6187 (int) BFD_RELOC_LO16
);
6190 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6196 load_register (&icnt
, AT
, &imm_expr
, 0);
6197 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6198 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6199 (int) BFD_RELOC_LO16
);
6203 if (imm_expr
.X_op
== O_constant
6204 && imm_expr
.X_add_number
>= -0x8000
6205 && imm_expr
.X_add_number
< 0x8000)
6207 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6208 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6211 load_register (&icnt
, AT
, &imm_expr
, 0);
6212 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6216 if (imm_expr
.X_op
== O_constant
6217 && imm_expr
.X_add_number
>= -0x8000
6218 && imm_expr
.X_add_number
< 0x8000)
6220 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6221 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6224 load_register (&icnt
, AT
, &imm_expr
, 0);
6225 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6231 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6234 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6238 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6240 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6246 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6248 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6254 as_warn ("Instruction %s: result is always true",
6256 macro_build ((char *) NULL
, &icnt
, &expr1
,
6257 ((bfd_arch_bits_per_address (stdoutput
) == 32
6258 || mips_opts
.isa
< 3)
6259 ? "addiu" : "daddiu"),
6260 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6263 if (imm_expr
.X_op
== O_constant
6264 && imm_expr
.X_add_number
>= 0
6265 && imm_expr
.X_add_number
< 0x10000)
6267 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6268 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6271 else if (imm_expr
.X_op
== O_constant
6272 && imm_expr
.X_add_number
> -0x8000
6273 && imm_expr
.X_add_number
< 0)
6275 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6276 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6277 ((bfd_arch_bits_per_address (stdoutput
) == 32
6278 || mips_opts
.isa
< 3)
6279 ? "addiu" : "daddiu"),
6280 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6285 load_register (&icnt
, AT
, &imm_expr
, 0);
6286 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6290 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6298 if (imm_expr
.X_op
== O_constant
6299 && imm_expr
.X_add_number
> -0x8000
6300 && imm_expr
.X_add_number
<= 0x8000)
6302 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6303 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6304 dbl
? "daddi" : "addi",
6305 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6308 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6309 macro_build ((char *) NULL
, &icnt
, NULL
,
6310 dbl
? "dsub" : "sub",
6311 "d,v,t", dreg
, sreg
, AT
);
6317 if (imm_expr
.X_op
== O_constant
6318 && imm_expr
.X_add_number
> -0x8000
6319 && imm_expr
.X_add_number
<= 0x8000)
6321 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6322 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6323 dbl
? "daddiu" : "addiu",
6324 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6327 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6328 macro_build ((char *) NULL
, &icnt
, NULL
,
6329 dbl
? "dsubu" : "subu",
6330 "d,v,t", dreg
, sreg
, AT
);
6351 load_register (&icnt
, AT
, &imm_expr
, 0);
6352 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6357 assert (mips_opts
.isa
< 2);
6358 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6359 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6362 * Is the double cfc1 instruction a bug in the mips assembler;
6363 * or is there a reason for it?
6365 mips_emit_delays (true);
6366 ++mips_opts
.noreorder
;
6367 mips_any_noreorder
= 1;
6368 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6369 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6370 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6371 expr1
.X_add_number
= 3;
6372 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6373 (int) BFD_RELOC_LO16
);
6374 expr1
.X_add_number
= 2;
6375 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6376 (int) BFD_RELOC_LO16
);
6377 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6378 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6379 macro_build ((char *) NULL
, &icnt
, NULL
,
6380 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6381 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6382 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6383 --mips_opts
.noreorder
;
6392 if (offset_expr
.X_add_number
>= 0x7fff)
6393 as_bad ("operand overflow");
6394 /* avoid load delay */
6395 if (! target_big_endian
)
6396 offset_expr
.X_add_number
+= 1;
6397 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6398 (int) BFD_RELOC_LO16
, breg
);
6399 if (! target_big_endian
)
6400 offset_expr
.X_add_number
-= 1;
6402 offset_expr
.X_add_number
+= 1;
6403 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6404 (int) BFD_RELOC_LO16
, breg
);
6405 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6406 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6419 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6420 as_bad ("operand overflow");
6421 if (! target_big_endian
)
6422 offset_expr
.X_add_number
+= off
;
6423 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6424 (int) BFD_RELOC_LO16
, breg
);
6425 if (! target_big_endian
)
6426 offset_expr
.X_add_number
-= off
;
6428 offset_expr
.X_add_number
+= off
;
6429 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6430 (int) BFD_RELOC_LO16
, breg
);
6443 load_address (&icnt
, AT
, &offset_expr
);
6445 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6446 ((bfd_arch_bits_per_address (stdoutput
) == 32
6447 || mips_opts
.isa
< 3)
6448 ? "addu" : "daddu"),
6449 "d,v,t", AT
, AT
, breg
);
6450 if (! target_big_endian
)
6451 expr1
.X_add_number
= off
;
6453 expr1
.X_add_number
= 0;
6454 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6455 (int) BFD_RELOC_LO16
, AT
);
6456 if (! target_big_endian
)
6457 expr1
.X_add_number
= 0;
6459 expr1
.X_add_number
= off
;
6460 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6461 (int) BFD_RELOC_LO16
, AT
);
6466 load_address (&icnt
, AT
, &offset_expr
);
6468 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6469 ((bfd_arch_bits_per_address (stdoutput
) == 32
6470 || mips_opts
.isa
< 3)
6471 ? "addu" : "daddu"),
6472 "d,v,t", AT
, AT
, breg
);
6473 if (target_big_endian
)
6474 expr1
.X_add_number
= 0;
6475 macro_build ((char *) NULL
, &icnt
, &expr1
,
6476 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6477 (int) BFD_RELOC_LO16
, AT
);
6478 if (target_big_endian
)
6479 expr1
.X_add_number
= 1;
6481 expr1
.X_add_number
= 0;
6482 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6483 (int) BFD_RELOC_LO16
, AT
);
6484 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6486 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6491 if (offset_expr
.X_add_number
>= 0x7fff)
6492 as_bad ("operand overflow");
6493 if (target_big_endian
)
6494 offset_expr
.X_add_number
+= 1;
6495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6496 (int) BFD_RELOC_LO16
, breg
);
6497 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6498 if (target_big_endian
)
6499 offset_expr
.X_add_number
-= 1;
6501 offset_expr
.X_add_number
+= 1;
6502 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6503 (int) BFD_RELOC_LO16
, breg
);
6516 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6517 as_bad ("operand overflow");
6518 if (! target_big_endian
)
6519 offset_expr
.X_add_number
+= off
;
6520 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6521 (int) BFD_RELOC_LO16
, breg
);
6522 if (! target_big_endian
)
6523 offset_expr
.X_add_number
-= off
;
6525 offset_expr
.X_add_number
+= off
;
6526 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6527 (int) BFD_RELOC_LO16
, breg
);
6540 load_address (&icnt
, AT
, &offset_expr
);
6542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6543 ((bfd_arch_bits_per_address (stdoutput
) == 32
6544 || mips_opts
.isa
< 3)
6545 ? "addu" : "daddu"),
6546 "d,v,t", AT
, AT
, breg
);
6547 if (! target_big_endian
)
6548 expr1
.X_add_number
= off
;
6550 expr1
.X_add_number
= 0;
6551 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6552 (int) BFD_RELOC_LO16
, AT
);
6553 if (! target_big_endian
)
6554 expr1
.X_add_number
= 0;
6556 expr1
.X_add_number
= off
;
6557 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6558 (int) BFD_RELOC_LO16
, AT
);
6562 load_address (&icnt
, AT
, &offset_expr
);
6564 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6565 ((bfd_arch_bits_per_address (stdoutput
) == 32
6566 || mips_opts
.isa
< 3)
6567 ? "addu" : "daddu"),
6568 "d,v,t", AT
, AT
, breg
);
6569 if (! target_big_endian
)
6570 expr1
.X_add_number
= 0;
6571 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6572 (int) BFD_RELOC_LO16
, AT
);
6573 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6575 if (! target_big_endian
)
6576 expr1
.X_add_number
= 1;
6578 expr1
.X_add_number
= 0;
6579 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6580 (int) BFD_RELOC_LO16
, AT
);
6581 if (! target_big_endian
)
6582 expr1
.X_add_number
= 0;
6584 expr1
.X_add_number
= 1;
6585 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6586 (int) BFD_RELOC_LO16
, AT
);
6587 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6589 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6594 /* FIXME: Check if this is one of the itbl macros, since they
6595 are added dynamically. */
6596 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6600 as_warn ("Macro used $at after \".set noat\"");
6603 /* Implement macros in mips16 mode. */
6607 struct mips_cl_insn
*ip
;
6610 int xreg
, yreg
, zreg
, tmp
;
6614 const char *s
, *s2
, *s3
;
6616 mask
= ip
->insn_mo
->mask
;
6618 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6619 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6620 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6624 expr1
.X_op
= O_constant
;
6625 expr1
.X_op_symbol
= NULL
;
6626 expr1
.X_add_symbol
= NULL
;
6627 expr1
.X_add_number
= 1;
6646 mips_emit_delays (true);
6647 ++mips_opts
.noreorder
;
6648 mips_any_noreorder
= 1;
6649 macro_build ((char *) NULL
, &icnt
, NULL
,
6650 dbl
? "ddiv" : "div",
6651 "0,x,y", xreg
, yreg
);
6652 expr1
.X_add_number
= 2;
6653 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6654 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6655 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6656 since that causes an overflow. We should do that as well,
6657 but I don't see how to do the comparisons without a temporary
6659 --mips_opts
.noreorder
;
6660 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6679 mips_emit_delays (true);
6680 ++mips_opts
.noreorder
;
6681 mips_any_noreorder
= 1;
6682 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6683 expr1
.X_add_number
= 2;
6684 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6685 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6686 --mips_opts
.noreorder
;
6687 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6693 macro_build ((char *) NULL
, &icnt
, NULL
,
6694 dbl
? "dmultu" : "multu",
6696 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6704 if (imm_expr
.X_op
!= O_constant
)
6705 as_bad ("Unsupported large constant");
6706 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6707 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6708 dbl
? "daddiu" : "addiu",
6709 "y,x,4", yreg
, xreg
);
6713 if (imm_expr
.X_op
!= O_constant
)
6714 as_bad ("Unsupported large constant");
6715 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6716 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6721 if (imm_expr
.X_op
!= O_constant
)
6722 as_bad ("Unsupported large constant");
6723 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6724 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6747 goto do_reverse_branch
;
6751 goto do_reverse_branch
;
6763 goto do_reverse_branch
;
6774 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6776 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6803 goto do_addone_branch_i
;
6808 goto do_addone_branch_i
;
6823 goto do_addone_branch_i
;
6830 if (imm_expr
.X_op
!= O_constant
)
6831 as_bad ("Unsupported large constant");
6832 ++imm_expr
.X_add_number
;
6835 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6836 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6840 expr1
.X_add_number
= 0;
6841 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6843 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6844 "move", "y,X", xreg
, yreg
);
6845 expr1
.X_add_number
= 2;
6846 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6847 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6848 "neg", "x,w", xreg
, xreg
);
6852 /* For consistency checking, verify that all bits are specified either
6853 by the match/mask part of the instruction definition, or by the
6856 validate_mips_insn (opc
)
6857 const struct mips_opcode
*opc
;
6859 const char *p
= opc
->args
;
6861 unsigned long used_bits
= opc
->mask
;
6863 if ((used_bits
& opc
->match
) != opc
->match
)
6865 as_bad ("internal: bad mips opcode (mask error): %s %s",
6866 opc
->name
, opc
->args
);
6869 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6876 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6877 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6879 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6880 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6881 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6882 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6884 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6887 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6888 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6889 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6890 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6891 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6892 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6893 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6894 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6895 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6896 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6897 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6899 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6900 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6901 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6902 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6904 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6905 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6906 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6907 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6908 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6909 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6910 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6911 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6914 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6915 /* start-sanitize-vr5400 */
6916 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
6917 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
6920 /* end-sanitize-vr5400 */
6922 as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s",
6923 c
, opc
->name
, opc
->args
);
6927 /* Some of the trapping instructions (break, t*, sdbbp) have "code"
6928 fields that cannot currently be set by assembly code. Ignore them
6930 if (opc
->pinfo
& INSN_TRAP
)
6932 static const char *const trap_insns
[] = {
6934 "teq", "tge", "tgeu", "tlt", "tltu", "tne",
6937 for (i
= sizeof(trap_insns
)/sizeof(trap_insns
[0]) - 1; i
>= 0; i
--)
6938 if (!strcmp (trap_insns
[i
], opc
->name
))
6940 used_bits
|= 0xffc0;
6944 if (used_bits
!= 0xffffffff)
6946 as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s",
6947 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6953 /* This routine assembles an instruction into its binary format. As a
6954 side effect, it sets one of the global variables imm_reloc or
6955 offset_reloc to the type of relocation to do if one of the operands
6956 is an address expression. */
6961 struct mips_cl_insn
*ip
;
6966 struct mips_opcode
*insn
;
6969 unsigned int lastregno
= 0;
6975 /* If the instruction contains a '.', we first try to match an instruction
6976 including the '.'. Then we try again without the '.'. */
6978 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6981 /* If we stopped on whitespace, then replace the whitespace with null for
6982 the call to hash_find. Save the character we replaced just in case we
6983 have to re-parse the instruction. */
6990 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
6992 /* If we didn't find the instruction in the opcode table, try again, but
6993 this time with just the instruction up to, but not including the
6997 /* Restore the character we overwrite above (if any). */
7001 /* Scan up to the first '.' or whitespace. */
7002 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
7005 /* If we did not find a '.', then we can quit now. */
7008 insn_error
= "unrecognized opcode";
7012 /* Lookup the instruction in the hash table. */
7014 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7016 insn_error
= "unrecognized opcode";
7027 assert (strcmp (insn
->name
, str
) == 0);
7029 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7031 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7033 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7035 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7040 if (insn_isa
<= mips_opts
.isa
)
7042 else if (insn
->pinfo
== INSN_MACRO
)
7044 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7045 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7046 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7047 /* start-sanitize-vr4320 */
7048 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7049 /* end-sanitize-vr4320 */
7050 /* start-sanitize-tx49 */
7051 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7052 /* end-sanitize-tx49 */
7053 /* start-sanitize-r5900 */
7054 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7055 /* end-sanitize-r5900 */
7056 /* start-sanitize-vr5400 */
7057 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7058 /* end-sanitize-vr5400 */
7059 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7064 if (insn
->pinfo
!= INSN_MACRO
)
7066 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7068 /* start-sanitize-r5900 */
7069 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7071 /* end-sanitize-r5900 */
7076 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7077 && strcmp (insn
->name
, insn
[1].name
) == 0)
7083 || insn_isa
<= mips_opts
.isa
)
7084 insn_error
= "opcode not supported on this processor";
7087 static char buf
[100];
7089 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
7096 ip
->insn_opcode
= insn
->match
;
7097 for (args
= insn
->args
;; ++args
)
7103 case '\0': /* end of args */
7116 ip
->insn_opcode
|= lastregno
<< 21;
7121 ip
->insn_opcode
|= lastregno
<< 16;
7125 ip
->insn_opcode
|= lastregno
<< 11;
7131 /* Handle optional base register.
7132 Either the base register is omitted or
7133 we must have a left paren. */
7134 /* This is dependent on the next operand specifier
7135 is a base register specification. */
7136 assert (args
[1] == 'b' || args
[1] == '5'
7137 || args
[1] == '-' || args
[1] == '4');
7141 case ')': /* these must match exactly */
7142 /* start-sanitize-vr5400 */
7145 /* end-sanitize-vr5400 */
7146 /* start-sanitize-r5900 */
7149 /* end-sanitize-r5900 */
7154 case '<': /* must be at least one digit */
7156 * According to the manual, if the shift amount is greater
7157 * than 31 or less than 0 the the shift amount should be
7158 * mod 32. In reality the mips assembler issues an error.
7159 * We issue a warning and mask out all but the low 5 bits.
7161 my_getExpression (&imm_expr
, s
);
7162 check_absolute_expr (ip
, &imm_expr
);
7163 if ((unsigned long) imm_expr
.X_add_number
> 31)
7165 as_warn ("Improper shift amount (%ld)",
7166 (long) imm_expr
.X_add_number
);
7167 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7169 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7170 imm_expr
.X_op
= O_absent
;
7174 case '>': /* shift amount minus 32 */
7175 my_getExpression (&imm_expr
, s
);
7176 check_absolute_expr (ip
, &imm_expr
);
7177 if ((unsigned long) imm_expr
.X_add_number
< 32
7178 || (unsigned long) imm_expr
.X_add_number
> 63)
7180 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7181 imm_expr
.X_op
= O_absent
;
7185 /* start-sanitize-r5900 */
7186 case '0': /* 5 bit signed immediate at 6 */
7187 my_getExpression (&imm_expr
, s
);
7188 check_absolute_expr (ip
, &imm_expr
);
7189 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7190 || ((imm_expr
.X_add_number
< -16
7191 || imm_expr
.X_add_number
>= 16)
7192 && imm_expr
.X_op
== O_constant
))
7194 if (imm_expr
.X_op
!= O_constant
7195 && imm_expr
.X_op
!= O_big
)
7196 insn_error
= "absolute expression required";
7198 as_bad ("5 bit expression not in range -16..15");
7200 ip
->insn_opcode
|= (imm_expr
.X_add_number
) << 6;
7201 imm_expr
.X_op
= O_absent
;
7205 case '9': /* vi19 for vcallmsr */
7206 if (strncmp (s
, "vi19", 4) == 0)
7209 as_bad ("expected vi19");
7212 case '#': /* escape character */
7213 /* '#' specifies that we've got an optional suffix to this
7214 operand that must match exactly (if it exists). */
7215 if (*s
!= '\0' && *s
!= ','
7216 && *s
!= ' ' && *s
!= '\t' && *s
!= '\n')
7218 if (*s
== *(args
+ 1))
7229 case 'K': /* DEST operand completer (optional), must
7230 match previous dest if specified. */
7231 case '&': /* DEST instruction completer */
7238 /* Parse the completer. */
7240 while (*s
!= '\0' && *s
!= ' ' && *s
!= ',')
7252 insn_error
= "Invalid dest specification";
7258 /* Each completer can only appear once. */
7259 if (w
> 1 || x
> 1 || y
> 1 || z
> 1)
7261 insn_error
= "Invalid dest specification";
7265 /* If this is the opcode completer, then we must insert
7266 the appropriate value into the insn. */
7269 ip
->insn_opcode
|= ((w
<< 21) | (x
<< 24)
7270 | (y
<< 23) | (z
<< 22));
7271 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7277 /* This is the operand completer, make sure it matches
7278 the previous opcode completer. */
7279 temp
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7280 if (temp
&& temp
!= last_h
)
7282 insn_error
= "DEST field in operand does not match DEST field in instruction";
7291 case 'J': /* vu0 I register */
7295 insn_error
= "operand `I' expected";
7298 case 'Q': /* vu0 Q register */
7302 insn_error
= "operand `Q' expected";
7305 case 'X': /* vu0 R register */
7309 insn_error
= "operand `R' expected";
7312 case 'U': /* vu0 ACC register */
7313 if (s
[0] == 'A' && s
[1] == 'C' && s
[2] == 'C')
7316 insn_error
= "operand `ACC' expected";
7320 my_getSmallExpression (&imm_expr
, s
);
7321 imm_reloc
= BFD_RELOC_MIPS15_S3
;
7324 /* end-sanitize-r5900 */
7326 case 'k': /* cache code */
7327 case 'h': /* prefx code */
7328 my_getExpression (&imm_expr
, s
);
7329 check_absolute_expr (ip
, &imm_expr
);
7330 if ((unsigned long) imm_expr
.X_add_number
> 31)
7332 as_warn ("Invalid value for `%s' (%lu)",
7334 (unsigned long) imm_expr
.X_add_number
);
7335 imm_expr
.X_add_number
&= 0x1f;
7338 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7340 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7341 imm_expr
.X_op
= O_absent
;
7345 case 'c': /* break code */
7346 my_getExpression (&imm_expr
, s
);
7347 check_absolute_expr (ip
, &imm_expr
);
7348 if ((unsigned) imm_expr
.X_add_number
> 1023)
7349 as_warn ("Illegal break code (%ld)",
7350 (long) imm_expr
.X_add_number
);
7351 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7352 imm_expr
.X_op
= O_absent
;
7356 case 'B': /* syscall code */
7357 my_getExpression (&imm_expr
, s
);
7358 check_absolute_expr (ip
, &imm_expr
);
7359 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7360 as_warn ("Illegal syscall code (%ld)",
7361 (long) imm_expr
.X_add_number
);
7362 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7363 imm_expr
.X_op
= O_absent
;
7367 case 'C': /* Coprocessor code */
7368 my_getExpression (&imm_expr
, s
);
7369 check_absolute_expr (ip
, &imm_expr
);
7370 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7372 as_warn ("Coproccesor code > 25 bits (%ld)",
7373 (long) imm_expr
.X_add_number
);
7374 imm_expr
.X_add_number
&= ((1<<25) - 1);
7376 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7377 imm_expr
.X_op
= O_absent
;
7381 case 'P': /* Performance register */
7382 my_getExpression (&imm_expr
, s
);
7383 check_absolute_expr (ip
, &imm_expr
);
7384 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7386 as_warn ("Invalidate performance regster (%ld)",
7387 (long) imm_expr
.X_add_number
);
7388 imm_expr
.X_add_number
&= 1;
7390 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7391 imm_expr
.X_op
= O_absent
;
7395 case 'b': /* base register */
7396 case 'd': /* destination register */
7397 case 's': /* source register */
7398 case 't': /* target register */
7399 case 'r': /* both target and source */
7400 case 'v': /* both dest and source */
7401 case 'w': /* both dest and target */
7402 case 'E': /* coprocessor target register */
7403 case 'G': /* coprocessor destination register */
7404 case 'x': /* ignore register name */
7405 case 'z': /* must be zero register */
7419 while (isdigit (*s
));
7421 as_bad ("Invalid register number (%d)", regno
);
7423 else if (*args
== 'E' || *args
== 'G')
7427 if (s
[1] == 'f' && s
[2] == 'p')
7432 else if (s
[1] == 's' && s
[2] == 'p')
7437 else if (s
[1] == 'g' && s
[2] == 'p')
7442 else if (s
[1] == 'a' && s
[2] == 't')
7447 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7452 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7457 else if (itbl_have_entries
)
7462 p
= s
+1; /* advance past '$' */
7463 n
= itbl_get_field (&p
); /* n is name */
7465 /* See if this is a register defined in an
7467 r
= itbl_get_reg_val (n
);
7470 /* Get_field advances to the start of
7471 the next field, so we need to back
7472 rack to the end of the last field. */
7476 s
= strchr (s
,'\0');
7489 as_warn ("Used $at without \".set noat\"");
7495 if (c
== 'r' || c
== 'v' || c
== 'w')
7502 /* 'z' only matches $0. */
7503 if (c
== 'z' && regno
!= 0)
7506 /* Now that we have assembled one operand, we use the args string
7507 * to figure out where it goes in the instruction. */
7514 ip
->insn_opcode
|= regno
<< 21;
7518 ip
->insn_opcode
|= regno
<< 11;
7523 ip
->insn_opcode
|= regno
<< 16;
7526 /* This case exists because on the r3000 trunc
7527 expands into a macro which requires a gp
7528 register. On the r6000 or r4000 it is
7529 assembled into a single instruction which
7530 ignores the register. Thus the insn version
7531 is MIPS_ISA2 and uses 'x', and the macro
7532 version is MIPS_ISA1 and uses 't'. */
7535 /* This case is for the div instruction, which
7536 acts differently if the destination argument
7537 is $0. This only matches $0, and is checked
7538 outside the switch. */
7541 /* Itbl operand; not yet implemented. FIXME ?? */
7543 /* What about all other operands like 'i', which
7544 can be specified in the opcode table? */
7554 ip
->insn_opcode
|= lastregno
<< 21;
7557 ip
->insn_opcode
|= lastregno
<< 16;
7562 case 'D': /* floating point destination register */
7563 case 'S': /* floating point source register */
7564 case 'T': /* floating point target register */
7565 case 'R': /* floating point source register */
7568 /* start-sanitize-r5900 */
7569 case '1': /* vu0 fp reg position 1 */
7570 case '2': /* vu0 fp reg position 2 */
7571 case '3': /* vu0 fp reg position 3 */
7572 case '4': /* vu0 int reg position 1 */
7573 case '5': /* vu0 int reg position 2 */
7574 case '6': /* vu0 int reg position 3 */
7575 case '7': /* vu0 fp reg with ftf modifier */
7576 case '8': /* vu0 fp reg with fsf modifier */
7577 /* end-sanitize-r5900 */
7579 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7589 while (isdigit (*s
));
7592 as_bad ("Invalid float register number (%d)", regno
);
7594 if ((regno
& 1) != 0
7595 && mips_opts
.isa
< 3
7596 && ! (strcmp (str
, "mtc1") == 0
7597 || strcmp (str
, "mfc1") == 0
7598 || strcmp (str
, "lwc1") == 0
7599 || strcmp (str
, "swc1") == 0
7600 || strcmp (str
, "l.s") == 0
7601 || strcmp (str
, "s.s") == 0))
7602 as_warn ("Float register should be even, was %d",
7610 if (c
== 'V' || c
== 'W')
7620 ip
->insn_opcode
|= regno
<< 6;
7624 ip
->insn_opcode
|= regno
<< 11;
7628 ip
->insn_opcode
|= regno
<< 16;
7631 ip
->insn_opcode
|= regno
<< 21;
7638 /* start-sanitize-r5900 */
7639 /* Handle vf and vi regsiters for vu0. */
7641 && (s
[1] == 'f' || s
[1] == 'i')
7652 while (isdigit (*s
));
7655 as_bad ("Invalid vu0 register number (%d)", regno
);
7659 if (c
== '7' || c
== '8')
7668 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7673 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7678 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7683 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7686 as_bad ("Invalid FSF/FTF specification");
7694 if (c
== 'V' || c
== 'W')
7706 ip
->insn_opcode
|= regno
<< 16;
7711 ip
->insn_opcode
|= regno
<< 11;
7715 ip
->insn_opcode
|= regno
<< 6;
7721 /* end-sanitize-r5900 */
7726 ip
->insn_opcode
|= lastregno
<< 11;
7729 ip
->insn_opcode
|= lastregno
<< 16;
7735 my_getExpression (&imm_expr
, s
);
7736 if (imm_expr
.X_op
!= O_big
7737 && imm_expr
.X_op
!= O_constant
)
7738 insn_error
= "absolute expression required";
7743 my_getExpression (&offset_expr
, s
);
7744 imm_reloc
= BFD_RELOC_32
;
7756 unsigned char temp
[8];
7758 unsigned int length
;
7763 /* These only appear as the last operand in an
7764 instruction, and every instruction that accepts
7765 them in any variant accepts them in all variants.
7766 This means we don't have to worry about backing out
7767 any changes if the instruction does not match.
7769 The difference between them is the size of the
7770 floating point constant and where it goes. For 'F'
7771 and 'L' the constant is 64 bits; for 'f' and 'l' it
7772 is 32 bits. Where the constant is placed is based
7773 on how the MIPS assembler does things:
7776 f -- immediate value
7779 The .lit4 and .lit8 sections are only used if
7780 permitted by the -G argument.
7782 When generating embedded PIC code, we use the
7783 .lit8 section but not the .lit4 section (we can do
7784 .lit4 inline easily; we need to put .lit8
7785 somewhere in the data segment, and using .lit8
7786 permits the linker to eventually combine identical
7789 f64
= *args
== 'F' || *args
== 'L';
7791 save_in
= input_line_pointer
;
7792 input_line_pointer
= s
;
7793 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7795 s
= input_line_pointer
;
7796 input_line_pointer
= save_in
;
7797 if (err
!= NULL
&& *err
!= '\0')
7799 as_bad ("Bad floating point constant: %s", err
);
7800 memset (temp
, '\0', sizeof temp
);
7801 length
= f64
? 8 : 4;
7804 assert (length
== (f64
? 8 : 4));
7808 && (! USE_GLOBAL_POINTER_OPT
7809 || mips_pic
== EMBEDDED_PIC
7810 || g_switch_value
< 4
7811 || (temp
[0] == 0 && temp
[1] == 0)
7812 || (temp
[2] == 0 && temp
[3] == 0))))
7814 imm_expr
.X_op
= O_constant
;
7815 if (! target_big_endian
)
7816 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7818 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7821 && ((temp
[0] == 0 && temp
[1] == 0)
7822 || (temp
[2] == 0 && temp
[3] == 0))
7823 && ((temp
[4] == 0 && temp
[5] == 0)
7824 || (temp
[6] == 0 && temp
[7] == 0)))
7826 /* The value is simple enough to load with a
7827 couple of instructions. In mips1 mode, set
7828 imm_expr to the high order 32 bits and
7829 offset_expr to the low order 32 bits.
7830 Otherwise, set imm_expr to the entire 64 bit
7832 if (mips_opts
.isa
< 3)
7834 imm_expr
.X_op
= O_constant
;
7835 offset_expr
.X_op
= O_constant
;
7836 if (! target_big_endian
)
7838 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7839 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7843 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7844 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7846 if (offset_expr
.X_add_number
== 0)
7847 offset_expr
.X_op
= O_absent
;
7849 else if (sizeof (imm_expr
.X_add_number
) > 4)
7851 imm_expr
.X_op
= O_constant
;
7852 if (! target_big_endian
)
7853 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7855 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7859 imm_expr
.X_op
= O_big
;
7860 imm_expr
.X_add_number
= 4;
7861 if (! target_big_endian
)
7863 generic_bignum
[0] = bfd_getl16 (temp
);
7864 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7865 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7866 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7870 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7871 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7872 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7873 generic_bignum
[3] = bfd_getb16 (temp
);
7879 const char *newname
;
7882 /* Switch to the right section. */
7884 subseg
= now_subseg
;
7887 default: /* unused default case avoids warnings. */
7889 newname
= RDATA_SECTION_NAME
;
7890 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7894 newname
= RDATA_SECTION_NAME
;
7897 assert (!USE_GLOBAL_POINTER_OPT
7898 || g_switch_value
>= 4);
7902 new_seg
= subseg_new (newname
, (subsegT
) 0);
7903 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7904 bfd_set_section_flags (stdoutput
, new_seg
,
7909 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7910 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7911 && strcmp (TARGET_OS
, "elf") != 0)
7912 record_alignment (new_seg
, 4);
7914 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7916 as_bad ("Can't use floating point insn in this section");
7918 /* Set the argument to the current address in the
7920 offset_expr
.X_op
= O_symbol
;
7921 offset_expr
.X_add_symbol
=
7922 symbol_new ("L0\001", now_seg
,
7923 (valueT
) frag_now_fix (), frag_now
);
7924 offset_expr
.X_add_number
= 0;
7926 /* Put the floating point number into the section. */
7927 p
= frag_more ((int) length
);
7928 memcpy (p
, temp
, length
);
7930 /* Switch back to the original section. */
7931 subseg_set (seg
, subseg
);
7936 case 'i': /* 16 bit unsigned immediate */
7937 case 'j': /* 16 bit signed immediate */
7938 imm_reloc
= BFD_RELOC_LO16
;
7939 c
= my_getSmallExpression (&imm_expr
, s
);
7944 if (imm_expr
.X_op
== O_constant
)
7945 imm_expr
.X_add_number
=
7946 (imm_expr
.X_add_number
>> 16) & 0xffff;
7949 imm_reloc
= BFD_RELOC_HI16_S
;
7950 imm_unmatched_hi
= true;
7953 imm_reloc
= BFD_RELOC_HI16
;
7958 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7959 || ((imm_expr
.X_add_number
< 0
7960 || imm_expr
.X_add_number
>= 0x10000)
7961 && imm_expr
.X_op
== O_constant
))
7963 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7964 !strcmp (insn
->name
, insn
[1].name
))
7966 if (imm_expr
.X_op
!= O_constant
7967 && imm_expr
.X_op
!= O_big
)
7968 insn_error
= "absolute expression required";
7970 as_bad ("16 bit expression not in range 0..65535");
7978 /* The upper bound should be 0x8000, but
7979 unfortunately the MIPS assembler accepts numbers
7980 from 0x8000 to 0xffff and sign extends them, and
7981 we want to be compatible. We only permit this
7982 extended range for an instruction which does not
7983 provide any further alternates, since those
7984 alternates may handle other cases. People should
7985 use the numbers they mean, rather than relying on
7986 a mysterious sign extension. */
7987 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7988 strcmp (insn
->name
, insn
[1].name
) == 0);
7993 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7994 || ((imm_expr
.X_add_number
< -0x8000
7995 || imm_expr
.X_add_number
>= max
)
7996 && imm_expr
.X_op
== O_constant
)
7998 && imm_expr
.X_add_number
< 0
7999 && mips_opts
.isa
>= 3
8000 && imm_expr
.X_unsigned
8001 && sizeof (imm_expr
.X_add_number
) <= 4))
8005 if (imm_expr
.X_op
!= O_constant
8006 && imm_expr
.X_op
!= O_big
)
8007 insn_error
= "absolute expression required";
8009 as_bad ("16 bit expression not in range -32768..32767");
8015 case 'o': /* 16 bit offset */
8016 c
= my_getSmallExpression (&offset_expr
, s
);
8018 /* If this value won't fit into a 16 bit offset, then go
8019 find a macro that will generate the 32 bit offset
8020 code pattern. As a special hack, we accept the
8021 difference of two local symbols as a constant. This
8022 is required to suppose embedded PIC switches, which
8023 use an instruction which looks like
8024 lw $4,$L12-$LS12($4)
8025 The problem with handling this in a more general
8026 fashion is that the macro function doesn't expect to
8027 see anything which can be handled in a single
8028 constant instruction. */
8030 && (offset_expr
.X_op
!= O_constant
8031 || offset_expr
.X_add_number
>= 0x8000
8032 || offset_expr
.X_add_number
< -0x8000)
8033 && (mips_pic
!= EMBEDDED_PIC
8034 || offset_expr
.X_op
!= O_subtract
8035 || now_seg
!= text_section
8036 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
8040 offset_reloc
= BFD_RELOC_LO16
;
8041 if (c
== 'h' || c
== 'H')
8043 assert (offset_expr
.X_op
== O_constant
);
8044 offset_expr
.X_add_number
=
8045 (offset_expr
.X_add_number
>> 16) & 0xffff;
8050 case 'p': /* pc relative offset */
8051 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8052 my_getExpression (&offset_expr
, s
);
8056 case 'u': /* upper 16 bits */
8057 c
= my_getSmallExpression (&imm_expr
, s
);
8058 if (imm_expr
.X_op
== O_constant
8059 && (imm_expr
.X_add_number
< 0
8060 || imm_expr
.X_add_number
>= 0x10000))
8061 as_bad ("lui expression not in range 0..65535");
8062 imm_reloc
= BFD_RELOC_LO16
;
8067 if (imm_expr
.X_op
== O_constant
)
8068 imm_expr
.X_add_number
=
8069 (imm_expr
.X_add_number
>> 16) & 0xffff;
8072 imm_reloc
= BFD_RELOC_HI16_S
;
8073 imm_unmatched_hi
= true;
8076 imm_reloc
= BFD_RELOC_HI16
;
8082 case 'a': /* 26 bit address */
8083 my_getExpression (&offset_expr
, s
);
8085 offset_reloc
= BFD_RELOC_MIPS_JMP
;
8088 case 'N': /* 3 bit branch condition code */
8089 case 'M': /* 3 bit compare condition code */
8090 if (strncmp (s
, "$fcc", 4) != 0)
8100 while (isdigit (*s
));
8102 as_bad ("invalid condition code register $fcc%d", regno
);
8104 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8106 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8109 /* start-sanitize-vr5400 */
8110 case 'e': /* must be at least one digit */
8111 my_getExpression (&imm_expr
, s
);
8112 check_absolute_expr (ip
, &imm_expr
);
8113 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
8115 as_bad ("bad byte vector index (%ld)",
8116 (long) imm_expr
.X_add_number
);
8117 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8119 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8120 imm_expr
.X_op
= O_absent
;
8125 my_getExpression (&imm_expr
, s
);
8126 check_absolute_expr (ip
, &imm_expr
);
8127 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
8129 as_bad ("bad byte vector index (%ld)",
8130 (long) imm_expr
.X_add_number
);
8131 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8133 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8134 imm_expr
.X_op
= O_absent
;
8138 /* end-sanitize-vr5400 */
8140 as_bad ("bad char = '%c'\n", *args
);
8145 /* Args don't match. */
8146 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8147 !strcmp (insn
->name
, insn
[1].name
))
8153 insn_error
= "illegal operands";
8158 /* This routine assembles an instruction into its binary format when
8159 assembling for the mips16. As a side effect, it sets one of the
8160 global variables imm_reloc or offset_reloc to the type of
8161 relocation to do if one of the operands is an address expression.
8162 It also sets mips16_small and mips16_ext if the user explicitly
8163 requested a small or extended instruction. */
8168 struct mips_cl_insn
*ip
;
8172 struct mips_opcode
*insn
;
8175 unsigned int lastregno
= 0;
8180 mips16_small
= false;
8183 for (s
= str
; islower (*s
); ++s
)
8195 if (s
[1] == 't' && s
[2] == ' ')
8198 mips16_small
= true;
8202 else if (s
[1] == 'e' && s
[2] == ' ')
8211 insn_error
= "unknown opcode";
8215 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8216 mips16_small
= true;
8218 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8220 insn_error
= "unrecognized opcode";
8227 assert (strcmp (insn
->name
, str
) == 0);
8230 ip
->insn_opcode
= insn
->match
;
8231 ip
->use_extend
= false;
8232 imm_expr
.X_op
= O_absent
;
8233 imm_reloc
= BFD_RELOC_UNUSED
;
8234 offset_expr
.X_op
= O_absent
;
8235 offset_reloc
= BFD_RELOC_UNUSED
;
8236 for (args
= insn
->args
; 1; ++args
)
8243 /* In this switch statement we call break if we did not find
8244 a match, continue if we did find a match, or return if we
8253 /* Stuff the immediate value in now, if we can. */
8254 if (imm_expr
.X_op
== O_constant
8255 && imm_reloc
> BFD_RELOC_UNUSED
8256 && insn
->pinfo
!= INSN_MACRO
)
8258 mips16_immed ((char *) NULL
, 0,
8259 imm_reloc
- BFD_RELOC_UNUSED
,
8260 imm_expr
.X_add_number
, true, mips16_small
,
8261 mips16_ext
, &ip
->insn_opcode
,
8262 &ip
->use_extend
, &ip
->extend
);
8263 imm_expr
.X_op
= O_absent
;
8264 imm_reloc
= BFD_RELOC_UNUSED
;
8278 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8281 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8297 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8299 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8326 while (isdigit (*s
));
8329 as_bad ("invalid register number (%d)", regno
);
8335 if (s
[1] == 'f' && s
[2] == 'p')
8340 else if (s
[1] == 's' && s
[2] == 'p')
8345 else if (s
[1] == 'g' && s
[2] == 'p')
8350 else if (s
[1] == 'a' && s
[2] == 't')
8355 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8360 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8373 if (c
== 'v' || c
== 'w')
8375 regno
= mips16_to_32_reg_map
[lastregno
];
8389 regno
= mips32_to_16_reg_map
[regno
];
8394 regno
= ILLEGAL_REG
;
8399 regno
= ILLEGAL_REG
;
8404 regno
= ILLEGAL_REG
;
8409 if (regno
== AT
&& ! mips_opts
.noat
)
8410 as_warn ("used $at without \".set noat\"");
8417 if (regno
== ILLEGAL_REG
)
8424 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8428 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8431 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8434 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8440 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8443 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8444 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8454 if (strncmp (s
, "$pc", 3) == 0)
8478 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8480 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8481 and generate the appropriate reloc. If the text
8482 inside %gprel is not a symbol name with an
8483 optional offset, then we generate a normal reloc
8484 and will probably fail later. */
8485 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8486 if (imm_expr
.X_op
== O_symbol
)
8489 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8491 ip
->use_extend
= true;
8498 /* Just pick up a normal expression. */
8499 my_getExpression (&imm_expr
, s
);
8502 if (imm_expr
.X_op
== O_register
)
8504 /* What we thought was an expression turned out to
8507 if (s
[0] == '(' && args
[1] == '(')
8509 /* It looks like the expression was omitted
8510 before a register indirection, which means
8511 that the expression is implicitly zero. We
8512 still set up imm_expr, so that we handle
8513 explicit extensions correctly. */
8514 imm_expr
.X_op
= O_constant
;
8515 imm_expr
.X_add_number
= 0;
8516 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8523 /* We need to relax this instruction. */
8524 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8533 /* We use offset_reloc rather than imm_reloc for the PC
8534 relative operands. This lets macros with both
8535 immediate and address operands work correctly. */
8536 my_getExpression (&offset_expr
, s
);
8538 if (offset_expr
.X_op
== O_register
)
8541 /* We need to relax this instruction. */
8542 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8546 case '6': /* break code */
8547 my_getExpression (&imm_expr
, s
);
8548 check_absolute_expr (ip
, &imm_expr
);
8549 if ((unsigned long) imm_expr
.X_add_number
> 63)
8551 as_warn ("Invalid value for `%s' (%lu)",
8553 (unsigned long) imm_expr
.X_add_number
);
8554 imm_expr
.X_add_number
&= 0x3f;
8556 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8557 imm_expr
.X_op
= O_absent
;
8561 case 'a': /* 26 bit address */
8562 my_getExpression (&offset_expr
, s
);
8564 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8565 ip
->insn_opcode
<<= 16;
8568 case 'l': /* register list for entry macro */
8569 case 'L': /* register list for exit macro */
8579 int freg
, reg1
, reg2
;
8581 while (*s
== ' ' || *s
== ',')
8585 as_bad ("can't parse register list");
8597 while (isdigit (*s
))
8619 as_bad ("invalid register list");
8624 while (isdigit (*s
))
8631 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8636 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8641 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8642 mask
|= (reg2
- 3) << 3;
8643 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8644 mask
|= (reg2
- 15) << 1;
8645 else if (reg1
== 31 && reg2
== 31)
8649 as_bad ("invalid register list");
8653 /* The mask is filled in in the opcode table for the
8654 benefit of the disassembler. We remove it before
8655 applying the actual mask. */
8656 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8657 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8661 case 'e': /* extend code */
8662 my_getExpression (&imm_expr
, s
);
8663 check_absolute_expr (ip
, &imm_expr
);
8664 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8666 as_warn ("Invalid value for `%s' (%lu)",
8668 (unsigned long) imm_expr
.X_add_number
);
8669 imm_expr
.X_add_number
&= 0x7ff;
8671 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8672 imm_expr
.X_op
= O_absent
;
8682 /* Args don't match. */
8683 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8684 strcmp (insn
->name
, insn
[1].name
) == 0)
8691 insn_error
= "illegal operands";
8697 /* This structure holds information we know about a mips16 immediate
8700 struct mips16_immed_operand
8702 /* The type code used in the argument string in the opcode table. */
8704 /* The number of bits in the short form of the opcode. */
8706 /* The number of bits in the extended form of the opcode. */
8708 /* The amount by which the short form is shifted when it is used;
8709 for example, the sw instruction has a shift count of 2. */
8711 /* The amount by which the short form is shifted when it is stored
8712 into the instruction code. */
8714 /* Non-zero if the short form is unsigned. */
8716 /* Non-zero if the extended form is unsigned. */
8718 /* Non-zero if the value is PC relative. */
8722 /* The mips16 immediate operand types. */
8724 static const struct mips16_immed_operand mips16_immed_operands
[] =
8726 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8727 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8728 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8729 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8730 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8731 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8732 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8733 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8734 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8735 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8736 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8737 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8738 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8739 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8740 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8741 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8742 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8743 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8744 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8745 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8746 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8749 #define MIPS16_NUM_IMMED \
8750 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8752 /* Handle a mips16 instruction with an immediate value. This or's the
8753 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8754 whether an extended value is needed; if one is needed, it sets
8755 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8756 If SMALL is true, an unextended opcode was explicitly requested.
8757 If EXT is true, an extended opcode was explicitly requested. If
8758 WARN is true, warn if EXT does not match reality. */
8761 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8770 unsigned long *insn
;
8771 boolean
*use_extend
;
8772 unsigned short *extend
;
8774 register const struct mips16_immed_operand
*op
;
8775 int mintiny
, maxtiny
;
8778 op
= mips16_immed_operands
;
8779 while (op
->type
!= type
)
8782 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8787 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8790 maxtiny
= 1 << op
->nbits
;
8795 maxtiny
= (1 << op
->nbits
) - 1;
8800 mintiny
= - (1 << (op
->nbits
- 1));
8801 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8804 /* Branch offsets have an implicit 0 in the lowest bit. */
8805 if (type
== 'p' || type
== 'q')
8808 if ((val
& ((1 << op
->shift
) - 1)) != 0
8809 || val
< (mintiny
<< op
->shift
)
8810 || val
> (maxtiny
<< op
->shift
))
8815 if (warn
&& ext
&& ! needext
)
8816 as_warn_where (file
, line
, "extended operand requested but not required");
8817 if (small
&& needext
)
8818 as_bad_where (file
, line
, "invalid unextended operand value");
8820 if (small
|| (! ext
&& ! needext
))
8824 *use_extend
= false;
8825 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8826 insnval
<<= op
->op_shift
;
8831 long minext
, maxext
;
8837 maxext
= (1 << op
->extbits
) - 1;
8841 minext
= - (1 << (op
->extbits
- 1));
8842 maxext
= (1 << (op
->extbits
- 1)) - 1;
8844 if (val
< minext
|| val
> maxext
)
8845 as_bad_where (file
, line
,
8846 "operand value out of range for instruction");
8849 if (op
->extbits
== 16)
8851 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8854 else if (op
->extbits
== 15)
8856 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8861 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8865 *extend
= (unsigned short) extval
;
8874 my_getSmallExpression (ep
, str
)
8885 ((str
[1] == 'h' && str
[2] == 'i')
8886 || (str
[1] == 'H' && str
[2] == 'I')
8887 || (str
[1] == 'l' && str
[2] == 'o'))
8899 * A small expression may be followed by a base register.
8900 * Scan to the end of this operand, and then back over a possible
8901 * base register. Then scan the small expression up to that
8902 * point. (Based on code in sparc.c...)
8904 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8906 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8908 if (isdigit (sp
[-2]))
8910 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8912 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8918 else if (sp
- 5 >= str
8921 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8922 || (sp
[-3] == 's' && sp
[-2] == 'p')
8923 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8924 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8930 /* no expression means zero offset */
8933 /* %xx(reg) is an error */
8934 ep
->X_op
= O_absent
;
8939 ep
->X_op
= O_constant
;
8942 ep
->X_add_symbol
= NULL
;
8943 ep
->X_op_symbol
= NULL
;
8944 ep
->X_add_number
= 0;
8949 my_getExpression (ep
, str
);
8956 my_getExpression (ep
, str
);
8957 return c
; /* => %hi or %lo encountered */
8961 my_getExpression (ep
, str
)
8967 save_in
= input_line_pointer
;
8968 input_line_pointer
= str
;
8970 expr_end
= input_line_pointer
;
8971 input_line_pointer
= save_in
;
8973 /* If we are in mips16 mode, and this is an expression based on `.',
8974 then we bump the value of the symbol by 1 since that is how other
8975 text symbols are handled. We don't bother to handle complex
8976 expressions, just `.' plus or minus a constant. */
8977 if (mips_opts
.mips16
8978 && ep
->X_op
== O_symbol
8979 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8980 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8981 && ep
->X_add_symbol
->sy_frag
== frag_now
8982 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8983 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8984 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8987 /* Turn a string in input_line_pointer into a floating point constant
8988 of type type, and store the appropriate bytes in *litP. The number
8989 of LITTLENUMS emitted is stored in *sizeP . An error message is
8990 returned, or NULL on OK. */
8993 md_atof (type
, litP
, sizeP
)
8999 LITTLENUM_TYPE words
[4];
9015 return "bad call to md_atof";
9018 t
= atof_ieee (input_line_pointer
, type
, words
);
9020 input_line_pointer
= t
;
9024 if (! target_big_endian
)
9026 for (i
= prec
- 1; i
>= 0; i
--)
9028 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9034 for (i
= 0; i
< prec
; i
++)
9036 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9045 md_number_to_chars (buf
, val
, n
)
9050 if (target_big_endian
)
9051 number_to_chars_bigendian (buf
, val
, n
);
9053 number_to_chars_littleendian (buf
, val
, n
);
9056 CONST
char *md_shortopts
= "O::g::G:";
9058 struct option md_longopts
[] = {
9059 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9060 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9061 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9062 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9063 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9064 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9065 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9066 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9067 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9068 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9069 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9070 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9071 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9072 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9073 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9074 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9075 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9076 {"break", no_argument
, NULL
, OPTION_BREAK
},
9077 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9078 #define OPTION_EB (OPTION_MD_BASE + 11)
9079 {"EB", no_argument
, NULL
, OPTION_EB
},
9080 #define OPTION_EL (OPTION_MD_BASE + 12)
9081 {"EL", no_argument
, NULL
, OPTION_EL
},
9082 #define OPTION_M4650 (OPTION_MD_BASE + 13)
9083 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9084 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
9085 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9086 #define OPTION_M4010 (OPTION_MD_BASE + 15)
9087 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9088 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
9089 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9090 #define OPTION_M4100 (OPTION_MD_BASE + 17)
9091 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9092 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
9093 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9094 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
9095 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9096 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
9097 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9098 /* start-sanitize-r5900 */
9099 #define OPTION_M5900 (OPTION_MD_BASE + 24)
9100 {"m5900", no_argument
, NULL
, OPTION_M5900
},
9101 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
9102 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
9103 /* end-sanitize-r5900 */
9104 #define OPTION_M3900 (OPTION_MD_BASE + 26)
9105 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9106 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
9107 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9109 /* start-sanitize-tx19 */
9110 {"m1900", no_argument
, NULL
, OPTION_M3900
},
9111 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
9112 /* end-sanitize-tx19 */
9114 /* start-sanitize-vr5400 */
9115 #define OPTION_M5400 (OPTION_MD_BASE + 28)
9116 {"m5400", no_argument
, NULL
, OPTION_M5400
},
9117 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
9118 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
9120 /* end-sanitize-vr5400 */
9121 /* start-sanitize-tx49 */
9122 #define OPTION_M4900 (OPTION_MD_BASE + 30)
9123 {"m4900", no_argument
, NULL
, OPTION_M4900
},
9124 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
9125 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
9127 /* end-sanitize-tx49 */
9128 /* start-sanitize-vr4320 */
9129 #define OPTION_M4320 (OPTION_MD_BASE + 32)
9130 {"m4320", no_argument
, NULL
, OPTION_M4320
},
9131 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
9132 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
9134 /* end-sanitize-vr4320 */
9135 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
9136 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
9137 #define OPTION_XGOT (OPTION_MD_BASE + 19)
9138 #define OPTION_32 (OPTION_MD_BASE + 20)
9139 #define OPTION_64 (OPTION_MD_BASE + 21)
9141 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9142 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9143 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9144 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9145 {"32", no_argument
, NULL
, OPTION_32
},
9146 {"64", no_argument
, NULL
, OPTION_64
},
9149 {NULL
, no_argument
, NULL
, 0}
9151 size_t md_longopts_size
= sizeof(md_longopts
);
9154 md_parse_option (c
, arg
)
9169 target_big_endian
= 1;
9173 target_big_endian
= 0;
9177 if (arg
&& arg
[1] == '0')
9187 mips_debug
= atoi (arg
);
9188 /* When the MIPS assembler sees -g or -g2, it does not do
9189 optimizations which limit full symbolic debugging. We take
9190 that to be equivalent to -O0. */
9191 if (mips_debug
== 2)
9215 /* Identify the processor type */
9217 if (strcmp (p
, "default") == 0
9218 || strcmp (p
, "DEFAULT") == 0)
9224 /* We need to cope with the various "vr" prefixes for the 4300
9226 if (*p
== 'v' || *p
== 'V')
9232 if (*p
== 'r' || *p
== 'R')
9239 if (strcmp (p
, "10000") == 0
9240 || strcmp (p
, "10k") == 0
9241 || strcmp (p
, "10K") == 0)
9243 /* start-sanitize-tx19 */
9244 else if (strcmp (p
, "1900") == 0)
9246 /* end-sanitize-tx19 */
9250 if (strcmp (p
, "2000") == 0
9251 || strcmp (p
, "2k") == 0
9252 || strcmp (p
, "2K") == 0)
9257 if (strcmp (p
, "3000") == 0
9258 || strcmp (p
, "3k") == 0
9259 || strcmp (p
, "3K") == 0)
9261 else if (strcmp (p
, "3900") == 0)
9266 if (strcmp (p
, "4000") == 0
9267 || strcmp (p
, "4k") == 0
9268 || strcmp (p
, "4K") == 0)
9270 else if (strcmp (p
, "4100") == 0)
9272 else if (strcmp (p
, "4300") == 0)
9274 /* start-sanitize-vr4320 */
9275 else if (strcmp (p
, "4320") == 0)
9277 /* end-sanitize-vr4320 */
9278 else if (strcmp (p
, "4400") == 0)
9280 else if (strcmp (p
, "4600") == 0)
9282 else if (strcmp (p
, "4650") == 0)
9284 /* start-sanitize-tx49 */
9285 else if (strcmp (p
, "4900") == 0)
9287 /* end-sanitize-tx49 */
9288 else if (strcmp (p
, "4010") == 0)
9293 if (strcmp (p
, "5000") == 0
9294 || strcmp (p
, "5k") == 0
9295 || strcmp (p
, "5K") == 0)
9297 /* start-sanitize-vr5400 */
9298 else if (strcmp (p
, "5400") == 0)
9300 /* end-sanitize-vr5400 */
9301 /* start-sanitize-r5900 */
9302 else if (strcmp (p
, "5900") == 0)
9304 /* end-sanitize-r5900 */
9308 if (strcmp (p
, "6000") == 0
9309 || strcmp (p
, "6k") == 0
9310 || strcmp (p
, "6K") == 0)
9315 if (strcmp (p
, "8000") == 0
9316 || strcmp (p
, "8k") == 0
9317 || strcmp (p
, "8K") == 0)
9322 if (strcmp (p
, "orion") == 0)
9328 && (mips_cpu
!= 4300
9330 /* start-sanitize-vr4320 */
9332 /* end-sanitize-vr4320 */
9333 /* start-sanitize-vr5400 */
9335 /* end-sanitize-vr5400 */
9336 && mips_cpu
!= 5000))
9338 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
9344 as_bad ("invalid architecture -mcpu=%s", arg
);
9355 case OPTION_NO_M4650
:
9363 case OPTION_NO_M4010
:
9371 case OPTION_NO_M4100
:
9375 /* start-sanitize-r5900 */
9380 case OPTION_NO_M5900
:
9383 /* end-sanitize-r5900 */
9385 /* start-sanitize-vr4320 */
9390 case OPTION_NO_M4320
:
9394 /* end-sanitize-vr4320 */
9395 /* start-sanitize-vr5400 */
9400 case OPTION_NO_M5400
:
9404 /* end-sanitize-vr5400 */
9409 case OPTION_NO_M3900
:
9413 /* start-sanitize-tx49 */
9418 case OPTION_NO_M4900
:
9422 /* end-sanitize-tx49 */
9424 mips_opts
.mips16
= 1;
9425 mips_no_prev_insn (false);
9428 case OPTION_NO_MIPS16
:
9429 mips_opts
.mips16
= 0;
9430 mips_no_prev_insn (false);
9433 case OPTION_MEMBEDDED_PIC
:
9434 mips_pic
= EMBEDDED_PIC
;
9435 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9437 as_bad ("-G may not be used with embedded PIC code");
9440 g_switch_value
= 0x7fffffff;
9443 /* When generating ELF code, we permit -KPIC and -call_shared to
9444 select SVR4_PIC, and -non_shared to select no PIC. This is
9445 intended to be compatible with Irix 5. */
9446 case OPTION_CALL_SHARED
:
9447 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9449 as_bad ("-call_shared is supported only for ELF format");
9452 mips_pic
= SVR4_PIC
;
9453 if (g_switch_seen
&& g_switch_value
!= 0)
9455 as_bad ("-G may not be used with SVR4 PIC code");
9461 case OPTION_NON_SHARED
:
9462 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9464 as_bad ("-non_shared is supported only for ELF format");
9470 /* The -xgot option tells the assembler to use 32 offsets when
9471 accessing the got in SVR4_PIC mode. It is for Irix
9478 if (! USE_GLOBAL_POINTER_OPT
)
9480 as_bad ("-G is not supported for this configuration");
9483 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9485 as_bad ("-G may not be used with SVR4 or embedded PIC code");
9489 g_switch_value
= atoi (arg
);
9493 /* The -32 and -64 options tell the assembler to output the 32
9494 bit or the 64 bit MIPS ELF format. */
9501 const char **list
, **l
;
9503 list
= bfd_target_list ();
9504 for (l
= list
; *l
!= NULL
; l
++)
9505 if (strcmp (*l
, "elf64-bigmips") == 0
9506 || strcmp (*l
, "elf64-littlemips") == 0)
9509 as_fatal ("No compiled in support for 64 bit object file format");
9523 md_show_usage (stream
)
9528 -membedded-pic generate embedded position independent code\n\
9529 -EB generate big endian output\n\
9530 -EL generate little endian output\n\
9531 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9532 -G NUM allow referencing objects up to NUM bytes\n\
9533 implicitly with the gp register [default 8]\n");
9535 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
9536 -mips2, -mcpu=r6000 generate code for r6000\n\
9537 -mips3, -mcpu=r4000 generate code for r4000\n\
9538 -mips4, -mcpu=r8000 generate code for r8000\n\
9539 -mcpu=vr4300 generate code for vr4300\n\
9540 -mcpu=vr4100 generate code for vr4100\n\
9541 -m4650 permit R4650 instructions\n\
9542 -no-m4650 do not permit R4650 instructions\n\
9543 -m4010 permit R4010 instructions\n\
9544 -no-m4010 do not permit R4010 instructions\n\
9545 -m4100 permit VR4100 instructions\n\
9546 -no-m4100 do not permit VR4100 instructions\n");
9548 -mips16 generate mips16 instructions\n\
9549 -no-mips16 do not generate mips16 instructions\n");
9551 -O0 remove unneeded NOPs, do not swap branches\n\
9552 -O remove unneeded NOPs and swap branches\n\
9553 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9554 --break, --no-trap break exception on div by 0 and mult overflow\n");
9557 -KPIC, -call_shared generate SVR4 position independent code\n\
9558 -non_shared do not generate position independent code\n\
9559 -xgot assume a 32 bit GOT\n\
9560 -32 create 32 bit object file (default)\n\
9561 -64 create 64 bit object file\n");
9566 mips_init_after_args ()
9568 /* initialize opcodes */
9569 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9570 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9574 md_pcrel_from (fixP
)
9577 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9578 && fixP
->fx_addsy
!= (symbolS
*) NULL
9579 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9581 /* This makes a branch to an undefined symbol be a branch to the
9582 current location. */
9586 /* return the address of the delay slot */
9587 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9590 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9591 reloc for a cons. We could use the definition there, except that
9592 we want to handle 64 bit relocs specially. */
9595 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9598 unsigned int nbytes
;
9602 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9604 if (nbytes
== 8 && ! mips_64
)
9606 if (target_big_endian
)
9612 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9613 as_bad ("Unsupported reloc size %d", nbytes
);
9615 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9618 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9621 /* This is called before the symbol table is processed. In order to
9622 work with gcc when using mips-tfile, we must keep all local labels.
9623 However, in other cases, we want to discard them. If we were
9624 called with -g, but we didn't see any debugging information, it may
9625 mean that gcc is smuggling debugging information through to
9626 mips-tfile, in which case we must generate all local labels. */
9629 mips_frob_file_before_adjust ()
9631 #ifndef NO_ECOFF_DEBUGGING
9634 && ! ecoff_debugging_seen
)
9635 flag_keep_locals
= 1;
9639 /* Sort any unmatched HI16_S relocs so that they immediately precede
9640 the corresponding LO reloc. This is called before md_apply_fix and
9641 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9642 explicit use of the %hi modifier. */
9647 struct mips_hi_fixup
*l
;
9649 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9651 segment_info_type
*seginfo
;
9654 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9656 /* Check quickly whether the next fixup happens to be a matching
9658 if (l
->fixp
->fx_next
!= NULL
9659 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9660 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9661 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9664 /* Look through the fixups for this segment for a matching %lo.
9665 When we find one, move the %hi just in front of it. We do
9666 this in two passes. In the first pass, we try to find a
9667 unique %lo. In the second pass, we permit multiple %hi
9668 relocs for a single %lo (this is a GNU extension). */
9669 seginfo
= seg_info (l
->seg
);
9670 for (pass
= 0; pass
< 2; pass
++)
9675 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9677 /* Check whether this is a %lo fixup which matches l->fixp. */
9678 if (f
->fx_r_type
== BFD_RELOC_LO16
9679 && f
->fx_addsy
== l
->fixp
->fx_addsy
9680 && f
->fx_offset
== l
->fixp
->fx_offset
9683 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9684 || prev
->fx_addsy
!= f
->fx_addsy
9685 || prev
->fx_offset
!= f
->fx_offset
))
9689 /* Move l->fixp before f. */
9690 for (pf
= &seginfo
->fix_root
;
9692 pf
= &(*pf
)->fx_next
)
9693 assert (*pf
!= NULL
);
9695 *pf
= l
->fixp
->fx_next
;
9697 l
->fixp
->fx_next
= f
;
9699 seginfo
->fix_root
= l
->fixp
;
9701 prev
->fx_next
= l
->fixp
;
9713 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9714 "Unmatched %%hi reloc");
9719 /* When generating embedded PIC code we need to use a special
9720 relocation to represent the difference of two symbols in the .text
9721 section (switch tables use a difference of this sort). See
9722 include/coff/mips.h for details. This macro checks whether this
9723 fixup requires the special reloc. */
9724 #define SWITCH_TABLE(fixp) \
9725 ((fixp)->fx_r_type == BFD_RELOC_32 \
9726 && (fixp)->fx_addsy != NULL \
9727 && (fixp)->fx_subsy != NULL \
9728 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9729 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9731 /* When generating embedded PIC code we must keep all PC relative
9732 relocations, in case the linker has to relax a call. We also need
9733 to keep relocations for switch table entries. */
9737 mips_force_relocation (fixp
)
9740 return (mips_pic
== EMBEDDED_PIC
9742 || SWITCH_TABLE (fixp
)
9743 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9744 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9747 /* Apply a fixup to the object file. */
9750 md_apply_fix (fixP
, valueP
)
9757 assert (fixP
->fx_size
== 4
9758 || fixP
->fx_r_type
== BFD_RELOC_16
9759 || fixP
->fx_r_type
== BFD_RELOC_64
);
9763 /* If we aren't adjusting this fixup to be against the section
9764 symbol, we need to adjust the value. */
9766 if (fixP
->fx_addsy
!= NULL
9767 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
9768 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
9770 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9771 if (value
!= 0 && ! fixP
->fx_pcrel
)
9773 /* In this case, the bfd_install_relocation routine will
9774 incorrectly add the symbol value back in. We just want
9775 the addend to appear in the object file. */
9776 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9781 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9783 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9786 switch (fixP
->fx_r_type
)
9788 case BFD_RELOC_MIPS_JMP
:
9789 case BFD_RELOC_HI16
:
9790 case BFD_RELOC_HI16_S
:
9791 case BFD_RELOC_MIPS_GPREL
:
9792 case BFD_RELOC_MIPS_LITERAL
:
9793 case BFD_RELOC_MIPS_CALL16
:
9794 case BFD_RELOC_MIPS_GOT16
:
9795 case BFD_RELOC_MIPS_GPREL32
:
9796 case BFD_RELOC_MIPS_GOT_HI16
:
9797 case BFD_RELOC_MIPS_GOT_LO16
:
9798 case BFD_RELOC_MIPS_CALL_HI16
:
9799 case BFD_RELOC_MIPS_CALL_LO16
:
9800 case BFD_RELOC_MIPS16_GPREL
:
9801 /* start-sanitize-r5900 */
9802 case BFD_RELOC_MIPS15_S3
:
9803 /* end-sanitize-r5900 */
9805 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9806 "Invalid PC relative reloc");
9807 /* Nothing needed to do. The value comes from the reloc entry */
9810 case BFD_RELOC_MIPS16_JMP
:
9811 /* We currently always generate a reloc against a symbol, which
9812 means that we don't want an addend even if the symbol is
9814 fixP
->fx_addnumber
= 0;
9817 case BFD_RELOC_PCREL_HI16_S
:
9818 /* The addend for this is tricky if it is internal, so we just
9819 do everything here rather than in bfd_install_relocation. */
9820 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9822 /* For an external symbol adjust by the address to make it
9823 pcrel_offset. We use the address of the RELLO reloc
9824 which follows this one. */
9825 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9826 + fixP
->fx_next
->fx_where
);
9831 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9832 if (target_big_endian
)
9834 md_number_to_chars (buf
, value
, 2);
9837 case BFD_RELOC_PCREL_LO16
:
9838 /* The addend for this is tricky if it is internal, so we just
9839 do everything here rather than in bfd_install_relocation. */
9840 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9841 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9842 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9843 if (target_big_endian
)
9845 md_number_to_chars (buf
, value
, 2);
9849 /* This is handled like BFD_RELOC_32, but we output a sign
9850 extended value if we are only 32 bits. */
9852 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9854 if (8 <= sizeof (valueT
))
9855 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9862 w1
= w2
= fixP
->fx_where
;
9863 if (target_big_endian
)
9867 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9868 if ((value
& 0x80000000) != 0)
9872 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9878 /* If we are deleting this reloc entry, we must fill in the
9879 value now. This can happen if we have a .word which is not
9880 resolved when it appears but is later defined. We also need
9881 to fill in the value if this is an embedded PIC switch table
9884 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9885 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9890 /* If we are deleting this reloc entry, we must fill in the
9892 assert (fixP
->fx_size
== 2);
9894 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9898 case BFD_RELOC_LO16
:
9899 /* When handling an embedded PIC switch statement, we can wind
9900 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9903 if (value
< -0x8000 || value
> 0x7fff)
9904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9905 "relocation overflow");
9906 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9907 if (target_big_endian
)
9909 md_number_to_chars (buf
, value
, 2);
9913 case BFD_RELOC_16_PCREL_S2
:
9915 * We need to save the bits in the instruction since fixup_segment()
9916 * might be deleting the relocation entry (i.e., a branch within
9917 * the current segment).
9919 if ((value
& 0x3) != 0)
9920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9921 "Branch to odd address (%lx)", value
);
9924 /* update old instruction data */
9925 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9926 if (target_big_endian
)
9927 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9929 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9931 if (value
>= -0x8000 && value
< 0x8000)
9932 insn
|= value
& 0xffff;
9935 /* The branch offset is too large. If this is an
9936 unconditional branch, and we are not generating PIC code,
9937 we can convert it to an absolute jump instruction. */
9938 if (mips_pic
== NO_PIC
9940 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9941 && (fixP
->fx_frag
->fr_address
9942 < text_section
->vma
+ text_section
->_raw_size
)
9943 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9944 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9945 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9947 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9948 insn
= 0x0c000000; /* jal */
9950 insn
= 0x08000000; /* j */
9951 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9953 fixP
->fx_addsy
= section_symbol (text_section
);
9954 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9958 /* FIXME. It would be possible in principle to handle
9959 conditional branches which overflow. They could be
9960 transformed into a branch around a jump. This would
9961 require setting up variant frags for each different
9962 branch type. The native MIPS assembler attempts to
9963 handle these cases, but it appears to do it
9965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9966 "Branch out of range");
9970 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9985 const struct mips_opcode
*p
;
9986 int treg
, sreg
, dreg
, shamt
;
9991 for (i
= 0; i
< NUMOPCODES
; ++i
)
9993 p
= &mips_opcodes
[i
];
9994 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9996 printf ("%08lx %s\t", oc
, p
->name
);
9997 treg
= (oc
>> 16) & 0x1f;
9998 sreg
= (oc
>> 21) & 0x1f;
9999 dreg
= (oc
>> 11) & 0x1f;
10000 shamt
= (oc
>> 6) & 0x1f;
10002 for (args
= p
->args
;; ++args
)
10013 printf ("%c", *args
);
10017 assert (treg
== sreg
);
10018 printf ("$%d,$%d", treg
, sreg
);
10023 printf ("$%d", dreg
);
10028 printf ("$%d", treg
);
10032 printf ("0x%x", treg
);
10037 printf ("$%d", sreg
);
10041 printf ("0x%08lx", oc
& 0x1ffffff);
10048 printf ("%d", imm
);
10053 printf ("$%d", shamt
);
10064 printf ("%08lx UNDEFINED\n", oc
);
10075 name
= input_line_pointer
;
10076 c
= get_symbol_end ();
10077 p
= (symbolS
*) symbol_find_or_make (name
);
10078 *input_line_pointer
= c
;
10082 /* Align the current frag to a given power of two. The MIPS assembler
10083 also automatically adjusts any preceding label. */
10086 mips_align (to
, fill
, label
)
10091 mips_emit_delays (false);
10092 frag_align (to
, fill
, 0);
10093 record_alignment (now_seg
, to
);
10096 assert (S_GET_SEGMENT (label
) == now_seg
);
10097 label
->sy_frag
= frag_now
;
10098 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10102 /* Align to a given power of two. .align 0 turns off the automatic
10103 alignment used by the data creating pseudo-ops. */
10110 register long temp_fill
;
10111 long max_alignment
= 15;
10115 o Note that the assembler pulls down any immediately preceeding label
10116 to the aligned address.
10117 o It's not documented but auto alignment is reinstated by
10118 a .align pseudo instruction.
10119 o Note also that after auto alignment is turned off the mips assembler
10120 issues an error on attempt to assemble an improperly aligned data item.
10125 temp
= get_absolute_expression ();
10126 if (temp
> max_alignment
)
10127 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
10130 as_warn ("Alignment negative: 0 assumed.");
10133 if (*input_line_pointer
== ',')
10135 input_line_pointer
++;
10136 temp_fill
= get_absolute_expression ();
10143 mips_align (temp
, (int) temp_fill
,
10144 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10151 demand_empty_rest_of_line ();
10155 mips_flush_pending_output ()
10157 mips_emit_delays (false);
10158 mips_clear_insn_labels ();
10167 /* When generating embedded PIC code, we only use the .text, .lit8,
10168 .sdata and .sbss sections. We change the .data and .rdata
10169 pseudo-ops to use .sdata. */
10170 if (mips_pic
== EMBEDDED_PIC
10171 && (sec
== 'd' || sec
== 'r'))
10175 /* The ELF backend needs to know that we are changing sections, so
10176 that .previous works correctly. We could do something like check
10177 for a obj_section_change_hook macro, but that might be confusing
10178 as it would not be appropriate to use it in the section changing
10179 functions in read.c, since obj-elf.c intercepts those. FIXME:
10180 This should be cleaner, somehow. */
10181 obj_elf_section_change_hook ();
10184 mips_emit_delays (false);
10194 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10195 demand_empty_rest_of_line ();
10199 if (USE_GLOBAL_POINTER_OPT
)
10201 seg
= subseg_new (RDATA_SECTION_NAME
,
10202 (subsegT
) get_absolute_expression ());
10203 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10205 bfd_set_section_flags (stdoutput
, seg
,
10211 if (strcmp (TARGET_OS
, "elf") != 0)
10212 bfd_set_section_alignment (stdoutput
, seg
, 4);
10214 demand_empty_rest_of_line ();
10218 as_bad ("No read only data section in this object file format");
10219 demand_empty_rest_of_line ();
10225 if (USE_GLOBAL_POINTER_OPT
)
10227 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10228 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10230 bfd_set_section_flags (stdoutput
, seg
,
10231 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10233 if (strcmp (TARGET_OS
, "elf") != 0)
10234 bfd_set_section_alignment (stdoutput
, seg
, 4);
10236 demand_empty_rest_of_line ();
10241 as_bad ("Global pointers not supported; recompile -G 0");
10242 demand_empty_rest_of_line ();
10251 mips_enable_auto_align ()
10262 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10263 mips_emit_delays (false);
10264 if (log_size
> 0 && auto_align
)
10265 mips_align (log_size
, 0, label
);
10266 mips_clear_insn_labels ();
10267 cons (1 << log_size
);
10271 s_float_cons (type
)
10276 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10278 mips_emit_delays (false);
10282 mips_align (3, 0, label
);
10284 mips_align (2, 0, label
);
10286 mips_clear_insn_labels ();
10291 /* Handle .globl. We need to override it because on Irix 5 you are
10294 where foo is an undefined symbol, to mean that foo should be
10295 considered to be the address of a function. */
10306 name
= input_line_pointer
;
10307 c
= get_symbol_end ();
10308 symbolP
= symbol_find_or_make (name
);
10309 *input_line_pointer
= c
;
10310 SKIP_WHITESPACE ();
10312 /* On Irix 5, every global symbol that is not explicitly labelled as
10313 being a function is apparently labelled as being an object. */
10316 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10321 secname
= input_line_pointer
;
10322 c
= get_symbol_end ();
10323 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10325 as_bad ("%s: no such section", secname
);
10326 *input_line_pointer
= c
;
10328 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10329 flag
= BSF_FUNCTION
;
10332 symbolP
->bsym
->flags
|= flag
;
10334 S_SET_EXTERNAL (symbolP
);
10335 demand_empty_rest_of_line ();
10345 opt
= input_line_pointer
;
10346 c
= get_symbol_end ();
10350 /* FIXME: What does this mean? */
10352 else if (strncmp (opt
, "pic", 3) == 0)
10356 i
= atoi (opt
+ 3);
10360 mips_pic
= SVR4_PIC
;
10362 as_bad (".option pic%d not supported", i
);
10364 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10366 if (g_switch_seen
&& g_switch_value
!= 0)
10367 as_warn ("-G may not be used with SVR4 PIC code");
10368 g_switch_value
= 0;
10369 bfd_set_gp_size (stdoutput
, 0);
10373 as_warn ("Unrecognized option \"%s\"", opt
);
10375 *input_line_pointer
= c
;
10376 demand_empty_rest_of_line ();
10379 /* This structure is used to hold a stack of .set values. */
10381 struct mips_option_stack
10383 struct mips_option_stack
*next
;
10384 struct mips_set_options options
;
10387 static struct mips_option_stack
*mips_opts_stack
;
10389 /* Handle the .set pseudo-op. */
10395 char *name
= input_line_pointer
, ch
;
10397 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10398 input_line_pointer
++;
10399 ch
= *input_line_pointer
;
10400 *input_line_pointer
= '\0';
10402 if (strcmp (name
, "reorder") == 0)
10404 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10406 /* If we still have pending nops, we can discard them. The
10407 usual nop handling will insert any that are still
10409 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10410 * (mips_opts
.mips16
? 2 : 4));
10411 prev_nop_frag
= NULL
;
10413 mips_opts
.noreorder
= 0;
10415 else if (strcmp (name
, "noreorder") == 0)
10417 mips_emit_delays (true);
10418 mips_opts
.noreorder
= 1;
10419 mips_any_noreorder
= 1;
10421 else if (strcmp (name
, "at") == 0)
10423 mips_opts
.noat
= 0;
10425 else if (strcmp (name
, "noat") == 0)
10427 mips_opts
.noat
= 1;
10429 else if (strcmp (name
, "macro") == 0)
10431 mips_opts
.warn_about_macros
= 0;
10433 else if (strcmp (name
, "nomacro") == 0)
10435 if (mips_opts
.noreorder
== 0)
10436 as_bad ("`noreorder' must be set before `nomacro'");
10437 mips_opts
.warn_about_macros
= 1;
10439 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10441 mips_opts
.nomove
= 0;
10443 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10445 mips_opts
.nomove
= 1;
10447 else if (strcmp (name
, "bopt") == 0)
10449 mips_opts
.nobopt
= 0;
10451 else if (strcmp (name
, "nobopt") == 0)
10453 mips_opts
.nobopt
= 1;
10455 else if (strcmp (name
, "mips16") == 0
10456 || strcmp (name
, "MIPS-16") == 0)
10457 mips_opts
.mips16
= 1;
10458 else if (strcmp (name
, "nomips16") == 0
10459 || strcmp (name
, "noMIPS-16") == 0)
10460 mips_opts
.mips16
= 0;
10461 else if (strncmp (name
, "mips", 4) == 0)
10465 /* Permit the user to change the ISA on the fly. Needless to
10466 say, misuse can cause serious problems. */
10467 isa
= atoi (name
+ 4);
10469 mips_opts
.isa
= file_mips_isa
;
10470 else if (isa
< 1 || isa
> 4)
10471 as_bad ("unknown ISA level");
10473 mips_opts
.isa
= isa
;
10475 else if (strcmp (name
, "autoextend") == 0)
10476 mips_opts
.noautoextend
= 0;
10477 else if (strcmp (name
, "noautoextend") == 0)
10478 mips_opts
.noautoextend
= 1;
10479 else if (strcmp (name
, "push") == 0)
10481 struct mips_option_stack
*s
;
10483 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10484 s
->next
= mips_opts_stack
;
10485 s
->options
= mips_opts
;
10486 mips_opts_stack
= s
;
10488 else if (strcmp (name
, "pop") == 0)
10490 struct mips_option_stack
*s
;
10492 s
= mips_opts_stack
;
10494 as_bad (".set pop with no .set push");
10497 /* If we're changing the reorder mode we need to handle
10498 delay slots correctly. */
10499 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10500 mips_emit_delays (true);
10501 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10503 if (prev_nop_frag
!= NULL
)
10505 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10506 * (mips_opts
.mips16
? 2 : 4));
10507 prev_nop_frag
= NULL
;
10511 mips_opts
= s
->options
;
10512 mips_opts_stack
= s
->next
;
10518 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
10520 *input_line_pointer
= ch
;
10521 demand_empty_rest_of_line ();
10524 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10525 .option pic2. It means to generate SVR4 PIC calls. */
10528 s_abicalls (ignore
)
10531 mips_pic
= SVR4_PIC
;
10532 if (USE_GLOBAL_POINTER_OPT
)
10534 if (g_switch_seen
&& g_switch_value
!= 0)
10535 as_warn ("-G may not be used with SVR4 PIC code");
10536 g_switch_value
= 0;
10538 bfd_set_gp_size (stdoutput
, 0);
10539 demand_empty_rest_of_line ();
10542 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10543 PIC code. It sets the $gp register for the function based on the
10544 function address, which is in the register named in the argument.
10545 This uses a relocation against _gp_disp, which is handled specially
10546 by the linker. The result is:
10547 lui $gp,%hi(_gp_disp)
10548 addiu $gp,$gp,%lo(_gp_disp)
10549 addu $gp,$gp,.cpload argument
10550 The .cpload argument is normally $25 == $t9. */
10559 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10560 if (mips_pic
!= SVR4_PIC
)
10566 /* .cpload should be a in .set noreorder section. */
10567 if (mips_opts
.noreorder
== 0)
10568 as_warn (".cpload not in noreorder section");
10570 ex
.X_op
= O_symbol
;
10571 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10572 ex
.X_op_symbol
= NULL
;
10573 ex
.X_add_number
= 0;
10575 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10576 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10578 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10579 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10580 (int) BFD_RELOC_LO16
);
10582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10583 GP
, GP
, tc_get_register (0));
10585 demand_empty_rest_of_line ();
10588 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10589 offset from $sp. The offset is remembered, and after making a PIC
10590 call $gp is restored from that location. */
10593 s_cprestore (ignore
)
10599 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10600 if (mips_pic
!= SVR4_PIC
)
10606 mips_cprestore_offset
= get_absolute_expression ();
10608 ex
.X_op
= O_constant
;
10609 ex
.X_add_symbol
= NULL
;
10610 ex
.X_op_symbol
= NULL
;
10611 ex
.X_add_number
= mips_cprestore_offset
;
10613 macro_build ((char *) NULL
, &icnt
, &ex
,
10614 ((bfd_arch_bits_per_address (stdoutput
) == 32
10615 || mips_opts
.isa
< 3)
10617 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10619 demand_empty_rest_of_line ();
10622 /* Handle the .gpword pseudo-op. This is used when generating PIC
10623 code. It generates a 32 bit GP relative reloc. */
10633 /* When not generating PIC code, this is treated as .word. */
10634 if (mips_pic
!= SVR4_PIC
)
10640 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10641 mips_emit_delays (true);
10643 mips_align (2, 0, label
);
10644 mips_clear_insn_labels ();
10648 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10650 as_bad ("Unsupported use of .gpword");
10651 ignore_rest_of_line ();
10655 md_number_to_chars (p
, (valueT
) 0, 4);
10656 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10657 BFD_RELOC_MIPS_GPREL32
);
10659 demand_empty_rest_of_line ();
10662 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10663 tables in SVR4 PIC code. */
10672 /* This is ignored when not generating SVR4 PIC code. */
10673 if (mips_pic
!= SVR4_PIC
)
10679 /* Add $gp to the register named as an argument. */
10680 reg
= tc_get_register (0);
10681 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10682 ((bfd_arch_bits_per_address (stdoutput
) == 32
10683 || mips_opts
.isa
< 3)
10684 ? "addu" : "daddu"),
10685 "d,v,t", reg
, reg
, GP
);
10687 demand_empty_rest_of_line ();
10690 /* Handle the .insn pseudo-op. This marks instruction labels in
10691 mips16 mode. This permits the linker to handle them specially,
10692 such as generating jalx instructions when needed. We also make
10693 them odd for the duration of the assembly, in order to generate the
10694 right sort of code. We will make them even in the adjust_symtab
10695 routine, while leaving them marked. This is convenient for the
10696 debugger and the disassembler. The linker knows to make them odd
10703 if (mips_opts
.mips16
)
10704 mips16_mark_labels ();
10706 demand_empty_rest_of_line ();
10709 /* Handle a .stabn directive. We need these in order to mark a label
10710 as being a mips16 text label correctly. Sometimes the compiler
10711 will emit a label, followed by a .stabn, and then switch sections.
10712 If the label and .stabn are in mips16 mode, then the label is
10713 really a mips16 text label. */
10719 if (type
== 'n' && mips_opts
.mips16
)
10720 mips16_mark_labels ();
10725 /* Parse a register string into a number. Called from the ECOFF code
10726 to parse .frame. The argument is non-zero if this is the frame
10727 register, so that we can record it in mips_frame_reg. */
10730 tc_get_register (frame
)
10735 SKIP_WHITESPACE ();
10736 if (*input_line_pointer
++ != '$')
10738 as_warn ("expected `$'");
10741 else if (isdigit ((unsigned char) *input_line_pointer
))
10743 reg
= get_absolute_expression ();
10744 if (reg
< 0 || reg
>= 32)
10746 as_warn ("Bad register number");
10752 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10754 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10756 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10758 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10762 as_warn ("Unrecognized register name");
10765 input_line_pointer
+= 2;
10768 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10773 md_section_align (seg
, addr
)
10777 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10780 /* We don't need to align ELF sections to the full alignment.
10781 However, Irix 5 may prefer that we align them at least to a 16
10782 byte boundary. We don't bother to align the sections if we are
10783 targeted for an embedded system. */
10784 if (strcmp (TARGET_OS
, "elf") == 0)
10790 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10793 /* Utility routine, called from above as well. If called while the
10794 input file is still being read, it's only an approximation. (For
10795 example, a symbol may later become defined which appeared to be
10796 undefined earlier.) */
10799 nopic_need_relax (sym
, before_relaxing
)
10801 int before_relaxing
;
10806 if (USE_GLOBAL_POINTER_OPT
)
10808 const char *symname
;
10811 /* Find out whether this symbol can be referenced off the GP
10812 register. It can be if it is smaller than the -G size or if
10813 it is in the .sdata or .sbss section. Certain symbols can
10814 not be referenced off the GP, although it appears as though
10816 symname
= S_GET_NAME (sym
);
10817 if (symname
!= (const char *) NULL
10818 && (strcmp (symname
, "eprol") == 0
10819 || strcmp (symname
, "etext") == 0
10820 || strcmp (symname
, "_gp") == 0
10821 || strcmp (symname
, "edata") == 0
10822 || strcmp (symname
, "_fbss") == 0
10823 || strcmp (symname
, "_fdata") == 0
10824 || strcmp (symname
, "_ftext") == 0
10825 || strcmp (symname
, "end") == 0
10826 || strcmp (symname
, "_gp_disp") == 0))
10828 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10830 #ifndef NO_ECOFF_DEBUGGING
10831 || (sym
->ecoff_extern_size
!= 0
10832 && sym
->ecoff_extern_size
<= g_switch_value
)
10834 /* We must defer this decision until after the whole
10835 file has been read, since there might be a .extern
10836 after the first use of this symbol. */
10837 || (before_relaxing
10838 #ifndef NO_ECOFF_DEBUGGING
10839 && sym
->ecoff_extern_size
== 0
10841 && S_GET_VALUE (sym
) == 0)
10842 || (S_GET_VALUE (sym
) != 0
10843 && S_GET_VALUE (sym
) <= g_switch_value
)))
10847 const char *segname
;
10849 segname
= segment_name (S_GET_SEGMENT (sym
));
10850 assert (strcmp (segname
, ".lit8") != 0
10851 && strcmp (segname
, ".lit4") != 0);
10852 change
= (strcmp (segname
, ".sdata") != 0
10853 && strcmp (segname
, ".sbss") != 0);
10858 /* We are not optimizing for the GP register. */
10862 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10863 extended opcode. SEC is the section the frag is in. */
10866 mips16_extended_frag (fragp
, sec
, stretch
)
10872 register const struct mips16_immed_operand
*op
;
10874 int mintiny
, maxtiny
;
10877 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10879 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10882 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10883 op
= mips16_immed_operands
;
10884 while (op
->type
!= type
)
10887 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10892 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10895 maxtiny
= 1 << op
->nbits
;
10900 maxtiny
= (1 << op
->nbits
) - 1;
10905 mintiny
= - (1 << (op
->nbits
- 1));
10906 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10909 /* We can't call S_GET_VALUE here, because we don't want to lock in
10910 a particular frag address. */
10911 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10913 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10914 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10915 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10917 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10918 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10921 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10922 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10923 + fragp
->fr_symbol
->sy_value
.X_add_number
10924 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10925 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10934 /* We won't have the section when we are called from
10935 mips_relax_frag. However, we will always have been called
10936 from md_estimate_size_before_relax first. If this is a
10937 branch to a different section, we mark it as such. If SEC is
10938 NULL, and the frag is not marked, then it must be a branch to
10939 the same section. */
10942 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10949 fragp
->fr_subtype
=
10950 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10952 /* FIXME: We should support this, and let the linker
10953 catch branches and loads that are out of range. */
10954 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10955 "unsupported PC relative reference to different section");
10961 /* In this case, we know for sure that the symbol fragment is in
10962 the same section. If the fr_address of the symbol fragment
10963 is greater then the address of this fragment we want to add
10964 in STRETCH in order to get a better estimate of the address.
10965 This particularly matters because of the shift bits. */
10967 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10971 /* Adjust stretch for any alignment frag. Note that if have
10972 been expanding the earlier code, the symbol may be
10973 defined in what appears to be an earlier frag. FIXME:
10974 This doesn't handle the fr_subtype field, which specifies
10975 a maximum number of bytes to skip when doing an
10978 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10981 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10984 stretch
= - ((- stretch
)
10985 & ~ ((1 << (int) f
->fr_offset
) - 1));
10987 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10996 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10998 /* The base address rules are complicated. The base address of
10999 a branch is the following instruction. The base address of a
11000 PC relative load or add is the instruction itself, but if it
11001 is in a delay slot (in which case it can not be extended) use
11002 the address of the instruction whose delay slot it is in. */
11003 if (type
== 'p' || type
== 'q')
11007 /* If we are currently assuming that this frag should be
11008 extended, then, the current address is two bytes
11010 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11013 /* Ignore the low bit in the target, since it will be set
11014 for a text label. */
11015 if ((val
& 1) != 0)
11018 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11020 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11023 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11025 /* Branch offsets have an implicit 0 in the lowest bit. */
11026 if (type
== 'p' || type
== 'q')
11029 /* If any of the shifted bits are set, we must use an extended
11030 opcode. If the address depends on the size of this
11031 instruction, this can lead to a loop, so we arrange to always
11032 use an extended opcode. We only check this when we are in
11033 the main relaxation loop, when SEC is NULL. */
11034 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11036 fragp
->fr_subtype
=
11037 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11041 /* If we are about to mark a frag as extended because the value
11042 is precisely maxtiny + 1, then there is a chance of an
11043 infinite loop as in the following code:
11048 In this case when the la is extended, foo is 0x3fc bytes
11049 away, so the la can be shrunk, but then foo is 0x400 away, so
11050 the la must be extended. To avoid this loop, we mark the
11051 frag as extended if it was small, and is about to become
11052 extended with a value of maxtiny + 1. */
11053 if (val
== ((maxtiny
+ 1) << op
->shift
)
11054 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11057 fragp
->fr_subtype
=
11058 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11062 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11063 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
11065 if ((val
& ((1 << op
->shift
) - 1)) != 0
11066 || val
< (mintiny
<< op
->shift
)
11067 || val
> (maxtiny
<< op
->shift
))
11073 /* Estimate the size of a frag before relaxing. Unless this is the
11074 mips16, we are not really relaxing here, and the final size is
11075 encoded in the subtype information. For the mips16, we have to
11076 decide whether we are using an extended opcode or not. */
11080 md_estimate_size_before_relax (fragp
, segtype
)
11086 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11088 if (mips16_extended_frag (fragp
, segtype
, 0))
11090 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11095 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11100 if (mips_pic
== NO_PIC
)
11102 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11104 else if (mips_pic
== SVR4_PIC
)
11109 sym
= fragp
->fr_symbol
;
11111 /* Handle the case of a symbol equated to another symbol. */
11112 while (sym
->sy_value
.X_op
== O_symbol
11113 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11117 /* It's possible to get a loop here in a badly written
11119 n
= sym
->sy_value
.X_add_symbol
;
11125 symsec
= S_GET_SEGMENT (sym
);
11127 /* This must duplicate the test in adjust_reloc_syms. */
11128 change
= (symsec
!= &bfd_und_section
11129 && symsec
!= &bfd_abs_section
11130 && ! bfd_is_com_section (symsec
));
11137 /* Record the offset to the first reloc in the fr_opcode field.
11138 This lets md_convert_frag and tc_gen_reloc know that the code
11139 must be expanded. */
11140 fragp
->fr_opcode
= (fragp
->fr_literal
11142 - RELAX_OLD (fragp
->fr_subtype
)
11143 + RELAX_RELOC1 (fragp
->fr_subtype
));
11144 /* FIXME: This really needs as_warn_where. */
11145 if (RELAX_WARN (fragp
->fr_subtype
))
11146 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
11152 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11155 /* This is called to see whether a reloc against a defined symbol
11156 should be converted into a reloc against a section. Don't adjust
11157 MIPS16 jump relocations, so we don't have to worry about the format
11158 of the offset in the .o file. Don't adjust relocations against
11159 mips16 symbols, so that the linker can find them if it needs to set
11163 mips_fix_adjustable (fixp
)
11166 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11168 if (fixp
->fx_addsy
== NULL
)
11171 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11172 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11173 && fixp
->fx_subsy
== NULL
)
11179 /* Translate internal representation of relocation info to BFD target
11183 tc_gen_reloc (section
, fixp
)
11187 static arelent
*retval
[4];
11189 bfd_reloc_code_real_type code
;
11191 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11194 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11195 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11197 if (mips_pic
== EMBEDDED_PIC
11198 && SWITCH_TABLE (fixp
))
11200 /* For a switch table entry we use a special reloc. The addend
11201 is actually the difference between the reloc address and the
11203 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11204 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11205 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
11206 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11208 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11210 /* We use a special addend for an internal RELLO reloc. */
11211 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11212 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11214 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11216 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11218 assert (fixp
->fx_next
!= NULL
11219 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11220 /* We use a special addend for an internal RELHI reloc. The
11221 reloc is relative to the RELLO; adjust the addend
11223 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11224 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11225 + fixp
->fx_next
->fx_where
11226 - S_GET_VALUE (fixp
->fx_subsy
));
11228 reloc
->addend
= (fixp
->fx_addnumber
11229 + fixp
->fx_next
->fx_frag
->fr_address
11230 + fixp
->fx_next
->fx_where
);
11232 else if (fixp
->fx_pcrel
== 0)
11233 reloc
->addend
= fixp
->fx_addnumber
;
11236 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11237 /* A gruesome hack which is a result of the gruesome gas reloc
11239 reloc
->addend
= reloc
->address
;
11241 reloc
->addend
= -reloc
->address
;
11244 /* If this is a variant frag, we may need to adjust the existing
11245 reloc and generate a new one. */
11246 if (fixp
->fx_frag
->fr_opcode
!= NULL
11247 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11248 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11249 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11250 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11251 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11252 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11253 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11257 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11259 /* If this is not the last reloc in this frag, then we have two
11260 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11261 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11262 the second one handle all of them. */
11263 if (fixp
->fx_next
!= NULL
11264 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11266 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11267 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11268 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11269 && (fixp
->fx_next
->fx_r_type
11270 == BFD_RELOC_MIPS_GOT_LO16
))
11271 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11272 && (fixp
->fx_next
->fx_r_type
11273 == BFD_RELOC_MIPS_CALL_LO16
)));
11278 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11279 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11280 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11282 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11283 reloc2
->address
= (reloc
->address
11284 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11285 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11286 reloc2
->addend
= fixp
->fx_addnumber
;
11287 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11288 assert (reloc2
->howto
!= NULL
);
11290 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11294 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11297 reloc3
->address
+= 4;
11300 if (mips_pic
== NO_PIC
)
11302 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11303 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11305 else if (mips_pic
== SVR4_PIC
)
11307 switch (fixp
->fx_r_type
)
11311 case BFD_RELOC_MIPS_GOT16
:
11313 case BFD_RELOC_MIPS_CALL16
:
11314 case BFD_RELOC_MIPS_GOT_LO16
:
11315 case BFD_RELOC_MIPS_CALL_LO16
:
11316 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11324 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11325 fixup_segment converted a non-PC relative reloc into a PC
11326 relative reloc. In such a case, we need to convert the reloc
11328 code
= fixp
->fx_r_type
;
11329 if (fixp
->fx_pcrel
)
11334 code
= BFD_RELOC_8_PCREL
;
11337 code
= BFD_RELOC_16_PCREL
;
11340 code
= BFD_RELOC_32_PCREL
;
11343 code
= BFD_RELOC_64_PCREL
;
11345 case BFD_RELOC_8_PCREL
:
11346 case BFD_RELOC_16_PCREL
:
11347 case BFD_RELOC_32_PCREL
:
11348 case BFD_RELOC_64_PCREL
:
11349 case BFD_RELOC_16_PCREL_S2
:
11350 case BFD_RELOC_PCREL_HI16_S
:
11351 case BFD_RELOC_PCREL_LO16
:
11354 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11355 "Cannot make %s relocation PC relative",
11356 bfd_get_reloc_code_name (code
));
11360 /* To support a PC relative reloc when generating embedded PIC code
11361 for ECOFF, we use a Cygnus extension. We check for that here to
11362 make sure that we don't let such a reloc escape normally. */
11363 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11364 && code
== BFD_RELOC_16_PCREL_S2
11365 && mips_pic
!= EMBEDDED_PIC
)
11366 reloc
->howto
= NULL
;
11368 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11370 if (reloc
->howto
== NULL
)
11372 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11373 "Can not represent %s relocation in this object file format",
11374 bfd_get_reloc_code_name (code
));
11381 /* Relax a machine dependent frag. This returns the amount by which
11382 the current size of the frag should change. */
11385 mips_relax_frag (fragp
, stretch
)
11389 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11392 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11394 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11396 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11401 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11403 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11410 /* Convert a machine dependent frag. */
11413 md_convert_frag (abfd
, asec
, fragp
)
11421 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11424 register const struct mips16_immed_operand
*op
;
11425 boolean small
, ext
;
11428 unsigned long insn
;
11429 boolean use_extend
;
11430 unsigned short extend
;
11432 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11433 op
= mips16_immed_operands
;
11434 while (op
->type
!= type
)
11437 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11448 resolve_symbol_value (fragp
->fr_symbol
, 1);
11449 val
= S_GET_VALUE (fragp
->fr_symbol
);
11454 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11456 /* The rules for the base address of a PC relative reloc are
11457 complicated; see mips16_extended_frag. */
11458 if (type
== 'p' || type
== 'q')
11463 /* Ignore the low bit in the target, since it will be
11464 set for a text label. */
11465 if ((val
& 1) != 0)
11468 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11470 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11473 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11476 /* Make sure the section winds up with the alignment we have
11479 record_alignment (asec
, op
->shift
);
11483 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11484 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11485 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11486 "extended instruction in delay slot");
11488 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11490 if (target_big_endian
)
11491 insn
= bfd_getb16 (buf
);
11493 insn
= bfd_getl16 (buf
);
11495 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11496 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11497 small
, ext
, &insn
, &use_extend
, &extend
);
11501 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11502 fragp
->fr_fix
+= 2;
11506 md_number_to_chars (buf
, insn
, 2);
11507 fragp
->fr_fix
+= 2;
11512 if (fragp
->fr_opcode
== NULL
)
11515 old
= RELAX_OLD (fragp
->fr_subtype
);
11516 new = RELAX_NEW (fragp
->fr_subtype
);
11517 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11520 memcpy (fixptr
- old
, fixptr
, new);
11522 fragp
->fr_fix
+= new - old
;
11528 /* This function is called after the relocs have been generated.
11529 We've been storing mips16 text labels as odd. Here we convert them
11530 back to even for the convenience of the debugger. */
11533 mips_frob_file_after_relocs ()
11536 unsigned int count
, i
;
11538 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11541 syms
= bfd_get_outsymbols (stdoutput
);
11542 count
= bfd_get_symcount (stdoutput
);
11543 for (i
= 0; i
< count
; i
++, syms
++)
11545 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11546 && ((*syms
)->value
& 1) != 0)
11548 (*syms
)->value
&= ~1;
11549 /* If the symbol has an odd size, it was probably computed
11550 incorrectly, so adjust that as well. */
11551 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11552 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11559 /* This function is called whenever a label is defined. It is used
11560 when handling branch delays; if a branch has a label, we assume we
11561 can not move it. */
11564 mips_define_label (sym
)
11567 struct insn_label_list
*l
;
11569 if (free_insn_labels
== NULL
)
11570 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11573 l
= free_insn_labels
;
11574 free_insn_labels
= l
->next
;
11578 l
->next
= insn_labels
;
11582 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11584 /* Some special processing for a MIPS ELF file. */
11587 mips_elf_final_processing ()
11589 /* Write out the register information. */
11594 s
.ri_gprmask
= mips_gprmask
;
11595 s
.ri_cprmask
[0] = mips_cprmask
[0];
11596 s
.ri_cprmask
[1] = mips_cprmask
[1];
11597 s
.ri_cprmask
[2] = mips_cprmask
[2];
11598 s
.ri_cprmask
[3] = mips_cprmask
[3];
11599 /* The gp_value field is set by the MIPS ELF backend. */
11601 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11602 ((Elf32_External_RegInfo
*)
11603 mips_regmask_frag
));
11607 Elf64_Internal_RegInfo s
;
11609 s
.ri_gprmask
= mips_gprmask
;
11611 s
.ri_cprmask
[0] = mips_cprmask
[0];
11612 s
.ri_cprmask
[1] = mips_cprmask
[1];
11613 s
.ri_cprmask
[2] = mips_cprmask
[2];
11614 s
.ri_cprmask
[3] = mips_cprmask
[3];
11615 /* The gp_value field is set by the MIPS ELF backend. */
11617 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11618 ((Elf64_External_RegInfo
*)
11619 mips_regmask_frag
));
11622 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11623 sort of BFD interface for this. */
11624 if (mips_any_noreorder
)
11625 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11626 if (mips_pic
!= NO_PIC
)
11627 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11630 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11632 /* These functions should really be defined by the object file format,
11633 since they are related to debugging information. However, this
11634 code has to work for the a.out format, which does not define them,
11635 so we provide simple versions here. These don't actually generate
11636 any debugging information, but they do simple checking and someday
11637 somebody may make them useful. */
11641 struct loc
*loc_next
;
11642 unsigned long loc_fileno
;
11643 unsigned long loc_lineno
;
11644 unsigned long loc_offset
;
11645 unsigned short loc_delta
;
11646 unsigned short loc_count
;
11653 typedef struct proc
11655 struct proc
*proc_next
;
11656 struct symbol
*proc_isym
;
11657 struct symbol
*proc_end
;
11658 unsigned long proc_reg_mask
;
11659 unsigned long proc_reg_offset
;
11660 unsigned long proc_fpreg_mask
;
11661 unsigned long proc_fpreg_offset
;
11662 unsigned long proc_frameoffset
;
11663 unsigned long proc_framereg
;
11664 unsigned long proc_pcreg
;
11666 struct file
*proc_file
;
11671 typedef struct file
11673 struct file
*file_next
;
11674 unsigned long file_fileno
;
11675 struct symbol
*file_symbol
;
11676 struct symbol
*file_end
;
11677 struct proc
*file_proc
;
11682 static struct obstack proc_frags
;
11683 static procS
*proc_lastP
;
11684 static procS
*proc_rootP
;
11685 static int numprocs
;
11690 obstack_begin (&proc_frags
, 0x2000);
11696 /* check for premature end, nesting errors, etc */
11697 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11698 as_warn ("missing `.end' at end of assembly");
11707 if (*input_line_pointer
== '-')
11709 ++input_line_pointer
;
11712 if (!isdigit (*input_line_pointer
))
11713 as_bad ("Expected simple number.");
11714 if (input_line_pointer
[0] == '0')
11716 if (input_line_pointer
[1] == 'x')
11718 input_line_pointer
+= 2;
11719 while (isxdigit (*input_line_pointer
))
11722 val
|= hex_value (*input_line_pointer
++);
11724 return negative
? -val
: val
;
11728 ++input_line_pointer
;
11729 while (isdigit (*input_line_pointer
))
11732 val
|= *input_line_pointer
++ - '0';
11734 return negative
? -val
: val
;
11737 if (!isdigit (*input_line_pointer
))
11739 printf (" *input_line_pointer == '%c' 0x%02x\n",
11740 *input_line_pointer
, *input_line_pointer
);
11741 as_warn ("Invalid number");
11744 while (isdigit (*input_line_pointer
))
11747 val
+= *input_line_pointer
++ - '0';
11749 return negative
? -val
: val
;
11752 /* The .file directive; just like the usual .file directive, but there
11753 is an initial number which is the ECOFF file index. */
11761 line
= get_number ();
11766 /* The .end directive. */
11774 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11777 demand_empty_rest_of_line ();
11781 if (now_seg
!= text_section
)
11782 as_warn (".end not in text section");
11785 as_warn (".end and no .ent seen yet.");
11791 assert (S_GET_NAME (p
));
11792 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
11793 as_warn (".end symbol does not match .ent symbol.");
11796 proc_lastP
->proc_end
= (symbolS
*) 1;
11799 /* The .aent and .ent directives. */
11809 symbolP
= get_symbol ();
11810 if (*input_line_pointer
== ',')
11811 input_line_pointer
++;
11812 SKIP_WHITESPACE ();
11813 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11814 number
= get_number ();
11815 if (now_seg
!= text_section
)
11816 as_warn (".ent or .aent not in text section.");
11818 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11819 as_warn ("missing `.end'");
11823 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11824 procP
->proc_isym
= symbolP
;
11825 procP
->proc_reg_mask
= 0;
11826 procP
->proc_reg_offset
= 0;
11827 procP
->proc_fpreg_mask
= 0;
11828 procP
->proc_fpreg_offset
= 0;
11829 procP
->proc_frameoffset
= 0;
11830 procP
->proc_framereg
= 0;
11831 procP
->proc_pcreg
= 0;
11832 procP
->proc_end
= NULL
;
11833 procP
->proc_next
= NULL
;
11835 proc_lastP
->proc_next
= procP
;
11837 proc_rootP
= procP
;
11838 proc_lastP
= procP
;
11841 demand_empty_rest_of_line ();
11844 /* The .frame directive. */
11857 frame_reg
= tc_get_register (1);
11858 if (*input_line_pointer
== ',')
11859 input_line_pointer
++;
11860 frame_off
= get_absolute_expression ();
11861 if (*input_line_pointer
== ',')
11862 input_line_pointer
++;
11863 pcreg
= tc_get_register (0);
11865 /* bob third eye */
11866 assert (proc_rootP
);
11867 proc_rootP
->proc_framereg
= frame_reg
;
11868 proc_rootP
->proc_frameoffset
= frame_off
;
11869 proc_rootP
->proc_pcreg
= pcreg
;
11870 /* bob macho .frame */
11872 /* We don't have to write out a frame stab for unoptimized code. */
11873 if (!(frame_reg
== FP
&& frame_off
== 0))
11876 as_warn ("No .ent for .frame to use.");
11877 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11878 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11879 S_SET_TYPE (symP
, N_RMASK
);
11880 S_SET_OTHER (symP
, 0);
11881 S_SET_DESC (symP
, 0);
11882 symP
->sy_forward
= proc_lastP
->proc_isym
;
11883 /* bob perhaps I should have used pseudo set */
11885 demand_empty_rest_of_line ();
11889 /* The .fmask and .mask directives. */
11896 char str
[100], *strP
;
11902 mask
= get_number ();
11903 if (*input_line_pointer
== ',')
11904 input_line_pointer
++;
11905 off
= get_absolute_expression ();
11907 /* bob only for coff */
11908 assert (proc_rootP
);
11909 if (reg_type
== 'F')
11911 proc_rootP
->proc_fpreg_mask
= mask
;
11912 proc_rootP
->proc_fpreg_offset
= off
;
11916 proc_rootP
->proc_reg_mask
= mask
;
11917 proc_rootP
->proc_reg_offset
= off
;
11920 /* bob macho .mask + .fmask */
11922 /* We don't have to write out a mask stab if no saved regs. */
11926 as_warn ("No .ent for .mask to use.");
11928 for (i
= 0; i
< 32; i
++)
11932 sprintf (strP
, "%c%d,", reg_type
, i
);
11933 strP
+= strlen (strP
);
11937 sprintf (strP
, ";%d,", off
);
11938 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11939 S_SET_TYPE (symP
, N_RMASK
);
11940 S_SET_OTHER (symP
, 0);
11941 S_SET_DESC (symP
, 0);
11942 symP
->sy_forward
= proc_lastP
->proc_isym
;
11943 /* bob perhaps I should have used pseudo set */
11948 /* The .loc directive. */
11959 assert (now_seg
== text_section
);
11961 lineno
= get_number ();
11962 addroff
= frag_now_fix ();
11964 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11965 S_SET_TYPE (symbolP
, N_SLINE
);
11966 S_SET_OTHER (symbolP
, 0);
11967 S_SET_DESC (symbolP
, lineno
);
11968 symbolP
->sy_segment
= now_seg
;