1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
3 Copyright (C) 2002-2015 Free Software Foundation, Inc.
4 Contributed by Dmitry Diky <diwil@mail.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #define PUSH_1X_WORKAROUND
27 #include "opcode/msp430.h"
28 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "elf/msp430.h"
32 /* We will disable polymorphs by default because it is dangerous.
33 The potential problem here is the following: assume we got the
38 jump subroutine ; external symbol
43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
51 If the 'subroutine' is within +-1024 bytes range then linker
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
60 The workaround is the following:
61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
62 2. Declare global var enable_relax which set to 1 via option -mQ.
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
69 int msp430_enable_relax
;
70 int msp430_enable_polys
;
72 /* Set linkrelax here to avoid fixups in most sections. */
75 /* GCC uses the some condition codes which we'll
76 implement as new polymorph instructions.
78 COND EXPL SHORT JUMP LONG JUMP
79 ===============================================
80 eq == jeq jne +4; br lab
81 ne != jne jeq +4; br lab
83 ltn honours no-overflow flag
84 ltn < jn jn +2; jmp +4; br lab
86 lt < jl jge +4; br lab
87 ltu < jlo lhs +4; br lab
93 ge >= jge jl +4; br lab
94 geu >= jhs jlo +4; br lab
95 ===============================================
97 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
98 beq,bne,blt,bltn,bltu,bge,bgeu
99 'u' means unsigned compares
101 Also, we add 'jump' instruction:
102 jump UNCOND -> jmp br lab
104 They will have fmt == 4, and insn_opnumb == number of instruction. */
109 int index
; /* Corresponding insn_opnumb. */
110 int sop
; /* Opcode if jump length is short. */
111 long lpos
; /* Label position. */
112 long lop0
; /* Opcode 1 _word_ (16 bits). */
113 long lop1
; /* Opcode second word. */
114 long lop2
; /* Opcode third word. */
117 #define MSP430_RLC(n,i,sop,o1) \
118 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
120 static struct rcodes_s msp430_rcodes
[] =
122 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
123 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
124 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
125 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
126 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
127 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
128 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
129 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
134 #define MSP430_RLC(n,i,sop,o1) \
135 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
137 static struct rcodes_s msp430x_rcodes
[] =
139 MSP430_RLC (beq
, 0, 0x2400, 0x2000),
140 MSP430_RLC (bne
, 1, 0x2000, 0x2400),
141 MSP430_RLC (blt
, 2, 0x3800, 0x3400),
142 MSP430_RLC (bltu
, 3, 0x2800, 0x2c00),
143 MSP430_RLC (bge
, 4, 0x3400, 0x3800),
144 MSP430_RLC (bgeu
, 5, 0x2c00, 0x2800),
145 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
146 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
151 /* More difficult than above and they have format 5.
154 =================================================================
155 gt > jeq +2; jge label jeq +6; jl +4; br label
156 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
157 leu <= jeq label; jlo label jeq +2; jhs +4; br label
158 le <= jeq label; jl label jeq +2; jge +4; br label
159 ================================================================= */
164 int index
; /* Corresponding insn_opnumb. */
165 int tlab
; /* Number of labels in short mode. */
166 int op0
; /* Opcode for first word of short jump. */
167 int op1
; /* Opcode for second word of short jump. */
168 int lop0
; /* Opcodes for long jump mode. */
173 static struct hcodes_s msp430_hcodes
[] =
175 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
176 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
177 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
178 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
182 static struct hcodes_s msp430x_hcodes
[] =
184 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
185 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
186 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
187 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
191 const char comment_chars
[] = ";";
192 const char line_comment_chars
[] = "#";
193 const char line_separator_chars
[] = "{";
194 const char EXP_CHARS
[] = "eE";
195 const char FLT_CHARS
[] = "dD";
197 /* Handle long expressions. */
198 extern LITTLENUM_TYPE generic_bignum
[];
200 static struct hash_control
*msp430_hash
;
203 #define STATE_UNCOND_BRANCH 1 /* jump */
204 #define STATE_NOOV_BRANCH 3 /* bltn */
205 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
206 #define STATE_EMUL_BRANCH 4
215 #define STATE_BITS10 1 /* wild guess. short jump */
216 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more */
217 #define STATE_UNDEF 3 /* cannot handle this yet. convert to word mode */
219 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
220 #define RELAX_STATE(s) ((s) & 3)
221 #define RELAX_LEN(s) ((s) >> 2)
222 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
224 relax_typeS md_relax_table
[] =
232 /* Unconditional jump. */
234 {1024, -1024, CNRL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
235 {0, 0, CUBL
, RELAX_NEXT (STATE_UNCOND_BRANCH
, STATE_WORD
)}, /* state word */
236 {1, 1, CUBL
, 0}, /* state undef */
238 /* Simple branches. */
240 {1024, -1024, CNRL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
241 {0, 0, CSBL
, RELAX_NEXT (STATE_SIMPLE_BRANCH
, STATE_WORD
)}, /* state word */
244 /* blt no overflow branch. */
246 {1024, -1024, CNRL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
247 {0, 0, CNOL
, RELAX_NEXT (STATE_NOOV_BRANCH
, STATE_WORD
)}, /* state word */
250 /* Emulated branches. */
252 {1020, -1020, CEBL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_BITS10
)}, /* state 10 bits displ */
253 {0, 0, CNOL
, RELAX_NEXT (STATE_EMUL_BRANCH
, STATE_WORD
)}, /* state word */
258 #define MAX_OP_LEN 256
267 static enum msp_isa selected_isa
= MSP_ISA_430Xv2
;
269 static inline bfd_boolean
270 target_is_430x (void)
272 return selected_isa
>= MSP_ISA_430X
;
275 static inline bfd_boolean
276 target_is_430xv2 (void)
278 return selected_isa
== MSP_ISA_430Xv2
;
281 /* Generate an absolute 16-bit relocation.
282 For the 430X we generate a relocation without linker range checking
283 if the value is being used in an extended (ie 20-bit) instruction,
284 otherwise if have a shifted expression we use a HI reloc.
285 For the 430 we generate a relocation without assembler range checking
286 if we are handling an immediate value or a byte-width instruction. */
288 #undef CHECK_RELOC_MSP430
289 #define CHECK_RELOC_MSP430(OP) \
293 : ((OP).vshift == 1) \
294 ? BFD_RELOC_MSP430_ABS_HI16 \
295 : BFD_RELOC_MSP430X_ABS16) \
296 : ((imm_op || byte_op) \
297 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
299 /* Generate a 16-bit pc-relative relocation.
300 For the 430X we generate a relocation without linkwer range checking.
301 For the 430 we generate a relocation without assembler range checking
302 if we are handling an immediate value or a byte-width instruction. */
303 #undef CHECK_RELOC_MSP430_PCREL
304 #define CHECK_RELOC_MSP430_PCREL \
306 ? BFD_RELOC_MSP430X_PCR16 \
307 : (imm_op || byte_op) \
308 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
310 /* Profiling capability:
311 It is a performance hit to use gcc's profiling approach for this tiny target.
312 Even more -- jtag hardware facility does not perform any profiling functions.
313 However we've got gdb's built-in simulator where we can do anything.
314 Therefore my suggestion is:
316 We define new section ".profiler" which holds all profiling information.
317 We define new pseudo operation .profiler which will instruct assembler to
318 add new profile entry to the object file. Profile should take place at the
323 .profiler flags,function_to_profile [, cycle_corrector, extra]
325 where 'flags' is a combination of the following chars:
328 i - function is in Init section
329 f - function is in Fini section
331 c - libC standard call
332 d - stack value Demand (saved at run-time in simulator)
333 I - Interrupt service routine
338 j - long Jump/ sjlj unwind
339 a - an Arbitrary code fragment
340 t - exTra parameter saved (constant value like frame size)
341 '""' optional: "sil" == sil
343 function_to_profile - function's address
344 cycle_corrector - a value which should be added to the cycle
345 counter, zero if omitted
346 extra - some extra parameter, zero if omitted.
349 ------------------------------
353 .LFrameOffset_fxx=0x08
354 .profiler "scdP", fxx ; function entry.
355 ; we also demand stack value to be displayed
360 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
361 ; (this is a prologue end)
362 ; note, that spare var filled with the frame size
365 .profiler cdE,fxx ; check stack
370 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
371 ret ; cause 'ret' insn takes 3 cycles
372 -------------------------------
374 This profiling approach does not produce any overhead and
376 So, even profiled code can be uploaded to the MCU. */
377 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
378 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */
379 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
380 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
381 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
382 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
383 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
384 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
385 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
386 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
387 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
388 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
389 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
390 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
391 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
392 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
405 for (; x
; x
= x
>> 1)
412 /* Parse ordinary expression. */
415 parse_exp (char * s
, expressionS
* op
)
417 input_line_pointer
= s
;
419 if (op
->X_op
== O_absent
)
420 as_bad (_("missing operand"));
421 return input_line_pointer
;
425 /* Delete spaces from s: X ( r 1 2) => X(r12). */
428 del_spaces (char * s
)
436 while (ISSPACE (*m
) && *m
)
438 memmove (s
, m
, strlen (m
) + 1);
446 skip_space (char * s
)
453 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
456 extract_operand (char * from
, char * to
, int limit
)
460 /* Drop leading whitespace. */
461 from
= skip_space (from
);
463 while (size
< limit
&& *from
)
465 *(to
+ size
) = *from
;
466 if (*from
== ',' || *from
== ';' || *from
== '\n')
481 msp430_profiler (int dummy ATTRIBUTE_UNUSED
)
498 s
= input_line_pointer
;
499 end
= input_line_pointer
;
501 while (*end
&& *end
!= '\n')
504 while (*s
&& *s
!= '\n')
515 as_bad (_(".profiler pseudo requires at least two operands."));
516 input_line_pointer
= end
;
520 input_line_pointer
= extract_operand (input_line_pointer
, flags
, 32);
529 p_flags
|= MSP430_PROFILER_FLAG_FRAGMENT
;
532 p_flags
|= MSP430_PROFILER_FLAG_JUMP
;
535 p_flags
|= MSP430_PROFILER_FLAG_PROLSTART
;
538 p_flags
|= MSP430_PROFILER_FLAG_PROLEND
;
541 p_flags
|= MSP430_PROFILER_FLAG_EPISTART
;
544 p_flags
|= MSP430_PROFILER_FLAG_EPIEND
;
547 p_flags
|= MSP430_PROFILER_FLAG_ENTRY
;
550 p_flags
|= MSP430_PROFILER_FLAG_EXIT
;
553 p_flags
|= MSP430_PROFILER_FLAG_INITSECT
;
556 p_flags
|= MSP430_PROFILER_FLAG_FINISECT
;
559 p_flags
|= MSP430_PROFILER_FLAG_LIBCALL
;
562 p_flags
|= MSP430_PROFILER_FLAG_STDCALL
;
565 p_flags
|= MSP430_PROFILER_FLAG_STACKDMD
;
568 p_flags
|= MSP430_PROFILER_FLAG_ISR
;
571 p_flags
|= MSP430_PROFILER_FLAG_EXTRA
;
574 as_warn (_("unknown profiling flag - ignored."));
581 && ( ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_ENTRY
582 | MSP430_PROFILER_FLAG_EXIT
))
583 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_PROLSTART
584 | MSP430_PROFILER_FLAG_PROLEND
585 | MSP430_PROFILER_FLAG_EPISTART
586 | MSP430_PROFILER_FLAG_EPIEND
))
587 || ! pow2value (p_flags
& ( MSP430_PROFILER_FLAG_INITSECT
588 | MSP430_PROFILER_FLAG_FINISECT
))))
590 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
591 input_line_pointer
= end
;
595 /* Generate temp symbol which denotes current location. */
596 if (now_seg
== absolute_section
) /* Paranoia ? */
598 exp1
.X_op
= O_constant
;
599 exp1
.X_add_number
= abs_section_offset
;
600 as_warn (_("profiling in absolute section?"));
604 exp1
.X_op
= O_symbol
;
605 exp1
.X_add_symbol
= symbol_temp_new_now ();
606 exp1
.X_add_number
= 0;
609 /* Generate a symbol which holds flags value. */
610 exp
.X_op
= O_constant
;
611 exp
.X_add_number
= p_flags
;
613 /* Save current section. */
617 /* Now go to .profiler section. */
618 obj_elf_change_section (".profiler", SHT_PROGBITS
, 0, 0, 0, 0, 0);
621 emit_expr (& exp
, 2);
623 /* Save label value. */
624 emit_expr (& exp1
, 2);
628 /* Now get profiling info. */
629 halt
= extract_operand (input_line_pointer
, str
, 1024);
630 /* Process like ".word xxx" directive. */
631 parse_exp (str
, & exp
);
632 emit_expr (& exp
, 2);
633 input_line_pointer
= halt
;
636 /* Fill the rest with zeros. */
637 exp
.X_op
= O_constant
;
638 exp
.X_add_number
= 0;
640 emit_expr (& exp
, 2);
642 /* Return to current section. */
643 subseg_set (seg
, subseg
);
647 extract_word (char * from
, char * to
, int limit
)
652 /* Drop leading whitespace. */
653 from
= skip_space (from
);
656 /* Find the op code end. */
657 for (op_end
= from
; *op_end
!= 0 && is_part_of_name (*op_end
);)
659 to
[size
++] = *op_end
++;
660 if (size
+ 1 >= limit
)
668 #define OPTION_MMCU 'm'
669 #define OPTION_RELAX 'Q'
670 #define OPTION_POLYMORPHS 'P'
671 #define OPTION_LARGE 'l'
672 static bfd_boolean large_model
= FALSE
;
673 #define OPTION_NO_INTR_NOPS 'N'
674 #define OPTION_INTR_NOPS 'n'
675 static bfd_boolean gen_interrupt_nops
= FALSE
;
676 #define OPTION_WARN_INTR_NOPS 'y'
677 #define OPTION_NO_WARN_INTR_NOPS 'Y'
678 static bfd_boolean warn_interrupt_nops
= TRUE
;
679 #define OPTION_MCPU 'c'
680 #define OPTION_MOVE_DATA 'd'
681 static bfd_boolean move_data
= FALSE
;
684 msp430_set_arch (int option
)
686 char *str
= (char *) alloca (32); /* 32 for good measure. */
688 input_line_pointer
= extract_word (input_line_pointer
, str
, 32);
690 md_parse_option (option
, str
);
691 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
692 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
695 /* This is the full list of MCU names that are known to only
696 support the 430 ISA. */
697 static const char * msp430_mcu_names
[] =
699 "msp430afe221", "msp430afe222", "msp430afe223", "msp430afe231",
700 "msp430afe232", "msp430afe233", "msp430afe251", "msp430afe252",
701 "msp430afe253", "msp430c091", "msp430c092", "msp430c111",
702 "msp430c1111", "msp430c112", "msp430c1121", "msp430c1331",
703 "msp430c1351", "msp430c311s", "msp430c312", "msp430c313",
704 "msp430c314", "msp430c315", "msp430c323", "msp430c325",
705 "msp430c336", "msp430c337", "msp430c412", "msp430c413",
706 "msp430e112", "msp430e313", "msp430e315", "msp430e325",
707 "msp430e337", "msp430f110", "msp430f1101", "msp430f1101a",
708 "msp430f1111", "msp430f1111a", "msp430f112", "msp430f1121",
709 "msp430f1121a", "msp430f1122", "msp430f1132", "msp430f122",
710 "msp430f1222", "msp430f123", "msp430f1232", "msp430f133",
711 "msp430f135", "msp430f147", "msp430f1471", "msp430f148",
712 "msp430f1481", "msp430f149", "msp430f1491", "msp430f155",
713 "msp430f156", "msp430f157", "msp430f1610", "msp430f1611",
714 "msp430f1612", "msp430f167", "msp430f168", "msp430f169",
715 "msp430f2001", "msp430f2002", "msp430f2003", "msp430f2011",
716 "msp430f2012", "msp430f2013", "msp430f2101", "msp430f2111",
717 "msp430f2112", "msp430f2121", "msp430f2122", "msp430f2131",
718 "msp430f2132", "msp430f2232", "msp430f2234", "msp430f2252",
719 "msp430f2254", "msp430f2272", "msp430f2274", "msp430f233",
720 "msp430f2330", "msp430f235", "msp430f2350", "msp430f2370",
721 "msp430f2410", "msp430f247", "msp430f2471", "msp430f248",
722 "msp430f2481", "msp430f249", "msp430f2491", "msp430f412",
723 "msp430f413", "msp430f4132", "msp430f415", "msp430f4152",
724 "msp430f417", "msp430f423", "msp430f423a", "msp430f425",
725 "msp430f4250", "msp430f425a", "msp430f4260", "msp430f427",
726 "msp430f4270", "msp430f427a", "msp430f435", "msp430f4351",
727 "msp430f436", "msp430f4361", "msp430f437", "msp430f4371",
728 "msp430f438", "msp430f439", "msp430f447", "msp430f448",
729 "msp430f4481", "msp430f449", "msp430f4491", "msp430f477",
730 "msp430f478", "msp430f4783", "msp430f4784", "msp430f479",
731 "msp430f4793", "msp430f4794", "msp430fe423", "msp430fe4232",
732 "msp430fe423a", "msp430fe4242", "msp430fe425", "msp430fe4252",
733 "msp430fe425a", "msp430fe427", "msp430fe4272", "msp430fe427a",
734 "msp430fg4250", "msp430fg4260", "msp430fg4270", "msp430fg437",
735 "msp430fg438", "msp430fg439", "msp430fg477", "msp430fg478",
736 "msp430fg479", "msp430fw423", "msp430fw425", "msp430fw427",
737 "msp430fw428", "msp430fw429", "msp430g2001", "msp430g2101",
738 "msp430g2102", "msp430g2111", "msp430g2112", "msp430g2113",
739 "msp430g2121", "msp430g2131", "msp430g2132", "msp430g2152",
740 "msp430g2153", "msp430g2201", "msp430g2202", "msp430g2203",
741 "msp430g2210", "msp430g2211", "msp430g2212", "msp430g2213",
742 "msp430g2221", "msp430g2230", "msp430g2231", "msp430g2232",
743 "msp430g2233", "msp430g2252", "msp430g2253", "msp430g2302",
744 "msp430g2303", "msp430g2312", "msp430g2313", "msp430g2332",
745 "msp430g2333", "msp430g2352", "msp430g2353", "msp430g2402",
746 "msp430g2403", "msp430g2412", "msp430g2413", "msp430g2432",
747 "msp430g2433", "msp430g2444", "msp430g2452", "msp430g2453",
748 "msp430g2513", "msp430g2533", "msp430g2544", "msp430g2553",
749 "msp430g2744", "msp430g2755", "msp430g2855", "msp430g2955",
750 "msp430i2020", "msp430i2021", "msp430i2030", "msp430i2031",
751 "msp430i2040", "msp430i2041", "msp430l092", "msp430p112",
752 "msp430p313", "msp430p315", "msp430p315s", "msp430p325",
753 "msp430p337", "msp430tch5e"
757 md_parse_option (int c
, char * arg
)
763 as_fatal (_("MCU option requires a name\n"));
765 if (strcasecmp ("msp430", arg
) == 0)
766 selected_isa
= MSP_ISA_430
;
767 else if (strcasecmp ("msp430xv2", arg
) == 0)
768 selected_isa
= MSP_ISA_430Xv2
;
769 else if (strcasecmp ("msp430x", arg
) == 0)
770 selected_isa
= MSP_ISA_430X
;
775 for (i
= sizeof msp430_mcu_names
/ sizeof msp430_mcu_names
[0]; i
--;)
776 if (strcasecmp (msp430_mcu_names
[i
], arg
) == 0)
778 selected_isa
= MSP_ISA_430
;
782 /* It is not an error if we do not match the MCU name. */
786 if (strcmp (arg
, "430") == 0
787 || strcasecmp (arg
, "msp430") == 0)
788 selected_isa
= MSP_ISA_430
;
789 else if (strcasecmp (arg
, "430x") == 0
790 || strcasecmp (arg
, "msp430x") == 0)
791 selected_isa
= MSP_ISA_430X
;
792 else if (strcasecmp (arg
, "430xv2") == 0
793 || strcasecmp (arg
, "msp430xv2") == 0)
794 selected_isa
= MSP_ISA_430Xv2
;
796 as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg
);
800 msp430_enable_relax
= 1;
803 case OPTION_POLYMORPHS
:
804 msp430_enable_polys
= 1;
811 case OPTION_NO_INTR_NOPS
:
812 gen_interrupt_nops
= FALSE
;
814 case OPTION_INTR_NOPS
:
815 gen_interrupt_nops
= TRUE
;
818 case OPTION_WARN_INTR_NOPS
:
819 warn_interrupt_nops
= TRUE
;
821 case OPTION_NO_WARN_INTR_NOPS
:
822 warn_interrupt_nops
= FALSE
;
825 case OPTION_MOVE_DATA
:
833 /* The intention here is to have the mere presence of these sections
834 cause the object to have a reference to a well-known symbol. This
835 reference pulls in the bits of the runtime (crt0) that initialize
836 these sections. Thus, for example, the startup code to call
837 memset() to initialize .bss will only be linked in when there is a
838 non-empty .bss section. Otherwise, the call would exist but have a
839 zero length parameter, which is a waste of memory and cycles.
841 The code which initializes these sections should have a global
842 label for these symbols, and should be marked with KEEP() in the
846 msp430_section (int arg
)
848 char * saved_ilp
= input_line_pointer
;
849 char * name
= obj_elf_section_name ();
851 if (strncmp (name
, ".bss", 4) == 0
852 || strncmp (name
, ".gnu.linkonce.b.", 16) == 0)
853 (void) symbol_find_or_make ("__crt0_init_bss");
855 if (strncmp (name
, ".data", 5) == 0
856 || strncmp (name
, ".gnu.linkonce.d.", 16) == 0)
857 (void) symbol_find_or_make ("__crt0_movedata");
859 input_line_pointer
= saved_ilp
;
860 obj_elf_section (arg
);
864 msp430_frob_section (asection
*sec
)
866 const char *name
= sec
->name
;
871 if (strncmp (name
, ".bss", 4) == 0
872 || strncmp (name
, ".gnu.linkonce.b.", 16) == 0)
873 (void) symbol_find_or_make ("__crt0_init_bss");
875 if (strncmp (name
, ".data", 5) == 0
876 || strncmp (name
, ".gnu.linkonce.d.", 16) == 0)
877 (void) symbol_find_or_make ("__crt0_movedata");
881 msp430_lcomm (int ignore ATTRIBUTE_UNUSED
)
883 symbolS
*symbolP
= s_comm_internal (0, s_lcomm_internal
);
886 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
887 (void) symbol_find_or_make ("__crt0_init_bss");
891 msp430_comm (int needs_align
)
893 s_comm_internal (needs_align
, elf_common_parse
);
894 (void) symbol_find_or_make ("__crt0_init_bss");
898 msp430_refsym (int arg ATTRIBUTE_UNUSED
)
901 input_line_pointer
= extract_word (input_line_pointer
, sym_name
, 1024);
903 (void) symbol_find_or_make (sym_name
);
906 const pseudo_typeS md_pseudo_table
[] =
908 {"arch", msp430_set_arch
, OPTION_MMCU
},
909 {"cpu", msp430_set_arch
, OPTION_MCPU
},
910 {"profiler", msp430_profiler
, 0},
911 {"section", msp430_section
, 0},
912 {"section.s", msp430_section
, 0},
913 {"sect", msp430_section
, 0},
914 {"sect.s", msp430_section
, 0},
915 {"pushsection", msp430_section
, 1},
916 {"refsym", msp430_refsym
, 0},
917 {"comm", msp430_comm
, 0},
918 {"lcomm", msp430_lcomm
, 0},
922 const char *md_shortopts
= "mm:,mP,mQ,ml,mN,mn,my,mY";
924 struct option md_longopts
[] =
926 {"mmcu", required_argument
, NULL
, OPTION_MMCU
},
927 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
928 {"mP", no_argument
, NULL
, OPTION_POLYMORPHS
},
929 {"mQ", no_argument
, NULL
, OPTION_RELAX
},
930 {"ml", no_argument
, NULL
, OPTION_LARGE
},
931 {"mN", no_argument
, NULL
, OPTION_NO_INTR_NOPS
},
932 {"mn", no_argument
, NULL
, OPTION_INTR_NOPS
},
933 {"mY", no_argument
, NULL
, OPTION_NO_WARN_INTR_NOPS
},
934 {"my", no_argument
, NULL
, OPTION_WARN_INTR_NOPS
},
935 {"md", no_argument
, NULL
, OPTION_MOVE_DATA
},
936 {NULL
, no_argument
, NULL
, 0}
939 size_t md_longopts_size
= sizeof (md_longopts
);
942 md_show_usage (FILE * stream
)
945 _("MSP430 options:\n"
946 " -mmcu=<msp430-name> - select microcontroller type\n"
947 " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
949 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
950 " -mP - enable polymorph instructions\n"));
952 _(" -ml - enable large code model\n"));
954 _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
956 _(" -mn - insert a NOP after changing interrupts\n"));
958 _(" -mY - do not warn about missing NOPs after changing interrupts\n"));
960 _(" -my - warn about missing NOPs after changing interrupts (default)\n"));
962 _(" -md - Force copying of data from ROM to RAM at startup\n"));
966 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
972 extract_cmd (char * from
, char * to
, int limit
)
976 while (*from
&& ! ISSPACE (*from
) && *from
!= '.' && limit
> size
)
978 *(to
+ size
) = *from
;
989 md_atof (int type
, char * litP
, int * sizeP
)
991 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
997 struct msp430_opcode_s
* opcode
;
998 msp430_hash
= hash_new ();
1000 for (opcode
= msp430_opcodes
; opcode
->name
; opcode
++)
1001 hash_insert (msp430_hash
, opcode
->name
, (char *) opcode
);
1003 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
1004 target_is_430x () ? bfd_mach_msp430x
: bfd_mach_msp11
);
1007 /* Returns the register number equivalent to the string T.
1008 Returns -1 if there is no such register.
1009 Skips a leading 'r' or 'R' character if there is one.
1010 Handles the register aliases PC and SP. */
1013 check_reg (char * t
)
1020 if (*t
== 'r' || *t
== 'R')
1023 if (strncasecmp (t
, "pc", 2) == 0)
1026 if (strncasecmp (t
, "sp", 2) == 0)
1029 if (strncasecmp (t
, "sr", 2) == 0)
1037 if (val
< 1 || val
> 15)
1044 msp430_srcoperand (struct msp430_operand_s
* op
,
1047 bfd_boolean
* imm_op
,
1048 bfd_boolean allow_20bit_values
,
1049 bfd_boolean constants_allowed
)
1053 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1060 /* Check if there is:
1061 llo(x) - least significant 16 bits, x &= 0xffff
1062 lhi(x) - x = (x >> 16) & 0xffff,
1063 hlo(x) - x = (x >> 32) & 0xffff,
1064 hhi(x) - x = (x >> 48) & 0xffff
1065 The value _MUST_ be constant expression: #hlo(1231231231). */
1069 if (strncasecmp (h
, "#llo(", 5) == 0)
1074 else if (strncasecmp (h
, "#lhi(", 5) == 0)
1079 else if (strncasecmp (h
, "#hlo(", 5) == 0)
1084 else if (strncasecmp (h
, "#hhi(", 5) == 0)
1089 else if (strncasecmp (h
, "#lo(", 4) == 0)
1094 else if (strncasecmp (h
, "#hi(", 4) == 0)
1100 op
->reg
= 0; /* Reg PC. */
1102 op
->ol
= 1; /* Immediate will follow an instruction. */
1103 __tl
= h
+ 1 + rval
;
1105 op
->vshift
= vshift
;
1107 parse_exp (__tl
, &(op
->exp
));
1108 if (op
->exp
.X_op
== O_constant
)
1110 int x
= op
->exp
.X_add_number
;
1115 op
->exp
.X_add_number
= x
;
1117 else if (vshift
== 1)
1119 x
= (x
>> 16) & 0xffff;
1120 op
->exp
.X_add_number
= x
;
1123 else if (vshift
> 1)
1126 op
->exp
.X_add_number
= -1;
1128 op
->exp
.X_add_number
= 0; /* Nothing left. */
1129 x
= op
->exp
.X_add_number
;
1133 if (allow_20bit_values
)
1135 if (op
->exp
.X_add_number
> 0xfffff || op
->exp
.X_add_number
< -524288)
1137 as_bad (_("value 0x%x out of extended range."), x
);
1141 else if (op
->exp
.X_add_number
> 65535 || op
->exp
.X_add_number
< -32768)
1143 as_bad (_("value %d out of range. Use #lo() or #hi()"), x
);
1147 /* Now check constants. */
1148 /* Substitute register mode with a constant generator if applicable. */
1150 if (!allow_20bit_values
)
1151 x
= (short) x
; /* Extend sign. */
1153 if (! constants_allowed
)
1185 #ifdef PUSH_1X_WORKAROUND
1188 /* Remove warning as confusing.
1189 as_warn (_("Hardware push bug workaround")); */
1202 #ifdef PUSH_1X_WORKAROUND
1205 /* Remove warning as confusing.
1206 as_warn (_("Hardware push bug workaround")); */
1218 else if (op
->exp
.X_op
== O_symbol
)
1221 as_bad (_("error: unsupported #foo() directive used on symbol"));
1224 else if (op
->exp
.X_op
== O_big
)
1230 op
->exp
.X_op
= O_constant
;
1231 op
->exp
.X_add_number
= 0xffff & generic_bignum
[vshift
];
1232 x
= op
->exp
.X_add_number
;
1238 ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
1286 /* Redundant (yet) check. */
1287 else if (op
->exp
.X_op
== O_register
)
1289 (_("Registers cannot be used within immediate expression [%s]"), l
);
1291 as_bad (_("unknown operand %s"), l
);
1296 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
1301 op
->reg
= 2; /* reg 2 in absolute addr mode. */
1302 op
->am
= 1; /* mode As == 01 bin. */
1303 op
->ol
= 1; /* Immediate value followed by instruction. */
1305 parse_exp (__tl
, &(op
->exp
));
1308 if (op
->exp
.X_op
== O_constant
)
1310 int x
= op
->exp
.X_add_number
;
1312 if (allow_20bit_values
)
1314 if (x
> 0xfffff || x
< -(0x7ffff))
1316 as_bad (_("value 0x%x out of extended range."), x
);
1320 else if (x
> 65535 || x
< -32768)
1322 as_bad (_("value out of range: 0x%x"), x
);
1326 else if (op
->exp
.X_op
== O_symbol
)
1330 /* Redundant (yet) check. */
1331 if (op
->exp
.X_op
== O_register
)
1333 (_("Registers cannot be used within absolute expression [%s]"), l
);
1335 as_bad (_("unknown expression in operand %s"), l
);
1341 /* Check if indirect register mode @Rn / postincrement @Rn+. */
1345 char *m
= strchr (l
, '+');
1349 as_bad (_("unknown addressing mode %s"), l
);
1355 if ((op
->reg
= check_reg (t
)) == -1)
1357 as_bad (_("Bad register name %s"), t
);
1365 /* PC cannot be used in indirect addressing. */
1366 if (target_is_430xv2 () && op
->reg
== 0)
1368 as_bad (_("cannot use indirect addressing with the PC"));
1375 /* Check if register indexed X(Rn). */
1378 char *h
= strrchr (l
, '(');
1379 char *m
= strrchr (l
, ')');
1388 as_bad (_("')' required"));
1396 /* Extract a register. */
1397 if ((op
->reg
= check_reg (t
+ 1)) == -1)
1400 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
1407 as_bad (_("r2 should not be used in indexed addressing mode"));
1411 /* Extract constant. */
1416 parse_exp (__tl
, &(op
->exp
));
1417 if (op
->exp
.X_op
== O_constant
)
1419 int x
= op
->exp
.X_add_number
;
1421 if (allow_20bit_values
)
1423 if (x
> 0xfffff || x
< - (0x7ffff))
1425 as_bad (_("value 0x%x out of extended range."), x
);
1429 else if (x
> 65535 || x
< -32768)
1431 as_bad (_("value out of range: 0x%x"), x
);
1443 else if (op
->exp
.X_op
== O_symbol
)
1447 /* Redundant (yet) check. */
1448 if (op
->exp
.X_op
== O_register
)
1450 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l
);
1452 as_bad (_("unknown expression in operand %s"), l
);
1460 /* Possibly register mode 'mov r1,r2'. */
1461 if ((op
->reg
= check_reg (l
)) != -1)
1469 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
1473 op
->reg
= 0; /* PC relative... be careful. */
1474 /* An expression starting with a minus sign is a constant, not an address. */
1475 op
->am
= (*l
== '-' ? 3 : 1);
1479 parse_exp (__tl
, &(op
->exp
));
1485 as_bad (_("unknown addressing mode for operand %s"), l
);
1491 msp430_dstoperand (struct msp430_operand_s
* op
,
1494 bfd_boolean allow_20bit_values
,
1495 bfd_boolean constants_allowed
)
1498 int ret
= msp430_srcoperand (op
, l
, bin
, & dummy
,
1513 parse_exp (__tl
, &(op
->exp
));
1515 if (op
->exp
.X_op
!= O_constant
|| op
->exp
.X_add_number
!= 0)
1517 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
1527 ("this addressing mode is not applicable for destination operand"));
1533 /* Attempt to encode a MOVA instruction with the given operands.
1534 Returns the length of the encoded instruction if successful
1535 or 0 upon failure. If the encoding fails, an error message
1536 will be returned if a pointer is provided. */
1539 try_encode_mova (bfd_boolean imm_op
,
1541 struct msp430_operand_s
* op1
,
1542 struct msp430_operand_s
* op2
,
1543 const char ** error_message_return
)
1549 /* Only a restricted subset of the normal MSP430 addressing modes
1550 are supported here, so check for the ones that are allowed. */
1553 if (op1
->mode
== OP_EXP
)
1555 if (op2
->mode
!= OP_REG
)
1557 if (error_message_return
!= NULL
)
1558 * error_message_return
= _("expected register as second argument of %s");
1564 /* MOVA #imm20, Rdst. */
1565 bin
|= 0x80 | op2
->reg
;
1566 frag
= frag_more (4);
1567 where
= frag
- frag_now
->fr_literal
;
1568 if (op1
->exp
.X_op
== O_constant
)
1570 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
1571 bfd_putl16 ((bfd_vma
) bin
, frag
);
1572 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1576 bfd_putl16 ((bfd_vma
) bin
, frag
);
1577 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
1578 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
1579 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1584 else if (op1
->am
== 1)
1586 /* MOVA z16(Rsrc), Rdst. */
1587 bin
|= 0x30 | (op1
->reg
<< 8) | op2
->reg
;
1588 frag
= frag_more (4);
1589 where
= frag
- frag_now
->fr_literal
;
1590 bfd_putl16 ((bfd_vma
) bin
, frag
);
1591 if (op1
->exp
.X_op
== O_constant
)
1593 if (op1
->exp
.X_add_number
> 0xffff
1594 || op1
->exp
.X_add_number
< -(0x7fff))
1596 if (error_message_return
!= NULL
)
1597 * error_message_return
= _("index value too big for %s");
1600 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1604 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1605 fix_new_exp (frag_now
, where
+ 2, 2, &(op1
->exp
), FALSE
,
1607 BFD_RELOC_MSP430X_PCR16
:
1608 BFD_RELOC_MSP430X_ABS16
);
1613 if (error_message_return
!= NULL
)
1614 * error_message_return
= _("unexpected addressing mode for %s");
1617 else if (op1
->am
== 0)
1619 /* MOVA Rsrc, ... */
1620 if (op2
->mode
== OP_REG
)
1622 bin
|= 0xc0 | (op1
->reg
<< 8) | op2
->reg
;
1623 frag
= frag_more (2);
1624 where
= frag
- frag_now
->fr_literal
;
1625 bfd_putl16 ((bfd_vma
) bin
, frag
);
1628 else if (op2
->am
== 1)
1632 /* MOVA Rsrc, &abs20. */
1633 bin
|= 0x60 | (op1
->reg
<< 8);
1634 frag
= frag_more (4);
1635 where
= frag
- frag_now
->fr_literal
;
1636 if (op2
->exp
.X_op
== O_constant
)
1638 bin
|= (op2
->exp
.X_add_number
>> 16) & 0xf;
1639 bfd_putl16 ((bfd_vma
) bin
, frag
);
1640 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
1644 bfd_putl16 ((bfd_vma
) bin
, frag
);
1645 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1646 fix_new_exp (frag_now
, where
, 4, &(op2
->exp
), FALSE
,
1647 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
1652 /* MOVA Rsrc, z16(Rdst). */
1653 bin
|= 0x70 | (op1
->reg
<< 8) | op2
->reg
;
1654 frag
= frag_more (4);
1655 where
= frag
- frag_now
->fr_literal
;
1656 bfd_putl16 ((bfd_vma
) bin
, frag
);
1657 if (op2
->exp
.X_op
== O_constant
)
1659 if (op2
->exp
.X_add_number
> 0xffff
1660 || op2
->exp
.X_add_number
< -(0x7fff))
1662 if (error_message_return
!= NULL
)
1663 * error_message_return
= _("index value too big for %s");
1666 bfd_putl16 (op2
->exp
.X_add_number
& 0xffff, frag
+ 2);
1670 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1671 fix_new_exp (frag_now
, where
+ 2, 2, &(op2
->exp
), FALSE
,
1673 BFD_RELOC_MSP430X_PCR16
:
1674 BFD_RELOC_MSP430X_ABS16
);
1679 if (error_message_return
!= NULL
)
1680 * error_message_return
= _("unexpected addressing mode for %s");
1685 /* imm_op == FALSE. */
1687 if (op1
->reg
== 2 && op1
->am
== 1 && op1
->mode
== OP_EXP
)
1689 /* MOVA &abs20, Rdst. */
1690 if (op2
->mode
!= OP_REG
)
1692 if (error_message_return
!= NULL
)
1693 * error_message_return
= _("expected register as second argument of %s");
1697 if (op2
->reg
== 2 || op2
->reg
== 3)
1699 if (error_message_return
!= NULL
)
1700 * error_message_return
= _("constant generator destination register found in %s");
1704 bin
|= 0x20 | op2
->reg
;
1705 frag
= frag_more (4);
1706 where
= frag
- frag_now
->fr_literal
;
1707 if (op1
->exp
.X_op
== O_constant
)
1709 bin
|= ((op1
->exp
.X_add_number
>> 16) & 0xf) << 8;
1710 bfd_putl16 ((bfd_vma
) bin
, frag
);
1711 bfd_putl16 (op1
->exp
.X_add_number
& 0xffff, frag
+ 2);
1715 bfd_putl16 ((bfd_vma
) bin
, frag
);
1716 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
1717 fix_new_exp (frag_now
, where
, 4, &(op1
->exp
), FALSE
,
1718 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
1722 else if (op1
->mode
== OP_REG
)
1726 /* MOVA @Rsrc+, Rdst. */
1727 if (op2
->mode
!= OP_REG
)
1729 if (error_message_return
!= NULL
)
1730 * error_message_return
= _("expected register as second argument of %s");
1734 if (op2
->reg
== 2 || op2
->reg
== 3)
1736 if (error_message_return
!= NULL
)
1737 * error_message_return
= _("constant generator destination register found in %s");
1741 if (op1
->reg
== 2 || op1
->reg
== 3)
1743 if (error_message_return
!= NULL
)
1744 * error_message_return
= _("constant generator source register found in %s");
1748 bin
|= 0x10 | (op1
->reg
<< 8) | op2
->reg
;
1749 frag
= frag_more (2);
1750 where
= frag
- frag_now
->fr_literal
;
1751 bfd_putl16 ((bfd_vma
) bin
, frag
);
1754 else if (op1
->am
== 2)
1756 /* MOVA @Rsrc,Rdst */
1757 if (op2
->mode
!= OP_REG
)
1759 if (error_message_return
!= NULL
)
1760 * error_message_return
= _("expected register as second argument of %s");
1764 if (op2
->reg
== 2 || op2
->reg
== 3)
1766 if (error_message_return
!= NULL
)
1767 * error_message_return
= _("constant generator destination register found in %s");
1771 if (op1
->reg
== 2 || op1
->reg
== 3)
1773 if (error_message_return
!= NULL
)
1774 * error_message_return
= _("constant generator source register found in %s");
1778 bin
|= (op1
->reg
<< 8) | op2
->reg
;
1779 frag
= frag_more (2);
1780 where
= frag
- frag_now
->fr_literal
;
1781 bfd_putl16 ((bfd_vma
) bin
, frag
);
1786 if (error_message_return
!= NULL
)
1787 * error_message_return
= _("unexpected addressing mode for %s");
1792 static bfd_boolean check_for_nop
= FALSE
;
1794 #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
1796 /* Parse instruction operands.
1797 Return binary opcode. */
1800 msp430_operands (struct msp430_opcode_s
* opcode
, char * line
)
1802 int bin
= opcode
->bin_opcode
; /* Opcode mask. */
1803 int insn_length
= 0;
1804 char l1
[MAX_OP_LEN
], l2
[MAX_OP_LEN
];
1807 struct msp430_operand_s op1
, op2
;
1809 static short ZEROS
= 0;
1810 bfd_boolean byte_op
, imm_op
;
1813 int extended
= 0x1800;
1814 bfd_boolean extended_op
= FALSE
;
1815 bfd_boolean addr_op
;
1816 const char * error_message
;
1817 static signed int repeat_count
= 0;
1818 bfd_boolean fix_emitted
;
1819 bfd_boolean nop_check_needed
= FALSE
;
1821 /* Opcode is the one from opcodes table
1822 line contains something like
1831 bfd_boolean check
= FALSE
;
1834 switch (TOLOWER (* line
))
1837 /* Byte operation. */
1838 bin
|= BYTE_OPERATION
;
1844 /* "Address" ops work on 20-bit values. */
1846 bin
|= BYTE_OPERATION
;
1851 /* Word operation - this is the default. */
1859 as_warn (_("no size modifier after period, .w assumed"));
1863 as_bad (_("unrecognised instruction size modifier .%c"),
1875 if (*line
&& ! ISSPACE (*line
))
1877 as_bad (_("junk found after instruction: %s.%s"),
1878 opcode
->name
, line
);
1882 /* Catch the case where the programmer has used a ".a" size modifier on an
1883 instruction that does not support it. Look for an alternative extended
1884 instruction that has the same name without the period. Eg: "add.a"
1885 becomes "adda". Although this not an officially supported way of
1886 specifing instruction aliases other MSP430 assemblers allow it. So we
1887 support it for compatibility purposes. */
1888 if (addr_op
&& opcode
->fmt
>= 0)
1890 char * old_name
= opcode
->name
;
1893 sprintf (real_name
, "%sa", old_name
);
1894 opcode
= hash_find (msp430_hash
, real_name
);
1897 as_bad (_("instruction %s.a does not exist"), old_name
);
1900 #if 0 /* Enable for debugging. */
1901 as_warn ("treating %s.a as %s", old_name
, real_name
);
1904 bin
= opcode
->bin_opcode
;
1907 if (opcode
->fmt
!= -1
1908 && opcode
->insn_opnumb
1909 && (!*line
|| *line
== '\n'))
1911 as_bad (_("instruction %s requires %d operand(s)"),
1912 opcode
->name
, opcode
->insn_opnumb
);
1916 memset (l1
, 0, sizeof (l1
));
1917 memset (l2
, 0, sizeof (l2
));
1918 memset (&op1
, 0, sizeof (op1
));
1919 memset (&op2
, 0, sizeof (op2
));
1923 if ((fmt
= opcode
->fmt
) < 0)
1925 if (! target_is_430x ())
1927 as_bad (_("instruction %s requires MSP430X mcu"),
1938 /* If requested set the extended instruction repeat count. */
1941 if (repeat_count
> 0)
1942 extended
|= (repeat_count
- 1);
1944 extended
|= (1 << 7) | (- repeat_count
);
1947 as_bad (_("unable to repeat %s insn"), opcode
->name
);
1952 if (check_for_nop
&& is_opcode ("nop"))
1953 check_for_nop
= FALSE
;
1957 case 0: /* Emulated. */
1958 switch (opcode
->insn_opnumb
)
1961 if (is_opcode ("eint") || is_opcode ("dint"))
1965 if (warn_interrupt_nops
)
1967 if (gen_interrupt_nops
)
1968 as_warn (_("NOP inserted between two instructions that change interrupt state"));
1970 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
1973 if (gen_interrupt_nops
)
1975 /* Emit a NOP between interrupt enable/disable.
1976 See 1.3.4.1 of the MSP430x5xx User Guide. */
1978 frag
= frag_more (2);
1979 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
1983 nop_check_needed
= TRUE
;
1986 /* Set/clear bits instructions. */
1990 extended
|= BYTE_OPERATION
;
1992 /* Emit the extension word. */
1994 frag
= frag_more (2);
1995 bfd_putl16 (extended
, frag
);
1999 frag
= frag_more (2);
2000 bfd_putl16 ((bfd_vma
) bin
, frag
);
2001 dwarf2_emit_insn (insn_length
);
2005 /* Something which works with destination operand. */
2006 line
= extract_operand (line
, l1
, sizeof (l1
));
2007 res
= msp430_dstoperand (&op1
, l1
, opcode
->bin_opcode
, extended_op
, TRUE
);
2011 bin
|= (op1
.reg
| (op1
.am
<< 7));
2013 if (is_opcode ("clr") && bin
== 0x4302 /* CLR R2*/)
2017 if (warn_interrupt_nops
)
2019 if (gen_interrupt_nops
)
2020 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2022 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2025 if (gen_interrupt_nops
)
2027 /* Emit a NOP between interrupt enable/disable.
2028 See 1.3.4.1 of the MSP430x5xx User Guide. */
2030 frag
= frag_more (2);
2031 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
2035 nop_check_needed
= TRUE
;
2038 /* Compute the entire instruction length, in bytes. */
2039 op_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
2040 insn_length
+= op_length
;
2041 frag
= frag_more (op_length
);
2042 where
= frag
- frag_now
->fr_literal
;
2047 extended
|= BYTE_OPERATION
;
2049 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
2051 as_bad (_("repeat instruction used with non-register mode instruction"));
2055 if (op1
.mode
== OP_EXP
)
2057 if (op1
.exp
.X_op
== O_constant
)
2058 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2060 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2061 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2062 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2064 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2065 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2068 /* Emit the extension word. */
2069 bfd_putl16 (extended
, frag
);
2074 bfd_putl16 ((bfd_vma
) bin
, frag
);
2078 if (op1
.mode
== OP_EXP
)
2080 if (op1
.exp
.X_op
== O_constant
)
2082 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2086 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2091 fix_new_exp (frag_now
, where
, 2,
2092 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2094 fix_new_exp (frag_now
, where
, 2,
2095 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2100 dwarf2_emit_insn (insn_length
);
2104 /* Shift instruction. */
2105 line
= extract_operand (line
, l1
, sizeof (l1
));
2106 strncpy (l2
, l1
, sizeof (l2
));
2107 l2
[sizeof (l2
) - 1] = '\0';
2108 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
2109 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
2112 break; /* An error occurred. All warnings were done before. */
2114 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2) + (op2
.ol
* 2);
2115 frag
= frag_more (insn_length
);
2116 where
= frag
- frag_now
->fr_literal
;
2118 if (target_is_430xv2 ()
2119 && op1
.mode
== OP_REG
2121 && (is_opcode ("rlax")
2122 || is_opcode ("rlcx")
2123 || is_opcode ("rla")
2124 || is_opcode ("rlc")))
2126 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2133 extended
|= BYTE_OPERATION
;
2135 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
2137 as_bad (_("repeat instruction used with non-register mode instruction"));
2141 if (op1
.mode
== OP_EXP
)
2143 if (op1
.exp
.X_op
== O_constant
)
2144 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2146 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2147 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2148 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2150 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2151 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2154 if (op2
.mode
== OP_EXP
)
2156 if (op2
.exp
.X_op
== O_constant
)
2157 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
2159 else if (op1
.mode
== OP_EXP
)
2160 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
2161 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2162 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
2164 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
2165 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
2166 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
2169 /* Emit the extension word. */
2170 bfd_putl16 (extended
, frag
);
2175 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
2176 bfd_putl16 ((bfd_vma
) bin
, frag
);
2180 if (op1
.mode
== OP_EXP
)
2182 if (op1
.exp
.X_op
== O_constant
)
2184 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2188 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2192 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2193 fix_new_exp (frag_now
, where
, 2,
2194 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2196 fix_new_exp (frag_now
, where
, 2,
2197 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2204 if (op2
.mode
== OP_EXP
)
2206 if (op2
.exp
.X_op
== O_constant
)
2208 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
2212 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2216 if (op2
.reg
) /* Not PC relative. */
2217 fix_new_exp (frag_now
, where
, 2,
2218 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430 (op2
));
2220 fix_new_exp (frag_now
, where
, 2,
2221 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2226 dwarf2_emit_insn (insn_length
);
2230 /* Branch instruction => mov dst, r0. */
2233 as_bad ("Internal error: state 0/3 not coded for extended instructions");
2237 line
= extract_operand (line
, l1
, sizeof (l1
));
2238 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, FALSE
);
2244 bin
|= ((op1
.reg
<< 8) | (op1
.am
<< 4));
2245 op_length
= 2 + 2 * op1
.ol
;
2246 frag
= frag_more (op_length
);
2247 where
= frag
- frag_now
->fr_literal
;
2248 bfd_putl16 ((bfd_vma
) bin
, frag
);
2250 if (op1
.mode
== OP_EXP
)
2252 if (op1
.exp
.X_op
== O_constant
)
2254 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
+ 2);
2260 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2262 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3))
2263 fix_new_exp (frag_now
, where
, 2,
2264 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2266 fix_new_exp (frag_now
, where
, 2,
2267 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2271 dwarf2_emit_insn (insn_length
+ op_length
);
2275 /* CALLA instructions. */
2276 fix_emitted
= FALSE
;
2278 line
= extract_operand (line
, l1
, sizeof (l1
));
2281 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
,
2282 extended_op
, FALSE
);
2288 op_length
= 2 + 2 * op1
.ol
;
2289 frag
= frag_more (op_length
);
2290 where
= frag
- frag_now
->fr_literal
;
2298 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2299 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
2302 else if (op1
.am
== 1)
2308 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2309 BFD_RELOC_MSP430X_PCR20_CALL
);
2313 bin
|= 0x50 | op1
.reg
;
2315 else if (op1
.am
== 0)
2316 bin
|= 0x40 | op1
.reg
;
2318 else if (op1
.am
== 1)
2322 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2323 BFD_RELOC_MSP430X_ABS20_ADR_DST
);
2326 else if (op1
.am
== 2)
2327 bin
|= 0x60 | op1
.reg
;
2328 else if (op1
.am
== 3)
2329 bin
|= 0x70 | op1
.reg
;
2331 bfd_putl16 ((bfd_vma
) bin
, frag
);
2333 if (op1
.mode
== OP_EXP
)
2337 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1
.ol
);
2341 bfd_putl16 ((bfd_vma
) ZEROS
, frag
+ 2);
2344 fix_new_exp (frag_now
, where
+ 2, 2,
2345 &(op1
.exp
), FALSE
, BFD_RELOC_16
);
2348 dwarf2_emit_insn (insn_length
+ op_length
);
2356 /* [POP|PUSH]M[.A] #N, Rd */
2357 line
= extract_operand (line
, l1
, sizeof (l1
));
2358 line
= extract_operand (line
, l2
, sizeof (l2
));
2362 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
2365 parse_exp (l1
+ 1, &(op1
.exp
));
2366 if (op1
.exp
.X_op
!= O_constant
)
2368 as_bad (_("expected constant expression for first argument of %s"),
2373 if ((reg
= check_reg (l2
)) == -1)
2375 as_bad (_("expected register as second argument of %s"),
2381 frag
= frag_more (op_length
);
2382 where
= frag
- frag_now
->fr_literal
;
2383 bin
= opcode
->bin_opcode
;
2386 n
= op1
.exp
.X_add_number
;
2387 bin
|= (n
- 1) << 4;
2388 if (is_opcode ("pushm"))
2392 if (reg
- n
+ 1 < 0)
2394 as_bad (_("Too many registers popped"));
2398 /* CPU21 errata: cannot use POPM to restore the SR register. */
2399 if (target_is_430xv2 ()
2400 && (reg
- n
+ 1 < 3)
2402 && is_opcode ("popm"))
2404 as_bad (_("Cannot use POPM to restore the SR register"));
2408 bin
|= (reg
- n
+ 1);
2411 bfd_putl16 ((bfd_vma
) bin
, frag
);
2412 dwarf2_emit_insn (op_length
);
2421 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
2422 if (extended
& 0xff)
2424 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2428 line
= extract_operand (line
, l1
, sizeof (l1
));
2429 line
= extract_operand (line
, l2
, sizeof (l2
));
2433 as_bad (_("expected #n as first argument of %s"), opcode
->name
);
2436 parse_exp (l1
+ 1, &(op1
.exp
));
2437 if (op1
.exp
.X_op
!= O_constant
)
2439 as_bad (_("expected constant expression for first argument of %s"),
2443 n
= op1
.exp
.X_add_number
;
2446 as_bad (_("expected first argument of %s to be in the range 1-4"),
2451 if ((reg
= check_reg (l2
)) == -1)
2453 as_bad (_("expected register as second argument of %s"),
2458 if (target_is_430xv2 () && reg
== 0)
2460 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2465 frag
= frag_more (op_length
);
2466 where
= frag
- frag_now
->fr_literal
;
2468 bin
= opcode
->bin_opcode
;
2471 bin
|= (n
- 1) << 10;
2474 bfd_putl16 ((bfd_vma
) bin
, frag
);
2475 dwarf2_emit_insn (op_length
);
2483 /* RRUX: Synthetic unsigned right shift of a register by one bit. */
2484 if (extended
& 0xff)
2486 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2490 line
= extract_operand (line
, l1
, sizeof (l1
));
2491 if ((reg
= check_reg (l1
)) == -1)
2493 as_bad (_("expected register as argument of %s"),
2498 if (target_is_430xv2 () && reg
== 0)
2500 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2506 /* Tricky - there is no single instruction that will do this.
2507 Encode as: RRA.B rN { BIC.B #0x80, rN */
2509 frag
= frag_more (op_length
);
2510 where
= frag
- frag_now
->fr_literal
;
2512 bfd_putl16 ((bfd_vma
) bin
, frag
);
2513 dwarf2_emit_insn (2);
2515 bfd_putl16 ((bfd_vma
) bin
, frag
+ 2);
2517 bfd_putl16 ((bfd_vma
) bin
, frag
+ 4);
2518 dwarf2_emit_insn (4);
2522 /* Encode as RRUM[.A] rN. */
2523 bin
= opcode
->bin_opcode
;
2528 frag
= frag_more (op_length
);
2529 where
= frag
- frag_now
->fr_literal
;
2530 bfd_putl16 ((bfd_vma
) bin
, frag
);
2531 dwarf2_emit_insn (op_length
);
2538 bfd_boolean need_reloc
= FALSE
;
2542 /* ADDA, CMPA and SUBA address instructions. */
2543 if (extended
& 0xff)
2545 as_bad (_("repeat count cannot be used with %s"), opcode
->name
);
2549 line
= extract_operand (line
, l1
, sizeof (l1
));
2550 line
= extract_operand (line
, l2
, sizeof (l2
));
2552 bin
= opcode
->bin_opcode
;
2556 parse_exp (l1
+ 1, &(op1
.exp
));
2558 if (op1
.exp
.X_op
== O_constant
)
2560 n
= op1
.exp
.X_add_number
;
2561 if (n
> 0xfffff || n
< - (0x7ffff))
2563 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
2568 bin
|= ((n
>> 16) & 0xf) << 8;
2580 if ((n
= check_reg (l1
)) == -1)
2582 as_bad (_("expected register name or constant as first argument of %s"),
2587 bin
|= (n
<< 8) | (1 << 6);
2591 if ((reg
= check_reg (l2
)) == -1)
2593 as_bad (_("expected register as second argument of %s"),
2598 frag
= frag_more (op_length
);
2599 where
= frag
- frag_now
->fr_literal
;
2602 fix_new_exp (frag_now
, where
, 4, &(op1
.exp
), FALSE
,
2603 BFD_RELOC_MSP430X_ABS20_ADR_SRC
);
2605 bfd_putl16 ((bfd_vma
) bin
, frag
);
2607 bfd_putl16 ((bfd_vma
) (n
& 0xffff), frag
+ 2);
2608 dwarf2_emit_insn (op_length
);
2612 case 9: /* MOVA, BRA, RETA. */
2614 bin
= opcode
->bin_opcode
;
2616 if (is_opcode ("reta"))
2618 /* The RETA instruction does not take any arguments.
2619 The implicit first argument is @SP+.
2620 The implicit second argument is PC. */
2630 line
= extract_operand (line
, l1
, sizeof (l1
));
2631 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
2632 &imm_op
, extended_op
, FALSE
);
2634 if (is_opcode ("bra"))
2636 /* This is the BRA synthetic instruction.
2637 The second argument is always PC. */
2643 line
= extract_operand (line
, l2
, sizeof (l2
));
2644 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
,
2649 break; /* Error occurred. All warnings were done before. */
2652 /* Only a restricted subset of the normal MSP430 addressing modes
2653 are supported here, so check for the ones that are allowed. */
2654 if ((op_length
= try_encode_mova (imm_op
, bin
, & op1
, & op2
,
2655 & error_message
)) == 0)
2657 as_bad (error_message
, opcode
->name
);
2660 dwarf2_emit_insn (op_length
);
2664 line
= extract_operand (line
, l1
, sizeof l1
);
2665 /* The RPT instruction only accepted immediates and registers. */
2668 parse_exp (l1
+ 1, &(op1
.exp
));
2669 if (op1
.exp
.X_op
!= O_constant
)
2671 as_bad (_("expected constant value as argument to RPT"));
2674 if (op1
.exp
.X_add_number
< 1
2675 || op1
.exp
.X_add_number
> (1 << 4))
2677 as_bad (_("expected constant in the range 2..16"));
2681 /* We silently accept and ignore a repeat count of 1. */
2682 if (op1
.exp
.X_add_number
> 1)
2683 repeat_count
= op1
.exp
.X_add_number
;
2689 if ((reg
= check_reg (l1
)) != -1)
2692 as_warn (_("PC used as an argument to RPT"));
2694 repeat_count
= - reg
;
2698 as_bad (_("expected constant or register name as argument to RPT insn"));
2705 as_bad (_("Illegal emulated instruction "));
2710 case 1: /* Format 1, double operand. */
2711 line
= extract_operand (line
, l1
, sizeof (l1
));
2712 line
= extract_operand (line
, l2
, sizeof (l2
));
2713 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
, &imm_op
, extended_op
, TRUE
);
2714 res
+= msp430_dstoperand (&op2
, l2
, opcode
->bin_opcode
, extended_op
, TRUE
);
2717 break; /* Error occurred. All warnings were done before. */
2720 && is_opcode ("movx")
2722 && msp430_enable_relax
)
2724 /* This is the MOVX.A instruction. See if we can convert
2725 it into the MOVA instruction instead. This saves 2 bytes. */
2726 if ((op_length
= try_encode_mova (imm_op
, 0x0000, & op1
, & op2
,
2729 dwarf2_emit_insn (op_length
);
2734 bin
|= (op2
.reg
| (op1
.reg
<< 8) | (op1
.am
<< 4) | (op2
.am
<< 7));
2736 if ( (is_opcode ("bic") && bin
== 0xc232)
2737 || (is_opcode ("bis") && bin
== 0xd232)
2738 || (is_opcode ("mov") && op2
.mode
== OP_REG
&& op2
.reg
== 2))
2742 if (warn_interrupt_nops
)
2744 if (gen_interrupt_nops
)
2745 as_warn (_("NOP inserted between two instructions that change interrupt state"));
2747 as_warn (_("a NOP might be needed here because of successive changes in interrupt state"));
2750 if (gen_interrupt_nops
)
2752 /* Emit a NOP between interrupt enable/disable.
2753 See 1.3.4.1 of the MSP430x5xx User Guide. */
2755 frag
= frag_more (2);
2756 bfd_putl16 ((bfd_vma
) 0x4303 /* NOP */, frag
);
2760 nop_check_needed
= TRUE
;
2763 /* Compute the entire length of the instruction in bytes. */
2764 op_length
= (extended_op
? 2 : 0) /* The extension word. */
2765 + 2 /* The opcode */
2766 + (2 * op1
.ol
) /* The first operand. */
2767 + (2 * op2
.ol
); /* The second operand. */
2769 insn_length
+= op_length
;
2770 frag
= frag_more (op_length
);
2771 where
= frag
- frag_now
->fr_literal
;
2776 extended
|= BYTE_OPERATION
;
2778 if ((op1
.ol
!= 0 || op2
.ol
!= 0) && ((extended
& 0xf) != 0))
2780 as_bad (_("repeat instruction used with non-register mode instruction"));
2784 /* If necessary, emit a reloc to update the extension word. */
2785 if (op1
.mode
== OP_EXP
)
2787 if (op1
.exp
.X_op
== O_constant
)
2788 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2790 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2791 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2792 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2794 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2795 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2798 if (op2
.mode
== OP_EXP
)
2800 if (op2
.exp
.X_op
== O_constant
)
2801 extended
|= (op2
.exp
.X_add_number
>> 16) & 0xf;
2803 else if (op1
.mode
== OP_EXP
)
2804 fix_new_exp (frag_now
, where
, 8, &(op2
.exp
), FALSE
,
2805 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_ODST
2806 : BFD_RELOC_MSP430X_PCR20_EXT_ODST
);
2809 fix_new_exp (frag_now
, where
, 6, &(op2
.exp
), FALSE
,
2810 op2
.reg
? BFD_RELOC_MSP430X_ABS20_EXT_DST
2811 : BFD_RELOC_MSP430X_PCR20_EXT_DST
);
2814 /* Emit the extension word. */
2815 bfd_putl16 (extended
, frag
);
2820 bfd_putl16 ((bfd_vma
) bin
, frag
);
2824 if (op1
.mode
== OP_EXP
)
2826 if (op1
.exp
.X_op
== O_constant
)
2828 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2832 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2836 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2837 fix_new_exp (frag_now
, where
, 2,
2838 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2840 fix_new_exp (frag_now
, where
, 2,
2841 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2849 if (op2
.mode
== OP_EXP
)
2851 if (op2
.exp
.X_op
== O_constant
)
2853 bfd_putl16 (op2
.exp
.X_add_number
& 0xffff, frag
);
2857 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2861 if (op2
.reg
) /* Not PC relative. */
2862 fix_new_exp (frag_now
, where
, 2,
2863 &(op2
.exp
), FALSE
, CHECK_RELOC_MSP430 (op2
));
2865 fix_new_exp (frag_now
, where
, 2,
2866 &(op2
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2871 dwarf2_emit_insn (insn_length
);
2874 case 2: /* Single-operand mostly instr. */
2875 if (opcode
->insn_opnumb
== 0)
2877 /* reti instruction. */
2879 frag
= frag_more (2);
2880 bfd_putl16 ((bfd_vma
) bin
, frag
);
2881 dwarf2_emit_insn (insn_length
);
2885 line
= extract_operand (line
, l1
, sizeof (l1
));
2886 res
= msp430_srcoperand (&op1
, l1
, opcode
->bin_opcode
,
2887 &imm_op
, extended_op
, TRUE
);
2889 break; /* Error in operand. */
2891 if (target_is_430xv2 ()
2892 && op1
.mode
== OP_REG
2894 && (is_opcode ("rrax")
2895 || is_opcode ("rrcx")
2896 || is_opcode ("rra")
2897 || is_opcode ("rrc")))
2899 as_bad (_("%s: attempt to rotate the PC register"), opcode
->name
);
2903 insn_length
= (extended_op
? 2 : 0) + 2 + (op1
.ol
* 2);
2904 frag
= frag_more (insn_length
);
2905 where
= frag
- frag_now
->fr_literal
;
2909 if (is_opcode ("swpbx") || is_opcode ("sxtx"))
2911 /* These two instructions use a special
2912 encoding of the A/L and B/W bits. */
2913 bin
&= ~ BYTE_OPERATION
;
2917 as_bad (_("%s instruction does not accept a .b suffix"),
2922 extended
|= BYTE_OPERATION
;
2925 extended
|= BYTE_OPERATION
;
2927 if (op1
.ol
!= 0 && ((extended
& 0xf) != 0))
2929 as_bad (_("repeat instruction used with non-register mode instruction"));
2933 if (op1
.mode
== OP_EXP
)
2935 if (op1
.exp
.X_op
== O_constant
)
2936 extended
|= ((op1
.exp
.X_add_number
>> 16) & 0xf) << 7;
2938 else if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2939 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2940 BFD_RELOC_MSP430X_ABS20_EXT_SRC
);
2942 fix_new_exp (frag_now
, where
, 6, &(op1
.exp
), FALSE
,
2943 BFD_RELOC_MSP430X_PCR20_EXT_SRC
);
2946 /* Emit the extension word. */
2947 bfd_putl16 (extended
, frag
);
2952 bin
|= op1
.reg
| (op1
.am
<< 4);
2953 bfd_putl16 ((bfd_vma
) bin
, frag
);
2957 if (op1
.mode
== OP_EXP
)
2959 if (op1
.exp
.X_op
== O_constant
)
2961 bfd_putl16 (op1
.exp
.X_add_number
& 0xffff, frag
);
2965 bfd_putl16 ((bfd_vma
) ZEROS
, frag
);
2969 if (op1
.reg
|| (op1
.reg
== 0 && op1
.am
== 3)) /* Not PC relative. */
2970 fix_new_exp (frag_now
, where
, 2,
2971 &(op1
.exp
), FALSE
, CHECK_RELOC_MSP430 (op1
));
2973 fix_new_exp (frag_now
, where
, 2,
2974 &(op1
.exp
), TRUE
, CHECK_RELOC_MSP430_PCREL
);
2979 dwarf2_emit_insn (insn_length
);
2982 case 3: /* Conditional jumps instructions. */
2983 line
= extract_operand (line
, l1
, sizeof (l1
));
2984 /* l1 is a label. */
2993 parse_exp (m
, &exp
);
2995 /* In order to handle something like:
2999 jz 4 ; skip next 4 bytes
3002 nop ; will jump here if r5 positive or zero
3004 jCOND -n ;assumes jump n bytes backward:
3014 jCOND $n ; jump from PC in either direction. */
3016 if (exp
.X_op
== O_constant
)
3018 int x
= exp
.X_add_number
;
3022 as_warn (_("Even number required. Rounded to %d"), x
+ 1);
3026 if ((*l1
== '$' && x
> 0) || x
< 0)
3031 if (x
> 512 || x
< -511)
3033 as_bad (_("Wrong displacement %d"), x
<< 1);
3038 frag
= frag_more (2); /* Instr size is 1 word. */
3041 bfd_putl16 ((bfd_vma
) bin
, frag
);
3043 else if (exp
.X_op
== O_symbol
&& *l1
!= '$')
3046 frag
= frag_more (2); /* Instr size is 1 word. */
3047 where
= frag
- frag_now
->fr_literal
;
3048 fix_new_exp (frag_now
, where
, 2,
3049 &exp
, TRUE
, BFD_RELOC_MSP430_10_PCREL
);
3051 bfd_putl16 ((bfd_vma
) bin
, frag
);
3053 else if (*l1
== '$')
3055 as_bad (_("instruction requires label sans '$'"));
3059 ("instruction requires label or value in range -511:512"));
3060 dwarf2_emit_insn (insn_length
);
3065 as_bad (_("instruction requires label"));
3070 case 4: /* Extended jumps. */
3071 if (!msp430_enable_polys
)
3073 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3077 line
= extract_operand (line
, l1
, sizeof (l1
));
3083 /* Ignore absolute addressing. make it PC relative anyway. */
3084 if (*m
== '#' || *m
== '$')
3087 parse_exp (m
, & exp
);
3088 if (exp
.X_op
== O_symbol
)
3090 /* Relaxation required. */
3091 struct rcodes_s rc
= msp430_rcodes
[opcode
->insn_opnumb
];
3093 if (target_is_430x ())
3094 rc
= msp430x_rcodes
[opcode
->insn_opnumb
];
3096 /* The parameter to dwarf2_emit_insn is actually the offset to
3097 the start of the insn from the fix piece of instruction that
3098 was emitted. Since next fragments may have variable size we
3099 tie debug info to the beginning of the instruction. */
3101 frag
= frag_more (8);
3102 dwarf2_emit_insn (0);
3103 bfd_putl16 ((bfd_vma
) rc
.sop
, frag
);
3104 frag
= frag_variant (rs_machine_dependent
, 8, 2,
3106 ENCODE_RELAX (rc
.lpos
, STATE_BITS10
),
3108 0, /* Offset is zero if jump dist less than 1K. */
3114 as_bad (_("instruction requires label"));
3117 case 5: /* Emulated extended branches. */
3118 if (!msp430_enable_polys
)
3120 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
3123 line
= extract_operand (line
, l1
, sizeof (l1
));
3129 /* Ignore absolute addressing. make it PC relative anyway. */
3130 if (*m
== '#' || *m
== '$')
3133 parse_exp (m
, & exp
);
3134 if (exp
.X_op
== O_symbol
)
3136 /* Relaxation required. */
3137 struct hcodes_s hc
= msp430_hcodes
[opcode
->insn_opnumb
];
3139 if (target_is_430x ())
3140 hc
= msp430x_hcodes
[opcode
->insn_opnumb
];
3143 frag
= frag_more (8);
3144 dwarf2_emit_insn (0);
3145 bfd_putl16 ((bfd_vma
) hc
.op0
, frag
);
3146 bfd_putl16 ((bfd_vma
) hc
.op1
, frag
+2);
3148 frag
= frag_variant (rs_machine_dependent
, 8, 2,
3149 ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
), /* Wild guess. */
3151 0, /* Offset is zero if jump dist less than 1K. */
3157 as_bad (_("instruction requires label"));
3161 as_bad (_("Illegal instruction or not implemented opcode."));
3164 input_line_pointer
= line
;
3165 check_for_nop
= nop_check_needed
;
3170 md_assemble (char * str
)
3172 struct msp430_opcode_s
* opcode
;
3176 str
= skip_space (str
); /* Skip leading spaces. */
3177 str
= extract_cmd (str
, cmd
, sizeof (cmd
) - 1);
3181 char a
= TOLOWER (cmd
[i
]);
3188 as_bad (_("can't find opcode "));
3192 opcode
= (struct msp430_opcode_s
*) hash_find (msp430_hash
, cmd
);
3196 as_bad (_("unknown opcode `%s'"), cmd
);
3201 char *__t
= input_line_pointer
;
3203 msp430_operands (opcode
, str
);
3204 input_line_pointer
= __t
;
3208 /* GAS will call this function for each section at the end of the assembly,
3209 to permit the CPU backend to adjust the alignment of a section. */
3212 md_section_align (asection
* seg
, valueT addr
)
3214 int align
= bfd_get_section_alignment (stdoutput
, seg
);
3216 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
3219 /* If you define this macro, it should return the offset between the
3220 address of a PC relative fixup and the position from which the PC
3221 relative adjustment should be made. On many processors, the base
3222 of a PC relative instruction is the next instruction, so this
3223 macro would return the length of an instruction. */
3226 md_pcrel_from_section (fixS
* fixp
, segT sec
)
3228 if (fixp
->fx_addsy
!= (symbolS
*) NULL
3229 && (!S_IS_DEFINED (fixp
->fx_addsy
)
3230 || (S_GET_SEGMENT (fixp
->fx_addsy
) != sec
)))
3233 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3236 /* Replaces standard TC_FORCE_RELOCATION_LOCAL.
3237 Now it handles the situation when relocations
3238 have to be passed to linker. */
3240 msp430_force_relocation_local (fixS
*fixp
)
3242 if (fixp
->fx_r_type
== BFD_RELOC_MSP430_10_PCREL
)
3246 if (msp430_enable_polys
3247 && !msp430_enable_relax
)
3250 return (!fixp
->fx_pcrel
3251 || generic_force_reloc (fixp
));
3255 /* GAS will call this for each fixup. It should store the correct
3256 value in the object file. */
3258 md_apply_fix (fixS
* fixp
, valueT
* valuep
, segT seg
)
3260 unsigned char * where
;
3264 if (fixp
->fx_addsy
== (symbolS
*) NULL
)
3269 else if (fixp
->fx_pcrel
)
3271 segT s
= S_GET_SEGMENT (fixp
->fx_addsy
);
3273 if (fixp
->fx_addsy
&& (s
== seg
|| s
== absolute_section
))
3275 /* FIXME: We can appear here only in case if we perform a pc
3276 relative jump to the label which is i) global, ii) locally
3277 defined or this is a jump to an absolute symbol.
3278 If this is an absolute symbol -- everything is OK.
3279 If this is a global label, we've got a symbol value defined
3281 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
3282 from this section start
3283 2. *valuep will contain the real offset from jump insn to the
3285 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
3286 will be incorrect. Therefore remove s_get_value. */
3287 value
= /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep
;
3295 value
= fixp
->fx_offset
;
3297 if (fixp
->fx_subsy
!= (symbolS
*) NULL
)
3299 if (S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
3301 value
-= S_GET_VALUE (fixp
->fx_subsy
);
3307 fixp
->fx_no_overflow
= 1;
3309 /* If polymorphs are enabled and relax disabled.
3310 do not kill any relocs and pass them to linker. */
3311 if (msp430_enable_polys
3312 && !msp430_enable_relax
)
3314 if (!fixp
->fx_addsy
|| (fixp
->fx_addsy
3315 && S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
))
3316 fixp
->fx_done
= 1; /* It is ok to kill 'abs' reloc. */
3323 /* Fetch the instruction, insert the fully resolved operand
3324 value, and stuff the instruction back again. */
3325 where
= (unsigned char *) fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
;
3327 insn
= bfd_getl16 (where
);
3329 switch (fixp
->fx_r_type
)
3331 case BFD_RELOC_MSP430_10_PCREL
:
3333 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3334 _("odd address operand: %ld"), value
);
3336 /* Jumps are in words. */
3338 --value
; /* Correct PC. */
3340 if (value
< -512 || value
> 511)
3341 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3342 _("operand out of range: %ld"), value
);
3344 value
&= 0x3ff; /* get rid of extended sign */
3345 bfd_putl16 ((bfd_vma
) (value
| insn
), where
);
3348 case BFD_RELOC_MSP430X_PCR16
:
3349 case BFD_RELOC_MSP430_RL_PCREL
:
3350 case BFD_RELOC_MSP430_16_PCREL
:
3352 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3353 _("odd address operand: %ld"), value
);
3356 case BFD_RELOC_MSP430_16_PCREL_BYTE
:
3357 /* Nothing to be corrected here. */
3358 if (value
< -32768 || value
> 65536)
3359 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3360 _("operand out of range: %ld"), value
);
3363 case BFD_RELOC_MSP430X_ABS16
:
3364 case BFD_RELOC_MSP430_16
:
3366 case BFD_RELOC_MSP430_16_BYTE
:
3367 value
&= 0xffff; /* Get rid of extended sign. */
3368 bfd_putl16 ((bfd_vma
) value
, where
);
3371 case BFD_RELOC_MSP430_ABS_HI16
:
3373 value
&= 0xffff; /* Get rid of extended sign. */
3374 bfd_putl16 ((bfd_vma
) value
, where
);
3378 bfd_putl16 ((bfd_vma
) value
, where
);
3381 case BFD_RELOC_MSP430_ABS8
:
3383 bfd_put_8 (NULL
, (bfd_vma
) value
, where
);
3386 case BFD_RELOC_MSP430X_ABS20_EXT_SRC
:
3387 case BFD_RELOC_MSP430X_PCR20_EXT_SRC
:
3388 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
3390 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 7) | insn
), where
);
3393 case BFD_RELOC_MSP430X_ABS20_ADR_SRC
:
3394 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3396 bfd_putl16 ((bfd_vma
) (((value
& 0xf) << 8) | insn
), where
);
3399 case BFD_RELOC_MSP430X_ABS20_EXT_ODST
:
3400 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
3402 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3405 case BFD_RELOC_MSP430X_PCR20_CALL
:
3406 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3408 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3411 case BFD_RELOC_MSP430X_ABS20_EXT_DST
:
3412 case BFD_RELOC_MSP430X_PCR20_EXT_DST
:
3413 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 4);
3415 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3418 case BFD_RELOC_MSP430X_PCR20_EXT_ODST
:
3419 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 6);
3421 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3424 case BFD_RELOC_MSP430X_ABS20_ADR_DST
:
3425 bfd_putl16 ((bfd_vma
) (value
& 0xffff), where
+ 2);
3427 bfd_putl16 ((bfd_vma
) ((value
& 0xf) | insn
), where
);
3431 as_fatal (_("line %d: unknown relocation type: 0x%x"),
3432 fixp
->fx_line
, fixp
->fx_r_type
);
3438 fixp
->fx_addnumber
= value
;
3443 S_IS_GAS_LOCAL (symbolS
* s
)
3450 name
= S_GET_NAME (s
);
3451 len
= strlen (name
) - 1;
3453 return name
[len
] == 1 || name
[len
] == 2;
3456 /* GAS will call this to generate a reloc, passing the resulting reloc
3457 to `bfd_install_relocation'. This currently works poorly, as
3458 `bfd_install_relocation' often does the wrong thing, and instances of
3459 `tc_gen_reloc' have been written to work around the problems, which
3460 in turns makes it difficult to fix `bfd_install_relocation'. */
3462 /* If while processing a fixup, a reloc really needs to be created
3463 then it is done here. */
3466 tc_gen_reloc (asection
* seg ATTRIBUTE_UNUSED
, fixS
* fixp
)
3468 static arelent
* no_relocs
= NULL
;
3469 static arelent
* relocs
[MAX_RELOC_EXPANSION
+ 1];
3472 reloc
= xmalloc (sizeof (arelent
));
3473 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3474 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3476 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
3478 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3479 _("reloc %d not supported by object file format"),
3480 (int) fixp
->fx_r_type
);
3489 && S_GET_SEGMENT (fixp
->fx_subsy
) == absolute_section
)
3491 fixp
->fx_offset
-= S_GET_VALUE (fixp
->fx_subsy
);
3492 fixp
->fx_subsy
= NULL
;
3495 if (fixp
->fx_addsy
&& fixp
->fx_subsy
)
3497 asection
*asec
, *ssec
;
3499 asec
= S_GET_SEGMENT (fixp
->fx_addsy
);
3500 ssec
= S_GET_SEGMENT (fixp
->fx_subsy
);
3502 /* If we have a difference between two different, non-absolute symbols
3503 we must generate two relocs (one for each symbol) and allow the
3504 linker to resolve them - relaxation may change the distances between
3505 symbols, even local symbols defined in the same section.
3507 Unfortunately we cannot do this with assembler generated local labels
3508 because there can be multiple incarnations of the same label, with
3509 exactly the same name, in any given section and the linker will have
3510 no way to identify the correct one. Instead we just have to hope
3511 that no relaxtion will occur between the local label and the other
3512 symbol in the expression.
3514 Similarly we have to compute differences between symbols in the .eh_frame
3515 section as the linker is not smart enough to apply relocations there
3516 before attempting to process it. */
3517 if ((ssec
!= absolute_section
|| asec
!= absolute_section
)
3518 && (fixp
->fx_addsy
!= fixp
->fx_subsy
)
3519 && strcmp (ssec
->name
, ".eh_frame") != 0
3520 && ! S_IS_GAS_LOCAL (fixp
->fx_addsy
)
3521 && ! S_IS_GAS_LOCAL (fixp
->fx_subsy
))
3523 arelent
* reloc2
= xmalloc (sizeof * reloc
);
3528 reloc2
->address
= reloc
->address
;
3529 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
,
3530 BFD_RELOC_MSP430_SYM_DIFF
);
3531 reloc2
->addend
= - S_GET_VALUE (fixp
->fx_subsy
);
3533 if (ssec
== absolute_section
)
3534 reloc2
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
3537 reloc2
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3538 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_subsy
);
3541 reloc
->addend
= fixp
->fx_offset
;
3542 if (asec
== absolute_section
)
3544 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
3545 reloc
->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
3549 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3550 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3559 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
3561 reloc
->addend
= (S_GET_VALUE (fixp
->fx_addsy
)
3562 - S_GET_VALUE (fixp
->fx_subsy
) + fixp
->fx_offset
);
3564 switch (fixp
->fx_r_type
)
3567 md_number_to_chars (fixpos
, reloc
->addend
, 1);
3571 md_number_to_chars (fixpos
, reloc
->addend
, 2);
3575 md_number_to_chars (fixpos
, reloc
->addend
, 3);
3579 md_number_to_chars (fixpos
, reloc
->addend
, 4);
3584 = (asymbol
**) bfd_abs_section_ptr
->symbol_ptr_ptr
;
3595 if (fixp
->fx_r_type
== BFD_RELOC_MSP430X_ABS16
3596 && S_GET_SEGMENT (fixp
->fx_addsy
) == absolute_section
)
3598 bfd_vma amount
= S_GET_VALUE (fixp
->fx_addsy
);
3599 char *fixpos
= fixp
->fx_where
+ fixp
->fx_frag
->fr_literal
;
3601 md_number_to_chars (fixpos
, amount
, 2);
3606 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3607 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3608 reloc
->addend
= fixp
->fx_offset
;
3610 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3611 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3612 reloc
->address
= fixp
->fx_offset
;
3619 md_estimate_size_before_relax (fragS
* fragP ATTRIBUTE_UNUSED
,
3620 asection
* segment_type ATTRIBUTE_UNUSED
)
3622 if (fragP
->fr_symbol
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment_type
)
3624 /* This is a jump -> pcrel mode. Nothing to do much here.
3625 Return value == 2. */
3627 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_BITS10
);
3629 else if (fragP
->fr_symbol
)
3631 /* Its got a segment, but its not ours. Even if fr_symbol is in
3632 an absolute segment, we don't know a displacement until we link
3633 object files. So it will always be long. This also applies to
3634 labels in a subsegment of current. Liker may relax it to short
3635 jump later. Return value == 8. */
3637 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_WORD
);
3641 /* We know the abs value. may be it is a jump to fixed address.
3642 Impossible in our case, cause all constants already handled. */
3644 ENCODE_RELAX (RELAX_LEN (fragP
->fr_subtype
), STATE_UNDEF
);
3647 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
3651 md_convert_frag (bfd
* abfd ATTRIBUTE_UNUSED
,
3652 asection
* sec ATTRIBUTE_UNUSED
,
3658 struct rcodes_s
* cc
= NULL
;
3659 struct hcodes_s
* hc
= NULL
;
3661 switch (fragP
->fr_subtype
)
3663 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_BITS10
):
3664 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_BITS10
):
3665 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_BITS10
):
3666 /* We do not have to convert anything here.
3667 Just apply a fix. */
3668 rela
= BFD_RELOC_MSP430_10_PCREL
;
3671 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_WORD
):
3672 case ENCODE_RELAX (STATE_UNCOND_BRANCH
, STATE_UNDEF
):
3673 /* Convert uncond branch jmp lab -> br lab. */
3674 if (target_is_430x ())
3675 cc
= msp430x_rcodes
+ 7;
3677 cc
= msp430_rcodes
+ 7;
3678 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3679 bfd_putl16 (cc
->lop0
, where
);
3680 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3684 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_WORD
):
3685 case ENCODE_RELAX (STATE_SIMPLE_BRANCH
, STATE_UNDEF
):
3687 /* Other simple branches. */
3688 int insn
= bfd_getl16 (fragP
->fr_opcode
);
3691 /* Find actual instruction. */
3692 if (target_is_430x ())
3694 for (i
= 0; i
< 7 && !cc
; i
++)
3695 if (msp430x_rcodes
[i
].sop
== insn
)
3696 cc
= msp430x_rcodes
+ i
;
3700 for (i
= 0; i
< 7 && !cc
; i
++)
3701 if (msp430_rcodes
[i
].sop
== insn
)
3702 cc
= & msp430_rcodes
[i
];
3705 if (!cc
|| !cc
->name
)
3706 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
3707 __FUNCTION__
, (long) insn
);
3708 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3709 bfd_putl16 (cc
->lop0
, where
);
3710 bfd_putl16 (cc
->lop1
, where
+ 2);
3711 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3716 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_WORD
):
3717 case ENCODE_RELAX (STATE_NOOV_BRANCH
, STATE_UNDEF
):
3718 if (target_is_430x ())
3719 cc
= msp430x_rcodes
+ 6;
3721 cc
= msp430_rcodes
+ 6;
3722 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3723 bfd_putl16 (cc
->lop0
, where
);
3724 bfd_putl16 (cc
->lop1
, where
+ 2);
3725 bfd_putl16 (cc
->lop2
, where
+ 4);
3726 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3730 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_BITS10
):
3732 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
3735 if (target_is_430x ())
3737 for (i
= 0; i
< 4 && !hc
; i
++)
3738 if (msp430x_hcodes
[i
].op1
== insn
)
3739 hc
= msp430x_hcodes
+ i
;
3743 for (i
= 0; i
< 4 && !hc
; i
++)
3744 if (msp430_hcodes
[i
].op1
== insn
)
3745 hc
= &msp430_hcodes
[i
];
3747 if (!hc
|| !hc
->name
)
3748 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3749 __FUNCTION__
, (long) insn
);
3750 rela
= BFD_RELOC_MSP430_10_PCREL
;
3751 /* Apply a fix for a first label if necessary.
3752 another fix will be applied to the next word of insn anyway. */
3754 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3755 fragP
->fr_offset
, TRUE
, rela
);
3761 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_WORD
):
3762 case ENCODE_RELAX (STATE_EMUL_BRANCH
, STATE_UNDEF
):
3764 int insn
= bfd_getl16 (fragP
->fr_opcode
+ 2);
3767 if (target_is_430x ())
3769 for (i
= 0; i
< 4 && !hc
; i
++)
3770 if (msp430x_hcodes
[i
].op1
== insn
)
3771 hc
= msp430x_hcodes
+ i
;
3775 for (i
= 0; i
< 4 && !hc
; i
++)
3776 if (msp430_hcodes
[i
].op1
== insn
)
3777 hc
= & msp430_hcodes
[i
];
3779 if (!hc
|| !hc
->name
)
3780 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
3781 __FUNCTION__
, (long) insn
);
3782 rela
= BFD_RELOC_MSP430_RL_PCREL
;
3783 where
= fragP
->fr_literal
+ fragP
->fr_fix
;
3784 bfd_putl16 (hc
->lop0
, where
);
3785 bfd_putl16 (hc
->lop1
, where
+ 2);
3786 bfd_putl16 (hc
->lop2
, where
+ 4);
3792 as_fatal (_("internal inconsistency problem in %s: %lx"),
3793 __FUNCTION__
, (long) fragP
->fr_subtype
);
3797 /* Now apply fix. */
3798 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
3799 fragP
->fr_offset
, TRUE
, rela
);
3800 /* Just fixed 2 bytes. */
3804 /* Relax fragment. Mostly stolen from hc11 and mcore
3805 which arches I think I know. */
3808 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED
, fragS
* fragP
,
3809 long stretch ATTRIBUTE_UNUSED
)
3814 const relax_typeS
*this_type
;
3815 const relax_typeS
*start_type
;
3816 relax_substateT next_state
;
3817 relax_substateT this_state
;
3818 const relax_typeS
*table
= md_relax_table
;
3820 /* Nothing to be done if the frag has already max size. */
3821 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_UNDEF
3822 || RELAX_STATE (fragP
->fr_subtype
) == STATE_WORD
)
3825 if (RELAX_STATE (fragP
->fr_subtype
) == STATE_BITS10
)
3827 symbolP
= fragP
->fr_symbol
;
3828 if (symbol_resolved_p (symbolP
))
3829 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
3831 /* We know the offset. calculate a distance. */
3832 aim
= S_GET_VALUE (symbolP
) - fragP
->fr_address
- fragP
->fr_fix
;
3835 if (!msp430_enable_relax
)
3837 /* Relaxation is not enabled. So, make all jump as long ones
3838 by setting 'aim' to quite high value. */
3842 this_state
= fragP
->fr_subtype
;
3843 start_type
= this_type
= table
+ this_state
;
3847 /* Look backwards. */
3848 for (next_state
= this_type
->rlx_more
; next_state
;)
3849 if (aim
>= this_type
->rlx_backward
|| !this_type
->rlx_backward
)
3853 /* Grow to next state. */
3854 this_state
= next_state
;
3855 this_type
= table
+ this_state
;
3856 next_state
= this_type
->rlx_more
;
3861 /* Look forwards. */
3862 for (next_state
= this_type
->rlx_more
; next_state
;)
3863 if (aim
<= this_type
->rlx_forward
|| !this_type
->rlx_forward
)
3867 /* Grow to next state. */
3868 this_state
= next_state
;
3869 this_type
= table
+ this_state
;
3870 next_state
= this_type
->rlx_more
;
3874 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
3876 fragP
->fr_subtype
= this_state
;
3880 /* Return FALSE if the fixup in fixp should be left alone and not
3881 adjusted. We return FALSE here so that linker relaxation will
3885 msp430_fix_adjustable (struct fix
*fixp ATTRIBUTE_UNUSED
)
3887 /* If the symbol is in a non-code section then it should be OK. */
3889 && ((S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_CODE
) == 0))
3895 /* Set the contents of the .MSP430.attributes section. */
3898 msp430_md_end (void)
3900 if (check_for_nop
== TRUE
&& warn_interrupt_nops
)
3901 as_warn ("assembly finished with the last instruction changing interrupt state - a NOP might be needed");
3903 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_ISA
,
3904 target_is_430x () ? 2 : 1);
3906 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Code_Model
,
3907 large_model
? 2 : 1);
3909 bfd_elf_add_proc_attr_int (stdoutput
, OFBA_MSPABI_Tag_Data_Model
,
3910 large_model
? 2 : 1);
3913 /* Returns FALSE if there is a msp430 specific reason why the
3914 subtraction of two same-section symbols cannot be computed by
3918 msp430_allow_local_subtract (expressionS
* left
,
3919 expressionS
* right
,
3922 /* If the symbols are not in a code section then they are OK. */
3923 if ((section
->flags
& SEC_CODE
) == 0)
3926 if (S_IS_GAS_LOCAL (left
->X_add_symbol
) || S_IS_GAS_LOCAL (right
->X_add_symbol
))
3929 if (left
->X_add_symbol
== right
->X_add_symbol
)
3932 /* We have to assume that there may be instructions between the
3933 two symbols and that relaxation may increase the distance between