projects / deliverable / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Port gas/config/* to str_htab.
[deliverable/binutils-gdb.git] / gas / config / tc-msp430.c
1 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
2
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
4 Contributed by Dmitry Diky <diwil@mail.ru>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "as.h"
24 #include <limits.h>
25 #include "subsegs.h"
26 #include "opcode/msp430.h"
27 #include "safe-ctype.h"
28 #include "dwarf2dbg.h"
29 #include "elf/msp430.h"
30 #include "libiberty.h"
31
32 /* We will disable polymorphs by default because it is dangerous.
33 The potential problem here is the following: assume we got the
34 following code:
35
36 jump .l1
37 nop
38 jump subroutine ; external symbol
39 .l1:
40 nop
41 ret
42
43 In case of assembly time relaxation we'll get:
44 0: jmp .l1 <.text +0x08> (reloc deleted)
45 2: nop
46 4: br subroutine
47 .l1:
48 8: nop
49 10: ret
50
51 If the 'subroutine' is within +-1024 bytes range then linker
52 will produce:
53 0: jmp .text +0x08
54 2: nop
55 4: jmp subroutine
56 .l1:
57 6: nop
58 8: ret ; 'jmp .text +0x08' will land here. WRONG!!!
59
60 The workaround is the following:
61 1. Declare global var enable_polymorphs which set to 1 via option -mp.
62 2. Declare global var enable_relax which set to 1 via option -mQ.
63
64 If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
65 do not delete any relocs and leave them for linker.
66
67 If relax is enabled, relax at assembly time and kill relocs as necessary. */
68
69 int msp430_enable_relax;
70 int msp430_enable_polys;
71
72 /* GCC uses the some condition codes which we'll
73 implement as new polymorph instructions.
74
75 COND EXPL SHORT JUMP LONG JUMP
76 ===============================================
77 eq == jeq jne +4; br lab
78 ne != jne jeq +4; br lab
79
80 ltn honours no-overflow flag
81 ltn < jn jn +2; jmp +4; br lab
82
83 lt < jl jge +4; br lab
84 ltu < jlo lhs +4; br lab
85 le <= see below
86 leu <= see below
87
88 gt > see below
89 gtu > see below
90 ge >= jge jl +4; br lab
91 geu >= jhs jlo +4; br lab
92 ===============================================
93
94 Therefore, new opcodes are (BranchEQ -> beq; and so on...)
95 beq,bne,blt,bltn,bltu,bge,bgeu
96 'u' means unsigned compares
97
98 Also, we add 'jump' instruction:
99 jump UNCOND -> jmp br lab
100
101 They will have fmt == 4, and insn_opnumb == number of instruction. */
102
103 struct rcodes_s
104 {
105 const char * name;
106 int index; /* Corresponding insn_opnumb. */
107 int sop; /* Opcode if jump length is short. */
108 long lpos; /* Label position. */
109 long lop0; /* Opcode 1 _word_ (16 bits). */
110 long lop1; /* Opcode second word. */
111 long lop2; /* Opcode third word. */
112 };
113
114 #define MSP430_RLC(n,i,sop,o1) \
115 {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
116
117 static struct rcodes_s msp430_rcodes[] =
118 {
119 MSP430_RLC (beq, 0, 0x2400, 0x2000),
120 MSP430_RLC (bne, 1, 0x2000, 0x2400),
121 MSP430_RLC (blt, 2, 0x3800, 0x3400),
122 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
123 MSP430_RLC (bge, 4, 0x3400, 0x3800),
124 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
125 {"bltn", 6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
126 {"jump", 7, 0x3c00, 1, 0x4010, 0, 0},
127 {0,0,0,0,0,0,0}
128 };
129
130 #undef MSP430_RLC
131 #define MSP430_RLC(n,i,sop,o1) \
132 {#n, i, sop, 2, (o1 + 2), 0x0030, 0}
133
134 static struct rcodes_s msp430x_rcodes[] =
135 {
136 MSP430_RLC (beq, 0, 0x2400, 0x2000),
137 MSP430_RLC (bne, 1, 0x2000, 0x2400),
138 MSP430_RLC (blt, 2, 0x3800, 0x3400),
139 MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
140 MSP430_RLC (bge, 4, 0x3400, 0x3800),
141 MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
142 {"bltn", 6, 0x3000, 3, 0x0030 + 1, 0x3c00 + 2, 0x3000},
143 {"jump", 7, 0x3c00, 1, 0x0030, 0, 0},
144 {0,0,0,0,0,0,0}
145 };
146 #undef MSP430_RLC
147
148 /* More difficult than above and they have format 5.
149
150 COND EXPL SHORT LONG
151 =================================================================
152 gt > jeq +2; jge label jeq +6; jl +4; br label
153 gtu > jeq +2; jhs label jeq +6; jlo +4; br label
154 leu <= jeq label; jlo label jeq +2; jhs +4; br label
155 le <= jeq label; jl label jeq +2; jge +4; br label
156 ================================================================= */
157
158 struct hcodes_s
159 {
160 const char * name;
161 int index; /* Corresponding insn_opnumb. */
162 int tlab; /* Number of labels in short mode. */
163 int op0; /* Opcode for first word of short jump. */
164 int op1; /* Opcode for second word of short jump. */
165 int lop0; /* Opcodes for long jump mode. */
166 int lop1;
167 int lop2;
168 };
169
170 static struct hcodes_s msp430_hcodes[] =
171 {
172 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
173 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
174 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
175 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
176 {0,0,0,0,0,0,0,0}
177 };
178
179 static struct hcodes_s msp430x_hcodes[] =
180 {
181 {"bgt", 0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x0030 },
182 {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x0030 },
183 {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x0030 },
184 {"ble", 3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x0030 },
185 {0,0,0,0,0,0,0,0}
186 };
187
188 const char comment_chars[] = ";";
189 const char line_comment_chars[] = "#";
190 const char line_separator_chars[] = "{";
191 const char EXP_CHARS[] = "eE";
192 const char FLT_CHARS[] = "dD";
193
194 /* Handle long expressions. */
195 extern LITTLENUM_TYPE generic_bignum[];
196
197 static htab_t msp430_hash;
198
199 /* Relaxations. */
200 #define STATE_UNCOND_BRANCH 1 /* jump */
201 #define STATE_NOOV_BRANCH 3 /* bltn */
202 #define STATE_SIMPLE_BRANCH 2 /* bne, beq, etc... */
203 #define STATE_EMUL_BRANCH 4
204
205 #define CNRL 2
206 #define CUBL 4
207 #define CNOL 8
208 #define CSBL 6
209 #define CEBL 4
210
211 /* Length. */
212 #define STATE_BITS10 1 /* Wild guess. short jump. */
213 #define STATE_WORD 2 /* 2 bytes pc rel. addr. more. */
214 #define STATE_UNDEF 3 /* Cannot handle this yet. convert to word mode. */
215
216 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
217 #define RELAX_STATE(s) ((s) & 3)
218 #define RELAX_LEN(s) ((s) >> 2)
219 #define RELAX_NEXT(a,b) ENCODE_RELAX (a, b + 1)
220
221 relax_typeS md_relax_table[] =
222 {
223 /* Unused. */
224 {1, 1, 0, 0},
225 {1, 1, 0, 0},
226 {1, 1, 0, 0},
227 {1, 1, 0, 0},
228
229 /* Unconditional jump. */
230 {1, 1, 8, 5},
231 {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
232 {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)}, /* state word */
233 {1, 1, CUBL, 0}, /* state undef */
234
235 /* Simple branches. */
236 {0, 0, 8, 9},
237 {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
238 {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)}, /* state word */
239 {1, 1, CSBL, 0},
240
241 /* blt no overflow branch. */
242 {1, 1, 8, 13},
243 {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
244 {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)}, /* state word */
245 {1, 1, CNOL, 0},
246
247 /* Emulated branches. */
248 {1, 1, 8, 17},
249 {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)}, /* state 10 bits displ */
250 {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)}, /* state word */
251 {1, 1, CNOL, 0}
252 };
253
254
255 #define MAX_OP_LEN 4096
256
257 typedef enum msp_isa
258 {
259 MSP_ISA_430,
260 MSP_ISA_430X,
261 MSP_ISA_430Xv2
262 } msp_isa;
263
264 static enum msp_isa selected_isa = MSP_ISA_430Xv2;
265
266 static inline bfd_boolean
267 target_is_430x (void)
268 {
269 return selected_isa >= MSP_ISA_430X;
270 }
271
272 static inline bfd_boolean
273 target_is_430xv2 (void)
274 {
275 return selected_isa == MSP_ISA_430Xv2;
276 }
277
278 /* Generate an absolute 16-bit relocation, for 430 (!extended_op) instructions
279 only.
280 For the 430X we generate a 430 relocation only for the case where part of an
281 expression is being extracted (e.g. #hi(EXP), #lo(EXP). Otherwise generate
282 a 430X relocation.
283 For the 430 we generate a relocation without assembler range checking
284 if we are handling an immediate value or a byte-width instruction. */
285
286 #undef CHECK_RELOC_MSP430
287 #define CHECK_RELOC_MSP430(OP) \
288 (target_is_430x () \
289 ? ((OP).expp == MSP_EXPP_ALL \
290 ? BFD_RELOC_MSP430X_ABS16 \
291 : ((OP).vshift == 1 \
292 ? BFD_RELOC_MSP430_ABS_HI16 : BFD_RELOC_16)) \
293 : ((imm_op || byte_op) \
294 ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
295
296 /* Generate a 16-bit pc-relative relocation.
297 For the 430X we generate a relocation without linker range checking.
298 For the 430 we generate a relocation without assembler range checking
299 if we are handling an immediate value or a byte-width instruction. */
300 #undef CHECK_RELOC_MSP430_PCREL
301 #define CHECK_RELOC_MSP430_PCREL \
302 (target_is_430x () \
303 ? BFD_RELOC_MSP430X_PCR16 \
304 : (imm_op || byte_op) \
305 ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL)
306
307 /* Profiling capability:
308 It is a performance hit to use gcc's profiling approach for this tiny target.
309 Even more -- jtag hardware facility does not perform any profiling functions.
310 However we've got gdb's built-in simulator where we can do anything.
311 Therefore my suggestion is:
312
313 We define new section ".profiler" which holds all profiling information.
314 We define new pseudo operation .profiler which will instruct assembler to
315 add new profile entry to the object file. Profile should take place at the
316 present address.
317
318 Pseudo-op format:
319
320 .profiler flags,function_to_profile [, cycle_corrector, extra]
321
322 where 'flags' is a combination of the following chars:
323 s - function Start
324 x - function eXit
325 i - function is in Init section
326 f - function is in Fini section
327 l - Library call
328 c - libC standard call
329 d - stack value Demand (saved at run-time in simulator)
330 I - Interrupt service routine
331 P - Prologue start
332 p - Prologue end
333 E - Epilogue start
334 e - Epilogue end
335 j - long Jump/ sjlj unwind
336 a - an Arbitrary code fragment
337 t - exTra parameter saved (constant value like frame size)
338 '""' optional: "sil" == sil
339
340 function_to_profile - function's address
341 cycle_corrector - a value which should be added to the cycle
342 counter, zero if omitted
343 extra - some extra parameter, zero if omitted.
344
345 For example:
346 ------------------------------
347 .global fxx
348 .type fxx,@function
349 fxx:
350 .LFrameOffset_fxx=0x08
351 .profiler "scdP", fxx ; function entry.
352 ; we also demand stack value to be displayed
353 push r11
354 push r10
355 push r9
356 push r8
357 .profiler "cdp",fxx,0, .LFrameOffset_fxx ; check stack value at this point
358 ; (this is a prologue end)
359 ; note, that spare var filled with the frame size
360 mov r15,r8
361 ....
362 .profiler cdE,fxx ; check stack
363 pop r8
364 pop r9
365 pop r10
366 pop r11
367 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter
368 ret ; cause 'ret' insn takes 3 cycles
369 -------------------------------
370
371 This profiling approach does not produce any overhead and
372 absolutely harmless.
373 So, even profiled code can be uploaded to the MCU. */
374 #define MSP430_PROFILER_FLAG_ENTRY 1 /* s */
375 #define MSP430_PROFILER_FLAG_EXIT 2 /* x */
376 #define MSP430_PROFILER_FLAG_INITSECT 4 /* i */
377 #define MSP430_PROFILER_FLAG_FINISECT 8 /* f */
378 #define MSP430_PROFILER_FLAG_LIBCALL 0x10 /* l */
379 #define MSP430_PROFILER_FLAG_STDCALL 0x20 /* c */
380 #define MSP430_PROFILER_FLAG_STACKDMD 0x40 /* d */
381 #define MSP430_PROFILER_FLAG_ISR 0x80 /* I */
382 #define MSP430_PROFILER_FLAG_PROLSTART 0x100 /* P */
383 #define MSP430_PROFILER_FLAG_PROLEND 0x200 /* p */
384 #define MSP430_PROFILER_FLAG_EPISTART 0x400 /* E */
385 #define MSP430_PROFILER_FLAG_EPIEND 0x800 /* e */
386 #define MSP430_PROFILER_FLAG_JUMP 0x1000 /* j */
387 #define MSP430_PROFILER_FLAG_FRAGMENT 0x2000 /* a */
388 #define MSP430_PROFILER_FLAG_EXTRA 0x4000 /* t */
389 #define MSP430_PROFILER_FLAG_notyet 0x8000 /* ? */
390
391 static int
392 pow2value (int y)
393 {
394 int n = 0;
395 unsigned int x;
396
397 x = y;
398
399 if (!x)
400 return 1;
401
402 for (; x; x = x >> 1)
403 if (x & 1)
404 n++;
405
406 return n == 1;
407 }
408
409 /* Parse ordinary expression. */
410
411 static char *
412 parse_exp (char * s, expressionS * op)
413 {
414 input_line_pointer = s;
415 expression (op);
416 if (op->X_op == O_absent)
417 as_bad (_("missing operand"));
418
419 /* Our caller is likely to check that the entire expression was parsed.
420 If we have found a hex constant with an 'h' suffix, ilp will be left
421 pointing at the 'h', so skip it here. */
422 if (input_line_pointer != NULL
423 && op->X_op == O_constant
424 && (*input_line_pointer == 'h' || *input_line_pointer == 'H'))
425 ++ input_line_pointer;
426 return input_line_pointer;
427 }
428
429
430 /* Delete spaces from s: X ( r 1 2) => X(r12). */
431
432 static void
433 del_spaces (char * s)
434 {
435 while (*s)
436 {
437 if (ISSPACE (*s))
438 {
439 char *m = s + 1;
440
441 while (ISSPACE (*m) && *m)
442 m++;
443 memmove (s, m, strlen (m) + 1);
444 }
445 else
446 s++;
447 }
448 }
449
450 static inline char *
451 skip_space (char * s)
452 {
453 while (ISSPACE (*s))
454 ++s;
455 return s;
456 }
457
458 /* Extract one word from FROM and copy it to TO. Delimiters are ",;\n" */
459
460 static char *
461 extract_operand (char * from, char * to, int limit)
462 {
463 int size = 0;
464
465 /* Drop leading whitespace. */
466 from = skip_space (from);
467
468 while (size < limit && *from)
469 {
470 *(to + size) = *from;
471 if (*from == ',' || *from == ';' || *from == '\n')
472 break;
473 from++;
474 size++;
475 }
476
477 *(to + size) = 0;
478 del_spaces (to);
479
480 from++;
481
482 return from;
483 }
484
485 static void
486 msp430_profiler (int dummy ATTRIBUTE_UNUSED)
487 {
488 char buffer[1024];
489 char f[32];
490 char * str = buffer;
491 char * flags = f;
492 int p_flags = 0;
493 char * halt;
494 int ops = 0;
495 int left;
496 char * s;
497 segT seg;
498 int subseg;
499 char * end = 0;
500 expressionS exp;
501 expressionS exp1;
502
503 s = input_line_pointer;
504 end = input_line_pointer;
505
506 while (*end && *end != '\n')
507 end++;
508
509 while (*s && *s != '\n')
510 {
511 if (*s == ',')
512 ops++;
513 s++;
514 }
515
516 left = 3 - ops;
517
518 if (ops < 1)
519 {
520 as_bad (_(".profiler pseudo requires at least two operands."));
521 input_line_pointer = end;
522 return;
523 }
524
525 input_line_pointer = extract_operand (input_line_pointer, flags, 32);
526
527 while (*flags)
528 {
529 switch (*flags)
530 {
531 case '"':
532 break;
533 case 'a':
534 p_flags |= MSP430_PROFILER_FLAG_FRAGMENT;
535 break;
536 case 'j':
537 p_flags |= MSP430_PROFILER_FLAG_JUMP;
538 break;
539 case 'P':
540 p_flags |= MSP430_PROFILER_FLAG_PROLSTART;
541 break;
542 case 'p':
543 p_flags |= MSP430_PROFILER_FLAG_PROLEND;
544 break;
545 case 'E':
546 p_flags |= MSP430_PROFILER_FLAG_EPISTART;
547 break;
548 case 'e':
549 p_flags |= MSP430_PROFILER_FLAG_EPIEND;
550 break;
551 case 's':
552 p_flags |= MSP430_PROFILER_FLAG_ENTRY;
553 break;
554 case 'x':
555 p_flags |= MSP430_PROFILER_FLAG_EXIT;
556 break;
557 case 'i':
558 p_flags |= MSP430_PROFILER_FLAG_INITSECT;
559 break;
560 case 'f':
561 p_flags |= MSP430_PROFILER_FLAG_FINISECT;
562 break;
563 case 'l':
564 p_flags |= MSP430_PROFILER_FLAG_LIBCALL;
565 break;
566 case 'c':
567 p_flags |= MSP430_PROFILER_FLAG_STDCALL;
568 break;
569 case 'd':
570 p_flags |= MSP430_PROFILER_FLAG_STACKDMD;
571 break;
572 case 'I':
573 p_flags |= MSP430_PROFILER_FLAG_ISR;
574 break;
575 case 't':
576 p_flags |= MSP430_PROFILER_FLAG_EXTRA;
577 break;
578 default:
579 as_warn (_("unknown profiling flag - ignored."));
580 break;
581 }
582 flags++;
583 }
584
585 if (p_flags
586 && ( ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_ENTRY
587 | MSP430_PROFILER_FLAG_EXIT))
588 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_PROLSTART
589 | MSP430_PROFILER_FLAG_PROLEND
590 | MSP430_PROFILER_FLAG_EPISTART
591 | MSP430_PROFILER_FLAG_EPIEND))
592 || ! pow2value (p_flags & ( MSP430_PROFILER_FLAG_INITSECT
593 | MSP430_PROFILER_FLAG_FINISECT))))
594 {
595 as_bad (_("ambiguous flags combination - '.profiler' directive ignored."));
596 input_line_pointer = end;
597 return;
598 }
599
600 /* Generate temp symbol which denotes current location. */
601 if (now_seg == absolute_section) /* Paranoia ? */
602 {
603 exp1.X_op = O_constant;
604 exp1.X_add_number = abs_section_offset;
605 as_warn (_("profiling in absolute section?"));
606 }
607 else
608 {
609 exp1.X_op = O_symbol;
610 exp1.X_add_symbol = symbol_temp_new_now ();
611 exp1.X_add_number = 0;
612 }
613
614 /* Generate a symbol which holds flags value. */
615 exp.X_op = O_constant;
616 exp.X_add_number = p_flags;
617
618 /* Save current section. */
619 seg = now_seg;
620 subseg = now_subseg;
621
622 /* Now go to .profiler section. */
623 obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0);
624
625 /* Save flags. */
626 emit_expr (& exp, 2);
627
628 /* Save label value. */
629 emit_expr (& exp1, 2);
630
631 while (ops--)
632 {
633 /* Now get profiling info. */
634 halt = extract_operand (input_line_pointer, str, 1024);
635 /* Process like ".word xxx" directive. */
636 (void) parse_exp (str, & exp);
637 emit_expr (& exp, 2);
638 input_line_pointer = halt;
639 }
640
641 /* Fill the rest with zeros. */
642 exp.X_op = O_constant;
643 exp.X_add_number = 0;
644 while (left--)
645 emit_expr (& exp, 2);
646
647 /* Return to current section. */
648 subseg_set (seg, subseg);
649 }
650
651 static char *
652 extract_word (char * from, char * to, int limit)
653 {
654 char *op_end;
655 int size = 0;
656
657 /* Drop leading whitespace. */
658 from = skip_space (from);
659 *to = 0;
660
661 /* Find the op code end. */
662 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
663 {
664 to[size++] = *op_end++;
665 if (size + 1 >= limit)
666 break;
667 }
668
669 to[size] = 0;
670 return op_end;
671 }
672
673 #define OPTION_MMCU 'm'
674 #define OPTION_RELAX 'Q'
675 #define OPTION_POLYMORPHS 'P'
676 #define OPTION_LARGE 'l'
677 static bfd_boolean large_model = FALSE;
678 #define OPTION_NO_INTR_NOPS 'N'
679 #define OPTION_INTR_NOPS 'n'
680 static bfd_boolean gen_interrupt_nops = FALSE;
681 #define OPTION_WARN_INTR_NOPS 'y'
682 #define OPTION_NO_WARN_INTR_NOPS 'Y'
683 static bfd_boolean warn_interrupt_nops = TRUE;
684 #define OPTION_UNKNOWN_INTR_NOPS 'u'
685 #define OPTION_NO_UNKNOWN_INTR_NOPS 'U'
686 static bfd_boolean do_unknown_interrupt_nops = TRUE;
687 #define OPTION_MCPU 'c'
688 #define OPTION_DATA_REGION 'r'
689 static bfd_boolean upper_data_region_in_use = FALSE;
690 /* The default is to use the lower region only. */
691 static bfd_boolean lower_data_region_only = TRUE;
692
693 enum
694 {
695 OPTION_SILICON_ERRATA = OPTION_MD_BASE,
696 OPTION_SILICON_ERRATA_WARN,
697 };
698
699 static unsigned int silicon_errata_fix = 0;
700 static unsigned int silicon_errata_warn = 0;
701 #define SILICON_ERRATA_CPU4 (1 << 0)
702 #define SILICON_ERRATA_CPU8 (1 << 1)
703 #define SILICON_ERRATA_CPU11 (1 << 2)
704 #define SILICON_ERRATA_CPU12 (1 << 3)
705 #define SILICON_ERRATA_CPU13 (1 << 4)
706 #define SILICON_ERRATA_CPU19 (1 << 5)
707
708 static void
709 msp430_set_arch (int option)
710 {
711 char str[32]; /* 32 for good measure. */
712
713 input_line_pointer = extract_word (input_line_pointer, str, 32);
714
715 md_parse_option (option, str);
716 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
717 target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
718 }
719
720 /* This is a copy of the same data structure found in gcc/config/msp430/msp430.c
721 Keep these two structures in sync.
722 The data in this structure has been extracted from version 1.194 of the
723 devices.csv file released by TI in September 2016. */
724
725 struct msp430_mcu_data
726 {
727 const char * name;
728 unsigned int revision; /* 0=> MSP430, 1=>MSP430X, 2=> MSP430Xv2. */
729 unsigned int hwmpy; /* 0=>none, 1=>16-bit, 2=>16-bit w/sign extend, 4=>32-bit, 8=> 32-bit (5xx). */
730 }
731 msp430_mcu_data [] =
732 {
733 { "cc430f5123",2,8 },
734 { "cc430f5125",2,8 },
735 { "cc430f5133",2,8 },
736 { "cc430f5135",2,8 },
737 { "cc430f5137",2,8 },
738 { "cc430f5143",2,8 },
739 { "cc430f5145",2,8 },
740 { "cc430f5147",2,8 },
741 { "cc430f6125",2,8 },
742 { "cc430f6126",2,8 },
743 { "cc430f6127",2,8 },
744 { "cc430f6135",2,8 },
745 { "cc430f6137",2,8 },
746 { "cc430f6143",2,8 },
747 { "cc430f6145",2,8 },
748 { "cc430f6147",2,8 },
749 { "msp430afe221",0,2 },
750 { "msp430afe222",0,2 },
751 { "msp430afe223",0,2 },
752 { "msp430afe231",0,2 },
753 { "msp430afe232",0,2 },
754 { "msp430afe233",0,2 },
755 { "msp430afe251",0,2 },
756 { "msp430afe252",0,2 },
757 { "msp430afe253",0,2 },
758 { "msp430bt5190",2,8 },
759 { "msp430c091",0,0 },
760 { "msp430c092",0,0 },
761 { "msp430c111",0,0 },
762 { "msp430c1111",0,0 },
763 { "msp430c112",0,0 },
764 { "msp430c1121",0,0 },
765 { "msp430c1331",0,0 },
766 { "msp430c1351",0,0 },
767 { "msp430c311s",0,0 },
768 { "msp430c312",0,0 },
769 { "msp430c313",0,0 },
770 { "msp430c314",0,0 },
771 { "msp430c315",0,0 },
772 { "msp430c323",0,0 },
773 { "msp430c325",0,0 },
774 { "msp430c336",0,1 },
775 { "msp430c337",0,1 },
776 { "msp430c412",0,0 },
777 { "msp430c413",0,0 },
778 { "msp430cg4616",1,1 },
779 { "msp430cg4617",1,1 },
780 { "msp430cg4618",1,1 },
781 { "msp430cg4619",1,1 },
782 { "msp430e112",0,0 },
783 { "msp430e313",0,0 },
784 { "msp430e315",0,0 },
785 { "msp430e325",0,0 },
786 { "msp430e337",0,1 },
787 { "msp430f110",0,0 },
788 { "msp430f1101",0,0 },
789 { "msp430f1101a",0,0 },
790 { "msp430f1111",0,0 },
791 { "msp430f1111a",0,0 },
792 { "msp430f112",0,0 },
793 { "msp430f1121",0,0 },
794 { "msp430f1121a",0,0 },
795 { "msp430f1122",0,0 },
796 { "msp430f1132",0,0 },
797 { "msp430f122",0,0 },
798 { "msp430f1222",0,0 },
799 { "msp430f123",0,0 },
800 { "msp430f1232",0,0 },
801 { "msp430f133",0,0 },
802 { "msp430f135",0,0 },
803 { "msp430f147",0,1 },
804 { "msp430f1471",0,1 },
805 { "msp430f148",0,1 },
806 { "msp430f1481",0,1 },
807 { "msp430f149",0,1 },
808 { "msp430f1491",0,1 },
809 { "msp430f155",0,0 },
810 { "msp430f156",0,0 },
811 { "msp430f157",0,0 },
812 { "msp430f1610",0,1 },
813 { "msp430f1611",0,1 },
814 { "msp430f1612",0,1 },
815 { "msp430f167",0,1 },
816 { "msp430f168",0,1 },
817 { "msp430f169",0,1 },
818 { "msp430f2001",0,0 },
819 { "msp430f2002",0,0 },
820 { "msp430f2003",0,0 },
821 { "msp430f2011",0,0 },
822 { "msp430f2012",0,0 },
823 { "msp430f2013",0,0 },
824 { "msp430f2101",0,0 },
825 { "msp430f2111",0,0 },
826 { "msp430f2112",0,0 },
827 { "msp430f2121",0,0 },
828 { "msp430f2122",0,0 },
829 { "msp430f2131",0,0 },
830 { "msp430f2132",0,0 },
831 { "msp430f2232",0,0 },
832 { "msp430f2234",0,0 },
833 { "msp430f2252",0,0 },
834 { "msp430f2254",0,0 },
835 { "msp430f2272",0,0 },
836 { "msp430f2274",0,0 },
837 { "msp430f233",0,2 },
838 { "msp430f2330",0,2 },
839 { "msp430f235",0,2 },
840 { "msp430f2350",0,2 },
841 { "msp430f2370",0,2 },
842 { "msp430f2410",0,2 },
843 { "msp430f2416",1,2 },
844 { "msp430f2417",1,2 },
845 { "msp430f2418",1,2 },
846 { "msp430f2419",1,2 },
847 { "msp430f247",0,2 },
848 { "msp430f2471",0,2 },
849 { "msp430f248",0,2 },
850 { "msp430f2481",0,2 },
851 { "msp430f249",0,2 },
852 { "msp430f2491",0,2 },
853 { "msp430f2616",1,2 },
854 { "msp430f2617",1,2 },
855 { "msp430f2618",1,2 },
856 { "msp430f2619",1,2 },
857 { "msp430f412",0,0 },
858 { "msp430f413",0,0 },
859 { "msp430f4132",0,0 },
860 { "msp430f415",0,0 },
861 { "msp430f4152",0,0 },
862 { "msp430f417",0,0 },
863 { "msp430f423",0,1 },
864 { "msp430f423a",0,1 },
865 { "msp430f425",0,1 },
866 { "msp430f4250",0,0 },
867 { "msp430f425a",0,1 },
868 { "msp430f4260",0,0 },
869 { "msp430f427",0,1 },
870 { "msp430f4270",0,0 },
871 { "msp430f427a",0,1 },
872 { "msp430f435",0,0 },
873 { "msp430f4351",0,0 },
874 { "msp430f436",0,0 },
875 { "msp430f4361",0,0 },
876 { "msp430f437",0,0 },
877 { "msp430f4371",0,0 },
878 { "msp430f438",0,0 },
879 { "msp430f439",0,0 },
880 { "msp430f447",0,1 },
881 { "msp430f448",0,1 },
882 { "msp430f4481",0,1 },
883 { "msp430f449",0,1 },
884 { "msp430f4491",0,1 },
885 { "msp430f4616",1,1 },
886 { "msp430f46161",1,1 },
887 { "msp430f4617",1,1 },
888 { "msp430f46171",1,1 },
889 { "msp430f4618",1,1 },
890 { "msp430f46181",1,1 },
891 { "msp430f4619",1,1 },
892 { "msp430f46191",1,1 },
893 { "msp430f47126",1,4 },
894 { "msp430f47127",1,4 },
895 { "msp430f47163",1,4 },
896 { "msp430f47166",1,4 },
897 { "msp430f47167",1,4 },
898 { "msp430f47173",1,4 },
899 { "msp430f47176",1,4 },
900 { "msp430f47177",1,4 },
901 { "msp430f47183",1,4 },
902 { "msp430f47186",1,4 },
903 { "msp430f47187",1,4 },
904 { "msp430f47193",1,4 },
905 { "msp430f47196",1,4 },
906 { "msp430f47197",1,4 },
907 { "msp430f477",0,0 },
908 { "msp430f478",0,0 },
909 { "msp430f4783",0,4 },
910 { "msp430f4784",0,4 },
911 { "msp430f479",0,0 },
912 { "msp430f4793",0,4 },
913 { "msp430f4794",0,4 },
914 { "msp430f5131",2,8 },
915 { "msp430f5132",2,8 },
916 { "msp430f5151",2,8 },
917 { "msp430f5152",2,8 },
918 { "msp430f5171",2,8 },
919 { "msp430f5172",2,8 },
920 { "msp430f5212",2,8 },
921 { "msp430f5213",2,8 },
922 { "msp430f5214",2,8 },
923 { "msp430f5217",2,8 },
924 { "msp430f5218",2,8 },
925 { "msp430f5219",2,8 },
926 { "msp430f5222",2,8 },
927 { "msp430f5223",2,8 },
928 { "msp430f5224",2,8 },
929 { "msp430f5227",2,8 },
930 { "msp430f5228",2,8 },
931 { "msp430f5229",2,8 },
932 { "msp430f5232",2,8 },
933 { "msp430f5234",2,8 },
934 { "msp430f5237",2,8 },
935 { "msp430f5239",2,8 },
936 { "msp430f5242",2,8 },
937 { "msp430f5244",2,8 },
938 { "msp430f5247",2,8 },
939 { "msp430f5249",2,8 },
940 { "msp430f5252",2,8 },
941 { "msp430f5253",2,8 },
942 { "msp430f5254",2,8 },
943 { "msp430f5255",2,8 },
944 { "msp430f5256",2,8 },
945 { "msp430f5257",2,8 },
946 { "msp430f5258",2,8 },
947 { "msp430f5259",2,8 },
948 { "msp430f5304",2,8 },
949 { "msp430f5308",2,8 },
950 { "msp430f5309",2,8 },
951 { "msp430f5310",2,8 },
952 { "msp430f5324",2,8 },
953 { "msp430f5325",2,8 },
954 { "msp430f5326",2,8 },
955 { "msp430f5327",2,8 },
956 { "msp430f5328",2,8 },
957 { "msp430f5329",2,8 },
958 { "msp430f5333",2,8 },
959 { "msp430f5335",2,8 },
960 { "msp430f5336",2,8 },
961 { "msp430f5338",2,8 },
962 { "msp430f5340",2,8 },
963 { "msp430f5341",2,8 },
964 { "msp430f5342",2,8 },
965 { "msp430f5358",2,8 },
966 { "msp430f5359",2,8 },
967 { "msp430f5418",2,8 },
968 { "msp430f5418a",2,8 },
969 { "msp430f5419",2,8 },
970 { "msp430f5419a",2,8 },
971 { "msp430f5435",2,8 },
972 { "msp430f5435a",2,8 },
973 { "msp430f5436",2,8 },
974 { "msp430f5436a",2,8 },
975 { "msp430f5437",2,8 },
976 { "msp430f5437a",2,8 },
977 { "msp430f5438",2,8 },
978 { "msp430f5438a",2,8 },
979 { "msp430f5500",2,8 },
980 { "msp430f5501",2,8 },
981 { "msp430f5502",2,8 },
982 { "msp430f5503",2,8 },
983 { "msp430f5504",2,8 },
984 { "msp430f5505",2,8 },
985 { "msp430f5506",2,8 },
986 { "msp430f5507",2,8 },
987 { "msp430f5508",2,8 },
988 { "msp430f5509",2,8 },
989 { "msp430f5510",2,8 },
990 { "msp430f5513",2,8 },
991 { "msp430f5514",2,8 },
992 { "msp430f5515",2,8 },
993 { "msp430f5517",2,8 },
994 { "msp430f5519",2,8 },
995 { "msp430f5521",2,8 },
996 { "msp430f5522",2,8 },
997 { "msp430f5524",2,8 },
998 { "msp430f5525",2,8 },
999 { "msp430f5526",2,8 },
1000 { "msp430f5527",2,8 },
1001 { "msp430f5528",2,8 },
1002 { "msp430f5529",2,8 },
1003 { "msp430f5630",2,8 },
1004 { "msp430f5631",2,8 },
1005 { "msp430f5632",2,8 },
1006 { "msp430f5633",2,8 },
1007 { "msp430f5634",2,8 },
1008 { "msp430f5635",2,8 },
1009 { "msp430f5636",2,8 },
1010 { "msp430f5637",2,8 },
1011 { "msp430f5638",2,8 },
1012 { "msp430f5658",2,8 },
1013 { "msp430f5659",2,8 },
1014 { "msp430f5xx_6xxgeneric",2,8 },
1015 { "msp430f6433",2,8 },
1016 { "msp430f6435",2,8 },
1017 { "msp430f6436",2,8 },
1018 { "msp430f6438",2,8 },
1019 { "msp430f6458",2,8 },
1020 { "msp430f6459",2,8 },
1021 { "msp430f6630",2,8 },
1022 { "msp430f6631",2,8 },
1023 { "msp430f6632",2,8 },
1024 { "msp430f6633",2,8 },
1025 { "msp430f6634",2,8 },
1026 { "msp430f6635",2,8 },
1027 { "msp430f6636",2,8 },
1028 { "msp430f6637",2,8 },
1029 { "msp430f6638",2,8 },
1030 { "msp430f6658",2,8 },
1031 { "msp430f6659",2,8 },
1032 { "msp430f6720",2,8 },
1033 { "msp430f6720a",2,8 },
1034 { "msp430f6721",2,8 },
1035 { "msp430f6721a",2,8 },
1036 { "msp430f6723",2,8 },
1037 { "msp430f6723a",2,8 },
1038 { "msp430f6724",2,8 },
1039 { "msp430f6724a",2,8 },
1040 { "msp430f6725",2,8 },
1041 { "msp430f6725a",2,8 },
1042 { "msp430f6726",2,8 },
1043 { "msp430f6726a",2,8 },
1044 { "msp430f6730",2,8 },
1045 { "msp430f6730a",2,8 },
1046 { "msp430f6731",2,8 },
1047 { "msp430f6731a",2,8 },
1048 { "msp430f6733",2,8 },
1049 { "msp430f6733a",2,8 },
1050 { "msp430f6734",2,8 },
1051 { "msp430f6734a",2,8 },
1052 { "msp430f6735",2,8 },
1053 { "msp430f6735a",2,8 },
1054 { "msp430f6736",2,8 },
1055 { "msp430f6736a",2,8 },
1056 { "msp430f6745",2,8 },
1057 { "msp430f67451",2,8 },
1058 { "msp430f67451a",2,8 },
1059 { "msp430f6745a",2,8 },
1060 { "msp430f6746",2,8 },
1061 { "msp430f67461",2,8 },
1062 { "msp430f67461a",2,8 },
1063 { "msp430f6746a",2,8 },
1064 { "msp430f6747",2,8 },
1065 { "msp430f67471",2,8 },
1066 { "msp430f67471a",2,8 },
1067 { "msp430f6747a",2,8 },
1068 { "msp430f6748",2,8 },
1069 { "msp430f67481",2,8 },
1070 { "msp430f67481a",2,8 },
1071 { "msp430f6748a",2,8 },
1072 { "msp430f6749",2,8 },
1073 { "msp430f67491",2,8 },
1074 { "msp430f67491a",2,8 },
1075 { "msp430f6749a",2,8 },
1076 { "msp430f67621",2,8 },
1077 { "msp430f67621a",2,8 },
1078 { "msp430f67641",2,8 },
1079 { "msp430f67641a",2,8 },
1080 { "msp430f6765",2,8 },
1081 { "msp430f67651",2,8 },
1082 { "msp430f67651a",2,8 },
1083 { "msp430f6765a",2,8 },
1084 { "msp430f6766",2,8 },
1085 { "msp430f67661",2,8 },
1086 { "msp430f67661a",2,8 },
1087 { "msp430f6766a",2,8 },
1088 { "msp430f6767",2,8 },
1089 { "msp430f67671",2,8 },
1090 { "msp430f67671a",2,8 },
1091 { "msp430f6767a",2,8 },
1092 { "msp430f6768",2,8 },
1093 { "msp430f67681",2,8 },
1094 { "msp430f67681a",2,8 },
1095 { "msp430f6768a",2,8 },
1096 { "msp430f6769",2,8 },
1097 { "msp430f67691",2,8 },
1098 { "msp430f67691a",2,8 },
1099 { "msp430f6769a",2,8 },
1100 { "msp430f6775",2,8 },
1101 { "msp430f67751",2,8 },
1102 { "msp430f67751a",2,8 },
1103 { "msp430f6775a",2,8 },
1104 { "msp430f6776",2,8 },
1105 { "msp430f67761",2,8 },
1106 { "msp430f67761a",2,8 },
1107 { "msp430f6776a",2,8 },
1108 { "msp430f6777",2,8 },
1109 { "msp430f67771",2,8 },
1110 { "msp430f67771a",2,8 },
1111 { "msp430f6777a",2,8 },
1112 { "msp430f6778",2,8 },
1113 { "msp430f67781",2,8 },
1114 { "msp430f67781a",2,8 },
1115 { "msp430f6778a",2,8 },
1116 { "msp430f6779",2,8 },
1117 { "msp430f67791",2,8 },
1118 { "msp430f67791a",2,8 },
1119 { "msp430f6779a",2,8 },
1120 { "msp430fe423",0,0 },
1121 { "msp430fe4232",0,0 },
1122 { "msp430fe423a",0,0 },
1123 { "msp430fe4242",0,0 },
1124 { "msp430fe425",0,0 },
1125 { "msp430fe4252",0,0 },
1126 { "msp430fe425a",0,0 },
1127 { "msp430fe427",0,0 },
1128 { "msp430fe4272",0,0 },
1129 { "msp430fe427a",0,0 },
1130 { "msp430fg4250",0,0 },
1131 { "msp430fg4260",0,0 },
1132 { "msp430fg4270",0,0 },
1133 { "msp430fg437",0,0 },
1134 { "msp430fg438",0,0 },
1135 { "msp430fg439",0,0 },
1136 { "msp430fg4616",1,1 },
1137 { "msp430fg4617",1,1 },
1138 { "msp430fg4618",1,1 },
1139 { "msp430fg4619",1,1 },
1140 { "msp430fg477",0,0 },
1141 { "msp430fg478",0,0 },
1142 { "msp430fg479",0,0 },
1143 { "msp430fg6425",2,8 },
1144 { "msp430fg6426",2,8 },
1145 { "msp430fg6625",2,8 },
1146 { "msp430fg6626",2,8 },
1147 { "msp430fr2032",2,0 },
1148 { "msp430fr2033",2,0 },
1149 { "msp430fr2110",2,0 },
1150 { "msp430fr2111",2,0 },
1151 { "msp430fr2310",2,0 },
1152 { "msp430fr2311",2,0 },
1153 { "msp430fr2433",2,8 },
1154 { "msp430fr2532",2,8 },
1155 { "msp430fr2533",2,8 },
1156 { "msp430fr2632",2,8 },
1157 { "msp430fr2633",2,8 },
1158 { "msp430fr2xx_4xxgeneric",2,8 },
1159 { "msp430fr4131",2,0 },
1160 { "msp430fr4132",2,0 },
1161 { "msp430fr4133",2,0 },
1162 { "msp430fr5720",2,8 },
1163 { "msp430fr5721",2,8 },
1164 { "msp430fr5722",2,8 },
1165 { "msp430fr5723",2,8 },
1166 { "msp430fr5724",2,8 },
1167 { "msp430fr5725",2,8 },
1168 { "msp430fr5726",2,8 },
1169 { "msp430fr5727",2,8 },
1170 { "msp430fr5728",2,8 },
1171 { "msp430fr5729",2,8 },
1172 { "msp430fr5730",2,8 },
1173 { "msp430fr5731",2,8 },
1174 { "msp430fr5732",2,8 },
1175 { "msp430fr5733",2,8 },
1176 { "msp430fr5734",2,8 },
1177 { "msp430fr5735",2,8 },
1178 { "msp430fr5736",2,8 },
1179 { "msp430fr5737",2,8 },
1180 { "msp430fr5738",2,8 },
1181 { "msp430fr5739",2,8 },
1182 { "msp430fr57xxgeneric",2,8 },
1183 { "msp430fr5847",2,8 },
1184 { "msp430fr58471",2,8 },
1185 { "msp430fr5848",2,8 },
1186 { "msp430fr5849",2,8 },
1187 { "msp430fr5857",2,8 },
1188 { "msp430fr5858",2,8 },
1189 { "msp430fr5859",2,8 },
1190 { "msp430fr5867",2,8 },
1191 { "msp430fr58671",2,8 },
1192 { "msp430fr5868",2,8 },
1193 { "msp430fr5869",2,8 },
1194 { "msp430fr5870",2,8 },
1195 { "msp430fr5872",2,8 },
1196 { "msp430fr58721",2,8 },
1197 { "msp430fr5887",2,8 },
1198 { "msp430fr5888",2,8 },
1199 { "msp430fr5889",2,8 },
1200 { "msp430fr58891",2,8 },
1201 { "msp430fr5922",2,8 },
1202 { "msp430fr59221",2,8 },
1203 { "msp430fr5947",2,8 },
1204 { "msp430fr59471",2,8 },
1205 { "msp430fr5948",2,8 },
1206 { "msp430fr5949",2,8 },
1207 { "msp430fr5957",2,8 },
1208 { "msp430fr5958",2,8 },
1209 { "msp430fr5959",2,8 },
1210 { "msp430fr5962",2,8 },
1211 { "msp430fr5964",2,8 },
1212 { "msp430fr5967",2,8 },
1213 { "msp430fr5968",2,8 },
1214 { "msp430fr5969",2,8 },
1215 { "msp430fr59691",2,8 },
1216 { "msp430fr5970",2,8 },
1217 { "msp430fr5972",2,8 },
1218 { "msp430fr59721",2,8 },
1219 { "msp430fr5986",2,8 },
1220 { "msp430fr5987",2,8 },
1221 { "msp430fr5988",2,8 },
1222 { "msp430fr5989",2,8 },
1223 { "msp430fr59891",2,8 },
1224 { "msp430fr5992",2,8 },
1225 { "msp430fr5994",2,8 },
1226 { "msp430fr59941",2,8 },
1227 { "msp430fr5xx_6xxgeneric",2,8 },
1228 { "msp430fr6820",2,8 },
1229 { "msp430fr6822",2,8 },
1230 { "msp430fr68221",2,8 },
1231 { "msp430fr6870",2,8 },
1232 { "msp430fr6872",2,8 },
1233 { "msp430fr68721",2,8 },
1234 { "msp430fr6877",2,8 },
1235 { "msp430fr6879",2,8 },
1236 { "msp430fr68791",2,8 },
1237 { "msp430fr6887",2,8 },
1238 { "msp430fr6888",2,8 },
1239 { "msp430fr6889",2,8 },
1240 { "msp430fr68891",2,8 },
1241 { "msp430fr6920",2,8 },
1242 { "msp430fr6922",2,8 },
1243 { "msp430fr69221",2,8 },
1244 { "msp430fr6927",2,8 },
1245 { "msp430fr69271",2,8 },
1246 { "msp430fr6928",2,8 },
1247 { "msp430fr6970",2,8 },
1248 { "msp430fr6972",2,8 },
1249 { "msp430fr69721",2,8 },
1250 { "msp430fr6977",2,8 },
1251 { "msp430fr6979",2,8 },
1252 { "msp430fr69791",2,8 },
1253 { "msp430fr6987",2,8 },
1254 { "msp430fr6988",2,8 },
1255 { "msp430fr6989",2,8 },
1256 { "msp430fr69891",2,8 },
1257 { "msp430fw423",0,0 },
1258 { "msp430fw425",0,0 },
1259 { "msp430fw427",0,0 },
1260 { "msp430fw428",0,0 },
1261 { "msp430fw429",0,0 },
1262 { "msp430g2001",0,0 },
1263 { "msp430g2101",0,0 },
1264 { "msp430g2102",0,0 },
1265 { "msp430g2111",0,0 },
1266 { "msp430g2112",0,0 },
1267 { "msp430g2113",0,0 },
1268 { "msp430g2121",0,0 },
1269 { "msp430g2131",0,0 },
1270 { "msp430g2132",0,0 },
1271 { "msp430g2152",0,0 },
1272 { "msp430g2153",0,0 },
1273 { "msp430g2201",0,0 },
1274 { "msp430g2202",0,0 },
1275 { "msp430g2203",0,0 },
1276 { "msp430g2210",0,0 },
1277 { "msp430g2211",0,0 },
1278 { "msp430g2212",0,0 },
1279 { "msp430g2213",0,0 },
1280 { "msp430g2221",0,0 },
1281 { "msp430g2230",0,0 },
1282 { "msp430g2231",0,0 },
1283 { "msp430g2232",0,0 },
1284 { "msp430g2233",0,0 },
1285 { "msp430g2252",0,0 },
1286 { "msp430g2253",0,0 },
1287 { "msp430g2302",0,0 },
1288 { "msp430g2303",0,0 },
1289 { "msp430g2312",0,0 },
1290 { "msp430g2313",0,0 },
1291 { "msp430g2332",0,0 },
1292 { "msp430g2333",0,0 },
1293 { "msp430g2352",0,0 },
1294 { "msp430g2353",0,0 },
1295 { "msp430g2402",0,0 },
1296 { "msp430g2403",0,0 },
1297 { "msp430g2412",0,0 },
1298 { "msp430g2413",0,0 },
1299 { "msp430g2432",0,0 },
1300 { "msp430g2433",0,0 },
1301 { "msp430g2444",0,0 },
1302 { "msp430g2452",0,0 },
1303 { "msp430g2453",0,0 },
1304 { "msp430g2513",0,0 },
1305 { "msp430g2533",0,0 },
1306 { "msp430g2544",0,0 },
1307 { "msp430g2553",0,0 },
1308 { "msp430g2744",0,0 },
1309 { "msp430g2755",0,0 },
1310 { "msp430g2855",0,0 },
1311 { "msp430g2955",0,0 },
1312 { "msp430i2020",0,2 },
1313 { "msp430i2021",0,2 },
1314 { "msp430i2030",0,2 },
1315 { "msp430i2031",0,2 },
1316 { "msp430i2040",0,2 },
1317 { "msp430i2041",0,2 },
1318 { "msp430i2xxgeneric",0,2 },
1319 { "msp430l092",0,0 },
1320 { "msp430p112",0,0 },
1321 { "msp430p313",0,0 },
1322 { "msp430p315",0,0 },
1323 { "msp430p315s",0,0 },
1324 { "msp430p325",0,0 },
1325 { "msp430p337",0,1 },
1326 { "msp430sl5438a",2,8 },
1327 { "msp430tch5e",0,0 },
1328 { "msp430xgeneric",2,8 },
1329 { "rf430f5144",2,8 },
1330 { "rf430f5155",2,8 },
1331 { "rf430f5175",2,8 },
1332 { "rf430frl152h",0,0 },
1333 { "rf430frl152h_rom",0,0 },
1334 { "rf430frl153h",0,0 },
1335 { "rf430frl153h_rom",0,0 },
1336 { "rf430frl154h",0,0 },
1337 { "rf430frl154h_rom",0,0 }
1338 };
1339
1340 int
1341 md_parse_option (int c, const char * arg)
1342 {
1343 switch (c)
1344 {
1345 case OPTION_SILICON_ERRATA:
1346 case OPTION_SILICON_ERRATA_WARN:
1347 {
1348 signed int i;
1349 const struct
1350 {
1351 const char * name;
1352 unsigned int length;
1353 unsigned int bitfield;
1354 } erratas[] =
1355 {
1356 { STRING_COMMA_LEN ("cpu4"), SILICON_ERRATA_CPU4 },
1357 { STRING_COMMA_LEN ("cpu8"), SILICON_ERRATA_CPU8 },
1358 { STRING_COMMA_LEN ("cpu11"), SILICON_ERRATA_CPU11 },
1359 { STRING_COMMA_LEN ("cpu12"), SILICON_ERRATA_CPU12 },
1360 { STRING_COMMA_LEN ("cpu13"), SILICON_ERRATA_CPU13 },
1361 { STRING_COMMA_LEN ("cpu19"), SILICON_ERRATA_CPU19 },
1362 };
1363
1364 do
1365 {
1366 for (i = ARRAY_SIZE (erratas); i--;)
1367 if (strncasecmp (arg, erratas[i].name, erratas[i].length) == 0)
1368 {
1369 if (c == OPTION_SILICON_ERRATA)
1370 silicon_errata_fix |= erratas[i].bitfield;
1371 else
1372 silicon_errata_warn |= erratas[i].bitfield;
1373 arg += erratas[i].length;
1374 break;
1375 }
1376 if (i < 0)
1377 {
1378 as_warn (_("Unrecognised CPU errata name starting here: %s"), arg);
1379 break;
1380 }
1381 if (*arg == 0)
1382 break;
1383 if (*arg != ',')
1384 as_warn (_("Expecting comma after CPU errata name, not: %s"), arg);
1385 else
1386 arg ++;
1387 }
1388 while (*arg != 0);
1389 }
1390 return 1;
1391
1392 case OPTION_MMCU:
1393 if (arg == NULL)
1394 as_fatal (_("MCU option requires a name\n"));
1395
1396 if (strcasecmp ("msp430", arg) == 0)
1397 selected_isa = MSP_ISA_430;
1398 else if (strcasecmp ("msp430xv2", arg) == 0)
1399 selected_isa = MSP_ISA_430Xv2;
1400 else if (strcasecmp ("msp430x", arg) == 0)
1401 selected_isa = MSP_ISA_430X;
1402 else
1403 {
1404 int i;
1405
1406 for (i = ARRAY_SIZE (msp430_mcu_data); i--;)
1407 if (strcasecmp (msp430_mcu_data[i].name, arg) == 0)
1408 {
1409 switch (msp430_mcu_data[i].revision)
1410 {
1411 case 0: selected_isa = MSP_ISA_430; break;
1412 case 1: selected_isa = MSP_ISA_430X; break;
1413 case 2: selected_isa = MSP_ISA_430Xv2; break;
1414 }
1415 break;
1416 }
1417 }
1418 /* It is not an error if we do not match the MCU name. */
1419 return 1;
1420
1421 case OPTION_MCPU:
1422 if (strcmp (arg, "430") == 0
1423 || strcasecmp (arg, "msp430") == 0)
1424 selected_isa = MSP_ISA_430;
1425 else if (strcasecmp (arg, "430x") == 0
1426 || strcasecmp (arg, "msp430x") == 0)
1427 selected_isa = MSP_ISA_430X;
1428 else if (strcasecmp (arg, "430xv2") == 0
1429 || strcasecmp (arg, "msp430xv2") == 0)
1430 selected_isa = MSP_ISA_430Xv2;
1431 else
1432 as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg);
1433 return 1;
1434
1435 case OPTION_RELAX:
1436 msp430_enable_relax = 1;
1437 return 1;
1438
1439 case OPTION_POLYMORPHS:
1440 msp430_enable_polys = 1;
1441 return 1;
1442
1443 case OPTION_LARGE:
1444 large_model = TRUE;
1445 return 1;
1446
1447 case OPTION_NO_INTR_NOPS:
1448 gen_interrupt_nops = FALSE;
1449 return 1;
1450 case OPTION_INTR_NOPS:
1451 gen_interrupt_nops = TRUE;
1452 return 1;
1453
1454 case OPTION_WARN_INTR_NOPS:
1455 warn_interrupt_nops = TRUE;
1456 return 1;
1457 case OPTION_NO_WARN_INTR_NOPS:
1458 warn_interrupt_nops = FALSE;
1459 return 1;
1460
1461 case OPTION_UNKNOWN_INTR_NOPS:
1462 do_unknown_interrupt_nops = TRUE;
1463 return 1;
1464 case OPTION_NO_UNKNOWN_INTR_NOPS:
1465 do_unknown_interrupt_nops = FALSE;
1466 return 1;
1467
1468 case OPTION_DATA_REGION:
1469 if (strcmp (arg, "upper") == 0
1470 || strcmp (arg, "either") == 0)
1471 upper_data_region_in_use = TRUE;
1472 if (strcmp (arg, "upper") == 0
1473 || strcmp (arg, "either") == 0
1474 /* With data-region=none, the compiler has generated code assuming
1475 data could be in the upper region, but nothing has been explicitly
1476 placed there. */
1477 || strcmp (arg, "none") == 0)
1478 lower_data_region_only = FALSE;
1479 return 1;
1480 }
1481
1482 return 0;
1483 }
1484
1485 /* The intention here is to have the mere presence of these sections
1486 cause the object to have a reference to a well-known symbol. This
1487 reference pulls in the bits of the runtime (crt0) that initialize
1488 these sections. Thus, for example, the startup code to call
1489 memset() to initialize .bss will only be linked in when there is a
1490 non-empty .bss section. Otherwise, the call would exist but have a
1491 zero length parameter, which is a waste of memory and cycles.
1492
1493 The code which initializes these sections should have a global
1494 label for these symbols, and should be marked with KEEP() in the
1495 linker script. */
1496
1497 static void
1498 msp430_make_init_symbols (const char * name)
1499 {
1500 if (strncmp (name, ".bss", 4) == 0
1501 || strncmp (name, ".lower.bss", 10) == 0
1502 || strncmp (name, ".either.bss", 11) == 0
1503 || strncmp (name, ".gnu.linkonce.b.", 16) == 0)
1504 (void) symbol_find_or_make ("__crt0_init_bss");
1505
1506 if (strncmp (name, ".data", 5) == 0
1507 || strncmp (name, ".lower.data", 11) == 0
1508 || strncmp (name, ".either.data", 12) == 0
1509 || strncmp (name, ".gnu.linkonce.d.", 16) == 0)
1510 (void) symbol_find_or_make ("__crt0_movedata");
1511 /* Note - data assigned to the .either.data section may end up being
1512 placed in the .upper.data section if the .lower.data section is
1513 full. Hence the need to define the crt0 symbol.
1514 The linker may create upper or either data sections, even when none exist
1515 at the moment, so use the value of the data-region flag to determine if
1516 the symbol is needed. */
1517 if (strncmp (name, ".either.data", 12) == 0
1518 || strncmp (name, ".upper.data", 11) == 0
1519 || upper_data_region_in_use)
1520 (void) symbol_find_or_make ("__crt0_move_highdata");
1521
1522 /* See note about .either.data above. */
1523 if (strncmp (name, ".upper.bss", 10) == 0
1524 || strncmp (name, ".either.bss", 11) == 0
1525 || upper_data_region_in_use)
1526 (void) symbol_find_or_make ("__crt0_init_highbss");
1527
1528 /* The following symbols are for the crt0 functions that run through
1529 the different .*_array sections and call the functions placed there.
1530 - init_array stores global static C++ constructors to run before main.
1531 - preinit_array is not expected to ever be used for MSP430.
1532 GCC only places initialization functions for runtime "sanitizers"
1533 (i.e. {a,l,t,u}san) and "virtual table verification" in preinit_array.
1534 - fini_array stores global static C++ destructors to run after calling
1535 exit() or returning from main.
1536 __crt0_run_array is required to actually call the functions in the above
1537 arrays. */
1538 if (strncmp (name, ".init_array", 11) == 0)
1539 {
1540 (void) symbol_find_or_make ("__crt0_run_init_array");
1541 (void) symbol_find_or_make ("__crt0_run_array");
1542 }
1543 else if (strncmp (name, ".preinit_array", 14) == 0)
1544 {
1545 (void) symbol_find_or_make ("__crt0_run_preinit_array");
1546 (void) symbol_find_or_make ("__crt0_run_array");
1547 }
1548 else if (strncmp (name, ".fini_array", 11) == 0)
1549 {
1550 (void) symbol_find_or_make ("__crt0_run_fini_array");
1551 (void) symbol_find_or_make ("__crt0_run_array");
1552 }
1553 }
1554
1555 static void
1556 msp430_section (int arg)
1557 {
1558 char * saved_ilp = input_line_pointer;
1559 const char * name = obj_elf_section_name ();
1560
1561 msp430_make_init_symbols (name);
1562
1563 input_line_pointer = saved_ilp;
1564 obj_elf_section (arg);
1565 }
1566
1567 void
1568 msp430_frob_section (asection *sec)
1569 {
1570 const char *name = sec->name;
1571
1572 if (sec->size == 0)
1573 return;
1574
1575 msp430_make_init_symbols (name);
1576 }
1577
1578 static void
1579 msp430_lcomm (int ignore ATTRIBUTE_UNUSED)
1580 {
1581 symbolS *symbolP = s_comm_internal (0, s_lcomm_internal);
1582
1583 if (symbolP)
1584 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
1585 (void) symbol_find_or_make ("__crt0_init_bss");
1586 }
1587
1588 static void
1589 msp430_comm (int needs_align)
1590 {
1591 s_comm_internal (needs_align, elf_common_parse);
1592 (void) symbol_find_or_make ("__crt0_init_bss");
1593 }
1594
1595 static void
1596 msp430_refsym (int arg ATTRIBUTE_UNUSED)
1597 {
1598 char sym_name[1024];
1599 input_line_pointer = extract_word (input_line_pointer, sym_name, 1024);
1600
1601 (void) symbol_find_or_make (sym_name);
1602 }
1603
1604 /* Handle a .mspabi_attribute or .gnu_attribute directive.
1605 attr_type is 0 for .mspabi_attribute or 1 for .gnu_attribute.
1606 This is only used for validating the attributes in the assembly file against
1607 the options gas has been invoked with. If the attributes and options are
1608 compatible then we add the attributes to the assembly file in
1609 msp430_md_end. */
1610 static void
1611 msp430_object_attribute (int attr_type)
1612 {
1613 char tag_name_s[32];
1614 char tag_value_s[32];
1615 int tag_name, tag_value;
1616 /* First operand is the tag name, second is the tag value e.g.
1617 ".mspabi_attribute 4, 2". */
1618 input_line_pointer = extract_operand (input_line_pointer, tag_name_s, 32);
1619 input_line_pointer = extract_operand (input_line_pointer, tag_value_s, 32);
1620 tag_name = atoi (tag_name_s);
1621 tag_value = atoi (tag_value_s);
1622 /* If the attribute directive is present, the tag_value should never be set
1623 to 0. */
1624 if (tag_name == 0 || tag_value == 0)
1625 as_bad (_("bad arguments \"%s\" and/or \"%s\" in %s directive"),
1626 tag_name_s, tag_value_s, (attr_type ? ".gnu_attribute"
1627 : ".mspabi_attribute"));
1628 else if (attr_type == 0)
1629 /* Handle .mspabi_attribute. */
1630 switch (tag_name)
1631 {
1632 case OFBA_MSPABI_Tag_ISA:
1633 switch (tag_value)
1634 {
1635 case OFBA_MSPABI_Val_ISA_MSP430:
1636 if (target_is_430x ())
1637 as_bad (_("file was compiled for the 430 ISA but the %s ISA is "
1638 "selected"), (target_is_430xv2 () ? "430X" : "430Xv2"));
1639 break;
1640 case OFBA_MSPABI_Val_ISA_MSP430X:
1641 if (!target_is_430x ())
1642 as_bad (_("file was compiled for the 430X ISA but the 430 ISA is "
1643 "selected"));
1644 break;
1645 default:
1646 as_bad (_("unknown MSPABI build attribute value '%d' for "
1647 "OFBA_MSPABI_Tag_ISA(%d) in .mspabi_attribute directive"),
1648 tag_value, OFBA_MSPABI_Tag_ISA);
1649 break;
1650 }
1651 break;
1652 case OFBA_MSPABI_Tag_Code_Model:
1653 /* Fall through. */
1654 case OFBA_MSPABI_Tag_Data_Model:
1655 /* FIXME: Might we want to set the memory model to large if the assembly
1656 file has the large model attribute, but -ml has not been passed? */
1657 switch (tag_value)
1658 {
1659 case OFBA_MSPABI_Val_Code_Model_SMALL:
1660 if (large_model)
1661 as_bad (_("file was compiled for the small memory model, but the "
1662 "large memory model is selected"));
1663 break;
1664 case OFBA_MSPABI_Val_Code_Model_LARGE:
1665 if (!large_model)
1666 as_bad (_("file was compiled for the large memory model, "
1667 "but the small memory model is selected"));
1668 break;
1669 default:
1670 as_bad (_("unknown MSPABI build attribute value '%d' for %s(%d) "
1671 "in .mspabi_attribute directive"), tag_value,
1672 (tag_name == OFBA_MSPABI_Tag_Code_Model
1673 ? "OFBA_MSPABI_Tag_Code_Model"
1674 : "OFBA_MSPABI_Tag_Data_Model"),
1675 (tag_name == OFBA_MSPABI_Tag_Code_Model
1676 ? OFBA_MSPABI_Tag_Code_Model
1677 : OFBA_MSPABI_Tag_Data_Model));
1678 break;
1679 }
1680 break;
1681 default:
1682 as_bad (_("unknown MSPABI build attribute tag '%d' in "
1683 ".mspabi_attribute directive"), tag_name);
1684 break;
1685 }
1686 else if (attr_type == 1)
1687 /* Handle .gnu_attribute. */
1688 switch (tag_name)
1689 {
1690 case Tag_GNU_MSP430_Data_Region:
1691 /* This attribute is only applicable in the large memory model. */
1692 if (!large_model)
1693 break;
1694 switch (tag_value)
1695 {
1696 case Val_GNU_MSP430_Data_Region_Lower:
1697 if (!lower_data_region_only)
1698 as_bad (_("file was compiled assuming all data will be in the "
1699 "lower memory region, but the upper region is in use"));
1700 break;
1701 case Val_GNU_MSP430_Data_Region_Any:
1702 if (lower_data_region_only)
1703 as_bad (_("file was compiled assuming data could be in the upper "
1704 "memory region, but the lower data region is "
1705 "exclusively in use"));
1706 break;
1707 default:
1708 as_bad (_("unknown GNU build attribute value '%d' for "
1709 "Tag_GNU_MSP430_Data_Region(%d) in .gnu_attribute "
1710 "directive"), tag_value, Tag_GNU_MSP430_Data_Region);
1711 }
1712 }
1713 else
1714 as_bad (_("internal: unexpected argument '%d' to msp430_object_attribute"),
1715 attr_type);
1716 }
1717
1718 const pseudo_typeS md_pseudo_table[] =
1719 {
1720 {"arch", msp430_set_arch, OPTION_MMCU},
1721 {"cpu", msp430_set_arch, OPTION_MCPU},
1722 {"profiler", msp430_profiler, 0},
1723 {"section", msp430_section, 0},
1724 {"section.s", msp430_section, 0},
1725 {"sect", msp430_section, 0},
1726 {"sect.s", msp430_section, 0},
1727 {"pushsection", msp430_section, 1},
1728 {"refsym", msp430_refsym, 0},
1729 {"comm", msp430_comm, 0},
1730 {"lcomm", msp430_lcomm, 0},
1731 {"mspabi_attribute", msp430_object_attribute, 0},
1732 {"gnu_attribute", msp430_object_attribute, 1},
1733 {NULL, NULL, 0}
1734 };
1735
1736 const char *md_shortopts = "mm:,mP,mQ,ml,mN,mn,my,mY,mu,mU";
1737
1738 struct option md_longopts[] =
1739 {
1740 {"msilicon-errata", required_argument, NULL, OPTION_SILICON_ERRATA},
1741 {"msilicon-errata-warn", required_argument, NULL, OPTION_SILICON_ERRATA_WARN},
1742 {"mmcu", required_argument, NULL, OPTION_MMCU},
1743 {"mcpu", required_argument, NULL, OPTION_MCPU},
1744 {"mP", no_argument, NULL, OPTION_POLYMORPHS},
1745 {"mQ", no_argument, NULL, OPTION_RELAX},
1746 {"ml", no_argument, NULL, OPTION_LARGE},
1747 {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS},
1748 {"mn", no_argument, NULL, OPTION_INTR_NOPS},
1749 {"mY", no_argument, NULL, OPTION_NO_WARN_INTR_NOPS},
1750 {"my", no_argument, NULL, OPTION_WARN_INTR_NOPS},
1751 {"mu", no_argument, NULL, OPTION_UNKNOWN_INTR_NOPS},
1752 {"mU", no_argument, NULL, OPTION_NO_UNKNOWN_INTR_NOPS},
1753 {"mdata-region", required_argument, NULL, OPTION_DATA_REGION},
1754 {NULL, no_argument, NULL, 0}
1755 };
1756
1757 size_t md_longopts_size = sizeof (md_longopts);
1758
1759 void
1760 md_show_usage (FILE * stream)
1761 {
1762 fprintf (stream,
1763 _("MSP430 options:\n"
1764 " -mmcu=<msp430-name> - select microcontroller type\n"
1765 " -mcpu={430|430x|430xv2} - select microcontroller architecture\n"));
1766 fprintf (stream,
1767 _(" -msilicon-errata=<name>[,<name>...] - enable fixups for silicon errata\n"
1768 " -msilicon-errata-warn=<name>[,<name>...] - warn when a fixup might be needed\n"
1769 " supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19\n"));
1770 fprintf (stream,
1771 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n"
1772 " -mP - enable polymorph instructions\n"));
1773 fprintf (stream,
1774 _(" -ml - enable large code model\n"));
1775 fprintf (stream,
1776 _(" -mN - do not insert NOPs after changing interrupts (default)\n"));
1777 fprintf (stream,
1778 _(" -mn - insert a NOP after changing interrupts\n"));
1779 fprintf (stream,
1780 _(" -mY - do not warn about missing NOPs after changing interrupts\n"));
1781 fprintf (stream,
1782 _(" -my - warn about missing NOPs after changing interrupts (default)\n"));
1783 fprintf (stream,
1784 _(" -mU - for an instruction which changes interrupt state, but where it is not\n"
1785 " known how the state is changed, do not warn/insert NOPs\n"));
1786 fprintf (stream,
1787 _(" -mu - for an instruction which changes interrupt state, but where it is not\n"
1788 " known how the state is changed, warn/insert NOPs (default)\n"
1789 " -mn and/or -my are required for this to have any effect\n"));
1790 fprintf (stream,
1791 _(" -mdata-region={none|lower|upper|either} - select region data will be\n"
1792 " placed in.\n"));
1793 }
1794
1795 symbolS *
1796 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
1797 {
1798 return NULL;
1799 }
1800
1801 static char *
1802 extract_cmd (char * from, char * to, int limit)
1803 {
1804 int size = 0;
1805
1806 while (*from && ! ISSPACE (*from) && *from != '.' && limit > size)
1807 {
1808 *(to + size) = *from;
1809 from++;
1810 size++;
1811 }
1812
1813 *(to + size) = 0;
1814
1815 return from;
1816 }
1817
1818 const char *
1819 md_atof (int type, char * litP, int * sizeP)
1820 {
1821 return ieee_md_atof (type, litP, sizeP, FALSE);
1822 }
1823
1824 void
1825 md_begin (void)
1826 {
1827 struct msp430_opcode_s * opcode;
1828 msp430_hash = str_htab_create ();
1829
1830 for (opcode = msp430_opcodes; opcode->name; opcode++)
1831 if (str_hash_find (msp430_hash, opcode->name) == NULL)
1832 str_hash_insert (msp430_hash, opcode->name, (char *) opcode);
1833
1834 bfd_set_arch_mach (stdoutput, TARGET_ARCH,
1835 target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11);
1836
1837 /* Set linkrelax here to avoid fixups in most sections. */
1838 linkrelax = 1;
1839 }
1840
1841 static inline bfd_boolean
1842 is_regname_end (char c)
1843 {
1844 return (c == 0 || ! ISALNUM (c));
1845 }
1846
1847 /* Returns the register number equivalent to the string T.
1848 Returns -1 if there is no such register.
1849 Skips a leading 'r' or 'R' character if there is one.
1850 Handles the register aliases PC and SP. */
1851
1852 static signed int
1853 check_reg (char * t)
1854 {
1855 char * endt;
1856 signed long int val;
1857
1858 if (t == NULL || t[0] == 0)
1859 return -1;
1860
1861 if (*t == 'r' || *t == 'R')
1862 ++t;
1863
1864 if (strncasecmp (t, "pc", 2) == 0 && is_regname_end (t[2]))
1865 return 0;
1866
1867 if (strncasecmp (t, "sp", 2) == 0 && is_regname_end (t[2]))
1868 return 1;
1869
1870 if (strncasecmp (t, "sr", 2) == 0 && is_regname_end (t[2]))
1871 return 2;
1872
1873 if (*t == '0' && is_regname_end (t[1]))
1874 return 0;
1875
1876 val = strtol (t, & endt, 0);
1877
1878 if (val < 1 || val > 15)
1879 return -1;
1880
1881 if (is_regname_end (*endt))
1882 return val;
1883
1884 return -1;
1885 }
1886
1887 static int
1888 msp430_srcoperand (struct msp430_operand_s * op,
1889 char * l,
1890 int bin,
1891 bfd_boolean * imm_op,
1892 bfd_boolean allow_20bit_values,
1893 bfd_boolean constants_allowed)
1894 {
1895 char * end;
1896 char *__tl = l;
1897
1898 /* Check if an immediate #VALUE. The hash sign should be only at the beginning! */
1899 if (*l == '#')
1900 {
1901 char *h = l;
1902 int vshift = -1;
1903 int rval = 0;
1904 /* Use all parts of the constant expression by default. */
1905 enum msp430_expp_e expp = MSP_EXPP_ALL;
1906
1907 /* Check if there is:
1908 llo(x) - least significant 16 bits, x &= 0xffff
1909 lhi(x) - x = (x >> 16) & 0xffff,
1910 hlo(x) - x = (x >> 32) & 0xffff,
1911 hhi(x) - x = (x >> 48) & 0xffff
1912 The value _MUST_ be an immediate expression: #hlo(1231231231). */
1913
1914 *imm_op = TRUE;
1915
1916 if (strncasecmp (h, "#llo(", 5) == 0)
1917 {
1918 vshift = 0;
1919 rval = 3;
1920 expp = MSP_EXPP_LLO;
1921 }
1922 else if (strncasecmp (h, "#lhi(", 5) == 0)
1923 {
1924 vshift = 1;
1925 rval = 3;
1926 expp = MSP_EXPP_LHI;
1927 }
1928 else if (strncasecmp (h, "#hlo(", 5) == 0)
1929 {
1930 vshift = 2;
1931 rval = 3;
1932 expp = MSP_EXPP_HLO;
1933 }
1934 else if (strncasecmp (h, "#hhi(", 5) == 0)
1935 {
1936 vshift = 3;
1937 rval = 3;
1938 expp = MSP_EXPP_HHI;
1939 }
1940 else if (strncasecmp (h, "#lo(", 4) == 0)
1941 {
1942 vshift = 0;
1943 rval = 2;
1944 expp = MSP_EXPP_LO;
1945 }
1946 else if (strncasecmp (h, "#hi(", 4) == 0)
1947 {
1948 vshift = 1;
1949 rval = 2;
1950 expp = MSP_EXPP_HI;
1951 }
1952
1953 op->reg = 0; /* Reg PC. */
1954 op->am = 3;
1955 op->ol = 1; /* Immediate will follow an instruction. */
1956 __tl = h + 1 + rval;
1957 op->mode = OP_EXP;
1958 op->vshift = vshift;
1959 op->expp = expp;
1960
1961 end = parse_exp (__tl, &(op->exp));
1962 if (end != NULL && *end != 0 && *end != ')' )
1963 {
1964 as_bad (_("extra characters '%s' at end of immediate expression '%s'"), end, l);
1965 return 1;
1966 }
1967 if (op->exp.X_op == O_constant)
1968 {
1969 int x = op->exp.X_add_number;
1970
1971 if (vshift == 0)
1972 {
1973 x = x & 0xffff;
1974 op->exp.X_add_number = x;
1975 }
1976 else if (vshift == 1)
1977 {
1978 x = (x >> 16) & 0xffff;
1979 op->exp.X_add_number = x;
1980 op->vshift = 0;
1981 }
1982 else if (vshift > 1)
1983 {
1984 if (x < 0)
1985 op->exp.X_add_number = -1;
1986 else
1987 op->exp.X_add_number = 0; /* Nothing left. */
1988 x = op->exp.X_add_number;
1989 op->vshift = 0;
1990 }
1991
1992 if (allow_20bit_values)
1993 {
1994 if (op->exp.X_add_number > 0xfffff || op->exp.X_add_number < -524288)
1995 {
1996 as_bad (_("value 0x%x out of extended range."), x);
1997 return 1;
1998 }
1999 }
2000 else if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)
2001 {
2002 as_bad (_("value %d out of range. Use #lo() or #hi()"), x);
2003 return 1;
2004 }
2005
2006 /* Now check constants. */
2007 /* Substitute register mode with a constant generator if applicable. */
2008
2009 if (!allow_20bit_values)
2010 x = (short) x; /* Extend sign. */
2011
2012 if (! constants_allowed)
2013 ;
2014 else if (x == 0)
2015 {
2016 op->reg = 3;
2017 op->am = 0;
2018 op->ol = 0;
2019 op->mode = OP_REG;
2020 }
2021 else if (x == 1)
2022 {
2023 op->reg = 3;
2024 op->am = 1;
2025 op->ol = 0;
2026 op->mode = OP_REG;
2027 }
2028 else if (x == 2)
2029 {
2030 op->reg = 3;
2031 op->am = 2;
2032 op->ol = 0;
2033 op->mode = OP_REG;
2034 }
2035 else if (x == -1)
2036 {
2037 op->reg = 3;
2038 op->am = 3;
2039 op->ol = 0;
2040 op->mode = OP_REG;
2041 }
2042 else if (x == 4)
2043 {
2044 if (bin == 0x1200 && ! target_is_430x ())
2045 {
2046 /* CPU4: The shorter form of PUSH #4 is not supported on MSP430. */
2047 if (silicon_errata_warn & SILICON_ERRATA_CPU4)
2048 as_warn (_("cpu4: not converting PUSH #4 to shorter form"));
2049 /* No need to check silicon_errata_fixes - this fix is always implemented. */
2050 }
2051 else
2052 {
2053 op->reg = 2;
2054 op->am = 2;
2055 op->ol = 0;
2056 op->mode = OP_REG;
2057 }
2058 }
2059 else if (x == 8)
2060 {
2061 if (bin == 0x1200 && ! target_is_430x ())
2062 {
2063 /* CPU4: The shorter form of PUSH #8 is not supported on MSP430. */
2064 if (silicon_errata_warn & SILICON_ERRATA_CPU4)
2065 as_warn (_("cpu4: not converting PUSH #8 to shorter form"));
2066 }
2067 else
2068 {
2069 op->reg = 2;
2070 op->am = 3;
2071 op->ol = 0;
2072 op->mode = OP_REG;
2073 }
2074 }
2075 }
2076 else if (op->exp.X_op == O_symbol)
2077 {
2078 if (vshift > 1)
2079 as_bad (_("error: unsupported #foo() directive used on symbol"));
2080 op->mode = OP_EXP;
2081 }
2082 else if (op->exp.X_op == O_big)
2083 {
2084 short x;
2085
2086 if (vshift != -1)
2087 {
2088 op->exp.X_op = O_constant;
2089 op->exp.X_add_number = 0xffff & generic_bignum[vshift];
2090 x = op->exp.X_add_number;
2091 op->vshift = 0;
2092 }
2093 else
2094 {
2095 as_bad (_
2096 ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
2097 l);
2098 return 1;
2099 }
2100
2101 if (x == 0)
2102 {
2103 op->reg = 3;
2104 op->am = 0;
2105 op->ol = 0;
2106 op->mode = OP_REG;
2107 }
2108 else if (x == 1)
2109 {
2110 op->reg = 3;
2111 op->am = 1;
2112 op->ol = 0;
2113 op->mode = OP_REG;
2114 }
2115 else if (x == 2)
2116 {
2117 op->reg = 3;
2118 op->am = 2;
2119 op->ol = 0;
2120 op->mode = OP_REG;
2121 }
2122 else if (x == -1)
2123 {
2124 op->reg = 3;
2125 op->am = 3;
2126 op->ol = 0;
2127 op->mode = OP_REG;
2128 }
2129 else if (x == 4)
2130 {
2131 op->reg = 2;
2132 op->am = 2;
2133 op->ol = 0;
2134 op->mode = OP_REG;
2135 }
2136 else if (x == 8)
2137 {
2138 op->reg = 2;
2139 op->am = 3;
2140 op->ol = 0;
2141 op->mode = OP_REG;
2142 }
2143 }
2144 /* Redundant (yet) check. */
2145 else if (op->exp.X_op == O_register)
2146 as_bad
2147 (_("Registers cannot be used within immediate expression [%s]"), l);
2148 else
2149 as_bad (_("unknown operand %s"), l);
2150
2151 return 0;
2152 }
2153
2154 /* Check if absolute &VALUE (assume that we can construct something like ((a&b)<<7 + 25). */
2155 if (*l == '&')
2156 {
2157 char *h = l;
2158
2159 op->reg = 2; /* Reg 2 in absolute addr mode. */
2160 op->am = 1; /* Mode As == 01 bin. */
2161 op->ol = 1; /* Immediate value followed by instruction. */
2162 __tl = h + 1;
2163 end = parse_exp (__tl, &(op->exp));
2164 if (end != NULL && *end != 0)
2165 {
2166 as_bad (_("extra characters '%s' at the end of absolute operand '%s'"), end, l);
2167 return 1;
2168 }
2169 op->mode = OP_EXP;
2170 op->vshift = 0;
2171 op->expp = MSP_EXPP_ALL;
2172 if (op->exp.X_op == O_constant)
2173 {
2174 int x = op->exp.X_add_number;
2175
2176 if (allow_20bit_values)
2177 {
2178 if (x > 0xfffff || x < -(0x7ffff))
2179 {
2180 as_bad (_("value 0x%x out of extended range."), x);
2181 return 1;
2182 }
2183 }
2184 else if (x > 65535 || x < -32768)
2185 {
2186 as_bad (_("value out of range: 0x%x"), x);
2187 return 1;
2188 }
2189 }
2190 else if (op->exp.X_op == O_symbol)
2191 ;
2192 else
2193 {
2194 /* Redundant (yet) check. */
2195 if (op->exp.X_op == O_register)
2196 as_bad
2197 (_("Registers cannot be used within absolute expression [%s]"), l);
2198 else
2199 as_bad (_("unknown expression in operand %s"), l);
2200 return 1;
2201 }
2202 return 0;
2203 }
2204
2205 /* Check if indirect register mode @Rn / postincrement @Rn+. */
2206 if (*l == '@')
2207 {
2208 char *t = l;
2209 char *m = strchr (l, '+');
2210
2211 if (t != l)
2212 {
2213 as_bad (_("unknown addressing mode %s"), l);
2214 return 1;
2215 }
2216
2217 t++;
2218
2219 if ((op->reg = check_reg (t)) == -1)
2220 {
2221 as_bad (_("Bad register name %s"), t);
2222 return 1;
2223 }
2224
2225 op->mode = OP_REG;
2226 op->am = m ? 3 : 2;
2227 op->ol = 0;
2228
2229 /* PC cannot be used in indirect addressing. */
2230 if (target_is_430xv2 () && op->reg == 0)
2231 {
2232 as_bad (_("cannot use indirect addressing with the PC"));
2233 return 1;
2234 }
2235
2236 return 0;
2237 }
2238
2239 /* Check if register indexed X(Rn). */
2240 do
2241 {
2242 char *h = strrchr (l, '(');
2243 char *m = strrchr (l, ')');
2244 char *t;
2245
2246 *imm_op = TRUE;
2247
2248 if (!h)
2249 break;
2250 if (!m)
2251 {
2252 as_bad (_("')' required"));
2253 return 1;
2254 }
2255
2256 t = h;
2257 op->am = 1;
2258 op->ol = 1;
2259
2260 /* Extract a register. */
2261 if ((op->reg = check_reg (t + 1)) == -1)
2262 {
2263 as_bad (_
2264 ("unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"),
2265 l);
2266 return 1;
2267 }
2268
2269 if (op->reg == 2)
2270 {
2271 as_bad (_("r2 should not be used in indexed addressing mode"));
2272 return 1;
2273 }
2274
2275 /* Extract constant. */
2276 __tl = l;
2277 *h = 0;
2278 op->mode = OP_EXP;
2279 op->vshift = 0;
2280 op->expp = MSP_EXPP_ALL;
2281 end = parse_exp (__tl, &(op->exp));
2282 if (end != NULL && *end != 0)
2283 {
2284 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
2285 return 1;
2286 }
2287 if (op->exp.X_op == O_constant)
2288 {
2289 int x = op->exp.X_add_number;
2290
2291 if (allow_20bit_values)
2292 {
2293 if (x > 0xfffff || x < - (0x7ffff))
2294 {
2295 as_bad (_("value 0x%x out of extended range."), x);
2296 return 1;
2297 }
2298 }
2299 else if (x > 65535 || x < -32768)
2300 {
2301 as_bad (_("value out of range: 0x%x"), x);
2302 return 1;
2303 }
2304
2305 if (x == 0)
2306 {
2307 op->mode = OP_REG;
2308 op->am = 2;
2309 op->ol = 0;
2310 return 0;
2311 }
2312
2313 if (op->reg == 1 && (x & 1))
2314 {
2315 if (silicon_errata_fix & SILICON_ERRATA_CPU8)
2316 as_bad (_("CPU8: Stack pointer accessed with an odd offset"));
2317 else if (silicon_errata_warn & SILICON_ERRATA_CPU8)
2318 as_warn (_("CPU8: Stack pointer accessed with an odd offset"));
2319 }
2320 }
2321 else if (op->exp.X_op == O_symbol)
2322 ;
2323 else
2324 {
2325 /* Redundant (yet) check. */
2326 if (op->exp.X_op == O_register)
2327 as_bad
2328 (_("Registers cannot be used as a prefix of indexed expression [%s]"), l);
2329 else
2330 as_bad (_("unknown expression in operand %s"), l);
2331 return 1;
2332 }
2333
2334 return 0;
2335 }
2336 while (0);
2337
2338 /* Possibly register mode 'mov r1,r2'. */
2339 if ((op->reg = check_reg (l)) != -1)
2340 {
2341 op->mode = OP_REG;
2342 op->am = 0;
2343 op->ol = 0;
2344 return 0;
2345 }
2346
2347 /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'. */
2348 op->mode = OP_EXP;
2349 op->reg = 0; /* PC relative... be careful. */
2350 /* An expression starting with a minus sign is a constant, not an address. */
2351 op->am = (*l == '-' ? 3 : 1);
2352 op->ol = 1;
2353 op->vshift = 0;
2354 op->expp = MSP_EXPP_ALL;
2355 __tl = l;
2356 end = parse_exp (__tl, &(op->exp));
2357 if (end != NULL && * end != 0)
2358 {
2359 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l);
2360 return 1;
2361 }
2362 return 0;
2363 }
2364
2365
2366 static int
2367 msp430_dstoperand (struct msp430_operand_s * op,
2368 char * l,
2369 int bin,
2370 bfd_boolean allow_20bit_values,
2371 bfd_boolean constants_allowed)
2372 {
2373 int dummy;
2374 int ret = msp430_srcoperand (op, l, bin, & dummy,
2375 allow_20bit_values,
2376 constants_allowed);
2377
2378 if (ret)
2379 return ret;
2380
2381 if (op->am == 2)
2382 {
2383 char *__tl = (char *) "0";
2384
2385 op->mode = OP_EXP;
2386 op->am = 1;
2387 op->ol = 1;
2388 op->vshift = 0;
2389 op->expp = MSP_EXPP_ALL;
2390 (void) parse_exp (__tl, &(op->exp));
2391
2392 if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
2393 {
2394 as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
2395 op->reg, op->reg);
2396 return 1;
2397 }
2398 return 0;
2399 }
2400
2401 if (op->am > 1)
2402 {
2403 as_bad (_
2404 ("this addressing mode is not applicable for destination operand"));
2405 return 1;
2406 }
2407 return 0;
2408 }
2409
2410 /* Attempt to encode a MOVA instruction with the given operands.
2411 Returns the length of the encoded instruction if successful
2412 or 0 upon failure. If the encoding fails, an error message
2413 will be returned if a pointer is provided. */
2414
2415 static int
2416 try_encode_mova (bfd_boolean imm_op,
2417 int bin,
2418 struct msp430_operand_s * op1,
2419 struct msp430_operand_s * op2,
2420 const char ** error_message_return)
2421 {
2422 short ZEROS = 0;
2423 char *frag;
2424 int where;
2425
2426 /* Only a restricted subset of the normal MSP430 addressing modes
2427 are supported here, so check for the ones that are allowed. */
2428 if (imm_op)
2429 {
2430 if (op1->mode == OP_EXP)
2431 {
2432 if (op2->mode != OP_REG)
2433 {
2434 if (error_message_return != NULL)
2435 * error_message_return = _("expected register as second argument of %s");
2436 return 0;
2437 }
2438
2439 if (op1->am == 3)
2440 {
2441 /* MOVA #imm20, Rdst. */
2442 bin |= 0x80 | op2->reg;
2443 frag = frag_more (4);
2444 where = frag - frag_now->fr_literal;
2445 if (op1->exp.X_op == O_constant)
2446 {
2447 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
2448 bfd_putl16 ((bfd_vma) bin, frag);
2449 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2450 }
2451 else
2452 {
2453 bfd_putl16 ((bfd_vma) bin, frag);
2454 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
2455 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
2456 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2457 }
2458
2459 return 4;
2460 }
2461 else if (op1->am == 1)
2462 {
2463 /* MOVA z16(Rsrc), Rdst. */
2464 bin |= 0x30 | (op1->reg << 8) | op2->reg;
2465 frag = frag_more (4);
2466 where = frag - frag_now->fr_literal;
2467 bfd_putl16 ((bfd_vma) bin, frag);
2468 if (op1->exp.X_op == O_constant)
2469 {
2470 if (op1->exp.X_add_number > 0xffff
2471 || op1->exp.X_add_number < -(0x7fff))
2472 {
2473 if (error_message_return != NULL)
2474 * error_message_return = _("index value too big for %s");
2475 return 0;
2476 }
2477 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2478 }
2479 else
2480 {
2481 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2482 fix_new_exp (frag_now, where + 2, 2, &(op1->exp), FALSE,
2483 op1->reg == 0 ?
2484 BFD_RELOC_MSP430X_PCR16 :
2485 BFD_RELOC_MSP430X_ABS16);
2486 }
2487 return 4;
2488 }
2489
2490 if (error_message_return != NULL)
2491 * error_message_return = _("unexpected addressing mode for %s");
2492 return 0;
2493 }
2494 else if (op1->am == 0)
2495 {
2496 /* MOVA Rsrc, ... */
2497 if (op2->mode == OP_REG)
2498 {
2499 bin |= 0xc0 | (op1->reg << 8) | op2->reg;
2500 frag = frag_more (2);
2501 where = frag - frag_now->fr_literal;
2502 bfd_putl16 ((bfd_vma) bin, frag);
2503 return 2;
2504 }
2505 else if (op2->am == 1)
2506 {
2507 if (op2->reg == 2)
2508 {
2509 /* MOVA Rsrc, &abs20. */
2510 bin |= 0x60 | (op1->reg << 8);
2511 frag = frag_more (4);
2512 where = frag - frag_now->fr_literal;
2513 if (op2->exp.X_op == O_constant)
2514 {
2515 bin |= (op2->exp.X_add_number >> 16) & 0xf;
2516 bfd_putl16 ((bfd_vma) bin, frag);
2517 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
2518 }
2519 else
2520 {
2521 bfd_putl16 ((bfd_vma) bin, frag);
2522 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2523 fix_new_exp (frag_now, where, 4, &(op2->exp), FALSE,
2524 BFD_RELOC_MSP430X_ABS20_ADR_DST);
2525 }
2526 return 4;
2527 }
2528
2529 /* MOVA Rsrc, z16(Rdst). */
2530 bin |= 0x70 | (op1->reg << 8) | op2->reg;
2531 frag = frag_more (4);
2532 where = frag - frag_now->fr_literal;
2533 bfd_putl16 ((bfd_vma) bin, frag);
2534 if (op2->exp.X_op == O_constant)
2535 {
2536 if (op2->exp.X_add_number > 0xffff
2537 || op2->exp.X_add_number < -(0x7fff))
2538 {
2539 if (error_message_return != NULL)
2540 * error_message_return = _("index value too big for %s");
2541 return 0;
2542 }
2543 bfd_putl16 (op2->exp.X_add_number & 0xffff, frag + 2);
2544 }
2545 else
2546 {
2547 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2548 fix_new_exp (frag_now, where + 2, 2, &(op2->exp), FALSE,
2549 op2->reg == 0 ?
2550 BFD_RELOC_MSP430X_PCR16 :
2551 BFD_RELOC_MSP430X_ABS16);
2552 }
2553 return 4;
2554 }
2555
2556 if (error_message_return != NULL)
2557 * error_message_return = _("unexpected addressing mode for %s");
2558 return 0;
2559 }
2560 }
2561
2562 /* imm_op == FALSE. */
2563
2564 if (op1->reg == 2 && op1->am == 1 && op1->mode == OP_EXP)
2565 {
2566 /* MOVA &abs20, Rdst. */
2567 if (op2->mode != OP_REG)
2568 {
2569 if (error_message_return != NULL)
2570 * error_message_return = _("expected register as second argument of %s");
2571 return 0;
2572 }
2573
2574 if (op2->reg == 2 || op2->reg == 3)
2575 {
2576 if (error_message_return != NULL)
2577 * error_message_return = _("constant generator destination register found in %s");
2578 return 0;
2579 }
2580
2581 bin |= 0x20 | op2->reg;
2582 frag = frag_more (4);
2583 where = frag - frag_now->fr_literal;
2584 if (op1->exp.X_op == O_constant)
2585 {
2586 bin |= ((op1->exp.X_add_number >> 16) & 0xf) << 8;
2587 bfd_putl16 ((bfd_vma) bin, frag);
2588 bfd_putl16 (op1->exp.X_add_number & 0xffff, frag + 2);
2589 }
2590 else
2591 {
2592 bfd_putl16 ((bfd_vma) bin, frag);
2593 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
2594 fix_new_exp (frag_now, where, 4, &(op1->exp), FALSE,
2595 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
2596 }
2597 return 4;
2598 }
2599 else if (op1->mode == OP_REG)
2600 {
2601 if (op1->am == 3)
2602 {
2603 /* MOVA @Rsrc+, Rdst. */
2604 if (op2->mode != OP_REG)
2605 {
2606 if (error_message_return != NULL)
2607 * error_message_return = _("expected register as second argument of %s");
2608 return 0;
2609 }
2610
2611 if (op2->reg == 2 || op2->reg == 3)
2612 {
2613 if (error_message_return != NULL)
2614 * error_message_return = _("constant generator destination register found in %s");
2615 return 0;
2616 }
2617
2618 if (op1->reg == 2 || op1->reg == 3)
2619 {
2620 if (error_message_return != NULL)
2621 * error_message_return = _("constant generator source register found in %s");
2622 return 0;
2623 }
2624
2625 bin |= 0x10 | (op1->reg << 8) | op2->reg;
2626 frag = frag_more (2);
2627 where = frag - frag_now->fr_literal;
2628 bfd_putl16 ((bfd_vma) bin, frag);
2629 return 2;
2630 }
2631 else if (op1->am == 2)
2632 {
2633 /* MOVA @Rsrc,Rdst */
2634 if (op2->mode != OP_REG)
2635 {
2636 if (error_message_return != NULL)
2637 * error_message_return = _("expected register as second argument of %s");
2638 return 0;
2639 }
2640
2641 if (op2->reg == 2 || op2->reg == 3)
2642 {
2643 if (error_message_return != NULL)
2644 * error_message_return = _("constant generator destination register found in %s");
2645 return 0;
2646 }
2647
2648 if (op1->reg == 2 || op1->reg == 3)
2649 {
2650 if (error_message_return != NULL)
2651 * error_message_return = _("constant generator source register found in %s");
2652 return 0;
2653 }
2654
2655 bin |= (op1->reg << 8) | op2->reg;
2656 frag = frag_more (2);
2657 where = frag - frag_now->fr_literal;
2658 bfd_putl16 ((bfd_vma) bin, frag);
2659 return 2;
2660 }
2661 }
2662
2663 if (error_message_return != NULL)
2664 * error_message_return = _("unexpected addressing mode for %s");
2665
2666 return 0;
2667 }
2668
2669 #define NOP_CHECK_INTERRUPT (1 << 0)
2670 #define NOP_CHECK_CPU12 (1 << 1)
2671 #define NOP_CHECK_CPU19 (1 << 2)
2672
2673 static signed int check_for_nop = 0;
2674
2675 #define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0)
2676
2677 /* is_{e,d}int only check the explicit enabling/disabling of interrupts.
2678 For MOV insns, more sophisticated processing is needed to determine if they
2679 result in enabling/disabling interrupts. */
2680 #define is_dint(OPCODE, BIN) ((strcmp (OPCODE, "dint") == 0) \
2681 || ((strcmp (OPCODE, "bic") == 0) \
2682 && BIN == 0xc232) \
2683 || ((strcmp (OPCODE, "clr") == 0) \
2684 && BIN == 0x4302))
2685
2686 #define is_eint(OPCODE, BIN) ((strcmp (OPCODE, "eint") == 0) \
2687 || ((strcmp (OPCODE, "bis") == 0) \
2688 && BIN == 0xd232))
2689
2690 const char * const INSERT_NOP_BEFORE_EINT = "NOP inserted here, before an interrupt enable instruction";
2691 const char * const INSERT_NOP_AFTER_DINT = "NOP inserted here, after an interrupt disable instruction";
2692 const char * const INSERT_NOP_AFTER_EINT = "NOP inserted here, after an interrupt enable instruction";
2693 const char * const INSERT_NOP_BEFORE_UNKNOWN = "NOP inserted here, before this interrupt state change";
2694 const char * const INSERT_NOP_AFTER_UNKNOWN ="NOP inserted here, after the instruction that changed interrupt state";
2695 const char * const INSERT_NOP_AT_EOF = "NOP inserted after the interrupt state change at the end of the file";
2696
2697 const char * const WARN_NOP_BEFORE_EINT = "a NOP might be needed here, before an interrupt enable instruction";
2698 const char * const WARN_NOP_AFTER_DINT = "a NOP might be needed here, after an interrupt disable instruction";
2699 const char * const WARN_NOP_AFTER_EINT = "a NOP might be needed here, after an interrupt enable instruction";
2700 const char * const WARN_NOP_BEFORE_UNKNOWN = "a NOP might be needed here, before this interrupt state change";
2701 const char * const WARN_NOP_AFTER_UNKNOWN = "a NOP might also be needed here, after the instruction that changed interrupt state";
2702 const char * const WARN_NOP_AT_EOF = "a NOP might be needed after the interrupt state change at the end of the file";
2703
2704 static void
2705 gen_nop (void)
2706 {
2707 char *frag;
2708 frag = frag_more (2);
2709 bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag);
2710 dwarf2_emit_insn (2);
2711 }
2712
2713 /* Insert/inform about adding a NOP if this insn enables interrupts. */
2714
2715 static void
2716 warn_eint_nop (bfd_boolean prev_insn_is_nop, bfd_boolean prev_insn_is_dint)
2717 {
2718 if (prev_insn_is_nop
2719 /* If the last insn was a DINT, we will have already warned that a NOP is
2720 required after it. */
2721 || prev_insn_is_dint
2722 /* 430 ISA does not require a NOP before EINT. */
2723 || (! target_is_430x ()))
2724 return;
2725
2726 if (gen_interrupt_nops)
2727 {
2728 gen_nop ();
2729 if (warn_interrupt_nops)
2730 as_warn (_(INSERT_NOP_BEFORE_EINT));
2731 }
2732 else if (warn_interrupt_nops)
2733 as_warn (_(WARN_NOP_BEFORE_EINT));
2734 }
2735
2736 /* Use when unsure what effect the insn will have on the interrupt status,
2737 to insert/warn about adding a NOP before the current insn. */
2738
2739 static void
2740 warn_unsure_interrupt (bfd_boolean prev_insn_is_nop,
2741 bfd_boolean prev_insn_is_dint)
2742 {
2743 if (prev_insn_is_nop
2744 /* If the last insn was a DINT, we will have already warned that a NOP is
2745 required after it. */
2746 || prev_insn_is_dint
2747 /* 430 ISA does not require a NOP before EINT or DINT. */
2748 || (! target_is_430x ()))
2749 return;
2750
2751 if (gen_interrupt_nops)
2752 {
2753 gen_nop ();
2754 if (warn_interrupt_nops)
2755 as_warn (_(INSERT_NOP_BEFORE_UNKNOWN));
2756 }
2757 else if (warn_interrupt_nops)
2758 as_warn (_(WARN_NOP_BEFORE_UNKNOWN));
2759 }
2760
2761 /* Parse instruction operands.
2762 Return binary opcode. */
2763
2764 static unsigned int
2765 msp430_operands (struct msp430_opcode_s * opcode, char * line)
2766 {
2767 int bin = opcode->bin_opcode; /* Opcode mask. */
2768 int insn_length = 0;
2769 char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
2770 char *frag;
2771 char *end;
2772 int where;
2773 struct msp430_operand_s op1, op2;
2774 int res = 0;
2775 static short ZEROS = 0;
2776 bfd_boolean byte_op, imm_op;
2777 int op_length = 0;
2778 int fmt;
2779 int extended = 0x1800;
2780 bfd_boolean extended_op = FALSE;
2781 bfd_boolean addr_op;
2782 const char * error_message;
2783 static signed int repeat_count = 0;
2784 static bfd_boolean prev_insn_is_nop = FALSE;
2785 static bfd_boolean prev_insn_is_dint = FALSE;
2786 static bfd_boolean prev_insn_is_eint = FALSE;
2787 /* We might decide before the end of the function that the current insn is
2788 equivalent to DINT/EINT. */
2789 bfd_boolean this_insn_is_dint = FALSE;
2790 bfd_boolean this_insn_is_eint = FALSE;
2791 bfd_boolean fix_emitted;
2792
2793 /* Opcode is the one from opcodes table
2794 line contains something like
2795 [.w] @r2+, 5(R1)
2796 or
2797 .b @r2+, 5(R1). */
2798
2799 byte_op = FALSE;
2800 addr_op = FALSE;
2801 if (*line == '.')
2802 {
2803 bfd_boolean check = FALSE;
2804 ++ line;
2805
2806 switch (TOLOWER (* line))
2807 {
2808 case 'b':
2809 /* Byte operation. */
2810 bin |= BYTE_OPERATION;
2811 byte_op = TRUE;
2812 check = TRUE;
2813 break;
2814
2815 case 'a':
2816 /* "Address" ops work on 20-bit values. */
2817 addr_op = TRUE;
2818 bin |= BYTE_OPERATION;
2819 check = TRUE;
2820 break;
2821
2822 case 'w':
2823 /* Word operation - this is the default. */
2824 check = TRUE;
2825 break;
2826
2827 case 0:
2828 case ' ':
2829 case '\n':
2830 case '\r':
2831 as_warn (_("no size modifier after period, .w assumed"));
2832 break;
2833
2834 default:
2835 as_bad (_("unrecognised instruction size modifier .%c"),
2836 * line);
2837 return 0;
2838 }
2839
2840 if (check)
2841 {
2842 ++ line;
2843
2844 }
2845 }
2846
2847 if (*line && ! ISSPACE (*line))
2848 {
2849 as_bad (_("junk found after instruction: %s.%s"),
2850 opcode->name, line);
2851 return 0;
2852 }
2853
2854 /* Catch the case where the programmer has used a ".a" size modifier on an
2855 instruction that does not support it. Look for an alternative extended
2856 instruction that has the same name without the period. Eg: "add.a"
2857 becomes "adda". Although this not an officially supported way of
2858 specifying instruction aliases other MSP430 assemblers allow it. So we
2859 support it for compatibility purposes. */
2860 if (addr_op && opcode->fmt >= 0)
2861 {
2862 const char * old_name = opcode->name;
2863 char real_name[32];
2864
2865 sprintf (real_name, "%sa", old_name);
2866 opcode = str_hash_find (msp430_hash, real_name);
2867 if (opcode == NULL)
2868 {
2869 as_bad (_("instruction %s.a does not exist"), old_name);
2870 return 0;
2871 }
2872 #if 0 /* Enable for debugging. */
2873 as_warn ("treating %s.a as %s", old_name, real_name);
2874 #endif
2875 addr_op = FALSE;
2876 bin = opcode->bin_opcode;
2877 }
2878
2879 if (opcode->fmt != -1
2880 && opcode->insn_opnumb
2881 && (!*line || *line == '\n'))
2882 {
2883 as_bad (ngettext ("instruction %s requires %d operand",
2884 "instruction %s requires %d operands",
2885 opcode->insn_opnumb),
2886 opcode->name, opcode->insn_opnumb);
2887 return 0;
2888 }
2889
2890 memset (l1, 0, sizeof (l1));
2891 memset (l2, 0, sizeof (l2));
2892 memset (&op1, 0, sizeof (op1));
2893 memset (&op2, 0, sizeof (op2));
2894
2895 imm_op = FALSE;
2896
2897 if ((fmt = opcode->fmt) < 0)
2898 {
2899 if (! target_is_430x ())
2900 {
2901 as_bad (_("instruction %s requires MSP430X mcu"),
2902 opcode->name);
2903 return 0;
2904 }
2905
2906 fmt = (-fmt) - 1;
2907 extended_op = TRUE;
2908 }
2909
2910 if (repeat_count)
2911 {
2912 /* If requested set the extended instruction repeat count. */
2913 if (extended_op)
2914 {
2915 if (repeat_count > 0)
2916 extended |= (repeat_count - 1);
2917 else
2918 extended |= (1 << 7) | (- repeat_count);
2919 }
2920 else
2921 as_bad (_("unable to repeat %s insn"), opcode->name);
2922
2923 repeat_count = 0;
2924 }
2925
2926 /* The previous instruction set this flag if it wants to check if this insn
2927 is a NOP. */
2928 if (check_for_nop)
2929 {
2930 if (! is_opcode ("nop"))
2931 {
2932 do
2933 {
2934 switch (check_for_nop & - check_for_nop)
2935 {
2936 case NOP_CHECK_INTERRUPT:
2937 /* NOP_CHECK_INTERRUPT rules:
2938 1. 430 and 430x ISA require a NOP after DINT.
2939 2. Only the 430x ISA requires NOP before EINT (this has
2940 been dealt with in the previous call to this function).
2941 3. Only the 430x ISA requires NOP after every EINT.
2942 CPU42 errata. */
2943 if (gen_interrupt_nops || warn_interrupt_nops)
2944 {
2945 if (prev_insn_is_dint)
2946 {
2947 if (gen_interrupt_nops)
2948 {
2949 gen_nop ();
2950 if (warn_interrupt_nops)
2951 as_warn (_(INSERT_NOP_AFTER_DINT));
2952 }
2953 else
2954 as_warn (_(WARN_NOP_AFTER_DINT));
2955 }
2956 else if (prev_insn_is_eint)
2957 {
2958 if (gen_interrupt_nops)
2959 {
2960 gen_nop ();
2961 if (warn_interrupt_nops)
2962 as_warn (_(INSERT_NOP_AFTER_EINT));
2963 }
2964 else
2965 as_warn (_(WARN_NOP_AFTER_EINT));
2966 }
2967 /* If we get here it's because the last instruction was
2968 determined to either disable or enable interrupts, but
2969 we're not sure which.
2970 We have no information yet about what effect the
2971 current instruction has on interrupts, that has to be
2972 sorted out later.
2973 The last insn may have required a NOP after it, so we
2974 deal with that now. */
2975 else
2976 {
2977 if (gen_interrupt_nops)
2978 {
2979 gen_nop ();
2980 if (warn_interrupt_nops)
2981 as_warn (_(INSERT_NOP_AFTER_UNKNOWN));
2982 }
2983 else
2984 /* warn_unsure_interrupt was called on the previous
2985 insn. */
2986 as_warn (_(WARN_NOP_AFTER_UNKNOWN));
2987 }
2988 }
2989 break;
2990
2991 case NOP_CHECK_CPU12:
2992 if (silicon_errata_warn & SILICON_ERRATA_CPU12)
2993 as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
2994
2995 if (silicon_errata_fix & SILICON_ERRATA_CPU12)
2996 gen_nop ();
2997 break;
2998
2999 case NOP_CHECK_CPU19:
3000 if (silicon_errata_warn & SILICON_ERRATA_CPU19)
3001 as_warn (_("CPU19: Instruction setting CPUOFF must be followed by a NOP"));
3002
3003 if (silicon_errata_fix & SILICON_ERRATA_CPU19)
3004 gen_nop ();
3005 break;
3006
3007 default:
3008 as_bad (_("internal error: unknown nop check state"));
3009 break;
3010 }
3011 check_for_nop &= ~ (check_for_nop & - check_for_nop);
3012 }
3013 while (check_for_nop);
3014 }
3015 check_for_nop = 0;
3016 }
3017
3018 switch (fmt)
3019 {
3020 case 0:
3021 /* Emulated. */
3022 switch (opcode->insn_opnumb)
3023 {
3024 case 0:
3025 if (is_opcode ("eint"))
3026 warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
3027
3028 /* Set/clear bits instructions. */
3029 if (extended_op)
3030 {
3031 if (!addr_op)
3032 extended |= BYTE_OPERATION;
3033
3034 /* Emit the extension word. */
3035 insn_length += 2;
3036 frag = frag_more (2);
3037 bfd_putl16 (extended, frag);
3038 }
3039
3040 insn_length += 2;
3041 frag = frag_more (2);
3042 bfd_putl16 ((bfd_vma) bin, frag);
3043 dwarf2_emit_insn (insn_length);
3044 break;
3045
3046 case 1:
3047 /* Something which works with destination operand. */
3048 line = extract_operand (line, l1, sizeof (l1));
3049 res = msp430_dstoperand (&op1, l1, opcode->bin_opcode, extended_op, TRUE);
3050 if (res)
3051 break;
3052
3053 bin |= (op1.reg | (op1.am << 7));
3054
3055 /* If the PC is the destination... */
3056 if (op1.am == 0 && op1.reg == 0
3057 /* ... and the opcode alters the SR. */
3058 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
3059 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
3060 {
3061 if (silicon_errata_fix & SILICON_ERRATA_CPU11)
3062 as_bad (_("CPU11: PC is destination of SR altering instruction"));
3063 else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
3064 as_warn (_("CPU11: PC is destination of SR altering instruction"));
3065 }
3066
3067 /* If the status register is the destination... */
3068 if (op1.am == 0 && op1.reg == 2
3069 /* ... and the opcode alters the SR. */
3070 && (is_opcode ("adc") || is_opcode ("dec") || is_opcode ("decd")
3071 || is_opcode ("inc") || is_opcode ("incd") || is_opcode ("inv")
3072 || is_opcode ("sbc") || is_opcode ("sxt")
3073 || is_opcode ("adcx") || is_opcode ("decx") || is_opcode ("decdx")
3074 || is_opcode ("incx") || is_opcode ("incdx") || is_opcode ("invx")
3075 || is_opcode ("sbcx")
3076 ))
3077 {
3078 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
3079 as_bad (_("CPU13: SR is destination of SR altering instruction"));
3080 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
3081 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3082 }
3083
3084 /* Compute the entire instruction length, in bytes. */
3085 op_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
3086 insn_length += op_length;
3087 frag = frag_more (op_length);
3088 where = frag - frag_now->fr_literal;
3089
3090 if (extended_op)
3091 {
3092 if (!addr_op)
3093 extended |= BYTE_OPERATION;
3094
3095 if (op1.ol != 0 && ((extended & 0xf) != 0))
3096 {
3097 as_bad (_("repeat instruction used with non-register mode instruction"));
3098 extended &= ~ 0xf;
3099 }
3100
3101 if (op1.mode == OP_EXP)
3102 {
3103 if (op1.exp.X_op == O_constant)
3104 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
3105
3106 else if (op1.reg || op1.am == 3) /* Not PC relative. */
3107 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3108 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
3109 else
3110 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3111 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
3112 }
3113
3114 /* Emit the extension word. */
3115 bfd_putl16 (extended, frag);
3116 frag += 2;
3117 where += 2;
3118 }
3119
3120 bfd_putl16 ((bfd_vma) bin, frag);
3121 frag += 2;
3122 where += 2;
3123
3124 if (op1.mode == OP_EXP)
3125 {
3126 if (op1.exp.X_op == O_constant)
3127 {
3128 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
3129 }
3130 else
3131 {
3132 bfd_putl16 ((bfd_vma) ZEROS, frag);
3133
3134 if (!extended_op)
3135 {
3136 if (op1.reg)
3137 fix_new_exp (frag_now, where, 2,
3138 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
3139 else
3140 fix_new_exp (frag_now, where, 2,
3141 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3142 }
3143 }
3144 }
3145
3146 dwarf2_emit_insn (insn_length);
3147 break;
3148
3149 case 2:
3150 /* Shift instruction. */
3151 line = extract_operand (line, l1, sizeof (l1));
3152 strncpy (l2, l1, sizeof (l2));
3153 l2[sizeof (l2) - 1] = '\0';
3154 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
3155 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
3156
3157 if (res)
3158 break; /* An error occurred. All warnings were done before. */
3159
3160 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2) + (op2.ol * 2);
3161 frag = frag_more (insn_length);
3162 where = frag - frag_now->fr_literal;
3163
3164 if (target_is_430xv2 ()
3165 && op1.mode == OP_REG
3166 && op1.reg == 0
3167 && (is_opcode ("rlax")
3168 || is_opcode ("rlcx")
3169 || is_opcode ("rla")
3170 || is_opcode ("rlc")))
3171 {
3172 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
3173 break;
3174 }
3175
3176 /* If the status register is the destination... */
3177 if (op1.am == 0 && op1.reg == 2
3178 /* ... and the opcode alters the SR. */
3179 && (is_opcode ("rla") || is_opcode ("rlc")
3180 || is_opcode ("rlax") || is_opcode ("rlcx")
3181 || is_opcode ("sxt") || is_opcode ("sxtx")
3182 || is_opcode ("swpb")
3183 ))
3184 {
3185 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
3186 as_bad (_("CPU13: SR is destination of SR altering instruction"));
3187 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
3188 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3189 }
3190
3191 if (extended_op)
3192 {
3193 if (!addr_op)
3194 extended |= BYTE_OPERATION;
3195
3196 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
3197 {
3198 as_bad (_("repeat instruction used with non-register mode instruction"));
3199 extended &= ~ 0xf;
3200 }
3201
3202 if (op1.mode == OP_EXP)
3203 {
3204 if (op1.exp.X_op == O_constant)
3205 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
3206
3207 else if (op1.reg || op1.am == 3) /* Not PC relative. */
3208 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3209 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
3210 else
3211 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3212 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
3213 }
3214
3215 if (op2.mode == OP_EXP)
3216 {
3217 if (op2.exp.X_op == O_constant)
3218 extended |= (op2.exp.X_add_number >> 16) & 0xf;
3219
3220 else if (op1.mode == OP_EXP)
3221 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
3222 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
3223 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
3224 else
3225 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
3226 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
3227 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
3228 }
3229
3230 /* Emit the extension word. */
3231 bfd_putl16 (extended, frag);
3232 frag += 2;
3233 where += 2;
3234 }
3235
3236 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
3237 bfd_putl16 ((bfd_vma) bin, frag);
3238 frag += 2;
3239 where += 2;
3240
3241 if (op1.mode == OP_EXP)
3242 {
3243 if (op1.exp.X_op == O_constant)
3244 {
3245 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
3246 }
3247 else
3248 {
3249 bfd_putl16 ((bfd_vma) ZEROS, frag);
3250
3251 if (!extended_op)
3252 {
3253 if (op1.reg || op1.am == 3) /* Not PC relative. */
3254 fix_new_exp (frag_now, where, 2,
3255 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
3256 else
3257 fix_new_exp (frag_now, where, 2,
3258 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3259 }
3260 }
3261 frag += 2;
3262 where += 2;
3263 }
3264
3265 if (op2.mode == OP_EXP)
3266 {
3267 if (op2.exp.X_op == O_constant)
3268 {
3269 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
3270 }
3271 else
3272 {
3273 bfd_putl16 ((bfd_vma) ZEROS, frag);
3274
3275 if (!extended_op)
3276 {
3277 if (op2.reg) /* Not PC relative. */
3278 fix_new_exp (frag_now, where, 2,
3279 &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
3280 else
3281 fix_new_exp (frag_now, where, 2,
3282 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3283 }
3284 }
3285 }
3286
3287 dwarf2_emit_insn (insn_length);
3288 break;
3289
3290 case 3:
3291 /* Branch instruction => mov dst, r0. */
3292 if (extended_op)
3293 {
3294 as_bad ("Internal error: state 0/3 not coded for extended instructions");
3295 break;
3296 }
3297
3298 line = extract_operand (line, l1, sizeof (l1));
3299 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, FALSE);
3300 if (res)
3301 break;
3302
3303 byte_op = FALSE;
3304 imm_op = FALSE;
3305 bin |= ((op1.reg << 8) | (op1.am << 4));
3306 op_length = 2 + 2 * op1.ol;
3307 frag = frag_more (op_length);
3308 where = frag - frag_now->fr_literal;
3309 bfd_putl16 ((bfd_vma) bin, frag);
3310
3311 if (op1.mode == OP_EXP)
3312 {
3313 if (op1.exp.X_op == O_constant)
3314 {
3315 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag + 2);
3316 }
3317 else
3318 {
3319 where += 2;
3320
3321 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
3322
3323 if (op1.reg || op1.am == 3)
3324 fix_new_exp (frag_now, where, 2,
3325 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
3326 else
3327 fix_new_exp (frag_now, where, 2,
3328 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3329 }
3330 }
3331
3332 dwarf2_emit_insn (insn_length + op_length);
3333 break;
3334
3335 case 4:
3336 /* CALLA instructions. */
3337 fix_emitted = FALSE;
3338
3339 line = extract_operand (line, l1, sizeof (l1));
3340 imm_op = FALSE;
3341
3342 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op,
3343 extended_op, FALSE);
3344 if (res)
3345 break;
3346
3347 byte_op = FALSE;
3348
3349 op_length = 2 + 2 * op1.ol;
3350 frag = frag_more (op_length);
3351 where = frag - frag_now->fr_literal;
3352
3353 if (imm_op)
3354 {
3355 if (op1.am == 3)
3356 {
3357 bin |= 0xb0;
3358
3359 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3360 BFD_RELOC_MSP430X_ABS20_ADR_DST);
3361 fix_emitted = TRUE;
3362 }
3363 else if (op1.am == 1)
3364 {
3365 if (op1.reg == 0)
3366 {
3367 bin |= 0x90;
3368
3369 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3370 BFD_RELOC_MSP430X_PCR20_CALL);
3371 fix_emitted = TRUE;
3372 }
3373 else
3374 bin |= 0x50 | op1.reg;
3375 }
3376 else if (op1.am == 0)
3377 bin |= 0x40 | op1.reg;
3378 }
3379 else if (op1.am == 1)
3380 {
3381 bin |= 0x80;
3382
3383 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3384 BFD_RELOC_MSP430X_ABS20_ADR_DST);
3385 fix_emitted = TRUE;
3386 }
3387 else if (op1.am == 2)
3388 bin |= 0x60 | op1.reg;
3389 else if (op1.am == 3)
3390 bin |= 0x70 | op1.reg;
3391
3392 bfd_putl16 ((bfd_vma) bin, frag);
3393
3394 if (op1.mode == OP_EXP)
3395 {
3396 if (op1.ol != 1)
3397 {
3398 as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1.ol);
3399 break;
3400 }
3401
3402 bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
3403
3404 if (! fix_emitted)
3405 fix_new_exp (frag_now, where + 2, 2,
3406 &(op1.exp), FALSE, BFD_RELOC_16);
3407 }
3408
3409 dwarf2_emit_insn (insn_length + op_length);
3410 break;
3411
3412 case 5:
3413 {
3414 int n;
3415 int reg;
3416
3417 /* [POP|PUSH]M[.A] #N, Rd */
3418 line = extract_operand (line, l1, sizeof (l1));
3419 line = extract_operand (line, l2, sizeof (l2));
3420
3421 if (*l1 != '#')
3422 {
3423 as_bad (_("expected #n as first argument of %s"), opcode->name);
3424 break;
3425 }
3426 end = parse_exp (l1 + 1, &(op1.exp));
3427 if (end != NULL && *end != 0)
3428 {
3429 as_bad (_("extra characters '%s' at end of constant expression '%s'"), end, l1);
3430 break;
3431 }
3432 if (op1.exp.X_op != O_constant)
3433 {
3434 as_bad (_("expected constant expression as first argument of %s"),
3435 opcode->name);
3436 break;
3437 }
3438
3439 if ((reg = check_reg (l2)) == -1)
3440 {
3441 as_bad (_("expected register as second argument of %s"),
3442 opcode->name);
3443 break;
3444 }
3445
3446 op_length = 2;
3447 frag = frag_more (op_length);
3448 where = frag - frag_now->fr_literal;
3449 bin = opcode->bin_opcode;
3450 if (! addr_op)
3451 bin |= 0x100;
3452 n = op1.exp.X_add_number;
3453 bin |= (n - 1) << 4;
3454 if (is_opcode ("pushm"))
3455 bin |= reg;
3456 else
3457 {
3458 if (reg - n + 1 < 0)
3459 {
3460 as_bad (_("Too many registers popped"));
3461 break;
3462 }
3463
3464 /* CPU21 errata: cannot use POPM to restore the SR register. */
3465 if (target_is_430xv2 ()
3466 && (reg - n + 1 < 3)
3467 && reg >= 2
3468 && is_opcode ("popm"))
3469 {
3470 as_bad (_("Cannot use POPM to restore the SR register"));
3471 break;
3472 }
3473
3474 bin |= (reg - n + 1);
3475 }
3476
3477 bfd_putl16 ((bfd_vma) bin, frag);
3478 dwarf2_emit_insn (op_length);
3479 break;
3480 }
3481
3482 case 6:
3483 {
3484 int n;
3485 int reg;
3486
3487 /* Bit rotation instructions. RRCM, RRAM, RRUM, RLAM. */
3488 if (extended & 0xff)
3489 {
3490 as_bad (_("repeat count cannot be used with %s"), opcode->name);
3491 break;
3492 }
3493
3494 line = extract_operand (line, l1, sizeof (l1));
3495 line = extract_operand (line, l2, sizeof (l2));
3496
3497 if (*l1 != '#')
3498 {
3499 as_bad (_("expected #n as first argument of %s"), opcode->name);
3500 break;
3501 }
3502 end = parse_exp (l1 + 1, &(op1.exp));
3503 if (end != NULL && *end != 0)
3504 {
3505 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3506 break;
3507 }
3508 if (op1.exp.X_op != O_constant)
3509 {
3510 as_bad (_("expected constant expression as first argument of %s"),
3511 opcode->name);
3512 break;
3513 }
3514 n = op1.exp.X_add_number;
3515 if (n > 4 || n < 1)
3516 {
3517 as_bad (_("expected first argument of %s to be in the range 1-4"),
3518 opcode->name);
3519 break;
3520 }
3521
3522 if ((reg = check_reg (l2)) == -1)
3523 {
3524 as_bad (_("expected register as second argument of %s"),
3525 opcode->name);
3526 break;
3527 }
3528
3529 if (target_is_430xv2 () && reg == 0)
3530 {
3531 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
3532 break;
3533 }
3534
3535 op_length = 2;
3536 frag = frag_more (op_length);
3537 where = frag - frag_now->fr_literal;
3538
3539 bin = opcode->bin_opcode;
3540 if (! addr_op)
3541 bin |= 0x10;
3542 bin |= (n - 1) << 10;
3543 bin |= reg;
3544
3545 bfd_putl16 ((bfd_vma) bin, frag);
3546 dwarf2_emit_insn (op_length);
3547 break;
3548 }
3549
3550 case 8:
3551 {
3552 bfd_boolean need_reloc = FALSE;
3553 int n;
3554 int reg;
3555
3556 /* ADDA, CMPA and SUBA address instructions. */
3557 if (extended & 0xff)
3558 {
3559 as_bad (_("repeat count cannot be used with %s"), opcode->name);
3560 break;
3561 }
3562
3563 line = extract_operand (line, l1, sizeof (l1));
3564 line = extract_operand (line, l2, sizeof (l2));
3565
3566 bin = opcode->bin_opcode;
3567
3568 if (*l1 == '#')
3569 {
3570 end = parse_exp (l1 + 1, &(op1.exp));
3571 if (end != NULL && *end != 0)
3572 {
3573 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3574 break;
3575 }
3576
3577 if (op1.exp.X_op == O_constant)
3578 {
3579 n = op1.exp.X_add_number;
3580 if (n > 0xfffff || n < - (0x7ffff))
3581 {
3582 as_bad (_("expected value of first argument of %s to fit into 20-bits"),
3583 opcode->name);
3584 break;
3585 }
3586
3587 bin |= ((n >> 16) & 0xf) << 8;
3588 }
3589 else
3590 {
3591 n = 0;
3592 need_reloc = TRUE;
3593 }
3594
3595 op_length = 4;
3596 }
3597 else
3598 {
3599 if ((n = check_reg (l1)) == -1)
3600 {
3601 as_bad (_("expected register name or constant as first argument of %s"),
3602 opcode->name);
3603 break;
3604 }
3605
3606 bin |= (n << 8) | (1 << 6);
3607 op_length = 2;
3608 }
3609
3610 if ((reg = check_reg (l2)) == -1)
3611 {
3612 as_bad (_("expected register as second argument of %s"),
3613 opcode->name);
3614 break;
3615 }
3616
3617 frag = frag_more (op_length);
3618 where = frag - frag_now->fr_literal;
3619 bin |= reg;
3620 if (need_reloc)
3621 fix_new_exp (frag_now, where, 4, &(op1.exp), FALSE,
3622 BFD_RELOC_MSP430X_ABS20_ADR_SRC);
3623
3624 bfd_putl16 ((bfd_vma) bin, frag);
3625 if (op_length == 4)
3626 bfd_putl16 ((bfd_vma) (n & 0xffff), frag + 2);
3627 dwarf2_emit_insn (op_length);
3628 break;
3629 }
3630
3631 case 9: /* MOVA, BRA, RETA. */
3632 imm_op = FALSE;
3633 bin = opcode->bin_opcode;
3634
3635 if (is_opcode ("reta"))
3636 {
3637 /* The RETA instruction does not take any arguments.
3638 The implicit first argument is @SP+.
3639 The implicit second argument is PC. */
3640 op1.mode = OP_REG;
3641 op1.am = 3;
3642 op1.reg = 1;
3643
3644 op2.mode = OP_REG;
3645 op2.reg = 0;
3646 }
3647 else
3648 {
3649 line = extract_operand (line, l1, sizeof (l1));
3650 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
3651 &imm_op, extended_op, FALSE);
3652
3653 if (is_opcode ("bra"))
3654 {
3655 /* This is the BRA synthetic instruction.
3656 The second argument is always PC. */
3657 op2.mode = OP_REG;
3658 op2.reg = 0;
3659 }
3660 else
3661 {
3662 line = extract_operand (line, l2, sizeof (l2));
3663 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode,
3664 extended_op, TRUE);
3665 }
3666
3667 if (res)
3668 break; /* Error occurred. All warnings were done before. */
3669 }
3670
3671 /* Only a restricted subset of the normal MSP430 addressing modes
3672 are supported here, so check for the ones that are allowed. */
3673 if ((op_length = try_encode_mova (imm_op, bin, & op1, & op2,
3674 & error_message)) == 0)
3675 {
3676 as_bad (error_message, opcode->name);
3677 break;
3678 }
3679 dwarf2_emit_insn (op_length);
3680 break;
3681
3682 case 10: /* RPT */
3683 line = extract_operand (line, l1, sizeof l1);
3684 /* The RPT instruction only accepted immediates and registers. */
3685 if (*l1 == '#')
3686 {
3687 end = parse_exp (l1 + 1, &(op1.exp));
3688 if (end != NULL && *end != 0)
3689 {
3690 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
3691 break;
3692 }
3693 if (op1.exp.X_op != O_constant)
3694 {
3695 as_bad (_("expected constant value as argument to RPT"));
3696 break;
3697 }
3698 if (op1.exp.X_add_number < 1
3699 || op1.exp.X_add_number > (1 << 4))
3700 {
3701 as_bad (_("expected constant in the range 2..16"));
3702 break;
3703 }
3704
3705 /* We silently accept and ignore a repeat count of 1. */
3706 if (op1.exp.X_add_number > 1)
3707 repeat_count = op1.exp.X_add_number;
3708 }
3709 else
3710 {
3711 int reg;
3712
3713 if ((reg = check_reg (l1)) != -1)
3714 {
3715 if (reg == 0)
3716 as_warn (_("PC used as an argument to RPT"));
3717 else
3718 repeat_count = - reg;
3719 }
3720 else
3721 {
3722 as_bad (_("expected constant or register name as argument to RPT insn"));
3723 break;
3724 }
3725 }
3726 break;
3727
3728 default:
3729 as_bad (_("Illegal emulated instruction"));
3730 break;
3731 }
3732 break;
3733
3734 /* FIXME: Emit warning when dest reg SR(R2) is addressed with .B or .A.
3735 From f5 ref man 6.3.3:
3736 The 16-bit Status Register (SR, also called R2), used as a source or
3737 destination register, can only be used in register mode addressed
3738 with word instructions. */
3739
3740 case 1: /* Format 1, double operand. */
3741 line = extract_operand (line, l1, sizeof (l1));
3742 line = extract_operand (line, l2, sizeof (l2));
3743 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, extended_op, TRUE);
3744 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode, extended_op, TRUE);
3745
3746 if (res)
3747 break; /* Error occurred. All warnings were done before. */
3748
3749 if (extended_op
3750 && is_opcode ("movx")
3751 && addr_op
3752 && msp430_enable_relax)
3753 {
3754 /* This is the MOVX.A instruction. See if we can convert
3755 it into the MOVA instruction instead. This saves 2 bytes. */
3756 if ((op_length = try_encode_mova (imm_op, 0x0000, & op1, & op2,
3757 NULL)) != 0)
3758 {
3759 dwarf2_emit_insn (op_length);
3760 break;
3761 }
3762 }
3763
3764 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
3765
3766 /* If the PC is the destination... */
3767 if (op2.am == 0 && op2.reg == 0
3768 /* ... and the opcode alters the SR. */
3769 && !(is_opcode ("bic") || is_opcode ("bis") || is_opcode ("mov")
3770 || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
3771 {
3772 if (silicon_errata_fix & SILICON_ERRATA_CPU11)
3773 as_bad (_("CPU11: PC is destination of SR altering instruction"));
3774 else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
3775 as_warn (_("CPU11: PC is destination of SR altering instruction"));
3776 }
3777
3778 /* If the status register is the destination... */
3779 if (op2.am == 0 && op2.reg == 2
3780 /* ... and the opcode alters the SR. */
3781 && (is_opcode ("add") || is_opcode ("addc") || is_opcode ("and")
3782 || is_opcode ("dadd") || is_opcode ("sub") || is_opcode ("subc")
3783 || is_opcode ("xor")
3784 || is_opcode ("addx") || is_opcode ("addcx") || is_opcode ("andx")
3785 || is_opcode ("daddx") || is_opcode ("subx") || is_opcode ("subcx")
3786 || is_opcode ("xorx")
3787 ))
3788 {
3789 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
3790 as_bad (_("CPU13: SR is destination of SR altering instruction"));
3791 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
3792 as_warn (_("CPU13: SR is destination of SR altering instruction"));
3793 }
3794
3795 /* Chain these checks for SR manipulations so we can warn if they are not
3796 caught. */
3797 if (((is_opcode ("bis") && bin == 0xd032)
3798 || (is_opcode ("mov") && bin == 0x4032)
3799 || (is_opcode ("xor") && bin == 0xe032))
3800 && op1.mode == OP_EXP
3801 && op1.exp.X_op == O_constant
3802 && (op1.exp.X_add_number & 0x10) == 0x10)
3803 check_for_nop |= NOP_CHECK_CPU19;
3804 else if ((is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))
3805 {
3806 /* Any MOV with the SR as the destination either enables or disables
3807 interrupts. */
3808 if (op1.mode == OP_EXP
3809 && op1.exp.X_op == O_constant)
3810 {
3811 if ((op1.exp.X_add_number & 0x8) == 0x8)
3812 {
3813 /* The GIE bit is being set. */
3814 warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
3815 this_insn_is_eint = TRUE;
3816 }
3817 else
3818 /* The GIE bit is being cleared. */
3819 this_insn_is_dint = TRUE;
3820 }
3821 /* If an immediate value which is covered by the constant generator
3822 is the src, then op1 will have been changed to either R2 or R3 by
3823 this point.
3824 The only constants covered by CG1 and CG2, which have bit 3 set
3825 and therefore would enable interrupts when writing to the SR, are
3826 R2 with addresing mode 0b11 and R3 with 0b11.
3827 The addressing mode is in bits 5:4 of the binary opcode. */
3828 else if (op1.mode == OP_REG
3829 && (op1.reg == 2 || op1.reg == 3)
3830 && (bin & 0x30) == 0x30)
3831 {
3832 warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
3833 this_insn_is_eint = TRUE;
3834 }
3835 /* Any other use of the constant generator with destination R2, will
3836 disable interrupts. */
3837 else if (op1.mode == OP_REG
3838 && (op1.reg == 2 || op1.reg == 3))
3839 this_insn_is_dint = TRUE;
3840 else if (do_unknown_interrupt_nops)
3841 {
3842 /* FIXME: Couldn't work out whether the insn is enabling or
3843 disabling interrupts, so for safety need to treat it as both
3844 a DINT and EINT. */
3845 warn_unsure_interrupt (prev_insn_is_nop, prev_insn_is_dint);
3846 check_for_nop |= NOP_CHECK_INTERRUPT;
3847 }
3848 }
3849 else if (is_eint (opcode->name, bin))
3850 warn_eint_nop (prev_insn_is_nop, prev_insn_is_dint);
3851 else if ((bin & 0x32) == 0x32)
3852 {
3853 /* Double-operand insn with the As==0b11 and Rdst==0x2 will result in
3854 * an interrupt state change if a write happens. */
3855 /* FIXME: How strict to be here? */
3856 ;
3857 }
3858
3859 /* Compute the entire length of the instruction in bytes. */
3860 op_length = (extended_op ? 2 : 0) /* The extension word. */
3861 + 2 /* The opcode */
3862 + (2 * op1.ol) /* The first operand. */
3863 + (2 * op2.ol); /* The second operand. */
3864
3865 insn_length += op_length;
3866 frag = frag_more (op_length);
3867 where = frag - frag_now->fr_literal;
3868
3869 if (extended_op)
3870 {
3871 if (!addr_op)
3872 extended |= BYTE_OPERATION;
3873
3874 if ((op1.ol != 0 || op2.ol != 0) && ((extended & 0xf) != 0))
3875 {
3876 as_bad (_("repeat instruction used with non-register mode instruction"));
3877 extended &= ~ 0xf;
3878 }
3879
3880 /* If necessary, emit a reloc to update the extension word. */
3881 if (op1.mode == OP_EXP)
3882 {
3883 if (op1.exp.X_op == O_constant)
3884 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
3885
3886 else if (op1.reg || op1.am == 3) /* Not PC relative. */
3887 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3888 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
3889 else
3890 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
3891 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
3892 }
3893
3894 if (op2.mode == OP_EXP)
3895 {
3896 if (op2.exp.X_op == O_constant)
3897 extended |= (op2.exp.X_add_number >> 16) & 0xf;
3898
3899 else if (op1.mode == OP_EXP)
3900 fix_new_exp (frag_now, where, 8, &(op2.exp), FALSE,
3901 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_ODST
3902 : BFD_RELOC_MSP430X_PCR20_EXT_ODST);
3903
3904 else
3905 fix_new_exp (frag_now, where, 6, &(op2.exp), FALSE,
3906 op2.reg ? BFD_RELOC_MSP430X_ABS20_EXT_DST
3907 : BFD_RELOC_MSP430X_PCR20_EXT_DST);
3908 }
3909
3910 /* Emit the extension word. */
3911 bfd_putl16 (extended, frag);
3912 where += 2;
3913 frag += 2;
3914 }
3915
3916 bfd_putl16 ((bfd_vma) bin, frag);
3917 where += 2;
3918 frag += 2;
3919
3920 if (op1.mode == OP_EXP)
3921 {
3922 if (op1.exp.X_op == O_constant)
3923 {
3924 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
3925 }
3926 else
3927 {
3928 bfd_putl16 ((bfd_vma) ZEROS, frag);
3929
3930 if (!extended_op)
3931 {
3932 if (op1.reg || op1.am == 3) /* Not PC relative. */
3933 fix_new_exp (frag_now, where, 2,
3934 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
3935 else
3936 fix_new_exp (frag_now, where, 2,
3937 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3938 }
3939 }
3940
3941 where += 2;
3942 frag += 2;
3943 }
3944
3945 if (op2.mode == OP_EXP)
3946 {
3947 if (op2.exp.X_op == O_constant)
3948 {
3949 bfd_putl16 (op2.exp.X_add_number & 0xffff, frag);
3950 }
3951 else
3952 {
3953 bfd_putl16 ((bfd_vma) ZEROS, frag);
3954
3955 if (!extended_op)
3956 {
3957 if (op2.reg) /* Not PC relative. */
3958 fix_new_exp (frag_now, where, 2,
3959 &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2));
3960 else
3961 fix_new_exp (frag_now, where, 2,
3962 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
3963 }
3964 }
3965 }
3966
3967 dwarf2_emit_insn (insn_length);
3968
3969 /* If the PC is the destination... */
3970 if (op2.am == 0 && op2.reg == 0
3971 /* ... but the opcode does not alter the destination. */
3972 && (is_opcode ("cmp") || is_opcode ("bit") || is_opcode ("cmpx")))
3973 check_for_nop |= NOP_CHECK_CPU12;
3974 break;
3975
3976 case 2: /* Single-operand mostly instr. */
3977 if (opcode->insn_opnumb == 0)
3978 {
3979 /* reti instruction. */
3980 insn_length += 2;
3981 frag = frag_more (2);
3982 bfd_putl16 ((bfd_vma) bin, frag);
3983 dwarf2_emit_insn (insn_length);
3984 break;
3985 }
3986
3987 line = extract_operand (line, l1, sizeof (l1));
3988 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode,
3989 &imm_op, extended_op, TRUE);
3990 if (res)
3991 break; /* Error in operand. */
3992
3993 if (target_is_430xv2 ()
3994 && op1.mode == OP_REG
3995 && op1.reg == 0
3996 && (is_opcode ("rrax")
3997 || is_opcode ("rrcx")
3998 || is_opcode ("rra")
3999 || is_opcode ("rrc")))
4000 {
4001 as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
4002 break;
4003 }
4004
4005 /* If the status register is the destination... */
4006 if (op1.am == 0 && op1.reg == 2
4007 /* ... and the opcode alters the SR. */
4008 && (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
4009 {
4010 if (silicon_errata_fix & SILICON_ERRATA_CPU13)
4011 as_bad (_("CPU13: SR is destination of SR altering instruction"));
4012 else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
4013 as_warn (_("CPU13: SR is destination of SR altering instruction"));
4014 }
4015
4016 insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
4017 frag = frag_more (insn_length);
4018 where = frag - frag_now->fr_literal;
4019
4020 if (extended_op)
4021 {
4022 if (is_opcode ("swpbx") || is_opcode ("sxtx"))
4023 {
4024 /* These two instructions use a special
4025 encoding of the A/L and B/W bits. */
4026 bin &= ~ BYTE_OPERATION;
4027
4028 if (byte_op)
4029 {
4030 as_bad (_("%s instruction does not accept a .b suffix"),
4031 opcode->name);
4032 break;
4033 }
4034 else if (! addr_op)
4035 extended |= BYTE_OPERATION;
4036 }
4037 else if (! addr_op)
4038 extended |= BYTE_OPERATION;
4039
4040 if (is_opcode ("rrux"))
4041 extended |= IGNORE_CARRY_BIT;
4042
4043 if (op1.ol != 0 && ((extended & 0xf) != 0))
4044 {
4045 as_bad (_("repeat instruction used with non-register mode instruction"));
4046 extended &= ~ 0xf;
4047 }
4048
4049 if (op1.mode == OP_EXP)
4050 {
4051 if (op1.exp.X_op == O_constant)
4052 extended |= ((op1.exp.X_add_number >> 16) & 0xf) << 7;
4053
4054 else if (op1.reg || op1.am == 3) /* Not PC relative. */
4055 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
4056 BFD_RELOC_MSP430X_ABS20_EXT_SRC);
4057 else
4058 fix_new_exp (frag_now, where, 6, &(op1.exp), FALSE,
4059 BFD_RELOC_MSP430X_PCR20_EXT_SRC);
4060 }
4061
4062 /* Emit the extension word. */
4063 bfd_putl16 (extended, frag);
4064 frag += 2;
4065 where += 2;
4066 }
4067
4068 bin |= op1.reg | (op1.am << 4);
4069 bfd_putl16 ((bfd_vma) bin, frag);
4070 frag += 2;
4071 where += 2;
4072
4073 if (op1.mode == OP_EXP)
4074 {
4075 if (op1.exp.X_op == O_constant)
4076 {
4077 bfd_putl16 (op1.exp.X_add_number & 0xffff, frag);
4078 }
4079 else
4080 {
4081 bfd_putl16 ((bfd_vma) ZEROS, frag);
4082
4083 if (!extended_op)
4084 {
4085 if (op1.reg || op1.am == 3) /* Not PC relative. */
4086 fix_new_exp (frag_now, where, 2,
4087 &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1));
4088 else
4089 fix_new_exp (frag_now, where, 2,
4090 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
4091 }
4092 }
4093 }
4094
4095 dwarf2_emit_insn (insn_length);
4096 break;
4097
4098 case 3: /* Conditional jumps instructions. */
4099 line = extract_operand (line, l1, sizeof (l1));
4100 /* l1 is a label. */
4101 if (l1[0])
4102 {
4103 char *m = l1;
4104 expressionS exp;
4105
4106 if (*m == '$')
4107 m++;
4108
4109 end = parse_exp (m, &exp);
4110 if (end != NULL && *end != 0)
4111 {
4112 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
4113 break;
4114 }
4115
4116 /* In order to handle something like:
4117
4118 and #0x8000, r5
4119 tst r5
4120 jz 4 ; skip next 4 bytes
4121 inv r5
4122 inc r5
4123 nop ; will jump here if r5 positive or zero
4124
4125 jCOND -n ;assumes jump n bytes backward:
4126
4127 mov r5,r6
4128 jmp -2
4129
4130 is equal to:
4131 lab:
4132 mov r5,r6
4133 jmp lab
4134
4135 jCOND $n ; jump from PC in either direction. */
4136
4137 if (exp.X_op == O_constant)
4138 {
4139 int x = exp.X_add_number;
4140
4141 if (x & 1)
4142 {
4143 as_warn (_("Even number required. Rounded to %d"), x + 1);
4144 x++;
4145 }
4146
4147 if ((*l1 == '$' && x > 0) || x < 0)
4148 x -= 2;
4149
4150 x >>= 1;
4151
4152 if (x > 512 || x < -511)
4153 {
4154 as_bad (_("Wrong displacement %d"), x << 1);
4155 break;
4156 }
4157
4158 insn_length += 2;
4159 frag = frag_more (2); /* Instr size is 1 word. */
4160
4161 bin |= x & 0x3ff;
4162 bfd_putl16 ((bfd_vma) bin, frag);
4163 }
4164 else if (exp.X_op == O_symbol && *l1 != '$')
4165 {
4166 insn_length += 2;
4167 frag = frag_more (2); /* Instr size is 1 word. */
4168 where = frag - frag_now->fr_literal;
4169 fix_new_exp (frag_now, where, 2,
4170 &exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
4171
4172 bfd_putl16 ((bfd_vma) bin, frag);
4173 }
4174 else if (*l1 == '$')
4175 {
4176 as_bad (_("instruction requires label sans '$'"));
4177 }
4178 else
4179 as_bad (_
4180 ("instruction requires label or value in range -511:512"));
4181 dwarf2_emit_insn (insn_length);
4182 break;
4183 }
4184 else
4185 {
4186 as_bad (_("instruction requires label"));
4187 break;
4188 }
4189 break;
4190
4191 case 4: /* Extended jumps. */
4192 if (!msp430_enable_polys)
4193 {
4194 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
4195 break;
4196 }
4197
4198 line = extract_operand (line, l1, sizeof (l1));
4199 if (l1[0])
4200 {
4201 char *m = l1;
4202 expressionS exp;
4203
4204 /* Ignore absolute addressing. make it PC relative anyway. */
4205 if (*m == '#' || *m == '$')
4206 m++;
4207
4208 end = parse_exp (m, & exp);
4209 if (end != NULL && *end != 0)
4210 {
4211 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
4212 break;
4213 }
4214 if (exp.X_op == O_symbol)
4215 {
4216 /* Relaxation required. */
4217 struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb];
4218
4219 if (target_is_430x ())
4220 rc = msp430x_rcodes[opcode->insn_opnumb];
4221
4222 /* The parameter to dwarf2_emit_insn is actually the offset to
4223 the start of the insn from the fix piece of instruction that
4224 was emitted. Since next fragments may have variable size we
4225 tie debug info to the beginning of the instruction. */
4226 insn_length += 8;
4227 frag = frag_more (8);
4228 dwarf2_emit_insn (0);
4229 bfd_putl16 ((bfd_vma) rc.sop, frag);
4230 frag = frag_variant (rs_machine_dependent, 8, 2,
4231 /* Wild guess. */
4232 ENCODE_RELAX (rc.lpos, STATE_BITS10),
4233 exp.X_add_symbol,
4234 0, /* Offset is zero if jump dist less than 1K. */
4235 (char *) frag);
4236 break;
4237 }
4238 }
4239
4240 as_bad (_("instruction requires label"));
4241 break;
4242
4243 case 5: /* Emulated extended branches. */
4244 if (!msp430_enable_polys)
4245 {
4246 as_bad (_("polymorphs are not enabled. Use -mP option to enable."));
4247 break;
4248 }
4249 line = extract_operand (line, l1, sizeof (l1));
4250 if (l1[0])
4251 {
4252 char * m = l1;
4253 expressionS exp;
4254
4255 /* Ignore absolute addressing. make it PC relative anyway. */
4256 if (*m == '#' || *m == '$')
4257 m++;
4258
4259 end = parse_exp (m, & exp);
4260 if (end != NULL && *end != 0)
4261 {
4262 as_bad (_("extra characters '%s' at end of operand '%s'"), end, l1);
4263 break;
4264 }
4265 if (exp.X_op == O_symbol)
4266 {
4267 /* Relaxation required. */
4268 struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb];
4269
4270 if (target_is_430x ())
4271 hc = msp430x_hcodes[opcode->insn_opnumb];
4272
4273 insn_length += 8;
4274 frag = frag_more (8);
4275 dwarf2_emit_insn (0);
4276 bfd_putl16 ((bfd_vma) hc.op0, frag);
4277 bfd_putl16 ((bfd_vma) hc.op1, frag+2);
4278
4279 frag = frag_variant (rs_machine_dependent, 8, 2,
4280 ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess. */
4281 exp.X_add_symbol,
4282 0, /* Offset is zero if jump dist less than 1K. */
4283 (char *) frag);
4284 break;
4285 }
4286 }
4287
4288 as_bad (_("instruction requires label"));
4289 break;
4290
4291 default:
4292 as_bad (_("Illegal instruction or not implemented opcode."));
4293 }
4294
4295 if (is_opcode ("nop"))
4296 {
4297 prev_insn_is_nop = TRUE;
4298 prev_insn_is_dint = FALSE;
4299 prev_insn_is_eint = FALSE;
4300 }
4301 else if (this_insn_is_dint || is_dint (opcode->name, bin))
4302 {
4303 prev_insn_is_dint = TRUE;
4304 prev_insn_is_eint = FALSE;
4305 prev_insn_is_nop = FALSE;
4306 check_for_nop |= NOP_CHECK_INTERRUPT;
4307 }
4308 /* NOP is not needed after EINT for 430 ISA. */
4309 else if (target_is_430x () && (this_insn_is_eint || is_eint (opcode->name, bin)))
4310 {
4311 prev_insn_is_eint = TRUE;
4312 prev_insn_is_nop = FALSE;
4313 prev_insn_is_dint = FALSE;
4314 check_for_nop |= NOP_CHECK_INTERRUPT;
4315 }
4316 else
4317 {
4318 prev_insn_is_nop = FALSE;
4319 prev_insn_is_dint = FALSE;
4320 prev_insn_is_eint = FALSE;
4321 }
4322
4323 input_line_pointer = line;
4324 return 0;
4325 }
4326
4327 void
4328 md_assemble (char * str)
4329 {
4330 struct msp430_opcode_s * opcode;
4331 char cmd[32];
4332 unsigned int i = 0;
4333
4334 str = skip_space (str); /* Skip leading spaces. */
4335 str = extract_cmd (str, cmd, sizeof (cmd) - 1);
4336
4337 while (cmd[i])
4338 {
4339 char a = TOLOWER (cmd[i]);
4340 cmd[i] = a;
4341 i++;
4342 }
4343
4344 if (!cmd[0])
4345 {
4346 as_bad (_("can't find opcode"));
4347 return;
4348 }
4349
4350 opcode = (struct msp430_opcode_s *) str_hash_find (msp430_hash, cmd);
4351
4352 if (opcode == NULL)
4353 {
4354 as_bad (_("unknown opcode `%s'"), cmd);
4355 return;
4356 }
4357
4358 {
4359 char *__t = input_line_pointer;
4360
4361 msp430_operands (opcode, str);
4362 input_line_pointer = __t;
4363 }
4364 }
4365
4366 /* GAS will call this function for each section at the end of the assembly,
4367 to permit the CPU backend to adjust the alignment of a section. */
4368
4369 valueT
4370 md_section_align (asection * seg, valueT addr)
4371 {
4372 int align = bfd_section_alignment (seg);
4373
4374 return ((addr + (1 << align) - 1) & -(1 << align));
4375 }
4376
4377 /* If you define this macro, it should return the offset between the
4378 address of a PC relative fixup and the position from which the PC
4379 relative adjustment should be made. On many processors, the base
4380 of a PC relative instruction is the next instruction, so this
4381 macro would return the length of an instruction. */
4382
4383 long
4384 md_pcrel_from_section (fixS * fixp, segT sec)
4385 {
4386 if (fixp->fx_addsy != (symbolS *) NULL
4387 && (!S_IS_DEFINED (fixp->fx_addsy)
4388 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
4389 return 0;
4390
4391 return fixp->fx_frag->fr_address + fixp->fx_where;
4392 }
4393
4394 /* Addition to the standard TC_FORCE_RELOCATION_LOCAL.
4395 Now it handles the situation when relocations
4396 have to be passed to linker. */
4397 int
4398 msp430_force_relocation_local (fixS *fixp)
4399 {
4400 if (fixp->fx_r_type == BFD_RELOC_MSP430_10_PCREL)
4401 return 1;
4402 if (fixp->fx_pcrel)
4403 return 1;
4404 if (msp430_enable_polys
4405 && !msp430_enable_relax)
4406 return 1;
4407
4408 return 0;
4409 }
4410
4411
4412 /* GAS will call this for each fixup. It should store the correct
4413 value in the object file. */
4414 void
4415 md_apply_fix (fixS * fixp, valueT * valuep, segT seg)
4416 {
4417 unsigned char * where;
4418 unsigned long insn;
4419 long value;
4420
4421 if (fixp->fx_addsy == (symbolS *) NULL)
4422 {
4423 value = *valuep;
4424 fixp->fx_done = 1;
4425 }
4426 else if (fixp->fx_pcrel)
4427 {
4428 segT s = S_GET_SEGMENT (fixp->fx_addsy);
4429
4430 if (fixp->fx_addsy && (s == seg || s == absolute_section))
4431 {
4432 /* FIXME: We can appear here only in case if we perform a pc
4433 relative jump to the label which is i) global, ii) locally
4434 defined or this is a jump to an absolute symbol.
4435 If this is an absolute symbol -- everything is OK.
4436 If this is a global label, we've got a symbol value defined
4437 twice:
4438 1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
4439 from this section start
4440 2. *valuep will contain the real offset from jump insn to the
4441 label
4442 So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
4443 will be incorrect. Therefore remove s_get_value. */
4444 value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep;
4445 fixp->fx_done = 1;
4446 }
4447 else
4448 value = *valuep;
4449 }
4450 else
4451 {
4452 value = fixp->fx_offset;
4453
4454 if (fixp->fx_subsy != (symbolS *) NULL)
4455 {
4456 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
4457 {
4458 value -= S_GET_VALUE (fixp->fx_subsy);
4459 fixp->fx_done = 1;
4460 }
4461 }
4462 }
4463
4464 fixp->fx_no_overflow = 1;
4465
4466 /* If polymorphs are enabled and relax disabled.
4467 do not kill any relocs and pass them to linker. */
4468 if (msp430_enable_polys
4469 && !msp430_enable_relax)
4470 {
4471 if (!fixp->fx_addsy
4472 || S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)
4473 fixp->fx_done = 1; /* It is ok to kill 'abs' reloc. */
4474 else
4475 fixp->fx_done = 0;
4476 }
4477
4478 if (fixp->fx_done)
4479 {
4480 /* Fetch the instruction, insert the fully resolved operand
4481 value, and stuff the instruction back again. */
4482 where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where;
4483
4484 insn = bfd_getl16 (where);
4485
4486 switch (fixp->fx_r_type)
4487 {
4488 case BFD_RELOC_MSP430_10_PCREL:
4489 if (value & 1)
4490 as_bad_where (fixp->fx_file, fixp->fx_line,
4491 _("odd address operand: %ld"), value);
4492
4493 /* Jumps are in words. */
4494 value >>= 1;
4495 --value; /* Correct PC. */
4496
4497 if (value < -512 || value > 511)
4498 as_bad_where (fixp->fx_file, fixp->fx_line,
4499 _("operand out of range: %ld"), value);
4500
4501 value &= 0x3ff; /* get rid of extended sign */
4502 bfd_putl16 ((bfd_vma) (value | insn), where);
4503 break;
4504
4505 case BFD_RELOC_MSP430X_PCR16:
4506 case BFD_RELOC_MSP430_RL_PCREL:
4507 case BFD_RELOC_MSP430_16_PCREL:
4508 if (value & 1)
4509 as_bad_where (fixp->fx_file, fixp->fx_line,
4510 _("odd address operand: %ld"), value);
4511 /* Fall through. */
4512
4513 case BFD_RELOC_MSP430_16_PCREL_BYTE:
4514 /* Nothing to be corrected here. */
4515 if (value < -32768 || value > 65536)
4516 as_bad_where (fixp->fx_file, fixp->fx_line,
4517 _("operand out of range: %ld"), value);
4518 /* Fall through. */
4519
4520 case BFD_RELOC_MSP430X_ABS16:
4521 case BFD_RELOC_MSP430_16:
4522 case BFD_RELOC_16:
4523 case BFD_RELOC_MSP430_16_BYTE:
4524 value &= 0xffff; /* Get rid of extended sign. */
4525 bfd_putl16 ((bfd_vma) value, where);
4526 break;
4527
4528 case BFD_RELOC_MSP430_ABS_HI16:
4529 value >>= 16;
4530 value &= 0xffff; /* Get rid of extended sign. */
4531 bfd_putl16 ((bfd_vma) value, where);
4532 break;
4533
4534 case BFD_RELOC_32:
4535 bfd_putl16 ((bfd_vma) value, where);
4536 break;
4537
4538 case BFD_RELOC_MSP430_ABS8:
4539 case BFD_RELOC_8:
4540 bfd_put_8 (NULL, (bfd_vma) value, where);
4541 break;
4542
4543 case BFD_RELOC_MSP430X_ABS20_EXT_SRC:
4544 case BFD_RELOC_MSP430X_PCR20_EXT_SRC:
4545 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
4546 value >>= 16;
4547 bfd_putl16 ((bfd_vma) (((value & 0xf) << 7) | insn), where);
4548 break;
4549
4550 case BFD_RELOC_MSP430X_ABS20_ADR_SRC:
4551 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4552 value >>= 16;
4553 bfd_putl16 ((bfd_vma) (((value & 0xf) << 8) | insn), where);
4554 break;
4555
4556 case BFD_RELOC_MSP430X_ABS20_EXT_ODST:
4557 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
4558 value >>= 16;
4559 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4560 break;
4561
4562 case BFD_RELOC_MSP430X_PCR20_CALL:
4563 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4564 value >>= 16;
4565 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4566 break;
4567
4568 case BFD_RELOC_MSP430X_ABS20_EXT_DST:
4569 case BFD_RELOC_MSP430X_PCR20_EXT_DST:
4570 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4);
4571 value >>= 16;
4572 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4573 break;
4574
4575 case BFD_RELOC_MSP430X_PCR20_EXT_ODST:
4576 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6);
4577 value >>= 16;
4578 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4579 break;
4580
4581 case BFD_RELOC_MSP430X_ABS20_ADR_DST:
4582 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
4583 value >>= 16;
4584 bfd_putl16 ((bfd_vma) ((value & 0xf) | insn), where);
4585 break;
4586
4587 default:
4588 as_fatal (_("line %d: unknown relocation type: 0x%x"),
4589 fixp->fx_line, fixp->fx_r_type);
4590 break;
4591 }
4592 }
4593 else
4594 {
4595 fixp->fx_addnumber = value;
4596 }
4597 }
4598
4599 static bfd_boolean
4600 S_IS_GAS_LOCAL (symbolS * s)
4601 {
4602 const char * name;
4603 unsigned int len;
4604
4605 if (s == NULL)
4606 return FALSE;
4607 name = S_GET_NAME (s);
4608 len = strlen (name) - 1;
4609
4610 return name[len] == 1 || name[len] == 2;
4611 }
4612
4613 /* GAS will call this to generate a reloc, passing the resulting reloc
4614 to `bfd_install_relocation'. This currently works poorly, as
4615 `bfd_install_relocation' often does the wrong thing, and instances of
4616 `tc_gen_reloc' have been written to work around the problems, which
4617 in turns makes it difficult to fix `bfd_install_relocation'. */
4618
4619 /* If while processing a fixup, a reloc really needs to be created
4620 then it is done here. */
4621
4622 arelent **
4623 tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp)
4624 {
4625 static arelent * no_relocs = NULL;
4626 static arelent * relocs[MAX_RELOC_EXPANSION + 1];
4627 arelent *reloc;
4628
4629 reloc = XNEW (arelent);
4630 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
4631 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
4632
4633 if (reloc->howto == (reloc_howto_type *) NULL)
4634 {
4635 as_bad_where (fixp->fx_file, fixp->fx_line,
4636 _("reloc %d not supported by object file format"),
4637 (int) fixp->fx_r_type);
4638 free (reloc);
4639 return & no_relocs;
4640 }
4641
4642 relocs[0] = reloc;
4643 relocs[1] = NULL;
4644
4645 if (fixp->fx_subsy
4646 && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
4647 {
4648 fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy);
4649 fixp->fx_subsy = NULL;
4650 }
4651
4652 if (fixp->fx_addsy && fixp->fx_subsy)
4653 {
4654 asection *asec, *ssec;
4655
4656 asec = S_GET_SEGMENT (fixp->fx_addsy);
4657 ssec = S_GET_SEGMENT (fixp->fx_subsy);
4658
4659 /* If we have a difference between two different, non-absolute symbols
4660 we must generate two relocs (one for each symbol) and allow the
4661 linker to resolve them - relaxation may change the distances between
4662 symbols, even local symbols defined in the same section.
4663
4664 Unfortunately we cannot do this with assembler generated local labels
4665 because there can be multiple incarnations of the same label, with
4666 exactly the same name, in any given section and the linker will have
4667 no way to identify the correct one. Instead we just have to hope
4668 that no relaxation will occur between the local label and the other
4669 symbol in the expression.
4670
4671 Similarly we have to compute differences between symbols in the .eh_frame
4672 section as the linker is not smart enough to apply relocations there
4673 before attempting to process it. */
4674 if ((ssec != absolute_section || asec != absolute_section)
4675 && (fixp->fx_addsy != fixp->fx_subsy)
4676 && strcmp (ssec->name, ".eh_frame") != 0
4677 && ! S_IS_GAS_LOCAL (fixp->fx_addsy)
4678 && ! S_IS_GAS_LOCAL (fixp->fx_subsy))
4679 {
4680 arelent * reloc2 = XNEW (arelent);
4681
4682 relocs[0] = reloc2;
4683 relocs[1] = reloc;
4684
4685 reloc2->address = reloc->address;
4686 reloc2->howto = bfd_reloc_type_lookup (stdoutput,
4687 BFD_RELOC_MSP430_SYM_DIFF);
4688 reloc2->addend = - S_GET_VALUE (fixp->fx_subsy);
4689
4690 if (ssec == absolute_section)
4691 reloc2->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
4692 else
4693 {
4694 reloc2->sym_ptr_ptr = XNEW (asymbol *);
4695 *reloc2->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy);
4696 }
4697
4698 reloc->addend = fixp->fx_offset;
4699 if (asec == absolute_section)
4700 {
4701 reloc->addend += S_GET_VALUE (fixp->fx_addsy);
4702 reloc->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
4703 }
4704 else
4705 {
4706 reloc->sym_ptr_ptr = XNEW (asymbol *);
4707 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4708 }
4709
4710 fixp->fx_pcrel = 0;
4711 fixp->fx_done = 1;
4712 return relocs;
4713 }
4714 else
4715 {
4716 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
4717
4718 reloc->addend = (S_GET_VALUE (fixp->fx_addsy)
4719 - S_GET_VALUE (fixp->fx_subsy) + fixp->fx_offset);
4720
4721 switch (fixp->fx_r_type)
4722 {
4723 case BFD_RELOC_8:
4724 md_number_to_chars (fixpos, reloc->addend, 1);
4725 break;
4726
4727 case BFD_RELOC_16:
4728 md_number_to_chars (fixpos, reloc->addend, 2);
4729 break;
4730
4731 case BFD_RELOC_24:
4732 md_number_to_chars (fixpos, reloc->addend, 3);
4733 break;
4734
4735 case BFD_RELOC_32:
4736 md_number_to_chars (fixpos, reloc->addend, 4);
4737 break;
4738
4739 default:
4740 reloc->sym_ptr_ptr
4741 = (asymbol **) bfd_abs_section_ptr->symbol_ptr_ptr;
4742 return relocs;
4743 }
4744
4745 free (reloc);
4746 return & no_relocs;
4747 }
4748 }
4749 else
4750 {
4751 #if 0
4752 if (fixp->fx_r_type == BFD_RELOC_MSP430X_ABS16
4753 && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section)
4754 {
4755 bfd_vma amount = S_GET_VALUE (fixp->fx_addsy);
4756 char *fixpos = fixp->fx_where + fixp->fx_frag->fr_literal;
4757
4758 md_number_to_chars (fixpos, amount, 2);
4759 free (reloc);
4760 return & no_relocs;
4761 }
4762 #endif
4763 reloc->sym_ptr_ptr = XNEW (asymbol *);
4764 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4765 reloc->addend = fixp->fx_offset;
4766
4767 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4768 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4769 reloc->address = fixp->fx_offset;
4770 }
4771
4772 return relocs;
4773 }
4774
4775 int
4776 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
4777 asection * segment_type ATTRIBUTE_UNUSED)
4778 {
4779 if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
4780 {
4781 /* This is a jump -> pcrel mode. Nothing to do much here.
4782 Return value == 2. */
4783 fragP->fr_subtype =
4784 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10);
4785 }
4786 else if (fragP->fr_symbol)
4787 {
4788 /* It's got a segment, but it's not ours. Even if fr_symbol is in
4789 an absolute segment, we don't know a displacement until we link
4790 object files. So it will always be long. This also applies to
4791 labels in a subsegment of current. Liker may relax it to short
4792 jump later. Return value == 8. */
4793 fragP->fr_subtype =
4794 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD);
4795 }
4796 else
4797 {
4798 /* We know the abs value. may be it is a jump to fixed address.
4799 Impossible in our case, cause all constants already handled. */
4800 fragP->fr_subtype =
4801 ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF);
4802 }
4803
4804 return md_relax_table[fragP->fr_subtype].rlx_length;
4805 }
4806
4807 void
4808 md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
4809 asection * sec ATTRIBUTE_UNUSED,
4810 fragS * fragP)
4811 {
4812 char * where = 0;
4813 int rela = -1;
4814 int i;
4815 struct rcodes_s * cc = NULL;
4816 struct hcodes_s * hc = NULL;
4817
4818 switch (fragP->fr_subtype)
4819 {
4820 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10):
4821 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10):
4822 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10):
4823 /* We do not have to convert anything here.
4824 Just apply a fix. */
4825 rela = BFD_RELOC_MSP430_10_PCREL;
4826 break;
4827
4828 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD):
4829 case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF):
4830 /* Convert uncond branch jmp lab -> br lab. */
4831 if (target_is_430x ())
4832 cc = msp430x_rcodes + 7;
4833 else
4834 cc = msp430_rcodes + 7;
4835 where = fragP->fr_literal + fragP->fr_fix;
4836 bfd_putl16 (cc->lop0, where);
4837 rela = BFD_RELOC_MSP430_RL_PCREL;
4838 fragP->fr_fix += 2;
4839 break;
4840
4841 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD):
4842 case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF):
4843 {
4844 /* Other simple branches. */
4845 int insn = bfd_getl16 (fragP->fr_opcode);
4846
4847 insn &= 0xffff;
4848 /* Find actual instruction. */
4849 if (target_is_430x ())
4850 {
4851 for (i = 0; i < 7 && !cc; i++)
4852 if (msp430x_rcodes[i].sop == insn)
4853 cc = msp430x_rcodes + i;
4854 }
4855 else
4856 {
4857 for (i = 0; i < 7 && !cc; i++)
4858 if (msp430_rcodes[i].sop == insn)
4859 cc = & msp430_rcodes[i];
4860 }
4861
4862 if (!cc || !cc->name)
4863 as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
4864 __FUNCTION__, (long) insn);
4865 where = fragP->fr_literal + fragP->fr_fix;
4866 bfd_putl16 (cc->lop0, where);
4867 bfd_putl16 (cc->lop1, where + 2);
4868 rela = BFD_RELOC_MSP430_RL_PCREL;
4869 fragP->fr_fix += 4;
4870 }
4871 break;
4872
4873 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD):
4874 case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF):
4875 if (target_is_430x ())
4876 cc = msp430x_rcodes + 6;
4877 else
4878 cc = msp430_rcodes + 6;
4879 where = fragP->fr_literal + fragP->fr_fix;
4880 bfd_putl16 (cc->lop0, where);
4881 bfd_putl16 (cc->lop1, where + 2);
4882 bfd_putl16 (cc->lop2, where + 4);
4883 rela = BFD_RELOC_MSP430_RL_PCREL;
4884 fragP->fr_fix += 6;
4885 break;
4886
4887 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10):
4888 {
4889 int insn = bfd_getl16 (fragP->fr_opcode + 2);
4890
4891 insn &= 0xffff;
4892 if (target_is_430x ())
4893 {
4894 for (i = 0; i < 4 && !hc; i++)
4895 if (msp430x_hcodes[i].op1 == insn)
4896 hc = msp430x_hcodes + i;
4897 }
4898 else
4899 {
4900 for (i = 0; i < 4 && !hc; i++)
4901 if (msp430_hcodes[i].op1 == insn)
4902 hc = &msp430_hcodes[i];
4903 }
4904 if (!hc || !hc->name)
4905 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4906 __FUNCTION__, (long) insn);
4907 rela = BFD_RELOC_MSP430_10_PCREL;
4908 /* Apply a fix for a first label if necessary.
4909 another fix will be applied to the next word of insn anyway. */
4910 if (hc->tlab == 2)
4911 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4912 fragP->fr_offset, TRUE, rela);
4913 fragP->fr_fix += 2;
4914 }
4915
4916 break;
4917
4918 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD):
4919 case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF):
4920 {
4921 int insn = bfd_getl16 (fragP->fr_opcode + 2);
4922
4923 insn &= 0xffff;
4924 if (target_is_430x ())
4925 {
4926 for (i = 0; i < 4 && !hc; i++)
4927 if (msp430x_hcodes[i].op1 == insn)
4928 hc = msp430x_hcodes + i;
4929 }
4930 else
4931 {
4932 for (i = 0; i < 4 && !hc; i++)
4933 if (msp430_hcodes[i].op1 == insn)
4934 hc = & msp430_hcodes[i];
4935 }
4936 if (!hc || !hc->name)
4937 as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
4938 __FUNCTION__, (long) insn);
4939 rela = BFD_RELOC_MSP430_RL_PCREL;
4940 where = fragP->fr_literal + fragP->fr_fix;
4941 bfd_putl16 (hc->lop0, where);
4942 bfd_putl16 (hc->lop1, where + 2);
4943 bfd_putl16 (hc->lop2, where + 4);
4944 fragP->fr_fix += 6;
4945 }
4946 break;
4947
4948 default:
4949 as_fatal (_("internal inconsistency problem in %s: %lx"),
4950 __FUNCTION__, (long) fragP->fr_subtype);
4951 break;
4952 }
4953
4954 /* Now apply fix. */
4955 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4956 fragP->fr_offset, TRUE, rela);
4957 /* Just fixed 2 bytes. */
4958 fragP->fr_fix += 2;
4959 }
4960
4961 /* Relax fragment. Mostly stolen from hc11 and mcore
4962 which arches I think I know. */
4963
4964 long
4965 msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP,
4966 long stretch ATTRIBUTE_UNUSED)
4967 {
4968 long growth;
4969 offsetT aim = 0;
4970 symbolS *symbolP;
4971 const relax_typeS *this_type;
4972 const relax_typeS *start_type;
4973 relax_substateT next_state;
4974 relax_substateT this_state;
4975 const relax_typeS *table = md_relax_table;
4976
4977 /* Nothing to be done if the frag has already max size. */
4978 if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF
4979 || RELAX_STATE (fragP->fr_subtype) == STATE_WORD)
4980 return 0;
4981
4982 if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10)
4983 {
4984 symbolP = fragP->fr_symbol;
4985 if (symbol_resolved_p (symbolP))
4986 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
4987 __FUNCTION__);
4988 /* We know the offset. calculate a distance. */
4989 aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix;
4990 }
4991
4992 if (!msp430_enable_relax)
4993 {
4994 /* Relaxation is not enabled. So, make all jump as long ones
4995 by setting 'aim' to quite high value. */
4996 aim = 0x7fff;
4997 }
4998
4999 this_state = fragP->fr_subtype;
5000 start_type = this_type = table + this_state;
5001
5002 if (aim < 0)
5003 {
5004 /* Look backwards. */
5005 for (next_state = this_type->rlx_more; next_state;)
5006 if (aim >= this_type->rlx_backward || !this_type->rlx_backward)
5007 next_state = 0;
5008 else
5009 {
5010 /* Grow to next state. */
5011 this_state = next_state;
5012 this_type = table + this_state;
5013 next_state = this_type->rlx_more;
5014 }
5015 }
5016 else
5017 {
5018 /* Look forwards. */
5019 for (next_state = this_type->rlx_more; next_state;)
5020 if (aim <= this_type->rlx_forward || !this_type->rlx_forward)
5021 next_state = 0;
5022 else
5023 {
5024 /* Grow to next state. */
5025 this_state = next_state;
5026 this_type = table + this_state;
5027 next_state = this_type->rlx_more;
5028 }
5029 }
5030
5031 growth = this_type->rlx_length - start_type->rlx_length;
5032 if (growth != 0)
5033 fragP->fr_subtype = this_state;
5034 return growth;
5035 }
5036
5037 /* Return FALSE if the fixup in fixp should be left alone and not
5038 adjusted. We return FALSE here so that linker relaxation will
5039 work. */
5040
5041 bfd_boolean
5042 msp430_fix_adjustable (struct fix *fixp ATTRIBUTE_UNUSED)
5043 {
5044 /* If the symbol is in a non-code section then it should be OK. */
5045 if (fixp->fx_addsy
5046 && ((S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) == 0))
5047 return TRUE;
5048
5049 return FALSE;
5050 }
5051
5052 /* Set the contents of the .MSP430.attributes and .GNU.attributes sections. */
5053
5054 void
5055 msp430_md_end (void)
5056 {
5057 if (check_for_nop)
5058 {
5059 if (gen_interrupt_nops)
5060 {
5061 gen_nop ();
5062 if (warn_interrupt_nops)
5063 as_warn (INSERT_NOP_AT_EOF);
5064 }
5065 else if (warn_interrupt_nops)
5066 as_warn (_(WARN_NOP_AT_EOF));
5067 }
5068
5069 /* We have already emitted an error if any of the following attributes
5070 disagree with the attributes in the input assembly file. See
5071 msp430_object_attribute. */
5072 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA,
5073 target_is_430x () ? OFBA_MSPABI_Val_ISA_MSP430X
5074 : OFBA_MSPABI_Val_ISA_MSP430);
5075
5076 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Code_Model,
5077 large_model ? OFBA_MSPABI_Val_Code_Model_LARGE
5078 : OFBA_MSPABI_Val_Code_Model_SMALL);
5079
5080 bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_Data_Model,
5081 large_model ? OFBA_MSPABI_Val_Code_Model_LARGE
5082 : OFBA_MSPABI_Val_Code_Model_SMALL);
5083
5084 /* The data region GNU attribute is ignored for the small memory model. */
5085 if (large_model)
5086 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU,
5087 Tag_GNU_MSP430_Data_Region, lower_data_region_only
5088 ? Val_GNU_MSP430_Data_Region_Lower
5089 : Val_GNU_MSP430_Data_Region_Any);
5090 }
5091
5092 /* Returns FALSE if there is a msp430 specific reason why the
5093 subtraction of two same-section symbols cannot be computed by
5094 the assembler. */
5095
5096 bfd_boolean
5097 msp430_allow_local_subtract (expressionS * left,
5098 expressionS * right,
5099 segT section)
5100 {
5101 /* If the symbols are not in a code section then they are OK. */
5102 if ((section->flags & SEC_CODE) == 0)
5103 return TRUE;
5104
5105 if (S_IS_GAS_LOCAL (left->X_add_symbol) || S_IS_GAS_LOCAL (right->X_add_symbol))
5106 return TRUE;
5107
5108 if (left->X_add_symbol == right->X_add_symbol)
5109 return TRUE;
5110
5111 /* We have to assume that there may be instructions between the
5112 two symbols and that relaxation may increase the distance between
5113 them. */
5114 return FALSE;
5115 }
GDB Binutils - Deliverables
This page took 0.248638 seconds and 4 git commands to generate.