1 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
25 #include "dw2gencfi.h"
26 #include "opcode/ppc.h"
30 #include "elf/ppc64.h"
31 #include "dwarf2dbg.h"
39 #include "coff/xcoff.h"
43 /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */
45 /* Tell the main code what the endianness is. */
46 extern int target_big_endian
;
48 /* Whether or not, we've set target_big_endian. */
49 static int set_target_endian
= 0;
51 /* Whether to use user friendly register names. */
52 #ifndef TARGET_REG_NAMES_P
54 #define TARGET_REG_NAMES_P TRUE
56 #define TARGET_REG_NAMES_P FALSE
60 /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
63 /* #lo(value) denotes the least significant 16 bits of the indicated. */
64 #define PPC_LO(v) ((v) & 0xffff)
66 /* #hi(value) denotes bits 16 through 31 of the indicated value. */
67 #define PPC_HI(v) (((v) >> 16) & 0xffff)
69 /* #ha(value) denotes the high adjusted value: bits 16 through 31 of
70 the indicated value, compensating for #lo() being treated as a
72 #define PPC_HA(v) PPC_HI ((v) + 0x8000)
74 /* #higher(value) denotes bits 32 through 47 of the indicated value. */
75 #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
77 /* #highera(value) denotes bits 32 through 47 of the indicated value,
78 compensating for #lo() being treated as a signed number. */
79 #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000)
81 /* #highest(value) denotes bits 48 through 63 of the indicated value. */
82 #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff)
84 /* #highesta(value) denotes bits 48 through 63 of the indicated value,
85 compensating for #lo being treated as a signed number. */
86 #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000)
88 #define SEX16(val) (((val) ^ 0x8000) - 0x8000)
90 /* For the time being on ppc64, don't report overflow on @h and @ha
91 applied to constants. */
92 #define REPORT_OVERFLOW_HI 0
94 static bfd_boolean reg_names_p
= TARGET_REG_NAMES_P
;
96 static void ppc_macro (char *, const struct powerpc_macro
*);
97 static void ppc_byte (int);
99 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
100 static void ppc_tc (int);
101 static void ppc_machine (int);
105 static void ppc_comm (int);
106 static void ppc_bb (int);
107 static void ppc_bc (int);
108 static void ppc_bf (int);
109 static void ppc_biei (int);
110 static void ppc_bs (int);
111 static void ppc_eb (int);
112 static void ppc_ec (int);
113 static void ppc_ef (int);
114 static void ppc_es (int);
115 static void ppc_csect (int);
116 static void ppc_dwsect (int);
117 static void ppc_change_csect (symbolS
*, offsetT
);
118 static void ppc_function (int);
119 static void ppc_extern (int);
120 static void ppc_lglobl (int);
121 static void ppc_ref (int);
122 static void ppc_section (int);
123 static void ppc_named_section (int);
124 static void ppc_stabx (int);
125 static void ppc_rename (int);
126 static void ppc_toc (int);
127 static void ppc_xcoff_cons (int);
128 static void ppc_vbyte (int);
132 static void ppc_elf_rdata (int);
133 static void ppc_elf_lcomm (int);
134 static void ppc_elf_localentry (int);
135 static void ppc_elf_abiversion (int);
136 static void ppc_elf_gnu_attribute (int);
140 static void ppc_previous (int);
141 static void ppc_pdata (int);
142 static void ppc_ydata (int);
143 static void ppc_reldata (int);
144 static void ppc_rdata (int);
145 static void ppc_ualong (int);
146 static void ppc_znop (int);
147 static void ppc_pe_comm (int);
148 static void ppc_pe_section (int);
149 static void ppc_pe_function (int);
150 static void ppc_pe_tocd (int);
153 /* Generic assembler global variables which must be defined by all
157 /* This string holds the chars that always start a comment. If the
158 pre-processor is disabled, these aren't very useful. The macro
159 tc_comment_chars points to this. We use this, rather than the
160 usual comment_chars, so that we can switch for Solaris conventions. */
161 static const char ppc_solaris_comment_chars
[] = "#!";
162 static const char ppc_eabi_comment_chars
[] = "#";
164 #ifdef TARGET_SOLARIS_COMMENT
165 const char *ppc_comment_chars
= ppc_solaris_comment_chars
;
167 const char *ppc_comment_chars
= ppc_eabi_comment_chars
;
170 const char comment_chars
[] = "#";
173 /* Characters which start a comment at the beginning of a line. */
174 const char line_comment_chars
[] = "#";
176 /* Characters which may be used to separate multiple commands on a
178 const char line_separator_chars
[] = ";";
180 /* Characters which are used to indicate an exponent in a floating
182 const char EXP_CHARS
[] = "eE";
184 /* Characters which mean that a number is a floating point constant,
186 const char FLT_CHARS
[] = "dD";
188 /* Anything that can start an operand needs to be mentioned here,
189 to stop the input scrubber eating whitespace. */
190 const char ppc_symbol_chars
[] = "%[";
192 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
193 int ppc_cie_data_alignment
;
195 /* The dwarf2 minimum instruction length. */
196 int ppc_dwarf2_line_min_insn_length
;
198 /* More than this number of nops in an alignment op gets a branch
200 unsigned long nop_limit
= 4;
202 /* The type of processor we are assembling for. This is one or more
203 of the PPC_OPCODE flags defined in opcode/ppc.h. */
204 ppc_cpu_t ppc_cpu
= 0;
205 ppc_cpu_t sticky
= 0;
207 /* Value for ELF e_flags EF_PPC64_ABI. */
208 unsigned int ppc_abiversion
= 0;
211 /* Flags set on encountering toc relocs. */
213 has_large_toc_reloc
= 1,
214 has_small_toc_reloc
= 2
218 /* Warn on emitting data to code sections. */
224 /* The target specific pseudo-ops which we support. */
226 const pseudo_typeS md_pseudo_table
[] =
228 /* Pseudo-ops which must be overridden. */
229 { "byte", ppc_byte
, 0 },
232 /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these
233 legitimately belong in the obj-*.c file. However, XCOFF is based
234 on COFF, and is only implemented for the RS/6000. We just use
235 obj-coff.c, and add what we need here. */
236 { "comm", ppc_comm
, 0 },
237 { "lcomm", ppc_comm
, 1 },
241 { "bi", ppc_biei
, 0 },
243 { "csect", ppc_csect
, 0 },
244 { "dwsect", ppc_dwsect
, 0 },
245 { "data", ppc_section
, 'd' },
249 { "ei", ppc_biei
, 1 },
251 { "extern", ppc_extern
, 0 },
252 { "function", ppc_function
, 0 },
253 { "lglobl", ppc_lglobl
, 0 },
254 { "ref", ppc_ref
, 0 },
255 { "rename", ppc_rename
, 0 },
256 { "section", ppc_named_section
, 0 },
257 { "stabx", ppc_stabx
, 0 },
258 { "text", ppc_section
, 't' },
259 { "toc", ppc_toc
, 0 },
260 { "long", ppc_xcoff_cons
, 2 },
261 { "llong", ppc_xcoff_cons
, 3 },
262 { "word", ppc_xcoff_cons
, 1 },
263 { "short", ppc_xcoff_cons
, 1 },
264 { "vbyte", ppc_vbyte
, 0 },
268 { "llong", cons
, 8 },
269 { "rdata", ppc_elf_rdata
, 0 },
270 { "rodata", ppc_elf_rdata
, 0 },
271 { "lcomm", ppc_elf_lcomm
, 0 },
272 { "localentry", ppc_elf_localentry
, 0 },
273 { "abiversion", ppc_elf_abiversion
, 0 },
274 { "gnu_attribute", ppc_elf_gnu_attribute
, 0},
278 /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */
279 { "previous", ppc_previous
, 0 },
280 { "pdata", ppc_pdata
, 0 },
281 { "ydata", ppc_ydata
, 0 },
282 { "reldata", ppc_reldata
, 0 },
283 { "rdata", ppc_rdata
, 0 },
284 { "ualong", ppc_ualong
, 0 },
285 { "znop", ppc_znop
, 0 },
286 { "comm", ppc_pe_comm
, 0 },
287 { "lcomm", ppc_pe_comm
, 1 },
288 { "section", ppc_pe_section
, 0 },
289 { "function", ppc_pe_function
,0 },
290 { "tocd", ppc_pe_tocd
, 0 },
293 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
295 { "machine", ppc_machine
, 0 },
302 /* Predefined register names if -mregnames (or default for Windows NT).
303 In general, there are lots of them, in an attempt to be compatible
304 with a number of other Windows NT assemblers. */
306 /* Structure to hold information about predefined registers. */
310 unsigned short value
;
311 unsigned short flags
;
314 /* List of registers that are pre-defined:
316 Each general register has predefined names of the form:
317 1. r<reg_num> which has the value <reg_num>.
318 2. r.<reg_num> which has the value <reg_num>.
320 Each floating point register has predefined names of the form:
321 1. f<reg_num> which has the value <reg_num>.
322 2. f.<reg_num> which has the value <reg_num>.
324 Each vector unit register has predefined names of the form:
325 1. v<reg_num> which has the value <reg_num>.
326 2. v.<reg_num> which has the value <reg_num>.
328 Each condition register has predefined names of the form:
329 1. cr<reg_num> which has the value <reg_num>.
330 2. cr.<reg_num> which has the value <reg_num>.
332 There are individual registers as well:
333 sp or r.sp has the value 1
334 rtoc or r.toc has the value 2
339 dsisr has the value 18
341 sdr1 has the value 25
342 srr0 has the value 26
343 srr1 has the value 27
345 The table is sorted. Suitable for searching by a binary search. */
347 static const struct pd_reg pre_defined_registers
[] =
349 /* VSX accumulators. */
350 { "a0", 0, PPC_OPERAND_ACC
},
351 { "a1", 1, PPC_OPERAND_ACC
},
352 { "a2", 2, PPC_OPERAND_ACC
},
353 { "a3", 3, PPC_OPERAND_ACC
},
354 { "a4", 4, PPC_OPERAND_ACC
},
355 { "a5", 5, PPC_OPERAND_ACC
},
356 { "a6", 6, PPC_OPERAND_ACC
},
357 { "a7", 7, PPC_OPERAND_ACC
},
359 /* Condition Registers */
360 { "cr.0", 0, PPC_OPERAND_CR_REG
},
361 { "cr.1", 1, PPC_OPERAND_CR_REG
},
362 { "cr.2", 2, PPC_OPERAND_CR_REG
},
363 { "cr.3", 3, PPC_OPERAND_CR_REG
},
364 { "cr.4", 4, PPC_OPERAND_CR_REG
},
365 { "cr.5", 5, PPC_OPERAND_CR_REG
},
366 { "cr.6", 6, PPC_OPERAND_CR_REG
},
367 { "cr.7", 7, PPC_OPERAND_CR_REG
},
369 { "cr0", 0, PPC_OPERAND_CR_REG
},
370 { "cr1", 1, PPC_OPERAND_CR_REG
},
371 { "cr2", 2, PPC_OPERAND_CR_REG
},
372 { "cr3", 3, PPC_OPERAND_CR_REG
},
373 { "cr4", 4, PPC_OPERAND_CR_REG
},
374 { "cr5", 5, PPC_OPERAND_CR_REG
},
375 { "cr6", 6, PPC_OPERAND_CR_REG
},
376 { "cr7", 7, PPC_OPERAND_CR_REG
},
378 { "ctr", 9, PPC_OPERAND_SPR
},
379 { "dar", 19, PPC_OPERAND_SPR
},
380 { "dec", 22, PPC_OPERAND_SPR
},
381 { "dsisr", 18, PPC_OPERAND_SPR
},
383 /* Floating point registers */
384 { "f.0", 0, PPC_OPERAND_FPR
},
385 { "f.1", 1, PPC_OPERAND_FPR
},
386 { "f.10", 10, PPC_OPERAND_FPR
},
387 { "f.11", 11, PPC_OPERAND_FPR
},
388 { "f.12", 12, PPC_OPERAND_FPR
},
389 { "f.13", 13, PPC_OPERAND_FPR
},
390 { "f.14", 14, PPC_OPERAND_FPR
},
391 { "f.15", 15, PPC_OPERAND_FPR
},
392 { "f.16", 16, PPC_OPERAND_FPR
},
393 { "f.17", 17, PPC_OPERAND_FPR
},
394 { "f.18", 18, PPC_OPERAND_FPR
},
395 { "f.19", 19, PPC_OPERAND_FPR
},
396 { "f.2", 2, PPC_OPERAND_FPR
},
397 { "f.20", 20, PPC_OPERAND_FPR
},
398 { "f.21", 21, PPC_OPERAND_FPR
},
399 { "f.22", 22, PPC_OPERAND_FPR
},
400 { "f.23", 23, PPC_OPERAND_FPR
},
401 { "f.24", 24, PPC_OPERAND_FPR
},
402 { "f.25", 25, PPC_OPERAND_FPR
},
403 { "f.26", 26, PPC_OPERAND_FPR
},
404 { "f.27", 27, PPC_OPERAND_FPR
},
405 { "f.28", 28, PPC_OPERAND_FPR
},
406 { "f.29", 29, PPC_OPERAND_FPR
},
407 { "f.3", 3, PPC_OPERAND_FPR
},
408 { "f.30", 30, PPC_OPERAND_FPR
},
409 { "f.31", 31, PPC_OPERAND_FPR
},
410 { "f.32", 32, PPC_OPERAND_VSR
},
411 { "f.33", 33, PPC_OPERAND_VSR
},
412 { "f.34", 34, PPC_OPERAND_VSR
},
413 { "f.35", 35, PPC_OPERAND_VSR
},
414 { "f.36", 36, PPC_OPERAND_VSR
},
415 { "f.37", 37, PPC_OPERAND_VSR
},
416 { "f.38", 38, PPC_OPERAND_VSR
},
417 { "f.39", 39, PPC_OPERAND_VSR
},
418 { "f.4", 4, PPC_OPERAND_FPR
},
419 { "f.40", 40, PPC_OPERAND_VSR
},
420 { "f.41", 41, PPC_OPERAND_VSR
},
421 { "f.42", 42, PPC_OPERAND_VSR
},
422 { "f.43", 43, PPC_OPERAND_VSR
},
423 { "f.44", 44, PPC_OPERAND_VSR
},
424 { "f.45", 45, PPC_OPERAND_VSR
},
425 { "f.46", 46, PPC_OPERAND_VSR
},
426 { "f.47", 47, PPC_OPERAND_VSR
},
427 { "f.48", 48, PPC_OPERAND_VSR
},
428 { "f.49", 49, PPC_OPERAND_VSR
},
429 { "f.5", 5, PPC_OPERAND_FPR
},
430 { "f.50", 50, PPC_OPERAND_VSR
},
431 { "f.51", 51, PPC_OPERAND_VSR
},
432 { "f.52", 52, PPC_OPERAND_VSR
},
433 { "f.53", 53, PPC_OPERAND_VSR
},
434 { "f.54", 54, PPC_OPERAND_VSR
},
435 { "f.55", 55, PPC_OPERAND_VSR
},
436 { "f.56", 56, PPC_OPERAND_VSR
},
437 { "f.57", 57, PPC_OPERAND_VSR
},
438 { "f.58", 58, PPC_OPERAND_VSR
},
439 { "f.59", 59, PPC_OPERAND_VSR
},
440 { "f.6", 6, PPC_OPERAND_FPR
},
441 { "f.60", 60, PPC_OPERAND_VSR
},
442 { "f.61", 61, PPC_OPERAND_VSR
},
443 { "f.62", 62, PPC_OPERAND_VSR
},
444 { "f.63", 63, PPC_OPERAND_VSR
},
445 { "f.7", 7, PPC_OPERAND_FPR
},
446 { "f.8", 8, PPC_OPERAND_FPR
},
447 { "f.9", 9, PPC_OPERAND_FPR
},
449 { "f0", 0, PPC_OPERAND_FPR
},
450 { "f1", 1, PPC_OPERAND_FPR
},
451 { "f10", 10, PPC_OPERAND_FPR
},
452 { "f11", 11, PPC_OPERAND_FPR
},
453 { "f12", 12, PPC_OPERAND_FPR
},
454 { "f13", 13, PPC_OPERAND_FPR
},
455 { "f14", 14, PPC_OPERAND_FPR
},
456 { "f15", 15, PPC_OPERAND_FPR
},
457 { "f16", 16, PPC_OPERAND_FPR
},
458 { "f17", 17, PPC_OPERAND_FPR
},
459 { "f18", 18, PPC_OPERAND_FPR
},
460 { "f19", 19, PPC_OPERAND_FPR
},
461 { "f2", 2, PPC_OPERAND_FPR
},
462 { "f20", 20, PPC_OPERAND_FPR
},
463 { "f21", 21, PPC_OPERAND_FPR
},
464 { "f22", 22, PPC_OPERAND_FPR
},
465 { "f23", 23, PPC_OPERAND_FPR
},
466 { "f24", 24, PPC_OPERAND_FPR
},
467 { "f25", 25, PPC_OPERAND_FPR
},
468 { "f26", 26, PPC_OPERAND_FPR
},
469 { "f27", 27, PPC_OPERAND_FPR
},
470 { "f28", 28, PPC_OPERAND_FPR
},
471 { "f29", 29, PPC_OPERAND_FPR
},
472 { "f3", 3, PPC_OPERAND_FPR
},
473 { "f30", 30, PPC_OPERAND_FPR
},
474 { "f31", 31, PPC_OPERAND_FPR
},
475 { "f32", 32, PPC_OPERAND_VSR
},
476 { "f33", 33, PPC_OPERAND_VSR
},
477 { "f34", 34, PPC_OPERAND_VSR
},
478 { "f35", 35, PPC_OPERAND_VSR
},
479 { "f36", 36, PPC_OPERAND_VSR
},
480 { "f37", 37, PPC_OPERAND_VSR
},
481 { "f38", 38, PPC_OPERAND_VSR
},
482 { "f39", 39, PPC_OPERAND_VSR
},
483 { "f4", 4, PPC_OPERAND_FPR
},
484 { "f40", 40, PPC_OPERAND_VSR
},
485 { "f41", 41, PPC_OPERAND_VSR
},
486 { "f42", 42, PPC_OPERAND_VSR
},
487 { "f43", 43, PPC_OPERAND_VSR
},
488 { "f44", 44, PPC_OPERAND_VSR
},
489 { "f45", 45, PPC_OPERAND_VSR
},
490 { "f46", 46, PPC_OPERAND_VSR
},
491 { "f47", 47, PPC_OPERAND_VSR
},
492 { "f48", 48, PPC_OPERAND_VSR
},
493 { "f49", 49, PPC_OPERAND_VSR
},
494 { "f5", 5, PPC_OPERAND_FPR
},
495 { "f50", 50, PPC_OPERAND_VSR
},
496 { "f51", 51, PPC_OPERAND_VSR
},
497 { "f52", 52, PPC_OPERAND_VSR
},
498 { "f53", 53, PPC_OPERAND_VSR
},
499 { "f54", 54, PPC_OPERAND_VSR
},
500 { "f55", 55, PPC_OPERAND_VSR
},
501 { "f56", 56, PPC_OPERAND_VSR
},
502 { "f57", 57, PPC_OPERAND_VSR
},
503 { "f58", 58, PPC_OPERAND_VSR
},
504 { "f59", 59, PPC_OPERAND_VSR
},
505 { "f6", 6, PPC_OPERAND_FPR
},
506 { "f60", 60, PPC_OPERAND_VSR
},
507 { "f61", 61, PPC_OPERAND_VSR
},
508 { "f62", 62, PPC_OPERAND_VSR
},
509 { "f63", 63, PPC_OPERAND_VSR
},
510 { "f7", 7, PPC_OPERAND_FPR
},
511 { "f8", 8, PPC_OPERAND_FPR
},
512 { "f9", 9, PPC_OPERAND_FPR
},
514 /* Quantization registers used with pair single instructions. */
515 { "gqr.0", 0, PPC_OPERAND_GQR
},
516 { "gqr.1", 1, PPC_OPERAND_GQR
},
517 { "gqr.2", 2, PPC_OPERAND_GQR
},
518 { "gqr.3", 3, PPC_OPERAND_GQR
},
519 { "gqr.4", 4, PPC_OPERAND_GQR
},
520 { "gqr.5", 5, PPC_OPERAND_GQR
},
521 { "gqr.6", 6, PPC_OPERAND_GQR
},
522 { "gqr.7", 7, PPC_OPERAND_GQR
},
523 { "gqr0", 0, PPC_OPERAND_GQR
},
524 { "gqr1", 1, PPC_OPERAND_GQR
},
525 { "gqr2", 2, PPC_OPERAND_GQR
},
526 { "gqr3", 3, PPC_OPERAND_GQR
},
527 { "gqr4", 4, PPC_OPERAND_GQR
},
528 { "gqr5", 5, PPC_OPERAND_GQR
},
529 { "gqr6", 6, PPC_OPERAND_GQR
},
530 { "gqr7", 7, PPC_OPERAND_GQR
},
532 { "lr", 8, PPC_OPERAND_SPR
},
534 /* General Purpose Registers */
535 { "r.0", 0, PPC_OPERAND_GPR
},
536 { "r.1", 1, PPC_OPERAND_GPR
},
537 { "r.10", 10, PPC_OPERAND_GPR
},
538 { "r.11", 11, PPC_OPERAND_GPR
},
539 { "r.12", 12, PPC_OPERAND_GPR
},
540 { "r.13", 13, PPC_OPERAND_GPR
},
541 { "r.14", 14, PPC_OPERAND_GPR
},
542 { "r.15", 15, PPC_OPERAND_GPR
},
543 { "r.16", 16, PPC_OPERAND_GPR
},
544 { "r.17", 17, PPC_OPERAND_GPR
},
545 { "r.18", 18, PPC_OPERAND_GPR
},
546 { "r.19", 19, PPC_OPERAND_GPR
},
547 { "r.2", 2, PPC_OPERAND_GPR
},
548 { "r.20", 20, PPC_OPERAND_GPR
},
549 { "r.21", 21, PPC_OPERAND_GPR
},
550 { "r.22", 22, PPC_OPERAND_GPR
},
551 { "r.23", 23, PPC_OPERAND_GPR
},
552 { "r.24", 24, PPC_OPERAND_GPR
},
553 { "r.25", 25, PPC_OPERAND_GPR
},
554 { "r.26", 26, PPC_OPERAND_GPR
},
555 { "r.27", 27, PPC_OPERAND_GPR
},
556 { "r.28", 28, PPC_OPERAND_GPR
},
557 { "r.29", 29, PPC_OPERAND_GPR
},
558 { "r.3", 3, PPC_OPERAND_GPR
},
559 { "r.30", 30, PPC_OPERAND_GPR
},
560 { "r.31", 31, PPC_OPERAND_GPR
},
561 { "r.4", 4, PPC_OPERAND_GPR
},
562 { "r.5", 5, PPC_OPERAND_GPR
},
563 { "r.6", 6, PPC_OPERAND_GPR
},
564 { "r.7", 7, PPC_OPERAND_GPR
},
565 { "r.8", 8, PPC_OPERAND_GPR
},
566 { "r.9", 9, PPC_OPERAND_GPR
},
568 { "r.sp", 1, PPC_OPERAND_GPR
},
570 { "r.toc", 2, PPC_OPERAND_GPR
},
572 { "r0", 0, PPC_OPERAND_GPR
},
573 { "r1", 1, PPC_OPERAND_GPR
},
574 { "r10", 10, PPC_OPERAND_GPR
},
575 { "r11", 11, PPC_OPERAND_GPR
},
576 { "r12", 12, PPC_OPERAND_GPR
},
577 { "r13", 13, PPC_OPERAND_GPR
},
578 { "r14", 14, PPC_OPERAND_GPR
},
579 { "r15", 15, PPC_OPERAND_GPR
},
580 { "r16", 16, PPC_OPERAND_GPR
},
581 { "r17", 17, PPC_OPERAND_GPR
},
582 { "r18", 18, PPC_OPERAND_GPR
},
583 { "r19", 19, PPC_OPERAND_GPR
},
584 { "r2", 2, PPC_OPERAND_GPR
},
585 { "r20", 20, PPC_OPERAND_GPR
},
586 { "r21", 21, PPC_OPERAND_GPR
},
587 { "r22", 22, PPC_OPERAND_GPR
},
588 { "r23", 23, PPC_OPERAND_GPR
},
589 { "r24", 24, PPC_OPERAND_GPR
},
590 { "r25", 25, PPC_OPERAND_GPR
},
591 { "r26", 26, PPC_OPERAND_GPR
},
592 { "r27", 27, PPC_OPERAND_GPR
},
593 { "r28", 28, PPC_OPERAND_GPR
},
594 { "r29", 29, PPC_OPERAND_GPR
},
595 { "r3", 3, PPC_OPERAND_GPR
},
596 { "r30", 30, PPC_OPERAND_GPR
},
597 { "r31", 31, PPC_OPERAND_GPR
},
598 { "r4", 4, PPC_OPERAND_GPR
},
599 { "r5", 5, PPC_OPERAND_GPR
},
600 { "r6", 6, PPC_OPERAND_GPR
},
601 { "r7", 7, PPC_OPERAND_GPR
},
602 { "r8", 8, PPC_OPERAND_GPR
},
603 { "r9", 9, PPC_OPERAND_GPR
},
605 { "rtoc", 2, PPC_OPERAND_GPR
},
607 { "sdr1", 25, PPC_OPERAND_SPR
},
609 { "sp", 1, PPC_OPERAND_GPR
},
611 { "srr0", 26, PPC_OPERAND_SPR
},
612 { "srr1", 27, PPC_OPERAND_SPR
},
614 /* Vector (Altivec/VMX) registers */
615 { "v.0", 0, PPC_OPERAND_VR
},
616 { "v.1", 1, PPC_OPERAND_VR
},
617 { "v.10", 10, PPC_OPERAND_VR
},
618 { "v.11", 11, PPC_OPERAND_VR
},
619 { "v.12", 12, PPC_OPERAND_VR
},
620 { "v.13", 13, PPC_OPERAND_VR
},
621 { "v.14", 14, PPC_OPERAND_VR
},
622 { "v.15", 15, PPC_OPERAND_VR
},
623 { "v.16", 16, PPC_OPERAND_VR
},
624 { "v.17", 17, PPC_OPERAND_VR
},
625 { "v.18", 18, PPC_OPERAND_VR
},
626 { "v.19", 19, PPC_OPERAND_VR
},
627 { "v.2", 2, PPC_OPERAND_VR
},
628 { "v.20", 20, PPC_OPERAND_VR
},
629 { "v.21", 21, PPC_OPERAND_VR
},
630 { "v.22", 22, PPC_OPERAND_VR
},
631 { "v.23", 23, PPC_OPERAND_VR
},
632 { "v.24", 24, PPC_OPERAND_VR
},
633 { "v.25", 25, PPC_OPERAND_VR
},
634 { "v.26", 26, PPC_OPERAND_VR
},
635 { "v.27", 27, PPC_OPERAND_VR
},
636 { "v.28", 28, PPC_OPERAND_VR
},
637 { "v.29", 29, PPC_OPERAND_VR
},
638 { "v.3", 3, PPC_OPERAND_VR
},
639 { "v.30", 30, PPC_OPERAND_VR
},
640 { "v.31", 31, PPC_OPERAND_VR
},
641 { "v.4", 4, PPC_OPERAND_VR
},
642 { "v.5", 5, PPC_OPERAND_VR
},
643 { "v.6", 6, PPC_OPERAND_VR
},
644 { "v.7", 7, PPC_OPERAND_VR
},
645 { "v.8", 8, PPC_OPERAND_VR
},
646 { "v.9", 9, PPC_OPERAND_VR
},
648 { "v0", 0, PPC_OPERAND_VR
},
649 { "v1", 1, PPC_OPERAND_VR
},
650 { "v10", 10, PPC_OPERAND_VR
},
651 { "v11", 11, PPC_OPERAND_VR
},
652 { "v12", 12, PPC_OPERAND_VR
},
653 { "v13", 13, PPC_OPERAND_VR
},
654 { "v14", 14, PPC_OPERAND_VR
},
655 { "v15", 15, PPC_OPERAND_VR
},
656 { "v16", 16, PPC_OPERAND_VR
},
657 { "v17", 17, PPC_OPERAND_VR
},
658 { "v18", 18, PPC_OPERAND_VR
},
659 { "v19", 19, PPC_OPERAND_VR
},
660 { "v2", 2, PPC_OPERAND_VR
},
661 { "v20", 20, PPC_OPERAND_VR
},
662 { "v21", 21, PPC_OPERAND_VR
},
663 { "v22", 22, PPC_OPERAND_VR
},
664 { "v23", 23, PPC_OPERAND_VR
},
665 { "v24", 24, PPC_OPERAND_VR
},
666 { "v25", 25, PPC_OPERAND_VR
},
667 { "v26", 26, PPC_OPERAND_VR
},
668 { "v27", 27, PPC_OPERAND_VR
},
669 { "v28", 28, PPC_OPERAND_VR
},
670 { "v29", 29, PPC_OPERAND_VR
},
671 { "v3", 3, PPC_OPERAND_VR
},
672 { "v30", 30, PPC_OPERAND_VR
},
673 { "v31", 31, PPC_OPERAND_VR
},
674 { "v4", 4, PPC_OPERAND_VR
},
675 { "v5", 5, PPC_OPERAND_VR
},
676 { "v6", 6, PPC_OPERAND_VR
},
677 { "v7", 7, PPC_OPERAND_VR
},
678 { "v8", 8, PPC_OPERAND_VR
},
679 { "v9", 9, PPC_OPERAND_VR
},
681 /* Vector Scalar (VSX) registers (ISA 2.06). */
682 { "vs.0", 0, PPC_OPERAND_VSR
},
683 { "vs.1", 1, PPC_OPERAND_VSR
},
684 { "vs.10", 10, PPC_OPERAND_VSR
},
685 { "vs.11", 11, PPC_OPERAND_VSR
},
686 { "vs.12", 12, PPC_OPERAND_VSR
},
687 { "vs.13", 13, PPC_OPERAND_VSR
},
688 { "vs.14", 14, PPC_OPERAND_VSR
},
689 { "vs.15", 15, PPC_OPERAND_VSR
},
690 { "vs.16", 16, PPC_OPERAND_VSR
},
691 { "vs.17", 17, PPC_OPERAND_VSR
},
692 { "vs.18", 18, PPC_OPERAND_VSR
},
693 { "vs.19", 19, PPC_OPERAND_VSR
},
694 { "vs.2", 2, PPC_OPERAND_VSR
},
695 { "vs.20", 20, PPC_OPERAND_VSR
},
696 { "vs.21", 21, PPC_OPERAND_VSR
},
697 { "vs.22", 22, PPC_OPERAND_VSR
},
698 { "vs.23", 23, PPC_OPERAND_VSR
},
699 { "vs.24", 24, PPC_OPERAND_VSR
},
700 { "vs.25", 25, PPC_OPERAND_VSR
},
701 { "vs.26", 26, PPC_OPERAND_VSR
},
702 { "vs.27", 27, PPC_OPERAND_VSR
},
703 { "vs.28", 28, PPC_OPERAND_VSR
},
704 { "vs.29", 29, PPC_OPERAND_VSR
},
705 { "vs.3", 3, PPC_OPERAND_VSR
},
706 { "vs.30", 30, PPC_OPERAND_VSR
},
707 { "vs.31", 31, PPC_OPERAND_VSR
},
708 { "vs.32", 32, PPC_OPERAND_VSR
},
709 { "vs.33", 33, PPC_OPERAND_VSR
},
710 { "vs.34", 34, PPC_OPERAND_VSR
},
711 { "vs.35", 35, PPC_OPERAND_VSR
},
712 { "vs.36", 36, PPC_OPERAND_VSR
},
713 { "vs.37", 37, PPC_OPERAND_VSR
},
714 { "vs.38", 38, PPC_OPERAND_VSR
},
715 { "vs.39", 39, PPC_OPERAND_VSR
},
716 { "vs.4", 4, PPC_OPERAND_VSR
},
717 { "vs.40", 40, PPC_OPERAND_VSR
},
718 { "vs.41", 41, PPC_OPERAND_VSR
},
719 { "vs.42", 42, PPC_OPERAND_VSR
},
720 { "vs.43", 43, PPC_OPERAND_VSR
},
721 { "vs.44", 44, PPC_OPERAND_VSR
},
722 { "vs.45", 45, PPC_OPERAND_VSR
},
723 { "vs.46", 46, PPC_OPERAND_VSR
},
724 { "vs.47", 47, PPC_OPERAND_VSR
},
725 { "vs.48", 48, PPC_OPERAND_VSR
},
726 { "vs.49", 49, PPC_OPERAND_VSR
},
727 { "vs.5", 5, PPC_OPERAND_VSR
},
728 { "vs.50", 50, PPC_OPERAND_VSR
},
729 { "vs.51", 51, PPC_OPERAND_VSR
},
730 { "vs.52", 52, PPC_OPERAND_VSR
},
731 { "vs.53", 53, PPC_OPERAND_VSR
},
732 { "vs.54", 54, PPC_OPERAND_VSR
},
733 { "vs.55", 55, PPC_OPERAND_VSR
},
734 { "vs.56", 56, PPC_OPERAND_VSR
},
735 { "vs.57", 57, PPC_OPERAND_VSR
},
736 { "vs.58", 58, PPC_OPERAND_VSR
},
737 { "vs.59", 59, PPC_OPERAND_VSR
},
738 { "vs.6", 6, PPC_OPERAND_VSR
},
739 { "vs.60", 60, PPC_OPERAND_VSR
},
740 { "vs.61", 61, PPC_OPERAND_VSR
},
741 { "vs.62", 62, PPC_OPERAND_VSR
},
742 { "vs.63", 63, PPC_OPERAND_VSR
},
743 { "vs.7", 7, PPC_OPERAND_VSR
},
744 { "vs.8", 8, PPC_OPERAND_VSR
},
745 { "vs.9", 9, PPC_OPERAND_VSR
},
747 { "vs0", 0, PPC_OPERAND_VSR
},
748 { "vs1", 1, PPC_OPERAND_VSR
},
749 { "vs10", 10, PPC_OPERAND_VSR
},
750 { "vs11", 11, PPC_OPERAND_VSR
},
751 { "vs12", 12, PPC_OPERAND_VSR
},
752 { "vs13", 13, PPC_OPERAND_VSR
},
753 { "vs14", 14, PPC_OPERAND_VSR
},
754 { "vs15", 15, PPC_OPERAND_VSR
},
755 { "vs16", 16, PPC_OPERAND_VSR
},
756 { "vs17", 17, PPC_OPERAND_VSR
},
757 { "vs18", 18, PPC_OPERAND_VSR
},
758 { "vs19", 19, PPC_OPERAND_VSR
},
759 { "vs2", 2, PPC_OPERAND_VSR
},
760 { "vs20", 20, PPC_OPERAND_VSR
},
761 { "vs21", 21, PPC_OPERAND_VSR
},
762 { "vs22", 22, PPC_OPERAND_VSR
},
763 { "vs23", 23, PPC_OPERAND_VSR
},
764 { "vs24", 24, PPC_OPERAND_VSR
},
765 { "vs25", 25, PPC_OPERAND_VSR
},
766 { "vs26", 26, PPC_OPERAND_VSR
},
767 { "vs27", 27, PPC_OPERAND_VSR
},
768 { "vs28", 28, PPC_OPERAND_VSR
},
769 { "vs29", 29, PPC_OPERAND_VSR
},
770 { "vs3", 3, PPC_OPERAND_VSR
},
771 { "vs30", 30, PPC_OPERAND_VSR
},
772 { "vs31", 31, PPC_OPERAND_VSR
},
773 { "vs32", 32, PPC_OPERAND_VSR
},
774 { "vs33", 33, PPC_OPERAND_VSR
},
775 { "vs34", 34, PPC_OPERAND_VSR
},
776 { "vs35", 35, PPC_OPERAND_VSR
},
777 { "vs36", 36, PPC_OPERAND_VSR
},
778 { "vs37", 37, PPC_OPERAND_VSR
},
779 { "vs38", 38, PPC_OPERAND_VSR
},
780 { "vs39", 39, PPC_OPERAND_VSR
},
781 { "vs4", 4, PPC_OPERAND_VSR
},
782 { "vs40", 40, PPC_OPERAND_VSR
},
783 { "vs41", 41, PPC_OPERAND_VSR
},
784 { "vs42", 42, PPC_OPERAND_VSR
},
785 { "vs43", 43, PPC_OPERAND_VSR
},
786 { "vs44", 44, PPC_OPERAND_VSR
},
787 { "vs45", 45, PPC_OPERAND_VSR
},
788 { "vs46", 46, PPC_OPERAND_VSR
},
789 { "vs47", 47, PPC_OPERAND_VSR
},
790 { "vs48", 48, PPC_OPERAND_VSR
},
791 { "vs49", 49, PPC_OPERAND_VSR
},
792 { "vs5", 5, PPC_OPERAND_VSR
},
793 { "vs50", 50, PPC_OPERAND_VSR
},
794 { "vs51", 51, PPC_OPERAND_VSR
},
795 { "vs52", 52, PPC_OPERAND_VSR
},
796 { "vs53", 53, PPC_OPERAND_VSR
},
797 { "vs54", 54, PPC_OPERAND_VSR
},
798 { "vs55", 55, PPC_OPERAND_VSR
},
799 { "vs56", 56, PPC_OPERAND_VSR
},
800 { "vs57", 57, PPC_OPERAND_VSR
},
801 { "vs58", 58, PPC_OPERAND_VSR
},
802 { "vs59", 59, PPC_OPERAND_VSR
},
803 { "vs6", 6, PPC_OPERAND_VSR
},
804 { "vs60", 60, PPC_OPERAND_VSR
},
805 { "vs61", 61, PPC_OPERAND_VSR
},
806 { "vs62", 62, PPC_OPERAND_VSR
},
807 { "vs63", 63, PPC_OPERAND_VSR
},
808 { "vs7", 7, PPC_OPERAND_VSR
},
809 { "vs8", 8, PPC_OPERAND_VSR
},
810 { "vs9", 9, PPC_OPERAND_VSR
},
812 { "xer", 1, PPC_OPERAND_SPR
}
815 #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg))
817 /* Given NAME, find the register number associated with that name, return
818 the integer value associated with the given name or -1 on failure. */
820 static const struct pd_reg
*
821 reg_name_search (const struct pd_reg
*regs
, int regcount
, const char *name
)
823 int middle
, low
, high
;
831 middle
= (low
+ high
) / 2;
832 cmp
= strcasecmp (name
, regs
[middle
].name
);
838 return ®s
[middle
];
846 * Summary of register_name.
848 * in: Input_line_pointer points to 1st char of operand.
850 * out: A expressionS.
851 * The operand may have been a register: in this case, X_op == O_register,
852 * X_add_number is set to the register number, and truth is returned.
853 * Input_line_pointer->(next non-blank) char after operand, or is in its
858 register_name (expressionS
*expressionP
)
860 const struct pd_reg
*reg
;
865 /* Find the spelling of the operand. */
866 start
= name
= input_line_pointer
;
867 if (name
[0] == '%' && ISALPHA (name
[1]))
868 name
= ++input_line_pointer
;
870 else if (!reg_names_p
|| !ISALPHA (name
[0]))
873 c
= get_symbol_name (&name
);
874 reg
= reg_name_search (pre_defined_registers
, REG_NAME_CNT
, name
);
876 /* Put back the delimiting char. */
877 *input_line_pointer
= c
;
879 /* Look to see if it's in the register table. */
882 expressionP
->X_op
= O_register
;
883 expressionP
->X_add_number
= reg
->value
;
884 expressionP
->X_md
= reg
->flags
;
886 /* Make the rest nice. */
887 expressionP
->X_add_symbol
= NULL
;
888 expressionP
->X_op_symbol
= NULL
;
892 /* Reset the line as if we had not done anything. */
893 input_line_pointer
= start
;
897 /* This function is called for each symbol seen in an expression. It
898 handles the special parsing which PowerPC assemblers are supposed
899 to use for condition codes. */
901 /* Whether to do the special parsing. */
902 static bfd_boolean cr_operand
;
904 /* Names to recognize in a condition code. This table is sorted. */
905 static const struct pd_reg cr_names
[] =
907 { "cr0", 0, PPC_OPERAND_CR_REG
},
908 { "cr1", 1, PPC_OPERAND_CR_REG
},
909 { "cr2", 2, PPC_OPERAND_CR_REG
},
910 { "cr3", 3, PPC_OPERAND_CR_REG
},
911 { "cr4", 4, PPC_OPERAND_CR_REG
},
912 { "cr5", 5, PPC_OPERAND_CR_REG
},
913 { "cr6", 6, PPC_OPERAND_CR_REG
},
914 { "cr7", 7, PPC_OPERAND_CR_REG
},
915 { "eq", 2, PPC_OPERAND_CR_BIT
},
916 { "gt", 1, PPC_OPERAND_CR_BIT
},
917 { "lt", 0, PPC_OPERAND_CR_BIT
},
918 { "so", 3, PPC_OPERAND_CR_BIT
},
919 { "un", 3, PPC_OPERAND_CR_BIT
}
922 /* Parsing function. This returns non-zero if it recognized an
926 ppc_parse_name (const char *name
, expressionS
*exp
)
928 const struct pd_reg
*reg
;
935 reg
= reg_name_search (cr_names
, sizeof cr_names
/ sizeof cr_names
[0],
940 exp
->X_op
= O_register
;
941 exp
->X_add_number
= reg
->value
;
942 exp
->X_md
= reg
->flags
;
947 /* Propagate X_md and check register expressions. This is to support
948 condition codes like 4*cr5+eq. */
951 ppc_optimize_expr (expressionS
*left
, operatorT op
, expressionS
*right
)
953 /* Accept 4*cr<n> and cr<n>*4. */
955 && ((right
->X_op
== O_register
956 && right
->X_md
== PPC_OPERAND_CR_REG
957 && left
->X_op
== O_constant
958 && left
->X_add_number
== 4)
959 || (left
->X_op
== O_register
960 && left
->X_md
== PPC_OPERAND_CR_REG
961 && right
->X_op
== O_constant
962 && right
->X_add_number
== 4)))
964 left
->X_op
= O_register
;
965 left
->X_md
= PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
;
966 left
->X_add_number
*= right
->X_add_number
;
970 /* Accept the above plus <cr bit>, and <cr bit> plus the above. */
971 if (right
->X_op
== O_register
972 && left
->X_op
== O_register
974 && ((right
->X_md
== PPC_OPERAND_CR_BIT
975 && left
->X_md
== (PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
))
976 || (right
->X_md
== (PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
)
977 && left
->X_md
== PPC_OPERAND_CR_BIT
)))
979 left
->X_md
= PPC_OPERAND_CR_BIT
;
980 right
->X_op
= O_constant
;
984 /* Accept reg +/- constant. */
985 if (left
->X_op
== O_register
986 && !((op
== O_add
|| op
== O_subtract
) && right
->X_op
== O_constant
))
987 as_warn (_("invalid register expression"));
989 /* Accept constant + reg. */
990 if (right
->X_op
== O_register
)
992 if (op
== O_add
&& left
->X_op
== O_constant
)
993 left
->X_md
= right
->X_md
;
995 as_warn (_("invalid register expression"));
1001 /* Local variables. */
1003 /* Whether to target xcoff64/elf64. */
1004 static unsigned int ppc_obj64
= BFD_DEFAULT_TARGET_SIZE
== 64;
1006 /* Opcode hash table. */
1007 static struct hash_control
*ppc_hash
;
1009 /* Macro hash table. */
1010 static struct hash_control
*ppc_macro_hash
;
1013 /* What type of shared library support to use. */
1014 static enum { SHLIB_NONE
, SHLIB_PIC
, SHLIB_MRELOCATABLE
} shlib
= SHLIB_NONE
;
1016 /* Flags to set in the elf header. */
1017 static flagword ppc_flags
= 0;
1019 /* Whether this is Solaris or not. */
1020 #ifdef TARGET_SOLARIS_COMMENT
1021 #define SOLARIS_P TRUE
1023 #define SOLARIS_P FALSE
1026 static bfd_boolean msolaris
= SOLARIS_P
;
1031 /* The RS/6000 assembler uses the .csect pseudo-op to generate code
1032 using a bunch of different sections. These assembler sections,
1033 however, are all encompassed within the .text or .data sections of
1034 the final output file. We handle this by using different
1035 subsegments within these main segments. */
1037 /* Next subsegment to allocate within the .text segment. */
1038 static subsegT ppc_text_subsegment
= 2;
1040 /* Linked list of csects in the text section. */
1041 static symbolS
*ppc_text_csects
;
1043 /* Next subsegment to allocate within the .data segment. */
1044 static subsegT ppc_data_subsegment
= 2;
1046 /* Linked list of csects in the data section. */
1047 static symbolS
*ppc_data_csects
;
1049 /* The current csect. */
1050 static symbolS
*ppc_current_csect
;
1052 /* The RS/6000 assembler uses a TOC which holds addresses of functions
1053 and variables. Symbols are put in the TOC with the .tc pseudo-op.
1054 A special relocation is used when accessing TOC entries. We handle
1055 the TOC as a subsegment within the .data segment. We set it up if
1056 we see a .toc pseudo-op, and save the csect symbol here. */
1057 static symbolS
*ppc_toc_csect
;
1059 /* The first frag in the TOC subsegment. */
1060 static fragS
*ppc_toc_frag
;
1062 /* The first frag in the first subsegment after the TOC in the .data
1063 segment. NULL if there are no subsegments after the TOC. */
1064 static fragS
*ppc_after_toc_frag
;
1066 /* The current static block. */
1067 static symbolS
*ppc_current_block
;
1069 /* The COFF debugging section; set by md_begin. This is not the
1070 .debug section, but is instead the secret BFD section which will
1071 cause BFD to set the section number of a symbol to N_DEBUG. */
1072 static asection
*ppc_coff_debug_section
;
1074 /* Structure to set the length field of the dwarf sections. */
1075 struct dw_subsection
{
1076 /* Subsections are simply linked. */
1077 struct dw_subsection
*link
;
1079 /* The subsection number. */
1082 /* Expression to compute the length of the section. */
1083 expressionS end_exp
;
1086 static struct dw_section
{
1087 /* Corresponding section. */
1090 /* Simply linked list of subsections with a label. */
1091 struct dw_subsection
*list_subseg
;
1093 /* The anonymous subsection. */
1094 struct dw_subsection
*anon_subseg
;
1095 } dw_sections
[XCOFF_DWSECT_NBR_NAMES
];
1096 #endif /* OBJ_XCOFF */
1100 /* Various sections that we need for PE coff support. */
1101 static segT ydata_section
;
1102 static segT pdata_section
;
1103 static segT reldata_section
;
1104 static segT rdata_section
;
1105 static segT tocdata_section
;
1107 /* The current section and the previous section. See ppc_previous. */
1108 static segT ppc_previous_section
;
1109 static segT ppc_current_section
;
1114 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
1115 unsigned long *ppc_apuinfo_list
;
1116 unsigned int ppc_apuinfo_num
;
1117 unsigned int ppc_apuinfo_num_alloc
;
1118 #endif /* OBJ_ELF */
1121 const char *const md_shortopts
= "b:l:usm:K:VQ:";
1123 const char *const md_shortopts
= "um:";
1125 #define OPTION_NOPS (OPTION_MD_BASE + 0)
1126 const struct option md_longopts
[] = {
1127 {"nops", required_argument
, NULL
, OPTION_NOPS
},
1128 {"ppc476-workaround", no_argument
, &warn_476
, 1},
1129 {"no-ppc476-workaround", no_argument
, &warn_476
, 0},
1130 {NULL
, no_argument
, NULL
, 0}
1132 const size_t md_longopts_size
= sizeof (md_longopts
);
1135 md_parse_option (int c
, const char *arg
)
1142 /* -u means that any undefined symbols should be treated as
1143 external, which is the default for gas anyhow. */
1148 /* Solaris as takes -le (presumably for little endian). For completeness
1149 sake, recognize -be also. */
1150 if (strcmp (arg
, "e") == 0)
1152 target_big_endian
= 0;
1153 set_target_endian
= 1;
1154 if (ppc_cpu
& PPC_OPCODE_VLE
)
1155 as_bad (_("the use of -mvle requires big endian."));
1163 if (strcmp (arg
, "e") == 0)
1165 target_big_endian
= 1;
1166 set_target_endian
= 1;
1174 /* Recognize -K PIC. */
1175 if (strcmp (arg
, "PIC") == 0 || strcmp (arg
, "pic") == 0)
1178 ppc_flags
|= EF_PPC_RELOCATABLE_LIB
;
1186 /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */
1188 if (strcmp (arg
, "64") == 0)
1192 if (ppc_cpu
& PPC_OPCODE_VLE
)
1193 as_bad (_("the use of -mvle requires -a32."));
1195 as_fatal (_("%s unsupported"), "-a64");
1198 else if (strcmp (arg
, "32") == 0)
1205 new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, arg
);
1206 /* "raw" is only valid for the disassembler. */
1207 if (new_cpu
!= 0 && (new_cpu
& PPC_OPCODE_RAW
) == 0)
1210 if (strcmp (arg
, "vle") == 0)
1212 if (set_target_endian
&& target_big_endian
== 0)
1213 as_bad (_("the use of -mvle requires big endian."));
1215 as_bad (_("the use of -mvle requires -a32."));
1219 else if (strcmp (arg
, "no-vle") == 0)
1221 sticky
&= ~PPC_OPCODE_VLE
;
1223 new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, "booke");
1224 new_cpu
&= ~PPC_OPCODE_VLE
;
1229 else if (strcmp (arg
, "regnames") == 0)
1232 else if (strcmp (arg
, "no-regnames") == 0)
1233 reg_names_p
= FALSE
;
1236 /* -mrelocatable/-mrelocatable-lib -- warn about initializations
1237 that require relocation. */
1238 else if (strcmp (arg
, "relocatable") == 0)
1240 shlib
= SHLIB_MRELOCATABLE
;
1241 ppc_flags
|= EF_PPC_RELOCATABLE
;
1244 else if (strcmp (arg
, "relocatable-lib") == 0)
1246 shlib
= SHLIB_MRELOCATABLE
;
1247 ppc_flags
|= EF_PPC_RELOCATABLE_LIB
;
1250 /* -memb, set embedded bit. */
1251 else if (strcmp (arg
, "emb") == 0)
1252 ppc_flags
|= EF_PPC_EMB
;
1254 /* -mlittle/-mbig set the endianness. */
1255 else if (strcmp (arg
, "little") == 0
1256 || strcmp (arg
, "little-endian") == 0)
1258 target_big_endian
= 0;
1259 set_target_endian
= 1;
1260 if (ppc_cpu
& PPC_OPCODE_VLE
)
1261 as_bad (_("the use of -mvle requires big endian."));
1264 else if (strcmp (arg
, "big") == 0 || strcmp (arg
, "big-endian") == 0)
1266 target_big_endian
= 1;
1267 set_target_endian
= 1;
1270 else if (strcmp (arg
, "solaris") == 0)
1273 ppc_comment_chars
= ppc_solaris_comment_chars
;
1276 else if (strcmp (arg
, "no-solaris") == 0)
1279 ppc_comment_chars
= ppc_eabi_comment_chars
;
1281 else if (strcmp (arg
, "spe2") == 0)
1283 ppc_cpu
|= PPC_OPCODE_SPE2
;
1288 as_bad (_("invalid switch -m%s"), arg
);
1294 /* -V: SVR4 argument to print version ID. */
1296 print_version_id ();
1299 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
1300 should be emitted or not. FIXME: Not implemented. */
1304 /* Solaris takes -s to specify that .stabs go in a .stabs section,
1305 rather than .stabs.excl, which is ignored by the linker.
1306 FIXME: Not implemented. */
1317 nop_limit
= strtoul (optarg
, &end
, 0);
1319 as_bad (_("--nops needs a numeric argument"));
1334 is_ppc64_target (const bfd_target
*targ
, void *data ATTRIBUTE_UNUSED
)
1336 switch (targ
->flavour
)
1339 case bfd_target_elf_flavour
:
1340 return strncmp (targ
->name
, "elf64-powerpc", 13) == 0;
1343 case bfd_target_xcoff_flavour
:
1344 return (strcmp (targ
->name
, "aixcoff64-rs6000") == 0
1345 || strcmp (targ
->name
, "aix5coff64-rs6000") == 0);
1353 md_show_usage (FILE *stream
)
1355 fprintf (stream
, _("\
1356 PowerPC options:\n"));
1357 fprintf (stream
, _("\
1358 -a32 generate ELF32/XCOFF32\n"));
1359 if (bfd_iterate_over_targets (is_ppc64_target
, NULL
))
1360 fprintf (stream
, _("\
1361 -a64 generate ELF64/XCOFF64\n"));
1362 fprintf (stream
, _("\
1364 fprintf (stream
, _("\
1365 -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n"));
1366 fprintf (stream
, _("\
1367 -mpwr generate code for POWER (RIOS1)\n"));
1368 fprintf (stream
, _("\
1369 -m601 generate code for PowerPC 601\n"));
1370 fprintf (stream
, _("\
1371 -mppc, -mppc32, -m603, -m604\n\
1372 generate code for PowerPC 603/604\n"));
1373 fprintf (stream
, _("\
1374 -m403 generate code for PowerPC 403\n"));
1375 fprintf (stream
, _("\
1376 -m405 generate code for PowerPC 405\n"));
1377 fprintf (stream
, _("\
1378 -m440 generate code for PowerPC 440\n"));
1379 fprintf (stream
, _("\
1380 -m464 generate code for PowerPC 464\n"));
1381 fprintf (stream
, _("\
1382 -m476 generate code for PowerPC 476\n"));
1383 fprintf (stream
, _("\
1384 -m7400, -m7410, -m7450, -m7455\n\
1385 generate code for PowerPC 7400/7410/7450/7455\n"));
1386 fprintf (stream
, _("\
1387 -m750cl, -mgekko, -mbroadway\n\
1388 generate code for PowerPC 750cl/Gekko/Broadway\n"));
1389 fprintf (stream
, _("\
1390 -m821, -m850, -m860 generate code for PowerPC 821/850/860\n"));
1391 fprintf (stream
, _("\
1392 -mppc64, -m620 generate code for PowerPC 620/625/630\n"));
1393 fprintf (stream
, _("\
1394 -mppc64bridge generate code for PowerPC 64, including bridge insns\n"));
1395 fprintf (stream
, _("\
1396 -mbooke generate code for 32-bit PowerPC BookE\n"));
1397 fprintf (stream
, _("\
1398 -ma2 generate code for A2 architecture\n"));
1399 fprintf (stream
, _("\
1400 -mpower4, -mpwr4 generate code for Power4 architecture\n"));
1401 fprintf (stream
, _("\
1402 -mpower5, -mpwr5, -mpwr5x\n\
1403 generate code for Power5 architecture\n"));
1404 fprintf (stream
, _("\
1405 -mpower6, -mpwr6 generate code for Power6 architecture\n"));
1406 fprintf (stream
, _("\
1407 -mpower7, -mpwr7 generate code for Power7 architecture\n"));
1408 fprintf (stream
, _("\
1409 -mpower8, -mpwr8 generate code for Power8 architecture\n"));
1410 fprintf (stream
, _("\
1411 -mpower9, -mpwr9 generate code for Power9 architecture\n"));
1412 fprintf (stream
, _("\
1413 -mcell generate code for Cell Broadband Engine architecture\n"));
1414 fprintf (stream
, _("\
1415 -mcom generate code for Power/PowerPC common instructions\n"));
1416 fprintf (stream
, _("\
1417 -many generate code for any architecture (PWR/PWRX/PPC)\n"));
1418 fprintf (stream
, _("\
1419 -maltivec generate code for AltiVec\n"));
1420 fprintf (stream
, _("\
1421 -mvsx generate code for Vector-Scalar (VSX) instructions\n"));
1422 fprintf (stream
, _("\
1423 -me300 generate code for PowerPC e300 family\n"));
1424 fprintf (stream
, _("\
1425 -me500, -me500x2 generate code for Motorola e500 core complex\n"));
1426 fprintf (stream
, _("\
1427 -me500mc, generate code for Freescale e500mc core complex\n"));
1428 fprintf (stream
, _("\
1429 -me500mc64, generate code for Freescale e500mc64 core complex\n"));
1430 fprintf (stream
, _("\
1431 -me5500, generate code for Freescale e5500 core complex\n"));
1432 fprintf (stream
, _("\
1433 -me6500, generate code for Freescale e6500 core complex\n"));
1434 fprintf (stream
, _("\
1435 -mspe generate code for Motorola SPE instructions\n"));
1436 fprintf (stream
, _("\
1437 -mspe2 generate code for Freescale SPE2 instructions\n"));
1438 fprintf (stream
, _("\
1439 -mvle generate code for Freescale VLE instructions\n"));
1440 fprintf (stream
, _("\
1441 -mtitan generate code for AppliedMicro Titan core complex\n"));
1442 fprintf (stream
, _("\
1443 -mregnames Allow symbolic names for registers\n"));
1444 fprintf (stream
, _("\
1445 -mno-regnames Do not allow symbolic names for registers\n"));
1447 fprintf (stream
, _("\
1448 -mrelocatable support for GCC's -mrelocatble option\n"));
1449 fprintf (stream
, _("\
1450 -mrelocatable-lib support for GCC's -mrelocatble-lib option\n"));
1451 fprintf (stream
, _("\
1452 -memb set PPC_EMB bit in ELF flags\n"));
1453 fprintf (stream
, _("\
1454 -mlittle, -mlittle-endian, -le\n\
1455 generate code for a little endian machine\n"));
1456 fprintf (stream
, _("\
1457 -mbig, -mbig-endian, -be\n\
1458 generate code for a big endian machine\n"));
1459 fprintf (stream
, _("\
1460 -msolaris generate code for Solaris\n"));
1461 fprintf (stream
, _("\
1462 -mno-solaris do not generate code for Solaris\n"));
1463 fprintf (stream
, _("\
1464 -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n"));
1465 fprintf (stream
, _("\
1466 -V print assembler version number\n"));
1467 fprintf (stream
, _("\
1468 -Qy, -Qn ignored\n"));
1470 fprintf (stream
, _("\
1471 -nops=count when aligning, more than COUNT nops uses a branch\n"));
1472 fprintf (stream
, _("\
1473 -ppc476-workaround warn if emitting data to code sections\n"));
1476 /* Set ppc_cpu if it is not already set. */
1481 const char *default_os
= TARGET_OS
;
1482 const char *default_cpu
= TARGET_CPU
;
1484 if ((ppc_cpu
& ~(ppc_cpu_t
) PPC_OPCODE_ANY
) == 0)
1487 if (target_big_endian
)
1488 ppc_cpu
|= PPC_OPCODE_PPC
| PPC_OPCODE_64
;
1490 /* The minimum supported cpu for 64-bit little-endian is power8. */
1491 ppc_cpu
|= ppc_parse_cpu (ppc_cpu
, &sticky
, "power8");
1492 else if (strncmp (default_os
, "aix", 3) == 0
1493 && default_os
[3] >= '4' && default_os
[3] <= '9')
1494 ppc_cpu
|= PPC_OPCODE_COMMON
;
1495 else if (strncmp (default_os
, "aix3", 4) == 0)
1496 ppc_cpu
|= PPC_OPCODE_POWER
;
1497 else if (strcmp (default_cpu
, "rs6000") == 0)
1498 ppc_cpu
|= PPC_OPCODE_POWER
;
1499 else if (strncmp (default_cpu
, "powerpc", 7) == 0)
1500 ppc_cpu
|= PPC_OPCODE_PPC
;
1502 as_fatal (_("unknown default cpu = %s, os = %s"),
1503 default_cpu
, default_os
);
1507 /* Figure out the BFD architecture to use. This function and ppc_mach
1508 are called well before md_begin, when the output file is opened. */
1510 enum bfd_architecture
1513 const char *default_cpu
= TARGET_CPU
;
1516 if ((ppc_cpu
& PPC_OPCODE_PPC
) != 0)
1517 return bfd_arch_powerpc
;
1518 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
1519 return bfd_arch_powerpc
;
1520 if ((ppc_cpu
& PPC_OPCODE_POWER
) != 0)
1521 return bfd_arch_rs6000
;
1522 if ((ppc_cpu
& (PPC_OPCODE_COMMON
| PPC_OPCODE_ANY
)) != 0)
1524 if (strcmp (default_cpu
, "rs6000") == 0)
1525 return bfd_arch_rs6000
;
1526 else if (strncmp (default_cpu
, "powerpc", 7) == 0)
1527 return bfd_arch_powerpc
;
1530 as_fatal (_("neither Power nor PowerPC opcodes were selected."));
1531 return bfd_arch_unknown
;
1538 return bfd_mach_ppc64
;
1539 else if (ppc_arch () == bfd_arch_rs6000
)
1540 return bfd_mach_rs6k
;
1541 else if (ppc_cpu
& PPC_OPCODE_TITAN
)
1542 return bfd_mach_ppc_titan
;
1543 else if (ppc_cpu
& PPC_OPCODE_VLE
)
1544 return bfd_mach_ppc_vle
;
1546 return bfd_mach_ppc
;
1550 ppc_target_format (void)
1554 return target_big_endian
? "pe-powerpc" : "pe-powerpcle";
1556 return "xcoff-powermac";
1559 return (ppc_obj64
? "aix5coff64-rs6000" : "aixcoff-rs6000");
1561 return (ppc_obj64
? "aixcoff64-rs6000" : "aixcoff-rs6000");
1567 return (ppc_obj64
? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd");
1568 # elif defined (TE_VXWORKS)
1569 return "elf32-powerpc-vxworks";
1571 return (target_big_endian
1572 ? (ppc_obj64
? "elf64-powerpc" : "elf32-powerpc")
1573 : (ppc_obj64
? "elf64-powerpcle" : "elf32-powerpcle"));
1578 /* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
1579 Return TRUE if there's a problem, otherwise FALSE. */
1582 insn_validate (const struct powerpc_opcode
*op
)
1584 const unsigned char *o
;
1585 uint64_t omask
= op
->mask
;
1587 /* The mask had better not trim off opcode bits. */
1588 if ((op
->opcode
& omask
) != op
->opcode
)
1590 as_bad (_("mask trims opcode bits for %s"), op
->name
);
1594 /* The operands must not overlap the opcode or each other. */
1595 for (o
= op
->operands
; *o
; ++o
)
1597 bfd_boolean optional
= FALSE
;
1598 if (*o
>= num_powerpc_operands
)
1600 as_bad (_("operand index error for %s"), op
->name
);
1606 const struct powerpc_operand
*operand
= &powerpc_operands
[*o
];
1607 if (operand
->shift
== (int) PPC_OPSHIFT_INV
)
1614 if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
1616 else if ((operand
->flags
& PPC_OPERAND_PLUS1
) != 0)
1618 mask
= (*operand
->insert
) (0, val
, ppc_cpu
, &errmsg
);
1620 else if (operand
->shift
>= 0)
1621 mask
= operand
->bitm
<< operand
->shift
;
1623 mask
= operand
->bitm
>> -operand
->shift
;
1626 as_bad (_("operand %d overlap in %s"),
1627 (int) (o
- op
->operands
), op
->name
);
1631 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
1635 as_bad (_("non-optional operand %d follows optional operand in %s"),
1636 (int) (o
- op
->operands
), op
->name
);
1644 /* Insert opcodes and macros into hash tables. Called at startup and
1645 for .machine pseudo. */
1648 ppc_setup_opcodes (void)
1650 const struct powerpc_opcode
*op
;
1651 const struct powerpc_opcode
*op_end
;
1652 const struct powerpc_macro
*macro
;
1653 const struct powerpc_macro
*macro_end
;
1654 bfd_boolean bad_insn
= FALSE
;
1656 if (ppc_hash
!= NULL
)
1657 hash_die (ppc_hash
);
1658 if (ppc_macro_hash
!= NULL
)
1659 hash_die (ppc_macro_hash
);
1661 /* Insert the opcodes into a hash table. */
1662 ppc_hash
= hash_new ();
1664 if (ENABLE_CHECKING
)
1668 /* An index into powerpc_operands is stored in struct fix
1669 fx_pcrel_adjust which is 8 bits wide. */
1670 gas_assert (num_powerpc_operands
< 256);
1672 /* Check operand masks. Code here and in the disassembler assumes
1673 all the 1's in the mask are contiguous. */
1674 for (i
= 0; i
< num_powerpc_operands
; ++i
)
1676 uint64_t mask
= powerpc_operands
[i
].bitm
;
1680 right_bit
= mask
& -mask
;
1682 right_bit
= mask
& -mask
;
1683 if (mask
!= right_bit
)
1685 as_bad (_("powerpc_operands[%d].bitm invalid"), i
);
1688 for (j
= i
+ 1; j
< num_powerpc_operands
; ++j
)
1689 if (memcmp (&powerpc_operands
[i
], &powerpc_operands
[j
],
1690 sizeof (powerpc_operands
[0])) == 0)
1692 as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
1699 op_end
= powerpc_opcodes
+ powerpc_num_opcodes
;
1700 for (op
= powerpc_opcodes
; op
< op_end
; op
++)
1702 if (ENABLE_CHECKING
)
1704 unsigned int new_opcode
= PPC_OP (op
[0].opcode
);
1706 #ifdef PRINT_OPCODE_TABLE
1707 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1708 op
->name
, (unsigned int) (op
- powerpc_opcodes
),
1709 new_opcode
, (unsigned long long) op
->opcode
,
1710 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1713 /* The major opcodes had better be sorted. Code in the disassembler
1714 assumes the insns are sorted according to major opcode. */
1715 if (op
!= powerpc_opcodes
1716 && new_opcode
< PPC_OP (op
[-1].opcode
))
1718 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1722 if ((op
->flags
& PPC_OPCODE_VLE
) != 0)
1724 as_bad (_("%s is enabled by vle flag"), op
->name
);
1727 if (PPC_OP (op
->opcode
) != 4
1728 && PPC_OP (op
->opcode
) != 31
1729 && (op
->deprecated
& PPC_OPCODE_VLE
) == 0)
1731 as_bad (_("%s not disabled by vle flag"), op
->name
);
1734 bad_insn
|= insn_validate (op
);
1737 if ((ppc_cpu
& op
->flags
) != 0
1738 && !(ppc_cpu
& op
->deprecated
))
1742 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1745 as_bad (_("duplicate instruction %s"),
1752 if ((ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1753 for (op
= powerpc_opcodes
; op
< op_end
; op
++)
1754 hash_insert (ppc_hash
, op
->name
, (void *) op
);
1756 op_end
= prefix_opcodes
+ prefix_num_opcodes
;
1757 for (op
= prefix_opcodes
; op
< op_end
; op
++)
1759 if (ENABLE_CHECKING
)
1761 unsigned int new_opcode
= PPC_PREFIX_SEG (op
[0].opcode
);
1763 #ifdef PRINT_OPCODE_TABLE
1764 printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1765 op
->name
, (unsigned int) (op
- prefix_opcodes
),
1766 new_opcode
, (unsigned long long) op
->opcode
,
1767 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1770 /* The major opcodes had better be sorted. Code in the disassembler
1771 assumes the insns are sorted according to major opcode. */
1772 if (op
!= prefix_opcodes
1773 && new_opcode
< PPC_PREFIX_SEG (op
[-1].opcode
))
1775 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1778 bad_insn
|= insn_validate (op
);
1781 if ((ppc_cpu
& op
->flags
) != 0
1782 && !(ppc_cpu
& op
->deprecated
))
1786 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1789 as_bad (_("duplicate instruction %s"),
1796 if ((ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1797 for (op
= prefix_opcodes
; op
< op_end
; op
++)
1798 hash_insert (ppc_hash
, op
->name
, (void *) op
);
1800 op_end
= vle_opcodes
+ vle_num_opcodes
;
1801 for (op
= vle_opcodes
; op
< op_end
; op
++)
1803 if (ENABLE_CHECKING
)
1805 unsigned new_seg
= VLE_OP_TO_SEG (VLE_OP (op
[0].opcode
, op
[0].mask
));
1807 #ifdef PRINT_OPCODE_TABLE
1808 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1809 op
->name
, (unsigned int) (op
- vle_opcodes
),
1810 (unsigned int) new_seg
, (unsigned long long) op
->opcode
,
1811 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1814 /* The major opcodes had better be sorted. Code in the disassembler
1815 assumes the insns are sorted according to major opcode. */
1816 if (op
!= vle_opcodes
1817 && new_seg
< VLE_OP_TO_SEG (VLE_OP (op
[-1].opcode
, op
[-1].mask
)))
1819 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1823 bad_insn
|= insn_validate (op
);
1826 if ((ppc_cpu
& op
->flags
) != 0
1827 && !(ppc_cpu
& op
->deprecated
))
1831 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1834 as_bad (_("duplicate instruction %s"),
1841 /* SPE2 instructions */
1842 if ((ppc_cpu
& PPC_OPCODE_SPE2
) == PPC_OPCODE_SPE2
)
1844 op_end
= spe2_opcodes
+ spe2_num_opcodes
;
1845 for (op
= spe2_opcodes
; op
< op_end
; op
++)
1847 if (ENABLE_CHECKING
)
1849 if (op
!= spe2_opcodes
)
1851 unsigned old_seg
, new_seg
;
1853 old_seg
= VLE_OP (op
[-1].opcode
, op
[-1].mask
);
1854 old_seg
= VLE_OP_TO_SEG (old_seg
);
1855 new_seg
= VLE_OP (op
[0].opcode
, op
[0].mask
);
1856 new_seg
= VLE_OP_TO_SEG (new_seg
);
1858 /* The major opcodes had better be sorted. Code in the
1859 disassembler assumes the insns are sorted according to
1861 if (new_seg
< old_seg
)
1863 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1868 bad_insn
|= insn_validate (op
);
1871 if ((ppc_cpu
& op
->flags
) != 0 && !(ppc_cpu
& op
->deprecated
))
1875 retval
= hash_insert (ppc_hash
, op
->name
, (void *) op
);
1878 as_bad (_("duplicate instruction %s"),
1885 for (op
= spe2_opcodes
; op
< op_end
; op
++)
1886 hash_insert (ppc_hash
, op
->name
, (void *) op
);
1889 /* Insert the macros into a hash table. */
1890 ppc_macro_hash
= hash_new ();
1892 macro_end
= powerpc_macros
+ powerpc_num_macros
;
1893 for (macro
= powerpc_macros
; macro
< macro_end
; macro
++)
1895 if ((macro
->flags
& ppc_cpu
) != 0 || (ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1899 retval
= hash_insert (ppc_macro_hash
, macro
->name
, (void *) macro
);
1900 if (retval
!= (const char *) NULL
)
1902 as_bad (_("duplicate macro %s"), macro
->name
);
1912 /* This function is called when the assembler starts up. It is called
1913 after the options have been parsed and the output file has been
1921 ppc_cie_data_alignment
= ppc_obj64
? -8 : -4;
1922 ppc_dwarf2_line_min_insn_length
= (ppc_cpu
& PPC_OPCODE_VLE
) ? 2 : 4;
1925 /* Set the ELF flags if desired. */
1926 if (ppc_flags
&& !msolaris
)
1927 bfd_set_private_flags (stdoutput
, ppc_flags
);
1930 ppc_setup_opcodes ();
1932 /* Tell the main code what the endianness is if it is not overridden
1934 if (!set_target_endian
)
1936 set_target_endian
= 1;
1937 target_big_endian
= PPC_BIG_ENDIAN
;
1941 ppc_coff_debug_section
= coff_section_from_bfd_index (stdoutput
, N_DEBUG
);
1943 /* Create dummy symbols to serve as initial csects. This forces the
1944 text csects to precede the data csects. These symbols will not
1946 ppc_text_csects
= symbol_make ("dummy\001");
1947 symbol_get_tc (ppc_text_csects
)->within
= ppc_text_csects
;
1948 ppc_data_csects
= symbol_make ("dummy\001");
1949 symbol_get_tc (ppc_data_csects
)->within
= ppc_data_csects
;
1954 ppc_current_section
= text_section
;
1955 ppc_previous_section
= 0;
1964 if (ppc_apuinfo_list
== NULL
)
1967 /* Ok, so write the section info out. We have this layout:
1971 0 8 length of "APUinfo\0"
1972 4 (n*4) number of APU's (4 bytes each)
1975 20 APU#1 first APU's info
1976 24 APU#2 second APU's info
1981 asection
*seg
= now_seg
;
1982 subsegT subseg
= now_subseg
;
1983 asection
*apuinfo_secp
= (asection
*) NULL
;
1986 /* Create the .PPC.EMB.apuinfo section. */
1987 apuinfo_secp
= subseg_new (APUINFO_SECTION_NAME
, 0);
1988 bfd_set_section_flags (apuinfo_secp
, SEC_HAS_CONTENTS
| SEC_READONLY
);
1991 md_number_to_chars (p
, (valueT
) 8, 4);
1994 md_number_to_chars (p
, (valueT
) ppc_apuinfo_num
* 4, 4);
1997 md_number_to_chars (p
, (valueT
) 2, 4);
2000 strcpy (p
, APUINFO_LABEL
);
2002 for (i
= 0; i
< ppc_apuinfo_num
; i
++)
2005 md_number_to_chars (p
, (valueT
) ppc_apuinfo_list
[i
], 4);
2008 frag_align (2, 0, 0);
2010 /* We probably can't restore the current segment, for there likely
2013 subseg_set (seg
, subseg
);
2018 /* Insert an operand value into an instruction. */
2021 ppc_insert_operand (uint64_t insn
,
2022 const struct powerpc_operand
*operand
,
2028 int64_t min
, max
, right
;
2030 max
= operand
->bitm
;
2034 if ((operand
->flags
& PPC_OPERAND_SIGNOPT
) != 0)
2036 /* Extend the allowed range for addis to [-32768, 65535].
2037 Similarly for cmpli and some VLE high part insns. For 64-bit
2038 it would be good to disable this for signed fields since the
2039 value is sign extended into the high 32 bits of the register.
2040 If the value is, say, an address, then we might care about
2041 the high bits. However, gcc as of 2014-06 uses unsigned
2042 values when loading the high part of 64-bit constants using
2044 min
= ~(max
>> 1) & -right
;
2046 else if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
2048 max
= (max
>> 1) & -right
;
2049 min
= ~max
& -right
;
2052 if ((operand
->flags
& PPC_OPERAND_PLUS1
) != 0)
2055 if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
2064 /* Some people write constants with the sign extension done by
2065 hand but only up to 32 bits. This shouldn't really be valid,
2066 but, to permit this code to assemble on a 64-bit host, we
2067 sign extend the 32-bit value to 64 bits if so doing makes the
2068 value valid. We only do this for operands that are 32-bits or
2071 && (operand
->bitm
& ~0xffffffffULL
) == 0
2072 && (val
- (1LL << 32)) >= min
2073 && (val
- (1LL << 32)) <= max
2074 && ((val
- (1LL << 32)) & (right
- 1)) == 0)
2075 val
= val
- (1LL << 32);
2077 /* Similarly, people write expressions like ~(1<<15), and expect
2078 this to be OK for a 32-bit unsigned value. */
2080 && (operand
->bitm
& ~0xffffffffULL
) == 0
2081 && (val
+ (1LL << 32)) >= min
2082 && (val
+ (1LL << 32)) <= max
2083 && ((val
+ (1LL << 32)) & (right
- 1)) == 0)
2084 val
= val
+ (1LL << 32);
2088 || (val
& (right
- 1)) != 0)
2089 as_bad_value_out_of_range (_("operand"), val
, min
, max
, file
, line
);
2092 if (operand
->insert
)
2097 insn
= (*operand
->insert
) (insn
, val
, cpu
, &errmsg
);
2098 if (errmsg
!= (const char *) NULL
)
2099 as_bad_where (file
, line
, "%s", errmsg
);
2101 else if (operand
->shift
>= 0)
2102 insn
|= (val
& operand
->bitm
) << operand
->shift
;
2104 insn
|= (val
& operand
->bitm
) >> -operand
->shift
;
2111 /* Parse @got, etc. and return the desired relocation. */
2112 static bfd_reloc_code_real_type
2113 ppc_elf_suffix (char **str_p
, expressionS
*exp_p
)
2117 unsigned int length
: 8;
2118 unsigned int valid32
: 1;
2119 unsigned int valid64
: 1;
2128 const struct map_bfd
*ptr
;
2130 #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc }
2131 #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc }
2132 #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc }
2134 static const struct map_bfd mapping
[] = {
2135 MAP ("l", BFD_RELOC_LO16
),
2136 MAP ("h", BFD_RELOC_HI16
),
2137 MAP ("ha", BFD_RELOC_HI16_S
),
2138 MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN
),
2139 MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN
),
2140 MAP ("got", BFD_RELOC_16_GOTOFF
),
2141 MAP ("got@l", BFD_RELOC_LO16_GOTOFF
),
2142 MAP ("got@h", BFD_RELOC_HI16_GOTOFF
),
2143 MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF
),
2144 MAP ("plt@l", BFD_RELOC_LO16_PLTOFF
),
2145 MAP ("plt@h", BFD_RELOC_HI16_PLTOFF
),
2146 MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF
),
2147 MAP ("copy", BFD_RELOC_PPC_COPY
),
2148 MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT
),
2149 MAP ("sectoff", BFD_RELOC_16_BASEREL
),
2150 MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL
),
2151 MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL
),
2152 MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL
),
2153 MAP ("tls", BFD_RELOC_PPC_TLS
),
2154 MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD
),
2155 MAP ("dtprel", BFD_RELOC_PPC_DTPREL
),
2156 MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO
),
2157 MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI
),
2158 MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA
),
2159 MAP ("tprel", BFD_RELOC_PPC_TPREL
),
2160 MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO
),
2161 MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI
),
2162 MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA
),
2163 MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16
),
2164 MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO
),
2165 MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI
),
2166 MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA
),
2167 MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16
),
2168 MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO
),
2169 MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI
),
2170 MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA
),
2171 MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16
),
2172 MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO
),
2173 MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI
),
2174 MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA
),
2175 MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16
),
2176 MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO
),
2177 MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI
),
2178 MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA
),
2179 MAP32 ("fixup", BFD_RELOC_CTOR
),
2180 MAP32 ("plt", BFD_RELOC_24_PLT_PCREL
),
2181 MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL
),
2182 MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC
),
2183 MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC
),
2184 MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL
),
2185 MAP32 ("sdarel", BFD_RELOC_GPREL16
),
2186 MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A
),
2187 MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A
),
2188 MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A
),
2189 MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32
),
2190 MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16
),
2191 MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO
),
2192 MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI
),
2193 MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA
),
2194 MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16
),
2195 MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL
),
2196 MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16
),
2197 MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21
),
2198 MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO
),
2199 MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF
),
2200 MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16
),
2201 MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO
),
2202 MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI
),
2203 MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA
),
2204 MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD
),
2205 MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA
),
2206 MAP32 ("xgot", BFD_RELOC_PPC_TOC16
),
2207 MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH
),
2208 MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA
),
2209 MAP64 ("higher", BFD_RELOC_PPC64_HIGHER
),
2210 MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S
),
2211 MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST
),
2212 MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S
),
2213 MAP64 ("tocbase", BFD_RELOC_PPC64_TOC
),
2214 MAP64 ("toc", BFD_RELOC_PPC_TOC16
),
2215 MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO
),
2216 MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI
),
2217 MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA
),
2218 MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH
),
2219 MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA
),
2220 MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER
),
2221 MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA
),
2222 MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST
),
2223 MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA
),
2224 MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL
),
2225 MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH
),
2226 MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA
),
2227 MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER
),
2228 MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA
),
2229 MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST
),
2230 MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA
),
2231 MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC
),
2232 MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34
),
2233 MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34
),
2234 MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34
),
2235 MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL
),
2236 MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD34
),
2237 MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD34
),
2238 MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL34
),
2239 MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL34
),
2240 MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34
),
2241 MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34
),
2242 MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34
),
2243 MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34
),
2244 { (char *) 0, 0, 0, 0, BFD_RELOC_NONE
}
2248 return BFD_RELOC_NONE
;
2250 for (ch
= *str
, str2
= ident
;
2251 (str2
< ident
+ sizeof (ident
) - 1
2252 && (ISALNUM (ch
) || ch
== '@'));
2255 *str2
++ = TOLOWER (ch
);
2262 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
2263 if (ch
== ptr
->string
[0]
2264 && len
== ptr
->length
2265 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0
2266 && (ppc_obj64
? ptr
->valid64
: ptr
->valid32
))
2268 int reloc
= ptr
->reloc
;
2270 if (!ppc_obj64
&& exp_p
->X_add_number
!= 0)
2274 case BFD_RELOC_16_GOTOFF
:
2275 case BFD_RELOC_LO16_GOTOFF
:
2276 case BFD_RELOC_HI16_GOTOFF
:
2277 case BFD_RELOC_HI16_S_GOTOFF
:
2278 as_warn (_("symbol+offset@%s means symbol@%s+offset"),
2279 ptr
->string
, ptr
->string
);
2282 case BFD_RELOC_PPC_GOT_TLSGD16
:
2283 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
2284 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
2285 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
2286 case BFD_RELOC_PPC_GOT_TLSLD16
:
2287 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
2288 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
2289 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
2290 case BFD_RELOC_PPC_GOT_DTPREL16
:
2291 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
2292 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
2293 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
2294 case BFD_RELOC_PPC_GOT_TPREL16
:
2295 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
2296 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
2297 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
2298 as_bad (_("symbol+offset@%s not supported"), ptr
->string
);
2303 /* Now check for identifier@suffix+constant. */
2304 if (*str
== '-' || *str
== '+')
2306 char *orig_line
= input_line_pointer
;
2307 expressionS new_exp
;
2309 input_line_pointer
= str
;
2310 expression (&new_exp
);
2311 if (new_exp
.X_op
== O_constant
)
2313 exp_p
->X_add_number
+= new_exp
.X_add_number
;
2314 str
= input_line_pointer
;
2317 if (&input_line_pointer
!= str_p
)
2318 input_line_pointer
= orig_line
;
2322 if (reloc
== (int) BFD_RELOC_PPC64_TOC
2323 && exp_p
->X_op
== O_symbol
2324 && strcmp (S_GET_NAME (exp_p
->X_add_symbol
), ".TOC.") == 0)
2326 /* Change the symbol so that the dummy .TOC. symbol can be
2327 omitted from the object file. */
2328 exp_p
->X_add_symbol
= &abs_symbol
;
2331 return (bfd_reloc_code_real_type
) reloc
;
2334 return BFD_RELOC_NONE
;
2337 /* Support @got, etc. on constants emitted via .short, .int etc. */
2339 bfd_reloc_code_real_type
2340 ppc_elf_parse_cons (expressionS
*exp
, unsigned int nbytes
)
2343 if (nbytes
>= 2 && *input_line_pointer
== '@')
2344 return ppc_elf_suffix (&input_line_pointer
, exp
);
2345 return BFD_RELOC_NONE
;
2348 /* Warn when emitting data to code sections, unless we are emitting
2349 a relocation that ld --ppc476-workaround uses to recognise data
2350 *and* there was an unconditional branch prior to the data. */
2353 ppc_elf_cons_fix_check (expressionS
*exp ATTRIBUTE_UNUSED
,
2354 unsigned int nbytes
, fixS
*fix
)
2357 && (now_seg
->flags
& SEC_CODE
) != 0
2360 || !(fix
->fx_r_type
== BFD_RELOC_32
2361 || fix
->fx_r_type
== BFD_RELOC_CTOR
2362 || fix
->fx_r_type
== BFD_RELOC_32_PCREL
)
2363 || !(last_seg
== now_seg
&& last_subseg
== now_subseg
)
2364 || !((last_insn
& (0x3f << 26)) == (18u << 26)
2365 || ((last_insn
& (0x3f << 26)) == (16u << 26)
2366 && (last_insn
& (0x14 << 21)) == (0x14 << 21))
2367 || ((last_insn
& (0x3f << 26)) == (19u << 26)
2368 && (last_insn
& (0x3ff << 1)) == (16u << 1)
2369 && (last_insn
& (0x14 << 21)) == (0x14 << 21)))))
2371 /* Flag that we've warned. */
2375 as_warn (_("data in executable section"));
2379 /* Solaris pseduo op to change to the .rodata section. */
2381 ppc_elf_rdata (int xxx
)
2383 char *save_line
= input_line_pointer
;
2384 static char section
[] = ".rodata\n";
2386 /* Just pretend this is .section .rodata */
2387 input_line_pointer
= section
;
2388 obj_elf_section (xxx
);
2390 input_line_pointer
= save_line
;
2393 /* Pseudo op to make file scope bss items. */
2395 ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED
)
2408 c
= get_symbol_name (&name
);
2410 /* Just after name is now '\0'. */
2411 p
= input_line_pointer
;
2413 SKIP_WHITESPACE_AFTER_NAME ();
2414 if (*input_line_pointer
!= ',')
2416 as_bad (_("expected comma after symbol-name: rest of line ignored."));
2417 ignore_rest_of_line ();
2421 input_line_pointer
++; /* skip ',' */
2422 if ((size
= get_absolute_expression ()) < 0)
2424 as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size
);
2425 ignore_rest_of_line ();
2429 /* The third argument to .lcomm is the alignment. */
2430 if (*input_line_pointer
!= ',')
2434 ++input_line_pointer
;
2435 align
= get_absolute_expression ();
2438 as_warn (_("ignoring bad alignment"));
2444 symbolP
= symbol_find_or_make (name
);
2447 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
2449 as_bad (_("ignoring attempt to re-define symbol `%s'."),
2450 S_GET_NAME (symbolP
));
2451 ignore_rest_of_line ();
2455 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
2457 as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."),
2458 S_GET_NAME (symbolP
),
2459 (long) S_GET_VALUE (symbolP
),
2462 ignore_rest_of_line ();
2468 old_subsec
= now_subseg
;
2471 /* Convert to a power of 2 alignment. */
2472 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
);
2475 as_bad (_("common alignment not a power of 2"));
2476 ignore_rest_of_line ();
2483 record_alignment (bss_section
, align2
);
2484 subseg_set (bss_section
, 1);
2486 frag_align (align2
, 0, 0);
2487 if (S_GET_SEGMENT (symbolP
) == bss_section
)
2488 symbol_get_frag (symbolP
)->fr_symbol
= 0;
2489 symbol_set_frag (symbolP
, frag_now
);
2490 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
2493 S_SET_SIZE (symbolP
, size
);
2494 S_SET_SEGMENT (symbolP
, bss_section
);
2495 subseg_set (old_sec
, old_subsec
);
2496 demand_empty_rest_of_line ();
2499 /* Pseudo op to set symbol local entry point. */
2501 ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED
)
2504 char c
= get_symbol_name (&name
);
2509 elf_symbol_type
*elfsym
;
2511 p
= input_line_pointer
;
2513 SKIP_WHITESPACE_AFTER_NAME ();
2514 if (*input_line_pointer
!= ',')
2517 as_bad (_("expected comma after name `%s' in .localentry directive"),
2520 ignore_rest_of_line ();
2523 input_line_pointer
++;
2525 if (exp
.X_op
== O_absent
)
2527 as_bad (_("missing expression in .localentry directive"));
2528 exp
.X_op
= O_constant
;
2529 exp
.X_add_number
= 0;
2532 sym
= symbol_find_or_make (name
);
2535 if (resolve_expression (&exp
)
2536 && exp
.X_op
== O_constant
)
2538 unsigned int encoded
, ok
;
2541 if (exp
.X_add_number
== 1 || exp
.X_add_number
== 7)
2542 encoded
= exp
.X_add_number
<< STO_PPC64_LOCAL_BIT
;
2545 encoded
= PPC64_SET_LOCAL_ENTRY_OFFSET (exp
.X_add_number
);
2546 if (exp
.X_add_number
!= (offsetT
) PPC64_LOCAL_ENTRY_OFFSET (encoded
))
2548 as_bad (_(".localentry expression for `%s' "
2549 "is not a valid power of 2"), S_GET_NAME (sym
));
2555 bfdsym
= symbol_get_bfdsym (sym
);
2556 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
2557 gas_assert (elfsym
);
2558 elfsym
->internal_elf_sym
.st_other
&= ~STO_PPC64_LOCAL_MASK
;
2559 elfsym
->internal_elf_sym
.st_other
|= encoded
;
2560 if (ppc_abiversion
== 0)
2565 as_bad (_(".localentry expression for `%s' "
2566 "does not evaluate to a constant"), S_GET_NAME (sym
));
2568 demand_empty_rest_of_line ();
2571 /* Pseudo op to set ABI version. */
2573 ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED
)
2578 if (exp
.X_op
== O_absent
)
2580 as_bad (_("missing expression in .abiversion directive"));
2581 exp
.X_op
= O_constant
;
2582 exp
.X_add_number
= 0;
2585 if (resolve_expression (&exp
)
2586 && exp
.X_op
== O_constant
)
2587 ppc_abiversion
= exp
.X_add_number
;
2589 as_bad (_(".abiversion expression does not evaluate to a constant"));
2590 demand_empty_rest_of_line ();
2593 /* Parse a .gnu_attribute directive. */
2595 ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED
)
2597 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_GNU
);
2599 /* Check validity of defined powerpc tags. */
2600 if (tag
== Tag_GNU_Power_ABI_FP
2601 || tag
== Tag_GNU_Power_ABI_Vector
2602 || tag
== Tag_GNU_Power_ABI_Struct_Return
)
2606 val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, tag
);
2608 if ((tag
== Tag_GNU_Power_ABI_FP
&& val
> 15)
2609 || (tag
== Tag_GNU_Power_ABI_Vector
&& val
> 3)
2610 || (tag
== Tag_GNU_Power_ABI_Struct_Return
&& val
> 2))
2611 as_warn (_("unknown .gnu_attribute value"));
2615 /* Set ABI version in output file. */
2619 if (ppc_obj64
&& ppc_abiversion
!= 0)
2621 elf_elfheader (stdoutput
)->e_flags
&= ~EF_PPC64_ABI
;
2622 elf_elfheader (stdoutput
)->e_flags
|= ppc_abiversion
& EF_PPC64_ABI
;
2624 /* Any selection of opcodes based on ppc_cpu after gas has finished
2625 parsing the file is invalid. md_apply_fix and ppc_handle_align
2626 must select opcodes based on the machine in force at the point
2627 where the fixup or alignment frag was created, not the machine in
2628 force at the end of file. */
2632 /* Validate any relocations emitted for -mrelocatable, possibly adding
2633 fixups for word relocations in writable segments, so we can adjust
2636 ppc_elf_validate_fix (fixS
*fixp
, segT seg
)
2638 if (fixp
->fx_done
|| fixp
->fx_pcrel
)
2647 case SHLIB_MRELOCATABLE
:
2648 if (fixp
->fx_r_type
!= BFD_RELOC_16_GOTOFF
2649 && fixp
->fx_r_type
!= BFD_RELOC_HI16_GOTOFF
2650 && fixp
->fx_r_type
!= BFD_RELOC_LO16_GOTOFF
2651 && fixp
->fx_r_type
!= BFD_RELOC_HI16_S_GOTOFF
2652 && fixp
->fx_r_type
!= BFD_RELOC_16_BASEREL
2653 && fixp
->fx_r_type
!= BFD_RELOC_LO16_BASEREL
2654 && fixp
->fx_r_type
!= BFD_RELOC_HI16_BASEREL
2655 && fixp
->fx_r_type
!= BFD_RELOC_HI16_S_BASEREL
2656 && (seg
->flags
& SEC_LOAD
) != 0
2657 && strcmp (segment_name (seg
), ".got2") != 0
2658 && strcmp (segment_name (seg
), ".dtors") != 0
2659 && strcmp (segment_name (seg
), ".ctors") != 0
2660 && strcmp (segment_name (seg
), ".fixup") != 0
2661 && strcmp (segment_name (seg
), ".gcc_except_table") != 0
2662 && strcmp (segment_name (seg
), ".eh_frame") != 0
2663 && strcmp (segment_name (seg
), ".ex_shared") != 0)
2665 if ((seg
->flags
& (SEC_READONLY
| SEC_CODE
)) != 0
2666 || fixp
->fx_r_type
!= BFD_RELOC_CTOR
)
2668 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2669 _("relocation cannot be done when using -mrelocatable"));
2676 /* Prevent elf_frob_file_before_adjust removing a weak undefined
2677 function descriptor sym if the corresponding code sym is used. */
2680 ppc_frob_file_before_adjust (void)
2688 for (symp
= symbol_rootP
; symp
; symp
= symbol_next (symp
))
2694 name
= S_GET_NAME (symp
);
2698 if (! S_IS_WEAK (symp
)
2699 || S_IS_DEFINED (symp
))
2702 dotname
= concat (".", name
, (char *) NULL
);
2703 dotsym
= symbol_find_noref (dotname
, 1);
2705 if (dotsym
!= NULL
&& (symbol_used_p (dotsym
)
2706 || symbol_used_in_reloc_p (dotsym
)))
2707 symbol_mark_used (symp
);
2711 toc
= bfd_get_section_by_name (stdoutput
, ".toc");
2713 && toc_reloc_types
!= has_large_toc_reloc
2714 && bfd_section_size (toc
) > 0x10000)
2715 as_warn (_("TOC section size exceeds 64k"));
2718 /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be
2719 emitted. Other uses of .TOC. will cause the symbol to be marked
2720 with BSF_KEEP in md_apply_fix. */
2723 ppc_elf_adjust_symtab (void)
2728 symp
= symbol_find (".TOC.");
2731 asymbol
*bsym
= symbol_get_bfdsym (symp
);
2732 if ((bsym
->flags
& BSF_KEEP
) == 0)
2733 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2737 #endif /* OBJ_ELF */
2742 * Summary of parse_toc_entry.
2744 * in: Input_line_pointer points to the '[' in one of:
2746 * [toc] [tocv] [toc32] [toc64]
2748 * Anything else is an error of one kind or another.
2751 * return value: success or failure
2752 * toc_kind: kind of toc reference
2753 * input_line_pointer:
2754 * success: first char after the ']'
2755 * failure: unchanged
2759 * [toc] - rv == success, toc_kind = default_toc
2760 * [tocv] - rv == success, toc_kind = data_in_toc
2761 * [toc32] - rv == success, toc_kind = must_be_32
2762 * [toc64] - rv == success, toc_kind = must_be_64
2766 enum toc_size_qualifier
2768 default_toc
, /* The toc cell constructed should be the system default size */
2769 data_in_toc
, /* This is a direct reference to a toc cell */
2770 must_be_32
, /* The toc cell constructed must be 32 bits wide */
2771 must_be_64
/* The toc cell constructed must be 64 bits wide */
2775 parse_toc_entry (enum toc_size_qualifier
*toc_kind
)
2780 enum toc_size_qualifier t
;
2782 /* Save the input_line_pointer. */
2783 start
= input_line_pointer
;
2785 /* Skip over the '[' , and whitespace. */
2786 ++input_line_pointer
;
2789 /* Find the spelling of the operand. */
2790 c
= get_symbol_name (&toc_spec
);
2792 if (strcmp (toc_spec
, "toc") == 0)
2796 else if (strcmp (toc_spec
, "tocv") == 0)
2800 else if (strcmp (toc_spec
, "toc32") == 0)
2804 else if (strcmp (toc_spec
, "toc64") == 0)
2810 as_bad (_("syntax error: invalid toc specifier `%s'"), toc_spec
);
2811 *input_line_pointer
= c
;
2812 input_line_pointer
= start
;
2816 /* Now find the ']'. */
2817 *input_line_pointer
= c
;
2819 SKIP_WHITESPACE_AFTER_NAME (); /* leading whitespace could be there. */
2820 c
= *input_line_pointer
++; /* input_line_pointer->past char in c. */
2824 as_bad (_("syntax error: expected `]', found `%c'"), c
);
2825 input_line_pointer
= start
;
2834 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
2835 /* See whether a symbol is in the TOC section. */
2838 ppc_is_toc_sym (symbolS
*sym
)
2841 return (symbol_get_tc (sym
)->symbol_class
== XMC_TC
2842 || symbol_get_tc (sym
)->symbol_class
== XMC_TC0
);
2845 const char *sname
= segment_name (S_GET_SEGMENT (sym
));
2847 return strcmp (sname
, ".toc") == 0;
2849 return strcmp (sname
, ".got") == 0;
2852 #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
2856 #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff))
2858 ppc_apuinfo_section_add (unsigned int apu
, unsigned int version
)
2862 /* Check we don't already exist. */
2863 for (i
= 0; i
< ppc_apuinfo_num
; i
++)
2864 if (ppc_apuinfo_list
[i
] == APUID (apu
, version
))
2867 if (ppc_apuinfo_num
== ppc_apuinfo_num_alloc
)
2869 if (ppc_apuinfo_num_alloc
== 0)
2871 ppc_apuinfo_num_alloc
= 4;
2872 ppc_apuinfo_list
= XNEWVEC (unsigned long, ppc_apuinfo_num_alloc
);
2876 ppc_apuinfo_num_alloc
+= 4;
2877 ppc_apuinfo_list
= XRESIZEVEC (unsigned long, ppc_apuinfo_list
,
2878 ppc_apuinfo_num_alloc
);
2881 ppc_apuinfo_list
[ppc_apuinfo_num
++] = APUID (apu
, version
);
2886 /* Various frobbings of labels and their addresses. */
2888 /* Symbols labelling the current insn. */
2889 struct insn_label_list
2891 struct insn_label_list
*next
;
2895 static struct insn_label_list
*insn_labels
;
2896 static struct insn_label_list
*free_insn_labels
;
2899 ppc_record_label (symbolS
*sym
)
2901 struct insn_label_list
*l
;
2903 if (free_insn_labels
== NULL
)
2904 l
= XNEW (struct insn_label_list
);
2907 l
= free_insn_labels
;
2908 free_insn_labels
= l
->next
;
2912 l
->next
= insn_labels
;
2917 ppc_clear_labels (void)
2919 while (insn_labels
!= NULL
)
2921 struct insn_label_list
*l
= insn_labels
;
2922 insn_labels
= l
->next
;
2923 l
->next
= free_insn_labels
;
2924 free_insn_labels
= l
;
2929 ppc_start_line_hook (void)
2931 ppc_clear_labels ();
2935 ppc_new_dot_label (symbolS
*sym
)
2937 ppc_record_label (sym
);
2939 /* Anchor this label to the current csect for relocations. */
2940 symbol_get_tc (sym
)->within
= ppc_current_csect
;
2945 ppc_frob_label (symbolS
*sym
)
2947 ppc_record_label (sym
);
2950 /* Set the class of a label based on where it is defined. This handles
2951 symbols without suffixes. Also, move the symbol so that it follows
2952 the csect symbol. */
2953 if (ppc_current_csect
!= (symbolS
*) NULL
)
2955 if (symbol_get_tc (sym
)->symbol_class
== -1)
2956 symbol_get_tc (sym
)->symbol_class
= symbol_get_tc (ppc_current_csect
)->symbol_class
;
2958 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
2959 symbol_append (sym
, symbol_get_tc (ppc_current_csect
)->within
,
2960 &symbol_rootP
, &symbol_lastP
);
2961 symbol_get_tc (ppc_current_csect
)->within
= sym
;
2962 symbol_get_tc (sym
)->within
= ppc_current_csect
;
2967 dwarf2_emit_label (sym
);
2971 /* We need to keep a list of fixups. We can't simply generate them as
2972 we go, because that would require us to first create the frag, and
2973 that would screw up references to ``.''. */
2979 bfd_reloc_code_real_type reloc
;
2982 #define MAX_INSN_FIXUPS (5)
2984 /* Return the field size operated on by RELOC, and whether it is
2985 pc-relative in PC_RELATIVE. */
2988 fixup_size (bfd_reloc_code_real_type reloc
, bfd_boolean
*pc_relative
)
2990 unsigned int size
= 0;
2991 bfd_boolean pcrel
= FALSE
;
2995 /* This switch statement must handle all BFD_RELOC values
2996 possible in instruction fixups. As is, it handles all
2997 BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c,
2998 bfd/coff-ppc, bfd/coff-rs6000.c and bfd/coff64-rs6000.c.
2999 Overkill since data and marker relocs need not be handled
3000 here, but this way we can be sure a needed fixup reloc isn't
3001 accidentally omitted. */
3002 case BFD_RELOC_PPC_EMB_MRKREF
:
3003 case BFD_RELOC_VTABLE_ENTRY
:
3004 case BFD_RELOC_VTABLE_INHERIT
:
3012 case BFD_RELOC_16_BASEREL
:
3013 case BFD_RELOC_16_GOTOFF
:
3014 case BFD_RELOC_GPREL16
:
3015 case BFD_RELOC_HI16
:
3016 case BFD_RELOC_HI16_BASEREL
:
3017 case BFD_RELOC_HI16_GOTOFF
:
3018 case BFD_RELOC_HI16_PLTOFF
:
3019 case BFD_RELOC_HI16_S
:
3020 case BFD_RELOC_HI16_S_BASEREL
:
3021 case BFD_RELOC_HI16_S_GOTOFF
:
3022 case BFD_RELOC_HI16_S_PLTOFF
:
3023 case BFD_RELOC_LO16
:
3024 case BFD_RELOC_LO16_BASEREL
:
3025 case BFD_RELOC_LO16_GOTOFF
:
3026 case BFD_RELOC_LO16_PLTOFF
:
3027 case BFD_RELOC_PPC64_ADDR16_DS
:
3028 case BFD_RELOC_PPC64_ADDR16_HIGH
:
3029 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
3030 case BFD_RELOC_PPC64_ADDR16_HIGHER34
:
3031 case BFD_RELOC_PPC64_ADDR16_HIGHERA34
:
3032 case BFD_RELOC_PPC64_ADDR16_HIGHEST34
:
3033 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34
:
3034 case BFD_RELOC_PPC64_ADDR16_LO_DS
:
3035 case BFD_RELOC_PPC64_DTPREL16_DS
:
3036 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
3037 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
3038 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
3039 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
3040 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
3041 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
3042 case BFD_RELOC_PPC64_DTPREL16_LO_DS
:
3043 case BFD_RELOC_PPC64_GOT16_DS
:
3044 case BFD_RELOC_PPC64_GOT16_LO_DS
:
3045 case BFD_RELOC_PPC64_HIGHER
:
3046 case BFD_RELOC_PPC64_HIGHER_S
:
3047 case BFD_RELOC_PPC64_HIGHEST
:
3048 case BFD_RELOC_PPC64_HIGHEST_S
:
3049 case BFD_RELOC_PPC64_PLT16_LO_DS
:
3050 case BFD_RELOC_PPC64_PLTGOT16
:
3051 case BFD_RELOC_PPC64_PLTGOT16_DS
:
3052 case BFD_RELOC_PPC64_PLTGOT16_HA
:
3053 case BFD_RELOC_PPC64_PLTGOT16_HI
:
3054 case BFD_RELOC_PPC64_PLTGOT16_LO
:
3055 case BFD_RELOC_PPC64_PLTGOT16_LO_DS
:
3056 case BFD_RELOC_PPC64_SECTOFF_DS
:
3057 case BFD_RELOC_PPC64_SECTOFF_LO_DS
:
3058 case BFD_RELOC_PPC64_TOC16_DS
:
3059 case BFD_RELOC_PPC64_TOC16_HA
:
3060 case BFD_RELOC_PPC64_TOC16_HI
:
3061 case BFD_RELOC_PPC64_TOC16_LO
:
3062 case BFD_RELOC_PPC64_TOC16_LO_DS
:
3063 case BFD_RELOC_PPC64_TPREL16_DS
:
3064 case BFD_RELOC_PPC64_TPREL16_HIGH
:
3065 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
3066 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
3067 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
3068 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
3069 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
3070 case BFD_RELOC_PPC64_TPREL16_LO_DS
:
3072 case BFD_RELOC_PPC_BA16
:
3074 case BFD_RELOC_PPC_DTPREL16
:
3075 case BFD_RELOC_PPC_DTPREL16_HA
:
3076 case BFD_RELOC_PPC_DTPREL16_HI
:
3077 case BFD_RELOC_PPC_DTPREL16_LO
:
3078 case BFD_RELOC_PPC_EMB_NADDR16
:
3079 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
3080 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
3081 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
3082 case BFD_RELOC_PPC_EMB_RELSDA
:
3083 case BFD_RELOC_PPC_EMB_RELSEC16
:
3084 case BFD_RELOC_PPC_EMB_RELST_LO
:
3085 case BFD_RELOC_PPC_EMB_RELST_HI
:
3086 case BFD_RELOC_PPC_EMB_RELST_HA
:
3087 case BFD_RELOC_PPC_EMB_SDA2I16
:
3088 case BFD_RELOC_PPC_EMB_SDA2REL
:
3089 case BFD_RELOC_PPC_EMB_SDAI16
:
3090 case BFD_RELOC_PPC_GOT_DTPREL16
:
3091 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
3092 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
3093 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
3094 case BFD_RELOC_PPC_GOT_TLSGD16
:
3095 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
3096 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
3097 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
3098 case BFD_RELOC_PPC_GOT_TLSLD16
:
3099 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
3100 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
3101 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
3102 case BFD_RELOC_PPC_GOT_TPREL16
:
3103 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
3104 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
3105 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
3106 case BFD_RELOC_PPC_TOC16
:
3107 case BFD_RELOC_PPC_TPREL16
:
3108 case BFD_RELOC_PPC_TPREL16_HA
:
3109 case BFD_RELOC_PPC_TPREL16_HI
:
3110 case BFD_RELOC_PPC_TPREL16_LO
:
3114 case BFD_RELOC_16_PCREL
:
3115 case BFD_RELOC_HI16_PCREL
:
3116 case BFD_RELOC_HI16_S_PCREL
:
3117 case BFD_RELOC_LO16_PCREL
:
3118 case BFD_RELOC_PPC64_REL16_HIGH
:
3119 case BFD_RELOC_PPC64_REL16_HIGHA
:
3120 case BFD_RELOC_PPC64_REL16_HIGHER
:
3121 case BFD_RELOC_PPC64_REL16_HIGHER34
:
3122 case BFD_RELOC_PPC64_REL16_HIGHERA
:
3123 case BFD_RELOC_PPC64_REL16_HIGHERA34
:
3124 case BFD_RELOC_PPC64_REL16_HIGHEST
:
3125 case BFD_RELOC_PPC64_REL16_HIGHEST34
:
3126 case BFD_RELOC_PPC64_REL16_HIGHESTA
:
3127 case BFD_RELOC_PPC64_REL16_HIGHESTA34
:
3129 case BFD_RELOC_PPC_B16
:
3131 case BFD_RELOC_PPC_VLE_REL8
:
3136 case BFD_RELOC_16_GOT_PCREL
: /* coff reloc, bad name re size. */
3138 case BFD_RELOC_32_GOTOFF
:
3139 case BFD_RELOC_32_PLTOFF
:
3141 case BFD_RELOC_CTOR
:
3143 case BFD_RELOC_PPC64_ENTRY
:
3144 case BFD_RELOC_PPC_16DX_HA
:
3146 case BFD_RELOC_PPC_BA16
:
3148 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
3149 case BFD_RELOC_PPC_BA16_BRTAKEN
:
3150 case BFD_RELOC_PPC_BA26
:
3151 case BFD_RELOC_PPC_EMB_BIT_FLD
:
3152 case BFD_RELOC_PPC_EMB_NADDR32
:
3153 case BFD_RELOC_PPC_EMB_SDA21
:
3154 case BFD_RELOC_PPC_TLS
:
3155 case BFD_RELOC_PPC_TLSGD
:
3156 case BFD_RELOC_PPC_TLSLD
:
3157 case BFD_RELOC_PPC_VLE_HA16A
:
3158 case BFD_RELOC_PPC_VLE_HA16D
:
3159 case BFD_RELOC_PPC_VLE_HI16A
:
3160 case BFD_RELOC_PPC_VLE_HI16D
:
3161 case BFD_RELOC_PPC_VLE_LO16A
:
3162 case BFD_RELOC_PPC_VLE_LO16D
:
3163 case BFD_RELOC_PPC_VLE_SDA21
:
3164 case BFD_RELOC_PPC_VLE_SDA21_LO
:
3165 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
3166 case BFD_RELOC_PPC_VLE_SDAREL_HA16D
:
3167 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
3168 case BFD_RELOC_PPC_VLE_SDAREL_HI16D
:
3169 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
3170 case BFD_RELOC_PPC_VLE_SDAREL_LO16D
:
3171 case BFD_RELOC_PPC64_TLS_PCREL
:
3176 case BFD_RELOC_24_PLT_PCREL
:
3177 case BFD_RELOC_32_PCREL
:
3178 case BFD_RELOC_32_PLT_PCREL
:
3179 case BFD_RELOC_PPC64_REL24_NOTOC
:
3181 case BFD_RELOC_PPC_B16
:
3183 case BFD_RELOC_PPC_B16_BRNTAKEN
:
3184 case BFD_RELOC_PPC_B16_BRTAKEN
:
3185 case BFD_RELOC_PPC_B26
:
3186 case BFD_RELOC_PPC_LOCAL24PC
:
3187 case BFD_RELOC_PPC_REL16DX_HA
:
3188 case BFD_RELOC_PPC_VLE_REL15
:
3189 case BFD_RELOC_PPC_VLE_REL24
:
3195 case BFD_RELOC_CTOR
:
3197 case BFD_RELOC_PPC_COPY
:
3198 case BFD_RELOC_PPC_DTPMOD
:
3199 case BFD_RELOC_PPC_DTPREL
:
3200 case BFD_RELOC_PPC_GLOB_DAT
:
3201 case BFD_RELOC_PPC_TPREL
:
3202 size
= ppc_obj64
? 8 : 4;
3206 case BFD_RELOC_64_PLTOFF
:
3207 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
3208 case BFD_RELOC_PPC64_D28
:
3209 case BFD_RELOC_PPC64_D34
:
3210 case BFD_RELOC_PPC64_D34_LO
:
3211 case BFD_RELOC_PPC64_D34_HI30
:
3212 case BFD_RELOC_PPC64_D34_HA30
:
3213 case BFD_RELOC_PPC64_TPREL34
:
3214 case BFD_RELOC_PPC64_DTPREL34
:
3215 case BFD_RELOC_PPC64_TOC
:
3219 case BFD_RELOC_64_PCREL
:
3220 case BFD_RELOC_64_PLT_PCREL
:
3221 case BFD_RELOC_PPC64_GOT_PCREL34
:
3222 case BFD_RELOC_PPC64_GOT_TLSGD34
:
3223 case BFD_RELOC_PPC64_GOT_TLSLD34
:
3224 case BFD_RELOC_PPC64_GOT_TPREL34
:
3225 case BFD_RELOC_PPC64_GOT_DTPREL34
:
3226 case BFD_RELOC_PPC64_PCREL28
:
3227 case BFD_RELOC_PPC64_PCREL34
:
3228 case BFD_RELOC_PPC64_PLT_PCREL34
:
3237 if (ENABLE_CHECKING
)
3239 reloc_howto_type
*reloc_howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
3240 if (reloc_howto
!= NULL
3241 && (size
!= bfd_get_reloc_size (reloc_howto
)
3242 || pcrel
!= reloc_howto
->pc_relative
))
3244 as_bad (_("%s howto doesn't match size/pcrel in gas"),
3249 *pc_relative
= pcrel
;
3254 /* If we have parsed a call to __tls_get_addr, parse an argument like
3255 (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg
3256 is successfully parsed, *STR is updated past the trailing
3257 parenthesis and trailing white space, and *TLS_FIX contains the
3258 reloc and arg expression. */
3261 parse_tls_arg (char **str
, const expressionS
*exp
, struct ppc_fixup
*tls_fix
)
3263 const char *sym_name
= S_GET_NAME (exp
->X_add_symbol
);
3264 if (sym_name
[0] == '.')
3267 tls_fix
->reloc
= BFD_RELOC_NONE
;
3268 if (strncasecmp (sym_name
, "__tls_get_addr", 14) == 0
3269 && (sym_name
[14] == 0
3270 || strcasecmp (sym_name
+ 14, "_desc") == 0
3271 || strcasecmp (sym_name
+ 14, "_opt") == 0))
3273 char *hold
= input_line_pointer
;
3274 input_line_pointer
= *str
+ 1;
3275 expression (&tls_fix
->exp
);
3276 if (tls_fix
->exp
.X_op
== O_symbol
)
3278 if (strncasecmp (input_line_pointer
, "@tlsgd)", 7) == 0)
3279 tls_fix
->reloc
= BFD_RELOC_PPC_TLSGD
;
3280 else if (strncasecmp (input_line_pointer
, "@tlsld)", 7) == 0)
3281 tls_fix
->reloc
= BFD_RELOC_PPC_TLSLD
;
3282 if (tls_fix
->reloc
!= BFD_RELOC_NONE
)
3284 input_line_pointer
+= 7;
3286 *str
= input_line_pointer
;
3289 input_line_pointer
= hold
;
3291 return tls_fix
->reloc
!= BFD_RELOC_NONE
;
3295 /* This routine is called for each instruction to be assembled. */
3298 md_assemble (char *str
)
3301 const struct powerpc_opcode
*opcode
;
3303 const unsigned char *opindex_ptr
;
3306 struct ppc_fixup fixups
[MAX_INSN_FIXUPS
];
3311 unsigned int insn_length
;
3313 /* Get the opcode. */
3314 for (s
= str
; *s
!= '\0' && ! ISSPACE (*s
); s
++)
3319 /* Look up the opcode in the hash table. */
3320 opcode
= (const struct powerpc_opcode
*) hash_find (ppc_hash
, str
);
3321 if (opcode
== (const struct powerpc_opcode
*) NULL
)
3323 const struct powerpc_macro
*macro
;
3325 macro
= (const struct powerpc_macro
*) hash_find (ppc_macro_hash
, str
);
3326 if (macro
== (const struct powerpc_macro
*) NULL
)
3327 as_bad (_("unrecognized opcode: `%s'"), str
);
3329 ppc_macro (s
, macro
);
3331 ppc_clear_labels ();
3335 insn
= opcode
->opcode
;
3338 while (ISSPACE (*str
))
3341 /* PowerPC operands are just expressions. The only real issue is
3342 that a few operand types are optional. If an instruction has
3343 multiple optional operands and one is omitted, then all optional
3344 operands past the first omitted one must also be omitted. */
3345 int num_optional_operands
= 0;
3346 int num_optional_provided
= 0;
3348 /* Gather the operands. */
3352 for (opindex_ptr
= opcode
->operands
; *opindex_ptr
!= 0; opindex_ptr
++)
3354 const struct powerpc_operand
*operand
;
3360 if (next_opindex
== 0)
3361 operand
= &powerpc_operands
[*opindex_ptr
];
3364 operand
= &powerpc_operands
[next_opindex
];
3369 /* If this is an optional operand, and we are skipping it, just
3370 insert the default value, usually a zero. */
3371 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
3372 && !((operand
->flags
& PPC_OPERAND_OPTIONAL32
) != 0 && ppc_obj64
))
3374 if (num_optional_operands
== 0)
3376 const unsigned char *optr
;
3382 for (optr
= opindex_ptr
; *optr
!= 0; optr
++)
3384 const struct powerpc_operand
*op
;
3385 op
= &powerpc_operands
[*optr
];
3389 if ((op
->flags
& PPC_OPERAND_OPTIONAL
) != 0
3390 && !((op
->flags
& PPC_OPERAND_OPTIONAL32
) != 0
3392 ++num_optional_operands
;
3394 if (s
!= NULL
&& *s
!= '\0')
3398 /* Look for the start of the next operand. */
3399 if ((op
->flags
& PPC_OPERAND_PARENS
) != 0)
3400 s
= strpbrk (s
, "(,");
3402 s
= strchr (s
, ',');
3408 omitted
= total
- provided
;
3409 num_optional_provided
= num_optional_operands
- omitted
;
3411 if (--num_optional_provided
< 0)
3413 int64_t val
= ppc_optional_operand_value (operand
, insn
, ppc_cpu
,
3414 num_optional_provided
);
3415 if (operand
->insert
)
3417 insn
= (*operand
->insert
) (insn
, val
, ppc_cpu
, &errmsg
);
3418 if (errmsg
!= (const char *) NULL
)
3419 as_bad ("%s", errmsg
);
3421 else if (operand
->shift
>= 0)
3422 insn
|= (val
& operand
->bitm
) << operand
->shift
;
3424 insn
|= (val
& operand
->bitm
) >> -operand
->shift
;
3426 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0)
3427 next_opindex
= *opindex_ptr
+ 1;
3432 /* Gather the operand. */
3433 hold
= input_line_pointer
;
3434 input_line_pointer
= str
;
3437 if (*input_line_pointer
== '[')
3439 /* We are expecting something like the second argument here:
3441 * lwz r4,[toc].GS.0.static_int(rtoc)
3442 * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
3443 * The argument following the `]' must be a symbol name, and the
3444 * register must be the toc register: 'rtoc' or '2'
3446 * The effect is to 0 as the displacement field
3447 * in the instruction, and issue an IMAGE_REL_PPC_TOCREL16 (or
3448 * the appropriate variation) reloc against it based on the symbol.
3449 * The linker will build the toc, and insert the resolved toc offset.
3452 * o The size of the toc entry is currently assumed to be
3453 * 32 bits. This should not be assumed to be a hard coded
3455 * o In an effort to cope with a change from 32 to 64 bits,
3456 * there are also toc entries that are specified to be
3457 * either 32 or 64 bits:
3458 * lwz r4,[toc32].GS.0.static_int(rtoc)
3459 * lwz r4,[toc64].GS.0.static_int(rtoc)
3460 * These demand toc entries of the specified size, and the
3461 * instruction probably requires it.
3465 enum toc_size_qualifier toc_kind
;
3466 bfd_reloc_code_real_type toc_reloc
;
3468 /* Go parse off the [tocXX] part. */
3469 valid_toc
= parse_toc_entry (&toc_kind
);
3473 ignore_rest_of_line ();
3477 /* Now get the symbol following the ']'. */
3483 /* In this case, we may not have seen the symbol yet,
3484 since it is allowed to appear on a .extern or .globl
3485 or just be a label in the .data section. */
3486 toc_reloc
= BFD_RELOC_PPC_TOC16
;
3489 /* 1. The symbol must be defined and either in the toc
3490 section, or a global.
3491 2. The reloc generated must have the TOCDEFN flag set
3492 in upper bit mess of the reloc type.
3493 FIXME: It's a little confusing what the tocv
3494 qualifier can be used for. At the very least, I've
3495 seen three uses, only one of which I'm sure I can
3497 if (ex
.X_op
== O_symbol
)
3499 gas_assert (ex
.X_add_symbol
!= NULL
);
3500 if (symbol_get_bfdsym (ex
.X_add_symbol
)->section
3503 as_bad (_("[tocv] symbol is not a toc symbol"));
3507 toc_reloc
= BFD_RELOC_PPC_TOC16
;
3510 /* FIXME: these next two specifically specify 32/64 bit
3511 toc entries. We don't support them today. Is this
3512 the right way to say that? */
3513 toc_reloc
= BFD_RELOC_NONE
;
3514 as_bad (_("unimplemented toc32 expression modifier"));
3517 /* FIXME: see above. */
3518 toc_reloc
= BFD_RELOC_NONE
;
3519 as_bad (_("unimplemented toc64 expression modifier"));
3523 _("Unexpected return value [%d] from parse_toc_entry!\n"),
3529 /* We need to generate a fixup for this expression. */
3530 if (fc
>= MAX_INSN_FIXUPS
)
3531 as_fatal (_("too many fixups"));
3533 fixups
[fc
].reloc
= toc_reloc
;
3534 fixups
[fc
].exp
= ex
;
3535 fixups
[fc
].opindex
= *opindex_ptr
;
3538 /* Ok. We've set up the fixup for the instruction. Now make it
3539 look like the constant 0 was found here. */
3541 ex
.X_op
= O_constant
;
3542 ex
.X_add_number
= 0;
3543 ex
.X_add_symbol
= NULL
;
3544 ex
.X_op_symbol
= NULL
;
3551 && (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
3552 || ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0)))
3553 || !register_name (&ex
))
3555 char save_lex
= lex_type
['%'];
3557 if (((operand
->flags
& PPC_OPERAND_CR_REG
) != 0)
3558 || (operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
3561 lex_type
['%'] |= LEX_BEGIN_NAME
;
3565 lex_type
['%'] = save_lex
;
3569 str
= input_line_pointer
;
3570 input_line_pointer
= hold
;
3572 if (ex
.X_op
== O_illegal
)
3573 as_bad (_("illegal operand"));
3574 else if (ex
.X_op
== O_absent
)
3575 as_bad (_("missing operand"));
3576 else if (ex
.X_op
== O_register
)
3580 & (PPC_OPERAND_GPR
| PPC_OPERAND_FPR
| PPC_OPERAND_VR
3581 | PPC_OPERAND_VSR
| PPC_OPERAND_CR_BIT
| PPC_OPERAND_CR_REG
3582 | PPC_OPERAND_SPR
| PPC_OPERAND_GQR
| PPC_OPERAND_ACC
)) != 0
3583 && !((ex
.X_md
& PPC_OPERAND_GPR
) != 0
3584 && ex
.X_add_number
!= 0
3585 && (operand
->flags
& PPC_OPERAND_GPR_0
) != 0))
3586 as_warn (_("invalid register expression"));
3587 insn
= ppc_insert_operand (insn
, operand
, ex
.X_add_number
,
3588 ppc_cpu
, (char *) NULL
, 0);
3590 else if (ex
.X_op
== O_constant
)
3593 /* Allow @HA, @L, @H on constants. */
3594 bfd_reloc_code_real_type reloc
;
3595 char *orig_str
= str
;
3597 if ((reloc
= ppc_elf_suffix (&str
, &ex
)) != BFD_RELOC_NONE
)
3604 case BFD_RELOC_LO16
:
3605 ex
.X_add_number
&= 0xffff;
3606 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3607 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3610 case BFD_RELOC_HI16
:
3611 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
3613 /* PowerPC64 @h is tested for overflow. */
3614 ex
.X_add_number
= (addressT
) ex
.X_add_number
>> 16;
3615 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3617 addressT sign
= (((addressT
) -1 >> 16) + 1) >> 1;
3619 = ((addressT
) ex
.X_add_number
^ sign
) - sign
;
3625 case BFD_RELOC_PPC64_ADDR16_HIGH
:
3626 ex
.X_add_number
= PPC_HI (ex
.X_add_number
);
3627 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3628 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3631 case BFD_RELOC_HI16_S
:
3632 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
3634 /* PowerPC64 @ha is tested for overflow. */
3636 = ((addressT
) ex
.X_add_number
+ 0x8000) >> 16;
3637 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3639 addressT sign
= (((addressT
) -1 >> 16) + 1) >> 1;
3641 = ((addressT
) ex
.X_add_number
^ sign
) - sign
;
3647 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
3648 ex
.X_add_number
= PPC_HA (ex
.X_add_number
);
3649 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3650 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3653 case BFD_RELOC_PPC64_HIGHER
:
3654 ex
.X_add_number
= PPC_HIGHER (ex
.X_add_number
);
3655 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3656 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3659 case BFD_RELOC_PPC64_HIGHER_S
:
3660 ex
.X_add_number
= PPC_HIGHERA (ex
.X_add_number
);
3661 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3662 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3665 case BFD_RELOC_PPC64_HIGHEST
:
3666 ex
.X_add_number
= PPC_HIGHEST (ex
.X_add_number
);
3667 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3668 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3671 case BFD_RELOC_PPC64_HIGHEST_S
:
3672 ex
.X_add_number
= PPC_HIGHESTA (ex
.X_add_number
);
3673 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3674 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3677 #endif /* OBJ_ELF */
3678 insn
= ppc_insert_operand (insn
, operand
, ex
.X_add_number
,
3679 ppc_cpu
, (char *) NULL
, 0);
3683 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
3685 /* Look for a __tls_get_addr arg using the insane old syntax. */
3686 if (ex
.X_op
== O_symbol
&& *str
== '(' && fc
< MAX_INSN_FIXUPS
3687 && parse_tls_arg (&str
, &ex
, &fixups
[fc
]))
3689 fixups
[fc
].opindex
= *opindex_ptr
;
3693 if ((reloc
= ppc_elf_suffix (&str
, &ex
)) != BFD_RELOC_NONE
)
3695 /* If VLE-mode convert LO/HI/HA relocations. */
3696 if (opcode
->flags
& PPC_OPCODE_VLE
)
3698 uint64_t tmp_insn
= insn
& opcode
->mask
;
3700 int use_a_reloc
= (tmp_insn
== E_OR2I_INSN
3701 || tmp_insn
== E_AND2I_DOT_INSN
3702 || tmp_insn
== E_OR2IS_INSN
3703 || tmp_insn
== E_LI_INSN
3704 || tmp_insn
== E_LIS_INSN
3705 || tmp_insn
== E_AND2IS_DOT_INSN
);
3708 int use_d_reloc
= (tmp_insn
== E_ADD2I_DOT_INSN
3709 || tmp_insn
== E_ADD2IS_INSN
3710 || tmp_insn
== E_CMP16I_INSN
3711 || tmp_insn
== E_MULL2I_INSN
3712 || tmp_insn
== E_CMPL16I_INSN
3713 || tmp_insn
== E_CMPH16I_INSN
3714 || tmp_insn
== E_CMPHL16I_INSN
);
3721 case BFD_RELOC_PPC_EMB_SDA21
:
3722 reloc
= BFD_RELOC_PPC_VLE_SDA21
;
3725 case BFD_RELOC_LO16
:
3727 reloc
= BFD_RELOC_PPC_VLE_LO16D
;
3728 else if (use_a_reloc
)
3729 reloc
= BFD_RELOC_PPC_VLE_LO16A
;
3732 case BFD_RELOC_HI16
:
3734 reloc
= BFD_RELOC_PPC_VLE_HI16D
;
3735 else if (use_a_reloc
)
3736 reloc
= BFD_RELOC_PPC_VLE_HI16A
;
3739 case BFD_RELOC_HI16_S
:
3741 reloc
= BFD_RELOC_PPC_VLE_HA16D
;
3742 else if (use_a_reloc
)
3743 reloc
= BFD_RELOC_PPC_VLE_HA16A
;
3746 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
3748 reloc
= BFD_RELOC_PPC_VLE_SDAREL_LO16D
;
3751 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
3753 reloc
= BFD_RELOC_PPC_VLE_SDAREL_HI16D
;
3756 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
3758 reloc
= BFD_RELOC_PPC_VLE_SDAREL_HA16D
;
3763 /* TLS and other tweaks. */
3769 case BFD_RELOC_PPC_TLS
:
3770 case BFD_RELOC_PPC64_TLS_PCREL
:
3771 if (!_bfd_elf_ppc_at_tls_transform (opcode
->opcode
, 0))
3772 as_bad (_("@tls may not be used with \"%s\" operands"),
3774 else if (operand
->shift
!= 11)
3775 as_bad (_("@tls may only be used in last operand"));
3777 insn
= ppc_insert_operand (insn
, operand
,
3779 ppc_cpu
, (char *) NULL
, 0);
3782 /* We'll only use the 32 (or 64) bit form of these relocations
3783 in constants. Instructions get the 16 or 34 bit form. */
3784 case BFD_RELOC_PPC_DTPREL
:
3785 if (operand
->bitm
== 0x3ffffffffULL
)
3786 reloc
= BFD_RELOC_PPC64_DTPREL34
;
3788 reloc
= BFD_RELOC_PPC_DTPREL16
;
3791 case BFD_RELOC_PPC_TPREL
:
3792 if (operand
->bitm
== 0x3ffffffffULL
)
3793 reloc
= BFD_RELOC_PPC64_TPREL34
;
3795 reloc
= BFD_RELOC_PPC_TPREL16
;
3798 case BFD_RELOC_PPC64_PCREL34
:
3799 if (operand
->bitm
== 0xfffffffULL
)
3801 reloc
= BFD_RELOC_PPC64_PCREL28
;
3805 case BFD_RELOC_PPC64_GOT_PCREL34
:
3806 case BFD_RELOC_PPC64_PLT_PCREL34
:
3807 case BFD_RELOC_PPC64_GOT_TLSGD34
:
3808 case BFD_RELOC_PPC64_GOT_TLSLD34
:
3809 case BFD_RELOC_PPC64_GOT_TPREL34
:
3810 case BFD_RELOC_PPC64_GOT_DTPREL34
:
3811 if (operand
->bitm
!= 0x3ffffffffULL
3812 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3813 as_warn (_("%s unsupported on this instruction"), "@pcrel");
3816 case BFD_RELOC_LO16
:
3817 if (operand
->bitm
== 0x3ffffffffULL
3818 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3819 reloc
= BFD_RELOC_PPC64_D34_LO
;
3820 else if ((operand
->bitm
| 0xf) != 0xffff
3821 || operand
->shift
!= 0
3822 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3823 as_warn (_("%s unsupported on this instruction"), "@l");
3826 case BFD_RELOC_HI16
:
3827 if (operand
->bitm
== 0x3ffffffffULL
3828 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3829 reloc
= BFD_RELOC_PPC64_D34_HI30
;
3830 else if (operand
->bitm
!= 0xffff
3831 || operand
->shift
!= 0
3832 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3833 as_warn (_("%s unsupported on this instruction"), "@h");
3836 case BFD_RELOC_HI16_S
:
3837 if (operand
->bitm
== 0x3ffffffffULL
3838 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3839 reloc
= BFD_RELOC_PPC64_D34_HA30
;
3840 else if (operand
->bitm
== 0xffff
3841 && operand
->shift
== (int) PPC_OPSHIFT_INV
3842 && opcode
->opcode
== (19 << 26) + (2 << 1))
3844 reloc
= BFD_RELOC_PPC_16DX_HA
;
3845 else if (operand
->bitm
!= 0xffff
3846 || operand
->shift
!= 0
3847 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3848 as_warn (_("%s unsupported on this instruction"), "@ha");
3851 #endif /* OBJ_ELF */
3853 if (reloc
!= BFD_RELOC_NONE
)
3855 /* Determine a BFD reloc value based on the operand information.
3856 We are only prepared to turn a few of the operands into
3858 else if ((operand
->flags
& (PPC_OPERAND_RELATIVE
3859 | PPC_OPERAND_ABSOLUTE
)) != 0
3860 && operand
->bitm
== 0x3fffffc
3861 && operand
->shift
== 0)
3862 reloc
= BFD_RELOC_PPC_B26
;
3863 else if ((operand
->flags
& (PPC_OPERAND_RELATIVE
3864 | PPC_OPERAND_ABSOLUTE
)) != 0
3865 && operand
->bitm
== 0xfffc
3866 && operand
->shift
== 0)
3867 reloc
= BFD_RELOC_PPC_B16
;
3868 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3869 && operand
->bitm
== 0x1fe
3870 && operand
->shift
== -1)
3871 reloc
= BFD_RELOC_PPC_VLE_REL8
;
3872 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3873 && operand
->bitm
== 0xfffe
3874 && operand
->shift
== 0)
3875 reloc
= BFD_RELOC_PPC_VLE_REL15
;
3876 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3877 && operand
->bitm
== 0x1fffffe
3878 && operand
->shift
== 0)
3879 reloc
= BFD_RELOC_PPC_VLE_REL24
;
3880 else if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0
3881 && (operand
->bitm
& 0xfff0) == 0xfff0
3882 && operand
->shift
== 0)
3884 reloc
= BFD_RELOC_16
;
3885 #if defined OBJ_XCOFF || defined OBJ_ELF
3886 /* Note: the symbol may be not yet defined. */
3887 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0
3888 && ppc_is_toc_sym (ex
.X_add_symbol
))
3890 reloc
= BFD_RELOC_PPC_TOC16
;
3892 as_warn (_("assuming %s on symbol"),
3893 ppc_obj64
? "@toc" : "@xgot");
3898 else if (operand
->bitm
== 0x3ffffffffULL
)
3899 reloc
= BFD_RELOC_PPC64_D34
;
3900 else if (operand
->bitm
== 0xfffffffULL
)
3901 reloc
= BFD_RELOC_PPC64_D28
;
3903 /* For the absolute forms of branches, convert the PC
3904 relative form back into the absolute. */
3905 if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
3909 case BFD_RELOC_PPC_B26
:
3910 reloc
= BFD_RELOC_PPC_BA26
;
3912 case BFD_RELOC_PPC_B16
:
3913 reloc
= BFD_RELOC_PPC_BA16
;
3916 case BFD_RELOC_PPC_B16_BRTAKEN
:
3917 reloc
= BFD_RELOC_PPC_BA16_BRTAKEN
;
3919 case BFD_RELOC_PPC_B16_BRNTAKEN
:
3920 reloc
= BFD_RELOC_PPC_BA16_BRNTAKEN
;
3931 case BFD_RELOC_PPC_TOC16
:
3932 toc_reloc_types
|= has_small_toc_reloc
;
3934 case BFD_RELOC_PPC64_TOC16_LO
:
3935 case BFD_RELOC_PPC64_TOC16_HI
:
3936 case BFD_RELOC_PPC64_TOC16_HA
:
3937 toc_reloc_types
|= has_large_toc_reloc
;
3944 && (operand
->flags
& (PPC_OPERAND_DS
| PPC_OPERAND_DQ
)) != 0)
3949 reloc
= BFD_RELOC_PPC64_ADDR16_DS
;
3952 case BFD_RELOC_LO16
:
3953 reloc
= BFD_RELOC_PPC64_ADDR16_LO_DS
;
3956 case BFD_RELOC_16_GOTOFF
:
3957 reloc
= BFD_RELOC_PPC64_GOT16_DS
;
3960 case BFD_RELOC_LO16_GOTOFF
:
3961 reloc
= BFD_RELOC_PPC64_GOT16_LO_DS
;
3964 case BFD_RELOC_LO16_PLTOFF
:
3965 reloc
= BFD_RELOC_PPC64_PLT16_LO_DS
;
3968 case BFD_RELOC_16_BASEREL
:
3969 reloc
= BFD_RELOC_PPC64_SECTOFF_DS
;
3972 case BFD_RELOC_LO16_BASEREL
:
3973 reloc
= BFD_RELOC_PPC64_SECTOFF_LO_DS
;
3976 case BFD_RELOC_PPC_TOC16
:
3977 reloc
= BFD_RELOC_PPC64_TOC16_DS
;
3980 case BFD_RELOC_PPC64_TOC16_LO
:
3981 reloc
= BFD_RELOC_PPC64_TOC16_LO_DS
;
3984 case BFD_RELOC_PPC64_PLTGOT16
:
3985 reloc
= BFD_RELOC_PPC64_PLTGOT16_DS
;
3988 case BFD_RELOC_PPC64_PLTGOT16_LO
:
3989 reloc
= BFD_RELOC_PPC64_PLTGOT16_LO_DS
;
3992 case BFD_RELOC_PPC_DTPREL16
:
3993 reloc
= BFD_RELOC_PPC64_DTPREL16_DS
;
3996 case BFD_RELOC_PPC_DTPREL16_LO
:
3997 reloc
= BFD_RELOC_PPC64_DTPREL16_LO_DS
;
4000 case BFD_RELOC_PPC_TPREL16
:
4001 reloc
= BFD_RELOC_PPC64_TPREL16_DS
;
4004 case BFD_RELOC_PPC_TPREL16_LO
:
4005 reloc
= BFD_RELOC_PPC64_TPREL16_LO_DS
;
4008 case BFD_RELOC_PPC_GOT_DTPREL16
:
4009 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
4010 case BFD_RELOC_PPC_GOT_TPREL16
:
4011 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
4015 as_bad (_("unsupported relocation for DS offset field"));
4020 /* Look for a __tls_get_addr arg after any __tls_get_addr
4021 modifiers like @plt. This fixup must be emitted before
4022 the usual call fixup. */
4023 if (ex
.X_op
== O_symbol
&& *str
== '(' && fc
< MAX_INSN_FIXUPS
4024 && parse_tls_arg (&str
, &ex
, &fixups
[fc
]))
4026 fixups
[fc
].opindex
= *opindex_ptr
;
4031 /* We need to generate a fixup for this expression. */
4032 if (fc
>= MAX_INSN_FIXUPS
)
4033 as_fatal (_("too many fixups"));
4034 fixups
[fc
].exp
= ex
;
4035 fixups
[fc
].opindex
= *opindex_ptr
;
4036 fixups
[fc
].reloc
= reloc
;
4044 /* If expecting more operands, then we want to see "),". */
4045 if (*str
== endc
&& opindex_ptr
[1] != 0)
4049 while (ISSPACE (*str
));
4053 else if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0)
4058 /* The call to expression should have advanced str past any
4066 else if (*str
!= '\0')
4068 as_bad (_("syntax error; found `%c', expected `%c'"), *str
, endc
);
4071 else if (endc
== ')')
4073 as_bad (_("syntax error; end of line, expected `%c'"), endc
);
4078 while (ISSPACE (*str
))
4082 as_bad (_("junk at end of line: `%s'"), str
);
4085 /* Do we need/want an APUinfo section? */
4086 if ((ppc_cpu
& (PPC_OPCODE_E500
| PPC_OPCODE_E500MC
| PPC_OPCODE_VLE
)) != 0
4089 /* These are all version "1". */
4090 if (opcode
->flags
& PPC_OPCODE_SPE
)
4091 ppc_apuinfo_section_add (PPC_APUINFO_SPE
, 1);
4092 if (opcode
->flags
& PPC_OPCODE_ISEL
)
4093 ppc_apuinfo_section_add (PPC_APUINFO_ISEL
, 1);
4094 if (opcode
->flags
& PPC_OPCODE_EFS
)
4095 ppc_apuinfo_section_add (PPC_APUINFO_EFS
, 1);
4096 if (opcode
->flags
& PPC_OPCODE_BRLOCK
)
4097 ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK
, 1);
4098 if (opcode
->flags
& PPC_OPCODE_PMR
)
4099 ppc_apuinfo_section_add (PPC_APUINFO_PMR
, 1);
4100 if (opcode
->flags
& PPC_OPCODE_CACHELCK
)
4101 ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK
, 1);
4102 if (opcode
->flags
& PPC_OPCODE_RFMCI
)
4103 ppc_apuinfo_section_add (PPC_APUINFO_RFMCI
, 1);
4104 /* Only set the VLE flag if the instruction has been pulled via
4105 the VLE instruction set. This way the flag is guaranteed to
4106 be set for VLE-only instructions or for VLE-only processors,
4107 however it'll remain clear for dual-mode instructions on
4108 dual-mode and, more importantly, standard-mode processors. */
4109 if ((ppc_cpu
& opcode
->flags
) == PPC_OPCODE_VLE
)
4111 ppc_apuinfo_section_add (PPC_APUINFO_VLE
, 1);
4112 if (elf_section_data (now_seg
) != NULL
)
4113 elf_section_data (now_seg
)->this_hdr
.sh_flags
|= SHF_PPC_VLE
;
4118 /* Write out the instruction. */
4121 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
4122 /* All instructions can start on a 2 byte boundary for VLE. */
4125 if (frag_now
->insn_addr
!= addr_mask
)
4127 /* Don't emit instructions to a frag started for data, or for a
4128 CPU differing in VLE mode. Data is allowed to be misaligned,
4129 and it's possible to start a new frag in the middle of
4131 frag_wane (frag_now
);
4135 /* Check that insns within the frag are aligned. ppc_frag_check
4136 will ensure that the frag start address is aligned. */
4137 if ((frag_now_fix () & addr_mask
) != 0)
4138 as_bad (_("instruction address is not a multiple of %d"), addr_mask
+ 1);
4140 /* Differentiate between two, four, and eight byte insns. */
4142 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0 && PPC_OP_SE_VLE (insn
))
4144 else if ((opcode
->flags
& PPC_OPCODE_POWER10
) != 0
4145 && PPC_PREFIX_P (insn
))
4147 struct insn_label_list
*l
;
4151 /* 8-byte prefix instructions are not allowed to cross 64-byte
4153 frag_align_code (6, 4);
4154 record_alignment (now_seg
, 6);
4156 /* Update "dot" in any expressions used by this instruction, and
4157 a label attached to the instruction. By "attached" we mean
4158 on the same source line as the instruction and without any
4159 intervening semicolons. */
4160 dot_value
= frag_now_fix ();
4161 dot_frag
= frag_now
;
4162 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
4164 symbol_set_frag (l
->label
, dot_frag
);
4165 S_SET_VALUE (l
->label
, dot_value
);
4169 ppc_clear_labels ();
4171 f
= frag_more (insn_length
);
4172 frag_now
->insn_addr
= addr_mask
;
4174 /* The prefix part of an 8-byte instruction always occupies the lower
4175 addressed word in a doubleword, regardless of endianness. */
4176 if (!target_big_endian
&& insn_length
== 8)
4178 md_number_to_chars (f
, PPC_GET_PREFIX (insn
), 4);
4179 md_number_to_chars (f
+ 4, PPC_GET_SUFFIX (insn
), 4);
4182 md_number_to_chars (f
, insn
, insn_length
);
4186 last_subseg
= now_subseg
;
4189 dwarf2_emit_insn (insn_length
);
4192 /* Create any fixups. */
4193 for (i
= 0; i
< fc
; i
++)
4196 if (fixups
[i
].reloc
!= BFD_RELOC_NONE
)
4199 unsigned int size
= fixup_size (fixups
[i
].reloc
, &pcrel
);
4200 int offset
= target_big_endian
? (insn_length
- size
) : 0;
4202 fixP
= fix_new_exp (frag_now
,
4203 f
- frag_now
->fr_literal
+ offset
,
4211 const struct powerpc_operand
*operand
;
4213 operand
= &powerpc_operands
[fixups
[i
].opindex
];
4214 fixP
= fix_new_exp (frag_now
,
4215 f
- frag_now
->fr_literal
,
4218 (operand
->flags
& PPC_OPERAND_RELATIVE
) != 0,
4221 fixP
->fx_pcrel_adjust
= fixups
[i
].opindex
;
4225 /* Handle a macro. Gather all the operands, transform them as
4226 described by the macro, and call md_assemble recursively. All the
4227 operands are separated by commas; we don't accept parentheses
4228 around operands here. */
4231 ppc_macro (char *str
, const struct powerpc_macro
*macro
)
4242 /* Gather the users operands into the operands array. */
4247 if (count
>= sizeof operands
/ sizeof operands
[0])
4249 operands
[count
++] = s
;
4250 s
= strchr (s
, ',');
4251 if (s
== (char *) NULL
)
4256 if (count
!= macro
->operands
)
4258 as_bad (_("wrong number of operands"));
4262 /* Work out how large the string must be (the size is unbounded
4263 because it includes user input). */
4265 format
= macro
->format
;
4266 while (*format
!= '\0')
4275 arg
= strtol (format
+ 1, &send
, 10);
4276 know (send
!= format
&& arg
< count
);
4277 len
+= strlen (operands
[arg
]);
4282 /* Put the string together. */
4283 complete
= s
= XNEWVEC (char, len
+ 1);
4284 format
= macro
->format
;
4285 while (*format
!= '\0')
4291 arg
= strtol (format
+ 1, &send
, 10);
4292 strcpy (s
, operands
[arg
]);
4299 /* Assemble the constructed instruction. */
4300 md_assemble (complete
);
4305 /* For ELF, add support for SHT_ORDERED. */
4308 ppc_section_type (char *str
, size_t len
)
4310 if (len
== 7 && strncmp (str
, "ordered", 7) == 0)
4317 ppc_section_flags (flagword flags
, bfd_vma attr ATTRIBUTE_UNUSED
, int type
)
4319 if (type
== SHT_ORDERED
)
4320 flags
|= SEC_ALLOC
| SEC_LOAD
| SEC_SORT_ENTRIES
;
4326 ppc_elf_section_letter (int letter
, const char **ptrmsg
)
4331 *ptrmsg
= _("bad .section directive: want a,e,v,w,x,M,S,G,T in string");
4334 #endif /* OBJ_ELF */
4337 /* Pseudo-op handling. */
4339 /* The .byte pseudo-op. This is similar to the normal .byte
4340 pseudo-op, but it can also take a single ASCII string. */
4343 ppc_byte (int ignore ATTRIBUTE_UNUSED
)
4347 if (*input_line_pointer
!= '\"')
4353 /* Gather characters. A real double quote is doubled. Unusual
4354 characters are not permitted. */
4355 ++input_line_pointer
;
4360 c
= *input_line_pointer
++;
4364 if (*input_line_pointer
!= '\"')
4366 ++input_line_pointer
;
4369 FRAG_APPEND_1_CHAR (c
);
4373 if (warn_476
&& count
!= 0 && (now_seg
->flags
& SEC_CODE
) != 0)
4374 as_warn (_("data in executable section"));
4375 demand_empty_rest_of_line ();
4380 /* XCOFF specific pseudo-op handling. */
4382 /* This is set if we are creating a .stabx symbol, since we don't want
4383 to handle symbol suffixes for such symbols. */
4384 static bfd_boolean ppc_stab_symbol
;
4386 /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
4387 symbols in the .bss segment as though they were local common
4388 symbols, and uses a different smclas. The native Aix 4.3.3 assembler
4389 aligns .comm and .lcomm to 4 bytes. */
4392 ppc_comm (int lcomm
)
4394 asection
*current_seg
= now_seg
;
4395 subsegT current_subseg
= now_subseg
;
4401 symbolS
*lcomm_sym
= NULL
;
4405 endc
= get_symbol_name (&name
);
4406 end_name
= input_line_pointer
;
4407 (void) restore_line_pointer (endc
);
4409 if (*input_line_pointer
!= ',')
4411 as_bad (_("missing size"));
4412 ignore_rest_of_line ();
4415 ++input_line_pointer
;
4417 size
= get_absolute_expression ();
4420 as_bad (_("negative size"));
4421 ignore_rest_of_line ();
4427 /* The third argument to .comm is the alignment. */
4428 if (*input_line_pointer
!= ',')
4432 ++input_line_pointer
;
4433 align
= get_absolute_expression ();
4436 as_warn (_("ignoring bad alignment"));
4446 /* The third argument to .lcomm appears to be the real local
4447 common symbol to create. References to the symbol named in
4448 the first argument are turned into references to the third
4450 if (*input_line_pointer
!= ',')
4452 as_bad (_("missing real symbol name"));
4453 ignore_rest_of_line ();
4456 ++input_line_pointer
;
4458 lcomm_endc
= get_symbol_name (&lcomm_name
);
4460 lcomm_sym
= symbol_find_or_make (lcomm_name
);
4462 (void) restore_line_pointer (lcomm_endc
);
4464 /* The fourth argument to .lcomm is the alignment. */
4465 if (*input_line_pointer
!= ',')
4474 ++input_line_pointer
;
4475 align
= get_absolute_expression ();
4478 as_warn (_("ignoring bad alignment"));
4485 sym
= symbol_find_or_make (name
);
4488 if (S_IS_DEFINED (sym
)
4489 || S_GET_VALUE (sym
) != 0)
4491 as_bad (_("attempt to redefine symbol"));
4492 ignore_rest_of_line ();
4496 record_alignment (bss_section
, align
);
4499 || ! S_IS_DEFINED (lcomm_sym
))
4508 S_SET_EXTERNAL (sym
);
4512 symbol_get_tc (lcomm_sym
)->output
= 1;
4513 def_sym
= lcomm_sym
;
4517 subseg_set (bss_section
, 1);
4518 frag_align (align
, 0, 0);
4520 symbol_set_frag (def_sym
, frag_now
);
4521 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, def_sym
,
4522 def_size
, (char *) NULL
);
4524 S_SET_SEGMENT (def_sym
, bss_section
);
4525 symbol_get_tc (def_sym
)->align
= align
;
4529 /* Align the size of lcomm_sym. */
4530 symbol_get_frag (lcomm_sym
)->fr_offset
=
4531 ((symbol_get_frag (lcomm_sym
)->fr_offset
+ (1 << align
) - 1)
4532 &~ ((1 << align
) - 1));
4533 if (align
> symbol_get_tc (lcomm_sym
)->align
)
4534 symbol_get_tc (lcomm_sym
)->align
= align
;
4539 /* Make sym an offset from lcomm_sym. */
4540 S_SET_SEGMENT (sym
, bss_section
);
4541 symbol_set_frag (sym
, symbol_get_frag (lcomm_sym
));
4542 S_SET_VALUE (sym
, symbol_get_frag (lcomm_sym
)->fr_offset
);
4543 symbol_get_frag (lcomm_sym
)->fr_offset
+= size
;
4546 subseg_set (current_seg
, current_subseg
);
4548 demand_empty_rest_of_line ();
4551 /* The .csect pseudo-op. This switches us into a different
4552 subsegment. The first argument is a symbol whose value is the
4553 start of the .csect. In COFF, csect symbols get special aux
4554 entries defined by the x_csect field of union internal_auxent. The
4555 optional second argument is the alignment (the default is 2). */
4558 ppc_csect (int ignore ATTRIBUTE_UNUSED
)
4565 endc
= get_symbol_name (&name
);
4567 sym
= symbol_find_or_make (name
);
4569 (void) restore_line_pointer (endc
);
4571 if (S_GET_NAME (sym
)[0] == '\0')
4573 /* An unnamed csect is assumed to be [PR]. */
4574 symbol_get_tc (sym
)->symbol_class
= XMC_PR
;
4578 if (*input_line_pointer
== ',')
4580 ++input_line_pointer
;
4581 align
= get_absolute_expression ();
4584 ppc_change_csect (sym
, align
);
4586 demand_empty_rest_of_line ();
4589 /* Change to a different csect. */
4592 ppc_change_csect (symbolS
*sym
, offsetT align
)
4594 if (S_IS_DEFINED (sym
))
4595 subseg_set (S_GET_SEGMENT (sym
), symbol_get_tc (sym
)->subseg
);
4605 /* This is a new csect. We need to look at the symbol class to
4606 figure out whether it should go in the text section or the
4610 switch (symbol_get_tc (sym
)->symbol_class
)
4620 S_SET_SEGMENT (sym
, text_section
);
4621 symbol_get_tc (sym
)->subseg
= ppc_text_subsegment
;
4622 ++ppc_text_subsegment
;
4623 list_ptr
= &ppc_text_csects
;
4633 if (ppc_toc_csect
!= NULL
4634 && (symbol_get_tc (ppc_toc_csect
)->subseg
+ 1
4635 == ppc_data_subsegment
))
4637 S_SET_SEGMENT (sym
, data_section
);
4638 symbol_get_tc (sym
)->subseg
= ppc_data_subsegment
;
4639 ++ppc_data_subsegment
;
4640 list_ptr
= &ppc_data_csects
;
4646 /* We set the obstack chunk size to a small value before
4647 changing subsegments, so that we don't use a lot of memory
4648 space for what may be a small section. */
4649 hold_chunksize
= chunksize
;
4652 sec
= subseg_new (segment_name (S_GET_SEGMENT (sym
)),
4653 symbol_get_tc (sym
)->subseg
);
4655 chunksize
= hold_chunksize
;
4658 ppc_after_toc_frag
= frag_now
;
4660 record_alignment (sec
, align
);
4662 frag_align_code (align
, 0);
4664 frag_align (align
, 0, 0);
4666 symbol_set_frag (sym
, frag_now
);
4667 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
4669 symbol_get_tc (sym
)->align
= align
;
4670 symbol_get_tc (sym
)->output
= 1;
4671 symbol_get_tc (sym
)->within
= sym
;
4673 for (list
= *list_ptr
;
4674 symbol_get_tc (list
)->next
!= (symbolS
*) NULL
;
4675 list
= symbol_get_tc (list
)->next
)
4677 symbol_get_tc (list
)->next
= sym
;
4679 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4680 symbol_append (sym
, symbol_get_tc (list
)->within
, &symbol_rootP
,
4684 ppc_current_csect
= sym
;
4688 ppc_change_debug_section (unsigned int idx
, subsegT subseg
)
4692 const struct xcoff_dwsect_name
*dw
= &xcoff_dwsect_names
[idx
];
4694 sec
= subseg_new (dw
->name
, subseg
);
4695 oldflags
= bfd_section_flags (sec
);
4696 if (oldflags
== SEC_NO_FLAGS
)
4698 /* Just created section. */
4699 gas_assert (dw_sections
[idx
].sect
== NULL
);
4701 bfd_set_section_flags (sec
, SEC_DEBUGGING
);
4702 bfd_set_section_alignment (sec
, 0);
4703 dw_sections
[idx
].sect
= sec
;
4706 /* Not anymore in a csect. */
4707 ppc_current_csect
= NULL
;
4710 /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is:
4711 .dwsect flag [, opt-label ]
4715 ppc_dwsect (int ignore ATTRIBUTE_UNUSED
)
4719 const struct xcoff_dwsect_name
*dw
;
4720 struct dw_subsection
*subseg
;
4721 struct dw_section
*dws
;
4725 flag
= get_absolute_expression ();
4727 for (i
= 0; i
< XCOFF_DWSECT_NBR_NAMES
; i
++)
4728 if (xcoff_dwsect_names
[i
].flag
== flag
)
4730 dw
= &xcoff_dwsect_names
[i
];
4734 /* Parse opt-label. */
4735 if (*input_line_pointer
== ',')
4740 ++input_line_pointer
;
4742 c
= get_symbol_name (&label
);
4743 opt_label
= symbol_find_or_make (label
);
4744 (void) restore_line_pointer (c
);
4749 demand_empty_rest_of_line ();
4751 /* Return now in case of unknown subsection. */
4754 as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"),
4759 /* Find the subsection. */
4760 dws
= &dw_sections
[i
];
4762 if (opt_label
!= NULL
&& S_IS_DEFINED (opt_label
))
4764 /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */
4765 if (dws
->sect
== NULL
|| S_GET_SEGMENT (opt_label
) != dws
->sect
)
4767 as_bad (_("label %s was not defined in this dwarf section"),
4768 S_GET_NAME (opt_label
));
4769 subseg
= dws
->anon_subseg
;
4773 subseg
= symbol_get_tc (opt_label
)->u
.dw
;
4778 /* Switch to the subsection. */
4779 ppc_change_debug_section (i
, subseg
->subseg
);
4783 /* Create a new dw subsection. */
4784 subseg
= XNEW (struct dw_subsection
);
4786 if (opt_label
== NULL
)
4788 /* The anonymous one. */
4790 subseg
->link
= NULL
;
4791 dws
->anon_subseg
= subseg
;
4796 if (dws
->list_subseg
!= NULL
)
4797 subseg
->subseg
= dws
->list_subseg
->subseg
+ 1;
4801 subseg
->link
= dws
->list_subseg
;
4802 dws
->list_subseg
= subseg
;
4803 symbol_get_tc (opt_label
)->u
.dw
= subseg
;
4806 ppc_change_debug_section (i
, subseg
->subseg
);
4810 /* Add the length field. */
4811 expressionS
*exp
= &subseg
->end_exp
;
4814 if (opt_label
!= NULL
)
4815 symbol_set_value_now (opt_label
);
4817 /* Add the length field. Note that according to the AIX assembler
4818 manual, the size of the length field is 4 for powerpc32 but
4819 12 for powerpc64. */
4822 /* Write the 64bit marker. */
4823 md_number_to_chars (frag_more (4), -1, 4);
4826 exp
->X_op
= O_subtract
;
4827 exp
->X_op_symbol
= symbol_temp_new_now ();
4828 exp
->X_add_symbol
= symbol_temp_make ();
4830 sz
= ppc_obj64
? 8 : 4;
4831 exp
->X_add_number
= -sz
;
4832 emit_expr (exp
, sz
);
4837 /* This function handles the .text and .data pseudo-ops. These
4838 pseudo-ops aren't really used by XCOFF; we implement them for the
4839 convenience of people who aren't used to XCOFF. */
4842 ppc_section (int type
)
4849 else if (type
== 'd')
4854 sym
= symbol_find_or_make (name
);
4856 ppc_change_csect (sym
, 2);
4858 demand_empty_rest_of_line ();
4861 /* This function handles the .section pseudo-op. This is mostly to
4862 give an error, since XCOFF only supports .text, .data and .bss, but
4863 we do permit the user to name the text or data section. */
4866 ppc_named_section (int ignore ATTRIBUTE_UNUSED
)
4869 const char *real_name
;
4873 c
= get_symbol_name (&user_name
);
4875 if (strcmp (user_name
, ".text") == 0)
4876 real_name
= ".text[PR]";
4877 else if (strcmp (user_name
, ".data") == 0)
4878 real_name
= ".data[RW]";
4881 as_bad (_("the XCOFF file format does not support arbitrary sections"));
4882 (void) restore_line_pointer (c
);
4883 ignore_rest_of_line ();
4887 (void) restore_line_pointer (c
);
4889 sym
= symbol_find_or_make (real_name
);
4891 ppc_change_csect (sym
, 2);
4893 demand_empty_rest_of_line ();
4896 /* The .extern pseudo-op. We create an undefined symbol. */
4899 ppc_extern (int ignore ATTRIBUTE_UNUSED
)
4904 endc
= get_symbol_name (&name
);
4906 (void) symbol_find_or_make (name
);
4908 (void) restore_line_pointer (endc
);
4910 demand_empty_rest_of_line ();
4913 /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */
4916 ppc_lglobl (int ignore ATTRIBUTE_UNUSED
)
4922 endc
= get_symbol_name (&name
);
4924 sym
= symbol_find_or_make (name
);
4926 (void) restore_line_pointer (endc
);
4928 symbol_get_tc (sym
)->output
= 1;
4930 demand_empty_rest_of_line ();
4933 /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF
4934 relocations at the beginning of the current csect.
4936 (In principle, there's no reason why the relocations _have_ to be at
4937 the beginning. Anywhere in the csect would do. However, inserting
4938 at the beginning is what the native assembler does, and it helps to
4939 deal with cases where the .ref statements follow the section contents.)
4941 ??? .refs don't work for empty .csects. However, the native assembler
4942 doesn't report an error in this case, and neither yet do we. */
4945 ppc_ref (int ignore ATTRIBUTE_UNUSED
)
4950 if (ppc_current_csect
== NULL
)
4952 as_bad (_(".ref outside .csect"));
4953 ignore_rest_of_line ();
4959 c
= get_symbol_name (&name
);
4961 fix_at_start (symbol_get_frag (ppc_current_csect
), 0,
4962 symbol_find_or_make (name
), 0, FALSE
, BFD_RELOC_NONE
);
4964 *input_line_pointer
= c
;
4965 SKIP_WHITESPACE_AFTER_NAME ();
4966 c
= *input_line_pointer
;
4969 input_line_pointer
++;
4971 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
4973 as_bad (_("missing symbol name"));
4974 ignore_rest_of_line ();
4981 demand_empty_rest_of_line ();
4984 /* The .rename pseudo-op. The RS/6000 assembler can rename symbols,
4985 although I don't know why it bothers. */
4988 ppc_rename (int ignore ATTRIBUTE_UNUSED
)
4995 endc
= get_symbol_name (&name
);
4997 sym
= symbol_find_or_make (name
);
4999 (void) restore_line_pointer (endc
);
5001 if (*input_line_pointer
!= ',')
5003 as_bad (_("missing rename string"));
5004 ignore_rest_of_line ();
5007 ++input_line_pointer
;
5009 symbol_get_tc (sym
)->real_name
= demand_copy_C_string (&len
);
5011 demand_empty_rest_of_line ();
5014 /* The .stabx pseudo-op. This is similar to a normal .stabs
5015 pseudo-op, but slightly different. A sample is
5016 .stabx "main:F-1",.main,142,0
5017 The first argument is the symbol name to create. The second is the
5018 value, and the third is the storage class. The fourth seems to be
5019 always zero, and I am assuming it is the type. */
5022 ppc_stabx (int ignore ATTRIBUTE_UNUSED
)
5029 name
= demand_copy_C_string (&len
);
5031 if (*input_line_pointer
!= ',')
5033 as_bad (_("missing value"));
5036 ++input_line_pointer
;
5038 ppc_stab_symbol
= TRUE
;
5039 sym
= symbol_make (name
);
5040 ppc_stab_symbol
= FALSE
;
5042 symbol_get_tc (sym
)->real_name
= name
;
5044 (void) expression (&exp
);
5051 as_bad (_("illegal .stabx expression; zero assumed"));
5052 exp
.X_add_number
= 0;
5055 S_SET_VALUE (sym
, (valueT
) exp
.X_add_number
);
5056 symbol_set_frag (sym
, &zero_address_frag
);
5060 if (S_GET_SEGMENT (exp
.X_add_symbol
) == undefined_section
)
5061 symbol_set_value_expression (sym
, &exp
);
5065 exp
.X_add_number
+ S_GET_VALUE (exp
.X_add_symbol
));
5066 symbol_set_frag (sym
, symbol_get_frag (exp
.X_add_symbol
));
5071 /* The value is some complex expression. This will probably
5072 fail at some later point, but this is probably the right
5073 thing to do here. */
5074 symbol_set_value_expression (sym
, &exp
);
5078 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
5079 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5081 if (*input_line_pointer
!= ',')
5083 as_bad (_("missing class"));
5086 ++input_line_pointer
;
5088 S_SET_STORAGE_CLASS (sym
, get_absolute_expression ());
5090 if (*input_line_pointer
!= ',')
5092 as_bad (_("missing type"));
5095 ++input_line_pointer
;
5097 S_SET_DATA_TYPE (sym
, get_absolute_expression ());
5099 symbol_get_tc (sym
)->output
= 1;
5101 if (S_GET_STORAGE_CLASS (sym
) == C_STSYM
)
5106 .stabx "z",arrays_,133,0
5109 .comm arrays_,13768,3
5111 resolve_symbol_value will copy the exp's "within" into sym's when the
5112 offset is 0. Since this seems to be corner case problem,
5113 only do the correction for storage class C_STSYM. A better solution
5114 would be to have the tc field updated in ppc_symbol_new_hook. */
5116 if (exp
.X_op
== O_symbol
)
5118 if (ppc_current_block
== NULL
)
5119 as_bad (_(".stabx of storage class stsym must be within .bs/.es"));
5121 symbol_get_tc (sym
)->within
= ppc_current_block
;
5122 symbol_get_tc (exp
.X_add_symbol
)->within
= ppc_current_block
;
5126 if (exp
.X_op
!= O_symbol
5127 || ! S_IS_EXTERNAL (exp
.X_add_symbol
)
5128 || S_GET_SEGMENT (exp
.X_add_symbol
) != bss_section
)
5129 ppc_frob_label (sym
);
5132 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
5133 symbol_append (sym
, exp
.X_add_symbol
, &symbol_rootP
, &symbol_lastP
);
5134 if (symbol_get_tc (ppc_current_csect
)->within
== exp
.X_add_symbol
)
5135 symbol_get_tc (ppc_current_csect
)->within
= sym
;
5138 demand_empty_rest_of_line ();
5141 /* The .function pseudo-op. This takes several arguments. The first
5142 argument seems to be the external name of the symbol. The second
5143 argument seems to be the label for the start of the function. gcc
5144 uses the same name for both. I have no idea what the third and
5145 fourth arguments are meant to be. The optional fifth argument is
5146 an expression for the size of the function. In COFF this symbol
5147 gets an aux entry like that used for a csect. */
5150 ppc_function (int ignore ATTRIBUTE_UNUSED
)
5158 endc
= get_symbol_name (&name
);
5160 /* Ignore any [PR] suffix. */
5161 name
= ppc_canonicalize_symbol_name (name
);
5162 s
= strchr (name
, '[');
5163 if (s
!= (char *) NULL
5164 && strcmp (s
+ 1, "PR]") == 0)
5167 ext_sym
= symbol_find_or_make (name
);
5169 (void) restore_line_pointer (endc
);
5171 if (*input_line_pointer
!= ',')
5173 as_bad (_("missing symbol name"));
5174 ignore_rest_of_line ();
5177 ++input_line_pointer
;
5179 endc
= get_symbol_name (&name
);
5181 lab_sym
= symbol_find_or_make (name
);
5183 (void) restore_line_pointer (endc
);
5185 if (ext_sym
!= lab_sym
)
5189 exp
.X_op
= O_symbol
;
5190 exp
.X_add_symbol
= lab_sym
;
5191 exp
.X_op_symbol
= NULL
;
5192 exp
.X_add_number
= 0;
5194 symbol_set_value_expression (ext_sym
, &exp
);
5197 if (symbol_get_tc (ext_sym
)->symbol_class
== -1)
5198 symbol_get_tc (ext_sym
)->symbol_class
= XMC_PR
;
5199 symbol_get_tc (ext_sym
)->output
= 1;
5201 if (*input_line_pointer
== ',')
5205 /* Ignore the third argument. */
5206 ++input_line_pointer
;
5208 if (*input_line_pointer
== ',')
5210 /* Ignore the fourth argument. */
5211 ++input_line_pointer
;
5213 if (*input_line_pointer
== ',')
5215 /* The fifth argument is the function size. */
5216 ++input_line_pointer
;
5217 symbol_get_tc (ext_sym
)->u
.size
= symbol_new
5218 ("L0\001", absolute_section
,(valueT
) 0, &zero_address_frag
);
5219 pseudo_set (symbol_get_tc (ext_sym
)->u
.size
);
5224 S_SET_DATA_TYPE (ext_sym
, DT_FCN
<< N_BTSHFT
);
5225 SF_SET_FUNCTION (ext_sym
);
5226 SF_SET_PROCESS (ext_sym
);
5227 coff_add_linesym (ext_sym
);
5229 demand_empty_rest_of_line ();
5232 /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named
5233 ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym
5234 with the correct line number */
5236 static symbolS
*saved_bi_sym
= 0;
5239 ppc_bf (int ignore ATTRIBUTE_UNUSED
)
5243 sym
= symbol_make (".bf");
5244 S_SET_SEGMENT (sym
, text_section
);
5245 symbol_set_frag (sym
, frag_now
);
5246 S_SET_VALUE (sym
, frag_now_fix ());
5247 S_SET_STORAGE_CLASS (sym
, C_FCN
);
5249 coff_line_base
= get_absolute_expression ();
5251 S_SET_NUMBER_AUXILIARY (sym
, 1);
5252 SA_SET_SYM_LNNO (sym
, coff_line_base
);
5254 /* Line number for bi. */
5257 S_SET_VALUE (saved_bi_sym
, coff_n_line_nos
);
5262 symbol_get_tc (sym
)->output
= 1;
5264 ppc_frob_label (sym
);
5266 demand_empty_rest_of_line ();
5269 /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named
5270 ".ef", except that the line number is absolute, not relative to the
5271 most recent ".bf" symbol. */
5274 ppc_ef (int ignore ATTRIBUTE_UNUSED
)
5278 sym
= symbol_make (".ef");
5279 S_SET_SEGMENT (sym
, text_section
);
5280 symbol_set_frag (sym
, frag_now
);
5281 S_SET_VALUE (sym
, frag_now_fix ());
5282 S_SET_STORAGE_CLASS (sym
, C_FCN
);
5283 S_SET_NUMBER_AUXILIARY (sym
, 1);
5284 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5285 symbol_get_tc (sym
)->output
= 1;
5287 ppc_frob_label (sym
);
5289 demand_empty_rest_of_line ();
5292 /* The .bi and .ei pseudo-ops. These take a string argument and
5293 generates a C_BINCL or C_EINCL symbol, which goes at the start of
5294 the symbol list. The value of .bi will be know when the next .bf
5300 static symbolS
*last_biei
;
5307 name
= demand_copy_C_string (&len
);
5309 /* The value of these symbols is actually file offset. Here we set
5310 the value to the index into the line number entries. In
5311 ppc_frob_symbols we set the fix_line field, which will cause BFD
5312 to do the right thing. */
5314 sym
= symbol_make (name
);
5315 /* obj-coff.c currently only handles line numbers correctly in the
5317 S_SET_SEGMENT (sym
, text_section
);
5318 S_SET_VALUE (sym
, coff_n_line_nos
);
5319 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5321 S_SET_STORAGE_CLASS (sym
, ei
? C_EINCL
: C_BINCL
);
5322 symbol_get_tc (sym
)->output
= 1;
5330 for (look
= last_biei
? last_biei
: symbol_rootP
;
5331 (look
!= (symbolS
*) NULL
5332 && (S_GET_STORAGE_CLASS (look
) == C_FILE
5333 || S_GET_STORAGE_CLASS (look
) == C_BINCL
5334 || S_GET_STORAGE_CLASS (look
) == C_EINCL
));
5335 look
= symbol_next (look
))
5337 if (look
!= (symbolS
*) NULL
)
5339 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
5340 symbol_insert (sym
, look
, &symbol_rootP
, &symbol_lastP
);
5344 demand_empty_rest_of_line ();
5347 /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs".
5348 There is one argument, which is a csect symbol. The value of the
5349 .bs symbol is the index of this csect symbol. */
5352 ppc_bs (int ignore ATTRIBUTE_UNUSED
)
5359 if (ppc_current_block
!= NULL
)
5360 as_bad (_("nested .bs blocks"));
5362 endc
= get_symbol_name (&name
);
5364 csect
= symbol_find_or_make (name
);
5366 (void) restore_line_pointer (endc
);
5368 sym
= symbol_make (".bs");
5369 S_SET_SEGMENT (sym
, now_seg
);
5370 S_SET_STORAGE_CLASS (sym
, C_BSTAT
);
5371 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5372 symbol_get_tc (sym
)->output
= 1;
5374 symbol_get_tc (sym
)->within
= csect
;
5376 ppc_frob_label (sym
);
5378 ppc_current_block
= sym
;
5380 demand_empty_rest_of_line ();
5383 /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */
5386 ppc_es (int ignore ATTRIBUTE_UNUSED
)
5390 if (ppc_current_block
== NULL
)
5391 as_bad (_(".es without preceding .bs"));
5393 sym
= symbol_make (".es");
5394 S_SET_SEGMENT (sym
, now_seg
);
5395 S_SET_STORAGE_CLASS (sym
, C_ESTAT
);
5396 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5397 symbol_get_tc (sym
)->output
= 1;
5399 ppc_frob_label (sym
);
5401 ppc_current_block
= NULL
;
5403 demand_empty_rest_of_line ();
5406 /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a
5410 ppc_bb (int ignore ATTRIBUTE_UNUSED
)
5414 sym
= symbol_make (".bb");
5415 S_SET_SEGMENT (sym
, text_section
);
5416 symbol_set_frag (sym
, frag_now
);
5417 S_SET_VALUE (sym
, frag_now_fix ());
5418 S_SET_STORAGE_CLASS (sym
, C_BLOCK
);
5420 S_SET_NUMBER_AUXILIARY (sym
, 1);
5421 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5423 symbol_get_tc (sym
)->output
= 1;
5425 SF_SET_PROCESS (sym
);
5427 ppc_frob_label (sym
);
5429 demand_empty_rest_of_line ();
5432 /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a
5436 ppc_eb (int ignore ATTRIBUTE_UNUSED
)
5440 sym
= symbol_make (".eb");
5441 S_SET_SEGMENT (sym
, text_section
);
5442 symbol_set_frag (sym
, frag_now
);
5443 S_SET_VALUE (sym
, frag_now_fix ());
5444 S_SET_STORAGE_CLASS (sym
, C_BLOCK
);
5445 S_SET_NUMBER_AUXILIARY (sym
, 1);
5446 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5447 symbol_get_tc (sym
)->output
= 1;
5449 SF_SET_PROCESS (sym
);
5451 ppc_frob_label (sym
);
5453 demand_empty_rest_of_line ();
5456 /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a
5460 ppc_bc (int ignore ATTRIBUTE_UNUSED
)
5466 name
= demand_copy_C_string (&len
);
5467 sym
= symbol_make (name
);
5468 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
5469 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5470 S_SET_STORAGE_CLASS (sym
, C_BCOMM
);
5471 S_SET_VALUE (sym
, 0);
5472 symbol_get_tc (sym
)->output
= 1;
5474 ppc_frob_label (sym
);
5476 demand_empty_rest_of_line ();
5479 /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */
5482 ppc_ec (int ignore ATTRIBUTE_UNUSED
)
5486 sym
= symbol_make (".ec");
5487 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
5488 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5489 S_SET_STORAGE_CLASS (sym
, C_ECOMM
);
5490 S_SET_VALUE (sym
, 0);
5491 symbol_get_tc (sym
)->output
= 1;
5493 ppc_frob_label (sym
);
5495 demand_empty_rest_of_line ();
5498 /* The .toc pseudo-op. Switch to the .toc subsegment. */
5501 ppc_toc (int ignore ATTRIBUTE_UNUSED
)
5503 if (ppc_toc_csect
!= (symbolS
*) NULL
)
5504 subseg_set (data_section
, symbol_get_tc (ppc_toc_csect
)->subseg
);
5511 subseg
= ppc_data_subsegment
;
5512 ++ppc_data_subsegment
;
5514 subseg_new (segment_name (data_section
), subseg
);
5515 ppc_toc_frag
= frag_now
;
5517 sym
= symbol_find_or_make ("TOC[TC0]");
5518 symbol_set_frag (sym
, frag_now
);
5519 S_SET_SEGMENT (sym
, data_section
);
5520 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5521 symbol_get_tc (sym
)->subseg
= subseg
;
5522 symbol_get_tc (sym
)->output
= 1;
5523 symbol_get_tc (sym
)->within
= sym
;
5525 ppc_toc_csect
= sym
;
5527 for (list
= ppc_data_csects
;
5528 symbol_get_tc (list
)->next
!= (symbolS
*) NULL
;
5529 list
= symbol_get_tc (list
)->next
)
5531 symbol_get_tc (list
)->next
= sym
;
5533 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
5534 symbol_append (sym
, symbol_get_tc (list
)->within
, &symbol_rootP
,
5538 ppc_current_csect
= ppc_toc_csect
;
5540 demand_empty_rest_of_line ();
5543 /* The AIX assembler automatically aligns the operands of a .long or
5544 .short pseudo-op, and we want to be compatible. */
5547 ppc_xcoff_cons (int log_size
)
5549 frag_align (log_size
, 0, 0);
5550 record_alignment (now_seg
, log_size
);
5551 cons (1 << log_size
);
5555 ppc_vbyte (int dummy ATTRIBUTE_UNUSED
)
5560 (void) expression (&exp
);
5562 if (exp
.X_op
!= O_constant
)
5564 as_bad (_("non-constant byte count"));
5568 byte_count
= exp
.X_add_number
;
5570 if (*input_line_pointer
!= ',')
5572 as_bad (_("missing value"));
5576 ++input_line_pointer
;
5581 ppc_xcoff_end (void)
5585 for (i
= 0; i
< XCOFF_DWSECT_NBR_NAMES
; i
++)
5587 struct dw_section
*dws
= &dw_sections
[i
];
5588 struct dw_subsection
*dwss
;
5590 if (dws
->anon_subseg
)
5592 dwss
= dws
->anon_subseg
;
5593 dwss
->link
= dws
->list_subseg
;
5596 dwss
= dws
->list_subseg
;
5598 for (; dwss
!= NULL
; dwss
= dwss
->link
)
5599 if (dwss
->end_exp
.X_add_symbol
!= NULL
)
5601 subseg_set (dws
->sect
, dwss
->subseg
);
5602 symbol_set_value_now (dwss
->end_exp
.X_add_symbol
);
5608 #endif /* OBJ_XCOFF */
5609 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
5611 /* The .tc pseudo-op. This is used when generating either XCOFF or
5612 ELF. This takes two or more arguments.
5614 When generating XCOFF output, the first argument is the name to
5615 give to this location in the toc; this will be a symbol with class
5616 TC. The rest of the arguments are N-byte values to actually put at
5617 this location in the TOC; often there is just one more argument, a
5618 relocatable symbol reference. The size of the value to store
5619 depends on target word size. A 32-bit target uses 4-byte values, a
5620 64-bit target uses 8-byte values.
5622 When not generating XCOFF output, the arguments are the same, but
5623 the first argument is simply ignored. */
5626 ppc_tc (int ignore ATTRIBUTE_UNUSED
)
5630 /* Define the TOC symbol name. */
5636 if (ppc_toc_csect
== (symbolS
*) NULL
5637 || ppc_toc_csect
!= ppc_current_csect
)
5639 as_bad (_(".tc not in .toc section"));
5640 ignore_rest_of_line ();
5644 endc
= get_symbol_name (&name
);
5646 sym
= symbol_find_or_make (name
);
5648 (void) restore_line_pointer (endc
);
5650 if (S_IS_DEFINED (sym
))
5654 label
= symbol_get_tc (ppc_current_csect
)->within
;
5655 if (symbol_get_tc (label
)->symbol_class
!= XMC_TC0
)
5657 as_bad (_(".tc with no label"));
5658 ignore_rest_of_line ();
5662 S_SET_SEGMENT (label
, S_GET_SEGMENT (sym
));
5663 symbol_set_frag (label
, symbol_get_frag (sym
));
5664 S_SET_VALUE (label
, S_GET_VALUE (sym
));
5666 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5667 ++input_line_pointer
;
5672 S_SET_SEGMENT (sym
, now_seg
);
5673 symbol_set_frag (sym
, frag_now
);
5674 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5675 symbol_get_tc (sym
)->symbol_class
= XMC_TC
;
5676 symbol_get_tc (sym
)->output
= 1;
5678 ppc_frob_label (sym
);
5681 #endif /* OBJ_XCOFF */
5685 /* Skip the TOC symbol name. */
5686 while (is_part_of_name (*input_line_pointer
)
5687 || *input_line_pointer
== ' '
5688 || *input_line_pointer
== '['
5689 || *input_line_pointer
== ']'
5690 || *input_line_pointer
== '{'
5691 || *input_line_pointer
== '}')
5692 ++input_line_pointer
;
5694 /* Align to a four/eight byte boundary. */
5695 align
= ppc_obj64
? 3 : 2;
5696 frag_align (align
, 0, 0);
5697 record_alignment (now_seg
, align
);
5698 #endif /* OBJ_ELF */
5700 if (*input_line_pointer
!= ',')
5701 demand_empty_rest_of_line ();
5704 ++input_line_pointer
;
5705 cons (ppc_obj64
? 8 : 4);
5709 /* Pseudo-op .machine. */
5712 ppc_machine (int ignore ATTRIBUTE_UNUSED
)
5716 #define MAX_HISTORY 100
5717 static ppc_cpu_t
*cpu_history
;
5718 static int curr_hist
;
5722 c
= get_symbol_name (&cpu_string
);
5723 cpu_string
= xstrdup (cpu_string
);
5724 (void) restore_line_pointer (c
);
5726 if (cpu_string
!= NULL
)
5728 ppc_cpu_t old_cpu
= ppc_cpu
;
5732 for (p
= cpu_string
; *p
!= 0; p
++)
5735 if (strcmp (cpu_string
, "push") == 0)
5737 if (cpu_history
== NULL
)
5738 cpu_history
= XNEWVEC (ppc_cpu_t
, MAX_HISTORY
);
5740 if (curr_hist
>= MAX_HISTORY
)
5741 as_bad (_(".machine stack overflow"));
5743 cpu_history
[curr_hist
++] = ppc_cpu
;
5745 else if (strcmp (cpu_string
, "pop") == 0)
5748 as_bad (_(".machine stack underflow"));
5750 ppc_cpu
= cpu_history
[--curr_hist
];
5752 else if ((new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, cpu_string
)) != 0)
5755 as_bad (_("invalid machine `%s'"), cpu_string
);
5757 if (ppc_cpu
!= old_cpu
)
5758 ppc_setup_opcodes ();
5761 demand_empty_rest_of_line ();
5763 #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
5767 /* Pseudo-ops specific to the Windows NT PowerPC PE (coff) format. */
5769 /* Set the current section. */
5771 ppc_set_current_section (segT
new)
5773 ppc_previous_section
= ppc_current_section
;
5774 ppc_current_section
= new;
5777 /* pseudo-op: .previous
5778 behaviour: toggles the current section with the previous section.
5780 warnings: "No previous section" */
5783 ppc_previous (int ignore ATTRIBUTE_UNUSED
)
5785 if (ppc_previous_section
== NULL
)
5787 as_warn (_("no previous section to return to, ignored."));
5791 subseg_set (ppc_previous_section
, 0);
5793 ppc_set_current_section (ppc_previous_section
);
5796 /* pseudo-op: .pdata
5797 behaviour: predefined read only data section
5801 initial: .section .pdata "adr3"
5802 a - don't know -- maybe a misprint
5803 d - initialized data
5805 3 - double word aligned (that would be 4 byte boundary)
5808 Tag index tables (also known as the function table) for exception
5809 handling, debugging, etc. */
5812 ppc_pdata (int ignore ATTRIBUTE_UNUSED
)
5814 if (pdata_section
== 0)
5816 pdata_section
= subseg_new (".pdata", 0);
5818 bfd_set_section_flags (pdata_section
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
5819 | SEC_READONLY
| SEC_DATA
));
5821 bfd_set_section_alignment (pdata_section
, 2);
5825 pdata_section
= subseg_new (".pdata", 0);
5827 ppc_set_current_section (pdata_section
);
5830 /* pseudo-op: .ydata
5831 behaviour: predefined read only data section
5835 initial: .section .ydata "drw3"
5836 a - don't know -- maybe a misprint
5837 d - initialized data
5839 3 - double word aligned (that would be 4 byte boundary)
5841 Tag tables (also known as the scope table) for exception handling,
5845 ppc_ydata (int ignore ATTRIBUTE_UNUSED
)
5847 if (ydata_section
== 0)
5849 ydata_section
= subseg_new (".ydata", 0);
5850 bfd_set_section_flags (ydata_section
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
5851 | SEC_READONLY
| SEC_DATA
));
5853 bfd_set_section_alignment (ydata_section
, 3);
5857 ydata_section
= subseg_new (".ydata", 0);
5859 ppc_set_current_section (ydata_section
);
5862 /* pseudo-op: .reldata
5863 behaviour: predefined read write data section
5864 double word aligned (4-byte)
5865 FIXME: relocation is applied to it
5866 FIXME: what's the difference between this and .data?
5869 initial: .section .reldata "drw3"
5870 d - initialized data
5873 3 - double word aligned (that would be 8 byte boundary)
5876 Like .data, but intended to hold data subject to relocation, such as
5877 function descriptors, etc. */
5880 ppc_reldata (int ignore ATTRIBUTE_UNUSED
)
5882 if (reldata_section
== 0)
5884 reldata_section
= subseg_new (".reldata", 0);
5886 bfd_set_section_flags (reldata_section
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
5889 bfd_set_section_alignment (reldata_section
, 2);
5893 reldata_section
= subseg_new (".reldata", 0);
5895 ppc_set_current_section (reldata_section
);
5898 /* pseudo-op: .rdata
5899 behaviour: predefined read only data section
5903 initial: .section .rdata "dr3"
5904 d - initialized data
5906 3 - double word aligned (that would be 4 byte boundary) */
5909 ppc_rdata (int ignore ATTRIBUTE_UNUSED
)
5911 if (rdata_section
== 0)
5913 rdata_section
= subseg_new (".rdata", 0);
5914 bfd_set_section_flags (rdata_section
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
5915 | SEC_READONLY
| SEC_DATA
));
5917 bfd_set_section_alignment (rdata_section
, 2);
5921 rdata_section
= subseg_new (".rdata", 0);
5923 ppc_set_current_section (rdata_section
);
5926 /* pseudo-op: .ualong
5927 behaviour: much like .int, with the exception that no alignment is
5929 FIXME: test the alignment statement
5934 ppc_ualong (int ignore ATTRIBUTE_UNUSED
)
5940 /* pseudo-op: .znop <symbol name>
5941 behaviour: Issue a nop instruction
5942 Issue a IMAGE_REL_PPC_IFGLUE relocation against it, using
5943 the supplied symbol name.
5945 warnings: Missing symbol name */
5948 ppc_znop (int ignore ATTRIBUTE_UNUSED
)
5951 const struct powerpc_opcode
*opcode
;
5958 /* Strip out the symbol name. */
5959 c
= get_symbol_name (&symbol_name
);
5961 name
= xstrdup (symbol_name
);
5963 sym
= symbol_find_or_make (name
);
5965 *input_line_pointer
= c
;
5967 SKIP_WHITESPACE_AFTER_NAME ();
5969 /* Look up the opcode in the hash table. */
5970 opcode
= (const struct powerpc_opcode
*) hash_find (ppc_hash
, "nop");
5972 /* Stick in the nop. */
5973 insn
= opcode
->opcode
;
5975 /* Write out the instruction. */
5977 md_number_to_chars (f
, insn
, 4);
5979 f
- frag_now
->fr_literal
,
5984 BFD_RELOC_16_GOT_PCREL
);
5994 ppc_pe_comm (int lcomm
)
6003 c
= get_symbol_name (&name
);
6005 /* just after name is now '\0'. */
6006 p
= input_line_pointer
;
6008 SKIP_WHITESPACE_AFTER_NAME ();
6009 if (*input_line_pointer
!= ',')
6011 as_bad (_("expected comma after symbol-name: rest of line ignored."));
6012 ignore_rest_of_line ();
6016 input_line_pointer
++; /* skip ',' */
6017 if ((temp
= get_absolute_expression ()) < 0)
6019 as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) temp
);
6020 ignore_rest_of_line ();
6026 /* The third argument to .comm is the alignment. */
6027 if (*input_line_pointer
!= ',')
6031 ++input_line_pointer
;
6032 align
= get_absolute_expression ();
6035 as_warn (_("ignoring bad alignment"));
6042 symbolP
= symbol_find_or_make (name
);
6045 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
6047 as_bad (_("ignoring attempt to re-define symbol `%s'."),
6048 S_GET_NAME (symbolP
));
6049 ignore_rest_of_line ();
6053 if (S_GET_VALUE (symbolP
))
6055 if (S_GET_VALUE (symbolP
) != (valueT
) temp
)
6056 as_bad (_("length of .comm \"%s\" is already %ld. Not changed to %ld."),
6057 S_GET_NAME (symbolP
),
6058 (long) S_GET_VALUE (symbolP
),
6063 S_SET_VALUE (symbolP
, (valueT
) temp
);
6064 S_SET_EXTERNAL (symbolP
);
6065 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
6068 demand_empty_rest_of_line ();
6072 * implement the .section pseudo op:
6073 * .section name {, "flags"}
6075 * | +--- optional flags: 'b' for bss
6077 * +-- section name 'l' for lib
6081 * 'd' (apparently m88k for data)
6083 * But if the argument is not a quoted string, treat it as a
6084 * subsegment number.
6086 * FIXME: this is a copy of the section processing from obj-coff.c, with
6087 * additions/changes for the moto-pas assembler support. There are three
6090 * FIXME: I just noticed this. This doesn't work at all really. It it
6091 * setting bits that bfd probably neither understands or uses. The
6092 * correct approach (?) will have to incorporate extra fields attached
6093 * to the section to hold the system specific stuff. (krk)
6096 * 'a' - unknown - referred to in documentation, but no definition supplied
6097 * 'c' - section has code
6098 * 'd' - section has initialized data
6099 * 'u' - section has uninitialized data
6100 * 'i' - section contains directives (info)
6101 * 'n' - section can be discarded
6102 * 'R' - remove section at link time
6104 * Section Protection:
6105 * 'r' - section is readable
6106 * 'w' - section is writable
6107 * 'x' - section is executable
6108 * 's' - section is sharable
6110 * Section Alignment:
6111 * '0' - align to byte boundary
6112 * '1' - align to halfword boundary
6113 * '2' - align to word boundary
6114 * '3' - align to doubleword boundary
6115 * '4' - align to quadword boundary
6116 * '5' - align to 32 byte boundary
6117 * '6' - align to 64 byte boundary
6122 ppc_pe_section (int ignore ATTRIBUTE_UNUSED
)
6124 /* Strip out the section name. */
6133 c
= get_symbol_name (§ion_name
);
6135 name
= xstrdup (section_name
);
6137 *input_line_pointer
= c
;
6139 SKIP_WHITESPACE_AFTER_NAME ();
6142 flags
= SEC_NO_FLAGS
;
6144 if (strcmp (name
, ".idata$2") == 0)
6148 else if (strcmp (name
, ".idata$3") == 0)
6152 else if (strcmp (name
, ".idata$4") == 0)
6156 else if (strcmp (name
, ".idata$5") == 0)
6160 else if (strcmp (name
, ".idata$6") == 0)
6165 /* Default alignment to 16 byte boundary. */
6168 if (*input_line_pointer
== ',')
6170 ++input_line_pointer
;
6172 if (*input_line_pointer
!= '"')
6173 exp
= get_absolute_expression ();
6176 ++input_line_pointer
;
6177 while (*input_line_pointer
!= '"'
6178 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
6180 switch (*input_line_pointer
)
6182 /* Section Contents */
6183 case 'a': /* unknown */
6184 as_bad (_("unsupported section attribute -- 'a'"));
6186 case 'c': /* code section */
6189 case 'd': /* section has initialized data */
6192 case 'u': /* section has uninitialized data */
6193 /* FIXME: This is IMAGE_SCN_CNT_UNINITIALIZED_DATA
6197 case 'i': /* section contains directives (info) */
6198 /* FIXME: This is IMAGE_SCN_LNK_INFO
6200 flags
|= SEC_HAS_CONTENTS
;
6202 case 'n': /* section can be discarded */
6205 case 'R': /* Remove section at link time */
6206 flags
|= SEC_NEVER_LOAD
;
6208 #if IFLICT_BRAIN_DAMAGE
6209 /* Section Protection */
6210 case 'r': /* section is readable */
6211 flags
|= IMAGE_SCN_MEM_READ
;
6213 case 'w': /* section is writable */
6214 flags
|= IMAGE_SCN_MEM_WRITE
;
6216 case 'x': /* section is executable */
6217 flags
|= IMAGE_SCN_MEM_EXECUTE
;
6219 case 's': /* section is sharable */
6220 flags
|= IMAGE_SCN_MEM_SHARED
;
6223 /* Section Alignment */
6224 case '0': /* align to byte boundary */
6225 flags
|= IMAGE_SCN_ALIGN_1BYTES
;
6228 case '1': /* align to halfword boundary */
6229 flags
|= IMAGE_SCN_ALIGN_2BYTES
;
6232 case '2': /* align to word boundary */
6233 flags
|= IMAGE_SCN_ALIGN_4BYTES
;
6236 case '3': /* align to doubleword boundary */
6237 flags
|= IMAGE_SCN_ALIGN_8BYTES
;
6240 case '4': /* align to quadword boundary */
6241 flags
|= IMAGE_SCN_ALIGN_16BYTES
;
6244 case '5': /* align to 32 byte boundary */
6245 flags
|= IMAGE_SCN_ALIGN_32BYTES
;
6248 case '6': /* align to 64 byte boundary */
6249 flags
|= IMAGE_SCN_ALIGN_64BYTES
;
6254 as_bad (_("unknown section attribute '%c'"),
6255 *input_line_pointer
);
6258 ++input_line_pointer
;
6260 if (*input_line_pointer
== '"')
6261 ++input_line_pointer
;
6265 sec
= subseg_new (name
, (subsegT
) exp
);
6267 ppc_set_current_section (sec
);
6269 if (flags
!= SEC_NO_FLAGS
)
6271 if (!bfd_set_section_flags (sec
, flags
))
6272 as_bad (_("error setting flags for \"%s\": %s"),
6273 bfd_section_name (sec
),
6274 bfd_errmsg (bfd_get_error ()));
6277 bfd_set_section_alignment (sec
, align
);
6281 ppc_pe_function (int ignore ATTRIBUTE_UNUSED
)
6287 endc
= get_symbol_name (&name
);
6289 ext_sym
= symbol_find_or_make (name
);
6291 (void) restore_line_pointer (endc
);
6293 S_SET_DATA_TYPE (ext_sym
, DT_FCN
<< N_BTSHFT
);
6294 SF_SET_FUNCTION (ext_sym
);
6295 SF_SET_PROCESS (ext_sym
);
6296 coff_add_linesym (ext_sym
);
6298 demand_empty_rest_of_line ();
6302 ppc_pe_tocd (int ignore ATTRIBUTE_UNUSED
)
6304 if (tocdata_section
== 0)
6306 tocdata_section
= subseg_new (".tocd", 0);
6307 /* FIXME: section flags won't work. */
6308 bfd_set_section_flags (tocdata_section
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6309 | SEC_READONLY
| SEC_DATA
));
6311 bfd_set_section_alignment (tocdata_section
, 2);
6315 rdata_section
= subseg_new (".tocd", 0);
6318 ppc_set_current_section (tocdata_section
);
6320 demand_empty_rest_of_line ();
6323 /* Don't adjust TOC relocs to use the section symbol. */
6326 ppc_pe_fix_adjustable (fixS
*fix
)
6328 return fix
->fx_r_type
!= BFD_RELOC_PPC_TOC16
;
6335 /* XCOFF specific symbol and file handling. */
6337 /* Canonicalize the symbol name. We use the to force the suffix, if
6338 any, to use square brackets, and to be in upper case. */
6341 ppc_canonicalize_symbol_name (char *name
)
6345 if (ppc_stab_symbol
)
6348 for (s
= name
; *s
!= '\0' && *s
!= '{' && *s
!= '['; s
++)
6362 for (s
++; *s
!= '\0' && *s
!= brac
; s
++)
6365 if (*s
== '\0' || s
[1] != '\0')
6366 as_bad (_("bad symbol suffix"));
6374 /* Set the class of a symbol based on the suffix, if any. This is
6375 called whenever a new symbol is created. */
6378 ppc_symbol_new_hook (symbolS
*sym
)
6380 struct ppc_tc_sy
*tc
;
6383 tc
= symbol_get_tc (sym
);
6386 tc
->symbol_class
= -1;
6387 tc
->real_name
= NULL
;
6394 if (ppc_stab_symbol
)
6397 s
= strchr (S_GET_NAME (sym
), '[');
6398 if (s
== (const char *) NULL
)
6400 /* There is no suffix. */
6409 if (strcmp (s
, "BS]") == 0)
6410 tc
->symbol_class
= XMC_BS
;
6413 if (strcmp (s
, "DB]") == 0)
6414 tc
->symbol_class
= XMC_DB
;
6415 else if (strcmp (s
, "DS]") == 0)
6416 tc
->symbol_class
= XMC_DS
;
6419 if (strcmp (s
, "GL]") == 0)
6420 tc
->symbol_class
= XMC_GL
;
6423 if (strcmp (s
, "PR]") == 0)
6424 tc
->symbol_class
= XMC_PR
;
6427 if (strcmp (s
, "RO]") == 0)
6428 tc
->symbol_class
= XMC_RO
;
6429 else if (strcmp (s
, "RW]") == 0)
6430 tc
->symbol_class
= XMC_RW
;
6433 if (strcmp (s
, "SV]") == 0)
6434 tc
->symbol_class
= XMC_SV
;
6437 if (strcmp (s
, "TC]") == 0)
6438 tc
->symbol_class
= XMC_TC
;
6439 else if (strcmp (s
, "TI]") == 0)
6440 tc
->symbol_class
= XMC_TI
;
6441 else if (strcmp (s
, "TB]") == 0)
6442 tc
->symbol_class
= XMC_TB
;
6443 else if (strcmp (s
, "TC0]") == 0 || strcmp (s
, "T0]") == 0)
6444 tc
->symbol_class
= XMC_TC0
;
6447 if (strcmp (s
, "UA]") == 0)
6448 tc
->symbol_class
= XMC_UA
;
6449 else if (strcmp (s
, "UC]") == 0)
6450 tc
->symbol_class
= XMC_UC
;
6453 if (strcmp (s
, "XO]") == 0)
6454 tc
->symbol_class
= XMC_XO
;
6458 if (tc
->symbol_class
== -1)
6459 as_bad (_("unrecognized symbol suffix"));
6462 /* This variable is set by ppc_frob_symbol if any absolute symbols are
6463 seen. It tells ppc_adjust_symtab whether it needs to look through
6466 static bfd_boolean ppc_saw_abs
;
6468 /* Change the name of a symbol just before writing it out. Set the
6469 real name if the .rename pseudo-op was used. Otherwise, remove any
6470 class suffix. Return 1 if the symbol should not be included in the
6474 ppc_frob_symbol (symbolS
*sym
)
6476 static symbolS
*ppc_last_function
;
6477 static symbolS
*set_end
;
6479 /* Discard symbols that should not be included in the output symbol
6481 if (! symbol_used_in_reloc_p (sym
)
6482 && ((symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
) != 0
6483 || (! (S_IS_EXTERNAL (sym
) || S_IS_WEAK (sym
))
6484 && ! symbol_get_tc (sym
)->output
6485 && S_GET_STORAGE_CLASS (sym
) != C_FILE
)))
6488 /* This one will disappear anyway. Don't make a csect sym for it. */
6489 if (sym
== abs_section_sym
)
6492 if (symbol_get_tc (sym
)->real_name
!= (char *) NULL
)
6493 S_SET_NAME (sym
, symbol_get_tc (sym
)->real_name
);
6499 name
= S_GET_NAME (sym
);
6500 s
= strchr (name
, '[');
6501 if (s
!= (char *) NULL
)
6507 snew
= xstrndup (name
, len
);
6509 S_SET_NAME (sym
, snew
);
6513 if (set_end
!= (symbolS
*) NULL
)
6515 SA_SET_SYM_ENDNDX (set_end
, sym
);
6519 if (SF_GET_FUNCTION (sym
))
6521 if (ppc_last_function
!= (symbolS
*) NULL
)
6522 as_bad (_("two .function pseudo-ops with no intervening .ef"));
6523 ppc_last_function
= sym
;
6524 if (symbol_get_tc (sym
)->u
.size
!= (symbolS
*) NULL
)
6526 resolve_symbol_value (symbol_get_tc (sym
)->u
.size
);
6527 SA_SET_SYM_FSIZE (sym
,
6528 (long) S_GET_VALUE (symbol_get_tc (sym
)->u
.size
));
6531 else if (S_GET_STORAGE_CLASS (sym
) == C_FCN
6532 && strcmp (S_GET_NAME (sym
), ".ef") == 0)
6534 if (ppc_last_function
== (symbolS
*) NULL
)
6535 as_bad (_(".ef with no preceding .function"));
6538 set_end
= ppc_last_function
;
6539 ppc_last_function
= NULL
;
6541 /* We don't have a C_EFCN symbol, but we need to force the
6542 COFF backend to believe that it has seen one. */
6543 coff_last_function
= NULL
;
6547 if (! (S_IS_EXTERNAL (sym
) || S_IS_WEAK (sym
))
6548 && (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
) == 0
6549 && S_GET_STORAGE_CLASS (sym
) != C_FILE
6550 && S_GET_STORAGE_CLASS (sym
) != C_FCN
6551 && S_GET_STORAGE_CLASS (sym
) != C_BLOCK
6552 && S_GET_STORAGE_CLASS (sym
) != C_BSTAT
6553 && S_GET_STORAGE_CLASS (sym
) != C_ESTAT
6554 && S_GET_STORAGE_CLASS (sym
) != C_BINCL
6555 && S_GET_STORAGE_CLASS (sym
) != C_EINCL
6556 && S_GET_SEGMENT (sym
) != ppc_coff_debug_section
)
6557 S_SET_STORAGE_CLASS (sym
, C_HIDEXT
);
6559 if (S_GET_STORAGE_CLASS (sym
) == C_EXT
6560 || S_GET_STORAGE_CLASS (sym
) == C_AIX_WEAKEXT
6561 || S_GET_STORAGE_CLASS (sym
) == C_HIDEXT
)
6564 union internal_auxent
*a
;
6566 /* Create a csect aux. */
6567 i
= S_GET_NUMBER_AUXILIARY (sym
);
6568 S_SET_NUMBER_AUXILIARY (sym
, i
+ 1);
6569 a
= &coffsymbol (symbol_get_bfdsym (sym
))->native
[i
+ 1].u
.auxent
;
6570 if (symbol_get_tc (sym
)->symbol_class
== XMC_TC0
)
6572 /* This is the TOC table. */
6573 know (strcmp (S_GET_NAME (sym
), "TOC") == 0);
6574 a
->x_csect
.x_scnlen
.l
= 0;
6575 a
->x_csect
.x_smtyp
= (2 << 3) | XTY_SD
;
6577 else if (symbol_get_tc (sym
)->subseg
!= 0)
6579 /* This is a csect symbol. x_scnlen is the size of the
6581 if (symbol_get_tc (sym
)->next
== (symbolS
*) NULL
)
6582 a
->x_csect
.x_scnlen
.l
= (bfd_section_size (S_GET_SEGMENT (sym
))
6583 - S_GET_VALUE (sym
));
6586 resolve_symbol_value (symbol_get_tc (sym
)->next
);
6587 a
->x_csect
.x_scnlen
.l
= (S_GET_VALUE (symbol_get_tc (sym
)->next
)
6588 - S_GET_VALUE (sym
));
6590 a
->x_csect
.x_smtyp
= (symbol_get_tc (sym
)->align
<< 3) | XTY_SD
;
6592 else if (S_GET_SEGMENT (sym
) == bss_section
)
6594 /* This is a common symbol. */
6595 a
->x_csect
.x_scnlen
.l
= symbol_get_frag (sym
)->fr_offset
;
6596 a
->x_csect
.x_smtyp
= (symbol_get_tc (sym
)->align
<< 3) | XTY_CM
;
6597 if (S_IS_EXTERNAL (sym
))
6598 symbol_get_tc (sym
)->symbol_class
= XMC_RW
;
6600 symbol_get_tc (sym
)->symbol_class
= XMC_BS
;
6602 else if (S_GET_SEGMENT (sym
) == absolute_section
)
6604 /* This is an absolute symbol. The csect will be created by
6605 ppc_adjust_symtab. */
6607 a
->x_csect
.x_smtyp
= XTY_LD
;
6608 if (symbol_get_tc (sym
)->symbol_class
== -1)
6609 symbol_get_tc (sym
)->symbol_class
= XMC_XO
;
6611 else if (! S_IS_DEFINED (sym
))
6613 /* This is an external symbol. */
6614 a
->x_csect
.x_scnlen
.l
= 0;
6615 a
->x_csect
.x_smtyp
= XTY_ER
;
6617 else if (symbol_get_tc (sym
)->symbol_class
== XMC_TC
)
6621 /* This is a TOC definition. x_scnlen is the size of the
6623 next
= symbol_next (sym
);
6624 while (symbol_get_tc (next
)->symbol_class
== XMC_TC0
)
6625 next
= symbol_next (next
);
6626 if (next
== (symbolS
*) NULL
6627 || symbol_get_tc (next
)->symbol_class
!= XMC_TC
)
6629 if (ppc_after_toc_frag
== (fragS
*) NULL
)
6630 a
->x_csect
.x_scnlen
.l
= (bfd_section_size (data_section
)
6631 - S_GET_VALUE (sym
));
6633 a
->x_csect
.x_scnlen
.l
= (ppc_after_toc_frag
->fr_address
6634 - S_GET_VALUE (sym
));
6638 resolve_symbol_value (next
);
6639 a
->x_csect
.x_scnlen
.l
= (S_GET_VALUE (next
)
6640 - S_GET_VALUE (sym
));
6642 a
->x_csect
.x_smtyp
= (2 << 3) | XTY_SD
;
6648 /* This is a normal symbol definition. x_scnlen is the
6649 symbol index of the containing csect. */
6650 if (S_GET_SEGMENT (sym
) == text_section
)
6651 csect
= ppc_text_csects
;
6652 else if (S_GET_SEGMENT (sym
) == data_section
)
6653 csect
= ppc_data_csects
;
6657 /* Skip the initial dummy symbol. */
6658 csect
= symbol_get_tc (csect
)->next
;
6660 if (csect
== (symbolS
*) NULL
)
6662 as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym
));
6663 a
->x_csect
.x_scnlen
.l
= 0;
6667 while (symbol_get_tc (csect
)->next
!= (symbolS
*) NULL
)
6669 resolve_symbol_value (symbol_get_tc (csect
)->next
);
6670 if (S_GET_VALUE (symbol_get_tc (csect
)->next
)
6671 > S_GET_VALUE (sym
))
6673 csect
= symbol_get_tc (csect
)->next
;
6676 a
->x_csect
.x_scnlen
.p
=
6677 coffsymbol (symbol_get_bfdsym (csect
))->native
;
6678 coffsymbol (symbol_get_bfdsym (sym
))->native
[i
+ 1].fix_scnlen
=
6681 a
->x_csect
.x_smtyp
= XTY_LD
;
6684 a
->x_csect
.x_parmhash
= 0;
6685 a
->x_csect
.x_snhash
= 0;
6686 if (symbol_get_tc (sym
)->symbol_class
== -1)
6687 a
->x_csect
.x_smclas
= XMC_PR
;
6689 a
->x_csect
.x_smclas
= symbol_get_tc (sym
)->symbol_class
;
6690 a
->x_csect
.x_stab
= 0;
6691 a
->x_csect
.x_snstab
= 0;
6693 /* Don't let the COFF backend resort these symbols. */
6694 symbol_get_bfdsym (sym
)->flags
|= BSF_NOT_AT_END
;
6696 else if (S_GET_STORAGE_CLASS (sym
) == C_BSTAT
)
6698 /* We want the value to be the symbol index of the referenced
6699 csect symbol. BFD will do that for us if we set the right
6701 asymbol
*bsym
= symbol_get_bfdsym (symbol_get_tc (sym
)->within
);
6702 combined_entry_type
*c
= coffsymbol (bsym
)->native
;
6704 S_SET_VALUE (sym
, (valueT
) (size_t) c
);
6705 coffsymbol (symbol_get_bfdsym (sym
))->native
->fix_value
= 1;
6707 else if (S_GET_STORAGE_CLASS (sym
) == C_STSYM
)
6712 block
= symbol_get_tc (sym
)->within
;
6715 /* The value is the offset from the enclosing csect. */
6718 csect
= symbol_get_tc (block
)->within
;
6719 resolve_symbol_value (csect
);
6720 base
= S_GET_VALUE (csect
);
6725 S_SET_VALUE (sym
, S_GET_VALUE (sym
) - base
);
6727 else if (S_GET_STORAGE_CLASS (sym
) == C_BINCL
6728 || S_GET_STORAGE_CLASS (sym
) == C_EINCL
)
6730 /* We want the value to be a file offset into the line numbers.
6731 BFD will do that for us if we set the right flags. We have
6732 already set the value correctly. */
6733 coffsymbol (symbol_get_bfdsym (sym
))->native
->fix_line
= 1;
6739 /* Adjust the symbol table. This creates csect symbols for all
6740 absolute symbols. */
6743 ppc_adjust_symtab (void)
6750 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
6754 union internal_auxent
*a
;
6756 if (S_GET_SEGMENT (sym
) != absolute_section
)
6759 csect
= symbol_create (".abs[XO]", absolute_section
,
6760 S_GET_VALUE (sym
), &zero_address_frag
);
6761 symbol_get_bfdsym (csect
)->value
= S_GET_VALUE (sym
);
6762 S_SET_STORAGE_CLASS (csect
, C_HIDEXT
);
6763 i
= S_GET_NUMBER_AUXILIARY (csect
);
6764 S_SET_NUMBER_AUXILIARY (csect
, i
+ 1);
6765 a
= &coffsymbol (symbol_get_bfdsym (csect
))->native
[i
+ 1].u
.auxent
;
6766 a
->x_csect
.x_scnlen
.l
= 0;
6767 a
->x_csect
.x_smtyp
= XTY_SD
;
6768 a
->x_csect
.x_parmhash
= 0;
6769 a
->x_csect
.x_snhash
= 0;
6770 a
->x_csect
.x_smclas
= XMC_XO
;
6771 a
->x_csect
.x_stab
= 0;
6772 a
->x_csect
.x_snstab
= 0;
6774 symbol_insert (csect
, sym
, &symbol_rootP
, &symbol_lastP
);
6776 i
= S_GET_NUMBER_AUXILIARY (sym
);
6777 a
= &coffsymbol (symbol_get_bfdsym (sym
))->native
[i
].u
.auxent
;
6778 a
->x_csect
.x_scnlen
.p
= coffsymbol (symbol_get_bfdsym (csect
))->native
;
6779 coffsymbol (symbol_get_bfdsym (sym
))->native
[i
].fix_scnlen
= 1;
6782 ppc_saw_abs
= FALSE
;
6785 /* Set the VMA for a section. This is called on all the sections in
6789 ppc_frob_section (asection
*sec
)
6791 static bfd_vma vma
= 0;
6793 /* Dwarf sections start at 0. */
6794 if (bfd_section_flags (sec
) & SEC_DEBUGGING
)
6797 vma
= md_section_align (sec
, vma
);
6798 bfd_set_section_vma (sec
, vma
);
6799 vma
+= bfd_section_size (sec
);
6802 #endif /* OBJ_XCOFF */
6805 md_atof (int type
, char *litp
, int *sizep
)
6807 return ieee_md_atof (type
, litp
, sizep
, target_big_endian
);
6810 /* Write a value out to the object file, using the appropriate
6814 md_number_to_chars (char *buf
, valueT val
, int n
)
6816 if (target_big_endian
)
6817 number_to_chars_bigendian (buf
, val
, n
);
6819 number_to_chars_littleendian (buf
, val
, n
);
6822 /* Align a section (I don't know why this is machine dependent). */
6825 md_section_align (asection
*seg ATTRIBUTE_UNUSED
, valueT addr
)
6830 int align
= bfd_section_alignment (seg
);
6832 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
6836 /* We don't have any form of relaxing. */
6839 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
6840 asection
*seg ATTRIBUTE_UNUSED
)
6846 /* Convert a machine dependent frag. We never generate these. */
6849 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
6850 asection
*sec ATTRIBUTE_UNUSED
,
6851 fragS
*fragp ATTRIBUTE_UNUSED
)
6856 /* We have no need to default values of symbols. */
6859 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
6864 /* Functions concerning relocs. */
6866 /* The location from which a PC relative jump should be calculated,
6867 given a PC relative reloc. */
6870 md_pcrel_from_section (fixS
*fixp
, segT sec ATTRIBUTE_UNUSED
)
6872 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6877 /* This is called to see whether a fixup should be adjusted to use a
6878 section symbol. We take the opportunity to change a fixup against
6879 a symbol in the TOC subsegment into a reloc against the
6880 corresponding .tc symbol. */
6883 ppc_fix_adjustable (fixS
*fix
)
6885 valueT val
= resolve_symbol_value (fix
->fx_addsy
);
6886 segT symseg
= S_GET_SEGMENT (fix
->fx_addsy
);
6887 TC_SYMFIELD_TYPE
*tc
;
6889 if (symseg
== absolute_section
)
6892 /* Always adjust symbols in debugging sections. */
6893 if (bfd_section_flags (symseg
) & SEC_DEBUGGING
)
6896 if (ppc_toc_csect
!= (symbolS
*) NULL
6897 && fix
->fx_addsy
!= ppc_toc_csect
6898 && symseg
== data_section
6899 && val
>= ppc_toc_frag
->fr_address
6900 && (ppc_after_toc_frag
== (fragS
*) NULL
6901 || val
< ppc_after_toc_frag
->fr_address
))
6905 for (sy
= symbol_next (ppc_toc_csect
);
6906 sy
!= (symbolS
*) NULL
;
6907 sy
= symbol_next (sy
))
6909 TC_SYMFIELD_TYPE
*sy_tc
= symbol_get_tc (sy
);
6911 if (sy_tc
->symbol_class
== XMC_TC0
)
6913 if (sy_tc
->symbol_class
!= XMC_TC
)
6915 if (val
== resolve_symbol_value (sy
))
6918 fix
->fx_addnumber
= val
- ppc_toc_frag
->fr_address
;
6923 as_bad_where (fix
->fx_file
, fix
->fx_line
,
6924 _("symbol in .toc does not match any .tc"));
6927 /* Possibly adjust the reloc to be against the csect. */
6928 tc
= symbol_get_tc (fix
->fx_addsy
);
6930 && tc
->symbol_class
!= XMC_TC0
6931 && tc
->symbol_class
!= XMC_TC
6932 && symseg
!= bss_section
6933 /* Don't adjust if this is a reloc in the toc section. */
6934 && (symseg
!= data_section
6935 || ppc_toc_csect
== NULL
6936 || val
< ppc_toc_frag
->fr_address
6937 || (ppc_after_toc_frag
!= NULL
6938 && val
>= ppc_after_toc_frag
->fr_address
)))
6940 symbolS
*csect
= tc
->within
;
6942 /* If the symbol was not declared by a label (eg: a section symbol),
6943 use the section instead of the csect. This doesn't happen in
6944 normal AIX assembly code. */
6946 csect
= seg_info (symseg
)->sym
;
6948 fix
->fx_offset
+= val
- symbol_get_frag (csect
)->fr_address
;
6949 fix
->fx_addsy
= csect
;
6954 /* Adjust a reloc against a .lcomm symbol to be against the base
6956 if (symseg
== bss_section
6957 && ! S_IS_EXTERNAL (fix
->fx_addsy
))
6959 symbolS
*sy
= symbol_get_frag (fix
->fx_addsy
)->fr_symbol
;
6961 fix
->fx_offset
+= val
- resolve_symbol_value (sy
);
6968 /* A reloc from one csect to another must be kept. The assembler
6969 will, of course, keep relocs between sections, and it will keep
6970 absolute relocs, but we need to force it to keep PC relative relocs
6971 between two csects in the same section. */
6974 ppc_force_relocation (fixS
*fix
)
6976 /* At this point fix->fx_addsy should already have been converted to
6977 a csect symbol. If the csect does not include the fragment, then
6978 we need to force the relocation. */
6980 && fix
->fx_addsy
!= NULL
6981 && symbol_get_tc (fix
->fx_addsy
)->subseg
!= 0
6982 && ((symbol_get_frag (fix
->fx_addsy
)->fr_address
6983 > fix
->fx_frag
->fr_address
)
6984 || (symbol_get_tc (fix
->fx_addsy
)->next
!= NULL
6985 && (symbol_get_frag (symbol_get_tc (fix
->fx_addsy
)->next
)->fr_address
6986 <= fix
->fx_frag
->fr_address
))))
6989 return generic_force_reloc (fix
);
6991 #endif /* OBJ_XCOFF */
6994 /* If this function returns non-zero, it guarantees that a relocation
6995 will be emitted for a fixup. */
6998 ppc_force_relocation (fixS
*fix
)
7000 /* Branch prediction relocations must force a relocation, as must
7001 the vtable description relocs. */
7002 switch (fix
->fx_r_type
)
7004 case BFD_RELOC_PPC_B16_BRTAKEN
:
7005 case BFD_RELOC_PPC_B16_BRNTAKEN
:
7006 case BFD_RELOC_PPC_BA16_BRTAKEN
:
7007 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
7008 case BFD_RELOC_24_PLT_PCREL
:
7009 case BFD_RELOC_PPC64_TOC
:
7011 case BFD_RELOC_PPC_B26
:
7012 case BFD_RELOC_PPC_BA26
:
7013 case BFD_RELOC_PPC_B16
:
7014 case BFD_RELOC_PPC_BA16
:
7015 case BFD_RELOC_PPC64_REL24_NOTOC
:
7016 /* All branch fixups targeting a localentry symbol must
7017 force a relocation. */
7020 asymbol
*bfdsym
= symbol_get_bfdsym (fix
->fx_addsy
);
7021 elf_symbol_type
*elfsym
7022 = elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
7023 gas_assert (elfsym
);
7024 if ((STO_PPC64_LOCAL_MASK
& elfsym
->internal_elf_sym
.st_other
) != 0)
7032 if (fix
->fx_r_type
>= BFD_RELOC_PPC_TLS
7033 && fix
->fx_r_type
<= BFD_RELOC_PPC64_TLS_PCREL
)
7036 return generic_force_reloc (fix
);
7040 ppc_fix_adjustable (fixS
*fix
)
7042 switch (fix
->fx_r_type
)
7044 /* All branch fixups targeting a localentry symbol must
7045 continue using the symbol. */
7046 case BFD_RELOC_PPC_B26
:
7047 case BFD_RELOC_PPC_BA26
:
7048 case BFD_RELOC_PPC_B16
:
7049 case BFD_RELOC_PPC_BA16
:
7050 case BFD_RELOC_PPC_B16_BRTAKEN
:
7051 case BFD_RELOC_PPC_B16_BRNTAKEN
:
7052 case BFD_RELOC_PPC_BA16_BRTAKEN
:
7053 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
7054 case BFD_RELOC_PPC64_REL24_NOTOC
:
7057 asymbol
*bfdsym
= symbol_get_bfdsym (fix
->fx_addsy
);
7058 elf_symbol_type
*elfsym
7059 = elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
7060 gas_assert (elfsym
);
7061 if ((STO_PPC64_LOCAL_MASK
& elfsym
->internal_elf_sym
.st_other
) != 0)
7069 return (fix
->fx_r_type
!= BFD_RELOC_16_GOTOFF
7070 && fix
->fx_r_type
!= BFD_RELOC_LO16_GOTOFF
7071 && fix
->fx_r_type
!= BFD_RELOC_HI16_GOTOFF
7072 && fix
->fx_r_type
!= BFD_RELOC_HI16_S_GOTOFF
7073 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT16_DS
7074 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT16_LO_DS
7075 && fix
->fx_r_type
!= BFD_RELOC_16_GOT_PCREL
7076 && fix
->fx_r_type
!= BFD_RELOC_32_GOTOFF
7077 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT_PCREL34
7078 && fix
->fx_r_type
!= BFD_RELOC_24_PLT_PCREL
7079 && fix
->fx_r_type
!= BFD_RELOC_32_PLTOFF
7080 && fix
->fx_r_type
!= BFD_RELOC_32_PLT_PCREL
7081 && fix
->fx_r_type
!= BFD_RELOC_LO16_PLTOFF
7082 && fix
->fx_r_type
!= BFD_RELOC_HI16_PLTOFF
7083 && fix
->fx_r_type
!= BFD_RELOC_HI16_S_PLTOFF
7084 && fix
->fx_r_type
!= BFD_RELOC_64_PLTOFF
7085 && fix
->fx_r_type
!= BFD_RELOC_64_PLT_PCREL
7086 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLT16_LO_DS
7087 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLT_PCREL34
7088 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16
7089 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_LO
7090 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_HI
7091 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_HA
7092 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_DS
7093 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_LO_DS
7094 && fix
->fx_r_type
!= BFD_RELOC_GPREL16
7095 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_LO16A
7096 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_HI16A
7097 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_HA16A
7098 && fix
->fx_r_type
!= BFD_RELOC_VTABLE_INHERIT
7099 && fix
->fx_r_type
!= BFD_RELOC_VTABLE_ENTRY
7100 && !(fix
->fx_r_type
>= BFD_RELOC_PPC_TLS
7101 && fix
->fx_r_type
<= BFD_RELOC_PPC64_TLS_PCREL
));
7106 ppc_frag_check (struct frag
*fragP
)
7108 if ((fragP
->fr_address
& fragP
->insn_addr
) != 0)
7109 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7110 _("instruction address is not a multiple of %d"),
7111 fragP
->insn_addr
+ 1);
7114 /* rs_align_code frag handling. */
7116 enum ppc_nop_encoding_for_rs_align_code
7125 ppc_nop_select (void)
7127 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
7129 if ((ppc_cpu
& (PPC_OPCODE_POWER9
| PPC_OPCODE_E500MC
)) == 0)
7131 if ((ppc_cpu
& PPC_OPCODE_POWER7
) != 0)
7132 return PPC_NOP_GROUP_P7
;
7133 if ((ppc_cpu
& PPC_OPCODE_POWER6
) != 0)
7134 return PPC_NOP_GROUP_P6
;
7136 return PPC_NOP_VANILLA
;
7140 ppc_handle_align (struct frag
*fragP
)
7142 valueT count
= (fragP
->fr_next
->fr_address
7143 - (fragP
->fr_address
+ fragP
->fr_fix
));
7144 char *dest
= fragP
->fr_literal
+ fragP
->fr_fix
;
7145 enum ppc_nop_encoding_for_rs_align_code nop_select
= *dest
& 0xff;
7147 /* Pad with zeros if not inserting a whole number of instructions.
7148 We could pad with zeros up to an instruction boundary then follow
7149 with nops but odd counts indicate data in an executable section
7150 so padding with zeros is most appropriate. */
7152 || (nop_select
== PPC_NOP_VLE
? (count
& 1) != 0 : (count
& 3) != 0))
7158 if (nop_select
== PPC_NOP_VLE
)
7162 md_number_to_chars (dest
, 0x4400, 2);
7168 if (count
> 4 * nop_limit
&& count
< 0x2000000)
7172 /* Make a branch, then follow with nops. Insert another
7173 frag to handle the nops. */
7174 md_number_to_chars (dest
, 0x48000000 + count
, 4);
7179 rest
= xmalloc (SIZEOF_STRUCT_FRAG
+ 4);
7180 memcpy (rest
, fragP
, SIZEOF_STRUCT_FRAG
);
7181 fragP
->fr_next
= rest
;
7183 rest
->fr_address
+= rest
->fr_fix
+ 4;
7185 /* If we leave the next frag as rs_align_code we'll come here
7186 again, resulting in a bunch of branches rather than a
7187 branch followed by nops. */
7188 rest
->fr_type
= rs_align
;
7189 dest
= rest
->fr_literal
;
7192 md_number_to_chars (dest
, 0x60000000, 4);
7194 if (nop_select
>= PPC_NOP_GROUP_P6
)
7196 /* For power6, power7, and power8, we want the last nop to
7197 be a group terminating one. Do this by inserting an
7198 rs_fill frag immediately after this one, with its address
7199 set to the last nop location. This will automatically
7200 reduce the number of nops in the current frag by one. */
7203 struct frag
*group_nop
= xmalloc (SIZEOF_STRUCT_FRAG
+ 4);
7205 memcpy (group_nop
, fragP
, SIZEOF_STRUCT_FRAG
);
7206 group_nop
->fr_address
= group_nop
->fr_next
->fr_address
- 4;
7207 group_nop
->fr_fix
= 0;
7208 group_nop
->fr_offset
= 1;
7209 group_nop
->fr_type
= rs_fill
;
7210 fragP
->fr_next
= group_nop
;
7211 dest
= group_nop
->fr_literal
;
7214 if (nop_select
== PPC_NOP_GROUP_P6
)
7215 /* power6 group terminating nop: "ori 1,1,0". */
7216 md_number_to_chars (dest
, 0x60210000, 4);
7218 /* power7/power8 group terminating nop: "ori 2,2,0". */
7219 md_number_to_chars (dest
, 0x60420000, 4);
7224 /* Apply a fixup to the object code. This is called for all the
7225 fixups we generated by the calls to fix_new_exp, above. */
7228 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
7230 valueT value
= * valP
;
7232 const struct powerpc_operand
*operand
;
7235 if (fixP
->fx_addsy
!= NULL
)
7237 /* Hack around bfd_install_relocation brain damage. */
7239 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
7241 if (fixP
->fx_addsy
== abs_section_sym
)
7247 /* FIXME FIXME FIXME: The value we are passed in *valP includes
7248 the symbol values. If we are doing this relocation the code in
7249 write.c is going to call bfd_install_relocation, which is also
7250 going to use the symbol value. That means that if the reloc is
7251 fully resolved we want to use *valP since bfd_install_relocation is
7253 However, if the reloc is not fully resolved we do not want to
7254 use *valP, and must use fx_offset instead. If the relocation
7255 is PC-relative, we then need to re-apply md_pcrel_from_section
7256 to this new relocation value. */
7257 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
7262 value
= fixP
->fx_offset
;
7264 value
-= md_pcrel_from_section (fixP
, seg
);
7268 /* We are only able to convert some relocs to pc-relative. */
7271 switch (fixP
->fx_r_type
)
7274 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7278 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7282 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7285 case BFD_RELOC_LO16
:
7286 fixP
->fx_r_type
= BFD_RELOC_LO16_PCREL
;
7289 case BFD_RELOC_HI16
:
7290 fixP
->fx_r_type
= BFD_RELOC_HI16_PCREL
;
7293 case BFD_RELOC_HI16_S
:
7294 fixP
->fx_r_type
= BFD_RELOC_HI16_S_PCREL
;
7297 case BFD_RELOC_PPC64_ADDR16_HIGH
:
7298 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGH
;
7301 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
7302 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHA
;
7305 case BFD_RELOC_PPC64_HIGHER
:
7306 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHER
;
7309 case BFD_RELOC_PPC64_HIGHER_S
:
7310 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHERA
;
7313 case BFD_RELOC_PPC64_HIGHEST
:
7314 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHEST
;
7317 case BFD_RELOC_PPC64_HIGHEST_S
:
7318 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHESTA
;
7321 case BFD_RELOC_PPC64_ADDR16_HIGHER34
:
7322 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHER34
;
7325 case BFD_RELOC_PPC64_ADDR16_HIGHERA34
:
7326 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHERA34
;
7329 case BFD_RELOC_PPC64_ADDR16_HIGHEST34
:
7330 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHEST34
;
7333 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34
:
7334 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHESTA34
;
7337 case BFD_RELOC_PPC_16DX_HA
:
7338 fixP
->fx_r_type
= BFD_RELOC_PPC_REL16DX_HA
;
7341 case BFD_RELOC_PPC64_D34
:
7342 fixP
->fx_r_type
= BFD_RELOC_PPC64_PCREL34
;
7345 case BFD_RELOC_PPC64_D28
:
7346 fixP
->fx_r_type
= BFD_RELOC_PPC64_PCREL28
;
7353 else if (!fixP
->fx_done
7354 && fixP
->fx_r_type
== BFD_RELOC_PPC_16DX_HA
)
7356 /* addpcis is relative to next insn address. */
7358 fixP
->fx_r_type
= BFD_RELOC_PPC_REL16DX_HA
;
7363 if (fixP
->fx_pcrel_adjust
!= 0)
7365 /* This is a fixup on an instruction. */
7366 int opindex
= fixP
->fx_pcrel_adjust
& 0xff;
7368 operand
= &powerpc_operands
[opindex
];
7370 /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol
7371 does not generate a reloc. It uses the offset of `sym' within its
7372 csect. Other usages, such as `.long sym', generate relocs. This
7373 is the documented behaviour of non-TOC symbols. */
7374 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0
7375 && (operand
->bitm
& 0xfff0) == 0xfff0
7376 && operand
->shift
== 0
7377 && (operand
->insert
== NULL
|| ppc_obj64
)
7378 && fixP
->fx_addsy
!= NULL
7379 && symbol_get_tc (fixP
->fx_addsy
)->subseg
!= 0
7380 && symbol_get_tc (fixP
->fx_addsy
)->symbol_class
!= XMC_TC
7381 && symbol_get_tc (fixP
->fx_addsy
)->symbol_class
!= XMC_TC0
7382 && S_GET_SEGMENT (fixP
->fx_addsy
) != bss_section
)
7384 value
= fixP
->fx_offset
;
7388 /* During parsing of instructions, a TOC16 reloc is generated for
7389 instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined
7390 in the toc. But at parse time, SYM may be not yet defined, so
7391 check again here. */
7392 if (fixP
->fx_r_type
== BFD_RELOC_16
7393 && fixP
->fx_addsy
!= NULL
7394 && ppc_is_toc_sym (fixP
->fx_addsy
))
7395 fixP
->fx_r_type
= BFD_RELOC_PPC_TOC16
;
7399 /* Calculate value to be stored in field. */
7401 switch (fixP
->fx_r_type
)
7404 case BFD_RELOC_PPC64_ADDR16_LO_DS
:
7405 case BFD_RELOC_PPC_VLE_LO16A
:
7406 case BFD_RELOC_PPC_VLE_LO16D
:
7408 case BFD_RELOC_LO16
:
7409 case BFD_RELOC_LO16_PCREL
:
7410 fieldval
= value
& 0xffff;
7412 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
7413 fieldval
= SEX16 (fieldval
);
7414 fixP
->fx_no_overflow
= 1;
7417 case BFD_RELOC_HI16
:
7418 case BFD_RELOC_HI16_PCREL
:
7420 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
7422 fieldval
= value
>> 16;
7423 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
7425 valueT sign
= (((valueT
) -1 >> 16) + 1) >> 1;
7426 fieldval
= ((valueT
) fieldval
^ sign
) - sign
;
7432 case BFD_RELOC_PPC_VLE_HI16A
:
7433 case BFD_RELOC_PPC_VLE_HI16D
:
7434 case BFD_RELOC_PPC64_ADDR16_HIGH
:
7436 fieldval
= PPC_HI (value
);
7437 goto sign_extend_16
;
7439 case BFD_RELOC_HI16_S
:
7440 case BFD_RELOC_HI16_S_PCREL
:
7441 case BFD_RELOC_PPC_16DX_HA
:
7442 case BFD_RELOC_PPC_REL16DX_HA
:
7444 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
7446 fieldval
= (value
+ 0x8000) >> 16;
7447 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
7449 valueT sign
= (((valueT
) -1 >> 16) + 1) >> 1;
7450 fieldval
= ((valueT
) fieldval
^ sign
) - sign
;
7456 case BFD_RELOC_PPC_VLE_HA16A
:
7457 case BFD_RELOC_PPC_VLE_HA16D
:
7458 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
7460 fieldval
= PPC_HA (value
);
7461 goto sign_extend_16
;
7464 case BFD_RELOC_PPC64_HIGHER
:
7465 fieldval
= PPC_HIGHER (value
);
7466 goto sign_extend_16
;
7468 case BFD_RELOC_PPC64_HIGHER_S
:
7469 fieldval
= PPC_HIGHERA (value
);
7470 goto sign_extend_16
;
7472 case BFD_RELOC_PPC64_HIGHEST
:
7473 fieldval
= PPC_HIGHEST (value
);
7474 goto sign_extend_16
;
7476 case BFD_RELOC_PPC64_HIGHEST_S
:
7477 fieldval
= PPC_HIGHESTA (value
);
7478 goto sign_extend_16
;
7485 if (operand
!= NULL
)
7487 /* Handle relocs in an insn. */
7488 switch (fixP
->fx_r_type
)
7491 /* The following relocs can't be calculated by the assembler.
7492 Leave the field zero. */
7493 case BFD_RELOC_PPC_TPREL16
:
7494 case BFD_RELOC_PPC_TPREL16_LO
:
7495 case BFD_RELOC_PPC_TPREL16_HI
:
7496 case BFD_RELOC_PPC_TPREL16_HA
:
7497 case BFD_RELOC_PPC_DTPREL16
:
7498 case BFD_RELOC_PPC_DTPREL16_LO
:
7499 case BFD_RELOC_PPC_DTPREL16_HI
:
7500 case BFD_RELOC_PPC_DTPREL16_HA
:
7501 case BFD_RELOC_PPC_GOT_TLSGD16
:
7502 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
7503 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
7504 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
7505 case BFD_RELOC_PPC_GOT_TLSLD16
:
7506 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
7507 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
7508 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
7509 case BFD_RELOC_PPC_GOT_TPREL16
:
7510 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
7511 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
7512 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
7513 case BFD_RELOC_PPC_GOT_DTPREL16
:
7514 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
7515 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
7516 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
7517 case BFD_RELOC_PPC64_TPREL16_DS
:
7518 case BFD_RELOC_PPC64_TPREL16_LO_DS
:
7519 case BFD_RELOC_PPC64_TPREL16_HIGH
:
7520 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
7521 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
7522 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
7523 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
7524 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
7525 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
7526 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
7527 case BFD_RELOC_PPC64_DTPREL16_DS
:
7528 case BFD_RELOC_PPC64_DTPREL16_LO_DS
:
7529 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
7530 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
7531 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
7532 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
7533 case BFD_RELOC_PPC64_TPREL34
:
7534 case BFD_RELOC_PPC64_DTPREL34
:
7535 case BFD_RELOC_PPC64_GOT_TLSGD34
:
7536 case BFD_RELOC_PPC64_GOT_TLSLD34
:
7537 case BFD_RELOC_PPC64_GOT_TPREL34
:
7538 case BFD_RELOC_PPC64_GOT_DTPREL34
:
7539 gas_assert (fixP
->fx_addsy
!= NULL
);
7540 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7544 /* These also should leave the field zero for the same
7545 reason. Note that older versions of gas wrote values
7546 here. If we want to go back to the old behaviour, then
7547 all _LO and _LO_DS cases will need to be treated like
7548 BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */
7549 case BFD_RELOC_16_GOTOFF
:
7550 case BFD_RELOC_LO16_GOTOFF
:
7551 case BFD_RELOC_HI16_GOTOFF
:
7552 case BFD_RELOC_HI16_S_GOTOFF
:
7553 case BFD_RELOC_LO16_PLTOFF
:
7554 case BFD_RELOC_HI16_PLTOFF
:
7555 case BFD_RELOC_HI16_S_PLTOFF
:
7556 case BFD_RELOC_GPREL16
:
7557 case BFD_RELOC_16_BASEREL
:
7558 case BFD_RELOC_LO16_BASEREL
:
7559 case BFD_RELOC_HI16_BASEREL
:
7560 case BFD_RELOC_HI16_S_BASEREL
:
7561 case BFD_RELOC_PPC_TOC16
:
7562 case BFD_RELOC_PPC64_TOC16_LO
:
7563 case BFD_RELOC_PPC64_TOC16_HI
:
7564 case BFD_RELOC_PPC64_TOC16_HA
:
7565 case BFD_RELOC_PPC64_PLTGOT16
:
7566 case BFD_RELOC_PPC64_PLTGOT16_LO
:
7567 case BFD_RELOC_PPC64_PLTGOT16_HI
:
7568 case BFD_RELOC_PPC64_PLTGOT16_HA
:
7569 case BFD_RELOC_PPC64_GOT16_DS
:
7570 case BFD_RELOC_PPC64_GOT16_LO_DS
:
7571 case BFD_RELOC_PPC64_PLT16_LO_DS
:
7572 case BFD_RELOC_PPC64_SECTOFF_DS
:
7573 case BFD_RELOC_PPC64_SECTOFF_LO_DS
:
7574 case BFD_RELOC_PPC64_TOC16_DS
:
7575 case BFD_RELOC_PPC64_TOC16_LO_DS
:
7576 case BFD_RELOC_PPC64_PLTGOT16_DS
:
7577 case BFD_RELOC_PPC64_PLTGOT16_LO_DS
:
7578 case BFD_RELOC_PPC_EMB_NADDR16
:
7579 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
7580 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
7581 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
7582 case BFD_RELOC_PPC_EMB_SDAI16
:
7583 case BFD_RELOC_PPC_EMB_SDA2I16
:
7584 case BFD_RELOC_PPC_EMB_SDA2REL
:
7585 case BFD_RELOC_PPC_EMB_SDA21
:
7586 case BFD_RELOC_PPC_EMB_MRKREF
:
7587 case BFD_RELOC_PPC_EMB_RELSEC16
:
7588 case BFD_RELOC_PPC_EMB_RELST_LO
:
7589 case BFD_RELOC_PPC_EMB_RELST_HI
:
7590 case BFD_RELOC_PPC_EMB_RELST_HA
:
7591 case BFD_RELOC_PPC_EMB_BIT_FLD
:
7592 case BFD_RELOC_PPC_EMB_RELSDA
:
7593 case BFD_RELOC_PPC_VLE_SDA21
:
7594 case BFD_RELOC_PPC_VLE_SDA21_LO
:
7595 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
7596 case BFD_RELOC_PPC_VLE_SDAREL_LO16D
:
7597 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
7598 case BFD_RELOC_PPC_VLE_SDAREL_HI16D
:
7599 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
7600 case BFD_RELOC_PPC_VLE_SDAREL_HA16D
:
7601 case BFD_RELOC_PPC64_GOT_PCREL34
:
7602 case BFD_RELOC_PPC64_PLT_PCREL34
:
7603 gas_assert (fixP
->fx_addsy
!= NULL
);
7606 case BFD_RELOC_PPC_TLS
:
7607 case BFD_RELOC_PPC_TLSGD
:
7608 case BFD_RELOC_PPC_TLSLD
:
7609 case BFD_RELOC_PPC64_TLS_PCREL
:
7615 case BFD_RELOC_PPC_B16
:
7616 /* Adjust the offset to the instruction boundary. */
7621 case BFD_RELOC_VTABLE_INHERIT
:
7622 case BFD_RELOC_VTABLE_ENTRY
:
7623 case BFD_RELOC_PPC_DTPMOD
:
7624 case BFD_RELOC_PPC_TPREL
:
7625 case BFD_RELOC_PPC_DTPREL
:
7626 case BFD_RELOC_PPC_COPY
:
7627 case BFD_RELOC_PPC_GLOB_DAT
:
7628 case BFD_RELOC_32_PLT_PCREL
:
7629 case BFD_RELOC_PPC_EMB_NADDR32
:
7630 case BFD_RELOC_PPC64_TOC
:
7631 case BFD_RELOC_CTOR
:
7633 case BFD_RELOC_32_PCREL
:
7636 case BFD_RELOC_64_PCREL
:
7637 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
7638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7639 _("%s unsupported as instruction fixup"),
7640 bfd_get_reloc_code_name (fixP
->fx_r_type
));
7649 /* powerpc uses RELA style relocs, so if emitting a reloc the field
7650 contents can stay at zero. */
7651 #define APPLY_RELOC fixP->fx_done
7653 #define APPLY_RELOC 1
7655 /* We need to call the insert function even when fieldval is
7656 zero if the insert function would translate that zero to a
7657 bit pattern other than all zeros. */
7658 if ((fieldval
!= 0 && APPLY_RELOC
) || operand
->insert
!= NULL
)
7661 unsigned char *where
;
7663 /* Fetch the instruction, insert the fully resolved operand
7664 value, and stuff the instruction back again. */
7665 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
7666 if (target_big_endian
)
7668 if (fixP
->fx_size
< 4)
7669 insn
= bfd_getb16 (where
);
7672 insn
= bfd_getb32 (where
);
7673 if (fixP
->fx_size
> 4)
7674 insn
= insn
<< 32 | bfd_getb32 (where
+ 4);
7679 if (fixP
->fx_size
< 4)
7680 insn
= bfd_getl16 (where
);
7683 insn
= bfd_getl32 (where
);
7684 if (fixP
->fx_size
> 4)
7685 insn
= insn
<< 32 | bfd_getl32 (where
+ 4);
7688 insn
= ppc_insert_operand (insn
, operand
, fieldval
,
7689 fixP
->tc_fix_data
.ppc_cpu
,
7690 fixP
->fx_file
, fixP
->fx_line
);
7691 if (target_big_endian
)
7693 if (fixP
->fx_size
< 4)
7694 bfd_putb16 (insn
, where
);
7697 if (fixP
->fx_size
> 4)
7699 bfd_putb32 (insn
, where
+ 4);
7702 bfd_putb32 (insn
, where
);
7707 if (fixP
->fx_size
< 4)
7708 bfd_putl16 (insn
, where
);
7711 if (fixP
->fx_size
> 4)
7713 bfd_putl32 (insn
, where
+ 4);
7716 bfd_putl32 (insn
, where
);
7722 /* Nothing else to do here. */
7725 gas_assert (fixP
->fx_addsy
!= NULL
);
7726 if (fixP
->fx_r_type
== BFD_RELOC_NONE
)
7731 /* Use expr_symbol_where to see if this is an expression
7733 if (expr_symbol_where (fixP
->fx_addsy
, &sfile
, &sline
))
7734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7735 _("unresolved expression that must be resolved"));
7737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
7738 _("unsupported relocation against %s"),
7739 S_GET_NAME (fixP
->fx_addsy
));
7746 /* Handle relocs in data. */
7747 switch (fixP
->fx_r_type
)
7749 case BFD_RELOC_VTABLE_INHERIT
:
7751 && !S_IS_DEFINED (fixP
->fx_addsy
)
7752 && !S_IS_WEAK (fixP
->fx_addsy
))
7753 S_SET_WEAK (fixP
->fx_addsy
);
7756 case BFD_RELOC_VTABLE_ENTRY
:
7761 /* These can appear with @l etc. in data. */
7762 case BFD_RELOC_LO16
:
7763 case BFD_RELOC_LO16_PCREL
:
7764 case BFD_RELOC_HI16
:
7765 case BFD_RELOC_HI16_PCREL
:
7766 case BFD_RELOC_HI16_S
:
7767 case BFD_RELOC_HI16_S_PCREL
:
7768 case BFD_RELOC_PPC64_HIGHER
:
7769 case BFD_RELOC_PPC64_HIGHER_S
:
7770 case BFD_RELOC_PPC64_HIGHEST
:
7771 case BFD_RELOC_PPC64_HIGHEST_S
:
7772 case BFD_RELOC_PPC64_ADDR16_HIGH
:
7773 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
7774 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
7777 case BFD_RELOC_PPC_DTPMOD
:
7778 case BFD_RELOC_PPC_TPREL
:
7779 case BFD_RELOC_PPC_DTPREL
:
7780 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7783 /* Just punt all of these to the linker. */
7784 case BFD_RELOC_PPC_B16_BRTAKEN
:
7785 case BFD_RELOC_PPC_B16_BRNTAKEN
:
7786 case BFD_RELOC_16_GOTOFF
:
7787 case BFD_RELOC_LO16_GOTOFF
:
7788 case BFD_RELOC_HI16_GOTOFF
:
7789 case BFD_RELOC_HI16_S_GOTOFF
:
7790 case BFD_RELOC_LO16_PLTOFF
:
7791 case BFD_RELOC_HI16_PLTOFF
:
7792 case BFD_RELOC_HI16_S_PLTOFF
:
7793 case BFD_RELOC_PPC_COPY
:
7794 case BFD_RELOC_PPC_GLOB_DAT
:
7795 case BFD_RELOC_16_BASEREL
:
7796 case BFD_RELOC_LO16_BASEREL
:
7797 case BFD_RELOC_HI16_BASEREL
:
7798 case BFD_RELOC_HI16_S_BASEREL
:
7799 case BFD_RELOC_PPC_TLS
:
7800 case BFD_RELOC_PPC_DTPREL16_LO
:
7801 case BFD_RELOC_PPC_DTPREL16_HI
:
7802 case BFD_RELOC_PPC_DTPREL16_HA
:
7803 case BFD_RELOC_PPC_TPREL16_LO
:
7804 case BFD_RELOC_PPC_TPREL16_HI
:
7805 case BFD_RELOC_PPC_TPREL16_HA
:
7806 case BFD_RELOC_PPC_GOT_TLSGD16
:
7807 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
7808 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
7809 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
7810 case BFD_RELOC_PPC_GOT_TLSLD16
:
7811 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
7812 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
7813 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
7814 case BFD_RELOC_PPC_GOT_DTPREL16
:
7815 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
7816 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
7817 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
7818 case BFD_RELOC_PPC_GOT_TPREL16
:
7819 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
7820 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
7821 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
7822 case BFD_RELOC_24_PLT_PCREL
:
7823 case BFD_RELOC_PPC_LOCAL24PC
:
7824 case BFD_RELOC_32_PLT_PCREL
:
7825 case BFD_RELOC_GPREL16
:
7826 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
7827 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
7828 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
7829 case BFD_RELOC_PPC_EMB_NADDR32
:
7830 case BFD_RELOC_PPC_EMB_NADDR16
:
7831 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
7832 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
7833 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
7834 case BFD_RELOC_PPC_EMB_SDAI16
:
7835 case BFD_RELOC_PPC_EMB_SDA2REL
:
7836 case BFD_RELOC_PPC_EMB_SDA2I16
:
7837 case BFD_RELOC_PPC_EMB_SDA21
:
7838 case BFD_RELOC_PPC_VLE_SDA21_LO
:
7839 case BFD_RELOC_PPC_EMB_MRKREF
:
7840 case BFD_RELOC_PPC_EMB_RELSEC16
:
7841 case BFD_RELOC_PPC_EMB_RELST_LO
:
7842 case BFD_RELOC_PPC_EMB_RELST_HI
:
7843 case BFD_RELOC_PPC_EMB_RELST_HA
:
7844 case BFD_RELOC_PPC_EMB_BIT_FLD
:
7845 case BFD_RELOC_PPC_EMB_RELSDA
:
7846 case BFD_RELOC_PPC64_TOC
:
7847 case BFD_RELOC_PPC_TOC16
:
7848 case BFD_RELOC_PPC64_TOC16_LO
:
7849 case BFD_RELOC_PPC64_TOC16_HI
:
7850 case BFD_RELOC_PPC64_TOC16_HA
:
7851 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
7852 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
7853 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
7854 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
7855 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
7856 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
7857 case BFD_RELOC_PPC64_TPREL16_HIGH
:
7858 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
7859 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
7860 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
7861 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
7862 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
7863 case BFD_RELOC_PPC64_TLS_PCREL
:
7869 case BFD_RELOC_NONE
:
7871 case BFD_RELOC_CTOR
:
7873 case BFD_RELOC_32_PCREL
:
7876 case BFD_RELOC_64_PCREL
:
7878 case BFD_RELOC_16_PCREL
:
7884 _("Gas failure, reloc value %d\n"), fixP
->fx_r_type
);
7889 if (fixP
->fx_size
&& APPLY_RELOC
)
7890 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
7891 fieldval
, fixP
->fx_size
);
7893 && (seg
->flags
& SEC_CODE
) != 0
7894 && fixP
->fx_size
== 4
7897 && (fixP
->fx_r_type
== BFD_RELOC_32
7898 || fixP
->fx_r_type
== BFD_RELOC_CTOR
7899 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
))
7900 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
7901 _("data in executable section"));
7905 ppc_elf_validate_fix (fixP
, seg
);
7906 fixP
->fx_addnumber
= value
;
7908 /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately
7909 from the section contents. If we are going to be emitting a reloc
7910 then the section contents are immaterial, so don't warn if they
7911 happen to overflow. Leave such warnings to ld. */
7914 fixP
->fx_no_overflow
= 1;
7916 /* Arrange to emit .TOC. as a normal symbol if used in anything
7917 but .TOC.@tocbase. */
7919 && fixP
->fx_r_type
!= BFD_RELOC_PPC64_TOC
7920 && fixP
->fx_addsy
!= NULL
7921 && strcmp (S_GET_NAME (fixP
->fx_addsy
), ".TOC.") == 0)
7922 symbol_get_bfdsym (fixP
->fx_addsy
)->flags
|= BSF_KEEP
;
7925 if (fixP
->fx_r_type
!= BFD_RELOC_PPC_TOC16
)
7926 fixP
->fx_addnumber
= 0;
7930 fixP
->fx_addnumber
= 0;
7932 /* We want to use the offset within the toc, not the actual VMA
7934 fixP
->fx_addnumber
= (- bfd_section_vma (S_GET_SEGMENT (fixP
->fx_addsy
))
7935 - S_GET_VALUE (ppc_toc_csect
));
7936 /* Set *valP to avoid errors. */
7943 /* Generate a reloc for a fixup. */
7946 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
7950 reloc
= XNEW (arelent
);
7952 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7953 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7954 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7955 /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */
7956 if (fixp
->fx_r_type
== BFD_RELOC_PPC64_TLS_PCREL
)
7958 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7959 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
7961 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7962 _("reloc %d not supported by object file format"),
7963 (int) fixp
->fx_r_type
);
7966 reloc
->addend
= fixp
->fx_addnumber
;
7972 ppc_cfi_frame_initial_instructions (void)
7974 cfi_add_CFA_def_cfa (1, 0);
7978 tc_ppc_regname_to_dw2regnum (char *regname
)
7980 unsigned int regnum
= -1;
7984 static struct { const char *name
; int dw2regnum
; } regnames
[] =
7986 { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 },
7987 { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 },
7988 { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 },
7989 { "spe_acc", 111 }, { "spefscr", 112 }
7992 for (i
= 0; i
< ARRAY_SIZE (regnames
); ++i
)
7993 if (strcmp (regnames
[i
].name
, regname
) == 0)
7994 return regnames
[i
].dw2regnum
;
7996 if (regname
[0] == 'r' || regname
[0] == 'f' || regname
[0] == 'v')
7998 p
= regname
+ 1 + (regname
[1] == '.');
7999 regnum
= strtoul (p
, &q
, 10);
8000 if (p
== q
|| *q
|| regnum
>= 32)
8002 if (regname
[0] == 'f')
8004 else if (regname
[0] == 'v')
8007 else if (regname
[0] == 'c' && regname
[1] == 'r')
8009 p
= regname
+ 2 + (regname
[2] == '.');
8010 if (p
[0] < '0' || p
[0] > '7' || p
[1])
8012 regnum
= p
[0] - '0' + 68;