1 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "safe-ctype.h"
25 #include "dw2gencfi.h"
26 #include "opcode/ppc.h"
30 #include "elf/ppc64.h"
31 #include "dwarf2dbg.h"
35 #include "coff/xcoff.h"
39 /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */
41 /* Tell the main code what the endianness is. */
42 extern int target_big_endian
;
44 /* Whether or not, we've set target_big_endian. */
45 static int set_target_endian
= 0;
47 /* Whether to use user friendly register names. */
48 #ifndef TARGET_REG_NAMES_P
49 #define TARGET_REG_NAMES_P FALSE
52 /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST,
55 /* #lo(value) denotes the least significant 16 bits of the indicated. */
56 #define PPC_LO(v) ((v) & 0xffff)
58 /* #hi(value) denotes bits 16 through 31 of the indicated value. */
59 #define PPC_HI(v) (((v) >> 16) & 0xffff)
61 /* #ha(value) denotes the high adjusted value: bits 16 through 31 of
62 the indicated value, compensating for #lo() being treated as a
64 #define PPC_HA(v) PPC_HI ((v) + 0x8000)
66 /* #higher(value) denotes bits 32 through 47 of the indicated value. */
67 #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff)
69 /* #highera(value) denotes bits 32 through 47 of the indicated value,
70 compensating for #lo() being treated as a signed number. */
71 #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000)
73 /* #highest(value) denotes bits 48 through 63 of the indicated value. */
74 #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff)
76 /* #highesta(value) denotes bits 48 through 63 of the indicated value,
77 compensating for #lo being treated as a signed number. */
78 #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000)
80 #define SEX16(val) (((val) ^ 0x8000) - 0x8000)
82 /* For the time being on ppc64, don't report overflow on @h and @ha
83 applied to constants. */
84 #define REPORT_OVERFLOW_HI 0
86 static bfd_boolean reg_names_p
= TARGET_REG_NAMES_P
;
88 static void ppc_macro (char *, const struct powerpc_macro
*);
89 static void ppc_byte (int);
91 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
92 static void ppc_tc (int);
93 static void ppc_machine (int);
97 static void ppc_comm (int);
98 static void ppc_bb (int);
99 static void ppc_bc (int);
100 static void ppc_bf (int);
101 static void ppc_biei (int);
102 static void ppc_bs (int);
103 static void ppc_eb (int);
104 static void ppc_ec (int);
105 static void ppc_ef (int);
106 static void ppc_es (int);
107 static void ppc_csect (int);
108 static void ppc_dwsect (int);
109 static void ppc_change_csect (symbolS
*, offsetT
);
110 static void ppc_function (int);
111 static void ppc_extern (int);
112 static void ppc_lglobl (int);
113 static void ppc_ref (int);
114 static void ppc_section (int);
115 static void ppc_named_section (int);
116 static void ppc_stabx (int);
117 static void ppc_rename (int);
118 static void ppc_toc (int);
119 static void ppc_xcoff_cons (int);
120 static void ppc_vbyte (int);
124 static void ppc_elf_rdata (int);
125 static void ppc_elf_lcomm (int);
126 static void ppc_elf_localentry (int);
127 static void ppc_elf_abiversion (int);
128 static void ppc_elf_gnu_attribute (int);
131 /* Generic assembler global variables which must be defined by all
135 /* This string holds the chars that always start a comment. If the
136 pre-processor is disabled, these aren't very useful. The macro
137 tc_comment_chars points to this. We use this, rather than the
138 usual comment_chars, so that we can switch for Solaris conventions. */
139 static const char ppc_solaris_comment_chars
[] = "#!";
140 static const char ppc_eabi_comment_chars
[] = "#";
142 #ifdef TARGET_SOLARIS_COMMENT
143 const char *ppc_comment_chars
= ppc_solaris_comment_chars
;
145 const char *ppc_comment_chars
= ppc_eabi_comment_chars
;
148 const char comment_chars
[] = "#";
151 /* Characters which start a comment at the beginning of a line. */
152 const char line_comment_chars
[] = "#";
154 /* Characters which may be used to separate multiple commands on a
156 const char line_separator_chars
[] = ";";
158 /* Characters which are used to indicate an exponent in a floating
160 const char EXP_CHARS
[] = "eE";
162 /* Characters which mean that a number is a floating point constant,
164 const char FLT_CHARS
[] = "dD";
166 /* Anything that can start an operand needs to be mentioned here,
167 to stop the input scrubber eating whitespace. */
168 const char ppc_symbol_chars
[] = "%[";
170 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
171 int ppc_cie_data_alignment
;
173 /* The dwarf2 minimum instruction length. */
174 int ppc_dwarf2_line_min_insn_length
;
176 /* More than this number of nops in an alignment op gets a branch
178 unsigned long nop_limit
= 4;
180 /* The type of processor we are assembling for. This is one or more
181 of the PPC_OPCODE flags defined in opcode/ppc.h. */
182 ppc_cpu_t ppc_cpu
= 0;
183 ppc_cpu_t sticky
= 0;
185 /* Value for ELF e_flags EF_PPC64_ABI. */
186 unsigned int ppc_abiversion
= 0;
189 /* Flags set on encountering toc relocs. */
191 has_large_toc_reloc
= 1,
192 has_small_toc_reloc
= 2
196 /* Warn on emitting data to code sections. */
202 /* The target specific pseudo-ops which we support. */
204 const pseudo_typeS md_pseudo_table
[] =
206 /* Pseudo-ops which must be overridden. */
207 { "byte", ppc_byte
, 0 },
210 /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these
211 legitimately belong in the obj-*.c file. However, XCOFF is based
212 on COFF, and is only implemented for the RS/6000. We just use
213 obj-coff.c, and add what we need here. */
214 { "comm", ppc_comm
, 0 },
215 { "lcomm", ppc_comm
, 1 },
219 { "bi", ppc_biei
, 0 },
221 { "csect", ppc_csect
, 0 },
222 { "dwsect", ppc_dwsect
, 0 },
223 { "data", ppc_section
, 'd' },
227 { "ei", ppc_biei
, 1 },
229 { "extern", ppc_extern
, 0 },
230 { "function", ppc_function
, 0 },
231 { "lglobl", ppc_lglobl
, 0 },
232 { "ref", ppc_ref
, 0 },
233 { "rename", ppc_rename
, 0 },
234 { "section", ppc_named_section
, 0 },
235 { "stabx", ppc_stabx
, 0 },
236 { "text", ppc_section
, 't' },
237 { "toc", ppc_toc
, 0 },
238 { "long", ppc_xcoff_cons
, 2 },
239 { "llong", ppc_xcoff_cons
, 3 },
240 { "word", ppc_xcoff_cons
, 1 },
241 { "short", ppc_xcoff_cons
, 1 },
242 { "vbyte", ppc_vbyte
, 0 },
246 { "llong", cons
, 8 },
247 { "rdata", ppc_elf_rdata
, 0 },
248 { "rodata", ppc_elf_rdata
, 0 },
249 { "lcomm", ppc_elf_lcomm
, 0 },
250 { "localentry", ppc_elf_localentry
, 0 },
251 { "abiversion", ppc_elf_abiversion
, 0 },
252 { "gnu_attribute", ppc_elf_gnu_attribute
, 0},
255 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
257 { "machine", ppc_machine
, 0 },
264 /* Predefined register names if -mregnames (or default for Windows NT).
265 In general, there are lots of them, in an attempt to be compatible
266 with a number of other Windows NT assemblers. */
268 /* Structure to hold information about predefined registers. */
272 unsigned short value
;
273 unsigned short flags
;
276 /* List of registers that are pre-defined:
278 Each general register has predefined names of the form:
279 1. r<reg_num> which has the value <reg_num>.
280 2. r.<reg_num> which has the value <reg_num>.
282 Each floating point register has predefined names of the form:
283 1. f<reg_num> which has the value <reg_num>.
284 2. f.<reg_num> which has the value <reg_num>.
286 Each vector unit register has predefined names of the form:
287 1. v<reg_num> which has the value <reg_num>.
288 2. v.<reg_num> which has the value <reg_num>.
290 Each condition register has predefined names of the form:
291 1. cr<reg_num> which has the value <reg_num>.
292 2. cr.<reg_num> which has the value <reg_num>.
294 There are individual registers as well:
295 sp or r.sp has the value 1
296 rtoc or r.toc has the value 2
301 dsisr has the value 18
303 sdr1 has the value 25
304 srr0 has the value 26
305 srr1 has the value 27
307 The table is sorted. Suitable for searching by a binary search. */
309 static const struct pd_reg pre_defined_registers
[] =
311 /* VSX accumulators. */
312 { "a0", 0, PPC_OPERAND_ACC
},
313 { "a1", 1, PPC_OPERAND_ACC
},
314 { "a2", 2, PPC_OPERAND_ACC
},
315 { "a3", 3, PPC_OPERAND_ACC
},
316 { "a4", 4, PPC_OPERAND_ACC
},
317 { "a5", 5, PPC_OPERAND_ACC
},
318 { "a6", 6, PPC_OPERAND_ACC
},
319 { "a7", 7, PPC_OPERAND_ACC
},
321 /* Condition Registers */
322 { "cr.0", 0, PPC_OPERAND_CR_REG
},
323 { "cr.1", 1, PPC_OPERAND_CR_REG
},
324 { "cr.2", 2, PPC_OPERAND_CR_REG
},
325 { "cr.3", 3, PPC_OPERAND_CR_REG
},
326 { "cr.4", 4, PPC_OPERAND_CR_REG
},
327 { "cr.5", 5, PPC_OPERAND_CR_REG
},
328 { "cr.6", 6, PPC_OPERAND_CR_REG
},
329 { "cr.7", 7, PPC_OPERAND_CR_REG
},
331 { "cr0", 0, PPC_OPERAND_CR_REG
},
332 { "cr1", 1, PPC_OPERAND_CR_REG
},
333 { "cr2", 2, PPC_OPERAND_CR_REG
},
334 { "cr3", 3, PPC_OPERAND_CR_REG
},
335 { "cr4", 4, PPC_OPERAND_CR_REG
},
336 { "cr5", 5, PPC_OPERAND_CR_REG
},
337 { "cr6", 6, PPC_OPERAND_CR_REG
},
338 { "cr7", 7, PPC_OPERAND_CR_REG
},
340 { "ctr", 9, PPC_OPERAND_SPR
},
341 { "dar", 19, PPC_OPERAND_SPR
},
342 { "dec", 22, PPC_OPERAND_SPR
},
343 { "dsisr", 18, PPC_OPERAND_SPR
},
345 /* Floating point registers */
346 { "f.0", 0, PPC_OPERAND_FPR
},
347 { "f.1", 1, PPC_OPERAND_FPR
},
348 { "f.10", 10, PPC_OPERAND_FPR
},
349 { "f.11", 11, PPC_OPERAND_FPR
},
350 { "f.12", 12, PPC_OPERAND_FPR
},
351 { "f.13", 13, PPC_OPERAND_FPR
},
352 { "f.14", 14, PPC_OPERAND_FPR
},
353 { "f.15", 15, PPC_OPERAND_FPR
},
354 { "f.16", 16, PPC_OPERAND_FPR
},
355 { "f.17", 17, PPC_OPERAND_FPR
},
356 { "f.18", 18, PPC_OPERAND_FPR
},
357 { "f.19", 19, PPC_OPERAND_FPR
},
358 { "f.2", 2, PPC_OPERAND_FPR
},
359 { "f.20", 20, PPC_OPERAND_FPR
},
360 { "f.21", 21, PPC_OPERAND_FPR
},
361 { "f.22", 22, PPC_OPERAND_FPR
},
362 { "f.23", 23, PPC_OPERAND_FPR
},
363 { "f.24", 24, PPC_OPERAND_FPR
},
364 { "f.25", 25, PPC_OPERAND_FPR
},
365 { "f.26", 26, PPC_OPERAND_FPR
},
366 { "f.27", 27, PPC_OPERAND_FPR
},
367 { "f.28", 28, PPC_OPERAND_FPR
},
368 { "f.29", 29, PPC_OPERAND_FPR
},
369 { "f.3", 3, PPC_OPERAND_FPR
},
370 { "f.30", 30, PPC_OPERAND_FPR
},
371 { "f.31", 31, PPC_OPERAND_FPR
},
372 { "f.32", 32, PPC_OPERAND_VSR
},
373 { "f.33", 33, PPC_OPERAND_VSR
},
374 { "f.34", 34, PPC_OPERAND_VSR
},
375 { "f.35", 35, PPC_OPERAND_VSR
},
376 { "f.36", 36, PPC_OPERAND_VSR
},
377 { "f.37", 37, PPC_OPERAND_VSR
},
378 { "f.38", 38, PPC_OPERAND_VSR
},
379 { "f.39", 39, PPC_OPERAND_VSR
},
380 { "f.4", 4, PPC_OPERAND_FPR
},
381 { "f.40", 40, PPC_OPERAND_VSR
},
382 { "f.41", 41, PPC_OPERAND_VSR
},
383 { "f.42", 42, PPC_OPERAND_VSR
},
384 { "f.43", 43, PPC_OPERAND_VSR
},
385 { "f.44", 44, PPC_OPERAND_VSR
},
386 { "f.45", 45, PPC_OPERAND_VSR
},
387 { "f.46", 46, PPC_OPERAND_VSR
},
388 { "f.47", 47, PPC_OPERAND_VSR
},
389 { "f.48", 48, PPC_OPERAND_VSR
},
390 { "f.49", 49, PPC_OPERAND_VSR
},
391 { "f.5", 5, PPC_OPERAND_FPR
},
392 { "f.50", 50, PPC_OPERAND_VSR
},
393 { "f.51", 51, PPC_OPERAND_VSR
},
394 { "f.52", 52, PPC_OPERAND_VSR
},
395 { "f.53", 53, PPC_OPERAND_VSR
},
396 { "f.54", 54, PPC_OPERAND_VSR
},
397 { "f.55", 55, PPC_OPERAND_VSR
},
398 { "f.56", 56, PPC_OPERAND_VSR
},
399 { "f.57", 57, PPC_OPERAND_VSR
},
400 { "f.58", 58, PPC_OPERAND_VSR
},
401 { "f.59", 59, PPC_OPERAND_VSR
},
402 { "f.6", 6, PPC_OPERAND_FPR
},
403 { "f.60", 60, PPC_OPERAND_VSR
},
404 { "f.61", 61, PPC_OPERAND_VSR
},
405 { "f.62", 62, PPC_OPERAND_VSR
},
406 { "f.63", 63, PPC_OPERAND_VSR
},
407 { "f.7", 7, PPC_OPERAND_FPR
},
408 { "f.8", 8, PPC_OPERAND_FPR
},
409 { "f.9", 9, PPC_OPERAND_FPR
},
411 { "f0", 0, PPC_OPERAND_FPR
},
412 { "f1", 1, PPC_OPERAND_FPR
},
413 { "f10", 10, PPC_OPERAND_FPR
},
414 { "f11", 11, PPC_OPERAND_FPR
},
415 { "f12", 12, PPC_OPERAND_FPR
},
416 { "f13", 13, PPC_OPERAND_FPR
},
417 { "f14", 14, PPC_OPERAND_FPR
},
418 { "f15", 15, PPC_OPERAND_FPR
},
419 { "f16", 16, PPC_OPERAND_FPR
},
420 { "f17", 17, PPC_OPERAND_FPR
},
421 { "f18", 18, PPC_OPERAND_FPR
},
422 { "f19", 19, PPC_OPERAND_FPR
},
423 { "f2", 2, PPC_OPERAND_FPR
},
424 { "f20", 20, PPC_OPERAND_FPR
},
425 { "f21", 21, PPC_OPERAND_FPR
},
426 { "f22", 22, PPC_OPERAND_FPR
},
427 { "f23", 23, PPC_OPERAND_FPR
},
428 { "f24", 24, PPC_OPERAND_FPR
},
429 { "f25", 25, PPC_OPERAND_FPR
},
430 { "f26", 26, PPC_OPERAND_FPR
},
431 { "f27", 27, PPC_OPERAND_FPR
},
432 { "f28", 28, PPC_OPERAND_FPR
},
433 { "f29", 29, PPC_OPERAND_FPR
},
434 { "f3", 3, PPC_OPERAND_FPR
},
435 { "f30", 30, PPC_OPERAND_FPR
},
436 { "f31", 31, PPC_OPERAND_FPR
},
437 { "f32", 32, PPC_OPERAND_VSR
},
438 { "f33", 33, PPC_OPERAND_VSR
},
439 { "f34", 34, PPC_OPERAND_VSR
},
440 { "f35", 35, PPC_OPERAND_VSR
},
441 { "f36", 36, PPC_OPERAND_VSR
},
442 { "f37", 37, PPC_OPERAND_VSR
},
443 { "f38", 38, PPC_OPERAND_VSR
},
444 { "f39", 39, PPC_OPERAND_VSR
},
445 { "f4", 4, PPC_OPERAND_FPR
},
446 { "f40", 40, PPC_OPERAND_VSR
},
447 { "f41", 41, PPC_OPERAND_VSR
},
448 { "f42", 42, PPC_OPERAND_VSR
},
449 { "f43", 43, PPC_OPERAND_VSR
},
450 { "f44", 44, PPC_OPERAND_VSR
},
451 { "f45", 45, PPC_OPERAND_VSR
},
452 { "f46", 46, PPC_OPERAND_VSR
},
453 { "f47", 47, PPC_OPERAND_VSR
},
454 { "f48", 48, PPC_OPERAND_VSR
},
455 { "f49", 49, PPC_OPERAND_VSR
},
456 { "f5", 5, PPC_OPERAND_FPR
},
457 { "f50", 50, PPC_OPERAND_VSR
},
458 { "f51", 51, PPC_OPERAND_VSR
},
459 { "f52", 52, PPC_OPERAND_VSR
},
460 { "f53", 53, PPC_OPERAND_VSR
},
461 { "f54", 54, PPC_OPERAND_VSR
},
462 { "f55", 55, PPC_OPERAND_VSR
},
463 { "f56", 56, PPC_OPERAND_VSR
},
464 { "f57", 57, PPC_OPERAND_VSR
},
465 { "f58", 58, PPC_OPERAND_VSR
},
466 { "f59", 59, PPC_OPERAND_VSR
},
467 { "f6", 6, PPC_OPERAND_FPR
},
468 { "f60", 60, PPC_OPERAND_VSR
},
469 { "f61", 61, PPC_OPERAND_VSR
},
470 { "f62", 62, PPC_OPERAND_VSR
},
471 { "f63", 63, PPC_OPERAND_VSR
},
472 { "f7", 7, PPC_OPERAND_FPR
},
473 { "f8", 8, PPC_OPERAND_FPR
},
474 { "f9", 9, PPC_OPERAND_FPR
},
476 /* Quantization registers used with pair single instructions. */
477 { "gqr.0", 0, PPC_OPERAND_GQR
},
478 { "gqr.1", 1, PPC_OPERAND_GQR
},
479 { "gqr.2", 2, PPC_OPERAND_GQR
},
480 { "gqr.3", 3, PPC_OPERAND_GQR
},
481 { "gqr.4", 4, PPC_OPERAND_GQR
},
482 { "gqr.5", 5, PPC_OPERAND_GQR
},
483 { "gqr.6", 6, PPC_OPERAND_GQR
},
484 { "gqr.7", 7, PPC_OPERAND_GQR
},
485 { "gqr0", 0, PPC_OPERAND_GQR
},
486 { "gqr1", 1, PPC_OPERAND_GQR
},
487 { "gqr2", 2, PPC_OPERAND_GQR
},
488 { "gqr3", 3, PPC_OPERAND_GQR
},
489 { "gqr4", 4, PPC_OPERAND_GQR
},
490 { "gqr5", 5, PPC_OPERAND_GQR
},
491 { "gqr6", 6, PPC_OPERAND_GQR
},
492 { "gqr7", 7, PPC_OPERAND_GQR
},
494 { "lr", 8, PPC_OPERAND_SPR
},
496 /* General Purpose Registers */
497 { "r.0", 0, PPC_OPERAND_GPR
},
498 { "r.1", 1, PPC_OPERAND_GPR
},
499 { "r.10", 10, PPC_OPERAND_GPR
},
500 { "r.11", 11, PPC_OPERAND_GPR
},
501 { "r.12", 12, PPC_OPERAND_GPR
},
502 { "r.13", 13, PPC_OPERAND_GPR
},
503 { "r.14", 14, PPC_OPERAND_GPR
},
504 { "r.15", 15, PPC_OPERAND_GPR
},
505 { "r.16", 16, PPC_OPERAND_GPR
},
506 { "r.17", 17, PPC_OPERAND_GPR
},
507 { "r.18", 18, PPC_OPERAND_GPR
},
508 { "r.19", 19, PPC_OPERAND_GPR
},
509 { "r.2", 2, PPC_OPERAND_GPR
},
510 { "r.20", 20, PPC_OPERAND_GPR
},
511 { "r.21", 21, PPC_OPERAND_GPR
},
512 { "r.22", 22, PPC_OPERAND_GPR
},
513 { "r.23", 23, PPC_OPERAND_GPR
},
514 { "r.24", 24, PPC_OPERAND_GPR
},
515 { "r.25", 25, PPC_OPERAND_GPR
},
516 { "r.26", 26, PPC_OPERAND_GPR
},
517 { "r.27", 27, PPC_OPERAND_GPR
},
518 { "r.28", 28, PPC_OPERAND_GPR
},
519 { "r.29", 29, PPC_OPERAND_GPR
},
520 { "r.3", 3, PPC_OPERAND_GPR
},
521 { "r.30", 30, PPC_OPERAND_GPR
},
522 { "r.31", 31, PPC_OPERAND_GPR
},
523 { "r.4", 4, PPC_OPERAND_GPR
},
524 { "r.5", 5, PPC_OPERAND_GPR
},
525 { "r.6", 6, PPC_OPERAND_GPR
},
526 { "r.7", 7, PPC_OPERAND_GPR
},
527 { "r.8", 8, PPC_OPERAND_GPR
},
528 { "r.9", 9, PPC_OPERAND_GPR
},
530 { "r.sp", 1, PPC_OPERAND_GPR
},
532 { "r.toc", 2, PPC_OPERAND_GPR
},
534 { "r0", 0, PPC_OPERAND_GPR
},
535 { "r1", 1, PPC_OPERAND_GPR
},
536 { "r10", 10, PPC_OPERAND_GPR
},
537 { "r11", 11, PPC_OPERAND_GPR
},
538 { "r12", 12, PPC_OPERAND_GPR
},
539 { "r13", 13, PPC_OPERAND_GPR
},
540 { "r14", 14, PPC_OPERAND_GPR
},
541 { "r15", 15, PPC_OPERAND_GPR
},
542 { "r16", 16, PPC_OPERAND_GPR
},
543 { "r17", 17, PPC_OPERAND_GPR
},
544 { "r18", 18, PPC_OPERAND_GPR
},
545 { "r19", 19, PPC_OPERAND_GPR
},
546 { "r2", 2, PPC_OPERAND_GPR
},
547 { "r20", 20, PPC_OPERAND_GPR
},
548 { "r21", 21, PPC_OPERAND_GPR
},
549 { "r22", 22, PPC_OPERAND_GPR
},
550 { "r23", 23, PPC_OPERAND_GPR
},
551 { "r24", 24, PPC_OPERAND_GPR
},
552 { "r25", 25, PPC_OPERAND_GPR
},
553 { "r26", 26, PPC_OPERAND_GPR
},
554 { "r27", 27, PPC_OPERAND_GPR
},
555 { "r28", 28, PPC_OPERAND_GPR
},
556 { "r29", 29, PPC_OPERAND_GPR
},
557 { "r3", 3, PPC_OPERAND_GPR
},
558 { "r30", 30, PPC_OPERAND_GPR
},
559 { "r31", 31, PPC_OPERAND_GPR
},
560 { "r4", 4, PPC_OPERAND_GPR
},
561 { "r5", 5, PPC_OPERAND_GPR
},
562 { "r6", 6, PPC_OPERAND_GPR
},
563 { "r7", 7, PPC_OPERAND_GPR
},
564 { "r8", 8, PPC_OPERAND_GPR
},
565 { "r9", 9, PPC_OPERAND_GPR
},
567 { "rtoc", 2, PPC_OPERAND_GPR
},
569 { "sdr1", 25, PPC_OPERAND_SPR
},
571 { "sp", 1, PPC_OPERAND_GPR
},
573 { "srr0", 26, PPC_OPERAND_SPR
},
574 { "srr1", 27, PPC_OPERAND_SPR
},
576 /* Vector (Altivec/VMX) registers */
577 { "v.0", 0, PPC_OPERAND_VR
},
578 { "v.1", 1, PPC_OPERAND_VR
},
579 { "v.10", 10, PPC_OPERAND_VR
},
580 { "v.11", 11, PPC_OPERAND_VR
},
581 { "v.12", 12, PPC_OPERAND_VR
},
582 { "v.13", 13, PPC_OPERAND_VR
},
583 { "v.14", 14, PPC_OPERAND_VR
},
584 { "v.15", 15, PPC_OPERAND_VR
},
585 { "v.16", 16, PPC_OPERAND_VR
},
586 { "v.17", 17, PPC_OPERAND_VR
},
587 { "v.18", 18, PPC_OPERAND_VR
},
588 { "v.19", 19, PPC_OPERAND_VR
},
589 { "v.2", 2, PPC_OPERAND_VR
},
590 { "v.20", 20, PPC_OPERAND_VR
},
591 { "v.21", 21, PPC_OPERAND_VR
},
592 { "v.22", 22, PPC_OPERAND_VR
},
593 { "v.23", 23, PPC_OPERAND_VR
},
594 { "v.24", 24, PPC_OPERAND_VR
},
595 { "v.25", 25, PPC_OPERAND_VR
},
596 { "v.26", 26, PPC_OPERAND_VR
},
597 { "v.27", 27, PPC_OPERAND_VR
},
598 { "v.28", 28, PPC_OPERAND_VR
},
599 { "v.29", 29, PPC_OPERAND_VR
},
600 { "v.3", 3, PPC_OPERAND_VR
},
601 { "v.30", 30, PPC_OPERAND_VR
},
602 { "v.31", 31, PPC_OPERAND_VR
},
603 { "v.4", 4, PPC_OPERAND_VR
},
604 { "v.5", 5, PPC_OPERAND_VR
},
605 { "v.6", 6, PPC_OPERAND_VR
},
606 { "v.7", 7, PPC_OPERAND_VR
},
607 { "v.8", 8, PPC_OPERAND_VR
},
608 { "v.9", 9, PPC_OPERAND_VR
},
610 { "v0", 0, PPC_OPERAND_VR
},
611 { "v1", 1, PPC_OPERAND_VR
},
612 { "v10", 10, PPC_OPERAND_VR
},
613 { "v11", 11, PPC_OPERAND_VR
},
614 { "v12", 12, PPC_OPERAND_VR
},
615 { "v13", 13, PPC_OPERAND_VR
},
616 { "v14", 14, PPC_OPERAND_VR
},
617 { "v15", 15, PPC_OPERAND_VR
},
618 { "v16", 16, PPC_OPERAND_VR
},
619 { "v17", 17, PPC_OPERAND_VR
},
620 { "v18", 18, PPC_OPERAND_VR
},
621 { "v19", 19, PPC_OPERAND_VR
},
622 { "v2", 2, PPC_OPERAND_VR
},
623 { "v20", 20, PPC_OPERAND_VR
},
624 { "v21", 21, PPC_OPERAND_VR
},
625 { "v22", 22, PPC_OPERAND_VR
},
626 { "v23", 23, PPC_OPERAND_VR
},
627 { "v24", 24, PPC_OPERAND_VR
},
628 { "v25", 25, PPC_OPERAND_VR
},
629 { "v26", 26, PPC_OPERAND_VR
},
630 { "v27", 27, PPC_OPERAND_VR
},
631 { "v28", 28, PPC_OPERAND_VR
},
632 { "v29", 29, PPC_OPERAND_VR
},
633 { "v3", 3, PPC_OPERAND_VR
},
634 { "v30", 30, PPC_OPERAND_VR
},
635 { "v31", 31, PPC_OPERAND_VR
},
636 { "v4", 4, PPC_OPERAND_VR
},
637 { "v5", 5, PPC_OPERAND_VR
},
638 { "v6", 6, PPC_OPERAND_VR
},
639 { "v7", 7, PPC_OPERAND_VR
},
640 { "v8", 8, PPC_OPERAND_VR
},
641 { "v9", 9, PPC_OPERAND_VR
},
643 /* Vector Scalar (VSX) registers (ISA 2.06). */
644 { "vs.0", 0, PPC_OPERAND_VSR
},
645 { "vs.1", 1, PPC_OPERAND_VSR
},
646 { "vs.10", 10, PPC_OPERAND_VSR
},
647 { "vs.11", 11, PPC_OPERAND_VSR
},
648 { "vs.12", 12, PPC_OPERAND_VSR
},
649 { "vs.13", 13, PPC_OPERAND_VSR
},
650 { "vs.14", 14, PPC_OPERAND_VSR
},
651 { "vs.15", 15, PPC_OPERAND_VSR
},
652 { "vs.16", 16, PPC_OPERAND_VSR
},
653 { "vs.17", 17, PPC_OPERAND_VSR
},
654 { "vs.18", 18, PPC_OPERAND_VSR
},
655 { "vs.19", 19, PPC_OPERAND_VSR
},
656 { "vs.2", 2, PPC_OPERAND_VSR
},
657 { "vs.20", 20, PPC_OPERAND_VSR
},
658 { "vs.21", 21, PPC_OPERAND_VSR
},
659 { "vs.22", 22, PPC_OPERAND_VSR
},
660 { "vs.23", 23, PPC_OPERAND_VSR
},
661 { "vs.24", 24, PPC_OPERAND_VSR
},
662 { "vs.25", 25, PPC_OPERAND_VSR
},
663 { "vs.26", 26, PPC_OPERAND_VSR
},
664 { "vs.27", 27, PPC_OPERAND_VSR
},
665 { "vs.28", 28, PPC_OPERAND_VSR
},
666 { "vs.29", 29, PPC_OPERAND_VSR
},
667 { "vs.3", 3, PPC_OPERAND_VSR
},
668 { "vs.30", 30, PPC_OPERAND_VSR
},
669 { "vs.31", 31, PPC_OPERAND_VSR
},
670 { "vs.32", 32, PPC_OPERAND_VSR
},
671 { "vs.33", 33, PPC_OPERAND_VSR
},
672 { "vs.34", 34, PPC_OPERAND_VSR
},
673 { "vs.35", 35, PPC_OPERAND_VSR
},
674 { "vs.36", 36, PPC_OPERAND_VSR
},
675 { "vs.37", 37, PPC_OPERAND_VSR
},
676 { "vs.38", 38, PPC_OPERAND_VSR
},
677 { "vs.39", 39, PPC_OPERAND_VSR
},
678 { "vs.4", 4, PPC_OPERAND_VSR
},
679 { "vs.40", 40, PPC_OPERAND_VSR
},
680 { "vs.41", 41, PPC_OPERAND_VSR
},
681 { "vs.42", 42, PPC_OPERAND_VSR
},
682 { "vs.43", 43, PPC_OPERAND_VSR
},
683 { "vs.44", 44, PPC_OPERAND_VSR
},
684 { "vs.45", 45, PPC_OPERAND_VSR
},
685 { "vs.46", 46, PPC_OPERAND_VSR
},
686 { "vs.47", 47, PPC_OPERAND_VSR
},
687 { "vs.48", 48, PPC_OPERAND_VSR
},
688 { "vs.49", 49, PPC_OPERAND_VSR
},
689 { "vs.5", 5, PPC_OPERAND_VSR
},
690 { "vs.50", 50, PPC_OPERAND_VSR
},
691 { "vs.51", 51, PPC_OPERAND_VSR
},
692 { "vs.52", 52, PPC_OPERAND_VSR
},
693 { "vs.53", 53, PPC_OPERAND_VSR
},
694 { "vs.54", 54, PPC_OPERAND_VSR
},
695 { "vs.55", 55, PPC_OPERAND_VSR
},
696 { "vs.56", 56, PPC_OPERAND_VSR
},
697 { "vs.57", 57, PPC_OPERAND_VSR
},
698 { "vs.58", 58, PPC_OPERAND_VSR
},
699 { "vs.59", 59, PPC_OPERAND_VSR
},
700 { "vs.6", 6, PPC_OPERAND_VSR
},
701 { "vs.60", 60, PPC_OPERAND_VSR
},
702 { "vs.61", 61, PPC_OPERAND_VSR
},
703 { "vs.62", 62, PPC_OPERAND_VSR
},
704 { "vs.63", 63, PPC_OPERAND_VSR
},
705 { "vs.7", 7, PPC_OPERAND_VSR
},
706 { "vs.8", 8, PPC_OPERAND_VSR
},
707 { "vs.9", 9, PPC_OPERAND_VSR
},
709 { "vs0", 0, PPC_OPERAND_VSR
},
710 { "vs1", 1, PPC_OPERAND_VSR
},
711 { "vs10", 10, PPC_OPERAND_VSR
},
712 { "vs11", 11, PPC_OPERAND_VSR
},
713 { "vs12", 12, PPC_OPERAND_VSR
},
714 { "vs13", 13, PPC_OPERAND_VSR
},
715 { "vs14", 14, PPC_OPERAND_VSR
},
716 { "vs15", 15, PPC_OPERAND_VSR
},
717 { "vs16", 16, PPC_OPERAND_VSR
},
718 { "vs17", 17, PPC_OPERAND_VSR
},
719 { "vs18", 18, PPC_OPERAND_VSR
},
720 { "vs19", 19, PPC_OPERAND_VSR
},
721 { "vs2", 2, PPC_OPERAND_VSR
},
722 { "vs20", 20, PPC_OPERAND_VSR
},
723 { "vs21", 21, PPC_OPERAND_VSR
},
724 { "vs22", 22, PPC_OPERAND_VSR
},
725 { "vs23", 23, PPC_OPERAND_VSR
},
726 { "vs24", 24, PPC_OPERAND_VSR
},
727 { "vs25", 25, PPC_OPERAND_VSR
},
728 { "vs26", 26, PPC_OPERAND_VSR
},
729 { "vs27", 27, PPC_OPERAND_VSR
},
730 { "vs28", 28, PPC_OPERAND_VSR
},
731 { "vs29", 29, PPC_OPERAND_VSR
},
732 { "vs3", 3, PPC_OPERAND_VSR
},
733 { "vs30", 30, PPC_OPERAND_VSR
},
734 { "vs31", 31, PPC_OPERAND_VSR
},
735 { "vs32", 32, PPC_OPERAND_VSR
},
736 { "vs33", 33, PPC_OPERAND_VSR
},
737 { "vs34", 34, PPC_OPERAND_VSR
},
738 { "vs35", 35, PPC_OPERAND_VSR
},
739 { "vs36", 36, PPC_OPERAND_VSR
},
740 { "vs37", 37, PPC_OPERAND_VSR
},
741 { "vs38", 38, PPC_OPERAND_VSR
},
742 { "vs39", 39, PPC_OPERAND_VSR
},
743 { "vs4", 4, PPC_OPERAND_VSR
},
744 { "vs40", 40, PPC_OPERAND_VSR
},
745 { "vs41", 41, PPC_OPERAND_VSR
},
746 { "vs42", 42, PPC_OPERAND_VSR
},
747 { "vs43", 43, PPC_OPERAND_VSR
},
748 { "vs44", 44, PPC_OPERAND_VSR
},
749 { "vs45", 45, PPC_OPERAND_VSR
},
750 { "vs46", 46, PPC_OPERAND_VSR
},
751 { "vs47", 47, PPC_OPERAND_VSR
},
752 { "vs48", 48, PPC_OPERAND_VSR
},
753 { "vs49", 49, PPC_OPERAND_VSR
},
754 { "vs5", 5, PPC_OPERAND_VSR
},
755 { "vs50", 50, PPC_OPERAND_VSR
},
756 { "vs51", 51, PPC_OPERAND_VSR
},
757 { "vs52", 52, PPC_OPERAND_VSR
},
758 { "vs53", 53, PPC_OPERAND_VSR
},
759 { "vs54", 54, PPC_OPERAND_VSR
},
760 { "vs55", 55, PPC_OPERAND_VSR
},
761 { "vs56", 56, PPC_OPERAND_VSR
},
762 { "vs57", 57, PPC_OPERAND_VSR
},
763 { "vs58", 58, PPC_OPERAND_VSR
},
764 { "vs59", 59, PPC_OPERAND_VSR
},
765 { "vs6", 6, PPC_OPERAND_VSR
},
766 { "vs60", 60, PPC_OPERAND_VSR
},
767 { "vs61", 61, PPC_OPERAND_VSR
},
768 { "vs62", 62, PPC_OPERAND_VSR
},
769 { "vs63", 63, PPC_OPERAND_VSR
},
770 { "vs7", 7, PPC_OPERAND_VSR
},
771 { "vs8", 8, PPC_OPERAND_VSR
},
772 { "vs9", 9, PPC_OPERAND_VSR
},
774 { "xer", 1, PPC_OPERAND_SPR
}
777 #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg))
779 /* Given NAME, find the register number associated with that name, return
780 the integer value associated with the given name or -1 on failure. */
782 static const struct pd_reg
*
783 reg_name_search (const struct pd_reg
*regs
, int regcount
, const char *name
)
785 int middle
, low
, high
;
793 middle
= (low
+ high
) / 2;
794 cmp
= strcasecmp (name
, regs
[middle
].name
);
800 return ®s
[middle
];
808 * Summary of register_name.
810 * in: Input_line_pointer points to 1st char of operand.
812 * out: A expressionS.
813 * The operand may have been a register: in this case, X_op == O_register,
814 * X_add_number is set to the register number, and truth is returned.
815 * Input_line_pointer->(next non-blank) char after operand, or is in its
820 register_name (expressionS
*expressionP
)
822 const struct pd_reg
*reg
;
827 /* Find the spelling of the operand. */
828 start
= name
= input_line_pointer
;
829 if (name
[0] == '%' && ISALPHA (name
[1]))
830 name
= ++input_line_pointer
;
832 else if (!reg_names_p
|| !ISALPHA (name
[0]))
835 c
= get_symbol_name (&name
);
836 reg
= reg_name_search (pre_defined_registers
, REG_NAME_CNT
, name
);
838 /* Put back the delimiting char. */
839 *input_line_pointer
= c
;
841 /* Look to see if it's in the register table. */
844 expressionP
->X_op
= O_register
;
845 expressionP
->X_add_number
= reg
->value
;
846 expressionP
->X_md
= reg
->flags
;
848 /* Make the rest nice. */
849 expressionP
->X_add_symbol
= NULL
;
850 expressionP
->X_op_symbol
= NULL
;
854 /* Reset the line as if we had not done anything. */
855 input_line_pointer
= start
;
859 /* This function is called for each symbol seen in an expression. It
860 handles the special parsing which PowerPC assemblers are supposed
861 to use for condition codes. */
863 /* Whether to do the special parsing. */
864 static bfd_boolean cr_operand
;
866 /* Names to recognize in a condition code. This table is sorted. */
867 static const struct pd_reg cr_names
[] =
869 { "cr0", 0, PPC_OPERAND_CR_REG
},
870 { "cr1", 1, PPC_OPERAND_CR_REG
},
871 { "cr2", 2, PPC_OPERAND_CR_REG
},
872 { "cr3", 3, PPC_OPERAND_CR_REG
},
873 { "cr4", 4, PPC_OPERAND_CR_REG
},
874 { "cr5", 5, PPC_OPERAND_CR_REG
},
875 { "cr6", 6, PPC_OPERAND_CR_REG
},
876 { "cr7", 7, PPC_OPERAND_CR_REG
},
877 { "eq", 2, PPC_OPERAND_CR_BIT
},
878 { "gt", 1, PPC_OPERAND_CR_BIT
},
879 { "lt", 0, PPC_OPERAND_CR_BIT
},
880 { "so", 3, PPC_OPERAND_CR_BIT
},
881 { "un", 3, PPC_OPERAND_CR_BIT
}
884 /* Parsing function. This returns non-zero if it recognized an
888 ppc_parse_name (const char *name
, expressionS
*exp
)
890 const struct pd_reg
*reg
;
897 reg
= reg_name_search (cr_names
, sizeof cr_names
/ sizeof cr_names
[0],
902 exp
->X_op
= O_register
;
903 exp
->X_add_number
= reg
->value
;
904 exp
->X_md
= reg
->flags
;
909 /* Propagate X_md and check register expressions. This is to support
910 condition codes like 4*cr5+eq. */
913 ppc_optimize_expr (expressionS
*left
, operatorT op
, expressionS
*right
)
915 /* Accept 4*cr<n> and cr<n>*4. */
917 && ((right
->X_op
== O_register
918 && right
->X_md
== PPC_OPERAND_CR_REG
919 && left
->X_op
== O_constant
920 && left
->X_add_number
== 4)
921 || (left
->X_op
== O_register
922 && left
->X_md
== PPC_OPERAND_CR_REG
923 && right
->X_op
== O_constant
924 && right
->X_add_number
== 4)))
926 left
->X_op
= O_register
;
927 left
->X_md
= PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
;
928 left
->X_add_number
*= right
->X_add_number
;
932 /* Accept the above plus <cr bit>, and <cr bit> plus the above. */
933 if (right
->X_op
== O_register
934 && left
->X_op
== O_register
936 && ((right
->X_md
== PPC_OPERAND_CR_BIT
937 && left
->X_md
== (PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
))
938 || (right
->X_md
== (PPC_OPERAND_CR_REG
| PPC_OPERAND_CR_BIT
)
939 && left
->X_md
== PPC_OPERAND_CR_BIT
)))
941 left
->X_md
= PPC_OPERAND_CR_BIT
;
942 right
->X_op
= O_constant
;
946 /* Accept reg +/- constant. */
947 if (left
->X_op
== O_register
948 && !((op
== O_add
|| op
== O_subtract
) && right
->X_op
== O_constant
))
949 as_warn (_("invalid register expression"));
951 /* Accept constant + reg. */
952 if (right
->X_op
== O_register
)
954 if (op
== O_add
&& left
->X_op
== O_constant
)
955 left
->X_md
= right
->X_md
;
957 as_warn (_("invalid register expression"));
963 /* Local variables. */
965 /* Whether to target xcoff64/elf64. */
966 static unsigned int ppc_obj64
= BFD_DEFAULT_TARGET_SIZE
== 64;
968 /* Opcode hash table. */
969 static htab_t ppc_hash
;
971 /* Macro hash table. */
972 static htab_t ppc_macro_hash
;
975 /* What type of shared library support to use. */
976 static enum { SHLIB_NONE
, SHLIB_PIC
, SHLIB_MRELOCATABLE
} shlib
= SHLIB_NONE
;
978 /* Flags to set in the elf header. */
979 static flagword ppc_flags
= 0;
981 /* Whether this is Solaris or not. */
982 #ifdef TARGET_SOLARIS_COMMENT
983 #define SOLARIS_P TRUE
985 #define SOLARIS_P FALSE
988 static bfd_boolean msolaris
= SOLARIS_P
;
993 /* The RS/6000 assembler uses the .csect pseudo-op to generate code
994 using a bunch of different sections. These assembler sections,
995 however, are all encompassed within the .text or .data sections of
996 the final output file. We handle this by using different
997 subsegments within these main segments. */
999 /* Next subsegment to allocate within the .text segment. */
1000 static subsegT ppc_text_subsegment
= 2;
1002 /* Linked list of csects in the text section. */
1003 static symbolS
*ppc_text_csects
;
1005 /* Next subsegment to allocate within the .data segment. */
1006 static subsegT ppc_data_subsegment
= 2;
1008 /* Linked list of csects in the data section. */
1009 static symbolS
*ppc_data_csects
;
1011 /* The current csect. */
1012 static symbolS
*ppc_current_csect
;
1014 /* The RS/6000 assembler uses a TOC which holds addresses of functions
1015 and variables. Symbols are put in the TOC with the .tc pseudo-op.
1016 A special relocation is used when accessing TOC entries. We handle
1017 the TOC as a subsegment within the .data segment. We set it up if
1018 we see a .toc pseudo-op, and save the csect symbol here. */
1019 static symbolS
*ppc_toc_csect
;
1021 /* The first frag in the TOC subsegment. */
1022 static fragS
*ppc_toc_frag
;
1024 /* The first frag in the first subsegment after the TOC in the .data
1025 segment. NULL if there are no subsegments after the TOC. */
1026 static fragS
*ppc_after_toc_frag
;
1028 /* The current static block. */
1029 static symbolS
*ppc_current_block
;
1031 /* The COFF debugging section; set by md_begin. This is not the
1032 .debug section, but is instead the secret BFD section which will
1033 cause BFD to set the section number of a symbol to N_DEBUG. */
1034 static asection
*ppc_coff_debug_section
;
1036 /* Structure to set the length field of the dwarf sections. */
1037 struct dw_subsection
{
1038 /* Subsections are simply linked. */
1039 struct dw_subsection
*link
;
1041 /* The subsection number. */
1044 /* Expression to compute the length of the section. */
1045 expressionS end_exp
;
1048 static struct dw_section
{
1049 /* Corresponding section. */
1052 /* Simply linked list of subsections with a label. */
1053 struct dw_subsection
*list_subseg
;
1055 /* The anonymous subsection. */
1056 struct dw_subsection
*anon_subseg
;
1057 } dw_sections
[XCOFF_DWSECT_NBR_NAMES
];
1058 #endif /* OBJ_XCOFF */
1061 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */
1062 unsigned long *ppc_apuinfo_list
;
1063 unsigned int ppc_apuinfo_num
;
1064 unsigned int ppc_apuinfo_num_alloc
;
1065 #endif /* OBJ_ELF */
1068 const char *const md_shortopts
= "b:l:usm:K:VQ:";
1070 const char *const md_shortopts
= "um:";
1072 #define OPTION_NOPS (OPTION_MD_BASE + 0)
1073 const struct option md_longopts
[] = {
1074 {"nops", required_argument
, NULL
, OPTION_NOPS
},
1075 {"ppc476-workaround", no_argument
, &warn_476
, 1},
1076 {"no-ppc476-workaround", no_argument
, &warn_476
, 0},
1077 {NULL
, no_argument
, NULL
, 0}
1079 const size_t md_longopts_size
= sizeof (md_longopts
);
1082 md_parse_option (int c
, const char *arg
)
1089 /* -u means that any undefined symbols should be treated as
1090 external, which is the default for gas anyhow. */
1095 /* Solaris as takes -le (presumably for little endian). For completeness
1096 sake, recognize -be also. */
1097 if (strcmp (arg
, "e") == 0)
1099 target_big_endian
= 0;
1100 set_target_endian
= 1;
1101 if (ppc_cpu
& PPC_OPCODE_VLE
)
1102 as_bad (_("the use of -mvle requires big endian."));
1110 if (strcmp (arg
, "e") == 0)
1112 target_big_endian
= 1;
1113 set_target_endian
= 1;
1121 /* Recognize -K PIC. */
1122 if (strcmp (arg
, "PIC") == 0 || strcmp (arg
, "pic") == 0)
1125 ppc_flags
|= EF_PPC_RELOCATABLE_LIB
;
1133 /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */
1135 if (strcmp (arg
, "64") == 0)
1139 if (ppc_cpu
& PPC_OPCODE_VLE
)
1140 as_bad (_("the use of -mvle requires -a32."));
1142 as_fatal (_("%s unsupported"), "-a64");
1145 else if (strcmp (arg
, "32") == 0)
1152 new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, arg
);
1153 /* "raw" is only valid for the disassembler. */
1154 if (new_cpu
!= 0 && (new_cpu
& PPC_OPCODE_RAW
) == 0)
1157 if (strcmp (arg
, "vle") == 0)
1159 if (set_target_endian
&& target_big_endian
== 0)
1160 as_bad (_("the use of -mvle requires big endian."));
1162 as_bad (_("the use of -mvle requires -a32."));
1166 else if (strcmp (arg
, "no-vle") == 0)
1168 sticky
&= ~PPC_OPCODE_VLE
;
1170 new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, "booke");
1171 new_cpu
&= ~PPC_OPCODE_VLE
;
1176 else if (strcmp (arg
, "regnames") == 0)
1179 else if (strcmp (arg
, "no-regnames") == 0)
1180 reg_names_p
= FALSE
;
1183 /* -mrelocatable/-mrelocatable-lib -- warn about initializations
1184 that require relocation. */
1185 else if (strcmp (arg
, "relocatable") == 0)
1187 shlib
= SHLIB_MRELOCATABLE
;
1188 ppc_flags
|= EF_PPC_RELOCATABLE
;
1191 else if (strcmp (arg
, "relocatable-lib") == 0)
1193 shlib
= SHLIB_MRELOCATABLE
;
1194 ppc_flags
|= EF_PPC_RELOCATABLE_LIB
;
1197 /* -memb, set embedded bit. */
1198 else if (strcmp (arg
, "emb") == 0)
1199 ppc_flags
|= EF_PPC_EMB
;
1201 /* -mlittle/-mbig set the endianness. */
1202 else if (strcmp (arg
, "little") == 0
1203 || strcmp (arg
, "little-endian") == 0)
1205 target_big_endian
= 0;
1206 set_target_endian
= 1;
1207 if (ppc_cpu
& PPC_OPCODE_VLE
)
1208 as_bad (_("the use of -mvle requires big endian."));
1211 else if (strcmp (arg
, "big") == 0 || strcmp (arg
, "big-endian") == 0)
1213 target_big_endian
= 1;
1214 set_target_endian
= 1;
1217 else if (strcmp (arg
, "solaris") == 0)
1220 ppc_comment_chars
= ppc_solaris_comment_chars
;
1223 else if (strcmp (arg
, "no-solaris") == 0)
1226 ppc_comment_chars
= ppc_eabi_comment_chars
;
1228 else if (strcmp (arg
, "spe2") == 0)
1230 ppc_cpu
|= PPC_OPCODE_SPE2
;
1235 as_bad (_("invalid switch -m%s"), arg
);
1241 /* -V: SVR4 argument to print version ID. */
1243 print_version_id ();
1246 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
1247 should be emitted or not. FIXME: Not implemented. */
1251 /* Solaris takes -s to specify that .stabs go in a .stabs section,
1252 rather than .stabs.excl, which is ignored by the linker.
1253 FIXME: Not implemented. */
1264 nop_limit
= strtoul (optarg
, &end
, 0);
1266 as_bad (_("--nops needs a numeric argument"));
1281 is_ppc64_target (const bfd_target
*targ
, void *data ATTRIBUTE_UNUSED
)
1283 switch (targ
->flavour
)
1286 case bfd_target_elf_flavour
:
1287 return strncmp (targ
->name
, "elf64-powerpc", 13) == 0;
1290 case bfd_target_xcoff_flavour
:
1291 return (strcmp (targ
->name
, "aixcoff64-rs6000") == 0
1292 || strcmp (targ
->name
, "aix5coff64-rs6000") == 0);
1300 md_show_usage (FILE *stream
)
1302 fprintf (stream
, _("\
1303 PowerPC options:\n"));
1304 fprintf (stream
, _("\
1305 -a32 generate ELF32/XCOFF32\n"));
1306 if (bfd_iterate_over_targets (is_ppc64_target
, NULL
))
1307 fprintf (stream
, _("\
1308 -a64 generate ELF64/XCOFF64\n"));
1309 fprintf (stream
, _("\
1311 fprintf (stream
, _("\
1312 -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n"));
1313 fprintf (stream
, _("\
1314 -mpwr generate code for POWER (RIOS1)\n"));
1315 fprintf (stream
, _("\
1316 -m601 generate code for PowerPC 601\n"));
1317 fprintf (stream
, _("\
1318 -mppc, -mppc32, -m603, -m604\n\
1319 generate code for PowerPC 603/604\n"));
1320 fprintf (stream
, _("\
1321 -m403 generate code for PowerPC 403\n"));
1322 fprintf (stream
, _("\
1323 -m405 generate code for PowerPC 405\n"));
1324 fprintf (stream
, _("\
1325 -m440 generate code for PowerPC 440\n"));
1326 fprintf (stream
, _("\
1327 -m464 generate code for PowerPC 464\n"));
1328 fprintf (stream
, _("\
1329 -m476 generate code for PowerPC 476\n"));
1330 fprintf (stream
, _("\
1331 -m7400, -m7410, -m7450, -m7455\n\
1332 generate code for PowerPC 7400/7410/7450/7455\n"));
1333 fprintf (stream
, _("\
1334 -m750cl, -mgekko, -mbroadway\n\
1335 generate code for PowerPC 750cl/Gekko/Broadway\n"));
1336 fprintf (stream
, _("\
1337 -m821, -m850, -m860 generate code for PowerPC 821/850/860\n"));
1338 fprintf (stream
, _("\
1339 -mppc64, -m620 generate code for PowerPC 620/625/630\n"));
1340 fprintf (stream
, _("\
1341 -mppc64bridge generate code for PowerPC 64, including bridge insns\n"));
1342 fprintf (stream
, _("\
1343 -mbooke generate code for 32-bit PowerPC BookE\n"));
1344 fprintf (stream
, _("\
1345 -ma2 generate code for A2 architecture\n"));
1346 fprintf (stream
, _("\
1347 -mpower4, -mpwr4 generate code for Power4 architecture\n"));
1348 fprintf (stream
, _("\
1349 -mpower5, -mpwr5, -mpwr5x\n\
1350 generate code for Power5 architecture\n"));
1351 fprintf (stream
, _("\
1352 -mpower6, -mpwr6 generate code for Power6 architecture\n"));
1353 fprintf (stream
, _("\
1354 -mpower7, -mpwr7 generate code for Power7 architecture\n"));
1355 fprintf (stream
, _("\
1356 -mpower8, -mpwr8 generate code for Power8 architecture\n"));
1357 fprintf (stream
, _("\
1358 -mpower9, -mpwr9 generate code for Power9 architecture\n"));
1359 fprintf (stream
, _("\
1360 -mpower10, -mpwr10 generate code for Power10 architecture\n"));
1361 fprintf (stream
, _("\
1362 -mcell generate code for Cell Broadband Engine architecture\n"));
1363 fprintf (stream
, _("\
1364 -mcom generate code for Power/PowerPC common instructions\n"));
1365 fprintf (stream
, _("\
1366 -many generate code for any architecture (PWR/PWRX/PPC)\n"));
1367 fprintf (stream
, _("\
1368 -maltivec generate code for AltiVec\n"));
1369 fprintf (stream
, _("\
1370 -mvsx generate code for Vector-Scalar (VSX) instructions\n"));
1371 fprintf (stream
, _("\
1372 -me300 generate code for PowerPC e300 family\n"));
1373 fprintf (stream
, _("\
1374 -me500, -me500x2 generate code for Motorola e500 core complex\n"));
1375 fprintf (stream
, _("\
1376 -me500mc, generate code for Freescale e500mc core complex\n"));
1377 fprintf (stream
, _("\
1378 -me500mc64, generate code for Freescale e500mc64 core complex\n"));
1379 fprintf (stream
, _("\
1380 -me5500, generate code for Freescale e5500 core complex\n"));
1381 fprintf (stream
, _("\
1382 -me6500, generate code for Freescale e6500 core complex\n"));
1383 fprintf (stream
, _("\
1384 -mspe generate code for Motorola SPE instructions\n"));
1385 fprintf (stream
, _("\
1386 -mspe2 generate code for Freescale SPE2 instructions\n"));
1387 fprintf (stream
, _("\
1388 -mvle generate code for Freescale VLE instructions\n"));
1389 fprintf (stream
, _("\
1390 -mtitan generate code for AppliedMicro Titan core complex\n"));
1391 fprintf (stream
, _("\
1392 -mregnames Allow symbolic names for registers\n"));
1393 fprintf (stream
, _("\
1394 -mno-regnames Do not allow symbolic names for registers\n"));
1396 fprintf (stream
, _("\
1397 -mrelocatable support for GCC's -mrelocatble option\n"));
1398 fprintf (stream
, _("\
1399 -mrelocatable-lib support for GCC's -mrelocatble-lib option\n"));
1400 fprintf (stream
, _("\
1401 -memb set PPC_EMB bit in ELF flags\n"));
1402 fprintf (stream
, _("\
1403 -mlittle, -mlittle-endian, -le\n\
1404 generate code for a little endian machine\n"));
1405 fprintf (stream
, _("\
1406 -mbig, -mbig-endian, -be\n\
1407 generate code for a big endian machine\n"));
1408 fprintf (stream
, _("\
1409 -msolaris generate code for Solaris\n"));
1410 fprintf (stream
, _("\
1411 -mno-solaris do not generate code for Solaris\n"));
1412 fprintf (stream
, _("\
1413 -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n"));
1414 fprintf (stream
, _("\
1415 -V print assembler version number\n"));
1416 fprintf (stream
, _("\
1417 -Qy, -Qn ignored\n"));
1419 fprintf (stream
, _("\
1420 -nops=count when aligning, more than COUNT nops uses a branch\n"));
1421 fprintf (stream
, _("\
1422 -ppc476-workaround warn if emitting data to code sections\n"));
1425 /* Set ppc_cpu if it is not already set. */
1430 const char *default_os
= TARGET_OS
;
1431 const char *default_cpu
= TARGET_CPU
;
1433 if ((ppc_cpu
& ~(ppc_cpu_t
) PPC_OPCODE_ANY
) == 0)
1436 if (target_big_endian
)
1437 ppc_cpu
|= PPC_OPCODE_PPC
| PPC_OPCODE_64
;
1439 /* The minimum supported cpu for 64-bit little-endian is power8. */
1440 ppc_cpu
|= ppc_parse_cpu (ppc_cpu
, &sticky
, "power8");
1441 else if (strncmp (default_os
, "aix", 3) == 0
1442 && default_os
[3] >= '4' && default_os
[3] <= '9')
1443 ppc_cpu
|= PPC_OPCODE_COMMON
;
1444 else if (strncmp (default_os
, "aix3", 4) == 0)
1445 ppc_cpu
|= PPC_OPCODE_POWER
;
1446 else if (strcmp (default_cpu
, "rs6000") == 0)
1447 ppc_cpu
|= PPC_OPCODE_POWER
;
1448 else if (strncmp (default_cpu
, "powerpc", 7) == 0)
1449 ppc_cpu
|= PPC_OPCODE_PPC
;
1451 as_fatal (_("unknown default cpu = %s, os = %s"),
1452 default_cpu
, default_os
);
1456 /* Figure out the BFD architecture to use. This function and ppc_mach
1457 are called well before md_begin, when the output file is opened. */
1459 enum bfd_architecture
1462 const char *default_cpu
= TARGET_CPU
;
1465 if ((ppc_cpu
& PPC_OPCODE_PPC
) != 0)
1466 return bfd_arch_powerpc
;
1467 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
1468 return bfd_arch_powerpc
;
1469 if ((ppc_cpu
& PPC_OPCODE_POWER
) != 0)
1470 return bfd_arch_rs6000
;
1471 if ((ppc_cpu
& (PPC_OPCODE_COMMON
| PPC_OPCODE_ANY
)) != 0)
1473 if (strcmp (default_cpu
, "rs6000") == 0)
1474 return bfd_arch_rs6000
;
1475 else if (strncmp (default_cpu
, "powerpc", 7) == 0)
1476 return bfd_arch_powerpc
;
1479 as_fatal (_("neither Power nor PowerPC opcodes were selected."));
1480 return bfd_arch_unknown
;
1487 return bfd_mach_ppc64
;
1488 else if (ppc_arch () == bfd_arch_rs6000
)
1489 return bfd_mach_rs6k
;
1490 else if (ppc_cpu
& PPC_OPCODE_TITAN
)
1491 return bfd_mach_ppc_titan
;
1492 else if (ppc_cpu
& PPC_OPCODE_VLE
)
1493 return bfd_mach_ppc_vle
;
1495 return bfd_mach_ppc
;
1499 ppc_target_format (void)
1503 return "xcoff-powermac";
1506 return (ppc_obj64
? "aix5coff64-rs6000" : "aixcoff-rs6000");
1508 return (ppc_obj64
? "aixcoff64-rs6000" : "aixcoff-rs6000");
1514 return (ppc_obj64
? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd");
1515 # elif defined (TE_VXWORKS)
1516 return "elf32-powerpc-vxworks";
1518 return (target_big_endian
1519 ? (ppc_obj64
? "elf64-powerpc" : "elf32-powerpc")
1520 : (ppc_obj64
? "elf64-powerpcle" : "elf32-powerpcle"));
1525 /* Validate one entry in powerpc_opcodes[] or vle_opcodes[].
1526 Return TRUE if there's a problem, otherwise FALSE. */
1529 insn_validate (const struct powerpc_opcode
*op
)
1531 const unsigned char *o
;
1532 uint64_t omask
= op
->mask
;
1534 /* The mask had better not trim off opcode bits. */
1535 if ((op
->opcode
& omask
) != op
->opcode
)
1537 as_bad (_("mask trims opcode bits for %s"), op
->name
);
1541 /* The operands must not overlap the opcode or each other. */
1542 for (o
= op
->operands
; *o
; ++o
)
1544 bfd_boolean optional
= FALSE
;
1545 if (*o
>= num_powerpc_operands
)
1547 as_bad (_("operand index error for %s"), op
->name
);
1553 const struct powerpc_operand
*operand
= &powerpc_operands
[*o
];
1554 if (operand
->shift
== (int) PPC_OPSHIFT_INV
)
1561 if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
1563 else if ((operand
->flags
& PPC_OPERAND_PLUS1
) != 0)
1565 mask
= (*operand
->insert
) (0, val
, ppc_cpu
, &errmsg
);
1567 else if (operand
->shift
>= 0)
1568 mask
= operand
->bitm
<< operand
->shift
;
1570 mask
= operand
->bitm
>> -operand
->shift
;
1573 as_bad (_("operand %d overlap in %s"),
1574 (int) (o
- op
->operands
), op
->name
);
1578 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0)
1582 as_bad (_("non-optional operand %d follows optional operand in %s"),
1583 (int) (o
- op
->operands
), op
->name
);
1591 /* Insert opcodes and macros into hash tables. Called at startup and
1592 for .machine pseudo. */
1595 ppc_setup_opcodes (void)
1597 const struct powerpc_opcode
*op
;
1598 const struct powerpc_opcode
*op_end
;
1599 const struct powerpc_macro
*macro
;
1600 const struct powerpc_macro
*macro_end
;
1601 bfd_boolean bad_insn
= FALSE
;
1603 if (ppc_hash
!= NULL
)
1604 htab_delete (ppc_hash
);
1605 if (ppc_macro_hash
!= NULL
)
1606 htab_delete (ppc_macro_hash
);
1608 /* Insert the opcodes into a hash table. */
1609 ppc_hash
= str_htab_create ();
1611 if (ENABLE_CHECKING
)
1615 /* An index into powerpc_operands is stored in struct fix
1616 fx_pcrel_adjust which is 8 bits wide. */
1617 gas_assert (num_powerpc_operands
< 256);
1619 /* Check operand masks. Code here and in the disassembler assumes
1620 all the 1's in the mask are contiguous. */
1621 for (i
= 0; i
< num_powerpc_operands
; ++i
)
1623 uint64_t mask
= powerpc_operands
[i
].bitm
;
1627 right_bit
= mask
& -mask
;
1629 right_bit
= mask
& -mask
;
1630 if (mask
!= right_bit
)
1632 as_bad (_("powerpc_operands[%d].bitm invalid"), i
);
1635 for (j
= i
+ 1; j
< num_powerpc_operands
; ++j
)
1636 if (memcmp (&powerpc_operands
[i
], &powerpc_operands
[j
],
1637 sizeof (powerpc_operands
[0])) == 0)
1639 as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"),
1646 op_end
= powerpc_opcodes
+ powerpc_num_opcodes
;
1647 for (op
= powerpc_opcodes
; op
< op_end
; op
++)
1649 if (ENABLE_CHECKING
)
1651 unsigned int new_opcode
= PPC_OP (op
[0].opcode
);
1653 #ifdef PRINT_OPCODE_TABLE
1654 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1655 op
->name
, (unsigned int) (op
- powerpc_opcodes
),
1656 new_opcode
, (unsigned long long) op
->opcode
,
1657 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1660 /* The major opcodes had better be sorted. Code in the disassembler
1661 assumes the insns are sorted according to major opcode. */
1662 if (op
!= powerpc_opcodes
1663 && new_opcode
< PPC_OP (op
[-1].opcode
))
1665 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1669 if ((op
->flags
& PPC_OPCODE_VLE
) != 0)
1671 as_bad (_("%s is enabled by vle flag"), op
->name
);
1674 if (PPC_OP (op
->opcode
) != 4
1675 && PPC_OP (op
->opcode
) != 31
1676 && (op
->deprecated
& PPC_OPCODE_VLE
) == 0)
1678 as_bad (_("%s not disabled by vle flag"), op
->name
);
1681 bad_insn
|= insn_validate (op
);
1684 if ((ppc_cpu
& op
->flags
) != 0
1685 && !(ppc_cpu
& op
->deprecated
))
1686 str_hash_insert (ppc_hash
, op
->name
, (void *) op
);
1689 if ((ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1690 for (op
= powerpc_opcodes
; op
< op_end
; op
++)
1691 str_hash_insert (ppc_hash
, op
->name
, (void *) op
);
1693 op_end
= prefix_opcodes
+ prefix_num_opcodes
;
1694 for (op
= prefix_opcodes
; op
< op_end
; op
++)
1696 if (ENABLE_CHECKING
)
1698 unsigned int new_opcode
= PPC_PREFIX_SEG (op
[0].opcode
);
1700 #ifdef PRINT_OPCODE_TABLE
1701 printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1702 op
->name
, (unsigned int) (op
- prefix_opcodes
),
1703 new_opcode
, (unsigned long long) op
->opcode
,
1704 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1707 /* The major opcodes had better be sorted. Code in the disassembler
1708 assumes the insns are sorted according to major opcode. */
1709 if (op
!= prefix_opcodes
1710 && new_opcode
< PPC_PREFIX_SEG (op
[-1].opcode
))
1712 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1715 bad_insn
|= insn_validate (op
);
1718 if ((ppc_cpu
& op
->flags
) != 0
1719 && !(ppc_cpu
& op
->deprecated
))
1720 str_hash_insert (ppc_hash
, op
->name
, (void *) op
);
1723 if ((ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1724 for (op
= prefix_opcodes
; op
< op_end
; op
++)
1725 str_hash_insert (ppc_hash
, op
->name
, (void *) op
);
1727 op_end
= vle_opcodes
+ vle_num_opcodes
;
1728 for (op
= vle_opcodes
; op
< op_end
; op
++)
1730 if (ENABLE_CHECKING
)
1732 unsigned new_seg
= VLE_OP_TO_SEG (VLE_OP (op
[0].opcode
, op
[0].mask
));
1734 #ifdef PRINT_OPCODE_TABLE
1735 printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n",
1736 op
->name
, (unsigned int) (op
- vle_opcodes
),
1737 (unsigned int) new_seg
, (unsigned long long) op
->opcode
,
1738 (unsigned long long) op
->mask
, (unsigned long long) op
->flags
);
1741 /* The major opcodes had better be sorted. Code in the disassembler
1742 assumes the insns are sorted according to major opcode. */
1743 if (op
!= vle_opcodes
1744 && new_seg
< VLE_OP_TO_SEG (VLE_OP (op
[-1].opcode
, op
[-1].mask
)))
1746 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1750 bad_insn
|= insn_validate (op
);
1753 if ((ppc_cpu
& op
->flags
) != 0
1754 && !(ppc_cpu
& op
->deprecated
))
1755 str_hash_insert (ppc_hash
, op
->name
, (void *) op
);
1758 /* SPE2 instructions */
1759 if ((ppc_cpu
& PPC_OPCODE_SPE2
) == PPC_OPCODE_SPE2
)
1761 op_end
= spe2_opcodes
+ spe2_num_opcodes
;
1762 for (op
= spe2_opcodes
; op
< op_end
; op
++)
1764 if (ENABLE_CHECKING
)
1766 if (op
!= spe2_opcodes
)
1768 unsigned old_seg
, new_seg
;
1770 old_seg
= VLE_OP (op
[-1].opcode
, op
[-1].mask
);
1771 old_seg
= VLE_OP_TO_SEG (old_seg
);
1772 new_seg
= VLE_OP (op
[0].opcode
, op
[0].mask
);
1773 new_seg
= VLE_OP_TO_SEG (new_seg
);
1775 /* The major opcodes had better be sorted. Code in the
1776 disassembler assumes the insns are sorted according to
1778 if (new_seg
< old_seg
)
1780 as_bad (_("major opcode is not sorted for %s"), op
->name
);
1785 bad_insn
|= insn_validate (op
);
1788 if ((ppc_cpu
& op
->flags
) != 0 && !(ppc_cpu
& op
->deprecated
))
1789 str_hash_insert (ppc_hash
, op
->name
, (void *) op
);
1792 for (op
= spe2_opcodes
; op
< op_end
; op
++)
1793 str_hash_insert (ppc_hash
, op
->name
, (void *) op
);
1796 /* Insert the macros into a hash table. */
1797 ppc_macro_hash
= str_htab_create ();
1799 macro_end
= powerpc_macros
+ powerpc_num_macros
;
1800 for (macro
= powerpc_macros
; macro
< macro_end
; macro
++)
1802 if ((macro
->flags
& ppc_cpu
) != 0 || (ppc_cpu
& PPC_OPCODE_ANY
) != 0)
1803 str_hash_insert (ppc_macro_hash
, macro
->name
, (void *) macro
);
1810 /* This function is called when the assembler starts up. It is called
1811 after the options have been parsed and the output file has been
1819 ppc_cie_data_alignment
= ppc_obj64
? -8 : -4;
1820 ppc_dwarf2_line_min_insn_length
= (ppc_cpu
& PPC_OPCODE_VLE
) ? 2 : 4;
1823 /* Set the ELF flags if desired. */
1824 if (ppc_flags
&& !msolaris
)
1825 bfd_set_private_flags (stdoutput
, ppc_flags
);
1828 ppc_setup_opcodes ();
1830 /* Tell the main code what the endianness is if it is not overridden
1832 if (!set_target_endian
)
1834 set_target_endian
= 1;
1835 target_big_endian
= PPC_BIG_ENDIAN
;
1839 ppc_coff_debug_section
= coff_section_from_bfd_index (stdoutput
, N_DEBUG
);
1841 /* Create dummy symbols to serve as initial csects. This forces the
1842 text csects to precede the data csects. These symbols will not
1844 ppc_text_csects
= symbol_make ("dummy\001");
1845 symbol_get_tc (ppc_text_csects
)->within
= ppc_text_csects
;
1846 ppc_data_csects
= symbol_make ("dummy\001");
1847 symbol_get_tc (ppc_data_csects
)->within
= ppc_data_csects
;
1855 if (ppc_apuinfo_list
== NULL
)
1858 /* Ok, so write the section info out. We have this layout:
1862 0 8 length of "APUinfo\0"
1863 4 (n*4) number of APU's (4 bytes each)
1866 20 APU#1 first APU's info
1867 24 APU#2 second APU's info
1872 asection
*seg
= now_seg
;
1873 subsegT subseg
= now_subseg
;
1874 asection
*apuinfo_secp
= (asection
*) NULL
;
1877 /* Create the .PPC.EMB.apuinfo section. */
1878 apuinfo_secp
= subseg_new (APUINFO_SECTION_NAME
, 0);
1879 bfd_set_section_flags (apuinfo_secp
, SEC_HAS_CONTENTS
| SEC_READONLY
);
1882 md_number_to_chars (p
, (valueT
) 8, 4);
1885 md_number_to_chars (p
, (valueT
) ppc_apuinfo_num
* 4, 4);
1888 md_number_to_chars (p
, (valueT
) 2, 4);
1891 strcpy (p
, APUINFO_LABEL
);
1893 for (i
= 0; i
< ppc_apuinfo_num
; i
++)
1896 md_number_to_chars (p
, (valueT
) ppc_apuinfo_list
[i
], 4);
1899 frag_align (2, 0, 0);
1901 /* We probably can't restore the current segment, for there likely
1904 subseg_set (seg
, subseg
);
1909 /* Insert an operand value into an instruction. */
1912 ppc_insert_operand (uint64_t insn
,
1913 const struct powerpc_operand
*operand
,
1919 int64_t min
, max
, right
;
1921 max
= operand
->bitm
;
1925 if ((operand
->flags
& PPC_OPERAND_SIGNOPT
) != 0)
1927 /* Extend the allowed range for addis to [-32768, 65535].
1928 Similarly for cmpli and some VLE high part insns. For 64-bit
1929 it would be good to disable this for signed fields since the
1930 value is sign extended into the high 32 bits of the register.
1931 If the value is, say, an address, then we might care about
1932 the high bits. However, gcc as of 2014-06 uses unsigned
1933 values when loading the high part of 64-bit constants using
1935 min
= ~(max
>> 1) & -right
;
1937 else if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
1939 max
= (max
>> 1) & -right
;
1940 min
= ~max
& -right
;
1943 if ((operand
->flags
& PPC_OPERAND_PLUS1
) != 0)
1946 if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
1955 /* Some people write constants with the sign extension done by
1956 hand but only up to 32 bits. This shouldn't really be valid,
1957 but, to permit this code to assemble on a 64-bit host, we
1958 sign extend the 32-bit value to 64 bits if so doing makes the
1959 value valid. We only do this for operands that are 32-bits or
1962 && (operand
->bitm
& ~0xffffffffULL
) == 0
1963 && (val
- (1LL << 32)) >= min
1964 && (val
- (1LL << 32)) <= max
1965 && ((val
- (1LL << 32)) & (right
- 1)) == 0)
1966 val
= val
- (1LL << 32);
1968 /* Similarly, people write expressions like ~(1<<15), and expect
1969 this to be OK for a 32-bit unsigned value. */
1971 && (operand
->bitm
& ~0xffffffffULL
) == 0
1972 && (val
+ (1LL << 32)) >= min
1973 && (val
+ (1LL << 32)) <= max
1974 && ((val
+ (1LL << 32)) & (right
- 1)) == 0)
1975 val
= val
+ (1LL << 32);
1979 || (val
& (right
- 1)) != 0)
1980 as_bad_value_out_of_range (_("operand"), val
, min
, max
, file
, line
);
1983 if (operand
->insert
)
1988 insn
= (*operand
->insert
) (insn
, val
, cpu
, &errmsg
);
1989 if (errmsg
!= (const char *) NULL
)
1990 as_bad_where (file
, line
, "%s", errmsg
);
1992 else if (operand
->shift
>= 0)
1993 insn
|= (val
& operand
->bitm
) << operand
->shift
;
1995 insn
|= (val
& operand
->bitm
) >> -operand
->shift
;
2002 /* Parse @got, etc. and return the desired relocation. */
2003 static bfd_reloc_code_real_type
2004 ppc_elf_suffix (char **str_p
, expressionS
*exp_p
)
2008 unsigned int length
: 8;
2009 unsigned int valid32
: 1;
2010 unsigned int valid64
: 1;
2019 const struct map_bfd
*ptr
;
2021 #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc }
2022 #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc }
2023 #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc }
2025 static const struct map_bfd mapping
[] = {
2026 MAP ("l", BFD_RELOC_LO16
),
2027 MAP ("h", BFD_RELOC_HI16
),
2028 MAP ("ha", BFD_RELOC_HI16_S
),
2029 MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN
),
2030 MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN
),
2031 MAP ("got", BFD_RELOC_16_GOTOFF
),
2032 MAP ("got@l", BFD_RELOC_LO16_GOTOFF
),
2033 MAP ("got@h", BFD_RELOC_HI16_GOTOFF
),
2034 MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF
),
2035 MAP ("plt@l", BFD_RELOC_LO16_PLTOFF
),
2036 MAP ("plt@h", BFD_RELOC_HI16_PLTOFF
),
2037 MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF
),
2038 MAP ("copy", BFD_RELOC_PPC_COPY
),
2039 MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT
),
2040 MAP ("sectoff", BFD_RELOC_16_BASEREL
),
2041 MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL
),
2042 MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL
),
2043 MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL
),
2044 MAP ("tls", BFD_RELOC_PPC_TLS
),
2045 MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD
),
2046 MAP ("dtprel", BFD_RELOC_PPC_DTPREL
),
2047 MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO
),
2048 MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI
),
2049 MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA
),
2050 MAP ("tprel", BFD_RELOC_PPC_TPREL
),
2051 MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO
),
2052 MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI
),
2053 MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA
),
2054 MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16
),
2055 MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO
),
2056 MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI
),
2057 MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA
),
2058 MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16
),
2059 MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO
),
2060 MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI
),
2061 MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA
),
2062 MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16
),
2063 MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO
),
2064 MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI
),
2065 MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA
),
2066 MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16
),
2067 MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO
),
2068 MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI
),
2069 MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA
),
2070 MAP32 ("fixup", BFD_RELOC_CTOR
),
2071 MAP32 ("plt", BFD_RELOC_24_PLT_PCREL
),
2072 MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL
),
2073 MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC
),
2074 MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC
),
2075 MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL
),
2076 MAP32 ("sdarel", BFD_RELOC_GPREL16
),
2077 MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A
),
2078 MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A
),
2079 MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A
),
2080 MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32
),
2081 MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16
),
2082 MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO
),
2083 MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI
),
2084 MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA
),
2085 MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16
),
2086 MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL
),
2087 MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16
),
2088 MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21
),
2089 MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO
),
2090 MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF
),
2091 MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16
),
2092 MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO
),
2093 MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI
),
2094 MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA
),
2095 MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD
),
2096 MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA
),
2097 MAP32 ("xgot", BFD_RELOC_PPC_TOC16
),
2098 MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH
),
2099 MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA
),
2100 MAP64 ("higher", BFD_RELOC_PPC64_HIGHER
),
2101 MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S
),
2102 MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST
),
2103 MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S
),
2104 MAP64 ("tocbase", BFD_RELOC_PPC64_TOC
),
2105 MAP64 ("toc", BFD_RELOC_PPC_TOC16
),
2106 MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO
),
2107 MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI
),
2108 MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA
),
2109 MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH
),
2110 MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA
),
2111 MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER
),
2112 MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA
),
2113 MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST
),
2114 MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA
),
2115 MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL
),
2116 MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH
),
2117 MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA
),
2118 MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER
),
2119 MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA
),
2120 MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST
),
2121 MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA
),
2122 MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC
),
2123 MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34
),
2124 MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34
),
2125 MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34
),
2126 MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL
),
2127 MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
),
2128 MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
),
2129 MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34
),
2130 MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
),
2131 MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34
),
2132 MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34
),
2133 MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34
),
2134 MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34
),
2135 { (char *) 0, 0, 0, 0, BFD_RELOC_NONE
}
2139 return BFD_RELOC_NONE
;
2141 for (ch
= *str
, str2
= ident
;
2142 (str2
< ident
+ sizeof (ident
) - 1
2143 && (ISALNUM (ch
) || ch
== '@'));
2146 *str2
++ = TOLOWER (ch
);
2153 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
2154 if (ch
== ptr
->string
[0]
2155 && len
== ptr
->length
2156 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0
2157 && (ppc_obj64
? ptr
->valid64
: ptr
->valid32
))
2159 int reloc
= ptr
->reloc
;
2161 if (!ppc_obj64
&& exp_p
->X_add_number
!= 0)
2165 case BFD_RELOC_16_GOTOFF
:
2166 case BFD_RELOC_LO16_GOTOFF
:
2167 case BFD_RELOC_HI16_GOTOFF
:
2168 case BFD_RELOC_HI16_S_GOTOFF
:
2169 as_warn (_("symbol+offset@%s means symbol@%s+offset"),
2170 ptr
->string
, ptr
->string
);
2173 case BFD_RELOC_PPC_GOT_TLSGD16
:
2174 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
2175 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
2176 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
2177 case BFD_RELOC_PPC_GOT_TLSLD16
:
2178 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
2179 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
2180 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
2181 case BFD_RELOC_PPC_GOT_DTPREL16
:
2182 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
2183 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
2184 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
2185 case BFD_RELOC_PPC_GOT_TPREL16
:
2186 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
2187 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
2188 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
2189 as_bad (_("symbol+offset@%s not supported"), ptr
->string
);
2194 /* Now check for identifier@suffix+constant. */
2195 if (*str
== '-' || *str
== '+')
2197 char *orig_line
= input_line_pointer
;
2198 expressionS new_exp
;
2200 input_line_pointer
= str
;
2201 expression (&new_exp
);
2202 if (new_exp
.X_op
== O_constant
)
2204 exp_p
->X_add_number
+= new_exp
.X_add_number
;
2205 str
= input_line_pointer
;
2208 if (&input_line_pointer
!= str_p
)
2209 input_line_pointer
= orig_line
;
2213 if (reloc
== (int) BFD_RELOC_PPC64_TOC
2214 && exp_p
->X_op
== O_symbol
2215 && strcmp (S_GET_NAME (exp_p
->X_add_symbol
), ".TOC.") == 0)
2217 /* Change the symbol so that the dummy .TOC. symbol can be
2218 omitted from the object file. */
2219 exp_p
->X_add_symbol
= &abs_symbol
;
2222 return (bfd_reloc_code_real_type
) reloc
;
2225 return BFD_RELOC_NONE
;
2228 /* Support @got, etc. on constants emitted via .short, .int etc. */
2230 bfd_reloc_code_real_type
2231 ppc_elf_parse_cons (expressionS
*exp
, unsigned int nbytes
)
2234 if (nbytes
>= 2 && *input_line_pointer
== '@')
2235 return ppc_elf_suffix (&input_line_pointer
, exp
);
2236 return BFD_RELOC_NONE
;
2239 /* Warn when emitting data to code sections, unless we are emitting
2240 a relocation that ld --ppc476-workaround uses to recognise data
2241 *and* there was an unconditional branch prior to the data. */
2244 ppc_elf_cons_fix_check (expressionS
*exp ATTRIBUTE_UNUSED
,
2245 unsigned int nbytes
, fixS
*fix
)
2248 && (now_seg
->flags
& SEC_CODE
) != 0
2251 || !(fix
->fx_r_type
== BFD_RELOC_32
2252 || fix
->fx_r_type
== BFD_RELOC_CTOR
2253 || fix
->fx_r_type
== BFD_RELOC_32_PCREL
)
2254 || !(last_seg
== now_seg
&& last_subseg
== now_subseg
)
2255 || !((last_insn
& (0x3f << 26)) == (18u << 26)
2256 || ((last_insn
& (0x3f << 26)) == (16u << 26)
2257 && (last_insn
& (0x14 << 21)) == (0x14 << 21))
2258 || ((last_insn
& (0x3f << 26)) == (19u << 26)
2259 && (last_insn
& (0x3ff << 1)) == (16u << 1)
2260 && (last_insn
& (0x14 << 21)) == (0x14 << 21)))))
2262 /* Flag that we've warned. */
2266 as_warn (_("data in executable section"));
2270 /* Solaris pseduo op to change to the .rodata section. */
2272 ppc_elf_rdata (int xxx
)
2274 char *save_line
= input_line_pointer
;
2275 static char section
[] = ".rodata\n";
2277 /* Just pretend this is .section .rodata */
2278 input_line_pointer
= section
;
2279 obj_elf_section (xxx
);
2281 input_line_pointer
= save_line
;
2284 /* Pseudo op to make file scope bss items. */
2286 ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED
)
2299 c
= get_symbol_name (&name
);
2301 /* Just after name is now '\0'. */
2302 p
= input_line_pointer
;
2304 SKIP_WHITESPACE_AFTER_NAME ();
2305 if (*input_line_pointer
!= ',')
2307 as_bad (_("expected comma after symbol-name: rest of line ignored."));
2308 ignore_rest_of_line ();
2312 input_line_pointer
++; /* skip ',' */
2313 if ((size
= get_absolute_expression ()) < 0)
2315 as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size
);
2316 ignore_rest_of_line ();
2320 /* The third argument to .lcomm is the alignment. */
2321 if (*input_line_pointer
!= ',')
2325 ++input_line_pointer
;
2326 align
= get_absolute_expression ();
2329 as_warn (_("ignoring bad alignment"));
2335 symbolP
= symbol_find_or_make (name
);
2338 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
2340 as_bad (_("ignoring attempt to re-define symbol `%s'."),
2341 S_GET_NAME (symbolP
));
2342 ignore_rest_of_line ();
2346 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
2348 as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."),
2349 S_GET_NAME (symbolP
),
2350 (long) S_GET_VALUE (symbolP
),
2353 ignore_rest_of_line ();
2359 old_subsec
= now_subseg
;
2362 /* Convert to a power of 2 alignment. */
2363 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++align2
);
2366 as_bad (_("common alignment not a power of 2"));
2367 ignore_rest_of_line ();
2374 record_alignment (bss_section
, align2
);
2375 subseg_set (bss_section
, 1);
2377 frag_align (align2
, 0, 0);
2378 if (S_GET_SEGMENT (symbolP
) == bss_section
)
2379 symbol_get_frag (symbolP
)->fr_symbol
= 0;
2380 symbol_set_frag (symbolP
, frag_now
);
2381 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
2384 S_SET_SIZE (symbolP
, size
);
2385 S_SET_SEGMENT (symbolP
, bss_section
);
2386 subseg_set (old_sec
, old_subsec
);
2387 demand_empty_rest_of_line ();
2390 /* Pseudo op to set symbol local entry point. */
2392 ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED
)
2395 char c
= get_symbol_name (&name
);
2400 elf_symbol_type
*elfsym
;
2402 p
= input_line_pointer
;
2404 SKIP_WHITESPACE_AFTER_NAME ();
2405 if (*input_line_pointer
!= ',')
2408 as_bad (_("expected comma after name `%s' in .localentry directive"),
2411 ignore_rest_of_line ();
2414 input_line_pointer
++;
2416 if (exp
.X_op
== O_absent
)
2418 as_bad (_("missing expression in .localentry directive"));
2419 exp
.X_op
= O_constant
;
2420 exp
.X_add_number
= 0;
2423 sym
= symbol_find_or_make (name
);
2426 if (resolve_expression (&exp
)
2427 && exp
.X_op
== O_constant
)
2429 unsigned int encoded
, ok
;
2432 if (exp
.X_add_number
== 1 || exp
.X_add_number
== 7)
2433 encoded
= exp
.X_add_number
<< STO_PPC64_LOCAL_BIT
;
2436 encoded
= PPC64_SET_LOCAL_ENTRY_OFFSET (exp
.X_add_number
);
2437 if (exp
.X_add_number
!= (offsetT
) PPC64_LOCAL_ENTRY_OFFSET (encoded
))
2439 as_bad (_(".localentry expression for `%s' "
2440 "is not a valid power of 2"), S_GET_NAME (sym
));
2446 bfdsym
= symbol_get_bfdsym (sym
);
2447 elfsym
= elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
2448 gas_assert (elfsym
);
2449 elfsym
->internal_elf_sym
.st_other
&= ~STO_PPC64_LOCAL_MASK
;
2450 elfsym
->internal_elf_sym
.st_other
|= encoded
;
2451 if (ppc_abiversion
== 0)
2456 as_bad (_(".localentry expression for `%s' "
2457 "does not evaluate to a constant"), S_GET_NAME (sym
));
2459 demand_empty_rest_of_line ();
2462 /* Pseudo op to set ABI version. */
2464 ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED
)
2469 if (exp
.X_op
== O_absent
)
2471 as_bad (_("missing expression in .abiversion directive"));
2472 exp
.X_op
= O_constant
;
2473 exp
.X_add_number
= 0;
2476 if (resolve_expression (&exp
)
2477 && exp
.X_op
== O_constant
)
2478 ppc_abiversion
= exp
.X_add_number
;
2480 as_bad (_(".abiversion expression does not evaluate to a constant"));
2481 demand_empty_rest_of_line ();
2484 /* Parse a .gnu_attribute directive. */
2486 ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED
)
2488 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_GNU
);
2490 /* Check validity of defined powerpc tags. */
2491 if (tag
== Tag_GNU_Power_ABI_FP
2492 || tag
== Tag_GNU_Power_ABI_Vector
2493 || tag
== Tag_GNU_Power_ABI_Struct_Return
)
2497 val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, tag
);
2499 if ((tag
== Tag_GNU_Power_ABI_FP
&& val
> 15)
2500 || (tag
== Tag_GNU_Power_ABI_Vector
&& val
> 3)
2501 || (tag
== Tag_GNU_Power_ABI_Struct_Return
&& val
> 2))
2502 as_warn (_("unknown .gnu_attribute value"));
2506 /* Set ABI version in output file. */
2510 if (ppc_obj64
&& ppc_abiversion
!= 0)
2512 elf_elfheader (stdoutput
)->e_flags
&= ~EF_PPC64_ABI
;
2513 elf_elfheader (stdoutput
)->e_flags
|= ppc_abiversion
& EF_PPC64_ABI
;
2515 /* Any selection of opcodes based on ppc_cpu after gas has finished
2516 parsing the file is invalid. md_apply_fix and ppc_handle_align
2517 must select opcodes based on the machine in force at the point
2518 where the fixup or alignment frag was created, not the machine in
2519 force at the end of file. */
2523 /* Validate any relocations emitted for -mrelocatable, possibly adding
2524 fixups for word relocations in writable segments, so we can adjust
2527 ppc_elf_validate_fix (fixS
*fixp
, segT seg
)
2529 if (fixp
->fx_done
|| fixp
->fx_pcrel
)
2538 case SHLIB_MRELOCATABLE
:
2539 if (fixp
->fx_r_type
!= BFD_RELOC_16_GOTOFF
2540 && fixp
->fx_r_type
!= BFD_RELOC_HI16_GOTOFF
2541 && fixp
->fx_r_type
!= BFD_RELOC_LO16_GOTOFF
2542 && fixp
->fx_r_type
!= BFD_RELOC_HI16_S_GOTOFF
2543 && fixp
->fx_r_type
!= BFD_RELOC_16_BASEREL
2544 && fixp
->fx_r_type
!= BFD_RELOC_LO16_BASEREL
2545 && fixp
->fx_r_type
!= BFD_RELOC_HI16_BASEREL
2546 && fixp
->fx_r_type
!= BFD_RELOC_HI16_S_BASEREL
2547 && (seg
->flags
& SEC_LOAD
) != 0
2548 && strcmp (segment_name (seg
), ".got2") != 0
2549 && strcmp (segment_name (seg
), ".dtors") != 0
2550 && strcmp (segment_name (seg
), ".ctors") != 0
2551 && strcmp (segment_name (seg
), ".fixup") != 0
2552 && strcmp (segment_name (seg
), ".gcc_except_table") != 0
2553 && strcmp (segment_name (seg
), ".eh_frame") != 0
2554 && strcmp (segment_name (seg
), ".ex_shared") != 0)
2556 if ((seg
->flags
& (SEC_READONLY
| SEC_CODE
)) != 0
2557 || fixp
->fx_r_type
!= BFD_RELOC_CTOR
)
2559 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2560 _("relocation cannot be done when using -mrelocatable"));
2567 /* Prevent elf_frob_file_before_adjust removing a weak undefined
2568 function descriptor sym if the corresponding code sym is used. */
2571 ppc_frob_file_before_adjust (void)
2579 for (symp
= symbol_rootP
; symp
; symp
= symbol_next (symp
))
2585 name
= S_GET_NAME (symp
);
2589 if (! S_IS_WEAK (symp
)
2590 || S_IS_DEFINED (symp
))
2593 dotname
= concat (".", name
, (char *) NULL
);
2594 dotsym
= symbol_find_noref (dotname
, 1);
2596 if (dotsym
!= NULL
&& (symbol_used_p (dotsym
)
2597 || symbol_used_in_reloc_p (dotsym
)))
2598 symbol_mark_used (symp
);
2602 toc
= bfd_get_section_by_name (stdoutput
, ".toc");
2604 && toc_reloc_types
!= has_large_toc_reloc
2605 && bfd_section_size (toc
) > 0x10000)
2606 as_warn (_("TOC section size exceeds 64k"));
2609 /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be
2610 emitted. Other uses of .TOC. will cause the symbol to be marked
2611 with BSF_KEEP in md_apply_fix. */
2614 ppc_elf_adjust_symtab (void)
2619 symp
= symbol_find (".TOC.");
2622 asymbol
*bsym
= symbol_get_bfdsym (symp
);
2623 if ((bsym
->flags
& BSF_KEEP
) == 0)
2624 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2628 #endif /* OBJ_ELF */
2630 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
2631 /* See whether a symbol is in the TOC section. */
2634 ppc_is_toc_sym (symbolS
*sym
)
2637 return (symbol_get_tc (sym
)->symbol_class
== XMC_TC
2638 || symbol_get_tc (sym
)->symbol_class
== XMC_TC0
);
2641 const char *sname
= segment_name (S_GET_SEGMENT (sym
));
2643 return strcmp (sname
, ".toc") == 0;
2645 return strcmp (sname
, ".got") == 0;
2648 #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
2652 #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff))
2654 ppc_apuinfo_section_add (unsigned int apu
, unsigned int version
)
2658 /* Check we don't already exist. */
2659 for (i
= 0; i
< ppc_apuinfo_num
; i
++)
2660 if (ppc_apuinfo_list
[i
] == APUID (apu
, version
))
2663 if (ppc_apuinfo_num
== ppc_apuinfo_num_alloc
)
2665 if (ppc_apuinfo_num_alloc
== 0)
2667 ppc_apuinfo_num_alloc
= 4;
2668 ppc_apuinfo_list
= XNEWVEC (unsigned long, ppc_apuinfo_num_alloc
);
2672 ppc_apuinfo_num_alloc
+= 4;
2673 ppc_apuinfo_list
= XRESIZEVEC (unsigned long, ppc_apuinfo_list
,
2674 ppc_apuinfo_num_alloc
);
2677 ppc_apuinfo_list
[ppc_apuinfo_num
++] = APUID (apu
, version
);
2682 /* Various frobbings of labels and their addresses. */
2684 /* Symbols labelling the current insn. */
2685 struct insn_label_list
2687 struct insn_label_list
*next
;
2691 static struct insn_label_list
*insn_labels
;
2692 static struct insn_label_list
*free_insn_labels
;
2695 ppc_record_label (symbolS
*sym
)
2697 struct insn_label_list
*l
;
2699 if (free_insn_labels
== NULL
)
2700 l
= XNEW (struct insn_label_list
);
2703 l
= free_insn_labels
;
2704 free_insn_labels
= l
->next
;
2708 l
->next
= insn_labels
;
2713 ppc_clear_labels (void)
2715 while (insn_labels
!= NULL
)
2717 struct insn_label_list
*l
= insn_labels
;
2718 insn_labels
= l
->next
;
2719 l
->next
= free_insn_labels
;
2720 free_insn_labels
= l
;
2725 ppc_start_line_hook (void)
2727 ppc_clear_labels ();
2731 ppc_new_dot_label (symbolS
*sym
)
2733 ppc_record_label (sym
);
2735 /* Anchor this label to the current csect for relocations. */
2736 symbol_get_tc (sym
)->within
= ppc_current_csect
;
2741 ppc_frob_label (symbolS
*sym
)
2743 ppc_record_label (sym
);
2746 /* Set the class of a label based on where it is defined. This handles
2747 symbols without suffixes. Also, move the symbol so that it follows
2748 the csect symbol. */
2749 if (ppc_current_csect
!= (symbolS
*) NULL
)
2751 if (symbol_get_tc (sym
)->symbol_class
== -1)
2752 symbol_get_tc (sym
)->symbol_class
= symbol_get_tc (ppc_current_csect
)->symbol_class
;
2754 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
2755 symbol_append (sym
, symbol_get_tc (ppc_current_csect
)->within
,
2756 &symbol_rootP
, &symbol_lastP
);
2757 symbol_get_tc (ppc_current_csect
)->within
= sym
;
2758 symbol_get_tc (sym
)->within
= ppc_current_csect
;
2763 dwarf2_emit_label (sym
);
2767 /* We need to keep a list of fixups. We can't simply generate them as
2768 we go, because that would require us to first create the frag, and
2769 that would screw up references to ``.''. */
2775 bfd_reloc_code_real_type reloc
;
2778 #define MAX_INSN_FIXUPS (5)
2780 /* Return the field size operated on by RELOC, and whether it is
2781 pc-relative in PC_RELATIVE. */
2784 fixup_size (bfd_reloc_code_real_type reloc
, bfd_boolean
*pc_relative
)
2786 unsigned int size
= 0;
2787 bfd_boolean pcrel
= FALSE
;
2791 /* This switch statement must handle all BFD_RELOC values
2792 possible in instruction fixups. As is, it handles all
2793 BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c,
2794 bfd/coff-rs6000.c and bfd/coff64-rs6000.c.
2795 Overkill since data and marker relocs need not be handled
2796 here, but this way we can be sure a needed fixup reloc isn't
2797 accidentally omitted. */
2798 case BFD_RELOC_PPC_EMB_MRKREF
:
2799 case BFD_RELOC_VTABLE_ENTRY
:
2800 case BFD_RELOC_VTABLE_INHERIT
:
2808 case BFD_RELOC_16_BASEREL
:
2809 case BFD_RELOC_16_GOTOFF
:
2810 case BFD_RELOC_GPREL16
:
2811 case BFD_RELOC_HI16
:
2812 case BFD_RELOC_HI16_BASEREL
:
2813 case BFD_RELOC_HI16_GOTOFF
:
2814 case BFD_RELOC_HI16_PLTOFF
:
2815 case BFD_RELOC_HI16_S
:
2816 case BFD_RELOC_HI16_S_BASEREL
:
2817 case BFD_RELOC_HI16_S_GOTOFF
:
2818 case BFD_RELOC_HI16_S_PLTOFF
:
2819 case BFD_RELOC_LO16
:
2820 case BFD_RELOC_LO16_BASEREL
:
2821 case BFD_RELOC_LO16_GOTOFF
:
2822 case BFD_RELOC_LO16_PLTOFF
:
2823 case BFD_RELOC_PPC64_ADDR16_DS
:
2824 case BFD_RELOC_PPC64_ADDR16_HIGH
:
2825 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
2826 case BFD_RELOC_PPC64_ADDR16_HIGHER34
:
2827 case BFD_RELOC_PPC64_ADDR16_HIGHERA34
:
2828 case BFD_RELOC_PPC64_ADDR16_HIGHEST34
:
2829 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34
:
2830 case BFD_RELOC_PPC64_ADDR16_LO_DS
:
2831 case BFD_RELOC_PPC64_DTPREL16_DS
:
2832 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
2833 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
2834 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
2835 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
2836 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
2837 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
2838 case BFD_RELOC_PPC64_DTPREL16_LO_DS
:
2839 case BFD_RELOC_PPC64_GOT16_DS
:
2840 case BFD_RELOC_PPC64_GOT16_LO_DS
:
2841 case BFD_RELOC_PPC64_HIGHER
:
2842 case BFD_RELOC_PPC64_HIGHER_S
:
2843 case BFD_RELOC_PPC64_HIGHEST
:
2844 case BFD_RELOC_PPC64_HIGHEST_S
:
2845 case BFD_RELOC_PPC64_PLT16_LO_DS
:
2846 case BFD_RELOC_PPC64_PLTGOT16
:
2847 case BFD_RELOC_PPC64_PLTGOT16_DS
:
2848 case BFD_RELOC_PPC64_PLTGOT16_HA
:
2849 case BFD_RELOC_PPC64_PLTGOT16_HI
:
2850 case BFD_RELOC_PPC64_PLTGOT16_LO
:
2851 case BFD_RELOC_PPC64_PLTGOT16_LO_DS
:
2852 case BFD_RELOC_PPC64_SECTOFF_DS
:
2853 case BFD_RELOC_PPC64_SECTOFF_LO_DS
:
2854 case BFD_RELOC_PPC64_TOC16_DS
:
2855 case BFD_RELOC_PPC64_TOC16_HA
:
2856 case BFD_RELOC_PPC64_TOC16_HI
:
2857 case BFD_RELOC_PPC64_TOC16_LO
:
2858 case BFD_RELOC_PPC64_TOC16_LO_DS
:
2859 case BFD_RELOC_PPC64_TPREL16_DS
:
2860 case BFD_RELOC_PPC64_TPREL16_HIGH
:
2861 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
2862 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
2863 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
2864 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
2865 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
2866 case BFD_RELOC_PPC64_TPREL16_LO_DS
:
2868 case BFD_RELOC_PPC_BA16
:
2870 case BFD_RELOC_PPC_DTPREL16
:
2871 case BFD_RELOC_PPC_DTPREL16_HA
:
2872 case BFD_RELOC_PPC_DTPREL16_HI
:
2873 case BFD_RELOC_PPC_DTPREL16_LO
:
2874 case BFD_RELOC_PPC_EMB_NADDR16
:
2875 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
2876 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
2877 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
2878 case BFD_RELOC_PPC_EMB_RELSDA
:
2879 case BFD_RELOC_PPC_EMB_RELSEC16
:
2880 case BFD_RELOC_PPC_EMB_RELST_LO
:
2881 case BFD_RELOC_PPC_EMB_RELST_HI
:
2882 case BFD_RELOC_PPC_EMB_RELST_HA
:
2883 case BFD_RELOC_PPC_EMB_SDA2I16
:
2884 case BFD_RELOC_PPC_EMB_SDA2REL
:
2885 case BFD_RELOC_PPC_EMB_SDAI16
:
2886 case BFD_RELOC_PPC_GOT_DTPREL16
:
2887 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
2888 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
2889 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
2890 case BFD_RELOC_PPC_GOT_TLSGD16
:
2891 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
2892 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
2893 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
2894 case BFD_RELOC_PPC_GOT_TLSLD16
:
2895 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
2896 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
2897 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
2898 case BFD_RELOC_PPC_GOT_TPREL16
:
2899 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
2900 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
2901 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
2902 case BFD_RELOC_PPC_TOC16
:
2903 case BFD_RELOC_PPC_TPREL16
:
2904 case BFD_RELOC_PPC_TPREL16_HA
:
2905 case BFD_RELOC_PPC_TPREL16_HI
:
2906 case BFD_RELOC_PPC_TPREL16_LO
:
2910 case BFD_RELOC_16_PCREL
:
2911 case BFD_RELOC_HI16_PCREL
:
2912 case BFD_RELOC_HI16_S_PCREL
:
2913 case BFD_RELOC_LO16_PCREL
:
2914 case BFD_RELOC_PPC64_REL16_HIGH
:
2915 case BFD_RELOC_PPC64_REL16_HIGHA
:
2916 case BFD_RELOC_PPC64_REL16_HIGHER
:
2917 case BFD_RELOC_PPC64_REL16_HIGHER34
:
2918 case BFD_RELOC_PPC64_REL16_HIGHERA
:
2919 case BFD_RELOC_PPC64_REL16_HIGHERA34
:
2920 case BFD_RELOC_PPC64_REL16_HIGHEST
:
2921 case BFD_RELOC_PPC64_REL16_HIGHEST34
:
2922 case BFD_RELOC_PPC64_REL16_HIGHESTA
:
2923 case BFD_RELOC_PPC64_REL16_HIGHESTA34
:
2925 case BFD_RELOC_PPC_B16
:
2927 case BFD_RELOC_PPC_VLE_REL8
:
2933 case BFD_RELOC_32_PLTOFF
:
2935 case BFD_RELOC_CTOR
:
2937 case BFD_RELOC_PPC64_ENTRY
:
2938 case BFD_RELOC_PPC_16DX_HA
:
2940 case BFD_RELOC_PPC_BA16
:
2942 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
2943 case BFD_RELOC_PPC_BA16_BRTAKEN
:
2944 case BFD_RELOC_PPC_BA26
:
2945 case BFD_RELOC_PPC_EMB_BIT_FLD
:
2946 case BFD_RELOC_PPC_EMB_NADDR32
:
2947 case BFD_RELOC_PPC_EMB_SDA21
:
2948 case BFD_RELOC_PPC_TLS
:
2949 case BFD_RELOC_PPC_TLSGD
:
2950 case BFD_RELOC_PPC_TLSLD
:
2951 case BFD_RELOC_PPC_VLE_HA16A
:
2952 case BFD_RELOC_PPC_VLE_HA16D
:
2953 case BFD_RELOC_PPC_VLE_HI16A
:
2954 case BFD_RELOC_PPC_VLE_HI16D
:
2955 case BFD_RELOC_PPC_VLE_LO16A
:
2956 case BFD_RELOC_PPC_VLE_LO16D
:
2957 case BFD_RELOC_PPC_VLE_SDA21
:
2958 case BFD_RELOC_PPC_VLE_SDA21_LO
:
2959 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
2960 case BFD_RELOC_PPC_VLE_SDAREL_HA16D
:
2961 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
2962 case BFD_RELOC_PPC_VLE_SDAREL_HI16D
:
2963 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
2964 case BFD_RELOC_PPC_VLE_SDAREL_LO16D
:
2965 case BFD_RELOC_PPC64_TLS_PCREL
:
2970 case BFD_RELOC_24_PLT_PCREL
:
2971 case BFD_RELOC_32_PCREL
:
2972 case BFD_RELOC_32_PLT_PCREL
:
2973 case BFD_RELOC_PPC64_REL24_NOTOC
:
2975 case BFD_RELOC_PPC_B16
:
2977 case BFD_RELOC_PPC_B16_BRNTAKEN
:
2978 case BFD_RELOC_PPC_B16_BRTAKEN
:
2979 case BFD_RELOC_PPC_B26
:
2980 case BFD_RELOC_PPC_LOCAL24PC
:
2981 case BFD_RELOC_PPC_REL16DX_HA
:
2982 case BFD_RELOC_PPC_VLE_REL15
:
2983 case BFD_RELOC_PPC_VLE_REL24
:
2989 case BFD_RELOC_CTOR
:
2991 case BFD_RELOC_PPC_COPY
:
2992 case BFD_RELOC_PPC_DTPMOD
:
2993 case BFD_RELOC_PPC_DTPREL
:
2994 case BFD_RELOC_PPC_GLOB_DAT
:
2995 case BFD_RELOC_PPC_TPREL
:
2996 size
= ppc_obj64
? 8 : 4;
3000 case BFD_RELOC_64_PLTOFF
:
3001 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
3002 case BFD_RELOC_PPC64_D28
:
3003 case BFD_RELOC_PPC64_D34
:
3004 case BFD_RELOC_PPC64_D34_LO
:
3005 case BFD_RELOC_PPC64_D34_HI30
:
3006 case BFD_RELOC_PPC64_D34_HA30
:
3007 case BFD_RELOC_PPC64_TPREL34
:
3008 case BFD_RELOC_PPC64_DTPREL34
:
3009 case BFD_RELOC_PPC64_TOC
:
3013 case BFD_RELOC_64_PCREL
:
3014 case BFD_RELOC_64_PLT_PCREL
:
3015 case BFD_RELOC_PPC64_GOT_PCREL34
:
3016 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
:
3017 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
:
3018 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34
:
3019 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
:
3020 case BFD_RELOC_PPC64_PCREL28
:
3021 case BFD_RELOC_PPC64_PCREL34
:
3022 case BFD_RELOC_PPC64_PLT_PCREL34
:
3031 if (ENABLE_CHECKING
)
3033 reloc_howto_type
*reloc_howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
3034 if (reloc_howto
!= NULL
3035 && (size
!= bfd_get_reloc_size (reloc_howto
)
3036 || pcrel
!= reloc_howto
->pc_relative
))
3038 as_bad (_("%s howto doesn't match size/pcrel in gas"),
3043 *pc_relative
= pcrel
;
3048 /* If we have parsed a call to __tls_get_addr, parse an argument like
3049 (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg
3050 is successfully parsed, *STR is updated past the trailing
3051 parenthesis and trailing white space, and *TLS_FIX contains the
3052 reloc and arg expression. */
3055 parse_tls_arg (char **str
, const expressionS
*exp
, struct ppc_fixup
*tls_fix
)
3057 const char *sym_name
= S_GET_NAME (exp
->X_add_symbol
);
3058 if (sym_name
[0] == '.')
3061 tls_fix
->reloc
= BFD_RELOC_NONE
;
3062 if (strncasecmp (sym_name
, "__tls_get_addr", 14) == 0
3063 && (sym_name
[14] == 0
3064 || strcasecmp (sym_name
+ 14, "_desc") == 0
3065 || strcasecmp (sym_name
+ 14, "_opt") == 0))
3067 char *hold
= input_line_pointer
;
3068 input_line_pointer
= *str
+ 1;
3069 expression (&tls_fix
->exp
);
3070 if (tls_fix
->exp
.X_op
== O_symbol
)
3072 if (strncasecmp (input_line_pointer
, "@tlsgd)", 7) == 0)
3073 tls_fix
->reloc
= BFD_RELOC_PPC_TLSGD
;
3074 else if (strncasecmp (input_line_pointer
, "@tlsld)", 7) == 0)
3075 tls_fix
->reloc
= BFD_RELOC_PPC_TLSLD
;
3076 if (tls_fix
->reloc
!= BFD_RELOC_NONE
)
3078 input_line_pointer
+= 7;
3080 *str
= input_line_pointer
;
3083 input_line_pointer
= hold
;
3085 return tls_fix
->reloc
!= BFD_RELOC_NONE
;
3089 /* This routine is called for each instruction to be assembled. */
3092 md_assemble (char *str
)
3095 const struct powerpc_opcode
*opcode
;
3097 const unsigned char *opindex_ptr
;
3100 struct ppc_fixup fixups
[MAX_INSN_FIXUPS
];
3105 unsigned int insn_length
;
3107 /* Get the opcode. */
3108 for (s
= str
; *s
!= '\0' && ! ISSPACE (*s
); s
++)
3113 /* Look up the opcode in the hash table. */
3114 opcode
= (const struct powerpc_opcode
*) str_hash_find (ppc_hash
, str
);
3115 if (opcode
== (const struct powerpc_opcode
*) NULL
)
3117 const struct powerpc_macro
*macro
;
3119 macro
= (const struct powerpc_macro
*) str_hash_find (ppc_macro_hash
, str
);
3120 if (macro
== (const struct powerpc_macro
*) NULL
)
3121 as_bad (_("unrecognized opcode: `%s'"), str
);
3123 ppc_macro (s
, macro
);
3125 ppc_clear_labels ();
3129 insn
= opcode
->opcode
;
3130 if (!target_big_endian
3131 && ((insn
& ~(1 << 26)) == 46u << 26
3132 || (insn
& ~(0xc0 << 1)) == (31u << 26 | 533 << 1)))
3134 /* lmw, stmw, lswi, lswx, stswi, stswx */
3135 as_bad (_("`%s' invalid when little-endian"), str
);
3136 ppc_clear_labels ();
3141 while (ISSPACE (*str
))
3144 /* PowerPC operands are just expressions. The only real issue is
3145 that a few operand types are optional. If an instruction has
3146 multiple optional operands and one is omitted, then all optional
3147 operands past the first omitted one must also be omitted. */
3148 int num_optional_operands
= 0;
3149 int num_optional_provided
= 0;
3151 /* Gather the operands. */
3155 for (opindex_ptr
= opcode
->operands
; *opindex_ptr
!= 0; opindex_ptr
++)
3157 const struct powerpc_operand
*operand
;
3163 if (next_opindex
== 0)
3164 operand
= &powerpc_operands
[*opindex_ptr
];
3167 operand
= &powerpc_operands
[next_opindex
];
3172 /* If this is an optional operand, and we are skipping it, just
3173 insert the default value, usually a zero. */
3174 if ((operand
->flags
& PPC_OPERAND_OPTIONAL
) != 0
3175 && !((operand
->flags
& PPC_OPERAND_OPTIONAL32
) != 0 && ppc_obj64
))
3177 if (num_optional_operands
== 0)
3179 const unsigned char *optr
;
3185 for (optr
= opindex_ptr
; *optr
!= 0; optr
++)
3187 const struct powerpc_operand
*op
;
3188 op
= &powerpc_operands
[*optr
];
3192 if ((op
->flags
& PPC_OPERAND_OPTIONAL
) != 0
3193 && !((op
->flags
& PPC_OPERAND_OPTIONAL32
) != 0
3195 ++num_optional_operands
;
3197 if (s
!= NULL
&& *s
!= '\0')
3201 /* Look for the start of the next operand. */
3202 if ((op
->flags
& PPC_OPERAND_PARENS
) != 0)
3203 s
= strpbrk (s
, "(,");
3205 s
= strchr (s
, ',');
3211 omitted
= total
- provided
;
3212 num_optional_provided
= num_optional_operands
- omitted
;
3214 if (--num_optional_provided
< 0)
3216 int64_t val
= ppc_optional_operand_value (operand
, insn
, ppc_cpu
,
3217 num_optional_provided
);
3218 if (operand
->insert
)
3220 insn
= (*operand
->insert
) (insn
, val
, ppc_cpu
, &errmsg
);
3221 if (errmsg
!= (const char *) NULL
)
3222 as_bad ("%s", errmsg
);
3224 else if (operand
->shift
>= 0)
3225 insn
|= (val
& operand
->bitm
) << operand
->shift
;
3227 insn
|= (val
& operand
->bitm
) >> -operand
->shift
;
3229 if ((operand
->flags
& PPC_OPERAND_NEXT
) != 0)
3230 next_opindex
= *opindex_ptr
+ 1;
3235 /* Gather the operand. */
3236 hold
= input_line_pointer
;
3237 input_line_pointer
= str
;
3240 && (((operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
3241 || ((operand
->flags
& PPC_OPERAND_CR_REG
) != 0)))
3242 || !register_name (&ex
))
3244 char save_lex
= lex_type
['%'];
3246 if (((operand
->flags
& PPC_OPERAND_CR_REG
) != 0)
3247 || (operand
->flags
& PPC_OPERAND_CR_BIT
) != 0)
3250 lex_type
['%'] |= LEX_BEGIN_NAME
;
3254 lex_type
['%'] = save_lex
;
3257 str
= input_line_pointer
;
3258 input_line_pointer
= hold
;
3260 if (ex
.X_op
== O_illegal
)
3261 as_bad (_("illegal operand"));
3262 else if (ex
.X_op
== O_absent
)
3263 as_bad (_("missing operand"));
3264 else if (ex
.X_op
== O_register
)
3268 & (PPC_OPERAND_GPR
| PPC_OPERAND_FPR
| PPC_OPERAND_VR
3269 | PPC_OPERAND_VSR
| PPC_OPERAND_CR_BIT
| PPC_OPERAND_CR_REG
3270 | PPC_OPERAND_SPR
| PPC_OPERAND_GQR
| PPC_OPERAND_ACC
)) != 0
3271 && !((ex
.X_md
& PPC_OPERAND_GPR
) != 0
3272 && ex
.X_add_number
!= 0
3273 && (operand
->flags
& PPC_OPERAND_GPR_0
) != 0))
3274 as_warn (_("invalid register expression"));
3275 insn
= ppc_insert_operand (insn
, operand
, ex
.X_add_number
,
3276 ppc_cpu
, (char *) NULL
, 0);
3278 else if (ex
.X_op
== O_constant
)
3281 /* Allow @HA, @L, @H on constants. */
3282 bfd_reloc_code_real_type reloc
;
3283 char *orig_str
= str
;
3285 if ((reloc
= ppc_elf_suffix (&str
, &ex
)) != BFD_RELOC_NONE
)
3292 case BFD_RELOC_LO16
:
3293 ex
.X_add_number
&= 0xffff;
3294 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3295 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3298 case BFD_RELOC_HI16
:
3299 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
3301 /* PowerPC64 @h is tested for overflow. */
3302 ex
.X_add_number
= (addressT
) ex
.X_add_number
>> 16;
3303 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3305 addressT sign
= (((addressT
) -1 >> 16) + 1) >> 1;
3307 = ((addressT
) ex
.X_add_number
^ sign
) - sign
;
3313 case BFD_RELOC_PPC64_ADDR16_HIGH
:
3314 ex
.X_add_number
= PPC_HI (ex
.X_add_number
);
3315 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3316 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3319 case BFD_RELOC_HI16_S
:
3320 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
3322 /* PowerPC64 @ha is tested for overflow. */
3324 = ((addressT
) ex
.X_add_number
+ 0x8000) >> 16;
3325 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3327 addressT sign
= (((addressT
) -1 >> 16) + 1) >> 1;
3329 = ((addressT
) ex
.X_add_number
^ sign
) - sign
;
3335 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
3336 ex
.X_add_number
= PPC_HA (ex
.X_add_number
);
3337 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3338 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3341 case BFD_RELOC_PPC64_HIGHER
:
3342 ex
.X_add_number
= PPC_HIGHER (ex
.X_add_number
);
3343 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3344 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3347 case BFD_RELOC_PPC64_HIGHER_S
:
3348 ex
.X_add_number
= PPC_HIGHERA (ex
.X_add_number
);
3349 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3350 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3353 case BFD_RELOC_PPC64_HIGHEST
:
3354 ex
.X_add_number
= PPC_HIGHEST (ex
.X_add_number
);
3355 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3356 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3359 case BFD_RELOC_PPC64_HIGHEST_S
:
3360 ex
.X_add_number
= PPC_HIGHESTA (ex
.X_add_number
);
3361 if ((operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
3362 ex
.X_add_number
= SEX16 (ex
.X_add_number
);
3365 #endif /* OBJ_ELF */
3366 insn
= ppc_insert_operand (insn
, operand
, ex
.X_add_number
,
3367 ppc_cpu
, (char *) NULL
, 0);
3371 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
3373 /* Look for a __tls_get_addr arg using the insane old syntax. */
3374 if (ex
.X_op
== O_symbol
&& *str
== '(' && fc
< MAX_INSN_FIXUPS
3375 && parse_tls_arg (&str
, &ex
, &fixups
[fc
]))
3377 fixups
[fc
].opindex
= *opindex_ptr
;
3381 if ((reloc
= ppc_elf_suffix (&str
, &ex
)) != BFD_RELOC_NONE
)
3383 /* If VLE-mode convert LO/HI/HA relocations. */
3384 if (opcode
->flags
& PPC_OPCODE_VLE
)
3386 uint64_t tmp_insn
= insn
& opcode
->mask
;
3388 int use_a_reloc
= (tmp_insn
== E_OR2I_INSN
3389 || tmp_insn
== E_AND2I_DOT_INSN
3390 || tmp_insn
== E_OR2IS_INSN
3391 || tmp_insn
== E_LI_INSN
3392 || tmp_insn
== E_LIS_INSN
3393 || tmp_insn
== E_AND2IS_DOT_INSN
);
3396 int use_d_reloc
= (tmp_insn
== E_ADD2I_DOT_INSN
3397 || tmp_insn
== E_ADD2IS_INSN
3398 || tmp_insn
== E_CMP16I_INSN
3399 || tmp_insn
== E_MULL2I_INSN
3400 || tmp_insn
== E_CMPL16I_INSN
3401 || tmp_insn
== E_CMPH16I_INSN
3402 || tmp_insn
== E_CMPHL16I_INSN
);
3409 case BFD_RELOC_PPC_EMB_SDA21
:
3410 reloc
= BFD_RELOC_PPC_VLE_SDA21
;
3413 case BFD_RELOC_LO16
:
3415 reloc
= BFD_RELOC_PPC_VLE_LO16D
;
3416 else if (use_a_reloc
)
3417 reloc
= BFD_RELOC_PPC_VLE_LO16A
;
3420 case BFD_RELOC_HI16
:
3422 reloc
= BFD_RELOC_PPC_VLE_HI16D
;
3423 else if (use_a_reloc
)
3424 reloc
= BFD_RELOC_PPC_VLE_HI16A
;
3427 case BFD_RELOC_HI16_S
:
3429 reloc
= BFD_RELOC_PPC_VLE_HA16D
;
3430 else if (use_a_reloc
)
3431 reloc
= BFD_RELOC_PPC_VLE_HA16A
;
3434 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
3436 reloc
= BFD_RELOC_PPC_VLE_SDAREL_LO16D
;
3439 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
3441 reloc
= BFD_RELOC_PPC_VLE_SDAREL_HI16D
;
3444 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
3446 reloc
= BFD_RELOC_PPC_VLE_SDAREL_HA16D
;
3451 /* TLS and other tweaks. */
3457 case BFD_RELOC_PPC_TLS
:
3458 case BFD_RELOC_PPC64_TLS_PCREL
:
3459 if (!_bfd_elf_ppc_at_tls_transform (opcode
->opcode
, 0))
3460 as_bad (_("@tls may not be used with \"%s\" operands"),
3462 else if (operand
->shift
!= 11)
3463 as_bad (_("@tls may only be used in last operand"));
3465 insn
= ppc_insert_operand (insn
, operand
,
3467 ppc_cpu
, (char *) NULL
, 0);
3470 /* We'll only use the 32 (or 64) bit form of these relocations
3471 in constants. Instructions get the 16 or 34 bit form. */
3472 case BFD_RELOC_PPC_DTPREL
:
3473 if (operand
->bitm
== 0x3ffffffffULL
)
3474 reloc
= BFD_RELOC_PPC64_DTPREL34
;
3476 reloc
= BFD_RELOC_PPC_DTPREL16
;
3479 case BFD_RELOC_PPC_TPREL
:
3480 if (operand
->bitm
== 0x3ffffffffULL
)
3481 reloc
= BFD_RELOC_PPC64_TPREL34
;
3483 reloc
= BFD_RELOC_PPC_TPREL16
;
3486 case BFD_RELOC_PPC64_PCREL34
:
3487 if (operand
->bitm
== 0xfffffffULL
)
3489 reloc
= BFD_RELOC_PPC64_PCREL28
;
3493 case BFD_RELOC_PPC64_GOT_PCREL34
:
3494 case BFD_RELOC_PPC64_PLT_PCREL34
:
3495 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
:
3496 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
:
3497 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34
:
3498 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
:
3499 if (operand
->bitm
!= 0x3ffffffffULL
3500 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3501 as_warn (_("%s unsupported on this instruction"), "@pcrel");
3504 case BFD_RELOC_LO16
:
3505 if (operand
->bitm
== 0x3ffffffffULL
3506 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3507 reloc
= BFD_RELOC_PPC64_D34_LO
;
3508 else if ((operand
->bitm
| 0xf) != 0xffff
3509 || operand
->shift
!= 0
3510 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3511 as_warn (_("%s unsupported on this instruction"), "@l");
3514 case BFD_RELOC_HI16
:
3515 if (operand
->bitm
== 0x3ffffffffULL
3516 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3517 reloc
= BFD_RELOC_PPC64_D34_HI30
;
3518 else if (operand
->bitm
!= 0xffff
3519 || operand
->shift
!= 0
3520 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3521 as_warn (_("%s unsupported on this instruction"), "@h");
3524 case BFD_RELOC_HI16_S
:
3525 if (operand
->bitm
== 0x3ffffffffULL
3526 && (operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0)
3527 reloc
= BFD_RELOC_PPC64_D34_HA30
;
3528 else if (operand
->bitm
== 0xffff
3529 && operand
->shift
== (int) PPC_OPSHIFT_INV
3530 && opcode
->opcode
== (19 << 26) + (2 << 1))
3532 reloc
= BFD_RELOC_PPC_16DX_HA
;
3533 else if (operand
->bitm
!= 0xffff
3534 || operand
->shift
!= 0
3535 || (operand
->flags
& PPC_OPERAND_NEGATIVE
) != 0)
3536 as_warn (_("%s unsupported on this instruction"), "@ha");
3539 #endif /* OBJ_ELF */
3541 if (reloc
!= BFD_RELOC_NONE
)
3543 /* Determine a BFD reloc value based on the operand information.
3544 We are only prepared to turn a few of the operands into
3546 else if ((operand
->flags
& (PPC_OPERAND_RELATIVE
3547 | PPC_OPERAND_ABSOLUTE
)) != 0
3548 && operand
->bitm
== 0x3fffffc
3549 && operand
->shift
== 0)
3550 reloc
= BFD_RELOC_PPC_B26
;
3551 else if ((operand
->flags
& (PPC_OPERAND_RELATIVE
3552 | PPC_OPERAND_ABSOLUTE
)) != 0
3553 && operand
->bitm
== 0xfffc
3554 && operand
->shift
== 0)
3555 reloc
= BFD_RELOC_PPC_B16
;
3556 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3557 && operand
->bitm
== 0x1fe
3558 && operand
->shift
== -1)
3559 reloc
= BFD_RELOC_PPC_VLE_REL8
;
3560 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3561 && operand
->bitm
== 0xfffe
3562 && operand
->shift
== 0)
3563 reloc
= BFD_RELOC_PPC_VLE_REL15
;
3564 else if ((operand
->flags
& PPC_OPERAND_RELATIVE
) != 0
3565 && operand
->bitm
== 0x1fffffe
3566 && operand
->shift
== 0)
3567 reloc
= BFD_RELOC_PPC_VLE_REL24
;
3568 else if ((operand
->flags
& PPC_OPERAND_NEGATIVE
) == 0
3569 && (operand
->bitm
& 0xfff0) == 0xfff0
3570 && operand
->shift
== 0)
3572 reloc
= BFD_RELOC_16
;
3573 #if defined OBJ_XCOFF || defined OBJ_ELF
3574 /* Note: the symbol may be not yet defined. */
3575 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0
3576 && ppc_is_toc_sym (ex
.X_add_symbol
))
3578 reloc
= BFD_RELOC_PPC_TOC16
;
3580 as_warn (_("assuming %s on symbol"),
3581 ppc_obj64
? "@toc" : "@xgot");
3586 else if (operand
->bitm
== 0x3ffffffffULL
)
3587 reloc
= BFD_RELOC_PPC64_D34
;
3588 else if (operand
->bitm
== 0xfffffffULL
)
3589 reloc
= BFD_RELOC_PPC64_D28
;
3591 /* For the absolute forms of branches, convert the PC
3592 relative form back into the absolute. */
3593 if ((operand
->flags
& PPC_OPERAND_ABSOLUTE
) != 0)
3597 case BFD_RELOC_PPC_B26
:
3598 reloc
= BFD_RELOC_PPC_BA26
;
3600 case BFD_RELOC_PPC_B16
:
3601 reloc
= BFD_RELOC_PPC_BA16
;
3604 case BFD_RELOC_PPC_B16_BRTAKEN
:
3605 reloc
= BFD_RELOC_PPC_BA16_BRTAKEN
;
3607 case BFD_RELOC_PPC_B16_BRNTAKEN
:
3608 reloc
= BFD_RELOC_PPC_BA16_BRNTAKEN
;
3619 case BFD_RELOC_PPC_TOC16
:
3620 toc_reloc_types
|= has_small_toc_reloc
;
3622 case BFD_RELOC_PPC64_TOC16_LO
:
3623 case BFD_RELOC_PPC64_TOC16_HI
:
3624 case BFD_RELOC_PPC64_TOC16_HA
:
3625 toc_reloc_types
|= has_large_toc_reloc
;
3632 && (operand
->flags
& (PPC_OPERAND_DS
| PPC_OPERAND_DQ
)) != 0)
3637 reloc
= BFD_RELOC_PPC64_ADDR16_DS
;
3640 case BFD_RELOC_LO16
:
3641 reloc
= BFD_RELOC_PPC64_ADDR16_LO_DS
;
3644 case BFD_RELOC_16_GOTOFF
:
3645 reloc
= BFD_RELOC_PPC64_GOT16_DS
;
3648 case BFD_RELOC_LO16_GOTOFF
:
3649 reloc
= BFD_RELOC_PPC64_GOT16_LO_DS
;
3652 case BFD_RELOC_LO16_PLTOFF
:
3653 reloc
= BFD_RELOC_PPC64_PLT16_LO_DS
;
3656 case BFD_RELOC_16_BASEREL
:
3657 reloc
= BFD_RELOC_PPC64_SECTOFF_DS
;
3660 case BFD_RELOC_LO16_BASEREL
:
3661 reloc
= BFD_RELOC_PPC64_SECTOFF_LO_DS
;
3664 case BFD_RELOC_PPC_TOC16
:
3665 reloc
= BFD_RELOC_PPC64_TOC16_DS
;
3668 case BFD_RELOC_PPC64_TOC16_LO
:
3669 reloc
= BFD_RELOC_PPC64_TOC16_LO_DS
;
3672 case BFD_RELOC_PPC64_PLTGOT16
:
3673 reloc
= BFD_RELOC_PPC64_PLTGOT16_DS
;
3676 case BFD_RELOC_PPC64_PLTGOT16_LO
:
3677 reloc
= BFD_RELOC_PPC64_PLTGOT16_LO_DS
;
3680 case BFD_RELOC_PPC_DTPREL16
:
3681 reloc
= BFD_RELOC_PPC64_DTPREL16_DS
;
3684 case BFD_RELOC_PPC_DTPREL16_LO
:
3685 reloc
= BFD_RELOC_PPC64_DTPREL16_LO_DS
;
3688 case BFD_RELOC_PPC_TPREL16
:
3689 reloc
= BFD_RELOC_PPC64_TPREL16_DS
;
3692 case BFD_RELOC_PPC_TPREL16_LO
:
3693 reloc
= BFD_RELOC_PPC64_TPREL16_LO_DS
;
3696 case BFD_RELOC_PPC_GOT_DTPREL16
:
3697 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
3698 case BFD_RELOC_PPC_GOT_TPREL16
:
3699 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
3703 as_bad (_("unsupported relocation for DS offset field"));
3708 /* Look for a __tls_get_addr arg after any __tls_get_addr
3709 modifiers like @plt. This fixup must be emitted before
3710 the usual call fixup. */
3711 if (ex
.X_op
== O_symbol
&& *str
== '(' && fc
< MAX_INSN_FIXUPS
3712 && parse_tls_arg (&str
, &ex
, &fixups
[fc
]))
3714 fixups
[fc
].opindex
= *opindex_ptr
;
3719 /* We need to generate a fixup for this expression. */
3720 if (fc
>= MAX_INSN_FIXUPS
)
3721 as_fatal (_("too many fixups"));
3722 fixups
[fc
].exp
= ex
;
3723 fixups
[fc
].opindex
= *opindex_ptr
;
3724 fixups
[fc
].reloc
= reloc
;
3732 /* If expecting more operands, then we want to see "),". */
3733 if (*str
== endc
&& opindex_ptr
[1] != 0)
3737 while (ISSPACE (*str
));
3741 else if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0)
3746 /* The call to expression should have advanced str past any
3754 else if (*str
!= '\0')
3756 as_bad (_("syntax error; found `%c', expected `%c'"), *str
, endc
);
3759 else if (endc
== ')')
3761 as_bad (_("syntax error; end of line, expected `%c'"), endc
);
3766 while (ISSPACE (*str
))
3770 as_bad (_("junk at end of line: `%s'"), str
);
3773 /* Do we need/want an APUinfo section? */
3774 if ((ppc_cpu
& (PPC_OPCODE_E500
| PPC_OPCODE_E500MC
| PPC_OPCODE_VLE
)) != 0
3777 /* These are all version "1". */
3778 if (opcode
->flags
& PPC_OPCODE_SPE
)
3779 ppc_apuinfo_section_add (PPC_APUINFO_SPE
, 1);
3780 if (opcode
->flags
& PPC_OPCODE_ISEL
)
3781 ppc_apuinfo_section_add (PPC_APUINFO_ISEL
, 1);
3782 if (opcode
->flags
& PPC_OPCODE_EFS
)
3783 ppc_apuinfo_section_add (PPC_APUINFO_EFS
, 1);
3784 if (opcode
->flags
& PPC_OPCODE_BRLOCK
)
3785 ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK
, 1);
3786 if (opcode
->flags
& PPC_OPCODE_PMR
)
3787 ppc_apuinfo_section_add (PPC_APUINFO_PMR
, 1);
3788 if (opcode
->flags
& PPC_OPCODE_CACHELCK
)
3789 ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK
, 1);
3790 if (opcode
->flags
& PPC_OPCODE_RFMCI
)
3791 ppc_apuinfo_section_add (PPC_APUINFO_RFMCI
, 1);
3792 /* Only set the VLE flag if the instruction has been pulled via
3793 the VLE instruction set. This way the flag is guaranteed to
3794 be set for VLE-only instructions or for VLE-only processors,
3795 however it'll remain clear for dual-mode instructions on
3796 dual-mode and, more importantly, standard-mode processors. */
3797 if ((ppc_cpu
& opcode
->flags
) == PPC_OPCODE_VLE
)
3799 ppc_apuinfo_section_add (PPC_APUINFO_VLE
, 1);
3800 if (elf_section_data (now_seg
) != NULL
)
3801 elf_section_data (now_seg
)->this_hdr
.sh_flags
|= SHF_PPC_VLE
;
3806 /* Write out the instruction. */
3809 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
3810 /* All instructions can start on a 2 byte boundary for VLE. */
3813 if (frag_now
->insn_addr
!= addr_mask
)
3815 /* Don't emit instructions to a frag started for data, or for a
3816 CPU differing in VLE mode. Data is allowed to be misaligned,
3817 and it's possible to start a new frag in the middle of
3819 frag_wane (frag_now
);
3823 /* Check that insns within the frag are aligned. ppc_frag_check
3824 will ensure that the frag start address is aligned. */
3825 if ((frag_now_fix () & addr_mask
) != 0)
3826 as_bad (_("instruction address is not a multiple of %d"), addr_mask
+ 1);
3828 /* Differentiate between two, four, and eight byte insns. */
3830 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0 && PPC_OP_SE_VLE (insn
))
3832 else if ((opcode
->flags
& PPC_OPCODE_POWER10
) != 0
3833 && PPC_PREFIX_P (insn
))
3835 struct insn_label_list
*l
;
3839 /* 8-byte prefix instructions are not allowed to cross 64-byte
3841 frag_align_code (6, 4);
3842 record_alignment (now_seg
, 6);
3844 /* Update "dot" in any expressions used by this instruction, and
3845 a label attached to the instruction. By "attached" we mean
3846 on the same source line as the instruction and without any
3847 intervening semicolons. */
3848 dot_value
= frag_now_fix ();
3849 dot_frag
= frag_now
;
3850 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
3852 symbol_set_frag (l
->label
, dot_frag
);
3853 S_SET_VALUE (l
->label
, dot_value
);
3857 ppc_clear_labels ();
3859 f
= frag_more (insn_length
);
3860 frag_now
->insn_addr
= addr_mask
;
3862 /* The prefix part of an 8-byte instruction always occupies the lower
3863 addressed word in a doubleword, regardless of endianness. */
3864 if (!target_big_endian
&& insn_length
== 8)
3866 md_number_to_chars (f
, PPC_GET_PREFIX (insn
), 4);
3867 md_number_to_chars (f
+ 4, PPC_GET_SUFFIX (insn
), 4);
3870 md_number_to_chars (f
, insn
, insn_length
);
3874 last_subseg
= now_subseg
;
3877 dwarf2_emit_insn (insn_length
);
3880 /* Create any fixups. */
3881 for (i
= 0; i
< fc
; i
++)
3884 if (fixups
[i
].reloc
!= BFD_RELOC_NONE
)
3887 unsigned int size
= fixup_size (fixups
[i
].reloc
, &pcrel
);
3888 int offset
= target_big_endian
? (insn_length
- size
) : 0;
3890 fixP
= fix_new_exp (frag_now
,
3891 f
- frag_now
->fr_literal
+ offset
,
3899 const struct powerpc_operand
*operand
;
3901 operand
= &powerpc_operands
[fixups
[i
].opindex
];
3902 fixP
= fix_new_exp (frag_now
,
3903 f
- frag_now
->fr_literal
,
3906 (operand
->flags
& PPC_OPERAND_RELATIVE
) != 0,
3909 fixP
->fx_pcrel_adjust
= fixups
[i
].opindex
;
3913 /* Handle a macro. Gather all the operands, transform them as
3914 described by the macro, and call md_assemble recursively. All the
3915 operands are separated by commas; we don't accept parentheses
3916 around operands here. */
3919 ppc_macro (char *str
, const struct powerpc_macro
*macro
)
3930 /* Gather the users operands into the operands array. */
3935 if (count
>= sizeof operands
/ sizeof operands
[0])
3937 operands
[count
++] = s
;
3938 s
= strchr (s
, ',');
3939 if (s
== (char *) NULL
)
3944 if (count
!= macro
->operands
)
3946 as_bad (_("wrong number of operands"));
3950 /* Work out how large the string must be (the size is unbounded
3951 because it includes user input). */
3953 format
= macro
->format
;
3954 while (*format
!= '\0')
3963 arg
= strtol (format
+ 1, &send
, 10);
3964 know (send
!= format
&& arg
< count
);
3965 len
+= strlen (operands
[arg
]);
3970 /* Put the string together. */
3971 complete
= s
= XNEWVEC (char, len
+ 1);
3972 format
= macro
->format
;
3973 while (*format
!= '\0')
3979 arg
= strtol (format
+ 1, &send
, 10);
3980 strcpy (s
, operands
[arg
]);
3987 /* Assemble the constructed instruction. */
3988 md_assemble (complete
);
3993 /* For ELF, add support for SHT_ORDERED. */
3996 ppc_section_type (char *str
, size_t len
)
3998 if (len
== 7 && strncmp (str
, "ordered", 7) == 0)
4005 ppc_section_flags (flagword flags
, bfd_vma attr ATTRIBUTE_UNUSED
, int type
)
4007 if (type
== SHT_ORDERED
)
4008 flags
|= SEC_ALLOC
| SEC_LOAD
| SEC_SORT_ENTRIES
;
4014 ppc_elf_section_letter (int letter
, const char **ptrmsg
)
4019 *ptrmsg
= _("bad .section directive: want a,e,v,w,x,M,S,G,T in string");
4022 #endif /* OBJ_ELF */
4025 /* Pseudo-op handling. */
4027 /* The .byte pseudo-op. This is similar to the normal .byte
4028 pseudo-op, but it can also take a single ASCII string. */
4031 ppc_byte (int ignore ATTRIBUTE_UNUSED
)
4035 if (*input_line_pointer
!= '\"')
4041 /* Gather characters. A real double quote is doubled. Unusual
4042 characters are not permitted. */
4043 ++input_line_pointer
;
4048 c
= *input_line_pointer
++;
4052 if (*input_line_pointer
!= '\"')
4054 ++input_line_pointer
;
4057 FRAG_APPEND_1_CHAR (c
);
4061 if (warn_476
&& count
!= 0 && (now_seg
->flags
& SEC_CODE
) != 0)
4062 as_warn (_("data in executable section"));
4063 demand_empty_rest_of_line ();
4068 /* XCOFF specific pseudo-op handling. */
4070 /* This is set if we are creating a .stabx symbol, since we don't want
4071 to handle symbol suffixes for such symbols. */
4072 static bfd_boolean ppc_stab_symbol
;
4074 /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
4075 symbols in the .bss segment as though they were local common
4076 symbols, and uses a different smclas. The native Aix 4.3.3 assembler
4077 aligns .comm and .lcomm to 4 bytes. */
4080 ppc_comm (int lcomm
)
4082 asection
*current_seg
= now_seg
;
4083 subsegT current_subseg
= now_subseg
;
4089 symbolS
*lcomm_sym
= NULL
;
4093 endc
= get_symbol_name (&name
);
4094 end_name
= input_line_pointer
;
4095 (void) restore_line_pointer (endc
);
4097 if (*input_line_pointer
!= ',')
4099 as_bad (_("missing size"));
4100 ignore_rest_of_line ();
4103 ++input_line_pointer
;
4105 size
= get_absolute_expression ();
4108 as_bad (_("negative size"));
4109 ignore_rest_of_line ();
4115 /* The third argument to .comm is the alignment. */
4116 if (*input_line_pointer
!= ',')
4120 ++input_line_pointer
;
4121 align
= get_absolute_expression ();
4124 as_warn (_("ignoring bad alignment"));
4134 /* The third argument to .lcomm appears to be the real local
4135 common symbol to create. References to the symbol named in
4136 the first argument are turned into references to the third
4138 if (*input_line_pointer
!= ',')
4140 as_bad (_("missing real symbol name"));
4141 ignore_rest_of_line ();
4144 ++input_line_pointer
;
4146 lcomm_endc
= get_symbol_name (&lcomm_name
);
4148 lcomm_sym
= symbol_find_or_make (lcomm_name
);
4150 (void) restore_line_pointer (lcomm_endc
);
4152 /* The fourth argument to .lcomm is the alignment. */
4153 if (*input_line_pointer
!= ',')
4162 ++input_line_pointer
;
4163 align
= get_absolute_expression ();
4166 as_warn (_("ignoring bad alignment"));
4173 sym
= symbol_find_or_make (name
);
4176 if (S_IS_DEFINED (sym
)
4177 || S_GET_VALUE (sym
) != 0)
4179 as_bad (_("attempt to redefine symbol"));
4180 ignore_rest_of_line ();
4184 record_alignment (bss_section
, align
);
4187 || ! S_IS_DEFINED (lcomm_sym
))
4196 S_SET_EXTERNAL (sym
);
4200 symbol_get_tc (lcomm_sym
)->output
= 1;
4201 def_sym
= lcomm_sym
;
4205 subseg_set (bss_section
, 1);
4206 frag_align (align
, 0, 0);
4208 symbol_set_frag (def_sym
, frag_now
);
4209 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, def_sym
,
4210 def_size
, (char *) NULL
);
4212 S_SET_SEGMENT (def_sym
, bss_section
);
4213 symbol_get_tc (def_sym
)->align
= align
;
4217 /* Align the size of lcomm_sym. */
4218 symbol_get_frag (lcomm_sym
)->fr_offset
=
4219 ((symbol_get_frag (lcomm_sym
)->fr_offset
+ (1 << align
) - 1)
4220 &~ ((1 << align
) - 1));
4221 if (align
> symbol_get_tc (lcomm_sym
)->align
)
4222 symbol_get_tc (lcomm_sym
)->align
= align
;
4227 /* Make sym an offset from lcomm_sym. */
4228 S_SET_SEGMENT (sym
, bss_section
);
4229 symbol_set_frag (sym
, symbol_get_frag (lcomm_sym
));
4230 S_SET_VALUE (sym
, symbol_get_frag (lcomm_sym
)->fr_offset
);
4231 symbol_get_frag (lcomm_sym
)->fr_offset
+= size
;
4234 subseg_set (current_seg
, current_subseg
);
4236 demand_empty_rest_of_line ();
4239 /* The .csect pseudo-op. This switches us into a different
4240 subsegment. The first argument is a symbol whose value is the
4241 start of the .csect. In COFF, csect symbols get special aux
4242 entries defined by the x_csect field of union internal_auxent. The
4243 optional second argument is the alignment (the default is 2). */
4246 ppc_csect (int ignore ATTRIBUTE_UNUSED
)
4253 endc
= get_symbol_name (&name
);
4255 sym
= symbol_find_or_make (name
);
4257 (void) restore_line_pointer (endc
);
4259 if (S_GET_NAME (sym
)[0] == '\0')
4261 /* An unnamed csect is assumed to be [PR]. */
4262 symbol_get_tc (sym
)->symbol_class
= XMC_PR
;
4266 if (*input_line_pointer
== ',')
4268 ++input_line_pointer
;
4269 align
= get_absolute_expression ();
4272 ppc_change_csect (sym
, align
);
4274 demand_empty_rest_of_line ();
4277 /* Change to a different csect. */
4280 ppc_change_csect (symbolS
*sym
, offsetT align
)
4282 if (S_IS_DEFINED (sym
))
4283 subseg_set (S_GET_SEGMENT (sym
), symbol_get_tc (sym
)->subseg
);
4293 /* This is a new csect. We need to look at the symbol class to
4294 figure out whether it should go in the text section or the
4298 switch (symbol_get_tc (sym
)->symbol_class
)
4308 S_SET_SEGMENT (sym
, text_section
);
4309 symbol_get_tc (sym
)->subseg
= ppc_text_subsegment
;
4310 ++ppc_text_subsegment
;
4311 list_ptr
= &ppc_text_csects
;
4321 if (ppc_toc_csect
!= NULL
4322 && (symbol_get_tc (ppc_toc_csect
)->subseg
+ 1
4323 == ppc_data_subsegment
))
4325 S_SET_SEGMENT (sym
, data_section
);
4326 symbol_get_tc (sym
)->subseg
= ppc_data_subsegment
;
4327 ++ppc_data_subsegment
;
4328 list_ptr
= &ppc_data_csects
;
4334 /* We set the obstack chunk size to a small value before
4335 changing subsegments, so that we don't use a lot of memory
4336 space for what may be a small section. */
4337 hold_chunksize
= chunksize
;
4340 sec
= subseg_new (segment_name (S_GET_SEGMENT (sym
)),
4341 symbol_get_tc (sym
)->subseg
);
4343 chunksize
= hold_chunksize
;
4346 ppc_after_toc_frag
= frag_now
;
4348 record_alignment (sec
, align
);
4350 frag_align_code (align
, 0);
4352 frag_align (align
, 0, 0);
4354 symbol_set_frag (sym
, frag_now
);
4355 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
4357 symbol_get_tc (sym
)->align
= align
;
4358 symbol_get_tc (sym
)->output
= 1;
4359 symbol_get_tc (sym
)->within
= sym
;
4361 for (list
= *list_ptr
;
4362 symbol_get_tc (list
)->next
!= (symbolS
*) NULL
;
4363 list
= symbol_get_tc (list
)->next
)
4365 symbol_get_tc (list
)->next
= sym
;
4367 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4368 symbol_append (sym
, symbol_get_tc (list
)->within
, &symbol_rootP
,
4372 ppc_current_csect
= sym
;
4376 ppc_change_debug_section (unsigned int idx
, subsegT subseg
)
4380 const struct xcoff_dwsect_name
*dw
= &xcoff_dwsect_names
[idx
];
4382 sec
= subseg_new (dw
->name
, subseg
);
4383 oldflags
= bfd_section_flags (sec
);
4384 if (oldflags
== SEC_NO_FLAGS
)
4386 /* Just created section. */
4387 gas_assert (dw_sections
[idx
].sect
== NULL
);
4389 bfd_set_section_flags (sec
, SEC_DEBUGGING
);
4390 bfd_set_section_alignment (sec
, 0);
4391 dw_sections
[idx
].sect
= sec
;
4394 /* Not anymore in a csect. */
4395 ppc_current_csect
= NULL
;
4398 /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is:
4399 .dwsect flag [, opt-label ]
4403 ppc_dwsect (int ignore ATTRIBUTE_UNUSED
)
4407 const struct xcoff_dwsect_name
*dw
;
4408 struct dw_subsection
*subseg
;
4409 struct dw_section
*dws
;
4413 flag
= get_absolute_expression ();
4415 for (i
= 0; i
< XCOFF_DWSECT_NBR_NAMES
; i
++)
4416 if (xcoff_dwsect_names
[i
].flag
== flag
)
4418 dw
= &xcoff_dwsect_names
[i
];
4422 /* Parse opt-label. */
4423 if (*input_line_pointer
== ',')
4428 ++input_line_pointer
;
4430 c
= get_symbol_name (&label
);
4431 opt_label
= symbol_find_or_make (label
);
4432 (void) restore_line_pointer (c
);
4437 demand_empty_rest_of_line ();
4439 /* Return now in case of unknown subsection. */
4442 as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"),
4447 /* Find the subsection. */
4448 dws
= &dw_sections
[i
];
4450 if (opt_label
!= NULL
&& S_IS_DEFINED (opt_label
))
4452 /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */
4453 if (dws
->sect
== NULL
|| S_GET_SEGMENT (opt_label
) != dws
->sect
)
4455 as_bad (_("label %s was not defined in this dwarf section"),
4456 S_GET_NAME (opt_label
));
4457 subseg
= dws
->anon_subseg
;
4461 subseg
= symbol_get_tc (opt_label
)->u
.dw
;
4466 /* Switch to the subsection. */
4467 ppc_change_debug_section (i
, subseg
->subseg
);
4471 /* Create a new dw subsection. */
4472 subseg
= XNEW (struct dw_subsection
);
4474 if (opt_label
== NULL
)
4476 /* The anonymous one. */
4478 subseg
->link
= NULL
;
4479 dws
->anon_subseg
= subseg
;
4484 if (dws
->list_subseg
!= NULL
)
4485 subseg
->subseg
= dws
->list_subseg
->subseg
+ 1;
4489 subseg
->link
= dws
->list_subseg
;
4490 dws
->list_subseg
= subseg
;
4491 symbol_get_tc (opt_label
)->u
.dw
= subseg
;
4494 ppc_change_debug_section (i
, subseg
->subseg
);
4498 /* Add the length field. */
4499 expressionS
*exp
= &subseg
->end_exp
;
4502 if (opt_label
!= NULL
)
4503 symbol_set_value_now (opt_label
);
4505 /* Add the length field. Note that according to the AIX assembler
4506 manual, the size of the length field is 4 for powerpc32 but
4507 12 for powerpc64. */
4510 /* Write the 64bit marker. */
4511 md_number_to_chars (frag_more (4), -1, 4);
4514 exp
->X_op
= O_subtract
;
4515 exp
->X_op_symbol
= symbol_temp_new_now ();
4516 exp
->X_add_symbol
= symbol_temp_make ();
4518 sz
= ppc_obj64
? 8 : 4;
4519 exp
->X_add_number
= -sz
;
4520 emit_expr (exp
, sz
);
4525 /* This function handles the .text and .data pseudo-ops. These
4526 pseudo-ops aren't really used by XCOFF; we implement them for the
4527 convenience of people who aren't used to XCOFF. */
4530 ppc_section (int type
)
4537 else if (type
== 'd')
4542 sym
= symbol_find_or_make (name
);
4544 ppc_change_csect (sym
, 2);
4546 demand_empty_rest_of_line ();
4549 /* This function handles the .section pseudo-op. This is mostly to
4550 give an error, since XCOFF only supports .text, .data and .bss, but
4551 we do permit the user to name the text or data section. */
4554 ppc_named_section (int ignore ATTRIBUTE_UNUSED
)
4557 const char *real_name
;
4561 c
= get_symbol_name (&user_name
);
4563 if (strcmp (user_name
, ".text") == 0)
4564 real_name
= ".text[PR]";
4565 else if (strcmp (user_name
, ".data") == 0)
4566 real_name
= ".data[RW]";
4569 as_bad (_("the XCOFF file format does not support arbitrary sections"));
4570 (void) restore_line_pointer (c
);
4571 ignore_rest_of_line ();
4575 (void) restore_line_pointer (c
);
4577 sym
= symbol_find_or_make (real_name
);
4579 ppc_change_csect (sym
, 2);
4581 demand_empty_rest_of_line ();
4584 /* The .extern pseudo-op. We create an undefined symbol. */
4587 ppc_extern (int ignore ATTRIBUTE_UNUSED
)
4592 endc
= get_symbol_name (&name
);
4594 (void) symbol_find_or_make (name
);
4596 (void) restore_line_pointer (endc
);
4598 demand_empty_rest_of_line ();
4601 /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */
4604 ppc_lglobl (int ignore ATTRIBUTE_UNUSED
)
4610 endc
= get_symbol_name (&name
);
4612 sym
= symbol_find_or_make (name
);
4614 (void) restore_line_pointer (endc
);
4616 symbol_get_tc (sym
)->output
= 1;
4618 demand_empty_rest_of_line ();
4621 /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF
4622 relocations at the beginning of the current csect.
4624 (In principle, there's no reason why the relocations _have_ to be at
4625 the beginning. Anywhere in the csect would do. However, inserting
4626 at the beginning is what the native assembler does, and it helps to
4627 deal with cases where the .ref statements follow the section contents.)
4629 ??? .refs don't work for empty .csects. However, the native assembler
4630 doesn't report an error in this case, and neither yet do we. */
4633 ppc_ref (int ignore ATTRIBUTE_UNUSED
)
4638 if (ppc_current_csect
== NULL
)
4640 as_bad (_(".ref outside .csect"));
4641 ignore_rest_of_line ();
4647 c
= get_symbol_name (&name
);
4649 fix_at_start (symbol_get_frag (ppc_current_csect
), 0,
4650 symbol_find_or_make (name
), 0, FALSE
, BFD_RELOC_NONE
);
4652 *input_line_pointer
= c
;
4653 SKIP_WHITESPACE_AFTER_NAME ();
4654 c
= *input_line_pointer
;
4657 input_line_pointer
++;
4659 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
4661 as_bad (_("missing symbol name"));
4662 ignore_rest_of_line ();
4669 demand_empty_rest_of_line ();
4672 /* The .rename pseudo-op. The RS/6000 assembler can rename symbols,
4673 although I don't know why it bothers. */
4676 ppc_rename (int ignore ATTRIBUTE_UNUSED
)
4683 endc
= get_symbol_name (&name
);
4685 sym
= symbol_find_or_make (name
);
4687 (void) restore_line_pointer (endc
);
4689 if (*input_line_pointer
!= ',')
4691 as_bad (_("missing rename string"));
4692 ignore_rest_of_line ();
4695 ++input_line_pointer
;
4697 symbol_get_tc (sym
)->real_name
= demand_copy_C_string (&len
);
4699 demand_empty_rest_of_line ();
4702 /* The .stabx pseudo-op. This is similar to a normal .stabs
4703 pseudo-op, but slightly different. A sample is
4704 .stabx "main:F-1",.main,142,0
4705 The first argument is the symbol name to create. The second is the
4706 value, and the third is the storage class. The fourth seems to be
4707 always zero, and I am assuming it is the type. */
4710 ppc_stabx (int ignore ATTRIBUTE_UNUSED
)
4717 name
= demand_copy_C_string (&len
);
4719 if (*input_line_pointer
!= ',')
4721 as_bad (_("missing value"));
4724 ++input_line_pointer
;
4726 ppc_stab_symbol
= TRUE
;
4727 sym
= symbol_make (name
);
4728 ppc_stab_symbol
= FALSE
;
4730 symbol_get_tc (sym
)->real_name
= name
;
4732 (void) expression (&exp
);
4739 as_bad (_("illegal .stabx expression; zero assumed"));
4740 exp
.X_add_number
= 0;
4743 S_SET_VALUE (sym
, (valueT
) exp
.X_add_number
);
4744 symbol_set_frag (sym
, &zero_address_frag
);
4748 if (S_GET_SEGMENT (exp
.X_add_symbol
) == undefined_section
)
4749 symbol_set_value_expression (sym
, &exp
);
4753 exp
.X_add_number
+ S_GET_VALUE (exp
.X_add_symbol
));
4754 symbol_set_frag (sym
, symbol_get_frag (exp
.X_add_symbol
));
4759 /* The value is some complex expression. This will probably
4760 fail at some later point, but this is probably the right
4761 thing to do here. */
4762 symbol_set_value_expression (sym
, &exp
);
4766 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
4767 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
4769 if (*input_line_pointer
!= ',')
4771 as_bad (_("missing class"));
4774 ++input_line_pointer
;
4776 S_SET_STORAGE_CLASS (sym
, get_absolute_expression ());
4778 if (*input_line_pointer
!= ',')
4780 as_bad (_("missing type"));
4783 ++input_line_pointer
;
4785 S_SET_DATA_TYPE (sym
, get_absolute_expression ());
4787 symbol_get_tc (sym
)->output
= 1;
4789 if (S_GET_STORAGE_CLASS (sym
) == C_STSYM
)
4794 .stabx "z",arrays_,133,0
4797 .comm arrays_,13768,3
4799 resolve_symbol_value will copy the exp's "within" into sym's when the
4800 offset is 0. Since this seems to be corner case problem,
4801 only do the correction for storage class C_STSYM. A better solution
4802 would be to have the tc field updated in ppc_symbol_new_hook. */
4804 if (exp
.X_op
== O_symbol
)
4806 if (ppc_current_block
== NULL
)
4807 as_bad (_(".stabx of storage class stsym must be within .bs/.es"));
4809 symbol_get_tc (sym
)->within
= ppc_current_block
;
4810 symbol_get_tc (exp
.X_add_symbol
)->within
= ppc_current_block
;
4814 if (exp
.X_op
!= O_symbol
4815 || ! S_IS_EXTERNAL (exp
.X_add_symbol
)
4816 || S_GET_SEGMENT (exp
.X_add_symbol
) != bss_section
)
4817 ppc_frob_label (sym
);
4820 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
4821 symbol_append (sym
, exp
.X_add_symbol
, &symbol_rootP
, &symbol_lastP
);
4822 if (symbol_get_tc (ppc_current_csect
)->within
== exp
.X_add_symbol
)
4823 symbol_get_tc (ppc_current_csect
)->within
= sym
;
4826 demand_empty_rest_of_line ();
4829 /* The .function pseudo-op. This takes several arguments. The first
4830 argument seems to be the external name of the symbol. The second
4831 argument seems to be the label for the start of the function. gcc
4832 uses the same name for both. I have no idea what the third and
4833 fourth arguments are meant to be. The optional fifth argument is
4834 an expression for the size of the function. In COFF this symbol
4835 gets an aux entry like that used for a csect. */
4838 ppc_function (int ignore ATTRIBUTE_UNUSED
)
4846 endc
= get_symbol_name (&name
);
4848 /* Ignore any [PR] suffix. */
4849 name
= ppc_canonicalize_symbol_name (name
);
4850 s
= strchr (name
, '[');
4851 if (s
!= (char *) NULL
4852 && strcmp (s
+ 1, "PR]") == 0)
4855 ext_sym
= symbol_find_or_make (name
);
4857 (void) restore_line_pointer (endc
);
4859 if (*input_line_pointer
!= ',')
4861 as_bad (_("missing symbol name"));
4862 ignore_rest_of_line ();
4865 ++input_line_pointer
;
4867 endc
= get_symbol_name (&name
);
4869 lab_sym
= symbol_find_or_make (name
);
4871 (void) restore_line_pointer (endc
);
4873 if (ext_sym
!= lab_sym
)
4877 exp
.X_op
= O_symbol
;
4878 exp
.X_add_symbol
= lab_sym
;
4879 exp
.X_op_symbol
= NULL
;
4880 exp
.X_add_number
= 0;
4882 symbol_set_value_expression (ext_sym
, &exp
);
4885 if (symbol_get_tc (ext_sym
)->symbol_class
== -1)
4886 symbol_get_tc (ext_sym
)->symbol_class
= XMC_PR
;
4887 symbol_get_tc (ext_sym
)->output
= 1;
4889 if (*input_line_pointer
== ',')
4893 /* Ignore the third argument. */
4894 ++input_line_pointer
;
4896 if (*input_line_pointer
== ',')
4898 /* Ignore the fourth argument. */
4899 ++input_line_pointer
;
4901 if (*input_line_pointer
== ',')
4903 /* The fifth argument is the function size. */
4904 ++input_line_pointer
;
4905 symbol_get_tc (ext_sym
)->u
.size
= symbol_new
4906 ("L0\001", absolute_section
,(valueT
) 0, &zero_address_frag
);
4907 pseudo_set (symbol_get_tc (ext_sym
)->u
.size
);
4912 S_SET_DATA_TYPE (ext_sym
, DT_FCN
<< N_BTSHFT
);
4913 SF_SET_FUNCTION (ext_sym
);
4914 SF_SET_PROCESS (ext_sym
);
4915 coff_add_linesym (ext_sym
);
4917 demand_empty_rest_of_line ();
4920 /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named
4921 ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym
4922 with the correct line number */
4924 static symbolS
*saved_bi_sym
= 0;
4927 ppc_bf (int ignore ATTRIBUTE_UNUSED
)
4931 sym
= symbol_make (".bf");
4932 S_SET_SEGMENT (sym
, text_section
);
4933 symbol_set_frag (sym
, frag_now
);
4934 S_SET_VALUE (sym
, frag_now_fix ());
4935 S_SET_STORAGE_CLASS (sym
, C_FCN
);
4937 coff_line_base
= get_absolute_expression ();
4939 S_SET_NUMBER_AUXILIARY (sym
, 1);
4940 SA_SET_SYM_LNNO (sym
, coff_line_base
);
4942 /* Line number for bi. */
4945 S_SET_VALUE (saved_bi_sym
, coff_n_line_nos
);
4950 symbol_get_tc (sym
)->output
= 1;
4952 ppc_frob_label (sym
);
4954 demand_empty_rest_of_line ();
4957 /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named
4958 ".ef", except that the line number is absolute, not relative to the
4959 most recent ".bf" symbol. */
4962 ppc_ef (int ignore ATTRIBUTE_UNUSED
)
4966 sym
= symbol_make (".ef");
4967 S_SET_SEGMENT (sym
, text_section
);
4968 symbol_set_frag (sym
, frag_now
);
4969 S_SET_VALUE (sym
, frag_now_fix ());
4970 S_SET_STORAGE_CLASS (sym
, C_FCN
);
4971 S_SET_NUMBER_AUXILIARY (sym
, 1);
4972 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
4973 symbol_get_tc (sym
)->output
= 1;
4975 ppc_frob_label (sym
);
4977 demand_empty_rest_of_line ();
4980 /* The .bi and .ei pseudo-ops. These take a string argument and
4981 generates a C_BINCL or C_EINCL symbol, which goes at the start of
4982 the symbol list. The value of .bi will be know when the next .bf
4988 static symbolS
*last_biei
;
4995 name
= demand_copy_C_string (&len
);
4997 /* The value of these symbols is actually file offset. Here we set
4998 the value to the index into the line number entries. In
4999 ppc_frob_symbols we set the fix_line field, which will cause BFD
5000 to do the right thing. */
5002 sym
= symbol_make (name
);
5003 /* obj-coff.c currently only handles line numbers correctly in the
5005 S_SET_SEGMENT (sym
, text_section
);
5006 S_SET_VALUE (sym
, coff_n_line_nos
);
5007 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5009 S_SET_STORAGE_CLASS (sym
, ei
? C_EINCL
: C_BINCL
);
5010 symbol_get_tc (sym
)->output
= 1;
5018 for (look
= last_biei
? last_biei
: symbol_rootP
;
5019 (look
!= (symbolS
*) NULL
5020 && (S_GET_STORAGE_CLASS (look
) == C_FILE
5021 || S_GET_STORAGE_CLASS (look
) == C_BINCL
5022 || S_GET_STORAGE_CLASS (look
) == C_EINCL
));
5023 look
= symbol_next (look
))
5025 if (look
!= (symbolS
*) NULL
)
5027 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
5028 symbol_insert (sym
, look
, &symbol_rootP
, &symbol_lastP
);
5032 demand_empty_rest_of_line ();
5035 /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs".
5036 There is one argument, which is a csect symbol. The value of the
5037 .bs symbol is the index of this csect symbol. */
5040 ppc_bs (int ignore ATTRIBUTE_UNUSED
)
5047 if (ppc_current_block
!= NULL
)
5048 as_bad (_("nested .bs blocks"));
5050 endc
= get_symbol_name (&name
);
5052 csect
= symbol_find_or_make (name
);
5054 (void) restore_line_pointer (endc
);
5056 sym
= symbol_make (".bs");
5057 S_SET_SEGMENT (sym
, now_seg
);
5058 S_SET_STORAGE_CLASS (sym
, C_BSTAT
);
5059 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5060 symbol_get_tc (sym
)->output
= 1;
5062 symbol_get_tc (sym
)->within
= csect
;
5064 ppc_frob_label (sym
);
5066 ppc_current_block
= sym
;
5068 demand_empty_rest_of_line ();
5071 /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */
5074 ppc_es (int ignore ATTRIBUTE_UNUSED
)
5078 if (ppc_current_block
== NULL
)
5079 as_bad (_(".es without preceding .bs"));
5081 sym
= symbol_make (".es");
5082 S_SET_SEGMENT (sym
, now_seg
);
5083 S_SET_STORAGE_CLASS (sym
, C_ESTAT
);
5084 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5085 symbol_get_tc (sym
)->output
= 1;
5087 ppc_frob_label (sym
);
5089 ppc_current_block
= NULL
;
5091 demand_empty_rest_of_line ();
5094 /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a
5098 ppc_bb (int ignore ATTRIBUTE_UNUSED
)
5102 sym
= symbol_make (".bb");
5103 S_SET_SEGMENT (sym
, text_section
);
5104 symbol_set_frag (sym
, frag_now
);
5105 S_SET_VALUE (sym
, frag_now_fix ());
5106 S_SET_STORAGE_CLASS (sym
, C_BLOCK
);
5108 S_SET_NUMBER_AUXILIARY (sym
, 1);
5109 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5111 symbol_get_tc (sym
)->output
= 1;
5113 SF_SET_PROCESS (sym
);
5115 ppc_frob_label (sym
);
5117 demand_empty_rest_of_line ();
5120 /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a
5124 ppc_eb (int ignore ATTRIBUTE_UNUSED
)
5128 sym
= symbol_make (".eb");
5129 S_SET_SEGMENT (sym
, text_section
);
5130 symbol_set_frag (sym
, frag_now
);
5131 S_SET_VALUE (sym
, frag_now_fix ());
5132 S_SET_STORAGE_CLASS (sym
, C_BLOCK
);
5133 S_SET_NUMBER_AUXILIARY (sym
, 1);
5134 SA_SET_SYM_LNNO (sym
, get_absolute_expression ());
5135 symbol_get_tc (sym
)->output
= 1;
5137 SF_SET_PROCESS (sym
);
5139 ppc_frob_label (sym
);
5141 demand_empty_rest_of_line ();
5144 /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a
5148 ppc_bc (int ignore ATTRIBUTE_UNUSED
)
5154 name
= demand_copy_C_string (&len
);
5155 sym
= symbol_make (name
);
5156 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
5157 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5158 S_SET_STORAGE_CLASS (sym
, C_BCOMM
);
5159 S_SET_VALUE (sym
, 0);
5160 symbol_get_tc (sym
)->output
= 1;
5162 ppc_frob_label (sym
);
5164 demand_empty_rest_of_line ();
5167 /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */
5170 ppc_ec (int ignore ATTRIBUTE_UNUSED
)
5174 sym
= symbol_make (".ec");
5175 S_SET_SEGMENT (sym
, ppc_coff_debug_section
);
5176 symbol_get_bfdsym (sym
)->flags
|= BSF_DEBUGGING
;
5177 S_SET_STORAGE_CLASS (sym
, C_ECOMM
);
5178 S_SET_VALUE (sym
, 0);
5179 symbol_get_tc (sym
)->output
= 1;
5181 ppc_frob_label (sym
);
5183 demand_empty_rest_of_line ();
5186 /* The .toc pseudo-op. Switch to the .toc subsegment. */
5189 ppc_toc (int ignore ATTRIBUTE_UNUSED
)
5191 if (ppc_toc_csect
!= (symbolS
*) NULL
)
5192 subseg_set (data_section
, symbol_get_tc (ppc_toc_csect
)->subseg
);
5199 subseg
= ppc_data_subsegment
;
5200 ++ppc_data_subsegment
;
5202 subseg_new (segment_name (data_section
), subseg
);
5203 ppc_toc_frag
= frag_now
;
5205 sym
= symbol_find_or_make ("TOC[TC0]");
5206 symbol_set_frag (sym
, frag_now
);
5207 S_SET_SEGMENT (sym
, data_section
);
5208 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5209 symbol_get_tc (sym
)->subseg
= subseg
;
5210 symbol_get_tc (sym
)->output
= 1;
5211 symbol_get_tc (sym
)->within
= sym
;
5213 ppc_toc_csect
= sym
;
5215 for (list
= ppc_data_csects
;
5216 symbol_get_tc (list
)->next
!= (symbolS
*) NULL
;
5217 list
= symbol_get_tc (list
)->next
)
5219 symbol_get_tc (list
)->next
= sym
;
5221 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
5222 symbol_append (sym
, symbol_get_tc (list
)->within
, &symbol_rootP
,
5226 ppc_current_csect
= ppc_toc_csect
;
5228 demand_empty_rest_of_line ();
5231 /* The AIX assembler automatically aligns the operands of a .long or
5232 .short pseudo-op, and we want to be compatible. */
5235 ppc_xcoff_cons (int log_size
)
5237 frag_align (log_size
, 0, 0);
5238 record_alignment (now_seg
, log_size
);
5239 cons (1 << log_size
);
5243 ppc_vbyte (int dummy ATTRIBUTE_UNUSED
)
5248 (void) expression (&exp
);
5250 if (exp
.X_op
!= O_constant
)
5252 as_bad (_("non-constant byte count"));
5256 byte_count
= exp
.X_add_number
;
5258 if (*input_line_pointer
!= ',')
5260 as_bad (_("missing value"));
5264 ++input_line_pointer
;
5269 ppc_xcoff_end (void)
5273 for (i
= 0; i
< XCOFF_DWSECT_NBR_NAMES
; i
++)
5275 struct dw_section
*dws
= &dw_sections
[i
];
5276 struct dw_subsection
*dwss
;
5278 if (dws
->anon_subseg
)
5280 dwss
= dws
->anon_subseg
;
5281 dwss
->link
= dws
->list_subseg
;
5284 dwss
= dws
->list_subseg
;
5286 for (; dwss
!= NULL
; dwss
= dwss
->link
)
5287 if (dwss
->end_exp
.X_add_symbol
!= NULL
)
5289 subseg_set (dws
->sect
, dwss
->subseg
);
5290 symbol_set_value_now (dwss
->end_exp
.X_add_symbol
);
5296 #endif /* OBJ_XCOFF */
5297 #if defined (OBJ_XCOFF) || defined (OBJ_ELF)
5299 /* The .tc pseudo-op. This is used when generating either XCOFF or
5300 ELF. This takes two or more arguments.
5302 When generating XCOFF output, the first argument is the name to
5303 give to this location in the toc; this will be a symbol with class
5304 TC. The rest of the arguments are N-byte values to actually put at
5305 this location in the TOC; often there is just one more argument, a
5306 relocatable symbol reference. The size of the value to store
5307 depends on target word size. A 32-bit target uses 4-byte values, a
5308 64-bit target uses 8-byte values.
5310 When not generating XCOFF output, the arguments are the same, but
5311 the first argument is simply ignored. */
5314 ppc_tc (int ignore ATTRIBUTE_UNUSED
)
5318 /* Define the TOC symbol name. */
5324 if (ppc_toc_csect
== (symbolS
*) NULL
5325 || ppc_toc_csect
!= ppc_current_csect
)
5327 as_bad (_(".tc not in .toc section"));
5328 ignore_rest_of_line ();
5332 endc
= get_symbol_name (&name
);
5334 sym
= symbol_find_or_make (name
);
5336 (void) restore_line_pointer (endc
);
5338 if (S_IS_DEFINED (sym
))
5342 label
= symbol_get_tc (ppc_current_csect
)->within
;
5343 if (symbol_get_tc (label
)->symbol_class
!= XMC_TC0
)
5345 as_bad (_(".tc with no label"));
5346 ignore_rest_of_line ();
5350 S_SET_SEGMENT (label
, S_GET_SEGMENT (sym
));
5351 symbol_set_frag (label
, symbol_get_frag (sym
));
5352 S_SET_VALUE (label
, S_GET_VALUE (sym
));
5354 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
5355 ++input_line_pointer
;
5360 S_SET_SEGMENT (sym
, now_seg
);
5361 symbol_set_frag (sym
, frag_now
);
5362 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5363 symbol_get_tc (sym
)->symbol_class
= XMC_TC
;
5364 symbol_get_tc (sym
)->output
= 1;
5366 ppc_frob_label (sym
);
5369 #endif /* OBJ_XCOFF */
5373 /* Skip the TOC symbol name. */
5374 while (is_part_of_name (*input_line_pointer
)
5375 || *input_line_pointer
== ' '
5376 || *input_line_pointer
== '['
5377 || *input_line_pointer
== ']'
5378 || *input_line_pointer
== '{'
5379 || *input_line_pointer
== '}')
5380 ++input_line_pointer
;
5382 /* Align to a four/eight byte boundary. */
5383 align
= ppc_obj64
? 3 : 2;
5384 frag_align (align
, 0, 0);
5385 record_alignment (now_seg
, align
);
5386 #endif /* OBJ_ELF */
5388 if (*input_line_pointer
!= ',')
5389 demand_empty_rest_of_line ();
5392 ++input_line_pointer
;
5393 cons (ppc_obj64
? 8 : 4);
5397 /* Pseudo-op .machine. */
5400 ppc_machine (int ignore ATTRIBUTE_UNUSED
)
5404 #define MAX_HISTORY 100
5405 static ppc_cpu_t
*cpu_history
;
5406 static int curr_hist
;
5410 c
= get_symbol_name (&cpu_string
);
5411 cpu_string
= xstrdup (cpu_string
);
5412 (void) restore_line_pointer (c
);
5414 if (cpu_string
!= NULL
)
5416 ppc_cpu_t old_cpu
= ppc_cpu
;
5420 for (p
= cpu_string
; *p
!= 0; p
++)
5423 if (strcmp (cpu_string
, "push") == 0)
5425 if (cpu_history
== NULL
)
5426 cpu_history
= XNEWVEC (ppc_cpu_t
, MAX_HISTORY
);
5428 if (curr_hist
>= MAX_HISTORY
)
5429 as_bad (_(".machine stack overflow"));
5431 cpu_history
[curr_hist
++] = ppc_cpu
;
5433 else if (strcmp (cpu_string
, "pop") == 0)
5436 as_bad (_(".machine stack underflow"));
5438 ppc_cpu
= cpu_history
[--curr_hist
];
5440 else if ((new_cpu
= ppc_parse_cpu (ppc_cpu
, &sticky
, cpu_string
)) != 0)
5443 as_bad (_("invalid machine `%s'"), cpu_string
);
5445 if (ppc_cpu
!= old_cpu
)
5446 ppc_setup_opcodes ();
5449 demand_empty_rest_of_line ();
5451 #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */
5455 /* XCOFF specific symbol and file handling. */
5457 /* Canonicalize the symbol name. We use the to force the suffix, if
5458 any, to use square brackets, and to be in upper case. */
5461 ppc_canonicalize_symbol_name (char *name
)
5465 if (ppc_stab_symbol
)
5468 for (s
= name
; *s
!= '\0' && *s
!= '{' && *s
!= '['; s
++)
5482 for (s
++; *s
!= '\0' && *s
!= brac
; s
++)
5485 if (*s
== '\0' || s
[1] != '\0')
5486 as_bad (_("bad symbol suffix"));
5494 /* Set the class of a symbol based on the suffix, if any. This is
5495 called whenever a new symbol is created. */
5498 ppc_symbol_new_hook (symbolS
*sym
)
5500 struct ppc_tc_sy
*tc
;
5503 tc
= symbol_get_tc (sym
);
5506 tc
->symbol_class
= -1;
5507 tc
->real_name
= NULL
;
5514 if (ppc_stab_symbol
)
5517 s
= strchr (S_GET_NAME (sym
), '[');
5518 if (s
== (const char *) NULL
)
5520 /* There is no suffix. */
5529 if (strcmp (s
, "BS]") == 0)
5530 tc
->symbol_class
= XMC_BS
;
5533 if (strcmp (s
, "DB]") == 0)
5534 tc
->symbol_class
= XMC_DB
;
5535 else if (strcmp (s
, "DS]") == 0)
5536 tc
->symbol_class
= XMC_DS
;
5539 if (strcmp (s
, "GL]") == 0)
5540 tc
->symbol_class
= XMC_GL
;
5543 if (strcmp (s
, "PR]") == 0)
5544 tc
->symbol_class
= XMC_PR
;
5547 if (strcmp (s
, "RO]") == 0)
5548 tc
->symbol_class
= XMC_RO
;
5549 else if (strcmp (s
, "RW]") == 0)
5550 tc
->symbol_class
= XMC_RW
;
5553 if (strcmp (s
, "SV]") == 0)
5554 tc
->symbol_class
= XMC_SV
;
5557 if (strcmp (s
, "TC]") == 0)
5558 tc
->symbol_class
= XMC_TC
;
5559 else if (strcmp (s
, "TI]") == 0)
5560 tc
->symbol_class
= XMC_TI
;
5561 else if (strcmp (s
, "TB]") == 0)
5562 tc
->symbol_class
= XMC_TB
;
5563 else if (strcmp (s
, "TC0]") == 0 || strcmp (s
, "T0]") == 0)
5564 tc
->symbol_class
= XMC_TC0
;
5567 if (strcmp (s
, "UA]") == 0)
5568 tc
->symbol_class
= XMC_UA
;
5569 else if (strcmp (s
, "UC]") == 0)
5570 tc
->symbol_class
= XMC_UC
;
5573 if (strcmp (s
, "XO]") == 0)
5574 tc
->symbol_class
= XMC_XO
;
5578 if (tc
->symbol_class
== -1)
5579 as_bad (_("unrecognized symbol suffix"));
5582 /* This variable is set by ppc_frob_symbol if any absolute symbols are
5583 seen. It tells ppc_adjust_symtab whether it needs to look through
5586 static bfd_boolean ppc_saw_abs
;
5588 /* Change the name of a symbol just before writing it out. Set the
5589 real name if the .rename pseudo-op was used. Otherwise, remove any
5590 class suffix. Return 1 if the symbol should not be included in the
5594 ppc_frob_symbol (symbolS
*sym
)
5596 static symbolS
*ppc_last_function
;
5597 static symbolS
*set_end
;
5599 /* Discard symbols that should not be included in the output symbol
5601 if (! symbol_used_in_reloc_p (sym
)
5602 && ((symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
) != 0
5603 || (! (S_IS_EXTERNAL (sym
) || S_IS_WEAK (sym
))
5604 && ! symbol_get_tc (sym
)->output
5605 && S_GET_STORAGE_CLASS (sym
) != C_FILE
)))
5608 /* This one will disappear anyway. Don't make a csect sym for it. */
5609 if (sym
== abs_section_sym
)
5612 if (symbol_get_tc (sym
)->real_name
!= (char *) NULL
)
5613 S_SET_NAME (sym
, symbol_get_tc (sym
)->real_name
);
5619 name
= S_GET_NAME (sym
);
5620 s
= strchr (name
, '[');
5621 if (s
!= (char *) NULL
)
5627 snew
= xstrndup (name
, len
);
5629 S_SET_NAME (sym
, snew
);
5633 if (set_end
!= (symbolS
*) NULL
)
5635 SA_SET_SYM_ENDNDX (set_end
, sym
);
5639 if (SF_GET_FUNCTION (sym
))
5641 if (ppc_last_function
!= (symbolS
*) NULL
)
5642 as_bad (_("two .function pseudo-ops with no intervening .ef"));
5643 ppc_last_function
= sym
;
5644 if (symbol_get_tc (sym
)->u
.size
!= (symbolS
*) NULL
)
5646 resolve_symbol_value (symbol_get_tc (sym
)->u
.size
);
5647 SA_SET_SYM_FSIZE (sym
,
5648 (long) S_GET_VALUE (symbol_get_tc (sym
)->u
.size
));
5651 else if (S_GET_STORAGE_CLASS (sym
) == C_FCN
5652 && strcmp (S_GET_NAME (sym
), ".ef") == 0)
5654 if (ppc_last_function
== (symbolS
*) NULL
)
5655 as_bad (_(".ef with no preceding .function"));
5658 set_end
= ppc_last_function
;
5659 ppc_last_function
= NULL
;
5661 /* We don't have a C_EFCN symbol, but we need to force the
5662 COFF backend to believe that it has seen one. */
5663 coff_last_function
= NULL
;
5667 if (! (S_IS_EXTERNAL (sym
) || S_IS_WEAK (sym
))
5668 && (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
) == 0
5669 && S_GET_STORAGE_CLASS (sym
) != C_FILE
5670 && S_GET_STORAGE_CLASS (sym
) != C_FCN
5671 && S_GET_STORAGE_CLASS (sym
) != C_BLOCK
5672 && S_GET_STORAGE_CLASS (sym
) != C_BSTAT
5673 && S_GET_STORAGE_CLASS (sym
) != C_ESTAT
5674 && S_GET_STORAGE_CLASS (sym
) != C_BINCL
5675 && S_GET_STORAGE_CLASS (sym
) != C_EINCL
5676 && S_GET_SEGMENT (sym
) != ppc_coff_debug_section
)
5677 S_SET_STORAGE_CLASS (sym
, C_HIDEXT
);
5679 if (S_GET_STORAGE_CLASS (sym
) == C_EXT
5680 || S_GET_STORAGE_CLASS (sym
) == C_AIX_WEAKEXT
5681 || S_GET_STORAGE_CLASS (sym
) == C_HIDEXT
)
5684 union internal_auxent
*a
;
5686 /* Create a csect aux. */
5687 i
= S_GET_NUMBER_AUXILIARY (sym
);
5688 S_SET_NUMBER_AUXILIARY (sym
, i
+ 1);
5689 a
= &coffsymbol (symbol_get_bfdsym (sym
))->native
[i
+ 1].u
.auxent
;
5690 if (symbol_get_tc (sym
)->symbol_class
== XMC_TC0
)
5692 /* This is the TOC table. */
5693 know (strcmp (S_GET_NAME (sym
), "TOC") == 0);
5694 a
->x_csect
.x_scnlen
.l
= 0;
5695 a
->x_csect
.x_smtyp
= (2 << 3) | XTY_SD
;
5697 else if (symbol_get_tc (sym
)->subseg
!= 0)
5699 /* This is a csect symbol. x_scnlen is the size of the
5701 if (symbol_get_tc (sym
)->next
== (symbolS
*) NULL
)
5702 a
->x_csect
.x_scnlen
.l
= (bfd_section_size (S_GET_SEGMENT (sym
))
5703 - S_GET_VALUE (sym
));
5706 resolve_symbol_value (symbol_get_tc (sym
)->next
);
5707 a
->x_csect
.x_scnlen
.l
= (S_GET_VALUE (symbol_get_tc (sym
)->next
)
5708 - S_GET_VALUE (sym
));
5710 a
->x_csect
.x_smtyp
= (symbol_get_tc (sym
)->align
<< 3) | XTY_SD
;
5712 else if (S_GET_SEGMENT (sym
) == bss_section
)
5714 /* This is a common symbol. */
5715 a
->x_csect
.x_scnlen
.l
= symbol_get_frag (sym
)->fr_offset
;
5716 a
->x_csect
.x_smtyp
= (symbol_get_tc (sym
)->align
<< 3) | XTY_CM
;
5717 if (S_IS_EXTERNAL (sym
))
5718 symbol_get_tc (sym
)->symbol_class
= XMC_RW
;
5720 symbol_get_tc (sym
)->symbol_class
= XMC_BS
;
5722 else if (S_GET_SEGMENT (sym
) == absolute_section
)
5724 /* This is an absolute symbol. The csect will be created by
5725 ppc_adjust_symtab. */
5727 a
->x_csect
.x_smtyp
= XTY_LD
;
5728 if (symbol_get_tc (sym
)->symbol_class
== -1)
5729 symbol_get_tc (sym
)->symbol_class
= XMC_XO
;
5731 else if (! S_IS_DEFINED (sym
))
5733 /* This is an external symbol. */
5734 a
->x_csect
.x_scnlen
.l
= 0;
5735 a
->x_csect
.x_smtyp
= XTY_ER
;
5737 else if (symbol_get_tc (sym
)->symbol_class
== XMC_TC
)
5741 /* This is a TOC definition. x_scnlen is the size of the
5743 next
= symbol_next (sym
);
5744 while (symbol_get_tc (next
)->symbol_class
== XMC_TC0
)
5745 next
= symbol_next (next
);
5746 if (next
== (symbolS
*) NULL
5747 || symbol_get_tc (next
)->symbol_class
!= XMC_TC
)
5749 if (ppc_after_toc_frag
== (fragS
*) NULL
)
5750 a
->x_csect
.x_scnlen
.l
= (bfd_section_size (data_section
)
5751 - S_GET_VALUE (sym
));
5753 a
->x_csect
.x_scnlen
.l
= (ppc_after_toc_frag
->fr_address
5754 - S_GET_VALUE (sym
));
5758 resolve_symbol_value (next
);
5759 a
->x_csect
.x_scnlen
.l
= (S_GET_VALUE (next
)
5760 - S_GET_VALUE (sym
));
5762 a
->x_csect
.x_smtyp
= (2 << 3) | XTY_SD
;
5768 /* This is a normal symbol definition. x_scnlen is the
5769 symbol index of the containing csect. */
5770 if (S_GET_SEGMENT (sym
) == text_section
)
5771 csect
= ppc_text_csects
;
5772 else if (S_GET_SEGMENT (sym
) == data_section
)
5773 csect
= ppc_data_csects
;
5777 /* Skip the initial dummy symbol. */
5778 csect
= symbol_get_tc (csect
)->next
;
5780 if (csect
== (symbolS
*) NULL
)
5782 as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym
));
5783 a
->x_csect
.x_scnlen
.l
= 0;
5787 while (symbol_get_tc (csect
)->next
!= (symbolS
*) NULL
)
5789 resolve_symbol_value (symbol_get_tc (csect
)->next
);
5790 if (S_GET_VALUE (symbol_get_tc (csect
)->next
)
5791 > S_GET_VALUE (sym
))
5793 csect
= symbol_get_tc (csect
)->next
;
5796 a
->x_csect
.x_scnlen
.p
=
5797 coffsymbol (symbol_get_bfdsym (csect
))->native
;
5798 coffsymbol (symbol_get_bfdsym (sym
))->native
[i
+ 1].fix_scnlen
=
5801 a
->x_csect
.x_smtyp
= XTY_LD
;
5804 a
->x_csect
.x_parmhash
= 0;
5805 a
->x_csect
.x_snhash
= 0;
5806 if (symbol_get_tc (sym
)->symbol_class
== -1)
5807 a
->x_csect
.x_smclas
= XMC_PR
;
5809 a
->x_csect
.x_smclas
= symbol_get_tc (sym
)->symbol_class
;
5810 a
->x_csect
.x_stab
= 0;
5811 a
->x_csect
.x_snstab
= 0;
5813 /* Don't let the COFF backend resort these symbols. */
5814 symbol_get_bfdsym (sym
)->flags
|= BSF_NOT_AT_END
;
5816 else if (S_GET_STORAGE_CLASS (sym
) == C_BSTAT
)
5818 /* We want the value to be the symbol index of the referenced
5819 csect symbol. BFD will do that for us if we set the right
5821 asymbol
*bsym
= symbol_get_bfdsym (symbol_get_tc (sym
)->within
);
5822 combined_entry_type
*c
= coffsymbol (bsym
)->native
;
5824 S_SET_VALUE (sym
, (valueT
) (size_t) c
);
5825 coffsymbol (symbol_get_bfdsym (sym
))->native
->fix_value
= 1;
5827 else if (S_GET_STORAGE_CLASS (sym
) == C_STSYM
)
5832 block
= symbol_get_tc (sym
)->within
;
5835 /* The value is the offset from the enclosing csect. */
5838 csect
= symbol_get_tc (block
)->within
;
5839 resolve_symbol_value (csect
);
5840 base
= S_GET_VALUE (csect
);
5845 S_SET_VALUE (sym
, S_GET_VALUE (sym
) - base
);
5847 else if (S_GET_STORAGE_CLASS (sym
) == C_BINCL
5848 || S_GET_STORAGE_CLASS (sym
) == C_EINCL
)
5850 /* We want the value to be a file offset into the line numbers.
5851 BFD will do that for us if we set the right flags. We have
5852 already set the value correctly. */
5853 coffsymbol (symbol_get_bfdsym (sym
))->native
->fix_line
= 1;
5859 /* Adjust the symbol table. This creates csect symbols for all
5860 absolute symbols. */
5863 ppc_adjust_symtab (void)
5870 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
5874 union internal_auxent
*a
;
5876 if (S_GET_SEGMENT (sym
) != absolute_section
)
5879 csect
= symbol_create (".abs[XO]", absolute_section
,
5880 S_GET_VALUE (sym
), &zero_address_frag
);
5881 symbol_get_bfdsym (csect
)->value
= S_GET_VALUE (sym
);
5882 S_SET_STORAGE_CLASS (csect
, C_HIDEXT
);
5883 i
= S_GET_NUMBER_AUXILIARY (csect
);
5884 S_SET_NUMBER_AUXILIARY (csect
, i
+ 1);
5885 a
= &coffsymbol (symbol_get_bfdsym (csect
))->native
[i
+ 1].u
.auxent
;
5886 a
->x_csect
.x_scnlen
.l
= 0;
5887 a
->x_csect
.x_smtyp
= XTY_SD
;
5888 a
->x_csect
.x_parmhash
= 0;
5889 a
->x_csect
.x_snhash
= 0;
5890 a
->x_csect
.x_smclas
= XMC_XO
;
5891 a
->x_csect
.x_stab
= 0;
5892 a
->x_csect
.x_snstab
= 0;
5894 symbol_insert (csect
, sym
, &symbol_rootP
, &symbol_lastP
);
5896 i
= S_GET_NUMBER_AUXILIARY (sym
);
5897 a
= &coffsymbol (symbol_get_bfdsym (sym
))->native
[i
].u
.auxent
;
5898 a
->x_csect
.x_scnlen
.p
= coffsymbol (symbol_get_bfdsym (csect
))->native
;
5899 coffsymbol (symbol_get_bfdsym (sym
))->native
[i
].fix_scnlen
= 1;
5902 ppc_saw_abs
= FALSE
;
5905 /* Set the VMA for a section. This is called on all the sections in
5909 ppc_frob_section (asection
*sec
)
5911 static bfd_vma vma
= 0;
5913 /* Dwarf sections start at 0. */
5914 if (bfd_section_flags (sec
) & SEC_DEBUGGING
)
5917 vma
= md_section_align (sec
, vma
);
5918 bfd_set_section_vma (sec
, vma
);
5919 vma
+= bfd_section_size (sec
);
5922 #endif /* OBJ_XCOFF */
5925 md_atof (int type
, char *litp
, int *sizep
)
5927 return ieee_md_atof (type
, litp
, sizep
, target_big_endian
);
5930 /* Write a value out to the object file, using the appropriate
5934 md_number_to_chars (char *buf
, valueT val
, int n
)
5936 if (target_big_endian
)
5937 number_to_chars_bigendian (buf
, val
, n
);
5939 number_to_chars_littleendian (buf
, val
, n
);
5942 /* Align a section (I don't know why this is machine dependent). */
5945 md_section_align (asection
*seg ATTRIBUTE_UNUSED
, valueT addr
)
5950 int align
= bfd_section_alignment (seg
);
5952 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
5956 /* We don't have any form of relaxing. */
5959 md_estimate_size_before_relax (fragS
*fragp ATTRIBUTE_UNUSED
,
5960 asection
*seg ATTRIBUTE_UNUSED
)
5966 /* Convert a machine dependent frag. We never generate these. */
5969 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
5970 asection
*sec ATTRIBUTE_UNUSED
,
5971 fragS
*fragp ATTRIBUTE_UNUSED
)
5976 /* We have no need to default values of symbols. */
5979 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5984 /* Functions concerning relocs. */
5986 /* The location from which a PC relative jump should be calculated,
5987 given a PC relative reloc. */
5990 md_pcrel_from_section (fixS
*fixp
, segT sec ATTRIBUTE_UNUSED
)
5992 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5997 /* This is called to see whether a fixup should be adjusted to use a
5998 section symbol. We take the opportunity to change a fixup against
5999 a symbol in the TOC subsegment into a reloc against the
6000 corresponding .tc symbol. */
6003 ppc_fix_adjustable (fixS
*fix
)
6005 valueT val
= resolve_symbol_value (fix
->fx_addsy
);
6006 segT symseg
= S_GET_SEGMENT (fix
->fx_addsy
);
6007 TC_SYMFIELD_TYPE
*tc
;
6009 if (symseg
== absolute_section
)
6012 /* Always adjust symbols in debugging sections. */
6013 if (bfd_section_flags (symseg
) & SEC_DEBUGGING
)
6016 if (ppc_toc_csect
!= (symbolS
*) NULL
6017 && fix
->fx_addsy
!= ppc_toc_csect
6018 && symseg
== data_section
6019 && val
>= ppc_toc_frag
->fr_address
6020 && (ppc_after_toc_frag
== (fragS
*) NULL
6021 || val
< ppc_after_toc_frag
->fr_address
))
6025 for (sy
= symbol_next (ppc_toc_csect
);
6026 sy
!= (symbolS
*) NULL
;
6027 sy
= symbol_next (sy
))
6029 TC_SYMFIELD_TYPE
*sy_tc
= symbol_get_tc (sy
);
6031 if (sy_tc
->symbol_class
== XMC_TC0
)
6033 if (sy_tc
->symbol_class
!= XMC_TC
)
6035 if (val
== resolve_symbol_value (sy
))
6038 fix
->fx_addnumber
= val
- ppc_toc_frag
->fr_address
;
6043 as_bad_where (fix
->fx_file
, fix
->fx_line
,
6044 _("symbol in .toc does not match any .tc"));
6047 /* Possibly adjust the reloc to be against the csect. */
6048 tc
= symbol_get_tc (fix
->fx_addsy
);
6050 && tc
->symbol_class
!= XMC_TC0
6051 && tc
->symbol_class
!= XMC_TC
6052 && symseg
!= bss_section
6053 /* Don't adjust if this is a reloc in the toc section. */
6054 && (symseg
!= data_section
6055 || ppc_toc_csect
== NULL
6056 || val
< ppc_toc_frag
->fr_address
6057 || (ppc_after_toc_frag
!= NULL
6058 && val
>= ppc_after_toc_frag
->fr_address
)))
6060 symbolS
*csect
= tc
->within
;
6062 /* If the symbol was not declared by a label (eg: a section symbol),
6063 use the section instead of the csect. This doesn't happen in
6064 normal AIX assembly code. */
6066 csect
= seg_info (symseg
)->sym
;
6068 fix
->fx_offset
+= val
- symbol_get_frag (csect
)->fr_address
;
6069 fix
->fx_addsy
= csect
;
6074 /* Adjust a reloc against a .lcomm symbol to be against the base
6076 if (symseg
== bss_section
6077 && ! S_IS_EXTERNAL (fix
->fx_addsy
))
6079 symbolS
*sy
= symbol_get_frag (fix
->fx_addsy
)->fr_symbol
;
6081 fix
->fx_offset
+= val
- resolve_symbol_value (sy
);
6088 /* A reloc from one csect to another must be kept. The assembler
6089 will, of course, keep relocs between sections, and it will keep
6090 absolute relocs, but we need to force it to keep PC relative relocs
6091 between two csects in the same section. */
6094 ppc_force_relocation (fixS
*fix
)
6096 /* At this point fix->fx_addsy should already have been converted to
6097 a csect symbol. If the csect does not include the fragment, then
6098 we need to force the relocation. */
6100 && fix
->fx_addsy
!= NULL
6101 && symbol_get_tc (fix
->fx_addsy
)->subseg
!= 0
6102 && ((symbol_get_frag (fix
->fx_addsy
)->fr_address
6103 > fix
->fx_frag
->fr_address
)
6104 || (symbol_get_tc (fix
->fx_addsy
)->next
!= NULL
6105 && (symbol_get_frag (symbol_get_tc (fix
->fx_addsy
)->next
)->fr_address
6106 <= fix
->fx_frag
->fr_address
))))
6109 return generic_force_reloc (fix
);
6111 #endif /* OBJ_XCOFF */
6114 /* If this function returns non-zero, it guarantees that a relocation
6115 will be emitted for a fixup. */
6118 ppc_force_relocation (fixS
*fix
)
6120 /* Branch prediction relocations must force a relocation, as must
6121 the vtable description relocs. */
6122 switch (fix
->fx_r_type
)
6124 case BFD_RELOC_PPC_B16_BRTAKEN
:
6125 case BFD_RELOC_PPC_B16_BRNTAKEN
:
6126 case BFD_RELOC_PPC_BA16_BRTAKEN
:
6127 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
6128 case BFD_RELOC_24_PLT_PCREL
:
6129 case BFD_RELOC_PPC64_TOC
:
6131 case BFD_RELOC_PPC_B26
:
6132 case BFD_RELOC_PPC_BA26
:
6133 case BFD_RELOC_PPC_B16
:
6134 case BFD_RELOC_PPC_BA16
:
6135 case BFD_RELOC_PPC64_REL24_NOTOC
:
6136 /* All branch fixups targeting a localentry symbol must
6137 force a relocation. */
6140 asymbol
*bfdsym
= symbol_get_bfdsym (fix
->fx_addsy
);
6141 elf_symbol_type
*elfsym
6142 = elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
6143 gas_assert (elfsym
);
6144 if ((STO_PPC64_LOCAL_MASK
& elfsym
->internal_elf_sym
.st_other
) != 0)
6152 if (fix
->fx_r_type
>= BFD_RELOC_PPC_TLS
6153 && fix
->fx_r_type
<= BFD_RELOC_PPC64_TLS_PCREL
)
6156 return generic_force_reloc (fix
);
6160 ppc_fix_adjustable (fixS
*fix
)
6162 switch (fix
->fx_r_type
)
6164 /* All branch fixups targeting a localentry symbol must
6165 continue using the symbol. */
6166 case BFD_RELOC_PPC_B26
:
6167 case BFD_RELOC_PPC_BA26
:
6168 case BFD_RELOC_PPC_B16
:
6169 case BFD_RELOC_PPC_BA16
:
6170 case BFD_RELOC_PPC_B16_BRTAKEN
:
6171 case BFD_RELOC_PPC_B16_BRNTAKEN
:
6172 case BFD_RELOC_PPC_BA16_BRTAKEN
:
6173 case BFD_RELOC_PPC_BA16_BRNTAKEN
:
6174 case BFD_RELOC_PPC64_REL24_NOTOC
:
6177 asymbol
*bfdsym
= symbol_get_bfdsym (fix
->fx_addsy
);
6178 elf_symbol_type
*elfsym
6179 = elf_symbol_from (bfd_asymbol_bfd (bfdsym
), bfdsym
);
6180 gas_assert (elfsym
);
6181 if ((STO_PPC64_LOCAL_MASK
& elfsym
->internal_elf_sym
.st_other
) != 0)
6189 return (fix
->fx_r_type
!= BFD_RELOC_16_GOTOFF
6190 && fix
->fx_r_type
!= BFD_RELOC_LO16_GOTOFF
6191 && fix
->fx_r_type
!= BFD_RELOC_HI16_GOTOFF
6192 && fix
->fx_r_type
!= BFD_RELOC_HI16_S_GOTOFF
6193 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT16_DS
6194 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT16_LO_DS
6195 && fix
->fx_r_type
!= BFD_RELOC_PPC64_GOT_PCREL34
6196 && fix
->fx_r_type
!= BFD_RELOC_24_PLT_PCREL
6197 && fix
->fx_r_type
!= BFD_RELOC_32_PLTOFF
6198 && fix
->fx_r_type
!= BFD_RELOC_32_PLT_PCREL
6199 && fix
->fx_r_type
!= BFD_RELOC_LO16_PLTOFF
6200 && fix
->fx_r_type
!= BFD_RELOC_HI16_PLTOFF
6201 && fix
->fx_r_type
!= BFD_RELOC_HI16_S_PLTOFF
6202 && fix
->fx_r_type
!= BFD_RELOC_64_PLTOFF
6203 && fix
->fx_r_type
!= BFD_RELOC_64_PLT_PCREL
6204 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLT16_LO_DS
6205 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLT_PCREL34
6206 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16
6207 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_LO
6208 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_HI
6209 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_HA
6210 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_DS
6211 && fix
->fx_r_type
!= BFD_RELOC_PPC64_PLTGOT16_LO_DS
6212 && fix
->fx_r_type
!= BFD_RELOC_GPREL16
6213 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_LO16A
6214 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_HI16A
6215 && fix
->fx_r_type
!= BFD_RELOC_PPC_VLE_SDAREL_HA16A
6216 && fix
->fx_r_type
!= BFD_RELOC_VTABLE_INHERIT
6217 && fix
->fx_r_type
!= BFD_RELOC_VTABLE_ENTRY
6218 && !(fix
->fx_r_type
>= BFD_RELOC_PPC_TLS
6219 && fix
->fx_r_type
<= BFD_RELOC_PPC64_TLS_PCREL
));
6224 ppc_frag_check (struct frag
*fragP
)
6226 if ((fragP
->fr_address
& fragP
->insn_addr
) != 0)
6227 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
6228 _("instruction address is not a multiple of %d"),
6229 fragP
->insn_addr
+ 1);
6232 /* rs_align_code frag handling. */
6234 enum ppc_nop_encoding_for_rs_align_code
6243 ppc_nop_select (void)
6245 if ((ppc_cpu
& PPC_OPCODE_VLE
) != 0)
6247 if ((ppc_cpu
& (PPC_OPCODE_POWER9
| PPC_OPCODE_E500MC
)) == 0)
6249 if ((ppc_cpu
& PPC_OPCODE_POWER7
) != 0)
6250 return PPC_NOP_GROUP_P7
;
6251 if ((ppc_cpu
& PPC_OPCODE_POWER6
) != 0)
6252 return PPC_NOP_GROUP_P6
;
6254 return PPC_NOP_VANILLA
;
6258 ppc_handle_align (struct frag
*fragP
)
6260 valueT count
= (fragP
->fr_next
->fr_address
6261 - (fragP
->fr_address
+ fragP
->fr_fix
));
6262 char *dest
= fragP
->fr_literal
+ fragP
->fr_fix
;
6263 enum ppc_nop_encoding_for_rs_align_code nop_select
= *dest
& 0xff;
6265 /* Pad with zeros if not inserting a whole number of instructions.
6266 We could pad with zeros up to an instruction boundary then follow
6267 with nops but odd counts indicate data in an executable section
6268 so padding with zeros is most appropriate. */
6270 || (nop_select
== PPC_NOP_VLE
? (count
& 1) != 0 : (count
& 3) != 0))
6276 if (nop_select
== PPC_NOP_VLE
)
6280 md_number_to_chars (dest
, 0x4400, 2);
6286 if (count
> 4 * nop_limit
&& count
< 0x2000000)
6290 /* Make a branch, then follow with nops. Insert another
6291 frag to handle the nops. */
6292 md_number_to_chars (dest
, 0x48000000 + count
, 4);
6297 rest
= xmalloc (SIZEOF_STRUCT_FRAG
+ 4);
6298 memcpy (rest
, fragP
, SIZEOF_STRUCT_FRAG
);
6299 fragP
->fr_next
= rest
;
6301 rest
->fr_address
+= rest
->fr_fix
+ 4;
6303 /* If we leave the next frag as rs_align_code we'll come here
6304 again, resulting in a bunch of branches rather than a
6305 branch followed by nops. */
6306 rest
->fr_type
= rs_align
;
6307 dest
= rest
->fr_literal
;
6310 md_number_to_chars (dest
, 0x60000000, 4);
6312 if (nop_select
>= PPC_NOP_GROUP_P6
)
6314 /* For power6, power7, and power8, we want the last nop to
6315 be a group terminating one. Do this by inserting an
6316 rs_fill frag immediately after this one, with its address
6317 set to the last nop location. This will automatically
6318 reduce the number of nops in the current frag by one. */
6321 struct frag
*group_nop
= xmalloc (SIZEOF_STRUCT_FRAG
+ 4);
6323 memcpy (group_nop
, fragP
, SIZEOF_STRUCT_FRAG
);
6324 group_nop
->fr_address
= group_nop
->fr_next
->fr_address
- 4;
6325 group_nop
->fr_fix
= 0;
6326 group_nop
->fr_offset
= 1;
6327 group_nop
->fr_type
= rs_fill
;
6328 fragP
->fr_next
= group_nop
;
6329 dest
= group_nop
->fr_literal
;
6332 if (nop_select
== PPC_NOP_GROUP_P6
)
6333 /* power6 group terminating nop: "ori 1,1,0". */
6334 md_number_to_chars (dest
, 0x60210000, 4);
6336 /* power7/power8 group terminating nop: "ori 2,2,0". */
6337 md_number_to_chars (dest
, 0x60420000, 4);
6342 /* Apply a fixup to the object code. This is called for all the
6343 fixups we generated by the calls to fix_new_exp, above. */
6346 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
6348 valueT value
= * valP
;
6350 const struct powerpc_operand
*operand
;
6353 if (fixP
->fx_addsy
!= NULL
)
6355 /* Hack around bfd_install_relocation brain damage. */
6357 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6359 if (fixP
->fx_addsy
== abs_section_sym
)
6365 /* FIXME FIXME FIXME: The value we are passed in *valP includes
6366 the symbol values. If we are doing this relocation the code in
6367 write.c is going to call bfd_install_relocation, which is also
6368 going to use the symbol value. That means that if the reloc is
6369 fully resolved we want to use *valP since bfd_install_relocation is
6371 However, if the reloc is not fully resolved we do not want to
6372 use *valP, and must use fx_offset instead. If the relocation
6373 is PC-relative, we then need to re-apply md_pcrel_from_section
6374 to this new relocation value. */
6375 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
6380 value
= fixP
->fx_offset
;
6382 value
-= md_pcrel_from_section (fixP
, seg
);
6386 /* We are only able to convert some relocs to pc-relative. */
6389 switch (fixP
->fx_r_type
)
6392 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
6396 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
6400 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
6403 case BFD_RELOC_LO16
:
6404 fixP
->fx_r_type
= BFD_RELOC_LO16_PCREL
;
6407 case BFD_RELOC_HI16
:
6408 fixP
->fx_r_type
= BFD_RELOC_HI16_PCREL
;
6411 case BFD_RELOC_HI16_S
:
6412 fixP
->fx_r_type
= BFD_RELOC_HI16_S_PCREL
;
6415 case BFD_RELOC_PPC64_ADDR16_HIGH
:
6416 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGH
;
6419 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
6420 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHA
;
6423 case BFD_RELOC_PPC64_HIGHER
:
6424 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHER
;
6427 case BFD_RELOC_PPC64_HIGHER_S
:
6428 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHERA
;
6431 case BFD_RELOC_PPC64_HIGHEST
:
6432 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHEST
;
6435 case BFD_RELOC_PPC64_HIGHEST_S
:
6436 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHESTA
;
6439 case BFD_RELOC_PPC64_ADDR16_HIGHER34
:
6440 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHER34
;
6443 case BFD_RELOC_PPC64_ADDR16_HIGHERA34
:
6444 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHERA34
;
6447 case BFD_RELOC_PPC64_ADDR16_HIGHEST34
:
6448 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHEST34
;
6451 case BFD_RELOC_PPC64_ADDR16_HIGHESTA34
:
6452 fixP
->fx_r_type
= BFD_RELOC_PPC64_REL16_HIGHESTA34
;
6455 case BFD_RELOC_PPC_16DX_HA
:
6456 fixP
->fx_r_type
= BFD_RELOC_PPC_REL16DX_HA
;
6459 case BFD_RELOC_PPC64_D34
:
6460 fixP
->fx_r_type
= BFD_RELOC_PPC64_PCREL34
;
6463 case BFD_RELOC_PPC64_D28
:
6464 fixP
->fx_r_type
= BFD_RELOC_PPC64_PCREL28
;
6471 else if (!fixP
->fx_done
6472 && fixP
->fx_r_type
== BFD_RELOC_PPC_16DX_HA
)
6474 /* addpcis is relative to next insn address. */
6476 fixP
->fx_r_type
= BFD_RELOC_PPC_REL16DX_HA
;
6481 if (fixP
->fx_pcrel_adjust
!= 0)
6483 /* This is a fixup on an instruction. */
6484 int opindex
= fixP
->fx_pcrel_adjust
& 0xff;
6486 operand
= &powerpc_operands
[opindex
];
6488 /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol
6489 does not generate a reloc. It uses the offset of `sym' within its
6490 csect. Other usages, such as `.long sym', generate relocs. This
6491 is the documented behaviour of non-TOC symbols. */
6492 if ((operand
->flags
& PPC_OPERAND_PARENS
) != 0
6493 && (operand
->bitm
& 0xfff0) == 0xfff0
6494 && operand
->shift
== 0
6495 && (operand
->insert
== NULL
|| ppc_obj64
)
6496 && fixP
->fx_addsy
!= NULL
6497 && symbol_get_tc (fixP
->fx_addsy
)->subseg
!= 0
6498 && symbol_get_tc (fixP
->fx_addsy
)->symbol_class
!= XMC_TC
6499 && symbol_get_tc (fixP
->fx_addsy
)->symbol_class
!= XMC_TC0
6500 && S_GET_SEGMENT (fixP
->fx_addsy
) != bss_section
)
6502 value
= fixP
->fx_offset
;
6506 /* During parsing of instructions, a TOC16 reloc is generated for
6507 instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined
6508 in the toc. But at parse time, SYM may be not yet defined, so
6509 check again here. */
6510 if (fixP
->fx_r_type
== BFD_RELOC_16
6511 && fixP
->fx_addsy
!= NULL
6512 && ppc_is_toc_sym (fixP
->fx_addsy
))
6513 fixP
->fx_r_type
= BFD_RELOC_PPC_TOC16
;
6517 /* Calculate value to be stored in field. */
6519 switch (fixP
->fx_r_type
)
6522 case BFD_RELOC_PPC64_ADDR16_LO_DS
:
6523 case BFD_RELOC_PPC_VLE_LO16A
:
6524 case BFD_RELOC_PPC_VLE_LO16D
:
6526 case BFD_RELOC_LO16
:
6527 case BFD_RELOC_LO16_PCREL
:
6528 fieldval
= value
& 0xffff;
6530 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
6531 fieldval
= SEX16 (fieldval
);
6532 fixP
->fx_no_overflow
= 1;
6535 case BFD_RELOC_HI16
:
6536 case BFD_RELOC_HI16_PCREL
:
6538 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
6540 fieldval
= value
>> 16;
6541 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
6543 valueT sign
= (((valueT
) -1 >> 16) + 1) >> 1;
6544 fieldval
= ((valueT
) fieldval
^ sign
) - sign
;
6550 case BFD_RELOC_PPC_VLE_HI16A
:
6551 case BFD_RELOC_PPC_VLE_HI16D
:
6552 case BFD_RELOC_PPC64_ADDR16_HIGH
:
6554 fieldval
= PPC_HI (value
);
6555 goto sign_extend_16
;
6557 case BFD_RELOC_HI16_S
:
6558 case BFD_RELOC_HI16_S_PCREL
:
6559 case BFD_RELOC_PPC_16DX_HA
:
6560 case BFD_RELOC_PPC_REL16DX_HA
:
6562 if (REPORT_OVERFLOW_HI
&& ppc_obj64
)
6564 fieldval
= (value
+ 0x8000) >> 16;
6565 if (operand
!= NULL
&& (operand
->flags
& PPC_OPERAND_SIGNED
) != 0)
6567 valueT sign
= (((valueT
) -1 >> 16) + 1) >> 1;
6568 fieldval
= ((valueT
) fieldval
^ sign
) - sign
;
6574 case BFD_RELOC_PPC_VLE_HA16A
:
6575 case BFD_RELOC_PPC_VLE_HA16D
:
6576 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
6578 fieldval
= PPC_HA (value
);
6579 goto sign_extend_16
;
6582 case BFD_RELOC_PPC64_HIGHER
:
6583 fieldval
= PPC_HIGHER (value
);
6584 goto sign_extend_16
;
6586 case BFD_RELOC_PPC64_HIGHER_S
:
6587 fieldval
= PPC_HIGHERA (value
);
6588 goto sign_extend_16
;
6590 case BFD_RELOC_PPC64_HIGHEST
:
6591 fieldval
= PPC_HIGHEST (value
);
6592 goto sign_extend_16
;
6594 case BFD_RELOC_PPC64_HIGHEST_S
:
6595 fieldval
= PPC_HIGHESTA (value
);
6596 goto sign_extend_16
;
6603 if (operand
!= NULL
)
6605 /* Handle relocs in an insn. */
6606 switch (fixP
->fx_r_type
)
6609 /* The following relocs can't be calculated by the assembler.
6610 Leave the field zero. */
6611 case BFD_RELOC_PPC_TPREL16
:
6612 case BFD_RELOC_PPC_TPREL16_LO
:
6613 case BFD_RELOC_PPC_TPREL16_HI
:
6614 case BFD_RELOC_PPC_TPREL16_HA
:
6615 case BFD_RELOC_PPC_DTPREL16
:
6616 case BFD_RELOC_PPC_DTPREL16_LO
:
6617 case BFD_RELOC_PPC_DTPREL16_HI
:
6618 case BFD_RELOC_PPC_DTPREL16_HA
:
6619 case BFD_RELOC_PPC_GOT_TLSGD16
:
6620 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
6621 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
6622 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
6623 case BFD_RELOC_PPC_GOT_TLSLD16
:
6624 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
6625 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
6626 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
6627 case BFD_RELOC_PPC_GOT_TPREL16
:
6628 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
6629 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
6630 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
6631 case BFD_RELOC_PPC_GOT_DTPREL16
:
6632 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
6633 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
6634 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
6635 case BFD_RELOC_PPC64_TPREL16_DS
:
6636 case BFD_RELOC_PPC64_TPREL16_LO_DS
:
6637 case BFD_RELOC_PPC64_TPREL16_HIGH
:
6638 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
6639 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
6640 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
6641 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
6642 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
6643 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
6644 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
6645 case BFD_RELOC_PPC64_DTPREL16_DS
:
6646 case BFD_RELOC_PPC64_DTPREL16_LO_DS
:
6647 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
6648 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
6649 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
6650 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
6651 case BFD_RELOC_PPC64_TPREL34
:
6652 case BFD_RELOC_PPC64_DTPREL34
:
6653 case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
:
6654 case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
:
6655 case BFD_RELOC_PPC64_GOT_TPREL_PCREL34
:
6656 case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
:
6657 gas_assert (fixP
->fx_addsy
!= NULL
);
6658 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6662 /* These also should leave the field zero for the same
6663 reason. Note that older versions of gas wrote values
6664 here. If we want to go back to the old behaviour, then
6665 all _LO and _LO_DS cases will need to be treated like
6666 BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */
6667 case BFD_RELOC_16_GOTOFF
:
6668 case BFD_RELOC_LO16_GOTOFF
:
6669 case BFD_RELOC_HI16_GOTOFF
:
6670 case BFD_RELOC_HI16_S_GOTOFF
:
6671 case BFD_RELOC_LO16_PLTOFF
:
6672 case BFD_RELOC_HI16_PLTOFF
:
6673 case BFD_RELOC_HI16_S_PLTOFF
:
6674 case BFD_RELOC_GPREL16
:
6675 case BFD_RELOC_16_BASEREL
:
6676 case BFD_RELOC_LO16_BASEREL
:
6677 case BFD_RELOC_HI16_BASEREL
:
6678 case BFD_RELOC_HI16_S_BASEREL
:
6679 case BFD_RELOC_PPC_TOC16
:
6680 case BFD_RELOC_PPC64_TOC16_LO
:
6681 case BFD_RELOC_PPC64_TOC16_HI
:
6682 case BFD_RELOC_PPC64_TOC16_HA
:
6683 case BFD_RELOC_PPC64_PLTGOT16
:
6684 case BFD_RELOC_PPC64_PLTGOT16_LO
:
6685 case BFD_RELOC_PPC64_PLTGOT16_HI
:
6686 case BFD_RELOC_PPC64_PLTGOT16_HA
:
6687 case BFD_RELOC_PPC64_GOT16_DS
:
6688 case BFD_RELOC_PPC64_GOT16_LO_DS
:
6689 case BFD_RELOC_PPC64_PLT16_LO_DS
:
6690 case BFD_RELOC_PPC64_SECTOFF_DS
:
6691 case BFD_RELOC_PPC64_SECTOFF_LO_DS
:
6692 case BFD_RELOC_PPC64_TOC16_DS
:
6693 case BFD_RELOC_PPC64_TOC16_LO_DS
:
6694 case BFD_RELOC_PPC64_PLTGOT16_DS
:
6695 case BFD_RELOC_PPC64_PLTGOT16_LO_DS
:
6696 case BFD_RELOC_PPC_EMB_NADDR16
:
6697 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
6698 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
6699 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
6700 case BFD_RELOC_PPC_EMB_SDAI16
:
6701 case BFD_RELOC_PPC_EMB_SDA2I16
:
6702 case BFD_RELOC_PPC_EMB_SDA2REL
:
6703 case BFD_RELOC_PPC_EMB_SDA21
:
6704 case BFD_RELOC_PPC_EMB_MRKREF
:
6705 case BFD_RELOC_PPC_EMB_RELSEC16
:
6706 case BFD_RELOC_PPC_EMB_RELST_LO
:
6707 case BFD_RELOC_PPC_EMB_RELST_HI
:
6708 case BFD_RELOC_PPC_EMB_RELST_HA
:
6709 case BFD_RELOC_PPC_EMB_BIT_FLD
:
6710 case BFD_RELOC_PPC_EMB_RELSDA
:
6711 case BFD_RELOC_PPC_VLE_SDA21
:
6712 case BFD_RELOC_PPC_VLE_SDA21_LO
:
6713 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
6714 case BFD_RELOC_PPC_VLE_SDAREL_LO16D
:
6715 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
6716 case BFD_RELOC_PPC_VLE_SDAREL_HI16D
:
6717 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
6718 case BFD_RELOC_PPC_VLE_SDAREL_HA16D
:
6719 case BFD_RELOC_PPC64_GOT_PCREL34
:
6720 case BFD_RELOC_PPC64_PLT_PCREL34
:
6721 gas_assert (fixP
->fx_addsy
!= NULL
);
6724 case BFD_RELOC_PPC_TLS
:
6725 case BFD_RELOC_PPC_TLSGD
:
6726 case BFD_RELOC_PPC_TLSLD
:
6727 case BFD_RELOC_PPC64_TLS_PCREL
:
6733 case BFD_RELOC_PPC_B16
:
6734 /* Adjust the offset to the instruction boundary. */
6739 case BFD_RELOC_VTABLE_INHERIT
:
6740 case BFD_RELOC_VTABLE_ENTRY
:
6741 case BFD_RELOC_PPC_DTPMOD
:
6742 case BFD_RELOC_PPC_TPREL
:
6743 case BFD_RELOC_PPC_DTPREL
:
6744 case BFD_RELOC_PPC_COPY
:
6745 case BFD_RELOC_PPC_GLOB_DAT
:
6746 case BFD_RELOC_32_PLT_PCREL
:
6747 case BFD_RELOC_PPC_EMB_NADDR32
:
6748 case BFD_RELOC_PPC64_TOC
:
6749 case BFD_RELOC_CTOR
:
6751 case BFD_RELOC_32_PCREL
:
6754 case BFD_RELOC_64_PCREL
:
6755 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
6756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6757 _("%s unsupported as instruction fixup"),
6758 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6767 /* powerpc uses RELA style relocs, so if emitting a reloc the field
6768 contents can stay at zero. */
6769 #define APPLY_RELOC fixP->fx_done
6771 #define APPLY_RELOC 1
6773 /* We need to call the insert function even when fieldval is
6774 zero if the insert function would translate that zero to a
6775 bit pattern other than all zeros. */
6776 if ((fieldval
!= 0 && APPLY_RELOC
) || operand
->insert
!= NULL
)
6779 unsigned char *where
;
6781 /* Fetch the instruction, insert the fully resolved operand
6782 value, and stuff the instruction back again. */
6783 where
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6784 if (target_big_endian
)
6786 if (fixP
->fx_size
< 4)
6787 insn
= bfd_getb16 (where
);
6790 insn
= bfd_getb32 (where
);
6791 if (fixP
->fx_size
> 4)
6792 insn
= insn
<< 32 | bfd_getb32 (where
+ 4);
6797 if (fixP
->fx_size
< 4)
6798 insn
= bfd_getl16 (where
);
6801 insn
= bfd_getl32 (where
);
6802 if (fixP
->fx_size
> 4)
6803 insn
= insn
<< 32 | bfd_getl32 (where
+ 4);
6806 insn
= ppc_insert_operand (insn
, operand
, fieldval
,
6807 fixP
->tc_fix_data
.ppc_cpu
,
6808 fixP
->fx_file
, fixP
->fx_line
);
6809 if (target_big_endian
)
6811 if (fixP
->fx_size
< 4)
6812 bfd_putb16 (insn
, where
);
6815 if (fixP
->fx_size
> 4)
6817 bfd_putb32 (insn
, where
+ 4);
6820 bfd_putb32 (insn
, where
);
6825 if (fixP
->fx_size
< 4)
6826 bfd_putl16 (insn
, where
);
6829 if (fixP
->fx_size
> 4)
6831 bfd_putl32 (insn
, where
+ 4);
6834 bfd_putl32 (insn
, where
);
6840 /* Nothing else to do here. */
6843 gas_assert (fixP
->fx_addsy
!= NULL
);
6844 if (fixP
->fx_r_type
== BFD_RELOC_NONE
)
6849 /* Use expr_symbol_where to see if this is an expression
6851 if (expr_symbol_where (fixP
->fx_addsy
, &sfile
, &sline
))
6852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6853 _("unresolved expression that must be resolved"));
6855 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6856 _("unsupported relocation against %s"),
6857 S_GET_NAME (fixP
->fx_addsy
));
6864 /* Handle relocs in data. */
6865 switch (fixP
->fx_r_type
)
6867 case BFD_RELOC_VTABLE_INHERIT
:
6869 && !S_IS_DEFINED (fixP
->fx_addsy
)
6870 && !S_IS_WEAK (fixP
->fx_addsy
))
6871 S_SET_WEAK (fixP
->fx_addsy
);
6874 case BFD_RELOC_VTABLE_ENTRY
:
6879 /* These can appear with @l etc. in data. */
6880 case BFD_RELOC_LO16
:
6881 case BFD_RELOC_LO16_PCREL
:
6882 case BFD_RELOC_HI16
:
6883 case BFD_RELOC_HI16_PCREL
:
6884 case BFD_RELOC_HI16_S
:
6885 case BFD_RELOC_HI16_S_PCREL
:
6886 case BFD_RELOC_PPC64_HIGHER
:
6887 case BFD_RELOC_PPC64_HIGHER_S
:
6888 case BFD_RELOC_PPC64_HIGHEST
:
6889 case BFD_RELOC_PPC64_HIGHEST_S
:
6890 case BFD_RELOC_PPC64_ADDR16_HIGH
:
6891 case BFD_RELOC_PPC64_ADDR16_HIGHA
:
6892 case BFD_RELOC_PPC64_ADDR64_LOCAL
:
6895 case BFD_RELOC_PPC_DTPMOD
:
6896 case BFD_RELOC_PPC_TPREL
:
6897 case BFD_RELOC_PPC_DTPREL
:
6898 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6901 /* Just punt all of these to the linker. */
6902 case BFD_RELOC_PPC_B16_BRTAKEN
:
6903 case BFD_RELOC_PPC_B16_BRNTAKEN
:
6904 case BFD_RELOC_16_GOTOFF
:
6905 case BFD_RELOC_LO16_GOTOFF
:
6906 case BFD_RELOC_HI16_GOTOFF
:
6907 case BFD_RELOC_HI16_S_GOTOFF
:
6908 case BFD_RELOC_LO16_PLTOFF
:
6909 case BFD_RELOC_HI16_PLTOFF
:
6910 case BFD_RELOC_HI16_S_PLTOFF
:
6911 case BFD_RELOC_PPC_COPY
:
6912 case BFD_RELOC_PPC_GLOB_DAT
:
6913 case BFD_RELOC_16_BASEREL
:
6914 case BFD_RELOC_LO16_BASEREL
:
6915 case BFD_RELOC_HI16_BASEREL
:
6916 case BFD_RELOC_HI16_S_BASEREL
:
6917 case BFD_RELOC_PPC_TLS
:
6918 case BFD_RELOC_PPC_DTPREL16_LO
:
6919 case BFD_RELOC_PPC_DTPREL16_HI
:
6920 case BFD_RELOC_PPC_DTPREL16_HA
:
6921 case BFD_RELOC_PPC_TPREL16_LO
:
6922 case BFD_RELOC_PPC_TPREL16_HI
:
6923 case BFD_RELOC_PPC_TPREL16_HA
:
6924 case BFD_RELOC_PPC_GOT_TLSGD16
:
6925 case BFD_RELOC_PPC_GOT_TLSGD16_LO
:
6926 case BFD_RELOC_PPC_GOT_TLSGD16_HI
:
6927 case BFD_RELOC_PPC_GOT_TLSGD16_HA
:
6928 case BFD_RELOC_PPC_GOT_TLSLD16
:
6929 case BFD_RELOC_PPC_GOT_TLSLD16_LO
:
6930 case BFD_RELOC_PPC_GOT_TLSLD16_HI
:
6931 case BFD_RELOC_PPC_GOT_TLSLD16_HA
:
6932 case BFD_RELOC_PPC_GOT_DTPREL16
:
6933 case BFD_RELOC_PPC_GOT_DTPREL16_LO
:
6934 case BFD_RELOC_PPC_GOT_DTPREL16_HI
:
6935 case BFD_RELOC_PPC_GOT_DTPREL16_HA
:
6936 case BFD_RELOC_PPC_GOT_TPREL16
:
6937 case BFD_RELOC_PPC_GOT_TPREL16_LO
:
6938 case BFD_RELOC_PPC_GOT_TPREL16_HI
:
6939 case BFD_RELOC_PPC_GOT_TPREL16_HA
:
6940 case BFD_RELOC_24_PLT_PCREL
:
6941 case BFD_RELOC_PPC_LOCAL24PC
:
6942 case BFD_RELOC_32_PLT_PCREL
:
6943 case BFD_RELOC_GPREL16
:
6944 case BFD_RELOC_PPC_VLE_SDAREL_LO16A
:
6945 case BFD_RELOC_PPC_VLE_SDAREL_HI16A
:
6946 case BFD_RELOC_PPC_VLE_SDAREL_HA16A
:
6947 case BFD_RELOC_PPC_EMB_NADDR32
:
6948 case BFD_RELOC_PPC_EMB_NADDR16
:
6949 case BFD_RELOC_PPC_EMB_NADDR16_LO
:
6950 case BFD_RELOC_PPC_EMB_NADDR16_HI
:
6951 case BFD_RELOC_PPC_EMB_NADDR16_HA
:
6952 case BFD_RELOC_PPC_EMB_SDAI16
:
6953 case BFD_RELOC_PPC_EMB_SDA2REL
:
6954 case BFD_RELOC_PPC_EMB_SDA2I16
:
6955 case BFD_RELOC_PPC_EMB_SDA21
:
6956 case BFD_RELOC_PPC_VLE_SDA21_LO
:
6957 case BFD_RELOC_PPC_EMB_MRKREF
:
6958 case BFD_RELOC_PPC_EMB_RELSEC16
:
6959 case BFD_RELOC_PPC_EMB_RELST_LO
:
6960 case BFD_RELOC_PPC_EMB_RELST_HI
:
6961 case BFD_RELOC_PPC_EMB_RELST_HA
:
6962 case BFD_RELOC_PPC_EMB_BIT_FLD
:
6963 case BFD_RELOC_PPC_EMB_RELSDA
:
6964 case BFD_RELOC_PPC64_TOC
:
6965 case BFD_RELOC_PPC_TOC16
:
6966 case BFD_RELOC_PPC64_TOC16_LO
:
6967 case BFD_RELOC_PPC64_TOC16_HI
:
6968 case BFD_RELOC_PPC64_TOC16_HA
:
6969 case BFD_RELOC_PPC64_DTPREL16_HIGH
:
6970 case BFD_RELOC_PPC64_DTPREL16_HIGHA
:
6971 case BFD_RELOC_PPC64_DTPREL16_HIGHER
:
6972 case BFD_RELOC_PPC64_DTPREL16_HIGHERA
:
6973 case BFD_RELOC_PPC64_DTPREL16_HIGHEST
:
6974 case BFD_RELOC_PPC64_DTPREL16_HIGHESTA
:
6975 case BFD_RELOC_PPC64_TPREL16_HIGH
:
6976 case BFD_RELOC_PPC64_TPREL16_HIGHA
:
6977 case BFD_RELOC_PPC64_TPREL16_HIGHER
:
6978 case BFD_RELOC_PPC64_TPREL16_HIGHERA
:
6979 case BFD_RELOC_PPC64_TPREL16_HIGHEST
:
6980 case BFD_RELOC_PPC64_TPREL16_HIGHESTA
:
6981 case BFD_RELOC_PPC64_TLS_PCREL
:
6987 case BFD_RELOC_NONE
:
6989 case BFD_RELOC_CTOR
:
6991 case BFD_RELOC_32_PCREL
:
6994 case BFD_RELOC_64_PCREL
:
6996 case BFD_RELOC_16_PCREL
:
7002 _("Gas failure, reloc value %d\n"), fixP
->fx_r_type
);
7007 if (fixP
->fx_size
&& APPLY_RELOC
)
7008 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
7009 fieldval
, fixP
->fx_size
);
7011 && (seg
->flags
& SEC_CODE
) != 0
7012 && fixP
->fx_size
== 4
7015 && (fixP
->fx_r_type
== BFD_RELOC_32
7016 || fixP
->fx_r_type
== BFD_RELOC_CTOR
7017 || fixP
->fx_r_type
== BFD_RELOC_32_PCREL
))
7018 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
7019 _("data in executable section"));
7023 ppc_elf_validate_fix (fixP
, seg
);
7024 fixP
->fx_addnumber
= value
;
7026 /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately
7027 from the section contents. If we are going to be emitting a reloc
7028 then the section contents are immaterial, so don't warn if they
7029 happen to overflow. Leave such warnings to ld. */
7032 fixP
->fx_no_overflow
= 1;
7034 /* Arrange to emit .TOC. as a normal symbol if used in anything
7035 but .TOC.@tocbase. */
7037 && fixP
->fx_r_type
!= BFD_RELOC_PPC64_TOC
7038 && fixP
->fx_addsy
!= NULL
7039 && strcmp (S_GET_NAME (fixP
->fx_addsy
), ".TOC.") == 0)
7040 symbol_get_bfdsym (fixP
->fx_addsy
)->flags
|= BSF_KEEP
;
7043 if (fixP
->fx_r_type
!= BFD_RELOC_PPC_TOC16
)
7044 fixP
->fx_addnumber
= 0;
7047 /* We want to use the offset within the toc, not the actual VMA
7049 fixP
->fx_addnumber
= (- bfd_section_vma (S_GET_SEGMENT (fixP
->fx_addsy
))
7050 - S_GET_VALUE (ppc_toc_csect
));
7051 /* Set *valP to avoid errors. */
7057 /* Generate a reloc for a fixup. */
7060 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
7064 reloc
= XNEW (arelent
);
7066 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
7067 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
7068 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7069 /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */
7070 if (fixp
->fx_r_type
== BFD_RELOC_PPC64_TLS_PCREL
)
7072 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7073 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
7075 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7076 _("reloc %d not supported by object file format"),
7077 (int) fixp
->fx_r_type
);
7080 reloc
->addend
= fixp
->fx_addnumber
;
7086 ppc_cfi_frame_initial_instructions (void)
7088 cfi_add_CFA_def_cfa (1, 0);
7092 tc_ppc_regname_to_dw2regnum (char *regname
)
7094 unsigned int regnum
= -1;
7098 static struct { const char *name
; int dw2regnum
; } regnames
[] =
7100 { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 },
7101 { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 },
7102 { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 },
7103 { "spe_acc", 111 }, { "spefscr", 112 }
7106 for (i
= 0; i
< ARRAY_SIZE (regnames
); ++i
)
7107 if (strcmp (regnames
[i
].name
, regname
) == 0)
7108 return regnames
[i
].dw2regnum
;
7110 if (regname
[0] == 'r' || regname
[0] == 'f' || regname
[0] == 'v')
7112 p
= regname
+ 1 + (regname
[1] == '.');
7113 regnum
= strtoul (p
, &q
, 10);
7114 if (p
== q
|| *q
|| regnum
>= 32)
7116 if (regname
[0] == 'f')
7118 else if (regname
[0] == 'v')
7121 else if (regname
[0] == 'c' && regname
[1] == 'r')
7123 p
= regname
+ 2 + (regname
[2] == '.');
7124 if (p
[0] < '0' || p
[0] > '7' || p
[1])
7126 regnum
= p
[0] - '0' + 68;