1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 FLOAT_ABI_DEFAULT
= -1,
101 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
103 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
104 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
106 static unsigned elf_flags
= 0;
108 /* Set the default_isa_spec. Return 0 if the input spec string isn't
109 supported. Otherwise, return 1. */
112 riscv_set_default_isa_spec (const char *s
)
114 enum riscv_isa_spec_class
class;
115 if (!riscv_get_isa_spec_class (s
, &class))
117 as_bad ("Unknown default ISA spec `%s' set by "
118 "-misa-spec or --with-isa-spec", s
);
122 default_isa_spec
= class;
126 /* Set the default_priv_spec, assembler will find the suitable CSR address
127 according to default_priv_spec. We will try to check priv attributes if
128 the input string is NULL. Return 0 if the input priv spec string isn't
129 supported. Otherwise, return 1. */
132 riscv_set_default_priv_spec (const char *s
)
134 enum riscv_priv_spec_class
class;
135 unsigned major
, minor
, revision
;
138 /* Find the corresponding priv spec class. */
139 if (riscv_get_priv_spec_class (s
, &class))
141 default_priv_spec
= class;
147 as_bad (_("Unknown default privilege spec `%s' set by "
148 "-mpriv-spec or --with-priv-spec"), s
);
152 /* Try to set the default_priv_spec according to the priv attributes. */
153 attr
= elf_known_obj_attributes_proc (stdoutput
);
154 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
155 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
156 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
158 if (riscv_get_priv_spec_class_from_numbers (major
,
163 /* The priv attributes setting 0.0.0 is meaningless. We should have set
164 the default_priv_spec by md_parse_option and riscv_after_parse_args,
165 so just skip the following setting. */
166 if (class == PRIV_SPEC_CLASS_NONE
)
169 default_priv_spec
= class;
173 /* Still can not find the priv spec class. */
174 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
175 "privilege attributes"), major
, minor
, revision
);
179 /* This is the set of options which the .option pseudo-op may modify. */
181 struct riscv_set_options
183 int pic
; /* Generate position-independent code. */
184 int rvc
; /* Generate RVC code. */
185 int rve
; /* Generate RVE code. */
186 int relax
; /* Emit relocs the linker is allowed to relax. */
187 int arch_attr
; /* Emit arch attribute. */
188 int csr_check
; /* Enable the CSR checking. */
191 static struct riscv_set_options riscv_opts
=
197 DEFAULT_RISCV_ATTR
, /* arch_attr */
202 riscv_set_rvc (bfd_boolean rvc_value
)
205 elf_flags
|= EF_RISCV_RVC
;
207 riscv_opts
.rvc
= rvc_value
;
211 riscv_set_rve (bfd_boolean rve_value
)
213 riscv_opts
.rve
= rve_value
;
216 static riscv_subset_list_t riscv_subsets
;
219 riscv_subset_supports (const char *feature
)
221 struct riscv_subset_t
*subset
;
223 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
226 return riscv_lookup_subset (&riscv_subsets
, feature
, &subset
);
230 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
234 case INSN_CLASS_I
: return riscv_subset_supports ("i");
235 case INSN_CLASS_C
: return riscv_subset_supports ("c");
236 case INSN_CLASS_A
: return riscv_subset_supports ("a");
237 case INSN_CLASS_M
: return riscv_subset_supports ("m");
238 case INSN_CLASS_F
: return riscv_subset_supports ("f");
239 case INSN_CLASS_D
: return riscv_subset_supports ("d");
240 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
242 case INSN_CLASS_F_AND_C
:
243 return (riscv_subset_supports ("f")
244 && riscv_subset_supports ("c"));
245 case INSN_CLASS_D_AND_C
:
246 return (riscv_subset_supports ("d")
247 && riscv_subset_supports ("c"));
249 case INSN_CLASS_ZICSR
:
250 return riscv_subset_supports ("zicsr");
251 case INSN_CLASS_ZIFENCEI
:
252 return riscv_subset_supports ("zifencei");
255 as_fatal ("Unreachable");
260 /* Handle of the extension with version hash table. */
261 static htab_t ext_version_hash
= NULL
;
264 init_ext_version_hash (const struct riscv_ext_version
*table
)
267 htab_t hash
= str_htab_create ();
269 while (table
[i
].name
)
271 const char *name
= table
[i
].name
;
272 if (str_hash_insert (hash
, name
, &table
[i
], 0) != NULL
)
273 as_fatal (_("duplicate %s"), name
);
277 && strcmp (table
[i
].name
, name
) == 0)
285 riscv_get_default_ext_version (const char *name
,
289 struct riscv_ext_version
*ext
;
291 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
294 ext
= (struct riscv_ext_version
*) str_hash_find (ext_version_hash
, name
);
297 && strcmp (ext
->name
, name
) == 0)
299 if (ext
->isa_spec_class
== default_isa_spec
)
301 *major_version
= ext
->major_version
;
302 *minor_version
= ext
->minor_version
;
309 /* Set which ISA and extensions are available. */
312 riscv_set_arch (const char *s
)
314 riscv_parse_subset_t rps
;
315 rps
.subset_list
= &riscv_subsets
;
316 rps
.error_handler
= as_bad
;
318 rps
.get_default_version
= riscv_get_default_ext_version
;
323 riscv_release_subset_list (&riscv_subsets
);
324 riscv_parse_subset (&rps
, s
);
327 /* Indicate -mabi= option is explictly set. */
328 static bfd_boolean explicit_mabi
= FALSE
;
331 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
334 float_abi
= new_float_abi
;
338 /* If the -mabi option isn't set, then we set the abi according to the arch
339 string. Otherwise, check if there are conflicts between architecture
343 riscv_set_abi_by_arch (void)
347 if (riscv_subset_supports ("q"))
348 riscv_set_abi (xlen
, FLOAT_ABI_QUAD
, FALSE
);
349 else if (riscv_subset_supports ("d"))
350 riscv_set_abi (xlen
, FLOAT_ABI_DOUBLE
, FALSE
);
352 riscv_set_abi (xlen
, FLOAT_ABI_SOFT
, FALSE
);
356 gas_assert (abi_xlen
!= 0 && xlen
!= 0 && float_abi
!= FLOAT_ABI_DEFAULT
);
358 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
359 else if (abi_xlen
< xlen
)
360 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
363 /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
364 elf_flags
&= ~EF_RISCV_FLOAT_ABI
;
365 elf_flags
|= float_abi
<< 1;
368 elf_flags
|= EF_RISCV_RVE
;
371 /* Handle of the OPCODE hash table. */
372 static htab_t op_hash
= NULL
;
374 /* Handle of the type of .insn hash table. */
375 static htab_t insn_type_hash
= NULL
;
377 /* This array holds the chars that always start a comment. If the
378 pre-processor is disabled, these aren't very useful */
379 const char comment_chars
[] = "#";
381 /* This array holds the chars that only start a comment at the beginning of
382 a line. If the line seems to have the form '# 123 filename'
383 .line and .file directives will appear in the pre-processed output */
384 /* Note that input_file.c hand checks for '#' at the beginning of the
385 first line of the input file. This is because the compiler outputs
386 #NO_APP at the beginning of its output. */
387 /* Also note that C style comments are always supported. */
388 const char line_comment_chars
[] = "#";
390 /* This array holds machine specific line separator characters. */
391 const char line_separator_chars
[] = ";";
393 /* Chars that can be used to separate mant from exp in floating point nums */
394 const char EXP_CHARS
[] = "eE";
396 /* Chars that mean this number is a floating point constant */
399 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
401 /* Indicate we are already assemble any instructions or not. */
402 static bfd_boolean start_assemble
= FALSE
;
404 /* Indicate ELF attributes are explicitly set. */
405 static bfd_boolean explicit_attr
= FALSE
;
407 /* Indicate CSR or priv instructions are explicitly used. */
408 static bfd_boolean explicit_priv_attr
= FALSE
;
410 /* Macros for encoding relaxation state for RVC branches and far jumps. */
411 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
414 | ((uncond) ? 1 : 0) \
417 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
418 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
419 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
420 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
422 /* Is the given value a sign-extended 32-bit value? */
423 #define IS_SEXT_32BIT_NUM(x) \
424 (((x) &~ (offsetT) 0x7fffffff) == 0 \
425 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
427 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
428 #define IS_ZEXT_32BIT_NUM(x) \
429 (((x) &~ (offsetT) 0xffffffff) == 0 \
430 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
432 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
433 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
434 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
435 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
437 /* Determine if an instruction matches an opcode. */
438 #define OPCODE_MATCHES(OPCODE, OP) \
439 (((OPCODE) & MASK_##OP) == MATCH_##OP)
441 static char *expr_end
;
443 /* The default target format to use. */
446 riscv_target_format (void)
448 if (target_big_endian
)
449 return xlen
== 64 ? "elf64-bigriscv" : "elf32-bigriscv";
451 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
454 /* Return the length of instruction INSN. */
456 static inline unsigned int
457 insn_length (const struct riscv_cl_insn
*insn
)
459 return riscv_insn_length (insn
->insn_opcode
);
462 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
465 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
468 insn
->insn_opcode
= mo
->match
;
474 /* Install INSN at the location specified by its "frag" and "where" fields. */
477 install_insn (const struct riscv_cl_insn
*insn
)
479 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
480 number_to_chars_littleendian (f
, insn
->insn_opcode
, insn_length (insn
));
483 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
484 and install the opcode in the new location. */
487 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
491 if (insn
->fixp
!= NULL
)
493 insn
->fixp
->fx_frag
= frag
;
494 insn
->fixp
->fx_where
= where
;
499 /* Add INSN to the end of the output. */
502 add_fixed_insn (struct riscv_cl_insn
*insn
)
504 char *f
= frag_more (insn_length (insn
));
505 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
509 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
510 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
512 frag_grow (max_chars
);
513 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
514 frag_var (rs_machine_dependent
, max_chars
, var
,
515 subtype
, symbol
, offset
, NULL
);
518 /* Compute the length of a branch sequence, and adjust the stored length
519 accordingly. If FRAGP is NULL, the worst-case length is returned. */
522 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
524 int jump
, rvc
, length
= 8;
529 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
530 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
531 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
533 /* Assume jumps are in range; the linker will catch any that aren't. */
534 length
= jump
? 4 : 8;
536 if (fragp
->fr_symbol
!= NULL
537 && S_IS_DEFINED (fragp
->fr_symbol
)
538 && !S_IS_WEAK (fragp
->fr_symbol
)
539 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
541 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
542 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
543 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
545 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
547 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
549 else if (!jump
&& rvc
)
554 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
559 /* Information about an opcode name, mnemonics and its value. */
566 /* List for all supported opcode name. */
567 static const struct opcode_name_t opcode_name_list
[] =
612 /* Hash table for lookup opcode name. */
613 static htab_t opcode_names_hash
= NULL
;
615 /* Initialization for hash table of opcode name. */
617 init_opcode_names_hash (void)
619 const struct opcode_name_t
*opcode
;
621 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
622 if (str_hash_insert (opcode_names_hash
, opcode
->name
, opcode
, 0) != NULL
)
623 as_fatal (_("duplicate %s"), opcode
->name
);
626 /* Find `s` is a valid opcode name or not,
627 return the opcode name info if found. */
628 static const struct opcode_name_t
*
629 opcode_name_lookup (char **s
)
633 struct opcode_name_t
*o
;
635 /* Find end of name. */
637 if (is_name_beginner (*e
))
639 while (is_part_of_name (*e
))
642 /* Terminate name. */
646 o
= (struct opcode_name_t
*) str_hash_find (opcode_names_hash
, *s
);
648 /* Advance to next token if one was recognized. */
667 static htab_t reg_names_hash
= NULL
;
668 static htab_t csr_extra_hash
= NULL
;
670 #define ENCODE_REG_HASH(cls, n) \
671 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
672 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
673 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
676 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
678 void *hash
= ENCODE_REG_HASH (class, n
);
679 if (str_hash_insert (reg_names_hash
, name
, hash
, 0) != NULL
)
680 as_fatal (_("duplicate %s"), name
);
684 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
688 for (i
= 0; i
< n
; i
++)
689 hash_reg_name (class, names
[i
], i
);
692 /* Init hash table csr_extra_hash to handle CSR. */
694 riscv_init_csr_hash (const char *name
,
696 enum riscv_csr_class
class,
697 enum riscv_priv_spec_class define_version
,
698 enum riscv_priv_spec_class abort_version
)
700 struct riscv_csr_extra
*entry
, *pre_entry
;
701 bfd_boolean need_enrty
= TRUE
;
704 entry
= (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, name
);
705 while (need_enrty
&& entry
!= NULL
)
707 if (entry
->csr_class
== class
708 && entry
->address
== address
709 && entry
->define_version
== define_version
710 && entry
->abort_version
== abort_version
)
716 /* Duplicate setting for the CSR, just return and do nothing. */
720 entry
= XNEW (struct riscv_csr_extra
);
721 entry
->csr_class
= class;
722 entry
->address
= address
;
723 entry
->define_version
= define_version
;
724 entry
->abort_version
= abort_version
;
727 /* If the CSR hasn't been inserted in the hash table, then insert it.
728 Otherwise, attach the extra information to the entry which is already
729 in the hash table. */
730 if (pre_entry
== NULL
)
731 str_hash_insert (csr_extra_hash
, name
, entry
, 0);
733 pre_entry
->next
= entry
;
736 /* Return the suitable CSR address after checking the ISA dependency and
737 priv spec versions. */
740 riscv_csr_address (const char *csr_name
,
741 struct riscv_csr_extra
*entry
)
743 struct riscv_csr_extra
*saved_entry
= entry
;
744 enum riscv_csr_class csr_class
= entry
->csr_class
;
745 bfd_boolean need_check_version
= TRUE
;
746 bfd_boolean result
= TRUE
;
751 result
= riscv_subset_supports ("i");
754 result
= (xlen
== 32 && riscv_subset_supports ("i"));
757 result
= riscv_subset_supports ("f");
758 need_check_version
= FALSE
;
760 case CSR_CLASS_DEBUG
:
761 need_check_version
= FALSE
;
764 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
767 /* Don't report the ISA conflict when -mcsr-check isn't set. */
768 if (riscv_opts
.csr_check
&& !result
)
769 as_warn (_("Invalid CSR `%s' for the current ISA"), csr_name
);
771 while (entry
!= NULL
)
773 if (!need_check_version
774 || (default_priv_spec
>= entry
->define_version
775 && default_priv_spec
< entry
->abort_version
))
777 /* Find the suitable CSR according to the specific version. */
778 return entry
->address
;
783 /* We can not find the suitable CSR address according to the privilege
784 version. Therefore, we use the last defined value. Report the warning
785 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
786 otherwise, you may get the unexpected CSR address. */
787 if (riscv_opts
.csr_check
)
789 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
791 if (priv_name
!= NULL
)
792 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
793 csr_name
, priv_name
);
796 return saved_entry
->address
;
799 /* Once the CSR is defined, including the old privilege spec, then we call
800 riscv_csr_class_check and riscv_csr_version_check to do the further checking
801 and get the corresponding address. Return -1 if the CSR is never been
802 defined. Otherwise, return the address. */
805 reg_csr_lookup_internal (const char *s
)
807 struct riscv_csr_extra
*r
=
808 (struct riscv_csr_extra
*) str_hash_find (csr_extra_hash
, s
);
813 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
814 the CSR was defined, but isn't allowed for the current ISA setting or
815 the privilege spec. If the CSR is never been defined, then assembler
816 will regard it as a "Unknown CSR" and report error. If user use number
817 to set the CSR, but over the range (> 0xfff), then assembler will report
818 "Improper CSR" error for it. */
819 return riscv_csr_address (s
, r
);
823 reg_lookup_internal (const char *s
, enum reg_class
class)
827 if (class == RCLASS_CSR
)
828 return reg_csr_lookup_internal (s
);
830 r
= str_hash_find (reg_names_hash
, s
);
831 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
834 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
837 return DECODE_REG_NUM (r
);
841 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
847 /* Find end of name. */
849 if (is_name_beginner (*e
))
851 while (is_part_of_name (*e
))
854 /* Terminate name. */
858 /* Look for the register. Advance to next token if one was recognized. */
859 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
869 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
871 const char *p
= strchr (*s
, ',');
872 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
877 for (i
= 0; i
< size
; i
++)
878 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
888 /* For consistency checking, verify that all bits are specified either
889 by the match/mask part of the instruction definition, or by the
892 `length` could be 0, 4 or 8, 0 for auto detection. */
894 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
896 const char *p
= opc
->args
;
898 insn_t used_bits
= opc
->mask
;
900 insn_t required_bits
;
903 insn_width
= 8 * riscv_insn_length (opc
->match
);
905 insn_width
= 8 * length
;
907 required_bits
= ~0ULL >> (64 - insn_width
);
909 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
911 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
912 opc
->name
, opc
->args
);
916 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
923 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
924 case 'c': break; /* RS1, constrained to equal sp */
925 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
926 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
927 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
928 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
929 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
930 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
931 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
932 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
933 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
934 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
935 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
936 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
937 case 'w': break; /* RS1S, constrained to equal RD */
938 case 'x': break; /* RS2S, constrained to equal RD */
939 case 'z': break; /* RS2S, contrained to be x0 */
940 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
941 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
942 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
943 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
944 case 'U': break; /* RS1, constrained to equal RD */
945 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
946 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
947 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
948 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
949 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
950 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
951 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
952 case 'F': /* funct */
955 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
956 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
957 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
958 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
960 as_bad (_("internal: bad RISC-V opcode"
961 " (unknown operand type `CF%c'): %s %s"),
962 c
, opc
->name
, opc
->args
);
967 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
968 c
, opc
->name
, opc
->args
);
975 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
976 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
978 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
979 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
980 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
982 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
983 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
984 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
985 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
986 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
987 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
988 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
989 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
990 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
991 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
992 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
994 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
995 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
996 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
997 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
998 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
1004 case 'F': /* funct */
1007 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
1008 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
1009 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1011 as_bad (_("internal: bad RISC-V opcode"
1012 " (unknown operand type `F%c'): %s %s"),
1013 c
, opc
->name
, opc
->args
);
1017 case 'O': /* opcode */
1020 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1021 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1023 as_bad (_("internal: bad RISC-V opcode"
1024 " (unknown operand type `F%c'): %s %s"),
1025 c
, opc
->name
, opc
->args
);
1030 as_bad (_("internal: bad RISC-V opcode "
1031 "(unknown operand type `%c'): %s %s"),
1032 c
, opc
->name
, opc
->args
);
1036 if (used_bits
!= required_bits
)
1038 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1039 ~(unsigned long)(used_bits
& required_bits
),
1040 opc
->name
, opc
->args
);
1046 struct percent_op_match
1049 bfd_reloc_code_real_type reloc
;
1052 /* Common hash table initialization function for
1053 instruction and .insn directive. */
1055 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1056 bfd_boolean insn_directive_p
)
1060 htab_t hash
= str_htab_create ();
1061 while (opcodes
[i
].name
)
1063 const char *name
= opcodes
[i
].name
;
1064 if (str_hash_insert (hash
, name
, &opcodes
[i
], 0) != NULL
)
1065 as_fatal (_("duplicate %s"), name
);
1069 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1071 if (insn_directive_p
)
1072 length
= ((name
[0] == 'c') ? 2 : 4);
1074 length
= 0; /* Let assembler determine the length. */
1075 if (!validate_riscv_insn (&opcodes
[i
], length
))
1076 as_fatal (_("Broken assembler. No assembly attempted."));
1079 gas_assert (!insn_directive_p
);
1082 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1088 /* This function is called once, at assembler startup time. It should set up
1089 all the tables, etc. that the MD part of the assembler will need. */
1094 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1096 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1097 as_warn (_("Could not set architecture and machine"));
1099 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1100 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1102 reg_names_hash
= str_htab_create ();
1103 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1104 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1105 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1106 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1107 /* Add "fp" as an alias for "s0". */
1108 hash_reg_name (RCLASS_GPR
, "fp", 8);
1110 /* Create and insert CSR hash tables. */
1111 csr_extra_hash
= str_htab_create ();
1112 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1113 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1114 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1115 DECLARE_CSR(name, num, class, define_version, abort_version);
1116 #include "opcode/riscv-opc.h"
1119 opcode_names_hash
= str_htab_create ();
1120 init_opcode_names_hash ();
1122 /* Set the default alignment for the text section. */
1123 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1127 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1134 case BFD_RELOC_RISCV_HI20
:
1135 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1137 case BFD_RELOC_RISCV_LO12_S
:
1138 return ENCODE_STYPE_IMM (value
);
1140 case BFD_RELOC_RISCV_LO12_I
:
1141 return ENCODE_ITYPE_IMM (value
);
1148 /* Output an instruction. IP is the instruction information.
1149 ADDRESS_EXPR is an operand of the instruction to be used with
1153 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1154 bfd_reloc_code_real_type reloc_type
)
1156 dwarf2_emit_insn (0);
1158 if (reloc_type
!= BFD_RELOC_UNUSED
)
1160 reloc_howto_type
*howto
;
1162 gas_assert (address_expr
);
1163 if (reloc_type
== BFD_RELOC_12_PCREL
1164 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1166 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1167 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1168 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1170 if (now_seg
== absolute_section
)
1172 as_bad (_("relaxable branches not supported in absolute section"));
1176 add_relaxed_insn (ip
, worst_case
, best_case
,
1177 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1178 address_expr
->X_add_symbol
,
1179 address_expr
->X_add_number
);
1184 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1186 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1188 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1189 bfd_get_reloc_size (howto
),
1190 address_expr
, FALSE
, reloc_type
);
1192 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1196 add_fixed_insn (ip
);
1199 /* We need to start a new frag after any instruction that can be
1200 optimized away or compressed by the linker during relaxation, to prevent
1201 the assembler from computing static offsets across such an instruction.
1202 This is necessary to get correct EH info. */
1203 if (reloc_type
== BFD_RELOC_RISCV_HI20
1204 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1205 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1206 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1208 frag_wane (frag_now
);
1213 /* Build an instruction created by a macro expansion. This is passed
1214 a pointer to the count of instructions created so far, an
1215 expression, the name of the instruction to build, an operand format
1216 string, and corresponding arguments. */
1219 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1221 const struct riscv_opcode
*mo
;
1222 struct riscv_cl_insn insn
;
1223 bfd_reloc_code_real_type r
;
1226 va_start (args
, fmt
);
1228 r
= BFD_RELOC_UNUSED
;
1229 mo
= (struct riscv_opcode
*) str_hash_find (op_hash
, name
);
1232 /* Find a non-RVC variant of the instruction. append_insn will compress
1234 while (riscv_insn_length (mo
->match
) < 4)
1236 gas_assert (strcmp (name
, mo
->name
) == 0);
1238 create_insn (&insn
, mo
);
1244 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1248 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1252 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1256 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1262 gas_assert (ep
!= NULL
);
1263 r
= va_arg (args
, int);
1271 as_fatal (_("internal error: invalid macro"));
1276 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1278 append_insn (&insn
, ep
, r
);
1281 /* Build an instruction created by a macro expansion. Like md_assemble but
1282 accept a printf-style format string and arguments. */
1285 md_assemblef (const char *format
, ...)
1291 va_start (ap
, format
);
1293 r
= vasprintf (&buf
, format
, ap
);
1296 as_fatal (_("internal error: vasprintf failed"));
1304 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1307 normalize_constant_expr (expressionS
*ex
)
1311 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1312 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1313 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1317 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1318 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1321 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1322 bfd_boolean maybe_csr
)
1324 if (ex
->X_op
== O_big
)
1325 as_bad (_("unsupported large constant"));
1326 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1327 as_bad (_("unknown CSR `%s'"),
1328 S_GET_NAME (ex
->X_add_symbol
));
1329 else if (ex
->X_op
!= O_constant
)
1330 as_bad (_("Instruction %s requires absolute expression"),
1332 normalize_constant_expr (ex
);
1336 make_internal_label (void)
1338 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
, frag_now
,
1342 /* Load an entry from the GOT. */
1344 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1345 const char *lo_insn
, const char *lo_pattern
,
1346 bfd_reloc_code_real_type hi_reloc
,
1347 bfd_reloc_code_real_type lo_reloc
)
1350 ep2
.X_op
= O_symbol
;
1351 ep2
.X_add_symbol
= make_internal_label ();
1352 ep2
.X_add_number
= 0;
1354 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1355 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1359 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1360 bfd_reloc_code_real_type hi_reloc
,
1361 bfd_reloc_code_real_type lo_reloc
)
1363 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1367 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1368 bfd_reloc_code_real_type hi_reloc
,
1369 bfd_reloc_code_real_type lo_reloc
)
1371 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1374 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1376 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1377 bfd_reloc_code_real_type reloc
)
1379 /* Ensure the jalr is emitted to the same frag as the auipc. */
1381 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1382 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1383 /* See comment at end of append_insn. */
1384 frag_wane (frag_now
);
1388 /* Load an integer constant into a register. */
1391 load_const (int reg
, expressionS
*ep
)
1393 int shift
= RISCV_IMM_BITS
;
1394 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1395 expressionS upper
= *ep
, lower
= *ep
;
1396 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1397 upper
.X_add_number
-= lower
.X_add_number
;
1399 if (ep
->X_op
!= O_constant
)
1401 as_bad (_("unsupported large constant"));
1405 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1407 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1408 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1411 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1412 load_const (reg
, &upper
);
1414 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1415 if (lower
.X_add_number
!= 0)
1416 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1417 lower
.X_add_number
);
1421 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1424 if (upper
.X_add_number
!= 0)
1426 /* Discard low part and zero-extend upper immediate. */
1427 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1429 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1433 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1434 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1435 lower
.X_add_number
);
1439 /* Zero extend and sign extend byte/half-word/word. */
1442 riscv_ext (int destreg
, int srcreg
, unsigned shift
, bfd_boolean sign
)
1446 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1447 md_assemblef ("srai x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1451 md_assemblef ("slli x%d, x%d, 0x%x", destreg
, srcreg
, shift
);
1452 md_assemblef ("srli x%d, x%d, 0x%x", destreg
, destreg
, shift
);
1456 /* Expand RISC-V assembly macros into one or more instructions. */
1458 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1459 bfd_reloc_code_real_type
*imm_reloc
)
1461 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1462 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1463 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1464 int mask
= ip
->insn_mo
->mask
;
1469 load_const (rd
, imm_expr
);
1474 /* Load the address of a symbol into a register. */
1475 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1476 as_bad (_("offset too large"));
1478 if (imm_expr
->X_op
== O_constant
)
1479 load_const (rd
, imm_expr
);
1480 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1481 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1482 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1483 else /* Local PIC symbol, or any non-PIC symbol */
1484 pcrel_load (rd
, rd
, imm_expr
, "addi",
1485 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1489 pcrel_load (rd
, rd
, imm_expr
, "addi",
1490 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1494 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1495 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1499 pcrel_load (rd
, rd
, imm_expr
, "lb",
1500 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1504 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1505 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1509 pcrel_load (rd
, rd
, imm_expr
, "lh",
1510 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1514 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1515 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1519 pcrel_load (rd
, rd
, imm_expr
, "lw",
1520 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1524 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1525 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1529 pcrel_load (rd
, rd
, imm_expr
, "ld",
1530 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1534 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1535 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1539 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1540 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1544 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1545 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1549 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1550 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1554 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1555 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1559 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1560 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1564 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1565 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1569 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1570 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1574 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1578 riscv_ext (rd
, rs1
, xlen
- 16, FALSE
);
1582 riscv_ext (rd
, rs1
, xlen
- 32, FALSE
);
1586 riscv_ext (rd
, rs1
, xlen
- 8, TRUE
);
1590 riscv_ext (rd
, rs1
, xlen
- 16, TRUE
);
1594 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1599 static const struct percent_op_match percent_op_utype
[] =
1601 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1602 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1603 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1604 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1605 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1606 {"%hi", BFD_RELOC_RISCV_HI20
},
1610 static const struct percent_op_match percent_op_itype
[] =
1612 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1613 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1614 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1618 static const struct percent_op_match percent_op_stype
[] =
1620 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1621 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1622 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1626 static const struct percent_op_match percent_op_rtype
[] =
1628 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1632 static const struct percent_op_match percent_op_null
[] =
1637 /* Return true if *STR points to a relocation operator. When returning true,
1638 move *STR over the operator and store its relocation code in *RELOC.
1639 Leave both *STR and *RELOC alone when returning false. */
1642 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1643 const struct percent_op_match
*percent_op
)
1645 for ( ; percent_op
->str
; percent_op
++)
1646 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1648 int len
= strlen (percent_op
->str
);
1650 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1653 *str
+= strlen (percent_op
->str
);
1654 *reloc
= percent_op
->reloc
;
1656 /* Check whether the output BFD supports this relocation.
1657 If not, issue an error and fall back on something safe. */
1658 if (*reloc
!= BFD_RELOC_UNUSED
1659 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1661 as_bad ("relocation %s isn't supported by the current ABI",
1663 *reloc
= BFD_RELOC_UNUSED
;
1671 my_getExpression (expressionS
*ep
, char *str
)
1675 save_in
= input_line_pointer
;
1676 input_line_pointer
= str
;
1678 expr_end
= input_line_pointer
;
1679 input_line_pointer
= save_in
;
1682 /* Parse string STR as a 16-bit relocatable operand. Store the
1683 expression in *EP and the relocation, if any, in RELOC.
1684 Return the number of relocation operators used (0 or 1).
1686 On exit, EXPR_END points to the first character after the expression. */
1689 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1690 char *str
, const struct percent_op_match
*percent_op
)
1693 unsigned crux_depth
, str_depth
, regno
;
1696 /* First, check for integer registers. No callers can accept a reg, but
1697 we need to avoid accidentally creating a useless undefined symbol below,
1698 if this is an instruction pattern that can't match. A glibc build fails
1699 if this is removed. */
1700 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1702 ep
->X_op
= O_register
;
1703 ep
->X_add_number
= regno
;
1708 /* Search for the start of the main expression.
1709 End the loop with CRUX pointing to the start
1710 of the main expression and with CRUX_DEPTH containing the number
1711 of open brackets at that point. */
1718 crux_depth
= str_depth
;
1720 /* Skip over whitespace and brackets, keeping count of the number
1722 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1728 && parse_relocation (&str
, reloc
, percent_op
));
1730 my_getExpression (ep
, crux
);
1733 /* Match every open bracket. */
1734 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1739 as_bad ("unclosed '('");
1746 /* Parse opcode name, could be an mnemonics or number. */
1748 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1749 char *str
, const struct percent_op_match
*percent_op
)
1751 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1755 ep
->X_op
= O_constant
;
1756 ep
->X_add_number
= o
->val
;
1760 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1763 /* Detect and handle implicitly zero load-store offsets. For example,
1764 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1765 an implicit offset was detected. */
1768 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1770 /* Check whether there is only a single bracketed expression left.
1771 If so, it must be the base register and the constant must be zero. */
1772 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1774 ep
->X_op
= O_constant
;
1775 ep
->X_add_number
= 0;
1782 /* All RISC-V CSR instructions belong to one of these classes. */
1792 /* Return which CSR instruction is checking. */
1794 static enum csr_insn_type
1795 riscv_csr_insn_type (insn_t insn
)
1797 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1798 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1800 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1801 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1803 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1804 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1807 return INSN_NOT_CSR
;
1810 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1811 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1812 CSR address is 0x3. */
1815 riscv_csr_read_only_check (insn_t insn
)
1817 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1818 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1819 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1820 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1823 && (((csr_insn
== INSN_CSRRS
1824 || csr_insn
== INSN_CSRRC
)
1826 || csr_insn
== INSN_CSRRW
))
1832 /* Return True if it is a privileged instruction. Otherwise, return FALSE.
1834 uret is actually a N-ext instruction. So it is better to regard it as
1835 an user instruction rather than the priv instruction.
1837 hret is used to return from traps in H-mode. H-mode is removed since
1838 the v1.10 priv spec, but probably be added in the new hypervisor spec.
1839 Therefore, hret should be controlled by the hypervisor spec rather than
1840 priv spec in the future.
1842 dret is defined in the debug spec, so it should be checked in the future,
1846 riscv_is_priv_insn (insn_t insn
)
1848 return (((insn
^ MATCH_SRET
) & MASK_SRET
) == 0
1849 || ((insn
^ MATCH_MRET
) & MASK_MRET
) == 0
1850 || ((insn
^ MATCH_SFENCE_VMA
) & MASK_SFENCE_VMA
) == 0
1851 || ((insn
^ MATCH_WFI
) & MASK_WFI
) == 0
1852 /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to
1853 check it here to keep the compatible. Maybe we should issue warning
1854 if sfence.vm is used, but the priv spec newer than v1.10 is chosen.
1855 We already have a similar check for CSR, but not yet for instructions.
1856 It would be good if we could check the spec versions both for CSR and
1857 instructions, but not here. */
1858 || ((insn
^ MATCH_SFENCE_VM
) & MASK_SFENCE_VM
) == 0);
1861 /* This routine assembles an instruction into its binary format. As a
1862 side effect, it sets the global variable imm_reloc to the type of
1863 relocation to do if one of the operands is an address expression. */
1866 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1867 bfd_reloc_code_real_type
*imm_reloc
, htab_t hash
)
1872 struct riscv_opcode
*insn
;
1877 const struct percent_op_match
*p
;
1878 const char *error
= "unrecognized opcode";
1879 /* Indicate we are assembling instruction with CSR. */
1880 bfd_boolean insn_with_csr
= FALSE
;
1882 /* Parse the name of the instruction. Terminate the string if whitespace
1883 is found so that str_hash_find only sees the name part of the string. */
1884 for (s
= str
; *s
!= '\0'; ++s
)
1892 insn
= (struct riscv_opcode
*) str_hash_find (hash
, str
);
1895 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1897 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1900 if (!riscv_multi_subset_supports (insn
->insn_class
))
1903 create_insn (ip
, insn
);
1906 imm_expr
->X_op
= O_absent
;
1907 *imm_reloc
= BFD_RELOC_UNUSED
;
1908 p
= percent_op_itype
;
1910 for (args
= insn
->args
;; ++args
)
1912 s
+= strspn (s
, " \t");
1915 case '\0': /* End of args. */
1916 if (insn
->pinfo
!= INSN_MACRO
)
1918 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1921 /* For .insn, insn->match and insn->mask are 0. */
1922 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1928 if (riscv_is_priv_insn (ip
->insn_opcode
))
1929 explicit_priv_attr
= TRUE
;
1931 /* Check if we write a read-only CSR by the CSR
1934 && riscv_opts
.csr_check
1935 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1937 /* Restore the character in advance, since we want to
1938 report the detailed warning message here. */
1940 *(argsStart
- 1) = save_c
;
1941 as_warn (_("Read-only CSR is written `%s'"), str
);
1942 insn_with_csr
= FALSE
;
1947 /* Successful assembly. */
1949 insn_with_csr
= FALSE
;
1955 case 's': /* RS1 x8-x15 */
1956 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1957 || !(regno
>= 8 && regno
<= 15))
1959 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1961 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1962 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1963 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1966 case 't': /* RS2 x8-x15 */
1967 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1968 || !(regno
>= 8 && regno
<= 15))
1970 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1972 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1973 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1974 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1977 case 'U': /* RS1, constrained to equal RD. */
1978 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1979 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1983 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1985 INSERT_OPERAND (CRS2
, *ip
, regno
);
1987 case 'c': /* RS1, constrained to equal sp. */
1988 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1992 case 'z': /* RS2, contrained to equal x0. */
1993 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1998 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1999 || imm_expr
->X_op
!= O_constant
2000 || imm_expr
->X_add_number
<= 0
2001 || imm_expr
->X_add_number
>= 64)
2003 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2006 imm_expr
->X_op
= O_absent
;
2009 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2010 || imm_expr
->X_op
!= O_constant
2011 || imm_expr
->X_add_number
<= 0
2012 || imm_expr
->X_add_number
>= 32
2013 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2015 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2018 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2019 || imm_expr
->X_op
!= O_constant
2020 || imm_expr
->X_add_number
< 0
2021 || imm_expr
->X_add_number
>= 256
2022 || !VALID_RVC_UIMM8 ((valueT
) imm_expr
->X_add_number
))
2024 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
2027 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2028 || imm_expr
->X_op
!= O_constant
2029 || imm_expr
->X_add_number
== 0
2030 || !VALID_RVC_SIMM3 ((valueT
) imm_expr
->X_add_number
))
2032 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
2035 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2036 || imm_expr
->X_op
!= O_constant
2037 || imm_expr
->X_add_number
== 0
2038 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2040 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2043 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2045 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2046 || imm_expr
->X_op
!= O_constant
2047 || !VALID_RVC_LW_IMM ((valueT
) imm_expr
->X_add_number
))
2049 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
2052 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2054 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2055 || imm_expr
->X_op
!= O_constant
2056 || !VALID_RVC_LD_IMM ((valueT
) imm_expr
->X_add_number
))
2058 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
2061 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2063 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2064 || imm_expr
->X_op
!= O_constant
2065 || !VALID_RVC_LWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2068 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
2071 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2073 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2074 || imm_expr
->X_op
!= O_constant
2075 || !VALID_RVC_LDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2078 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2081 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2082 || imm_expr
->X_op
!= O_constant
2083 /* C.addiw, c.li, and c.andi allow zero immediate.
2084 C.addi allows zero immediate as hint. Otherwise this
2086 || !VALID_RVC_IMM ((valueT
) imm_expr
->X_add_number
))
2088 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2091 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2092 || imm_expr
->X_op
!= O_constant
2093 || imm_expr
->X_add_number
== 0
2094 || !VALID_RVC_ADDI4SPN_IMM ((valueT
) imm_expr
->X_add_number
))
2097 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2100 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2101 || imm_expr
->X_op
!= O_constant
2102 || imm_expr
->X_add_number
== 0
2103 || !VALID_RVC_ADDI16SP_IMM ((valueT
) imm_expr
->X_add_number
))
2106 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2109 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2111 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2112 || imm_expr
->X_op
!= O_constant
2113 || !VALID_RVC_SWSP_IMM ((valueT
) imm_expr
->X_add_number
))
2116 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2119 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2121 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2122 || imm_expr
->X_op
!= O_constant
2123 || !VALID_RVC_SDSP_IMM ((valueT
) imm_expr
->X_add_number
))
2126 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2129 p
= percent_op_utype
;
2130 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2133 if (imm_expr
->X_op
!= O_constant
2134 || imm_expr
->X_add_number
<= 0
2135 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2136 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2137 && (imm_expr
->X_add_number
<
2138 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2140 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2143 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2144 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2145 || ((int32_t)imm_expr
->X_add_number
2146 != imm_expr
->X_add_number
))
2148 imm_expr
->X_add_number
=
2149 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2155 case 'S': /* Floating-point RS1 x8-x15. */
2156 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2157 || !(regno
>= 8 && regno
<= 15))
2159 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2161 case 'D': /* Floating-point RS2 x8-x15. */
2162 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2163 || !(regno
>= 8 && regno
<= 15))
2165 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2167 case 'T': /* Floating-point RS2. */
2168 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2170 INSERT_OPERAND (CRS2
, *ip
, regno
);
2176 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2177 || imm_expr
->X_op
!= O_constant
2178 || imm_expr
->X_add_number
< 0
2179 || imm_expr
->X_add_number
>= 64)
2181 as_bad (_("bad value for funct6 field, "
2182 "value must be 0...64"));
2186 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2187 imm_expr
->X_op
= O_absent
;
2191 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2192 || imm_expr
->X_op
!= O_constant
2193 || imm_expr
->X_add_number
< 0
2194 || imm_expr
->X_add_number
>= 16)
2196 as_bad (_("bad value for funct4 field, "
2197 "value must be 0...15"));
2201 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2202 imm_expr
->X_op
= O_absent
;
2206 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2207 || imm_expr
->X_op
!= O_constant
2208 || imm_expr
->X_add_number
< 0
2209 || imm_expr
->X_add_number
>= 8)
2211 as_bad (_("bad value for funct3 field, "
2212 "value must be 0...7"));
2215 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2216 imm_expr
->X_op
= O_absent
;
2220 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2221 || imm_expr
->X_op
!= O_constant
2222 || imm_expr
->X_add_number
< 0
2223 || imm_expr
->X_add_number
>= 4)
2225 as_bad (_("bad value for funct2 field, "
2226 "value must be 0...3"));
2229 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2230 imm_expr
->X_op
= O_absent
;
2234 as_bad (_("bad compressed FUNCT field"
2235 " specifier 'CF%c'\n"),
2241 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2260 case '<': /* Shift amount, 0 - 31. */
2261 my_getExpression (imm_expr
, s
);
2262 check_absolute_expr (ip
, imm_expr
, FALSE
);
2263 if ((unsigned long) imm_expr
->X_add_number
> 31)
2264 as_bad (_("Improper shift amount (%lu)"),
2265 (unsigned long) imm_expr
->X_add_number
);
2266 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2267 imm_expr
->X_op
= O_absent
;
2271 case '>': /* Shift amount, 0 - (XLEN-1). */
2272 my_getExpression (imm_expr
, s
);
2273 check_absolute_expr (ip
, imm_expr
, FALSE
);
2274 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2275 as_bad (_("Improper shift amount (%lu)"),
2276 (unsigned long) imm_expr
->X_add_number
);
2277 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2278 imm_expr
->X_op
= O_absent
;
2282 case 'Z': /* CSRRxI immediate. */
2283 my_getExpression (imm_expr
, s
);
2284 check_absolute_expr (ip
, imm_expr
, FALSE
);
2285 if ((unsigned long) imm_expr
->X_add_number
> 31)
2286 as_bad (_("Improper CSRxI immediate (%lu)"),
2287 (unsigned long) imm_expr
->X_add_number
);
2288 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2289 imm_expr
->X_op
= O_absent
;
2293 case 'E': /* Control register. */
2294 insn_with_csr
= TRUE
;
2295 explicit_priv_attr
= TRUE
;
2296 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2297 INSERT_OPERAND (CSR
, *ip
, regno
);
2300 my_getExpression (imm_expr
, s
);
2301 check_absolute_expr (ip
, imm_expr
, TRUE
);
2302 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2303 as_bad (_("Improper CSR address (%lu)"),
2304 (unsigned long) imm_expr
->X_add_number
);
2305 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2306 imm_expr
->X_op
= O_absent
;
2311 case 'm': /* Rounding mode. */
2312 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2314 INSERT_OPERAND (RM
, *ip
, regno
);
2320 case 'Q': /* Fence predecessor/successor. */
2321 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2325 INSERT_OPERAND (PRED
, *ip
, regno
);
2327 INSERT_OPERAND (SUCC
, *ip
, regno
);
2332 case 'd': /* Destination register. */
2333 case 's': /* Source register. */
2334 case 't': /* Target register. */
2335 case 'r': /* rs3. */
2336 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2342 /* Now that we have assembled one operand, we use the args
2343 string to figure out where it goes in the instruction. */
2347 INSERT_OPERAND (RS1
, *ip
, regno
);
2350 INSERT_OPERAND (RD
, *ip
, regno
);
2353 INSERT_OPERAND (RS2
, *ip
, regno
);
2356 INSERT_OPERAND (RS3
, *ip
, regno
);
2363 case 'D': /* Floating point rd. */
2364 case 'S': /* Floating point rs1. */
2365 case 'T': /* Floating point rs2. */
2366 case 'U': /* Floating point rs1 and rs2. */
2367 case 'R': /* Floating point rs3. */
2368 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2376 INSERT_OPERAND (RD
, *ip
, regno
);
2379 INSERT_OPERAND (RS1
, *ip
, regno
);
2382 INSERT_OPERAND (RS1
, *ip
, regno
);
2385 INSERT_OPERAND (RS2
, *ip
, regno
);
2388 INSERT_OPERAND (RS3
, *ip
, regno
);
2397 my_getExpression (imm_expr
, s
);
2398 if (imm_expr
->X_op
!= O_big
2399 && imm_expr
->X_op
!= O_constant
)
2401 normalize_constant_expr (imm_expr
);
2406 my_getExpression (imm_expr
, s
);
2407 normalize_constant_expr (imm_expr
);
2408 /* The 'A' format specifier must be a symbol. */
2409 if (imm_expr
->X_op
!= O_symbol
)
2411 *imm_reloc
= BFD_RELOC_32
;
2416 my_getExpression (imm_expr
, s
);
2417 normalize_constant_expr (imm_expr
);
2418 /* The 'B' format specifier must be a symbol or a constant. */
2419 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2421 if (imm_expr
->X_op
== O_symbol
)
2422 *imm_reloc
= BFD_RELOC_32
;
2426 case 'j': /* Sign-extended immediate. */
2427 p
= percent_op_itype
;
2428 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2430 case 'q': /* Store displacement. */
2431 p
= percent_op_stype
;
2432 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2434 case 'o': /* Load displacement. */
2435 p
= percent_op_itype
;
2436 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2438 case '1': /* 4-operand add, must be %tprel_add. */
2439 p
= percent_op_rtype
;
2441 case '0': /* AMO "displacement," which must be zero. */
2442 p
= percent_op_null
;
2444 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2447 /* If this value won't fit into a 16 bit offset, then go
2448 find a macro that will generate the 32 bit offset
2450 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2452 normalize_constant_expr (imm_expr
);
2453 if (imm_expr
->X_op
!= O_constant
2454 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2456 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2457 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2464 case 'p': /* PC-relative offset. */
2466 *imm_reloc
= BFD_RELOC_12_PCREL
;
2467 my_getExpression (imm_expr
, s
);
2471 case 'u': /* Upper 20 bits. */
2472 p
= percent_op_utype
;
2473 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2475 if (imm_expr
->X_op
!= O_constant
)
2478 if (imm_expr
->X_add_number
< 0
2479 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2480 as_bad (_("lui expression not in range 0..1048575"));
2482 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2483 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2488 case 'a': /* 20-bit PC-relative offset. */
2490 my_getExpression (imm_expr
, s
);
2492 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2496 my_getExpression (imm_expr
, s
);
2498 if (strcmp (s
, "@plt") == 0)
2500 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2504 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2510 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2511 || imm_expr
->X_op
!= O_constant
2512 || imm_expr
->X_add_number
< 0
2513 || imm_expr
->X_add_number
>= 128
2514 || (imm_expr
->X_add_number
& 0x3) != 3)
2516 as_bad (_("bad value for opcode field, "
2517 "value must be 0...127 and "
2518 "lower 2 bits must be 0x3"));
2522 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2523 imm_expr
->X_op
= O_absent
;
2527 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2528 || imm_expr
->X_op
!= O_constant
2529 || imm_expr
->X_add_number
< 0
2530 || imm_expr
->X_add_number
>= 3)
2532 as_bad (_("bad value for opcode field, "
2533 "value must be 0...2"));
2537 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2538 imm_expr
->X_op
= O_absent
;
2542 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2550 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2551 || imm_expr
->X_op
!= O_constant
2552 || imm_expr
->X_add_number
< 0
2553 || imm_expr
->X_add_number
>= 128)
2555 as_bad (_("bad value for funct7 field, "
2556 "value must be 0...127"));
2560 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2561 imm_expr
->X_op
= O_absent
;
2565 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2566 || imm_expr
->X_op
!= O_constant
2567 || imm_expr
->X_add_number
< 0
2568 || imm_expr
->X_add_number
>= 8)
2570 as_bad (_("bad value for funct3 field, "
2571 "value must be 0...7"));
2575 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2576 imm_expr
->X_op
= O_absent
;
2580 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2581 || imm_expr
->X_op
!= O_constant
2582 || imm_expr
->X_add_number
< 0
2583 || imm_expr
->X_add_number
>= 4)
2585 as_bad (_("bad value for funct2 field, "
2586 "value must be 0...3"));
2590 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2591 imm_expr
->X_op
= O_absent
;
2596 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2601 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2602 || imm_expr
->X_op
!= O_constant
2603 || imm_expr
->X_add_number
!= 0)
2606 imm_expr
->X_op
= O_absent
;
2610 as_fatal (_("internal error: bad argument type %c"), *args
);
2615 error
= _("illegal operands");
2616 insn_with_csr
= FALSE
;
2620 /* Restore the character we might have clobbered above. */
2622 *(argsStart
- 1) = save_c
;
2628 md_assemble (char *str
)
2630 struct riscv_cl_insn insn
;
2631 expressionS imm_expr
;
2632 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2634 /* The arch and priv attributes should be set before assembling. */
2635 if (!start_assemble
)
2637 start_assemble
= TRUE
;
2638 riscv_set_abi_by_arch ();
2640 /* Set the default_priv_spec according to the priv attributes. */
2641 if (!riscv_set_default_priv_spec (NULL
))
2645 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2649 as_bad ("%s `%s'", error
, str
);
2653 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2654 macro (&insn
, &imm_expr
, &imm_reloc
);
2656 append_insn (&insn
, &imm_expr
, imm_reloc
);
2660 md_atof (int type
, char *litP
, int *sizeP
)
2662 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2666 md_number_to_chars (char *buf
, valueT val
, int n
)
2668 if (target_big_endian
)
2669 number_to_chars_bigendian (buf
, val
, n
);
2671 number_to_chars_littleendian (buf
, val
, n
);
2674 const char *md_shortopts
= "O::g::G:";
2678 OPTION_MARCH
= OPTION_MD_BASE
,
2685 OPTION_NO_ARCH_ATTR
,
2687 OPTION_NO_CSR_CHECK
,
2691 OPTION_LITTLE_ENDIAN
,
2695 struct option md_longopts
[] =
2697 {"march", required_argument
, NULL
, OPTION_MARCH
},
2698 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2699 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2700 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2701 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2702 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2703 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2704 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2705 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2706 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2707 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2708 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2709 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2710 {"mbig-endian", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
2711 {"mlittle-endian", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
2713 {NULL
, no_argument
, NULL
, 0}
2715 size_t md_longopts_size
= sizeof (md_longopts
);
2718 md_parse_option (int c
, const char *arg
)
2723 /* riscv_after_parse_args will call riscv_set_arch to parse
2724 the architecture. */
2725 default_arch_with_ext
= arg
;
2729 riscv_opts
.pic
= FALSE
;
2733 riscv_opts
.pic
= TRUE
;
2737 if (strcmp (arg
, "ilp32") == 0)
2738 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2739 else if (strcmp (arg
, "ilp32e") == 0)
2740 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2741 else if (strcmp (arg
, "ilp32f") == 0)
2742 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2743 else if (strcmp (arg
, "ilp32d") == 0)
2744 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2745 else if (strcmp (arg
, "ilp32q") == 0)
2746 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2747 else if (strcmp (arg
, "lp64") == 0)
2748 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2749 else if (strcmp (arg
, "lp64f") == 0)
2750 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2751 else if (strcmp (arg
, "lp64d") == 0)
2752 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2753 else if (strcmp (arg
, "lp64q") == 0)
2754 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2757 explicit_mabi
= TRUE
;
2761 riscv_opts
.relax
= TRUE
;
2764 case OPTION_NO_RELAX
:
2765 riscv_opts
.relax
= FALSE
;
2768 case OPTION_ARCH_ATTR
:
2769 riscv_opts
.arch_attr
= TRUE
;
2772 case OPTION_NO_ARCH_ATTR
:
2773 riscv_opts
.arch_attr
= FALSE
;
2776 case OPTION_CSR_CHECK
:
2777 riscv_opts
.csr_check
= TRUE
;
2780 case OPTION_NO_CSR_CHECK
:
2781 riscv_opts
.csr_check
= FALSE
;
2784 case OPTION_MISA_SPEC
:
2785 return riscv_set_default_isa_spec (arg
);
2787 case OPTION_MPRIV_SPEC
:
2788 return riscv_set_default_priv_spec (arg
);
2790 case OPTION_BIG_ENDIAN
:
2791 target_big_endian
= 1;
2794 case OPTION_LITTLE_ENDIAN
:
2795 target_big_endian
= 0;
2806 riscv_after_parse_args (void)
2808 /* The --with-arch is optional for now, so we have to set the xlen
2809 according to the default_arch, which is set by the --targte, first.
2810 Then, we use the xlen to set the default_arch_with_ext if the
2811 -march and --with-arch are not set. */
2814 if (strcmp (default_arch
, "riscv32") == 0)
2816 else if (strcmp (default_arch
, "riscv64") == 0)
2819 as_bad ("unknown default architecture `%s'", default_arch
);
2821 if (default_arch_with_ext
== NULL
)
2822 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2824 /* Initialize the hash table for extensions with default version. */
2825 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2827 /* If the -misa-spec isn't set, then we set the default ISA spec according
2828 to DEFAULT_RISCV_ISA_SPEC. */
2829 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2830 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2832 /* Set the architecture according to -march or or --with-arch. */
2833 riscv_set_arch (default_arch_with_ext
);
2835 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2836 riscv_set_rvc (FALSE
);
2837 if (riscv_subset_supports ("c"))
2838 riscv_set_rvc (TRUE
);
2840 /* Enable RVE if specified by the -march option. */
2841 riscv_set_rve (FALSE
);
2842 if (riscv_subset_supports ("e"))
2843 riscv_set_rve (TRUE
);
2845 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2846 according to DEFAULT_PRIV_SPEC. */
2847 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2848 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2850 /* If the CIE to be produced has not been overridden on the command line,
2851 then produce version 3 by default. This allows us to use the full
2852 range of registers in a .cfi_return_column directive. */
2853 if (flag_dwarf_cie_version
== -1)
2854 flag_dwarf_cie_version
= 3;
2858 md_pcrel_from (fixS
*fixP
)
2860 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2863 /* Apply a fixup to the object file. */
2866 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2868 unsigned int subtype
;
2869 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2870 bfd_boolean relaxable
= FALSE
;
2874 /* Remember value for tc_gen_reloc. */
2875 fixP
->fx_addnumber
= *valP
;
2877 switch (fixP
->fx_r_type
)
2879 case BFD_RELOC_RISCV_HI20
:
2880 case BFD_RELOC_RISCV_LO12_I
:
2881 case BFD_RELOC_RISCV_LO12_S
:
2882 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2883 | bfd_getl32 (buf
), buf
);
2884 if (fixP
->fx_addsy
== NULL
)
2885 fixP
->fx_done
= TRUE
;
2889 case BFD_RELOC_RISCV_GOT_HI20
:
2890 case BFD_RELOC_RISCV_ADD8
:
2891 case BFD_RELOC_RISCV_ADD16
:
2892 case BFD_RELOC_RISCV_ADD32
:
2893 case BFD_RELOC_RISCV_ADD64
:
2894 case BFD_RELOC_RISCV_SUB6
:
2895 case BFD_RELOC_RISCV_SUB8
:
2896 case BFD_RELOC_RISCV_SUB16
:
2897 case BFD_RELOC_RISCV_SUB32
:
2898 case BFD_RELOC_RISCV_SUB64
:
2899 case BFD_RELOC_RISCV_RELAX
:
2902 case BFD_RELOC_RISCV_TPREL_HI20
:
2903 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2904 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2905 case BFD_RELOC_RISCV_TPREL_ADD
:
2909 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2910 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2911 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2912 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2913 if (fixP
->fx_addsy
!= NULL
)
2914 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2917 _("TLS relocation against a constant"));
2921 /* Use pc-relative relocation for FDE initial location.
2922 The symbol address in .eh_frame may be adjusted in
2923 _bfd_elf_discard_section_eh_frame, and the content of
2924 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2925 Therefore, we cannot insert a relocation whose addend symbol is
2926 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2927 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2928 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2929 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2930 && S_GET_VALUE (fixP
->fx_subsy
)
2931 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2933 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2934 fixP
->fx_subsy
= NULL
;
2941 case BFD_RELOC_RISCV_CFA
:
2942 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2944 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2945 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2946 fixP
->fx_next
->fx_subsy
= NULL
;
2947 fixP
->fx_next
->fx_offset
= 0;
2948 fixP
->fx_subsy
= NULL
;
2950 switch (fixP
->fx_r_type
)
2953 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2954 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2958 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2959 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2963 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2964 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2968 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2969 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2972 case BFD_RELOC_RISCV_CFA
:
2973 /* Load the byte to get the subtype. */
2974 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2975 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2978 case DW_CFA_advance_loc1
:
2979 fixP
->fx_where
= loc
+ 1;
2980 fixP
->fx_next
->fx_where
= loc
+ 1;
2981 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2982 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2985 case DW_CFA_advance_loc2
:
2987 fixP
->fx_next
->fx_size
= 2;
2988 fixP
->fx_where
= loc
+ 1;
2989 fixP
->fx_next
->fx_where
= loc
+ 1;
2990 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2991 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2994 case DW_CFA_advance_loc4
:
2996 fixP
->fx_next
->fx_size
= 4;
2997 fixP
->fx_where
= loc
;
2998 fixP
->fx_next
->fx_where
= loc
;
2999 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
3000 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
3004 if (subtype
< 0x80 && (subtype
& 0x40))
3006 /* DW_CFA_advance_loc */
3007 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
3008 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
3009 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
3010 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
3013 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
3019 /* This case is unreachable. */
3026 /* If we are deleting this reloc entry, we must fill in the
3027 value now. This can happen if we have a .word which is not
3028 resolved when it appears but is later defined. */
3029 if (fixP
->fx_addsy
== NULL
)
3031 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
3032 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
3037 case BFD_RELOC_RISCV_JMP
:
3040 /* Fill in a tentative value to improve objdump readability. */
3041 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3042 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3043 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3047 case BFD_RELOC_12_PCREL
:
3050 /* Fill in a tentative value to improve objdump readability. */
3051 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3052 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3053 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3057 case BFD_RELOC_RISCV_RVC_BRANCH
:
3060 /* Fill in a tentative value to improve objdump readability. */
3061 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3062 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3063 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3067 case BFD_RELOC_RISCV_RVC_JUMP
:
3070 /* Fill in a tentative value to improve objdump readability. */
3071 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3072 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3073 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3077 case BFD_RELOC_RISCV_CALL
:
3078 case BFD_RELOC_RISCV_CALL_PLT
:
3082 case BFD_RELOC_RISCV_PCREL_HI20
:
3083 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3084 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3085 relaxable
= riscv_opts
.relax
;
3088 case BFD_RELOC_RISCV_ALIGN
:
3092 /* We ignore generic BFD relocations we don't know about. */
3093 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3094 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3097 if (fixP
->fx_subsy
!= NULL
)
3098 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3099 _("unsupported symbol subtraction"));
3101 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3102 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3104 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3105 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3106 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3107 fixP
->fx_next
->fx_size
= 0;
3111 /* Because the value of .cfi_remember_state may changed after relaxation,
3112 we insert a fix to relocate it again in link-time. */
3115 riscv_pre_output_hook (void)
3117 const frchainS
*frch
;
3120 /* Save the current segment info. */
3122 subsegT subseg
= now_subseg
;
3124 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3125 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3129 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3131 if (frag
->fr_type
== rs_cfa
)
3134 expressionS
*symval
;
3136 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3137 exp
.X_op
= O_subtract
;
3138 exp
.X_add_symbol
= symval
->X_add_symbol
;
3139 exp
.X_add_number
= 0;
3140 exp
.X_op_symbol
= symval
->X_op_symbol
;
3142 /* We must set the segment before creating a frag after all
3143 frag chains have been chained together. */
3144 subseg_set (s
, frch
->frch_subseg
);
3146 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3147 BFD_RELOC_RISCV_CFA
);
3152 /* Restore the original segment info. */
3153 subseg_set (seg
, subseg
);
3157 /* This structure is used to hold a stack of .option values. */
3159 struct riscv_option_stack
3161 struct riscv_option_stack
*next
;
3162 struct riscv_set_options options
;
3165 static struct riscv_option_stack
*riscv_opts_stack
;
3167 /* Handle the .option pseudo-op. */
3170 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3172 char *name
= input_line_pointer
, ch
;
3174 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3175 ++input_line_pointer
;
3176 ch
= *input_line_pointer
;
3177 *input_line_pointer
= '\0';
3179 if (strcmp (name
, "rvc") == 0)
3180 riscv_set_rvc (TRUE
);
3181 else if (strcmp (name
, "norvc") == 0)
3182 riscv_set_rvc (FALSE
);
3183 else if (strcmp (name
, "pic") == 0)
3184 riscv_opts
.pic
= TRUE
;
3185 else if (strcmp (name
, "nopic") == 0)
3186 riscv_opts
.pic
= FALSE
;
3187 else if (strcmp (name
, "relax") == 0)
3188 riscv_opts
.relax
= TRUE
;
3189 else if (strcmp (name
, "norelax") == 0)
3190 riscv_opts
.relax
= FALSE
;
3191 else if (strcmp (name
, "csr-check") == 0)
3192 riscv_opts
.csr_check
= TRUE
;
3193 else if (strcmp (name
, "no-csr-check") == 0)
3194 riscv_opts
.csr_check
= FALSE
;
3195 else if (strcmp (name
, "push") == 0)
3197 struct riscv_option_stack
*s
;
3199 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3200 s
->next
= riscv_opts_stack
;
3201 s
->options
= riscv_opts
;
3202 riscv_opts_stack
= s
;
3204 else if (strcmp (name
, "pop") == 0)
3206 struct riscv_option_stack
*s
;
3208 s
= riscv_opts_stack
;
3210 as_bad (_(".option pop with no .option push"));
3213 riscv_opts
= s
->options
;
3214 riscv_opts_stack
= s
->next
;
3220 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3222 *input_line_pointer
= ch
;
3223 demand_empty_rest_of_line ();
3226 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3227 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3228 use in DWARF debug information. */
3231 s_dtprel (int bytes
)
3238 if (ex
.X_op
!= O_symbol
)
3240 as_bad (_("Unsupported use of %s"), (bytes
== 8
3243 ignore_rest_of_line ();
3246 p
= frag_more (bytes
);
3247 md_number_to_chars (p
, 0, bytes
);
3248 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3250 ? BFD_RELOC_RISCV_TLS_DTPREL64
3251 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3253 demand_empty_rest_of_line ();
3256 /* Handle the .bss pseudo-op. */
3259 s_bss (int ignore ATTRIBUTE_UNUSED
)
3261 subseg_set (bss_section
, 0);
3262 demand_empty_rest_of_line ();
3266 riscv_make_nops (char *buf
, bfd_vma bytes
)
3270 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3271 means we are not within a valid instruction sequence. It is thus safe
3272 to use a zero byte, even though that is not a valid instruction. */
3276 /* Use at most one 2-byte NOP. */
3277 if ((bytes
- i
) % 4 == 2)
3279 number_to_chars_littleendian (buf
+ i
, RVC_NOP
, 2);
3283 /* Fill the remainder with 4-byte NOPs. */
3284 for ( ; i
< bytes
; i
+= 4)
3285 number_to_chars_littleendian (buf
+ i
, RISCV_NOP
, 4);
3288 /* Called from md_do_align. Used to create an alignment frag in a
3289 code section by emitting a worst-case NOP sequence that the linker
3290 will later relax to the correct number of NOPs. We can't compute
3291 the correct alignment now because of other linker relaxations. */
3294 riscv_frag_align_code (int n
)
3296 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3297 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3298 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3302 /* If we are moving to a smaller alignment than the instruction size, then no
3303 alignment is required. */
3304 if (bytes
<= insn_alignment
)
3307 /* When not relaxing, riscv_handle_align handles code alignment. */
3308 if (!riscv_opts
.relax
)
3311 nops
= frag_more (worst_case_bytes
);
3313 ex
.X_op
= O_constant
;
3314 ex
.X_add_number
= worst_case_bytes
;
3316 riscv_make_nops (nops
, worst_case_bytes
);
3318 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3319 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3324 /* Implement HANDLE_ALIGN. */
3327 riscv_handle_align (fragS
*fragP
)
3329 switch (fragP
->fr_type
)
3332 /* When relaxing, riscv_frag_align_code handles code alignment. */
3333 if (!riscv_opts
.relax
)
3335 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3336 - fragP
->fr_address
- fragP
->fr_fix
);
3337 /* We have 4 byte uncompressed nops. */
3338 bfd_signed_vma size
= 4;
3339 bfd_signed_vma excess
= bytes
% size
;
3340 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3345 /* Insert zeros or compressed nops to get 4 byte alignment. */
3348 riscv_make_nops (p
, excess
);
3349 fragP
->fr_fix
+= excess
;
3353 /* Insert variable number of 4 byte uncompressed nops. */
3354 riscv_make_nops (p
, size
);
3355 fragP
->fr_var
= size
;
3365 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3367 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3370 /* Translate internal representation of relocation info to BFD target
3374 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3376 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3378 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3379 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3380 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3381 reloc
->addend
= fixp
->fx_addnumber
;
3383 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3384 if (reloc
->howto
== NULL
)
3386 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3387 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3389 /* We don't have R_RISCV_8/16, but for this special case,
3390 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3394 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3395 _("cannot represent %s relocation in object file"),
3396 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3404 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3406 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3408 offsetT old_var
= fragp
->fr_var
;
3409 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3410 return fragp
->fr_var
- old_var
;
3416 /* Expand far branches to multi-instruction sequences. */
3419 md_convert_frag_branch (fragS
*fragp
)
3427 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3429 exp
.X_op
= O_symbol
;
3430 exp
.X_add_symbol
= fragp
->fr_symbol
;
3431 exp
.X_add_number
= fragp
->fr_offset
;
3433 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3435 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3437 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3441 /* Expand the RVC branch into a RISC-V one. */
3442 insn
= bfd_getl16 (buf
);
3443 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3444 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3446 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3447 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3448 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3449 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3450 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3451 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3454 bfd_putl32 (insn
, buf
);
3458 /* Invert the branch condition. Branch over the jump. */
3459 insn
= bfd_getl16 (buf
);
3460 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3461 insn
|= ENCODE_RVC_B_IMM (6);
3462 bfd_putl16 (insn
, buf
);
3467 /* Just keep the RVC branch. */
3468 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3469 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3470 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3471 2, &exp
, FALSE
, reloc
);
3480 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3483 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3485 /* Invert the branch condition. Branch over the jump. */
3486 insn
= bfd_getl32 (buf
);
3487 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3488 insn
|= ENCODE_SBTYPE_IMM (8);
3489 bfd_putl32 (insn
, buf
);
3493 /* Jump to the target. */
3494 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3495 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3496 bfd_putl32 (MATCH_JAL
, buf
);
3501 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3502 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3503 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3504 4, &exp
, FALSE
, reloc
);
3513 fixp
->fx_file
= fragp
->fr_file
;
3514 fixp
->fx_line
= fragp
->fr_line
;
3516 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3517 + fragp
->fr_fix
+ fragp
->fr_var
);
3519 fragp
->fr_fix
+= fragp
->fr_var
;
3522 /* Relax a machine dependent frag. This returns the amount by which
3523 the current size of the frag should change. */
3526 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3529 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3530 md_convert_frag_branch (fragp
);
3534 md_show_usage (FILE *stream
)
3536 fprintf (stream
, _("\
3538 -fpic generate position-independent code\n\
3539 -fno-pic don't generate position-independent code (default)\n\
3540 -march=ISA set the RISC-V architecture\n\
3541 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3542 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3543 -mabi=ABI set the RISC-V ABI\n\
3544 -mrelax enable relax (default)\n\
3545 -mno-relax disable relax\n\
3546 -march-attr generate RISC-V arch attribute\n\
3547 -mno-arch-attr don't generate RISC-V arch attribute\n\
3551 /* Standard calling conventions leave the CFA at SP on entry. */
3553 riscv_cfi_frame_initial_instructions (void)
3555 cfi_add_CFA_def_cfa_register (X_SP
);
3559 tc_riscv_regname_to_dw2regnum (char *regname
)
3563 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3566 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3569 /* CSRs are numbered 4096 -> 8191. */
3570 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3573 as_bad (_("unknown register `%s'"), regname
);
3578 riscv_elf_final_processing (void)
3580 riscv_set_abi_by_arch ();
3581 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3584 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3585 since these directives break relaxation when used with symbol deltas. */
3588 s_riscv_leb128 (int sign
)
3591 char *save_in
= input_line_pointer
;
3594 if (exp
.X_op
!= O_constant
)
3595 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3596 demand_empty_rest_of_line ();
3598 input_line_pointer
= save_in
;
3599 return s_leb128 (sign
);
3602 /* Parse the .insn directive. */
3605 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3607 char *str
= input_line_pointer
;
3608 struct riscv_cl_insn insn
;
3609 expressionS imm_expr
;
3610 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3613 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3614 ++input_line_pointer
;
3616 save_c
= *input_line_pointer
;
3617 *input_line_pointer
= '\0';
3619 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3620 &imm_reloc
, insn_type_hash
);
3624 as_bad ("%s `%s'", error
, str
);
3628 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3629 append_insn (&insn
, &imm_expr
, imm_reloc
);
3632 *input_line_pointer
= save_c
;
3633 demand_empty_rest_of_line ();
3636 /* Update arch and priv attributes. If we don't set the corresponding ELF
3637 attributes, then try to output the default ones. */
3640 riscv_write_out_attrs (void)
3642 const char *arch_str
, *priv_str
, *p
;
3643 /* versions[0] is major, versions[1] is minor,
3644 and versions[3] is revision. */
3645 unsigned versions
[3] = {0}, number
= 0;
3648 /* Re-write arch attribute to normalize the arch string. */
3649 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3650 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3651 xfree ((void *)arch_str
);
3653 /* For the file without any instruction, we don't set the default_priv_spec
3654 according to the priv attributes since the md_assemble isn't called.
3655 Call riscv_set_default_priv_spec here for the above case, although
3656 it seems strange. */
3658 && !riscv_set_default_priv_spec (NULL
))
3661 /* If we already have set elf priv attributes, then no need to do anything,
3662 assembler will generate them according to what you set. Otherwise, don't
3663 generate or update them when no CSR and priv instructions are used.
3664 Generate the priv attributes according to default_priv_spec, which can be
3665 set by -mpriv-spec and --with-priv-spec, and be updated by the original
3666 priv attribute sets. */
3667 if (!explicit_priv_attr
)
3670 /* Re-write priv attributes by default_priv_spec. */
3671 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3673 for (i
= 0; *p
; ++p
)
3675 if (*p
== '.' && i
< 3)
3677 versions
[i
++] = number
;
3680 else if (ISDIGIT (*p
))
3681 number
= (number
* 10) + (*p
- '0');
3684 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3688 versions
[i
] = number
;
3690 /* Set the priv attributes. */
3691 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3692 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3693 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3696 /* Add the default contents for the .riscv.attributes section. If any
3697 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3698 to update the arch and priv attributes. */
3701 riscv_set_public_attributes (void)
3703 if (riscv_opts
.arch_attr
|| explicit_attr
)
3704 riscv_write_out_attrs ();
3707 /* Called after all assembly has been done. */
3712 riscv_set_public_attributes ();
3715 /* Given a symbolic attribute NAME, return the proper integer value.
3716 Returns -1 if the attribute is not known. */
3719 riscv_convert_symbolic_attribute (const char *name
)
3728 /* When you modify this table you should
3729 also modify the list in doc/c-riscv.texi. */
3730 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3734 T(priv_spec_revision
),
3735 T(unaligned_access
),
3745 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3746 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3747 return attribute_table
[i
].tag
;
3752 /* Parse a .attribute directive. */
3755 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3757 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3759 obj_attribute
*attr
;
3761 explicit_attr
= TRUE
;
3764 case Tag_RISCV_arch
:
3766 attr
= elf_known_obj_attributes_proc (stdoutput
);
3767 if (!start_assemble
)
3768 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3770 as_fatal (_(".attribute arch must set before any instructions"));
3772 if (old_xlen
!= xlen
)
3774 /* We must re-init bfd again if xlen is changed. */
3775 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3776 bfd_find_target (riscv_target_format (), stdoutput
);
3778 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3779 as_warn (_("Could not set architecture and machine"));
3783 case Tag_RISCV_priv_spec
:
3784 case Tag_RISCV_priv_spec_minor
:
3785 case Tag_RISCV_priv_spec_revision
:
3787 as_fatal (_(".attribute priv spec must set before any instructions"));
3795 /* Pseudo-op table. */
3797 static const pseudo_typeS riscv_pseudo_table
[] =
3799 /* RISC-V-specific pseudo-ops. */
3800 {"option", s_riscv_option
, 0},
3804 {"dtprelword", s_dtprel
, 4},
3805 {"dtpreldword", s_dtprel
, 8},
3807 {"uleb128", s_riscv_leb128
, 0},
3808 {"sleb128", s_riscv_leb128
, 1},
3809 {"insn", s_riscv_insn
, 0},
3810 {"attribute", s_riscv_attribute
, 0},
3816 riscv_pop_insert (void)
3818 extern void pop_insert (const pseudo_typeS
*);
3820 pop_insert (riscv_pseudo_table
);