1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "elf/riscv.h"
33 #include "opcode/riscv.h"
37 /* Information about an instruction, including its format, operands
41 /* The opcode's entry in riscv_opcodes. */
42 const struct riscv_opcode
*insn_mo
;
44 /* The encoded instruction bits. */
47 /* The frag that contains the instruction. */
50 /* The offset into FRAG of the first instruction byte. */
53 /* The relocs associated with the instruction, if any. */
58 #define DEFAULT_ARCH "riscv64"
61 static const char default_arch
[] = DEFAULT_ARCH
;
63 static unsigned xlen
= 0; /* width of an x-register */
64 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
65 static bfd_boolean rve_abi
= FALSE
;
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int rve
; /* Generate RVE code. */
79 int relax
; /* Emit relocs the linker is allowed to relax. */
82 static struct riscv_set_options riscv_opts
=
91 riscv_set_rvc (bfd_boolean rvc_value
)
94 elf_flags
|= EF_RISCV_RVC
;
96 riscv_opts
.rvc
= rvc_value
;
100 riscv_set_rve (bfd_boolean rve_value
)
102 riscv_opts
.rve
= rve_value
;
109 struct riscv_subset
*next
;
112 static struct riscv_subset
*riscv_subsets
;
115 riscv_subset_supports (unsigned xlen_required
, const char *feature
)
117 struct riscv_subset
*s
;
119 if (xlen_required
&& xlen
!= xlen_required
)
122 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
123 if (strcasecmp (s
->name
, feature
) == 0)
130 riscv_multi_subset_supports (unsigned xlen_required
, const char *features
[])
133 bfd_boolean supported
= TRUE
;
135 for (;features
[i
]; ++i
)
136 supported
= supported
&& riscv_subset_supports (xlen_required
, features
[i
]);
142 riscv_clear_subsets (void)
144 while (riscv_subsets
!= NULL
)
146 struct riscv_subset
*next
= riscv_subsets
->next
;
147 free ((void *) riscv_subsets
->name
);
148 free (riscv_subsets
);
149 riscv_subsets
= next
;
154 riscv_add_subset (const char *subset
)
156 struct riscv_subset
*s
= xmalloc (sizeof *s
);
158 s
->name
= xstrdup (subset
);
159 s
->next
= riscv_subsets
;
163 /* Set which ISA and extensions are available. */
166 riscv_set_arch (const char *s
)
168 const char *all_subsets
= "imafdqc";
169 char *extension
= NULL
;
172 riscv_clear_subsets();
174 if (strncmp (p
, "rv32", 4) == 0)
179 else if (strncmp (p
, "rv64", 4) == 0)
185 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
194 riscv_add_subset ("e");
195 riscv_add_subset ("i");
198 as_fatal ("-march=%s: rv%de is not a valid base ISA", s
, xlen
);
204 for ( ; *all_subsets
!= 'q'; all_subsets
++)
206 const char subset
[] = {*all_subsets
, '\0'};
207 riscv_add_subset (subset
);
212 as_fatal ("-march=%s: first ISA subset must be `e', `i' or `g'", s
);
219 char *subset
= xstrdup (p
);
222 while (*++q
!= '\0' && *q
!= '_')
227 as_fatal ("-march=%s: only one non-standard extension is supported"
228 " (found `%s' and `%s')", s
, extension
, subset
);
230 riscv_add_subset (subset
);
231 p
+= strlen (subset
);
235 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
237 const char subset
[] = {*p
, 0};
238 riscv_add_subset (subset
);
243 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
246 if (riscv_subset_supports (0, "e") && riscv_subset_supports (0, "f"))
247 as_fatal ("-march=%s: rv32e does not support the `f' extension", s
);
249 if (riscv_subset_supports (0, "d") && !riscv_subset_supports (0, "f"))
250 as_fatal ("-march=%s: `d' extension requires `f' extension", s
);
252 if (riscv_subset_supports (0, "q") && !riscv_subset_supports (0, "d"))
253 as_fatal ("-march=%s: `q' extension requires `d' extension", s
);
255 if (riscv_subset_supports (0, "q") && xlen
< 64)
256 as_fatal ("-march=%s: rv32 does not support the `q' extension", s
);
261 /* Handle of the OPCODE hash table. */
262 static struct hash_control
*op_hash
= NULL
;
264 /* Handle of the type of .insn hash table. */
265 static struct hash_control
*insn_type_hash
= NULL
;
267 /* This array holds the chars that always start a comment. If the
268 pre-processor is disabled, these aren't very useful */
269 const char comment_chars
[] = "#";
271 /* This array holds the chars that only start a comment at the beginning of
272 a line. If the line seems to have the form '# 123 filename'
273 .line and .file directives will appear in the pre-processed output */
274 /* Note that input_file.c hand checks for '#' at the beginning of the
275 first line of the input file. This is because the compiler outputs
276 #NO_APP at the beginning of its output. */
277 /* Also note that C style comments are always supported. */
278 const char line_comment_chars
[] = "#";
280 /* This array holds machine specific line separator characters. */
281 const char line_separator_chars
[] = ";";
283 /* Chars that can be used to separate mant from exp in floating point nums */
284 const char EXP_CHARS
[] = "eE";
286 /* Chars that mean this number is a floating point constant */
289 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
291 /* Macros for encoding relaxation state for RVC branches and far jumps. */
292 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
295 | ((uncond) ? 1 : 0) \
298 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
299 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
300 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
301 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
303 /* Is the given value a sign-extended 32-bit value? */
304 #define IS_SEXT_32BIT_NUM(x) \
305 (((x) &~ (offsetT) 0x7fffffff) == 0 \
306 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
308 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
309 #define IS_ZEXT_32BIT_NUM(x) \
310 (((x) &~ (offsetT) 0xffffffff) == 0 \
311 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
313 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
314 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
315 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
316 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
318 /* Determine if an instruction matches an opcode. */
319 #define OPCODE_MATCHES(OPCODE, OP) \
320 (((OPCODE) & MASK_##OP) == MATCH_##OP)
322 static char *expr_end
;
324 /* The default target format to use. */
327 riscv_target_format (void)
329 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
332 /* Return the length of instruction INSN. */
334 static inline unsigned int
335 insn_length (const struct riscv_cl_insn
*insn
)
337 return riscv_insn_length (insn
->insn_opcode
);
340 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
343 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
346 insn
->insn_opcode
= mo
->match
;
352 /* Install INSN at the location specified by its "frag" and "where" fields. */
355 install_insn (const struct riscv_cl_insn
*insn
)
357 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
358 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
361 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
362 and install the opcode in the new location. */
365 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
369 if (insn
->fixp
!= NULL
)
371 insn
->fixp
->fx_frag
= frag
;
372 insn
->fixp
->fx_where
= where
;
377 /* Add INSN to the end of the output. */
380 add_fixed_insn (struct riscv_cl_insn
*insn
)
382 char *f
= frag_more (insn_length (insn
));
383 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
387 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
388 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
390 frag_grow (max_chars
);
391 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
392 frag_var (rs_machine_dependent
, max_chars
, var
,
393 subtype
, symbol
, offset
, NULL
);
396 /* Compute the length of a branch sequence, and adjust the stored length
397 accordingly. If FRAGP is NULL, the worst-case length is returned. */
400 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
402 int jump
, rvc
, length
= 8;
407 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
408 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
409 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
411 /* Assume jumps are in range; the linker will catch any that aren't. */
412 length
= jump
? 4 : 8;
414 if (fragp
->fr_symbol
!= NULL
415 && S_IS_DEFINED (fragp
->fr_symbol
)
416 && !S_IS_WEAK (fragp
->fr_symbol
)
417 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
419 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
420 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
421 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
423 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
425 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
427 else if (!jump
&& rvc
)
432 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
437 /* Information about an opcode name, mnemonics and its value. */
444 /* List for all supported opcode name. */
445 static const struct opcode_name_t opcode_name_list
[] =
490 /* Hash table for lookup opcode name. */
491 static struct hash_control
*opcode_names_hash
= NULL
;
493 /* Initialization for hash table of opcode name. */
495 init_opcode_names_hash (void)
498 const struct opcode_name_t
*opcode
;
500 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
502 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
505 as_fatal (_("internal error: can't hash `%s': %s"),
506 opcode
->name
, retval
);
510 /* Find `s` is a valid opcode name or not,
511 return the opcode name info if found. */
512 static const struct opcode_name_t
*
513 opcode_name_lookup (char **s
)
517 struct opcode_name_t
*o
;
519 /* Find end of name. */
521 if (is_name_beginner (*e
))
523 while (is_part_of_name (*e
))
526 /* Terminate name. */
530 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
532 /* Advance to next token if one was recognized. */
556 static struct hash_control
*reg_names_hash
= NULL
;
558 #define ENCODE_REG_HASH(cls, n) \
559 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
560 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
561 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
564 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
566 void *hash
= ENCODE_REG_HASH (class, n
);
567 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
570 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
574 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
578 for (i
= 0; i
< n
; i
++)
579 hash_reg_name (class, names
[i
], i
);
583 reg_lookup_internal (const char *s
, enum reg_class
class)
585 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
587 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
590 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
593 return DECODE_REG_NUM (r
);
597 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
603 /* Find end of name. */
605 if (is_name_beginner (*e
))
607 while (is_part_of_name (*e
))
610 /* Terminate name. */
614 /* Look for the register. Advance to next token if one was recognized. */
615 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
625 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
627 const char *p
= strchr (*s
, ',');
628 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
633 for (i
= 0; i
< size
; i
++)
634 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
644 /* For consistency checking, verify that all bits are specified either
645 by the match/mask part of the instruction definition, or by the
648 `length` could be 0, 4 or 8, 0 for auto detection. */
650 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
652 const char *p
= opc
->args
;
654 insn_t used_bits
= opc
->mask
;
656 insn_t required_bits
;
659 insn_width
= 8 * riscv_insn_length (opc
->match
);
661 insn_width
= 8 * length
;
663 required_bits
= ~0ULL >> (64 - insn_width
);
665 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
667 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
668 opc
->name
, opc
->args
);
672 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
679 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
680 case 'c': break; /* RS1, constrained to equal sp */
681 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
682 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
683 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
684 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
685 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
686 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
687 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
688 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
689 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
690 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
691 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
692 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
693 case 'w': break; /* RS1S, constrained to equal RD */
694 case 'x': break; /* RS2S, constrained to equal RD */
695 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
696 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
697 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
698 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
699 case 'U': break; /* RS1, constrained to equal RD */
700 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
701 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
702 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
703 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
704 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
705 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
706 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
707 case 'F': /* funct */
710 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
711 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
713 as_bad (_("internal: bad RISC-V opcode"
714 " (unknown operand type `CF%c'): %s %s"),
715 c
, opc
->name
, opc
->args
);
720 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
721 c
, opc
->name
, opc
->args
);
728 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
729 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
731 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
732 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
733 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
735 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
736 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
737 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
738 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
739 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
740 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
741 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
742 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
743 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
744 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
745 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
747 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
748 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
749 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
750 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
751 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
756 case 'F': /* funct */
759 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
760 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
761 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
763 as_bad (_("internal: bad RISC-V opcode"
764 " (unknown operand type `F%c'): %s %s"),
765 c
, opc
->name
, opc
->args
);
769 case 'O': /* opcode */
772 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
773 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
775 as_bad (_("internal: bad RISC-V opcode"
776 " (unknown operand type `F%c'): %s %s"),
777 c
, opc
->name
, opc
->args
);
782 as_bad (_("internal: bad RISC-V opcode "
783 "(unknown operand type `%c'): %s %s"),
784 c
, opc
->name
, opc
->args
);
788 if (used_bits
!= required_bits
)
790 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
791 ~(unsigned long)(used_bits
& required_bits
),
792 opc
->name
, opc
->args
);
798 struct percent_op_match
801 bfd_reloc_code_real_type reloc
;
804 /* Common hash table initialization function for
805 instruction and .insn directive. */
806 static struct hash_control
*
807 init_opcode_hash (const struct riscv_opcode
*opcodes
,
808 bfd_boolean insn_directive_p
)
812 struct hash_control
*hash
= hash_new ();
813 while (opcodes
[i
].name
)
815 const char *name
= opcodes
[i
].name
;
816 const char *hash_error
=
817 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
821 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
822 opcodes
[i
].name
, hash_error
);
823 /* Probably a memory allocation problem? Give up now. */
824 as_fatal (_("Broken assembler. No assembly attempted."));
829 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
831 if (insn_directive_p
)
832 length
= ((name
[0] == 'c') ? 2 : 4);
834 length
= 0; /* Let assembler determine the length. */
835 if (!validate_riscv_insn (&opcodes
[i
], length
))
836 as_fatal (_("Broken assembler. No assembly attempted."));
839 gas_assert (!insn_directive_p
);
842 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
848 /* This function is called once, at assembler startup time. It should set up
849 all the tables, etc. that the MD part of the assembler will need. */
854 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
856 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
857 as_warn (_("Could not set architecture and machine"));
859 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
860 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
862 reg_names_hash
= hash_new ();
863 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
864 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
865 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
866 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
868 /* Add "fp" as an alias for "s0". */
869 hash_reg_name (RCLASS_GPR
, "fp", 8);
871 opcode_names_hash
= hash_new ();
872 init_opcode_names_hash ();
874 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
875 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
876 #include "opcode/riscv-opc.h"
879 /* Set the default alignment for the text section. */
880 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
884 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
891 case BFD_RELOC_RISCV_HI20
:
892 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
894 case BFD_RELOC_RISCV_LO12_S
:
895 return ENCODE_STYPE_IMM (value
);
897 case BFD_RELOC_RISCV_LO12_I
:
898 return ENCODE_ITYPE_IMM (value
);
905 /* Output an instruction. IP is the instruction information.
906 ADDRESS_EXPR is an operand of the instruction to be used with
910 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
911 bfd_reloc_code_real_type reloc_type
)
913 dwarf2_emit_insn (0);
915 if (reloc_type
!= BFD_RELOC_UNUSED
)
917 reloc_howto_type
*howto
;
919 gas_assert (address_expr
);
920 if (reloc_type
== BFD_RELOC_12_PCREL
921 || reloc_type
== BFD_RELOC_RISCV_JMP
)
923 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
924 int best_case
= riscv_insn_length (ip
->insn_opcode
);
925 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
926 add_relaxed_insn (ip
, worst_case
, best_case
,
927 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
928 address_expr
->X_add_symbol
,
929 address_expr
->X_add_number
);
934 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
936 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
938 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
939 bfd_get_reloc_size (howto
),
940 address_expr
, FALSE
, reloc_type
);
942 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
949 /* We need to start a new frag after any instruction that can be
950 optimized away or compressed by the linker during relaxation, to prevent
951 the assembler from computing static offsets across such an instruction.
952 This is necessary to get correct EH info. */
953 if (reloc_type
== BFD_RELOC_RISCV_CALL
954 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
955 || reloc_type
== BFD_RELOC_RISCV_HI20
956 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
957 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
958 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
960 frag_wane (frag_now
);
965 /* Build an instruction created by a macro expansion. This is passed
966 a pointer to the count of instructions created so far, an
967 expression, the name of the instruction to build, an operand format
968 string, and corresponding arguments. */
971 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
973 const struct riscv_opcode
*mo
;
974 struct riscv_cl_insn insn
;
975 bfd_reloc_code_real_type r
;
978 va_start (args
, fmt
);
980 r
= BFD_RELOC_UNUSED
;
981 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
984 /* Find a non-RVC variant of the instruction. append_insn will compress
986 while (riscv_insn_length (mo
->match
) < 4)
988 gas_assert (strcmp (name
, mo
->name
) == 0);
990 create_insn (&insn
, mo
);
996 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1000 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1004 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1008 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1014 gas_assert (ep
!= NULL
);
1015 r
= va_arg (args
, int);
1023 as_fatal (_("internal error: invalid macro"));
1028 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1030 append_insn (&insn
, ep
, r
);
1033 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1036 normalize_constant_expr (expressionS
*ex
)
1040 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1041 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1042 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1046 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1047 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1050 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1051 bfd_boolean maybe_csr
)
1053 if (ex
->X_op
== O_big
)
1054 as_bad (_("unsupported large constant"));
1055 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1056 as_bad (_("unknown CSR `%s'"),
1057 S_GET_NAME (ex
->X_add_symbol
));
1058 else if (ex
->X_op
!= O_constant
)
1059 as_bad (_("Instruction %s requires absolute expression"),
1061 normalize_constant_expr (ex
);
1065 make_internal_label (void)
1067 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1068 (valueT
) frag_now_fix (), frag_now
);
1071 /* Load an entry from the GOT. */
1073 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1074 const char *lo_insn
, const char *lo_pattern
,
1075 bfd_reloc_code_real_type hi_reloc
,
1076 bfd_reloc_code_real_type lo_reloc
)
1079 ep2
.X_op
= O_symbol
;
1080 ep2
.X_add_symbol
= make_internal_label ();
1081 ep2
.X_add_number
= 0;
1083 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1084 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1088 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1089 bfd_reloc_code_real_type hi_reloc
,
1090 bfd_reloc_code_real_type lo_reloc
)
1092 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1096 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1097 bfd_reloc_code_real_type hi_reloc
,
1098 bfd_reloc_code_real_type lo_reloc
)
1100 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1103 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1105 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1106 bfd_reloc_code_real_type reloc
)
1108 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1109 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1112 /* Load an integer constant into a register. */
1115 load_const (int reg
, expressionS
*ep
)
1117 int shift
= RISCV_IMM_BITS
;
1118 expressionS upper
= *ep
, lower
= *ep
;
1119 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1120 upper
.X_add_number
-= lower
.X_add_number
;
1122 if (ep
->X_op
!= O_constant
)
1124 as_bad (_("unsupported large constant"));
1128 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1130 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1131 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1134 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1135 load_const (reg
, &upper
);
1137 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
1138 if (lower
.X_add_number
!= 0)
1139 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
1143 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1146 if (upper
.X_add_number
!= 0)
1148 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
1152 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1153 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
1154 BFD_RELOC_RISCV_LO12_I
);
1158 /* Expand RISC-V assembly macros into one or more instructions. */
1160 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1161 bfd_reloc_code_real_type
*imm_reloc
)
1163 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1164 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1165 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1166 int mask
= ip
->insn_mo
->mask
;
1171 load_const (rd
, imm_expr
);
1176 /* Load the address of a symbol into a register. */
1177 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1178 as_bad (_("offset too large"));
1180 if (imm_expr
->X_op
== O_constant
)
1181 load_const (rd
, imm_expr
);
1182 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1183 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1184 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1185 else /* Local PIC symbol, or any non-PIC symbol */
1186 pcrel_load (rd
, rd
, imm_expr
, "addi",
1187 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1191 pcrel_load (rd
, rd
, imm_expr
, "addi",
1192 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1196 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1197 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1201 pcrel_load (rd
, rd
, imm_expr
, "lb",
1202 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1206 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1207 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1211 pcrel_load (rd
, rd
, imm_expr
, "lh",
1212 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1216 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1217 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1221 pcrel_load (rd
, rd
, imm_expr
, "lw",
1222 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1226 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1227 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1231 pcrel_load (rd
, rd
, imm_expr
, "ld",
1232 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1236 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1237 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1241 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1242 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1246 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1247 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1251 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1252 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1256 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1257 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1261 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1262 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1266 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1267 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1271 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1272 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1276 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1280 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1285 static const struct percent_op_match percent_op_utype
[] =
1287 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1288 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1289 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1290 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1291 {"%hi", BFD_RELOC_RISCV_HI20
},
1295 static const struct percent_op_match percent_op_itype
[] =
1297 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1298 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1299 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1303 static const struct percent_op_match percent_op_stype
[] =
1305 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1306 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1307 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1311 static const struct percent_op_match percent_op_rtype
[] =
1313 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1317 /* Return true if *STR points to a relocation operator. When returning true,
1318 move *STR over the operator and store its relocation code in *RELOC.
1319 Leave both *STR and *RELOC alone when returning false. */
1322 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1323 const struct percent_op_match
*percent_op
)
1325 for ( ; percent_op
->str
; percent_op
++)
1326 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1328 int len
= strlen (percent_op
->str
);
1330 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1333 *str
+= strlen (percent_op
->str
);
1334 *reloc
= percent_op
->reloc
;
1336 /* Check whether the output BFD supports this relocation.
1337 If not, issue an error and fall back on something safe. */
1338 if (*reloc
!= BFD_RELOC_UNUSED
1339 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1341 as_bad ("relocation %s isn't supported by the current ABI",
1343 *reloc
= BFD_RELOC_UNUSED
;
1351 my_getExpression (expressionS
*ep
, char *str
)
1355 save_in
= input_line_pointer
;
1356 input_line_pointer
= str
;
1358 expr_end
= input_line_pointer
;
1359 input_line_pointer
= save_in
;
1362 /* Parse string STR as a 16-bit relocatable operand. Store the
1363 expression in *EP and the relocation, if any, in RELOC.
1364 Return the number of relocation operators used (0 or 1).
1366 On exit, EXPR_END points to the first character after the expression. */
1369 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1370 char *str
, const struct percent_op_match
*percent_op
)
1373 unsigned crux_depth
, str_depth
, regno
;
1376 /* First, check for integer registers. */
1377 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1379 ep
->X_op
= O_register
;
1380 ep
->X_add_number
= regno
;
1384 /* Search for the start of the main expression.
1385 End the loop with CRUX pointing to the start
1386 of the main expression and with CRUX_DEPTH containing the number
1387 of open brackets at that point. */
1394 crux_depth
= str_depth
;
1396 /* Skip over whitespace and brackets, keeping count of the number
1398 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1404 && parse_relocation (&str
, reloc
, percent_op
));
1406 my_getExpression (ep
, crux
);
1409 /* Match every open bracket. */
1410 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1415 as_bad ("unclosed '('");
1422 /* Parse opcode name, could be an mnemonics or number. */
1424 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1425 char *str
, const struct percent_op_match
*percent_op
)
1427 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1431 ep
->X_op
= O_constant
;
1432 ep
->X_add_number
= o
->val
;
1436 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1439 /* Detect and handle implicitly zero load-store offsets. For example,
1440 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1441 an implicit offset was detected. */
1444 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1446 /* Check whether there is only a single bracketed expression left.
1447 If so, it must be the base register and the constant must be zero. */
1448 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1450 ep
->X_op
= O_constant
;
1451 ep
->X_add_number
= 0;
1458 /* This routine assembles an instruction into its binary format. As a
1459 side effect, it sets the global variable imm_reloc to the type of
1460 relocation to do if one of the operands is an address expression. */
1463 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1464 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1469 struct riscv_opcode
*insn
;
1474 const struct percent_op_match
*p
;
1475 const char *error
= "unrecognized opcode";
1477 /* Parse the name of the instruction. Terminate the string if whitespace
1478 is found so that hash_find only sees the name part of the string. */
1479 for (s
= str
; *s
!= '\0'; ++s
)
1487 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1490 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1492 if (!riscv_multi_subset_supports (insn
->xlen_requirement
, insn
->subset
))
1495 create_insn (ip
, insn
);
1498 imm_expr
->X_op
= O_absent
;
1499 *imm_reloc
= BFD_RELOC_UNUSED
;
1500 p
= percent_op_itype
;
1502 for (args
= insn
->args
;; ++args
)
1504 s
+= strspn (s
, " \t");
1507 case '\0': /* End of args. */
1508 if (insn
->pinfo
!= INSN_MACRO
)
1510 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1513 /* For .insn, insn->match and insn->mask are 0. */
1514 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1522 /* Successful assembly. */
1529 case 's': /* RS1 x8-x15 */
1530 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1531 || !(regno
>= 8 && regno
<= 15))
1533 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1535 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1536 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1537 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1540 case 't': /* RS2 x8-x15 */
1541 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1542 || !(regno
>= 8 && regno
<= 15))
1544 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1546 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1547 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1548 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1551 case 'U': /* RS1, constrained to equal RD. */
1552 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1553 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1557 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1559 INSERT_OPERAND (CRS2
, *ip
, regno
);
1561 case 'c': /* RS1, constrained to equal sp. */
1562 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1567 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1568 || imm_expr
->X_op
!= O_constant
1569 || imm_expr
->X_add_number
<= 0
1570 || imm_expr
->X_add_number
>= 64)
1572 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1575 imm_expr
->X_op
= O_absent
;
1578 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1579 || imm_expr
->X_op
!= O_constant
1580 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1581 || imm_expr
->X_add_number
<= 0
1582 || imm_expr
->X_add_number
>= 32)
1584 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1587 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1588 || imm_expr
->X_op
!= O_constant
1589 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1590 || imm_expr
->X_add_number
< 0
1591 || imm_expr
->X_add_number
>= 256)
1593 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1596 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1597 || imm_expr
->X_op
!= O_constant
1598 || imm_expr
->X_add_number
== 0
1599 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1601 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1604 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1605 || imm_expr
->X_op
!= O_constant
1606 || imm_expr
->X_add_number
== 0
1607 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1609 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1612 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1614 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1615 || imm_expr
->X_op
!= O_constant
1616 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1618 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1621 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1623 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1624 || imm_expr
->X_op
!= O_constant
1625 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1627 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1630 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1632 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1633 || imm_expr
->X_op
!= O_constant
1634 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1637 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1640 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1642 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1643 || imm_expr
->X_op
!= O_constant
1644 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1647 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1650 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1651 || imm_expr
->X_op
!= O_constant
1652 /* C.addiw, c.li, and c.andi allow zero immediate.
1653 C.addi allows zero immediate as hint. Otherwise this
1655 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1657 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1660 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1661 || imm_expr
->X_op
!= O_constant
1662 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1663 || imm_expr
->X_add_number
== 0)
1666 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1669 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1670 || imm_expr
->X_op
!= O_constant
1671 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1672 || imm_expr
->X_add_number
== 0)
1675 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1678 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1680 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1681 || imm_expr
->X_op
!= O_constant
1682 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1685 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1688 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1690 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1691 || imm_expr
->X_op
!= O_constant
1692 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1695 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1698 p
= percent_op_utype
;
1699 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1702 if (imm_expr
->X_op
!= O_constant
1703 || imm_expr
->X_add_number
<= 0
1704 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1705 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1706 && (imm_expr
->X_add_number
<
1707 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1709 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1712 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1713 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1714 || ((int32_t)imm_expr
->X_add_number
1715 != imm_expr
->X_add_number
))
1717 imm_expr
->X_add_number
=
1718 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1724 case 'S': /* Floating-point RS1 x8-x15. */
1725 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1726 || !(regno
>= 8 && regno
<= 15))
1728 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1730 case 'D': /* Floating-point RS2 x8-x15. */
1731 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1732 || !(regno
>= 8 && regno
<= 15))
1734 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1736 case 'T': /* Floating-point RS2. */
1737 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1739 INSERT_OPERAND (CRS2
, *ip
, regno
);
1745 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1746 || imm_expr
->X_op
!= O_constant
1747 || imm_expr
->X_add_number
< 0
1748 || imm_expr
->X_add_number
>= 16)
1750 as_bad (_("bad value for funct4 field, "
1751 "value must be 0...15"));
1755 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1756 imm_expr
->X_op
= O_absent
;
1760 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1761 || imm_expr
->X_op
!= O_constant
1762 || imm_expr
->X_add_number
< 0
1763 || imm_expr
->X_add_number
>= 8)
1765 as_bad (_("bad value for funct3 field, "
1766 "value must be 0...7"));
1769 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1770 imm_expr
->X_op
= O_absent
;
1774 as_bad (_("bad compressed FUNCT field"
1775 " specifier 'CF%c'\n"),
1781 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1800 case '<': /* Shift amount, 0 - 31. */
1801 my_getExpression (imm_expr
, s
);
1802 check_absolute_expr (ip
, imm_expr
, FALSE
);
1803 if ((unsigned long) imm_expr
->X_add_number
> 31)
1804 as_bad (_("Improper shift amount (%lu)"),
1805 (unsigned long) imm_expr
->X_add_number
);
1806 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1807 imm_expr
->X_op
= O_absent
;
1811 case '>': /* Shift amount, 0 - (XLEN-1). */
1812 my_getExpression (imm_expr
, s
);
1813 check_absolute_expr (ip
, imm_expr
, FALSE
);
1814 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1815 as_bad (_("Improper shift amount (%lu)"),
1816 (unsigned long) imm_expr
->X_add_number
);
1817 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1818 imm_expr
->X_op
= O_absent
;
1822 case 'Z': /* CSRRxI immediate. */
1823 my_getExpression (imm_expr
, s
);
1824 check_absolute_expr (ip
, imm_expr
, FALSE
);
1825 if ((unsigned long) imm_expr
->X_add_number
> 31)
1826 as_bad (_("Improper CSRxI immediate (%lu)"),
1827 (unsigned long) imm_expr
->X_add_number
);
1828 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1829 imm_expr
->X_op
= O_absent
;
1833 case 'E': /* Control register. */
1834 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1835 INSERT_OPERAND (CSR
, *ip
, regno
);
1838 my_getExpression (imm_expr
, s
);
1839 check_absolute_expr (ip
, imm_expr
, TRUE
);
1840 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1841 as_bad (_("Improper CSR address (%lu)"),
1842 (unsigned long) imm_expr
->X_add_number
);
1843 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1844 imm_expr
->X_op
= O_absent
;
1849 case 'm': /* Rounding mode. */
1850 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1852 INSERT_OPERAND (RM
, *ip
, regno
);
1858 case 'Q': /* Fence predecessor/successor. */
1859 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1863 INSERT_OPERAND (PRED
, *ip
, regno
);
1865 INSERT_OPERAND (SUCC
, *ip
, regno
);
1870 case 'd': /* Destination register. */
1871 case 's': /* Source register. */
1872 case 't': /* Target register. */
1873 case 'r': /* rs3. */
1874 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1880 /* Now that we have assembled one operand, we use the args
1881 string to figure out where it goes in the instruction. */
1885 INSERT_OPERAND (RS1
, *ip
, regno
);
1888 INSERT_OPERAND (RD
, *ip
, regno
);
1891 INSERT_OPERAND (RS2
, *ip
, regno
);
1894 INSERT_OPERAND (RS3
, *ip
, regno
);
1901 case 'D': /* Floating point rd. */
1902 case 'S': /* Floating point rs1. */
1903 case 'T': /* Floating point rs2. */
1904 case 'U': /* Floating point rs1 and rs2. */
1905 case 'R': /* Floating point rs3. */
1906 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1914 INSERT_OPERAND (RD
, *ip
, regno
);
1917 INSERT_OPERAND (RS1
, *ip
, regno
);
1920 INSERT_OPERAND (RS1
, *ip
, regno
);
1923 INSERT_OPERAND (RS2
, *ip
, regno
);
1926 INSERT_OPERAND (RS3
, *ip
, regno
);
1935 my_getExpression (imm_expr
, s
);
1936 if (imm_expr
->X_op
!= O_big
1937 && imm_expr
->X_op
!= O_constant
)
1939 normalize_constant_expr (imm_expr
);
1944 my_getExpression (imm_expr
, s
);
1945 normalize_constant_expr (imm_expr
);
1946 /* The 'A' format specifier must be a symbol. */
1947 if (imm_expr
->X_op
!= O_symbol
)
1949 *imm_reloc
= BFD_RELOC_32
;
1954 my_getExpression (imm_expr
, s
);
1955 normalize_constant_expr (imm_expr
);
1956 /* The 'B' format specifier must be a symbol or a constant. */
1957 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1959 if (imm_expr
->X_op
== O_symbol
)
1960 *imm_reloc
= BFD_RELOC_32
;
1964 case 'j': /* Sign-extended immediate. */
1965 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1966 p
= percent_op_itype
;
1968 case 'q': /* Store displacement. */
1969 p
= percent_op_stype
;
1970 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1972 case 'o': /* Load displacement. */
1973 p
= percent_op_itype
;
1974 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1976 case '0': /* AMO "displacement," which must be zero. */
1977 p
= percent_op_rtype
;
1978 *imm_reloc
= BFD_RELOC_UNUSED
;
1980 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1983 /* If this value won't fit into a 16 bit offset, then go
1984 find a macro that will generate the 32 bit offset
1986 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1988 normalize_constant_expr (imm_expr
);
1989 if (imm_expr
->X_op
!= O_constant
1990 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1991 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1992 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1999 case 'p': /* PC-relative offset. */
2001 *imm_reloc
= BFD_RELOC_12_PCREL
;
2002 my_getExpression (imm_expr
, s
);
2006 case 'u': /* Upper 20 bits. */
2007 p
= percent_op_utype
;
2008 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2009 && imm_expr
->X_op
== O_constant
)
2011 if (imm_expr
->X_add_number
< 0
2012 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2013 as_bad (_("lui expression not in range 0..1048575"));
2015 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2016 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2021 case 'a': /* 20-bit PC-relative offset. */
2023 my_getExpression (imm_expr
, s
);
2025 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2029 my_getExpression (imm_expr
, s
);
2031 if (strcmp (s
, "@plt") == 0)
2033 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2037 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2043 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2044 || imm_expr
->X_op
!= O_constant
2045 || imm_expr
->X_add_number
< 0
2046 || imm_expr
->X_add_number
>= 128
2047 || (imm_expr
->X_add_number
& 0x3) != 3)
2049 as_bad (_("bad value for opcode field, "
2050 "value must be 0...127 and "
2051 "lower 2 bits must be 0x3"));
2055 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2056 imm_expr
->X_op
= O_absent
;
2060 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2061 || imm_expr
->X_op
!= O_constant
2062 || imm_expr
->X_add_number
< 0
2063 || imm_expr
->X_add_number
>= 3)
2065 as_bad (_("bad value for opcode field, "
2066 "value must be 0...2"));
2070 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2071 imm_expr
->X_op
= O_absent
;
2075 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2083 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2084 || imm_expr
->X_op
!= O_constant
2085 || imm_expr
->X_add_number
< 0
2086 || imm_expr
->X_add_number
>= 128)
2088 as_bad (_("bad value for funct7 field, "
2089 "value must be 0...127"));
2093 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2094 imm_expr
->X_op
= O_absent
;
2098 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2099 || imm_expr
->X_op
!= O_constant
2100 || imm_expr
->X_add_number
< 0
2101 || imm_expr
->X_add_number
>= 8)
2103 as_bad (_("bad value for funct3 field, "
2104 "value must be 0...7"));
2108 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2109 imm_expr
->X_op
= O_absent
;
2113 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2114 || imm_expr
->X_op
!= O_constant
2115 || imm_expr
->X_add_number
< 0
2116 || imm_expr
->X_add_number
>= 4)
2118 as_bad (_("bad value for funct2 field, "
2119 "value must be 0...3"));
2123 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2124 imm_expr
->X_op
= O_absent
;
2129 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2134 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2135 || imm_expr
->X_op
!= O_constant
2136 || imm_expr
->X_add_number
!= 0)
2139 imm_expr
->X_op
= O_absent
;
2143 as_fatal (_("internal error: bad argument type %c"), *args
);
2148 error
= _("illegal operands");
2152 /* Restore the character we might have clobbered above. */
2154 *(argsStart
- 1) = save_c
;
2160 md_assemble (char *str
)
2162 struct riscv_cl_insn insn
;
2163 expressionS imm_expr
;
2164 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2166 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2170 as_bad ("%s `%s'", error
, str
);
2174 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2175 macro (&insn
, &imm_expr
, &imm_reloc
);
2177 append_insn (&insn
, &imm_expr
, imm_reloc
);
2181 md_atof (int type
, char *litP
, int *sizeP
)
2183 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2187 md_number_to_chars (char *buf
, valueT val
, int n
)
2189 number_to_chars_littleendian (buf
, val
, n
);
2192 const char *md_shortopts
= "O::g::G:";
2196 OPTION_MARCH
= OPTION_MD_BASE
,
2205 struct option md_longopts
[] =
2207 {"march", required_argument
, NULL
, OPTION_MARCH
},
2208 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2209 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2210 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2211 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2212 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2213 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2215 {NULL
, no_argument
, NULL
, 0}
2217 size_t md_longopts_size
= sizeof (md_longopts
);
2220 FLOAT_ABI_DEFAULT
= -1,
2226 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2229 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2231 abi_xlen
= new_xlen
;
2232 float_abi
= new_float_abi
;
2237 md_parse_option (int c
, const char *arg
)
2242 riscv_set_arch (arg
);
2246 riscv_opts
.pic
= FALSE
;
2250 riscv_opts
.pic
= TRUE
;
2254 if (strcmp (arg
, "ilp32") == 0)
2255 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2256 else if (strcmp (arg
, "ilp32e") == 0)
2257 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2258 else if (strcmp (arg
, "ilp32f") == 0)
2259 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2260 else if (strcmp (arg
, "ilp32d") == 0)
2261 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2262 else if (strcmp (arg
, "ilp32q") == 0)
2263 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2264 else if (strcmp (arg
, "lp64") == 0)
2265 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2266 else if (strcmp (arg
, "lp64f") == 0)
2267 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2268 else if (strcmp (arg
, "lp64d") == 0)
2269 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2270 else if (strcmp (arg
, "lp64q") == 0)
2271 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2277 riscv_opts
.relax
= TRUE
;
2280 case OPTION_NO_RELAX
:
2281 riscv_opts
.relax
= FALSE
;
2292 riscv_after_parse_args (void)
2296 if (strcmp (default_arch
, "riscv32") == 0)
2298 else if (strcmp (default_arch
, "riscv64") == 0)
2301 as_bad ("unknown default architecture `%s'", default_arch
);
2304 if (riscv_subsets
== NULL
)
2305 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2307 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2308 riscv_set_rvc (FALSE
);
2309 if (riscv_subset_supports (0, "c"))
2310 riscv_set_rvc (TRUE
);
2312 riscv_add_subset ("c");
2314 /* Enable RVE if specified by the -march option. */
2315 riscv_set_rve (FALSE
);
2316 if (riscv_subset_supports (0, "e"))
2317 riscv_set_rve (TRUE
);
2319 /* Infer ABI from ISA if not specified on command line. */
2322 else if (abi_xlen
> xlen
)
2323 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2324 else if (abi_xlen
< xlen
)
2325 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2327 if (float_abi
== FLOAT_ABI_DEFAULT
)
2329 struct riscv_subset
*subset
;
2331 /* Assume soft-float unless D extension is present. */
2332 float_abi
= FLOAT_ABI_SOFT
;
2334 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
2336 if (strcasecmp (subset
->name
, "D") == 0)
2337 float_abi
= FLOAT_ABI_DOUBLE
;
2338 if (strcasecmp (subset
->name
, "Q") == 0)
2339 float_abi
= FLOAT_ABI_QUAD
;
2344 elf_flags
|= EF_RISCV_RVE
;
2346 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2347 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2351 md_pcrel_from (fixS
*fixP
)
2353 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2356 /* Apply a fixup to the object file. */
2359 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2361 unsigned int subtype
;
2362 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2363 bfd_boolean relaxable
= FALSE
;
2367 /* Remember value for tc_gen_reloc. */
2368 fixP
->fx_addnumber
= *valP
;
2370 switch (fixP
->fx_r_type
)
2372 case BFD_RELOC_RISCV_HI20
:
2373 case BFD_RELOC_RISCV_LO12_I
:
2374 case BFD_RELOC_RISCV_LO12_S
:
2375 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2376 | bfd_getl32 (buf
), buf
);
2377 if (fixP
->fx_addsy
== NULL
)
2378 fixP
->fx_done
= TRUE
;
2382 case BFD_RELOC_RISCV_GOT_HI20
:
2383 case BFD_RELOC_RISCV_ADD8
:
2384 case BFD_RELOC_RISCV_ADD16
:
2385 case BFD_RELOC_RISCV_ADD32
:
2386 case BFD_RELOC_RISCV_ADD64
:
2387 case BFD_RELOC_RISCV_SUB6
:
2388 case BFD_RELOC_RISCV_SUB8
:
2389 case BFD_RELOC_RISCV_SUB16
:
2390 case BFD_RELOC_RISCV_SUB32
:
2391 case BFD_RELOC_RISCV_SUB64
:
2392 case BFD_RELOC_RISCV_RELAX
:
2395 case BFD_RELOC_RISCV_TPREL_HI20
:
2396 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2397 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2398 case BFD_RELOC_RISCV_TPREL_ADD
:
2402 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2403 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2404 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2405 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2406 if (fixP
->fx_addsy
!= NULL
)
2407 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2409 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2410 _("TLS relocation against a constant"));
2414 /* Use pc-relative relocation for FDE initial location.
2415 The symbol address in .eh_frame may be adjusted in
2416 _bfd_elf_discard_section_eh_frame, and the content of
2417 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2418 Therefore, we cannot insert a relocation whose addend symbol is
2419 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2420 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2421 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2422 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2423 && S_GET_VALUE (fixP
->fx_subsy
)
2424 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2426 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2427 fixP
->fx_subsy
= NULL
;
2434 case BFD_RELOC_RISCV_CFA
:
2435 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2437 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2438 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2439 fixP
->fx_next
->fx_subsy
= NULL
;
2440 fixP
->fx_next
->fx_offset
= 0;
2441 fixP
->fx_subsy
= NULL
;
2443 switch (fixP
->fx_r_type
)
2446 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2447 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2451 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2452 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2456 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2457 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2461 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2462 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2465 case BFD_RELOC_RISCV_CFA
:
2466 /* Load the byte to get the subtype. */
2467 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2468 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2471 case DW_CFA_advance_loc1
:
2472 fixP
->fx_where
= loc
+ 1;
2473 fixP
->fx_next
->fx_where
= loc
+ 1;
2474 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2475 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2478 case DW_CFA_advance_loc2
:
2480 fixP
->fx_next
->fx_size
= 2;
2481 fixP
->fx_where
= loc
+ 1;
2482 fixP
->fx_next
->fx_where
= loc
+ 1;
2483 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2484 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2487 case DW_CFA_advance_loc4
:
2489 fixP
->fx_next
->fx_size
= 4;
2490 fixP
->fx_where
= loc
;
2491 fixP
->fx_next
->fx_where
= loc
;
2492 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2493 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2497 if (subtype
< 0x80 && (subtype
& 0x40))
2499 /* DW_CFA_advance_loc */
2500 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2501 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2502 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2503 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2506 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2512 /* This case is unreachable. */
2519 /* If we are deleting this reloc entry, we must fill in the
2520 value now. This can happen if we have a .word which is not
2521 resolved when it appears but is later defined. */
2522 if (fixP
->fx_addsy
== NULL
)
2524 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2525 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2530 case BFD_RELOC_RISCV_JMP
:
2533 /* Fill in a tentative value to improve objdump readability. */
2534 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2535 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2536 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2540 case BFD_RELOC_12_PCREL
:
2543 /* Fill in a tentative value to improve objdump readability. */
2544 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2545 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2546 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2550 case BFD_RELOC_RISCV_RVC_BRANCH
:
2553 /* Fill in a tentative value to improve objdump readability. */
2554 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2555 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2556 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2560 case BFD_RELOC_RISCV_RVC_JUMP
:
2563 /* Fill in a tentative value to improve objdump readability. */
2564 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2565 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2566 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2570 case BFD_RELOC_RISCV_CALL
:
2571 case BFD_RELOC_RISCV_CALL_PLT
:
2575 case BFD_RELOC_RISCV_PCREL_HI20
:
2576 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2577 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2578 relaxable
= riscv_opts
.relax
;
2581 case BFD_RELOC_RISCV_ALIGN
:
2585 /* We ignore generic BFD relocations we don't know about. */
2586 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2587 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2590 if (fixP
->fx_subsy
!= NULL
)
2591 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2592 _("unsupported symbol subtraction"));
2594 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2595 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2597 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2598 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2599 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2603 /* Because the value of .cfi_remember_state may changed after relaxation,
2604 we insert a fix to relocate it again in link-time. */
2607 riscv_pre_output_hook (void)
2609 const frchainS
*frch
;
2612 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2613 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2617 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2619 if (frag
->fr_type
== rs_cfa
)
2622 expressionS
*symval
;
2624 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2625 exp
.X_op
= O_subtract
;
2626 exp
.X_add_symbol
= symval
->X_add_symbol
;
2627 exp
.X_add_number
= 0;
2628 exp
.X_op_symbol
= symval
->X_op_symbol
;
2630 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2631 BFD_RELOC_RISCV_CFA
);
2638 /* This structure is used to hold a stack of .option values. */
2640 struct riscv_option_stack
2642 struct riscv_option_stack
*next
;
2643 struct riscv_set_options options
;
2646 static struct riscv_option_stack
*riscv_opts_stack
;
2648 /* Handle the .option pseudo-op. */
2651 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2653 char *name
= input_line_pointer
, ch
;
2655 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2656 ++input_line_pointer
;
2657 ch
= *input_line_pointer
;
2658 *input_line_pointer
= '\0';
2660 if (strcmp (name
, "rvc") == 0)
2661 riscv_set_rvc (TRUE
);
2662 else if (strcmp (name
, "norvc") == 0)
2663 riscv_set_rvc (FALSE
);
2664 else if (strcmp (name
, "pic") == 0)
2665 riscv_opts
.pic
= TRUE
;
2666 else if (strcmp (name
, "nopic") == 0)
2667 riscv_opts
.pic
= FALSE
;
2668 else if (strcmp (name
, "relax") == 0)
2669 riscv_opts
.relax
= TRUE
;
2670 else if (strcmp (name
, "norelax") == 0)
2671 riscv_opts
.relax
= FALSE
;
2672 else if (strcmp (name
, "push") == 0)
2674 struct riscv_option_stack
*s
;
2676 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2677 s
->next
= riscv_opts_stack
;
2678 s
->options
= riscv_opts
;
2679 riscv_opts_stack
= s
;
2681 else if (strcmp (name
, "pop") == 0)
2683 struct riscv_option_stack
*s
;
2685 s
= riscv_opts_stack
;
2687 as_bad (_(".option pop with no .option push"));
2690 riscv_opts
= s
->options
;
2691 riscv_opts_stack
= s
->next
;
2697 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2699 *input_line_pointer
= ch
;
2700 demand_empty_rest_of_line ();
2703 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2704 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2705 use in DWARF debug information. */
2708 s_dtprel (int bytes
)
2715 if (ex
.X_op
!= O_symbol
)
2717 as_bad (_("Unsupported use of %s"), (bytes
== 8
2720 ignore_rest_of_line ();
2723 p
= frag_more (bytes
);
2724 md_number_to_chars (p
, 0, bytes
);
2725 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2727 ? BFD_RELOC_RISCV_TLS_DTPREL64
2728 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2730 demand_empty_rest_of_line ();
2733 /* Handle the .bss pseudo-op. */
2736 s_bss (int ignore ATTRIBUTE_UNUSED
)
2738 subseg_set (bss_section
, 0);
2739 demand_empty_rest_of_line ();
2743 riscv_make_nops (char *buf
, bfd_vma bytes
)
2747 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2748 means we are not within a valid instruction sequence. It is thus safe
2749 to use a zero byte, even though that is not a valid instruction. */
2753 /* Use at most one 2-byte NOP. */
2754 if ((bytes
- i
) % 4 == 2)
2756 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2760 /* Fill the remainder with 4-byte NOPs. */
2761 for ( ; i
< bytes
; i
+= 4)
2762 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2765 /* Called from md_do_align. Used to create an alignment frag in a
2766 code section by emitting a worst-case NOP sequence that the linker
2767 will later relax to the correct number of NOPs. We can't compute
2768 the correct alignment now because of other linker relaxations. */
2771 riscv_frag_align_code (int n
)
2773 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2774 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2775 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2779 /* If we are moving to a smaller alignment than the instruction size, then no
2780 alignment is required. */
2781 if (bytes
<= insn_alignment
)
2784 /* When not relaxing, riscv_handle_align handles code alignment. */
2785 if (!riscv_opts
.relax
)
2788 nops
= frag_more (worst_case_bytes
);
2790 ex
.X_op
= O_constant
;
2791 ex
.X_add_number
= worst_case_bytes
;
2793 riscv_make_nops (nops
, worst_case_bytes
);
2795 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2796 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2801 /* Implement HANDLE_ALIGN. */
2804 riscv_handle_align (fragS
*fragP
)
2806 switch (fragP
->fr_type
)
2809 /* When relaxing, riscv_frag_align_code handles code alignment. */
2810 if (!riscv_opts
.relax
)
2812 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2813 - fragP
->fr_address
- fragP
->fr_fix
);
2814 /* We have 4 byte uncompressed nops. */
2815 bfd_signed_vma size
= 4;
2816 bfd_signed_vma excess
= bytes
% size
;
2817 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2822 /* Insert zeros or compressed nops to get 4 byte alignment. */
2825 riscv_make_nops (p
, excess
);
2826 fragP
->fr_fix
+= excess
;
2830 /* Insert variable number of 4 byte uncompressed nops. */
2831 riscv_make_nops (p
, size
);
2832 fragP
->fr_var
= size
;
2842 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2844 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2847 /* Translate internal representation of relocation info to BFD target
2851 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2853 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2855 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2856 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2857 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2858 reloc
->addend
= fixp
->fx_addnumber
;
2860 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2861 if (reloc
->howto
== NULL
)
2863 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2864 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2866 /* We don't have R_RISCV_8/16, but for this special case,
2867 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2871 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2872 _("cannot represent %s relocation in object file"),
2873 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2881 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2883 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2885 offsetT old_var
= fragp
->fr_var
;
2886 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2887 return fragp
->fr_var
- old_var
;
2893 /* Expand far branches to multi-instruction sequences. */
2896 md_convert_frag_branch (fragS
*fragp
)
2904 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2906 exp
.X_op
= O_symbol
;
2907 exp
.X_add_symbol
= fragp
->fr_symbol
;
2908 exp
.X_add_number
= fragp
->fr_offset
;
2910 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2912 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2914 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2918 /* Expand the RVC branch into a RISC-V one. */
2919 insn
= bfd_getl16 (buf
);
2920 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2921 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2923 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2924 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2925 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2926 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2927 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2928 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2931 bfd_putl32 (insn
, buf
);
2935 /* Invert the branch condition. Branch over the jump. */
2936 insn
= bfd_getl16 (buf
);
2937 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2938 insn
|= ENCODE_RVC_B_IMM (6);
2939 bfd_putl16 (insn
, buf
);
2944 /* Just keep the RVC branch. */
2945 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2946 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2947 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2948 2, &exp
, FALSE
, reloc
);
2957 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2960 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2962 /* Invert the branch condition. Branch over the jump. */
2963 insn
= bfd_getl32 (buf
);
2964 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2965 insn
|= ENCODE_SBTYPE_IMM (8);
2966 md_number_to_chars ((char *) buf
, insn
, 4);
2970 /* Jump to the target. */
2971 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2972 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2973 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2978 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2979 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2980 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2981 4, &exp
, FALSE
, reloc
);
2990 fixp
->fx_file
= fragp
->fr_file
;
2991 fixp
->fx_line
= fragp
->fr_line
;
2993 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2994 + fragp
->fr_fix
+ fragp
->fr_var
);
2996 fragp
->fr_fix
+= fragp
->fr_var
;
2999 /* Relax a machine dependent frag. This returns the amount by which
3000 the current size of the frag should change. */
3003 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3006 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3007 md_convert_frag_branch (fragp
);
3011 md_show_usage (FILE *stream
)
3013 fprintf (stream
, _("\
3015 -fpic generate position-independent code\n\
3016 -fno-pic don't generate position-independent code (default)\n\
3017 -march=ISA set the RISC-V architecture\n\
3018 -mabi=ABI set the RISC-V ABI\n\
3019 -mrelax enable relax (default)\n\
3020 -mno-relax disable relax\n\
3024 /* Standard calling conventions leave the CFA at SP on entry. */
3026 riscv_cfi_frame_initial_instructions (void)
3028 cfi_add_CFA_def_cfa_register (X_SP
);
3032 tc_riscv_regname_to_dw2regnum (char *regname
)
3036 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3039 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3042 as_bad (_("unknown register `%s'"), regname
);
3047 riscv_elf_final_processing (void)
3049 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3052 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3053 since these directives break relaxation when used with symbol deltas. */
3056 s_riscv_leb128 (int sign
)
3059 char *save_in
= input_line_pointer
;
3062 if (exp
.X_op
!= O_constant
)
3063 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3064 demand_empty_rest_of_line ();
3066 input_line_pointer
= save_in
;
3067 return s_leb128 (sign
);
3070 /* Parse the .insn directive. */
3073 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3075 char *str
= input_line_pointer
;
3076 struct riscv_cl_insn insn
;
3077 expressionS imm_expr
;
3078 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3081 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3082 ++input_line_pointer
;
3084 save_c
= *input_line_pointer
;
3085 *input_line_pointer
= '\0';
3087 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3088 &imm_reloc
, insn_type_hash
);
3092 as_bad ("%s `%s'", error
, str
);
3096 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3097 append_insn (&insn
, &imm_expr
, imm_reloc
);
3100 *input_line_pointer
= save_c
;
3101 demand_empty_rest_of_line ();
3104 /* Pseudo-op table. */
3106 static const pseudo_typeS riscv_pseudo_table
[] =
3108 /* RISC-V-specific pseudo-ops. */
3109 {"option", s_riscv_option
, 0},
3113 {"dtprelword", s_dtprel
, 4},
3114 {"dtpreldword", s_dtprel
, 8},
3116 {"uleb128", s_riscv_leb128
, 0},
3117 {"sleb128", s_riscv_leb128
, 1},
3118 {"insn", s_riscv_insn
, 0},
3124 riscv_pop_insert (void)
3126 extern void pop_insert (const pseudo_typeS
*);
3128 pop_insert (riscv_pseudo_table
);