1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int relax
; /* Emit relocs the linker is allowed to relax. */
81 static struct riscv_set_options riscv_opts
=
89 riscv_set_rvc (bfd_boolean rvc_value
)
92 elf_flags
|= EF_RISCV_RVC
;
94 riscv_opts
.rvc
= rvc_value
;
101 struct riscv_subset
*next
;
104 static struct riscv_subset
*riscv_subsets
;
107 riscv_subset_supports (const char *feature
)
109 struct riscv_subset
*s
;
111 unsigned xlen_required
= strtoul (feature
, &p
, 10);
113 if (xlen_required
&& xlen
!= xlen_required
)
116 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
117 if (strcasecmp (s
->name
, p
) == 0)
124 riscv_clear_subsets (void)
126 while (riscv_subsets
!= NULL
)
128 struct riscv_subset
*next
= riscv_subsets
->next
;
129 free ((void *) riscv_subsets
->name
);
130 free (riscv_subsets
);
131 riscv_subsets
= next
;
136 riscv_add_subset (const char *subset
)
138 struct riscv_subset
*s
= xmalloc (sizeof *s
);
140 s
->name
= xstrdup (subset
);
141 s
->next
= riscv_subsets
;
145 /* Set which ISA and extensions are available. */
148 riscv_set_arch (const char *s
)
150 const char *all_subsets
= "imafdqc";
151 char *extension
= NULL
;
154 riscv_clear_subsets();
156 if (strncmp (p
, "rv32", 4) == 0)
161 else if (strncmp (p
, "rv64", 4) == 0)
167 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
176 for ( ; *all_subsets
!= 'q'; all_subsets
++)
178 const char subset
[] = {*all_subsets
, '\0'};
179 riscv_add_subset (subset
);
184 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s
);
191 char *subset
= xstrdup (p
);
194 while (*++q
!= '\0' && *q
!= '_')
199 as_fatal ("-march=%s: only one non-standard extension is supported"
200 " (found `%s' and `%s')", s
, extension
, subset
);
202 riscv_add_subset (subset
);
203 p
+= strlen (subset
);
207 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
209 const char subset
[] = {*p
, 0};
210 riscv_add_subset (subset
);
215 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
221 /* Handle of the OPCODE hash table. */
222 static struct hash_control
*op_hash
= NULL
;
224 /* This array holds the chars that always start a comment. If the
225 pre-processor is disabled, these aren't very useful */
226 const char comment_chars
[] = "#";
228 /* This array holds the chars that only start a comment at the beginning of
229 a line. If the line seems to have the form '# 123 filename'
230 .line and .file directives will appear in the pre-processed output */
231 /* Note that input_file.c hand checks for '#' at the beginning of the
232 first line of the input file. This is because the compiler outputs
233 #NO_APP at the beginning of its output. */
234 /* Also note that C style comments are always supported. */
235 const char line_comment_chars
[] = "#";
237 /* This array holds machine specific line separator characters. */
238 const char line_separator_chars
[] = ";";
240 /* Chars that can be used to separate mant from exp in floating point nums */
241 const char EXP_CHARS
[] = "eE";
243 /* Chars that mean this number is a floating point constant */
246 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
248 /* Macros for encoding relaxation state for RVC branches and far jumps. */
249 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
252 | ((uncond) ? 1 : 0) \
255 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
256 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
257 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
258 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
260 /* Is the given value a sign-extended 32-bit value? */
261 #define IS_SEXT_32BIT_NUM(x) \
262 (((x) &~ (offsetT) 0x7fffffff) == 0 \
263 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
265 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
266 #define IS_ZEXT_32BIT_NUM(x) \
267 (((x) &~ (offsetT) 0xffffffff) == 0 \
268 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
270 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
271 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
272 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
273 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
275 /* Determine if an instruction matches an opcode. */
276 #define OPCODE_MATCHES(OPCODE, OP) \
277 (((OPCODE) & MASK_##OP) == MATCH_##OP)
279 static char *expr_end
;
281 /* The default target format to use. */
284 riscv_target_format (void)
286 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
289 /* Return the length of instruction INSN. */
291 static inline unsigned int
292 insn_length (const struct riscv_cl_insn
*insn
)
294 return riscv_insn_length (insn
->insn_opcode
);
297 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
300 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
303 insn
->insn_opcode
= mo
->match
;
309 /* Install INSN at the location specified by its "frag" and "where" fields. */
312 install_insn (const struct riscv_cl_insn
*insn
)
314 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
315 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
318 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
319 and install the opcode in the new location. */
322 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
326 if (insn
->fixp
!= NULL
)
328 insn
->fixp
->fx_frag
= frag
;
329 insn
->fixp
->fx_where
= where
;
334 /* Add INSN to the end of the output. */
337 add_fixed_insn (struct riscv_cl_insn
*insn
)
339 char *f
= frag_more (insn_length (insn
));
340 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
344 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
345 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
347 frag_grow (max_chars
);
348 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
349 frag_var (rs_machine_dependent
, max_chars
, var
,
350 subtype
, symbol
, offset
, NULL
);
353 /* Compute the length of a branch sequence, and adjust the stored length
354 accordingly. If FRAGP is NULL, the worst-case length is returned. */
357 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
359 int jump
, rvc
, length
= 8;
364 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
365 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
366 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
368 /* Assume jumps are in range; the linker will catch any that aren't. */
369 length
= jump
? 4 : 8;
371 if (fragp
->fr_symbol
!= NULL
372 && S_IS_DEFINED (fragp
->fr_symbol
)
373 && !S_IS_WEAK (fragp
->fr_symbol
)
374 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
376 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
377 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
378 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
380 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
382 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
384 else if (!jump
&& rvc
)
389 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
408 static struct hash_control
*reg_names_hash
= NULL
;
410 #define ENCODE_REG_HASH(cls, n) \
411 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
412 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
413 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
416 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
418 void *hash
= ENCODE_REG_HASH (class, n
);
419 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
422 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
426 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
430 for (i
= 0; i
< n
; i
++)
431 hash_reg_name (class, names
[i
], i
);
435 reg_lookup_internal (const char *s
, enum reg_class
class)
437 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
439 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
441 return DECODE_REG_NUM (r
);
445 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
451 /* Find end of name. */
453 if (is_name_beginner (*e
))
455 while (is_part_of_name (*e
))
458 /* Terminate name. */
462 /* Look for the register. Advance to next token if one was recognized. */
463 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
473 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
475 const char *p
= strchr (*s
, ',');
476 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
478 for (i
= 0; i
< size
; i
++)
479 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
489 /* For consistency checking, verify that all bits are specified either
490 by the match/mask part of the instruction definition, or by the
493 validate_riscv_insn (const struct riscv_opcode
*opc
)
495 const char *p
= opc
->args
;
497 insn_t used_bits
= opc
->mask
;
498 int insn_width
= 8 * riscv_insn_length (opc
->match
);
499 insn_t required_bits
= ~0ULL >> (64 - insn_width
);
501 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
503 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
504 opc
->name
, opc
->args
);
508 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
515 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
516 case 'c': break; /* RS1, constrained to equal sp */
517 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
518 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
519 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
520 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
521 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
522 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
523 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
524 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
525 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
526 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
527 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
528 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
529 case 'w': break; /* RS1S, constrained to equal RD */
530 case 'x': break; /* RS2S, constrained to equal RD */
531 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
532 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
533 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
534 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
535 case 'U': break; /* RS1, constrained to equal RD */
536 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
537 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
538 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
539 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
540 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
542 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
543 c
, opc
->name
, opc
->args
);
550 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
551 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
553 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
554 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
555 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
557 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
558 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
559 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
560 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
561 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
562 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
563 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
564 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
565 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
566 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
568 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
569 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
570 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
571 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
572 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
578 as_bad (_("internal: bad RISC-V opcode "
579 "(unknown operand type `%c'): %s %s"),
580 c
, opc
->name
, opc
->args
);
584 if (used_bits
!= required_bits
)
586 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
587 ~(unsigned long)(used_bits
& required_bits
),
588 opc
->name
, opc
->args
);
594 struct percent_op_match
597 bfd_reloc_code_real_type reloc
;
600 /* This function is called once, at assembler startup time. It should set up
601 all the tables, etc. that the MD part of the assembler will need. */
607 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
609 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
610 as_warn (_("Could not set architecture and machine"));
612 op_hash
= hash_new ();
614 while (riscv_opcodes
[i
].name
)
616 const char *name
= riscv_opcodes
[i
].name
;
617 const char *hash_error
=
618 hash_insert (op_hash
, name
, (void *) &riscv_opcodes
[i
]);
622 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
623 riscv_opcodes
[i
].name
, hash_error
);
624 /* Probably a memory allocation problem? Give up now. */
625 as_fatal (_("Broken assembler. No assembly attempted."));
630 if (riscv_opcodes
[i
].pinfo
!= INSN_MACRO
)
632 if (!validate_riscv_insn (&riscv_opcodes
[i
]))
633 as_fatal (_("Broken assembler. No assembly attempted."));
637 while (riscv_opcodes
[i
].name
&& !strcmp (riscv_opcodes
[i
].name
, name
));
640 reg_names_hash
= hash_new ();
641 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
642 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
643 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
644 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
646 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
647 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
648 #include "opcode/riscv-opc.h"
651 /* Set the default alignment for the text section. */
652 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
656 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
663 case BFD_RELOC_RISCV_HI20
:
664 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
666 case BFD_RELOC_RISCV_LO12_S
:
667 return ENCODE_STYPE_IMM (value
);
669 case BFD_RELOC_RISCV_LO12_I
:
670 return ENCODE_ITYPE_IMM (value
);
677 /* Output an instruction. IP is the instruction information.
678 ADDRESS_EXPR is an operand of the instruction to be used with
682 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
683 bfd_reloc_code_real_type reloc_type
)
685 dwarf2_emit_insn (0);
687 if (reloc_type
!= BFD_RELOC_UNUSED
)
689 reloc_howto_type
*howto
;
691 gas_assert (address_expr
);
692 if (reloc_type
== BFD_RELOC_12_PCREL
693 || reloc_type
== BFD_RELOC_RISCV_JMP
)
695 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
696 int best_case
= riscv_insn_length (ip
->insn_opcode
);
697 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
698 add_relaxed_insn (ip
, worst_case
, best_case
,
699 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
700 address_expr
->X_add_symbol
,
701 address_expr
->X_add_number
);
706 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
708 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
710 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
711 bfd_get_reloc_size (howto
),
712 address_expr
, FALSE
, reloc_type
);
714 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
721 /* We need to start a new frag after any instruction that can be
722 optimized away or compressed by the linker during relaxation, to prevent
723 the assembler from computing static offsets across such an instruction.
724 This is necessary to get correct EH info. */
725 if (reloc_type
== BFD_RELOC_RISCV_CALL
726 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
727 || reloc_type
== BFD_RELOC_RISCV_HI20
728 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
729 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
730 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
732 frag_wane (frag_now
);
737 /* Build an instruction created by a macro expansion. This is passed
738 a pointer to the count of instructions created so far, an
739 expression, the name of the instruction to build, an operand format
740 string, and corresponding arguments. */
743 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
745 const struct riscv_opcode
*mo
;
746 struct riscv_cl_insn insn
;
747 bfd_reloc_code_real_type r
;
750 va_start (args
, fmt
);
752 r
= BFD_RELOC_UNUSED
;
753 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
756 /* Find a non-RVC variant of the instruction. append_insn will compress
758 while (riscv_insn_length (mo
->match
) < 4)
760 gas_assert (strcmp (name
, mo
->name
) == 0);
762 create_insn (&insn
, mo
);
768 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
772 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
776 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
780 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
786 gas_assert (ep
!= NULL
);
787 r
= va_arg (args
, int);
795 as_fatal (_("internal error: invalid macro"));
800 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
802 append_insn (&insn
, ep
, r
);
805 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
808 normalize_constant_expr (expressionS
*ex
)
812 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
813 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
814 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
818 /* Fail if an expression is not a constant. */
821 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
)
823 if (ex
->X_op
== O_big
)
824 as_bad (_("unsupported large constant"));
825 else if (ex
->X_op
!= O_constant
)
826 as_bad (_("Instruction %s requires absolute expression"),
828 normalize_constant_expr (ex
);
832 make_internal_label (void)
834 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
835 (valueT
) frag_now_fix (), frag_now
);
838 /* Load an entry from the GOT. */
840 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
841 const char *lo_insn
, const char *lo_pattern
,
842 bfd_reloc_code_real_type hi_reloc
,
843 bfd_reloc_code_real_type lo_reloc
)
847 ep2
.X_add_symbol
= make_internal_label ();
848 ep2
.X_add_number
= 0;
850 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
851 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
855 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
856 bfd_reloc_code_real_type hi_reloc
,
857 bfd_reloc_code_real_type lo_reloc
)
859 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
863 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
864 bfd_reloc_code_real_type hi_reloc
,
865 bfd_reloc_code_real_type lo_reloc
)
867 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
870 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
872 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
873 bfd_reloc_code_real_type reloc
)
875 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
876 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
879 /* Load an integer constant into a register. */
882 load_const (int reg
, expressionS
*ep
)
884 int shift
= RISCV_IMM_BITS
;
885 expressionS upper
= *ep
, lower
= *ep
;
886 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
887 upper
.X_add_number
-= lower
.X_add_number
;
889 if (ep
->X_op
!= O_constant
)
891 as_bad (_("unsupported large constant"));
895 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
897 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
898 while (((upper
.X_add_number
>> shift
) & 1) == 0)
901 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
902 load_const (reg
, &upper
);
904 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
905 if (lower
.X_add_number
!= 0)
906 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
910 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
913 if (upper
.X_add_number
!= 0)
915 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
919 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
920 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
921 BFD_RELOC_RISCV_LO12_I
);
925 /* Expand RISC-V assembly macros into one or more instructions. */
927 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
928 bfd_reloc_code_real_type
*imm_reloc
)
930 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
931 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
932 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
933 int mask
= ip
->insn_mo
->mask
;
938 load_const (rd
, imm_expr
);
943 /* Load the address of a symbol into a register. */
944 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
945 as_bad (_("offset too large"));
947 if (imm_expr
->X_op
== O_constant
)
948 load_const (rd
, imm_expr
);
949 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
950 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
951 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
952 else /* Local PIC symbol, or any non-PIC symbol */
953 pcrel_load (rd
, rd
, imm_expr
, "addi",
954 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
958 pcrel_load (rd
, rd
, imm_expr
, "addi",
959 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
963 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
964 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
968 pcrel_load (rd
, rd
, imm_expr
, "lb",
969 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
973 pcrel_load (rd
, rd
, imm_expr
, "lbu",
974 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
978 pcrel_load (rd
, rd
, imm_expr
, "lh",
979 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
983 pcrel_load (rd
, rd
, imm_expr
, "lhu",
984 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
988 pcrel_load (rd
, rd
, imm_expr
, "lw",
989 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
993 pcrel_load (rd
, rd
, imm_expr
, "lwu",
994 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
998 pcrel_load (rd
, rd
, imm_expr
, "ld",
999 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1003 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1004 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1008 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1009 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1013 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1014 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1018 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1019 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1023 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1024 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1028 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1029 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1033 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1034 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1038 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1039 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1043 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1047 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1052 static const struct percent_op_match percent_op_utype
[] =
1054 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1055 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1056 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1057 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1058 {"%hi", BFD_RELOC_RISCV_HI20
},
1062 static const struct percent_op_match percent_op_itype
[] =
1064 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1065 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1066 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1070 static const struct percent_op_match percent_op_stype
[] =
1072 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1073 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1074 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1078 static const struct percent_op_match percent_op_rtype
[] =
1080 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1084 /* Return true if *STR points to a relocation operator. When returning true,
1085 move *STR over the operator and store its relocation code in *RELOC.
1086 Leave both *STR and *RELOC alone when returning false. */
1089 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1090 const struct percent_op_match
*percent_op
)
1092 for ( ; percent_op
->str
; percent_op
++)
1093 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1095 int len
= strlen (percent_op
->str
);
1097 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1100 *str
+= strlen (percent_op
->str
);
1101 *reloc
= percent_op
->reloc
;
1103 /* Check whether the output BFD supports this relocation.
1104 If not, issue an error and fall back on something safe. */
1105 if (*reloc
!= BFD_RELOC_UNUSED
1106 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1108 as_bad ("relocation %s isn't supported by the current ABI",
1110 *reloc
= BFD_RELOC_UNUSED
;
1118 my_getExpression (expressionS
*ep
, char *str
)
1122 save_in
= input_line_pointer
;
1123 input_line_pointer
= str
;
1125 expr_end
= input_line_pointer
;
1126 input_line_pointer
= save_in
;
1129 /* Parse string STR as a 16-bit relocatable operand. Store the
1130 expression in *EP and the relocation, if any, in RELOC.
1131 Return the number of relocation operators used (0 or 1).
1133 On exit, EXPR_END points to the first character after the expression. */
1136 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1137 char *str
, const struct percent_op_match
*percent_op
)
1140 unsigned crux_depth
, str_depth
, regno
;
1143 /* First, check for integer registers. */
1144 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1146 ep
->X_op
= O_register
;
1147 ep
->X_add_number
= regno
;
1151 /* Search for the start of the main expression.
1152 End the loop with CRUX pointing to the start
1153 of the main expression and with CRUX_DEPTH containing the number
1154 of open brackets at that point. */
1161 crux_depth
= str_depth
;
1163 /* Skip over whitespace and brackets, keeping count of the number
1165 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1171 && parse_relocation (&str
, reloc
, percent_op
));
1173 my_getExpression (ep
, crux
);
1176 /* Match every open bracket. */
1177 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1182 as_bad ("unclosed '('");
1189 /* Detect and handle implicitly zero load-store offsets. For example,
1190 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1191 an implicit offset was detected. */
1194 riscv_handle_implicit_zero_offset (expressionS
*expr
, const char *s
)
1196 /* Check whether there is only a single bracketed expression left.
1197 If so, it must be the base register and the constant must be zero. */
1198 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1200 expr
->X_op
= O_constant
;
1201 expr
->X_add_number
= 0;
1208 /* This routine assembles an instruction into its binary format. As a
1209 side effect, it sets the global variable imm_reloc to the type of
1210 relocation to do if one of the operands is an address expression. */
1213 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1214 bfd_reloc_code_real_type
*imm_reloc
)
1219 struct riscv_opcode
*insn
;
1224 const struct percent_op_match
*p
;
1225 const char *error
= "unrecognized opcode";
1227 /* Parse the name of the instruction. Terminate the string if whitespace
1228 is found so that hash_find only sees the name part of the string. */
1229 for (s
= str
; *s
!= '\0'; ++s
)
1237 insn
= (struct riscv_opcode
*) hash_find (op_hash
, str
);
1240 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1242 if (!riscv_subset_supports (insn
->subset
))
1245 create_insn (ip
, insn
);
1248 imm_expr
->X_op
= O_absent
;
1249 *imm_reloc
= BFD_RELOC_UNUSED
;
1250 p
= percent_op_itype
;
1252 for (args
= insn
->args
;; ++args
)
1254 s
+= strspn (s
, " \t");
1257 case '\0': /* End of args. */
1258 if (insn
->pinfo
!= INSN_MACRO
)
1260 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1262 if (riscv_insn_length (insn
->match
) == 2 && !riscv_opts
.rvc
)
1267 /* Successful assembly. */
1274 case 's': /* RS1 x8-x15 */
1275 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1276 || !(regno
>= 8 && regno
<= 15))
1278 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1280 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1281 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1282 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1285 case 't': /* RS2 x8-x15 */
1286 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1287 || !(regno
>= 8 && regno
<= 15))
1289 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1291 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1292 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1293 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1296 case 'U': /* RS1, constrained to equal RD. */
1297 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1298 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1302 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1304 INSERT_OPERAND (CRS2
, *ip
, regno
);
1306 case 'c': /* RS1, constrained to equal sp. */
1307 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1312 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1313 || imm_expr
->X_op
!= O_constant
1314 || imm_expr
->X_add_number
<= 0
1315 || imm_expr
->X_add_number
>= 64)
1317 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1320 imm_expr
->X_op
= O_absent
;
1323 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1324 || imm_expr
->X_op
!= O_constant
1325 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1326 || imm_expr
->X_add_number
<= 0
1327 || imm_expr
->X_add_number
>= 32)
1329 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1332 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1333 || imm_expr
->X_op
!= O_constant
1334 || imm_expr
->X_add_number
== 0
1335 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1337 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1340 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1341 || imm_expr
->X_op
!= O_constant
1342 || imm_expr
->X_add_number
== 0
1343 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1345 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1348 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1350 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1351 || imm_expr
->X_op
!= O_constant
1352 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1354 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1357 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1359 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1360 || imm_expr
->X_op
!= O_constant
1361 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1363 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1366 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1368 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1369 || imm_expr
->X_op
!= O_constant
1370 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1373 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1376 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1378 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1379 || imm_expr
->X_op
!= O_constant
1380 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1383 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1386 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1387 || imm_expr
->X_op
!= O_constant
1388 /* C.addiw, c.li, and c.andi allow zero immediate.
1389 C.addi allows zero immediate as hint. Otherwise this
1391 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1393 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1396 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1397 || imm_expr
->X_op
!= O_constant
1398 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1399 || imm_expr
->X_add_number
== 0)
1402 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1405 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1406 || imm_expr
->X_op
!= O_constant
1407 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1408 || imm_expr
->X_add_number
== 0)
1411 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1414 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1416 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1417 || imm_expr
->X_op
!= O_constant
1418 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1421 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1424 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1426 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1427 || imm_expr
->X_op
!= O_constant
1428 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1431 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1434 p
= percent_op_utype
;
1435 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1438 if (imm_expr
->X_op
!= O_constant
1439 || imm_expr
->X_add_number
<= 0
1440 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1441 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1442 && (imm_expr
->X_add_number
<
1443 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1445 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1448 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1449 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1450 || ((int32_t)imm_expr
->X_add_number
1451 != imm_expr
->X_add_number
))
1453 imm_expr
->X_add_number
=
1454 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1460 case 'D': /* Floating-point RS2 x8-x15. */
1461 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1462 || !(regno
>= 8 && regno
<= 15))
1464 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1466 case 'T': /* Floating-point RS2. */
1467 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1469 INSERT_OPERAND (CRS2
, *ip
, regno
);
1472 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1491 case '<': /* Shift amount, 0 - 31. */
1492 my_getExpression (imm_expr
, s
);
1493 check_absolute_expr (ip
, imm_expr
);
1494 if ((unsigned long) imm_expr
->X_add_number
> 31)
1495 as_bad (_("Improper shift amount (%lu)"),
1496 (unsigned long) imm_expr
->X_add_number
);
1497 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1498 imm_expr
->X_op
= O_absent
;
1502 case '>': /* Shift amount, 0 - (XLEN-1). */
1503 my_getExpression (imm_expr
, s
);
1504 check_absolute_expr (ip
, imm_expr
);
1505 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1506 as_bad (_("Improper shift amount (%lu)"),
1507 (unsigned long) imm_expr
->X_add_number
);
1508 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1509 imm_expr
->X_op
= O_absent
;
1513 case 'Z': /* CSRRxI immediate. */
1514 my_getExpression (imm_expr
, s
);
1515 check_absolute_expr (ip
, imm_expr
);
1516 if ((unsigned long) imm_expr
->X_add_number
> 31)
1517 as_bad (_("Improper CSRxI immediate (%lu)"),
1518 (unsigned long) imm_expr
->X_add_number
);
1519 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1520 imm_expr
->X_op
= O_absent
;
1524 case 'E': /* Control register. */
1525 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1526 INSERT_OPERAND (CSR
, *ip
, regno
);
1529 my_getExpression (imm_expr
, s
);
1530 check_absolute_expr (ip
, imm_expr
);
1531 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1532 as_bad (_("Improper CSR address (%lu)"),
1533 (unsigned long) imm_expr
->X_add_number
);
1534 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1535 imm_expr
->X_op
= O_absent
;
1540 case 'm': /* Rounding mode. */
1541 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1543 INSERT_OPERAND (RM
, *ip
, regno
);
1549 case 'Q': /* Fence predecessor/successor. */
1550 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1554 INSERT_OPERAND (PRED
, *ip
, regno
);
1556 INSERT_OPERAND (SUCC
, *ip
, regno
);
1561 case 'd': /* Destination register. */
1562 case 's': /* Source register. */
1563 case 't': /* Target register. */
1564 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1570 /* Now that we have assembled one operand, we use the args
1571 string to figure out where it goes in the instruction. */
1575 INSERT_OPERAND (RS1
, *ip
, regno
);
1578 INSERT_OPERAND (RD
, *ip
, regno
);
1581 INSERT_OPERAND (RS2
, *ip
, regno
);
1588 case 'D': /* Floating point rd. */
1589 case 'S': /* Floating point rs1. */
1590 case 'T': /* Floating point rs2. */
1591 case 'U': /* Floating point rs1 and rs2. */
1592 case 'R': /* Floating point rs3. */
1593 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1601 INSERT_OPERAND (RD
, *ip
, regno
);
1604 INSERT_OPERAND (RS1
, *ip
, regno
);
1607 INSERT_OPERAND (RS1
, *ip
, regno
);
1610 INSERT_OPERAND (RS2
, *ip
, regno
);
1613 INSERT_OPERAND (RS3
, *ip
, regno
);
1622 my_getExpression (imm_expr
, s
);
1623 if (imm_expr
->X_op
!= O_big
1624 && imm_expr
->X_op
!= O_constant
)
1626 normalize_constant_expr (imm_expr
);
1631 my_getExpression (imm_expr
, s
);
1632 normalize_constant_expr (imm_expr
);
1633 /* The 'A' format specifier must be a symbol. */
1634 if (imm_expr
->X_op
!= O_symbol
)
1636 *imm_reloc
= BFD_RELOC_32
;
1640 case 'j': /* Sign-extended immediate. */
1641 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1642 p
= percent_op_itype
;
1644 case 'q': /* Store displacement. */
1645 p
= percent_op_stype
;
1646 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1648 case 'o': /* Load displacement. */
1649 p
= percent_op_itype
;
1650 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1652 case '0': /* AMO "displacement," which must be zero. */
1653 p
= percent_op_rtype
;
1654 *imm_reloc
= BFD_RELOC_UNUSED
;
1656 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1659 /* If this value won't fit into a 16 bit offset, then go
1660 find a macro that will generate the 32 bit offset
1662 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1664 normalize_constant_expr (imm_expr
);
1665 if (imm_expr
->X_op
!= O_constant
1666 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1667 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1668 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1675 case 'p': /* PC-relative offset. */
1677 *imm_reloc
= BFD_RELOC_12_PCREL
;
1678 my_getExpression (imm_expr
, s
);
1682 case 'u': /* Upper 20 bits. */
1683 p
= percent_op_utype
;
1684 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1685 && imm_expr
->X_op
== O_constant
)
1687 if (imm_expr
->X_add_number
< 0
1688 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1689 as_bad (_("lui expression not in range 0..1048575"));
1691 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1692 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1697 case 'a': /* 20-bit PC-relative offset. */
1699 my_getExpression (imm_expr
, s
);
1701 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1705 my_getExpression (imm_expr
, s
);
1707 if (strcmp (s
, "@plt") == 0)
1709 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1713 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1717 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1718 || imm_expr
->X_op
!= O_constant
1719 || imm_expr
->X_add_number
!= 0)
1722 imm_expr
->X_op
= O_absent
;
1726 as_fatal (_("internal error: bad argument type %c"), *args
);
1731 error
= _("illegal operands");
1735 /* Restore the character we might have clobbered above. */
1737 *(argsStart
- 1) = save_c
;
1743 md_assemble (char *str
)
1745 struct riscv_cl_insn insn
;
1746 expressionS imm_expr
;
1747 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
1749 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
);
1753 as_bad ("%s `%s'", error
, str
);
1757 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1758 macro (&insn
, &imm_expr
, &imm_reloc
);
1760 append_insn (&insn
, &imm_expr
, imm_reloc
);
1764 md_atof (int type
, char *litP
, int *sizeP
)
1766 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
1770 md_number_to_chars (char *buf
, valueT val
, int n
)
1772 number_to_chars_littleendian (buf
, val
, n
);
1775 const char *md_shortopts
= "O::g::G:";
1779 OPTION_MARCH
= OPTION_MD_BASE
,
1786 struct option md_longopts
[] =
1788 {"march", required_argument
, NULL
, OPTION_MARCH
},
1789 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
1790 {"fpic", no_argument
, NULL
, OPTION_PIC
},
1791 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
1792 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1794 {NULL
, no_argument
, NULL
, 0}
1796 size_t md_longopts_size
= sizeof (md_longopts
);
1799 FLOAT_ABI_DEFAULT
= -1,
1805 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
1808 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
)
1810 abi_xlen
= new_xlen
;
1811 float_abi
= new_float_abi
;
1815 md_parse_option (int c
, const char *arg
)
1820 riscv_set_arch (arg
);
1824 riscv_opts
.pic
= FALSE
;
1828 riscv_opts
.pic
= TRUE
;
1832 if (strcmp (arg
, "ilp32") == 0)
1833 riscv_set_abi (32, FLOAT_ABI_SOFT
);
1834 else if (strcmp (arg
, "ilp32f") == 0)
1835 riscv_set_abi (32, FLOAT_ABI_SINGLE
);
1836 else if (strcmp (arg
, "ilp32d") == 0)
1837 riscv_set_abi (32, FLOAT_ABI_DOUBLE
);
1838 else if (strcmp (arg
, "ilp32q") == 0)
1839 riscv_set_abi (32, FLOAT_ABI_QUAD
);
1840 else if (strcmp (arg
, "lp64") == 0)
1841 riscv_set_abi (64, FLOAT_ABI_SOFT
);
1842 else if (strcmp (arg
, "lp64f") == 0)
1843 riscv_set_abi (64, FLOAT_ABI_SINGLE
);
1844 else if (strcmp (arg
, "lp64d") == 0)
1845 riscv_set_abi (64, FLOAT_ABI_DOUBLE
);
1846 else if (strcmp (arg
, "lp64q") == 0)
1847 riscv_set_abi (64, FLOAT_ABI_QUAD
);
1860 riscv_after_parse_args (void)
1864 if (strcmp (default_arch
, "riscv32") == 0)
1866 else if (strcmp (default_arch
, "riscv64") == 0)
1869 as_bad ("unknown default architecture `%s'", default_arch
);
1872 if (riscv_subsets
== NULL
)
1873 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
1875 /* Add the RVC extension, regardless of -march, to support .option rvc. */
1876 riscv_set_rvc (FALSE
);
1877 if (riscv_subset_supports ("c"))
1878 riscv_set_rvc (TRUE
);
1880 riscv_add_subset ("c");
1882 /* Infer ABI from ISA if not specified on command line. */
1885 else if (abi_xlen
> xlen
)
1886 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
1887 else if (abi_xlen
< xlen
)
1888 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
1890 if (float_abi
== FLOAT_ABI_DEFAULT
)
1892 struct riscv_subset
*subset
;
1894 /* Assume soft-float unless D extension is present. */
1895 float_abi
= FLOAT_ABI_SOFT
;
1897 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
1899 if (strcasecmp (subset
->name
, "D") == 0)
1900 float_abi
= FLOAT_ABI_DOUBLE
;
1901 if (strcasecmp (subset
->name
, "Q") == 0)
1902 float_abi
= FLOAT_ABI_QUAD
;
1906 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
1907 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
1911 md_pcrel_from (fixS
*fixP
)
1913 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1916 /* Apply a fixup to the object file. */
1919 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1921 unsigned int subtype
;
1922 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
1923 bfd_boolean relaxable
= FALSE
;
1927 /* Remember value for tc_gen_reloc. */
1928 fixP
->fx_addnumber
= *valP
;
1930 switch (fixP
->fx_r_type
)
1932 case BFD_RELOC_RISCV_HI20
:
1933 case BFD_RELOC_RISCV_LO12_I
:
1934 case BFD_RELOC_RISCV_LO12_S
:
1935 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
1936 | bfd_getl32 (buf
), buf
);
1937 if (fixP
->fx_addsy
== NULL
)
1938 fixP
->fx_done
= TRUE
;
1942 case BFD_RELOC_RISCV_GOT_HI20
:
1943 case BFD_RELOC_RISCV_ADD8
:
1944 case BFD_RELOC_RISCV_ADD16
:
1945 case BFD_RELOC_RISCV_ADD32
:
1946 case BFD_RELOC_RISCV_ADD64
:
1947 case BFD_RELOC_RISCV_SUB6
:
1948 case BFD_RELOC_RISCV_SUB8
:
1949 case BFD_RELOC_RISCV_SUB16
:
1950 case BFD_RELOC_RISCV_SUB32
:
1951 case BFD_RELOC_RISCV_SUB64
:
1952 case BFD_RELOC_RISCV_RELAX
:
1955 case BFD_RELOC_RISCV_TPREL_HI20
:
1956 case BFD_RELOC_RISCV_TPREL_LO12_I
:
1957 case BFD_RELOC_RISCV_TPREL_LO12_S
:
1958 case BFD_RELOC_RISCV_TPREL_ADD
:
1962 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
1963 case BFD_RELOC_RISCV_TLS_GD_HI20
:
1964 case BFD_RELOC_RISCV_TLS_DTPREL32
:
1965 case BFD_RELOC_RISCV_TLS_DTPREL64
:
1966 if (fixP
->fx_addsy
!= NULL
)
1967 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
1969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1970 _("TLS relocation against a constant"));
1974 /* Use pc-relative relocation for FDE initial location.
1975 The symbol address in .eh_frame may be adjusted in
1976 _bfd_elf_discard_section_eh_frame, and the content of
1977 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
1978 Therefore, we cannot insert a relocation whose addend symbol is
1979 in .eh_frame. Othrewise, the value may be adjusted twice.*/
1980 if (fixP
->fx_addsy
&& fixP
->fx_subsy
1981 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
1982 && strcmp (sub_segment
->name
, ".eh_frame") == 0
1983 && S_GET_VALUE (fixP
->fx_subsy
)
1984 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
1986 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
1987 fixP
->fx_subsy
= NULL
;
1994 case BFD_RELOC_RISCV_CFA
:
1995 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
1997 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
1998 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
1999 fixP
->fx_next
->fx_subsy
= NULL
;
2000 fixP
->fx_next
->fx_offset
= 0;
2001 fixP
->fx_subsy
= NULL
;
2003 switch (fixP
->fx_r_type
)
2006 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2007 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2011 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2012 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2016 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2017 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2021 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2022 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2025 case BFD_RELOC_RISCV_CFA
:
2026 /* Load the byte to get the subtype. */
2027 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2028 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2031 case DW_CFA_advance_loc1
:
2032 fixP
->fx_where
= loc
+ 1;
2033 fixP
->fx_next
->fx_where
= loc
+ 1;
2034 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2035 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2038 case DW_CFA_advance_loc2
:
2040 fixP
->fx_next
->fx_size
= 2;
2041 fixP
->fx_where
= loc
+ 1;
2042 fixP
->fx_next
->fx_where
= loc
+ 1;
2043 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2044 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2047 case DW_CFA_advance_loc4
:
2049 fixP
->fx_next
->fx_size
= 4;
2050 fixP
->fx_where
= loc
;
2051 fixP
->fx_next
->fx_where
= loc
;
2052 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2053 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2057 if (subtype
< 0x80 && (subtype
& 0x40))
2059 /* DW_CFA_advance_loc */
2060 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2061 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2062 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2063 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2066 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2072 /* This case is unreachable. */
2079 /* If we are deleting this reloc entry, we must fill in the
2080 value now. This can happen if we have a .word which is not
2081 resolved when it appears but is later defined. */
2082 if (fixP
->fx_addsy
== NULL
)
2084 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2085 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2090 case BFD_RELOC_RISCV_JMP
:
2093 /* Fill in a tentative value to improve objdump readability. */
2094 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2095 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2096 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2100 case BFD_RELOC_12_PCREL
:
2103 /* Fill in a tentative value to improve objdump readability. */
2104 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2105 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2106 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2110 case BFD_RELOC_RISCV_RVC_BRANCH
:
2113 /* Fill in a tentative value to improve objdump readability. */
2114 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2115 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2116 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2120 case BFD_RELOC_RISCV_RVC_JUMP
:
2123 /* Fill in a tentative value to improve objdump readability. */
2124 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2125 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2126 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2130 case BFD_RELOC_RISCV_CALL
:
2131 case BFD_RELOC_RISCV_CALL_PLT
:
2135 case BFD_RELOC_RISCV_PCREL_HI20
:
2136 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2137 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2138 relaxable
= riscv_opts
.relax
;
2141 case BFD_RELOC_RISCV_ALIGN
:
2145 /* We ignore generic BFD relocations we don't know about. */
2146 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2147 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2150 if (fixP
->fx_subsy
!= NULL
)
2151 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2152 _("unsupported symbol subtraction"));
2154 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2155 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2157 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2158 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2159 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2163 /* Because the value of .cfi_remember_state may changed after relaxation,
2164 we insert a fix to relocate it again in link-time. */
2167 riscv_pre_output_hook (void)
2169 const frchainS
*frch
;
2172 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2173 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2177 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2179 if (frag
->fr_type
== rs_cfa
)
2183 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2184 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2186 exp
.X_op
= O_subtract
;
2187 exp
.X_add_symbol
= add_symbol
;
2188 exp
.X_add_number
= 0;
2189 exp
.X_op_symbol
= op_symbol
;
2191 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2192 BFD_RELOC_RISCV_CFA
);
2199 /* This structure is used to hold a stack of .option values. */
2201 struct riscv_option_stack
2203 struct riscv_option_stack
*next
;
2204 struct riscv_set_options options
;
2207 static struct riscv_option_stack
*riscv_opts_stack
;
2209 /* Handle the .option pseudo-op. */
2212 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2214 char *name
= input_line_pointer
, ch
;
2216 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2217 ++input_line_pointer
;
2218 ch
= *input_line_pointer
;
2219 *input_line_pointer
= '\0';
2221 if (strcmp (name
, "rvc") == 0)
2222 riscv_set_rvc (TRUE
);
2223 else if (strcmp (name
, "norvc") == 0)
2224 riscv_set_rvc (FALSE
);
2225 else if (strcmp (name
, "pic") == 0)
2226 riscv_opts
.pic
= TRUE
;
2227 else if (strcmp (name
, "nopic") == 0)
2228 riscv_opts
.pic
= FALSE
;
2229 else if (strcmp (name
, "relax") == 0)
2230 riscv_opts
.relax
= TRUE
;
2231 else if (strcmp (name
, "norelax") == 0)
2232 riscv_opts
.relax
= FALSE
;
2233 else if (strcmp (name
, "push") == 0)
2235 struct riscv_option_stack
*s
;
2237 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2238 s
->next
= riscv_opts_stack
;
2239 s
->options
= riscv_opts
;
2240 riscv_opts_stack
= s
;
2242 else if (strcmp (name
, "pop") == 0)
2244 struct riscv_option_stack
*s
;
2246 s
= riscv_opts_stack
;
2248 as_bad (_(".option pop with no .option push"));
2251 riscv_opts
= s
->options
;
2252 riscv_opts_stack
= s
->next
;
2258 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2260 *input_line_pointer
= ch
;
2261 demand_empty_rest_of_line ();
2264 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2265 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2266 use in DWARF debug information. */
2269 s_dtprel (int bytes
)
2276 if (ex
.X_op
!= O_symbol
)
2278 as_bad (_("Unsupported use of %s"), (bytes
== 8
2281 ignore_rest_of_line ();
2284 p
= frag_more (bytes
);
2285 md_number_to_chars (p
, 0, bytes
);
2286 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2288 ? BFD_RELOC_RISCV_TLS_DTPREL64
2289 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2291 demand_empty_rest_of_line ();
2294 /* Handle the .bss pseudo-op. */
2297 s_bss (int ignore ATTRIBUTE_UNUSED
)
2299 subseg_set (bss_section
, 0);
2300 demand_empty_rest_of_line ();
2304 riscv_make_nops (char *buf
, bfd_vma bytes
)
2308 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2309 means we are not within a valid instruction sequence. It is thus safe
2310 to use a zero byte, even though that is not a valid instruction. */
2314 /* Use at most one 2-byte NOP. */
2315 if ((bytes
- i
) % 4 == 2)
2317 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2321 /* Fill the remainder with 4-byte NOPs. */
2322 for ( ; i
< bytes
; i
+= 4)
2323 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2326 /* Called from md_do_align. Used to create an alignment frag in a
2327 code section by emitting a worst-case NOP sequence that the linker
2328 will later relax to the correct number of NOPs. We can't compute
2329 the correct alignment now because of other linker relaxations. */
2332 riscv_frag_align_code (int n
)
2334 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2335 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2336 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2340 /* If we are moving to a smaller alignment than the instruction size, then no
2341 alignment is required. */
2342 if (bytes
<= insn_alignment
)
2345 nops
= frag_more (worst_case_bytes
);
2347 /* When not relaxing, riscv_handle_align handles code alignment. */
2348 if (!riscv_opts
.relax
)
2351 ex
.X_op
= O_constant
;
2352 ex
.X_add_number
= worst_case_bytes
;
2354 riscv_make_nops (nops
, worst_case_bytes
);
2356 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2357 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2362 /* Implement HANDLE_ALIGN. */
2365 riscv_handle_align (fragS
*fragP
)
2367 switch (fragP
->fr_type
)
2370 /* When relaxing, riscv_frag_align_code handles code alignment. */
2371 if (!riscv_opts
.relax
)
2373 bfd_signed_vma count
= fragP
->fr_next
->fr_address
2374 - fragP
->fr_address
- fragP
->fr_fix
;
2379 count
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
2380 riscv_make_nops (fragP
->fr_literal
+ fragP
->fr_fix
, count
);
2381 fragP
->fr_var
= count
;
2391 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2393 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2396 /* Translate internal representation of relocation info to BFD target
2400 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2402 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2404 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2405 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2406 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2407 reloc
->addend
= fixp
->fx_addnumber
;
2409 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2410 if (reloc
->howto
== NULL
)
2412 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2413 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2415 /* We don't have R_RISCV_8/16, but for this special case,
2416 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2420 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2421 _("cannot represent %s relocation in object file"),
2422 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2430 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2432 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2434 offsetT old_var
= fragp
->fr_var
;
2435 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2436 return fragp
->fr_var
- old_var
;
2442 /* Expand far branches to multi-instruction sequences. */
2445 md_convert_frag_branch (fragS
*fragp
)
2453 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2455 exp
.X_op
= O_symbol
;
2456 exp
.X_add_symbol
= fragp
->fr_symbol
;
2457 exp
.X_add_number
= fragp
->fr_offset
;
2459 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2461 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2463 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2467 /* Expand the RVC branch into a RISC-V one. */
2468 insn
= bfd_getl16 (buf
);
2469 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2470 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2472 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2473 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2474 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2475 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2476 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2477 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2480 bfd_putl32 (insn
, buf
);
2484 /* Invert the branch condition. Branch over the jump. */
2485 insn
= bfd_getl16 (buf
);
2486 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2487 insn
|= ENCODE_RVC_B_IMM (6);
2488 bfd_putl16 (insn
, buf
);
2493 /* Just keep the RVC branch. */
2494 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2495 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2496 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2497 2, &exp
, FALSE
, reloc
);
2506 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2509 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2511 /* Invert the branch condition. Branch over the jump. */
2512 insn
= bfd_getl32 (buf
);
2513 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2514 insn
|= ENCODE_SBTYPE_IMM (8);
2515 md_number_to_chars ((char *) buf
, insn
, 4);
2519 /* Jump to the target. */
2520 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2521 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2522 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2527 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2528 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2529 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2530 4, &exp
, FALSE
, reloc
);
2539 fixp
->fx_file
= fragp
->fr_file
;
2540 fixp
->fx_line
= fragp
->fr_line
;
2542 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2543 + fragp
->fr_fix
+ fragp
->fr_var
);
2545 fragp
->fr_fix
+= fragp
->fr_var
;
2548 /* Relax a machine dependent frag. This returns the amount by which
2549 the current size of the frag should change. */
2552 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2555 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2556 md_convert_frag_branch (fragp
);
2560 md_show_usage (FILE *stream
)
2562 fprintf (stream
, _("\
2564 -fpic generate position-independent code\n\
2565 -fno-pic don't generate position-independent code (default)\n\
2566 -march=ISA set the RISC-V architecture\n\
2567 -mabi=ABI set the RISC-V ABI\n\
2571 /* Standard calling conventions leave the CFA at SP on entry. */
2573 riscv_cfi_frame_initial_instructions (void)
2575 cfi_add_CFA_def_cfa_register (X_SP
);
2579 tc_riscv_regname_to_dw2regnum (char *regname
)
2583 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2586 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2589 as_bad (_("unknown register `%s'"), regname
);
2594 riscv_elf_final_processing (void)
2596 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2599 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2600 since these directives break relaxation when used with symbol deltas. */
2603 s_riscv_leb128 (int sign
)
2606 char *save_in
= input_line_pointer
;
2609 if (exp
.X_op
!= O_constant
)
2610 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2611 demand_empty_rest_of_line ();
2613 input_line_pointer
= save_in
;
2614 return s_leb128 (sign
);
2617 /* Pseudo-op table. */
2619 static const pseudo_typeS riscv_pseudo_table
[] =
2621 /* RISC-V-specific pseudo-ops. */
2622 {"option", s_riscv_option
, 0},
2626 {"dtprelword", s_dtprel
, 4},
2627 {"dtpreldword", s_dtprel
, 8},
2629 {"uleb128", s_riscv_leb128
, 0},
2630 {"sleb128", s_riscv_leb128
, 1},
2636 riscv_pop_insert (void)
2638 extern void pop_insert (const pseudo_typeS
*);
2640 pop_insert (riscv_pseudo_table
);