1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2017 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int relax
; /* Emit relocs the linker is allowed to relax. */
81 static struct riscv_set_options riscv_opts
=
89 riscv_set_rvc (bfd_boolean rvc_value
)
92 elf_flags
|= EF_RISCV_RVC
;
94 riscv_opts
.rvc
= rvc_value
;
101 struct riscv_subset
*next
;
104 static struct riscv_subset
*riscv_subsets
;
107 riscv_subset_supports (const char *feature
)
109 struct riscv_subset
*s
;
111 unsigned xlen_required
= strtoul (feature
, &p
, 10);
113 if (xlen_required
&& xlen
!= xlen_required
)
116 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
117 if (strcasecmp (s
->name
, p
) == 0)
124 riscv_clear_subsets (void)
126 while (riscv_subsets
!= NULL
)
128 struct riscv_subset
*next
= riscv_subsets
->next
;
129 free ((void *) riscv_subsets
->name
);
130 free (riscv_subsets
);
131 riscv_subsets
= next
;
136 riscv_add_subset (const char *subset
)
138 struct riscv_subset
*s
= xmalloc (sizeof *s
);
140 s
->name
= xstrdup (subset
);
141 s
->next
= riscv_subsets
;
145 /* Set which ISA and extensions are available. */
148 riscv_set_arch (const char *s
)
150 const char *all_subsets
= "imafdqc";
151 char *extension
= NULL
;
154 riscv_clear_subsets();
156 if (strncmp (p
, "rv32", 4) == 0)
161 else if (strncmp (p
, "rv64", 4) == 0)
167 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
176 for ( ; *all_subsets
!= 'q'; all_subsets
++)
178 const char subset
[] = {*all_subsets
, '\0'};
179 riscv_add_subset (subset
);
184 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s
);
191 char *subset
= xstrdup (p
);
194 while (*++q
!= '\0' && *q
!= '_')
199 as_fatal ("-march=%s: only one non-standard extension is supported"
200 " (found `%s' and `%s')", s
, extension
, subset
);
202 riscv_add_subset (subset
);
203 p
+= strlen (subset
);
207 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
209 const char subset
[] = {*p
, 0};
210 riscv_add_subset (subset
);
215 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
221 /* Handle of the OPCODE hash table. */
222 static struct hash_control
*op_hash
= NULL
;
224 /* This array holds the chars that always start a comment. If the
225 pre-processor is disabled, these aren't very useful */
226 const char comment_chars
[] = "#";
228 /* This array holds the chars that only start a comment at the beginning of
229 a line. If the line seems to have the form '# 123 filename'
230 .line and .file directives will appear in the pre-processed output */
231 /* Note that input_file.c hand checks for '#' at the beginning of the
232 first line of the input file. This is because the compiler outputs
233 #NO_APP at the beginning of its output. */
234 /* Also note that C style comments are always supported. */
235 const char line_comment_chars
[] = "#";
237 /* This array holds machine specific line separator characters. */
238 const char line_separator_chars
[] = ";";
240 /* Chars that can be used to separate mant from exp in floating point nums */
241 const char EXP_CHARS
[] = "eE";
243 /* Chars that mean this number is a floating point constant */
246 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
248 /* Macros for encoding relaxation state for RVC branches and far jumps. */
249 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
252 | ((uncond) ? 1 : 0) \
255 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
256 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
257 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
258 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
260 /* Is the given value a sign-extended 32-bit value? */
261 #define IS_SEXT_32BIT_NUM(x) \
262 (((x) &~ (offsetT) 0x7fffffff) == 0 \
263 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
265 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
266 #define IS_ZEXT_32BIT_NUM(x) \
267 (((x) &~ (offsetT) 0xffffffff) == 0 \
268 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
270 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
271 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
272 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
273 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
275 /* Determine if an instruction matches an opcode. */
276 #define OPCODE_MATCHES(OPCODE, OP) \
277 (((OPCODE) & MASK_##OP) == MATCH_##OP)
279 static char *expr_end
;
281 /* The default target format to use. */
284 riscv_target_format (void)
286 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
289 /* Return the length of instruction INSN. */
291 static inline unsigned int
292 insn_length (const struct riscv_cl_insn
*insn
)
294 return riscv_insn_length (insn
->insn_opcode
);
297 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
300 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
303 insn
->insn_opcode
= mo
->match
;
309 /* Install INSN at the location specified by its "frag" and "where" fields. */
312 install_insn (const struct riscv_cl_insn
*insn
)
314 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
315 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
318 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
319 and install the opcode in the new location. */
322 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
326 if (insn
->fixp
!= NULL
)
328 insn
->fixp
->fx_frag
= frag
;
329 insn
->fixp
->fx_where
= where
;
334 /* Add INSN to the end of the output. */
337 add_fixed_insn (struct riscv_cl_insn
*insn
)
339 char *f
= frag_more (insn_length (insn
));
340 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
344 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
345 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
347 frag_grow (max_chars
);
348 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
349 frag_var (rs_machine_dependent
, max_chars
, var
,
350 subtype
, symbol
, offset
, NULL
);
353 /* Compute the length of a branch sequence, and adjust the stored length
354 accordingly. If FRAGP is NULL, the worst-case length is returned. */
357 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
359 int jump
, rvc
, length
= 8;
364 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
365 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
366 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
368 /* Assume jumps are in range; the linker will catch any that aren't. */
369 length
= jump
? 4 : 8;
371 if (fragp
->fr_symbol
!= NULL
372 && S_IS_DEFINED (fragp
->fr_symbol
)
373 && !S_IS_WEAK (fragp
->fr_symbol
)
374 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
376 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
377 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
378 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
380 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
382 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
384 else if (!jump
&& rvc
)
389 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
408 static struct hash_control
*reg_names_hash
= NULL
;
410 #define ENCODE_REG_HASH(cls, n) \
411 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
412 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
413 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
416 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
418 void *hash
= ENCODE_REG_HASH (class, n
);
419 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
422 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
426 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
430 for (i
= 0; i
< n
; i
++)
431 hash_reg_name (class, names
[i
], i
);
435 reg_lookup_internal (const char *s
, enum reg_class
class)
437 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
439 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
441 return DECODE_REG_NUM (r
);
445 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
451 /* Find end of name. */
453 if (is_name_beginner (*e
))
455 while (is_part_of_name (*e
))
458 /* Terminate name. */
462 /* Look for the register. Advance to next token if one was recognized. */
463 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
473 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
475 const char *p
= strchr (*s
, ',');
476 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
478 for (i
= 0; i
< size
; i
++)
479 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
489 /* For consistency checking, verify that all bits are specified either
490 by the match/mask part of the instruction definition, or by the
493 validate_riscv_insn (const struct riscv_opcode
*opc
)
495 const char *p
= opc
->args
;
497 insn_t used_bits
= opc
->mask
;
498 int insn_width
= 8 * riscv_insn_length (opc
->match
);
499 insn_t required_bits
= ~0ULL >> (64 - insn_width
);
501 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
503 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
504 opc
->name
, opc
->args
);
508 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
515 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
516 case 'c': break; /* RS1, constrained to equal sp */
517 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
518 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
519 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
520 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
521 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
522 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
523 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
524 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
525 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
526 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
527 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
528 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
529 case 'w': break; /* RS1S, constrained to equal RD */
530 case 'x': break; /* RS2S, constrained to equal RD */
531 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
532 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
533 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
534 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
535 case 'U': break; /* RS1, constrained to equal RD */
536 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
537 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
538 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
539 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
540 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
542 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
543 c
, opc
->name
, opc
->args
);
550 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
551 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
553 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
554 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
555 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
557 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
558 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
559 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
560 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
561 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
562 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
563 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
564 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
565 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
566 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
568 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
569 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
570 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
571 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
572 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
577 as_bad (_("internal: bad RISC-V opcode "
578 "(unknown operand type `%c'): %s %s"),
579 c
, opc
->name
, opc
->args
);
583 if (used_bits
!= required_bits
)
585 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
586 ~(unsigned long)(used_bits
& required_bits
),
587 opc
->name
, opc
->args
);
593 struct percent_op_match
596 bfd_reloc_code_real_type reloc
;
599 /* This function is called once, at assembler startup time. It should set up
600 all the tables, etc. that the MD part of the assembler will need. */
606 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
608 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
609 as_warn (_("Could not set architecture and machine"));
611 op_hash
= hash_new ();
613 while (riscv_opcodes
[i
].name
)
615 const char *name
= riscv_opcodes
[i
].name
;
616 const char *hash_error
=
617 hash_insert (op_hash
, name
, (void *) &riscv_opcodes
[i
]);
621 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
622 riscv_opcodes
[i
].name
, hash_error
);
623 /* Probably a memory allocation problem? Give up now. */
624 as_fatal (_("Broken assembler. No assembly attempted."));
629 if (riscv_opcodes
[i
].pinfo
!= INSN_MACRO
)
631 if (!validate_riscv_insn (&riscv_opcodes
[i
]))
632 as_fatal (_("Broken assembler. No assembly attempted."));
636 while (riscv_opcodes
[i
].name
&& !strcmp (riscv_opcodes
[i
].name
, name
));
639 reg_names_hash
= hash_new ();
640 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
641 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
642 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
643 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
645 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
646 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
647 #include "opcode/riscv-opc.h"
650 /* Set the default alignment for the text section. */
651 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
655 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
662 case BFD_RELOC_RISCV_HI20
:
663 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
665 case BFD_RELOC_RISCV_LO12_S
:
666 return ENCODE_STYPE_IMM (value
);
668 case BFD_RELOC_RISCV_LO12_I
:
669 return ENCODE_ITYPE_IMM (value
);
676 /* Output an instruction. IP is the instruction information.
677 ADDRESS_EXPR is an operand of the instruction to be used with
681 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
682 bfd_reloc_code_real_type reloc_type
)
684 dwarf2_emit_insn (0);
686 if (reloc_type
!= BFD_RELOC_UNUSED
)
688 reloc_howto_type
*howto
;
690 gas_assert (address_expr
);
691 if (reloc_type
== BFD_RELOC_12_PCREL
692 || reloc_type
== BFD_RELOC_RISCV_JMP
)
694 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
695 int best_case
= riscv_insn_length (ip
->insn_opcode
);
696 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
697 add_relaxed_insn (ip
, worst_case
, best_case
,
698 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
699 address_expr
->X_add_symbol
,
700 address_expr
->X_add_number
);
705 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
707 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
709 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
710 bfd_get_reloc_size (howto
),
711 address_expr
, FALSE
, reloc_type
);
713 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
720 /* We need to start a new frag after any instruction that can be
721 optimized away or compressed by the linker during relaxation, to prevent
722 the assembler from computing static offsets across such an instruction.
723 This is necessary to get correct EH info. */
724 if (reloc_type
== BFD_RELOC_RISCV_CALL
725 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
726 || reloc_type
== BFD_RELOC_RISCV_HI20
727 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
728 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
729 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
731 frag_wane (frag_now
);
736 /* Build an instruction created by a macro expansion. This is passed
737 a pointer to the count of instructions created so far, an
738 expression, the name of the instruction to build, an operand format
739 string, and corresponding arguments. */
742 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
744 const struct riscv_opcode
*mo
;
745 struct riscv_cl_insn insn
;
746 bfd_reloc_code_real_type r
;
749 va_start (args
, fmt
);
751 r
= BFD_RELOC_UNUSED
;
752 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
755 /* Find a non-RVC variant of the instruction. append_insn will compress
757 while (riscv_insn_length (mo
->match
) < 4)
759 gas_assert (strcmp (name
, mo
->name
) == 0);
761 create_insn (&insn
, mo
);
767 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
771 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
775 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
779 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
785 gas_assert (ep
!= NULL
);
786 r
= va_arg (args
, int);
794 as_fatal (_("internal error: invalid macro"));
799 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
801 append_insn (&insn
, ep
, r
);
804 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
807 normalize_constant_expr (expressionS
*ex
)
811 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
812 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
813 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
817 /* Fail if an expression is not a constant. */
820 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
)
822 if (ex
->X_op
== O_big
)
823 as_bad (_("unsupported large constant"));
824 else if (ex
->X_op
!= O_constant
)
825 as_bad (_("Instruction %s requires absolute expression"),
827 normalize_constant_expr (ex
);
831 make_internal_label (void)
833 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
834 (valueT
) frag_now_fix (), frag_now
);
837 /* Load an entry from the GOT. */
839 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
840 const char *lo_insn
, const char *lo_pattern
,
841 bfd_reloc_code_real_type hi_reloc
,
842 bfd_reloc_code_real_type lo_reloc
)
846 ep2
.X_add_symbol
= make_internal_label ();
847 ep2
.X_add_number
= 0;
849 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
850 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
854 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
855 bfd_reloc_code_real_type hi_reloc
,
856 bfd_reloc_code_real_type lo_reloc
)
858 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
862 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
863 bfd_reloc_code_real_type hi_reloc
,
864 bfd_reloc_code_real_type lo_reloc
)
866 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
869 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
871 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
872 bfd_reloc_code_real_type reloc
)
874 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
875 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
878 /* Load an integer constant into a register. */
881 load_const (int reg
, expressionS
*ep
)
883 int shift
= RISCV_IMM_BITS
;
884 expressionS upper
= *ep
, lower
= *ep
;
885 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
886 upper
.X_add_number
-= lower
.X_add_number
;
888 if (ep
->X_op
!= O_constant
)
890 as_bad (_("unsupported large constant"));
894 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
896 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
897 while (((upper
.X_add_number
>> shift
) & 1) == 0)
900 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
901 load_const (reg
, &upper
);
903 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
904 if (lower
.X_add_number
!= 0)
905 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
909 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
912 if (upper
.X_add_number
!= 0)
914 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
918 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
919 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
920 BFD_RELOC_RISCV_LO12_I
);
924 /* Expand RISC-V assembly macros into one or more instructions. */
926 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
927 bfd_reloc_code_real_type
*imm_reloc
)
929 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
930 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
931 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
932 int mask
= ip
->insn_mo
->mask
;
937 load_const (rd
, imm_expr
);
942 /* Load the address of a symbol into a register. */
943 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
944 as_bad (_("offset too large"));
946 if (imm_expr
->X_op
== O_constant
)
947 load_const (rd
, imm_expr
);
948 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
949 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
950 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
951 else /* Local PIC symbol, or any non-PIC symbol */
952 pcrel_load (rd
, rd
, imm_expr
, "addi",
953 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
957 pcrel_load (rd
, rd
, imm_expr
, "addi",
958 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
962 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
963 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
967 pcrel_load (rd
, rd
, imm_expr
, "lb",
968 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
972 pcrel_load (rd
, rd
, imm_expr
, "lbu",
973 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
977 pcrel_load (rd
, rd
, imm_expr
, "lh",
978 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
982 pcrel_load (rd
, rd
, imm_expr
, "lhu",
983 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
987 pcrel_load (rd
, rd
, imm_expr
, "lw",
988 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
992 pcrel_load (rd
, rd
, imm_expr
, "lwu",
993 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
997 pcrel_load (rd
, rd
, imm_expr
, "ld",
998 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1002 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1003 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1007 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1008 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1012 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1013 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1017 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1018 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1022 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1023 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1027 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1028 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1032 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1033 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1037 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1038 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1042 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1046 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1051 static const struct percent_op_match percent_op_utype
[] =
1053 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1054 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1055 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1056 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1057 {"%hi", BFD_RELOC_RISCV_HI20
},
1061 static const struct percent_op_match percent_op_itype
[] =
1063 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1064 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1065 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1069 static const struct percent_op_match percent_op_stype
[] =
1071 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1072 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1073 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1077 static const struct percent_op_match percent_op_rtype
[] =
1079 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1083 /* Return true if *STR points to a relocation operator. When returning true,
1084 move *STR over the operator and store its relocation code in *RELOC.
1085 Leave both *STR and *RELOC alone when returning false. */
1088 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1089 const struct percent_op_match
*percent_op
)
1091 for ( ; percent_op
->str
; percent_op
++)
1092 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1094 int len
= strlen (percent_op
->str
);
1096 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1099 *str
+= strlen (percent_op
->str
);
1100 *reloc
= percent_op
->reloc
;
1102 /* Check whether the output BFD supports this relocation.
1103 If not, issue an error and fall back on something safe. */
1104 if (*reloc
!= BFD_RELOC_UNUSED
1105 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1107 as_bad ("relocation %s isn't supported by the current ABI",
1109 *reloc
= BFD_RELOC_UNUSED
;
1117 my_getExpression (expressionS
*ep
, char *str
)
1121 save_in
= input_line_pointer
;
1122 input_line_pointer
= str
;
1124 expr_end
= input_line_pointer
;
1125 input_line_pointer
= save_in
;
1128 /* Parse string STR as a 16-bit relocatable operand. Store the
1129 expression in *EP and the relocation, if any, in RELOC.
1130 Return the number of relocation operators used (0 or 1).
1132 On exit, EXPR_END points to the first character after the expression. */
1135 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1136 char *str
, const struct percent_op_match
*percent_op
)
1139 unsigned crux_depth
, str_depth
, regno
;
1142 /* First, check for integer registers. */
1143 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1145 ep
->X_op
= O_register
;
1146 ep
->X_add_number
= regno
;
1150 /* Search for the start of the main expression.
1151 End the loop with CRUX pointing to the start
1152 of the main expression and with CRUX_DEPTH containing the number
1153 of open brackets at that point. */
1160 crux_depth
= str_depth
;
1162 /* Skip over whitespace and brackets, keeping count of the number
1164 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1170 && parse_relocation (&str
, reloc
, percent_op
));
1172 my_getExpression (ep
, crux
);
1175 /* Match every open bracket. */
1176 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1181 as_bad ("unclosed '('");
1188 /* This routine assembles an instruction into its binary format. As a
1189 side effect, it sets the global variable imm_reloc to the type of
1190 relocation to do if one of the operands is an address expression. */
1193 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1194 bfd_reloc_code_real_type
*imm_reloc
)
1199 struct riscv_opcode
*insn
;
1204 const struct percent_op_match
*p
;
1205 const char *error
= "unrecognized opcode";
1207 /* Parse the name of the instruction. Terminate the string if whitespace
1208 is found so that hash_find only sees the name part of the string. */
1209 for (s
= str
; *s
!= '\0'; ++s
)
1217 insn
= (struct riscv_opcode
*) hash_find (op_hash
, str
);
1220 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1222 if (!riscv_subset_supports (insn
->subset
))
1225 create_insn (ip
, insn
);
1228 imm_expr
->X_op
= O_absent
;
1229 *imm_reloc
= BFD_RELOC_UNUSED
;
1230 p
= percent_op_itype
;
1232 for (args
= insn
->args
;; ++args
)
1234 s
+= strspn (s
, " \t");
1237 case '\0': /* End of args. */
1238 if (insn
->pinfo
!= INSN_MACRO
)
1240 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1242 if (riscv_insn_length (insn
->match
) == 2 && !riscv_opts
.rvc
)
1247 /* Successful assembly. */
1254 case 's': /* RS1 x8-x15 */
1255 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1256 || !(regno
>= 8 && regno
<= 15))
1258 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1260 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1261 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1262 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1265 case 't': /* RS2 x8-x15 */
1266 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1267 || !(regno
>= 8 && regno
<= 15))
1269 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1271 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1272 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1273 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1276 case 'U': /* RS1, constrained to equal RD. */
1277 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1278 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1282 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1284 INSERT_OPERAND (CRS2
, *ip
, regno
);
1286 case 'c': /* RS1, constrained to equal sp. */
1287 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1292 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1293 || imm_expr
->X_op
!= O_constant
1294 || imm_expr
->X_add_number
<= 0
1295 || imm_expr
->X_add_number
>= 64)
1297 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1300 imm_expr
->X_op
= O_absent
;
1303 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1304 || imm_expr
->X_op
!= O_constant
1305 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1306 || imm_expr
->X_add_number
<= 0
1307 || imm_expr
->X_add_number
>= 32)
1309 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1312 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1313 || imm_expr
->X_op
!= O_constant
1314 || imm_expr
->X_add_number
== 0
1315 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1317 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1320 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1321 || imm_expr
->X_op
!= O_constant
1322 || imm_expr
->X_add_number
== 0
1323 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1325 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1328 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1329 || imm_expr
->X_op
!= O_constant
1330 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1332 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1335 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1336 || imm_expr
->X_op
!= O_constant
1337 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1339 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1342 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1343 || imm_expr
->X_op
!= O_constant
1344 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1347 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1350 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1351 || imm_expr
->X_op
!= O_constant
1352 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1355 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1358 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1359 || imm_expr
->X_op
!= O_constant
1360 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1362 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1365 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1366 || imm_expr
->X_op
!= O_constant
1367 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1368 || imm_expr
->X_add_number
== 0)
1371 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1374 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1375 || imm_expr
->X_op
!= O_constant
1376 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1377 || imm_expr
->X_add_number
== 0)
1380 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1383 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1384 || imm_expr
->X_op
!= O_constant
1385 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1388 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1391 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1392 || imm_expr
->X_op
!= O_constant
1393 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1396 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1399 p
= percent_op_utype
;
1400 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1403 if (imm_expr
->X_op
!= O_constant
1404 || imm_expr
->X_add_number
<= 0
1405 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1406 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1407 && (imm_expr
->X_add_number
<
1408 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1410 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1413 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1414 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1415 || ((int32_t)imm_expr
->X_add_number
1416 != imm_expr
->X_add_number
))
1418 imm_expr
->X_add_number
=
1419 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1425 case 'D': /* Floating-point RS2 x8-x15. */
1426 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1427 || !(regno
>= 8 && regno
<= 15))
1429 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1431 case 'T': /* Floating-point RS2. */
1432 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1434 INSERT_OPERAND (CRS2
, *ip
, regno
);
1437 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1456 case '<': /* Shift amount, 0 - 31. */
1457 my_getExpression (imm_expr
, s
);
1458 check_absolute_expr (ip
, imm_expr
);
1459 if ((unsigned long) imm_expr
->X_add_number
> 31)
1460 as_bad (_("Improper shift amount (%lu)"),
1461 (unsigned long) imm_expr
->X_add_number
);
1462 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1463 imm_expr
->X_op
= O_absent
;
1467 case '>': /* Shift amount, 0 - (XLEN-1). */
1468 my_getExpression (imm_expr
, s
);
1469 check_absolute_expr (ip
, imm_expr
);
1470 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1471 as_bad (_("Improper shift amount (%lu)"),
1472 (unsigned long) imm_expr
->X_add_number
);
1473 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1474 imm_expr
->X_op
= O_absent
;
1478 case 'Z': /* CSRRxI immediate. */
1479 my_getExpression (imm_expr
, s
);
1480 check_absolute_expr (ip
, imm_expr
);
1481 if ((unsigned long) imm_expr
->X_add_number
> 31)
1482 as_bad (_("Improper CSRxI immediate (%lu)"),
1483 (unsigned long) imm_expr
->X_add_number
);
1484 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1485 imm_expr
->X_op
= O_absent
;
1489 case 'E': /* Control register. */
1490 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1491 INSERT_OPERAND (CSR
, *ip
, regno
);
1494 my_getExpression (imm_expr
, s
);
1495 check_absolute_expr (ip
, imm_expr
);
1496 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1497 as_bad (_("Improper CSR address (%lu)"),
1498 (unsigned long) imm_expr
->X_add_number
);
1499 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1500 imm_expr
->X_op
= O_absent
;
1505 case 'm': /* Rounding mode. */
1506 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1508 INSERT_OPERAND (RM
, *ip
, regno
);
1514 case 'Q': /* Fence predecessor/successor. */
1515 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1519 INSERT_OPERAND (PRED
, *ip
, regno
);
1521 INSERT_OPERAND (SUCC
, *ip
, regno
);
1526 case 'd': /* Destination register. */
1527 case 's': /* Source register. */
1528 case 't': /* Target register. */
1529 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1535 /* Now that we have assembled one operand, we use the args
1536 string to figure out where it goes in the instruction. */
1540 INSERT_OPERAND (RS1
, *ip
, regno
);
1543 INSERT_OPERAND (RD
, *ip
, regno
);
1546 INSERT_OPERAND (RS2
, *ip
, regno
);
1553 case 'D': /* Floating point rd. */
1554 case 'S': /* Floating point rs1. */
1555 case 'T': /* Floating point rs2. */
1556 case 'U': /* Floating point rs1 and rs2. */
1557 case 'R': /* Floating point rs3. */
1558 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1566 INSERT_OPERAND (RD
, *ip
, regno
);
1569 INSERT_OPERAND (RS1
, *ip
, regno
);
1572 INSERT_OPERAND (RS1
, *ip
, regno
);
1575 INSERT_OPERAND (RS2
, *ip
, regno
);
1578 INSERT_OPERAND (RS3
, *ip
, regno
);
1587 my_getExpression (imm_expr
, s
);
1588 if (imm_expr
->X_op
!= O_big
1589 && imm_expr
->X_op
!= O_constant
)
1591 normalize_constant_expr (imm_expr
);
1596 my_getExpression (imm_expr
, s
);
1597 normalize_constant_expr (imm_expr
);
1598 /* The 'A' format specifier must be a symbol. */
1599 if (imm_expr
->X_op
!= O_symbol
)
1601 *imm_reloc
= BFD_RELOC_32
;
1605 case 'j': /* Sign-extended immediate. */
1606 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1607 p
= percent_op_itype
;
1609 case 'q': /* Store displacement. */
1610 p
= percent_op_stype
;
1611 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1613 case 'o': /* Load displacement. */
1614 p
= percent_op_itype
;
1615 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1617 case '0': /* AMO "displacement," which must be zero. */
1618 p
= percent_op_rtype
;
1619 *imm_reloc
= BFD_RELOC_UNUSED
;
1621 /* Check whether there is only a single bracketed expression
1622 left. If so, it must be the base register and the
1623 constant must be zero. */
1624 imm_expr
->X_op
= O_constant
;
1625 imm_expr
->X_add_number
= 0;
1626 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1629 /* If this value won't fit into a 16 bit offset, then go
1630 find a macro that will generate the 32 bit offset
1632 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1634 normalize_constant_expr (imm_expr
);
1635 if (imm_expr
->X_op
!= O_constant
1636 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1637 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1638 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1645 case 'p': /* PC-relative offset. */
1647 *imm_reloc
= BFD_RELOC_12_PCREL
;
1648 my_getExpression (imm_expr
, s
);
1652 case 'u': /* Upper 20 bits. */
1653 p
= percent_op_utype
;
1654 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1655 && imm_expr
->X_op
== O_constant
)
1657 if (imm_expr
->X_add_number
< 0
1658 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1659 as_bad (_("lui expression not in range 0..1048575"));
1661 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1662 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1667 case 'a': /* 20-bit PC-relative offset. */
1669 my_getExpression (imm_expr
, s
);
1671 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1675 my_getExpression (imm_expr
, s
);
1677 if (strcmp (s
, "@plt") == 0)
1679 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1683 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1687 as_fatal (_("internal error: bad argument type %c"), *args
);
1692 error
= _("illegal operands");
1696 /* Restore the character we might have clobbered above. */
1698 *(argsStart
- 1) = save_c
;
1704 md_assemble (char *str
)
1706 struct riscv_cl_insn insn
;
1707 expressionS imm_expr
;
1708 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
1710 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
);
1714 as_bad ("%s `%s'", error
, str
);
1718 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1719 macro (&insn
, &imm_expr
, &imm_reloc
);
1721 append_insn (&insn
, &imm_expr
, imm_reloc
);
1725 md_atof (int type
, char *litP
, int *sizeP
)
1727 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
1731 md_number_to_chars (char *buf
, valueT val
, int n
)
1733 number_to_chars_littleendian (buf
, val
, n
);
1736 const char *md_shortopts
= "O::g::G:";
1740 OPTION_MARCH
= OPTION_MD_BASE
,
1747 struct option md_longopts
[] =
1749 {"march", required_argument
, NULL
, OPTION_MARCH
},
1750 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
1751 {"fpic", no_argument
, NULL
, OPTION_PIC
},
1752 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
1753 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1755 {NULL
, no_argument
, NULL
, 0}
1757 size_t md_longopts_size
= sizeof (md_longopts
);
1760 FLOAT_ABI_DEFAULT
= -1,
1766 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
1769 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
)
1771 abi_xlen
= new_xlen
;
1772 float_abi
= new_float_abi
;
1776 md_parse_option (int c
, const char *arg
)
1781 riscv_set_arch (arg
);
1785 riscv_opts
.pic
= FALSE
;
1789 riscv_opts
.pic
= TRUE
;
1793 if (strcmp (arg
, "ilp32") == 0)
1794 riscv_set_abi (32, FLOAT_ABI_SOFT
);
1795 else if (strcmp (arg
, "ilp32f") == 0)
1796 riscv_set_abi (32, FLOAT_ABI_SINGLE
);
1797 else if (strcmp (arg
, "ilp32d") == 0)
1798 riscv_set_abi (32, FLOAT_ABI_DOUBLE
);
1799 else if (strcmp (arg
, "ilp32q") == 0)
1800 riscv_set_abi (32, FLOAT_ABI_QUAD
);
1801 else if (strcmp (arg
, "lp64") == 0)
1802 riscv_set_abi (64, FLOAT_ABI_SOFT
);
1803 else if (strcmp (arg
, "lp64f") == 0)
1804 riscv_set_abi (64, FLOAT_ABI_SINGLE
);
1805 else if (strcmp (arg
, "lp64d") == 0)
1806 riscv_set_abi (64, FLOAT_ABI_DOUBLE
);
1807 else if (strcmp (arg
, "lp64q") == 0)
1808 riscv_set_abi (64, FLOAT_ABI_QUAD
);
1821 riscv_after_parse_args (void)
1825 if (strcmp (default_arch
, "riscv32") == 0)
1827 else if (strcmp (default_arch
, "riscv64") == 0)
1830 as_bad ("unknown default architecture `%s'", default_arch
);
1833 if (riscv_subsets
== NULL
)
1834 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
1836 /* Add the RVC extension, regardless of -march, to support .option rvc. */
1837 riscv_set_rvc (FALSE
);
1838 if (riscv_subset_supports ("c"))
1839 riscv_set_rvc (TRUE
);
1841 riscv_add_subset ("c");
1843 /* Infer ABI from ISA if not specified on command line. */
1846 else if (abi_xlen
> xlen
)
1847 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
1848 else if (abi_xlen
< xlen
)
1849 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
1851 if (float_abi
== FLOAT_ABI_DEFAULT
)
1853 struct riscv_subset
*subset
;
1855 /* Assume soft-float unless D extension is present. */
1856 float_abi
= FLOAT_ABI_SOFT
;
1858 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
1860 if (strcasecmp (subset
->name
, "D") == 0)
1861 float_abi
= FLOAT_ABI_DOUBLE
;
1862 if (strcasecmp (subset
->name
, "Q") == 0)
1863 float_abi
= FLOAT_ABI_QUAD
;
1867 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
1868 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
1872 md_pcrel_from (fixS
*fixP
)
1874 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
1877 /* Apply a fixup to the object file. */
1880 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
1882 unsigned int subtype
;
1883 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
1884 bfd_boolean relaxable
= FALSE
;
1888 /* Remember value for tc_gen_reloc. */
1889 fixP
->fx_addnumber
= *valP
;
1891 switch (fixP
->fx_r_type
)
1893 case BFD_RELOC_RISCV_HI20
:
1894 case BFD_RELOC_RISCV_LO12_I
:
1895 case BFD_RELOC_RISCV_LO12_S
:
1896 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
1897 | bfd_getl32 (buf
), buf
);
1898 if (fixP
->fx_addsy
== NULL
)
1899 fixP
->fx_done
= TRUE
;
1903 case BFD_RELOC_RISCV_GOT_HI20
:
1904 case BFD_RELOC_RISCV_ADD8
:
1905 case BFD_RELOC_RISCV_ADD16
:
1906 case BFD_RELOC_RISCV_ADD32
:
1907 case BFD_RELOC_RISCV_ADD64
:
1908 case BFD_RELOC_RISCV_SUB6
:
1909 case BFD_RELOC_RISCV_SUB8
:
1910 case BFD_RELOC_RISCV_SUB16
:
1911 case BFD_RELOC_RISCV_SUB32
:
1912 case BFD_RELOC_RISCV_SUB64
:
1913 case BFD_RELOC_RISCV_RELAX
:
1916 case BFD_RELOC_RISCV_TPREL_HI20
:
1917 case BFD_RELOC_RISCV_TPREL_LO12_I
:
1918 case BFD_RELOC_RISCV_TPREL_LO12_S
:
1919 case BFD_RELOC_RISCV_TPREL_ADD
:
1923 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
1924 case BFD_RELOC_RISCV_TLS_GD_HI20
:
1925 case BFD_RELOC_RISCV_TLS_DTPREL32
:
1926 case BFD_RELOC_RISCV_TLS_DTPREL64
:
1927 if (fixP
->fx_addsy
!= NULL
)
1928 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
1930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
1931 _("TLS relocation against a constant"));
1935 /* Use pc-relative relocation for FDE initial location.
1936 The symbol address in .eh_frame may be adjusted in
1937 _bfd_elf_discard_section_eh_frame, and the content of
1938 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
1939 Therefore, we cannot insert a relocation whose addend symbol is
1940 in .eh_frame. Othrewise, the value may be adjusted twice.*/
1941 if (fixP
->fx_addsy
&& fixP
->fx_subsy
1942 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
1943 && strcmp (sub_segment
->name
, ".eh_frame") == 0
1944 && S_GET_VALUE (fixP
->fx_subsy
)
1945 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
1947 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
1948 fixP
->fx_subsy
= NULL
;
1955 case BFD_RELOC_RISCV_CFA
:
1956 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
1958 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
1959 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
1960 fixP
->fx_next
->fx_subsy
= NULL
;
1961 fixP
->fx_next
->fx_offset
= 0;
1962 fixP
->fx_subsy
= NULL
;
1964 switch (fixP
->fx_r_type
)
1967 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
1968 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
1972 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
1973 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
1977 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
1978 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
1982 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
1983 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1986 case BFD_RELOC_RISCV_CFA
:
1987 /* Load the byte to get the subtype. */
1988 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
1989 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
1992 case DW_CFA_advance_loc1
:
1993 fixP
->fx_where
= loc
+ 1;
1994 fixP
->fx_next
->fx_where
= loc
+ 1;
1995 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
1996 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
1999 case DW_CFA_advance_loc2
:
2001 fixP
->fx_next
->fx_size
= 2;
2002 fixP
->fx_where
= loc
+ 1;
2003 fixP
->fx_next
->fx_where
= loc
+ 1;
2004 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2005 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2008 case DW_CFA_advance_loc4
:
2010 fixP
->fx_next
->fx_size
= 4;
2011 fixP
->fx_where
= loc
;
2012 fixP
->fx_next
->fx_where
= loc
;
2013 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2014 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2018 if (subtype
< 0x80 && (subtype
& 0x40))
2020 /* DW_CFA_advance_loc */
2021 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2022 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2023 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2024 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2027 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2033 /* This case is unreachable. */
2040 /* If we are deleting this reloc entry, we must fill in the
2041 value now. This can happen if we have a .word which is not
2042 resolved when it appears but is later defined. */
2043 if (fixP
->fx_addsy
== NULL
)
2045 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2046 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2051 case BFD_RELOC_RISCV_JMP
:
2054 /* Fill in a tentative value to improve objdump readability. */
2055 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2056 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2057 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2061 case BFD_RELOC_12_PCREL
:
2064 /* Fill in a tentative value to improve objdump readability. */
2065 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2066 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2067 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2071 case BFD_RELOC_RISCV_RVC_BRANCH
:
2074 /* Fill in a tentative value to improve objdump readability. */
2075 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2076 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2077 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2081 case BFD_RELOC_RISCV_RVC_JUMP
:
2084 /* Fill in a tentative value to improve objdump readability. */
2085 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2086 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2087 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2091 case BFD_RELOC_RISCV_CALL
:
2092 case BFD_RELOC_RISCV_CALL_PLT
:
2096 case BFD_RELOC_RISCV_PCREL_HI20
:
2097 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2098 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2099 relaxable
= riscv_opts
.relax
;
2102 case BFD_RELOC_RISCV_ALIGN
:
2106 /* We ignore generic BFD relocations we don't know about. */
2107 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2108 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2111 if (fixP
->fx_subsy
!= NULL
)
2112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2113 _("unsupported symbol subtraction"));
2115 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2116 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2118 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2119 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2120 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2124 /* Because the value of .cfi_remember_state may changed after relaxation,
2125 we insert a fix to relocate it again in link-time. */
2128 riscv_pre_output_hook (void)
2130 const frchainS
*frch
;
2133 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2134 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2138 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2140 if (frag
->fr_type
== rs_cfa
)
2144 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2145 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2147 exp
.X_op
= O_subtract
;
2148 exp
.X_add_symbol
= add_symbol
;
2149 exp
.X_add_number
= 0;
2150 exp
.X_op_symbol
= op_symbol
;
2152 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2153 BFD_RELOC_RISCV_CFA
);
2160 /* This structure is used to hold a stack of .option values. */
2162 struct riscv_option_stack
2164 struct riscv_option_stack
*next
;
2165 struct riscv_set_options options
;
2168 static struct riscv_option_stack
*riscv_opts_stack
;
2170 /* Handle the .option pseudo-op. */
2173 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2175 char *name
= input_line_pointer
, ch
;
2177 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2178 ++input_line_pointer
;
2179 ch
= *input_line_pointer
;
2180 *input_line_pointer
= '\0';
2182 if (strcmp (name
, "rvc") == 0)
2183 riscv_set_rvc (TRUE
);
2184 else if (strcmp (name
, "norvc") == 0)
2185 riscv_set_rvc (FALSE
);
2186 else if (strcmp (name
, "pic") == 0)
2187 riscv_opts
.pic
= TRUE
;
2188 else if (strcmp (name
, "nopic") == 0)
2189 riscv_opts
.pic
= FALSE
;
2190 else if (strcmp (name
, "relax") == 0)
2191 riscv_opts
.relax
= TRUE
;
2192 else if (strcmp (name
, "norelax") == 0)
2193 riscv_opts
.relax
= FALSE
;
2194 else if (strcmp (name
, "push") == 0)
2196 struct riscv_option_stack
*s
;
2198 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2199 s
->next
= riscv_opts_stack
;
2200 s
->options
= riscv_opts
;
2201 riscv_opts_stack
= s
;
2203 else if (strcmp (name
, "pop") == 0)
2205 struct riscv_option_stack
*s
;
2207 s
= riscv_opts_stack
;
2209 as_bad (_(".option pop with no .option push"));
2212 riscv_opts
= s
->options
;
2213 riscv_opts_stack
= s
->next
;
2219 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2221 *input_line_pointer
= ch
;
2222 demand_empty_rest_of_line ();
2225 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2226 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2227 use in DWARF debug information. */
2230 s_dtprel (int bytes
)
2237 if (ex
.X_op
!= O_symbol
)
2239 as_bad (_("Unsupported use of %s"), (bytes
== 8
2242 ignore_rest_of_line ();
2245 p
= frag_more (bytes
);
2246 md_number_to_chars (p
, 0, bytes
);
2247 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2249 ? BFD_RELOC_RISCV_TLS_DTPREL64
2250 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2252 demand_empty_rest_of_line ();
2255 /* Handle the .bss pseudo-op. */
2258 s_bss (int ignore ATTRIBUTE_UNUSED
)
2260 subseg_set (bss_section
, 0);
2261 demand_empty_rest_of_line ();
2265 riscv_make_nops (char *buf
, bfd_vma bytes
)
2269 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2270 means we are not within a valid instruction sequence. It is thus safe
2271 to use a zero byte, even though that is not a valid instruction. */
2275 /* Use at most one 2-byte NOP. */
2276 if ((bytes
- i
) % 4 == 2)
2278 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2282 /* Fill the remainder with 4-byte NOPs. */
2283 for ( ; i
< bytes
; i
+= 4)
2284 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2287 /* Called from md_do_align. Used to create an alignment frag in a
2288 code section by emitting a worst-case NOP sequence that the linker
2289 will later relax to the correct number of NOPs. We can't compute
2290 the correct alignment now because of other linker relaxations. */
2293 riscv_frag_align_code (int n
)
2295 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2296 bfd_vma worst_case_bytes
= bytes
- (riscv_opts
.rvc
? 2 : 4);
2297 char *nops
= frag_more (worst_case_bytes
);
2300 /* When not relaxing, riscv_handle_align handles code alignment. */
2301 if (!riscv_opts
.relax
)
2304 ex
.X_op
= O_constant
;
2305 ex
.X_add_number
= worst_case_bytes
;
2307 riscv_make_nops (nops
, worst_case_bytes
);
2309 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2310 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2315 /* Implement HANDLE_ALIGN. */
2318 riscv_handle_align (fragS
*fragP
)
2320 switch (fragP
->fr_type
)
2323 /* When relaxing, riscv_frag_align_code handles code alignment. */
2324 if (!riscv_opts
.relax
)
2326 bfd_signed_vma count
= fragP
->fr_next
->fr_address
2327 - fragP
->fr_address
- fragP
->fr_fix
;
2332 count
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
2333 riscv_make_nops (fragP
->fr_literal
+ fragP
->fr_fix
, count
);
2334 fragP
->fr_var
= count
;
2344 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2346 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2349 /* Translate internal representation of relocation info to BFD target
2353 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2355 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2357 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2358 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2359 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2360 reloc
->addend
= fixp
->fx_addnumber
;
2362 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2363 if (reloc
->howto
== NULL
)
2365 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2366 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2368 /* We don't have R_RISCV_8/16, but for this special case,
2369 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2373 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2374 _("cannot represent %s relocation in object file"),
2375 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2383 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2385 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2387 offsetT old_var
= fragp
->fr_var
;
2388 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2389 return fragp
->fr_var
- old_var
;
2395 /* Expand far branches to multi-instruction sequences. */
2398 md_convert_frag_branch (fragS
*fragp
)
2406 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2408 exp
.X_op
= O_symbol
;
2409 exp
.X_add_symbol
= fragp
->fr_symbol
;
2410 exp
.X_add_number
= fragp
->fr_offset
;
2412 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2414 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2416 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2420 /* Expand the RVC branch into a RISC-V one. */
2421 insn
= bfd_getl16 (buf
);
2422 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2423 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2425 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2426 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2427 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2428 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2429 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2430 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2433 bfd_putl32 (insn
, buf
);
2437 /* Invert the branch condition. Branch over the jump. */
2438 insn
= bfd_getl16 (buf
);
2439 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2440 insn
|= ENCODE_RVC_B_IMM (6);
2441 bfd_putl16 (insn
, buf
);
2446 /* Just keep the RVC branch. */
2447 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2448 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2449 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2450 2, &exp
, FALSE
, reloc
);
2459 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2462 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2464 /* Invert the branch condition. Branch over the jump. */
2465 insn
= bfd_getl32 (buf
);
2466 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2467 insn
|= ENCODE_SBTYPE_IMM (8);
2468 md_number_to_chars ((char *) buf
, insn
, 4);
2472 /* Jump to the target. */
2473 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2474 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2475 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2480 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2481 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2482 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2483 4, &exp
, FALSE
, reloc
);
2492 fixp
->fx_file
= fragp
->fr_file
;
2493 fixp
->fx_line
= fragp
->fr_line
;
2495 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2496 + fragp
->fr_fix
+ fragp
->fr_var
);
2498 fragp
->fr_fix
+= fragp
->fr_var
;
2501 /* Relax a machine dependent frag. This returns the amount by which
2502 the current size of the frag should change. */
2505 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2508 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2509 md_convert_frag_branch (fragp
);
2513 md_show_usage (FILE *stream
)
2515 fprintf (stream
, _("\
2517 -fpic generate position-independent code\n\
2518 -fno-pic don't generate position-independent code (default)\n\
2519 -march=ISA set the RISC-V architecture\n\
2520 -mabi=ABI set the RISC-V ABI\n\
2524 /* Standard calling conventions leave the CFA at SP on entry. */
2526 riscv_cfi_frame_initial_instructions (void)
2528 cfi_add_CFA_def_cfa_register (X_SP
);
2532 tc_riscv_regname_to_dw2regnum (char *regname
)
2536 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2539 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2542 as_bad (_("unknown register `%s'"), regname
);
2547 riscv_elf_final_processing (void)
2549 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2552 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2553 since these directives break relaxation when used with symbol deltas. */
2556 s_riscv_leb128 (int sign
)
2559 char *save_in
= input_line_pointer
;
2562 if (exp
.X_op
!= O_constant
)
2563 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2564 demand_empty_rest_of_line ();
2566 input_line_pointer
= save_in
;
2567 return s_leb128 (sign
);
2570 /* Pseudo-op table. */
2572 static const pseudo_typeS riscv_pseudo_table
[] =
2574 /* RISC-V-specific pseudo-ops. */
2575 {"option", s_riscv_option
, 0},
2579 {"dtprelword", s_dtprel
, 4},
2580 {"dtpreldword", s_dtprel
, 8},
2582 {"uleb128", s_riscv_leb128
, 0},
2583 {"sleb128", s_riscv_leb128
, 1},
2589 riscv_pop_insert (void)
2591 extern void pop_insert (const pseudo_typeS
*);
2593 pop_insert (riscv_pseudo_table
);