1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2018 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
31 #include "struc-symbol.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 static const char default_arch
[] = DEFAULT_ARCH
;
64 static unsigned xlen
= 0; /* width of an x-register */
65 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
67 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
68 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
70 static unsigned elf_flags
= 0;
72 /* This is the set of options which the .option pseudo-op may modify. */
74 struct riscv_set_options
76 int pic
; /* Generate position-independent code. */
77 int rvc
; /* Generate RVC code. */
78 int relax
; /* Emit relocs the linker is allowed to relax. */
81 static struct riscv_set_options riscv_opts
=
89 riscv_set_rvc (bfd_boolean rvc_value
)
92 elf_flags
|= EF_RISCV_RVC
;
94 riscv_opts
.rvc
= rvc_value
;
101 struct riscv_subset
*next
;
104 static struct riscv_subset
*riscv_subsets
;
107 riscv_subset_supports (const char *feature
)
109 struct riscv_subset
*s
;
111 unsigned xlen_required
= strtoul (feature
, &p
, 10);
113 if (xlen_required
&& xlen
!= xlen_required
)
116 for (s
= riscv_subsets
; s
!= NULL
; s
= s
->next
)
117 if (strcasecmp (s
->name
, p
) == 0)
124 riscv_clear_subsets (void)
126 while (riscv_subsets
!= NULL
)
128 struct riscv_subset
*next
= riscv_subsets
->next
;
129 free ((void *) riscv_subsets
->name
);
130 free (riscv_subsets
);
131 riscv_subsets
= next
;
136 riscv_add_subset (const char *subset
)
138 struct riscv_subset
*s
= xmalloc (sizeof *s
);
140 s
->name
= xstrdup (subset
);
141 s
->next
= riscv_subsets
;
145 /* Set which ISA and extensions are available. */
148 riscv_set_arch (const char *s
)
150 const char *all_subsets
= "imafdqc";
151 char *extension
= NULL
;
154 riscv_clear_subsets();
156 if (strncmp (p
, "rv32", 4) == 0)
161 else if (strncmp (p
, "rv64", 4) == 0)
167 as_fatal ("-march=%s: ISA string must begin with rv32 or rv64", s
);
176 for ( ; *all_subsets
!= 'q'; all_subsets
++)
178 const char subset
[] = {*all_subsets
, '\0'};
179 riscv_add_subset (subset
);
184 as_fatal ("-march=%s: first ISA subset must be `i' or `g'", s
);
191 char *subset
= xstrdup (p
);
194 while (*++q
!= '\0' && *q
!= '_')
199 as_fatal ("-march=%s: only one non-standard extension is supported"
200 " (found `%s' and `%s')", s
, extension
, subset
);
202 riscv_add_subset (subset
);
203 p
+= strlen (subset
);
207 else if ((all_subsets
= strchr (all_subsets
, *p
)) != NULL
)
209 const char subset
[] = {*p
, 0};
210 riscv_add_subset (subset
);
215 as_fatal ("-march=%s: unsupported ISA subset `%c'", s
, *p
);
221 /* Handle of the OPCODE hash table. */
222 static struct hash_control
*op_hash
= NULL
;
224 /* Handle of the type of .insn hash table. */
225 static struct hash_control
*insn_type_hash
= NULL
;
227 /* This array holds the chars that always start a comment. If the
228 pre-processor is disabled, these aren't very useful */
229 const char comment_chars
[] = "#";
231 /* This array holds the chars that only start a comment at the beginning of
232 a line. If the line seems to have the form '# 123 filename'
233 .line and .file directives will appear in the pre-processed output */
234 /* Note that input_file.c hand checks for '#' at the beginning of the
235 first line of the input file. This is because the compiler outputs
236 #NO_APP at the beginning of its output. */
237 /* Also note that C style comments are always supported. */
238 const char line_comment_chars
[] = "#";
240 /* This array holds machine specific line separator characters. */
241 const char line_separator_chars
[] = ";";
243 /* Chars that can be used to separate mant from exp in floating point nums */
244 const char EXP_CHARS
[] = "eE";
246 /* Chars that mean this number is a floating point constant */
249 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
251 /* Macros for encoding relaxation state for RVC branches and far jumps. */
252 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
255 | ((uncond) ? 1 : 0) \
258 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
259 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
260 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
261 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
263 /* Is the given value a sign-extended 32-bit value? */
264 #define IS_SEXT_32BIT_NUM(x) \
265 (((x) &~ (offsetT) 0x7fffffff) == 0 \
266 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
268 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
269 #define IS_ZEXT_32BIT_NUM(x) \
270 (((x) &~ (offsetT) 0xffffffff) == 0 \
271 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
273 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
274 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
275 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
276 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
278 /* Determine if an instruction matches an opcode. */
279 #define OPCODE_MATCHES(OPCODE, OP) \
280 (((OPCODE) & MASK_##OP) == MATCH_##OP)
282 static char *expr_end
;
284 /* The default target format to use. */
287 riscv_target_format (void)
289 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
292 /* Return the length of instruction INSN. */
294 static inline unsigned int
295 insn_length (const struct riscv_cl_insn
*insn
)
297 return riscv_insn_length (insn
->insn_opcode
);
300 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
303 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
306 insn
->insn_opcode
= mo
->match
;
312 /* Install INSN at the location specified by its "frag" and "where" fields. */
315 install_insn (const struct riscv_cl_insn
*insn
)
317 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
318 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
321 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
322 and install the opcode in the new location. */
325 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
329 if (insn
->fixp
!= NULL
)
331 insn
->fixp
->fx_frag
= frag
;
332 insn
->fixp
->fx_where
= where
;
337 /* Add INSN to the end of the output. */
340 add_fixed_insn (struct riscv_cl_insn
*insn
)
342 char *f
= frag_more (insn_length (insn
));
343 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
347 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
348 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
350 frag_grow (max_chars
);
351 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
352 frag_var (rs_machine_dependent
, max_chars
, var
,
353 subtype
, symbol
, offset
, NULL
);
356 /* Compute the length of a branch sequence, and adjust the stored length
357 accordingly. If FRAGP is NULL, the worst-case length is returned. */
360 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
362 int jump
, rvc
, length
= 8;
367 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
368 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
369 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
371 /* Assume jumps are in range; the linker will catch any that aren't. */
372 length
= jump
? 4 : 8;
374 if (fragp
->fr_symbol
!= NULL
375 && S_IS_DEFINED (fragp
->fr_symbol
)
376 && !S_IS_WEAK (fragp
->fr_symbol
)
377 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
379 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
380 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
381 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
383 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
385 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
387 else if (!jump
&& rvc
)
392 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
397 /* Information about an opcode name, mnemonics and its value. */
404 /* List for all supported opcode name. */
405 static const struct opcode_name_t opcode_name_list
[] =
450 /* Hash table for lookup opcode name. */
451 static struct hash_control
*opcode_names_hash
= NULL
;
453 /* Initialization for hash table of opcode name. */
455 init_opcode_names_hash (void)
458 const struct opcode_name_t
*opcode
;
460 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
462 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
465 as_fatal (_("internal error: can't hash `%s': %s"),
466 opcode
->name
, retval
);
470 /* Find `s` is a valid opcode name or not,
471 return the opcode name info if found. */
472 static const struct opcode_name_t
*
473 opcode_name_lookup (char **s
)
477 struct opcode_name_t
*o
;
479 /* Find end of name. */
481 if (is_name_beginner (*e
))
483 while (is_part_of_name (*e
))
486 /* Terminate name. */
490 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
492 /* Advance to next token if one was recognized. */
516 static struct hash_control
*reg_names_hash
= NULL
;
518 #define ENCODE_REG_HASH(cls, n) \
519 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
520 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
521 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
524 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
526 void *hash
= ENCODE_REG_HASH (class, n
);
527 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
530 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
534 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
538 for (i
= 0; i
< n
; i
++)
539 hash_reg_name (class, names
[i
], i
);
543 reg_lookup_internal (const char *s
, enum reg_class
class)
545 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
547 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
549 return DECODE_REG_NUM (r
);
553 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
559 /* Find end of name. */
561 if (is_name_beginner (*e
))
563 while (is_part_of_name (*e
))
566 /* Terminate name. */
570 /* Look for the register. Advance to next token if one was recognized. */
571 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
581 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
583 const char *p
= strchr (*s
, ',');
584 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
586 for (i
= 0; i
< size
; i
++)
587 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
597 /* For consistency checking, verify that all bits are specified either
598 by the match/mask part of the instruction definition, or by the
601 `length` could be 0, 4 or 8, 0 for auto detection. */
603 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
605 const char *p
= opc
->args
;
607 insn_t used_bits
= opc
->mask
;
609 insn_t required_bits
;
612 insn_width
= 8 * riscv_insn_length (opc
->match
);
614 insn_width
= 8 * length
;
616 required_bits
= ~0ULL >> (64 - insn_width
);
618 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
620 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
621 opc
->name
, opc
->args
);
625 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
632 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
633 case 'c': break; /* RS1, constrained to equal sp */
634 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
635 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
636 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
637 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
638 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
639 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
640 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
641 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
642 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
643 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
644 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
645 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
646 case 'w': break; /* RS1S, constrained to equal RD */
647 case 'x': break; /* RS2S, constrained to equal RD */
648 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
649 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
650 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
651 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
652 case 'U': break; /* RS1, constrained to equal RD */
653 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
654 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
655 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
656 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
657 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
658 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
659 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
660 case 'F': /* funct */
663 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
664 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
666 as_bad (_("internal: bad RISC-V opcode"
667 " (unknown operand type `CF%c'): %s %s"),
668 c
, opc
->name
, opc
->args
);
673 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
674 c
, opc
->name
, opc
->args
);
681 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
682 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
684 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
685 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
686 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
688 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
689 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
690 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
691 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
692 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
693 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
694 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
695 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
696 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
697 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
698 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
700 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
701 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
702 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
703 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
704 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
709 case 'F': /* funct */
712 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
713 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
714 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
716 as_bad (_("internal: bad RISC-V opcode"
717 " (unknown operand type `F%c'): %s %s"),
718 c
, opc
->name
, opc
->args
);
722 case 'O': /* opcode */
725 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
726 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
728 as_bad (_("internal: bad RISC-V opcode"
729 " (unknown operand type `F%c'): %s %s"),
730 c
, opc
->name
, opc
->args
);
735 as_bad (_("internal: bad RISC-V opcode "
736 "(unknown operand type `%c'): %s %s"),
737 c
, opc
->name
, opc
->args
);
741 if (used_bits
!= required_bits
)
743 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
744 ~(unsigned long)(used_bits
& required_bits
),
745 opc
->name
, opc
->args
);
751 struct percent_op_match
754 bfd_reloc_code_real_type reloc
;
757 /* Common hash table initialization function for
758 instruction and .insn directive. */
759 static struct hash_control
*
760 init_opcode_hash (const struct riscv_opcode
*opcodes
,
761 bfd_boolean insn_directive_p
)
765 struct hash_control
*hash
= hash_new ();
766 while (opcodes
[i
].name
)
768 const char *name
= opcodes
[i
].name
;
769 const char *hash_error
=
770 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
774 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
775 opcodes
[i
].name
, hash_error
);
776 /* Probably a memory allocation problem? Give up now. */
777 as_fatal (_("Broken assembler. No assembly attempted."));
782 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
784 if (insn_directive_p
)
785 length
= ((name
[0] == 'c') ? 2 : 4);
787 length
= 0; /* Let assembler determine the length. */
788 if (!validate_riscv_insn (&opcodes
[i
], length
))
789 as_fatal (_("Broken assembler. No assembly attempted."));
792 gas_assert (!insn_directive_p
);
795 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
801 /* This function is called once, at assembler startup time. It should set up
802 all the tables, etc. that the MD part of the assembler will need. */
807 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
809 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
810 as_warn (_("Could not set architecture and machine"));
812 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
813 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
815 reg_names_hash
= hash_new ();
816 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
817 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
818 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
819 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
821 opcode_names_hash
= hash_new ();
822 init_opcode_names_hash ();
824 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
825 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
826 #include "opcode/riscv-opc.h"
829 /* Set the default alignment for the text section. */
830 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
834 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
841 case BFD_RELOC_RISCV_HI20
:
842 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
844 case BFD_RELOC_RISCV_LO12_S
:
845 return ENCODE_STYPE_IMM (value
);
847 case BFD_RELOC_RISCV_LO12_I
:
848 return ENCODE_ITYPE_IMM (value
);
855 /* Output an instruction. IP is the instruction information.
856 ADDRESS_EXPR is an operand of the instruction to be used with
860 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
861 bfd_reloc_code_real_type reloc_type
)
863 dwarf2_emit_insn (0);
865 if (reloc_type
!= BFD_RELOC_UNUSED
)
867 reloc_howto_type
*howto
;
869 gas_assert (address_expr
);
870 if (reloc_type
== BFD_RELOC_12_PCREL
871 || reloc_type
== BFD_RELOC_RISCV_JMP
)
873 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
874 int best_case
= riscv_insn_length (ip
->insn_opcode
);
875 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
876 add_relaxed_insn (ip
, worst_case
, best_case
,
877 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
878 address_expr
->X_add_symbol
,
879 address_expr
->X_add_number
);
884 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
886 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
888 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
889 bfd_get_reloc_size (howto
),
890 address_expr
, FALSE
, reloc_type
);
892 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
899 /* We need to start a new frag after any instruction that can be
900 optimized away or compressed by the linker during relaxation, to prevent
901 the assembler from computing static offsets across such an instruction.
902 This is necessary to get correct EH info. */
903 if (reloc_type
== BFD_RELOC_RISCV_CALL
904 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
905 || reloc_type
== BFD_RELOC_RISCV_HI20
906 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
907 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
908 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
910 frag_wane (frag_now
);
915 /* Build an instruction created by a macro expansion. This is passed
916 a pointer to the count of instructions created so far, an
917 expression, the name of the instruction to build, an operand format
918 string, and corresponding arguments. */
921 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
923 const struct riscv_opcode
*mo
;
924 struct riscv_cl_insn insn
;
925 bfd_reloc_code_real_type r
;
928 va_start (args
, fmt
);
930 r
= BFD_RELOC_UNUSED
;
931 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
934 /* Find a non-RVC variant of the instruction. append_insn will compress
936 while (riscv_insn_length (mo
->match
) < 4)
938 gas_assert (strcmp (name
, mo
->name
) == 0);
940 create_insn (&insn
, mo
);
946 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
950 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
954 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
958 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
964 gas_assert (ep
!= NULL
);
965 r
= va_arg (args
, int);
973 as_fatal (_("internal error: invalid macro"));
978 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
980 append_insn (&insn
, ep
, r
);
983 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
986 normalize_constant_expr (expressionS
*ex
)
990 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
991 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
992 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
996 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
997 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1000 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1001 bfd_boolean maybe_csr
)
1003 if (ex
->X_op
== O_big
)
1004 as_bad (_("unsupported large constant"));
1005 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1006 as_bad (_("unknown CSR `%s'"),
1007 S_GET_NAME (ex
->X_add_symbol
));
1008 else if (ex
->X_op
!= O_constant
)
1009 as_bad (_("Instruction %s requires absolute expression"),
1011 normalize_constant_expr (ex
);
1015 make_internal_label (void)
1017 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1018 (valueT
) frag_now_fix (), frag_now
);
1021 /* Load an entry from the GOT. */
1023 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1024 const char *lo_insn
, const char *lo_pattern
,
1025 bfd_reloc_code_real_type hi_reloc
,
1026 bfd_reloc_code_real_type lo_reloc
)
1029 ep2
.X_op
= O_symbol
;
1030 ep2
.X_add_symbol
= make_internal_label ();
1031 ep2
.X_add_number
= 0;
1033 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1034 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1038 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1039 bfd_reloc_code_real_type hi_reloc
,
1040 bfd_reloc_code_real_type lo_reloc
)
1042 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1046 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1047 bfd_reloc_code_real_type hi_reloc
,
1048 bfd_reloc_code_real_type lo_reloc
)
1050 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1053 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1055 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1056 bfd_reloc_code_real_type reloc
)
1058 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1059 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1062 /* Load an integer constant into a register. */
1065 load_const (int reg
, expressionS
*ep
)
1067 int shift
= RISCV_IMM_BITS
;
1068 expressionS upper
= *ep
, lower
= *ep
;
1069 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1070 upper
.X_add_number
-= lower
.X_add_number
;
1072 if (ep
->X_op
!= O_constant
)
1074 as_bad (_("unsupported large constant"));
1078 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1080 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1081 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1084 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1085 load_const (reg
, &upper
);
1087 macro_build (NULL
, "slli", "d,s,>", reg
, reg
, shift
);
1088 if (lower
.X_add_number
!= 0)
1089 macro_build (&lower
, "addi", "d,s,j", reg
, reg
, BFD_RELOC_RISCV_LO12_I
);
1093 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1096 if (upper
.X_add_number
!= 0)
1098 macro_build (ep
, "lui", "d,u", reg
, BFD_RELOC_RISCV_HI20
);
1102 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1103 macro_build (ep
, ADD32_INSN
, "d,s,j", reg
, hi_reg
,
1104 BFD_RELOC_RISCV_LO12_I
);
1108 /* Expand RISC-V assembly macros into one or more instructions. */
1110 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1111 bfd_reloc_code_real_type
*imm_reloc
)
1113 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1114 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1115 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1116 int mask
= ip
->insn_mo
->mask
;
1121 load_const (rd
, imm_expr
);
1126 /* Load the address of a symbol into a register. */
1127 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1128 as_bad (_("offset too large"));
1130 if (imm_expr
->X_op
== O_constant
)
1131 load_const (rd
, imm_expr
);
1132 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1133 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1134 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1135 else /* Local PIC symbol, or any non-PIC symbol */
1136 pcrel_load (rd
, rd
, imm_expr
, "addi",
1137 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1141 pcrel_load (rd
, rd
, imm_expr
, "addi",
1142 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1146 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1147 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1151 pcrel_load (rd
, rd
, imm_expr
, "lb",
1152 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1156 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1157 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1161 pcrel_load (rd
, rd
, imm_expr
, "lh",
1162 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1166 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1167 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1171 pcrel_load (rd
, rd
, imm_expr
, "lw",
1172 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1176 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1177 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1181 pcrel_load (rd
, rd
, imm_expr
, "ld",
1182 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1186 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1187 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1191 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1192 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1196 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1197 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1201 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1202 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1206 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1207 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1211 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1212 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1216 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1217 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1221 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1222 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1226 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1230 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1235 static const struct percent_op_match percent_op_utype
[] =
1237 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1238 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1239 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1240 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1241 {"%hi", BFD_RELOC_RISCV_HI20
},
1245 static const struct percent_op_match percent_op_itype
[] =
1247 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1248 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1249 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1253 static const struct percent_op_match percent_op_stype
[] =
1255 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1256 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1257 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1261 static const struct percent_op_match percent_op_rtype
[] =
1263 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1267 /* Return true if *STR points to a relocation operator. When returning true,
1268 move *STR over the operator and store its relocation code in *RELOC.
1269 Leave both *STR and *RELOC alone when returning false. */
1272 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1273 const struct percent_op_match
*percent_op
)
1275 for ( ; percent_op
->str
; percent_op
++)
1276 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1278 int len
= strlen (percent_op
->str
);
1280 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1283 *str
+= strlen (percent_op
->str
);
1284 *reloc
= percent_op
->reloc
;
1286 /* Check whether the output BFD supports this relocation.
1287 If not, issue an error and fall back on something safe. */
1288 if (*reloc
!= BFD_RELOC_UNUSED
1289 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1291 as_bad ("relocation %s isn't supported by the current ABI",
1293 *reloc
= BFD_RELOC_UNUSED
;
1301 my_getExpression (expressionS
*ep
, char *str
)
1305 save_in
= input_line_pointer
;
1306 input_line_pointer
= str
;
1308 expr_end
= input_line_pointer
;
1309 input_line_pointer
= save_in
;
1312 /* Parse string STR as a 16-bit relocatable operand. Store the
1313 expression in *EP and the relocation, if any, in RELOC.
1314 Return the number of relocation operators used (0 or 1).
1316 On exit, EXPR_END points to the first character after the expression. */
1319 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1320 char *str
, const struct percent_op_match
*percent_op
)
1323 unsigned crux_depth
, str_depth
, regno
;
1326 /* First, check for integer registers. */
1327 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1329 ep
->X_op
= O_register
;
1330 ep
->X_add_number
= regno
;
1334 /* Search for the start of the main expression.
1335 End the loop with CRUX pointing to the start
1336 of the main expression and with CRUX_DEPTH containing the number
1337 of open brackets at that point. */
1344 crux_depth
= str_depth
;
1346 /* Skip over whitespace and brackets, keeping count of the number
1348 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1354 && parse_relocation (&str
, reloc
, percent_op
));
1356 my_getExpression (ep
, crux
);
1359 /* Match every open bracket. */
1360 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1365 as_bad ("unclosed '('");
1372 /* Parse opcode name, could be an mnemonics or number. */
1374 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1375 char *str
, const struct percent_op_match
*percent_op
)
1377 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1381 ep
->X_op
= O_constant
;
1382 ep
->X_add_number
= o
->val
;
1386 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1389 /* Detect and handle implicitly zero load-store offsets. For example,
1390 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1391 an implicit offset was detected. */
1394 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1396 /* Check whether there is only a single bracketed expression left.
1397 If so, it must be the base register and the constant must be zero. */
1398 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1400 ep
->X_op
= O_constant
;
1401 ep
->X_add_number
= 0;
1408 /* This routine assembles an instruction into its binary format. As a
1409 side effect, it sets the global variable imm_reloc to the type of
1410 relocation to do if one of the operands is an address expression. */
1413 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1414 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1419 struct riscv_opcode
*insn
;
1424 const struct percent_op_match
*p
;
1425 const char *error
= "unrecognized opcode";
1427 /* Parse the name of the instruction. Terminate the string if whitespace
1428 is found so that hash_find only sees the name part of the string. */
1429 for (s
= str
; *s
!= '\0'; ++s
)
1437 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1440 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1442 if (!riscv_subset_supports (insn
->subset
))
1445 create_insn (ip
, insn
);
1448 imm_expr
->X_op
= O_absent
;
1449 *imm_reloc
= BFD_RELOC_UNUSED
;
1450 p
= percent_op_itype
;
1452 for (args
= insn
->args
;; ++args
)
1454 s
+= strspn (s
, " \t");
1457 case '\0': /* End of args. */
1458 if (insn
->pinfo
!= INSN_MACRO
)
1460 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1463 /* For .insn, insn->match and insn->mask are 0. */
1464 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1472 /* Successful assembly. */
1479 case 's': /* RS1 x8-x15 */
1480 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1481 || !(regno
>= 8 && regno
<= 15))
1483 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1485 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1486 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1487 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1490 case 't': /* RS2 x8-x15 */
1491 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1492 || !(regno
>= 8 && regno
<= 15))
1494 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1496 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1497 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1498 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1501 case 'U': /* RS1, constrained to equal RD. */
1502 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1503 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1507 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1509 INSERT_OPERAND (CRS2
, *ip
, regno
);
1511 case 'c': /* RS1, constrained to equal sp. */
1512 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1517 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1518 || imm_expr
->X_op
!= O_constant
1519 || imm_expr
->X_add_number
<= 0
1520 || imm_expr
->X_add_number
>= 64)
1522 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1525 imm_expr
->X_op
= O_absent
;
1528 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1529 || imm_expr
->X_op
!= O_constant
1530 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1531 || imm_expr
->X_add_number
<= 0
1532 || imm_expr
->X_add_number
>= 32)
1534 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1537 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1538 || imm_expr
->X_op
!= O_constant
1539 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1540 || imm_expr
->X_add_number
< 0
1541 || imm_expr
->X_add_number
>= 256)
1543 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1546 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1547 || imm_expr
->X_op
!= O_constant
1548 || imm_expr
->X_add_number
== 0
1549 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1551 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1554 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1555 || imm_expr
->X_op
!= O_constant
1556 || imm_expr
->X_add_number
== 0
1557 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1559 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1562 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1564 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1565 || imm_expr
->X_op
!= O_constant
1566 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1568 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1571 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1573 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1574 || imm_expr
->X_op
!= O_constant
1575 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1577 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1580 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1582 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1583 || imm_expr
->X_op
!= O_constant
1584 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1587 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1590 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1592 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1593 || imm_expr
->X_op
!= O_constant
1594 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1597 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1600 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1601 || imm_expr
->X_op
!= O_constant
1602 /* C.addiw, c.li, and c.andi allow zero immediate.
1603 C.addi allows zero immediate as hint. Otherwise this
1605 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1607 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1610 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1611 || imm_expr
->X_op
!= O_constant
1612 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1613 || imm_expr
->X_add_number
== 0)
1616 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1619 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1620 || imm_expr
->X_op
!= O_constant
1621 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1622 || imm_expr
->X_add_number
== 0)
1625 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1628 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1630 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1631 || imm_expr
->X_op
!= O_constant
1632 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1635 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1638 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1640 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1641 || imm_expr
->X_op
!= O_constant
1642 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1645 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1648 p
= percent_op_utype
;
1649 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1652 if (imm_expr
->X_op
!= O_constant
1653 || imm_expr
->X_add_number
<= 0
1654 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1655 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1656 && (imm_expr
->X_add_number
<
1657 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1659 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1662 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1663 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1664 || ((int32_t)imm_expr
->X_add_number
1665 != imm_expr
->X_add_number
))
1667 imm_expr
->X_add_number
=
1668 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1674 case 'S': /* Floating-point RS1 x8-x15. */
1675 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1676 || !(regno
>= 8 && regno
<= 15))
1678 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1680 case 'D': /* Floating-point RS2 x8-x15. */
1681 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1682 || !(regno
>= 8 && regno
<= 15))
1684 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1686 case 'T': /* Floating-point RS2. */
1687 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1689 INSERT_OPERAND (CRS2
, *ip
, regno
);
1695 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1696 || imm_expr
->X_op
!= O_constant
1697 || imm_expr
->X_add_number
< 0
1698 || imm_expr
->X_add_number
>= 16)
1700 as_bad (_("bad value for funct4 field, "
1701 "value must be 0...15"));
1705 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1706 imm_expr
->X_op
= O_absent
;
1710 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1711 || imm_expr
->X_op
!= O_constant
1712 || imm_expr
->X_add_number
< 0
1713 || imm_expr
->X_add_number
>= 8)
1715 as_bad (_("bad value for funct3 field, "
1716 "value must be 0...7"));
1719 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1720 imm_expr
->X_op
= O_absent
;
1724 as_bad (_("bad compressed FUNCT field"
1725 " specifier 'CF%c'\n"),
1731 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1750 case '<': /* Shift amount, 0 - 31. */
1751 my_getExpression (imm_expr
, s
);
1752 check_absolute_expr (ip
, imm_expr
, FALSE
);
1753 if ((unsigned long) imm_expr
->X_add_number
> 31)
1754 as_bad (_("Improper shift amount (%lu)"),
1755 (unsigned long) imm_expr
->X_add_number
);
1756 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1757 imm_expr
->X_op
= O_absent
;
1761 case '>': /* Shift amount, 0 - (XLEN-1). */
1762 my_getExpression (imm_expr
, s
);
1763 check_absolute_expr (ip
, imm_expr
, FALSE
);
1764 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1765 as_bad (_("Improper shift amount (%lu)"),
1766 (unsigned long) imm_expr
->X_add_number
);
1767 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1768 imm_expr
->X_op
= O_absent
;
1772 case 'Z': /* CSRRxI immediate. */
1773 my_getExpression (imm_expr
, s
);
1774 check_absolute_expr (ip
, imm_expr
, FALSE
);
1775 if ((unsigned long) imm_expr
->X_add_number
> 31)
1776 as_bad (_("Improper CSRxI immediate (%lu)"),
1777 (unsigned long) imm_expr
->X_add_number
);
1778 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1779 imm_expr
->X_op
= O_absent
;
1783 case 'E': /* Control register. */
1784 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1785 INSERT_OPERAND (CSR
, *ip
, regno
);
1788 my_getExpression (imm_expr
, s
);
1789 check_absolute_expr (ip
, imm_expr
, TRUE
);
1790 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1791 as_bad (_("Improper CSR address (%lu)"),
1792 (unsigned long) imm_expr
->X_add_number
);
1793 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1794 imm_expr
->X_op
= O_absent
;
1799 case 'm': /* Rounding mode. */
1800 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1802 INSERT_OPERAND (RM
, *ip
, regno
);
1808 case 'Q': /* Fence predecessor/successor. */
1809 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1813 INSERT_OPERAND (PRED
, *ip
, regno
);
1815 INSERT_OPERAND (SUCC
, *ip
, regno
);
1820 case 'd': /* Destination register. */
1821 case 's': /* Source register. */
1822 case 't': /* Target register. */
1823 case 'r': /* rs3. */
1824 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1830 /* Now that we have assembled one operand, we use the args
1831 string to figure out where it goes in the instruction. */
1835 INSERT_OPERAND (RS1
, *ip
, regno
);
1838 INSERT_OPERAND (RD
, *ip
, regno
);
1841 INSERT_OPERAND (RS2
, *ip
, regno
);
1844 INSERT_OPERAND (RS3
, *ip
, regno
);
1851 case 'D': /* Floating point rd. */
1852 case 'S': /* Floating point rs1. */
1853 case 'T': /* Floating point rs2. */
1854 case 'U': /* Floating point rs1 and rs2. */
1855 case 'R': /* Floating point rs3. */
1856 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1864 INSERT_OPERAND (RD
, *ip
, regno
);
1867 INSERT_OPERAND (RS1
, *ip
, regno
);
1870 INSERT_OPERAND (RS1
, *ip
, regno
);
1873 INSERT_OPERAND (RS2
, *ip
, regno
);
1876 INSERT_OPERAND (RS3
, *ip
, regno
);
1885 my_getExpression (imm_expr
, s
);
1886 if (imm_expr
->X_op
!= O_big
1887 && imm_expr
->X_op
!= O_constant
)
1889 normalize_constant_expr (imm_expr
);
1894 my_getExpression (imm_expr
, s
);
1895 normalize_constant_expr (imm_expr
);
1896 /* The 'A' format specifier must be a symbol. */
1897 if (imm_expr
->X_op
!= O_symbol
)
1899 *imm_reloc
= BFD_RELOC_32
;
1903 case 'j': /* Sign-extended immediate. */
1904 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1905 p
= percent_op_itype
;
1907 case 'q': /* Store displacement. */
1908 p
= percent_op_stype
;
1909 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1911 case 'o': /* Load displacement. */
1912 p
= percent_op_itype
;
1913 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1915 case '0': /* AMO "displacement," which must be zero. */
1916 p
= percent_op_rtype
;
1917 *imm_reloc
= BFD_RELOC_UNUSED
;
1919 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1922 /* If this value won't fit into a 16 bit offset, then go
1923 find a macro that will generate the 32 bit offset
1925 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1927 normalize_constant_expr (imm_expr
);
1928 if (imm_expr
->X_op
!= O_constant
1929 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1930 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1931 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1938 case 'p': /* PC-relative offset. */
1940 *imm_reloc
= BFD_RELOC_12_PCREL
;
1941 my_getExpression (imm_expr
, s
);
1945 case 'u': /* Upper 20 bits. */
1946 p
= percent_op_utype
;
1947 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1948 && imm_expr
->X_op
== O_constant
)
1950 if (imm_expr
->X_add_number
< 0
1951 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
1952 as_bad (_("lui expression not in range 0..1048575"));
1954 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
1955 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
1960 case 'a': /* 20-bit PC-relative offset. */
1962 my_getExpression (imm_expr
, s
);
1964 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
1968 my_getExpression (imm_expr
, s
);
1970 if (strcmp (s
, "@plt") == 0)
1972 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
1976 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
1982 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
1983 || imm_expr
->X_op
!= O_constant
1984 || imm_expr
->X_add_number
< 0
1985 || imm_expr
->X_add_number
>= 128
1986 || (imm_expr
->X_add_number
& 0x3) != 3)
1988 as_bad (_("bad value for opcode field, "
1989 "value must be 0...127 and "
1990 "lower 2 bits must be 0x3"));
1994 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
1995 imm_expr
->X_op
= O_absent
;
1999 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2000 || imm_expr
->X_op
!= O_constant
2001 || imm_expr
->X_add_number
< 0
2002 || imm_expr
->X_add_number
>= 3)
2004 as_bad (_("bad value for opcode field, "
2005 "value must be 0...2"));
2009 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2010 imm_expr
->X_op
= O_absent
;
2014 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2022 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2023 || imm_expr
->X_op
!= O_constant
2024 || imm_expr
->X_add_number
< 0
2025 || imm_expr
->X_add_number
>= 128)
2027 as_bad (_("bad value for funct7 field, "
2028 "value must be 0...127"));
2032 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2033 imm_expr
->X_op
= O_absent
;
2037 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2038 || imm_expr
->X_op
!= O_constant
2039 || imm_expr
->X_add_number
< 0
2040 || imm_expr
->X_add_number
>= 8)
2042 as_bad (_("bad value for funct3 field, "
2043 "value must be 0...7"));
2047 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2048 imm_expr
->X_op
= O_absent
;
2052 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2053 || imm_expr
->X_op
!= O_constant
2054 || imm_expr
->X_add_number
< 0
2055 || imm_expr
->X_add_number
>= 4)
2057 as_bad (_("bad value for funct2 field, "
2058 "value must be 0...3"));
2062 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2063 imm_expr
->X_op
= O_absent
;
2068 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2073 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2074 || imm_expr
->X_op
!= O_constant
2075 || imm_expr
->X_add_number
!= 0)
2078 imm_expr
->X_op
= O_absent
;
2082 as_fatal (_("internal error: bad argument type %c"), *args
);
2087 error
= _("illegal operands");
2091 /* Restore the character we might have clobbered above. */
2093 *(argsStart
- 1) = save_c
;
2099 md_assemble (char *str
)
2101 struct riscv_cl_insn insn
;
2102 expressionS imm_expr
;
2103 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2105 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2109 as_bad ("%s `%s'", error
, str
);
2113 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2114 macro (&insn
, &imm_expr
, &imm_reloc
);
2116 append_insn (&insn
, &imm_expr
, imm_reloc
);
2120 md_atof (int type
, char *litP
, int *sizeP
)
2122 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2126 md_number_to_chars (char *buf
, valueT val
, int n
)
2128 number_to_chars_littleendian (buf
, val
, n
);
2131 const char *md_shortopts
= "O::g::G:";
2135 OPTION_MARCH
= OPTION_MD_BASE
,
2144 struct option md_longopts
[] =
2146 {"march", required_argument
, NULL
, OPTION_MARCH
},
2147 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2148 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2149 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2150 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2151 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2152 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2154 {NULL
, no_argument
, NULL
, 0}
2156 size_t md_longopts_size
= sizeof (md_longopts
);
2159 FLOAT_ABI_DEFAULT
= -1,
2165 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2168 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
)
2170 abi_xlen
= new_xlen
;
2171 float_abi
= new_float_abi
;
2175 md_parse_option (int c
, const char *arg
)
2180 riscv_set_arch (arg
);
2184 riscv_opts
.pic
= FALSE
;
2188 riscv_opts
.pic
= TRUE
;
2192 if (strcmp (arg
, "ilp32") == 0)
2193 riscv_set_abi (32, FLOAT_ABI_SOFT
);
2194 else if (strcmp (arg
, "ilp32f") == 0)
2195 riscv_set_abi (32, FLOAT_ABI_SINGLE
);
2196 else if (strcmp (arg
, "ilp32d") == 0)
2197 riscv_set_abi (32, FLOAT_ABI_DOUBLE
);
2198 else if (strcmp (arg
, "ilp32q") == 0)
2199 riscv_set_abi (32, FLOAT_ABI_QUAD
);
2200 else if (strcmp (arg
, "lp64") == 0)
2201 riscv_set_abi (64, FLOAT_ABI_SOFT
);
2202 else if (strcmp (arg
, "lp64f") == 0)
2203 riscv_set_abi (64, FLOAT_ABI_SINGLE
);
2204 else if (strcmp (arg
, "lp64d") == 0)
2205 riscv_set_abi (64, FLOAT_ABI_DOUBLE
);
2206 else if (strcmp (arg
, "lp64q") == 0)
2207 riscv_set_abi (64, FLOAT_ABI_QUAD
);
2213 riscv_opts
.relax
= TRUE
;
2216 case OPTION_NO_RELAX
:
2217 riscv_opts
.relax
= FALSE
;
2228 riscv_after_parse_args (void)
2232 if (strcmp (default_arch
, "riscv32") == 0)
2234 else if (strcmp (default_arch
, "riscv64") == 0)
2237 as_bad ("unknown default architecture `%s'", default_arch
);
2240 if (riscv_subsets
== NULL
)
2241 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2243 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2244 riscv_set_rvc (FALSE
);
2245 if (riscv_subset_supports ("c"))
2246 riscv_set_rvc (TRUE
);
2248 riscv_add_subset ("c");
2250 /* Infer ABI from ISA if not specified on command line. */
2253 else if (abi_xlen
> xlen
)
2254 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2255 else if (abi_xlen
< xlen
)
2256 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2258 if (float_abi
== FLOAT_ABI_DEFAULT
)
2260 struct riscv_subset
*subset
;
2262 /* Assume soft-float unless D extension is present. */
2263 float_abi
= FLOAT_ABI_SOFT
;
2265 for (subset
= riscv_subsets
; subset
!= NULL
; subset
= subset
->next
)
2267 if (strcasecmp (subset
->name
, "D") == 0)
2268 float_abi
= FLOAT_ABI_DOUBLE
;
2269 if (strcasecmp (subset
->name
, "Q") == 0)
2270 float_abi
= FLOAT_ABI_QUAD
;
2274 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2275 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2279 md_pcrel_from (fixS
*fixP
)
2281 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2284 /* Apply a fixup to the object file. */
2287 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2289 unsigned int subtype
;
2290 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2291 bfd_boolean relaxable
= FALSE
;
2295 /* Remember value for tc_gen_reloc. */
2296 fixP
->fx_addnumber
= *valP
;
2298 switch (fixP
->fx_r_type
)
2300 case BFD_RELOC_RISCV_HI20
:
2301 case BFD_RELOC_RISCV_LO12_I
:
2302 case BFD_RELOC_RISCV_LO12_S
:
2303 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2304 | bfd_getl32 (buf
), buf
);
2305 if (fixP
->fx_addsy
== NULL
)
2306 fixP
->fx_done
= TRUE
;
2310 case BFD_RELOC_RISCV_GOT_HI20
:
2311 case BFD_RELOC_RISCV_ADD8
:
2312 case BFD_RELOC_RISCV_ADD16
:
2313 case BFD_RELOC_RISCV_ADD32
:
2314 case BFD_RELOC_RISCV_ADD64
:
2315 case BFD_RELOC_RISCV_SUB6
:
2316 case BFD_RELOC_RISCV_SUB8
:
2317 case BFD_RELOC_RISCV_SUB16
:
2318 case BFD_RELOC_RISCV_SUB32
:
2319 case BFD_RELOC_RISCV_SUB64
:
2320 case BFD_RELOC_RISCV_RELAX
:
2323 case BFD_RELOC_RISCV_TPREL_HI20
:
2324 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2325 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2326 case BFD_RELOC_RISCV_TPREL_ADD
:
2330 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2331 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2332 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2333 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2334 if (fixP
->fx_addsy
!= NULL
)
2335 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2338 _("TLS relocation against a constant"));
2342 /* Use pc-relative relocation for FDE initial location.
2343 The symbol address in .eh_frame may be adjusted in
2344 _bfd_elf_discard_section_eh_frame, and the content of
2345 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2346 Therefore, we cannot insert a relocation whose addend symbol is
2347 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2348 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2349 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2350 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2351 && S_GET_VALUE (fixP
->fx_subsy
)
2352 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2354 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2355 fixP
->fx_subsy
= NULL
;
2362 case BFD_RELOC_RISCV_CFA
:
2363 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2365 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2366 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2367 fixP
->fx_next
->fx_subsy
= NULL
;
2368 fixP
->fx_next
->fx_offset
= 0;
2369 fixP
->fx_subsy
= NULL
;
2371 switch (fixP
->fx_r_type
)
2374 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2375 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2379 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2380 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2384 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2385 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2389 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2390 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2393 case BFD_RELOC_RISCV_CFA
:
2394 /* Load the byte to get the subtype. */
2395 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2396 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2399 case DW_CFA_advance_loc1
:
2400 fixP
->fx_where
= loc
+ 1;
2401 fixP
->fx_next
->fx_where
= loc
+ 1;
2402 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2403 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2406 case DW_CFA_advance_loc2
:
2408 fixP
->fx_next
->fx_size
= 2;
2409 fixP
->fx_where
= loc
+ 1;
2410 fixP
->fx_next
->fx_where
= loc
+ 1;
2411 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2412 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2415 case DW_CFA_advance_loc4
:
2417 fixP
->fx_next
->fx_size
= 4;
2418 fixP
->fx_where
= loc
;
2419 fixP
->fx_next
->fx_where
= loc
;
2420 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2421 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2425 if (subtype
< 0x80 && (subtype
& 0x40))
2427 /* DW_CFA_advance_loc */
2428 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2429 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2430 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2431 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2434 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2440 /* This case is unreachable. */
2447 /* If we are deleting this reloc entry, we must fill in the
2448 value now. This can happen if we have a .word which is not
2449 resolved when it appears but is later defined. */
2450 if (fixP
->fx_addsy
== NULL
)
2452 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2453 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2458 case BFD_RELOC_RISCV_JMP
:
2461 /* Fill in a tentative value to improve objdump readability. */
2462 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2463 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2464 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2468 case BFD_RELOC_12_PCREL
:
2471 /* Fill in a tentative value to improve objdump readability. */
2472 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2473 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2474 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2478 case BFD_RELOC_RISCV_RVC_BRANCH
:
2481 /* Fill in a tentative value to improve objdump readability. */
2482 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2483 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2484 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2488 case BFD_RELOC_RISCV_RVC_JUMP
:
2491 /* Fill in a tentative value to improve objdump readability. */
2492 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2493 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2494 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2498 case BFD_RELOC_RISCV_CALL
:
2499 case BFD_RELOC_RISCV_CALL_PLT
:
2503 case BFD_RELOC_RISCV_PCREL_HI20
:
2504 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2505 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2506 relaxable
= riscv_opts
.relax
;
2509 case BFD_RELOC_RISCV_ALIGN
:
2513 /* We ignore generic BFD relocations we don't know about. */
2514 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2515 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2518 if (fixP
->fx_subsy
!= NULL
)
2519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2520 _("unsupported symbol subtraction"));
2522 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2523 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2525 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2526 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2527 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2531 /* Because the value of .cfi_remember_state may changed after relaxation,
2532 we insert a fix to relocate it again in link-time. */
2535 riscv_pre_output_hook (void)
2537 const frchainS
*frch
;
2540 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2541 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2545 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2547 if (frag
->fr_type
== rs_cfa
)
2551 symbolS
*add_symbol
= frag
->fr_symbol
->sy_value
.X_add_symbol
;
2552 symbolS
*op_symbol
= frag
->fr_symbol
->sy_value
.X_op_symbol
;
2554 exp
.X_op
= O_subtract
;
2555 exp
.X_add_symbol
= add_symbol
;
2556 exp
.X_add_number
= 0;
2557 exp
.X_op_symbol
= op_symbol
;
2559 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2560 BFD_RELOC_RISCV_CFA
);
2567 /* This structure is used to hold a stack of .option values. */
2569 struct riscv_option_stack
2571 struct riscv_option_stack
*next
;
2572 struct riscv_set_options options
;
2575 static struct riscv_option_stack
*riscv_opts_stack
;
2577 /* Handle the .option pseudo-op. */
2580 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2582 char *name
= input_line_pointer
, ch
;
2584 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2585 ++input_line_pointer
;
2586 ch
= *input_line_pointer
;
2587 *input_line_pointer
= '\0';
2589 if (strcmp (name
, "rvc") == 0)
2590 riscv_set_rvc (TRUE
);
2591 else if (strcmp (name
, "norvc") == 0)
2592 riscv_set_rvc (FALSE
);
2593 else if (strcmp (name
, "pic") == 0)
2594 riscv_opts
.pic
= TRUE
;
2595 else if (strcmp (name
, "nopic") == 0)
2596 riscv_opts
.pic
= FALSE
;
2597 else if (strcmp (name
, "relax") == 0)
2598 riscv_opts
.relax
= TRUE
;
2599 else if (strcmp (name
, "norelax") == 0)
2600 riscv_opts
.relax
= FALSE
;
2601 else if (strcmp (name
, "push") == 0)
2603 struct riscv_option_stack
*s
;
2605 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2606 s
->next
= riscv_opts_stack
;
2607 s
->options
= riscv_opts
;
2608 riscv_opts_stack
= s
;
2610 else if (strcmp (name
, "pop") == 0)
2612 struct riscv_option_stack
*s
;
2614 s
= riscv_opts_stack
;
2616 as_bad (_(".option pop with no .option push"));
2619 riscv_opts
= s
->options
;
2620 riscv_opts_stack
= s
->next
;
2626 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2628 *input_line_pointer
= ch
;
2629 demand_empty_rest_of_line ();
2632 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2633 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2634 use in DWARF debug information. */
2637 s_dtprel (int bytes
)
2644 if (ex
.X_op
!= O_symbol
)
2646 as_bad (_("Unsupported use of %s"), (bytes
== 8
2649 ignore_rest_of_line ();
2652 p
= frag_more (bytes
);
2653 md_number_to_chars (p
, 0, bytes
);
2654 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2656 ? BFD_RELOC_RISCV_TLS_DTPREL64
2657 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2659 demand_empty_rest_of_line ();
2662 /* Handle the .bss pseudo-op. */
2665 s_bss (int ignore ATTRIBUTE_UNUSED
)
2667 subseg_set (bss_section
, 0);
2668 demand_empty_rest_of_line ();
2672 riscv_make_nops (char *buf
, bfd_vma bytes
)
2676 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2677 means we are not within a valid instruction sequence. It is thus safe
2678 to use a zero byte, even though that is not a valid instruction. */
2682 /* Use at most one 2-byte NOP. */
2683 if ((bytes
- i
) % 4 == 2)
2685 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2689 /* Fill the remainder with 4-byte NOPs. */
2690 for ( ; i
< bytes
; i
+= 4)
2691 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2694 /* Called from md_do_align. Used to create an alignment frag in a
2695 code section by emitting a worst-case NOP sequence that the linker
2696 will later relax to the correct number of NOPs. We can't compute
2697 the correct alignment now because of other linker relaxations. */
2700 riscv_frag_align_code (int n
)
2702 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2703 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2704 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2708 /* If we are moving to a smaller alignment than the instruction size, then no
2709 alignment is required. */
2710 if (bytes
<= insn_alignment
)
2713 nops
= frag_more (worst_case_bytes
);
2715 /* When not relaxing, riscv_handle_align handles code alignment. */
2716 if (!riscv_opts
.relax
)
2719 ex
.X_op
= O_constant
;
2720 ex
.X_add_number
= worst_case_bytes
;
2722 riscv_make_nops (nops
, worst_case_bytes
);
2724 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2725 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2730 /* Implement HANDLE_ALIGN. */
2733 riscv_handle_align (fragS
*fragP
)
2735 switch (fragP
->fr_type
)
2738 /* When relaxing, riscv_frag_align_code handles code alignment. */
2739 if (!riscv_opts
.relax
)
2741 bfd_signed_vma count
= fragP
->fr_next
->fr_address
2742 - fragP
->fr_address
- fragP
->fr_fix
;
2747 count
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
2748 riscv_make_nops (fragP
->fr_literal
+ fragP
->fr_fix
, count
);
2749 fragP
->fr_var
= count
;
2759 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2761 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2764 /* Translate internal representation of relocation info to BFD target
2768 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2770 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2772 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2773 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2774 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2775 reloc
->addend
= fixp
->fx_addnumber
;
2777 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2778 if (reloc
->howto
== NULL
)
2780 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2781 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2783 /* We don't have R_RISCV_8/16, but for this special case,
2784 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2788 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2789 _("cannot represent %s relocation in object file"),
2790 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2798 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2800 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2802 offsetT old_var
= fragp
->fr_var
;
2803 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2804 return fragp
->fr_var
- old_var
;
2810 /* Expand far branches to multi-instruction sequences. */
2813 md_convert_frag_branch (fragS
*fragp
)
2821 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2823 exp
.X_op
= O_symbol
;
2824 exp
.X_add_symbol
= fragp
->fr_symbol
;
2825 exp
.X_add_number
= fragp
->fr_offset
;
2827 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2829 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2831 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2835 /* Expand the RVC branch into a RISC-V one. */
2836 insn
= bfd_getl16 (buf
);
2837 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2838 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2840 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2841 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2842 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2843 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2844 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2845 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2848 bfd_putl32 (insn
, buf
);
2852 /* Invert the branch condition. Branch over the jump. */
2853 insn
= bfd_getl16 (buf
);
2854 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2855 insn
|= ENCODE_RVC_B_IMM (6);
2856 bfd_putl16 (insn
, buf
);
2861 /* Just keep the RVC branch. */
2862 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2863 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2864 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2865 2, &exp
, FALSE
, reloc
);
2874 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2877 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2879 /* Invert the branch condition. Branch over the jump. */
2880 insn
= bfd_getl32 (buf
);
2881 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2882 insn
|= ENCODE_SBTYPE_IMM (8);
2883 md_number_to_chars ((char *) buf
, insn
, 4);
2887 /* Jump to the target. */
2888 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2889 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2890 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2895 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2896 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2897 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2898 4, &exp
, FALSE
, reloc
);
2907 fixp
->fx_file
= fragp
->fr_file
;
2908 fixp
->fx_line
= fragp
->fr_line
;
2910 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2911 + fragp
->fr_fix
+ fragp
->fr_var
);
2913 fragp
->fr_fix
+= fragp
->fr_var
;
2916 /* Relax a machine dependent frag. This returns the amount by which
2917 the current size of the frag should change. */
2920 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
2923 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
2924 md_convert_frag_branch (fragp
);
2928 md_show_usage (FILE *stream
)
2930 fprintf (stream
, _("\
2932 -fpic generate position-independent code\n\
2933 -fno-pic don't generate position-independent code (default)\n\
2934 -march=ISA set the RISC-V architecture\n\
2935 -mabi=ABI set the RISC-V ABI\n\
2936 -mrelax enable relax (default)\n\
2937 -mno-relax disable relax\n\
2941 /* Standard calling conventions leave the CFA at SP on entry. */
2943 riscv_cfi_frame_initial_instructions (void)
2945 cfi_add_CFA_def_cfa_register (X_SP
);
2949 tc_riscv_regname_to_dw2regnum (char *regname
)
2953 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
2956 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
2959 as_bad (_("unknown register `%s'"), regname
);
2964 riscv_elf_final_processing (void)
2966 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
2969 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
2970 since these directives break relaxation when used with symbol deltas. */
2973 s_riscv_leb128 (int sign
)
2976 char *save_in
= input_line_pointer
;
2979 if (exp
.X_op
!= O_constant
)
2980 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
2981 demand_empty_rest_of_line ();
2983 input_line_pointer
= save_in
;
2984 return s_leb128 (sign
);
2987 /* Parse the .insn directive. */
2990 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
2992 char *str
= input_line_pointer
;
2993 struct riscv_cl_insn insn
;
2994 expressionS imm_expr
;
2995 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2998 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2999 ++input_line_pointer
;
3001 save_c
= *input_line_pointer
;
3002 *input_line_pointer
= '\0';
3004 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3005 &imm_reloc
, insn_type_hash
);
3009 as_bad ("%s `%s'", error
, str
);
3013 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3014 append_insn (&insn
, &imm_expr
, imm_reloc
);
3017 *input_line_pointer
= save_c
;
3018 demand_empty_rest_of_line ();
3021 /* Pseudo-op table. */
3023 static const pseudo_typeS riscv_pseudo_table
[] =
3025 /* RISC-V-specific pseudo-ops. */
3026 {"option", s_riscv_option
, 0},
3030 {"dtprelword", s_dtprel
, 4},
3031 {"dtpreldword", s_dtprel
, 8},
3033 {"uleb128", s_riscv_leb128
, 0},
3034 {"sleb128", s_riscv_leb128
, 1},
3035 {"insn", s_riscv_insn
, 0},
3041 riscv_pop_insert (void)
3043 extern void pop_insert (const pseudo_typeS
*);
3045 pop_insert (riscv_pseudo_table
);