1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2020 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 /* Let riscv_after_parse_args set the default value according to xlen. */
68 #ifndef DEFAULT_RISCV_ARCH_WITH_EXT
69 #define DEFAULT_RISCV_ARCH_WITH_EXT NULL
72 /* The default ISA spec is set to 2.2 rather than the lastest version.
73 The reason is that compiler generates the ISA string with fixed 2p0
74 verisons only for the RISCV ELF architecture attributes, but not for
75 the -march option. Therefore, we should update the compiler or linker
76 to resolve this problem. */
78 #ifndef DEFAULT_RISCV_ISA_SPEC
79 #define DEFAULT_RISCV_ISA_SPEC "2.2"
82 #ifndef DEFAULT_RISCV_PRIV_SPEC
83 #define DEFAULT_RISCV_PRIV_SPEC "1.11"
86 static const char default_arch
[] = DEFAULT_ARCH
;
87 static const char *default_arch_with_ext
= DEFAULT_RISCV_ARCH_WITH_EXT
;
88 static enum riscv_isa_spec_class default_isa_spec
= ISA_SPEC_CLASS_NONE
;
89 static enum riscv_priv_spec_class default_priv_spec
= PRIV_SPEC_CLASS_NONE
;
91 static unsigned xlen
= 0; /* width of an x-register */
92 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
93 static bfd_boolean rve_abi
= FALSE
;
95 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
96 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
98 static unsigned elf_flags
= 0;
100 /* Set the default_isa_spec. Return 0 if the input spec string isn't
101 supported. Otherwise, return 1. */
104 riscv_set_default_isa_spec (const char *s
)
106 enum riscv_isa_spec_class
class;
107 if (!riscv_get_isa_spec_class (s
, &class))
109 as_bad ("Unknown default ISA spec `%s' set by "
110 "-misa-spec or --with-isa-spec", s
);
114 default_isa_spec
= class;
118 /* Set the default_priv_spec, assembler will find the suitable CSR address
119 according to default_priv_spec. We will try to check priv attributes if
120 the input string is NULL. Return 0 if the input priv spec string isn't
121 supported. Otherwise, return 1. */
124 riscv_set_default_priv_spec (const char *s
)
126 enum riscv_priv_spec_class
class;
127 unsigned major
, minor
, revision
;
132 /* Find the corresponding priv spec class. */
133 if (riscv_get_priv_spec_class (s
, &class))
135 default_priv_spec
= class;
141 as_bad (_("Unknown default privilege spec `%s' set by "
142 "-mpriv-spec or --with-priv-spec"), s
);
146 /* Try to set the default_priv_spec according to the priv attributes. */
147 attr
= elf_known_obj_attributes_proc (stdoutput
);
148 major
= (unsigned) attr
[Tag_RISCV_priv_spec
].i
;
149 minor
= (unsigned) attr
[Tag_RISCV_priv_spec_minor
].i
;
150 revision
= (unsigned) attr
[Tag_RISCV_priv_spec_revision
].i
;
152 /* The priv attributes setting 0.0.0 is meaningless. We should have set
153 the default_priv_spec by md_parse_option and riscv_after_parse_args,
154 so just skip the following setting. */
155 if (major
== 0 && minor
== 0 && revision
== 0)
158 buf_size
= riscv_estimate_digit (major
)
160 + riscv_estimate_digit (minor
)
161 + 1; /* string terminator */
164 buf_size
+= 1 /* '.' */
165 + riscv_estimate_digit (revision
);
166 buf
= xmalloc (buf_size
);
167 snprintf (buf
, buf_size
, "%d.%d.%d", major
, minor
, revision
);
171 buf
= xmalloc (buf_size
);
172 snprintf (buf
, buf_size
, "%d.%d", major
, minor
);
175 if (riscv_get_priv_spec_class (buf
, &class))
177 default_priv_spec
= class;
182 /* Still can not find the priv spec class. */
183 as_bad (_("Unknown default privilege spec `%d.%d.%d' set by "
184 "privilege attributes"), major
, minor
, revision
);
189 /* This is the set of options which the .option pseudo-op may modify. */
191 struct riscv_set_options
193 int pic
; /* Generate position-independent code. */
194 int rvc
; /* Generate RVC code. */
195 int rve
; /* Generate RVE code. */
196 int relax
; /* Emit relocs the linker is allowed to relax. */
197 int arch_attr
; /* Emit arch attribute. */
198 int csr_check
; /* Enable the CSR checking. */
201 static struct riscv_set_options riscv_opts
=
207 DEFAULT_RISCV_ATTR
, /* arch_attr */
212 riscv_set_rvc (bfd_boolean rvc_value
)
215 elf_flags
|= EF_RISCV_RVC
;
217 riscv_opts
.rvc
= rvc_value
;
221 riscv_set_rve (bfd_boolean rve_value
)
223 riscv_opts
.rve
= rve_value
;
226 static riscv_subset_list_t riscv_subsets
;
229 riscv_subset_supports (const char *feature
)
231 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
234 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
238 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
242 case INSN_CLASS_I
: return riscv_subset_supports ("i");
243 case INSN_CLASS_C
: return riscv_subset_supports ("c");
244 case INSN_CLASS_A
: return riscv_subset_supports ("a");
245 case INSN_CLASS_M
: return riscv_subset_supports ("m");
246 case INSN_CLASS_F
: return riscv_subset_supports ("f");
247 case INSN_CLASS_D
: return riscv_subset_supports ("d");
248 case INSN_CLASS_D_AND_C
:
249 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
251 case INSN_CLASS_F_AND_C
:
252 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
254 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
257 as_fatal ("Unreachable");
262 /* Handle of the extension with version hash table. */
263 static struct hash_control
*ext_version_hash
= NULL
;
265 static struct hash_control
*
266 init_ext_version_hash (const struct riscv_ext_version
*table
)
269 struct hash_control
*hash
= hash_new ();
271 while (table
[i
].name
)
273 const char *name
= table
[i
].name
;
274 const char *hash_error
=
275 hash_insert (hash
, name
, (void *) &table
[i
]);
277 if (hash_error
!= NULL
)
279 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
280 table
[i
].name
, hash_error
);
281 /* Probably a memory allocation problem? Give up now. */
282 as_fatal (_("Broken assembler. No assembly attempted."));
288 && strcmp (table
[i
].name
, name
) == 0)
296 riscv_get_default_ext_version (const char *name
,
297 unsigned int *major_version
,
298 unsigned int *minor_version
)
300 struct riscv_ext_version
*ext
;
305 if (name
== NULL
|| default_isa_spec
== ISA_SPEC_CLASS_NONE
)
308 ext
= (struct riscv_ext_version
*) hash_find (ext_version_hash
, name
);
311 && strcmp (ext
->name
, name
) == 0)
313 if (ext
->isa_spec_class
== default_isa_spec
)
315 *major_version
= ext
->major_version
;
316 *minor_version
= ext
->minor_version
;
323 /* Set which ISA and extensions are available. */
326 riscv_set_arch (const char *s
)
328 riscv_parse_subset_t rps
;
329 rps
.subset_list
= &riscv_subsets
;
330 rps
.error_handler
= as_fatal
;
332 rps
.get_default_version
= riscv_get_default_ext_version
;
337 riscv_release_subset_list (&riscv_subsets
);
338 riscv_parse_subset (&rps
, s
);
341 /* Handle of the OPCODE hash table. */
342 static struct hash_control
*op_hash
= NULL
;
344 /* Handle of the type of .insn hash table. */
345 static struct hash_control
*insn_type_hash
= NULL
;
347 /* This array holds the chars that always start a comment. If the
348 pre-processor is disabled, these aren't very useful */
349 const char comment_chars
[] = "#";
351 /* This array holds the chars that only start a comment at the beginning of
352 a line. If the line seems to have the form '# 123 filename'
353 .line and .file directives will appear in the pre-processed output */
354 /* Note that input_file.c hand checks for '#' at the beginning of the
355 first line of the input file. This is because the compiler outputs
356 #NO_APP at the beginning of its output. */
357 /* Also note that C style comments are always supported. */
358 const char line_comment_chars
[] = "#";
360 /* This array holds machine specific line separator characters. */
361 const char line_separator_chars
[] = ";";
363 /* Chars that can be used to separate mant from exp in floating point nums */
364 const char EXP_CHARS
[] = "eE";
366 /* Chars that mean this number is a floating point constant */
369 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
371 /* Indicate we are already assemble any instructions or not. */
372 static bfd_boolean start_assemble
= FALSE
;
374 /* Indicate ELF attributes are explictly set. */
375 static bfd_boolean explicit_attr
= FALSE
;
377 /* Indicate CSR are explictly used. */
378 static bfd_boolean explicit_csr
= FALSE
;
380 /* Macros for encoding relaxation state for RVC branches and far jumps. */
381 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
384 | ((uncond) ? 1 : 0) \
387 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
388 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
389 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
390 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
392 /* Is the given value a sign-extended 32-bit value? */
393 #define IS_SEXT_32BIT_NUM(x) \
394 (((x) &~ (offsetT) 0x7fffffff) == 0 \
395 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
397 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
398 #define IS_ZEXT_32BIT_NUM(x) \
399 (((x) &~ (offsetT) 0xffffffff) == 0 \
400 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
402 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
403 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
404 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
405 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
407 /* Determine if an instruction matches an opcode. */
408 #define OPCODE_MATCHES(OPCODE, OP) \
409 (((OPCODE) & MASK_##OP) == MATCH_##OP)
411 static char *expr_end
;
413 /* The default target format to use. */
416 riscv_target_format (void)
418 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
421 /* Return the length of instruction INSN. */
423 static inline unsigned int
424 insn_length (const struct riscv_cl_insn
*insn
)
426 return riscv_insn_length (insn
->insn_opcode
);
429 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
432 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
435 insn
->insn_opcode
= mo
->match
;
441 /* Install INSN at the location specified by its "frag" and "where" fields. */
444 install_insn (const struct riscv_cl_insn
*insn
)
446 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
447 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
450 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
451 and install the opcode in the new location. */
454 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
458 if (insn
->fixp
!= NULL
)
460 insn
->fixp
->fx_frag
= frag
;
461 insn
->fixp
->fx_where
= where
;
466 /* Add INSN to the end of the output. */
469 add_fixed_insn (struct riscv_cl_insn
*insn
)
471 char *f
= frag_more (insn_length (insn
));
472 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
476 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
477 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
479 frag_grow (max_chars
);
480 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
481 frag_var (rs_machine_dependent
, max_chars
, var
,
482 subtype
, symbol
, offset
, NULL
);
485 /* Compute the length of a branch sequence, and adjust the stored length
486 accordingly. If FRAGP is NULL, the worst-case length is returned. */
489 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
491 int jump
, rvc
, length
= 8;
496 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
497 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
498 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
500 /* Assume jumps are in range; the linker will catch any that aren't. */
501 length
= jump
? 4 : 8;
503 if (fragp
->fr_symbol
!= NULL
504 && S_IS_DEFINED (fragp
->fr_symbol
)
505 && !S_IS_WEAK (fragp
->fr_symbol
)
506 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
508 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
509 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
510 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
512 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
514 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
516 else if (!jump
&& rvc
)
521 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
526 /* Information about an opcode name, mnemonics and its value. */
533 /* List for all supported opcode name. */
534 static const struct opcode_name_t opcode_name_list
[] =
579 /* Hash table for lookup opcode name. */
580 static struct hash_control
*opcode_names_hash
= NULL
;
582 /* Initialization for hash table of opcode name. */
584 init_opcode_names_hash (void)
587 const struct opcode_name_t
*opcode
;
589 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
591 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
594 as_fatal (_("internal error: can't hash `%s': %s"),
595 opcode
->name
, retval
);
599 /* Find `s` is a valid opcode name or not,
600 return the opcode name info if found. */
601 static const struct opcode_name_t
*
602 opcode_name_lookup (char **s
)
606 struct opcode_name_t
*o
;
608 /* Find end of name. */
610 if (is_name_beginner (*e
))
612 while (is_part_of_name (*e
))
615 /* Terminate name. */
619 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
621 /* Advance to next token if one was recognized. */
640 static struct hash_control
*reg_names_hash
= NULL
;
641 static struct hash_control
*csr_extra_hash
= NULL
;
643 #define ENCODE_REG_HASH(cls, n) \
644 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
645 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
646 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
649 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
651 void *hash
= ENCODE_REG_HASH (class, n
);
652 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
655 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
659 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
663 for (i
= 0; i
< n
; i
++)
664 hash_reg_name (class, names
[i
], i
);
667 /* Init hash table csr_extra_hash to handle CSR. */
669 riscv_init_csr_hash (const char *name
,
671 enum riscv_csr_class
class,
672 enum riscv_priv_spec_class define_version
,
673 enum riscv_priv_spec_class abort_version
)
675 struct riscv_csr_extra
*entry
, *pre_entry
;
676 const char *hash_error
= NULL
;
677 bfd_boolean need_enrty
= TRUE
;
680 entry
= (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, name
);
681 while (need_enrty
&& entry
!= NULL
)
683 if (entry
->csr_class
== class
684 && entry
->address
== address
685 && entry
->define_version
== define_version
686 && entry
->abort_version
== abort_version
)
692 /* Duplicate setting for the CSR, just return and do nothing. */
696 entry
= XNEW (struct riscv_csr_extra
);
697 entry
->csr_class
= class;
698 entry
->address
= address
;
699 entry
->define_version
= define_version
;
700 entry
->abort_version
= abort_version
;
703 /* If the CSR hasn't been inserted in the hash table, then insert it.
704 Otherwise, attach the extra information to the entry which is already
705 in the hash table. */
706 if (pre_entry
== NULL
)
708 hash_error
= hash_insert (csr_extra_hash
, name
, (void *) entry
);
709 if (hash_error
!= NULL
)
711 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
713 /* Probably a memory allocation problem? Give up now. */
714 as_fatal (_("Broken assembler. No assembly attempted."));
718 pre_entry
->next
= entry
;
721 /* Check wether the CSR is valid according to the ISA. */
724 riscv_csr_class_check (const char *s
,
725 enum riscv_csr_class csr_class
)
727 bfd_boolean result
= TRUE
;
729 /* Don't check the ISA dependency when -mcsr-check isn't set. */
730 if (!riscv_opts
.csr_check
)
736 result
= riscv_subset_supports ("i");
739 result
= riscv_subset_supports ("f");
742 result
= (xlen
== 32 && riscv_subset_supports ("i"));
745 as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class
);
749 as_warn (_("Invalid CSR `%s' for the current ISA"), s
);
752 /* Check and find the CSR address according to the privilege spec version. */
755 riscv_csr_version_check (const char *csr_name
,
756 struct riscv_csr_extra
**entryP
)
758 struct riscv_csr_extra
*entry
= *entryP
;
760 while (entry
!= NULL
)
762 if (default_priv_spec
>= entry
->define_version
763 && default_priv_spec
< entry
->abort_version
)
765 /* Find the suitable CSR according to the specific version. */
772 /* We can not find the suitable CSR address according to the privilege
773 version. Therefore, we use the last defined value. Report the warning
774 only when the -mcsr-check is set. Enable the -mcsr-check is recommended,
775 otherwise, you may get the unexpected CSR address. */
776 if (riscv_opts
.csr_check
)
778 const char *priv_name
= riscv_get_priv_spec_name (default_priv_spec
);
780 if (priv_name
!= NULL
)
781 as_warn (_("Invalid CSR `%s' for the privilege spec `%s'"),
782 csr_name
, priv_name
);
786 /* Once the CSR is defined, including the old privilege spec, then we call
787 riscv_csr_class_check and riscv_csr_version_check to do the further checking
788 and get the corresponding address. Return -1 if the CSR is never been
789 defined. Otherwise, return the address. */
792 reg_csr_lookup_internal (const char *s
)
794 struct riscv_csr_extra
*r
=
795 (struct riscv_csr_extra
*) hash_find (csr_extra_hash
, s
);
800 /* We just report the warning when the CSR is invalid. "Invalid CSR" means
801 the CSR was defined, but isn't allowed for the current ISA setting or
802 the privilege spec. If the CSR is never been defined, then assembler
803 will regard it as a "Unknown CSR" and report error. If user use number
804 to set the CSR, but over the range (> 0xfff), then assembler will report
805 "Improper CSR" error for it. */
806 riscv_csr_class_check (s
, r
->csr_class
);
807 riscv_csr_version_check (s
, &r
);
813 reg_lookup_internal (const char *s
, enum reg_class
class)
817 if (class == RCLASS_CSR
)
818 return reg_csr_lookup_internal (s
);
820 r
= hash_find (reg_names_hash
, s
);
821 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
824 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
827 return DECODE_REG_NUM (r
);
831 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
837 /* Find end of name. */
839 if (is_name_beginner (*e
))
841 while (is_part_of_name (*e
))
844 /* Terminate name. */
848 /* Look for the register. Advance to next token if one was recognized. */
849 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
859 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
861 const char *p
= strchr (*s
, ',');
862 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
867 for (i
= 0; i
< size
; i
++)
868 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
878 /* For consistency checking, verify that all bits are specified either
879 by the match/mask part of the instruction definition, or by the
882 `length` could be 0, 4 or 8, 0 for auto detection. */
884 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
886 const char *p
= opc
->args
;
888 insn_t used_bits
= opc
->mask
;
890 insn_t required_bits
;
893 insn_width
= 8 * riscv_insn_length (opc
->match
);
895 insn_width
= 8 * length
;
897 required_bits
= ~0ULL >> (64 - insn_width
);
899 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
901 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
902 opc
->name
, opc
->args
);
906 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
913 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
914 case 'c': break; /* RS1, constrained to equal sp */
915 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
916 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
917 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
918 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
919 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
920 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
921 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
922 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
923 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
924 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
925 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
926 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
927 case 'w': break; /* RS1S, constrained to equal RD */
928 case 'x': break; /* RS2S, constrained to equal RD */
929 case 'z': break; /* RS2S, contrained to be x0 */
930 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
931 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
932 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
933 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
934 case 'U': break; /* RS1, constrained to equal RD */
935 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
936 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
937 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
938 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
939 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
940 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
941 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
942 case 'F': /* funct */
945 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
946 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
947 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
948 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
950 as_bad (_("internal: bad RISC-V opcode"
951 " (unknown operand type `CF%c'): %s %s"),
952 c
, opc
->name
, opc
->args
);
957 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
958 c
, opc
->name
, opc
->args
);
965 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
966 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
968 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
969 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
970 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
972 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
973 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
974 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
975 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
976 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
977 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
978 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
979 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
980 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
981 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
982 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
984 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
985 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
986 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
987 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
988 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
994 case 'F': /* funct */
997 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
998 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
999 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
1001 as_bad (_("internal: bad RISC-V opcode"
1002 " (unknown operand type `F%c'): %s %s"),
1003 c
, opc
->name
, opc
->args
);
1007 case 'O': /* opcode */
1010 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
1011 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
1013 as_bad (_("internal: bad RISC-V opcode"
1014 " (unknown operand type `F%c'): %s %s"),
1015 c
, opc
->name
, opc
->args
);
1020 as_bad (_("internal: bad RISC-V opcode "
1021 "(unknown operand type `%c'): %s %s"),
1022 c
, opc
->name
, opc
->args
);
1026 if (used_bits
!= required_bits
)
1028 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
1029 ~(unsigned long)(used_bits
& required_bits
),
1030 opc
->name
, opc
->args
);
1036 struct percent_op_match
1039 bfd_reloc_code_real_type reloc
;
1042 /* Common hash table initialization function for
1043 instruction and .insn directive. */
1044 static struct hash_control
*
1045 init_opcode_hash (const struct riscv_opcode
*opcodes
,
1046 bfd_boolean insn_directive_p
)
1050 struct hash_control
*hash
= hash_new ();
1051 while (opcodes
[i
].name
)
1053 const char *name
= opcodes
[i
].name
;
1054 const char *hash_error
=
1055 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
1057 if (hash_error
!= NULL
)
1059 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1060 opcodes
[i
].name
, hash_error
);
1061 /* Probably a memory allocation problem? Give up now. */
1062 as_fatal (_("Broken assembler. No assembly attempted."));
1067 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
1069 if (insn_directive_p
)
1070 length
= ((name
[0] == 'c') ? 2 : 4);
1072 length
= 0; /* Let assembler determine the length. */
1073 if (!validate_riscv_insn (&opcodes
[i
], length
))
1074 as_fatal (_("Broken assembler. No assembly attempted."));
1077 gas_assert (!insn_directive_p
);
1080 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
1086 /* This function is called once, at assembler startup time. It should set up
1087 all the tables, etc. that the MD part of the assembler will need. */
1092 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
1094 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
1095 as_warn (_("Could not set architecture and machine"));
1097 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
1098 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
1100 reg_names_hash
= hash_new ();
1101 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
1102 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
1103 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
1104 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
1105 /* Add "fp" as an alias for "s0". */
1106 hash_reg_name (RCLASS_GPR
, "fp", 8);
1108 /* Create and insert CSR hash tables. */
1109 csr_extra_hash
= hash_new ();
1110 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
1111 riscv_init_csr_hash (#name, num, class, define_version, abort_version);
1112 #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
1113 DECLARE_CSR(name, num, class, define_version, abort_version);
1114 #include "opcode/riscv-opc.h"
1117 opcode_names_hash
= hash_new ();
1118 init_opcode_names_hash ();
1120 /* Set the default alignment for the text section. */
1121 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
1125 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
1132 case BFD_RELOC_RISCV_HI20
:
1133 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
1135 case BFD_RELOC_RISCV_LO12_S
:
1136 return ENCODE_STYPE_IMM (value
);
1138 case BFD_RELOC_RISCV_LO12_I
:
1139 return ENCODE_ITYPE_IMM (value
);
1146 /* Output an instruction. IP is the instruction information.
1147 ADDRESS_EXPR is an operand of the instruction to be used with
1151 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
1152 bfd_reloc_code_real_type reloc_type
)
1154 dwarf2_emit_insn (0);
1156 if (reloc_type
!= BFD_RELOC_UNUSED
)
1158 reloc_howto_type
*howto
;
1160 gas_assert (address_expr
);
1161 if (reloc_type
== BFD_RELOC_12_PCREL
1162 || reloc_type
== BFD_RELOC_RISCV_JMP
)
1164 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
1165 int best_case
= riscv_insn_length (ip
->insn_opcode
);
1166 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
1167 add_relaxed_insn (ip
, worst_case
, best_case
,
1168 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
1169 address_expr
->X_add_symbol
,
1170 address_expr
->X_add_number
);
1175 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
1177 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
1179 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
1180 bfd_get_reloc_size (howto
),
1181 address_expr
, FALSE
, reloc_type
);
1183 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
1187 add_fixed_insn (ip
);
1190 /* We need to start a new frag after any instruction that can be
1191 optimized away or compressed by the linker during relaxation, to prevent
1192 the assembler from computing static offsets across such an instruction.
1193 This is necessary to get correct EH info. */
1194 if (reloc_type
== BFD_RELOC_RISCV_CALL
1195 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
1196 || reloc_type
== BFD_RELOC_RISCV_HI20
1197 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
1198 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
1199 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
1201 frag_wane (frag_now
);
1206 /* Build an instruction created by a macro expansion. This is passed
1207 a pointer to the count of instructions created so far, an
1208 expression, the name of the instruction to build, an operand format
1209 string, and corresponding arguments. */
1212 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
1214 const struct riscv_opcode
*mo
;
1215 struct riscv_cl_insn insn
;
1216 bfd_reloc_code_real_type r
;
1219 va_start (args
, fmt
);
1221 r
= BFD_RELOC_UNUSED
;
1222 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
1225 /* Find a non-RVC variant of the instruction. append_insn will compress
1227 while (riscv_insn_length (mo
->match
) < 4)
1229 gas_assert (strcmp (name
, mo
->name
) == 0);
1231 create_insn (&insn
, mo
);
1237 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
1241 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
1245 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
1249 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
1255 gas_assert (ep
!= NULL
);
1256 r
= va_arg (args
, int);
1264 as_fatal (_("internal error: invalid macro"));
1269 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1271 append_insn (&insn
, ep
, r
);
1274 /* Build an instruction created by a macro expansion. Like md_assemble but
1275 accept a printf-style format string and arguments. */
1278 md_assemblef (const char *format
, ...)
1284 va_start (ap
, format
);
1286 r
= vasprintf (&buf
, format
, ap
);
1289 as_fatal (_("internal error: vasprintf failed"));
1297 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
1300 normalize_constant_expr (expressionS
*ex
)
1304 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
1305 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
1306 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
1310 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
1311 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
1314 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
1315 bfd_boolean maybe_csr
)
1317 if (ex
->X_op
== O_big
)
1318 as_bad (_("unsupported large constant"));
1319 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
1320 as_bad (_("unknown CSR `%s'"),
1321 S_GET_NAME (ex
->X_add_symbol
));
1322 else if (ex
->X_op
!= O_constant
)
1323 as_bad (_("Instruction %s requires absolute expression"),
1325 normalize_constant_expr (ex
);
1329 make_internal_label (void)
1331 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1332 (valueT
) frag_now_fix (), frag_now
);
1335 /* Load an entry from the GOT. */
1337 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1338 const char *lo_insn
, const char *lo_pattern
,
1339 bfd_reloc_code_real_type hi_reloc
,
1340 bfd_reloc_code_real_type lo_reloc
)
1343 ep2
.X_op
= O_symbol
;
1344 ep2
.X_add_symbol
= make_internal_label ();
1345 ep2
.X_add_number
= 0;
1347 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1348 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1352 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1353 bfd_reloc_code_real_type hi_reloc
,
1354 bfd_reloc_code_real_type lo_reloc
)
1356 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1360 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1361 bfd_reloc_code_real_type hi_reloc
,
1362 bfd_reloc_code_real_type lo_reloc
)
1364 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1367 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1369 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1370 bfd_reloc_code_real_type reloc
)
1372 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1373 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1376 /* Load an integer constant into a register. */
1379 load_const (int reg
, expressionS
*ep
)
1381 int shift
= RISCV_IMM_BITS
;
1382 bfd_vma upper_imm
, sign
= (bfd_vma
) 1 << (RISCV_IMM_BITS
- 1);
1383 expressionS upper
= *ep
, lower
= *ep
;
1384 lower
.X_add_number
= ((ep
->X_add_number
& (sign
+ sign
- 1)) ^ sign
) - sign
;
1385 upper
.X_add_number
-= lower
.X_add_number
;
1387 if (ep
->X_op
!= O_constant
)
1389 as_bad (_("unsupported large constant"));
1393 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1395 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1396 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1399 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1400 load_const (reg
, &upper
);
1402 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1403 if (lower
.X_add_number
!= 0)
1404 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1405 lower
.X_add_number
);
1409 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1412 if (upper
.X_add_number
!= 0)
1414 /* Discard low part and zero-extend upper immediate. */
1415 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1417 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1421 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1422 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1423 lower
.X_add_number
);
1427 /* Expand RISC-V assembly macros into one or more instructions. */
1429 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1430 bfd_reloc_code_real_type
*imm_reloc
)
1432 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1433 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1434 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1435 int mask
= ip
->insn_mo
->mask
;
1440 load_const (rd
, imm_expr
);
1445 /* Load the address of a symbol into a register. */
1446 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1447 as_bad (_("offset too large"));
1449 if (imm_expr
->X_op
== O_constant
)
1450 load_const (rd
, imm_expr
);
1451 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1452 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1453 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1454 else /* Local PIC symbol, or any non-PIC symbol */
1455 pcrel_load (rd
, rd
, imm_expr
, "addi",
1456 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1460 pcrel_load (rd
, rd
, imm_expr
, "addi",
1461 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1465 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1466 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1470 pcrel_load (rd
, rd
, imm_expr
, "lb",
1471 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1475 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1476 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1480 pcrel_load (rd
, rd
, imm_expr
, "lh",
1481 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1485 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1486 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1490 pcrel_load (rd
, rd
, imm_expr
, "lw",
1491 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1495 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1496 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1500 pcrel_load (rd
, rd
, imm_expr
, "ld",
1501 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1505 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1506 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1510 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1511 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1515 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1516 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1520 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1521 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1525 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1526 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1530 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1531 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1535 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1536 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1540 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1541 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1545 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1549 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1554 static const struct percent_op_match percent_op_utype
[] =
1556 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1557 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1558 {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20
},
1559 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1560 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1561 {"%hi", BFD_RELOC_RISCV_HI20
},
1565 static const struct percent_op_match percent_op_itype
[] =
1567 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1568 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1569 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1573 static const struct percent_op_match percent_op_stype
[] =
1575 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1576 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1577 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1581 static const struct percent_op_match percent_op_rtype
[] =
1583 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1587 static const struct percent_op_match percent_op_null
[] =
1592 /* Return true if *STR points to a relocation operator. When returning true,
1593 move *STR over the operator and store its relocation code in *RELOC.
1594 Leave both *STR and *RELOC alone when returning false. */
1597 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1598 const struct percent_op_match
*percent_op
)
1600 for ( ; percent_op
->str
; percent_op
++)
1601 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1603 int len
= strlen (percent_op
->str
);
1605 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1608 *str
+= strlen (percent_op
->str
);
1609 *reloc
= percent_op
->reloc
;
1611 /* Check whether the output BFD supports this relocation.
1612 If not, issue an error and fall back on something safe. */
1613 if (*reloc
!= BFD_RELOC_UNUSED
1614 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1616 as_bad ("relocation %s isn't supported by the current ABI",
1618 *reloc
= BFD_RELOC_UNUSED
;
1626 my_getExpression (expressionS
*ep
, char *str
)
1630 save_in
= input_line_pointer
;
1631 input_line_pointer
= str
;
1633 expr_end
= input_line_pointer
;
1634 input_line_pointer
= save_in
;
1637 /* Parse string STR as a 16-bit relocatable operand. Store the
1638 expression in *EP and the relocation, if any, in RELOC.
1639 Return the number of relocation operators used (0 or 1).
1641 On exit, EXPR_END points to the first character after the expression. */
1644 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1645 char *str
, const struct percent_op_match
*percent_op
)
1648 unsigned crux_depth
, str_depth
, regno
;
1651 /* First, check for integer registers. No callers can accept a reg, but
1652 we need to avoid accidentally creating a useless undefined symbol below,
1653 if this is an instruction pattern that can't match. A glibc build fails
1654 if this is removed. */
1655 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1657 ep
->X_op
= O_register
;
1658 ep
->X_add_number
= regno
;
1663 /* Search for the start of the main expression.
1664 End the loop with CRUX pointing to the start
1665 of the main expression and with CRUX_DEPTH containing the number
1666 of open brackets at that point. */
1673 crux_depth
= str_depth
;
1675 /* Skip over whitespace and brackets, keeping count of the number
1677 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1683 && parse_relocation (&str
, reloc
, percent_op
));
1685 my_getExpression (ep
, crux
);
1688 /* Match every open bracket. */
1689 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1694 as_bad ("unclosed '('");
1701 /* Parse opcode name, could be an mnemonics or number. */
1703 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1704 char *str
, const struct percent_op_match
*percent_op
)
1706 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1710 ep
->X_op
= O_constant
;
1711 ep
->X_add_number
= o
->val
;
1715 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1718 /* Detect and handle implicitly zero load-store offsets. For example,
1719 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1720 an implicit offset was detected. */
1723 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1725 /* Check whether there is only a single bracketed expression left.
1726 If so, it must be the base register and the constant must be zero. */
1727 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1729 ep
->X_op
= O_constant
;
1730 ep
->X_add_number
= 0;
1737 /* All RISC-V CSR instructions belong to one of these classes. */
1747 /* Return which CSR instruction is checking. */
1749 static enum csr_insn_type
1750 riscv_csr_insn_type (insn_t insn
)
1752 if (((insn
^ MATCH_CSRRW
) & MASK_CSRRW
) == 0
1753 || ((insn
^ MATCH_CSRRWI
) & MASK_CSRRWI
) == 0)
1755 else if (((insn
^ MATCH_CSRRS
) & MASK_CSRRS
) == 0
1756 || ((insn
^ MATCH_CSRRSI
) & MASK_CSRRSI
) == 0)
1758 else if (((insn
^ MATCH_CSRRC
) & MASK_CSRRC
) == 0
1759 || ((insn
^ MATCH_CSRRCI
) & MASK_CSRRCI
) == 0)
1762 return INSN_NOT_CSR
;
1765 /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write
1766 CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of
1767 CSR address is 0x3. */
1770 riscv_csr_read_only_check (insn_t insn
)
1772 int csr
= (insn
& (OP_MASK_CSR
<< OP_SH_CSR
)) >> OP_SH_CSR
;
1773 int rs1
= (insn
& (OP_MASK_RS1
<< OP_SH_RS1
)) >> OP_SH_RS1
;
1774 int readonly
= (((csr
& (0x3 << 10)) >> 10) == 0x3);
1775 enum csr_insn_type csr_insn
= riscv_csr_insn_type (insn
);
1778 && (((csr_insn
== INSN_CSRRS
1779 || csr_insn
== INSN_CSRRC
)
1781 || csr_insn
== INSN_CSRRW
))
1787 /* This routine assembles an instruction into its binary format. As a
1788 side effect, it sets the global variable imm_reloc to the type of
1789 relocation to do if one of the operands is an address expression. */
1792 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1793 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1798 struct riscv_opcode
*insn
;
1803 const struct percent_op_match
*p
;
1804 const char *error
= "unrecognized opcode";
1805 /* Indicate we are assembling instruction with CSR. */
1806 bfd_boolean insn_with_csr
= FALSE
;
1808 /* Parse the name of the instruction. Terminate the string if whitespace
1809 is found so that hash_find only sees the name part of the string. */
1810 for (s
= str
; *s
!= '\0'; ++s
)
1818 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1821 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1823 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1826 if (!riscv_multi_subset_supports (insn
->insn_class
))
1829 create_insn (ip
, insn
);
1832 imm_expr
->X_op
= O_absent
;
1833 *imm_reloc
= BFD_RELOC_UNUSED
;
1834 p
= percent_op_itype
;
1836 for (args
= insn
->args
;; ++args
)
1838 s
+= strspn (s
, " \t");
1841 case '\0': /* End of args. */
1842 if (insn
->pinfo
!= INSN_MACRO
)
1844 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1847 /* For .insn, insn->match and insn->mask are 0. */
1848 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1854 /* Check if we write a read-only CSR by the CSR
1857 && riscv_opts
.csr_check
1858 && !riscv_csr_read_only_check (ip
->insn_opcode
))
1860 /* Restore the character in advance, since we want to
1861 report the detailed warning message here. */
1863 *(argsStart
- 1) = save_c
;
1864 as_warn (_("Read-only CSR is written `%s'"), str
);
1865 insn_with_csr
= FALSE
;
1870 /* Successful assembly. */
1872 insn_with_csr
= FALSE
;
1878 case 's': /* RS1 x8-x15 */
1879 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1880 || !(regno
>= 8 && regno
<= 15))
1882 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1884 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1885 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1886 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1889 case 't': /* RS2 x8-x15 */
1890 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1891 || !(regno
>= 8 && regno
<= 15))
1893 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1895 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1896 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1897 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1900 case 'U': /* RS1, constrained to equal RD. */
1901 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1902 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1906 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1908 INSERT_OPERAND (CRS2
, *ip
, regno
);
1910 case 'c': /* RS1, constrained to equal sp. */
1911 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1915 case 'z': /* RS2, contrained to equal x0. */
1916 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1921 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1922 || imm_expr
->X_op
!= O_constant
1923 || imm_expr
->X_add_number
<= 0
1924 || imm_expr
->X_add_number
>= 64)
1926 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1929 imm_expr
->X_op
= O_absent
;
1932 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1933 || imm_expr
->X_op
!= O_constant
1934 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1935 || imm_expr
->X_add_number
<= 0
1936 || imm_expr
->X_add_number
>= 32)
1938 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1941 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1942 || imm_expr
->X_op
!= O_constant
1943 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1944 || imm_expr
->X_add_number
< 0
1945 || imm_expr
->X_add_number
>= 256)
1947 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1950 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1951 || imm_expr
->X_op
!= O_constant
1952 || imm_expr
->X_add_number
== 0
1953 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1955 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1958 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1959 || imm_expr
->X_op
!= O_constant
1960 || imm_expr
->X_add_number
== 0
1961 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1963 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1966 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1968 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1969 || imm_expr
->X_op
!= O_constant
1970 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1972 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1975 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1977 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1978 || imm_expr
->X_op
!= O_constant
1979 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1981 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1984 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1986 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1987 || imm_expr
->X_op
!= O_constant
1988 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1991 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1994 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1996 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1997 || imm_expr
->X_op
!= O_constant
1998 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
2001 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
2004 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2005 || imm_expr
->X_op
!= O_constant
2006 /* C.addiw, c.li, and c.andi allow zero immediate.
2007 C.addi allows zero immediate as hint. Otherwise this
2009 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
2011 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2014 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2015 || imm_expr
->X_op
!= O_constant
2016 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
2017 || imm_expr
->X_add_number
== 0)
2020 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
2023 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2024 || imm_expr
->X_op
!= O_constant
2025 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
2026 || imm_expr
->X_add_number
== 0)
2029 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
2032 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2034 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2035 || imm_expr
->X_op
!= O_constant
2036 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
2039 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
2042 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2044 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2045 || imm_expr
->X_op
!= O_constant
2046 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
2049 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
2052 p
= percent_op_utype
;
2053 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2056 if (imm_expr
->X_op
!= O_constant
2057 || imm_expr
->X_add_number
<= 0
2058 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
2059 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
2060 && (imm_expr
->X_add_number
<
2061 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
2063 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
2066 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2067 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
2068 || ((int32_t)imm_expr
->X_add_number
2069 != imm_expr
->X_add_number
))
2071 imm_expr
->X_add_number
=
2072 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
2078 case 'S': /* Floating-point RS1 x8-x15. */
2079 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2080 || !(regno
>= 8 && regno
<= 15))
2082 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
2084 case 'D': /* Floating-point RS2 x8-x15. */
2085 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
2086 || !(regno
>= 8 && regno
<= 15))
2088 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
2090 case 'T': /* Floating-point RS2. */
2091 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
2093 INSERT_OPERAND (CRS2
, *ip
, regno
);
2099 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2100 || imm_expr
->X_op
!= O_constant
2101 || imm_expr
->X_add_number
< 0
2102 || imm_expr
->X_add_number
>= 64)
2104 as_bad (_("bad value for funct6 field, "
2105 "value must be 0...64"));
2109 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
2110 imm_expr
->X_op
= O_absent
;
2114 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2115 || imm_expr
->X_op
!= O_constant
2116 || imm_expr
->X_add_number
< 0
2117 || imm_expr
->X_add_number
>= 16)
2119 as_bad (_("bad value for funct4 field, "
2120 "value must be 0...15"));
2124 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
2125 imm_expr
->X_op
= O_absent
;
2129 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2130 || imm_expr
->X_op
!= O_constant
2131 || imm_expr
->X_add_number
< 0
2132 || imm_expr
->X_add_number
>= 8)
2134 as_bad (_("bad value for funct3 field, "
2135 "value must be 0...7"));
2138 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
2139 imm_expr
->X_op
= O_absent
;
2143 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2144 || imm_expr
->X_op
!= O_constant
2145 || imm_expr
->X_add_number
< 0
2146 || imm_expr
->X_add_number
>= 4)
2148 as_bad (_("bad value for funct2 field, "
2149 "value must be 0...3"));
2152 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
2153 imm_expr
->X_op
= O_absent
;
2157 as_bad (_("bad compressed FUNCT field"
2158 " specifier 'CF%c'\n"),
2164 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
2183 case '<': /* Shift amount, 0 - 31. */
2184 my_getExpression (imm_expr
, s
);
2185 check_absolute_expr (ip
, imm_expr
, FALSE
);
2186 if ((unsigned long) imm_expr
->X_add_number
> 31)
2187 as_bad (_("Improper shift amount (%lu)"),
2188 (unsigned long) imm_expr
->X_add_number
);
2189 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
2190 imm_expr
->X_op
= O_absent
;
2194 case '>': /* Shift amount, 0 - (XLEN-1). */
2195 my_getExpression (imm_expr
, s
);
2196 check_absolute_expr (ip
, imm_expr
, FALSE
);
2197 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
2198 as_bad (_("Improper shift amount (%lu)"),
2199 (unsigned long) imm_expr
->X_add_number
);
2200 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
2201 imm_expr
->X_op
= O_absent
;
2205 case 'Z': /* CSRRxI immediate. */
2206 my_getExpression (imm_expr
, s
);
2207 check_absolute_expr (ip
, imm_expr
, FALSE
);
2208 if ((unsigned long) imm_expr
->X_add_number
> 31)
2209 as_bad (_("Improper CSRxI immediate (%lu)"),
2210 (unsigned long) imm_expr
->X_add_number
);
2211 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
2212 imm_expr
->X_op
= O_absent
;
2216 case 'E': /* Control register. */
2217 insn_with_csr
= TRUE
;
2218 explicit_csr
= TRUE
;
2219 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
2220 INSERT_OPERAND (CSR
, *ip
, regno
);
2223 my_getExpression (imm_expr
, s
);
2224 check_absolute_expr (ip
, imm_expr
, TRUE
);
2225 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
2226 as_bad (_("Improper CSR address (%lu)"),
2227 (unsigned long) imm_expr
->X_add_number
);
2228 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
2229 imm_expr
->X_op
= O_absent
;
2234 case 'm': /* Rounding mode. */
2235 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
2237 INSERT_OPERAND (RM
, *ip
, regno
);
2243 case 'Q': /* Fence predecessor/successor. */
2244 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
2248 INSERT_OPERAND (PRED
, *ip
, regno
);
2250 INSERT_OPERAND (SUCC
, *ip
, regno
);
2255 case 'd': /* Destination register. */
2256 case 's': /* Source register. */
2257 case 't': /* Target register. */
2258 case 'r': /* rs3. */
2259 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
2265 /* Now that we have assembled one operand, we use the args
2266 string to figure out where it goes in the instruction. */
2270 INSERT_OPERAND (RS1
, *ip
, regno
);
2273 INSERT_OPERAND (RD
, *ip
, regno
);
2276 INSERT_OPERAND (RS2
, *ip
, regno
);
2279 INSERT_OPERAND (RS3
, *ip
, regno
);
2286 case 'D': /* Floating point rd. */
2287 case 'S': /* Floating point rs1. */
2288 case 'T': /* Floating point rs2. */
2289 case 'U': /* Floating point rs1 and rs2. */
2290 case 'R': /* Floating point rs3. */
2291 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
2299 INSERT_OPERAND (RD
, *ip
, regno
);
2302 INSERT_OPERAND (RS1
, *ip
, regno
);
2305 INSERT_OPERAND (RS1
, *ip
, regno
);
2308 INSERT_OPERAND (RS2
, *ip
, regno
);
2311 INSERT_OPERAND (RS3
, *ip
, regno
);
2320 my_getExpression (imm_expr
, s
);
2321 if (imm_expr
->X_op
!= O_big
2322 && imm_expr
->X_op
!= O_constant
)
2324 normalize_constant_expr (imm_expr
);
2329 my_getExpression (imm_expr
, s
);
2330 normalize_constant_expr (imm_expr
);
2331 /* The 'A' format specifier must be a symbol. */
2332 if (imm_expr
->X_op
!= O_symbol
)
2334 *imm_reloc
= BFD_RELOC_32
;
2339 my_getExpression (imm_expr
, s
);
2340 normalize_constant_expr (imm_expr
);
2341 /* The 'B' format specifier must be a symbol or a constant. */
2342 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
2344 if (imm_expr
->X_op
== O_symbol
)
2345 *imm_reloc
= BFD_RELOC_32
;
2349 case 'j': /* Sign-extended immediate. */
2350 p
= percent_op_itype
;
2351 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2353 case 'q': /* Store displacement. */
2354 p
= percent_op_stype
;
2355 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
2357 case 'o': /* Load displacement. */
2358 p
= percent_op_itype
;
2359 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
2361 case '1': /* 4-operand add, must be %tprel_add. */
2362 p
= percent_op_rtype
;
2364 case '0': /* AMO "displacement," which must be zero. */
2365 p
= percent_op_null
;
2367 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
2370 /* If this value won't fit into a 16 bit offset, then go
2371 find a macro that will generate the 32 bit offset
2373 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2375 normalize_constant_expr (imm_expr
);
2376 if (imm_expr
->X_op
!= O_constant
2377 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
2379 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
2380 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
2387 case 'p': /* PC-relative offset. */
2389 *imm_reloc
= BFD_RELOC_12_PCREL
;
2390 my_getExpression (imm_expr
, s
);
2394 case 'u': /* Upper 20 bits. */
2395 p
= percent_op_utype
;
2396 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
2398 if (imm_expr
->X_op
!= O_constant
)
2401 if (imm_expr
->X_add_number
< 0
2402 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2403 as_bad (_("lui expression not in range 0..1048575"));
2405 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2406 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2411 case 'a': /* 20-bit PC-relative offset. */
2413 my_getExpression (imm_expr
, s
);
2415 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2419 my_getExpression (imm_expr
, s
);
2421 if (strcmp (s
, "@plt") == 0)
2423 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2427 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2433 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2434 || imm_expr
->X_op
!= O_constant
2435 || imm_expr
->X_add_number
< 0
2436 || imm_expr
->X_add_number
>= 128
2437 || (imm_expr
->X_add_number
& 0x3) != 3)
2439 as_bad (_("bad value for opcode field, "
2440 "value must be 0...127 and "
2441 "lower 2 bits must be 0x3"));
2445 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2446 imm_expr
->X_op
= O_absent
;
2450 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2451 || imm_expr
->X_op
!= O_constant
2452 || imm_expr
->X_add_number
< 0
2453 || imm_expr
->X_add_number
>= 3)
2455 as_bad (_("bad value for opcode field, "
2456 "value must be 0...2"));
2460 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2461 imm_expr
->X_op
= O_absent
;
2465 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2473 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2474 || imm_expr
->X_op
!= O_constant
2475 || imm_expr
->X_add_number
< 0
2476 || imm_expr
->X_add_number
>= 128)
2478 as_bad (_("bad value for funct7 field, "
2479 "value must be 0...127"));
2483 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2484 imm_expr
->X_op
= O_absent
;
2488 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2489 || imm_expr
->X_op
!= O_constant
2490 || imm_expr
->X_add_number
< 0
2491 || imm_expr
->X_add_number
>= 8)
2493 as_bad (_("bad value for funct3 field, "
2494 "value must be 0...7"));
2498 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2499 imm_expr
->X_op
= O_absent
;
2503 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2504 || imm_expr
->X_op
!= O_constant
2505 || imm_expr
->X_add_number
< 0
2506 || imm_expr
->X_add_number
>= 4)
2508 as_bad (_("bad value for funct2 field, "
2509 "value must be 0...3"));
2513 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2514 imm_expr
->X_op
= O_absent
;
2519 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2524 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2525 || imm_expr
->X_op
!= O_constant
2526 || imm_expr
->X_add_number
!= 0)
2529 imm_expr
->X_op
= O_absent
;
2533 as_fatal (_("internal error: bad argument type %c"), *args
);
2538 error
= _("illegal operands");
2539 insn_with_csr
= FALSE
;
2543 /* Restore the character we might have clobbered above. */
2545 *(argsStart
- 1) = save_c
;
2551 md_assemble (char *str
)
2553 struct riscv_cl_insn insn
;
2554 expressionS imm_expr
;
2555 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2557 /* The arch and priv attributes should be set before assembling. */
2558 if (!start_assemble
)
2560 start_assemble
= TRUE
;
2562 /* Set the default_priv_spec according to the priv attributes. */
2563 if (!riscv_set_default_priv_spec (NULL
))
2567 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2571 as_bad ("%s `%s'", error
, str
);
2575 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2576 macro (&insn
, &imm_expr
, &imm_reloc
);
2578 append_insn (&insn
, &imm_expr
, imm_reloc
);
2582 md_atof (int type
, char *litP
, int *sizeP
)
2584 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2588 md_number_to_chars (char *buf
, valueT val
, int n
)
2590 number_to_chars_littleendian (buf
, val
, n
);
2593 const char *md_shortopts
= "O::g::G:";
2597 OPTION_MARCH
= OPTION_MD_BASE
,
2604 OPTION_NO_ARCH_ATTR
,
2606 OPTION_NO_CSR_CHECK
,
2612 struct option md_longopts
[] =
2614 {"march", required_argument
, NULL
, OPTION_MARCH
},
2615 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2616 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2617 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2618 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2619 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2620 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2621 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2622 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2623 {"mcsr-check", no_argument
, NULL
, OPTION_CSR_CHECK
},
2624 {"mno-csr-check", no_argument
, NULL
, OPTION_NO_CSR_CHECK
},
2625 {"misa-spec", required_argument
, NULL
, OPTION_MISA_SPEC
},
2626 {"mpriv-spec", required_argument
, NULL
, OPTION_MPRIV_SPEC
},
2628 {NULL
, no_argument
, NULL
, 0}
2630 size_t md_longopts_size
= sizeof (md_longopts
);
2633 FLOAT_ABI_DEFAULT
= -1,
2639 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2642 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2644 abi_xlen
= new_xlen
;
2645 float_abi
= new_float_abi
;
2650 md_parse_option (int c
, const char *arg
)
2655 /* riscv_after_parse_args will call riscv_set_arch to parse
2656 the architecture. */
2657 default_arch_with_ext
= arg
;
2661 riscv_opts
.pic
= FALSE
;
2665 riscv_opts
.pic
= TRUE
;
2669 if (strcmp (arg
, "ilp32") == 0)
2670 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2671 else if (strcmp (arg
, "ilp32e") == 0)
2672 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2673 else if (strcmp (arg
, "ilp32f") == 0)
2674 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2675 else if (strcmp (arg
, "ilp32d") == 0)
2676 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2677 else if (strcmp (arg
, "ilp32q") == 0)
2678 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2679 else if (strcmp (arg
, "lp64") == 0)
2680 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2681 else if (strcmp (arg
, "lp64f") == 0)
2682 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2683 else if (strcmp (arg
, "lp64d") == 0)
2684 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2685 else if (strcmp (arg
, "lp64q") == 0)
2686 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2692 riscv_opts
.relax
= TRUE
;
2695 case OPTION_NO_RELAX
:
2696 riscv_opts
.relax
= FALSE
;
2699 case OPTION_ARCH_ATTR
:
2700 riscv_opts
.arch_attr
= TRUE
;
2703 case OPTION_NO_ARCH_ATTR
:
2704 riscv_opts
.arch_attr
= FALSE
;
2707 case OPTION_CSR_CHECK
:
2708 riscv_opts
.csr_check
= TRUE
;
2711 case OPTION_NO_CSR_CHECK
:
2712 riscv_opts
.csr_check
= FALSE
;
2715 case OPTION_MISA_SPEC
:
2716 return riscv_set_default_isa_spec (arg
);
2718 case OPTION_MPRIV_SPEC
:
2719 return riscv_set_default_priv_spec (arg
);
2729 riscv_after_parse_args (void)
2731 /* The --with-arch is optional for now, so we have to set the xlen
2732 according to the default_arch, which is set by the --targte, first.
2733 Then, we use the xlen to set the default_arch_with_ext if the
2734 -march and --with-arch are not set. */
2737 if (strcmp (default_arch
, "riscv32") == 0)
2739 else if (strcmp (default_arch
, "riscv64") == 0)
2742 as_bad ("unknown default architecture `%s'", default_arch
);
2744 if (default_arch_with_ext
== NULL
)
2745 default_arch_with_ext
= xlen
== 64 ? "rv64g" : "rv32g";
2747 /* Initialize the hash table for extensions with default version. */
2748 ext_version_hash
= init_ext_version_hash (riscv_ext_version_table
);
2750 /* If the -misa-spec isn't set, then we set the default ISA spec according
2751 to DEFAULT_RISCV_ISA_SPEC. */
2752 if (default_isa_spec
== ISA_SPEC_CLASS_NONE
)
2753 riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC
);
2755 /* Set the architecture according to -march or or --with-arch. */
2756 riscv_set_arch (default_arch_with_ext
);
2758 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2759 riscv_set_rvc (FALSE
);
2760 if (riscv_subset_supports ("c"))
2761 riscv_set_rvc (TRUE
);
2763 /* Enable RVE if specified by the -march option. */
2764 riscv_set_rve (FALSE
);
2765 if (riscv_subset_supports ("e"))
2766 riscv_set_rve (TRUE
);
2768 /* If the -mpriv-spec isn't set, then we set the default privilege spec
2769 according to DEFAULT_PRIV_SPEC. */
2770 if (default_priv_spec
== PRIV_SPEC_CLASS_NONE
)
2771 riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC
);
2773 /* Infer ABI from ISA if not specified on command line. */
2776 else if (abi_xlen
> xlen
)
2777 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2778 else if (abi_xlen
< xlen
)
2779 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2781 if (float_abi
== FLOAT_ABI_DEFAULT
)
2783 riscv_subset_t
*subset
;
2785 /* Assume soft-float unless D extension is present. */
2786 float_abi
= FLOAT_ABI_SOFT
;
2788 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2790 if (strcasecmp (subset
->name
, "D") == 0)
2791 float_abi
= FLOAT_ABI_DOUBLE
;
2792 if (strcasecmp (subset
->name
, "Q") == 0)
2793 float_abi
= FLOAT_ABI_QUAD
;
2798 elf_flags
|= EF_RISCV_RVE
;
2800 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2801 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2803 /* If the CIE to be produced has not been overridden on the command line,
2804 then produce version 3 by default. This allows us to use the full
2805 range of registers in a .cfi_return_column directive. */
2806 if (flag_dwarf_cie_version
== -1)
2807 flag_dwarf_cie_version
= 3;
2811 md_pcrel_from (fixS
*fixP
)
2813 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2816 /* Apply a fixup to the object file. */
2819 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2821 unsigned int subtype
;
2822 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2823 bfd_boolean relaxable
= FALSE
;
2827 /* Remember value for tc_gen_reloc. */
2828 fixP
->fx_addnumber
= *valP
;
2830 switch (fixP
->fx_r_type
)
2832 case BFD_RELOC_RISCV_HI20
:
2833 case BFD_RELOC_RISCV_LO12_I
:
2834 case BFD_RELOC_RISCV_LO12_S
:
2835 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2836 | bfd_getl32 (buf
), buf
);
2837 if (fixP
->fx_addsy
== NULL
)
2838 fixP
->fx_done
= TRUE
;
2842 case BFD_RELOC_RISCV_GOT_HI20
:
2843 case BFD_RELOC_RISCV_ADD8
:
2844 case BFD_RELOC_RISCV_ADD16
:
2845 case BFD_RELOC_RISCV_ADD32
:
2846 case BFD_RELOC_RISCV_ADD64
:
2847 case BFD_RELOC_RISCV_SUB6
:
2848 case BFD_RELOC_RISCV_SUB8
:
2849 case BFD_RELOC_RISCV_SUB16
:
2850 case BFD_RELOC_RISCV_SUB32
:
2851 case BFD_RELOC_RISCV_SUB64
:
2852 case BFD_RELOC_RISCV_RELAX
:
2855 case BFD_RELOC_RISCV_TPREL_HI20
:
2856 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2857 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2858 case BFD_RELOC_RISCV_TPREL_ADD
:
2862 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2863 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2864 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2865 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2866 if (fixP
->fx_addsy
!= NULL
)
2867 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2869 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2870 _("TLS relocation against a constant"));
2874 /* Use pc-relative relocation for FDE initial location.
2875 The symbol address in .eh_frame may be adjusted in
2876 _bfd_elf_discard_section_eh_frame, and the content of
2877 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2878 Therefore, we cannot insert a relocation whose addend symbol is
2879 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2880 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2881 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2882 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2883 && S_GET_VALUE (fixP
->fx_subsy
)
2884 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2886 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2887 fixP
->fx_subsy
= NULL
;
2894 case BFD_RELOC_RISCV_CFA
:
2895 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2897 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2898 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2899 fixP
->fx_next
->fx_subsy
= NULL
;
2900 fixP
->fx_next
->fx_offset
= 0;
2901 fixP
->fx_subsy
= NULL
;
2903 switch (fixP
->fx_r_type
)
2906 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2907 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2911 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2912 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2916 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2917 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2921 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2922 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2925 case BFD_RELOC_RISCV_CFA
:
2926 /* Load the byte to get the subtype. */
2927 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2928 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2931 case DW_CFA_advance_loc1
:
2932 fixP
->fx_where
= loc
+ 1;
2933 fixP
->fx_next
->fx_where
= loc
+ 1;
2934 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2935 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2938 case DW_CFA_advance_loc2
:
2940 fixP
->fx_next
->fx_size
= 2;
2941 fixP
->fx_where
= loc
+ 1;
2942 fixP
->fx_next
->fx_where
= loc
+ 1;
2943 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2944 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2947 case DW_CFA_advance_loc4
:
2949 fixP
->fx_next
->fx_size
= 4;
2950 fixP
->fx_where
= loc
;
2951 fixP
->fx_next
->fx_where
= loc
;
2952 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2953 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2957 if (subtype
< 0x80 && (subtype
& 0x40))
2959 /* DW_CFA_advance_loc */
2960 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2961 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2962 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2963 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2966 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2972 /* This case is unreachable. */
2979 /* If we are deleting this reloc entry, we must fill in the
2980 value now. This can happen if we have a .word which is not
2981 resolved when it appears but is later defined. */
2982 if (fixP
->fx_addsy
== NULL
)
2984 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2985 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2990 case BFD_RELOC_RISCV_JMP
:
2993 /* Fill in a tentative value to improve objdump readability. */
2994 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2995 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2996 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
3000 case BFD_RELOC_12_PCREL
:
3003 /* Fill in a tentative value to improve objdump readability. */
3004 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3005 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3006 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
3010 case BFD_RELOC_RISCV_RVC_BRANCH
:
3013 /* Fill in a tentative value to improve objdump readability. */
3014 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3015 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3016 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
3020 case BFD_RELOC_RISCV_RVC_JUMP
:
3023 /* Fill in a tentative value to improve objdump readability. */
3024 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
3025 bfd_vma delta
= target
- md_pcrel_from (fixP
);
3026 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
3030 case BFD_RELOC_RISCV_CALL
:
3031 case BFD_RELOC_RISCV_CALL_PLT
:
3035 case BFD_RELOC_RISCV_PCREL_HI20
:
3036 case BFD_RELOC_RISCV_PCREL_LO12_S
:
3037 case BFD_RELOC_RISCV_PCREL_LO12_I
:
3038 relaxable
= riscv_opts
.relax
;
3041 case BFD_RELOC_RISCV_ALIGN
:
3045 /* We ignore generic BFD relocations we don't know about. */
3046 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
3047 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
3050 if (fixP
->fx_subsy
!= NULL
)
3051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3052 _("unsupported symbol subtraction"));
3054 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
3055 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
3057 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
3058 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
3059 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
3063 /* Because the value of .cfi_remember_state may changed after relaxation,
3064 we insert a fix to relocate it again in link-time. */
3067 riscv_pre_output_hook (void)
3069 const frchainS
*frch
;
3072 /* Save the current segment info. */
3074 subsegT subseg
= now_subseg
;
3076 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
3077 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
3081 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
3083 if (frag
->fr_type
== rs_cfa
)
3086 expressionS
*symval
;
3088 symval
= symbol_get_value_expression (frag
->fr_symbol
);
3089 exp
.X_op
= O_subtract
;
3090 exp
.X_add_symbol
= symval
->X_add_symbol
;
3091 exp
.X_add_number
= 0;
3092 exp
.X_op_symbol
= symval
->X_op_symbol
;
3094 /* We must set the segment before creating a frag after all
3095 frag chains have been chained together. */
3096 subseg_set (s
, frch
->frch_subseg
);
3098 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
3099 BFD_RELOC_RISCV_CFA
);
3104 /* Restore the original segment info. */
3105 subseg_set (seg
, subseg
);
3109 /* This structure is used to hold a stack of .option values. */
3111 struct riscv_option_stack
3113 struct riscv_option_stack
*next
;
3114 struct riscv_set_options options
;
3117 static struct riscv_option_stack
*riscv_opts_stack
;
3119 /* Handle the .option pseudo-op. */
3122 s_riscv_option (int x ATTRIBUTE_UNUSED
)
3124 char *name
= input_line_pointer
, ch
;
3126 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3127 ++input_line_pointer
;
3128 ch
= *input_line_pointer
;
3129 *input_line_pointer
= '\0';
3131 if (strcmp (name
, "rvc") == 0)
3132 riscv_set_rvc (TRUE
);
3133 else if (strcmp (name
, "norvc") == 0)
3134 riscv_set_rvc (FALSE
);
3135 else if (strcmp (name
, "pic") == 0)
3136 riscv_opts
.pic
= TRUE
;
3137 else if (strcmp (name
, "nopic") == 0)
3138 riscv_opts
.pic
= FALSE
;
3139 else if (strcmp (name
, "relax") == 0)
3140 riscv_opts
.relax
= TRUE
;
3141 else if (strcmp (name
, "norelax") == 0)
3142 riscv_opts
.relax
= FALSE
;
3143 else if (strcmp (name
, "csr-check") == 0)
3144 riscv_opts
.csr_check
= TRUE
;
3145 else if (strcmp (name
, "no-csr-check") == 0)
3146 riscv_opts
.csr_check
= FALSE
;
3147 else if (strcmp (name
, "push") == 0)
3149 struct riscv_option_stack
*s
;
3151 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
3152 s
->next
= riscv_opts_stack
;
3153 s
->options
= riscv_opts
;
3154 riscv_opts_stack
= s
;
3156 else if (strcmp (name
, "pop") == 0)
3158 struct riscv_option_stack
*s
;
3160 s
= riscv_opts_stack
;
3162 as_bad (_(".option pop with no .option push"));
3165 riscv_opts
= s
->options
;
3166 riscv_opts_stack
= s
->next
;
3172 as_warn (_("Unrecognized .option directive: %s\n"), name
);
3174 *input_line_pointer
= ch
;
3175 demand_empty_rest_of_line ();
3178 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
3179 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
3180 use in DWARF debug information. */
3183 s_dtprel (int bytes
)
3190 if (ex
.X_op
!= O_symbol
)
3192 as_bad (_("Unsupported use of %s"), (bytes
== 8
3195 ignore_rest_of_line ();
3198 p
= frag_more (bytes
);
3199 md_number_to_chars (p
, 0, bytes
);
3200 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
3202 ? BFD_RELOC_RISCV_TLS_DTPREL64
3203 : BFD_RELOC_RISCV_TLS_DTPREL32
));
3205 demand_empty_rest_of_line ();
3208 /* Handle the .bss pseudo-op. */
3211 s_bss (int ignore ATTRIBUTE_UNUSED
)
3213 subseg_set (bss_section
, 0);
3214 demand_empty_rest_of_line ();
3218 riscv_make_nops (char *buf
, bfd_vma bytes
)
3222 /* RISC-V instructions cannot begin or end on odd addresses, so this case
3223 means we are not within a valid instruction sequence. It is thus safe
3224 to use a zero byte, even though that is not a valid instruction. */
3228 /* Use at most one 2-byte NOP. */
3229 if ((bytes
- i
) % 4 == 2)
3231 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
3235 /* Fill the remainder with 4-byte NOPs. */
3236 for ( ; i
< bytes
; i
+= 4)
3237 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
3240 /* Called from md_do_align. Used to create an alignment frag in a
3241 code section by emitting a worst-case NOP sequence that the linker
3242 will later relax to the correct number of NOPs. We can't compute
3243 the correct alignment now because of other linker relaxations. */
3246 riscv_frag_align_code (int n
)
3248 bfd_vma bytes
= (bfd_vma
) 1 << n
;
3249 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
3250 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
3254 /* If we are moving to a smaller alignment than the instruction size, then no
3255 alignment is required. */
3256 if (bytes
<= insn_alignment
)
3259 /* When not relaxing, riscv_handle_align handles code alignment. */
3260 if (!riscv_opts
.relax
)
3263 nops
= frag_more (worst_case_bytes
);
3265 ex
.X_op
= O_constant
;
3266 ex
.X_add_number
= worst_case_bytes
;
3268 riscv_make_nops (nops
, worst_case_bytes
);
3270 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
3271 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
3276 /* Implement HANDLE_ALIGN. */
3279 riscv_handle_align (fragS
*fragP
)
3281 switch (fragP
->fr_type
)
3284 /* When relaxing, riscv_frag_align_code handles code alignment. */
3285 if (!riscv_opts
.relax
)
3287 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
3288 - fragP
->fr_address
- fragP
->fr_fix
);
3289 /* We have 4 byte uncompressed nops. */
3290 bfd_signed_vma size
= 4;
3291 bfd_signed_vma excess
= bytes
% size
;
3292 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
3297 /* Insert zeros or compressed nops to get 4 byte alignment. */
3300 riscv_make_nops (p
, excess
);
3301 fragP
->fr_fix
+= excess
;
3305 /* Insert variable number of 4 byte uncompressed nops. */
3306 riscv_make_nops (p
, size
);
3307 fragP
->fr_var
= size
;
3317 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
3319 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
3322 /* Translate internal representation of relocation info to BFD target
3326 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3328 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3330 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3331 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3332 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3333 reloc
->addend
= fixp
->fx_addnumber
;
3335 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3336 if (reloc
->howto
== NULL
)
3338 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
3339 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
3341 /* We don't have R_RISCV_8/16, but for this special case,
3342 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
3346 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3347 _("cannot represent %s relocation in object file"),
3348 bfd_get_reloc_code_name (fixp
->fx_r_type
));
3356 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
3358 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
3360 offsetT old_var
= fragp
->fr_var
;
3361 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
3362 return fragp
->fr_var
- old_var
;
3368 /* Expand far branches to multi-instruction sequences. */
3371 md_convert_frag_branch (fragS
*fragp
)
3379 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
3381 exp
.X_op
= O_symbol
;
3382 exp
.X_add_symbol
= fragp
->fr_symbol
;
3383 exp
.X_add_number
= fragp
->fr_offset
;
3385 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
3387 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
3389 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3393 /* Expand the RVC branch into a RISC-V one. */
3394 insn
= bfd_getl16 (buf
);
3395 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
3396 if ((insn
& MASK_C_J
) == MATCH_C_J
)
3398 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
3399 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
3400 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
3401 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
3402 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
3403 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
3406 bfd_putl32 (insn
, buf
);
3410 /* Invert the branch condition. Branch over the jump. */
3411 insn
= bfd_getl16 (buf
);
3412 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
3413 insn
|= ENCODE_RVC_B_IMM (6);
3414 bfd_putl16 (insn
, buf
);
3419 /* Just keep the RVC branch. */
3420 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3421 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
3422 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3423 2, &exp
, FALSE
, reloc
);
3432 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
3435 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
3437 /* Invert the branch condition. Branch over the jump. */
3438 insn
= bfd_getl32 (buf
);
3439 insn
^= MATCH_BEQ
^ MATCH_BNE
;
3440 insn
|= ENCODE_SBTYPE_IMM (8);
3441 md_number_to_chars ((char *) buf
, insn
, 4);
3445 /* Jump to the target. */
3446 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3447 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
3448 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
3453 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
3454 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
3455 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
3456 4, &exp
, FALSE
, reloc
);
3465 fixp
->fx_file
= fragp
->fr_file
;
3466 fixp
->fx_line
= fragp
->fr_line
;
3468 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
3469 + fragp
->fr_fix
+ fragp
->fr_var
);
3471 fragp
->fr_fix
+= fragp
->fr_var
;
3474 /* Relax a machine dependent frag. This returns the amount by which
3475 the current size of the frag should change. */
3478 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3481 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3482 md_convert_frag_branch (fragp
);
3486 md_show_usage (FILE *stream
)
3488 fprintf (stream
, _("\
3490 -fpic generate position-independent code\n\
3491 -fno-pic don't generate position-independent code (default)\n\
3492 -march=ISA set the RISC-V architecture\n\
3493 -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\
3494 -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9, 1.9.1, 1.10, 1.11)\n\
3495 -mabi=ABI set the RISC-V ABI\n\
3496 -mrelax enable relax (default)\n\
3497 -mno-relax disable relax\n\
3498 -march-attr generate RISC-V arch attribute\n\
3499 -mno-arch-attr don't generate RISC-V arch attribute\n\
3503 /* Standard calling conventions leave the CFA at SP on entry. */
3505 riscv_cfi_frame_initial_instructions (void)
3507 cfi_add_CFA_def_cfa_register (X_SP
);
3511 tc_riscv_regname_to_dw2regnum (char *regname
)
3515 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3518 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3521 /* CSRs are numbered 4096 -> 8191. */
3522 if ((reg
= reg_lookup_internal (regname
, RCLASS_CSR
)) >= 0)
3525 as_bad (_("unknown register `%s'"), regname
);
3530 riscv_elf_final_processing (void)
3532 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3535 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3536 since these directives break relaxation when used with symbol deltas. */
3539 s_riscv_leb128 (int sign
)
3542 char *save_in
= input_line_pointer
;
3545 if (exp
.X_op
!= O_constant
)
3546 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3547 demand_empty_rest_of_line ();
3549 input_line_pointer
= save_in
;
3550 return s_leb128 (sign
);
3553 /* Parse the .insn directive. */
3556 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3558 char *str
= input_line_pointer
;
3559 struct riscv_cl_insn insn
;
3560 expressionS imm_expr
;
3561 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3564 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3565 ++input_line_pointer
;
3567 save_c
= *input_line_pointer
;
3568 *input_line_pointer
= '\0';
3570 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3571 &imm_reloc
, insn_type_hash
);
3575 as_bad ("%s `%s'", error
, str
);
3579 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3580 append_insn (&insn
, &imm_expr
, imm_reloc
);
3583 *input_line_pointer
= save_c
;
3584 demand_empty_rest_of_line ();
3587 /* Update arch and priv attributes. If we don't set the corresponding ELF
3588 attributes, then try to output the default ones. */
3591 riscv_write_out_attrs (void)
3593 const char *arch_str
, *priv_str
, *p
;
3594 /* versions[0] is major, versions[1] is minor,
3595 and versions[3] is revision. */
3596 unsigned versions
[3] = {0}, number
= 0;
3599 /* Re-write arch attribute to normalize the arch string. */
3600 arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3601 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3602 xfree ((void *)arch_str
);
3604 /* For the file without any instruction, we don't set the default_priv_spec
3605 according to the priv attributes since the md_assemble isn't called.
3606 Call riscv_set_default_priv_spec here for the above case, although
3607 it seems strange. */
3609 && !riscv_set_default_priv_spec (NULL
))
3612 /* If we already have set elf priv attributes, then generate them.
3613 Otherwise, don't generate them when no CSR are used. */
3617 /* Re-write priv attributes by default_priv_spec. */
3618 priv_str
= riscv_get_priv_spec_name (default_priv_spec
);
3620 for (i
= 0; *p
; ++p
)
3622 if (*p
== '.' && i
< 3)
3624 versions
[i
++] = number
;
3627 else if (ISDIGIT (*p
))
3628 number
= (number
* 10) + (*p
- '0');
3631 as_bad (_("internal: bad RISC-V priv spec string (%s)"), priv_str
);
3635 versions
[i
] = number
;
3637 /* Set the priv attributes. */
3638 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec
, versions
[0]);
3639 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_minor
, versions
[1]);
3640 bfd_elf_add_proc_attr_int (stdoutput
, Tag_RISCV_priv_spec_revision
, versions
[2]);
3643 /* Add the default contents for the .riscv.attributes section. If any
3644 ELF attribute or -march-attr options is set, call riscv_write_out_attrs
3645 to update the arch and priv attributes. */
3648 riscv_set_public_attributes (void)
3650 if (riscv_opts
.arch_attr
|| explicit_attr
)
3651 riscv_write_out_attrs ();
3654 /* Called after all assembly has been done. */
3659 riscv_set_public_attributes ();
3662 /* Given a symbolic attribute NAME, return the proper integer value.
3663 Returns -1 if the attribute is not known. */
3666 riscv_convert_symbolic_attribute (const char *name
)
3675 /* When you modify this table you should
3676 also modify the list in doc/c-riscv.texi. */
3677 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3681 T(priv_spec_revision
),
3682 T(unaligned_access
),
3692 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3693 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3694 return attribute_table
[i
].tag
;
3699 /* Parse a .attribute directive. */
3702 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3704 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3706 obj_attribute
*attr
;
3708 explicit_attr
= TRUE
;
3711 case Tag_RISCV_arch
:
3713 attr
= elf_known_obj_attributes_proc (stdoutput
);
3714 if (!start_assemble
)
3715 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3717 as_fatal (_(".attribute arch must set before any instructions"));
3719 if (old_xlen
!= xlen
)
3721 /* We must re-init bfd again if xlen is changed. */
3722 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3723 bfd_find_target (riscv_target_format (), stdoutput
);
3725 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3726 as_warn (_("Could not set architecture and machine"));
3730 case Tag_RISCV_priv_spec
:
3731 case Tag_RISCV_priv_spec_minor
:
3732 case Tag_RISCV_priv_spec_revision
:
3734 as_fatal (_(".attribute priv spec must set before any instructions"));
3742 /* Pseudo-op table. */
3744 static const pseudo_typeS riscv_pseudo_table
[] =
3746 /* RISC-V-specific pseudo-ops. */
3747 {"option", s_riscv_option
, 0},
3751 {"dtprelword", s_dtprel
, 4},
3752 {"dtpreldword", s_dtprel
, 8},
3754 {"uleb128", s_riscv_leb128
, 0},
3755 {"sleb128", s_riscv_leb128
, 1},
3756 {"insn", s_riscv_insn
, 0},
3757 {"attribute", s_riscv_attribute
, 0},
3763 riscv_pop_insert (void)
3765 extern void pop_insert (const pseudo_typeS
*);
3767 pop_insert (riscv_pseudo_table
);