1 /* tc-riscv.c -- RISC-V assembler
2 Copyright (C) 2011-2019 Free Software Foundation, Inc.
4 Contributed by Andrew Waterman (andrew@sifive.com).
7 This file is part of GAS.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING3. If not,
21 see <http://www.gnu.org/licenses/>. */
26 #include "safe-ctype.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 #include "bfd/elfxx-riscv.h"
33 #include "elf/riscv.h"
34 #include "opcode/riscv.h"
38 /* Information about an instruction, including its format, operands
42 /* The opcode's entry in riscv_opcodes. */
43 const struct riscv_opcode
*insn_mo
;
45 /* The encoded instruction bits. */
48 /* The frag that contains the instruction. */
51 /* The offset into FRAG of the first instruction byte. */
54 /* The relocs associated with the instruction, if any. */
59 #define DEFAULT_ARCH "riscv64"
62 #ifndef DEFAULT_RISCV_ATTR
63 #define DEFAULT_RISCV_ATTR 0
66 static const char default_arch
[] = DEFAULT_ARCH
;
68 static unsigned xlen
= 0; /* width of an x-register */
69 static unsigned abi_xlen
= 0; /* width of a pointer in the ABI */
70 static bfd_boolean rve_abi
= FALSE
;
72 #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
73 #define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
75 static unsigned elf_flags
= 0;
77 /* This is the set of options which the .option pseudo-op may modify. */
79 struct riscv_set_options
81 int pic
; /* Generate position-independent code. */
82 int rvc
; /* Generate RVC code. */
83 int rve
; /* Generate RVE code. */
84 int relax
; /* Emit relocs the linker is allowed to relax. */
85 int arch_attr
; /* Emit arch attribute. */
88 static struct riscv_set_options riscv_opts
=
94 DEFAULT_RISCV_ATTR
, /* arch_attr */
98 riscv_set_rvc (bfd_boolean rvc_value
)
101 elf_flags
|= EF_RISCV_RVC
;
103 riscv_opts
.rvc
= rvc_value
;
107 riscv_set_rve (bfd_boolean rve_value
)
109 riscv_opts
.rve
= rve_value
;
112 static riscv_subset_list_t riscv_subsets
;
115 riscv_subset_supports (const char *feature
)
117 if (riscv_opts
.rvc
&& (strcasecmp (feature
, "c") == 0))
120 return riscv_lookup_subset (&riscv_subsets
, feature
) != NULL
;
124 riscv_multi_subset_supports (enum riscv_insn_class insn_class
)
128 case INSN_CLASS_I
: return riscv_subset_supports ("i");
129 case INSN_CLASS_C
: return riscv_subset_supports ("c");
130 case INSN_CLASS_A
: return riscv_subset_supports ("a");
131 case INSN_CLASS_M
: return riscv_subset_supports ("m");
132 case INSN_CLASS_F
: return riscv_subset_supports ("f");
133 case INSN_CLASS_D
: return riscv_subset_supports ("d");
134 case INSN_CLASS_D_AND_C
:
135 return riscv_subset_supports ("d") && riscv_subset_supports ("c");
137 case INSN_CLASS_F_AND_C
:
138 return riscv_subset_supports ("f") && riscv_subset_supports ("c");
140 case INSN_CLASS_Q
: return riscv_subset_supports ("q");
143 as_fatal ("Unreachable");
148 /* Set which ISA and extensions are available. */
151 riscv_set_arch (const char *s
)
153 riscv_parse_subset_t rps
;
154 rps
.subset_list
= &riscv_subsets
;
155 rps
.error_handler
= as_fatal
;
158 riscv_release_subset_list (&riscv_subsets
);
159 riscv_parse_subset (&rps
, s
);
162 /* Handle of the OPCODE hash table. */
163 static struct hash_control
*op_hash
= NULL
;
165 /* Handle of the type of .insn hash table. */
166 static struct hash_control
*insn_type_hash
= NULL
;
168 /* This array holds the chars that always start a comment. If the
169 pre-processor is disabled, these aren't very useful */
170 const char comment_chars
[] = "#";
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that C style comments are always supported. */
179 const char line_comment_chars
[] = "#";
181 /* This array holds machine specific line separator characters. */
182 const char line_separator_chars
[] = ";";
184 /* Chars that can be used to separate mant from exp in floating point nums */
185 const char EXP_CHARS
[] = "eE";
187 /* Chars that mean this number is a floating point constant */
190 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
192 /* Indicate we are already assemble any instructions or not. */
193 static bfd_boolean start_assemble
= FALSE
;
195 /* Indicate arch attribute is explictly set. */
196 static bfd_boolean explicit_arch_attr
= FALSE
;
198 /* Macros for encoding relaxation state for RVC branches and far jumps. */
199 #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
202 | ((uncond) ? 1 : 0) \
205 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
206 #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
207 #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
208 #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
210 /* Is the given value a sign-extended 32-bit value? */
211 #define IS_SEXT_32BIT_NUM(x) \
212 (((x) &~ (offsetT) 0x7fffffff) == 0 \
213 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
215 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
216 #define IS_ZEXT_32BIT_NUM(x) \
217 (((x) &~ (offsetT) 0xffffffff) == 0 \
218 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
220 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
221 INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
222 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
223 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
225 /* Determine if an instruction matches an opcode. */
226 #define OPCODE_MATCHES(OPCODE, OP) \
227 (((OPCODE) & MASK_##OP) == MATCH_##OP)
229 static char *expr_end
;
231 /* The default target format to use. */
234 riscv_target_format (void)
236 return xlen
== 64 ? "elf64-littleriscv" : "elf32-littleriscv";
239 /* Return the length of instruction INSN. */
241 static inline unsigned int
242 insn_length (const struct riscv_cl_insn
*insn
)
244 return riscv_insn_length (insn
->insn_opcode
);
247 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
250 create_insn (struct riscv_cl_insn
*insn
, const struct riscv_opcode
*mo
)
253 insn
->insn_opcode
= mo
->match
;
259 /* Install INSN at the location specified by its "frag" and "where" fields. */
262 install_insn (const struct riscv_cl_insn
*insn
)
264 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
265 md_number_to_chars (f
, insn
->insn_opcode
, insn_length (insn
));
268 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
269 and install the opcode in the new location. */
272 move_insn (struct riscv_cl_insn
*insn
, fragS
*frag
, long where
)
276 if (insn
->fixp
!= NULL
)
278 insn
->fixp
->fx_frag
= frag
;
279 insn
->fixp
->fx_where
= where
;
284 /* Add INSN to the end of the output. */
287 add_fixed_insn (struct riscv_cl_insn
*insn
)
289 char *f
= frag_more (insn_length (insn
));
290 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
294 add_relaxed_insn (struct riscv_cl_insn
*insn
, int max_chars
, int var
,
295 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
297 frag_grow (max_chars
);
298 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
299 frag_var (rs_machine_dependent
, max_chars
, var
,
300 subtype
, symbol
, offset
, NULL
);
303 /* Compute the length of a branch sequence, and adjust the stored length
304 accordingly. If FRAGP is NULL, the worst-case length is returned. */
307 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
309 int jump
, rvc
, length
= 8;
314 jump
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
);
315 rvc
= RELAX_BRANCH_RVC (fragp
->fr_subtype
);
316 length
= RELAX_BRANCH_LENGTH (fragp
->fr_subtype
);
318 /* Assume jumps are in range; the linker will catch any that aren't. */
319 length
= jump
? 4 : 8;
321 if (fragp
->fr_symbol
!= NULL
322 && S_IS_DEFINED (fragp
->fr_symbol
)
323 && !S_IS_WEAK (fragp
->fr_symbol
)
324 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
326 offsetT val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
327 bfd_vma rvc_range
= jump
? RVC_JUMP_REACH
: RVC_BRANCH_REACH
;
328 val
-= fragp
->fr_address
+ fragp
->fr_fix
;
330 if (rvc
&& (bfd_vma
)(val
+ rvc_range
/2) < rvc_range
)
332 else if ((bfd_vma
)(val
+ RISCV_BRANCH_REACH
/2) < RISCV_BRANCH_REACH
)
334 else if (!jump
&& rvc
)
339 fragp
->fr_subtype
= RELAX_BRANCH_ENCODE (jump
, rvc
, length
);
344 /* Information about an opcode name, mnemonics and its value. */
351 /* List for all supported opcode name. */
352 static const struct opcode_name_t opcode_name_list
[] =
397 /* Hash table for lookup opcode name. */
398 static struct hash_control
*opcode_names_hash
= NULL
;
400 /* Initialization for hash table of opcode name. */
402 init_opcode_names_hash (void)
405 const struct opcode_name_t
*opcode
;
407 for (opcode
= &opcode_name_list
[0]; opcode
->name
!= NULL
; ++opcode
)
409 retval
= hash_insert (opcode_names_hash
, opcode
->name
, (void *)opcode
);
412 as_fatal (_("internal error: can't hash `%s': %s"),
413 opcode
->name
, retval
);
417 /* Find `s` is a valid opcode name or not,
418 return the opcode name info if found. */
419 static const struct opcode_name_t
*
420 opcode_name_lookup (char **s
)
424 struct opcode_name_t
*o
;
426 /* Find end of name. */
428 if (is_name_beginner (*e
))
430 while (is_part_of_name (*e
))
433 /* Terminate name. */
437 o
= (struct opcode_name_t
*) hash_find (opcode_names_hash
, *s
);
439 /* Advance to next token if one was recognized. */
463 static struct hash_control
*reg_names_hash
= NULL
;
465 #define ENCODE_REG_HASH(cls, n) \
466 ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
467 #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
468 #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
471 hash_reg_name (enum reg_class
class, const char *name
, unsigned n
)
473 void *hash
= ENCODE_REG_HASH (class, n
);
474 const char *retval
= hash_insert (reg_names_hash
, name
, hash
);
477 as_fatal (_("internal error: can't hash `%s': %s"), name
, retval
);
481 hash_reg_names (enum reg_class
class, const char * const names
[], unsigned n
)
485 for (i
= 0; i
< n
; i
++)
486 hash_reg_name (class, names
[i
], i
);
490 reg_lookup_internal (const char *s
, enum reg_class
class)
492 struct regname
*r
= (struct regname
*) hash_find (reg_names_hash
, s
);
494 if (r
== NULL
|| DECODE_REG_CLASS (r
) != class)
497 if (riscv_opts
.rve
&& class == RCLASS_GPR
&& DECODE_REG_NUM (r
) > 15)
500 return DECODE_REG_NUM (r
);
504 reg_lookup (char **s
, enum reg_class
class, unsigned int *regnop
)
510 /* Find end of name. */
512 if (is_name_beginner (*e
))
514 while (is_part_of_name (*e
))
517 /* Terminate name. */
521 /* Look for the register. Advance to next token if one was recognized. */
522 if ((reg
= reg_lookup_internal (*s
, class)) >= 0)
532 arg_lookup (char **s
, const char *const *array
, size_t size
, unsigned *regnop
)
534 const char *p
= strchr (*s
, ',');
535 size_t i
, len
= p
? (size_t)(p
- *s
) : strlen (*s
);
540 for (i
= 0; i
< size
; i
++)
541 if (array
[i
] != NULL
&& strncmp (array
[i
], *s
, len
) == 0)
551 /* For consistency checking, verify that all bits are specified either
552 by the match/mask part of the instruction definition, or by the
555 `length` could be 0, 4 or 8, 0 for auto detection. */
557 validate_riscv_insn (const struct riscv_opcode
*opc
, int length
)
559 const char *p
= opc
->args
;
561 insn_t used_bits
= opc
->mask
;
563 insn_t required_bits
;
566 insn_width
= 8 * riscv_insn_length (opc
->match
);
568 insn_width
= 8 * length
;
570 required_bits
= ~0ULL >> (64 - insn_width
);
572 if ((used_bits
& opc
->match
) != (opc
->match
& required_bits
))
574 as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"),
575 opc
->name
, opc
->args
);
579 #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift)))
586 case 'a': used_bits
|= ENCODE_RVC_J_IMM (-1U); break;
587 case 'c': break; /* RS1, constrained to equal sp */
588 case 'i': used_bits
|= ENCODE_RVC_SIMM3(-1U); break;
589 case 'j': used_bits
|= ENCODE_RVC_IMM (-1U); break;
590 case 'o': used_bits
|= ENCODE_RVC_IMM (-1U); break;
591 case 'k': used_bits
|= ENCODE_RVC_LW_IMM (-1U); break;
592 case 'l': used_bits
|= ENCODE_RVC_LD_IMM (-1U); break;
593 case 'm': used_bits
|= ENCODE_RVC_LWSP_IMM (-1U); break;
594 case 'n': used_bits
|= ENCODE_RVC_LDSP_IMM (-1U); break;
595 case 'p': used_bits
|= ENCODE_RVC_B_IMM (-1U); break;
596 case 's': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
597 case 't': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
598 case 'u': used_bits
|= ENCODE_RVC_IMM (-1U); break;
599 case 'v': used_bits
|= ENCODE_RVC_IMM (-1U); break;
600 case 'w': break; /* RS1S, constrained to equal RD */
601 case 'x': break; /* RS2S, constrained to equal RD */
602 case 'z': break; /* RS2S, contrained to be x0 */
603 case 'K': used_bits
|= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
604 case 'L': used_bits
|= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
605 case 'M': used_bits
|= ENCODE_RVC_SWSP_IMM (-1U); break;
606 case 'N': used_bits
|= ENCODE_RVC_SDSP_IMM (-1U); break;
607 case 'U': break; /* RS1, constrained to equal RD */
608 case 'V': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
609 case '<': used_bits
|= ENCODE_RVC_IMM (-1U); break;
610 case '>': used_bits
|= ENCODE_RVC_IMM (-1U); break;
611 case '8': used_bits
|= ENCODE_RVC_UIMM8 (-1U); break;
612 case 'S': USE_BITS (OP_MASK_CRS1S
, OP_SH_CRS1S
); break;
613 case 'T': USE_BITS (OP_MASK_CRS2
, OP_SH_CRS2
); break;
614 case 'D': USE_BITS (OP_MASK_CRS2S
, OP_SH_CRS2S
); break;
615 case 'F': /* funct */
618 case '6': USE_BITS (OP_MASK_CFUNCT6
, OP_SH_CFUNCT6
); break;
619 case '4': USE_BITS (OP_MASK_CFUNCT4
, OP_SH_CFUNCT4
); break;
620 case '3': USE_BITS (OP_MASK_CFUNCT3
, OP_SH_CFUNCT3
); break;
621 case '2': USE_BITS (OP_MASK_CFUNCT2
, OP_SH_CFUNCT2
); break;
623 as_bad (_("internal: bad RISC-V opcode"
624 " (unknown operand type `CF%c'): %s %s"),
625 c
, opc
->name
, opc
->args
);
630 as_bad (_("internal: bad RISC-V opcode (unknown operand type `C%c'): %s %s"),
631 c
, opc
->name
, opc
->args
);
638 case '<': USE_BITS (OP_MASK_SHAMTW
, OP_SH_SHAMTW
); break;
639 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
641 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
642 case 'Z': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
643 case 'E': USE_BITS (OP_MASK_CSR
, OP_SH_CSR
); break;
645 case 'R': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
646 case 'S': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
647 case 'U': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); /* fallthru */
648 case 'T': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
649 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
650 case 'm': USE_BITS (OP_MASK_RM
, OP_SH_RM
); break;
651 case 's': USE_BITS (OP_MASK_RS1
, OP_SH_RS1
); break;
652 case 't': USE_BITS (OP_MASK_RS2
, OP_SH_RS2
); break;
653 case 'r': USE_BITS (OP_MASK_RS3
, OP_SH_RS3
); break;
654 case 'P': USE_BITS (OP_MASK_PRED
, OP_SH_PRED
); break;
655 case 'Q': USE_BITS (OP_MASK_SUCC
, OP_SH_SUCC
); break;
657 case 'j': used_bits
|= ENCODE_ITYPE_IMM (-1U); break;
658 case 'a': used_bits
|= ENCODE_UJTYPE_IMM (-1U); break;
659 case 'p': used_bits
|= ENCODE_SBTYPE_IMM (-1U); break;
660 case 'q': used_bits
|= ENCODE_STYPE_IMM (-1U); break;
661 case 'u': used_bits
|= ENCODE_UTYPE_IMM (-1U); break;
667 case 'F': /* funct */
670 case '7': USE_BITS (OP_MASK_FUNCT7
, OP_SH_FUNCT7
); break;
671 case '3': USE_BITS (OP_MASK_FUNCT3
, OP_SH_FUNCT3
); break;
672 case '2': USE_BITS (OP_MASK_FUNCT2
, OP_SH_FUNCT2
); break;
674 as_bad (_("internal: bad RISC-V opcode"
675 " (unknown operand type `F%c'): %s %s"),
676 c
, opc
->name
, opc
->args
);
680 case 'O': /* opcode */
683 case '4': USE_BITS (OP_MASK_OP
, OP_SH_OP
); break;
684 case '2': USE_BITS (OP_MASK_OP2
, OP_SH_OP2
); break;
686 as_bad (_("internal: bad RISC-V opcode"
687 " (unknown operand type `F%c'): %s %s"),
688 c
, opc
->name
, opc
->args
);
693 as_bad (_("internal: bad RISC-V opcode "
694 "(unknown operand type `%c'): %s %s"),
695 c
, opc
->name
, opc
->args
);
699 if (used_bits
!= required_bits
)
701 as_bad (_("internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s"),
702 ~(unsigned long)(used_bits
& required_bits
),
703 opc
->name
, opc
->args
);
709 struct percent_op_match
712 bfd_reloc_code_real_type reloc
;
715 /* Common hash table initialization function for
716 instruction and .insn directive. */
717 static struct hash_control
*
718 init_opcode_hash (const struct riscv_opcode
*opcodes
,
719 bfd_boolean insn_directive_p
)
723 struct hash_control
*hash
= hash_new ();
724 while (opcodes
[i
].name
)
726 const char *name
= opcodes
[i
].name
;
727 const char *hash_error
=
728 hash_insert (hash
, name
, (void *) &opcodes
[i
]);
732 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
733 opcodes
[i
].name
, hash_error
);
734 /* Probably a memory allocation problem? Give up now. */
735 as_fatal (_("Broken assembler. No assembly attempted."));
740 if (opcodes
[i
].pinfo
!= INSN_MACRO
)
742 if (insn_directive_p
)
743 length
= ((name
[0] == 'c') ? 2 : 4);
745 length
= 0; /* Let assembler determine the length. */
746 if (!validate_riscv_insn (&opcodes
[i
], length
))
747 as_fatal (_("Broken assembler. No assembly attempted."));
750 gas_assert (!insn_directive_p
);
753 while (opcodes
[i
].name
&& !strcmp (opcodes
[i
].name
, name
));
759 /* This function is called once, at assembler startup time. It should set up
760 all the tables, etc. that the MD part of the assembler will need. */
765 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
767 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
768 as_warn (_("Could not set architecture and machine"));
770 op_hash
= init_opcode_hash (riscv_opcodes
, FALSE
);
771 insn_type_hash
= init_opcode_hash (riscv_insn_types
, TRUE
);
773 reg_names_hash
= hash_new ();
774 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_numeric
, NGPR
);
775 hash_reg_names (RCLASS_GPR
, riscv_gpr_names_abi
, NGPR
);
776 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_numeric
, NFPR
);
777 hash_reg_names (RCLASS_FPR
, riscv_fpr_names_abi
, NFPR
);
779 /* Add "fp" as an alias for "s0". */
780 hash_reg_name (RCLASS_GPR
, "fp", 8);
782 opcode_names_hash
= hash_new ();
783 init_opcode_names_hash ();
785 #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num);
786 #define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num);
787 #include "opcode/riscv-opc.h"
790 /* Set the default alignment for the text section. */
791 record_alignment (text_section
, riscv_opts
.rvc
? 1 : 2);
795 riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type
, bfd_vma value
)
802 case BFD_RELOC_RISCV_HI20
:
803 return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value
));
805 case BFD_RELOC_RISCV_LO12_S
:
806 return ENCODE_STYPE_IMM (value
);
808 case BFD_RELOC_RISCV_LO12_I
:
809 return ENCODE_ITYPE_IMM (value
);
816 /* Output an instruction. IP is the instruction information.
817 ADDRESS_EXPR is an operand of the instruction to be used with
821 append_insn (struct riscv_cl_insn
*ip
, expressionS
*address_expr
,
822 bfd_reloc_code_real_type reloc_type
)
824 dwarf2_emit_insn (0);
826 if (reloc_type
!= BFD_RELOC_UNUSED
)
828 reloc_howto_type
*howto
;
830 gas_assert (address_expr
);
831 if (reloc_type
== BFD_RELOC_12_PCREL
832 || reloc_type
== BFD_RELOC_RISCV_JMP
)
834 int j
= reloc_type
== BFD_RELOC_RISCV_JMP
;
835 int best_case
= riscv_insn_length (ip
->insn_opcode
);
836 unsigned worst_case
= relaxed_branch_length (NULL
, NULL
, 0);
837 add_relaxed_insn (ip
, worst_case
, best_case
,
838 RELAX_BRANCH_ENCODE (j
, best_case
== 2, worst_case
),
839 address_expr
->X_add_symbol
,
840 address_expr
->X_add_number
);
845 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
);
847 as_bad (_("Unsupported RISC-V relocation number %d"), reloc_type
);
849 ip
->fixp
= fix_new_exp (ip
->frag
, ip
->where
,
850 bfd_get_reloc_size (howto
),
851 address_expr
, FALSE
, reloc_type
);
853 ip
->fixp
->fx_tcbit
= riscv_opts
.relax
;
860 /* We need to start a new frag after any instruction that can be
861 optimized away or compressed by the linker during relaxation, to prevent
862 the assembler from computing static offsets across such an instruction.
863 This is necessary to get correct EH info. */
864 if (reloc_type
== BFD_RELOC_RISCV_CALL
865 || reloc_type
== BFD_RELOC_RISCV_CALL_PLT
866 || reloc_type
== BFD_RELOC_RISCV_HI20
867 || reloc_type
== BFD_RELOC_RISCV_PCREL_HI20
868 || reloc_type
== BFD_RELOC_RISCV_TPREL_HI20
869 || reloc_type
== BFD_RELOC_RISCV_TPREL_ADD
)
871 frag_wane (frag_now
);
876 /* Build an instruction created by a macro expansion. This is passed
877 a pointer to the count of instructions created so far, an
878 expression, the name of the instruction to build, an operand format
879 string, and corresponding arguments. */
882 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
884 const struct riscv_opcode
*mo
;
885 struct riscv_cl_insn insn
;
886 bfd_reloc_code_real_type r
;
889 va_start (args
, fmt
);
891 r
= BFD_RELOC_UNUSED
;
892 mo
= (struct riscv_opcode
*) hash_find (op_hash
, name
);
895 /* Find a non-RVC variant of the instruction. append_insn will compress
897 while (riscv_insn_length (mo
->match
) < 4)
899 gas_assert (strcmp (name
, mo
->name
) == 0);
901 create_insn (&insn
, mo
);
907 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
911 INSERT_OPERAND (RS1
, insn
, va_arg (args
, int));
915 INSERT_OPERAND (RS2
, insn
, va_arg (args
, int));
919 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
925 gas_assert (ep
!= NULL
);
926 r
= va_arg (args
, int);
934 as_fatal (_("internal error: invalid macro"));
939 gas_assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
941 append_insn (&insn
, ep
, r
);
944 /* Build an instruction created by a macro expansion. Like md_assemble but
945 accept a printf-style format string and arguments. */
948 md_assemblef (const char *format
, ...)
954 va_start (ap
, format
);
956 r
= vasprintf (&buf
, format
, ap
);
959 as_fatal (_("internal error: vasprintf failed"));
967 /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits
970 normalize_constant_expr (expressionS
*ex
)
974 if ((ex
->X_op
== O_constant
|| ex
->X_op
== O_symbol
)
975 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
976 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
980 /* Fail if an expression EX is not a constant. IP is the instruction using EX.
981 MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */
984 check_absolute_expr (struct riscv_cl_insn
*ip
, expressionS
*ex
,
985 bfd_boolean maybe_csr
)
987 if (ex
->X_op
== O_big
)
988 as_bad (_("unsupported large constant"));
989 else if (maybe_csr
&& ex
->X_op
== O_symbol
)
990 as_bad (_("unknown CSR `%s'"),
991 S_GET_NAME (ex
->X_add_symbol
));
992 else if (ex
->X_op
!= O_constant
)
993 as_bad (_("Instruction %s requires absolute expression"),
995 normalize_constant_expr (ex
);
999 make_internal_label (void)
1001 return (symbolS
*) local_symbol_make (FAKE_LABEL_NAME
, now_seg
,
1002 (valueT
) frag_now_fix (), frag_now
);
1005 /* Load an entry from the GOT. */
1007 pcrel_access (int destreg
, int tempreg
, expressionS
*ep
,
1008 const char *lo_insn
, const char *lo_pattern
,
1009 bfd_reloc_code_real_type hi_reloc
,
1010 bfd_reloc_code_real_type lo_reloc
)
1013 ep2
.X_op
= O_symbol
;
1014 ep2
.X_add_symbol
= make_internal_label ();
1015 ep2
.X_add_number
= 0;
1017 macro_build (ep
, "auipc", "d,u", tempreg
, hi_reloc
);
1018 macro_build (&ep2
, lo_insn
, lo_pattern
, destreg
, tempreg
, lo_reloc
);
1022 pcrel_load (int destreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1023 bfd_reloc_code_real_type hi_reloc
,
1024 bfd_reloc_code_real_type lo_reloc
)
1026 pcrel_access (destreg
, tempreg
, ep
, lo_insn
, "d,s,j", hi_reloc
, lo_reloc
);
1030 pcrel_store (int srcreg
, int tempreg
, expressionS
*ep
, const char *lo_insn
,
1031 bfd_reloc_code_real_type hi_reloc
,
1032 bfd_reloc_code_real_type lo_reloc
)
1034 pcrel_access (srcreg
, tempreg
, ep
, lo_insn
, "t,s,q", hi_reloc
, lo_reloc
);
1037 /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */
1039 riscv_call (int destreg
, int tempreg
, expressionS
*ep
,
1040 bfd_reloc_code_real_type reloc
)
1042 macro_build (ep
, "auipc", "d,u", tempreg
, reloc
);
1043 macro_build (NULL
, "jalr", "d,s", destreg
, tempreg
);
1046 /* Load an integer constant into a register. */
1049 load_const (int reg
, expressionS
*ep
)
1051 int shift
= RISCV_IMM_BITS
;
1053 expressionS upper
= *ep
, lower
= *ep
;
1054 lower
.X_add_number
= (int32_t) ep
->X_add_number
<< (32-shift
) >> (32-shift
);
1055 upper
.X_add_number
-= lower
.X_add_number
;
1057 if (ep
->X_op
!= O_constant
)
1059 as_bad (_("unsupported large constant"));
1063 if (xlen
> 32 && !IS_SEXT_32BIT_NUM (ep
->X_add_number
))
1065 /* Reduce to a signed 32-bit constant using SLLI and ADDI. */
1066 while (((upper
.X_add_number
>> shift
) & 1) == 0)
1069 upper
.X_add_number
= (int64_t) upper
.X_add_number
>> shift
;
1070 load_const (reg
, &upper
);
1072 md_assemblef ("slli x%d, x%d, 0x%x", reg
, reg
, shift
);
1073 if (lower
.X_add_number
!= 0)
1074 md_assemblef ("addi x%d, x%d, %" BFD_VMA_FMT
"d", reg
, reg
,
1075 lower
.X_add_number
);
1079 /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */
1082 if (upper
.X_add_number
!= 0)
1084 /* Discard low part and zero-extend upper immediate. */
1085 upper_imm
= ((uint32_t)upper
.X_add_number
>> shift
);
1087 md_assemblef ("lui x%d, 0x%" BFD_VMA_FMT
"x", reg
, upper_imm
);
1091 if (lower
.X_add_number
!= 0 || hi_reg
== 0)
1092 md_assemblef ("%s x%d, x%d, %" BFD_VMA_FMT
"d", ADD32_INSN
, reg
, hi_reg
,
1093 lower
.X_add_number
);
1097 /* Expand RISC-V assembly macros into one or more instructions. */
1099 macro (struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1100 bfd_reloc_code_real_type
*imm_reloc
)
1102 int rd
= (ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
;
1103 int rs1
= (ip
->insn_opcode
>> OP_SH_RS1
) & OP_MASK_RS1
;
1104 int rs2
= (ip
->insn_opcode
>> OP_SH_RS2
) & OP_MASK_RS2
;
1105 int mask
= ip
->insn_mo
->mask
;
1110 load_const (rd
, imm_expr
);
1115 /* Load the address of a symbol into a register. */
1116 if (!IS_SEXT_32BIT_NUM (imm_expr
->X_add_number
))
1117 as_bad (_("offset too large"));
1119 if (imm_expr
->X_op
== O_constant
)
1120 load_const (rd
, imm_expr
);
1121 else if (riscv_opts
.pic
&& mask
== M_LA
) /* Global PIC symbol */
1122 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1123 BFD_RELOC_RISCV_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1124 else /* Local PIC symbol, or any non-PIC symbol */
1125 pcrel_load (rd
, rd
, imm_expr
, "addi",
1126 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1130 pcrel_load (rd
, rd
, imm_expr
, "addi",
1131 BFD_RELOC_RISCV_TLS_GD_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1135 pcrel_load (rd
, rd
, imm_expr
, LOAD_ADDRESS_INSN
,
1136 BFD_RELOC_RISCV_TLS_GOT_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1140 pcrel_load (rd
, rd
, imm_expr
, "lb",
1141 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1145 pcrel_load (rd
, rd
, imm_expr
, "lbu",
1146 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1150 pcrel_load (rd
, rd
, imm_expr
, "lh",
1151 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1155 pcrel_load (rd
, rd
, imm_expr
, "lhu",
1156 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1160 pcrel_load (rd
, rd
, imm_expr
, "lw",
1161 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1165 pcrel_load (rd
, rd
, imm_expr
, "lwu",
1166 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1170 pcrel_load (rd
, rd
, imm_expr
, "ld",
1171 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1175 pcrel_load (rd
, rs1
, imm_expr
, "flw",
1176 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1180 pcrel_load (rd
, rs1
, imm_expr
, "fld",
1181 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_I
);
1185 pcrel_store (rs2
, rs1
, imm_expr
, "sb",
1186 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1190 pcrel_store (rs2
, rs1
, imm_expr
, "sh",
1191 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1195 pcrel_store (rs2
, rs1
, imm_expr
, "sw",
1196 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1200 pcrel_store (rs2
, rs1
, imm_expr
, "sd",
1201 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1205 pcrel_store (rs2
, rs1
, imm_expr
, "fsw",
1206 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1210 pcrel_store (rs2
, rs1
, imm_expr
, "fsd",
1211 BFD_RELOC_RISCV_PCREL_HI20
, BFD_RELOC_RISCV_PCREL_LO12_S
);
1215 riscv_call (rd
, rs1
, imm_expr
, *imm_reloc
);
1219 as_bad (_("Macro %s not implemented"), ip
->insn_mo
->name
);
1224 static const struct percent_op_match percent_op_utype
[] =
1226 {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20
},
1227 {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20
},
1228 {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20
},
1229 {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20
},
1230 {"%hi", BFD_RELOC_RISCV_HI20
},
1234 static const struct percent_op_match percent_op_itype
[] =
1236 {"%lo", BFD_RELOC_RISCV_LO12_I
},
1237 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I
},
1238 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I
},
1242 static const struct percent_op_match percent_op_stype
[] =
1244 {"%lo", BFD_RELOC_RISCV_LO12_S
},
1245 {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S
},
1246 {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S
},
1250 static const struct percent_op_match percent_op_rtype
[] =
1252 {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD
},
1256 static const struct percent_op_match percent_op_null
[] =
1261 /* Return true if *STR points to a relocation operator. When returning true,
1262 move *STR over the operator and store its relocation code in *RELOC.
1263 Leave both *STR and *RELOC alone when returning false. */
1266 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
,
1267 const struct percent_op_match
*percent_op
)
1269 for ( ; percent_op
->str
; percent_op
++)
1270 if (strncasecmp (*str
, percent_op
->str
, strlen (percent_op
->str
)) == 0)
1272 int len
= strlen (percent_op
->str
);
1274 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
1277 *str
+= strlen (percent_op
->str
);
1278 *reloc
= percent_op
->reloc
;
1280 /* Check whether the output BFD supports this relocation.
1281 If not, issue an error and fall back on something safe. */
1282 if (*reloc
!= BFD_RELOC_UNUSED
1283 && !bfd_reloc_type_lookup (stdoutput
, *reloc
))
1285 as_bad ("relocation %s isn't supported by the current ABI",
1287 *reloc
= BFD_RELOC_UNUSED
;
1295 my_getExpression (expressionS
*ep
, char *str
)
1299 save_in
= input_line_pointer
;
1300 input_line_pointer
= str
;
1302 expr_end
= input_line_pointer
;
1303 input_line_pointer
= save_in
;
1306 /* Parse string STR as a 16-bit relocatable operand. Store the
1307 expression in *EP and the relocation, if any, in RELOC.
1308 Return the number of relocation operators used (0 or 1).
1310 On exit, EXPR_END points to the first character after the expression. */
1313 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1314 char *str
, const struct percent_op_match
*percent_op
)
1317 unsigned crux_depth
, str_depth
, regno
;
1320 /* First, check for integer registers. No callers can accept a reg, but
1321 we need to avoid accidentally creating a useless undefined symbol below,
1322 if this is an instruction pattern that can't match. A glibc build fails
1323 if this is removed. */
1324 if (reg_lookup (&str
, RCLASS_GPR
, ®no
))
1326 ep
->X_op
= O_register
;
1327 ep
->X_add_number
= regno
;
1332 /* Search for the start of the main expression.
1333 End the loop with CRUX pointing to the start
1334 of the main expression and with CRUX_DEPTH containing the number
1335 of open brackets at that point. */
1342 crux_depth
= str_depth
;
1344 /* Skip over whitespace and brackets, keeping count of the number
1346 while (*str
== ' ' || *str
== '\t' || *str
== '(')
1352 && parse_relocation (&str
, reloc
, percent_op
));
1354 my_getExpression (ep
, crux
);
1357 /* Match every open bracket. */
1358 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
1363 as_bad ("unclosed '('");
1370 /* Parse opcode name, could be an mnemonics or number. */
1372 my_getOpcodeExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
1373 char *str
, const struct percent_op_match
*percent_op
)
1375 const struct opcode_name_t
*o
= opcode_name_lookup (&str
);
1379 ep
->X_op
= O_constant
;
1380 ep
->X_add_number
= o
->val
;
1384 return my_getSmallExpression (ep
, reloc
, str
, percent_op
);
1387 /* Detect and handle implicitly zero load-store offsets. For example,
1388 "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return TRUE iff such
1389 an implicit offset was detected. */
1392 riscv_handle_implicit_zero_offset (expressionS
*ep
, const char *s
)
1394 /* Check whether there is only a single bracketed expression left.
1395 If so, it must be the base register and the constant must be zero. */
1396 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
1398 ep
->X_op
= O_constant
;
1399 ep
->X_add_number
= 0;
1406 /* This routine assembles an instruction into its binary format. As a
1407 side effect, it sets the global variable imm_reloc to the type of
1408 relocation to do if one of the operands is an address expression. */
1411 riscv_ip (char *str
, struct riscv_cl_insn
*ip
, expressionS
*imm_expr
,
1412 bfd_reloc_code_real_type
*imm_reloc
, struct hash_control
*hash
)
1417 struct riscv_opcode
*insn
;
1422 const struct percent_op_match
*p
;
1423 const char *error
= "unrecognized opcode";
1425 /* Parse the name of the instruction. Terminate the string if whitespace
1426 is found so that hash_find only sees the name part of the string. */
1427 for (s
= str
; *s
!= '\0'; ++s
)
1435 insn
= (struct riscv_opcode
*) hash_find (hash
, str
);
1438 for ( ; insn
&& insn
->name
&& strcmp (insn
->name
, str
) == 0; insn
++)
1440 if ((insn
->xlen_requirement
!= 0) && (xlen
!= insn
->xlen_requirement
))
1443 if (!riscv_multi_subset_supports (insn
->insn_class
))
1446 create_insn (ip
, insn
);
1449 imm_expr
->X_op
= O_absent
;
1450 *imm_reloc
= BFD_RELOC_UNUSED
;
1451 p
= percent_op_itype
;
1453 for (args
= insn
->args
;; ++args
)
1455 s
+= strspn (s
, " \t");
1458 case '\0': /* End of args. */
1459 if (insn
->pinfo
!= INSN_MACRO
)
1461 if (!insn
->match_func (insn
, ip
->insn_opcode
))
1464 /* For .insn, insn->match and insn->mask are 0. */
1465 if (riscv_insn_length ((insn
->match
== 0 && insn
->mask
== 0)
1473 /* Successful assembly. */
1480 case 's': /* RS1 x8-x15 */
1481 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1482 || !(regno
>= 8 && regno
<= 15))
1484 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1486 case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */
1487 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1488 || EXTRACT_OPERAND (CRS1S
, ip
->insn_opcode
) + 8 != regno
)
1491 case 't': /* RS2 x8-x15 */
1492 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1493 || !(regno
>= 8 && regno
<= 15))
1495 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1497 case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */
1498 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1499 || EXTRACT_OPERAND (CRS2S
, ip
->insn_opcode
) + 8 != regno
)
1502 case 'U': /* RS1, constrained to equal RD. */
1503 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1504 || EXTRACT_OPERAND (RD
, ip
->insn_opcode
) != regno
)
1508 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
))
1510 INSERT_OPERAND (CRS2
, *ip
, regno
);
1512 case 'c': /* RS1, constrained to equal sp. */
1513 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1517 case 'z': /* RS2, contrained to equal x0. */
1518 if (!reg_lookup (&s
, RCLASS_GPR
, ®no
)
1523 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1524 || imm_expr
->X_op
!= O_constant
1525 || imm_expr
->X_add_number
<= 0
1526 || imm_expr
->X_add_number
>= 64)
1528 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1531 imm_expr
->X_op
= O_absent
;
1534 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1535 || imm_expr
->X_op
!= O_constant
1536 || !VALID_RVC_IMM (imm_expr
->X_add_number
)
1537 || imm_expr
->X_add_number
<= 0
1538 || imm_expr
->X_add_number
>= 32)
1540 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1543 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1544 || imm_expr
->X_op
!= O_constant
1545 || !VALID_RVC_UIMM8 (imm_expr
->X_add_number
)
1546 || imm_expr
->X_add_number
< 0
1547 || imm_expr
->X_add_number
>= 256)
1549 ip
->insn_opcode
|= ENCODE_RVC_UIMM8 (imm_expr
->X_add_number
);
1552 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1553 || imm_expr
->X_op
!= O_constant
1554 || imm_expr
->X_add_number
== 0
1555 || !VALID_RVC_SIMM3 (imm_expr
->X_add_number
))
1557 ip
->insn_opcode
|= ENCODE_RVC_SIMM3 (imm_expr
->X_add_number
);
1560 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1561 || imm_expr
->X_op
!= O_constant
1562 || imm_expr
->X_add_number
== 0
1563 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1565 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1568 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1570 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1571 || imm_expr
->X_op
!= O_constant
1572 || !VALID_RVC_LW_IMM (imm_expr
->X_add_number
))
1574 ip
->insn_opcode
|= ENCODE_RVC_LW_IMM (imm_expr
->X_add_number
);
1577 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1579 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1580 || imm_expr
->X_op
!= O_constant
1581 || !VALID_RVC_LD_IMM (imm_expr
->X_add_number
))
1583 ip
->insn_opcode
|= ENCODE_RVC_LD_IMM (imm_expr
->X_add_number
);
1586 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1588 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1589 || imm_expr
->X_op
!= O_constant
1590 || !VALID_RVC_LWSP_IMM (imm_expr
->X_add_number
))
1593 ENCODE_RVC_LWSP_IMM (imm_expr
->X_add_number
);
1596 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1598 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1599 || imm_expr
->X_op
!= O_constant
1600 || !VALID_RVC_LDSP_IMM (imm_expr
->X_add_number
))
1603 ENCODE_RVC_LDSP_IMM (imm_expr
->X_add_number
);
1606 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1607 || imm_expr
->X_op
!= O_constant
1608 /* C.addiw, c.li, and c.andi allow zero immediate.
1609 C.addi allows zero immediate as hint. Otherwise this
1611 || !VALID_RVC_IMM (imm_expr
->X_add_number
))
1613 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1616 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1617 || imm_expr
->X_op
!= O_constant
1618 || !VALID_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
)
1619 || imm_expr
->X_add_number
== 0)
1622 ENCODE_RVC_ADDI4SPN_IMM (imm_expr
->X_add_number
);
1625 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1626 || imm_expr
->X_op
!= O_constant
1627 || !VALID_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
)
1628 || imm_expr
->X_add_number
== 0)
1631 ENCODE_RVC_ADDI16SP_IMM (imm_expr
->X_add_number
);
1634 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1636 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1637 || imm_expr
->X_op
!= O_constant
1638 || !VALID_RVC_SWSP_IMM (imm_expr
->X_add_number
))
1641 ENCODE_RVC_SWSP_IMM (imm_expr
->X_add_number
);
1644 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1646 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1647 || imm_expr
->X_op
!= O_constant
1648 || !VALID_RVC_SDSP_IMM (imm_expr
->X_add_number
))
1651 ENCODE_RVC_SDSP_IMM (imm_expr
->X_add_number
);
1654 p
= percent_op_utype
;
1655 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1658 if (imm_expr
->X_op
!= O_constant
1659 || imm_expr
->X_add_number
<= 0
1660 || imm_expr
->X_add_number
>= RISCV_BIGIMM_REACH
1661 || (imm_expr
->X_add_number
>= RISCV_RVC_IMM_REACH
/ 2
1662 && (imm_expr
->X_add_number
<
1663 RISCV_BIGIMM_REACH
- RISCV_RVC_IMM_REACH
/ 2)))
1665 ip
->insn_opcode
|= ENCODE_RVC_IMM (imm_expr
->X_add_number
);
1668 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1669 || (imm_expr
->X_add_number
& (RISCV_IMM_REACH
- 1))
1670 || ((int32_t)imm_expr
->X_add_number
1671 != imm_expr
->X_add_number
))
1673 imm_expr
->X_add_number
=
1674 ((uint32_t) imm_expr
->X_add_number
) >> RISCV_IMM_BITS
;
1680 case 'S': /* Floating-point RS1 x8-x15. */
1681 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1682 || !(regno
>= 8 && regno
<= 15))
1684 INSERT_OPERAND (CRS1S
, *ip
, regno
% 8);
1686 case 'D': /* Floating-point RS2 x8-x15. */
1687 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
)
1688 || !(regno
>= 8 && regno
<= 15))
1690 INSERT_OPERAND (CRS2S
, *ip
, regno
% 8);
1692 case 'T': /* Floating-point RS2. */
1693 if (!reg_lookup (&s
, RCLASS_FPR
, ®no
))
1695 INSERT_OPERAND (CRS2
, *ip
, regno
);
1701 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1702 || imm_expr
->X_op
!= O_constant
1703 || imm_expr
->X_add_number
< 0
1704 || imm_expr
->X_add_number
>= 64)
1706 as_bad (_("bad value for funct6 field, "
1707 "value must be 0...64"));
1711 INSERT_OPERAND (CFUNCT6
, *ip
, imm_expr
->X_add_number
);
1712 imm_expr
->X_op
= O_absent
;
1716 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1717 || imm_expr
->X_op
!= O_constant
1718 || imm_expr
->X_add_number
< 0
1719 || imm_expr
->X_add_number
>= 16)
1721 as_bad (_("bad value for funct4 field, "
1722 "value must be 0...15"));
1726 INSERT_OPERAND (CFUNCT4
, *ip
, imm_expr
->X_add_number
);
1727 imm_expr
->X_op
= O_absent
;
1731 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1732 || imm_expr
->X_op
!= O_constant
1733 || imm_expr
->X_add_number
< 0
1734 || imm_expr
->X_add_number
>= 8)
1736 as_bad (_("bad value for funct3 field, "
1737 "value must be 0...7"));
1740 INSERT_OPERAND (CFUNCT3
, *ip
, imm_expr
->X_add_number
);
1741 imm_expr
->X_op
= O_absent
;
1745 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
1746 || imm_expr
->X_op
!= O_constant
1747 || imm_expr
->X_add_number
< 0
1748 || imm_expr
->X_add_number
>= 4)
1750 as_bad (_("bad value for funct2 field, "
1751 "value must be 0...3"));
1754 INSERT_OPERAND (CFUNCT2
, *ip
, imm_expr
->X_add_number
);
1755 imm_expr
->X_op
= O_absent
;
1759 as_bad (_("bad compressed FUNCT field"
1760 " specifier 'CF%c'\n"),
1766 as_bad (_("bad RVC field specifier 'C%c'\n"), *args
);
1785 case '<': /* Shift amount, 0 - 31. */
1786 my_getExpression (imm_expr
, s
);
1787 check_absolute_expr (ip
, imm_expr
, FALSE
);
1788 if ((unsigned long) imm_expr
->X_add_number
> 31)
1789 as_bad (_("Improper shift amount (%lu)"),
1790 (unsigned long) imm_expr
->X_add_number
);
1791 INSERT_OPERAND (SHAMTW
, *ip
, imm_expr
->X_add_number
);
1792 imm_expr
->X_op
= O_absent
;
1796 case '>': /* Shift amount, 0 - (XLEN-1). */
1797 my_getExpression (imm_expr
, s
);
1798 check_absolute_expr (ip
, imm_expr
, FALSE
);
1799 if ((unsigned long) imm_expr
->X_add_number
>= xlen
)
1800 as_bad (_("Improper shift amount (%lu)"),
1801 (unsigned long) imm_expr
->X_add_number
);
1802 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
->X_add_number
);
1803 imm_expr
->X_op
= O_absent
;
1807 case 'Z': /* CSRRxI immediate. */
1808 my_getExpression (imm_expr
, s
);
1809 check_absolute_expr (ip
, imm_expr
, FALSE
);
1810 if ((unsigned long) imm_expr
->X_add_number
> 31)
1811 as_bad (_("Improper CSRxI immediate (%lu)"),
1812 (unsigned long) imm_expr
->X_add_number
);
1813 INSERT_OPERAND (RS1
, *ip
, imm_expr
->X_add_number
);
1814 imm_expr
->X_op
= O_absent
;
1818 case 'E': /* Control register. */
1819 if (reg_lookup (&s
, RCLASS_CSR
, ®no
))
1820 INSERT_OPERAND (CSR
, *ip
, regno
);
1823 my_getExpression (imm_expr
, s
);
1824 check_absolute_expr (ip
, imm_expr
, TRUE
);
1825 if ((unsigned long) imm_expr
->X_add_number
> 0xfff)
1826 as_bad (_("Improper CSR address (%lu)"),
1827 (unsigned long) imm_expr
->X_add_number
);
1828 INSERT_OPERAND (CSR
, *ip
, imm_expr
->X_add_number
);
1829 imm_expr
->X_op
= O_absent
;
1834 case 'm': /* Rounding mode. */
1835 if (arg_lookup (&s
, riscv_rm
, ARRAY_SIZE (riscv_rm
), ®no
))
1837 INSERT_OPERAND (RM
, *ip
, regno
);
1843 case 'Q': /* Fence predecessor/successor. */
1844 if (arg_lookup (&s
, riscv_pred_succ
, ARRAY_SIZE (riscv_pred_succ
),
1848 INSERT_OPERAND (PRED
, *ip
, regno
);
1850 INSERT_OPERAND (SUCC
, *ip
, regno
);
1855 case 'd': /* Destination register. */
1856 case 's': /* Source register. */
1857 case 't': /* Target register. */
1858 case 'r': /* rs3. */
1859 if (reg_lookup (&s
, RCLASS_GPR
, ®no
))
1865 /* Now that we have assembled one operand, we use the args
1866 string to figure out where it goes in the instruction. */
1870 INSERT_OPERAND (RS1
, *ip
, regno
);
1873 INSERT_OPERAND (RD
, *ip
, regno
);
1876 INSERT_OPERAND (RS2
, *ip
, regno
);
1879 INSERT_OPERAND (RS3
, *ip
, regno
);
1886 case 'D': /* Floating point rd. */
1887 case 'S': /* Floating point rs1. */
1888 case 'T': /* Floating point rs2. */
1889 case 'U': /* Floating point rs1 and rs2. */
1890 case 'R': /* Floating point rs3. */
1891 if (reg_lookup (&s
, RCLASS_FPR
, ®no
))
1899 INSERT_OPERAND (RD
, *ip
, regno
);
1902 INSERT_OPERAND (RS1
, *ip
, regno
);
1905 INSERT_OPERAND (RS1
, *ip
, regno
);
1908 INSERT_OPERAND (RS2
, *ip
, regno
);
1911 INSERT_OPERAND (RS3
, *ip
, regno
);
1920 my_getExpression (imm_expr
, s
);
1921 if (imm_expr
->X_op
!= O_big
1922 && imm_expr
->X_op
!= O_constant
)
1924 normalize_constant_expr (imm_expr
);
1929 my_getExpression (imm_expr
, s
);
1930 normalize_constant_expr (imm_expr
);
1931 /* The 'A' format specifier must be a symbol. */
1932 if (imm_expr
->X_op
!= O_symbol
)
1934 *imm_reloc
= BFD_RELOC_32
;
1939 my_getExpression (imm_expr
, s
);
1940 normalize_constant_expr (imm_expr
);
1941 /* The 'B' format specifier must be a symbol or a constant. */
1942 if (imm_expr
->X_op
!= O_symbol
&& imm_expr
->X_op
!= O_constant
)
1944 if (imm_expr
->X_op
== O_symbol
)
1945 *imm_reloc
= BFD_RELOC_32
;
1949 case 'j': /* Sign-extended immediate. */
1950 p
= percent_op_itype
;
1951 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1953 case 'q': /* Store displacement. */
1954 p
= percent_op_stype
;
1955 *imm_reloc
= BFD_RELOC_RISCV_LO12_S
;
1957 case 'o': /* Load displacement. */
1958 p
= percent_op_itype
;
1959 *imm_reloc
= BFD_RELOC_RISCV_LO12_I
;
1961 case '1': /* 4-operand add, must be %tprel_add. */
1962 p
= percent_op_rtype
;
1964 case '0': /* AMO "displacement," which must be zero. */
1965 p
= percent_op_null
;
1967 if (riscv_handle_implicit_zero_offset (imm_expr
, s
))
1970 /* If this value won't fit into a 16 bit offset, then go
1971 find a macro that will generate the 32 bit offset
1973 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1975 normalize_constant_expr (imm_expr
);
1976 if (imm_expr
->X_op
!= O_constant
1977 || (*args
== '0' && imm_expr
->X_add_number
!= 0)
1979 || imm_expr
->X_add_number
>= (signed)RISCV_IMM_REACH
/2
1980 || imm_expr
->X_add_number
< -(signed)RISCV_IMM_REACH
/2)
1987 case 'p': /* PC-relative offset. */
1989 *imm_reloc
= BFD_RELOC_12_PCREL
;
1990 my_getExpression (imm_expr
, s
);
1994 case 'u': /* Upper 20 bits. */
1995 p
= percent_op_utype
;
1996 if (!my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
))
1998 if (imm_expr
->X_op
!= O_constant
)
2001 if (imm_expr
->X_add_number
< 0
2002 || imm_expr
->X_add_number
>= (signed)RISCV_BIGIMM_REACH
)
2003 as_bad (_("lui expression not in range 0..1048575"));
2005 *imm_reloc
= BFD_RELOC_RISCV_HI20
;
2006 imm_expr
->X_add_number
<<= RISCV_IMM_BITS
;
2011 case 'a': /* 20-bit PC-relative offset. */
2013 my_getExpression (imm_expr
, s
);
2015 *imm_reloc
= BFD_RELOC_RISCV_JMP
;
2019 my_getExpression (imm_expr
, s
);
2021 if (strcmp (s
, "@plt") == 0)
2023 *imm_reloc
= BFD_RELOC_RISCV_CALL_PLT
;
2027 *imm_reloc
= BFD_RELOC_RISCV_CALL
;
2033 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2034 || imm_expr
->X_op
!= O_constant
2035 || imm_expr
->X_add_number
< 0
2036 || imm_expr
->X_add_number
>= 128
2037 || (imm_expr
->X_add_number
& 0x3) != 3)
2039 as_bad (_("bad value for opcode field, "
2040 "value must be 0...127 and "
2041 "lower 2 bits must be 0x3"));
2045 INSERT_OPERAND (OP
, *ip
, imm_expr
->X_add_number
);
2046 imm_expr
->X_op
= O_absent
;
2050 if (my_getOpcodeExpression (imm_expr
, imm_reloc
, s
, p
)
2051 || imm_expr
->X_op
!= O_constant
2052 || imm_expr
->X_add_number
< 0
2053 || imm_expr
->X_add_number
>= 3)
2055 as_bad (_("bad value for opcode field, "
2056 "value must be 0...2"));
2060 INSERT_OPERAND (OP2
, *ip
, imm_expr
->X_add_number
);
2061 imm_expr
->X_op
= O_absent
;
2065 as_bad (_("bad Opcode field specifier 'O%c'\n"), *args
);
2073 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2074 || imm_expr
->X_op
!= O_constant
2075 || imm_expr
->X_add_number
< 0
2076 || imm_expr
->X_add_number
>= 128)
2078 as_bad (_("bad value for funct7 field, "
2079 "value must be 0...127"));
2083 INSERT_OPERAND (FUNCT7
, *ip
, imm_expr
->X_add_number
);
2084 imm_expr
->X_op
= O_absent
;
2088 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2089 || imm_expr
->X_op
!= O_constant
2090 || imm_expr
->X_add_number
< 0
2091 || imm_expr
->X_add_number
>= 8)
2093 as_bad (_("bad value for funct3 field, "
2094 "value must be 0...7"));
2098 INSERT_OPERAND (FUNCT3
, *ip
, imm_expr
->X_add_number
);
2099 imm_expr
->X_op
= O_absent
;
2103 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2104 || imm_expr
->X_op
!= O_constant
2105 || imm_expr
->X_add_number
< 0
2106 || imm_expr
->X_add_number
>= 4)
2108 as_bad (_("bad value for funct2 field, "
2109 "value must be 0...3"));
2113 INSERT_OPERAND (FUNCT2
, *ip
, imm_expr
->X_add_number
);
2114 imm_expr
->X_op
= O_absent
;
2119 as_bad (_("bad FUNCT field specifier 'F%c'\n"), *args
);
2124 if (my_getSmallExpression (imm_expr
, imm_reloc
, s
, p
)
2125 || imm_expr
->X_op
!= O_constant
2126 || imm_expr
->X_add_number
!= 0)
2129 imm_expr
->X_op
= O_absent
;
2133 as_fatal (_("internal error: bad argument type %c"), *args
);
2138 error
= _("illegal operands");
2142 /* Restore the character we might have clobbered above. */
2144 *(argsStart
- 1) = save_c
;
2150 md_assemble (char *str
)
2152 struct riscv_cl_insn insn
;
2153 expressionS imm_expr
;
2154 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
2156 const char *error
= riscv_ip (str
, &insn
, &imm_expr
, &imm_reloc
, op_hash
);
2158 start_assemble
= TRUE
;
2162 as_bad ("%s `%s'", error
, str
);
2166 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2167 macro (&insn
, &imm_expr
, &imm_reloc
);
2169 append_insn (&insn
, &imm_expr
, imm_reloc
);
2173 md_atof (int type
, char *litP
, int *sizeP
)
2175 return ieee_md_atof (type
, litP
, sizeP
, TARGET_BYTES_BIG_ENDIAN
);
2179 md_number_to_chars (char *buf
, valueT val
, int n
)
2181 number_to_chars_littleendian (buf
, val
, n
);
2184 const char *md_shortopts
= "O::g::G:";
2188 OPTION_MARCH
= OPTION_MD_BASE
,
2195 OPTION_NO_ARCH_ATTR
,
2199 struct option md_longopts
[] =
2201 {"march", required_argument
, NULL
, OPTION_MARCH
},
2202 {"fPIC", no_argument
, NULL
, OPTION_PIC
},
2203 {"fpic", no_argument
, NULL
, OPTION_PIC
},
2204 {"fno-pic", no_argument
, NULL
, OPTION_NO_PIC
},
2205 {"mabi", required_argument
, NULL
, OPTION_MABI
},
2206 {"mrelax", no_argument
, NULL
, OPTION_RELAX
},
2207 {"mno-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
2208 {"march-attr", no_argument
, NULL
, OPTION_ARCH_ATTR
},
2209 {"mno-arch-attr", no_argument
, NULL
, OPTION_NO_ARCH_ATTR
},
2211 {NULL
, no_argument
, NULL
, 0}
2213 size_t md_longopts_size
= sizeof (md_longopts
);
2216 FLOAT_ABI_DEFAULT
= -1,
2222 static enum float_abi float_abi
= FLOAT_ABI_DEFAULT
;
2225 riscv_set_abi (unsigned new_xlen
, enum float_abi new_float_abi
, bfd_boolean rve
)
2227 abi_xlen
= new_xlen
;
2228 float_abi
= new_float_abi
;
2233 md_parse_option (int c
, const char *arg
)
2238 riscv_set_arch (arg
);
2242 riscv_opts
.pic
= FALSE
;
2246 riscv_opts
.pic
= TRUE
;
2250 if (strcmp (arg
, "ilp32") == 0)
2251 riscv_set_abi (32, FLOAT_ABI_SOFT
, FALSE
);
2252 else if (strcmp (arg
, "ilp32e") == 0)
2253 riscv_set_abi (32, FLOAT_ABI_SOFT
, TRUE
);
2254 else if (strcmp (arg
, "ilp32f") == 0)
2255 riscv_set_abi (32, FLOAT_ABI_SINGLE
, FALSE
);
2256 else if (strcmp (arg
, "ilp32d") == 0)
2257 riscv_set_abi (32, FLOAT_ABI_DOUBLE
, FALSE
);
2258 else if (strcmp (arg
, "ilp32q") == 0)
2259 riscv_set_abi (32, FLOAT_ABI_QUAD
, FALSE
);
2260 else if (strcmp (arg
, "lp64") == 0)
2261 riscv_set_abi (64, FLOAT_ABI_SOFT
, FALSE
);
2262 else if (strcmp (arg
, "lp64f") == 0)
2263 riscv_set_abi (64, FLOAT_ABI_SINGLE
, FALSE
);
2264 else if (strcmp (arg
, "lp64d") == 0)
2265 riscv_set_abi (64, FLOAT_ABI_DOUBLE
, FALSE
);
2266 else if (strcmp (arg
, "lp64q") == 0)
2267 riscv_set_abi (64, FLOAT_ABI_QUAD
, FALSE
);
2273 riscv_opts
.relax
= TRUE
;
2276 case OPTION_NO_RELAX
:
2277 riscv_opts
.relax
= FALSE
;
2280 case OPTION_ARCH_ATTR
:
2281 riscv_opts
.arch_attr
= TRUE
;
2284 case OPTION_NO_ARCH_ATTR
:
2285 riscv_opts
.arch_attr
= FALSE
;
2296 riscv_after_parse_args (void)
2300 if (strcmp (default_arch
, "riscv32") == 0)
2302 else if (strcmp (default_arch
, "riscv64") == 0)
2305 as_bad ("unknown default architecture `%s'", default_arch
);
2308 if (riscv_subsets
.head
== NULL
)
2309 riscv_set_arch (xlen
== 64 ? "rv64g" : "rv32g");
2311 /* Add the RVC extension, regardless of -march, to support .option rvc. */
2312 riscv_set_rvc (FALSE
);
2313 if (riscv_subset_supports ("c"))
2314 riscv_set_rvc (TRUE
);
2316 /* Enable RVE if specified by the -march option. */
2317 riscv_set_rve (FALSE
);
2318 if (riscv_subset_supports ("e"))
2319 riscv_set_rve (TRUE
);
2321 /* Infer ABI from ISA if not specified on command line. */
2324 else if (abi_xlen
> xlen
)
2325 as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen
, xlen
);
2326 else if (abi_xlen
< xlen
)
2327 as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen
, xlen
);
2329 if (float_abi
== FLOAT_ABI_DEFAULT
)
2331 riscv_subset_t
*subset
;
2333 /* Assume soft-float unless D extension is present. */
2334 float_abi
= FLOAT_ABI_SOFT
;
2336 for (subset
= riscv_subsets
.head
; subset
!= NULL
; subset
= subset
->next
)
2338 if (strcasecmp (subset
->name
, "D") == 0)
2339 float_abi
= FLOAT_ABI_DOUBLE
;
2340 if (strcasecmp (subset
->name
, "Q") == 0)
2341 float_abi
= FLOAT_ABI_QUAD
;
2346 elf_flags
|= EF_RISCV_RVE
;
2348 /* Insert float_abi into the EF_RISCV_FLOAT_ABI field of elf_flags. */
2349 elf_flags
|= float_abi
* (EF_RISCV_FLOAT_ABI
& ~(EF_RISCV_FLOAT_ABI
<< 1));
2353 md_pcrel_from (fixS
*fixP
)
2355 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2358 /* Apply a fixup to the object file. */
2361 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
2363 unsigned int subtype
;
2364 bfd_byte
*buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
2365 bfd_boolean relaxable
= FALSE
;
2369 /* Remember value for tc_gen_reloc. */
2370 fixP
->fx_addnumber
= *valP
;
2372 switch (fixP
->fx_r_type
)
2374 case BFD_RELOC_RISCV_HI20
:
2375 case BFD_RELOC_RISCV_LO12_I
:
2376 case BFD_RELOC_RISCV_LO12_S
:
2377 bfd_putl32 (riscv_apply_const_reloc (fixP
->fx_r_type
, *valP
)
2378 | bfd_getl32 (buf
), buf
);
2379 if (fixP
->fx_addsy
== NULL
)
2380 fixP
->fx_done
= TRUE
;
2384 case BFD_RELOC_RISCV_GOT_HI20
:
2385 case BFD_RELOC_RISCV_ADD8
:
2386 case BFD_RELOC_RISCV_ADD16
:
2387 case BFD_RELOC_RISCV_ADD32
:
2388 case BFD_RELOC_RISCV_ADD64
:
2389 case BFD_RELOC_RISCV_SUB6
:
2390 case BFD_RELOC_RISCV_SUB8
:
2391 case BFD_RELOC_RISCV_SUB16
:
2392 case BFD_RELOC_RISCV_SUB32
:
2393 case BFD_RELOC_RISCV_SUB64
:
2394 case BFD_RELOC_RISCV_RELAX
:
2397 case BFD_RELOC_RISCV_TPREL_HI20
:
2398 case BFD_RELOC_RISCV_TPREL_LO12_I
:
2399 case BFD_RELOC_RISCV_TPREL_LO12_S
:
2400 case BFD_RELOC_RISCV_TPREL_ADD
:
2404 case BFD_RELOC_RISCV_TLS_GOT_HI20
:
2405 case BFD_RELOC_RISCV_TLS_GD_HI20
:
2406 case BFD_RELOC_RISCV_TLS_DTPREL32
:
2407 case BFD_RELOC_RISCV_TLS_DTPREL64
:
2408 if (fixP
->fx_addsy
!= NULL
)
2409 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
2411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2412 _("TLS relocation against a constant"));
2416 /* Use pc-relative relocation for FDE initial location.
2417 The symbol address in .eh_frame may be adjusted in
2418 _bfd_elf_discard_section_eh_frame, and the content of
2419 .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame.
2420 Therefore, we cannot insert a relocation whose addend symbol is
2421 in .eh_frame. Othrewise, the value may be adjusted twice.*/
2422 if (fixP
->fx_addsy
&& fixP
->fx_subsy
2423 && (sub_segment
= S_GET_SEGMENT (fixP
->fx_subsy
))
2424 && strcmp (sub_segment
->name
, ".eh_frame") == 0
2425 && S_GET_VALUE (fixP
->fx_subsy
)
2426 == fixP
->fx_frag
->fr_address
+ fixP
->fx_where
)
2428 fixP
->fx_r_type
= BFD_RELOC_RISCV_32_PCREL
;
2429 fixP
->fx_subsy
= NULL
;
2436 case BFD_RELOC_RISCV_CFA
:
2437 if (fixP
->fx_addsy
&& fixP
->fx_subsy
)
2439 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2440 fixP
->fx_next
->fx_addsy
= fixP
->fx_subsy
;
2441 fixP
->fx_next
->fx_subsy
= NULL
;
2442 fixP
->fx_next
->fx_offset
= 0;
2443 fixP
->fx_subsy
= NULL
;
2445 switch (fixP
->fx_r_type
)
2448 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD64
;
2449 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB64
;
2453 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD32
;
2454 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2458 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD16
;
2459 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2463 fixP
->fx_r_type
= BFD_RELOC_RISCV_ADD8
;
2464 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2467 case BFD_RELOC_RISCV_CFA
:
2468 /* Load the byte to get the subtype. */
2469 subtype
= bfd_get_8 (NULL
, &((fragS
*) (fixP
->fx_frag
->fr_opcode
))->fr_literal
[fixP
->fx_where
]);
2470 loc
= fixP
->fx_frag
->fr_fix
- (subtype
& 7);
2473 case DW_CFA_advance_loc1
:
2474 fixP
->fx_where
= loc
+ 1;
2475 fixP
->fx_next
->fx_where
= loc
+ 1;
2476 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET8
;
2477 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB8
;
2480 case DW_CFA_advance_loc2
:
2482 fixP
->fx_next
->fx_size
= 2;
2483 fixP
->fx_where
= loc
+ 1;
2484 fixP
->fx_next
->fx_where
= loc
+ 1;
2485 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET16
;
2486 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB16
;
2489 case DW_CFA_advance_loc4
:
2491 fixP
->fx_next
->fx_size
= 4;
2492 fixP
->fx_where
= loc
;
2493 fixP
->fx_next
->fx_where
= loc
;
2494 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET32
;
2495 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB32
;
2499 if (subtype
< 0x80 && (subtype
& 0x40))
2501 /* DW_CFA_advance_loc */
2502 fixP
->fx_frag
= (fragS
*) fixP
->fx_frag
->fr_opcode
;
2503 fixP
->fx_next
->fx_frag
= fixP
->fx_frag
;
2504 fixP
->fx_r_type
= BFD_RELOC_RISCV_SET6
;
2505 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_SUB6
;
2508 as_fatal (_("internal error: bad CFA value #%d"), subtype
);
2514 /* This case is unreachable. */
2521 /* If we are deleting this reloc entry, we must fill in the
2522 value now. This can happen if we have a .word which is not
2523 resolved when it appears but is later defined. */
2524 if (fixP
->fx_addsy
== NULL
)
2526 gas_assert (fixP
->fx_size
<= sizeof (valueT
));
2527 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
2532 case BFD_RELOC_RISCV_JMP
:
2535 /* Fill in a tentative value to improve objdump readability. */
2536 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2537 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2538 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_UJTYPE_IMM (delta
), buf
);
2542 case BFD_RELOC_12_PCREL
:
2545 /* Fill in a tentative value to improve objdump readability. */
2546 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2547 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2548 bfd_putl32 (bfd_getl32 (buf
) | ENCODE_SBTYPE_IMM (delta
), buf
);
2552 case BFD_RELOC_RISCV_RVC_BRANCH
:
2555 /* Fill in a tentative value to improve objdump readability. */
2556 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2557 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2558 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_B_IMM (delta
), buf
);
2562 case BFD_RELOC_RISCV_RVC_JUMP
:
2565 /* Fill in a tentative value to improve objdump readability. */
2566 bfd_vma target
= S_GET_VALUE (fixP
->fx_addsy
) + *valP
;
2567 bfd_vma delta
= target
- md_pcrel_from (fixP
);
2568 bfd_putl16 (bfd_getl16 (buf
) | ENCODE_RVC_J_IMM (delta
), buf
);
2572 case BFD_RELOC_RISCV_CALL
:
2573 case BFD_RELOC_RISCV_CALL_PLT
:
2577 case BFD_RELOC_RISCV_PCREL_HI20
:
2578 case BFD_RELOC_RISCV_PCREL_LO12_S
:
2579 case BFD_RELOC_RISCV_PCREL_LO12_I
:
2580 relaxable
= riscv_opts
.relax
;
2583 case BFD_RELOC_RISCV_ALIGN
:
2587 /* We ignore generic BFD relocations we don't know about. */
2588 if (bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
) != NULL
)
2589 as_fatal (_("internal error: bad relocation #%d"), fixP
->fx_r_type
);
2592 if (fixP
->fx_subsy
!= NULL
)
2593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2594 _("unsupported symbol subtraction"));
2596 /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
2597 if (relaxable
&& fixP
->fx_tcbit
&& fixP
->fx_addsy
!= NULL
)
2599 fixP
->fx_next
= xmemdup (fixP
, sizeof (*fixP
), sizeof (*fixP
));
2600 fixP
->fx_next
->fx_addsy
= fixP
->fx_next
->fx_subsy
= NULL
;
2601 fixP
->fx_next
->fx_r_type
= BFD_RELOC_RISCV_RELAX
;
2605 /* Because the value of .cfi_remember_state may changed after relaxation,
2606 we insert a fix to relocate it again in link-time. */
2609 riscv_pre_output_hook (void)
2611 const frchainS
*frch
;
2614 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
2615 for (frch
= seg_info (s
)->frchainP
; frch
; frch
= frch
->frch_next
)
2619 for (frag
= frch
->frch_root
; frag
; frag
= frag
->fr_next
)
2621 if (frag
->fr_type
== rs_cfa
)
2624 expressionS
*symval
;
2626 symval
= symbol_get_value_expression (frag
->fr_symbol
);
2627 exp
.X_op
= O_subtract
;
2628 exp
.X_add_symbol
= symval
->X_add_symbol
;
2629 exp
.X_add_number
= 0;
2630 exp
.X_op_symbol
= symval
->X_op_symbol
;
2632 fix_new_exp (frag
, (int) frag
->fr_offset
, 1, &exp
, 0,
2633 BFD_RELOC_RISCV_CFA
);
2640 /* This structure is used to hold a stack of .option values. */
2642 struct riscv_option_stack
2644 struct riscv_option_stack
*next
;
2645 struct riscv_set_options options
;
2648 static struct riscv_option_stack
*riscv_opts_stack
;
2650 /* Handle the .option pseudo-op. */
2653 s_riscv_option (int x ATTRIBUTE_UNUSED
)
2655 char *name
= input_line_pointer
, ch
;
2657 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2658 ++input_line_pointer
;
2659 ch
= *input_line_pointer
;
2660 *input_line_pointer
= '\0';
2662 if (strcmp (name
, "rvc") == 0)
2663 riscv_set_rvc (TRUE
);
2664 else if (strcmp (name
, "norvc") == 0)
2665 riscv_set_rvc (FALSE
);
2666 else if (strcmp (name
, "pic") == 0)
2667 riscv_opts
.pic
= TRUE
;
2668 else if (strcmp (name
, "nopic") == 0)
2669 riscv_opts
.pic
= FALSE
;
2670 else if (strcmp (name
, "relax") == 0)
2671 riscv_opts
.relax
= TRUE
;
2672 else if (strcmp (name
, "norelax") == 0)
2673 riscv_opts
.relax
= FALSE
;
2674 else if (strcmp (name
, "push") == 0)
2676 struct riscv_option_stack
*s
;
2678 s
= (struct riscv_option_stack
*) xmalloc (sizeof *s
);
2679 s
->next
= riscv_opts_stack
;
2680 s
->options
= riscv_opts
;
2681 riscv_opts_stack
= s
;
2683 else if (strcmp (name
, "pop") == 0)
2685 struct riscv_option_stack
*s
;
2687 s
= riscv_opts_stack
;
2689 as_bad (_(".option pop with no .option push"));
2692 riscv_opts
= s
->options
;
2693 riscv_opts_stack
= s
->next
;
2699 as_warn (_("Unrecognized .option directive: %s\n"), name
);
2701 *input_line_pointer
= ch
;
2702 demand_empty_rest_of_line ();
2705 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
2706 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
2707 use in DWARF debug information. */
2710 s_dtprel (int bytes
)
2717 if (ex
.X_op
!= O_symbol
)
2719 as_bad (_("Unsupported use of %s"), (bytes
== 8
2722 ignore_rest_of_line ();
2725 p
= frag_more (bytes
);
2726 md_number_to_chars (p
, 0, bytes
);
2727 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
2729 ? BFD_RELOC_RISCV_TLS_DTPREL64
2730 : BFD_RELOC_RISCV_TLS_DTPREL32
));
2732 demand_empty_rest_of_line ();
2735 /* Handle the .bss pseudo-op. */
2738 s_bss (int ignore ATTRIBUTE_UNUSED
)
2740 subseg_set (bss_section
, 0);
2741 demand_empty_rest_of_line ();
2745 riscv_make_nops (char *buf
, bfd_vma bytes
)
2749 /* RISC-V instructions cannot begin or end on odd addresses, so this case
2750 means we are not within a valid instruction sequence. It is thus safe
2751 to use a zero byte, even though that is not a valid instruction. */
2755 /* Use at most one 2-byte NOP. */
2756 if ((bytes
- i
) % 4 == 2)
2758 md_number_to_chars (buf
+ i
, RVC_NOP
, 2);
2762 /* Fill the remainder with 4-byte NOPs. */
2763 for ( ; i
< bytes
; i
+= 4)
2764 md_number_to_chars (buf
+ i
, RISCV_NOP
, 4);
2767 /* Called from md_do_align. Used to create an alignment frag in a
2768 code section by emitting a worst-case NOP sequence that the linker
2769 will later relax to the correct number of NOPs. We can't compute
2770 the correct alignment now because of other linker relaxations. */
2773 riscv_frag_align_code (int n
)
2775 bfd_vma bytes
= (bfd_vma
) 1 << n
;
2776 bfd_vma insn_alignment
= riscv_opts
.rvc
? 2 : 4;
2777 bfd_vma worst_case_bytes
= bytes
- insn_alignment
;
2781 /* If we are moving to a smaller alignment than the instruction size, then no
2782 alignment is required. */
2783 if (bytes
<= insn_alignment
)
2786 /* When not relaxing, riscv_handle_align handles code alignment. */
2787 if (!riscv_opts
.relax
)
2790 nops
= frag_more (worst_case_bytes
);
2792 ex
.X_op
= O_constant
;
2793 ex
.X_add_number
= worst_case_bytes
;
2795 riscv_make_nops (nops
, worst_case_bytes
);
2797 fix_new_exp (frag_now
, nops
- frag_now
->fr_literal
, 0,
2798 &ex
, FALSE
, BFD_RELOC_RISCV_ALIGN
);
2803 /* Implement HANDLE_ALIGN. */
2806 riscv_handle_align (fragS
*fragP
)
2808 switch (fragP
->fr_type
)
2811 /* When relaxing, riscv_frag_align_code handles code alignment. */
2812 if (!riscv_opts
.relax
)
2814 bfd_signed_vma bytes
= (fragP
->fr_next
->fr_address
2815 - fragP
->fr_address
- fragP
->fr_fix
);
2816 /* We have 4 byte uncompressed nops. */
2817 bfd_signed_vma size
= 4;
2818 bfd_signed_vma excess
= bytes
% size
;
2819 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
2824 /* Insert zeros or compressed nops to get 4 byte alignment. */
2827 riscv_make_nops (p
, excess
);
2828 fragP
->fr_fix
+= excess
;
2832 /* Insert variable number of 4 byte uncompressed nops. */
2833 riscv_make_nops (p
, size
);
2834 fragP
->fr_var
= size
;
2844 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
2846 return (fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
));
2849 /* Translate internal representation of relocation info to BFD target
2853 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
2855 arelent
*reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2857 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2858 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2859 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2860 reloc
->addend
= fixp
->fx_addnumber
;
2862 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
2863 if (reloc
->howto
== NULL
)
2865 if ((fixp
->fx_r_type
== BFD_RELOC_16
|| fixp
->fx_r_type
== BFD_RELOC_8
)
2866 && fixp
->fx_addsy
!= NULL
&& fixp
->fx_subsy
!= NULL
)
2868 /* We don't have R_RISCV_8/16, but for this special case,
2869 we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */
2873 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2874 _("cannot represent %s relocation in object file"),
2875 bfd_get_reloc_code_name (fixp
->fx_r_type
));
2883 riscv_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
2885 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
2887 offsetT old_var
= fragp
->fr_var
;
2888 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
2889 return fragp
->fr_var
- old_var
;
2895 /* Expand far branches to multi-instruction sequences. */
2898 md_convert_frag_branch (fragS
*fragp
)
2906 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
2908 exp
.X_op
= O_symbol
;
2909 exp
.X_add_symbol
= fragp
->fr_symbol
;
2910 exp
.X_add_number
= fragp
->fr_offset
;
2912 gas_assert (fragp
->fr_var
== RELAX_BRANCH_LENGTH (fragp
->fr_subtype
));
2914 if (RELAX_BRANCH_RVC (fragp
->fr_subtype
))
2916 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2920 /* Expand the RVC branch into a RISC-V one. */
2921 insn
= bfd_getl16 (buf
);
2922 rs1
= 8 + ((insn
>> OP_SH_CRS1S
) & OP_MASK_CRS1S
);
2923 if ((insn
& MASK_C_J
) == MATCH_C_J
)
2925 else if ((insn
& MASK_C_JAL
) == MATCH_C_JAL
)
2926 insn
= MATCH_JAL
| (X_RA
<< OP_SH_RD
);
2927 else if ((insn
& MASK_C_BEQZ
) == MATCH_C_BEQZ
)
2928 insn
= MATCH_BEQ
| (rs1
<< OP_SH_RS1
);
2929 else if ((insn
& MASK_C_BNEZ
) == MATCH_C_BNEZ
)
2930 insn
= MATCH_BNE
| (rs1
<< OP_SH_RS1
);
2933 bfd_putl32 (insn
, buf
);
2937 /* Invert the branch condition. Branch over the jump. */
2938 insn
= bfd_getl16 (buf
);
2939 insn
^= MATCH_C_BEQZ
^ MATCH_C_BNEZ
;
2940 insn
|= ENCODE_RVC_B_IMM (6);
2941 bfd_putl16 (insn
, buf
);
2946 /* Just keep the RVC branch. */
2947 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2948 ? BFD_RELOC_RISCV_RVC_JUMP
: BFD_RELOC_RISCV_RVC_BRANCH
;
2949 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2950 2, &exp
, FALSE
, reloc
);
2959 switch (RELAX_BRANCH_LENGTH (fragp
->fr_subtype
))
2962 gas_assert (!RELAX_BRANCH_UNCOND (fragp
->fr_subtype
));
2964 /* Invert the branch condition. Branch over the jump. */
2965 insn
= bfd_getl32 (buf
);
2966 insn
^= MATCH_BEQ
^ MATCH_BNE
;
2967 insn
|= ENCODE_SBTYPE_IMM (8);
2968 md_number_to_chars ((char *) buf
, insn
, 4);
2972 /* Jump to the target. */
2973 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2974 4, &exp
, FALSE
, BFD_RELOC_RISCV_JMP
);
2975 md_number_to_chars ((char *) buf
, MATCH_JAL
, 4);
2980 reloc
= RELAX_BRANCH_UNCOND (fragp
->fr_subtype
)
2981 ? BFD_RELOC_RISCV_JMP
: BFD_RELOC_12_PCREL
;
2982 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
2983 4, &exp
, FALSE
, reloc
);
2992 fixp
->fx_file
= fragp
->fr_file
;
2993 fixp
->fx_line
= fragp
->fr_line
;
2995 gas_assert (buf
== (bfd_byte
*)fragp
->fr_literal
2996 + fragp
->fr_fix
+ fragp
->fr_var
);
2998 fragp
->fr_fix
+= fragp
->fr_var
;
3001 /* Relax a machine dependent frag. This returns the amount by which
3002 the current size of the frag should change. */
3005 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec ATTRIBUTE_UNUSED
,
3008 gas_assert (RELAX_BRANCH_P (fragp
->fr_subtype
));
3009 md_convert_frag_branch (fragp
);
3013 md_show_usage (FILE *stream
)
3015 fprintf (stream
, _("\
3017 -fpic generate position-independent code\n\
3018 -fno-pic don't generate position-independent code (default)\n\
3019 -march=ISA set the RISC-V architecture\n\
3020 -mabi=ABI set the RISC-V ABI\n\
3021 -mrelax enable relax (default)\n\
3022 -mno-relax disable relax\n\
3023 -march-attr generate RISC-V arch attribute\n\
3024 -mno-arch-attr don't generate RISC-V arch attribute\n\
3028 /* Standard calling conventions leave the CFA at SP on entry. */
3030 riscv_cfi_frame_initial_instructions (void)
3032 cfi_add_CFA_def_cfa_register (X_SP
);
3036 tc_riscv_regname_to_dw2regnum (char *regname
)
3040 if ((reg
= reg_lookup_internal (regname
, RCLASS_GPR
)) >= 0)
3043 if ((reg
= reg_lookup_internal (regname
, RCLASS_FPR
)) >= 0)
3046 as_bad (_("unknown register `%s'"), regname
);
3051 riscv_elf_final_processing (void)
3053 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
3056 /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions,
3057 since these directives break relaxation when used with symbol deltas. */
3060 s_riscv_leb128 (int sign
)
3063 char *save_in
= input_line_pointer
;
3066 if (exp
.X_op
!= O_constant
)
3067 as_bad (_("non-constant .%cleb128 is not supported"), sign
? 's' : 'u');
3068 demand_empty_rest_of_line ();
3070 input_line_pointer
= save_in
;
3071 return s_leb128 (sign
);
3074 /* Parse the .insn directive. */
3077 s_riscv_insn (int x ATTRIBUTE_UNUSED
)
3079 char *str
= input_line_pointer
;
3080 struct riscv_cl_insn insn
;
3081 expressionS imm_expr
;
3082 bfd_reloc_code_real_type imm_reloc
= BFD_RELOC_UNUSED
;
3085 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3086 ++input_line_pointer
;
3088 save_c
= *input_line_pointer
;
3089 *input_line_pointer
= '\0';
3091 const char *error
= riscv_ip (str
, &insn
, &imm_expr
,
3092 &imm_reloc
, insn_type_hash
);
3096 as_bad ("%s `%s'", error
, str
);
3100 gas_assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
3101 append_insn (&insn
, &imm_expr
, imm_reloc
);
3104 *input_line_pointer
= save_c
;
3105 demand_empty_rest_of_line ();
3108 /* Update arch attributes. */
3111 riscv_write_out_arch_attr (void)
3113 const char *arch_str
= riscv_arch_str (xlen
, &riscv_subsets
);
3115 bfd_elf_add_proc_attr_string (stdoutput
, Tag_RISCV_arch
, arch_str
);
3117 xfree ((void *)arch_str
);
3120 /* Add the default contents for the .riscv.attributes section. */
3123 riscv_set_public_attributes (void)
3125 if (riscv_opts
.arch_attr
|| explicit_arch_attr
)
3126 /* Re-write arch attribute to normalize the arch string. */
3127 riscv_write_out_arch_attr ();
3130 /* Called after all assembly has been done. */
3135 riscv_set_public_attributes ();
3138 /* Given a symbolic attribute NAME, return the proper integer value.
3139 Returns -1 if the attribute is not known. */
3142 riscv_convert_symbolic_attribute (const char *name
)
3151 /* When you modify this table you should
3152 also modify the list in doc/c-riscv.texi. */
3153 #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag}
3157 T(priv_spec_revision
),
3158 T(unaligned_access
),
3168 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
3169 if (strcmp (name
, attribute_table
[i
].name
) == 0)
3170 return attribute_table
[i
].tag
;
3175 /* Parse a .attribute directive. */
3178 s_riscv_attribute (int ignored ATTRIBUTE_UNUSED
)
3180 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
3182 if (tag
== Tag_RISCV_arch
)
3184 unsigned old_xlen
= xlen
;
3186 explicit_arch_attr
= TRUE
;
3187 obj_attribute
*attr
;
3188 attr
= elf_known_obj_attributes_proc (stdoutput
);
3189 if (!start_assemble
)
3190 riscv_set_arch (attr
[Tag_RISCV_arch
].s
);
3192 as_fatal (_(".attribute arch must set before any instructions"));
3194 if (old_xlen
!= xlen
)
3196 /* We must re-init bfd again if xlen is changed. */
3197 unsigned long mach
= xlen
== 64 ? bfd_mach_riscv64
: bfd_mach_riscv32
;
3198 bfd_find_target (riscv_target_format (), stdoutput
);
3200 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_riscv
, mach
))
3201 as_warn (_("Could not set architecture and machine"));
3206 /* Pseudo-op table. */
3208 static const pseudo_typeS riscv_pseudo_table
[] =
3210 /* RISC-V-specific pseudo-ops. */
3211 {"option", s_riscv_option
, 0},
3215 {"dtprelword", s_dtprel
, 4},
3216 {"dtpreldword", s_dtprel
, 8},
3218 {"uleb128", s_riscv_leb128
, 0},
3219 {"sleb128", s_riscv_leb128
, 1},
3220 {"insn", s_riscv_insn
, 0},
3221 {"attribute", s_riscv_attribute
, 0},
3227 riscv_pop_insert (void)
3229 extern void pop_insert (const pseudo_typeS
*);
3231 pop_insert (riscv_pseudo_table
);