1 /* tc-sh.c -- Assemble code for the Hitachi Super-H
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 Written By Steve Chamberlain
31 #include "opcodes/sh-opc.h"
38 const char comment_chars
[] = "!";
39 const char line_separator_chars
[] = ";";
40 const char line_comment_chars
[] = "!#";
42 static void s_uses
PARAMS ((int));
44 static void sh_count_relocs
PARAMS ((bfd
*, segT
, PTR
));
45 static void sh_frob_section
PARAMS ((bfd
*, segT
, PTR
));
48 void s_align_bytes ();
49 static void s_uacons
PARAMS ((int));
50 static sh_opcode_info
*find_cooked_opcode
PARAMS ((char **));
51 static void assemble_ppi
PARAMS ((char *, sh_opcode_info
*));
60 target_big_endian
= 0;
63 /* This table describes all the machine specific pseudo-ops the assembler
64 has to support. The fields are:
65 pseudo-op name without dot
66 function to call to execute this pseudo-op
67 Integer arg to pass to the function
70 const pseudo_typeS md_pseudo_table
[] =
74 {"form", listing_psize
, 0},
75 {"little", little
, 0},
76 {"heading", listing_title
, 0},
77 {"import", s_ignore
, 0},
78 {"page", listing_eject
, 0},
79 {"program", s_ignore
, 0},
81 {"uaword", s_uacons
, 2},
82 {"ualong", s_uacons
, 4},
86 /*int md_reloc_size; */
88 int sh_relax
; /* set if -relax seen */
90 /* Whether -small was seen. */
94 /* Whether -dsp was seen. */
98 /* The bit mask of architectures that could
99 accomodate the insns seen so far. */
100 static int valid_arch
;
102 const char EXP_CHARS
[] = "eE";
104 /* Chars that mean this number is a floating point constant */
107 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
109 #define C(a,b) ENCODE_RELAX(a,b)
111 #define JREG 14 /* Register used as a temp when relaxing */
112 #define ENCODE_RELAX(what,length) (((what) << 4) + (length))
113 #define GET_WHAT(x) ((x>>4))
115 /* These are the three types of relaxable instrction */
117 #define COND_JUMP_DELAY 2
118 #define UNCOND_JUMP 3
127 #define UNDEF_WORD_DISP 4
132 /* Branch displacements are from the address of the branch plus
133 four, thus all minimum and maximum values have 4 added to them. */
136 #define COND8_LENGTH 2
138 /* There is one extra instruction before the branch, so we must add
139 two more bytes to account for it. */
140 #define COND12_F 4100
141 #define COND12_M -4090
142 #define COND12_LENGTH 6
144 #define COND12_DELAY_LENGTH 4
146 /* ??? The minimum and maximum values are wrong, but this does not matter
147 since this relocation type is not supported yet. */
148 #define COND32_F (1<<30)
149 #define COND32_M -(1<<30)
150 #define COND32_LENGTH 14
152 #define UNCOND12_F 4098
153 #define UNCOND12_M -4092
154 #define UNCOND12_LENGTH 2
156 /* ??? The minimum and maximum values are wrong, but this does not matter
157 since this relocation type is not supported yet. */
158 #define UNCOND32_F (1<<30)
159 #define UNCOND32_M -(1<<30)
160 #define UNCOND32_LENGTH 14
162 const relax_typeS md_relax_table
[C (END
, 0)] = {
163 { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 },
164 { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 },
167 /* C (COND_JUMP, COND8) */
168 { COND8_F
, COND8_M
, COND8_LENGTH
, C (COND_JUMP
, COND12
) },
169 /* C (COND_JUMP, COND12) */
170 { COND12_F
, COND12_M
, COND12_LENGTH
, C (COND_JUMP
, COND32
), },
171 /* C (COND_JUMP, COND32) */
172 { COND32_F
, COND32_M
, COND32_LENGTH
, 0, },
173 { 0 }, { 0 }, { 0 }, { 0 },
174 { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 },
177 /* C (COND_JUMP_DELAY, COND8) */
178 { COND8_F
, COND8_M
, COND8_LENGTH
, C (COND_JUMP_DELAY
, COND12
) },
179 /* C (COND_JUMP_DELAY, COND12) */
180 { COND12_F
, COND12_M
, COND12_DELAY_LENGTH
, C (COND_JUMP_DELAY
, COND32
), },
181 /* C (COND_JUMP_DELAY, COND32) */
182 { COND32_F
, COND32_M
, COND32_LENGTH
, 0, },
183 { 0 }, { 0 }, { 0 }, { 0 },
184 { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 },
187 /* C (UNCOND_JUMP, UNCOND12) */
188 { UNCOND12_F
, UNCOND12_M
, UNCOND12_LENGTH
, C (UNCOND_JUMP
, UNCOND32
), },
189 /* C (UNCOND_JUMP, UNCOND32) */
190 { UNCOND32_F
, UNCOND32_M
, UNCOND32_LENGTH
, 0, },
191 { 0 }, { 0 }, { 0 }, { 0 }, { 0 },
192 { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 },
195 static struct hash_control
*opcode_hash_control
; /* Opcode mnemonics */
198 This function is called once, at assembler startup time. This should
199 set up all the tables, etc that the MD part of the assembler needs
205 sh_opcode_info
*opcode
;
206 char *prev_name
= "";
210 target_big_endian
= 1;
212 target_arch
= arch_sh1_up
& ~(sh_dsp
? arch_sh3e_up
: arch_sh_dsp_up
);
213 valid_arch
= target_arch
;
215 opcode_hash_control
= hash_new ();
217 /* Insert unique names into hash table */
218 for (opcode
= sh_table
; opcode
->name
; opcode
++)
220 if (opcode
->arch
& target_arch
&& strcmp (prev_name
, opcode
->name
))
222 prev_name
= opcode
->name
;
223 hash_insert (opcode_hash_control
, opcode
->name
, (char *) opcode
);
227 /* Make all the opcodes with the same name point to the same
229 opcode
->name
= prev_name
;
236 static int reg_x
, reg_y
;
240 static expressionS immediate
; /* absolute expression */
250 /* try and parse a reg name, returns number of chars consumed */
252 parse_reg (src
, mode
, reg
)
257 /* We use !isalnum for the next character after the register name, to
258 make sure that we won't accidentally recognize a symbol name such as
259 'sram' as being a reference to the register 'sr'. */
265 if (src
[2] >= '0' && src
[2] <= '5'
266 && ! isalnum ((unsigned char) src
[3]))
269 *reg
= 10 + src
[2] - '0';
273 if (src
[1] >= '0' && src
[1] <= '9'
274 && ! isalnum ((unsigned char) src
[2]))
277 *reg
= (src
[1] - '0');
280 if (src
[1] >= '0' && src
[1] <= '7' && strncmp(&src
[2], "_bank", 5) == 0
281 && ! isalnum ((unsigned char) src
[7]))
284 *reg
= (src
[1] - '0');
288 if (src
[1] == 'e' && ! isalnum ((unsigned char) src
[2]))
293 if (src
[1] == 's' && ! isalnum ((unsigned char) src
[2]))
304 if (! isalnum ((unsigned char) src
[2]))
310 if (src
[2] == 'g' && ! isalnum ((unsigned char) src
[3]))
319 if (! isalnum ((unsigned char) src
[2]))
325 if (src
[2] == 'g' && ! isalnum ((unsigned char) src
[3]))
333 if (src
[1] == 'x' && src
[2] >= '0' && src
[2] <= '1'
334 && ! isalnum ((unsigned char) src
[3]))
337 *reg
= 4 + (src
[1] - '0');
340 if (src
[1] == 'y' && src
[2] >= '0' && src
[2] <= '1'
341 && ! isalnum ((unsigned char) src
[3]))
344 *reg
= 6 + (src
[1] - '0');
347 if (src
[1] == 's' && src
[2] >= '0' && src
[2] <= '3'
348 && ! isalnum ((unsigned char) src
[3]))
350 int n
= src
[1] - '0';
353 *reg
= n
| ((~n
& 2) << 1);
358 if (src
[0] == 'i' && src
[1] && ! isalnum ((unsigned char) src
[3]))
380 if (src
[0] == 'x' && src
[1] >= '0' && src
[1] <= '1'
381 && ! isalnum ((unsigned char) src
[2]))
384 *reg
= A_X0_NUM
+ src
[1] - '0';
388 if (src
[0] == 'y' && src
[1] >= '0' && src
[1] <= '1'
389 && ! isalnum ((unsigned char) src
[2]))
392 *reg
= A_Y0_NUM
+ src
[1] - '0';
396 if (src
[0] == 'm' && src
[1] >= '0' && src
[1] <= '1'
397 && ! isalnum ((unsigned char) src
[2]))
400 *reg
= src
[1] == '0' ? A_M0_NUM
: A_M1_NUM
;
406 && src
[2] == 'r' && ! isalnum ((unsigned char) src
[3]))
412 if (src
[0] == 's' && src
[1] == 'p' && src
[2] == 'c'
413 && ! isalnum ((unsigned char) src
[3]))
419 if (src
[0] == 's' && src
[1] == 'g' && src
[2] == 'r'
420 && ! isalnum ((unsigned char) src
[3]))
426 if (src
[0] == 'd' && src
[1] == 's' && src
[2] == 'r'
427 && ! isalnum ((unsigned char) src
[3]))
433 if (src
[0] == 'd' && src
[1] == 'b' && src
[2] == 'r'
434 && ! isalnum ((unsigned char) src
[3]))
440 if (src
[0] == 's' && src
[1] == 'r' && ! isalnum ((unsigned char) src
[2]))
446 if (src
[0] == 's' && src
[1] == 'p' && ! isalnum ((unsigned char) src
[2]))
453 if (src
[0] == 'p' && src
[1] == 'r' && ! isalnum ((unsigned char) src
[2]))
458 if (src
[0] == 'p' && src
[1] == 'c' && ! isalnum ((unsigned char) src
[2]))
463 if (src
[0] == 'g' && src
[1] == 'b' && src
[2] == 'r'
464 && ! isalnum ((unsigned char) src
[3]))
469 if (src
[0] == 'v' && src
[1] == 'b' && src
[2] == 'r'
470 && ! isalnum ((unsigned char) src
[3]))
476 if (src
[0] == 'm' && src
[1] == 'a' && src
[2] == 'c'
477 && ! isalnum ((unsigned char) src
[4]))
490 if (src
[0] == 'm' && src
[1] == 'o' && src
[2] == 'd'
491 && ! isalnum ((unsigned char) src
[4]))
496 if (src
[0] == 'f' && src
[1] == 'r')
500 if (src
[3] >= '0' && src
[3] <= '5'
501 && ! isalnum ((unsigned char) src
[4]))
504 *reg
= 10 + src
[3] - '0';
508 if (src
[2] >= '0' && src
[2] <= '9'
509 && ! isalnum ((unsigned char) src
[3]))
512 *reg
= (src
[2] - '0');
516 if (src
[0] == 'd' && src
[1] == 'r')
520 if (src
[3] >= '0' && src
[3] <= '4' && ! ((src
[3] - '0') & 1)
521 && ! isalnum ((unsigned char) src
[4]))
524 *reg
= 10 + src
[3] - '0';
528 if (src
[2] >= '0' && src
[2] <= '8' && ! ((src
[2] - '0') & 1)
529 && ! isalnum ((unsigned char) src
[3]))
532 *reg
= (src
[2] - '0');
536 if (src
[0] == 'x' && src
[1] == 'd')
540 if (src
[3] >= '0' && src
[3] <= '4' && ! ((src
[3] - '0') & 1)
541 && ! isalnum ((unsigned char) src
[4]))
544 *reg
= 11 + src
[3] - '0';
548 if (src
[2] >= '0' && src
[2] <= '8' && ! ((src
[2] - '0') & 1)
549 && ! isalnum ((unsigned char) src
[3]))
552 *reg
= (src
[2] - '0') + 1;
556 if (src
[0] == 'f' && src
[1] == 'v')
558 if (src
[2] == '1'&& src
[3] == '2' && ! isalnum ((unsigned char) src
[4]))
564 if ((src
[2] == '0' || src
[2] == '4' || src
[2] == '8')
565 && ! isalnum ((unsigned char) src
[3]))
568 *reg
= (src
[2] - '0');
572 if (src
[0] == 'f' && src
[1] == 'p' && src
[2] == 'u' && src
[3] == 'l'
573 && ! isalnum ((unsigned char) src
[4]))
579 if (src
[0] == 'f' && src
[1] == 'p' && src
[2] == 's' && src
[3] == 'c'
580 && src
[4] == 'r' && ! isalnum ((unsigned char) src
[5]))
586 if (src
[0] == 'x' && src
[1] == 'm' && src
[2] == 't' && src
[3] == 'r'
587 && src
[4] == 'x' && ! isalnum ((unsigned char) src
[5]))
596 static symbolS
*dot()
600 /* JF: '.' is pseudo symbol with value of current location
601 in current segment. */
602 fake
= FAKE_LABEL_NAME
;
603 return symbol_new (fake
,
605 (valueT
) frag_now_fix (),
619 save
= input_line_pointer
;
620 input_line_pointer
= s
;
621 expression (&immediate
);
622 if (immediate
.X_op
== O_absent
)
623 as_bad (_("missing operand"));
624 new = input_line_pointer
;
625 input_line_pointer
= save
;
630 /* The many forms of operand:
633 @Rn Register indirect
646 pr, gbr, vbr, macl, mach
661 /* Must be predecrement */
664 len
= parse_reg (src
, &mode
, &(op
->reg
));
666 as_bad (_("illegal register after @-"));
671 else if (src
[0] == '(')
673 /* Could be @(disp, rn), @(disp, gbr), @(disp, pc), @(r0, gbr) or
676 len
= parse_reg (src
, &mode
, &(op
->reg
));
677 if (len
&& mode
== A_REG_N
)
682 as_bad (_("must be @(r0,...)"));
686 /* Now can be rn or gbr */
687 len
= parse_reg (src
, &mode
, &(op
->reg
));
692 else if (mode
== A_REG_N
)
694 op
->type
= A_IND_R0_REG_N
;
698 as_bad (_("syntax error in @(r0,...)"));
703 /* Must be an @(disp,.. thing) */
704 src
= parse_exp (src
);
707 /* Now can be rn, gbr or pc */
708 len
= parse_reg (src
, &mode
, &op
->reg
);
713 op
->type
= A_DISP_REG_N
;
715 else if (mode
== A_GBR
)
717 op
->type
= A_DISP_GBR
;
719 else if (mode
== A_DISP_PC
)
721 /* Turn a plain @(4,pc) into @(.+4,pc) */
722 if (immediate
.X_op
== O_constant
) {
723 immediate
.X_add_symbol
= dot();
724 immediate
.X_op
= O_symbol
;
726 op
->type
= A_DISP_PC
;
730 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
735 as_bad (_("syntax error in @(disp,[Rn, gbr, pc])"));
740 as_bad (_("expecting )"));
746 src
+= parse_reg (src
, &mode
, &(op
->reg
));
749 as_bad (_("illegal register after @"));
754 if ((src
[0] == 'r' && src
[1] == '8')
755 || (src
[0] == 'i' && (src
[1] == 'x' || src
[1] == 's')))
760 if ((src
[0] == 'r' && src
[1] == '9')
761 || (src
[0] == 'i' && src
[1] == 'y'))
764 op
->type
= A_PMODY_N
;
778 get_operand (ptr
, op
)
789 *ptr
= parse_exp (src
);
794 else if (src
[0] == '@')
796 *ptr
= parse_at (src
, op
);
799 len
= parse_reg (src
, &mode
, &(op
->reg
));
808 /* Not a reg, the only thing left is a displacement */
809 *ptr
= parse_exp (src
);
810 op
->type
= A_DISP_PC
;
817 get_operands (info
, args
, operand
)
818 sh_opcode_info
*info
;
820 sh_operand_info
*operand
;
826 /* The pre-processor will eliminate whitespace in front of '@'
827 after the first argument; we may be called multiple times
828 from assemble_ppi, so don't insist on finding whitespace here. */
832 get_operand (&ptr
, operand
+ 0);
839 get_operand (&ptr
, operand
+ 1);
846 get_operand (&ptr
, operand
+ 2);
868 /* Passed a pointer to a list of opcodes which use different
869 addressing modes, return the opcode which matches the opcodes
875 get_specific (opcode
, operands
)
876 sh_opcode_info
*opcode
;
877 sh_operand_info
*operands
;
879 sh_opcode_info
*this_try
= opcode
;
880 char *name
= opcode
->name
;
885 if (this_try
->name
!= name
)
887 /* We've looked so far down the table that we've run out of
888 opcodes with the same name */
891 /* look at both operands needed by the opcodes and provided by
892 the user - since an arg test will often fail on the same arg
893 again and again, we'll try and test the last failing arg the
894 first on each opcode try */
896 for (n
= 0; this_try
->arg
[n
]; n
++)
898 sh_operand_info
*user
= operands
+ n
;
899 sh_arg_type arg
= this_try
->arg
[n
];
910 if (user
->type
!= arg
)
914 /* opcode needs r0 */
915 if (user
->type
!= A_REG_N
|| user
->reg
!= 0)
919 if (user
->type
!= A_R0_GBR
|| user
->reg
!= 0)
923 if (user
->type
!= F_REG_N
|| user
->reg
!= 0)
942 /* Opcode needs rn */
943 if (user
->type
!= arg
)
948 if (user
->type
!= D_REG_N
&& user
->type
!= X_REG_N
)
963 if (user
->type
!= arg
)
968 if (user
->type
!= arg
)
980 /* Opcode needs rn */
981 if (user
->type
!= arg
- A_REG_M
+ A_REG_N
)
987 if (user
->type
!= DSP_REG_N
)
1009 if (user
->type
!= DSP_REG_N
)
1031 if (user
->type
!= DSP_REG_N
)
1053 if (user
->type
!= DSP_REG_N
)
1075 if (user
->type
!= DSP_REG_N
)
1097 if (user
->type
!= DSP_REG_N
|| user
->reg
!= A_A0_NUM
)
1101 if (user
->type
!= DSP_REG_N
|| user
->reg
!= A_X0_NUM
)
1105 if (user
->type
!= DSP_REG_N
|| user
->reg
!= A_X1_NUM
)
1109 if (user
->type
!= DSP_REG_N
|| user
->reg
!= A_Y0_NUM
)
1113 if (user
->type
!= DSP_REG_N
|| user
->reg
!= A_Y1_NUM
)
1123 /* Opcode needs rn */
1124 if (user
->type
!= arg
- F_REG_M
+ F_REG_N
)
1129 if (user
->type
!= D_REG_N
&& user
->type
!= X_REG_N
)
1134 if (user
->type
!= XMTRX_M4
)
1140 printf (_("unhandled %d\n"), arg
);
1144 valid_arch
&= this_try
->arch
;
1153 check (operand
, low
, high
)
1154 expressionS
*operand
;
1158 if (operand
->X_op
!= O_constant
1159 || operand
->X_add_number
< low
1160 || operand
->X_add_number
> high
)
1162 as_bad (_("operand must be absolute in range %d..%d"), low
, high
);
1164 return operand
->X_add_number
;
1169 insert (where
, how
, pcrel
)
1174 fix_new_exp (frag_now
,
1175 where
- frag_now
->fr_literal
,
1183 build_relax (opcode
)
1184 sh_opcode_info
*opcode
;
1186 int high_byte
= target_big_endian
? 0 : 1;
1189 if (opcode
->arg
[0] == A_BDISP8
)
1191 int what
= (opcode
->nibbles
[1] & 4) ? COND_JUMP_DELAY
: COND_JUMP
;
1192 p
= frag_var (rs_machine_dependent
,
1193 md_relax_table
[C (what
, COND32
)].rlx_length
,
1194 md_relax_table
[C (what
, COND8
)].rlx_length
,
1196 immediate
.X_add_symbol
,
1197 immediate
.X_add_number
,
1199 p
[high_byte
] = (opcode
->nibbles
[0] << 4) | (opcode
->nibbles
[1]);
1201 else if (opcode
->arg
[0] == A_BDISP12
)
1203 p
= frag_var (rs_machine_dependent
,
1204 md_relax_table
[C (UNCOND_JUMP
, UNCOND32
)].rlx_length
,
1205 md_relax_table
[C (UNCOND_JUMP
, UNCOND12
)].rlx_length
,
1207 immediate
.X_add_symbol
,
1208 immediate
.X_add_number
,
1210 p
[high_byte
] = (opcode
->nibbles
[0] << 4);
1215 /* Now we know what sort of opcodes it is, lets build the bytes -
1218 build_Mytes (opcode
, operand
)
1219 sh_opcode_info
*opcode
;
1220 sh_operand_info
*operand
;
1225 char *output
= frag_more (2);
1226 int low_byte
= target_big_endian
? 1 : 0;
1232 for (index
= 0; index
< 4; index
++)
1234 sh_nibble_type i
= opcode
->nibbles
[index
];
1244 nbuf
[index
] = reg_n
;
1247 nbuf
[index
] = reg_m
;
1250 if (reg_n
< 2 || reg_n
> 5)
1251 as_bad (_("Invalid register: 'r%d'"), reg_n
);
1252 nbuf
[index
] = (reg_n
& 3) | 4;
1255 nbuf
[index
] = reg_n
| (reg_m
>> 2);
1258 nbuf
[index
] = reg_b
| 0x08;
1261 insert (output
+ low_byte
, BFD_RELOC_SH_IMM4
, 0);
1264 insert (output
+ low_byte
, BFD_RELOC_SH_IMM4BY4
, 0);
1267 insert (output
+ low_byte
, BFD_RELOC_SH_IMM4BY2
, 0);
1270 insert (output
+ low_byte
, BFD_RELOC_SH_IMM4
, 0);
1273 insert (output
+ low_byte
, BFD_RELOC_SH_IMM8BY4
, 0);
1276 insert (output
+ low_byte
, BFD_RELOC_SH_IMM8BY2
, 0);
1279 insert (output
+ low_byte
, BFD_RELOC_SH_IMM8
, 0);
1282 insert (output
, BFD_RELOC_SH_PCRELIMM8BY4
, 1);
1285 insert (output
, BFD_RELOC_SH_PCRELIMM8BY2
, 1);
1288 printf (_("failed for %d\n"), i
);
1292 if (! target_big_endian
) {
1293 output
[1] = (nbuf
[0] << 4) | (nbuf
[1]);
1294 output
[0] = (nbuf
[2] << 4) | (nbuf
[3]);
1297 output
[0] = (nbuf
[0] << 4) | (nbuf
[1]);
1298 output
[1] = (nbuf
[2] << 4) | (nbuf
[3]);
1302 /* Find an opcode at the start of *STR_P in the hash table, and set
1303 *STR_P to the first character after the last one read. */
1305 static sh_opcode_info
*
1306 find_cooked_opcode (str_p
)
1310 unsigned char *op_start
;
1311 unsigned char *op_end
;
1314 /* Drop leading whitespace */
1318 /* Find the op code end.
1319 The pre-processor will eliminate whitespace in front of
1320 any '@' after the first argument; we may be called from
1321 assemble_ppi, so the opcode might be terminated by an '@'. */
1322 for (op_start
= op_end
= (unsigned char *) (str
);
1325 && !is_end_of_line
[*op_end
] && *op_end
!= ' ' && *op_end
!= '@';
1328 unsigned char c
= op_start
[nlen
];
1330 /* The machine independent code will convert CMP/EQ into cmp/EQ
1331 because it thinks the '/' is the end of the symbol. Moreover,
1332 all but the first sub-insn is a parallel processing insn won't
1333 be capitailzed. Instead of hacking up the machine independent
1334 code, we just deal with it here. */
1335 c
= isupper (c
) ? tolower (c
) : c
;
1344 as_bad (_("can't find opcode "));
1347 return (sh_opcode_info
*) hash_find (opcode_hash_control
, name
);
1350 /* Assemble a parallel processing insn. */
1351 #define DDT_BASE 0xf000 /* Base value for double data transfer insns */
1353 assemble_ppi (op_end
, opcode
)
1355 sh_opcode_info
*opcode
;
1364 /* Some insn ignore one or more register fields, e.g. psts machl,a0.
1365 Make sure we encode a defined insn pattern. */
1371 sh_operand_info operand
[3];
1373 if (opcode
->arg
[0] != A_END
)
1374 op_end
= get_operands (opcode
, op_end
, operand
);
1375 opcode
= get_specific (opcode
, operand
);
1378 /* Couldn't find an opcode which matched the operands */
1379 char *where
= frag_more (2);
1383 as_bad (_("invalid operands for opcode"));
1386 if (opcode
->nibbles
[0] != PPI
)
1387 as_bad (_("insn can't be combined with parallel processing insn"));
1389 switch (opcode
->nibbles
[1])
1394 as_bad (_("multiple movx specifications"));
1399 as_bad (_("multiple movy specifications"));
1405 as_bad (_("multiple movx specifications"));
1406 if (reg_n
< 4 || reg_n
> 5)
1407 as_bad (_("invalid movx address register"));
1408 if (opcode
->nibbles
[2] & 8)
1410 if (reg_m
== A_A1_NUM
)
1412 else if (reg_m
!= A_A0_NUM
)
1413 as_bad (_("invalid movx dsp register"));
1418 as_bad (_("invalid movx dsp register"));
1421 movx
+= ((reg_n
- 4) << 9) + (opcode
->nibbles
[2] << 2) + DDT_BASE
;
1426 as_bad (_("multiple movy specifications"));
1427 if (opcode
->nibbles
[2] & 8)
1429 /* Bit 3 in nibbles[2] is intended for bit 4 of the opcode,
1432 if (reg_m
== A_A1_NUM
)
1434 else if (reg_m
!= A_A0_NUM
)
1435 as_bad (_("invalid movy dsp register"));
1440 as_bad (_("invalid movy dsp register"));
1443 if (reg_n
< 6 || reg_n
> 7)
1444 as_bad (_("invalid movy address register"));
1445 movy
+= ((reg_n
- 6) << 8) + opcode
->nibbles
[2] + DDT_BASE
;
1449 if (immediate
.X_op
!= O_constant
)
1450 as_bad (_("dsp immediate shift value not constant"));
1451 field_b
= ((opcode
->nibbles
[2] << 12)
1452 | (immediate
.X_add_number
& 127) << 4
1457 as_bad (_("multiple parallel processing specifications"));
1458 field_b
= ((opcode
->nibbles
[2] << 12) + (opcode
->nibbles
[3] << 8)
1459 + (reg_x
<< 6) + (reg_y
<< 4) + reg_n
);
1463 as_bad (_("multiple condition specifications"));
1464 cond
= opcode
->nibbles
[2] << 8;
1466 goto skip_cond_check
;
1470 as_bad (_("multiple parallel processing specifications"));
1471 field_b
= ((opcode
->nibbles
[2] << 12) + (opcode
->nibbles
[3] << 8)
1472 + cond
+ (reg_x
<< 6) + (reg_y
<< 4) + reg_n
);
1478 if ((field_b
& 0xef00) != 0xa100)
1479 as_bad (_("insn cannot be combined with pmuls"));
1481 switch (field_b
& 0xf)
1484 field_b
+= 0 - A_X0_NUM
;
1487 field_b
+= 1 - A_Y0_NUM
;
1490 field_b
+= 2 - A_A0_NUM
;
1493 field_b
+= 3 - A_A1_NUM
;
1496 as_bad (_("bad padd / psub pmuls output operand"));
1499 field_b
+= 0x4000 + reg_efg
;
1506 as_bad (_("condition not followed by conditionalizable insn"));
1512 opcode
= find_cooked_opcode (&op_end
);
1516 (_("unrecognized characters at end of parallel processing insn")));
1521 move_code
= movx
| movy
;
1524 /* Parallel processing insn. */
1525 unsigned long ppi_code
= (movx
| movy
| 0xf800) << 16 | field_b
;
1527 output
= frag_more (4);
1528 if (! target_big_endian
)
1530 output
[3] = ppi_code
>> 8;
1531 output
[2] = ppi_code
;
1535 output
[2] = ppi_code
>> 8;
1536 output
[3] = ppi_code
;
1538 move_code
|= 0xf800;
1541 /* Just a double data transfer. */
1542 output
= frag_more (2);
1543 if (! target_big_endian
)
1545 output
[1] = move_code
>> 8;
1546 output
[0] = move_code
;
1550 output
[0] = move_code
>> 8;
1551 output
[1] = move_code
;
1555 /* This is the guts of the machine-dependent assembler. STR points to a
1556 machine dependent instruction. This function is supposed to emit
1557 the frags/bytes it assembles to.
1564 unsigned char *op_end
;
1565 sh_operand_info operand
[3];
1566 sh_opcode_info
*opcode
;
1568 opcode
= find_cooked_opcode (&str
);
1573 as_bad (_("unknown opcode"));
1578 && ! seg_info (now_seg
)->tc_segment_info_data
.in_code
)
1580 /* Output a CODE reloc to tell the linker that the following
1581 bytes are instructions, not data. */
1582 fix_new (frag_now
, frag_now_fix (), 2, &abs_symbol
, 0, 0,
1584 seg_info (now_seg
)->tc_segment_info_data
.in_code
= 1;
1587 if (opcode
->nibbles
[0] == PPI
)
1589 assemble_ppi (op_end
, opcode
);
1593 if (opcode
->arg
[0] == A_BDISP12
1594 || opcode
->arg
[0] == A_BDISP8
)
1596 parse_exp (op_end
+ 1);
1597 build_relax (opcode
);
1601 if (opcode
->arg
[0] == A_END
)
1603 /* Ignore trailing whitespace. If there is any, it has already
1604 been compressed to a single space. */
1610 op_end
= get_operands (opcode
, op_end
, operand
);
1612 opcode
= get_specific (opcode
, operand
);
1616 /* Couldn't find an opcode which matched the operands */
1617 char *where
= frag_more (2);
1621 as_bad (_("invalid operands for opcode"));
1626 as_bad (_("excess operands: '%s'"), op_end
);
1628 build_Mytes (opcode
, operand
);
1633 /* This routine is called each time a label definition is seen. It
1634 emits a BFD_RELOC_SH_LABEL reloc if necessary. */
1639 static fragS
*last_label_frag
;
1640 static int last_label_offset
;
1643 && seg_info (now_seg
)->tc_segment_info_data
.in_code
)
1647 offset
= frag_now_fix ();
1648 if (frag_now
!= last_label_frag
1649 || offset
!= last_label_offset
)
1651 fix_new (frag_now
, offset
, 2, &abs_symbol
, 0, 0, BFD_RELOC_SH_LABEL
);
1652 last_label_frag
= frag_now
;
1653 last_label_offset
= offset
;
1658 /* This routine is called when the assembler is about to output some
1659 data. It emits a BFD_RELOC_SH_DATA reloc if necessary. */
1662 sh_flush_pending_output ()
1665 && seg_info (now_seg
)->tc_segment_info_data
.in_code
)
1667 fix_new (frag_now
, frag_now_fix (), 2, &abs_symbol
, 0, 0,
1669 seg_info (now_seg
)->tc_segment_info_data
.in_code
= 0;
1674 DEFUN (md_undefined_symbol
, (name
),
1683 DEFUN (tc_crawl_symbol_chain
, (headers
),
1684 object_headers
* headers
)
1686 printf (_("call to tc_crawl_symbol_chain \n"));
1690 DEFUN (tc_headers_hook
, (headers
),
1691 object_headers
* headers
)
1693 printf (_("call to tc_headers_hook \n"));
1698 /* Various routines to kill one day */
1699 /* Equal to MAX_PRECISION in atof-ieee.c */
1700 #define MAX_LITTLENUMS 6
1702 /* Turn a string in input_line_pointer into a floating point constant of type
1703 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1704 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1707 md_atof (type
, litP
, sizeP
)
1713 LITTLENUM_TYPE words
[4];
1729 return _("bad call to md_atof");
1732 t
= atof_ieee (input_line_pointer
, type
, words
);
1734 input_line_pointer
= t
;
1738 if (! target_big_endian
)
1740 for (i
= prec
- 1; i
>= 0; i
--)
1742 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
1748 for (i
= 0; i
< prec
; i
++)
1750 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
1758 /* Handle the .uses pseudo-op. This pseudo-op is used just before a
1759 call instruction. It refers to a label of the instruction which
1760 loads the register which the call uses. We use it to generate a
1761 special reloc for the linker. */
1770 as_warn (_(".uses pseudo-op seen when not relaxing"));
1774 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
1776 as_bad (_("bad .uses format"));
1777 ignore_rest_of_line ();
1781 fix_new_exp (frag_now
, frag_now_fix (), 2, &ex
, 1, BFD_RELOC_SH_USES
);
1783 demand_empty_rest_of_line ();
1786 CONST
char *md_shortopts
= "";
1787 struct option md_longopts
[] = {
1789 #define OPTION_RELAX (OPTION_MD_BASE)
1790 #define OPTION_LITTLE (OPTION_MD_BASE + 1)
1791 #define OPTION_SMALL (OPTION_LITTLE + 1)
1792 #define OPTION_DSP (OPTION_SMALL + 1)
1794 {"relax", no_argument
, NULL
, OPTION_RELAX
},
1795 {"little", no_argument
, NULL
, OPTION_LITTLE
},
1796 {"small", no_argument
, NULL
, OPTION_SMALL
},
1797 {"dsp", no_argument
, NULL
, OPTION_DSP
},
1798 {NULL
, no_argument
, NULL
, 0}
1800 size_t md_longopts_size
= sizeof(md_longopts
);
1803 md_parse_option (c
, arg
)
1815 target_big_endian
= 0;
1834 md_show_usage (stream
)
1837 fprintf(stream
, _("\
1839 -little generate little endian code\n\
1840 -relax alter jump instructions for long displacements\n\
1841 -small align sections to 4 byte boundaries, not 16\n"));
1845 tc_Nout_fix_to_chars ()
1847 printf (_("call to tc_Nout_fix_to_chars \n"));
1851 /* This struct is used to pass arguments to sh_count_relocs through
1852 bfd_map_over_sections. */
1854 struct sh_count_relocs
1856 /* Symbol we are looking for. */
1858 /* Count of relocs found. */
1862 /* Count the number of fixups in a section which refer to a particular
1863 symbol. When using BFD_ASSEMBLER, this is called via
1864 bfd_map_over_sections. */
1868 sh_count_relocs (abfd
, sec
, data
)
1873 struct sh_count_relocs
*info
= (struct sh_count_relocs
*) data
;
1874 segment_info_type
*seginfo
;
1878 seginfo
= seg_info (sec
);
1879 if (seginfo
== NULL
)
1883 for (fix
= seginfo
->fix_root
; fix
!= NULL
; fix
= fix
->fx_next
)
1885 if (fix
->fx_addsy
== sym
)
1893 /* Handle the count relocs for a particular section. When using
1894 BFD_ASSEMBLER, this is called via bfd_map_over_sections. */
1898 sh_frob_section (abfd
, sec
, ignore
)
1903 segment_info_type
*seginfo
;
1906 seginfo
= seg_info (sec
);
1907 if (seginfo
== NULL
)
1910 for (fix
= seginfo
->fix_root
; fix
!= NULL
; fix
= fix
->fx_next
)
1915 struct sh_count_relocs info
;
1917 if (fix
->fx_r_type
!= BFD_RELOC_SH_USES
)
1920 /* The BFD_RELOC_SH_USES reloc should refer to a defined local
1921 symbol in the same section. */
1922 sym
= fix
->fx_addsy
;
1924 || fix
->fx_subsy
!= NULL
1925 || fix
->fx_addnumber
!= 0
1926 || S_GET_SEGMENT (sym
) != sec
1927 #if ! defined (BFD_ASSEMBLER) && defined (OBJ_COFF)
1928 || S_GET_STORAGE_CLASS (sym
) == C_EXT
1930 || S_IS_EXTERNAL (sym
))
1932 as_warn_where (fix
->fx_file
, fix
->fx_line
,
1933 _(".uses does not refer to a local symbol in the same section"));
1937 /* Look through the fixups again, this time looking for one
1938 at the same location as sym. */
1939 val
= S_GET_VALUE (sym
);
1940 for (fscan
= seginfo
->fix_root
;
1942 fscan
= fscan
->fx_next
)
1943 if (val
== fscan
->fx_frag
->fr_address
+ fscan
->fx_where
1944 && fscan
->fx_r_type
!= BFD_RELOC_SH_ALIGN
1945 && fscan
->fx_r_type
!= BFD_RELOC_SH_CODE
1946 && fscan
->fx_r_type
!= BFD_RELOC_SH_DATA
1947 && fscan
->fx_r_type
!= BFD_RELOC_SH_LABEL
)
1951 as_warn_where (fix
->fx_file
, fix
->fx_line
,
1952 _("can't find fixup pointed to by .uses"));
1956 if (fscan
->fx_tcbit
)
1958 /* We've already done this one. */
1962 /* fscan should also be a fixup to a local symbol in the same
1964 sym
= fscan
->fx_addsy
;
1966 || fscan
->fx_subsy
!= NULL
1967 || fscan
->fx_addnumber
!= 0
1968 || S_GET_SEGMENT (sym
) != sec
1969 #if ! defined (BFD_ASSEMBLER) && defined (OBJ_COFF)
1970 || S_GET_STORAGE_CLASS (sym
) == C_EXT
1972 || S_IS_EXTERNAL (sym
))
1974 as_warn_where (fix
->fx_file
, fix
->fx_line
,
1975 _(".uses target does not refer to a local symbol in the same section"));
1979 /* Now we look through all the fixups of all the sections,
1980 counting the number of times we find a reference to sym. */
1983 #ifdef BFD_ASSEMBLER
1984 bfd_map_over_sections (stdoutput
, sh_count_relocs
, (PTR
) &info
);
1989 for (iscan
= SEG_E0
; iscan
< SEG_UNKNOWN
; iscan
++)
1990 sh_count_relocs ((bfd
*) NULL
, iscan
, (PTR
) &info
);
1997 /* Generate a BFD_RELOC_SH_COUNT fixup at the location of sym.
1998 We have already adjusted the value of sym to include the
1999 fragment address, so we undo that adjustment here. */
2000 subseg_change (sec
, 0);
2001 fix_new (symbol_get_frag (sym
),
2002 S_GET_VALUE (sym
) - symbol_get_frag (sym
)->fr_address
,
2003 4, &abs_symbol
, info
.count
, 0, BFD_RELOC_SH_COUNT
);
2007 /* This function is called after the symbol table has been completed,
2008 but before the relocs or section contents have been written out.
2009 If we have seen any .uses pseudo-ops, they point to an instruction
2010 which loads a register with the address of a function. We look
2011 through the fixups to find where the function address is being
2012 loaded from. We then generate a COUNT reloc giving the number of
2013 times that function address is referred to. The linker uses this
2014 information when doing relaxing, to decide when it can eliminate
2015 the stored function address entirely. */
2023 #ifdef BFD_ASSEMBLER
2024 bfd_map_over_sections (stdoutput
, sh_frob_section
, (PTR
) NULL
);
2029 for (iseg
= SEG_E0
; iseg
< SEG_UNKNOWN
; iseg
++)
2030 sh_frob_section ((bfd
*) NULL
, iseg
, (PTR
) NULL
);
2035 /* Called after relaxing. Set the correct sizes of the fragments, and
2036 create relocs so that md_apply_fix will fill in the correct values. */
2039 md_convert_frag (headers
, seg
, fragP
)
2040 #ifdef BFD_ASSEMBLER
2043 object_headers
*headers
;
2050 switch (fragP
->fr_subtype
)
2052 case C (COND_JUMP
, COND8
):
2053 case C (COND_JUMP_DELAY
, COND8
):
2054 subseg_change (seg
, 0);
2055 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
2056 1, BFD_RELOC_SH_PCDISP8BY2
);
2061 case C (UNCOND_JUMP
, UNCOND12
):
2062 subseg_change (seg
, 0);
2063 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, fragP
->fr_offset
,
2064 1, BFD_RELOC_SH_PCDISP12BY2
);
2069 case C (UNCOND_JUMP
, UNCOND32
):
2070 case C (UNCOND_JUMP
, UNDEF_WORD_DISP
):
2071 if (fragP
->fr_symbol
== NULL
)
2072 as_bad (_("at 0x%lx, displacement overflows 12-bit field"),
2073 (unsigned long) fragP
->fr_address
);
2074 else if (S_IS_DEFINED (fragP
->fr_symbol
))
2075 as_bad (_("at 0x%lx, displacement to defined symbol %s overflows 12-bit field"),
2076 (unsigned long) fragP
->fr_address
,
2077 S_GET_NAME (fragP
->fr_symbol
));
2079 as_bad (_("at 0x%lx, displacement to undefined symbol %s overflows 12-bit field"),
2080 (unsigned long) fragP
->fr_address
,
2081 S_GET_NAME (fragP
->fr_symbol
));
2083 #if 0 /* This code works, but generates poor code and the compiler
2084 should never produce a sequence that requires it to be used. */
2086 /* A jump wont fit in 12 bits, make code which looks like
2092 int t
= buffer
[0] & 0x10;
2094 buffer
[highbyte
] = 0xa0; /* branch over move and disp */
2095 buffer
[lowbyte
] = 3;
2096 buffer
[highbyte
+2] = 0xd0 | JREG
; /* Build mov insn */
2097 buffer
[lowbyte
+2] = 0x00;
2099 buffer
[highbyte
+4] = 0; /* space for 32 bit jump disp */
2100 buffer
[lowbyte
+4] = 0;
2101 buffer
[highbyte
+6] = 0;
2102 buffer
[lowbyte
+6] = 0;
2104 buffer
[highbyte
+8] = 0x40 | JREG
; /* Build jmp @JREG */
2105 buffer
[lowbyte
+8] = t
? 0xb : 0x2b;
2107 buffer
[highbyte
+10] = 0x20; /* build nop */
2108 buffer
[lowbyte
+10] = 0x0b;
2110 /* Make reloc for the long disp */
2118 fragP
->fr_fix
+= UNCOND32_LENGTH
;
2125 case C (COND_JUMP
, COND12
):
2126 case C (COND_JUMP_DELAY
, COND12
):
2127 /* A bcond won't fit, so turn it into a b!cond; bra disp; nop */
2128 /* I found that a relax failure for gcc.c-torture/execute/930628-1.c
2129 was due to gas incorrectly relaxing an out-of-range conditional
2130 branch with delay slot. It turned:
2131 bf.s L6 (slot mov.l r12,@(44,r0))
2134 2c: 8f 01 a0 8b bf.s 32 <_main+32> (slot bra L6)
2136 32: 10 cb mov.l r12,@(44,r0)
2137 Therefore, branches with delay slots have to be handled
2138 differently from ones without delay slots. */
2140 unsigned char *buffer
=
2141 (unsigned char *) (fragP
->fr_fix
+ fragP
->fr_literal
);
2142 int highbyte
= target_big_endian
? 0 : 1;
2143 int lowbyte
= target_big_endian
? 1 : 0;
2144 int delay
= fragP
->fr_subtype
== C (COND_JUMP_DELAY
, COND12
);
2146 /* Toggle the true/false bit of the bcond. */
2147 buffer
[highbyte
] ^= 0x2;
2149 /* If this is a dalayed branch, we may not put the the bra in the
2150 slot. So we change it to a non-delayed branch, like that:
2151 b! cond slot_label; bra disp; slot_label: slot_insn
2152 ??? We should try if swapping the conditional branch and
2153 its delay-slot insn already makes the branch reach. */
2155 /* Build a relocation to six / four bytes farther on. */
2156 subseg_change (seg
, 0);
2157 fix_new (fragP
, fragP
->fr_fix
, 2,
2158 #ifdef BFD_ASSEMBLER
2159 section_symbol (seg
),
2161 seg_info (seg
)->dot
,
2163 fragP
->fr_address
+ fragP
->fr_fix
+ (delay
? 4 : 6),
2164 1, BFD_RELOC_SH_PCDISP8BY2
);
2166 /* Set up a jump instruction. */
2167 buffer
[highbyte
+ 2] = 0xa0;
2168 buffer
[lowbyte
+ 2] = 0;
2169 fix_new (fragP
, fragP
->fr_fix
+ 2, 2, fragP
->fr_symbol
,
2170 fragP
->fr_offset
, 1, BFD_RELOC_SH_PCDISP12BY2
);
2174 buffer
[highbyte
] &= ~0x4; /* Removes delay slot from branch. */
2179 /* Fill in a NOP instruction. */
2180 buffer
[highbyte
+ 4] = 0x0;
2181 buffer
[lowbyte
+ 4] = 0x9;
2190 case C (COND_JUMP
, COND32
):
2191 case C (COND_JUMP_DELAY
, COND32
):
2192 case C (COND_JUMP
, UNDEF_WORD_DISP
):
2193 case C (COND_JUMP_DELAY
, UNDEF_WORD_DISP
):
2194 if (fragP
->fr_symbol
== NULL
)
2195 as_bad (_("at 0x%lx, displacement overflows 8-bit field"),
2196 (unsigned long) fragP
->fr_address
);
2197 else if (S_IS_DEFINED (fragP
->fr_symbol
))
2198 as_bad (_("at 0x%lx, displacement to defined symbol %s overflows 8-bit field "),
2199 (unsigned long) fragP
->fr_address
,
2200 S_GET_NAME (fragP
->fr_symbol
));
2202 as_bad (_("at 0x%lx, displacement to undefined symbol %s overflows 8-bit field "),
2203 (unsigned long) fragP
->fr_address
,
2204 S_GET_NAME (fragP
->fr_symbol
));
2206 #if 0 /* This code works, but generates poor code, and the compiler
2207 should never produce a sequence that requires it to be used. */
2209 /* A bcond won't fit and it won't go into a 12 bit
2210 displacement either, the code sequence looks like:
2219 buffer
[0] ^= 0x2; /* Toggle T/F bit */
2221 buffer
[1] = 5; /* branch over mov, jump, nop and ptr */
2222 buffer
[2] = 0xd0 | JREG
; /* Build mov insn */
2224 buffer
[4] = 0x40 | JREG
; /* Build jmp @JREG */
2226 buffer
[6] = 0x20; /* build nop */
2228 buffer
[8] = 0; /* space for 32 bit jump disp */
2234 /* Make reloc for the long disp */
2242 fragP
->fr_fix
+= COND32_LENGTH
;
2253 if (donerelax
&& !sh_relax
)
2254 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
2255 _("overflow in branch to %s; converted into longer instruction sequence"),
2256 (fragP
->fr_symbol
!= NULL
2257 ? S_GET_NAME (fragP
->fr_symbol
)
2262 DEFUN (md_section_align
, (seg
, size
),
2266 #ifdef BFD_ASSEMBLER
2269 #else /* ! OBJ_ELF */
2270 return ((size
+ (1 << bfd_get_section_alignment (stdoutput
, seg
)) - 1)
2271 & (-1 << bfd_get_section_alignment (stdoutput
, seg
)));
2272 #endif /* ! OBJ_ELF */
2273 #else /* ! BFD_ASSEMBLER */
2274 return ((size
+ (1 << section_alignment
[(int) seg
]) - 1)
2275 & (-1 << section_alignment
[(int) seg
]));
2276 #endif /* ! BFD_ASSEMBLER */
2279 /* This static variable is set by s_uacons to tell sh_cons_align that
2280 the expession does not need to be aligned. */
2282 static int sh_no_align_cons
= 0;
2284 /* This handles the unaligned space allocation pseudo-ops, such as
2285 .uaword. .uaword is just like .word, but the value does not need
2292 /* Tell sh_cons_align not to align this value. */
2293 sh_no_align_cons
= 1;
2297 /* If a .word, et. al., pseud-op is seen, warn if the value is not
2298 aligned correctly. Note that this can cause warnings to be issued
2299 when assembling initialized structured which were declared with the
2300 packed attribute. FIXME: Perhaps we should require an option to
2301 enable this warning? */
2304 sh_cons_align (nbytes
)
2310 if (sh_no_align_cons
)
2312 /* This is an unaligned pseudo-op. */
2313 sh_no_align_cons
= 0;
2318 while ((nbytes
& 1) == 0)
2327 if (now_seg
== absolute_section
)
2329 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
2330 as_warn (_("misaligned data"));
2334 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
2335 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
2337 record_alignment (now_seg
, nalign
);
2340 /* When relaxing, we need to output a reloc for any .align directive
2341 that requests alignment to a four byte boundary or larger. This is
2342 also where we check for misaligned data. */
2345 sh_handle_align (frag
)
2349 && frag
->fr_type
== rs_align
2350 && frag
->fr_address
+ frag
->fr_fix
> 0
2351 && frag
->fr_offset
> 1
2352 && now_seg
!= bss_section
)
2353 fix_new (frag
, frag
->fr_fix
, 2, &abs_symbol
, frag
->fr_offset
, 0,
2354 BFD_RELOC_SH_ALIGN
);
2356 if (frag
->fr_type
== rs_align_code
2357 && frag
->fr_next
->fr_address
- frag
->fr_address
- frag
->fr_fix
!= 0)
2358 as_warn_where (frag
->fr_file
, frag
->fr_line
, _("misaligned data"));
2361 /* This macro decides whether a particular reloc is an entry in a
2362 switch table. It is used when relaxing, because the linker needs
2363 to know about all such entries so that it can adjust them if
2366 #ifdef BFD_ASSEMBLER
2367 #define SWITCH_TABLE_CONS(fix) (0)
2369 #define SWITCH_TABLE_CONS(fix) \
2370 ((fix)->fx_r_type == 0 \
2371 && ((fix)->fx_size == 2 \
2372 || (fix)->fx_size == 1 \
2373 || (fix)->fx_size == 4))
2376 #define SWITCH_TABLE(fix) \
2377 ((fix)->fx_addsy != NULL \
2378 && (fix)->fx_subsy != NULL \
2379 && S_GET_SEGMENT ((fix)->fx_addsy) == text_section \
2380 && S_GET_SEGMENT ((fix)->fx_subsy) == text_section \
2381 && ((fix)->fx_r_type == BFD_RELOC_32 \
2382 || (fix)->fx_r_type == BFD_RELOC_16 \
2383 || (fix)->fx_r_type == BFD_RELOC_8 \
2384 || SWITCH_TABLE_CONS (fix)))
2386 /* See whether we need to force a relocation into the output file.
2387 This is used to force out switch and PC relative relocations when
2391 sh_force_relocation (fix
)
2395 if (fix
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2396 || fix
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2402 return (fix
->fx_pcrel
2403 || SWITCH_TABLE (fix
)
2404 || fix
->fx_r_type
== BFD_RELOC_SH_COUNT
2405 || fix
->fx_r_type
== BFD_RELOC_SH_ALIGN
2406 || fix
->fx_r_type
== BFD_RELOC_SH_CODE
2407 || fix
->fx_r_type
== BFD_RELOC_SH_DATA
2408 || fix
->fx_r_type
== BFD_RELOC_SH_LABEL
);
2413 sh_fix_adjustable (fixP
)
2417 if (fixP
->fx_addsy
== NULL
)
2420 /* We need the symbol name for the VTABLE entries */
2421 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2422 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2428 void sh_elf_final_processing()
2432 /* Set file-specific flags to indicate if this code needs
2433 a processor with the sh-dsp / sh3e ISA to execute. */
2434 if (valid_arch
& arch_sh1
)
2436 else if (valid_arch
& arch_sh2
)
2438 else if (valid_arch
& arch_sh_dsp
)
2440 else if (valid_arch
& arch_sh3
)
2442 else if (valid_arch
& arch_sh3_dsp
)
2444 else if (valid_arch
& arch_sh3e
)
2446 else if (valid_arch
& arch_sh4
)
2451 elf_elfheader (stdoutput
)->e_flags
&= ~EF_SH_MACH_MASK
;
2452 elf_elfheader (stdoutput
)->e_flags
|= val
;
2456 /* Apply a fixup to the object file. */
2458 #ifdef BFD_ASSEMBLER
2460 md_apply_fix (fixP
, valp
)
2465 md_apply_fix (fixP
, val
)
2470 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2471 int lowbyte
= target_big_endian
? 1 : 0;
2472 int highbyte
= target_big_endian
? 0 : 1;
2473 #ifdef BFD_ASSEMBLER
2479 #ifdef BFD_ASSEMBLER
2480 /* adjust_reloc_syms won't convert a reloc against a weak symbol
2481 into a reloc against a section, but bfd_install_relocation will
2482 screw up if the symbol is defined, so we have to adjust val here
2483 to avoid the screw up later. */
2484 if (fixP
->fx_addsy
!= NULL
2485 && S_IS_WEAK (fixP
->fx_addsy
))
2486 val
-= S_GET_VALUE (fixP
->fx_addsy
);
2489 #ifndef BFD_ASSEMBLER
2490 if (fixP
->fx_r_type
== 0)
2492 if (fixP
->fx_size
== 2)
2493 fixP
->fx_r_type
= BFD_RELOC_16
;
2494 else if (fixP
->fx_size
== 4)
2495 fixP
->fx_r_type
= BFD_RELOC_32
;
2496 else if (fixP
->fx_size
== 1)
2497 fixP
->fx_r_type
= BFD_RELOC_8
;
2505 switch (fixP
->fx_r_type
)
2507 case BFD_RELOC_SH_IMM4
:
2509 *buf
= (*buf
& 0xf0) | (val
& 0xf);
2512 case BFD_RELOC_SH_IMM4BY2
:
2515 *buf
= (*buf
& 0xf0) | ((val
>> 1) & 0xf);
2518 case BFD_RELOC_SH_IMM4BY4
:
2521 *buf
= (*buf
& 0xf0) | ((val
>> 2) & 0xf);
2524 case BFD_RELOC_SH_IMM8BY2
:
2530 case BFD_RELOC_SH_IMM8BY4
:
2537 case BFD_RELOC_SH_IMM8
:
2538 /* Sometimes the 8 bit value is sign extended (e.g., add) and
2539 sometimes it is not (e.g., and). We permit any 8 bit value.
2540 Note that adding further restrictions may invalidate
2541 reasonable looking assembly code, such as ``and -0x1,r0''. */
2547 case BFD_RELOC_SH_PCRELIMM8BY4
:
2548 /* The lower two bits of the PC are cleared before the
2549 displacement is added in. We can assume that the destination
2550 is on a 4 byte bounday. If this instruction is also on a 4
2551 byte boundary, then we want
2553 and target - here is a multiple of 4.
2554 Otherwise, we are on a 2 byte boundary, and we want
2555 (target - (here - 2)) / 4
2556 and target - here is not a multiple of 4. Computing
2557 (target - (here - 2)) / 4 == (target - here + 2) / 4
2558 works for both cases, since in the first case the addition of
2559 2 will be removed by the division. target - here is in the
2561 val
= (val
+ 2) / 4;
2563 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far"));
2567 case BFD_RELOC_SH_PCRELIMM8BY2
:
2570 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far"));
2574 case BFD_RELOC_SH_PCDISP8BY2
:
2576 if (val
< -0x80 || val
> 0x7f)
2577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far"));
2581 case BFD_RELOC_SH_PCDISP12BY2
:
2583 if (val
< -0x800 || val
>= 0x7ff)
2584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("pcrel too far"));
2585 buf
[lowbyte
] = val
& 0xff;
2586 buf
[highbyte
] |= (val
>> 8) & 0xf;
2590 if (! target_big_endian
)
2607 if (! target_big_endian
)
2619 case BFD_RELOC_SH_USES
:
2620 /* Pass the value into sh_coff_reloc_mangle. */
2621 fixP
->fx_addnumber
= val
;
2624 case BFD_RELOC_SH_COUNT
:
2625 case BFD_RELOC_SH_ALIGN
:
2626 case BFD_RELOC_SH_CODE
:
2627 case BFD_RELOC_SH_DATA
:
2628 case BFD_RELOC_SH_LABEL
:
2629 /* Nothing to do here. */
2632 case BFD_RELOC_VTABLE_INHERIT
:
2633 case BFD_RELOC_VTABLE_ENTRY
:
2635 #ifdef BFD_ASSEMBLER
2647 if ((val
& ((1 << shift
) - 1)) != 0)
2648 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("misaligned offset"));
2652 val
= ((val
>> shift
)
2653 | ((long) -1 & ~ ((long) -1 >> shift
)));
2655 if (max
!= 0 && (val
< min
|| val
> max
))
2656 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("offset out of range"));
2658 #ifdef BFD_ASSEMBLER
2663 /* Called just before address relaxation. Return the length
2664 by which a fragment must grow to reach it's destination. */
2667 md_estimate_size_before_relax (fragP
, segment_type
)
2668 register fragS
*fragP
;
2669 register segT segment_type
;
2671 switch (fragP
->fr_subtype
)
2673 case C (UNCOND_JUMP
, UNDEF_DISP
):
2674 /* used to be a branch to somewhere which was unknown */
2675 if (!fragP
->fr_symbol
)
2677 fragP
->fr_subtype
= C (UNCOND_JUMP
, UNCOND12
);
2678 fragP
->fr_var
= md_relax_table
[C (UNCOND_JUMP
, UNCOND12
)].rlx_length
;
2680 else if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment_type
)
2682 fragP
->fr_subtype
= C (UNCOND_JUMP
, UNCOND12
);
2683 fragP
->fr_var
= md_relax_table
[C (UNCOND_JUMP
, UNCOND12
)].rlx_length
;
2687 fragP
->fr_subtype
= C (UNCOND_JUMP
, UNDEF_WORD_DISP
);
2688 fragP
->fr_var
= md_relax_table
[C (UNCOND_JUMP
, UNCOND32
)].rlx_length
;
2689 return md_relax_table
[C (UNCOND_JUMP
, UNCOND32
)].rlx_length
;
2695 case C (COND_JUMP
, UNDEF_DISP
):
2696 case C (COND_JUMP_DELAY
, UNDEF_DISP
):
2697 /* used to be a branch to somewhere which was unknown */
2698 if (fragP
->fr_symbol
2699 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment_type
)
2701 int what
= GET_WHAT (fragP
->fr_subtype
);
2702 /* Got a symbol and it's defined in this segment, become byte
2703 sized - maybe it will fix up */
2704 fragP
->fr_subtype
= C (what
, COND8
);
2705 fragP
->fr_var
= md_relax_table
[C (what
, COND8
)].rlx_length
;
2707 else if (fragP
->fr_symbol
)
2709 int what
= GET_WHAT (fragP
->fr_subtype
);
2710 /* Its got a segment, but its not ours, so it will always be long */
2711 fragP
->fr_subtype
= C (what
, UNDEF_WORD_DISP
);
2712 fragP
->fr_var
= md_relax_table
[C (what
, COND32
)].rlx_length
;
2713 return md_relax_table
[C (what
, COND32
)].rlx_length
;
2717 int what
= GET_WHAT (fragP
->fr_subtype
);
2718 /* We know the abs value */
2719 fragP
->fr_subtype
= C (what
, COND8
);
2720 fragP
->fr_var
= md_relax_table
[C (what
, COND8
)].rlx_length
;
2725 return fragP
->fr_var
;
2728 /* Put number into target byte order */
2731 md_number_to_chars (ptr
, use
, nbytes
)
2736 if (! target_big_endian
)
2737 number_to_chars_littleendian (ptr
, use
, nbytes
);
2739 number_to_chars_bigendian (ptr
, use
, nbytes
);
2743 md_pcrel_from (fixP
)
2746 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
+ 2;
2752 tc_coff_sizemachdep (frag
)
2755 return md_relax_table
[frag
->fr_subtype
].rlx_length
;
2758 #endif /* OBJ_COFF */
2760 /* When we align the .text section, insert the correct NOP pattern. */
2763 sh_do_align (n
, fill
, len
, max
)
2770 && subseg_text_p (now_seg
)
2773 static const unsigned char big_nop_pattern
[] = { 0x00, 0x09 };
2774 static const unsigned char little_nop_pattern
[] = { 0x09, 0x00 };
2776 /* First align to a 2 byte boundary, in case there is an odd
2778 frag_align (1, 0, 0);
2779 if (target_big_endian
)
2780 frag_align_pattern (n
, big_nop_pattern
, sizeof big_nop_pattern
, max
);
2782 frag_align_pattern (n
, little_nop_pattern
, sizeof little_nop_pattern
,
2790 #ifndef BFD_ASSEMBLER
2793 /* Map BFD relocs to SH COFF relocs. */
2797 bfd_reloc_code_real_type bfd_reloc
;
2801 static const struct reloc_map coff_reloc_map
[] =
2803 { BFD_RELOC_32
, R_SH_IMM32
},
2804 { BFD_RELOC_16
, R_SH_IMM16
},
2805 { BFD_RELOC_8
, R_SH_IMM8
},
2806 { BFD_RELOC_SH_PCDISP8BY2
, R_SH_PCDISP8BY2
},
2807 { BFD_RELOC_SH_PCDISP12BY2
, R_SH_PCDISP
},
2808 { BFD_RELOC_SH_IMM4
, R_SH_IMM4
},
2809 { BFD_RELOC_SH_IMM4BY2
, R_SH_IMM4BY2
},
2810 { BFD_RELOC_SH_IMM4BY4
, R_SH_IMM4BY4
},
2811 { BFD_RELOC_SH_IMM8
, R_SH_IMM8
},
2812 { BFD_RELOC_SH_IMM8BY2
, R_SH_IMM8BY2
},
2813 { BFD_RELOC_SH_IMM8BY4
, R_SH_IMM8BY4
},
2814 { BFD_RELOC_SH_PCRELIMM8BY2
, R_SH_PCRELIMM8BY2
},
2815 { BFD_RELOC_SH_PCRELIMM8BY4
, R_SH_PCRELIMM8BY4
},
2816 { BFD_RELOC_8_PCREL
, R_SH_SWITCH8
},
2817 { BFD_RELOC_SH_SWITCH16
, R_SH_SWITCH16
},
2818 { BFD_RELOC_SH_SWITCH32
, R_SH_SWITCH32
},
2819 { BFD_RELOC_SH_USES
, R_SH_USES
},
2820 { BFD_RELOC_SH_COUNT
, R_SH_COUNT
},
2821 { BFD_RELOC_SH_ALIGN
, R_SH_ALIGN
},
2822 { BFD_RELOC_SH_CODE
, R_SH_CODE
},
2823 { BFD_RELOC_SH_DATA
, R_SH_DATA
},
2824 { BFD_RELOC_SH_LABEL
, R_SH_LABEL
},
2825 { BFD_RELOC_UNUSED
, 0 }
2828 /* Adjust a reloc for the SH. This is similar to the generic code,
2829 but does some minor tweaking. */
2832 sh_coff_reloc_mangle (seg
, fix
, intr
, paddr
)
2833 segment_info_type
*seg
;
2835 struct internal_reloc
*intr
;
2838 symbolS
*symbol_ptr
= fix
->fx_addsy
;
2841 intr
->r_vaddr
= paddr
+ fix
->fx_frag
->fr_address
+ fix
->fx_where
;
2843 if (! SWITCH_TABLE (fix
))
2845 const struct reloc_map
*rm
;
2847 for (rm
= coff_reloc_map
; rm
->bfd_reloc
!= BFD_RELOC_UNUSED
; rm
++)
2848 if (rm
->bfd_reloc
== (bfd_reloc_code_real_type
) fix
->fx_r_type
)
2850 if (rm
->bfd_reloc
== BFD_RELOC_UNUSED
)
2851 as_bad_where (fix
->fx_file
, fix
->fx_line
,
2852 _("Can not represent %s relocation in this object file format"),
2853 bfd_get_reloc_code_name (fix
->fx_r_type
));
2854 intr
->r_type
= rm
->sh_reloc
;
2861 if (fix
->fx_r_type
== BFD_RELOC_16
)
2862 intr
->r_type
= R_SH_SWITCH16
;
2863 else if (fix
->fx_r_type
== BFD_RELOC_8
)
2864 intr
->r_type
= R_SH_SWITCH8
;
2865 else if (fix
->fx_r_type
== BFD_RELOC_32
)
2866 intr
->r_type
= R_SH_SWITCH32
;
2870 /* For a switch reloc, we set r_offset to the difference between
2871 the reloc address and the subtrahend. When the linker is
2872 doing relaxing, it can use the determine the starting and
2873 ending points of the switch difference expression. */
2874 intr
->r_offset
= intr
->r_vaddr
- S_GET_VALUE (fix
->fx_subsy
);
2877 /* PC relative relocs are always against the current section. */
2878 if (symbol_ptr
== NULL
)
2880 switch (fix
->fx_r_type
)
2882 case BFD_RELOC_SH_PCRELIMM8BY2
:
2883 case BFD_RELOC_SH_PCRELIMM8BY4
:
2884 case BFD_RELOC_SH_PCDISP8BY2
:
2885 case BFD_RELOC_SH_PCDISP12BY2
:
2886 case BFD_RELOC_SH_USES
:
2887 symbol_ptr
= seg
->dot
;
2894 if (fix
->fx_r_type
== BFD_RELOC_SH_USES
)
2896 /* We can't store the offset in the object file, since this
2897 reloc does not take up any space, so we store it in r_offset.
2898 The fx_addnumber field was set in md_apply_fix. */
2899 intr
->r_offset
= fix
->fx_addnumber
;
2901 else if (fix
->fx_r_type
== BFD_RELOC_SH_COUNT
)
2903 /* We can't store the count in the object file, since this reloc
2904 does not take up any space, so we store it in r_offset. The
2905 fx_offset field was set when the fixup was created in
2906 sh_coff_frob_file. */
2907 intr
->r_offset
= fix
->fx_offset
;
2908 /* This reloc is always absolute. */
2911 else if (fix
->fx_r_type
== BFD_RELOC_SH_ALIGN
)
2913 /* Store the alignment in the r_offset field. */
2914 intr
->r_offset
= fix
->fx_offset
;
2915 /* This reloc is always absolute. */
2918 else if (fix
->fx_r_type
== BFD_RELOC_SH_CODE
2919 || fix
->fx_r_type
== BFD_RELOC_SH_DATA
2920 || fix
->fx_r_type
== BFD_RELOC_SH_LABEL
)
2922 /* These relocs are always absolute. */
2926 /* Turn the segment of the symbol into an offset. */
2927 if (symbol_ptr
!= NULL
)
2929 dot
= segment_info
[S_GET_SEGMENT (symbol_ptr
)].dot
;
2931 intr
->r_symndx
= dot
->sy_number
;
2933 intr
->r_symndx
= symbol_ptr
->sy_number
;
2936 intr
->r_symndx
= -1;
2939 #endif /* OBJ_COFF */
2940 #endif /* ! BFD_ASSEMBLER */
2942 #ifdef BFD_ASSEMBLER
2944 /* Create a reloc. */
2947 tc_gen_reloc (section
, fixp
)
2952 bfd_reloc_code_real_type r_type
;
2954 rel
= (arelent
*) xmalloc (sizeof (arelent
));
2955 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
2956 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
2957 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2959 r_type
= fixp
->fx_r_type
;
2961 if (SWITCH_TABLE (fixp
))
2963 rel
->addend
= rel
->address
- S_GET_VALUE (fixp
->fx_subsy
);
2964 if (r_type
== BFD_RELOC_16
)
2965 r_type
= BFD_RELOC_SH_SWITCH16
;
2966 else if (r_type
== BFD_RELOC_8
)
2967 r_type
= BFD_RELOC_8_PCREL
;
2968 else if (r_type
== BFD_RELOC_32
)
2969 r_type
= BFD_RELOC_SH_SWITCH32
;
2973 else if (r_type
== BFD_RELOC_SH_USES
)
2974 rel
->addend
= fixp
->fx_addnumber
;
2975 else if (r_type
== BFD_RELOC_SH_COUNT
)
2976 rel
->addend
= fixp
->fx_offset
;
2977 else if (r_type
== BFD_RELOC_SH_ALIGN
)
2978 rel
->addend
= fixp
->fx_offset
;
2979 else if (r_type
== BFD_RELOC_VTABLE_INHERIT
2980 || r_type
== BFD_RELOC_VTABLE_ENTRY
)
2981 rel
->addend
= fixp
->fx_offset
;
2982 else if (fixp
->fx_pcrel
)
2983 rel
->addend
= fixp
->fx_addnumber
;
2987 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, r_type
);
2988 if (rel
->howto
== NULL
)
2990 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2991 _("Cannot represent relocation type %s"),
2992 bfd_get_reloc_code_name (r_type
));
2993 /* Set howto to a garbage value so that we can keep going. */
2994 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
2995 assert (rel
->howto
!= NULL
);
3001 #endif /* BFD_ASSEMBLER */