1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_sparc_asi (char **, const sparc_asi
**);
40 static int parse_keyword_arg (int (*) (const char *), char **, int *);
41 static int parse_const_expr_arg (char **, int *);
42 static int get_expression (char *);
44 /* Default architecture. */
45 /* ??? The default value should be V8, but sparclite support was added
46 by making it the default. GCC now passes -Asparclite, so maybe sometime in
47 the future we can set this to V8. */
49 #define DEFAULT_ARCH "sparclite"
51 static const char *default_arch
= DEFAULT_ARCH
;
53 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 static int default_init_p
;
57 /* Current architecture. We don't bump up unless necessary. */
58 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
60 /* The maximum architecture level we can bump up to.
61 In a 32 bit environment, don't allow bumping up to v9 by default.
62 The native assembler works this way. The user is required to pass
63 an explicit argument before we'll create v9 object files. However, if
64 we don't see any v9 insns, a v8plus object file is not created. */
65 static enum sparc_opcode_arch_val max_architecture
;
67 /* Either 32 or 64, selects file format. */
68 static int sparc_arch_size
;
69 /* Initial (default) value, recorded separately in case a user option
70 changes the value before md_show_usage is called. */
71 static int default_arch_size
;
74 /* The currently selected v9 memory model. Currently only used for
76 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
79 /* Bitmask of instruction types seen so far, used to populate the
80 GNU attributes section with hwcap information. */
81 static bfd_uint64_t hwcap_seen
;
85 static bfd_uint64_t hwcap_allowed
;
87 static int architecture_requested
;
88 static int warn_on_bump
;
90 /* If warn_on_bump and the needed architecture is higher than this
91 architecture, issue a warning. */
92 static enum sparc_opcode_arch_val warn_after_architecture
;
94 /* Non-zero if the assembler should generate error if an undeclared
95 g[23] register has been used in -64. */
96 static int no_undeclared_regs
;
98 /* Non-zero if the assembler should generate a warning if an
99 unpredictable DCTI (delayed control transfer instruction) couple is
101 static int dcti_couples_detect
;
103 /* Non-zero if we should try to relax jumps and calls. */
104 static int sparc_relax
;
106 /* Non-zero if we are generating PIC code. */
109 /* Non-zero if we should give an error when misaligned data is seen. */
110 static int enforce_aligned_data
;
112 extern int target_big_endian
;
114 static int target_little_endian_data
;
116 /* Symbols for global registers on v9. */
117 static symbolS
*globals
[8];
119 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
120 int sparc_cie_data_alignment
;
122 /* V9 and 86x have big and little endian data, but instructions are always big
123 endian. The sparclet has bi-endian support but both data and insns have
124 the same endianness. Global `target_big_endian' is used for data.
125 The following macro is used for instructions. */
126 #ifndef INSN_BIG_ENDIAN
127 #define INSN_BIG_ENDIAN (target_big_endian \
128 || default_arch_type == sparc86x \
129 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
132 /* Handle of the OPCODE hash table. */
133 static struct hash_control
*op_hash
;
135 static void s_data1 (void);
136 static void s_seg (int);
137 static void s_proc (int);
138 static void s_reserve (int);
139 static void s_common (int);
140 static void s_empty (int);
141 static void s_uacons (int);
142 static void s_ncons (int);
144 static void s_register (int);
147 const pseudo_typeS md_pseudo_table
[] =
149 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common
, 0},
151 {"empty", s_empty
, 0},
152 {"global", s_globl
, 0},
154 {"nword", s_ncons
, 0},
155 {"optim", s_ignore
, 0},
157 {"reserve", s_reserve
, 0},
159 {"skip", s_space
, 0},
162 {"uahalf", s_uacons
, 2},
163 {"uaword", s_uacons
, 4},
164 {"uaxword", s_uacons
, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons
, 2},
168 {"4byte", s_uacons
, 4},
169 {"8byte", s_uacons
, 8},
170 {"register", s_register
, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars
[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars
[] = "#";
190 const char line_separator_chars
[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS
[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode
;
211 struct nlist
*nlistp
;
215 bfd_reloc_code_real_type reloc
;
218 struct sparc_it the_insn
, set_insn
;
220 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
222 /* Table of arguments to -A.
223 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
224 for this use. That table is for opcodes only. This table is for opcodes
227 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
228 v8plusa
, v9
, v9a
, v9b
, v9_64
};
230 static struct sparc_arch
{
232 const char *opcode_arch
;
233 enum sparc_arch_types arch_type
;
234 /* Default word size, as specified during configuration.
235 A value of zero means can't be used to specify default architecture. */
236 int default_arch_size
;
237 /* Allowable arg to -A? */
239 /* Extra hardware capabilities allowed. These are added to the
240 hardware capabilities associated with the opcode
244 } sparc_arch_table
[] = {
245 { "v6", "v6", v6
, 0, 1, 0, 0 },
246 { "v7", "v7", v7
, 0, 1, 0, 0 },
247 { "v8", "v8", v8
, 32, 1, 0, 0 },
248 { "v8a", "v8", v8
, 32, 1, 0, 0 },
249 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
250 { "sparcvis", "v9a", v9
, 0, 1, 0, 0 },
251 { "sparcvis2", "v9b", v9
, 0, 1, 0, 0 },
252 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_FMAF
, 0 },
253 { "sparcima", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_IMA
, 0 },
254 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
255 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
257 { "sparc4", "v9v", v9
, 0, 1, 0, 0 },
258 { "sparc5", "v9m", v9
, 0, 1, 0, 0 },
260 { "leon", "leon", leon
, 32, 1, 0, 0 },
261 { "sparclet", "sparclet", sparclet
, 32, 1, 0, 0 },
262 { "sparclite", "sparclite", sparclite
, 32, 1, 0, 0 },
263 { "sparc86x", "sparclite", sparc86x
, 32, 1, 0, 0 },
265 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
266 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
267 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
268 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
269 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
270 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
271 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
272 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
274 { "v9", "v9", v9
, 0, 1, 0, 0 },
275 { "v9a", "v9a", v9
, 0, 1, 0, 0 },
276 { "v9b", "v9b", v9
, 0, 1, 0, 0 },
277 { "v9c", "v9c", v9
, 0, 1, 0, 0 },
278 { "v9d", "v9d", v9
, 0, 1, 0, 0 },
279 { "v9e", "v9e", v9
, 0, 1, 0, 0 },
280 { "v9v", "v9v", v9
, 0, 1, 0, 0 },
281 { "v9m", "v9m", v9
, 0, 1, 0, 0 },
283 /* This exists to allow configure.tgt to pass one
284 value to specify both the default machine and default word size. */
285 { "v9-64", "v9", v9
, 64, 0, 0, 0 },
286 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
289 /* Variant of default_arch */
290 static enum sparc_arch_types default_arch_type
;
292 static struct sparc_arch
*
293 lookup_arch (const char *name
)
295 struct sparc_arch
*sa
;
297 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
298 if (strcmp (sa
->name
, name
) == 0)
300 if (sa
->name
== NULL
)
305 /* Initialize the default opcode arch and word size from the default
306 architecture name. */
309 init_default_arch (void)
311 struct sparc_arch
*sa
= lookup_arch (default_arch
);
314 || sa
->default_arch_size
== 0)
315 as_fatal (_("Invalid default architecture, broken assembler."));
317 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
318 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
319 as_fatal (_("Bad opcode table, broken assembler."));
320 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
322 default_arch_type
= sa
->arch_type
;
325 /* Called by TARGET_FORMAT. */
328 sparc_target_format (void)
330 /* We don't get a chance to initialize anything before we're called,
331 so handle that now. */
332 if (! default_init_p
)
333 init_default_arch ();
337 return "a.out-sparc-netbsd";
340 if (target_big_endian
)
341 return "a.out-sunos-big";
342 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
343 return "a.out-sunos-big";
345 return "a.out-sparc-little";
347 return "a.out-sunos-big";
358 return "coff-sparc-lynx";
365 return "elf32-sparc-vxworks";
369 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
376 * Invocation line includes a switch not recognized by the base assembler.
377 * See if it's a processor-specific option. These are:
380 * Warn on architecture bumps. See also -A.
382 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
383 * Standard 32 bit architectures.
385 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
386 * This used to only mean 64 bits, but properly specifying it
387 * complicated gcc's ASM_SPECs, so now opcode selection is
388 * specified orthogonally to word size (except when specifying
389 * the default, but that is an internal implementation detail).
390 * -Av8plus, -Av8plusa, -Av8plusb
391 * Same as -Av9{,a,b}.
392 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
393 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
395 * -xarch=v9, -xarch=v9a, -xarch=v9b
396 * Same as -Av9{,a,b} -64, for compatibility with Sun's
399 * Select the architecture and possibly the file format.
400 * Instructions or features not supported by the selected
401 * architecture cause fatal errors.
403 * The default is to start at v6, and bump the architecture up
404 * whenever an instruction is seen at a higher level. In 32 bit
405 * environments, v9 is not bumped up to, the user must pass
408 * If -bump is specified, a warning is printing when bumping to
411 * If an architecture is specified, all instructions must match
412 * that architecture. Any higher level instructions are flagged
413 * as errors. Note that in the 32 bit environment specifying
414 * -Av8plus does not automatically create a v8plus object file, a
415 * v9 insn must be seen.
417 * If both an architecture and -bump are specified, the
418 * architecture starts at the specified level, but bumps are
419 * warnings. Note that we can't set `current_architecture' to
420 * the requested level in this case: in the 32 bit environment,
421 * we still must avoid creating v8plus object files unless v9
425 * Bumping between incompatible architectures is always an
426 * error. For example, from sparclite to v9.
430 const char *md_shortopts
= "A:K:VQ:sq";
433 const char *md_shortopts
= "A:k";
435 const char *md_shortopts
= "A:";
438 struct option md_longopts
[] = {
439 #define OPTION_BUMP (OPTION_MD_BASE)
440 {"bump", no_argument
, NULL
, OPTION_BUMP
},
441 #define OPTION_SPARC (OPTION_MD_BASE + 1)
442 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
443 #define OPTION_XARCH (OPTION_MD_BASE + 2)
444 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
446 #define OPTION_32 (OPTION_MD_BASE + 3)
447 {"32", no_argument
, NULL
, OPTION_32
},
448 #define OPTION_64 (OPTION_MD_BASE + 4)
449 {"64", no_argument
, NULL
, OPTION_64
},
450 #define OPTION_TSO (OPTION_MD_BASE + 5)
451 {"TSO", no_argument
, NULL
, OPTION_TSO
},
452 #define OPTION_PSO (OPTION_MD_BASE + 6)
453 {"PSO", no_argument
, NULL
, OPTION_PSO
},
454 #define OPTION_RMO (OPTION_MD_BASE + 7)
455 {"RMO", no_argument
, NULL
, OPTION_RMO
},
457 #ifdef SPARC_BIENDIAN
458 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
459 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
460 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
461 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
463 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
464 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
465 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
466 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
468 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
469 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
470 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
471 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
473 #define OPTION_RELAX (OPTION_MD_BASE + 14)
474 {"relax", no_argument
, NULL
, OPTION_RELAX
},
475 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
476 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
477 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
478 {"dcti-couples-detect", no_argument
, NULL
, OPTION_DCTI_COUPLES_DETECT
},
479 {NULL
, no_argument
, NULL
, 0}
482 size_t md_longopts_size
= sizeof (md_longopts
);
485 md_parse_option (int c
, const char *arg
)
487 /* We don't get a chance to initialize anything before we're called,
488 so handle that now. */
489 if (! default_init_p
)
490 init_default_arch ();
496 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
501 if (!strncmp (arg
, "v9", 2))
502 md_parse_option (OPTION_64
, NULL
);
505 if (!strncmp (arg
, "v8", 2)
506 || !strncmp (arg
, "v7", 2)
507 || !strncmp (arg
, "v6", 2)
508 || !strcmp (arg
, "sparclet")
509 || !strcmp (arg
, "sparclite")
510 || !strcmp (arg
, "sparc86x"))
511 md_parse_option (OPTION_32
, NULL
);
518 struct sparc_arch
*sa
;
519 enum sparc_opcode_arch_val opcode_arch
;
521 sa
= lookup_arch (arg
);
523 || ! sa
->user_option_p
)
525 if (c
== OPTION_XARCH
)
526 as_bad (_("invalid architecture -xarch=%s"), arg
);
528 as_bad (_("invalid architecture -A%s"), arg
);
532 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
533 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
534 as_fatal (_("Bad opcode table, broken assembler."));
536 if (!architecture_requested
537 || opcode_arch
> max_architecture
)
538 max_architecture
= opcode_arch
;
540 /* The allowed hardware capabilities are the implied by the
541 opcodes arch plus any extra capabilities defined in the GAS
545 | (((bfd_uint64_t
) sparc_opcode_archs
[opcode_arch
].hwcaps2
) << 32)
546 | (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32)
547 | sparc_opcode_archs
[opcode_arch
].hwcaps
548 | sa
->hwcap_allowed
);
549 architecture_requested
= 1;
554 /* Ignore -sparc, used by SunOS make default .s.o rule. */
557 case OPTION_ENFORCE_ALIGNED_DATA
:
558 enforce_aligned_data
= 1;
561 #ifdef SPARC_BIENDIAN
562 case OPTION_LITTLE_ENDIAN
:
563 target_big_endian
= 0;
564 if (default_arch_type
!= sparclet
)
565 as_fatal ("This target does not support -EL");
567 case OPTION_LITTLE_ENDIAN_DATA
:
568 target_little_endian_data
= 1;
569 target_big_endian
= 0;
570 if (default_arch_type
!= sparc86x
571 && default_arch_type
!= v9
)
572 as_fatal ("This target does not support --little-endian-data");
574 case OPTION_BIG_ENDIAN
:
575 target_big_endian
= 1;
589 const char **list
, **l
;
591 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
592 list
= bfd_target_list ();
593 for (l
= list
; *l
!= NULL
; l
++)
595 if (sparc_arch_size
== 32)
597 if (CONST_STRNEQ (*l
, "elf32-sparc"))
602 if (CONST_STRNEQ (*l
, "elf64-sparc"))
607 as_fatal (_("No compiled in support for %d bit object file format"),
611 if (sparc_arch_size
== 64
612 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
613 max_architecture
= SPARC_OPCODE_ARCH_V9
;
618 sparc_memory_model
= MM_TSO
;
622 sparc_memory_model
= MM_PSO
;
626 sparc_memory_model
= MM_RMO
;
634 /* Qy - do emit .comment
635 Qn - do not emit .comment. */
639 /* Use .stab instead of .stab.excl. */
643 /* quick -- Native assembler does fewer checks. */
647 if (strcmp (arg
, "PIC") != 0)
648 as_warn (_("Unrecognized option following -K"));
653 case OPTION_NO_UNDECLARED_REGS
:
654 no_undeclared_regs
= 1;
657 case OPTION_UNDECLARED_REGS
:
658 no_undeclared_regs
= 0;
666 case OPTION_NO_RELAX
:
670 case OPTION_DCTI_COUPLES_DETECT
:
671 dcti_couples_detect
= 1;
682 md_show_usage (FILE *stream
)
684 const struct sparc_arch
*arch
;
687 /* We don't get a chance to initialize anything before we're called,
688 so handle that now. */
689 if (! default_init_p
)
690 init_default_arch ();
692 fprintf (stream
, _("SPARC options:\n"));
694 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
696 if (!arch
->user_option_p
)
698 if (arch
!= &sparc_arch_table
[0])
699 fprintf (stream
, " | ");
700 if (column
+ strlen (arch
->name
) > 70)
703 fputc ('\n', stream
);
705 column
+= 5 + 2 + strlen (arch
->name
);
706 fprintf (stream
, "-A%s", arch
->name
);
708 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
710 if (!arch
->user_option_p
)
712 fprintf (stream
, " | ");
713 if (column
+ strlen (arch
->name
) > 65)
716 fputc ('\n', stream
);
718 column
+= 5 + 7 + strlen (arch
->name
);
719 fprintf (stream
, "-xarch=%s", arch
->name
);
721 fprintf (stream
, _("\n\
722 specify variant of SPARC architecture\n\
723 -bump warn when assembler switches architectures\n\
725 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
726 -relax relax jumps and branches (default)\n\
727 -no-relax avoid changing any jumps and branches\n"));
729 fprintf (stream
, _("\
730 -k generate PIC\n"));
733 fprintf (stream
, _("\
734 -32 create 32 bit object file\n\
735 -64 create 64 bit object file\n"));
736 fprintf (stream
, _("\
737 [default is %d]\n"), default_arch_size
);
738 fprintf (stream
, _("\
739 -TSO use Total Store Ordering\n\
740 -PSO use Partial Store Ordering\n\
741 -RMO use Relaxed Memory Ordering\n"));
742 fprintf (stream
, _("\
743 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
744 fprintf (stream
, _("\
745 -KPIC generate PIC\n\
746 -V print assembler version number\n\
747 -undeclared-regs ignore application global register usage without\n\
748 appropriate .register directive (default)\n\
749 -no-undeclared-regs force error on application global register usage\n\
750 without appropriate .register directive\n\
751 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
756 #ifdef SPARC_BIENDIAN
757 fprintf (stream
, _("\
758 -EL generate code for a little endian machine\n\
759 -EB generate code for a big endian machine\n\
760 --little-endian-data generate code for a machine having big endian\n\
761 instructions and little endian data.\n"));
765 /* Native operand size opcode translation. */
771 } native_op_table
[] =
773 {"ldn", "ld", "ldx"},
774 {"ldna", "lda", "ldxa"},
775 {"stn", "st", "stx"},
776 {"stna", "sta", "stxa"},
777 {"slln", "sll", "sllx"},
778 {"srln", "srl", "srlx"},
779 {"sran", "sra", "srax"},
780 {"casn", "cas", "casx"},
781 {"casna", "casa", "casxa"},
782 {"clrn", "clr", "clrx"},
786 /* sparc64 privileged and hyperprivileged registers. */
788 struct priv_reg_entry
794 struct priv_reg_entry priv_reg_table
[] =
815 {NULL
, -1}, /* End marker. */
818 struct priv_reg_entry hpriv_reg_table
[] =
828 {"hstick_offset", 28},
829 {"hstick_enable", 29},
831 {NULL
, -1}, /* End marker. */
834 /* v9a or later specific ancillary state registers. */
836 struct priv_reg_entry v9a_asr_table
[] =
839 {"sys_tick_cmpr", 25},
843 {"softint_clear", 21},
854 {"clear_softint", 21},
855 {NULL
, -1}, /* End marker. */
859 cmp_reg_entry (const void *parg
, const void *qarg
)
861 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
862 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
864 if (p
->name
== q
->name
)
866 else if (p
->name
== NULL
)
868 else if (q
->name
== NULL
)
871 return strcmp (q
->name
, p
->name
);
874 /* sparc %-pseudo-operations. */
877 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
878 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
880 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
881 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
883 instruction. (Generally they can appear
884 anywhere an immediate operand is
888 /* The name as it appears in assembler. */
890 /* The reloc this pseudo-op translates to. */
891 bfd_reloc_code_real_type reloc
;
892 /* Flags. See F_POP_* above. */
896 struct pop_entry pop_table
[] =
898 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
899 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
900 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
901 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
902 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
903 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
904 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
905 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
906 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
907 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
908 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
909 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
910 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
911 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
912 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
913 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
914 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
915 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
916 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
917 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
918 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
919 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
920 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
921 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
922 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
923 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
924 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
925 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
926 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
927 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
928 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
929 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
930 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
931 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
932 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
933 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
934 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
937 /* Table of %-names that can appear in a sparc assembly program. This
938 table is initialized in md_begin and contains entries for each
939 privileged/hyperprivileged/alternate register and %-pseudo-op. */
952 enum perc_entry_type type
;
953 /* Name of the %-entity. */
957 /* Value. Either a pop or a reg depending on type.*/
960 struct pop_entry
*pop
;
961 struct priv_reg_entry
*reg
;
965 #define NUM_PERC_ENTRIES \
966 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
967 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
968 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
969 + ARRAY_SIZE (pop_table) \
972 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
975 cmp_perc_entry (const void *parg
, const void *qarg
)
977 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
978 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
980 if (p
->name
== q
->name
)
982 else if (p
->name
== NULL
)
984 else if (q
->name
== NULL
)
987 return strcmp (q
->name
, p
->name
);
990 /* This function is called once, at assembler startup time. It should
991 set up all the tables, etc. that the MD part of the assembler will
997 const char *retval
= NULL
;
1001 /* We don't get a chance to initialize anything before md_parse_option
1002 is called, and it may not be called, so handle default initialization
1003 now if not already done. */
1004 if (! default_init_p
)
1005 init_default_arch ();
1007 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
1008 op_hash
= hash_new ();
1010 while (i
< (unsigned int) sparc_num_opcodes
)
1012 const char *name
= sparc_opcodes
[i
].name
;
1013 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
1016 as_bad (_("Internal error: can't hash `%s': %s\n"),
1017 sparc_opcodes
[i
].name
, retval
);
1022 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
1024 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1025 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
1030 while (i
< (unsigned int) sparc_num_opcodes
1031 && !strcmp (sparc_opcodes
[i
].name
, name
));
1034 for (i
= 0; native_op_table
[i
].name
; i
++)
1036 const struct sparc_opcode
*insn
;
1037 const char *name
= ((sparc_arch_size
== 32)
1038 ? native_op_table
[i
].name32
1039 : native_op_table
[i
].name64
);
1040 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
1043 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1044 name
, native_op_table
[i
].name
);
1049 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1053 as_bad (_("Internal error: can't hash `%s': %s\n"),
1054 sparc_opcodes
[i
].name
, retval
);
1061 as_fatal (_("Broken assembler. No assembly attempted."));
1063 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1064 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1065 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1066 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1067 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1068 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1070 /* If -bump, record the architecture level at which we start issuing
1071 warnings. The behaviour is different depending upon whether an
1072 architecture was explicitly specified. If it wasn't, we issue warnings
1073 for all upwards bumps. If it was, we don't start issuing warnings until
1074 we need to bump beyond the requested architecture or when we bump between
1075 conflicting architectures. */
1078 && architecture_requested
)
1080 /* `max_architecture' records the requested architecture.
1081 Issue warnings if we go above it. */
1082 warn_after_architecture
= max_architecture
;
1085 /* Find the highest architecture level that doesn't conflict with
1086 the requested one. */
1089 || !architecture_requested
)
1091 enum sparc_opcode_arch_val current_max_architecture
1094 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1095 max_architecture
> warn_after_architecture
;
1097 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1098 current_max_architecture
))
1102 /* Prepare the tables of %-pseudo-ops. */
1104 struct priv_reg_entry
*reg_tables
[]
1105 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1106 struct priv_reg_entry
**reg_table
;
1109 /* Add registers. */
1110 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1112 struct priv_reg_entry
*reg
;
1113 for (reg
= *reg_table
; reg
->name
; reg
++)
1115 struct perc_entry
*p
= &perc_table
[entry
++];
1116 p
->type
= perc_entry_reg
;
1117 p
->name
= reg
->name
;
1118 p
->len
= strlen (reg
->name
);
1123 /* Add %-pseudo-ops. */
1124 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1126 struct perc_entry
*p
= &perc_table
[entry
++];
1127 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1128 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1129 p
->name
= pop_table
[i
].name
;
1130 p
->len
= strlen (pop_table
[i
].name
);
1131 p
->pop
= &pop_table
[i
];
1134 /* Last entry is the sentinel. */
1135 perc_table
[entry
].type
= perc_entry_none
;
1137 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1138 sizeof (perc_table
[0]), cmp_perc_entry
);
1143 /* Called after all assembly has been done. */
1148 unsigned long mach
= bfd_mach_sparc
;
1149 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1150 int hwcaps
, hwcaps2
;
1153 if (sparc_arch_size
== 64)
1154 switch (current_architecture
)
1156 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1157 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1158 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1159 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1160 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1161 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1162 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1163 default: mach
= bfd_mach_sparc_v9
; break;
1166 switch (current_architecture
)
1168 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1169 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1170 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1171 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1172 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1173 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1174 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1175 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1176 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1177 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1178 be but for now it is (since that's the way it's always been
1182 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1184 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1185 hwcaps
= hwcap_seen
& U0xffffffff
;
1186 hwcaps2
= hwcap_seen
>> 32;
1189 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1191 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1195 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1198 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1202 /* Sign-extend the value from the architecture word size, so that
1203 0xffffffff is always considered -1 on sparc32. */
1204 if (sparc_arch_size
== 32)
1206 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1207 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1216 /* Return non-zero if VAL is in the range 0 to MAX. */
1219 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1226 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1227 (e.g. -15 to +31). */
1230 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1236 if (val
< ~(max
>> 1))
1242 sparc_ffs (unsigned int mask
)
1249 for (i
= 0; (mask
& 1) == 0; ++i
)
1254 /* Implement big shift right. */
1256 BSR (bfd_vma val
, int amount
)
1258 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1259 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1260 return val
>> amount
;
1263 /* For communication between sparc_ip and get_expression. */
1264 static char *expr_end
;
1266 /* Values for `special_case'.
1267 Instructions that require weird handling because they're longer than
1269 #define SPECIAL_CASE_NONE 0
1270 #define SPECIAL_CASE_SET 1
1271 #define SPECIAL_CASE_SETSW 2
1272 #define SPECIAL_CASE_SETX 3
1273 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1274 #define SPECIAL_CASE_FDIV 4
1276 /* Bit masks of various insns. */
1277 #define NOP_INSN 0x01000000
1278 #define OR_INSN 0x80100000
1279 #define XOR_INSN 0x80180000
1280 #define FMOVS_INSN 0x81A00020
1281 #define SETHI_INSN 0x01000000
1282 #define SLLX_INSN 0x81281000
1283 #define SRA_INSN 0x81380000
1285 /* The last instruction to be assembled. */
1286 static const struct sparc_opcode
*last_insn
;
1287 /* The assembled opcode of `last_insn'. */
1288 static unsigned long last_opcode
;
1290 /* Handle the set and setuw synthetic instructions. */
1293 synthetize_setuw (const struct sparc_opcode
*insn
)
1295 int need_hi22_p
= 0;
1296 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1298 if (the_insn
.exp
.X_op
== O_constant
)
1300 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1302 if (sizeof (offsetT
) > 4
1303 && (the_insn
.exp
.X_add_number
< 0
1304 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1305 as_warn (_("set: number not in 0..4294967295 range"));
1309 if (sizeof (offsetT
) > 4
1310 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1311 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1312 as_warn (_("set: number not in -2147483648..4294967295 range"));
1313 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1317 /* See if operand is absolute and small; skip sethi if so. */
1318 if (the_insn
.exp
.X_op
!= O_constant
1319 || the_insn
.exp
.X_add_number
>= (1 << 12)
1320 || the_insn
.exp
.X_add_number
< -(1 << 12))
1322 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1323 | ((the_insn
.exp
.X_add_number
>> 10)
1324 & (the_insn
.exp
.X_op
== O_constant
1326 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1327 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1328 output_insn (insn
, &the_insn
);
1332 /* See if operand has no low-order bits; skip OR if so. */
1333 if (the_insn
.exp
.X_op
!= O_constant
1334 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1337 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1339 | (the_insn
.exp
.X_add_number
1340 & (the_insn
.exp
.X_op
!= O_constant
1341 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1342 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1343 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1344 output_insn (insn
, &the_insn
);
1348 /* Handle the setsw synthetic instruction. */
1351 synthetize_setsw (const struct sparc_opcode
*insn
)
1355 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1357 if (the_insn
.exp
.X_op
!= O_constant
)
1359 synthetize_setuw (insn
);
1361 /* Need to sign extend it. */
1362 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1363 the_insn
.reloc
= BFD_RELOC_NONE
;
1364 output_insn (insn
, &the_insn
);
1368 if (sizeof (offsetT
) > 4
1369 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1370 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1371 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1373 low32
= the_insn
.exp
.X_add_number
;
1377 synthetize_setuw (insn
);
1383 the_insn
.reloc
= BFD_RELOC_NONE
;
1384 /* See if operand is absolute and small; skip sethi if so. */
1385 if (low32
< -(1 << 12))
1387 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1388 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1389 output_insn (insn
, &the_insn
);
1390 low32
= 0x1c00 | (low32
& 0x3ff);
1391 opc
= RS1 (rd
) | XOR_INSN
;
1394 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1395 | (low32
& 0x1fff));
1396 output_insn (insn
, &the_insn
);
1399 /* Handle the setx synthetic instruction. */
1402 synthetize_setx (const struct sparc_opcode
*insn
)
1404 int upper32
, lower32
;
1405 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1406 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1408 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1409 int need_xor10_p
= 0;
1411 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1412 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1413 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1416 upper_dstreg
= tmpreg
;
1417 /* The tmp reg should not be the dst reg. */
1418 if (tmpreg
== dstreg
)
1419 as_warn (_("setx: temporary register same as destination register"));
1421 /* ??? Obviously there are other optimizations we can do
1422 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1423 doing some of these. Later. If you do change things, try to
1424 change all of this to be table driven as well. */
1425 /* What to output depends on the number if it's constant.
1426 Compute that first, then output what we've decided upon. */
1427 if (the_insn
.exp
.X_op
!= O_constant
)
1429 if (sparc_arch_size
== 32)
1431 /* When arch size is 32, we want setx to be equivalent
1432 to setuw for anything but constants. */
1433 the_insn
.exp
.X_add_number
&= 0xffffffff;
1434 synthetize_setuw (insn
);
1437 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1443 /* Reset X_add_number, we've extracted it as upper32/lower32.
1444 Otherwise fixup_segment will complain about not being able to
1445 write an 8 byte number in a 4 byte field. */
1446 the_insn
.exp
.X_add_number
= 0;
1448 /* Only need hh22 if `or' insn can't handle constant. */
1449 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1452 /* Does bottom part (after sethi) have bits? */
1453 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1454 /* No hh22, but does upper32 still have bits we can't set
1456 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1459 /* If the lower half is all zero, we build the upper half directly
1460 into the dst reg. */
1462 /* Need lower half if number is zero or 0xffffffff00000000. */
1463 || (! need_hh22_p
&& ! need_hm10_p
))
1465 /* No need for sethi if `or' insn can handle constant. */
1466 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1467 /* Note that we can't use a negative constant in the `or'
1468 insn unless the upper 32 bits are all ones. */
1469 || (lower32
< 0 && upper32
!= -1)
1470 || (lower32
>= 0 && upper32
== -1))
1473 if (need_hi22_p
&& upper32
== -1)
1476 /* Does bottom part (after sethi) have bits? */
1477 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1479 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1480 /* Need `or' if we didn't set anything else. */
1481 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1485 /* Output directly to dst reg if lower 32 bits are all zero. */
1486 upper_dstreg
= dstreg
;
1489 if (!upper_dstreg
&& dstreg
)
1490 as_warn (_("setx: illegal temporary register g0"));
1494 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1495 | ((upper32
>> 10) & 0x3fffff));
1496 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1497 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1498 output_insn (insn
, &the_insn
);
1503 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1504 | (((need_xor10_p
? ~lower32
: lower32
)
1505 >> 10) & 0x3fffff));
1506 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1507 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1508 output_insn (insn
, &the_insn
);
1513 the_insn
.opcode
= (OR_INSN
1514 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1517 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1518 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1519 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1520 output_insn (insn
, &the_insn
);
1525 /* FIXME: One nice optimization to do here is to OR the low part
1526 with the highpart if hi22 isn't needed and the low part is
1528 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1531 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1532 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1533 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1534 output_insn (insn
, &the_insn
);
1537 /* If we needed to build the upper part, shift it into place. */
1538 if (need_hh22_p
|| need_hm10_p
)
1540 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1542 the_insn
.reloc
= BFD_RELOC_NONE
;
1543 output_insn (insn
, &the_insn
);
1546 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1549 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1550 | 0x1c00 | (lower32
& 0x3ff));
1551 the_insn
.reloc
= BFD_RELOC_NONE
;
1552 output_insn (insn
, &the_insn
);
1555 /* If we needed to build both upper and lower parts, OR them together. */
1556 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1558 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1560 the_insn
.reloc
= BFD_RELOC_NONE
;
1561 output_insn (insn
, &the_insn
);
1565 /* Main entry point to assemble one instruction. */
1568 md_assemble (char *str
)
1570 const struct sparc_opcode
*insn
;
1574 special_case
= sparc_ip (str
, &insn
);
1578 /* Certain instructions may not appear on delay slots. Check for
1579 these situations. */
1580 if (last_insn
!= NULL
1581 && (last_insn
->flags
& F_DELAYED
) != 0)
1583 /* Before SPARC V9 the effect of having a delayed branch
1584 instruction in the delay slot of a conditional delayed branch
1587 In SPARC V9 DCTI couples are well defined.
1589 However, starting with the UltraSPARC Architecture 2005, DCTI
1590 couples (of all kind) are deprecated and should not be used,
1591 as they may be slow or behave differently to what the
1592 programmer expects. */
1593 if (dcti_couples_detect
1594 && (insn
->flags
& F_DELAYED
) != 0
1595 && ((max_architecture
< SPARC_OPCODE_ARCH_V9
1596 && (last_insn
->flags
& F_CONDBR
) != 0)
1597 || max_architecture
>= SPARC_OPCODE_ARCH_V9C
))
1598 as_warn (_("unpredictable DCTI couple"));
1601 /* We warn about attempts to put a floating point branch in a
1602 delay slot, unless the delay slot has been annulled. */
1603 if ((insn
->flags
& F_FBR
) != 0
1604 /* ??? This test isn't completely accurate. We assume anything with
1605 F_{UNBR,CONDBR,FBR} set is annullable. */
1606 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1607 || (last_opcode
& ANNUL
) == 0))
1608 as_warn (_("FP branch in delay slot"));
1611 /* SPARC before v9 requires a nop instruction between a floating
1612 point instruction and a floating point branch. We insert one
1613 automatically, with a warning. */
1614 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1615 && last_insn
!= NULL
1616 && (insn
->flags
& F_FBR
) != 0
1617 && (last_insn
->flags
& F_FLOAT
) != 0)
1619 struct sparc_it nop_insn
;
1621 nop_insn
.opcode
= NOP_INSN
;
1622 nop_insn
.reloc
= BFD_RELOC_NONE
;
1623 output_insn (insn
, &nop_insn
);
1624 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1627 switch (special_case
)
1629 case SPECIAL_CASE_NONE
:
1631 output_insn (insn
, &the_insn
);
1634 case SPECIAL_CASE_SETSW
:
1635 synthetize_setsw (insn
);
1638 case SPECIAL_CASE_SET
:
1639 synthetize_setuw (insn
);
1642 case SPECIAL_CASE_SETX
:
1643 synthetize_setx (insn
);
1646 case SPECIAL_CASE_FDIV
:
1648 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1650 output_insn (insn
, &the_insn
);
1652 /* According to information leaked from Sun, the "fdiv" instructions
1653 on early SPARC machines would produce incorrect results sometimes.
1654 The workaround is to add an fmovs of the destination register to
1655 itself just after the instruction. This was true on machines
1656 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1657 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1658 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1659 output_insn (insn
, &the_insn
);
1664 as_fatal (_("failed special case insn sanity check"));
1669 get_hwcap_name (bfd_uint64_t mask
)
1671 if (mask
& HWCAP_MUL32
)
1673 if (mask
& HWCAP_DIV32
)
1675 if (mask
& HWCAP_FSMULD
)
1677 if (mask
& HWCAP_V8PLUS
)
1679 if (mask
& HWCAP_POPC
)
1681 if (mask
& HWCAP_VIS
)
1683 if (mask
& HWCAP_VIS2
)
1685 if (mask
& HWCAP_ASI_BLK_INIT
)
1686 return "ASIBlkInit";
1687 if (mask
& HWCAP_FMAF
)
1689 if (mask
& HWCAP_VIS3
)
1691 if (mask
& HWCAP_HPC
)
1693 if (mask
& HWCAP_RANDOM
)
1695 if (mask
& HWCAP_TRANS
)
1697 if (mask
& HWCAP_FJFMAU
)
1699 if (mask
& HWCAP_IMA
)
1701 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1703 if (mask
& HWCAP_AES
)
1705 if (mask
& HWCAP_DES
)
1707 if (mask
& HWCAP_KASUMI
)
1709 if (mask
& HWCAP_CAMELLIA
)
1711 if (mask
& HWCAP_MD5
)
1713 if (mask
& HWCAP_SHA1
)
1715 if (mask
& HWCAP_SHA256
)
1717 if (mask
& HWCAP_SHA512
)
1719 if (mask
& HWCAP_MPMUL
)
1721 if (mask
& HWCAP_MONT
)
1723 if (mask
& HWCAP_PAUSE
)
1725 if (mask
& HWCAP_CBCOND
)
1727 if (mask
& HWCAP_CRC32C
)
1731 if (mask
& HWCAP2_FJATHPLUS
)
1733 if (mask
& HWCAP2_VIS3B
)
1735 if (mask
& HWCAP2_ADP
)
1737 if (mask
& HWCAP2_SPARC5
)
1739 if (mask
& HWCAP2_MWAIT
)
1741 if (mask
& HWCAP2_XMPMUL
)
1743 if (mask
& HWCAP2_XMONT
)
1745 if (mask
& HWCAP2_NSEC
)
1751 /* Subroutine of md_assemble to do the actual parsing. */
1754 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1756 const char *error_message
= "";
1760 const struct sparc_opcode
*insn
;
1762 unsigned long opcode
;
1763 unsigned int mask
= 0;
1767 int special_case
= SPECIAL_CASE_NONE
;
1768 const sparc_asi
*sasi
= NULL
;
1775 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1792 as_bad (_("Unknown opcode: `%s'"), str
);
1794 return special_case
;
1796 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1800 as_bad (_("Unknown opcode: `%s'"), str
);
1801 return special_case
;
1811 opcode
= insn
->match
;
1812 memset (&the_insn
, '\0', sizeof (the_insn
));
1813 the_insn
.reloc
= BFD_RELOC_NONE
;
1816 /* Build the opcode, checking as we go to make sure that the
1818 for (args
= insn
->args
;; ++args
)
1826 /* Parse a series of masks. */
1833 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1836 error_message
= _(": invalid membar mask name");
1842 if (*s
== '|' || *s
== '+')
1850 if (! parse_const_expr_arg (&s
, &kmask
))
1852 error_message
= _(": invalid membar mask expression");
1855 if (kmask
< 0 || kmask
> 127)
1857 error_message
= _(": invalid membar mask number");
1862 opcode
|= MEMBAR (kmask
);
1870 if (! parse_const_expr_arg (&s
, &smask
))
1872 error_message
= _(": invalid siam mode expression");
1875 if (smask
< 0 || smask
> 7)
1877 error_message
= _(": invalid siam mode number");
1888 /* Parse a prefetch function. */
1891 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1893 error_message
= _(": invalid prefetch function name");
1899 if (! parse_const_expr_arg (&s
, &fcn
))
1901 error_message
= _(": invalid prefetch function expression");
1904 if (fcn
< 0 || fcn
> 31)
1906 error_message
= _(": invalid prefetch function number");
1916 /* Parse a sparc64 privileged register. */
1919 struct priv_reg_entry
*p
;
1920 unsigned int len
= 9999999; /* Init to make gcc happy. */
1923 for (p
= priv_reg_table
; p
->name
; p
++)
1924 if (p
->name
[0] == s
[0])
1926 len
= strlen (p
->name
);
1927 if (strncmp (p
->name
, s
, len
) == 0)
1933 error_message
= _(": unrecognizable privileged register");
1937 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1939 error_message
= _(": unrecognizable privileged register");
1948 error_message
= _(": unrecognizable privileged register");
1954 /* Parse a sparc64 hyperprivileged register. */
1957 struct priv_reg_entry
*p
;
1958 unsigned int len
= 9999999; /* Init to make gcc happy. */
1961 for (p
= hpriv_reg_table
; p
->name
; p
++)
1962 if (p
->name
[0] == s
[0])
1964 len
= strlen (p
->name
);
1965 if (strncmp (p
->name
, s
, len
) == 0)
1971 error_message
= _(": unrecognizable hyperprivileged register");
1975 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1977 error_message
= _(": unrecognizable hyperprivileged register");
1986 error_message
= _(": unrecognizable hyperprivileged register");
1992 /* Parse a v9a or later ancillary state register. */
1995 struct priv_reg_entry
*p
;
1996 unsigned int len
= 9999999; /* Init to make gcc happy. */
1999 for (p
= v9a_asr_table
; p
->name
; p
++)
2000 if (p
->name
[0] == s
[0])
2002 len
= strlen (p
->name
);
2003 if (strncmp (p
->name
, s
, len
) == 0)
2009 error_message
= _(": unrecognizable ancillary state register");
2013 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
2015 error_message
= _(": unrecognizable ancillary state register");
2024 error_message
= _(": unrecognizable ancillary state register");
2030 if (strncmp (s
, "%asr", 4) == 0)
2038 while (ISDIGIT (*s
))
2040 num
= num
* 10 + *s
- '0';
2044 /* We used to check here for the asr number to
2045 be between 16 and 31 in V9 and later, as
2046 mandated by the section C.1.1 "Register
2047 Names" in the SPARC spec. However, we
2048 decided to remove this restriction as a) it
2049 introduces problems when new V9 asr registers
2050 are introduced, b) the Solaris assembler
2051 doesn't implement this restriction and c) the
2052 restriction will go away in future revisions
2053 of the Oracle SPARC Architecture. */
2055 if (num
< 0 || 31 < num
)
2057 error_message
= _(": asr number must be between 0 and 31");
2061 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2066 error_message
= _(": expecting %asrN");
2073 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2077 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2083 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2088 if (s
[0] == '0' && s
[1] == 'x')
2091 while (ISXDIGIT (*s
))
2094 num
|= hex_value (*s
);
2100 while (ISDIGIT (*s
))
2102 num
= num
* 10 + *s
- '0';
2106 if (num
< 0 || num
> 31)
2108 error_message
= _(": crypto immediate must be between 0 and 31");
2112 opcode
|= RS3 (num
);
2117 error_message
= _(": expecting crypto immediate");
2122 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2123 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2124 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2126 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2127 /* These fields are unsigned, but for upward compatibility,
2128 allow negative values as well. */
2132 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2133 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2134 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2136 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2137 /* These fields are unsigned, but for upward compatibility,
2138 allow negative values as well. */
2142 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2147 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2152 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2157 if (*s
== 'p' && s
[1] == 'n')
2165 if (*s
== 'p' && s
[1] == 't')
2177 if ((strncmp (s
, "%icc", 4) == 0)
2178 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2190 if ((strncmp (s
, "%xcc", 4) == 0)
2191 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2203 if (strncmp (s
, "%fcc0", 5) == 0)
2215 if (strncmp (s
, "%fcc1", 5) == 0)
2227 if (strncmp (s
, "%fcc2", 5) == 0)
2239 if (strncmp (s
, "%fcc3", 5) == 0)
2247 if (strncmp (s
, "%pc", 3) == 0)
2255 if (strncmp (s
, "%tick", 5) == 0)
2262 case '\0': /* End of args. */
2263 if (s
[0] == ',' && s
[1] == '%')
2267 const struct perc_entry
*p
;
2269 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2270 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2271 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2273 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2276 if (s
[p
->len
+ 2] != '(')
2278 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2279 return special_case
;
2282 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2283 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2285 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2287 return special_case
;
2290 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2291 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2292 || the_insn
.exp
.X_add_number
!= 0
2293 || the_insn
.exp
.X_add_symbol
2294 != symbol_find_or_make ("__tls_get_addr")))
2296 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2298 return special_case
;
2301 the_insn
.reloc
= p
->pop
->reloc
;
2302 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2305 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2308 else if (*s1
== ')')
2317 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2318 return special_case
;
2322 (void) get_expression (s
);
2342 case '[': /* These must match exactly. */
2350 case '#': /* Must be at least one digit. */
2353 while (ISDIGIT (*s
))
2361 case 'C': /* Coprocessor state register. */
2362 if (strncmp (s
, "%csr", 4) == 0)
2369 case 'b': /* Next operand is a coprocessor register. */
2372 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2377 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2391 opcode
|= mask
<< 14;
2399 opcode
|= mask
<< 25;
2405 case 'r': /* next operand must be a register */
2415 case 'f': /* frame pointer */
2423 case 'g': /* global register */
2432 case 'i': /* in register */
2436 mask
= c
- '0' + 24;
2441 case 'l': /* local register */
2445 mask
= (c
- '0' + 16);
2450 case 'o': /* out register */
2454 mask
= (c
- '0' + 8);
2459 case 's': /* stack pointer */
2467 case 'r': /* any register */
2468 if (!ISDIGIT ((c
= *s
++)))
2485 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2501 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2502 && no_undeclared_regs
&& ! globals
[mask
])
2503 as_bad (_("detected global register use not covered by .register pseudo-op"));
2505 /* Got the register, now figure out where
2506 it goes in the opcode. */
2510 opcode
|= mask
<< 14;
2518 opcode
|= mask
<< 25;
2522 opcode
|= (mask
<< 25) | (mask
<< 14);
2526 opcode
|= (mask
<< 25) | (mask
<< 0);
2532 case 'e': /* next operand is a floating point register */
2551 && ((format
= *s
) == 'f'
2556 for (mask
= 0; ISDIGIT (*s
); ++s
)
2558 mask
= 10 * mask
+ (*s
- '0');
2559 } /* read the number */
2568 /* register must be even numbered */
2578 /* register must be multiple of 4 */
2584 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2585 error_message
= _(": There are only 64 f registers; [0-63]");
2587 error_message
= _(": There are only 32 f registers; [0-31]");
2590 else if (mask
>= 32)
2592 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2594 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2597 = _(": There are only 32 single precision f registers; [0-31]");
2601 mask
-= 31; /* wrap high bit */
2605 error_message
= _(": There are only 32 f registers; [0-31]");
2613 } /* if not an 'f' register. */
2615 if (*args
== '}' && mask
!= RS2 (opcode
))
2618 = _(": Instruction requires frs2 and frsd must be the same register");
2627 opcode
|= RS1 (mask
);
2633 opcode
|= RS2 (mask
);
2638 opcode
|= RS3 (mask
);
2645 opcode
|= RD (mask
);
2654 if (strncmp (s
, "%fsr", 4) == 0)
2662 if (strncmp (s
, "%efsr", 5) == 0)
2669 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2670 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2673 case 'l': /* 22 bit PC relative immediate */
2674 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2678 case 'L': /* 30 bit immediate */
2679 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2684 case 'n': /* 22 bit immediate */
2685 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2688 case 'i': /* 13 bit immediate */
2689 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2699 const char *op_arg
= NULL
;
2700 static expressionS op_exp
;
2701 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2703 /* Check for %hi, etc. */
2706 const struct perc_entry
*p
;
2708 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2709 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2710 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2712 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2715 if (s
[p
->len
+ 1] != '(')
2717 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2718 return special_case
;
2722 the_insn
.reloc
= p
->pop
->reloc
;
2724 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2727 /* Note that if the get_expression() fails, we will still
2728 have created U entries in the symbol table for the
2729 'symbols' in the input string. Try not to create U
2730 symbols for registers, etc. */
2732 /* This stuff checks to see if the expression ends in
2733 +%reg. If it does, it removes the register from
2734 the expression, and re-sets 's' to point to the
2741 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2744 else if (*s1
== ')')
2753 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2754 return special_case
;
2758 (void) get_expression (s
);
2762 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2763 return special_case
;
2766 if (*s
== ',' || *s
== ']' || !*s
)
2768 if (*s
!= '+' && *s
!= '-')
2770 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2771 return special_case
;
2775 op_exp
= the_insn
.exp
;
2776 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2779 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2782 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2784 if (s1
[-2] == '%' && s1
[-3] == '+')
2786 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2788 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2795 if (op_arg
&& s1
== s
+ 1)
2796 the_insn
.exp
.X_op
= O_absent
;
2798 (void) get_expression (s
);
2810 (void) get_expression (s
);
2818 the_insn
.exp2
= the_insn
.exp
;
2819 the_insn
.exp
= op_exp
;
2820 if (the_insn
.exp2
.X_op
== O_absent
)
2821 the_insn
.exp2
.X_op
= O_illegal
;
2822 else if (the_insn
.exp
.X_op
== O_absent
)
2824 the_insn
.exp
= the_insn
.exp2
;
2825 the_insn
.exp2
.X_op
= O_illegal
;
2827 else if (the_insn
.exp
.X_op
== O_constant
)
2829 valueT val
= the_insn
.exp
.X_add_number
;
2830 switch (the_insn
.reloc
)
2835 case BFD_RELOC_SPARC_HH22
:
2836 val
= BSR (val
, 32);
2839 case BFD_RELOC_SPARC_LM22
:
2840 case BFD_RELOC_HI22
:
2841 val
= (val
>> 10) & 0x3fffff;
2844 case BFD_RELOC_SPARC_HM10
:
2845 val
= BSR (val
, 32);
2848 case BFD_RELOC_LO10
:
2852 case BFD_RELOC_SPARC_H34
:
2857 case BFD_RELOC_SPARC_H44
:
2862 case BFD_RELOC_SPARC_M44
:
2867 case BFD_RELOC_SPARC_L44
:
2871 case BFD_RELOC_SPARC_HIX22
:
2873 val
= (val
>> 10) & 0x3fffff;
2876 case BFD_RELOC_SPARC_LOX10
:
2877 val
= (val
& 0x3ff) | 0x1c00;
2880 the_insn
.exp
= the_insn
.exp2
;
2881 the_insn
.exp
.X_add_number
+= val
;
2882 the_insn
.exp2
.X_op
= O_illegal
;
2883 the_insn
.reloc
= old_reloc
;
2885 else if (the_insn
.exp2
.X_op
!= O_constant
)
2887 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2888 return special_case
;
2892 if (old_reloc
!= BFD_RELOC_SPARC13
2893 || the_insn
.reloc
!= BFD_RELOC_LO10
2894 || sparc_arch_size
!= 64
2897 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2898 return special_case
;
2900 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2904 /* Check for constants that don't require emitting a reloc. */
2905 if (the_insn
.exp
.X_op
== O_constant
2906 && the_insn
.exp
.X_add_symbol
== 0
2907 && the_insn
.exp
.X_op_symbol
== 0)
2909 /* For pc-relative call instructions, we reject
2910 constants to get better code. */
2912 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2913 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2915 error_message
= _(": PC-relative operand can't be a constant");
2919 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2920 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2922 error_message
= _(": TLS operand can't be a constant");
2926 /* Constants that won't fit are checked in md_apply_fix
2927 and bfd_install_relocation.
2928 ??? It would be preferable to install the constants
2929 into the insn here and save having to create a fixS
2930 for each one. There already exists code to handle
2931 all the various cases (e.g. in md_apply_fix and
2932 bfd_install_relocation) so duplicating all that code
2933 here isn't right. */
2935 /* This is a special case to handle cbcond instructions
2936 properly, which can need two relocations. The first
2937 one is for the 5-bit immediate field and the latter
2938 is going to be for the WDISP10 branch part. We
2939 handle the R_SPARC_5 immediate directly here so that
2940 we don't need to add support for multiple relocations
2941 in one instruction just yet. */
2942 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
2943 && ((insn
->match
& OP(0x3)) == 0))
2945 valueT val
= the_insn
.exp
.X_add_number
;
2947 the_insn
.reloc
= BFD_RELOC_NONE
;
2948 if (! in_bitfield_range (val
, 0x1f))
2950 error_message
= _(": Immediate value in cbcond is out of range.");
2953 opcode
|= val
& 0x1f;
2974 if (! parse_sparc_asi (&s
, &sasi
))
2976 error_message
= _(": invalid ASI name");
2983 if (! parse_const_expr_arg (&s
, &asi
))
2985 error_message
= _(": invalid ASI expression");
2988 if (asi
< 0 || asi
> 255)
2990 error_message
= _(": invalid ASI number");
2994 opcode
|= ASI (asi
);
2996 } /* Alternate space. */
2999 if (strncmp (s
, "%psr", 4) == 0)
3006 case 'q': /* Floating point queue. */
3007 if (strncmp (s
, "%fq", 3) == 0)
3014 case 'Q': /* Coprocessor queue. */
3015 if (strncmp (s
, "%cq", 3) == 0)
3023 if (strcmp (str
, "set") == 0
3024 || strcmp (str
, "setuw") == 0)
3026 special_case
= SPECIAL_CASE_SET
;
3029 else if (strcmp (str
, "setsw") == 0)
3031 special_case
= SPECIAL_CASE_SETSW
;
3034 else if (strcmp (str
, "setx") == 0)
3036 special_case
= SPECIAL_CASE_SETX
;
3039 else if (strncmp (str
, "fdiv", 4) == 0)
3041 special_case
= SPECIAL_CASE_FDIV
;
3047 if (strncmp (s
, "%asi", 4) != 0)
3053 if (strncmp (s
, "%fprs", 5) != 0)
3059 if (strncmp (s
, "%mcdper",7) != 0)
3065 if (strncmp (s
, "%ccr", 4) != 0)
3071 if (strncmp (s
, "%tbr", 4) != 0)
3077 if (strncmp (s
, "%wim", 4) != 0)
3084 char *push
= input_line_pointer
;
3087 input_line_pointer
= s
;
3089 if (e
.X_op
== O_constant
)
3091 int n
= e
.X_add_number
;
3092 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3093 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3095 opcode
|= e
.X_add_number
<< 5;
3098 as_bad (_("non-immediate OPF operand, ignored"));
3099 s
= input_line_pointer
;
3100 input_line_pointer
= push
;
3105 if (strncmp (s
, "%y", 2) != 0)
3113 /* Parse a sparclet cpreg. */
3115 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3117 error_message
= _(": invalid cpreg name");
3120 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3125 as_fatal (_("failed sanity check."));
3126 } /* switch on arg code. */
3128 /* Break out of for() loop. */
3130 } /* For each arg that we expect. */
3135 /* Args don't match. */
3136 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3137 && (insn
->name
== insn
[1].name
3138 || !strcmp (insn
->name
, insn
[1].name
)))
3146 as_bad (_("Illegal operands%s"), error_message
);
3147 return special_case
;
3152 /* We have a match. Now see if the architecture is OK. */
3153 /* String to use in case of architecture warning. */
3154 const char *msg_str
= str
;
3155 int needed_arch_mask
= insn
->architecture
;
3157 /* Include the ASI architecture needed as well */
3158 if (sasi
&& needed_arch_mask
> sasi
->architecture
)
3160 needed_arch_mask
= sasi
->architecture
;
3161 msg_str
= sasi
->name
;
3165 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3167 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3169 hwcap_seen
|= hwcaps
;
3174 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3175 if (! needed_arch_mask
)
3177 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3180 if (needed_arch_mask
3181 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3184 /* Can we bump up the architecture? */
3185 else if (needed_arch_mask
3186 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3188 enum sparc_opcode_arch_val needed_architecture
=
3189 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3190 & needed_arch_mask
);
3192 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3194 && needed_architecture
> warn_after_architecture
)
3196 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3197 sparc_opcode_archs
[current_architecture
].name
,
3198 sparc_opcode_archs
[needed_architecture
].name
,
3200 warn_after_architecture
= needed_architecture
;
3202 current_architecture
= needed_architecture
;
3206 | (((bfd_uint64_t
) sparc_opcode_archs
[current_architecture
].hwcaps2
) << 32)
3207 | sparc_opcode_archs
[current_architecture
].hwcaps
);
3210 /* ??? This seems to be a bit fragile. What if the next entry in
3211 the opcode table is the one we want and it is supported?
3212 It is possible to arrange the table today so that this can't
3213 happen but what about tomorrow? */
3216 int arch
, printed_one_p
= 0;
3218 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3220 /* Create a list of the architectures that support the insn. */
3221 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3223 arch
= sparc_ffs (needed_arch_mask
);
3224 while ((1 << arch
) <= needed_arch_mask
)
3226 if ((1 << arch
) & needed_arch_mask
)
3230 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3237 as_bad (_("Architecture mismatch on \"%s %s\"."), str
, argsStart
);
3238 as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
3240 sparc_opcode_archs
[max_architecture
].name
);
3241 return special_case
;
3244 /* Make sure the hwcaps used by the instruction are
3245 currently enabled. */
3246 if (hwcaps
& ~hwcap_allowed
)
3248 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3250 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3252 return special_case
;
3254 } /* If no match. */
3257 } /* Forever looking for a match. */
3259 the_insn
.opcode
= opcode
;
3260 return special_case
;
3264 skip_over_keyword (char *q
)
3266 for (q
= q
+ (*q
== '#' || *q
== '%');
3267 ISALNUM (*q
) || *q
== '_';
3274 parse_sparc_asi (char **input_pointer_p
, const sparc_asi
**value_p
)
3276 const sparc_asi
*value
;
3279 p
= *input_pointer_p
;
3280 q
= skip_over_keyword(p
);
3283 value
= sparc_encode_asi (p
);
3288 *input_pointer_p
= q
;
3292 /* Parse an argument that can be expressed as a keyword.
3293 (eg: #StoreStore or %ccfr).
3294 The result is a boolean indicating success.
3295 If successful, INPUT_POINTER is updated. */
3298 parse_keyword_arg (int (*lookup_fn
) (const char *),
3299 char **input_pointerP
,
3305 p
= *input_pointerP
;
3306 q
= skip_over_keyword(p
);
3309 value
= (*lookup_fn
) (p
);
3314 *input_pointerP
= q
;
3318 /* Parse an argument that is a constant expression.
3319 The result is a boolean indicating success. */
3322 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3324 char *save
= input_line_pointer
;
3327 input_line_pointer
= *input_pointerP
;
3328 /* The next expression may be something other than a constant
3329 (say if we're not processing the right variant of the insn).
3330 Don't call expression unless we're sure it will succeed as it will
3331 signal an error (which we want to defer until later). */
3332 /* FIXME: It might be better to define md_operand and have it recognize
3333 things like %asi, etc. but continuing that route through to the end
3334 is a lot of work. */
3335 if (*input_line_pointer
== '%')
3337 input_line_pointer
= save
;
3341 *input_pointerP
= input_line_pointer
;
3342 input_line_pointer
= save
;
3343 if (exp
.X_op
!= O_constant
)
3345 *valueP
= exp
.X_add_number
;
3349 /* Subroutine of sparc_ip to parse an expression. */
3352 get_expression (char *str
)
3357 save_in
= input_line_pointer
;
3358 input_line_pointer
= str
;
3359 seg
= expression (&the_insn
.exp
);
3360 if (seg
!= absolute_section
3361 && seg
!= text_section
3362 && seg
!= data_section
3363 && seg
!= bss_section
3364 && seg
!= undefined_section
)
3366 the_insn
.error
= _("bad segment");
3367 expr_end
= input_line_pointer
;
3368 input_line_pointer
= save_in
;
3371 expr_end
= input_line_pointer
;
3372 input_line_pointer
= save_in
;
3376 /* Subroutine of md_assemble to output one insn. */
3379 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3381 char *toP
= frag_more (4);
3383 /* Put out the opcode. */
3384 if (INSN_BIG_ENDIAN
)
3385 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3387 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3389 /* Put out the symbol-dependent stuff. */
3390 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3392 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3393 (toP
- frag_now
->fr_literal
), /* Where. */
3398 /* Turn off overflow checking in fixup_segment. We'll do our
3399 own overflow checking in md_apply_fix. This is necessary because
3400 the insn size is 4 and fixup_segment will signal an overflow for
3401 large 8 byte quantities. */
3402 fixP
->fx_no_overflow
= 1;
3403 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3404 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3408 last_opcode
= theinsn
->opcode
;
3411 dwarf2_emit_insn (4);
3416 md_atof (int type
, char *litP
, int *sizeP
)
3418 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3421 /* Write a value out to the object file, using the appropriate
3425 md_number_to_chars (char *buf
, valueT val
, int n
)
3427 if (target_big_endian
)
3428 number_to_chars_bigendian (buf
, val
, n
);
3429 else if (target_little_endian_data
3430 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3431 /* Output debug words, which are not in allocated sections, as big
3433 number_to_chars_bigendian (buf
, val
, n
);
3434 else if (target_little_endian_data
|| ! target_big_endian
)
3435 number_to_chars_littleendian (buf
, val
, n
);
3438 /* Apply a fixS to the frags, now that we know the value it ought to
3442 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3444 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3445 offsetT val
= * (offsetT
*) valP
;
3448 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3450 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3453 /* SPARC ELF relocations don't use an addend in the data field. */
3454 if (fixP
->fx_addsy
!= NULL
)
3456 switch (fixP
->fx_r_type
)
3458 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3459 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3460 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3461 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3462 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3463 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3464 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3465 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3466 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3467 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3468 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3469 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3470 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3471 case BFD_RELOC_SPARC_TLS_IE_LD
:
3472 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3473 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3474 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3475 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3476 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3477 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3478 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3479 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3480 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3481 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3482 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3492 /* This is a hack. There should be a better way to
3493 handle this. Probably in terms of howto fields, once
3494 we can look at these fixups in terms of howtos. */
3495 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3496 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3499 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3500 generate a reloc, then we just want to let the reloc addend set
3501 the value. We do not want to also stuff the addend into the
3502 object file. Including the addend in the object file works when
3503 doing a static link, because the linker will ignore the object
3504 file contents. However, the dynamic linker does not ignore the
3505 object file contents. */
3506 if (fixP
->fx_addsy
!= NULL
3507 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3510 /* When generating PIC code, we do not want an addend for a reloc
3511 against a local symbol. We adjust fx_addnumber to cancel out the
3512 value already included in val, and to also cancel out the
3513 adjustment which bfd_install_relocation will create. */
3515 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3516 && fixP
->fx_addsy
!= NULL
3517 && ! S_IS_COMMON (fixP
->fx_addsy
)
3518 && symbol_section_p (fixP
->fx_addsy
))
3519 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3521 /* When generating PIC code, we need to fiddle to get
3522 bfd_install_relocation to do the right thing for a PC relative
3523 reloc against a local symbol which we are going to keep. */
3525 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3526 && fixP
->fx_addsy
!= NULL
3527 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3528 || S_IS_WEAK (fixP
->fx_addsy
))
3529 && S_IS_DEFINED (fixP
->fx_addsy
)
3530 && ! S_IS_COMMON (fixP
->fx_addsy
))
3533 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3537 /* If this is a data relocation, just output VAL. */
3539 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3541 md_number_to_chars (buf
, val
, 1);
3543 else if (fixP
->fx_r_type
== BFD_RELOC_16
3544 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3546 md_number_to_chars (buf
, val
, 2);
3548 else if (fixP
->fx_r_type
== BFD_RELOC_32
3549 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3550 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3552 md_number_to_chars (buf
, val
, 4);
3554 else if (fixP
->fx_r_type
== BFD_RELOC_64
3555 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3557 md_number_to_chars (buf
, val
, 8);
3559 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3560 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3567 /* It's a relocation against an instruction. */
3569 if (INSN_BIG_ENDIAN
)
3570 insn
= bfd_getb32 ((unsigned char *) buf
);
3572 insn
= bfd_getl32 ((unsigned char *) buf
);
3574 switch (fixP
->fx_r_type
)
3576 case BFD_RELOC_32_PCREL_S2
:
3578 /* FIXME: This increment-by-one deserves a comment of why it's
3580 if (! sparc_pic_code
3581 || fixP
->fx_addsy
== NULL
3582 || symbol_section_p (fixP
->fx_addsy
))
3585 insn
|= val
& 0x3fffffff;
3587 /* See if we have a delay slot. */
3588 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3592 #define XCC (2 << 20)
3593 #define COND(x) (((x)&0xf)<<25)
3594 #define CONDA COND(0x8)
3595 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3596 #define INSN_BA (F2(0,2) | CONDA)
3597 #define INSN_OR F3(2, 0x2, 0)
3598 #define INSN_NOP F2(0,4)
3602 /* If the instruction is a call with either:
3604 arithmetic instruction with rd == %o7
3605 where rs1 != %o7 and rs2 if it is register != %o7
3606 then we can optimize if the call destination is near
3607 by changing the call into a branch always. */
3608 if (INSN_BIG_ENDIAN
)
3609 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3611 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3612 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3614 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3615 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3616 || ((delay
& RD (~0)) != RD (O7
))))
3618 if ((delay
& RS1 (~0)) == RS1 (O7
)
3619 || ((delay
& F3I (~0)) == 0
3620 && (delay
& RS2 (~0)) == RS2 (O7
)))
3622 /* Ensure the branch will fit into simm22. */
3623 if ((val
& 0x3fe00000)
3624 && (val
& 0x3fe00000) != 0x3fe00000)
3626 /* Check if the arch is v9 and branch will fit
3628 if (((val
& 0x3c0000) == 0
3629 || (val
& 0x3c0000) == 0x3c0000)
3630 && (sparc_arch_size
== 64
3631 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3633 insn
= INSN_BPA
| (val
& 0x7ffff);
3636 insn
= INSN_BA
| (val
& 0x3fffff);
3637 if (fixP
->fx_where
>= 4
3638 && ((delay
& (0xffffffff ^ RS1 (~0)))
3639 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3644 if (INSN_BIG_ENDIAN
)
3645 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3647 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3648 if ((setter
& (0xffffffff ^ RD (~0)))
3649 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3656 If call foo was replaced with ba, replace
3657 or %rN, %g0, %o7 with nop. */
3658 reg
= (delay
& RS1 (~0)) >> 14;
3659 if (reg
!= ((setter
& RD (~0)) >> 25)
3660 || reg
== G0
|| reg
== O7
)
3663 if (INSN_BIG_ENDIAN
)
3664 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3666 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3671 case BFD_RELOC_SPARC_11
:
3672 if (! in_signed_range (val
, 0x7ff))
3673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3674 _("relocation overflow"));
3675 insn
|= val
& 0x7ff;
3678 case BFD_RELOC_SPARC_10
:
3679 if (! in_signed_range (val
, 0x3ff))
3680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3681 _("relocation overflow"));
3682 insn
|= val
& 0x3ff;
3685 case BFD_RELOC_SPARC_7
:
3686 if (! in_bitfield_range (val
, 0x7f))
3687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3688 _("relocation overflow"));
3692 case BFD_RELOC_SPARC_6
:
3693 if (! in_bitfield_range (val
, 0x3f))
3694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3695 _("relocation overflow"));
3699 case BFD_RELOC_SPARC_5
:
3700 if (! in_bitfield_range (val
, 0x1f))
3701 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3702 _("relocation overflow"));
3706 case BFD_RELOC_SPARC_WDISP10
:
3709 || val
<= -(offsetT
) 0x808)
3710 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3711 _("relocation overflow"));
3712 /* FIXME: The +1 deserves a comment. */
3713 val
= (val
>> 2) + 1;
3714 insn
|= ((val
& 0x300) << 11)
3715 | ((val
& 0xff) << 5);
3718 case BFD_RELOC_SPARC_WDISP16
:
3721 || val
<= -(offsetT
) 0x20008)
3722 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3723 _("relocation overflow"));
3724 /* FIXME: The +1 deserves a comment. */
3725 val
= (val
>> 2) + 1;
3726 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3729 case BFD_RELOC_SPARC_WDISP19
:
3732 || val
<= -(offsetT
) 0x100008)
3733 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3734 _("relocation overflow"));
3735 /* FIXME: The +1 deserves a comment. */
3736 val
= (val
>> 2) + 1;
3737 insn
|= val
& 0x7ffff;
3740 case BFD_RELOC_SPARC_HH22
:
3741 val
= BSR (val
, 32);
3744 case BFD_RELOC_SPARC_LM22
:
3745 case BFD_RELOC_HI22
:
3746 if (!fixP
->fx_addsy
)
3747 insn
|= (val
>> 10) & 0x3fffff;
3749 /* FIXME: Need comment explaining why we do this. */
3753 case BFD_RELOC_SPARC22
:
3754 if (val
& ~0x003fffff)
3755 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3756 _("relocation overflow"));
3757 insn
|= (val
& 0x3fffff);
3760 case BFD_RELOC_SPARC_HM10
:
3761 val
= BSR (val
, 32);
3764 case BFD_RELOC_LO10
:
3765 if (!fixP
->fx_addsy
)
3766 insn
|= val
& 0x3ff;
3768 /* FIXME: Need comment explaining why we do this. */
3772 case BFD_RELOC_SPARC_OLO10
:
3774 val
+= fixP
->tc_fix_data
;
3777 case BFD_RELOC_SPARC13
:
3778 if (! in_signed_range (val
, 0x1fff))
3779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3780 _("relocation overflow"));
3781 insn
|= val
& 0x1fff;
3784 case BFD_RELOC_SPARC_WDISP22
:
3785 val
= (val
>> 2) + 1;
3787 case BFD_RELOC_SPARC_BASE22
:
3788 insn
|= val
& 0x3fffff;
3791 case BFD_RELOC_SPARC_H34
:
3792 if (!fixP
->fx_addsy
)
3796 insn
|= tval
& 0x3fffff;
3800 case BFD_RELOC_SPARC_H44
:
3801 if (!fixP
->fx_addsy
)
3805 insn
|= tval
& 0x3fffff;
3809 case BFD_RELOC_SPARC_M44
:
3810 if (!fixP
->fx_addsy
)
3811 insn
|= (val
>> 12) & 0x3ff;
3814 case BFD_RELOC_SPARC_L44
:
3815 if (!fixP
->fx_addsy
)
3816 insn
|= val
& 0xfff;
3819 case BFD_RELOC_SPARC_HIX22
:
3820 if (!fixP
->fx_addsy
)
3822 val
^= ~(offsetT
) 0;
3823 insn
|= (val
>> 10) & 0x3fffff;
3827 case BFD_RELOC_SPARC_LOX10
:
3828 if (!fixP
->fx_addsy
)
3829 insn
|= 0x1c00 | (val
& 0x3ff);
3832 case BFD_RELOC_NONE
:
3834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3835 _("bad or unhandled relocation type: 0x%02x"),
3840 if (INSN_BIG_ENDIAN
)
3841 bfd_putb32 (insn
, (unsigned char *) buf
);
3843 bfd_putl32 (insn
, (unsigned char *) buf
);
3846 /* Are we finished with this relocation now? */
3847 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3851 /* Translate internal representation of relocation info to BFD target
3855 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3857 static arelent
*relocs
[3];
3859 bfd_reloc_code_real_type code
;
3861 relocs
[0] = reloc
= XNEW (arelent
);
3864 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3865 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3866 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3868 switch (fixp
->fx_r_type
)
3872 case BFD_RELOC_HI22
:
3873 case BFD_RELOC_LO10
:
3874 case BFD_RELOC_32_PCREL_S2
:
3875 case BFD_RELOC_SPARC13
:
3876 case BFD_RELOC_SPARC22
:
3877 case BFD_RELOC_SPARC_PC22
:
3878 case BFD_RELOC_SPARC_PC10
:
3879 case BFD_RELOC_SPARC_BASE13
:
3880 case BFD_RELOC_SPARC_WDISP10
:
3881 case BFD_RELOC_SPARC_WDISP16
:
3882 case BFD_RELOC_SPARC_WDISP19
:
3883 case BFD_RELOC_SPARC_WDISP22
:
3885 case BFD_RELOC_SPARC_5
:
3886 case BFD_RELOC_SPARC_6
:
3887 case BFD_RELOC_SPARC_7
:
3888 case BFD_RELOC_SPARC_10
:
3889 case BFD_RELOC_SPARC_11
:
3890 case BFD_RELOC_SPARC_HH22
:
3891 case BFD_RELOC_SPARC_HM10
:
3892 case BFD_RELOC_SPARC_LM22
:
3893 case BFD_RELOC_SPARC_PC_HH22
:
3894 case BFD_RELOC_SPARC_PC_HM10
:
3895 case BFD_RELOC_SPARC_PC_LM22
:
3896 case BFD_RELOC_SPARC_H34
:
3897 case BFD_RELOC_SPARC_H44
:
3898 case BFD_RELOC_SPARC_M44
:
3899 case BFD_RELOC_SPARC_L44
:
3900 case BFD_RELOC_SPARC_HIX22
:
3901 case BFD_RELOC_SPARC_LOX10
:
3902 case BFD_RELOC_SPARC_REV32
:
3903 case BFD_RELOC_SPARC_OLO10
:
3904 case BFD_RELOC_SPARC_UA16
:
3905 case BFD_RELOC_SPARC_UA32
:
3906 case BFD_RELOC_SPARC_UA64
:
3907 case BFD_RELOC_8_PCREL
:
3908 case BFD_RELOC_16_PCREL
:
3909 case BFD_RELOC_32_PCREL
:
3910 case BFD_RELOC_64_PCREL
:
3911 case BFD_RELOC_SPARC_PLT32
:
3912 case BFD_RELOC_SPARC_PLT64
:
3913 case BFD_RELOC_VTABLE_ENTRY
:
3914 case BFD_RELOC_VTABLE_INHERIT
:
3915 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3916 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3917 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3918 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3919 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3920 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3921 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3922 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3923 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3924 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3925 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3926 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3927 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3928 case BFD_RELOC_SPARC_TLS_IE_LD
:
3929 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3930 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3931 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3932 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3933 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3934 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3935 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3936 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3937 case BFD_RELOC_SPARC_GOTDATA_OP
:
3938 code
= fixp
->fx_r_type
;
3945 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3946 /* If we are generating PIC code, we need to generate a different
3950 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3952 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3955 #define GOTT_BASE "__GOTT_BASE__"
3956 #define GOTT_INDEX "__GOTT_INDEX__"
3959 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3965 case BFD_RELOC_32_PCREL_S2
:
3966 if (generic_force_reloc (fixp
))
3967 code
= BFD_RELOC_SPARC_WPLT30
;
3969 case BFD_RELOC_HI22
:
3970 code
= BFD_RELOC_SPARC_GOT22
;
3971 if (fixp
->fx_addsy
!= NULL
)
3973 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3974 code
= BFD_RELOC_SPARC_PC22
;
3976 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3977 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3978 code
= BFD_RELOC_HI22
; /* Unchanged. */
3982 case BFD_RELOC_LO10
:
3983 code
= BFD_RELOC_SPARC_GOT10
;
3984 if (fixp
->fx_addsy
!= NULL
)
3986 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3987 code
= BFD_RELOC_SPARC_PC10
;
3989 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3990 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3991 code
= BFD_RELOC_LO10
; /* Unchanged. */
3995 case BFD_RELOC_SPARC13
:
3996 code
= BFD_RELOC_SPARC_GOT13
;
4002 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
4004 /* Nothing is aligned in DWARF debugging sections. */
4005 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
4008 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
4009 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
4010 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
4014 if (code
== BFD_RELOC_SPARC_OLO10
)
4015 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
4017 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4018 if (reloc
->howto
== 0)
4020 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4021 _("internal error: can't export reloc type %d (`%s')"),
4022 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
4028 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
4031 if (reloc
->howto
->pc_relative
== 0
4032 || code
== BFD_RELOC_SPARC_PC10
4033 || code
== BFD_RELOC_SPARC_PC22
)
4034 reloc
->addend
= fixp
->fx_addnumber
;
4035 else if (sparc_pic_code
4036 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
4037 && fixp
->fx_addsy
!= NULL
4038 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
4039 || S_IS_WEAK (fixp
->fx_addsy
))
4040 && S_IS_DEFINED (fixp
->fx_addsy
)
4041 && ! S_IS_COMMON (fixp
->fx_addsy
))
4042 reloc
->addend
= fixp
->fx_addnumber
;
4044 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
4046 #else /* elf or coff */
4048 if (code
!= BFD_RELOC_32_PCREL_S2
4049 && code
!= BFD_RELOC_SPARC_WDISP22
4050 && code
!= BFD_RELOC_SPARC_WDISP16
4051 && code
!= BFD_RELOC_SPARC_WDISP19
4052 && code
!= BFD_RELOC_SPARC_WDISP10
4053 && code
!= BFD_RELOC_SPARC_WPLT30
4054 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
4055 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
4056 reloc
->addend
= fixp
->fx_addnumber
;
4057 else if (symbol_section_p (fixp
->fx_addsy
))
4058 reloc
->addend
= (section
->vma
4059 + fixp
->fx_addnumber
4060 + md_pcrel_from (fixp
));
4062 reloc
->addend
= fixp
->fx_offset
;
4065 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4066 on the same location. */
4067 if (code
== BFD_RELOC_SPARC_OLO10
)
4069 relocs
[1] = reloc
= XNEW (arelent
);
4072 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4074 = symbol_get_bfdsym (section_symbol (absolute_section
));
4075 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4076 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4077 reloc
->addend
= fixp
->tc_fix_data
;
4083 /* We have no need to default values of symbols. */
4086 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4091 /* Round up a section size to the appropriate boundary. */
4094 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4097 /* This is not right for ELF; a.out wants it, and COFF will force
4098 the alignment anyways. */
4099 valueT align
= ((valueT
) 1
4100 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
4103 /* Turn alignment value into a mask. */
4105 newsize
= (size
+ align
) & ~align
;
4112 /* Exactly what point is a PC-relative offset relative TO?
4113 On the sparc, they're relative to the address of the offset, plus
4114 its size. This gets us to the following instruction.
4115 (??? Is this right? FIXME-SOON) */
4117 md_pcrel_from (fixS
*fixP
)
4121 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4122 if (! sparc_pic_code
4123 || fixP
->fx_addsy
== NULL
4124 || symbol_section_p (fixP
->fx_addsy
))
4125 ret
+= fixP
->fx_size
;
4129 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4140 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4143 return (value
== 1) ? shift
: -1;
4146 /* Sort of like s_lcomm. */
4149 static int max_alignment
= 15;
4153 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4163 c
= get_symbol_name (&name
);
4164 p
= input_line_pointer
;
4166 SKIP_WHITESPACE_AFTER_NAME ();
4168 if (*input_line_pointer
!= ',')
4170 as_bad (_("Expected comma after name"));
4171 ignore_rest_of_line ();
4175 ++input_line_pointer
;
4177 if ((size
= get_absolute_expression ()) < 0)
4179 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4180 ignore_rest_of_line ();
4185 symbolP
= symbol_find_or_make (name
);
4188 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4189 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4191 as_bad (_("bad .reserve segment -- expected BSS segment"));
4195 if (input_line_pointer
[2] == '.')
4196 input_line_pointer
+= 7;
4198 input_line_pointer
+= 6;
4201 if (*input_line_pointer
== ',')
4203 ++input_line_pointer
;
4206 if (*input_line_pointer
== '\n')
4208 as_bad (_("missing alignment"));
4209 ignore_rest_of_line ();
4213 align
= (int) get_absolute_expression ();
4216 if (align
> max_alignment
)
4218 align
= max_alignment
;
4219 as_warn (_("alignment too large; assuming %d"), align
);
4225 as_bad (_("negative alignment"));
4226 ignore_rest_of_line ();
4232 temp
= mylog2 (align
);
4235 as_bad (_("alignment not a power of 2"));
4236 ignore_rest_of_line ();
4243 record_alignment (bss_section
, align
);
4248 if (!S_IS_DEFINED (symbolP
)
4250 && S_GET_OTHER (symbolP
) == 0
4251 && S_GET_DESC (symbolP
) == 0
4258 segT current_seg
= now_seg
;
4259 subsegT current_subseg
= now_subseg
;
4261 /* Switch to bss. */
4262 subseg_set (bss_section
, 1);
4266 frag_align (align
, 0, 0);
4268 /* Detach from old frag. */
4269 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4270 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4272 symbol_set_frag (symbolP
, frag_now
);
4273 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4274 (offsetT
) size
, (char *) 0);
4277 S_SET_SEGMENT (symbolP
, bss_section
);
4279 subseg_set (current_seg
, current_subseg
);
4282 S_SET_SIZE (symbolP
, size
);
4288 as_warn (_("Ignoring attempt to re-define symbol %s"),
4289 S_GET_NAME (symbolP
));
4292 demand_empty_rest_of_line ();
4296 s_common (int ignore ATTRIBUTE_UNUSED
)
4304 c
= get_symbol_name (&name
);
4305 /* Just after name is now '\0'. */
4306 p
= input_line_pointer
;
4308 SKIP_WHITESPACE_AFTER_NAME ();
4309 if (*input_line_pointer
!= ',')
4311 as_bad (_("Expected comma after symbol-name"));
4312 ignore_rest_of_line ();
4317 input_line_pointer
++;
4319 if ((temp
= get_absolute_expression ()) < 0)
4321 as_bad (_(".COMMon length (%lu) out of range ignored"),
4322 (unsigned long) temp
);
4323 ignore_rest_of_line ();
4328 symbolP
= symbol_find_or_make (name
);
4330 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4332 as_bad (_("Ignoring attempt to re-define symbol"));
4333 ignore_rest_of_line ();
4336 if (S_GET_VALUE (symbolP
) != 0)
4338 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4340 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4341 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4347 S_SET_VALUE (symbolP
, (valueT
) size
);
4348 S_SET_EXTERNAL (symbolP
);
4351 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4352 if (*input_line_pointer
!= ',')
4354 as_bad (_("Expected comma after common length"));
4355 ignore_rest_of_line ();
4358 input_line_pointer
++;
4360 if (*input_line_pointer
!= '"')
4362 temp
= get_absolute_expression ();
4365 if (temp
> max_alignment
)
4367 temp
= max_alignment
;
4368 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4374 as_bad (_("negative alignment"));
4375 ignore_rest_of_line ();
4380 if (symbol_get_obj (symbolP
)->local
)
4387 old_subsec
= now_subseg
;
4392 align
= mylog2 (temp
);
4396 as_bad (_("alignment not a power of 2"));
4397 ignore_rest_of_line ();
4401 record_alignment (bss_section
, align
);
4402 subseg_set (bss_section
, 0);
4404 frag_align (align
, 0, 0);
4405 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4406 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4407 symbol_set_frag (symbolP
, frag_now
);
4408 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4409 (offsetT
) size
, (char *) 0);
4411 S_SET_SEGMENT (symbolP
, bss_section
);
4412 S_CLEAR_EXTERNAL (symbolP
);
4413 S_SET_SIZE (symbolP
, size
);
4414 subseg_set (old_sec
, old_subsec
);
4417 #endif /* OBJ_ELF */
4420 S_SET_VALUE (symbolP
, (valueT
) size
);
4422 S_SET_ALIGN (symbolP
, temp
);
4423 S_SET_SIZE (symbolP
, size
);
4425 S_SET_EXTERNAL (symbolP
);
4426 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4431 input_line_pointer
++;
4432 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4433 if (*input_line_pointer
== '.')
4434 input_line_pointer
++;
4435 /* @@ Some say data, some say bss. */
4436 if (strncmp (input_line_pointer
, "bss\"", 4)
4437 && strncmp (input_line_pointer
, "data\"", 5))
4439 while (*--input_line_pointer
!= '"')
4441 input_line_pointer
--;
4442 goto bad_common_segment
;
4444 while (*input_line_pointer
++ != '"')
4446 goto allocate_common
;
4449 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4451 demand_empty_rest_of_line ();
4456 p
= input_line_pointer
;
4457 while (*p
&& *p
!= '\n')
4461 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4463 input_line_pointer
= p
;
4464 ignore_rest_of_line ();
4469 /* Handle the .empty pseudo-op. This suppresses the warnings about
4470 invalid delay slot usage. */
4473 s_empty (int ignore ATTRIBUTE_UNUSED
)
4475 /* The easy way to implement is to just forget about the last
4481 s_seg (int ignore ATTRIBUTE_UNUSED
)
4484 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4486 input_line_pointer
+= 6;
4490 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4492 input_line_pointer
+= 6;
4496 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4498 input_line_pointer
+= 7;
4502 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4504 input_line_pointer
+= 5;
4505 /* We only support 2 segments -- text and data -- for now, so
4506 things in the "bss segment" will have to go into data for now.
4507 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4508 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4511 as_bad (_("Unknown segment type"));
4512 demand_empty_rest_of_line ();
4518 subseg_set (data_section
, 1);
4519 demand_empty_rest_of_line ();
4523 s_proc (int ignore ATTRIBUTE_UNUSED
)
4525 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4527 ++input_line_pointer
;
4529 ++input_line_pointer
;
4532 /* This static variable is set by s_uacons to tell sparc_cons_align
4533 that the expression does not need to be aligned. */
4535 static int sparc_no_align_cons
= 0;
4537 /* This handles the unaligned space allocation pseudo-ops, such as
4538 .uaword. .uaword is just like .word, but the value does not need
4542 s_uacons (int bytes
)
4544 /* Tell sparc_cons_align not to align this value. */
4545 sparc_no_align_cons
= 1;
4547 sparc_no_align_cons
= 0;
4550 /* This handles the native word allocation pseudo-op .nword.
4551 For sparc_arch_size 32 it is equivalent to .word, for
4552 sparc_arch_size 64 it is equivalent to .xword. */
4555 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4557 cons (sparc_arch_size
== 32 ? 4 : 8);
4561 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4565 .register %g[2367],{#scratch|symbolname|#ignore}
4569 s_register (int ignore ATTRIBUTE_UNUSED
)
4576 if (input_line_pointer
[0] != '%'
4577 || input_line_pointer
[1] != 'g'
4578 || ((input_line_pointer
[2] & ~1) != '2'
4579 && (input_line_pointer
[2] & ~1) != '6')
4580 || input_line_pointer
[3] != ',')
4581 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4582 reg
= input_line_pointer
[2] - '0';
4583 input_line_pointer
+= 4;
4585 if (*input_line_pointer
== '#')
4587 ++input_line_pointer
;
4588 c
= get_symbol_name (®name
);
4589 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4590 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4591 if (regname
[0] == 'i')
4594 regname
= (char *) "";
4598 c
= get_symbol_name (®name
);
4601 if (sparc_arch_size
== 64)
4605 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4606 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4607 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4608 as_bad (_("redefinition of global register"));
4612 if (regname
== NULL
)
4613 globals
[reg
] = (symbolS
*) 1;
4618 if (symbol_find (regname
))
4619 as_bad (_("Register symbol %s already defined."),
4622 globals
[reg
] = symbol_make (regname
);
4623 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4625 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4626 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4627 flags
|= BSF_GLOBAL
;
4628 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4629 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4630 S_SET_ALIGN (globals
[reg
], reg
);
4631 S_SET_SIZE (globals
[reg
], 0);
4632 /* Although we actually want undefined_section here,
4633 we have to use absolute_section, because otherwise
4634 generic as code will make it a COM section.
4635 We fix this up in sparc_adjust_symtab. */
4636 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4637 S_SET_OTHER (globals
[reg
], 0);
4638 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4639 ->internal_elf_sym
.st_info
=
4640 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4641 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4642 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4647 (void) restore_line_pointer (c
);
4649 demand_empty_rest_of_line ();
4652 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4653 symbols which need it. */
4656 sparc_adjust_symtab (void)
4660 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4662 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4663 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4666 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4667 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4670 S_SET_SEGMENT (sym
, undefined_section
);
4675 /* If the --enforce-aligned-data option is used, we require .word,
4676 et. al., to be aligned correctly. We do it by setting up an
4677 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4678 no unexpected alignment was introduced.
4680 The SunOS and Solaris native assemblers enforce aligned data by
4681 default. We don't want to do that, because gcc can deliberately
4682 generate misaligned data if the packed attribute is used. Instead,
4683 we permit misaligned data by default, and permit the user to set an
4684 option to check for it. */
4687 sparc_cons_align (int nbytes
)
4691 /* Only do this if we are enforcing aligned data. */
4692 if (! enforce_aligned_data
)
4695 /* Don't align if this is an unaligned pseudo-op. */
4696 if (sparc_no_align_cons
)
4699 nalign
= mylog2 (nbytes
);
4703 gas_assert (nalign
> 0);
4705 if (now_seg
== absolute_section
)
4707 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4708 as_bad (_("misaligned data"));
4712 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4713 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4715 record_alignment (now_seg
, nalign
);
4718 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4721 sparc_handle_align (fragS
*fragp
)
4726 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4728 switch (fragp
->fr_type
)
4732 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4736 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4747 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4749 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4750 if (INSN_BIG_ENDIAN
)
4751 number_to_chars_bigendian (p
, wval
, 4);
4753 number_to_chars_littleendian (p
, wval
, 4);
4759 if (INSN_BIG_ENDIAN
)
4760 number_to_chars_bigendian (p
, 0x01000000, 4);
4762 number_to_chars_littleendian (p
, 0x01000000, 4);
4764 fragp
->fr_fix
+= fix
;
4774 /* Some special processing for a Sparc ELF file. */
4777 sparc_elf_final_processing (void)
4779 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4780 sort of BFD interface for this. */
4781 if (sparc_arch_size
== 64)
4783 switch (sparc_memory_model
)
4786 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4789 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4795 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4796 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4797 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4798 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4799 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4800 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4804 sparc_cons (expressionS
*exp
, int size
)
4807 const char *sparc_cons_special_reloc
= NULL
;
4810 save
= input_line_pointer
;
4811 if (input_line_pointer
[0] == '%'
4812 && input_line_pointer
[1] == 'r'
4813 && input_line_pointer
[2] == '_')
4815 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4817 input_line_pointer
+= 7;
4818 sparc_cons_special_reloc
= "disp";
4820 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4822 if (size
!= 4 && size
!= 8)
4823 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4826 input_line_pointer
+= 6;
4827 sparc_cons_special_reloc
= "plt";
4830 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4832 if (size
!= 4 && size
!= 8)
4833 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4836 input_line_pointer
+= 13;
4837 sparc_cons_special_reloc
= "tls_dtpoff";
4840 if (sparc_cons_special_reloc
)
4847 if (*input_line_pointer
!= '8')
4849 input_line_pointer
--;
4852 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4856 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4860 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4870 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4871 sparc_cons_special_reloc
, size
* 8, size
);
4875 input_line_pointer
+= 2;
4876 if (*input_line_pointer
!= '(')
4878 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4879 sparc_cons_special_reloc
, size
* 8);
4886 input_line_pointer
= save
;
4887 sparc_cons_special_reloc
= NULL
;
4892 char *end
= ++input_line_pointer
;
4895 while (! is_end_of_line
[(c
= *end
)])
4909 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4910 sparc_cons_special_reloc
, size
* 8);
4916 if (input_line_pointer
!= end
)
4918 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4919 sparc_cons_special_reloc
, size
* 8);
4923 input_line_pointer
++;
4925 c
= *input_line_pointer
;
4926 if (! is_end_of_line
[c
] && c
!= ',')
4927 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4928 sparc_cons_special_reloc
, size
* 8);
4934 if (sparc_cons_special_reloc
== NULL
)
4936 return sparc_cons_special_reloc
;
4941 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4942 reloc for a cons. We could use the definition there, except that
4943 we want to handle little endian relocs specially. */
4946 cons_fix_new_sparc (fragS
*frag
,
4948 unsigned int nbytes
,
4950 const char *sparc_cons_special_reloc
)
4952 bfd_reloc_code_real_type r
;
4954 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4955 (nbytes
== 2 ? BFD_RELOC_16
:
4956 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4958 if (target_little_endian_data
4960 && now_seg
->flags
& SEC_ALLOC
)
4961 r
= BFD_RELOC_SPARC_REV32
;
4964 /* The Solaris linker does not allow R_SPARC_UA64
4965 relocations for 32-bit executables. */
4966 if (!target_little_endian_data
4967 && sparc_arch_size
!= 64
4968 && r
== BFD_RELOC_64
)
4972 if (sparc_cons_special_reloc
)
4974 if (*sparc_cons_special_reloc
== 'd')
4977 case 1: r
= BFD_RELOC_8_PCREL
; break;
4978 case 2: r
= BFD_RELOC_16_PCREL
; break;
4979 case 4: r
= BFD_RELOC_32_PCREL
; break;
4980 case 8: r
= BFD_RELOC_64_PCREL
; break;
4983 else if (*sparc_cons_special_reloc
== 'p')
4986 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4987 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4992 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4993 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4996 else if (sparc_no_align_cons
4997 || /* PR 20803 - relocs in the .eh_frame section
4998 need to support unaligned access. */
4999 strcmp (now_seg
->name
, ".eh_frame") == 0)
5003 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
5004 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
5006 /* The Solaris linker does not allow R_SPARC_UA64
5007 relocations for 32-bit executables. */
5008 case 8: r
= sparc_arch_size
== 64 ?
5009 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
5011 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
5017 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
5021 sparc_cfi_frame_initial_instructions (void)
5023 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
5027 sparc_regname_to_dw2regnum (char *regname
)
5037 case 'g': i
= 0; break;
5038 case 'o': i
= 1; break;
5039 case 'l': i
= 2; break;
5040 case 'i': i
= 3; break;
5041 default: i
= -1; break;
5045 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
5047 return i
* 8 + regname
[1] - '0';
5049 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
5051 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
5053 if (regname
[0] == 'f' || regname
[0] == 'r')
5055 unsigned int regnum
;
5057 regnum
= strtoul (regname
+ 1, &q
, 10);
5058 if (q
== NULL
|| *q
)
5060 if (regnum
>= ((regname
[0] == 'f'
5061 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
5064 if (regname
[0] == 'f')
5067 if (regnum
>= 64 && (regnum
& 1))
5076 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
5078 sparc_no_align_cons
= 1;
5079 emit_expr_with_reloc (exp
, nbytes
, "disp");
5080 sparc_no_align_cons
= 0;