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[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "subsegs.h"
26
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
29
30 #ifdef OBJ_ELF
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
33 #endif
34
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40
41 static int sparc_ip (char *, const struct sparc_opcode **);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
45
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
50 #ifndef DEFAULT_ARCH
51 #define DEFAULT_ARCH "sparclite"
52 #endif
53 static char *default_arch = DEFAULT_ARCH;
54
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 have been set. */
57 static int default_init_p;
58
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
61
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture;
68
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size;
74
75 #ifdef OBJ_ELF
76 /* The currently selected v9 memory model. Currently only used for
77 ELF. */
78 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
79
80 #ifndef TE_SOLARIS
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen;
84 #endif
85 #endif
86
87 static int hwcap_allowed;
88
89 static int architecture_requested;
90 static int warn_on_bump;
91
92 /* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94 static enum sparc_opcode_arch_val warn_after_architecture;
95
96 /* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98 static int no_undeclared_regs;
99
100 /* Non-zero if we should try to relax jumps and calls. */
101 static int sparc_relax;
102
103 /* Non-zero if we are generating PIC code. */
104 int sparc_pic_code;
105
106 /* Non-zero if we should give an error when misaligned data is seen. */
107 static int enforce_aligned_data;
108
109 extern int target_big_endian;
110
111 static int target_little_endian_data;
112
113 /* Symbols for global registers on v9. */
114 static symbolS *globals[8];
115
116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117 int sparc_cie_data_alignment;
118
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127 #endif
128
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control *op_hash;
131
132 static void s_data1 (void);
133 static void s_seg (int);
134 static void s_proc (int);
135 static void s_reserve (int);
136 static void s_common (int);
137 static void s_empty (int);
138 static void s_uacons (int);
139 static void s_ncons (int);
140 #ifdef OBJ_ELF
141 static void s_register (int);
142 #endif
143
144 const pseudo_typeS md_pseudo_table[] =
145 {
146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
147 {"common", s_common, 0},
148 {"empty", s_empty, 0},
149 {"global", s_globl, 0},
150 {"half", cons, 2},
151 {"nword", s_ncons, 0},
152 {"optim", s_ignore, 0},
153 {"proc", s_proc, 0},
154 {"reserve", s_reserve, 0},
155 {"seg", s_seg, 0},
156 {"skip", s_space, 0},
157 {"word", cons, 4},
158 {"xword", cons, 8},
159 {"uahalf", s_uacons, 2},
160 {"uaword", s_uacons, 4},
161 {"uaxword", s_uacons, 8},
162 #ifdef OBJ_ELF
163 /* These are specific to sparc/svr4. */
164 {"2byte", s_uacons, 2},
165 {"4byte", s_uacons, 4},
166 {"8byte", s_uacons, 8},
167 {"register", s_register, 0},
168 #endif
169 {NULL, 0, 0},
170 };
171
172 /* This array holds the chars that always start a comment. If the
173 pre-processor is disabled, these aren't very useful. */
174 const char comment_chars[] = "!"; /* JF removed '|' from
175 comment_chars. */
176
177 /* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
179 .line and .file directives will appear in the pre-processed output. */
180 /* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
182 #NO_APP at the beginning of its output. */
183 /* Also note that comments started like this one will always
184 work if '/' isn't otherwise defined. */
185 const char line_comment_chars[] = "#";
186
187 const char line_separator_chars[] = ";";
188
189 /* Chars that can be used to separate mant from exp in floating point
190 nums. */
191 const char EXP_CHARS[] = "eE";
192
193 /* Chars that mean this number is a floating point constant.
194 As in 0f12.456
195 or 0d1.2345e12 */
196 const char FLT_CHARS[] = "rRsSfFdDxXpP";
197
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
201
202 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
203
204 struct sparc_it
205 {
206 char *error;
207 unsigned long opcode;
208 struct nlist *nlistp;
209 expressionS exp;
210 expressionS exp2;
211 int pcrel;
212 bfd_reloc_code_real_type reloc;
213 };
214
215 struct sparc_it the_insn, set_insn;
216
217 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
218 \f
219 /* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
222 and file formats. */
223
224 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
225 v8plusa, v9, v9a, v9b, v9_64};
226
227 static struct sparc_arch {
228 char *name;
229 char *opcode_arch;
230 enum sparc_arch_types arch_type;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size;
234 /* Allowable arg to -A? */
235 int user_option_p;
236 int hwcap_allowed;
237 } sparc_arch_table[] = {
238 { "v6", "v6", v6, 0, 1, 0 },
239 { "v7", "v7", v7, 0, 1, 0 },
240 { "v8", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
241 { "v8a", "v8", v8, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
242 { "sparc", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
243 { "sparcvis", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
244 { "sparcvis2", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
245 { "sparcfmaf", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF },
246 { "sparcima", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_IMA },
247 { "sparcvis3", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC },
248 { "sparcvis3r", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU },
249 { "sparclet", "sparclet", sparclet, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
250 { "sparclite", "sparclite", sparclite, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
251 { "sparc86x", "sparclite", sparc86x, 32, 1, F_MUL32|F_DIV32|F_FSMULD },
252 { "v8plus", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS },
253 { "v8plusa", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS },
254 { "v8plusb", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2 },
255 { "v8plusc", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT },
256 { "v8plusd", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
257 { "v8plusv", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_V8PLUS|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
258 { "v9", "v9", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
259 { "v9a", "v9a", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS },
260 { "v9b", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2 },
261 { "v9c", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT },
262 { "v9d", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC },
263 { "v9v", "v9b", v9, 0, 1, F_MUL32|F_DIV32|F_FSMULD|F_POPC|F_VIS|F_VIS2|F_ASI_BLK_INIT|F_FMAF|F_VIS3|F_HPC|F_RANDOM|F_TRANS|F_FJFMAU|F_IMA|F_ASI_CACHE_SPARING },
264 /* This exists to allow configure.in/Makefile.in to pass one
265 value to specify both the default machine and default word size. */
266 { "v9-64", "v9", v9, 64, 0, F_MUL32|F_DIV32|F_FSMULD|F_POPC },
267 { NULL, NULL, v8, 0, 0, 0 }
268 };
269
270 /* Variant of default_arch */
271 static enum sparc_arch_types default_arch_type;
272
273 static struct sparc_arch *
274 lookup_arch (char *name)
275 {
276 struct sparc_arch *sa;
277
278 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
279 if (strcmp (sa->name, name) == 0)
280 break;
281 if (sa->name == NULL)
282 return NULL;
283 return sa;
284 }
285
286 /* Initialize the default opcode arch and word size from the default
287 architecture name. */
288
289 static void
290 init_default_arch (void)
291 {
292 struct sparc_arch *sa = lookup_arch (default_arch);
293
294 if (sa == NULL
295 || sa->default_arch_size == 0)
296 as_fatal (_("Invalid default architecture, broken assembler."));
297
298 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
299 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
300 as_fatal (_("Bad opcode table, broken assembler."));
301 default_arch_size = sparc_arch_size = sa->default_arch_size;
302 default_init_p = 1;
303 default_arch_type = sa->arch_type;
304 }
305
306 /* Called by TARGET_FORMAT. */
307
308 const char *
309 sparc_target_format (void)
310 {
311 /* We don't get a chance to initialize anything before we're called,
312 so handle that now. */
313 if (! default_init_p)
314 init_default_arch ();
315
316 #ifdef OBJ_AOUT
317 #ifdef TE_NetBSD
318 return "a.out-sparc-netbsd";
319 #else
320 #ifdef TE_SPARCAOUT
321 if (target_big_endian)
322 return "a.out-sunos-big";
323 else if (default_arch_type == sparc86x && target_little_endian_data)
324 return "a.out-sunos-big";
325 else
326 return "a.out-sparc-little";
327 #else
328 return "a.out-sunos-big";
329 #endif
330 #endif
331 #endif
332
333 #ifdef OBJ_BOUT
334 return "b.out.big";
335 #endif
336
337 #ifdef OBJ_COFF
338 #ifdef TE_LYNX
339 return "coff-sparc-lynx";
340 #else
341 return "coff-sparc";
342 #endif
343 #endif
344
345 #ifdef TE_VXWORKS
346 return "elf32-sparc-vxworks";
347 #endif
348
349 #ifdef OBJ_ELF
350 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
351 #endif
352
353 abort ();
354 }
355 \f
356 /* md_parse_option
357 * Invocation line includes a switch not recognized by the base assembler.
358 * See if it's a processor-specific option. These are:
359 *
360 * -bump
361 * Warn on architecture bumps. See also -A.
362 *
363 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
364 * Standard 32 bit architectures.
365 * -Av9, -Av9a, -Av9b
366 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
367 * This used to only mean 64 bits, but properly specifying it
368 * complicated gcc's ASM_SPECs, so now opcode selection is
369 * specified orthogonally to word size (except when specifying
370 * the default, but that is an internal implementation detail).
371 * -Av8plus, -Av8plusa, -Av8plusb
372 * Same as -Av9{,a,b}.
373 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
374 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
375 * assembler.
376 * -xarch=v9, -xarch=v9a, -xarch=v9b
377 * Same as -Av9{,a,b} -64, for compatibility with Sun's
378 * assembler.
379 *
380 * Select the architecture and possibly the file format.
381 * Instructions or features not supported by the selected
382 * architecture cause fatal errors.
383 *
384 * The default is to start at v6, and bump the architecture up
385 * whenever an instruction is seen at a higher level. In 32 bit
386 * environments, v9 is not bumped up to, the user must pass
387 * -Av8plus{,a,b}.
388 *
389 * If -bump is specified, a warning is printing when bumping to
390 * higher levels.
391 *
392 * If an architecture is specified, all instructions must match
393 * that architecture. Any higher level instructions are flagged
394 * as errors. Note that in the 32 bit environment specifying
395 * -Av8plus does not automatically create a v8plus object file, a
396 * v9 insn must be seen.
397 *
398 * If both an architecture and -bump are specified, the
399 * architecture starts at the specified level, but bumps are
400 * warnings. Note that we can't set `current_architecture' to
401 * the requested level in this case: in the 32 bit environment,
402 * we still must avoid creating v8plus object files unless v9
403 * insns are seen.
404 *
405 * Note:
406 * Bumping between incompatible architectures is always an
407 * error. For example, from sparclite to v9.
408 */
409
410 #ifdef OBJ_ELF
411 const char *md_shortopts = "A:K:VQ:sq";
412 #else
413 #ifdef OBJ_AOUT
414 const char *md_shortopts = "A:k";
415 #else
416 const char *md_shortopts = "A:";
417 #endif
418 #endif
419 struct option md_longopts[] = {
420 #define OPTION_BUMP (OPTION_MD_BASE)
421 {"bump", no_argument, NULL, OPTION_BUMP},
422 #define OPTION_SPARC (OPTION_MD_BASE + 1)
423 {"sparc", no_argument, NULL, OPTION_SPARC},
424 #define OPTION_XARCH (OPTION_MD_BASE + 2)
425 {"xarch", required_argument, NULL, OPTION_XARCH},
426 #ifdef OBJ_ELF
427 #define OPTION_32 (OPTION_MD_BASE + 3)
428 {"32", no_argument, NULL, OPTION_32},
429 #define OPTION_64 (OPTION_MD_BASE + 4)
430 {"64", no_argument, NULL, OPTION_64},
431 #define OPTION_TSO (OPTION_MD_BASE + 5)
432 {"TSO", no_argument, NULL, OPTION_TSO},
433 #define OPTION_PSO (OPTION_MD_BASE + 6)
434 {"PSO", no_argument, NULL, OPTION_PSO},
435 #define OPTION_RMO (OPTION_MD_BASE + 7)
436 {"RMO", no_argument, NULL, OPTION_RMO},
437 #endif
438 #ifdef SPARC_BIENDIAN
439 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
440 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
441 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
442 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
443 #endif
444 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
445 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
446 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
447 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
448 #ifdef OBJ_ELF
449 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
450 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
451 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
452 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
453 #endif
454 #define OPTION_RELAX (OPTION_MD_BASE + 14)
455 {"relax", no_argument, NULL, OPTION_RELAX},
456 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
457 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
458 {NULL, no_argument, NULL, 0}
459 };
460
461 size_t md_longopts_size = sizeof (md_longopts);
462
463 int
464 md_parse_option (int c, char *arg)
465 {
466 /* We don't get a chance to initialize anything before we're called,
467 so handle that now. */
468 if (! default_init_p)
469 init_default_arch ();
470
471 switch (c)
472 {
473 case OPTION_BUMP:
474 warn_on_bump = 1;
475 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
476 break;
477
478 case OPTION_XARCH:
479 #ifdef OBJ_ELF
480 if (strncmp (arg, "v9", 2) != 0)
481 md_parse_option (OPTION_32, NULL);
482 else
483 md_parse_option (OPTION_64, NULL);
484 #endif
485 /* Fall through. */
486
487 case 'A':
488 {
489 struct sparc_arch *sa;
490 enum sparc_opcode_arch_val opcode_arch;
491
492 sa = lookup_arch (arg);
493 if (sa == NULL
494 || ! sa->user_option_p)
495 {
496 if (c == OPTION_XARCH)
497 as_bad (_("invalid architecture -xarch=%s"), arg);
498 else
499 as_bad (_("invalid architecture -A%s"), arg);
500 return 0;
501 }
502
503 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
504 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
505 as_fatal (_("Bad opcode table, broken assembler."));
506
507 if (!architecture_requested
508 || opcode_arch > max_architecture)
509 max_architecture = opcode_arch;
510 hwcap_allowed |= sa->hwcap_allowed;
511 architecture_requested = 1;
512 }
513 break;
514
515 case OPTION_SPARC:
516 /* Ignore -sparc, used by SunOS make default .s.o rule. */
517 break;
518
519 case OPTION_ENFORCE_ALIGNED_DATA:
520 enforce_aligned_data = 1;
521 break;
522
523 #ifdef SPARC_BIENDIAN
524 case OPTION_LITTLE_ENDIAN:
525 target_big_endian = 0;
526 if (default_arch_type != sparclet)
527 as_fatal ("This target does not support -EL");
528 break;
529 case OPTION_LITTLE_ENDIAN_DATA:
530 target_little_endian_data = 1;
531 target_big_endian = 0;
532 if (default_arch_type != sparc86x
533 && default_arch_type != v9)
534 as_fatal ("This target does not support --little-endian-data");
535 break;
536 case OPTION_BIG_ENDIAN:
537 target_big_endian = 1;
538 break;
539 #endif
540
541 #ifdef OBJ_AOUT
542 case 'k':
543 sparc_pic_code = 1;
544 break;
545 #endif
546
547 #ifdef OBJ_ELF
548 case OPTION_32:
549 case OPTION_64:
550 {
551 const char **list, **l;
552
553 sparc_arch_size = c == OPTION_32 ? 32 : 64;
554 list = bfd_target_list ();
555 for (l = list; *l != NULL; l++)
556 {
557 if (sparc_arch_size == 32)
558 {
559 if (CONST_STRNEQ (*l, "elf32-sparc"))
560 break;
561 }
562 else
563 {
564 if (CONST_STRNEQ (*l, "elf64-sparc"))
565 break;
566 }
567 }
568 if (*l == NULL)
569 as_fatal (_("No compiled in support for %d bit object file format"),
570 sparc_arch_size);
571 free (list);
572
573 if (sparc_arch_size == 64
574 && max_architecture < SPARC_OPCODE_ARCH_V9)
575 max_architecture = SPARC_OPCODE_ARCH_V9;
576 }
577 break;
578
579 case OPTION_TSO:
580 sparc_memory_model = MM_TSO;
581 break;
582
583 case OPTION_PSO:
584 sparc_memory_model = MM_PSO;
585 break;
586
587 case OPTION_RMO:
588 sparc_memory_model = MM_RMO;
589 break;
590
591 case 'V':
592 print_version_id ();
593 break;
594
595 case 'Q':
596 /* Qy - do emit .comment
597 Qn - do not emit .comment. */
598 break;
599
600 case 's':
601 /* Use .stab instead of .stab.excl. */
602 break;
603
604 case 'q':
605 /* quick -- Native assembler does fewer checks. */
606 break;
607
608 case 'K':
609 if (strcmp (arg, "PIC") != 0)
610 as_warn (_("Unrecognized option following -K"));
611 else
612 sparc_pic_code = 1;
613 break;
614
615 case OPTION_NO_UNDECLARED_REGS:
616 no_undeclared_regs = 1;
617 break;
618
619 case OPTION_UNDECLARED_REGS:
620 no_undeclared_regs = 0;
621 break;
622 #endif
623
624 case OPTION_RELAX:
625 sparc_relax = 1;
626 break;
627
628 case OPTION_NO_RELAX:
629 sparc_relax = 0;
630 break;
631
632 default:
633 return 0;
634 }
635
636 return 1;
637 }
638
639 void
640 md_show_usage (FILE *stream)
641 {
642 const struct sparc_arch *arch;
643 int column;
644
645 /* We don't get a chance to initialize anything before we're called,
646 so handle that now. */
647 if (! default_init_p)
648 init_default_arch ();
649
650 fprintf (stream, _("SPARC options:\n"));
651 column = 0;
652 for (arch = &sparc_arch_table[0]; arch->name; arch++)
653 {
654 if (!arch->user_option_p)
655 continue;
656 if (arch != &sparc_arch_table[0])
657 fprintf (stream, " | ");
658 if (column + strlen (arch->name) > 70)
659 {
660 column = 0;
661 fputc ('\n', stream);
662 }
663 column += 5 + 2 + strlen (arch->name);
664 fprintf (stream, "-A%s", arch->name);
665 }
666 for (arch = &sparc_arch_table[0]; arch->name; arch++)
667 {
668 if (!arch->user_option_p)
669 continue;
670 fprintf (stream, " | ");
671 if (column + strlen (arch->name) > 65)
672 {
673 column = 0;
674 fputc ('\n', stream);
675 }
676 column += 5 + 7 + strlen (arch->name);
677 fprintf (stream, "-xarch=%s", arch->name);
678 }
679 fprintf (stream, _("\n\
680 specify variant of SPARC architecture\n\
681 -bump warn when assembler switches architectures\n\
682 -sparc ignored\n\
683 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
684 -relax relax jumps and branches (default)\n\
685 -no-relax avoid changing any jumps and branches\n"));
686 #ifdef OBJ_AOUT
687 fprintf (stream, _("\
688 -k generate PIC\n"));
689 #endif
690 #ifdef OBJ_ELF
691 fprintf (stream, _("\
692 -32 create 32 bit object file\n\
693 -64 create 64 bit object file\n"));
694 fprintf (stream, _("\
695 [default is %d]\n"), default_arch_size);
696 fprintf (stream, _("\
697 -TSO use Total Store Ordering\n\
698 -PSO use Partial Store Ordering\n\
699 -RMO use Relaxed Memory Ordering\n"));
700 fprintf (stream, _("\
701 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
702 fprintf (stream, _("\
703 -KPIC generate PIC\n\
704 -V print assembler version number\n\
705 -undeclared-regs ignore application global register usage without\n\
706 appropriate .register directive (default)\n\
707 -no-undeclared-regs force error on application global register usage\n\
708 without appropriate .register directive\n\
709 -q ignored\n\
710 -Qy, -Qn ignored\n\
711 -s ignored\n"));
712 #endif
713 #ifdef SPARC_BIENDIAN
714 fprintf (stream, _("\
715 -EL generate code for a little endian machine\n\
716 -EB generate code for a big endian machine\n\
717 --little-endian-data generate code for a machine having big endian\n\
718 instructions and little endian data.\n"));
719 #endif
720 }
721 \f
722 /* Native operand size opcode translation. */
723 struct
724 {
725 char *name;
726 char *name32;
727 char *name64;
728 } native_op_table[] =
729 {
730 {"ldn", "ld", "ldx"},
731 {"ldna", "lda", "ldxa"},
732 {"stn", "st", "stx"},
733 {"stna", "sta", "stxa"},
734 {"slln", "sll", "sllx"},
735 {"srln", "srl", "srlx"},
736 {"sran", "sra", "srax"},
737 {"casn", "cas", "casx"},
738 {"casna", "casa", "casxa"},
739 {"clrn", "clr", "clrx"},
740 {NULL, NULL, NULL},
741 };
742 \f
743 /* sparc64 privileged and hyperprivileged registers. */
744
745 struct priv_reg_entry
746 {
747 char *name;
748 int regnum;
749 };
750
751 struct priv_reg_entry priv_reg_table[] =
752 {
753 {"tpc", 0},
754 {"tnpc", 1},
755 {"tstate", 2},
756 {"tt", 3},
757 {"tick", 4},
758 {"tba", 5},
759 {"pstate", 6},
760 {"tl", 7},
761 {"pil", 8},
762 {"cwp", 9},
763 {"cansave", 10},
764 {"canrestore", 11},
765 {"cleanwin", 12},
766 {"otherwin", 13},
767 {"wstate", 14},
768 {"fq", 15},
769 {"gl", 16},
770 {"ver", 31},
771 {"", -1}, /* End marker. */
772 };
773
774 struct priv_reg_entry hpriv_reg_table[] =
775 {
776 {"hpstate", 0},
777 {"htstate", 1},
778 {"hintp", 3},
779 {"htba", 5},
780 {"hver", 6},
781 {"hstick_cmpr", 31},
782 {"", -1}, /* End marker. */
783 };
784
785 /* v9a specific asrs. This table is ordered by initial
786 letter, in reverse. */
787
788 struct priv_reg_entry v9a_asr_table[] =
789 {
790 {"tick_cmpr", 23},
791 {"sys_tick_cmpr", 25},
792 {"sys_tick", 24},
793 {"stick_cmpr", 25},
794 {"stick", 24},
795 {"softint_clear", 21},
796 {"softint_set", 20},
797 {"softint", 22},
798 {"set_softint", 20},
799 {"pic", 17},
800 {"pcr", 16},
801 {"gsr", 19},
802 {"dcr", 18},
803 {"cps", 28},
804 {"clear_softint", 21},
805 {"", -1}, /* End marker. */
806 };
807
808 static int
809 cmp_reg_entry (const void *parg, const void *qarg)
810 {
811 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
812 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
813
814 return strcmp (q->name, p->name);
815 }
816 \f
817 /* This function is called once, at assembler startup time. It should
818 set up all the tables, etc. that the MD part of the assembler will
819 need. */
820
821 void
822 md_begin (void)
823 {
824 register const char *retval = NULL;
825 int lose = 0;
826 register unsigned int i = 0;
827
828 /* We don't get a chance to initialize anything before md_parse_option
829 is called, and it may not be called, so handle default initialization
830 now if not already done. */
831 if (! default_init_p)
832 init_default_arch ();
833
834 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
835 op_hash = hash_new ();
836
837 while (i < (unsigned int) sparc_num_opcodes)
838 {
839 const char *name = sparc_opcodes[i].name;
840 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
841 if (retval != NULL)
842 {
843 as_bad (_("Internal error: can't hash `%s': %s\n"),
844 sparc_opcodes[i].name, retval);
845 lose = 1;
846 }
847 do
848 {
849 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
850 {
851 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
852 sparc_opcodes[i].name, sparc_opcodes[i].args);
853 lose = 1;
854 }
855 ++i;
856 }
857 while (i < (unsigned int) sparc_num_opcodes
858 && !strcmp (sparc_opcodes[i].name, name));
859 }
860
861 for (i = 0; native_op_table[i].name; i++)
862 {
863 const struct sparc_opcode *insn;
864 char *name = ((sparc_arch_size == 32)
865 ? native_op_table[i].name32
866 : native_op_table[i].name64);
867 insn = (struct sparc_opcode *) hash_find (op_hash, name);
868 if (insn == NULL)
869 {
870 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
871 name, native_op_table[i].name);
872 lose = 1;
873 }
874 else
875 {
876 retval = hash_insert (op_hash, native_op_table[i].name,
877 (void *) insn);
878 if (retval != NULL)
879 {
880 as_bad (_("Internal error: can't hash `%s': %s\n"),
881 sparc_opcodes[i].name, retval);
882 lose = 1;
883 }
884 }
885 }
886
887 if (lose)
888 as_fatal (_("Broken assembler. No assembly attempted."));
889
890 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
891 sizeof (priv_reg_table[0]), cmp_reg_entry);
892
893 /* If -bump, record the architecture level at which we start issuing
894 warnings. The behaviour is different depending upon whether an
895 architecture was explicitly specified. If it wasn't, we issue warnings
896 for all upwards bumps. If it was, we don't start issuing warnings until
897 we need to bump beyond the requested architecture or when we bump between
898 conflicting architectures. */
899
900 if (warn_on_bump
901 && architecture_requested)
902 {
903 /* `max_architecture' records the requested architecture.
904 Issue warnings if we go above it. */
905 warn_after_architecture = max_architecture;
906
907 /* Find the highest architecture level that doesn't conflict with
908 the requested one. */
909 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
910 max_architecture > warn_after_architecture;
911 --max_architecture)
912 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
913 warn_after_architecture))
914 break;
915 }
916 }
917
918 /* Called after all assembly has been done. */
919
920 void
921 sparc_md_end (void)
922 {
923 unsigned long mach = bfd_mach_sparc;
924
925 if (sparc_arch_size == 64)
926 switch (current_architecture)
927 {
928 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
929 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
930 default: mach = bfd_mach_sparc_v9; break;
931 }
932 else
933 switch (current_architecture)
934 {
935 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
936 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
937 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
938 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
939 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
940 be but for now it is (since that's the way it's always been
941 treated). */
942 default: break;
943 }
944 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
945
946 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
947 if (hwcap_seen)
948 {
949 int bits = 0;
950
951 if (hwcap_seen & F_MUL32)
952 bits |= ELF_SPARC_HWCAP_MUL32;
953 if (hwcap_seen & F_DIV32)
954 bits |= ELF_SPARC_HWCAP_DIV32;
955 if (hwcap_seen & F_FSMULD)
956 bits |= ELF_SPARC_HWCAP_FSMULD;
957 if (hwcap_seen & F_V8PLUS)
958 bits |= ELF_SPARC_HWCAP_V8PLUS;
959 if (hwcap_seen & F_POPC)
960 bits |= ELF_SPARC_HWCAP_POPC;
961 if (hwcap_seen & F_VIS)
962 bits |= ELF_SPARC_HWCAP_VIS;
963 if (hwcap_seen & F_VIS2)
964 bits |= ELF_SPARC_HWCAP_VIS2;
965 if (hwcap_seen & F_ASI_BLK_INIT)
966 bits |= ELF_SPARC_HWCAP_ASI_BLK_INIT;
967 if (hwcap_seen & F_FMAF)
968 bits |= ELF_SPARC_HWCAP_FMAF;
969 if (hwcap_seen & F_VIS3)
970 bits |= ELF_SPARC_HWCAP_VIS3;
971 if (hwcap_seen & F_HPC)
972 bits |= ELF_SPARC_HWCAP_HPC;
973 if (hwcap_seen & F_RANDOM)
974 bits |= ELF_SPARC_HWCAP_RANDOM;
975 if (hwcap_seen & F_TRANS)
976 bits |= ELF_SPARC_HWCAP_TRANS;
977 if (hwcap_seen & F_FJFMAU)
978 bits |= ELF_SPARC_HWCAP_FJFMAU;
979 if (hwcap_seen & F_IMA)
980 bits |= ELF_SPARC_HWCAP_IMA;
981 if (hwcap_seen & F_ASI_CACHE_SPARING)
982 bits |= ELF_SPARC_HWCAP_ASI_CACHE_SPARING;
983
984 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, bits);
985 }
986 #endif
987 }
988 \f
989 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
990
991 static inline int
992 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
993 {
994 if (max <= 0)
995 abort ();
996 /* Sign-extend the value from the architecture word size, so that
997 0xffffffff is always considered -1 on sparc32. */
998 if (sparc_arch_size == 32)
999 {
1000 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
1001 val = ((val & U0xffffffff) ^ sign) - sign;
1002 }
1003 if (val > max)
1004 return 0;
1005 if (val < ~max)
1006 return 0;
1007 return 1;
1008 }
1009
1010 /* Return non-zero if VAL is in the range 0 to MAX. */
1011
1012 static inline int
1013 in_unsigned_range (bfd_vma val, bfd_vma max)
1014 {
1015 if (val > max)
1016 return 0;
1017 return 1;
1018 }
1019
1020 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1021 (e.g. -15 to +31). */
1022
1023 static inline int
1024 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
1025 {
1026 if (max <= 0)
1027 abort ();
1028 if (val > max)
1029 return 0;
1030 if (val < ~(max >> 1))
1031 return 0;
1032 return 1;
1033 }
1034
1035 static int
1036 sparc_ffs (unsigned int mask)
1037 {
1038 int i;
1039
1040 if (mask == 0)
1041 return -1;
1042
1043 for (i = 0; (mask & 1) == 0; ++i)
1044 mask >>= 1;
1045 return i;
1046 }
1047
1048 /* Implement big shift right. */
1049 static bfd_vma
1050 BSR (bfd_vma val, int amount)
1051 {
1052 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1053 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1054 return val >> amount;
1055 }
1056 \f
1057 /* For communication between sparc_ip and get_expression. */
1058 static char *expr_end;
1059
1060 /* Values for `special_case'.
1061 Instructions that require wierd handling because they're longer than
1062 4 bytes. */
1063 #define SPECIAL_CASE_NONE 0
1064 #define SPECIAL_CASE_SET 1
1065 #define SPECIAL_CASE_SETSW 2
1066 #define SPECIAL_CASE_SETX 3
1067 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1068 #define SPECIAL_CASE_FDIV 4
1069
1070 /* Bit masks of various insns. */
1071 #define NOP_INSN 0x01000000
1072 #define OR_INSN 0x80100000
1073 #define XOR_INSN 0x80180000
1074 #define FMOVS_INSN 0x81A00020
1075 #define SETHI_INSN 0x01000000
1076 #define SLLX_INSN 0x81281000
1077 #define SRA_INSN 0x81380000
1078
1079 /* The last instruction to be assembled. */
1080 static const struct sparc_opcode *last_insn;
1081 /* The assembled opcode of `last_insn'. */
1082 static unsigned long last_opcode;
1083 \f
1084 /* Handle the set and setuw synthetic instructions. */
1085
1086 static void
1087 synthetize_setuw (const struct sparc_opcode *insn)
1088 {
1089 int need_hi22_p = 0;
1090 int rd = (the_insn.opcode & RD (~0)) >> 25;
1091
1092 if (the_insn.exp.X_op == O_constant)
1093 {
1094 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1095 {
1096 if (sizeof (offsetT) > 4
1097 && (the_insn.exp.X_add_number < 0
1098 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1099 as_warn (_("set: number not in 0..4294967295 range"));
1100 }
1101 else
1102 {
1103 if (sizeof (offsetT) > 4
1104 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1105 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1106 as_warn (_("set: number not in -2147483648..4294967295 range"));
1107 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1108 }
1109 }
1110
1111 /* See if operand is absolute and small; skip sethi if so. */
1112 if (the_insn.exp.X_op != O_constant
1113 || the_insn.exp.X_add_number >= (1 << 12)
1114 || the_insn.exp.X_add_number < -(1 << 12))
1115 {
1116 the_insn.opcode = (SETHI_INSN | RD (rd)
1117 | ((the_insn.exp.X_add_number >> 10)
1118 & (the_insn.exp.X_op == O_constant
1119 ? 0x3fffff : 0)));
1120 the_insn.reloc = (the_insn.exp.X_op != O_constant
1121 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1122 output_insn (insn, &the_insn);
1123 need_hi22_p = 1;
1124 }
1125
1126 /* See if operand has no low-order bits; skip OR if so. */
1127 if (the_insn.exp.X_op != O_constant
1128 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1129 || ! need_hi22_p)
1130 {
1131 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1132 | RD (rd) | IMMED
1133 | (the_insn.exp.X_add_number
1134 & (the_insn.exp.X_op != O_constant
1135 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1136 the_insn.reloc = (the_insn.exp.X_op != O_constant
1137 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1138 output_insn (insn, &the_insn);
1139 }
1140 }
1141
1142 /* Handle the setsw synthetic instruction. */
1143
1144 static void
1145 synthetize_setsw (const struct sparc_opcode *insn)
1146 {
1147 int low32, rd, opc;
1148
1149 rd = (the_insn.opcode & RD (~0)) >> 25;
1150
1151 if (the_insn.exp.X_op != O_constant)
1152 {
1153 synthetize_setuw (insn);
1154
1155 /* Need to sign extend it. */
1156 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1157 the_insn.reloc = BFD_RELOC_NONE;
1158 output_insn (insn, &the_insn);
1159 return;
1160 }
1161
1162 if (sizeof (offsetT) > 4
1163 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1164 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1165 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1166
1167 low32 = the_insn.exp.X_add_number;
1168
1169 if (low32 >= 0)
1170 {
1171 synthetize_setuw (insn);
1172 return;
1173 }
1174
1175 opc = OR_INSN;
1176
1177 the_insn.reloc = BFD_RELOC_NONE;
1178 /* See if operand is absolute and small; skip sethi if so. */
1179 if (low32 < -(1 << 12))
1180 {
1181 the_insn.opcode = (SETHI_INSN | RD (rd)
1182 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1183 output_insn (insn, &the_insn);
1184 low32 = 0x1c00 | (low32 & 0x3ff);
1185 opc = RS1 (rd) | XOR_INSN;
1186 }
1187
1188 the_insn.opcode = (opc | RD (rd) | IMMED
1189 | (low32 & 0x1fff));
1190 output_insn (insn, &the_insn);
1191 }
1192
1193 /* Handle the setsw synthetic instruction. */
1194
1195 static void
1196 synthetize_setx (const struct sparc_opcode *insn)
1197 {
1198 int upper32, lower32;
1199 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1200 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1201 int upper_dstreg;
1202 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1203 int need_xor10_p = 0;
1204
1205 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1206 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1207 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1208 #undef SIGNEXT32
1209
1210 upper_dstreg = tmpreg;
1211 /* The tmp reg should not be the dst reg. */
1212 if (tmpreg == dstreg)
1213 as_warn (_("setx: temporary register same as destination register"));
1214
1215 /* ??? Obviously there are other optimizations we can do
1216 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1217 doing some of these. Later. If you do change things, try to
1218 change all of this to be table driven as well. */
1219 /* What to output depends on the number if it's constant.
1220 Compute that first, then output what we've decided upon. */
1221 if (the_insn.exp.X_op != O_constant)
1222 {
1223 if (sparc_arch_size == 32)
1224 {
1225 /* When arch size is 32, we want setx to be equivalent
1226 to setuw for anything but constants. */
1227 the_insn.exp.X_add_number &= 0xffffffff;
1228 synthetize_setuw (insn);
1229 return;
1230 }
1231 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1232 lower32 = 0;
1233 upper32 = 0;
1234 }
1235 else
1236 {
1237 /* Reset X_add_number, we've extracted it as upper32/lower32.
1238 Otherwise fixup_segment will complain about not being able to
1239 write an 8 byte number in a 4 byte field. */
1240 the_insn.exp.X_add_number = 0;
1241
1242 /* Only need hh22 if `or' insn can't handle constant. */
1243 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1244 need_hh22_p = 1;
1245
1246 /* Does bottom part (after sethi) have bits? */
1247 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1248 /* No hh22, but does upper32 still have bits we can't set
1249 from lower32? */
1250 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1251 need_hm10_p = 1;
1252
1253 /* If the lower half is all zero, we build the upper half directly
1254 into the dst reg. */
1255 if (lower32 != 0
1256 /* Need lower half if number is zero or 0xffffffff00000000. */
1257 || (! need_hh22_p && ! need_hm10_p))
1258 {
1259 /* No need for sethi if `or' insn can handle constant. */
1260 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1261 /* Note that we can't use a negative constant in the `or'
1262 insn unless the upper 32 bits are all ones. */
1263 || (lower32 < 0 && upper32 != -1)
1264 || (lower32 >= 0 && upper32 == -1))
1265 need_hi22_p = 1;
1266
1267 if (need_hi22_p && upper32 == -1)
1268 need_xor10_p = 1;
1269
1270 /* Does bottom part (after sethi) have bits? */
1271 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1272 /* No sethi. */
1273 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1274 /* Need `or' if we didn't set anything else. */
1275 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1276 need_lo10_p = 1;
1277 }
1278 else
1279 /* Output directly to dst reg if lower 32 bits are all zero. */
1280 upper_dstreg = dstreg;
1281 }
1282
1283 if (!upper_dstreg && dstreg)
1284 as_warn (_("setx: illegal temporary register g0"));
1285
1286 if (need_hh22_p)
1287 {
1288 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1289 | ((upper32 >> 10) & 0x3fffff));
1290 the_insn.reloc = (the_insn.exp.X_op != O_constant
1291 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1292 output_insn (insn, &the_insn);
1293 }
1294
1295 if (need_hi22_p)
1296 {
1297 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1298 | (((need_xor10_p ? ~lower32 : lower32)
1299 >> 10) & 0x3fffff));
1300 the_insn.reloc = (the_insn.exp.X_op != O_constant
1301 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1302 output_insn (insn, &the_insn);
1303 }
1304
1305 if (need_hm10_p)
1306 {
1307 the_insn.opcode = (OR_INSN
1308 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1309 | RD (upper_dstreg)
1310 | IMMED
1311 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1312 the_insn.reloc = (the_insn.exp.X_op != O_constant
1313 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1314 output_insn (insn, &the_insn);
1315 }
1316
1317 if (need_lo10_p)
1318 {
1319 /* FIXME: One nice optimization to do here is to OR the low part
1320 with the highpart if hi22 isn't needed and the low part is
1321 positive. */
1322 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1323 | RD (dstreg)
1324 | IMMED
1325 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1326 the_insn.reloc = (the_insn.exp.X_op != O_constant
1327 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1328 output_insn (insn, &the_insn);
1329 }
1330
1331 /* If we needed to build the upper part, shift it into place. */
1332 if (need_hh22_p || need_hm10_p)
1333 {
1334 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1335 | IMMED | 32);
1336 the_insn.reloc = BFD_RELOC_NONE;
1337 output_insn (insn, &the_insn);
1338 }
1339
1340 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1341 if (need_xor10_p)
1342 {
1343 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1344 | 0x1c00 | (lower32 & 0x3ff));
1345 the_insn.reloc = BFD_RELOC_NONE;
1346 output_insn (insn, &the_insn);
1347 }
1348
1349 /* If we needed to build both upper and lower parts, OR them together. */
1350 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1351 {
1352 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1353 | RD (dstreg));
1354 the_insn.reloc = BFD_RELOC_NONE;
1355 output_insn (insn, &the_insn);
1356 }
1357 }
1358 \f
1359 /* Main entry point to assemble one instruction. */
1360
1361 void
1362 md_assemble (char *str)
1363 {
1364 const struct sparc_opcode *insn;
1365 int special_case;
1366
1367 know (str);
1368 special_case = sparc_ip (str, &insn);
1369 if (insn == NULL)
1370 return;
1371
1372 /* We warn about attempts to put a floating point branch in a delay slot,
1373 unless the delay slot has been annulled. */
1374 if (last_insn != NULL
1375 && (insn->flags & F_FBR) != 0
1376 && (last_insn->flags & F_DELAYED) != 0
1377 /* ??? This test isn't completely accurate. We assume anything with
1378 F_{UNBR,CONDBR,FBR} set is annullable. */
1379 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1380 || (last_opcode & ANNUL) == 0))
1381 as_warn (_("FP branch in delay slot"));
1382
1383 /* SPARC before v9 requires a nop instruction between a floating
1384 point instruction and a floating point branch. We insert one
1385 automatically, with a warning. */
1386 if (max_architecture < SPARC_OPCODE_ARCH_V9
1387 && last_insn != NULL
1388 && (insn->flags & F_FBR) != 0
1389 && (last_insn->flags & F_FLOAT) != 0)
1390 {
1391 struct sparc_it nop_insn;
1392
1393 nop_insn.opcode = NOP_INSN;
1394 nop_insn.reloc = BFD_RELOC_NONE;
1395 output_insn (insn, &nop_insn);
1396 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1397 }
1398
1399 switch (special_case)
1400 {
1401 case SPECIAL_CASE_NONE:
1402 /* Normal insn. */
1403 output_insn (insn, &the_insn);
1404 break;
1405
1406 case SPECIAL_CASE_SETSW:
1407 synthetize_setsw (insn);
1408 break;
1409
1410 case SPECIAL_CASE_SET:
1411 synthetize_setuw (insn);
1412 break;
1413
1414 case SPECIAL_CASE_SETX:
1415 synthetize_setx (insn);
1416 break;
1417
1418 case SPECIAL_CASE_FDIV:
1419 {
1420 int rd = (the_insn.opcode >> 25) & 0x1f;
1421
1422 output_insn (insn, &the_insn);
1423
1424 /* According to information leaked from Sun, the "fdiv" instructions
1425 on early SPARC machines would produce incorrect results sometimes.
1426 The workaround is to add an fmovs of the destination register to
1427 itself just after the instruction. This was true on machines
1428 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1429 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1430 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1431 output_insn (insn, &the_insn);
1432 return;
1433 }
1434
1435 default:
1436 as_fatal (_("failed special case insn sanity check"));
1437 }
1438 }
1439
1440 static const char *
1441 get_hwcap_name (int mask)
1442 {
1443 if (mask & F_MUL32)
1444 return "mul32";
1445 if (mask & F_DIV32)
1446 return "div32";
1447 if (mask & F_FSMULD)
1448 return "fsmuld";
1449 if (mask & F_V8PLUS)
1450 return "v8plus";
1451 if (mask & F_POPC)
1452 return "popc";
1453 if (mask & F_VIS)
1454 return "vis";
1455 if (mask & F_VIS2)
1456 return "vis2";
1457 if (mask & F_ASI_BLK_INIT)
1458 return "ASIBlkInit";
1459 if (mask & F_FMAF)
1460 return "fmaf";
1461 if (mask & F_VIS3)
1462 return "vis3";
1463 if (mask & F_HPC)
1464 return "hpc";
1465 if (mask & F_RANDOM)
1466 return "random";
1467 if (mask & F_TRANS)
1468 return "trans";
1469 if (mask & F_FJFMAU)
1470 return "fjfmau";
1471 if (mask & F_IMA)
1472 return "ima";
1473 if (mask & F_ASI_CACHE_SPARING)
1474 return "cspare";
1475 return "UNKNOWN";
1476 }
1477
1478 /* Subroutine of md_assemble to do the actual parsing. */
1479
1480 static int
1481 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1482 {
1483 char *error_message = "";
1484 char *s;
1485 const char *args;
1486 char c;
1487 const struct sparc_opcode *insn;
1488 char *argsStart;
1489 unsigned long opcode;
1490 unsigned int mask = 0;
1491 int match = 0;
1492 int comma = 0;
1493 int v9_arg_p;
1494 int special_case = SPECIAL_CASE_NONE;
1495
1496 s = str;
1497 if (ISLOWER (*s))
1498 {
1499 do
1500 ++s;
1501 while (ISLOWER (*s) || ISDIGIT (*s));
1502 }
1503
1504 switch (*s)
1505 {
1506 case '\0':
1507 break;
1508
1509 case ',':
1510 comma = 1;
1511 /* Fall through. */
1512
1513 case ' ':
1514 *s++ = '\0';
1515 break;
1516
1517 default:
1518 as_bad (_("Unknown opcode: `%s'"), str);
1519 *pinsn = NULL;
1520 return special_case;
1521 }
1522 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1523 *pinsn = insn;
1524 if (insn == NULL)
1525 {
1526 as_bad (_("Unknown opcode: `%s'"), str);
1527 return special_case;
1528 }
1529 if (comma)
1530 {
1531 *--s = ',';
1532 }
1533
1534 argsStart = s;
1535 for (;;)
1536 {
1537 opcode = insn->match;
1538 memset (&the_insn, '\0', sizeof (the_insn));
1539 the_insn.reloc = BFD_RELOC_NONE;
1540 v9_arg_p = 0;
1541
1542 /* Build the opcode, checking as we go to make sure that the
1543 operands match. */
1544 for (args = insn->args;; ++args)
1545 {
1546 switch (*args)
1547 {
1548 case 'K':
1549 {
1550 int kmask = 0;
1551
1552 /* Parse a series of masks. */
1553 if (*s == '#')
1554 {
1555 while (*s == '#')
1556 {
1557 int jmask;
1558
1559 if (! parse_keyword_arg (sparc_encode_membar, &s,
1560 &jmask))
1561 {
1562 error_message = _(": invalid membar mask name");
1563 goto error;
1564 }
1565 kmask |= jmask;
1566 while (*s == ' ')
1567 ++s;
1568 if (*s == '|' || *s == '+')
1569 ++s;
1570 while (*s == ' ')
1571 ++s;
1572 }
1573 }
1574 else
1575 {
1576 if (! parse_const_expr_arg (&s, &kmask))
1577 {
1578 error_message = _(": invalid membar mask expression");
1579 goto error;
1580 }
1581 if (kmask < 0 || kmask > 127)
1582 {
1583 error_message = _(": invalid membar mask number");
1584 goto error;
1585 }
1586 }
1587
1588 opcode |= MEMBAR (kmask);
1589 continue;
1590 }
1591
1592 case '3':
1593 {
1594 int smask = 0;
1595
1596 if (! parse_const_expr_arg (&s, &smask))
1597 {
1598 error_message = _(": invalid siam mode expression");
1599 goto error;
1600 }
1601 if (smask < 0 || smask > 7)
1602 {
1603 error_message = _(": invalid siam mode number");
1604 goto error;
1605 }
1606 opcode |= smask;
1607 continue;
1608 }
1609
1610 case '*':
1611 {
1612 int fcn = 0;
1613
1614 /* Parse a prefetch function. */
1615 if (*s == '#')
1616 {
1617 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1618 {
1619 error_message = _(": invalid prefetch function name");
1620 goto error;
1621 }
1622 }
1623 else
1624 {
1625 if (! parse_const_expr_arg (&s, &fcn))
1626 {
1627 error_message = _(": invalid prefetch function expression");
1628 goto error;
1629 }
1630 if (fcn < 0 || fcn > 31)
1631 {
1632 error_message = _(": invalid prefetch function number");
1633 goto error;
1634 }
1635 }
1636 opcode |= RD (fcn);
1637 continue;
1638 }
1639
1640 case '!':
1641 case '?':
1642 /* Parse a sparc64 privileged register. */
1643 if (*s == '%')
1644 {
1645 struct priv_reg_entry *p = priv_reg_table;
1646 unsigned int len = 9999999; /* Init to make gcc happy. */
1647
1648 s += 1;
1649 while (p->name[0] > s[0])
1650 p++;
1651 while (p->name[0] == s[0])
1652 {
1653 len = strlen (p->name);
1654 if (strncmp (p->name, s, len) == 0)
1655 break;
1656 p++;
1657 }
1658 if (p->name[0] != s[0])
1659 {
1660 error_message = _(": unrecognizable privileged register");
1661 goto error;
1662 }
1663 if (*args == '?')
1664 opcode |= (p->regnum << 14);
1665 else
1666 opcode |= (p->regnum << 25);
1667 s += len;
1668 continue;
1669 }
1670 else
1671 {
1672 error_message = _(": unrecognizable privileged register");
1673 goto error;
1674 }
1675
1676 case '$':
1677 case '%':
1678 /* Parse a sparc64 hyperprivileged register. */
1679 if (*s == '%')
1680 {
1681 struct priv_reg_entry *p = hpriv_reg_table;
1682 unsigned int len = 9999999; /* Init to make gcc happy. */
1683
1684 s += 1;
1685 while (p->name[0] > s[0])
1686 p++;
1687 while (p->name[0] == s[0])
1688 {
1689 len = strlen (p->name);
1690 if (strncmp (p->name, s, len) == 0)
1691 break;
1692 p++;
1693 }
1694 if (p->name[0] != s[0])
1695 {
1696 error_message = _(": unrecognizable hyperprivileged register");
1697 goto error;
1698 }
1699 if (*args == '$')
1700 opcode |= (p->regnum << 14);
1701 else
1702 opcode |= (p->regnum << 25);
1703 s += len;
1704 continue;
1705 }
1706 else
1707 {
1708 error_message = _(": unrecognizable hyperprivileged register");
1709 goto error;
1710 }
1711
1712 case '_':
1713 case '/':
1714 /* Parse a v9a/v9b ancillary state register. */
1715 if (*s == '%')
1716 {
1717 struct priv_reg_entry *p = v9a_asr_table;
1718 unsigned int len = 9999999; /* Init to make gcc happy. */
1719
1720 s += 1;
1721 while (p->name[0] > s[0])
1722 p++;
1723 while (p->name[0] == s[0])
1724 {
1725 len = strlen (p->name);
1726 if (strncmp (p->name, s, len) == 0)
1727 break;
1728 p++;
1729 }
1730 if (p->name[0] != s[0])
1731 {
1732 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1733 goto error;
1734 }
1735 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1736 {
1737 error_message = _(": rd on write only ancillary state register");
1738 goto error;
1739 }
1740 if (p->regnum >= 24
1741 && (insn->architecture
1742 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1743 {
1744 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1745 error_message = _(": unrecognizable v9a ancillary state register");
1746 goto error;
1747 }
1748 if (*args == '/')
1749 opcode |= (p->regnum << 14);
1750 else
1751 opcode |= (p->regnum << 25);
1752 s += len;
1753 continue;
1754 }
1755 else
1756 {
1757 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1758 goto error;
1759 }
1760
1761 case 'M':
1762 case 'm':
1763 if (strncmp (s, "%asr", 4) == 0)
1764 {
1765 s += 4;
1766
1767 if (ISDIGIT (*s))
1768 {
1769 long num = 0;
1770
1771 while (ISDIGIT (*s))
1772 {
1773 num = num * 10 + *s - '0';
1774 ++s;
1775 }
1776
1777 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1778 {
1779 if (num < 16 || 31 < num)
1780 {
1781 error_message = _(": asr number must be between 16 and 31");
1782 goto error;
1783 }
1784 }
1785 else
1786 {
1787 if (num < 0 || 31 < num)
1788 {
1789 error_message = _(": asr number must be between 0 and 31");
1790 goto error;
1791 }
1792 }
1793
1794 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1795 continue;
1796 }
1797 else
1798 {
1799 error_message = _(": expecting %asrN");
1800 goto error;
1801 }
1802 } /* if %asr */
1803 break;
1804
1805 case 'I':
1806 the_insn.reloc = BFD_RELOC_SPARC_11;
1807 goto immediate;
1808
1809 case 'j':
1810 the_insn.reloc = BFD_RELOC_SPARC_10;
1811 goto immediate;
1812
1813 case 'X':
1814 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1815 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1816 the_insn.reloc = BFD_RELOC_SPARC_5;
1817 else
1818 the_insn.reloc = BFD_RELOC_SPARC13;
1819 /* These fields are unsigned, but for upward compatibility,
1820 allow negative values as well. */
1821 goto immediate;
1822
1823 case 'Y':
1824 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1825 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1826 the_insn.reloc = BFD_RELOC_SPARC_6;
1827 else
1828 the_insn.reloc = BFD_RELOC_SPARC13;
1829 /* These fields are unsigned, but for upward compatibility,
1830 allow negative values as well. */
1831 goto immediate;
1832
1833 case 'k':
1834 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1835 the_insn.pcrel = 1;
1836 goto immediate;
1837
1838 case '=':
1839 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1840 the_insn.pcrel = 1;
1841 goto immediate;
1842
1843 case 'G':
1844 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1845 the_insn.pcrel = 1;
1846 goto immediate;
1847
1848 case 'N':
1849 if (*s == 'p' && s[1] == 'n')
1850 {
1851 s += 2;
1852 continue;
1853 }
1854 break;
1855
1856 case 'T':
1857 if (*s == 'p' && s[1] == 't')
1858 {
1859 s += 2;
1860 continue;
1861 }
1862 break;
1863
1864 case 'z':
1865 if (*s == ' ')
1866 {
1867 ++s;
1868 }
1869 if (strncmp (s, "%icc", 4) == 0)
1870 {
1871 s += 4;
1872 continue;
1873 }
1874 break;
1875
1876 case 'Z':
1877 if (*s == ' ')
1878 {
1879 ++s;
1880 }
1881 if (strncmp (s, "%xcc", 4) == 0)
1882 {
1883 s += 4;
1884 continue;
1885 }
1886 break;
1887
1888 case '6':
1889 if (*s == ' ')
1890 {
1891 ++s;
1892 }
1893 if (strncmp (s, "%fcc0", 5) == 0)
1894 {
1895 s += 5;
1896 continue;
1897 }
1898 break;
1899
1900 case '7':
1901 if (*s == ' ')
1902 {
1903 ++s;
1904 }
1905 if (strncmp (s, "%fcc1", 5) == 0)
1906 {
1907 s += 5;
1908 continue;
1909 }
1910 break;
1911
1912 case '8':
1913 if (*s == ' ')
1914 {
1915 ++s;
1916 }
1917 if (strncmp (s, "%fcc2", 5) == 0)
1918 {
1919 s += 5;
1920 continue;
1921 }
1922 break;
1923
1924 case '9':
1925 if (*s == ' ')
1926 {
1927 ++s;
1928 }
1929 if (strncmp (s, "%fcc3", 5) == 0)
1930 {
1931 s += 5;
1932 continue;
1933 }
1934 break;
1935
1936 case 'P':
1937 if (strncmp (s, "%pc", 3) == 0)
1938 {
1939 s += 3;
1940 continue;
1941 }
1942 break;
1943
1944 case 'W':
1945 if (strncmp (s, "%tick", 5) == 0)
1946 {
1947 s += 5;
1948 continue;
1949 }
1950 break;
1951
1952 case '\0': /* End of args. */
1953 if (s[0] == ',' && s[1] == '%')
1954 {
1955 static const struct ops
1956 {
1957 /* The name as it appears in assembler. */
1958 char *name;
1959 /* strlen (name), precomputed for speed */
1960 int len;
1961 /* The reloc this pseudo-op translates to. */
1962 int reloc;
1963 /* 1 if tls call. */
1964 int tls_call;
1965 }
1966 ops[] =
1967 {
1968 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
1969 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
1970 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
1971 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
1972 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
1973 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
1974 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
1975 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
1976 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
1977 { NULL, 0, 0, 0 }
1978 };
1979 const struct ops *o;
1980 char *s1;
1981 int npar = 0;
1982
1983 for (o = ops; o->name; o++)
1984 if (strncmp (s + 2, o->name, o->len) == 0)
1985 break;
1986 if (o->name == NULL)
1987 break;
1988
1989 if (s[o->len + 2] != '(')
1990 {
1991 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
1992 return special_case;
1993 }
1994
1995 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
1996 {
1997 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1998 o->name);
1999 return special_case;
2000 }
2001
2002 if (o->tls_call
2003 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2004 || the_insn.exp.X_add_number != 0
2005 || the_insn.exp.X_add_symbol
2006 != symbol_find_or_make ("__tls_get_addr")))
2007 {
2008 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2009 o->name);
2010 return special_case;
2011 }
2012
2013 the_insn.reloc = o->reloc;
2014 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2015 s += o->len + 3;
2016
2017 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2018 if (*s1 == '(')
2019 npar++;
2020 else if (*s1 == ')')
2021 {
2022 if (!npar)
2023 break;
2024 npar--;
2025 }
2026
2027 if (*s1 != ')')
2028 {
2029 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2030 return special_case;
2031 }
2032
2033 *s1 = '\0';
2034 (void) get_expression (s);
2035 *s1 = ')';
2036 s = s1 + 1;
2037 }
2038 if (*s == '\0')
2039 match = 1;
2040 break;
2041
2042 case '+':
2043 if (*s == '+')
2044 {
2045 ++s;
2046 continue;
2047 }
2048 if (*s == '-')
2049 {
2050 continue;
2051 }
2052 break;
2053
2054 case '[': /* These must match exactly. */
2055 case ']':
2056 case ',':
2057 case ' ':
2058 if (*s++ == *args)
2059 continue;
2060 break;
2061
2062 case '#': /* Must be at least one digit. */
2063 if (ISDIGIT (*s++))
2064 {
2065 while (ISDIGIT (*s))
2066 {
2067 ++s;
2068 }
2069 continue;
2070 }
2071 break;
2072
2073 case 'C': /* Coprocessor state register. */
2074 if (strncmp (s, "%csr", 4) == 0)
2075 {
2076 s += 4;
2077 continue;
2078 }
2079 break;
2080
2081 case 'b': /* Next operand is a coprocessor register. */
2082 case 'c':
2083 case 'D':
2084 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2085 {
2086 mask = *s++;
2087 if (ISDIGIT (*s))
2088 {
2089 mask = 10 * (mask - '0') + (*s++ - '0');
2090 if (mask >= 32)
2091 {
2092 break;
2093 }
2094 }
2095 else
2096 {
2097 mask -= '0';
2098 }
2099 switch (*args)
2100 {
2101
2102 case 'b':
2103 opcode |= mask << 14;
2104 continue;
2105
2106 case 'c':
2107 opcode |= mask;
2108 continue;
2109
2110 case 'D':
2111 opcode |= mask << 25;
2112 continue;
2113 }
2114 }
2115 break;
2116
2117 case 'r': /* next operand must be a register */
2118 case 'O':
2119 case '1':
2120 case '2':
2121 case 'd':
2122 if (*s++ == '%')
2123 {
2124 switch (c = *s++)
2125 {
2126
2127 case 'f': /* frame pointer */
2128 if (*s++ == 'p')
2129 {
2130 mask = 0x1e;
2131 break;
2132 }
2133 goto error;
2134
2135 case 'g': /* global register */
2136 c = *s++;
2137 if (isoctal (c))
2138 {
2139 mask = c - '0';
2140 break;
2141 }
2142 goto error;
2143
2144 case 'i': /* in register */
2145 c = *s++;
2146 if (isoctal (c))
2147 {
2148 mask = c - '0' + 24;
2149 break;
2150 }
2151 goto error;
2152
2153 case 'l': /* local register */
2154 c = *s++;
2155 if (isoctal (c))
2156 {
2157 mask = (c - '0' + 16);
2158 break;
2159 }
2160 goto error;
2161
2162 case 'o': /* out register */
2163 c = *s++;
2164 if (isoctal (c))
2165 {
2166 mask = (c - '0' + 8);
2167 break;
2168 }
2169 goto error;
2170
2171 case 's': /* stack pointer */
2172 if (*s++ == 'p')
2173 {
2174 mask = 0xe;
2175 break;
2176 }
2177 goto error;
2178
2179 case 'r': /* any register */
2180 if (!ISDIGIT ((c = *s++)))
2181 {
2182 goto error;
2183 }
2184 /* FALLTHROUGH */
2185 case '0':
2186 case '1':
2187 case '2':
2188 case '3':
2189 case '4':
2190 case '5':
2191 case '6':
2192 case '7':
2193 case '8':
2194 case '9':
2195 if (ISDIGIT (*s))
2196 {
2197 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2198 {
2199 goto error;
2200 }
2201 }
2202 else
2203 {
2204 c -= '0';
2205 }
2206 mask = c;
2207 break;
2208
2209 default:
2210 goto error;
2211 }
2212
2213 if ((mask & ~1) == 2 && sparc_arch_size == 64
2214 && no_undeclared_regs && ! globals[mask])
2215 as_bad (_("detected global register use not covered by .register pseudo-op"));
2216
2217 /* Got the register, now figure out where
2218 it goes in the opcode. */
2219 switch (*args)
2220 {
2221 case '1':
2222 opcode |= mask << 14;
2223 continue;
2224
2225 case '2':
2226 opcode |= mask;
2227 continue;
2228
2229 case 'd':
2230 opcode |= mask << 25;
2231 continue;
2232
2233 case 'r':
2234 opcode |= (mask << 25) | (mask << 14);
2235 continue;
2236
2237 case 'O':
2238 opcode |= (mask << 25) | (mask << 0);
2239 continue;
2240 }
2241 }
2242 break;
2243
2244 case 'e': /* next operand is a floating point register */
2245 case 'v':
2246 case 'V':
2247
2248 case 'f':
2249 case 'B':
2250 case 'R':
2251
2252 case '4':
2253 case '5':
2254
2255 case 'g':
2256 case 'H':
2257 case 'J':
2258 {
2259 char format;
2260
2261 if (*s++ == '%'
2262 && ((format = *s) == 'f')
2263 && ISDIGIT (*++s))
2264 {
2265 for (mask = 0; ISDIGIT (*s); ++s)
2266 {
2267 mask = 10 * mask + (*s - '0');
2268 } /* read the number */
2269
2270 if ((*args == 'v'
2271 || *args == 'B'
2272 || *args == '5'
2273 || *args == 'H')
2274 && (mask & 1))
2275 {
2276 break;
2277 } /* register must be even numbered */
2278
2279 if ((*args == 'V'
2280 || *args == 'R'
2281 || *args == 'J')
2282 && (mask & 3))
2283 {
2284 break;
2285 } /* register must be multiple of 4 */
2286
2287 if (mask >= 64)
2288 {
2289 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2290 error_message = _(": There are only 64 f registers; [0-63]");
2291 else
2292 error_message = _(": There are only 32 f registers; [0-31]");
2293 goto error;
2294 } /* on error */
2295 else if (mask >= 32)
2296 {
2297 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2298 {
2299 if (*args == 'e' || *args == 'f' || *args == 'g')
2300 {
2301 error_message
2302 = _(": There are only 32 single precision f registers; [0-31]");
2303 goto error;
2304 }
2305 v9_arg_p = 1;
2306 mask -= 31; /* wrap high bit */
2307 }
2308 else
2309 {
2310 error_message = _(": There are only 32 f registers; [0-31]");
2311 goto error;
2312 }
2313 }
2314 }
2315 else
2316 {
2317 break;
2318 } /* if not an 'f' register. */
2319
2320 switch (*args)
2321 {
2322 case 'v':
2323 case 'V':
2324 case 'e':
2325 opcode |= RS1 (mask);
2326 continue;
2327
2328 case 'f':
2329 case 'B':
2330 case 'R':
2331 opcode |= RS2 (mask);
2332 continue;
2333
2334 case '4':
2335 case '5':
2336 opcode |= RS3 (mask);
2337 continue;
2338
2339 case 'g':
2340 case 'H':
2341 case 'J':
2342 opcode |= RD (mask);
2343 continue;
2344 } /* Pack it in. */
2345
2346 know (0);
2347 break;
2348 } /* float arg */
2349
2350 case 'F':
2351 if (strncmp (s, "%fsr", 4) == 0)
2352 {
2353 s += 4;
2354 continue;
2355 }
2356 break;
2357
2358 case '(':
2359 if (strncmp (s, "%efsr", 5) == 0)
2360 {
2361 s += 5;
2362 continue;
2363 }
2364 break;
2365
2366 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2367 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2368 goto immediate;
2369
2370 case 'l': /* 22 bit PC relative immediate */
2371 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2372 the_insn.pcrel = 1;
2373 goto immediate;
2374
2375 case 'L': /* 30 bit immediate */
2376 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2377 the_insn.pcrel = 1;
2378 goto immediate;
2379
2380 case 'h':
2381 case 'n': /* 22 bit immediate */
2382 the_insn.reloc = BFD_RELOC_SPARC22;
2383 goto immediate;
2384
2385 case 'i': /* 13 bit immediate */
2386 the_insn.reloc = BFD_RELOC_SPARC13;
2387
2388 /* fallthrough */
2389
2390 immediate:
2391 if (*s == ' ')
2392 s++;
2393
2394 {
2395 char *s1;
2396 char *op_arg = NULL;
2397 static expressionS op_exp;
2398 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2399
2400 /* Check for %hi, etc. */
2401 if (*s == '%')
2402 {
2403 static const struct ops {
2404 /* The name as it appears in assembler. */
2405 char *name;
2406 /* strlen (name), precomputed for speed */
2407 int len;
2408 /* The reloc this pseudo-op translates to. */
2409 int reloc;
2410 /* Non-zero if for v9 only. */
2411 int v9_p;
2412 /* Non-zero if can be used in pc-relative contexts. */
2413 int pcrel_p;/*FIXME:wip*/
2414 } ops[] = {
2415 /* hix/lox must appear before hi/lo so %hix won't be
2416 mistaken for %hi. */
2417 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2418 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2419 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2420 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2421 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2422 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2423 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2424 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2425 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2426 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2427 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2428 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2429 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2430 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2431 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2432 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2433 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2434 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2435 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2436 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2437 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2438 0 },
2439 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2440 0 },
2441 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2442 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2443 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2444 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2445 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2446 0, 0 },
2447 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2448 0, 0 },
2449 { NULL, 0, 0, 0, 0 }
2450 };
2451 const struct ops *o;
2452
2453 for (o = ops; o->name; o++)
2454 if (strncmp (s + 1, o->name, o->len) == 0)
2455 break;
2456 if (o->name == NULL)
2457 break;
2458
2459 if (s[o->len + 1] != '(')
2460 {
2461 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2462 return special_case;
2463 }
2464
2465 op_arg = o->name;
2466 the_insn.reloc = o->reloc;
2467 s += o->len + 2;
2468 v9_arg_p = o->v9_p;
2469 }
2470
2471 /* Note that if the get_expression() fails, we will still
2472 have created U entries in the symbol table for the
2473 'symbols' in the input string. Try not to create U
2474 symbols for registers, etc. */
2475
2476 /* This stuff checks to see if the expression ends in
2477 +%reg. If it does, it removes the register from
2478 the expression, and re-sets 's' to point to the
2479 right place. */
2480
2481 if (op_arg)
2482 {
2483 int npar = 0;
2484
2485 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2486 if (*s1 == '(')
2487 npar++;
2488 else if (*s1 == ')')
2489 {
2490 if (!npar)
2491 break;
2492 npar--;
2493 }
2494
2495 if (*s1 != ')')
2496 {
2497 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2498 return special_case;
2499 }
2500
2501 *s1 = '\0';
2502 (void) get_expression (s);
2503 *s1 = ')';
2504 s = s1 + 1;
2505 if (*s == ',' || *s == ']' || !*s)
2506 continue;
2507 if (*s != '+' && *s != '-')
2508 {
2509 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2510 return special_case;
2511 }
2512 *s1 = '0';
2513 s = s1;
2514 op_exp = the_insn.exp;
2515 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2516 }
2517
2518 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2519 ;
2520
2521 if (s1 != s && ISDIGIT (s1[-1]))
2522 {
2523 if (s1[-2] == '%' && s1[-3] == '+')
2524 s1 -= 3;
2525 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2526 s1 -= 4;
2527 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2528 s1 -= 5;
2529 else
2530 s1 = NULL;
2531 if (s1)
2532 {
2533 *s1 = '\0';
2534 if (op_arg && s1 == s + 1)
2535 the_insn.exp.X_op = O_absent;
2536 else
2537 (void) get_expression (s);
2538 *s1 = '+';
2539 if (op_arg)
2540 *s = ')';
2541 s = s1;
2542 }
2543 }
2544 else
2545 s1 = NULL;
2546
2547 if (!s1)
2548 {
2549 (void) get_expression (s);
2550 if (op_arg)
2551 *s = ')';
2552 s = expr_end;
2553 }
2554
2555 if (op_arg)
2556 {
2557 the_insn.exp2 = the_insn.exp;
2558 the_insn.exp = op_exp;
2559 if (the_insn.exp2.X_op == O_absent)
2560 the_insn.exp2.X_op = O_illegal;
2561 else if (the_insn.exp.X_op == O_absent)
2562 {
2563 the_insn.exp = the_insn.exp2;
2564 the_insn.exp2.X_op = O_illegal;
2565 }
2566 else if (the_insn.exp.X_op == O_constant)
2567 {
2568 valueT val = the_insn.exp.X_add_number;
2569 switch (the_insn.reloc)
2570 {
2571 default:
2572 break;
2573
2574 case BFD_RELOC_SPARC_HH22:
2575 val = BSR (val, 32);
2576 /* Fall through. */
2577
2578 case BFD_RELOC_SPARC_LM22:
2579 case BFD_RELOC_HI22:
2580 val = (val >> 10) & 0x3fffff;
2581 break;
2582
2583 case BFD_RELOC_SPARC_HM10:
2584 val = BSR (val, 32);
2585 /* Fall through. */
2586
2587 case BFD_RELOC_LO10:
2588 val &= 0x3ff;
2589 break;
2590
2591 case BFD_RELOC_SPARC_H34:
2592 val >>= 12;
2593 val &= 0x3fffff;
2594 break;
2595
2596 case BFD_RELOC_SPARC_H44:
2597 val >>= 22;
2598 val &= 0x3fffff;
2599 break;
2600
2601 case BFD_RELOC_SPARC_M44:
2602 val >>= 12;
2603 val &= 0x3ff;
2604 break;
2605
2606 case BFD_RELOC_SPARC_L44:
2607 val &= 0xfff;
2608 break;
2609
2610 case BFD_RELOC_SPARC_HIX22:
2611 val = ~val;
2612 val = (val >> 10) & 0x3fffff;
2613 break;
2614
2615 case BFD_RELOC_SPARC_LOX10:
2616 val = (val & 0x3ff) | 0x1c00;
2617 break;
2618 }
2619 the_insn.exp = the_insn.exp2;
2620 the_insn.exp.X_add_number += val;
2621 the_insn.exp2.X_op = O_illegal;
2622 the_insn.reloc = old_reloc;
2623 }
2624 else if (the_insn.exp2.X_op != O_constant)
2625 {
2626 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2627 return special_case;
2628 }
2629 else
2630 {
2631 if (old_reloc != BFD_RELOC_SPARC13
2632 || the_insn.reloc != BFD_RELOC_LO10
2633 || sparc_arch_size != 64
2634 || sparc_pic_code)
2635 {
2636 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2637 return special_case;
2638 }
2639 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2640 }
2641 }
2642 }
2643 /* Check for constants that don't require emitting a reloc. */
2644 if (the_insn.exp.X_op == O_constant
2645 && the_insn.exp.X_add_symbol == 0
2646 && the_insn.exp.X_op_symbol == 0)
2647 {
2648 /* For pc-relative call instructions, we reject
2649 constants to get better code. */
2650 if (the_insn.pcrel
2651 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2652 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2653 {
2654 error_message = _(": PC-relative operand can't be a constant");
2655 goto error;
2656 }
2657
2658 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2659 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2660 {
2661 error_message = _(": TLS operand can't be a constant");
2662 goto error;
2663 }
2664
2665 /* Constants that won't fit are checked in md_apply_fix
2666 and bfd_install_relocation.
2667 ??? It would be preferable to install the constants
2668 into the insn here and save having to create a fixS
2669 for each one. There already exists code to handle
2670 all the various cases (e.g. in md_apply_fix and
2671 bfd_install_relocation) so duplicating all that code
2672 here isn't right. */
2673 }
2674
2675 continue;
2676
2677 case 'a':
2678 if (*s++ == 'a')
2679 {
2680 opcode |= ANNUL;
2681 continue;
2682 }
2683 break;
2684
2685 case 'A':
2686 {
2687 int asi = 0;
2688
2689 /* Parse an asi. */
2690 if (*s == '#')
2691 {
2692 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2693 {
2694 error_message = _(": invalid ASI name");
2695 goto error;
2696 }
2697 }
2698 else
2699 {
2700 if (! parse_const_expr_arg (&s, &asi))
2701 {
2702 error_message = _(": invalid ASI expression");
2703 goto error;
2704 }
2705 if (asi < 0 || asi > 255)
2706 {
2707 error_message = _(": invalid ASI number");
2708 goto error;
2709 }
2710 }
2711 opcode |= ASI (asi);
2712 continue;
2713 } /* Alternate space. */
2714
2715 case 'p':
2716 if (strncmp (s, "%psr", 4) == 0)
2717 {
2718 s += 4;
2719 continue;
2720 }
2721 break;
2722
2723 case 'q': /* Floating point queue. */
2724 if (strncmp (s, "%fq", 3) == 0)
2725 {
2726 s += 3;
2727 continue;
2728 }
2729 break;
2730
2731 case 'Q': /* Coprocessor queue. */
2732 if (strncmp (s, "%cq", 3) == 0)
2733 {
2734 s += 3;
2735 continue;
2736 }
2737 break;
2738
2739 case 'S':
2740 if (strcmp (str, "set") == 0
2741 || strcmp (str, "setuw") == 0)
2742 {
2743 special_case = SPECIAL_CASE_SET;
2744 continue;
2745 }
2746 else if (strcmp (str, "setsw") == 0)
2747 {
2748 special_case = SPECIAL_CASE_SETSW;
2749 continue;
2750 }
2751 else if (strcmp (str, "setx") == 0)
2752 {
2753 special_case = SPECIAL_CASE_SETX;
2754 continue;
2755 }
2756 else if (strncmp (str, "fdiv", 4) == 0)
2757 {
2758 special_case = SPECIAL_CASE_FDIV;
2759 continue;
2760 }
2761 break;
2762
2763 case 'o':
2764 if (strncmp (s, "%asi", 4) != 0)
2765 break;
2766 s += 4;
2767 continue;
2768
2769 case 's':
2770 if (strncmp (s, "%fprs", 5) != 0)
2771 break;
2772 s += 5;
2773 continue;
2774
2775 case 'E':
2776 if (strncmp (s, "%ccr", 4) != 0)
2777 break;
2778 s += 4;
2779 continue;
2780
2781 case 't':
2782 if (strncmp (s, "%tbr", 4) != 0)
2783 break;
2784 s += 4;
2785 continue;
2786
2787 case 'w':
2788 if (strncmp (s, "%wim", 4) != 0)
2789 break;
2790 s += 4;
2791 continue;
2792
2793 case 'x':
2794 {
2795 char *push = input_line_pointer;
2796 expressionS e;
2797
2798 input_line_pointer = s;
2799 expression (&e);
2800 if (e.X_op == O_constant)
2801 {
2802 int n = e.X_add_number;
2803 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2804 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2805 else
2806 opcode |= e.X_add_number << 5;
2807 }
2808 else
2809 as_bad (_("non-immediate OPF operand, ignored"));
2810 s = input_line_pointer;
2811 input_line_pointer = push;
2812 continue;
2813 }
2814
2815 case 'y':
2816 if (strncmp (s, "%y", 2) != 0)
2817 break;
2818 s += 2;
2819 continue;
2820
2821 case 'u':
2822 case 'U':
2823 {
2824 /* Parse a sparclet cpreg. */
2825 int cpreg;
2826 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2827 {
2828 error_message = _(": invalid cpreg name");
2829 goto error;
2830 }
2831 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2832 continue;
2833 }
2834
2835 default:
2836 as_fatal (_("failed sanity check."));
2837 } /* switch on arg code. */
2838
2839 /* Break out of for() loop. */
2840 break;
2841 } /* For each arg that we expect. */
2842
2843 error:
2844 if (match == 0)
2845 {
2846 /* Args don't match. */
2847 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2848 && (insn->name == insn[1].name
2849 || !strcmp (insn->name, insn[1].name)))
2850 {
2851 ++insn;
2852 s = argsStart;
2853 continue;
2854 }
2855 else
2856 {
2857 as_bad (_("Illegal operands%s"), error_message);
2858 return special_case;
2859 }
2860 }
2861 else
2862 {
2863 /* We have a match. Now see if the architecture is OK. */
2864 int needed_arch_mask = insn->architecture;
2865 int hwcaps = insn->flags & F_HWCAP_MASK;
2866
2867 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2868 if (hwcaps)
2869 hwcap_seen |= hwcaps;
2870 #endif
2871 if (v9_arg_p)
2872 {
2873 needed_arch_mask &=
2874 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2875 if (! needed_arch_mask)
2876 needed_arch_mask =
2877 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2878 }
2879
2880 if (needed_arch_mask
2881 & SPARC_OPCODE_SUPPORTED (current_architecture))
2882 /* OK. */
2883 ;
2884 /* Can we bump up the architecture? */
2885 else if (needed_arch_mask
2886 & SPARC_OPCODE_SUPPORTED (max_architecture))
2887 {
2888 enum sparc_opcode_arch_val needed_architecture =
2889 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2890 & needed_arch_mask);
2891
2892 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2893 if (warn_on_bump
2894 && needed_architecture > warn_after_architecture)
2895 {
2896 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2897 sparc_opcode_archs[current_architecture].name,
2898 sparc_opcode_archs[needed_architecture].name,
2899 str);
2900 warn_after_architecture = needed_architecture;
2901 }
2902 current_architecture = needed_architecture;
2903 }
2904 /* Conflict. */
2905 /* ??? This seems to be a bit fragile. What if the next entry in
2906 the opcode table is the one we want and it is supported?
2907 It is possible to arrange the table today so that this can't
2908 happen but what about tomorrow? */
2909 else
2910 {
2911 int arch, printed_one_p = 0;
2912 char *p;
2913 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2914
2915 /* Create a list of the architectures that support the insn. */
2916 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2917 p = required_archs;
2918 arch = sparc_ffs (needed_arch_mask);
2919 while ((1 << arch) <= needed_arch_mask)
2920 {
2921 if ((1 << arch) & needed_arch_mask)
2922 {
2923 if (printed_one_p)
2924 *p++ = '|';
2925 strcpy (p, sparc_opcode_archs[arch].name);
2926 p += strlen (p);
2927 printed_one_p = 1;
2928 }
2929 ++arch;
2930 }
2931
2932 as_bad (_("Architecture mismatch on \"%s\"."), str);
2933 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2934 required_archs,
2935 sparc_opcode_archs[max_architecture].name);
2936 return special_case;
2937 }
2938
2939 /* Make sure the the hwcaps used by the instruction are
2940 currently enabled. */
2941 if (hwcaps & ~hwcap_allowed)
2942 {
2943 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
2944
2945 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
2946 hwcap_name, str);
2947 return special_case;
2948 }
2949 } /* If no match. */
2950
2951 break;
2952 } /* Forever looking for a match. */
2953
2954 the_insn.opcode = opcode;
2955 return special_case;
2956 }
2957
2958 /* Parse an argument that can be expressed as a keyword.
2959 (eg: #StoreStore or %ccfr).
2960 The result is a boolean indicating success.
2961 If successful, INPUT_POINTER is updated. */
2962
2963 static int
2964 parse_keyword_arg (int (*lookup_fn) (const char *),
2965 char **input_pointerP,
2966 int *valueP)
2967 {
2968 int value;
2969 char c, *p, *q;
2970
2971 p = *input_pointerP;
2972 for (q = p + (*p == '#' || *p == '%');
2973 ISALNUM (*q) || *q == '_';
2974 ++q)
2975 continue;
2976 c = *q;
2977 *q = 0;
2978 value = (*lookup_fn) (p);
2979 *q = c;
2980 if (value == -1)
2981 return 0;
2982 *valueP = value;
2983 *input_pointerP = q;
2984 return 1;
2985 }
2986
2987 /* Parse an argument that is a constant expression.
2988 The result is a boolean indicating success. */
2989
2990 static int
2991 parse_const_expr_arg (char **input_pointerP, int *valueP)
2992 {
2993 char *save = input_line_pointer;
2994 expressionS exp;
2995
2996 input_line_pointer = *input_pointerP;
2997 /* The next expression may be something other than a constant
2998 (say if we're not processing the right variant of the insn).
2999 Don't call expression unless we're sure it will succeed as it will
3000 signal an error (which we want to defer until later). */
3001 /* FIXME: It might be better to define md_operand and have it recognize
3002 things like %asi, etc. but continuing that route through to the end
3003 is a lot of work. */
3004 if (*input_line_pointer == '%')
3005 {
3006 input_line_pointer = save;
3007 return 0;
3008 }
3009 expression (&exp);
3010 *input_pointerP = input_line_pointer;
3011 input_line_pointer = save;
3012 if (exp.X_op != O_constant)
3013 return 0;
3014 *valueP = exp.X_add_number;
3015 return 1;
3016 }
3017
3018 /* Subroutine of sparc_ip to parse an expression. */
3019
3020 static int
3021 get_expression (char *str)
3022 {
3023 char *save_in;
3024 segT seg;
3025
3026 save_in = input_line_pointer;
3027 input_line_pointer = str;
3028 seg = expression (&the_insn.exp);
3029 if (seg != absolute_section
3030 && seg != text_section
3031 && seg != data_section
3032 && seg != bss_section
3033 && seg != undefined_section)
3034 {
3035 the_insn.error = _("bad segment");
3036 expr_end = input_line_pointer;
3037 input_line_pointer = save_in;
3038 return 1;
3039 }
3040 expr_end = input_line_pointer;
3041 input_line_pointer = save_in;
3042 return 0;
3043 }
3044
3045 /* Subroutine of md_assemble to output one insn. */
3046
3047 static void
3048 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3049 {
3050 char *toP = frag_more (4);
3051
3052 /* Put out the opcode. */
3053 if (INSN_BIG_ENDIAN)
3054 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3055 else
3056 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3057
3058 /* Put out the symbol-dependent stuff. */
3059 if (theinsn->reloc != BFD_RELOC_NONE)
3060 {
3061 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3062 (toP - frag_now->fr_literal), /* Where. */
3063 4, /* Size. */
3064 &theinsn->exp,
3065 theinsn->pcrel,
3066 theinsn->reloc);
3067 /* Turn off overflow checking in fixup_segment. We'll do our
3068 own overflow checking in md_apply_fix. This is necessary because
3069 the insn size is 4 and fixup_segment will signal an overflow for
3070 large 8 byte quantities. */
3071 fixP->fx_no_overflow = 1;
3072 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3073 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3074 }
3075
3076 last_insn = insn;
3077 last_opcode = theinsn->opcode;
3078
3079 #ifdef OBJ_ELF
3080 dwarf2_emit_insn (4);
3081 #endif
3082 }
3083 \f
3084 char *
3085 md_atof (int type, char *litP, int *sizeP)
3086 {
3087 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3088 }
3089
3090 /* Write a value out to the object file, using the appropriate
3091 endianness. */
3092
3093 void
3094 md_number_to_chars (char *buf, valueT val, int n)
3095 {
3096 if (target_big_endian)
3097 number_to_chars_bigendian (buf, val, n);
3098 else if (target_little_endian_data
3099 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3100 /* Output debug words, which are not in allocated sections, as big
3101 endian. */
3102 number_to_chars_bigendian (buf, val, n);
3103 else if (target_little_endian_data || ! target_big_endian)
3104 number_to_chars_littleendian (buf, val, n);
3105 }
3106 \f
3107 /* Apply a fixS to the frags, now that we know the value it ought to
3108 hold. */
3109
3110 void
3111 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3112 {
3113 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3114 offsetT val = * (offsetT *) valP;
3115 long insn;
3116
3117 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3118
3119 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3120
3121 #ifdef OBJ_ELF
3122 /* SPARC ELF relocations don't use an addend in the data field. */
3123 if (fixP->fx_addsy != NULL)
3124 {
3125 switch (fixP->fx_r_type)
3126 {
3127 case BFD_RELOC_SPARC_TLS_GD_HI22:
3128 case BFD_RELOC_SPARC_TLS_GD_LO10:
3129 case BFD_RELOC_SPARC_TLS_GD_ADD:
3130 case BFD_RELOC_SPARC_TLS_GD_CALL:
3131 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3132 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3133 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3134 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3135 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3136 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3137 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3138 case BFD_RELOC_SPARC_TLS_IE_HI22:
3139 case BFD_RELOC_SPARC_TLS_IE_LO10:
3140 case BFD_RELOC_SPARC_TLS_IE_LD:
3141 case BFD_RELOC_SPARC_TLS_IE_LDX:
3142 case BFD_RELOC_SPARC_TLS_IE_ADD:
3143 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3144 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3145 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3146 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3147 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3148 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3149 case BFD_RELOC_SPARC_TLS_TPOFF32:
3150 case BFD_RELOC_SPARC_TLS_TPOFF64:
3151 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3152
3153 default:
3154 break;
3155 }
3156
3157 return;
3158 }
3159 #endif
3160
3161 /* This is a hack. There should be a better way to
3162 handle this. Probably in terms of howto fields, once
3163 we can look at these fixups in terms of howtos. */
3164 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3165 val += fixP->fx_where + fixP->fx_frag->fr_address;
3166
3167 #ifdef OBJ_AOUT
3168 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3169 generate a reloc, then we just want to let the reloc addend set
3170 the value. We do not want to also stuff the addend into the
3171 object file. Including the addend in the object file works when
3172 doing a static link, because the linker will ignore the object
3173 file contents. However, the dynamic linker does not ignore the
3174 object file contents. */
3175 if (fixP->fx_addsy != NULL
3176 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3177 val = 0;
3178
3179 /* When generating PIC code, we do not want an addend for a reloc
3180 against a local symbol. We adjust fx_addnumber to cancel out the
3181 value already included in val, and to also cancel out the
3182 adjustment which bfd_install_relocation will create. */
3183 if (sparc_pic_code
3184 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3185 && fixP->fx_addsy != NULL
3186 && ! S_IS_COMMON (fixP->fx_addsy)
3187 && symbol_section_p (fixP->fx_addsy))
3188 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3189
3190 /* When generating PIC code, we need to fiddle to get
3191 bfd_install_relocation to do the right thing for a PC relative
3192 reloc against a local symbol which we are going to keep. */
3193 if (sparc_pic_code
3194 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3195 && fixP->fx_addsy != NULL
3196 && (S_IS_EXTERNAL (fixP->fx_addsy)
3197 || S_IS_WEAK (fixP->fx_addsy))
3198 && S_IS_DEFINED (fixP->fx_addsy)
3199 && ! S_IS_COMMON (fixP->fx_addsy))
3200 {
3201 val = 0;
3202 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3203 }
3204 #endif
3205
3206 /* If this is a data relocation, just output VAL. */
3207
3208 if (fixP->fx_r_type == BFD_RELOC_8)
3209 {
3210 md_number_to_chars (buf, val, 1);
3211 }
3212 else if (fixP->fx_r_type == BFD_RELOC_16
3213 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3214 {
3215 md_number_to_chars (buf, val, 2);
3216 }
3217 else if (fixP->fx_r_type == BFD_RELOC_32
3218 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3219 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3220 {
3221 md_number_to_chars (buf, val, 4);
3222 }
3223 else if (fixP->fx_r_type == BFD_RELOC_64
3224 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3225 {
3226 md_number_to_chars (buf, val, 8);
3227 }
3228 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3229 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3230 {
3231 fixP->fx_done = 0;
3232 return;
3233 }
3234 else
3235 {
3236 /* It's a relocation against an instruction. */
3237
3238 if (INSN_BIG_ENDIAN)
3239 insn = bfd_getb32 ((unsigned char *) buf);
3240 else
3241 insn = bfd_getl32 ((unsigned char *) buf);
3242
3243 switch (fixP->fx_r_type)
3244 {
3245 case BFD_RELOC_32_PCREL_S2:
3246 val = val >> 2;
3247 /* FIXME: This increment-by-one deserves a comment of why it's
3248 being done! */
3249 if (! sparc_pic_code
3250 || fixP->fx_addsy == NULL
3251 || symbol_section_p (fixP->fx_addsy))
3252 ++val;
3253
3254 insn |= val & 0x3fffffff;
3255
3256 /* See if we have a delay slot. */
3257 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3258 {
3259 #define G0 0
3260 #define O7 15
3261 #define XCC (2 << 20)
3262 #define COND(x) (((x)&0xf)<<25)
3263 #define CONDA COND(0x8)
3264 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3265 #define INSN_BA (F2(0,2) | CONDA)
3266 #define INSN_OR F3(2, 0x2, 0)
3267 #define INSN_NOP F2(0,4)
3268
3269 long delay;
3270
3271 /* If the instruction is a call with either:
3272 restore
3273 arithmetic instruction with rd == %o7
3274 where rs1 != %o7 and rs2 if it is register != %o7
3275 then we can optimize if the call destination is near
3276 by changing the call into a branch always. */
3277 if (INSN_BIG_ENDIAN)
3278 delay = bfd_getb32 ((unsigned char *) buf + 4);
3279 else
3280 delay = bfd_getl32 ((unsigned char *) buf + 4);
3281 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3282 break;
3283 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3284 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3285 || ((delay & RD (~0)) != RD (O7))))
3286 break;
3287 if ((delay & RS1 (~0)) == RS1 (O7)
3288 || ((delay & F3I (~0)) == 0
3289 && (delay & RS2 (~0)) == RS2 (O7)))
3290 break;
3291 /* Ensure the branch will fit into simm22. */
3292 if ((val & 0x3fe00000)
3293 && (val & 0x3fe00000) != 0x3fe00000)
3294 break;
3295 /* Check if the arch is v9 and branch will fit
3296 into simm19. */
3297 if (((val & 0x3c0000) == 0
3298 || (val & 0x3c0000) == 0x3c0000)
3299 && (sparc_arch_size == 64
3300 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3301 /* ba,pt %xcc */
3302 insn = INSN_BPA | (val & 0x7ffff);
3303 else
3304 /* ba */
3305 insn = INSN_BA | (val & 0x3fffff);
3306 if (fixP->fx_where >= 4
3307 && ((delay & (0xffffffff ^ RS1 (~0)))
3308 == (INSN_OR | RD (O7) | RS2 (G0))))
3309 {
3310 long setter;
3311 int reg;
3312
3313 if (INSN_BIG_ENDIAN)
3314 setter = bfd_getb32 ((unsigned char *) buf - 4);
3315 else
3316 setter = bfd_getl32 ((unsigned char *) buf - 4);
3317 if ((setter & (0xffffffff ^ RD (~0)))
3318 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3319 break;
3320 /* The sequence was
3321 or %o7, %g0, %rN
3322 call foo
3323 or %rN, %g0, %o7
3324
3325 If call foo was replaced with ba, replace
3326 or %rN, %g0, %o7 with nop. */
3327 reg = (delay & RS1 (~0)) >> 14;
3328 if (reg != ((setter & RD (~0)) >> 25)
3329 || reg == G0 || reg == O7)
3330 break;
3331
3332 if (INSN_BIG_ENDIAN)
3333 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3334 else
3335 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3336 }
3337 }
3338 break;
3339
3340 case BFD_RELOC_SPARC_11:
3341 if (! in_signed_range (val, 0x7ff))
3342 as_bad_where (fixP->fx_file, fixP->fx_line,
3343 _("relocation overflow"));
3344 insn |= val & 0x7ff;
3345 break;
3346
3347 case BFD_RELOC_SPARC_10:
3348 if (! in_signed_range (val, 0x3ff))
3349 as_bad_where (fixP->fx_file, fixP->fx_line,
3350 _("relocation overflow"));
3351 insn |= val & 0x3ff;
3352 break;
3353
3354 case BFD_RELOC_SPARC_7:
3355 if (! in_bitfield_range (val, 0x7f))
3356 as_bad_where (fixP->fx_file, fixP->fx_line,
3357 _("relocation overflow"));
3358 insn |= val & 0x7f;
3359 break;
3360
3361 case BFD_RELOC_SPARC_6:
3362 if (! in_bitfield_range (val, 0x3f))
3363 as_bad_where (fixP->fx_file, fixP->fx_line,
3364 _("relocation overflow"));
3365 insn |= val & 0x3f;
3366 break;
3367
3368 case BFD_RELOC_SPARC_5:
3369 if (! in_bitfield_range (val, 0x1f))
3370 as_bad_where (fixP->fx_file, fixP->fx_line,
3371 _("relocation overflow"));
3372 insn |= val & 0x1f;
3373 break;
3374
3375 case BFD_RELOC_SPARC_WDISP10:
3376 if ((val & 3)
3377 || val >= 0x007fc
3378 || val <= -(offsetT) 0x808)
3379 as_bad_where (fixP->fx_file, fixP->fx_line,
3380 _("relocation overflow"));
3381 /* FIXME: The +1 deserves a comment. */
3382 val = (val >> 2) + 1;
3383 insn |= ((val & 0x300) << 11)
3384 | ((val & 0xff) << 5);
3385 break;
3386
3387 case BFD_RELOC_SPARC_WDISP16:
3388 if ((val & 3)
3389 || val >= 0x1fffc
3390 || val <= -(offsetT) 0x20008)
3391 as_bad_where (fixP->fx_file, fixP->fx_line,
3392 _("relocation overflow"));
3393 /* FIXME: The +1 deserves a comment. */
3394 val = (val >> 2) + 1;
3395 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3396 break;
3397
3398 case BFD_RELOC_SPARC_WDISP19:
3399 if ((val & 3)
3400 || val >= 0xffffc
3401 || val <= -(offsetT) 0x100008)
3402 as_bad_where (fixP->fx_file, fixP->fx_line,
3403 _("relocation overflow"));
3404 /* FIXME: The +1 deserves a comment. */
3405 val = (val >> 2) + 1;
3406 insn |= val & 0x7ffff;
3407 break;
3408
3409 case BFD_RELOC_SPARC_HH22:
3410 val = BSR (val, 32);
3411 /* Fall through. */
3412
3413 case BFD_RELOC_SPARC_LM22:
3414 case BFD_RELOC_HI22:
3415 if (!fixP->fx_addsy)
3416 insn |= (val >> 10) & 0x3fffff;
3417 else
3418 /* FIXME: Need comment explaining why we do this. */
3419 insn &= ~0xffff;
3420 break;
3421
3422 case BFD_RELOC_SPARC22:
3423 if (val & ~0x003fffff)
3424 as_bad_where (fixP->fx_file, fixP->fx_line,
3425 _("relocation overflow"));
3426 insn |= (val & 0x3fffff);
3427 break;
3428
3429 case BFD_RELOC_SPARC_HM10:
3430 val = BSR (val, 32);
3431 /* Fall through. */
3432
3433 case BFD_RELOC_LO10:
3434 if (!fixP->fx_addsy)
3435 insn |= val & 0x3ff;
3436 else
3437 /* FIXME: Need comment explaining why we do this. */
3438 insn &= ~0xff;
3439 break;
3440
3441 case BFD_RELOC_SPARC_OLO10:
3442 val &= 0x3ff;
3443 val += fixP->tc_fix_data;
3444 /* Fall through. */
3445
3446 case BFD_RELOC_SPARC13:
3447 if (! in_signed_range (val, 0x1fff))
3448 as_bad_where (fixP->fx_file, fixP->fx_line,
3449 _("relocation overflow"));
3450 insn |= val & 0x1fff;
3451 break;
3452
3453 case BFD_RELOC_SPARC_WDISP22:
3454 val = (val >> 2) + 1;
3455 /* Fall through. */
3456 case BFD_RELOC_SPARC_BASE22:
3457 insn |= val & 0x3fffff;
3458 break;
3459
3460 case BFD_RELOC_SPARC_H34:
3461 if (!fixP->fx_addsy)
3462 {
3463 bfd_vma tval = val;
3464 tval >>= 12;
3465 insn |= tval & 0x3fffff;
3466 }
3467 break;
3468
3469 case BFD_RELOC_SPARC_H44:
3470 if (!fixP->fx_addsy)
3471 {
3472 bfd_vma tval = val;
3473 tval >>= 22;
3474 insn |= tval & 0x3fffff;
3475 }
3476 break;
3477
3478 case BFD_RELOC_SPARC_M44:
3479 if (!fixP->fx_addsy)
3480 insn |= (val >> 12) & 0x3ff;
3481 break;
3482
3483 case BFD_RELOC_SPARC_L44:
3484 if (!fixP->fx_addsy)
3485 insn |= val & 0xfff;
3486 break;
3487
3488 case BFD_RELOC_SPARC_HIX22:
3489 if (!fixP->fx_addsy)
3490 {
3491 val ^= ~(offsetT) 0;
3492 insn |= (val >> 10) & 0x3fffff;
3493 }
3494 break;
3495
3496 case BFD_RELOC_SPARC_LOX10:
3497 if (!fixP->fx_addsy)
3498 insn |= 0x1c00 | (val & 0x3ff);
3499 break;
3500
3501 case BFD_RELOC_NONE:
3502 default:
3503 as_bad_where (fixP->fx_file, fixP->fx_line,
3504 _("bad or unhandled relocation type: 0x%02x"),
3505 fixP->fx_r_type);
3506 break;
3507 }
3508
3509 if (INSN_BIG_ENDIAN)
3510 bfd_putb32 (insn, (unsigned char *) buf);
3511 else
3512 bfd_putl32 (insn, (unsigned char *) buf);
3513 }
3514
3515 /* Are we finished with this relocation now? */
3516 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3517 fixP->fx_done = 1;
3518 }
3519
3520 /* Translate internal representation of relocation info to BFD target
3521 format. */
3522
3523 arelent **
3524 tc_gen_reloc (asection *section, fixS *fixp)
3525 {
3526 static arelent *relocs[3];
3527 arelent *reloc;
3528 bfd_reloc_code_real_type code;
3529
3530 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3531 relocs[1] = NULL;
3532
3533 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3534 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3535 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3536
3537 switch (fixp->fx_r_type)
3538 {
3539 case BFD_RELOC_16:
3540 case BFD_RELOC_32:
3541 case BFD_RELOC_HI22:
3542 case BFD_RELOC_LO10:
3543 case BFD_RELOC_32_PCREL_S2:
3544 case BFD_RELOC_SPARC13:
3545 case BFD_RELOC_SPARC22:
3546 case BFD_RELOC_SPARC_PC22:
3547 case BFD_RELOC_SPARC_PC10:
3548 case BFD_RELOC_SPARC_BASE13:
3549 case BFD_RELOC_SPARC_WDISP10:
3550 case BFD_RELOC_SPARC_WDISP16:
3551 case BFD_RELOC_SPARC_WDISP19:
3552 case BFD_RELOC_SPARC_WDISP22:
3553 case BFD_RELOC_64:
3554 case BFD_RELOC_SPARC_5:
3555 case BFD_RELOC_SPARC_6:
3556 case BFD_RELOC_SPARC_7:
3557 case BFD_RELOC_SPARC_10:
3558 case BFD_RELOC_SPARC_11:
3559 case BFD_RELOC_SPARC_HH22:
3560 case BFD_RELOC_SPARC_HM10:
3561 case BFD_RELOC_SPARC_LM22:
3562 case BFD_RELOC_SPARC_PC_HH22:
3563 case BFD_RELOC_SPARC_PC_HM10:
3564 case BFD_RELOC_SPARC_PC_LM22:
3565 case BFD_RELOC_SPARC_H34:
3566 case BFD_RELOC_SPARC_H44:
3567 case BFD_RELOC_SPARC_M44:
3568 case BFD_RELOC_SPARC_L44:
3569 case BFD_RELOC_SPARC_HIX22:
3570 case BFD_RELOC_SPARC_LOX10:
3571 case BFD_RELOC_SPARC_REV32:
3572 case BFD_RELOC_SPARC_OLO10:
3573 case BFD_RELOC_SPARC_UA16:
3574 case BFD_RELOC_SPARC_UA32:
3575 case BFD_RELOC_SPARC_UA64:
3576 case BFD_RELOC_8_PCREL:
3577 case BFD_RELOC_16_PCREL:
3578 case BFD_RELOC_32_PCREL:
3579 case BFD_RELOC_64_PCREL:
3580 case BFD_RELOC_SPARC_PLT32:
3581 case BFD_RELOC_SPARC_PLT64:
3582 case BFD_RELOC_VTABLE_ENTRY:
3583 case BFD_RELOC_VTABLE_INHERIT:
3584 case BFD_RELOC_SPARC_TLS_GD_HI22:
3585 case BFD_RELOC_SPARC_TLS_GD_LO10:
3586 case BFD_RELOC_SPARC_TLS_GD_ADD:
3587 case BFD_RELOC_SPARC_TLS_GD_CALL:
3588 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3589 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3590 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3591 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3592 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3593 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3594 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3595 case BFD_RELOC_SPARC_TLS_IE_HI22:
3596 case BFD_RELOC_SPARC_TLS_IE_LO10:
3597 case BFD_RELOC_SPARC_TLS_IE_LD:
3598 case BFD_RELOC_SPARC_TLS_IE_LDX:
3599 case BFD_RELOC_SPARC_TLS_IE_ADD:
3600 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3601 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3602 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3603 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3604 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3605 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3606 case BFD_RELOC_SPARC_GOTDATA_OP:
3607 code = fixp->fx_r_type;
3608 break;
3609 default:
3610 abort ();
3611 return NULL;
3612 }
3613
3614 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3615 /* If we are generating PIC code, we need to generate a different
3616 set of relocs. */
3617
3618 #ifdef OBJ_ELF
3619 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3620 #else
3621 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3622 #endif
3623 #ifdef TE_VXWORKS
3624 #define GOTT_BASE "__GOTT_BASE__"
3625 #define GOTT_INDEX "__GOTT_INDEX__"
3626 #endif
3627
3628 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3629
3630 if (sparc_pic_code)
3631 {
3632 switch (code)
3633 {
3634 case BFD_RELOC_32_PCREL_S2:
3635 if (generic_force_reloc (fixp))
3636 code = BFD_RELOC_SPARC_WPLT30;
3637 break;
3638 case BFD_RELOC_HI22:
3639 code = BFD_RELOC_SPARC_GOT22;
3640 if (fixp->fx_addsy != NULL)
3641 {
3642 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3643 code = BFD_RELOC_SPARC_PC22;
3644 #ifdef TE_VXWORKS
3645 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3646 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3647 code = BFD_RELOC_HI22; /* Unchanged. */
3648 #endif
3649 }
3650 break;
3651 case BFD_RELOC_LO10:
3652 code = BFD_RELOC_SPARC_GOT10;
3653 if (fixp->fx_addsy != NULL)
3654 {
3655 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3656 code = BFD_RELOC_SPARC_PC10;
3657 #ifdef TE_VXWORKS
3658 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3659 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3660 code = BFD_RELOC_LO10; /* Unchanged. */
3661 #endif
3662 }
3663 break;
3664 case BFD_RELOC_SPARC13:
3665 code = BFD_RELOC_SPARC_GOT13;
3666 break;
3667 default:
3668 break;
3669 }
3670 }
3671 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3672
3673 /* Nothing is aligned in DWARF debugging sections. */
3674 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3675 switch (code)
3676 {
3677 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3678 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3679 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3680 default: break;
3681 }
3682
3683 if (code == BFD_RELOC_SPARC_OLO10)
3684 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3685 else
3686 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3687 if (reloc->howto == 0)
3688 {
3689 as_bad_where (fixp->fx_file, fixp->fx_line,
3690 _("internal error: can't export reloc type %d (`%s')"),
3691 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3692 xfree (reloc);
3693 relocs[0] = NULL;
3694 return relocs;
3695 }
3696
3697 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3698 #ifdef OBJ_AOUT
3699
3700 if (reloc->howto->pc_relative == 0
3701 || code == BFD_RELOC_SPARC_PC10
3702 || code == BFD_RELOC_SPARC_PC22)
3703 reloc->addend = fixp->fx_addnumber;
3704 else if (sparc_pic_code
3705 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3706 && fixp->fx_addsy != NULL
3707 && (S_IS_EXTERNAL (fixp->fx_addsy)
3708 || S_IS_WEAK (fixp->fx_addsy))
3709 && S_IS_DEFINED (fixp->fx_addsy)
3710 && ! S_IS_COMMON (fixp->fx_addsy))
3711 reloc->addend = fixp->fx_addnumber;
3712 else
3713 reloc->addend = fixp->fx_offset - reloc->address;
3714
3715 #else /* elf or coff */
3716
3717 if (code != BFD_RELOC_32_PCREL_S2
3718 && code != BFD_RELOC_SPARC_WDISP22
3719 && code != BFD_RELOC_SPARC_WDISP16
3720 && code != BFD_RELOC_SPARC_WDISP19
3721 && code != BFD_RELOC_SPARC_WDISP10
3722 && code != BFD_RELOC_SPARC_WPLT30
3723 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3724 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3725 reloc->addend = fixp->fx_addnumber;
3726 else if (symbol_section_p (fixp->fx_addsy))
3727 reloc->addend = (section->vma
3728 + fixp->fx_addnumber
3729 + md_pcrel_from (fixp));
3730 else
3731 reloc->addend = fixp->fx_offset;
3732 #endif
3733
3734 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3735 on the same location. */
3736 if (code == BFD_RELOC_SPARC_OLO10)
3737 {
3738 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3739 relocs[2] = NULL;
3740
3741 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3742 *reloc->sym_ptr_ptr
3743 = symbol_get_bfdsym (section_symbol (absolute_section));
3744 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3745 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3746 reloc->addend = fixp->tc_fix_data;
3747 }
3748
3749 return relocs;
3750 }
3751 \f
3752 /* We have no need to default values of symbols. */
3753
3754 symbolS *
3755 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3756 {
3757 return 0;
3758 }
3759
3760 /* Round up a section size to the appropriate boundary. */
3761
3762 valueT
3763 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3764 {
3765 #ifndef OBJ_ELF
3766 /* This is not right for ELF; a.out wants it, and COFF will force
3767 the alignment anyways. */
3768 valueT align = ((valueT) 1
3769 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3770 valueT newsize;
3771
3772 /* Turn alignment value into a mask. */
3773 align--;
3774 newsize = (size + align) & ~align;
3775 return newsize;
3776 #else
3777 return size;
3778 #endif
3779 }
3780
3781 /* Exactly what point is a PC-relative offset relative TO?
3782 On the sparc, they're relative to the address of the offset, plus
3783 its size. This gets us to the following instruction.
3784 (??? Is this right? FIXME-SOON) */
3785 long
3786 md_pcrel_from (fixS *fixP)
3787 {
3788 long ret;
3789
3790 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3791 if (! sparc_pic_code
3792 || fixP->fx_addsy == NULL
3793 || symbol_section_p (fixP->fx_addsy))
3794 ret += fixP->fx_size;
3795 return ret;
3796 }
3797 \f
3798 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3799 of two. */
3800
3801 static int
3802 mylog2 (int value)
3803 {
3804 int shift;
3805
3806 if (value <= 0)
3807 return -1;
3808
3809 for (shift = 0; (value & 1) == 0; value >>= 1)
3810 ++shift;
3811
3812 return (value == 1) ? shift : -1;
3813 }
3814
3815 /* Sort of like s_lcomm. */
3816
3817 #ifndef OBJ_ELF
3818 static int max_alignment = 15;
3819 #endif
3820
3821 static void
3822 s_reserve (int ignore ATTRIBUTE_UNUSED)
3823 {
3824 char *name;
3825 char *p;
3826 char c;
3827 int align;
3828 int size;
3829 int temp;
3830 symbolS *symbolP;
3831
3832 name = input_line_pointer;
3833 c = get_symbol_end ();
3834 p = input_line_pointer;
3835 *p = c;
3836 SKIP_WHITESPACE ();
3837
3838 if (*input_line_pointer != ',')
3839 {
3840 as_bad (_("Expected comma after name"));
3841 ignore_rest_of_line ();
3842 return;
3843 }
3844
3845 ++input_line_pointer;
3846
3847 if ((size = get_absolute_expression ()) < 0)
3848 {
3849 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3850 ignore_rest_of_line ();
3851 return;
3852 } /* Bad length. */
3853
3854 *p = 0;
3855 symbolP = symbol_find_or_make (name);
3856 *p = c;
3857
3858 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3859 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3860 {
3861 as_bad (_("bad .reserve segment -- expected BSS segment"));
3862 return;
3863 }
3864
3865 if (input_line_pointer[2] == '.')
3866 input_line_pointer += 7;
3867 else
3868 input_line_pointer += 6;
3869 SKIP_WHITESPACE ();
3870
3871 if (*input_line_pointer == ',')
3872 {
3873 ++input_line_pointer;
3874
3875 SKIP_WHITESPACE ();
3876 if (*input_line_pointer == '\n')
3877 {
3878 as_bad (_("missing alignment"));
3879 ignore_rest_of_line ();
3880 return;
3881 }
3882
3883 align = (int) get_absolute_expression ();
3884
3885 #ifndef OBJ_ELF
3886 if (align > max_alignment)
3887 {
3888 align = max_alignment;
3889 as_warn (_("alignment too large; assuming %d"), align);
3890 }
3891 #endif
3892
3893 if (align < 0)
3894 {
3895 as_bad (_("negative alignment"));
3896 ignore_rest_of_line ();
3897 return;
3898 }
3899
3900 if (align != 0)
3901 {
3902 temp = mylog2 (align);
3903 if (temp < 0)
3904 {
3905 as_bad (_("alignment not a power of 2"));
3906 ignore_rest_of_line ();
3907 return;
3908 }
3909
3910 align = temp;
3911 }
3912
3913 record_alignment (bss_section, align);
3914 }
3915 else
3916 align = 0;
3917
3918 if (!S_IS_DEFINED (symbolP)
3919 #ifdef OBJ_AOUT
3920 && S_GET_OTHER (symbolP) == 0
3921 && S_GET_DESC (symbolP) == 0
3922 #endif
3923 )
3924 {
3925 if (! need_pass_2)
3926 {
3927 char *pfrag;
3928 segT current_seg = now_seg;
3929 subsegT current_subseg = now_subseg;
3930
3931 /* Switch to bss. */
3932 subseg_set (bss_section, 1);
3933
3934 if (align)
3935 /* Do alignment. */
3936 frag_align (align, 0, 0);
3937
3938 /* Detach from old frag. */
3939 if (S_GET_SEGMENT (symbolP) == bss_section)
3940 symbol_get_frag (symbolP)->fr_symbol = NULL;
3941
3942 symbol_set_frag (symbolP, frag_now);
3943 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3944 (offsetT) size, (char *) 0);
3945 *pfrag = 0;
3946
3947 S_SET_SEGMENT (symbolP, bss_section);
3948
3949 subseg_set (current_seg, current_subseg);
3950
3951 #ifdef OBJ_ELF
3952 S_SET_SIZE (symbolP, size);
3953 #endif
3954 }
3955 }
3956 else
3957 {
3958 as_warn (_("Ignoring attempt to re-define symbol %s"),
3959 S_GET_NAME (symbolP));
3960 }
3961
3962 demand_empty_rest_of_line ();
3963 }
3964
3965 static void
3966 s_common (int ignore ATTRIBUTE_UNUSED)
3967 {
3968 char *name;
3969 char c;
3970 char *p;
3971 offsetT temp, size;
3972 symbolS *symbolP;
3973
3974 name = input_line_pointer;
3975 c = get_symbol_end ();
3976 /* Just after name is now '\0'. */
3977 p = input_line_pointer;
3978 *p = c;
3979 SKIP_WHITESPACE ();
3980 if (*input_line_pointer != ',')
3981 {
3982 as_bad (_("Expected comma after symbol-name"));
3983 ignore_rest_of_line ();
3984 return;
3985 }
3986
3987 /* Skip ','. */
3988 input_line_pointer++;
3989
3990 if ((temp = get_absolute_expression ()) < 0)
3991 {
3992 as_bad (_(".COMMon length (%lu) out of range ignored"),
3993 (unsigned long) temp);
3994 ignore_rest_of_line ();
3995 return;
3996 }
3997 size = temp;
3998 *p = 0;
3999 symbolP = symbol_find_or_make (name);
4000 *p = c;
4001 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4002 {
4003 as_bad (_("Ignoring attempt to re-define symbol"));
4004 ignore_rest_of_line ();
4005 return;
4006 }
4007 if (S_GET_VALUE (symbolP) != 0)
4008 {
4009 if (S_GET_VALUE (symbolP) != (valueT) size)
4010 {
4011 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4012 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4013 }
4014 }
4015 else
4016 {
4017 #ifndef OBJ_ELF
4018 S_SET_VALUE (symbolP, (valueT) size);
4019 S_SET_EXTERNAL (symbolP);
4020 #endif
4021 }
4022 know (symbol_get_frag (symbolP) == &zero_address_frag);
4023 if (*input_line_pointer != ',')
4024 {
4025 as_bad (_("Expected comma after common length"));
4026 ignore_rest_of_line ();
4027 return;
4028 }
4029 input_line_pointer++;
4030 SKIP_WHITESPACE ();
4031 if (*input_line_pointer != '"')
4032 {
4033 temp = get_absolute_expression ();
4034
4035 #ifndef OBJ_ELF
4036 if (temp > max_alignment)
4037 {
4038 temp = max_alignment;
4039 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4040 }
4041 #endif
4042
4043 if (temp < 0)
4044 {
4045 as_bad (_("negative alignment"));
4046 ignore_rest_of_line ();
4047 return;
4048 }
4049
4050 #ifdef OBJ_ELF
4051 if (symbol_get_obj (symbolP)->local)
4052 {
4053 segT old_sec;
4054 int old_subsec;
4055 int align;
4056
4057 old_sec = now_seg;
4058 old_subsec = now_subseg;
4059
4060 if (temp == 0)
4061 align = 0;
4062 else
4063 align = mylog2 (temp);
4064
4065 if (align < 0)
4066 {
4067 as_bad (_("alignment not a power of 2"));
4068 ignore_rest_of_line ();
4069 return;
4070 }
4071
4072 record_alignment (bss_section, align);
4073 subseg_set (bss_section, 0);
4074 if (align)
4075 frag_align (align, 0, 0);
4076 if (S_GET_SEGMENT (symbolP) == bss_section)
4077 symbol_get_frag (symbolP)->fr_symbol = 0;
4078 symbol_set_frag (symbolP, frag_now);
4079 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4080 (offsetT) size, (char *) 0);
4081 *p = 0;
4082 S_SET_SEGMENT (symbolP, bss_section);
4083 S_CLEAR_EXTERNAL (symbolP);
4084 S_SET_SIZE (symbolP, size);
4085 subseg_set (old_sec, old_subsec);
4086 }
4087 else
4088 #endif /* OBJ_ELF */
4089 {
4090 allocate_common:
4091 S_SET_VALUE (symbolP, (valueT) size);
4092 #ifdef OBJ_ELF
4093 S_SET_ALIGN (symbolP, temp);
4094 S_SET_SIZE (symbolP, size);
4095 #endif
4096 S_SET_EXTERNAL (symbolP);
4097 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4098 }
4099 }
4100 else
4101 {
4102 input_line_pointer++;
4103 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4104 if (*input_line_pointer == '.')
4105 input_line_pointer++;
4106 /* @@ Some say data, some say bss. */
4107 if (strncmp (input_line_pointer, "bss\"", 4)
4108 && strncmp (input_line_pointer, "data\"", 5))
4109 {
4110 while (*--input_line_pointer != '"')
4111 ;
4112 input_line_pointer--;
4113 goto bad_common_segment;
4114 }
4115 while (*input_line_pointer++ != '"')
4116 ;
4117 goto allocate_common;
4118 }
4119
4120 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4121
4122 demand_empty_rest_of_line ();
4123 return;
4124
4125 {
4126 bad_common_segment:
4127 p = input_line_pointer;
4128 while (*p && *p != '\n')
4129 p++;
4130 c = *p;
4131 *p = '\0';
4132 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4133 *p = c;
4134 input_line_pointer = p;
4135 ignore_rest_of_line ();
4136 return;
4137 }
4138 }
4139
4140 /* Handle the .empty pseudo-op. This suppresses the warnings about
4141 invalid delay slot usage. */
4142
4143 static void
4144 s_empty (int ignore ATTRIBUTE_UNUSED)
4145 {
4146 /* The easy way to implement is to just forget about the last
4147 instruction. */
4148 last_insn = NULL;
4149 }
4150
4151 static void
4152 s_seg (int ignore ATTRIBUTE_UNUSED)
4153 {
4154
4155 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4156 {
4157 input_line_pointer += 6;
4158 s_text (0);
4159 return;
4160 }
4161 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4162 {
4163 input_line_pointer += 6;
4164 s_data (0);
4165 return;
4166 }
4167 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4168 {
4169 input_line_pointer += 7;
4170 s_data1 ();
4171 return;
4172 }
4173 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4174 {
4175 input_line_pointer += 5;
4176 /* We only support 2 segments -- text and data -- for now, so
4177 things in the "bss segment" will have to go into data for now.
4178 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4179 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4180 return;
4181 }
4182 as_bad (_("Unknown segment type"));
4183 demand_empty_rest_of_line ();
4184 }
4185
4186 static void
4187 s_data1 (void)
4188 {
4189 subseg_set (data_section, 1);
4190 demand_empty_rest_of_line ();
4191 }
4192
4193 static void
4194 s_proc (int ignore ATTRIBUTE_UNUSED)
4195 {
4196 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4197 {
4198 ++input_line_pointer;
4199 }
4200 ++input_line_pointer;
4201 }
4202
4203 /* This static variable is set by s_uacons to tell sparc_cons_align
4204 that the expression does not need to be aligned. */
4205
4206 static int sparc_no_align_cons = 0;
4207
4208 /* This static variable is set by sparc_cons to emit requested types
4209 of relocations in cons_fix_new_sparc. */
4210
4211 static const char *sparc_cons_special_reloc;
4212
4213 /* This handles the unaligned space allocation pseudo-ops, such as
4214 .uaword. .uaword is just like .word, but the value does not need
4215 to be aligned. */
4216
4217 static void
4218 s_uacons (int bytes)
4219 {
4220 /* Tell sparc_cons_align not to align this value. */
4221 sparc_no_align_cons = 1;
4222 cons (bytes);
4223 sparc_no_align_cons = 0;
4224 }
4225
4226 /* This handles the native word allocation pseudo-op .nword.
4227 For sparc_arch_size 32 it is equivalent to .word, for
4228 sparc_arch_size 64 it is equivalent to .xword. */
4229
4230 static void
4231 s_ncons (int bytes ATTRIBUTE_UNUSED)
4232 {
4233 cons (sparc_arch_size == 32 ? 4 : 8);
4234 }
4235
4236 #ifdef OBJ_ELF
4237 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4238 global register.
4239 The syntax is:
4240
4241 .register %g[2367],{#scratch|symbolname|#ignore}
4242 */
4243
4244 static void
4245 s_register (int ignore ATTRIBUTE_UNUSED)
4246 {
4247 char c;
4248 int reg;
4249 int flags;
4250 const char *regname;
4251
4252 if (input_line_pointer[0] != '%'
4253 || input_line_pointer[1] != 'g'
4254 || ((input_line_pointer[2] & ~1) != '2'
4255 && (input_line_pointer[2] & ~1) != '6')
4256 || input_line_pointer[3] != ',')
4257 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4258 reg = input_line_pointer[2] - '0';
4259 input_line_pointer += 4;
4260
4261 if (*input_line_pointer == '#')
4262 {
4263 ++input_line_pointer;
4264 regname = input_line_pointer;
4265 c = get_symbol_end ();
4266 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4267 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4268 if (regname[0] == 'i')
4269 regname = NULL;
4270 else
4271 regname = "";
4272 }
4273 else
4274 {
4275 regname = input_line_pointer;
4276 c = get_symbol_end ();
4277 }
4278 if (sparc_arch_size == 64)
4279 {
4280 if (globals[reg])
4281 {
4282 if ((regname && globals[reg] != (symbolS *) 1
4283 && strcmp (S_GET_NAME (globals[reg]), regname))
4284 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4285 as_bad (_("redefinition of global register"));
4286 }
4287 else
4288 {
4289 if (regname == NULL)
4290 globals[reg] = (symbolS *) 1;
4291 else
4292 {
4293 if (*regname)
4294 {
4295 if (symbol_find (regname))
4296 as_bad (_("Register symbol %s already defined."),
4297 regname);
4298 }
4299 globals[reg] = symbol_make (regname);
4300 flags = symbol_get_bfdsym (globals[reg])->flags;
4301 if (! *regname)
4302 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4303 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4304 flags |= BSF_GLOBAL;
4305 symbol_get_bfdsym (globals[reg])->flags = flags;
4306 S_SET_VALUE (globals[reg], (valueT) reg);
4307 S_SET_ALIGN (globals[reg], reg);
4308 S_SET_SIZE (globals[reg], 0);
4309 /* Although we actually want undefined_section here,
4310 we have to use absolute_section, because otherwise
4311 generic as code will make it a COM section.
4312 We fix this up in sparc_adjust_symtab. */
4313 S_SET_SEGMENT (globals[reg], absolute_section);
4314 S_SET_OTHER (globals[reg], 0);
4315 elf_symbol (symbol_get_bfdsym (globals[reg]))
4316 ->internal_elf_sym.st_info =
4317 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4318 elf_symbol (symbol_get_bfdsym (globals[reg]))
4319 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4320 }
4321 }
4322 }
4323
4324 *input_line_pointer = c;
4325
4326 demand_empty_rest_of_line ();
4327 }
4328
4329 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4330 symbols which need it. */
4331
4332 void
4333 sparc_adjust_symtab (void)
4334 {
4335 symbolS *sym;
4336
4337 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4338 {
4339 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4340 ->internal_elf_sym.st_info) != STT_REGISTER)
4341 continue;
4342
4343 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4344 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4345 continue;
4346
4347 S_SET_SEGMENT (sym, undefined_section);
4348 }
4349 }
4350 #endif
4351
4352 /* If the --enforce-aligned-data option is used, we require .word,
4353 et. al., to be aligned correctly. We do it by setting up an
4354 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4355 no unexpected alignment was introduced.
4356
4357 The SunOS and Solaris native assemblers enforce aligned data by
4358 default. We don't want to do that, because gcc can deliberately
4359 generate misaligned data if the packed attribute is used. Instead,
4360 we permit misaligned data by default, and permit the user to set an
4361 option to check for it. */
4362
4363 void
4364 sparc_cons_align (int nbytes)
4365 {
4366 int nalign;
4367
4368 /* Only do this if we are enforcing aligned data. */
4369 if (! enforce_aligned_data)
4370 return;
4371
4372 /* Don't align if this is an unaligned pseudo-op. */
4373 if (sparc_no_align_cons)
4374 return;
4375
4376 nalign = mylog2 (nbytes);
4377 if (nalign == 0)
4378 return;
4379
4380 gas_assert (nalign > 0);
4381
4382 if (now_seg == absolute_section)
4383 {
4384 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4385 as_bad (_("misaligned data"));
4386 return;
4387 }
4388
4389 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4390 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4391
4392 record_alignment (now_seg, nalign);
4393 }
4394
4395 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4396
4397 void
4398 sparc_handle_align (fragS *fragp)
4399 {
4400 int count, fix;
4401 char *p;
4402
4403 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4404
4405 switch (fragp->fr_type)
4406 {
4407 case rs_align_test:
4408 if (count != 0)
4409 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4410 break;
4411
4412 case rs_align_code:
4413 p = fragp->fr_literal + fragp->fr_fix;
4414 fix = 0;
4415
4416 if (count & 3)
4417 {
4418 fix = count & 3;
4419 memset (p, 0, fix);
4420 p += fix;
4421 count -= fix;
4422 }
4423
4424 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4425 {
4426 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4427 if (INSN_BIG_ENDIAN)
4428 number_to_chars_bigendian (p, wval, 4);
4429 else
4430 number_to_chars_littleendian (p, wval, 4);
4431 p += 4;
4432 count -= 4;
4433 fix += 4;
4434 }
4435
4436 if (INSN_BIG_ENDIAN)
4437 number_to_chars_bigendian (p, 0x01000000, 4);
4438 else
4439 number_to_chars_littleendian (p, 0x01000000, 4);
4440
4441 fragp->fr_fix += fix;
4442 fragp->fr_var = 4;
4443 break;
4444
4445 default:
4446 break;
4447 }
4448 }
4449
4450 #ifdef OBJ_ELF
4451 /* Some special processing for a Sparc ELF file. */
4452
4453 void
4454 sparc_elf_final_processing (void)
4455 {
4456 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4457 sort of BFD interface for this. */
4458 if (sparc_arch_size == 64)
4459 {
4460 switch (sparc_memory_model)
4461 {
4462 case MM_RMO:
4463 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4464 break;
4465 case MM_PSO:
4466 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4467 break;
4468 default:
4469 break;
4470 }
4471 }
4472 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4473 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4474 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4475 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4476 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4477 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4478 }
4479
4480 void
4481 sparc_cons (expressionS *exp, int size)
4482 {
4483 char *save;
4484
4485 SKIP_WHITESPACE ();
4486 sparc_cons_special_reloc = NULL;
4487 save = input_line_pointer;
4488 if (input_line_pointer[0] == '%'
4489 && input_line_pointer[1] == 'r'
4490 && input_line_pointer[2] == '_')
4491 {
4492 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4493 {
4494 input_line_pointer += 7;
4495 sparc_cons_special_reloc = "disp";
4496 }
4497 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4498 {
4499 if (size != 4 && size != 8)
4500 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4501 else
4502 {
4503 input_line_pointer += 6;
4504 sparc_cons_special_reloc = "plt";
4505 }
4506 }
4507 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4508 {
4509 if (size != 4 && size != 8)
4510 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4511 else
4512 {
4513 input_line_pointer += 13;
4514 sparc_cons_special_reloc = "tls_dtpoff";
4515 }
4516 }
4517 if (sparc_cons_special_reloc)
4518 {
4519 int bad = 0;
4520
4521 switch (size)
4522 {
4523 case 1:
4524 if (*input_line_pointer != '8')
4525 bad = 1;
4526 input_line_pointer--;
4527 break;
4528 case 2:
4529 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4530 bad = 1;
4531 break;
4532 case 4:
4533 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4534 bad = 1;
4535 break;
4536 case 8:
4537 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4538 bad = 1;
4539 break;
4540 default:
4541 bad = 1;
4542 break;
4543 }
4544
4545 if (bad)
4546 {
4547 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4548 sparc_cons_special_reloc, size * 8, size);
4549 }
4550 else
4551 {
4552 input_line_pointer += 2;
4553 if (*input_line_pointer != '(')
4554 {
4555 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4556 sparc_cons_special_reloc, size * 8);
4557 bad = 1;
4558 }
4559 }
4560
4561 if (bad)
4562 {
4563 input_line_pointer = save;
4564 sparc_cons_special_reloc = NULL;
4565 }
4566 else
4567 {
4568 int c;
4569 char *end = ++input_line_pointer;
4570 int npar = 0;
4571
4572 while (! is_end_of_line[(c = *end)])
4573 {
4574 if (c == '(')
4575 npar++;
4576 else if (c == ')')
4577 {
4578 if (!npar)
4579 break;
4580 npar--;
4581 }
4582 end++;
4583 }
4584
4585 if (c != ')')
4586 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4587 sparc_cons_special_reloc, size * 8);
4588 else
4589 {
4590 *end = '\0';
4591 expression (exp);
4592 *end = c;
4593 if (input_line_pointer != end)
4594 {
4595 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4596 sparc_cons_special_reloc, size * 8);
4597 }
4598 else
4599 {
4600 input_line_pointer++;
4601 SKIP_WHITESPACE ();
4602 c = *input_line_pointer;
4603 if (! is_end_of_line[c] && c != ',')
4604 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4605 sparc_cons_special_reloc, size * 8);
4606 }
4607 }
4608 }
4609 }
4610 }
4611 if (sparc_cons_special_reloc == NULL)
4612 expression (exp);
4613 }
4614
4615 #endif
4616
4617 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4618 reloc for a cons. We could use the definition there, except that
4619 we want to handle little endian relocs specially. */
4620
4621 void
4622 cons_fix_new_sparc (fragS *frag,
4623 int where,
4624 unsigned int nbytes,
4625 expressionS *exp)
4626 {
4627 bfd_reloc_code_real_type r;
4628
4629 r = (nbytes == 1 ? BFD_RELOC_8 :
4630 (nbytes == 2 ? BFD_RELOC_16 :
4631 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4632
4633 if (target_little_endian_data
4634 && nbytes == 4
4635 && now_seg->flags & SEC_ALLOC)
4636 r = BFD_RELOC_SPARC_REV32;
4637
4638 if (sparc_cons_special_reloc)
4639 {
4640 if (*sparc_cons_special_reloc == 'd')
4641 switch (nbytes)
4642 {
4643 case 1: r = BFD_RELOC_8_PCREL; break;
4644 case 2: r = BFD_RELOC_16_PCREL; break;
4645 case 4: r = BFD_RELOC_32_PCREL; break;
4646 case 8: r = BFD_RELOC_64_PCREL; break;
4647 default: abort ();
4648 }
4649 else if (*sparc_cons_special_reloc == 'p')
4650 switch (nbytes)
4651 {
4652 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4653 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4654 }
4655 else
4656 switch (nbytes)
4657 {
4658 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4659 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4660 }
4661 }
4662 else if (sparc_no_align_cons)
4663 {
4664 switch (nbytes)
4665 {
4666 case 2: r = BFD_RELOC_SPARC_UA16; break;
4667 case 4: r = BFD_RELOC_SPARC_UA32; break;
4668 case 8: r = BFD_RELOC_SPARC_UA64; break;
4669 default: abort ();
4670 }
4671 }
4672
4673 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4674 sparc_cons_special_reloc = NULL;
4675 }
4676
4677 void
4678 sparc_cfi_frame_initial_instructions (void)
4679 {
4680 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4681 }
4682
4683 int
4684 sparc_regname_to_dw2regnum (char *regname)
4685 {
4686 char *p, *q;
4687
4688 if (!regname[0])
4689 return -1;
4690
4691 q = "goli";
4692 p = strchr (q, regname[0]);
4693 if (p)
4694 {
4695 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4696 return -1;
4697 return (p - q) * 8 + regname[1] - '0';
4698 }
4699 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4700 return 14;
4701 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4702 return 30;
4703 if (regname[0] == 'f' || regname[0] == 'r')
4704 {
4705 unsigned int regnum;
4706
4707 regnum = strtoul (regname + 1, &q, 10);
4708 if (p == q || *q)
4709 return -1;
4710 if (regnum >= ((regname[0] == 'f'
4711 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4712 ? 64 : 32))
4713 return -1;
4714 if (regname[0] == 'f')
4715 {
4716 regnum += 32;
4717 if (regnum >= 64 && (regnum & 1))
4718 return -1;
4719 }
4720 return regnum;
4721 }
4722 return -1;
4723 }
4724
4725 void
4726 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4727 {
4728 sparc_cons_special_reloc = "disp";
4729 sparc_no_align_cons = 1;
4730 emit_expr (exp, nbytes);
4731 sparc_no_align_cons = 0;
4732 sparc_cons_special_reloc = NULL;
4733 }
GDB Binutils - Deliverables
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