1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_sparc_asi (char **, const sparc_asi
**);
40 static int parse_keyword_arg (int (*) (const char *), char **, int *);
41 static int parse_const_expr_arg (char **, int *);
42 static int get_expression (char *);
44 /* Default architecture. */
45 /* ??? The default value should be V8, but sparclite support was added
46 by making it the default. GCC now passes -Asparclite, so maybe sometime in
47 the future we can set this to V8. */
49 #define DEFAULT_ARCH "sparclite"
51 static const char *default_arch
= DEFAULT_ARCH
;
53 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 static int default_init_p
;
57 /* Current architecture. We don't bump up unless necessary. */
58 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
60 /* The maximum architecture level we can bump up to.
61 In a 32 bit environment, don't allow bumping up to v9 by default.
62 The native assembler works this way. The user is required to pass
63 an explicit argument before we'll create v9 object files. However, if
64 we don't see any v9 insns, a v8plus object file is not created. */
65 static enum sparc_opcode_arch_val max_architecture
;
67 /* Either 32 or 64, selects file format. */
68 static int sparc_arch_size
;
69 /* Initial (default) value, recorded separately in case a user option
70 changes the value before md_show_usage is called. */
71 static int default_arch_size
;
74 /* The currently selected v9 memory model. Currently only used for
76 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
79 /* Bitmask of instruction types seen so far, used to populate the
80 GNU attributes section with hwcap information. */
81 static bfd_uint64_t hwcap_seen
;
85 static bfd_uint64_t hwcap_allowed
;
87 static int architecture_requested
;
88 static int warn_on_bump
;
90 /* If warn_on_bump and the needed architecture is higher than this
91 architecture, issue a warning. */
92 static enum sparc_opcode_arch_val warn_after_architecture
;
94 /* Non-zero if the assembler should generate error if an undeclared
95 g[23] register has been used in -64. */
96 static int no_undeclared_regs
;
98 /* Non-zero if the assembler should generate a warning if an
99 unpredictable DCTI (delayed control transfer instruction) couple is
101 static int dcti_couples_detect
;
103 /* Non-zero if we should try to relax jumps and calls. */
104 static int sparc_relax
;
106 /* Non-zero if we are generating PIC code. */
109 /* Non-zero if we should give an error when misaligned data is seen. */
110 static int enforce_aligned_data
;
112 extern int target_big_endian
;
114 static int target_little_endian_data
;
116 /* Symbols for global registers on v9. */
117 static symbolS
*globals
[8];
119 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
120 int sparc_cie_data_alignment
;
122 /* V9 and 86x have big and little endian data, but instructions are always big
123 endian. The sparclet has bi-endian support but both data and insns have
124 the same endianness. Global `target_big_endian' is used for data.
125 The following macro is used for instructions. */
126 #ifndef INSN_BIG_ENDIAN
127 #define INSN_BIG_ENDIAN (target_big_endian \
128 || default_arch_type == sparc86x \
129 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
132 /* Handle of the OPCODE hash table. */
133 static struct hash_control
*op_hash
;
135 static void s_data1 (void);
136 static void s_seg (int);
137 static void s_proc (int);
138 static void s_reserve (int);
139 static void s_common (int);
140 static void s_empty (int);
141 static void s_uacons (int);
142 static void s_ncons (int);
144 static void s_register (int);
147 const pseudo_typeS md_pseudo_table
[] =
149 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common
, 0},
151 {"empty", s_empty
, 0},
152 {"global", s_globl
, 0},
154 {"nword", s_ncons
, 0},
155 {"optim", s_ignore
, 0},
157 {"reserve", s_reserve
, 0},
159 {"skip", s_space
, 0},
162 {"uahalf", s_uacons
, 2},
163 {"uaword", s_uacons
, 4},
164 {"uaxword", s_uacons
, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons
, 2},
168 {"4byte", s_uacons
, 4},
169 {"8byte", s_uacons
, 8},
170 {"register", s_register
, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars
[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars
[] = "#";
190 const char line_separator_chars
[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS
[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode
;
211 struct nlist
*nlistp
;
215 bfd_reloc_code_real_type reloc
;
218 struct sparc_it the_insn
, set_insn
;
220 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
222 /* Table of arguments to -A.
223 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
224 for this use. That table is for opcodes only. This table is for opcodes
227 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
228 v8plusa
, v9
, v9a
, v9b
, v9_64
};
230 static struct sparc_arch
{
232 const char *opcode_arch
;
233 enum sparc_arch_types arch_type
;
234 /* Default word size, as specified during configuration.
235 A value of zero means can't be used to specify default architecture. */
236 int default_arch_size
;
237 /* Allowable arg to -A? */
239 /* Extra hardware capabilities allowed. These are added to the
240 hardware capabilities associated with the opcode
244 } sparc_arch_table
[] = {
245 { "v6", "v6", v6
, 0, 1, 0, 0 },
246 { "v7", "v7", v7
, 0, 1, 0, 0 },
247 { "v8", "v8", v8
, 32, 1, 0, 0 },
248 { "v8a", "v8", v8
, 32, 1, 0, 0 },
249 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
250 { "sparcvis", "v9a", v9
, 0, 1, 0, 0 },
251 { "sparcvis2", "v9b", v9
, 0, 1, 0, 0 },
252 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_FMAF
, 0 },
253 { "sparcima", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_IMA
, 0 },
254 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
255 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
257 { "sparc4", "v9v", v9
, 0, 1, 0, 0 },
258 { "sparc5", "v9m", v9
, 0, 1, 0, 0 },
259 { "sparc6", "m8", v9
, 0, 1, 0, 0 },
261 { "leon", "leon", leon
, 32, 1, 0, 0 },
262 { "sparclet", "sparclet", sparclet
, 32, 1, 0, 0 },
263 { "sparclite", "sparclite", sparclite
, 32, 1, 0, 0 },
264 { "sparc86x", "sparclite", sparc86x
, 32, 1, 0, 0 },
266 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
267 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
268 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
269 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
270 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
271 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
272 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
273 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
274 { "v8plusm8", "m8", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
276 { "v9", "v9", v9
, 0, 1, 0, 0 },
277 { "v9a", "v9a", v9
, 0, 1, 0, 0 },
278 { "v9b", "v9b", v9
, 0, 1, 0, 0 },
279 { "v9c", "v9c", v9
, 0, 1, 0, 0 },
280 { "v9d", "v9d", v9
, 0, 1, 0, 0 },
281 { "v9e", "v9e", v9
, 0, 1, 0, 0 },
282 { "v9v", "v9v", v9
, 0, 1, 0, 0 },
283 { "v9m", "v9m", v9
, 0, 1, 0, 0 },
284 { "v9m8", "m8", v9
, 0, 1, 0, 0 },
286 /* This exists to allow configure.tgt to pass one
287 value to specify both the default machine and default word size. */
288 { "v9-64", "v9", v9
, 64, 0, 0, 0 },
289 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
292 /* Variant of default_arch */
293 static enum sparc_arch_types default_arch_type
;
295 static struct sparc_arch
*
296 lookup_arch (const char *name
)
298 struct sparc_arch
*sa
;
300 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
301 if (strcmp (sa
->name
, name
) == 0)
303 if (sa
->name
== NULL
)
308 /* Initialize the default opcode arch and word size from the default
309 architecture name. */
312 init_default_arch (void)
314 struct sparc_arch
*sa
= lookup_arch (default_arch
);
317 || sa
->default_arch_size
== 0)
318 as_fatal (_("Invalid default architecture, broken assembler."));
320 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
321 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
322 as_fatal (_("Bad opcode table, broken assembler."));
323 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
325 default_arch_type
= sa
->arch_type
;
328 /* Called by TARGET_MACH. */
333 /* We don't get a chance to initialize anything before we're called,
334 so handle that now. */
335 if (! default_init_p
)
336 init_default_arch ();
338 return sparc_arch_size
== 64 ? bfd_mach_sparc_v9
: bfd_mach_sparc
;
341 /* Called by TARGET_FORMAT. */
344 sparc_target_format (void)
346 /* We don't get a chance to initialize anything before we're called,
347 so handle that now. */
348 if (! default_init_p
)
349 init_default_arch ();
353 return "a.out-sparc-netbsd";
356 if (target_big_endian
)
357 return "a.out-sunos-big";
358 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
359 return "a.out-sunos-big";
361 return "a.out-sparc-little";
363 return "a.out-sunos-big";
370 return "coff-sparc-lynx";
377 return "elf32-sparc-vxworks";
381 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
388 * Invocation line includes a switch not recognized by the base assembler.
389 * See if it's a processor-specific option. These are:
392 * Warn on architecture bumps. See also -A.
394 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
395 * Standard 32 bit architectures.
397 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
398 * This used to only mean 64 bits, but properly specifying it
399 * complicated gcc's ASM_SPECs, so now opcode selection is
400 * specified orthogonally to word size (except when specifying
401 * the default, but that is an internal implementation detail).
402 * -Av8plus, -Av8plusa, -Av8plusb
403 * Same as -Av9{,a,b}.
404 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
405 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
407 * -xarch=v9, -xarch=v9a, -xarch=v9b
408 * Same as -Av9{,a,b} -64, for compatibility with Sun's
411 * Select the architecture and possibly the file format.
412 * Instructions or features not supported by the selected
413 * architecture cause fatal errors.
415 * The default is to start at v6, and bump the architecture up
416 * whenever an instruction is seen at a higher level. In 32 bit
417 * environments, v9 is not bumped up to, the user must pass
420 * If -bump is specified, a warning is printing when bumping to
423 * If an architecture is specified, all instructions must match
424 * that architecture. Any higher level instructions are flagged
425 * as errors. Note that in the 32 bit environment specifying
426 * -Av8plus does not automatically create a v8plus object file, a
427 * v9 insn must be seen.
429 * If both an architecture and -bump are specified, the
430 * architecture starts at the specified level, but bumps are
431 * warnings. Note that we can't set `current_architecture' to
432 * the requested level in this case: in the 32 bit environment,
433 * we still must avoid creating v8plus object files unless v9
437 * Bumping between incompatible architectures is always an
438 * error. For example, from sparclite to v9.
442 const char *md_shortopts
= "A:K:VQ:sq";
445 const char *md_shortopts
= "A:k";
447 const char *md_shortopts
= "A:";
450 struct option md_longopts
[] = {
451 #define OPTION_BUMP (OPTION_MD_BASE)
452 {"bump", no_argument
, NULL
, OPTION_BUMP
},
453 #define OPTION_SPARC (OPTION_MD_BASE + 1)
454 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
455 #define OPTION_XARCH (OPTION_MD_BASE + 2)
456 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
458 #define OPTION_32 (OPTION_MD_BASE + 3)
459 {"32", no_argument
, NULL
, OPTION_32
},
460 #define OPTION_64 (OPTION_MD_BASE + 4)
461 {"64", no_argument
, NULL
, OPTION_64
},
462 #define OPTION_TSO (OPTION_MD_BASE + 5)
463 {"TSO", no_argument
, NULL
, OPTION_TSO
},
464 #define OPTION_PSO (OPTION_MD_BASE + 6)
465 {"PSO", no_argument
, NULL
, OPTION_PSO
},
466 #define OPTION_RMO (OPTION_MD_BASE + 7)
467 {"RMO", no_argument
, NULL
, OPTION_RMO
},
469 #ifdef SPARC_BIENDIAN
470 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
471 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
472 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
473 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
475 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
476 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
477 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
478 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
480 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
481 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
482 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
483 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
485 #define OPTION_RELAX (OPTION_MD_BASE + 14)
486 {"relax", no_argument
, NULL
, OPTION_RELAX
},
487 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
488 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
489 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
490 {"dcti-couples-detect", no_argument
, NULL
, OPTION_DCTI_COUPLES_DETECT
},
491 {NULL
, no_argument
, NULL
, 0}
494 size_t md_longopts_size
= sizeof (md_longopts
);
497 md_parse_option (int c
, const char *arg
)
499 /* We don't get a chance to initialize anything before we're called,
500 so handle that now. */
501 if (! default_init_p
)
502 init_default_arch ();
508 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
513 if (!strncmp (arg
, "v9", 2))
514 md_parse_option (OPTION_64
, NULL
);
517 if (!strncmp (arg
, "v8", 2)
518 || !strncmp (arg
, "v7", 2)
519 || !strncmp (arg
, "v6", 2)
520 || !strcmp (arg
, "sparclet")
521 || !strcmp (arg
, "sparclite")
522 || !strcmp (arg
, "sparc86x"))
523 md_parse_option (OPTION_32
, NULL
);
530 struct sparc_arch
*sa
;
531 enum sparc_opcode_arch_val opcode_arch
;
533 sa
= lookup_arch (arg
);
535 || ! sa
->user_option_p
)
537 if (c
== OPTION_XARCH
)
538 as_bad (_("invalid architecture -xarch=%s"), arg
);
540 as_bad (_("invalid architecture -A%s"), arg
);
544 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
545 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
546 as_fatal (_("Bad opcode table, broken assembler."));
548 if (!architecture_requested
549 || opcode_arch
> max_architecture
)
550 max_architecture
= opcode_arch
;
552 /* The allowed hardware capabilities are the implied by the
553 opcodes arch plus any extra capabilities defined in the GAS
557 | (((bfd_uint64_t
) sparc_opcode_archs
[opcode_arch
].hwcaps2
) << 32)
558 | (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32)
559 | sparc_opcode_archs
[opcode_arch
].hwcaps
560 | sa
->hwcap_allowed
);
561 architecture_requested
= 1;
566 /* Ignore -sparc, used by SunOS make default .s.o rule. */
569 case OPTION_ENFORCE_ALIGNED_DATA
:
570 enforce_aligned_data
= 1;
573 #ifdef SPARC_BIENDIAN
574 case OPTION_LITTLE_ENDIAN
:
575 target_big_endian
= 0;
576 if (default_arch_type
!= sparclet
)
577 as_fatal ("This target does not support -EL");
579 case OPTION_LITTLE_ENDIAN_DATA
:
580 target_little_endian_data
= 1;
581 target_big_endian
= 0;
582 if (default_arch_type
!= sparc86x
583 && default_arch_type
!= v9
)
584 as_fatal ("This target does not support --little-endian-data");
586 case OPTION_BIG_ENDIAN
:
587 target_big_endian
= 1;
601 const char **list
, **l
;
603 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
604 list
= bfd_target_list ();
605 for (l
= list
; *l
!= NULL
; l
++)
607 if (sparc_arch_size
== 32)
609 if (CONST_STRNEQ (*l
, "elf32-sparc"))
614 if (CONST_STRNEQ (*l
, "elf64-sparc"))
619 as_fatal (_("No compiled in support for %d bit object file format"),
623 if (sparc_arch_size
== 64
624 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
625 max_architecture
= SPARC_OPCODE_ARCH_V9
;
630 sparc_memory_model
= MM_TSO
;
634 sparc_memory_model
= MM_PSO
;
638 sparc_memory_model
= MM_RMO
;
646 /* Qy - do emit .comment
647 Qn - do not emit .comment. */
651 /* Use .stab instead of .stab.excl. */
655 /* quick -- Native assembler does fewer checks. */
659 if (strcmp (arg
, "PIC") != 0)
660 as_warn (_("Unrecognized option following -K"));
665 case OPTION_NO_UNDECLARED_REGS
:
666 no_undeclared_regs
= 1;
669 case OPTION_UNDECLARED_REGS
:
670 no_undeclared_regs
= 0;
678 case OPTION_NO_RELAX
:
682 case OPTION_DCTI_COUPLES_DETECT
:
683 dcti_couples_detect
= 1;
694 md_show_usage (FILE *stream
)
696 const struct sparc_arch
*arch
;
699 /* We don't get a chance to initialize anything before we're called,
700 so handle that now. */
701 if (! default_init_p
)
702 init_default_arch ();
704 fprintf (stream
, _("SPARC options:\n"));
706 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
708 if (!arch
->user_option_p
)
710 if (arch
!= &sparc_arch_table
[0])
711 fprintf (stream
, " | ");
712 if (column
+ strlen (arch
->name
) > 70)
715 fputc ('\n', stream
);
717 column
+= 5 + 2 + strlen (arch
->name
);
718 fprintf (stream
, "-A%s", arch
->name
);
720 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
722 if (!arch
->user_option_p
)
724 fprintf (stream
, " | ");
725 if (column
+ strlen (arch
->name
) > 65)
728 fputc ('\n', stream
);
730 column
+= 5 + 7 + strlen (arch
->name
);
731 fprintf (stream
, "-xarch=%s", arch
->name
);
733 fprintf (stream
, _("\n\
734 specify variant of SPARC architecture\n\
735 -bump warn when assembler switches architectures\n\
737 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
738 -relax relax jumps and branches (default)\n\
739 -no-relax avoid changing any jumps and branches\n"));
741 fprintf (stream
, _("\
742 -k generate PIC\n"));
745 fprintf (stream
, _("\
746 -32 create 32 bit object file\n\
747 -64 create 64 bit object file\n"));
748 fprintf (stream
, _("\
749 [default is %d]\n"), default_arch_size
);
750 fprintf (stream
, _("\
751 -TSO use Total Store Ordering\n\
752 -PSO use Partial Store Ordering\n\
753 -RMO use Relaxed Memory Ordering\n"));
754 fprintf (stream
, _("\
755 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
756 fprintf (stream
, _("\
757 -KPIC generate PIC\n\
758 -V print assembler version number\n\
759 -undeclared-regs ignore application global register usage without\n\
760 appropriate .register directive (default)\n\
761 -no-undeclared-regs force error on application global register usage\n\
762 without appropriate .register directive\n\
763 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
768 #ifdef SPARC_BIENDIAN
769 fprintf (stream
, _("\
770 -EL generate code for a little endian machine\n\
771 -EB generate code for a big endian machine\n\
772 --little-endian-data generate code for a machine having big endian\n\
773 instructions and little endian data.\n"));
777 /* Native operand size opcode translation. */
783 } native_op_table
[] =
785 {"ldn", "ld", "ldx"},
786 {"ldna", "lda", "ldxa"},
787 {"stn", "st", "stx"},
788 {"stna", "sta", "stxa"},
789 {"slln", "sll", "sllx"},
790 {"srln", "srl", "srlx"},
791 {"sran", "sra", "srax"},
792 {"casn", "cas", "casx"},
793 {"casna", "casa", "casxa"},
794 {"clrn", "clr", "clrx"},
798 /* sparc64 privileged and hyperprivileged registers. */
800 struct priv_reg_entry
806 struct priv_reg_entry priv_reg_table
[] =
827 {NULL
, -1}, /* End marker. */
830 struct priv_reg_entry hpriv_reg_table
[] =
840 {"hstick_offset", 28},
841 {"hstick_enable", 29},
843 {NULL
, -1}, /* End marker. */
846 /* v9a or later specific ancillary state registers. */
848 struct priv_reg_entry v9a_asr_table
[] =
851 {"sys_tick_cmpr", 25},
855 {"softint_clear", 21},
866 {"clear_softint", 21},
867 {NULL
, -1}, /* End marker. */
871 cmp_reg_entry (const void *parg
, const void *qarg
)
873 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
874 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
876 if (p
->name
== q
->name
)
878 else if (p
->name
== NULL
)
880 else if (q
->name
== NULL
)
883 return strcmp (q
->name
, p
->name
);
886 /* sparc %-pseudo-operations. */
889 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
890 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
892 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
893 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
895 instruction. (Generally they can appear
896 anywhere an immediate operand is
900 /* The name as it appears in assembler. */
902 /* The reloc this pseudo-op translates to. */
903 bfd_reloc_code_real_type reloc
;
904 /* Flags. See F_POP_* above. */
908 struct pop_entry pop_table
[] =
910 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
911 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
912 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
913 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
914 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
915 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
916 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
917 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
918 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
919 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
920 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
921 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
922 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
923 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
924 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
925 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
926 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
927 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
928 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
929 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
930 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
931 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
932 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
933 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
934 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
935 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
936 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
937 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
938 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
939 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
940 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
941 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
942 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
943 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
944 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
945 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
946 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
949 /* Table of %-names that can appear in a sparc assembly program. This
950 table is initialized in md_begin and contains entries for each
951 privileged/hyperprivileged/alternate register and %-pseudo-op. */
964 enum perc_entry_type type
;
965 /* Name of the %-entity. */
969 /* Value. Either a pop or a reg depending on type.*/
972 struct pop_entry
*pop
;
973 struct priv_reg_entry
*reg
;
977 #define NUM_PERC_ENTRIES \
978 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
979 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
980 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
981 + ARRAY_SIZE (pop_table) \
984 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
987 cmp_perc_entry (const void *parg
, const void *qarg
)
989 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
990 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
992 if (p
->name
== q
->name
)
994 else if (p
->name
== NULL
)
996 else if (q
->name
== NULL
)
999 return strcmp (q
->name
, p
->name
);
1002 /* This function is called once, at assembler startup time. It should
1003 set up all the tables, etc. that the MD part of the assembler will
1009 const char *retval
= NULL
;
1013 /* We don't get a chance to initialize anything before md_parse_option
1014 is called, and it may not be called, so handle default initialization
1015 now if not already done. */
1016 if (! default_init_p
)
1017 init_default_arch ();
1019 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
1020 op_hash
= hash_new ();
1022 while (i
< (unsigned int) sparc_num_opcodes
)
1024 const char *name
= sparc_opcodes
[i
].name
;
1025 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
1028 as_bad (_("Internal error: can't hash `%s': %s\n"),
1029 sparc_opcodes
[i
].name
, retval
);
1034 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
1036 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1037 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
1042 while (i
< (unsigned int) sparc_num_opcodes
1043 && !strcmp (sparc_opcodes
[i
].name
, name
));
1046 for (i
= 0; native_op_table
[i
].name
; i
++)
1048 const struct sparc_opcode
*insn
;
1049 const char *name
= ((sparc_arch_size
== 32)
1050 ? native_op_table
[i
].name32
1051 : native_op_table
[i
].name64
);
1052 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
1055 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1056 name
, native_op_table
[i
].name
);
1061 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1065 as_bad (_("Internal error: can't hash `%s': %s\n"),
1066 sparc_opcodes
[i
].name
, retval
);
1073 as_fatal (_("Broken assembler. No assembly attempted."));
1075 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1076 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1077 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1078 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1079 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1080 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1082 /* If -bump, record the architecture level at which we start issuing
1083 warnings. The behaviour is different depending upon whether an
1084 architecture was explicitly specified. If it wasn't, we issue warnings
1085 for all upwards bumps. If it was, we don't start issuing warnings until
1086 we need to bump beyond the requested architecture or when we bump between
1087 conflicting architectures. */
1090 && architecture_requested
)
1092 /* `max_architecture' records the requested architecture.
1093 Issue warnings if we go above it. */
1094 warn_after_architecture
= max_architecture
;
1097 /* Find the highest architecture level that doesn't conflict with
1098 the requested one. */
1101 || !architecture_requested
)
1103 enum sparc_opcode_arch_val current_max_architecture
1106 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1107 max_architecture
> warn_after_architecture
;
1109 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1110 current_max_architecture
))
1114 /* Prepare the tables of %-pseudo-ops. */
1116 struct priv_reg_entry
*reg_tables
[]
1117 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1118 struct priv_reg_entry
**reg_table
;
1121 /* Add registers. */
1122 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1124 struct priv_reg_entry
*reg
;
1125 for (reg
= *reg_table
; reg
->name
; reg
++)
1127 struct perc_entry
*p
= &perc_table
[entry
++];
1128 p
->type
= perc_entry_reg
;
1129 p
->name
= reg
->name
;
1130 p
->len
= strlen (reg
->name
);
1135 /* Add %-pseudo-ops. */
1136 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1138 struct perc_entry
*p
= &perc_table
[entry
++];
1139 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1140 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1141 p
->name
= pop_table
[i
].name
;
1142 p
->len
= strlen (pop_table
[i
].name
);
1143 p
->pop
= &pop_table
[i
];
1146 /* Last entry is the sentinel. */
1147 perc_table
[entry
].type
= perc_entry_none
;
1149 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1150 sizeof (perc_table
[0]), cmp_perc_entry
);
1155 /* Called after all assembly has been done. */
1161 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1162 int hwcaps
, hwcaps2
;
1165 if (sparc_arch_size
== 64)
1166 switch (current_architecture
)
1168 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1169 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1170 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1171 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1172 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1173 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1174 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1175 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v9m8
; break;
1176 default: mach
= bfd_mach_sparc_v9
; break;
1179 switch (current_architecture
)
1181 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1182 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1183 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1184 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1185 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1186 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1187 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1188 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1189 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1190 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v8plusm8
; break;
1191 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1192 be but for now it is (since that's the way it's always been
1194 default: mach
= bfd_mach_sparc
; break;
1196 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1198 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1199 hwcaps
= hwcap_seen
& U0xffffffff
;
1200 hwcaps2
= hwcap_seen
>> 32;
1203 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1205 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1209 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1212 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1216 /* Sign-extend the value from the architecture word size, so that
1217 0xffffffff is always considered -1 on sparc32. */
1218 if (sparc_arch_size
== 32)
1220 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1221 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1230 /* Return non-zero if VAL is in the range 0 to MAX. */
1233 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1240 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1241 (e.g. -15 to +31). */
1244 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1250 if (val
< ~(max
>> 1))
1256 sparc_ffs (unsigned int mask
)
1263 for (i
= 0; (mask
& 1) == 0; ++i
)
1268 /* Implement big shift right. */
1270 BSR (bfd_vma val
, int amount
)
1272 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1273 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1274 return val
>> amount
;
1277 /* For communication between sparc_ip and get_expression. */
1278 static char *expr_end
;
1280 /* Values for `special_case'.
1281 Instructions that require weird handling because they're longer than
1283 #define SPECIAL_CASE_NONE 0
1284 #define SPECIAL_CASE_SET 1
1285 #define SPECIAL_CASE_SETSW 2
1286 #define SPECIAL_CASE_SETX 3
1287 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1288 #define SPECIAL_CASE_FDIV 4
1290 /* Bit masks of various insns. */
1291 #define NOP_INSN 0x01000000
1292 #define OR_INSN 0x80100000
1293 #define XOR_INSN 0x80180000
1294 #define FMOVS_INSN 0x81A00020
1295 #define SETHI_INSN 0x01000000
1296 #define SLLX_INSN 0x81281000
1297 #define SRA_INSN 0x81380000
1299 /* The last instruction to be assembled. */
1300 static const struct sparc_opcode
*last_insn
;
1301 /* The assembled opcode of `last_insn'. */
1302 static unsigned long last_opcode
;
1304 /* Handle the set and setuw synthetic instructions. */
1307 synthetize_setuw (const struct sparc_opcode
*insn
)
1309 int need_hi22_p
= 0;
1310 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1312 if (the_insn
.exp
.X_op
== O_constant
)
1314 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1316 if (sizeof (offsetT
) > 4
1317 && (the_insn
.exp
.X_add_number
< 0
1318 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1319 as_warn (_("set: number not in 0..4294967295 range"));
1323 if (sizeof (offsetT
) > 4
1324 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1325 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1326 as_warn (_("set: number not in -2147483648..4294967295 range"));
1327 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1331 /* See if operand is absolute and small; skip sethi if so. */
1332 if (the_insn
.exp
.X_op
!= O_constant
1333 || the_insn
.exp
.X_add_number
>= (1 << 12)
1334 || the_insn
.exp
.X_add_number
< -(1 << 12))
1336 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1337 | ((the_insn
.exp
.X_add_number
>> 10)
1338 & (the_insn
.exp
.X_op
== O_constant
1340 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1341 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1342 output_insn (insn
, &the_insn
);
1346 /* See if operand has no low-order bits; skip OR if so. */
1347 if (the_insn
.exp
.X_op
!= O_constant
1348 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1351 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1353 | (the_insn
.exp
.X_add_number
1354 & (the_insn
.exp
.X_op
!= O_constant
1355 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1356 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1357 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1358 output_insn (insn
, &the_insn
);
1362 /* Handle the setsw synthetic instruction. */
1365 synthetize_setsw (const struct sparc_opcode
*insn
)
1369 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1371 if (the_insn
.exp
.X_op
!= O_constant
)
1373 synthetize_setuw (insn
);
1375 /* Need to sign extend it. */
1376 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1377 the_insn
.reloc
= BFD_RELOC_NONE
;
1378 output_insn (insn
, &the_insn
);
1382 if (sizeof (offsetT
) > 4
1383 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1384 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1385 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1387 low32
= the_insn
.exp
.X_add_number
;
1391 synthetize_setuw (insn
);
1397 the_insn
.reloc
= BFD_RELOC_NONE
;
1398 /* See if operand is absolute and small; skip sethi if so. */
1399 if (low32
< -(1 << 12))
1401 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1402 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1403 output_insn (insn
, &the_insn
);
1404 low32
= 0x1c00 | (low32
& 0x3ff);
1405 opc
= RS1 (rd
) | XOR_INSN
;
1408 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1409 | (low32
& 0x1fff));
1410 output_insn (insn
, &the_insn
);
1413 /* Handle the setx synthetic instruction. */
1416 synthetize_setx (const struct sparc_opcode
*insn
)
1418 int upper32
, lower32
;
1419 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1420 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1422 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1423 int need_xor10_p
= 0;
1425 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1426 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1427 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1430 upper_dstreg
= tmpreg
;
1431 /* The tmp reg should not be the dst reg. */
1432 if (tmpreg
== dstreg
)
1433 as_warn (_("setx: temporary register same as destination register"));
1435 /* ??? Obviously there are other optimizations we can do
1436 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1437 doing some of these. Later. If you do change things, try to
1438 change all of this to be table driven as well. */
1439 /* What to output depends on the number if it's constant.
1440 Compute that first, then output what we've decided upon. */
1441 if (the_insn
.exp
.X_op
!= O_constant
)
1443 if (sparc_arch_size
== 32)
1445 /* When arch size is 32, we want setx to be equivalent
1446 to setuw for anything but constants. */
1447 the_insn
.exp
.X_add_number
&= 0xffffffff;
1448 synthetize_setuw (insn
);
1451 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1457 /* Reset X_add_number, we've extracted it as upper32/lower32.
1458 Otherwise fixup_segment will complain about not being able to
1459 write an 8 byte number in a 4 byte field. */
1460 the_insn
.exp
.X_add_number
= 0;
1462 /* Only need hh22 if `or' insn can't handle constant. */
1463 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1466 /* Does bottom part (after sethi) have bits? */
1467 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1468 /* No hh22, but does upper32 still have bits we can't set
1470 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1473 /* If the lower half is all zero, we build the upper half directly
1474 into the dst reg. */
1476 /* Need lower half if number is zero or 0xffffffff00000000. */
1477 || (! need_hh22_p
&& ! need_hm10_p
))
1479 /* No need for sethi if `or' insn can handle constant. */
1480 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1481 /* Note that we can't use a negative constant in the `or'
1482 insn unless the upper 32 bits are all ones. */
1483 || (lower32
< 0 && upper32
!= -1)
1484 || (lower32
>= 0 && upper32
== -1))
1487 if (need_hi22_p
&& upper32
== -1)
1490 /* Does bottom part (after sethi) have bits? */
1491 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1493 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1494 /* Need `or' if we didn't set anything else. */
1495 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1499 /* Output directly to dst reg if lower 32 bits are all zero. */
1500 upper_dstreg
= dstreg
;
1503 if (!upper_dstreg
&& dstreg
)
1504 as_warn (_("setx: illegal temporary register g0"));
1508 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1509 | ((upper32
>> 10) & 0x3fffff));
1510 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1511 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1512 output_insn (insn
, &the_insn
);
1517 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1518 | (((need_xor10_p
? ~lower32
: lower32
)
1519 >> 10) & 0x3fffff));
1520 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1521 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1522 output_insn (insn
, &the_insn
);
1527 the_insn
.opcode
= (OR_INSN
1528 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1531 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1532 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1533 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1534 output_insn (insn
, &the_insn
);
1539 /* FIXME: One nice optimization to do here is to OR the low part
1540 with the highpart if hi22 isn't needed and the low part is
1542 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1545 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1546 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1547 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1548 output_insn (insn
, &the_insn
);
1551 /* If we needed to build the upper part, shift it into place. */
1552 if (need_hh22_p
|| need_hm10_p
)
1554 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1556 the_insn
.reloc
= BFD_RELOC_NONE
;
1557 output_insn (insn
, &the_insn
);
1560 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1563 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1564 | 0x1c00 | (lower32
& 0x3ff));
1565 the_insn
.reloc
= BFD_RELOC_NONE
;
1566 output_insn (insn
, &the_insn
);
1569 /* If we needed to build both upper and lower parts, OR them together. */
1570 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1572 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1574 the_insn
.reloc
= BFD_RELOC_NONE
;
1575 output_insn (insn
, &the_insn
);
1579 /* Main entry point to assemble one instruction. */
1582 md_assemble (char *str
)
1584 const struct sparc_opcode
*insn
;
1588 special_case
= sparc_ip (str
, &insn
);
1592 /* Certain instructions may not appear on delay slots. Check for
1593 these situations. */
1594 if (last_insn
!= NULL
1595 && (last_insn
->flags
& F_DELAYED
) != 0)
1597 /* Before SPARC V9 the effect of having a delayed branch
1598 instruction in the delay slot of a conditional delayed branch
1601 In SPARC V9 DCTI couples are well defined.
1603 However, starting with the UltraSPARC Architecture 2005, DCTI
1604 couples (of all kind) are deprecated and should not be used,
1605 as they may be slow or behave differently to what the
1606 programmer expects. */
1607 if (dcti_couples_detect
1608 && (insn
->flags
& F_DELAYED
) != 0
1609 && ((max_architecture
< SPARC_OPCODE_ARCH_V9
1610 && (last_insn
->flags
& F_CONDBR
) != 0)
1611 || max_architecture
>= SPARC_OPCODE_ARCH_V9C
))
1612 as_warn (_("unpredictable DCTI couple"));
1615 /* We warn about attempts to put a floating point branch in a
1616 delay slot, unless the delay slot has been annulled. */
1617 if ((insn
->flags
& F_FBR
) != 0
1618 /* ??? This test isn't completely accurate. We assume anything with
1619 F_{UNBR,CONDBR,FBR} set is annullable. */
1620 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1621 || (last_opcode
& ANNUL
) == 0))
1622 as_warn (_("FP branch in delay slot"));
1625 /* SPARC before v9 requires a nop instruction between a floating
1626 point instruction and a floating point branch. We insert one
1627 automatically, with a warning. */
1628 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1629 && last_insn
!= NULL
1630 && (insn
->flags
& F_FBR
) != 0
1631 && (last_insn
->flags
& F_FLOAT
) != 0)
1633 struct sparc_it nop_insn
;
1635 nop_insn
.opcode
= NOP_INSN
;
1636 nop_insn
.reloc
= BFD_RELOC_NONE
;
1637 output_insn (insn
, &nop_insn
);
1638 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1641 switch (special_case
)
1643 case SPECIAL_CASE_NONE
:
1645 output_insn (insn
, &the_insn
);
1648 case SPECIAL_CASE_SETSW
:
1649 synthetize_setsw (insn
);
1652 case SPECIAL_CASE_SET
:
1653 synthetize_setuw (insn
);
1656 case SPECIAL_CASE_SETX
:
1657 synthetize_setx (insn
);
1660 case SPECIAL_CASE_FDIV
:
1662 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1664 output_insn (insn
, &the_insn
);
1666 /* According to information leaked from Sun, the "fdiv" instructions
1667 on early SPARC machines would produce incorrect results sometimes.
1668 The workaround is to add an fmovs of the destination register to
1669 itself just after the instruction. This was true on machines
1670 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1671 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1672 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1673 output_insn (insn
, &the_insn
);
1678 as_fatal (_("failed special case insn sanity check"));
1683 get_hwcap_name (bfd_uint64_t mask
)
1685 if (mask
& HWCAP_MUL32
)
1687 if (mask
& HWCAP_DIV32
)
1689 if (mask
& HWCAP_FSMULD
)
1691 if (mask
& HWCAP_V8PLUS
)
1693 if (mask
& HWCAP_POPC
)
1695 if (mask
& HWCAP_VIS
)
1697 if (mask
& HWCAP_VIS2
)
1699 if (mask
& HWCAP_ASI_BLK_INIT
)
1700 return "ASIBlkInit";
1701 if (mask
& HWCAP_FMAF
)
1703 if (mask
& HWCAP_VIS3
)
1705 if (mask
& HWCAP_HPC
)
1707 if (mask
& HWCAP_RANDOM
)
1709 if (mask
& HWCAP_TRANS
)
1711 if (mask
& HWCAP_FJFMAU
)
1713 if (mask
& HWCAP_IMA
)
1715 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1717 if (mask
& HWCAP_AES
)
1719 if (mask
& HWCAP_DES
)
1721 if (mask
& HWCAP_KASUMI
)
1723 if (mask
& HWCAP_CAMELLIA
)
1725 if (mask
& HWCAP_MD5
)
1727 if (mask
& HWCAP_SHA1
)
1729 if (mask
& HWCAP_SHA256
)
1731 if (mask
& HWCAP_SHA512
)
1733 if (mask
& HWCAP_MPMUL
)
1735 if (mask
& HWCAP_MONT
)
1737 if (mask
& HWCAP_PAUSE
)
1739 if (mask
& HWCAP_CBCOND
)
1741 if (mask
& HWCAP_CRC32C
)
1745 if (mask
& HWCAP2_FJATHPLUS
)
1747 if (mask
& HWCAP2_VIS3B
)
1749 if (mask
& HWCAP2_ADP
)
1751 if (mask
& HWCAP2_SPARC5
)
1753 if (mask
& HWCAP2_MWAIT
)
1755 if (mask
& HWCAP2_XMPMUL
)
1757 if (mask
& HWCAP2_XMONT
)
1759 if (mask
& HWCAP2_NSEC
)
1761 if (mask
& HWCAP2_SPARC6
)
1763 if (mask
& HWCAP2_ONADDSUB
)
1765 if (mask
& HWCAP2_ONMUL
)
1767 if (mask
& HWCAP2_ONDIV
)
1769 if (mask
& HWCAP2_DICTUNP
)
1771 if (mask
& HWCAP2_FPCMPSHL
)
1773 if (mask
& HWCAP2_RLE
)
1775 if (mask
& HWCAP2_SHA3
)
1781 /* Subroutine of md_assemble to do the actual parsing. */
1784 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1786 const char *error_message
= "";
1790 const struct sparc_opcode
*insn
;
1792 unsigned long opcode
;
1793 unsigned int mask
= 0;
1797 int special_case
= SPECIAL_CASE_NONE
;
1798 const sparc_asi
*sasi
= NULL
;
1805 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1822 as_bad (_("Unknown opcode: `%s'"), str
);
1824 return special_case
;
1826 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1830 as_bad (_("Unknown opcode: `%s'"), str
);
1831 return special_case
;
1841 opcode
= insn
->match
;
1842 memset (&the_insn
, '\0', sizeof (the_insn
));
1843 the_insn
.reloc
= BFD_RELOC_NONE
;
1846 /* Build the opcode, checking as we go to make sure that the
1848 for (args
= insn
->args
;; ++args
)
1856 /* Parse a series of masks. */
1863 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1866 error_message
= _(": invalid membar mask name");
1872 if (*s
== '|' || *s
== '+')
1880 if (! parse_const_expr_arg (&s
, &kmask
))
1882 error_message
= _(": invalid membar mask expression");
1885 if (kmask
< 0 || kmask
> 127)
1887 error_message
= _(": invalid membar mask number");
1892 opcode
|= MEMBAR (kmask
);
1900 if (! parse_const_expr_arg (&s
, &smask
))
1902 error_message
= _(": invalid siam mode expression");
1905 if (smask
< 0 || smask
> 7)
1907 error_message
= _(": invalid siam mode number");
1918 /* Parse a prefetch function. */
1921 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1923 error_message
= _(": invalid prefetch function name");
1929 if (! parse_const_expr_arg (&s
, &fcn
))
1931 error_message
= _(": invalid prefetch function expression");
1934 if (fcn
< 0 || fcn
> 31)
1936 error_message
= _(": invalid prefetch function number");
1946 /* Parse a sparc64 privileged register. */
1949 struct priv_reg_entry
*p
;
1950 unsigned int len
= 9999999; /* Init to make gcc happy. */
1953 for (p
= priv_reg_table
; p
->name
; p
++)
1954 if (p
->name
[0] == s
[0])
1956 len
= strlen (p
->name
);
1957 if (strncmp (p
->name
, s
, len
) == 0)
1963 error_message
= _(": unrecognizable privileged register");
1967 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1969 error_message
= _(": unrecognizable privileged register");
1978 error_message
= _(": unrecognizable privileged register");
1984 /* Parse a sparc64 hyperprivileged register. */
1987 struct priv_reg_entry
*p
;
1988 unsigned int len
= 9999999; /* Init to make gcc happy. */
1991 for (p
= hpriv_reg_table
; p
->name
; p
++)
1992 if (p
->name
[0] == s
[0])
1994 len
= strlen (p
->name
);
1995 if (strncmp (p
->name
, s
, len
) == 0)
2001 error_message
= _(": unrecognizable hyperprivileged register");
2005 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
2007 error_message
= _(": unrecognizable hyperprivileged register");
2016 error_message
= _(": unrecognizable hyperprivileged register");
2022 /* Parse a v9a or later ancillary state register. */
2025 struct priv_reg_entry
*p
;
2026 unsigned int len
= 9999999; /* Init to make gcc happy. */
2029 for (p
= v9a_asr_table
; p
->name
; p
++)
2030 if (p
->name
[0] == s
[0])
2032 len
= strlen (p
->name
);
2033 if (strncmp (p
->name
, s
, len
) == 0)
2039 error_message
= _(": unrecognizable ancillary state register");
2043 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
2045 error_message
= _(": unrecognizable ancillary state register");
2054 error_message
= _(": unrecognizable ancillary state register");
2060 if (strncmp (s
, "%asr", 4) == 0)
2068 while (ISDIGIT (*s
))
2070 num
= num
* 10 + *s
- '0';
2074 /* We used to check here for the asr number to
2075 be between 16 and 31 in V9 and later, as
2076 mandated by the section C.1.1 "Register
2077 Names" in the SPARC spec. However, we
2078 decided to remove this restriction as a) it
2079 introduces problems when new V9 asr registers
2080 are introduced, b) the Solaris assembler
2081 doesn't implement this restriction and c) the
2082 restriction will go away in future revisions
2083 of the Oracle SPARC Architecture. */
2085 if (num
< 0 || 31 < num
)
2087 error_message
= _(": asr number must be between 0 and 31");
2091 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2096 error_message
= _(": expecting %asrN");
2103 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2107 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2113 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2118 if (s
[0] == '0' && s
[1] == 'x')
2121 while (ISXDIGIT (*s
))
2124 num
|= hex_value (*s
);
2130 while (ISDIGIT (*s
))
2132 num
= num
* 10 + *s
- '0';
2136 if (num
< 0 || num
> 31)
2138 error_message
= _(": crypto immediate must be between 0 and 31");
2142 opcode
|= RS3 (num
);
2147 error_message
= _(": expecting crypto immediate");
2152 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2153 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2154 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2156 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2157 /* These fields are unsigned, but for upward compatibility,
2158 allow negative values as well. */
2162 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2163 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2164 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2166 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2167 /* These fields are unsigned, but for upward compatibility,
2168 allow negative values as well. */
2172 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2177 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2182 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2187 if (*s
== 'p' && s
[1] == 'n')
2195 if (*s
== 'p' && s
[1] == 't')
2207 if ((strncmp (s
, "%icc", 4) == 0)
2208 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2220 if ((strncmp (s
, "%xcc", 4) == 0)
2221 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2233 if (strncmp (s
, "%fcc0", 5) == 0)
2245 if (strncmp (s
, "%fcc1", 5) == 0)
2257 if (strncmp (s
, "%fcc2", 5) == 0)
2269 if (strncmp (s
, "%fcc3", 5) == 0)
2277 if (strncmp (s
, "%pc", 3) == 0)
2285 if (strncmp (s
, "%tick", 5) == 0)
2292 case '\0': /* End of args. */
2293 if (s
[0] == ',' && s
[1] == '%')
2297 const struct perc_entry
*p
;
2299 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2300 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2301 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2303 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2306 if (s
[p
->len
+ 2] != '(')
2308 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2309 return special_case
;
2312 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2313 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2315 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2317 return special_case
;
2320 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2321 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2322 || the_insn
.exp
.X_add_number
!= 0
2323 || the_insn
.exp
.X_add_symbol
2324 != symbol_find_or_make ("__tls_get_addr")))
2326 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2328 return special_case
;
2331 the_insn
.reloc
= p
->pop
->reloc
;
2332 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2335 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2338 else if (*s1
== ')')
2347 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2348 return special_case
;
2352 (void) get_expression (s
);
2372 case '[': /* These must match exactly. */
2380 case '#': /* Must be at least one digit. */
2383 while (ISDIGIT (*s
))
2391 case 'C': /* Coprocessor state register. */
2392 if (strncmp (s
, "%csr", 4) == 0)
2399 case 'b': /* Next operand is a coprocessor register. */
2402 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2407 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2421 opcode
|= mask
<< 14;
2429 opcode
|= mask
<< 25;
2435 case 'r': /* next operand must be a register */
2445 case 'f': /* frame pointer */
2453 case 'g': /* global register */
2462 case 'i': /* in register */
2466 mask
= c
- '0' + 24;
2471 case 'l': /* local register */
2475 mask
= (c
- '0' + 16);
2480 case 'o': /* out register */
2484 mask
= (c
- '0' + 8);
2489 case 's': /* stack pointer */
2497 case 'r': /* any register */
2498 if (!ISDIGIT ((c
= *s
++)))
2515 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2531 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2532 && no_undeclared_regs
&& ! globals
[mask
])
2533 as_bad (_("detected global register use not covered by .register pseudo-op"));
2535 /* Got the register, now figure out where
2536 it goes in the opcode. */
2540 opcode
|= mask
<< 14;
2548 opcode
|= mask
<< 25;
2552 opcode
|= (mask
<< 25) | (mask
<< 14);
2556 opcode
|= (mask
<< 25) | (mask
<< 0);
2562 case 'e': /* next operand is a floating point register */
2585 && ((format
= *s
) == 'f'
2590 for (mask
= 0; ISDIGIT (*s
); ++s
)
2592 mask
= 10 * mask
+ (*s
- '0');
2593 } /* read the number */
2603 /* register must be even numbered */
2613 /* register must be multiple of 4 */
2622 /* register must be multiple of 8 */
2626 if (*args
== '\'' && mask
< 48)
2628 /* register must be higher or equal than %f48 */
2634 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2635 error_message
= _(": There are only 64 f registers; [0-63]");
2637 error_message
= _(": There are only 32 f registers; [0-31]");
2640 else if (mask
>= 32)
2642 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2644 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2647 = _(": There are only 32 single precision f registers; [0-31]");
2651 mask
-= 31; /* wrap high bit */
2655 error_message
= _(": There are only 32 f registers; [0-31]");
2663 } /* if not an 'f' register. */
2665 if (*args
== '}' && mask
!= RS2 (opcode
))
2668 = _(": Instruction requires frs2 and frsd must be the same register");
2678 opcode
|= RS1 (mask
);
2685 opcode
|= RS2 (mask
);
2689 opcode
|= RS2 (mask
& 0xe);
2694 opcode
|= RS3 (mask
);
2702 opcode
|= RD (mask
);
2711 if (strncmp (s
, "%fsr", 4) == 0)
2719 if (strncmp (s
, "%efsr", 5) == 0)
2726 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2727 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2730 case 'l': /* 22 bit PC relative immediate */
2731 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2735 case 'L': /* 30 bit immediate */
2736 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2741 case 'n': /* 22 bit immediate */
2742 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2745 case 'i': /* 13 bit immediate */
2746 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2756 const char *op_arg
= NULL
;
2757 static expressionS op_exp
;
2758 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2760 /* Check for %hi, etc. */
2763 const struct perc_entry
*p
;
2765 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2766 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2767 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2769 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2772 if (s
[p
->len
+ 1] != '(')
2774 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2775 return special_case
;
2779 the_insn
.reloc
= p
->pop
->reloc
;
2781 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2784 /* Note that if the get_expression() fails, we will still
2785 have created U entries in the symbol table for the
2786 'symbols' in the input string. Try not to create U
2787 symbols for registers, etc. */
2789 /* This stuff checks to see if the expression ends in
2790 +%reg. If it does, it removes the register from
2791 the expression, and re-sets 's' to point to the
2798 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2801 else if (*s1
== ')')
2810 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2811 return special_case
;
2815 (void) get_expression (s
);
2819 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2820 return special_case
;
2823 if (*s
== ',' || *s
== ']' || !*s
)
2825 if (*s
!= '+' && *s
!= '-')
2827 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2828 return special_case
;
2832 op_exp
= the_insn
.exp
;
2833 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2836 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2839 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2841 if (s1
[-2] == '%' && s1
[-3] == '+')
2843 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2845 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2852 if (op_arg
&& s1
== s
+ 1)
2853 the_insn
.exp
.X_op
= O_absent
;
2855 (void) get_expression (s
);
2867 (void) get_expression (s
);
2875 the_insn
.exp2
= the_insn
.exp
;
2876 the_insn
.exp
= op_exp
;
2877 if (the_insn
.exp2
.X_op
== O_absent
)
2878 the_insn
.exp2
.X_op
= O_illegal
;
2879 else if (the_insn
.exp
.X_op
== O_absent
)
2881 the_insn
.exp
= the_insn
.exp2
;
2882 the_insn
.exp2
.X_op
= O_illegal
;
2884 else if (the_insn
.exp
.X_op
== O_constant
)
2886 valueT val
= the_insn
.exp
.X_add_number
;
2887 switch (the_insn
.reloc
)
2892 case BFD_RELOC_SPARC_HH22
:
2893 val
= BSR (val
, 32);
2896 case BFD_RELOC_SPARC_LM22
:
2897 case BFD_RELOC_HI22
:
2898 val
= (val
>> 10) & 0x3fffff;
2901 case BFD_RELOC_SPARC_HM10
:
2902 val
= BSR (val
, 32);
2905 case BFD_RELOC_LO10
:
2909 case BFD_RELOC_SPARC_H34
:
2914 case BFD_RELOC_SPARC_H44
:
2919 case BFD_RELOC_SPARC_M44
:
2924 case BFD_RELOC_SPARC_L44
:
2928 case BFD_RELOC_SPARC_HIX22
:
2930 val
= (val
>> 10) & 0x3fffff;
2933 case BFD_RELOC_SPARC_LOX10
:
2934 val
= (val
& 0x3ff) | 0x1c00;
2937 the_insn
.exp
= the_insn
.exp2
;
2938 the_insn
.exp
.X_add_number
+= val
;
2939 the_insn
.exp2
.X_op
= O_illegal
;
2940 the_insn
.reloc
= old_reloc
;
2942 else if (the_insn
.exp2
.X_op
!= O_constant
)
2944 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2945 return special_case
;
2949 if (old_reloc
!= BFD_RELOC_SPARC13
2950 || the_insn
.reloc
!= BFD_RELOC_LO10
2951 || sparc_arch_size
!= 64
2954 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2955 return special_case
;
2957 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2961 /* Check for constants that don't require emitting a reloc. */
2962 if (the_insn
.exp
.X_op
== O_constant
2963 && the_insn
.exp
.X_add_symbol
== 0
2964 && the_insn
.exp
.X_op_symbol
== 0)
2966 /* For pc-relative call instructions, we reject
2967 constants to get better code. */
2969 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2970 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2972 error_message
= _(": PC-relative operand can't be a constant");
2976 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2977 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2979 error_message
= _(": TLS operand can't be a constant");
2983 /* Constants that won't fit are checked in md_apply_fix
2984 and bfd_install_relocation.
2985 ??? It would be preferable to install the constants
2986 into the insn here and save having to create a fixS
2987 for each one. There already exists code to handle
2988 all the various cases (e.g. in md_apply_fix and
2989 bfd_install_relocation) so duplicating all that code
2990 here isn't right. */
2992 /* This is a special case to handle cbcond instructions
2993 properly, which can need two relocations. The first
2994 one is for the 5-bit immediate field and the latter
2995 is going to be for the WDISP10 branch part. We
2996 handle the R_SPARC_5 immediate directly here so that
2997 we don't need to add support for multiple relocations
2998 in one instruction just yet. */
2999 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
3000 && ((insn
->match
& OP(0x3)) == 0))
3002 valueT val
= the_insn
.exp
.X_add_number
;
3004 the_insn
.reloc
= BFD_RELOC_NONE
;
3005 if (! in_bitfield_range (val
, 0x1f))
3007 error_message
= _(": Immediate value in cbcond is out of range.");
3010 opcode
|= val
& 0x1f;
3031 if (! parse_sparc_asi (&s
, &sasi
))
3033 error_message
= _(": invalid ASI name");
3040 if (! parse_const_expr_arg (&s
, &asi
))
3042 error_message
= _(": invalid ASI expression");
3045 if (asi
< 0 || asi
> 255)
3047 error_message
= _(": invalid ASI number");
3051 opcode
|= ASI (asi
);
3053 } /* Alternate space. */
3056 if (strncmp (s
, "%psr", 4) == 0)
3063 case 'q': /* Floating point queue. */
3064 if (strncmp (s
, "%fq", 3) == 0)
3071 case 'Q': /* Coprocessor queue. */
3072 if (strncmp (s
, "%cq", 3) == 0)
3080 if (strcmp (str
, "set") == 0
3081 || strcmp (str
, "setuw") == 0)
3083 special_case
= SPECIAL_CASE_SET
;
3086 else if (strcmp (str
, "setsw") == 0)
3088 special_case
= SPECIAL_CASE_SETSW
;
3091 else if (strcmp (str
, "setx") == 0)
3093 special_case
= SPECIAL_CASE_SETX
;
3096 else if (strncmp (str
, "fdiv", 4) == 0)
3098 special_case
= SPECIAL_CASE_FDIV
;
3104 if (strncmp (s
, "%asi", 4) != 0)
3110 if (strncmp (s
, "%fprs", 5) != 0)
3116 if (strncmp (s
, "%mcdper",7) != 0)
3122 if (strncmp (s
, "%entropy", 8) != 0)
3128 if (strncmp (s
, "%ccr", 4) != 0)
3134 if (strncmp (s
, "%tbr", 4) != 0)
3140 if (strncmp (s
, "%wim", 4) != 0)
3149 /* Parse a 2-bit immediate. */
3150 if (! parse_const_expr_arg (&s
, &imm2
))
3152 error_message
= _(": non-immdiate imm2 operand");
3155 if ((imm2
& ~0x3) != 0)
3157 error_message
= _(": imm2 immediate operand out of range (0-3)");
3161 opcode
|= ((imm2
& 0x2) << 3) | (imm2
& 0x1);
3167 char *push
= input_line_pointer
;
3170 input_line_pointer
= s
;
3172 if (e
.X_op
== O_constant
)
3174 int n
= e
.X_add_number
;
3175 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3176 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3178 opcode
|= e
.X_add_number
<< 5;
3181 as_bad (_("non-immediate OPF operand, ignored"));
3182 s
= input_line_pointer
;
3183 input_line_pointer
= push
;
3188 if (strncmp (s
, "%y", 2) != 0)
3196 /* Parse a sparclet cpreg. */
3198 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3200 error_message
= _(": invalid cpreg name");
3203 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3208 as_fatal (_("failed sanity check."));
3209 } /* switch on arg code. */
3211 /* Break out of for() loop. */
3213 } /* For each arg that we expect. */
3218 /* Args don't match. */
3219 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3220 && (insn
->name
== insn
[1].name
3221 || !strcmp (insn
->name
, insn
[1].name
)))
3229 as_bad (_("Illegal operands%s"), error_message
);
3230 return special_case
;
3235 /* We have a match. Now see if the architecture is OK. */
3236 /* String to use in case of architecture warning. */
3237 const char *msg_str
= str
;
3238 int needed_arch_mask
= insn
->architecture
;
3240 /* Include the ASI architecture needed as well */
3241 if (sasi
&& needed_arch_mask
> sasi
->architecture
)
3243 needed_arch_mask
= sasi
->architecture
;
3244 msg_str
= sasi
->name
;
3248 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3250 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3252 hwcap_seen
|= hwcaps
;
3257 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3258 if (! needed_arch_mask
)
3260 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3263 if (needed_arch_mask
3264 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3267 /* Can we bump up the architecture? */
3268 else if (needed_arch_mask
3269 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3271 enum sparc_opcode_arch_val needed_architecture
=
3272 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3273 & needed_arch_mask
);
3275 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3277 && needed_architecture
> warn_after_architecture
)
3279 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3280 sparc_opcode_archs
[current_architecture
].name
,
3281 sparc_opcode_archs
[needed_architecture
].name
,
3283 warn_after_architecture
= needed_architecture
;
3285 current_architecture
= needed_architecture
;
3289 | (((bfd_uint64_t
) sparc_opcode_archs
[current_architecture
].hwcaps2
) << 32)
3290 | sparc_opcode_archs
[current_architecture
].hwcaps
);
3293 /* ??? This seems to be a bit fragile. What if the next entry in
3294 the opcode table is the one we want and it is supported?
3295 It is possible to arrange the table today so that this can't
3296 happen but what about tomorrow? */
3299 int arch
, printed_one_p
= 0;
3301 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3303 /* Create a list of the architectures that support the insn. */
3304 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3306 arch
= sparc_ffs (needed_arch_mask
);
3307 while ((1 << arch
) <= needed_arch_mask
)
3309 if ((1 << arch
) & needed_arch_mask
)
3313 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3320 as_bad (_("Architecture mismatch on \"%s %s\"."), str
, argsStart
);
3321 as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
3323 sparc_opcode_archs
[max_architecture
].name
);
3324 return special_case
;
3327 /* Make sure the hwcaps used by the instruction are
3328 currently enabled. */
3329 if (hwcaps
& ~hwcap_allowed
)
3331 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3333 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3335 return special_case
;
3337 } /* If no match. */
3340 } /* Forever looking for a match. */
3342 the_insn
.opcode
= opcode
;
3343 return special_case
;
3347 skip_over_keyword (char *q
)
3349 for (q
= q
+ (*q
== '#' || *q
== '%');
3350 ISALNUM (*q
) || *q
== '_';
3357 parse_sparc_asi (char **input_pointer_p
, const sparc_asi
**value_p
)
3359 const sparc_asi
*value
;
3362 p
= *input_pointer_p
;
3363 q
= skip_over_keyword(p
);
3366 value
= sparc_encode_asi (p
);
3371 *input_pointer_p
= q
;
3375 /* Parse an argument that can be expressed as a keyword.
3376 (eg: #StoreStore or %ccfr).
3377 The result is a boolean indicating success.
3378 If successful, INPUT_POINTER is updated. */
3381 parse_keyword_arg (int (*lookup_fn
) (const char *),
3382 char **input_pointerP
,
3388 p
= *input_pointerP
;
3389 q
= skip_over_keyword(p
);
3392 value
= (*lookup_fn
) (p
);
3397 *input_pointerP
= q
;
3401 /* Parse an argument that is a constant expression.
3402 The result is a boolean indicating success. */
3405 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3407 char *save
= input_line_pointer
;
3410 input_line_pointer
= *input_pointerP
;
3411 /* The next expression may be something other than a constant
3412 (say if we're not processing the right variant of the insn).
3413 Don't call expression unless we're sure it will succeed as it will
3414 signal an error (which we want to defer until later). */
3415 /* FIXME: It might be better to define md_operand and have it recognize
3416 things like %asi, etc. but continuing that route through to the end
3417 is a lot of work. */
3418 if (*input_line_pointer
== '%')
3420 input_line_pointer
= save
;
3424 *input_pointerP
= input_line_pointer
;
3425 input_line_pointer
= save
;
3426 if (exp
.X_op
!= O_constant
)
3428 *valueP
= exp
.X_add_number
;
3432 /* Subroutine of sparc_ip to parse an expression. */
3435 get_expression (char *str
)
3440 save_in
= input_line_pointer
;
3441 input_line_pointer
= str
;
3442 seg
= expression (&the_insn
.exp
);
3443 if (seg
!= absolute_section
3444 && seg
!= text_section
3445 && seg
!= data_section
3446 && seg
!= bss_section
3447 && seg
!= undefined_section
)
3449 the_insn
.error
= _("bad segment");
3450 expr_end
= input_line_pointer
;
3451 input_line_pointer
= save_in
;
3454 expr_end
= input_line_pointer
;
3455 input_line_pointer
= save_in
;
3459 /* Subroutine of md_assemble to output one insn. */
3462 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3464 char *toP
= frag_more (4);
3466 /* Put out the opcode. */
3467 if (INSN_BIG_ENDIAN
)
3468 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3470 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3472 /* Put out the symbol-dependent stuff. */
3473 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3475 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3476 (toP
- frag_now
->fr_literal
), /* Where. */
3481 /* Turn off overflow checking in fixup_segment. We'll do our
3482 own overflow checking in md_apply_fix. This is necessary because
3483 the insn size is 4 and fixup_segment will signal an overflow for
3484 large 8 byte quantities. */
3485 fixP
->fx_no_overflow
= 1;
3486 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3487 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3491 last_opcode
= theinsn
->opcode
;
3494 dwarf2_emit_insn (4);
3499 md_atof (int type
, char *litP
, int *sizeP
)
3501 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3504 /* Write a value out to the object file, using the appropriate
3508 md_number_to_chars (char *buf
, valueT val
, int n
)
3510 if (target_big_endian
)
3511 number_to_chars_bigendian (buf
, val
, n
);
3512 else if (target_little_endian_data
3513 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3514 /* Output debug words, which are not in allocated sections, as big
3516 number_to_chars_bigendian (buf
, val
, n
);
3517 else if (target_little_endian_data
|| ! target_big_endian
)
3518 number_to_chars_littleendian (buf
, val
, n
);
3521 /* Apply a fixS to the frags, now that we know the value it ought to
3525 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3527 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3528 offsetT val
= * (offsetT
*) valP
;
3531 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3533 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3536 /* SPARC ELF relocations don't use an addend in the data field. */
3537 if (fixP
->fx_addsy
!= NULL
)
3539 switch (fixP
->fx_r_type
)
3541 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3542 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3543 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3544 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3545 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3546 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3547 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3548 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3549 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3550 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3551 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3552 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3553 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3554 case BFD_RELOC_SPARC_TLS_IE_LD
:
3555 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3556 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3557 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3558 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3559 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3560 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3561 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3562 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3563 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3564 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3565 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3575 /* This is a hack. There should be a better way to
3576 handle this. Probably in terms of howto fields, once
3577 we can look at these fixups in terms of howtos. */
3578 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3579 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3582 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3583 generate a reloc, then we just want to let the reloc addend set
3584 the value. We do not want to also stuff the addend into the
3585 object file. Including the addend in the object file works when
3586 doing a static link, because the linker will ignore the object
3587 file contents. However, the dynamic linker does not ignore the
3588 object file contents. */
3589 if (fixP
->fx_addsy
!= NULL
3590 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3593 /* When generating PIC code, we do not want an addend for a reloc
3594 against a local symbol. We adjust fx_addnumber to cancel out the
3595 value already included in val, and to also cancel out the
3596 adjustment which bfd_install_relocation will create. */
3598 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3599 && fixP
->fx_addsy
!= NULL
3600 && ! S_IS_COMMON (fixP
->fx_addsy
)
3601 && symbol_section_p (fixP
->fx_addsy
))
3602 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3604 /* When generating PIC code, we need to fiddle to get
3605 bfd_install_relocation to do the right thing for a PC relative
3606 reloc against a local symbol which we are going to keep. */
3608 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3609 && fixP
->fx_addsy
!= NULL
3610 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3611 || S_IS_WEAK (fixP
->fx_addsy
))
3612 && S_IS_DEFINED (fixP
->fx_addsy
)
3613 && ! S_IS_COMMON (fixP
->fx_addsy
))
3616 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3620 /* If this is a data relocation, just output VAL. */
3622 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3624 md_number_to_chars (buf
, val
, 1);
3626 else if (fixP
->fx_r_type
== BFD_RELOC_16
3627 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3629 md_number_to_chars (buf
, val
, 2);
3631 else if (fixP
->fx_r_type
== BFD_RELOC_32
3632 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3633 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3635 md_number_to_chars (buf
, val
, 4);
3637 else if (fixP
->fx_r_type
== BFD_RELOC_64
3638 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3640 md_number_to_chars (buf
, val
, 8);
3642 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3643 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3650 /* It's a relocation against an instruction. */
3652 if (INSN_BIG_ENDIAN
)
3653 insn
= bfd_getb32 ((unsigned char *) buf
);
3655 insn
= bfd_getl32 ((unsigned char *) buf
);
3657 switch (fixP
->fx_r_type
)
3659 case BFD_RELOC_32_PCREL_S2
:
3661 /* FIXME: This increment-by-one deserves a comment of why it's
3663 if (! sparc_pic_code
3664 || fixP
->fx_addsy
== NULL
3665 || symbol_section_p (fixP
->fx_addsy
))
3668 insn
|= val
& 0x3fffffff;
3670 /* See if we have a delay slot. In that case we attempt to
3671 optimize several cases transforming CALL instructions
3672 into branches. But we can only do that if the relocation
3673 can be completely resolved here, i.e. if no undefined
3674 symbol is associated with it. */
3675 if (sparc_relax
&& fixP
->fx_addsy
== NULL
3676 && fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3680 #define XCC (2 << 20)
3681 #define COND(x) (((x)&0xf)<<25)
3682 #define CONDA COND(0x8)
3683 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3684 #define INSN_BA (F2(0,2) | CONDA)
3685 #define INSN_OR F3(2, 0x2, 0)
3686 #define INSN_NOP F2(0,4)
3690 /* If the instruction is a call with either:
3692 arithmetic instruction with rd == %o7
3693 where rs1 != %o7 and rs2 if it is register != %o7
3694 then we can optimize if the call destination is near
3695 by changing the call into a branch always. */
3696 if (INSN_BIG_ENDIAN
)
3697 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3699 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3700 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3702 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3703 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3704 || ((delay
& RD (~0)) != RD (O7
))))
3706 if ((delay
& RS1 (~0)) == RS1 (O7
)
3707 || ((delay
& F3I (~0)) == 0
3708 && (delay
& RS2 (~0)) == RS2 (O7
)))
3710 /* Ensure the branch will fit into simm22. */
3711 if ((val
& 0x3fe00000)
3712 && (val
& 0x3fe00000) != 0x3fe00000)
3714 /* Check if the arch is v9 and branch will fit
3716 if (((val
& 0x3c0000) == 0
3717 || (val
& 0x3c0000) == 0x3c0000)
3718 && (sparc_arch_size
== 64
3719 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3721 insn
= INSN_BPA
| (val
& 0x7ffff);
3724 insn
= INSN_BA
| (val
& 0x3fffff);
3725 if (fixP
->fx_where
>= 4
3726 && ((delay
& (0xffffffff ^ RS1 (~0)))
3727 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3732 if (INSN_BIG_ENDIAN
)
3733 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3735 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3736 if ((setter
& (0xffffffff ^ RD (~0)))
3737 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3744 If call foo was replaced with ba, replace
3745 or %rN, %g0, %o7 with nop. */
3746 reg
= (delay
& RS1 (~0)) >> 14;
3747 if (reg
!= ((setter
& RD (~0)) >> 25)
3748 || reg
== G0
|| reg
== O7
)
3751 if (INSN_BIG_ENDIAN
)
3752 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3754 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3759 case BFD_RELOC_SPARC_11
:
3760 if (! in_signed_range (val
, 0x7ff))
3761 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3762 _("relocation overflow"));
3763 insn
|= val
& 0x7ff;
3766 case BFD_RELOC_SPARC_10
:
3767 if (! in_signed_range (val
, 0x3ff))
3768 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3769 _("relocation overflow"));
3770 insn
|= val
& 0x3ff;
3773 case BFD_RELOC_SPARC_7
:
3774 if (! in_bitfield_range (val
, 0x7f))
3775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3776 _("relocation overflow"));
3780 case BFD_RELOC_SPARC_6
:
3781 if (! in_bitfield_range (val
, 0x3f))
3782 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3783 _("relocation overflow"));
3787 case BFD_RELOC_SPARC_5
:
3788 if (! in_bitfield_range (val
, 0x1f))
3789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3790 _("relocation overflow"));
3794 case BFD_RELOC_SPARC_WDISP10
:
3797 || val
<= -(offsetT
) 0x808)
3798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3799 _("relocation overflow"));
3800 /* FIXME: The +1 deserves a comment. */
3801 val
= (val
>> 2) + 1;
3802 insn
|= ((val
& 0x300) << 11)
3803 | ((val
& 0xff) << 5);
3806 case BFD_RELOC_SPARC_WDISP16
:
3809 || val
<= -(offsetT
) 0x20008)
3810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3811 _("relocation overflow"));
3812 /* FIXME: The +1 deserves a comment. */
3813 val
= (val
>> 2) + 1;
3814 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3817 case BFD_RELOC_SPARC_WDISP19
:
3820 || val
<= -(offsetT
) 0x100008)
3821 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3822 _("relocation overflow"));
3823 /* FIXME: The +1 deserves a comment. */
3824 val
= (val
>> 2) + 1;
3825 insn
|= val
& 0x7ffff;
3828 case BFD_RELOC_SPARC_HH22
:
3829 val
= BSR (val
, 32);
3832 case BFD_RELOC_SPARC_LM22
:
3833 case BFD_RELOC_HI22
:
3834 if (!fixP
->fx_addsy
)
3835 insn
|= (val
>> 10) & 0x3fffff;
3837 /* FIXME: Need comment explaining why we do this. */
3841 case BFD_RELOC_SPARC22
:
3842 if (val
& ~0x003fffff)
3843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3844 _("relocation overflow"));
3845 insn
|= (val
& 0x3fffff);
3848 case BFD_RELOC_SPARC_HM10
:
3849 val
= BSR (val
, 32);
3852 case BFD_RELOC_LO10
:
3853 if (!fixP
->fx_addsy
)
3854 insn
|= val
& 0x3ff;
3856 /* FIXME: Need comment explaining why we do this. */
3860 case BFD_RELOC_SPARC_OLO10
:
3862 val
+= fixP
->tc_fix_data
;
3865 case BFD_RELOC_SPARC13
:
3866 if (! in_signed_range (val
, 0x1fff))
3867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3868 _("relocation overflow"));
3869 insn
|= val
& 0x1fff;
3872 case BFD_RELOC_SPARC_WDISP22
:
3873 val
= (val
>> 2) + 1;
3875 case BFD_RELOC_SPARC_BASE22
:
3876 insn
|= val
& 0x3fffff;
3879 case BFD_RELOC_SPARC_H34
:
3880 if (!fixP
->fx_addsy
)
3884 insn
|= tval
& 0x3fffff;
3888 case BFD_RELOC_SPARC_H44
:
3889 if (!fixP
->fx_addsy
)
3893 insn
|= tval
& 0x3fffff;
3897 case BFD_RELOC_SPARC_M44
:
3898 if (!fixP
->fx_addsy
)
3899 insn
|= (val
>> 12) & 0x3ff;
3902 case BFD_RELOC_SPARC_L44
:
3903 if (!fixP
->fx_addsy
)
3904 insn
|= val
& 0xfff;
3907 case BFD_RELOC_SPARC_HIX22
:
3908 if (!fixP
->fx_addsy
)
3910 val
^= ~(offsetT
) 0;
3911 insn
|= (val
>> 10) & 0x3fffff;
3915 case BFD_RELOC_SPARC_LOX10
:
3916 if (!fixP
->fx_addsy
)
3917 insn
|= 0x1c00 | (val
& 0x3ff);
3920 case BFD_RELOC_NONE
:
3922 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3923 _("bad or unhandled relocation type: 0x%02x"),
3928 if (INSN_BIG_ENDIAN
)
3929 bfd_putb32 (insn
, (unsigned char *) buf
);
3931 bfd_putl32 (insn
, (unsigned char *) buf
);
3934 /* Are we finished with this relocation now? */
3935 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3939 /* Translate internal representation of relocation info to BFD target
3943 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3945 static arelent
*relocs
[3];
3947 bfd_reloc_code_real_type code
;
3949 relocs
[0] = reloc
= XNEW (arelent
);
3952 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3953 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3954 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3956 switch (fixp
->fx_r_type
)
3964 switch (fixp
->fx_size
)
3967 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3968 _("can not do %d byte pc-relative relocation"),
3970 code
= fixp
->fx_r_type
;
3973 case 1: code
= BFD_RELOC_8_PCREL
; break;
3974 case 2: code
= BFD_RELOC_16_PCREL
; break;
3975 case 4: code
= BFD_RELOC_32_PCREL
; break;
3977 case 8: code
= BFD_RELOC_64_PCREL
; break;
3981 fixp
->fx_addnumber
= fixp
->fx_offset
;
3985 case BFD_RELOC_HI22
:
3986 case BFD_RELOC_LO10
:
3987 case BFD_RELOC_32_PCREL_S2
:
3988 case BFD_RELOC_SPARC13
:
3989 case BFD_RELOC_SPARC22
:
3990 case BFD_RELOC_SPARC_PC22
:
3991 case BFD_RELOC_SPARC_PC10
:
3992 case BFD_RELOC_SPARC_BASE13
:
3993 case BFD_RELOC_SPARC_WDISP10
:
3994 case BFD_RELOC_SPARC_WDISP16
:
3995 case BFD_RELOC_SPARC_WDISP19
:
3996 case BFD_RELOC_SPARC_WDISP22
:
3997 case BFD_RELOC_SPARC_5
:
3998 case BFD_RELOC_SPARC_6
:
3999 case BFD_RELOC_SPARC_7
:
4000 case BFD_RELOC_SPARC_10
:
4001 case BFD_RELOC_SPARC_11
:
4002 case BFD_RELOC_SPARC_HH22
:
4003 case BFD_RELOC_SPARC_HM10
:
4004 case BFD_RELOC_SPARC_LM22
:
4005 case BFD_RELOC_SPARC_PC_HH22
:
4006 case BFD_RELOC_SPARC_PC_HM10
:
4007 case BFD_RELOC_SPARC_PC_LM22
:
4008 case BFD_RELOC_SPARC_H34
:
4009 case BFD_RELOC_SPARC_H44
:
4010 case BFD_RELOC_SPARC_M44
:
4011 case BFD_RELOC_SPARC_L44
:
4012 case BFD_RELOC_SPARC_HIX22
:
4013 case BFD_RELOC_SPARC_LOX10
:
4014 case BFD_RELOC_SPARC_REV32
:
4015 case BFD_RELOC_SPARC_OLO10
:
4016 case BFD_RELOC_SPARC_UA16
:
4017 case BFD_RELOC_SPARC_UA32
:
4018 case BFD_RELOC_SPARC_UA64
:
4019 case BFD_RELOC_8_PCREL
:
4020 case BFD_RELOC_16_PCREL
:
4021 case BFD_RELOC_32_PCREL
:
4022 case BFD_RELOC_64_PCREL
:
4023 case BFD_RELOC_SPARC_PLT32
:
4024 case BFD_RELOC_SPARC_PLT64
:
4025 case BFD_RELOC_VTABLE_ENTRY
:
4026 case BFD_RELOC_VTABLE_INHERIT
:
4027 case BFD_RELOC_SPARC_TLS_GD_HI22
:
4028 case BFD_RELOC_SPARC_TLS_GD_LO10
:
4029 case BFD_RELOC_SPARC_TLS_GD_ADD
:
4030 case BFD_RELOC_SPARC_TLS_GD_CALL
:
4031 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
4032 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
4033 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
4034 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
4035 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
4036 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
4037 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
4038 case BFD_RELOC_SPARC_TLS_IE_HI22
:
4039 case BFD_RELOC_SPARC_TLS_IE_LO10
:
4040 case BFD_RELOC_SPARC_TLS_IE_LD
:
4041 case BFD_RELOC_SPARC_TLS_IE_LDX
:
4042 case BFD_RELOC_SPARC_TLS_IE_ADD
:
4043 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
4044 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
4045 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
4046 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
4047 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
4048 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
4049 case BFD_RELOC_SPARC_GOTDATA_OP
:
4050 code
= fixp
->fx_r_type
;
4057 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
4058 /* If we are generating PIC code, we need to generate a different
4062 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
4064 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
4067 #define GOTT_BASE "__GOTT_BASE__"
4068 #define GOTT_INDEX "__GOTT_INDEX__"
4071 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
4077 case BFD_RELOC_32_PCREL_S2
:
4078 if (generic_force_reloc (fixp
))
4079 code
= BFD_RELOC_SPARC_WPLT30
;
4081 case BFD_RELOC_HI22
:
4082 code
= BFD_RELOC_SPARC_GOT22
;
4083 if (fixp
->fx_addsy
!= NULL
)
4085 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
4086 code
= BFD_RELOC_SPARC_PC22
;
4088 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
4089 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
4090 code
= BFD_RELOC_HI22
; /* Unchanged. */
4094 case BFD_RELOC_LO10
:
4095 code
= BFD_RELOC_SPARC_GOT10
;
4096 if (fixp
->fx_addsy
!= NULL
)
4098 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
4099 code
= BFD_RELOC_SPARC_PC10
;
4101 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
4102 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
4103 code
= BFD_RELOC_LO10
; /* Unchanged. */
4107 case BFD_RELOC_SPARC13
:
4108 code
= BFD_RELOC_SPARC_GOT13
;
4114 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
4116 /* Nothing is aligned in DWARF debugging sections. */
4117 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
4120 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
4121 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
4122 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
4126 if (code
== BFD_RELOC_SPARC_OLO10
)
4127 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
4129 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4130 if (reloc
->howto
== 0)
4132 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4133 _("internal error: can't export reloc type %d (`%s')"),
4134 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
4140 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
4143 if (reloc
->howto
->pc_relative
== 0
4144 || code
== BFD_RELOC_SPARC_PC10
4145 || code
== BFD_RELOC_SPARC_PC22
)
4146 reloc
->addend
= fixp
->fx_addnumber
;
4147 else if (sparc_pic_code
4148 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
4149 && fixp
->fx_addsy
!= NULL
4150 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
4151 || S_IS_WEAK (fixp
->fx_addsy
))
4152 && S_IS_DEFINED (fixp
->fx_addsy
)
4153 && ! S_IS_COMMON (fixp
->fx_addsy
))
4154 reloc
->addend
= fixp
->fx_addnumber
;
4156 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
4158 #else /* elf or coff */
4160 if (code
!= BFD_RELOC_32_PCREL_S2
4161 && code
!= BFD_RELOC_SPARC_WDISP22
4162 && code
!= BFD_RELOC_SPARC_WDISP16
4163 && code
!= BFD_RELOC_SPARC_WDISP19
4164 && code
!= BFD_RELOC_SPARC_WDISP10
4165 && code
!= BFD_RELOC_SPARC_WPLT30
4166 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
4167 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
4168 reloc
->addend
= fixp
->fx_addnumber
;
4169 else if (symbol_section_p (fixp
->fx_addsy
))
4170 reloc
->addend
= (section
->vma
4171 + fixp
->fx_addnumber
4172 + md_pcrel_from (fixp
));
4174 reloc
->addend
= fixp
->fx_offset
;
4177 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4178 on the same location. */
4179 if (code
== BFD_RELOC_SPARC_OLO10
)
4181 relocs
[1] = reloc
= XNEW (arelent
);
4184 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4186 = symbol_get_bfdsym (section_symbol (absolute_section
));
4187 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4188 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4189 reloc
->addend
= fixp
->tc_fix_data
;
4195 /* We have no need to default values of symbols. */
4198 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4203 /* Round up a section size to the appropriate boundary. */
4206 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4209 /* This is not right for ELF; a.out wants it, and COFF will force
4210 the alignment anyways. */
4211 valueT align
= ((valueT
) 1
4212 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
4215 /* Turn alignment value into a mask. */
4217 newsize
= (size
+ align
) & ~align
;
4224 /* Exactly what point is a PC-relative offset relative TO?
4225 On the sparc, they're relative to the address of the offset, plus
4226 its size. This gets us to the following instruction.
4227 (??? Is this right? FIXME-SOON) */
4229 md_pcrel_from (fixS
*fixP
)
4233 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4234 if (! sparc_pic_code
4235 || fixP
->fx_addsy
== NULL
4236 || symbol_section_p (fixP
->fx_addsy
))
4237 ret
+= fixP
->fx_size
;
4241 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4252 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4255 return (value
== 1) ? shift
: -1;
4258 /* Sort of like s_lcomm. */
4261 static int max_alignment
= 15;
4265 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4275 c
= get_symbol_name (&name
);
4276 p
= input_line_pointer
;
4278 SKIP_WHITESPACE_AFTER_NAME ();
4280 if (*input_line_pointer
!= ',')
4282 as_bad (_("Expected comma after name"));
4283 ignore_rest_of_line ();
4287 ++input_line_pointer
;
4289 if ((size
= get_absolute_expression ()) < 0)
4291 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4292 ignore_rest_of_line ();
4297 symbolP
= symbol_find_or_make (name
);
4300 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4301 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4303 as_bad (_("bad .reserve segment -- expected BSS segment"));
4307 if (input_line_pointer
[2] == '.')
4308 input_line_pointer
+= 7;
4310 input_line_pointer
+= 6;
4313 if (*input_line_pointer
== ',')
4315 ++input_line_pointer
;
4318 if (*input_line_pointer
== '\n')
4320 as_bad (_("missing alignment"));
4321 ignore_rest_of_line ();
4325 align
= (int) get_absolute_expression ();
4328 if (align
> max_alignment
)
4330 align
= max_alignment
;
4331 as_warn (_("alignment too large; assuming %d"), align
);
4337 as_bad (_("negative alignment"));
4338 ignore_rest_of_line ();
4344 temp
= mylog2 (align
);
4347 as_bad (_("alignment not a power of 2"));
4348 ignore_rest_of_line ();
4355 record_alignment (bss_section
, align
);
4360 if (!S_IS_DEFINED (symbolP
)
4362 && S_GET_OTHER (symbolP
) == 0
4363 && S_GET_DESC (symbolP
) == 0
4370 segT current_seg
= now_seg
;
4371 subsegT current_subseg
= now_subseg
;
4373 /* Switch to bss. */
4374 subseg_set (bss_section
, 1);
4378 frag_align (align
, 0, 0);
4380 /* Detach from old frag. */
4381 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4382 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4384 symbol_set_frag (symbolP
, frag_now
);
4385 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4386 (offsetT
) size
, (char *) 0);
4389 S_SET_SEGMENT (symbolP
, bss_section
);
4391 subseg_set (current_seg
, current_subseg
);
4394 S_SET_SIZE (symbolP
, size
);
4400 as_warn (_("Ignoring attempt to re-define symbol %s"),
4401 S_GET_NAME (symbolP
));
4404 demand_empty_rest_of_line ();
4408 s_common (int ignore ATTRIBUTE_UNUSED
)
4416 c
= get_symbol_name (&name
);
4417 /* Just after name is now '\0'. */
4418 p
= input_line_pointer
;
4420 SKIP_WHITESPACE_AFTER_NAME ();
4421 if (*input_line_pointer
!= ',')
4423 as_bad (_("Expected comma after symbol-name"));
4424 ignore_rest_of_line ();
4429 input_line_pointer
++;
4431 if ((temp
= get_absolute_expression ()) < 0)
4433 as_bad (_(".COMMon length (%lu) out of range ignored"),
4434 (unsigned long) temp
);
4435 ignore_rest_of_line ();
4440 symbolP
= symbol_find_or_make (name
);
4442 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4444 as_bad (_("Ignoring attempt to re-define symbol"));
4445 ignore_rest_of_line ();
4448 if (S_GET_VALUE (symbolP
) != 0)
4450 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4452 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4453 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4459 S_SET_VALUE (symbolP
, (valueT
) size
);
4460 S_SET_EXTERNAL (symbolP
);
4463 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4464 if (*input_line_pointer
!= ',')
4466 as_bad (_("Expected comma after common length"));
4467 ignore_rest_of_line ();
4470 input_line_pointer
++;
4472 if (*input_line_pointer
!= '"')
4474 temp
= get_absolute_expression ();
4477 if (temp
> max_alignment
)
4479 temp
= max_alignment
;
4480 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4486 as_bad (_("negative alignment"));
4487 ignore_rest_of_line ();
4492 if (symbol_get_obj (symbolP
)->local
)
4499 old_subsec
= now_subseg
;
4504 align
= mylog2 (temp
);
4508 as_bad (_("alignment not a power of 2"));
4509 ignore_rest_of_line ();
4513 record_alignment (bss_section
, align
);
4514 subseg_set (bss_section
, 0);
4516 frag_align (align
, 0, 0);
4517 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4518 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4519 symbol_set_frag (symbolP
, frag_now
);
4520 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4521 (offsetT
) size
, (char *) 0);
4523 S_SET_SEGMENT (symbolP
, bss_section
);
4524 S_CLEAR_EXTERNAL (symbolP
);
4525 S_SET_SIZE (symbolP
, size
);
4526 subseg_set (old_sec
, old_subsec
);
4529 #endif /* OBJ_ELF */
4532 S_SET_VALUE (symbolP
, (valueT
) size
);
4534 S_SET_ALIGN (symbolP
, temp
);
4535 S_SET_SIZE (symbolP
, size
);
4537 S_SET_EXTERNAL (symbolP
);
4538 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4543 input_line_pointer
++;
4544 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4545 if (*input_line_pointer
== '.')
4546 input_line_pointer
++;
4547 /* @@ Some say data, some say bss. */
4548 if (strncmp (input_line_pointer
, "bss\"", 4)
4549 && strncmp (input_line_pointer
, "data\"", 5))
4551 while (*--input_line_pointer
!= '"')
4553 input_line_pointer
--;
4554 goto bad_common_segment
;
4556 while (*input_line_pointer
++ != '"')
4558 goto allocate_common
;
4561 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4563 demand_empty_rest_of_line ();
4568 p
= input_line_pointer
;
4569 while (*p
&& *p
!= '\n')
4573 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4575 input_line_pointer
= p
;
4576 ignore_rest_of_line ();
4581 /* Handle the .empty pseudo-op. This suppresses the warnings about
4582 invalid delay slot usage. */
4585 s_empty (int ignore ATTRIBUTE_UNUSED
)
4587 /* The easy way to implement is to just forget about the last
4593 s_seg (int ignore ATTRIBUTE_UNUSED
)
4596 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4598 input_line_pointer
+= 6;
4602 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4604 input_line_pointer
+= 6;
4608 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4610 input_line_pointer
+= 7;
4614 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4616 input_line_pointer
+= 5;
4617 /* We only support 2 segments -- text and data -- for now, so
4618 things in the "bss segment" will have to go into data for now.
4619 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4620 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4623 as_bad (_("Unknown segment type"));
4624 demand_empty_rest_of_line ();
4630 subseg_set (data_section
, 1);
4631 demand_empty_rest_of_line ();
4635 s_proc (int ignore ATTRIBUTE_UNUSED
)
4637 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4639 ++input_line_pointer
;
4641 ++input_line_pointer
;
4644 /* This static variable is set by s_uacons to tell sparc_cons_align
4645 that the expression does not need to be aligned. */
4647 static int sparc_no_align_cons
= 0;
4649 /* This handles the unaligned space allocation pseudo-ops, such as
4650 .uaword. .uaword is just like .word, but the value does not need
4654 s_uacons (int bytes
)
4656 /* Tell sparc_cons_align not to align this value. */
4657 sparc_no_align_cons
= 1;
4659 sparc_no_align_cons
= 0;
4662 /* This handles the native word allocation pseudo-op .nword.
4663 For sparc_arch_size 32 it is equivalent to .word, for
4664 sparc_arch_size 64 it is equivalent to .xword. */
4667 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4669 cons (sparc_arch_size
== 32 ? 4 : 8);
4673 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4677 .register %g[2367],{#scratch|symbolname|#ignore}
4681 s_register (int ignore ATTRIBUTE_UNUSED
)
4688 if (input_line_pointer
[0] != '%'
4689 || input_line_pointer
[1] != 'g'
4690 || ((input_line_pointer
[2] & ~1) != '2'
4691 && (input_line_pointer
[2] & ~1) != '6')
4692 || input_line_pointer
[3] != ',')
4693 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4694 reg
= input_line_pointer
[2] - '0';
4695 input_line_pointer
+= 4;
4697 if (*input_line_pointer
== '#')
4699 ++input_line_pointer
;
4700 c
= get_symbol_name (®name
);
4701 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4702 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4703 if (regname
[0] == 'i')
4706 regname
= (char *) "";
4710 c
= get_symbol_name (®name
);
4713 if (sparc_arch_size
== 64)
4717 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4718 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4719 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4720 as_bad (_("redefinition of global register"));
4724 if (regname
== NULL
)
4725 globals
[reg
] = (symbolS
*) 1;
4730 if (symbol_find (regname
))
4731 as_bad (_("Register symbol %s already defined."),
4734 globals
[reg
] = symbol_make (regname
);
4735 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4737 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4738 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4739 flags
|= BSF_GLOBAL
;
4740 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4741 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4742 S_SET_ALIGN (globals
[reg
], reg
);
4743 S_SET_SIZE (globals
[reg
], 0);
4744 /* Although we actually want undefined_section here,
4745 we have to use absolute_section, because otherwise
4746 generic as code will make it a COM section.
4747 We fix this up in sparc_adjust_symtab. */
4748 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4749 S_SET_OTHER (globals
[reg
], 0);
4750 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4751 ->internal_elf_sym
.st_info
=
4752 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4753 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4754 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4759 (void) restore_line_pointer (c
);
4761 demand_empty_rest_of_line ();
4764 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4765 symbols which need it. */
4768 sparc_adjust_symtab (void)
4772 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4774 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4775 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4778 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4779 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4782 S_SET_SEGMENT (sym
, undefined_section
);
4787 /* If the --enforce-aligned-data option is used, we require .word,
4788 et. al., to be aligned correctly. We do it by setting up an
4789 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4790 no unexpected alignment was introduced.
4792 The SunOS and Solaris native assemblers enforce aligned data by
4793 default. We don't want to do that, because gcc can deliberately
4794 generate misaligned data if the packed attribute is used. Instead,
4795 we permit misaligned data by default, and permit the user to set an
4796 option to check for it. */
4799 sparc_cons_align (int nbytes
)
4803 /* Only do this if we are enforcing aligned data. */
4804 if (! enforce_aligned_data
)
4807 /* Don't align if this is an unaligned pseudo-op. */
4808 if (sparc_no_align_cons
)
4811 nalign
= mylog2 (nbytes
);
4815 gas_assert (nalign
> 0);
4817 if (now_seg
== absolute_section
)
4819 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4820 as_bad (_("misaligned data"));
4824 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4825 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4827 record_alignment (now_seg
, nalign
);
4830 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4833 sparc_handle_align (fragS
*fragp
)
4838 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4840 switch (fragp
->fr_type
)
4844 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4848 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4859 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4861 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4862 if (INSN_BIG_ENDIAN
)
4863 number_to_chars_bigendian (p
, wval
, 4);
4865 number_to_chars_littleendian (p
, wval
, 4);
4871 if (INSN_BIG_ENDIAN
)
4872 number_to_chars_bigendian (p
, 0x01000000, 4);
4874 number_to_chars_littleendian (p
, 0x01000000, 4);
4876 fragp
->fr_fix
+= fix
;
4886 /* Some special processing for a Sparc ELF file. */
4889 sparc_elf_final_processing (void)
4891 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4892 sort of BFD interface for this. */
4893 if (sparc_arch_size
== 64)
4895 switch (sparc_memory_model
)
4898 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4901 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4907 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4908 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4909 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4910 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4911 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4912 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4916 sparc_cons (expressionS
*exp
, int size
)
4919 const char *sparc_cons_special_reloc
= NULL
;
4922 save
= input_line_pointer
;
4923 if (input_line_pointer
[0] == '%'
4924 && input_line_pointer
[1] == 'r'
4925 && input_line_pointer
[2] == '_')
4927 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4929 input_line_pointer
+= 7;
4930 sparc_cons_special_reloc
= "disp";
4932 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4934 if (size
!= 4 && size
!= 8)
4935 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4938 input_line_pointer
+= 6;
4939 sparc_cons_special_reloc
= "plt";
4942 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4944 if (size
!= 4 && size
!= 8)
4945 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4948 input_line_pointer
+= 13;
4949 sparc_cons_special_reloc
= "tls_dtpoff";
4952 if (sparc_cons_special_reloc
)
4959 if (*input_line_pointer
!= '8')
4961 input_line_pointer
--;
4964 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4968 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4972 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4982 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4983 sparc_cons_special_reloc
, size
* 8, size
);
4987 input_line_pointer
+= 2;
4988 if (*input_line_pointer
!= '(')
4990 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4991 sparc_cons_special_reloc
, size
* 8);
4998 input_line_pointer
= save
;
4999 sparc_cons_special_reloc
= NULL
;
5004 char *end
= ++input_line_pointer
;
5007 while (! is_end_of_line
[(c
= *end
)])
5021 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
5022 sparc_cons_special_reloc
, size
* 8);
5028 if (input_line_pointer
!= end
)
5030 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
5031 sparc_cons_special_reloc
, size
* 8);
5035 input_line_pointer
++;
5037 c
= *input_line_pointer
;
5038 if (! is_end_of_line
[c
] && c
!= ',')
5039 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
5040 sparc_cons_special_reloc
, size
* 8);
5046 if (sparc_cons_special_reloc
== NULL
)
5048 return sparc_cons_special_reloc
;
5053 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5054 reloc for a cons. We could use the definition there, except that
5055 we want to handle little endian relocs specially. */
5058 cons_fix_new_sparc (fragS
*frag
,
5060 unsigned int nbytes
,
5062 const char *sparc_cons_special_reloc
)
5064 bfd_reloc_code_real_type r
;
5066 r
= (nbytes
== 1 ? BFD_RELOC_8
:
5067 (nbytes
== 2 ? BFD_RELOC_16
:
5068 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
5070 if (target_little_endian_data
5072 && now_seg
->flags
& SEC_ALLOC
)
5073 r
= BFD_RELOC_SPARC_REV32
;
5076 /* The Solaris linker does not allow R_SPARC_UA64
5077 relocations for 32-bit executables. */
5078 if (!target_little_endian_data
5079 && sparc_arch_size
!= 64
5080 && r
== BFD_RELOC_64
)
5084 if (sparc_cons_special_reloc
)
5086 if (*sparc_cons_special_reloc
== 'd')
5089 case 1: r
= BFD_RELOC_8_PCREL
; break;
5090 case 2: r
= BFD_RELOC_16_PCREL
; break;
5091 case 4: r
= BFD_RELOC_32_PCREL
; break;
5092 case 8: r
= BFD_RELOC_64_PCREL
; break;
5095 else if (*sparc_cons_special_reloc
== 'p')
5098 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
5099 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
5104 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
5105 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
5108 else if (sparc_no_align_cons
5109 || /* PR 20803 - relocs in the .eh_frame section
5110 need to support unaligned access. */
5111 strcmp (now_seg
->name
, ".eh_frame") == 0)
5115 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
5116 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
5118 /* The Solaris linker does not allow R_SPARC_UA64
5119 relocations for 32-bit executables. */
5120 case 8: r
= sparc_arch_size
== 64 ?
5121 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
5123 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
5129 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
5133 sparc_cfi_frame_initial_instructions (void)
5135 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
5139 sparc_regname_to_dw2regnum (char *regname
)
5149 case 'g': i
= 0; break;
5150 case 'o': i
= 1; break;
5151 case 'l': i
= 2; break;
5152 case 'i': i
= 3; break;
5153 default: i
= -1; break;
5157 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
5159 return i
* 8 + regname
[1] - '0';
5161 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
5163 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
5165 if (regname
[0] == 'f' || regname
[0] == 'r')
5167 unsigned int regnum
;
5169 regnum
= strtoul (regname
+ 1, &q
, 10);
5170 if (q
== NULL
|| *q
)
5172 if (regnum
>= ((regname
[0] == 'f'
5173 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
5176 if (regname
[0] == 'f')
5179 if (regnum
>= 64 && (regnum
& 1))
5188 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
5190 sparc_no_align_cons
= 1;
5191 emit_expr_with_reloc (exp
, nbytes
, "disp");
5192 sparc_no_align_cons
= 0;