1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static const char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static bfd_uint64_t hwcap_seen
;
84 static bfd_uint64_t hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax
;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data
;
106 extern int target_big_endian
;
108 static int target_little_endian_data
;
110 /* Symbols for global registers on v9. */
111 static symbolS
*globals
[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment
;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control
*op_hash
;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons
, 2},
162 {"4byte", s_uacons
, 4},
163 {"8byte", s_uacons
, 8},
164 {"register", s_register
, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars
[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars
[] = "#";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode
;
205 struct nlist
*nlistp
;
209 bfd_reloc_code_real_type reloc
;
212 struct sparc_it the_insn
, set_insn
;
214 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
222 v8plusa
, v9
, v9a
, v9b
, v9_64
};
224 /* Hardware capability sets, used to keep sparc_arch_table easy to
226 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
227 #define HWS_V9 HWS_V8 | HWCAP_POPC
228 #define HWS_VA HWS_V9 | HWCAP_VIS
229 #define HWS_VB HWS_VA | HWCAP_VIS2
230 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
231 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
232 #define HWS_VE HWS_VD \
233 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
234 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
235 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
236 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
237 #define HWS_VM HWS_VV
240 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
241 | HWCAP2_XMPMUL | HWCAP2_XMONT
243 static struct sparc_arch
{
245 const char *opcode_arch
;
246 enum sparc_arch_types arch_type
;
247 /* Default word size, as specified during configuration.
248 A value of zero means can't be used to specify default architecture. */
249 int default_arch_size
;
250 /* Allowable arg to -A? */
254 } sparc_arch_table
[] = {
255 { "v6", "v6", v6
, 0, 1, 0, 0 },
256 { "v7", "v7", v7
, 0, 1, 0, 0 },
257 { "v8", "v8", v8
, 32, 1, HWS_V8
, 0 },
258 { "v8a", "v8", v8
, 32, 1, HWS_V8
, 0 },
259 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
260 { "sparcvis", "v9a", v9
, 0, 1, HWS_VA
, 0 },
261 { "sparcvis2", "v9b", v9
, 0, 1, HWS_VB
, 0 },
262 { "sparcfmaf", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
, 0 },
263 { "sparcima", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_IMA
, 0 },
264 { "sparcvis3", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
265 { "sparcvis3r", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
267 { "sparc4", "v9v", v9
, 0, 1, HWS_VV
, 0 },
268 { "sparc5", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
270 { "leon", "leon", leon
, 32, 1, HWS_V8
, 0 },
271 { "sparclet", "sparclet", sparclet
, 32, 1, HWS_V8
, 0 },
272 { "sparclite", "sparclite", sparclite
, 32, 1, HWS_V8
, 0 },
273 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWS_V8
, 0 },
275 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
276 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VA
, 0 },
277 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VB
, 0 },
278 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VC
, 0 },
279 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VD
, 0 },
280 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VE
, 0 },
281 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VV
, 0 },
282 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VM
, 0 },
284 { "v9", "v9", v9
, 0, 1, HWS_V9
, 0 },
285 { "v9a", "v9a", v9
, 0, 1, HWS_VA
, 0 },
286 { "v9b", "v9b", v9
, 0, 1, HWS_VB
, 0 },
287 { "v9c", "v9c", v9
, 0, 1, HWS_VC
, 0 },
288 { "v9d", "v9d", v9
, 0, 1, HWS_VD
, 0 },
289 { "v9e", "v9e", v9
, 0, 1, HWS_VE
, 0 },
290 { "v9v", "v9v", v9
, 0, 1, HWS_VV
, 0 },
291 { "v9m", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
293 /* This exists to allow configure.tgt to pass one
294 value to specify both the default machine and default word size. */
295 { "v9-64", "v9", v9
, 64, 0, HWS_V9
, 0 },
296 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
299 /* Variant of default_arch */
300 static enum sparc_arch_types default_arch_type
;
302 static struct sparc_arch
*
303 lookup_arch (const char *name
)
305 struct sparc_arch
*sa
;
307 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
308 if (strcmp (sa
->name
, name
) == 0)
310 if (sa
->name
== NULL
)
315 /* Initialize the default opcode arch and word size from the default
316 architecture name. */
319 init_default_arch (void)
321 struct sparc_arch
*sa
= lookup_arch (default_arch
);
324 || sa
->default_arch_size
== 0)
325 as_fatal (_("Invalid default architecture, broken assembler."));
327 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
328 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
329 as_fatal (_("Bad opcode table, broken assembler."));
330 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
332 default_arch_type
= sa
->arch_type
;
335 /* Called by TARGET_FORMAT. */
338 sparc_target_format (void)
340 /* We don't get a chance to initialize anything before we're called,
341 so handle that now. */
342 if (! default_init_p
)
343 init_default_arch ();
347 return "a.out-sparc-netbsd";
350 if (target_big_endian
)
351 return "a.out-sunos-big";
352 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
353 return "a.out-sunos-big";
355 return "a.out-sparc-little";
357 return "a.out-sunos-big";
368 return "coff-sparc-lynx";
375 return "elf32-sparc-vxworks";
379 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
386 * Invocation line includes a switch not recognized by the base assembler.
387 * See if it's a processor-specific option. These are:
390 * Warn on architecture bumps. See also -A.
392 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
393 * Standard 32 bit architectures.
395 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
396 * This used to only mean 64 bits, but properly specifying it
397 * complicated gcc's ASM_SPECs, so now opcode selection is
398 * specified orthogonally to word size (except when specifying
399 * the default, but that is an internal implementation detail).
400 * -Av8plus, -Av8plusa, -Av8plusb
401 * Same as -Av9{,a,b}.
402 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
403 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
405 * -xarch=v9, -xarch=v9a, -xarch=v9b
406 * Same as -Av9{,a,b} -64, for compatibility with Sun's
409 * Select the architecture and possibly the file format.
410 * Instructions or features not supported by the selected
411 * architecture cause fatal errors.
413 * The default is to start at v6, and bump the architecture up
414 * whenever an instruction is seen at a higher level. In 32 bit
415 * environments, v9 is not bumped up to, the user must pass
418 * If -bump is specified, a warning is printing when bumping to
421 * If an architecture is specified, all instructions must match
422 * that architecture. Any higher level instructions are flagged
423 * as errors. Note that in the 32 bit environment specifying
424 * -Av8plus does not automatically create a v8plus object file, a
425 * v9 insn must be seen.
427 * If both an architecture and -bump are specified, the
428 * architecture starts at the specified level, but bumps are
429 * warnings. Note that we can't set `current_architecture' to
430 * the requested level in this case: in the 32 bit environment,
431 * we still must avoid creating v8plus object files unless v9
435 * Bumping between incompatible architectures is always an
436 * error. For example, from sparclite to v9.
440 const char *md_shortopts
= "A:K:VQ:sq";
443 const char *md_shortopts
= "A:k";
445 const char *md_shortopts
= "A:";
448 struct option md_longopts
[] = {
449 #define OPTION_BUMP (OPTION_MD_BASE)
450 {"bump", no_argument
, NULL
, OPTION_BUMP
},
451 #define OPTION_SPARC (OPTION_MD_BASE + 1)
452 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
453 #define OPTION_XARCH (OPTION_MD_BASE + 2)
454 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
456 #define OPTION_32 (OPTION_MD_BASE + 3)
457 {"32", no_argument
, NULL
, OPTION_32
},
458 #define OPTION_64 (OPTION_MD_BASE + 4)
459 {"64", no_argument
, NULL
, OPTION_64
},
460 #define OPTION_TSO (OPTION_MD_BASE + 5)
461 {"TSO", no_argument
, NULL
, OPTION_TSO
},
462 #define OPTION_PSO (OPTION_MD_BASE + 6)
463 {"PSO", no_argument
, NULL
, OPTION_PSO
},
464 #define OPTION_RMO (OPTION_MD_BASE + 7)
465 {"RMO", no_argument
, NULL
, OPTION_RMO
},
467 #ifdef SPARC_BIENDIAN
468 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
469 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
470 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
471 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
473 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
474 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
475 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
476 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
478 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
479 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
480 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
481 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
483 #define OPTION_RELAX (OPTION_MD_BASE + 14)
484 {"relax", no_argument
, NULL
, OPTION_RELAX
},
485 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
486 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
487 {NULL
, no_argument
, NULL
, 0}
490 size_t md_longopts_size
= sizeof (md_longopts
);
493 md_parse_option (int c
, const char *arg
)
495 /* We don't get a chance to initialize anything before we're called,
496 so handle that now. */
497 if (! default_init_p
)
498 init_default_arch ();
504 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
509 if (!strncmp (arg
, "v9", 2))
510 md_parse_option (OPTION_64
, NULL
);
513 if (!strncmp (arg
, "v8", 2)
514 || !strncmp (arg
, "v7", 2)
515 || !strncmp (arg
, "v6", 2)
516 || !strcmp (arg
, "sparclet")
517 || !strcmp (arg
, "sparclite")
518 || !strcmp (arg
, "sparc86x"))
519 md_parse_option (OPTION_32
, NULL
);
526 struct sparc_arch
*sa
;
527 enum sparc_opcode_arch_val opcode_arch
;
529 sa
= lookup_arch (arg
);
531 || ! sa
->user_option_p
)
533 if (c
== OPTION_XARCH
)
534 as_bad (_("invalid architecture -xarch=%s"), arg
);
536 as_bad (_("invalid architecture -A%s"), arg
);
540 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
541 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
542 as_fatal (_("Bad opcode table, broken assembler."));
544 if (!architecture_requested
545 || opcode_arch
> max_architecture
)
546 max_architecture
= opcode_arch
;
548 |= (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32) | sa
->hwcap_allowed
;
549 architecture_requested
= 1;
554 /* Ignore -sparc, used by SunOS make default .s.o rule. */
557 case OPTION_ENFORCE_ALIGNED_DATA
:
558 enforce_aligned_data
= 1;
561 #ifdef SPARC_BIENDIAN
562 case OPTION_LITTLE_ENDIAN
:
563 target_big_endian
= 0;
564 if (default_arch_type
!= sparclet
)
565 as_fatal ("This target does not support -EL");
567 case OPTION_LITTLE_ENDIAN_DATA
:
568 target_little_endian_data
= 1;
569 target_big_endian
= 0;
570 if (default_arch_type
!= sparc86x
571 && default_arch_type
!= v9
)
572 as_fatal ("This target does not support --little-endian-data");
574 case OPTION_BIG_ENDIAN
:
575 target_big_endian
= 1;
589 const char **list
, **l
;
591 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
592 list
= bfd_target_list ();
593 for (l
= list
; *l
!= NULL
; l
++)
595 if (sparc_arch_size
== 32)
597 if (CONST_STRNEQ (*l
, "elf32-sparc"))
602 if (CONST_STRNEQ (*l
, "elf64-sparc"))
607 as_fatal (_("No compiled in support for %d bit object file format"),
611 if (sparc_arch_size
== 64
612 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
613 max_architecture
= SPARC_OPCODE_ARCH_V9
;
618 sparc_memory_model
= MM_TSO
;
622 sparc_memory_model
= MM_PSO
;
626 sparc_memory_model
= MM_RMO
;
634 /* Qy - do emit .comment
635 Qn - do not emit .comment. */
639 /* Use .stab instead of .stab.excl. */
643 /* quick -- Native assembler does fewer checks. */
647 if (strcmp (arg
, "PIC") != 0)
648 as_warn (_("Unrecognized option following -K"));
653 case OPTION_NO_UNDECLARED_REGS
:
654 no_undeclared_regs
= 1;
657 case OPTION_UNDECLARED_REGS
:
658 no_undeclared_regs
= 0;
666 case OPTION_NO_RELAX
:
678 md_show_usage (FILE *stream
)
680 const struct sparc_arch
*arch
;
683 /* We don't get a chance to initialize anything before we're called,
684 so handle that now. */
685 if (! default_init_p
)
686 init_default_arch ();
688 fprintf (stream
, _("SPARC options:\n"));
690 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
692 if (!arch
->user_option_p
)
694 if (arch
!= &sparc_arch_table
[0])
695 fprintf (stream
, " | ");
696 if (column
+ strlen (arch
->name
) > 70)
699 fputc ('\n', stream
);
701 column
+= 5 + 2 + strlen (arch
->name
);
702 fprintf (stream
, "-A%s", arch
->name
);
704 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
706 if (!arch
->user_option_p
)
708 fprintf (stream
, " | ");
709 if (column
+ strlen (arch
->name
) > 65)
712 fputc ('\n', stream
);
714 column
+= 5 + 7 + strlen (arch
->name
);
715 fprintf (stream
, "-xarch=%s", arch
->name
);
717 fprintf (stream
, _("\n\
718 specify variant of SPARC architecture\n\
719 -bump warn when assembler switches architectures\n\
721 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
722 -relax relax jumps and branches (default)\n\
723 -no-relax avoid changing any jumps and branches\n"));
725 fprintf (stream
, _("\
726 -k generate PIC\n"));
729 fprintf (stream
, _("\
730 -32 create 32 bit object file\n\
731 -64 create 64 bit object file\n"));
732 fprintf (stream
, _("\
733 [default is %d]\n"), default_arch_size
);
734 fprintf (stream
, _("\
735 -TSO use Total Store Ordering\n\
736 -PSO use Partial Store Ordering\n\
737 -RMO use Relaxed Memory Ordering\n"));
738 fprintf (stream
, _("\
739 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
740 fprintf (stream
, _("\
741 -KPIC generate PIC\n\
742 -V print assembler version number\n\
743 -undeclared-regs ignore application global register usage without\n\
744 appropriate .register directive (default)\n\
745 -no-undeclared-regs force error on application global register usage\n\
746 without appropriate .register directive\n\
751 #ifdef SPARC_BIENDIAN
752 fprintf (stream
, _("\
753 -EL generate code for a little endian machine\n\
754 -EB generate code for a big endian machine\n\
755 --little-endian-data generate code for a machine having big endian\n\
756 instructions and little endian data.\n"));
760 /* Native operand size opcode translation. */
766 } native_op_table
[] =
768 {"ldn", "ld", "ldx"},
769 {"ldna", "lda", "ldxa"},
770 {"stn", "st", "stx"},
771 {"stna", "sta", "stxa"},
772 {"slln", "sll", "sllx"},
773 {"srln", "srl", "srlx"},
774 {"sran", "sra", "srax"},
775 {"casn", "cas", "casx"},
776 {"casna", "casa", "casxa"},
777 {"clrn", "clr", "clrx"},
781 /* sparc64 privileged and hyperprivileged registers. */
783 struct priv_reg_entry
789 struct priv_reg_entry priv_reg_table
[] =
810 {NULL
, -1}, /* End marker. */
813 struct priv_reg_entry hpriv_reg_table
[] =
820 {"hstick_offset", 28},
821 {"hstick_enable", 29},
823 {NULL
, -1}, /* End marker. */
826 /* v9a or later specific ancillary state registers. */
828 struct priv_reg_entry v9a_asr_table
[] =
831 {"sys_tick_cmpr", 25},
835 {"softint_clear", 21},
846 {"clear_softint", 21},
847 {NULL
, -1}, /* End marker. */
851 cmp_reg_entry (const void *parg
, const void *qarg
)
853 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
854 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
856 if (p
->name
== q
->name
)
858 else if (p
->name
== NULL
)
860 else if (q
->name
== NULL
)
863 return strcmp (q
->name
, p
->name
);
866 /* sparc %-pseudo-operations. */
869 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
870 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
872 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
873 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
875 instruction. (Generally they can appear
876 anywhere an immediate operand is
880 /* The name as it appears in assembler. */
882 /* The reloc this pseudo-op translates to. */
884 /* Flags. See F_POP_* above. */
888 struct pop_entry pop_table
[] =
890 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
891 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
892 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
893 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
894 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
895 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
896 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
897 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
898 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
899 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
900 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
901 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
902 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
903 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
904 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
905 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
906 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
907 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
908 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
909 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
910 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
911 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
912 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
913 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
914 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
915 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
916 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
917 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
918 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
919 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
920 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
921 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
922 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
923 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
924 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
925 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
926 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
},
930 /* Table of %-names that can appear in a sparc assembly program. This
931 table is initialized in md_begin and contains entries for each
932 privileged/hyperprivileged/alternate register and %-pseudo-op. */
945 enum perc_entry_type type
;
946 /* Name of the %-entity. */
950 /* Value. Either a pop or a reg depending on type.*/
953 struct pop_entry
*pop
;
954 struct priv_reg_entry
*reg
;
958 #define NUM_PERC_ENTRIES \
959 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
960 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
961 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
962 + ((sizeof (pop_table) / sizeof (pop_table[0])) - 1) \
965 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
968 cmp_perc_entry (const void *parg
, const void *qarg
)
970 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
971 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
973 if (p
->name
== q
->name
)
975 else if (p
->name
== NULL
)
977 else if (q
->name
== NULL
)
980 return strcmp (q
->name
, p
->name
);
983 /* This function is called once, at assembler startup time. It should
984 set up all the tables, etc. that the MD part of the assembler will
990 const char *retval
= NULL
;
994 /* We don't get a chance to initialize anything before md_parse_option
995 is called, and it may not be called, so handle default initialization
996 now if not already done. */
997 if (! default_init_p
)
998 init_default_arch ();
1000 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
1001 op_hash
= hash_new ();
1003 while (i
< (unsigned int) sparc_num_opcodes
)
1005 const char *name
= sparc_opcodes
[i
].name
;
1006 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
1009 as_bad (_("Internal error: can't hash `%s': %s\n"),
1010 sparc_opcodes
[i
].name
, retval
);
1015 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
1017 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1018 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
1023 while (i
< (unsigned int) sparc_num_opcodes
1024 && !strcmp (sparc_opcodes
[i
].name
, name
));
1027 for (i
= 0; native_op_table
[i
].name
; i
++)
1029 const struct sparc_opcode
*insn
;
1030 const char *name
= ((sparc_arch_size
== 32)
1031 ? native_op_table
[i
].name32
1032 : native_op_table
[i
].name64
);
1033 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
1036 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1037 name
, native_op_table
[i
].name
);
1042 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1046 as_bad (_("Internal error: can't hash `%s': %s\n"),
1047 sparc_opcodes
[i
].name
, retval
);
1054 as_fatal (_("Broken assembler. No assembly attempted."));
1056 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1057 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1058 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1059 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1060 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1061 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1063 /* If -bump, record the architecture level at which we start issuing
1064 warnings. The behaviour is different depending upon whether an
1065 architecture was explicitly specified. If it wasn't, we issue warnings
1066 for all upwards bumps. If it was, we don't start issuing warnings until
1067 we need to bump beyond the requested architecture or when we bump between
1068 conflicting architectures. */
1071 && architecture_requested
)
1073 /* `max_architecture' records the requested architecture.
1074 Issue warnings if we go above it. */
1075 warn_after_architecture
= max_architecture
;
1078 /* Find the highest architecture level that doesn't conflict with
1079 the requested one. */
1082 || !architecture_requested
)
1084 enum sparc_opcode_arch_val current_max_architecture
1087 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1088 max_architecture
> warn_after_architecture
;
1090 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1091 current_max_architecture
))
1095 /* Prepare the tables of %-pseudo-ops. */
1097 struct priv_reg_entry
*reg_tables
[]
1098 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1099 struct priv_reg_entry
**reg_table
;
1102 /* Add registers. */
1103 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1105 struct priv_reg_entry
*reg
;
1106 for (reg
= *reg_table
; reg
->name
; reg
++)
1108 struct perc_entry
*p
= &perc_table
[entry
++];
1109 p
->type
= perc_entry_reg
;
1110 p
->name
= reg
->name
;
1111 p
->len
= strlen (reg
->name
);
1116 /* Add %-pseudo-ops. */
1118 struct pop_entry
*pop
;
1120 for (pop
= pop_table
; pop
->name
; pop
++)
1122 struct perc_entry
*p
= &perc_table
[entry
++];
1123 p
->type
= (pop
->flags
& F_POP_POSTFIX
1124 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1125 p
->name
= pop
->name
;
1126 p
->len
= strlen (pop
->name
);
1131 /* Last entry is the centinel. */
1132 perc_table
[entry
].type
= perc_entry_none
;
1134 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1135 sizeof (perc_table
[0]), cmp_perc_entry
);
1140 /* Called after all assembly has been done. */
1145 unsigned long mach
= bfd_mach_sparc
;
1146 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1147 int hwcaps
, hwcaps2
;
1150 if (sparc_arch_size
== 64)
1151 switch (current_architecture
)
1153 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1154 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1155 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1156 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1157 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1158 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1159 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1160 default: mach
= bfd_mach_sparc_v9
; break;
1163 switch (current_architecture
)
1165 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1166 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1167 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1168 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1169 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1170 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1171 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1172 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1173 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1174 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1175 be but for now it is (since that's the way it's always been
1179 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1181 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1182 hwcaps
= hwcap_seen
& U0xffffffff
;
1183 hwcaps2
= hwcap_seen
>> 32;
1186 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1188 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1192 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1195 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1199 /* Sign-extend the value from the architecture word size, so that
1200 0xffffffff is always considered -1 on sparc32. */
1201 if (sparc_arch_size
== 32)
1203 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1204 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1213 /* Return non-zero if VAL is in the range 0 to MAX. */
1216 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1223 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1224 (e.g. -15 to +31). */
1227 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1233 if (val
< ~(max
>> 1))
1239 sparc_ffs (unsigned int mask
)
1246 for (i
= 0; (mask
& 1) == 0; ++i
)
1251 /* Implement big shift right. */
1253 BSR (bfd_vma val
, int amount
)
1255 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1256 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1257 return val
>> amount
;
1260 /* For communication between sparc_ip and get_expression. */
1261 static char *expr_end
;
1263 /* Values for `special_case'.
1264 Instructions that require wierd handling because they're longer than
1266 #define SPECIAL_CASE_NONE 0
1267 #define SPECIAL_CASE_SET 1
1268 #define SPECIAL_CASE_SETSW 2
1269 #define SPECIAL_CASE_SETX 3
1270 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1271 #define SPECIAL_CASE_FDIV 4
1273 /* Bit masks of various insns. */
1274 #define NOP_INSN 0x01000000
1275 #define OR_INSN 0x80100000
1276 #define XOR_INSN 0x80180000
1277 #define FMOVS_INSN 0x81A00020
1278 #define SETHI_INSN 0x01000000
1279 #define SLLX_INSN 0x81281000
1280 #define SRA_INSN 0x81380000
1282 /* The last instruction to be assembled. */
1283 static const struct sparc_opcode
*last_insn
;
1284 /* The assembled opcode of `last_insn'. */
1285 static unsigned long last_opcode
;
1287 /* Handle the set and setuw synthetic instructions. */
1290 synthetize_setuw (const struct sparc_opcode
*insn
)
1292 int need_hi22_p
= 0;
1293 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1295 if (the_insn
.exp
.X_op
== O_constant
)
1297 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1299 if (sizeof (offsetT
) > 4
1300 && (the_insn
.exp
.X_add_number
< 0
1301 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1302 as_warn (_("set: number not in 0..4294967295 range"));
1306 if (sizeof (offsetT
) > 4
1307 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1308 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1309 as_warn (_("set: number not in -2147483648..4294967295 range"));
1310 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1314 /* See if operand is absolute and small; skip sethi if so. */
1315 if (the_insn
.exp
.X_op
!= O_constant
1316 || the_insn
.exp
.X_add_number
>= (1 << 12)
1317 || the_insn
.exp
.X_add_number
< -(1 << 12))
1319 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1320 | ((the_insn
.exp
.X_add_number
>> 10)
1321 & (the_insn
.exp
.X_op
== O_constant
1323 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1324 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1325 output_insn (insn
, &the_insn
);
1329 /* See if operand has no low-order bits; skip OR if so. */
1330 if (the_insn
.exp
.X_op
!= O_constant
1331 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1334 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1336 | (the_insn
.exp
.X_add_number
1337 & (the_insn
.exp
.X_op
!= O_constant
1338 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1339 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1340 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1341 output_insn (insn
, &the_insn
);
1345 /* Handle the setsw synthetic instruction. */
1348 synthetize_setsw (const struct sparc_opcode
*insn
)
1352 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1354 if (the_insn
.exp
.X_op
!= O_constant
)
1356 synthetize_setuw (insn
);
1358 /* Need to sign extend it. */
1359 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1360 the_insn
.reloc
= BFD_RELOC_NONE
;
1361 output_insn (insn
, &the_insn
);
1365 if (sizeof (offsetT
) > 4
1366 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1367 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1368 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1370 low32
= the_insn
.exp
.X_add_number
;
1374 synthetize_setuw (insn
);
1380 the_insn
.reloc
= BFD_RELOC_NONE
;
1381 /* See if operand is absolute and small; skip sethi if so. */
1382 if (low32
< -(1 << 12))
1384 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1385 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1386 output_insn (insn
, &the_insn
);
1387 low32
= 0x1c00 | (low32
& 0x3ff);
1388 opc
= RS1 (rd
) | XOR_INSN
;
1391 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1392 | (low32
& 0x1fff));
1393 output_insn (insn
, &the_insn
);
1396 /* Handle the setx synthetic instruction. */
1399 synthetize_setx (const struct sparc_opcode
*insn
)
1401 int upper32
, lower32
;
1402 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1403 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1405 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1406 int need_xor10_p
= 0;
1408 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1409 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1410 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1413 upper_dstreg
= tmpreg
;
1414 /* The tmp reg should not be the dst reg. */
1415 if (tmpreg
== dstreg
)
1416 as_warn (_("setx: temporary register same as destination register"));
1418 /* ??? Obviously there are other optimizations we can do
1419 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1420 doing some of these. Later. If you do change things, try to
1421 change all of this to be table driven as well. */
1422 /* What to output depends on the number if it's constant.
1423 Compute that first, then output what we've decided upon. */
1424 if (the_insn
.exp
.X_op
!= O_constant
)
1426 if (sparc_arch_size
== 32)
1428 /* When arch size is 32, we want setx to be equivalent
1429 to setuw for anything but constants. */
1430 the_insn
.exp
.X_add_number
&= 0xffffffff;
1431 synthetize_setuw (insn
);
1434 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1440 /* Reset X_add_number, we've extracted it as upper32/lower32.
1441 Otherwise fixup_segment will complain about not being able to
1442 write an 8 byte number in a 4 byte field. */
1443 the_insn
.exp
.X_add_number
= 0;
1445 /* Only need hh22 if `or' insn can't handle constant. */
1446 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1449 /* Does bottom part (after sethi) have bits? */
1450 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1451 /* No hh22, but does upper32 still have bits we can't set
1453 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1456 /* If the lower half is all zero, we build the upper half directly
1457 into the dst reg. */
1459 /* Need lower half if number is zero or 0xffffffff00000000. */
1460 || (! need_hh22_p
&& ! need_hm10_p
))
1462 /* No need for sethi if `or' insn can handle constant. */
1463 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1464 /* Note that we can't use a negative constant in the `or'
1465 insn unless the upper 32 bits are all ones. */
1466 || (lower32
< 0 && upper32
!= -1)
1467 || (lower32
>= 0 && upper32
== -1))
1470 if (need_hi22_p
&& upper32
== -1)
1473 /* Does bottom part (after sethi) have bits? */
1474 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1476 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1477 /* Need `or' if we didn't set anything else. */
1478 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1482 /* Output directly to dst reg if lower 32 bits are all zero. */
1483 upper_dstreg
= dstreg
;
1486 if (!upper_dstreg
&& dstreg
)
1487 as_warn (_("setx: illegal temporary register g0"));
1491 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1492 | ((upper32
>> 10) & 0x3fffff));
1493 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1494 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1495 output_insn (insn
, &the_insn
);
1500 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1501 | (((need_xor10_p
? ~lower32
: lower32
)
1502 >> 10) & 0x3fffff));
1503 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1504 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1505 output_insn (insn
, &the_insn
);
1510 the_insn
.opcode
= (OR_INSN
1511 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1514 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1515 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1516 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1517 output_insn (insn
, &the_insn
);
1522 /* FIXME: One nice optimization to do here is to OR the low part
1523 with the highpart if hi22 isn't needed and the low part is
1525 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1528 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1529 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1530 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1531 output_insn (insn
, &the_insn
);
1534 /* If we needed to build the upper part, shift it into place. */
1535 if (need_hh22_p
|| need_hm10_p
)
1537 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1539 the_insn
.reloc
= BFD_RELOC_NONE
;
1540 output_insn (insn
, &the_insn
);
1543 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1546 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1547 | 0x1c00 | (lower32
& 0x3ff));
1548 the_insn
.reloc
= BFD_RELOC_NONE
;
1549 output_insn (insn
, &the_insn
);
1552 /* If we needed to build both upper and lower parts, OR them together. */
1553 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1555 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1557 the_insn
.reloc
= BFD_RELOC_NONE
;
1558 output_insn (insn
, &the_insn
);
1562 /* Main entry point to assemble one instruction. */
1565 md_assemble (char *str
)
1567 const struct sparc_opcode
*insn
;
1571 special_case
= sparc_ip (str
, &insn
);
1575 /* We warn about attempts to put a floating point branch in a delay slot,
1576 unless the delay slot has been annulled. */
1577 if (last_insn
!= NULL
1578 && (insn
->flags
& F_FBR
) != 0
1579 && (last_insn
->flags
& F_DELAYED
) != 0
1580 /* ??? This test isn't completely accurate. We assume anything with
1581 F_{UNBR,CONDBR,FBR} set is annullable. */
1582 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1583 || (last_opcode
& ANNUL
) == 0))
1584 as_warn (_("FP branch in delay slot"));
1586 /* SPARC before v9 requires a nop instruction between a floating
1587 point instruction and a floating point branch. We insert one
1588 automatically, with a warning. */
1589 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1590 && last_insn
!= NULL
1591 && (insn
->flags
& F_FBR
) != 0
1592 && (last_insn
->flags
& F_FLOAT
) != 0)
1594 struct sparc_it nop_insn
;
1596 nop_insn
.opcode
= NOP_INSN
;
1597 nop_insn
.reloc
= BFD_RELOC_NONE
;
1598 output_insn (insn
, &nop_insn
);
1599 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1602 switch (special_case
)
1604 case SPECIAL_CASE_NONE
:
1606 output_insn (insn
, &the_insn
);
1609 case SPECIAL_CASE_SETSW
:
1610 synthetize_setsw (insn
);
1613 case SPECIAL_CASE_SET
:
1614 synthetize_setuw (insn
);
1617 case SPECIAL_CASE_SETX
:
1618 synthetize_setx (insn
);
1621 case SPECIAL_CASE_FDIV
:
1623 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1625 output_insn (insn
, &the_insn
);
1627 /* According to information leaked from Sun, the "fdiv" instructions
1628 on early SPARC machines would produce incorrect results sometimes.
1629 The workaround is to add an fmovs of the destination register to
1630 itself just after the instruction. This was true on machines
1631 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1632 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1633 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1634 output_insn (insn
, &the_insn
);
1639 as_fatal (_("failed special case insn sanity check"));
1644 get_hwcap_name (bfd_uint64_t mask
)
1646 if (mask
& HWCAP_MUL32
)
1648 if (mask
& HWCAP_DIV32
)
1650 if (mask
& HWCAP_FSMULD
)
1652 if (mask
& HWCAP_V8PLUS
)
1654 if (mask
& HWCAP_POPC
)
1656 if (mask
& HWCAP_VIS
)
1658 if (mask
& HWCAP_VIS2
)
1660 if (mask
& HWCAP_ASI_BLK_INIT
)
1661 return "ASIBlkInit";
1662 if (mask
& HWCAP_FMAF
)
1664 if (mask
& HWCAP_VIS3
)
1666 if (mask
& HWCAP_HPC
)
1668 if (mask
& HWCAP_RANDOM
)
1670 if (mask
& HWCAP_TRANS
)
1672 if (mask
& HWCAP_FJFMAU
)
1674 if (mask
& HWCAP_IMA
)
1676 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1678 if (mask
& HWCAP_AES
)
1680 if (mask
& HWCAP_DES
)
1682 if (mask
& HWCAP_KASUMI
)
1684 if (mask
& HWCAP_CAMELLIA
)
1686 if (mask
& HWCAP_MD5
)
1688 if (mask
& HWCAP_SHA1
)
1690 if (mask
& HWCAP_SHA256
)
1692 if (mask
& HWCAP_SHA512
)
1694 if (mask
& HWCAP_MPMUL
)
1696 if (mask
& HWCAP_MONT
)
1698 if (mask
& HWCAP_PAUSE
)
1700 if (mask
& HWCAP_CBCOND
)
1702 if (mask
& HWCAP_CRC32C
)
1706 if (mask
& HWCAP2_FJATHPLUS
)
1708 if (mask
& HWCAP2_VIS3B
)
1710 if (mask
& HWCAP2_ADP
)
1712 if (mask
& HWCAP2_SPARC5
)
1714 if (mask
& HWCAP2_MWAIT
)
1716 if (mask
& HWCAP2_XMPMUL
)
1718 if (mask
& HWCAP2_XMONT
)
1720 if (mask
& HWCAP2_NSEC
)
1726 /* Subroutine of md_assemble to do the actual parsing. */
1729 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1731 const char *error_message
= "";
1735 const struct sparc_opcode
*insn
;
1737 unsigned long opcode
;
1738 unsigned int mask
= 0;
1742 int special_case
= SPECIAL_CASE_NONE
;
1749 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1766 as_bad (_("Unknown opcode: `%s'"), str
);
1768 return special_case
;
1770 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1774 as_bad (_("Unknown opcode: `%s'"), str
);
1775 return special_case
;
1785 opcode
= insn
->match
;
1786 memset (&the_insn
, '\0', sizeof (the_insn
));
1787 the_insn
.reloc
= BFD_RELOC_NONE
;
1790 /* Build the opcode, checking as we go to make sure that the
1792 for (args
= insn
->args
;; ++args
)
1800 /* Parse a series of masks. */
1807 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1810 error_message
= _(": invalid membar mask name");
1816 if (*s
== '|' || *s
== '+')
1824 if (! parse_const_expr_arg (&s
, &kmask
))
1826 error_message
= _(": invalid membar mask expression");
1829 if (kmask
< 0 || kmask
> 127)
1831 error_message
= _(": invalid membar mask number");
1836 opcode
|= MEMBAR (kmask
);
1844 if (! parse_const_expr_arg (&s
, &smask
))
1846 error_message
= _(": invalid siam mode expression");
1849 if (smask
< 0 || smask
> 7)
1851 error_message
= _(": invalid siam mode number");
1862 /* Parse a prefetch function. */
1865 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1867 error_message
= _(": invalid prefetch function name");
1873 if (! parse_const_expr_arg (&s
, &fcn
))
1875 error_message
= _(": invalid prefetch function expression");
1878 if (fcn
< 0 || fcn
> 31)
1880 error_message
= _(": invalid prefetch function number");
1890 /* Parse a sparc64 privileged register. */
1893 struct priv_reg_entry
*p
;
1894 unsigned int len
= 9999999; /* Init to make gcc happy. */
1897 for (p
= priv_reg_table
; p
->name
; p
++)
1898 if (p
->name
[0] == s
[0])
1900 len
= strlen (p
->name
);
1901 if (strncmp (p
->name
, s
, len
) == 0)
1907 error_message
= _(": unrecognizable privileged register");
1911 opcode
|= (p
->regnum
<< 14);
1913 opcode
|= (p
->regnum
<< 25);
1919 error_message
= _(": unrecognizable privileged register");
1925 /* Parse a sparc64 hyperprivileged register. */
1928 struct priv_reg_entry
*p
;
1929 unsigned int len
= 9999999; /* Init to make gcc happy. */
1932 for (p
= hpriv_reg_table
; p
->name
; p
++)
1933 if (p
->name
[0] == s
[0])
1935 len
= strlen (p
->name
);
1936 if (strncmp (p
->name
, s
, len
) == 0)
1942 error_message
= _(": unrecognizable hyperprivileged register");
1946 opcode
|= (p
->regnum
<< 14);
1948 opcode
|= (p
->regnum
<< 25);
1954 error_message
= _(": unrecognizable hyperprivileged register");
1960 /* Parse a v9a or later ancillary state register. */
1963 struct priv_reg_entry
*p
;
1964 unsigned int len
= 9999999; /* Init to make gcc happy. */
1967 for (p
= v9a_asr_table
; p
->name
; p
++)
1968 if (p
->name
[0] == s
[0])
1970 len
= strlen (p
->name
);
1971 if (strncmp (p
->name
, s
, len
) == 0)
1977 error_message
= _(": unrecognizable ancillary state register");
1980 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1982 error_message
= _(": rd on write only ancillary state register");
1986 && (insn
->architecture
1987 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1989 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1990 error_message
= _(": unrecognizable v9a ancillary state register");
1994 opcode
|= (p
->regnum
<< 14);
1996 opcode
|= (p
->regnum
<< 25);
2002 error_message
= _(": unrecognizable ancillary state register");
2008 if (strncmp (s
, "%asr", 4) == 0)
2016 while (ISDIGIT (*s
))
2018 num
= num
* 10 + *s
- '0';
2022 /* We used to check here for the asr number to
2023 be between 16 and 31 in V9 and later, as
2024 mandated by the section C.1.1 "Register
2025 Names" in the SPARC spec. However, we
2026 decided to remove this restriction as a) it
2027 introduces problems when new V9 asr registers
2028 are introduced, b) the Solaris assembler
2029 doesn't implement this restriction and c) the
2030 restriction will go away in future revisions
2031 of the Oracle SPARC Architecture. */
2033 if (num
< 0 || 31 < num
)
2035 error_message
= _(": asr number must be between 0 and 31");
2039 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2044 error_message
= _(": expecting %asrN");
2051 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2055 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2061 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2066 if (s
[0] == '0' && s
[1] == 'x')
2069 while (ISXDIGIT (*s
))
2072 num
|= hex_value (*s
);
2078 while (ISDIGIT (*s
))
2080 num
= num
* 10 + *s
- '0';
2084 if (num
< 0 || num
> 31)
2086 error_message
= _(": crypto immediate must be between 0 and 31");
2090 opcode
|= RS3 (num
);
2095 error_message
= _(": expecting crypto immediate");
2100 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2101 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2102 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2104 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2105 /* These fields are unsigned, but for upward compatibility,
2106 allow negative values as well. */
2110 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2111 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2112 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2114 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2115 /* These fields are unsigned, but for upward compatibility,
2116 allow negative values as well. */
2120 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2125 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2130 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2135 if (*s
== 'p' && s
[1] == 'n')
2143 if (*s
== 'p' && s
[1] == 't')
2155 if ((strncmp (s
, "%icc", 4) == 0)
2156 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2168 if ((strncmp (s
, "%xcc", 4) == 0)
2169 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2181 if (strncmp (s
, "%fcc0", 5) == 0)
2193 if (strncmp (s
, "%fcc1", 5) == 0)
2205 if (strncmp (s
, "%fcc2", 5) == 0)
2217 if (strncmp (s
, "%fcc3", 5) == 0)
2225 if (strncmp (s
, "%pc", 3) == 0)
2233 if (strncmp (s
, "%tick", 5) == 0)
2240 case '\0': /* End of args. */
2241 if (s
[0] == ',' && s
[1] == '%')
2245 const struct perc_entry
*p
;
2247 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2248 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2249 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2251 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2254 if (s
[p
->len
+ 2] != '(')
2256 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2257 return special_case
;
2260 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2261 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2263 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2265 return special_case
;
2268 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2269 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2270 || the_insn
.exp
.X_add_number
!= 0
2271 || the_insn
.exp
.X_add_symbol
2272 != symbol_find_or_make ("__tls_get_addr")))
2274 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2276 return special_case
;
2279 the_insn
.reloc
= p
->pop
->reloc
;
2280 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2283 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2286 else if (*s1
== ')')
2295 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2296 return special_case
;
2300 (void) get_expression (s
);
2320 case '[': /* These must match exactly. */
2328 case '#': /* Must be at least one digit. */
2331 while (ISDIGIT (*s
))
2339 case 'C': /* Coprocessor state register. */
2340 if (strncmp (s
, "%csr", 4) == 0)
2347 case 'b': /* Next operand is a coprocessor register. */
2350 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2355 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2369 opcode
|= mask
<< 14;
2377 opcode
|= mask
<< 25;
2383 case 'r': /* next operand must be a register */
2393 case 'f': /* frame pointer */
2401 case 'g': /* global register */
2410 case 'i': /* in register */
2414 mask
= c
- '0' + 24;
2419 case 'l': /* local register */
2423 mask
= (c
- '0' + 16);
2428 case 'o': /* out register */
2432 mask
= (c
- '0' + 8);
2437 case 's': /* stack pointer */
2445 case 'r': /* any register */
2446 if (!ISDIGIT ((c
= *s
++)))
2463 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2479 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2480 && no_undeclared_regs
&& ! globals
[mask
])
2481 as_bad (_("detected global register use not covered by .register pseudo-op"));
2483 /* Got the register, now figure out where
2484 it goes in the opcode. */
2488 opcode
|= mask
<< 14;
2496 opcode
|= mask
<< 25;
2500 opcode
|= (mask
<< 25) | (mask
<< 14);
2504 opcode
|= (mask
<< 25) | (mask
<< 0);
2510 case 'e': /* next operand is a floating point register */
2529 && ((format
= *s
) == 'f'
2534 for (mask
= 0; ISDIGIT (*s
); ++s
)
2536 mask
= 10 * mask
+ (*s
- '0');
2537 } /* read the number */
2546 /* register must be even numbered */
2556 /* register must be multiple of 4 */
2562 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2563 error_message
= _(": There are only 64 f registers; [0-63]");
2565 error_message
= _(": There are only 32 f registers; [0-31]");
2568 else if (mask
>= 32)
2570 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2572 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2575 = _(": There are only 32 single precision f registers; [0-31]");
2579 mask
-= 31; /* wrap high bit */
2583 error_message
= _(": There are only 32 f registers; [0-31]");
2591 } /* if not an 'f' register. */
2593 if (*args
== '}' && mask
!= RS2 (opcode
))
2596 = _(": Instruction requires frs2 and frsd must be the same register");
2605 opcode
|= RS1 (mask
);
2611 opcode
|= RS2 (mask
);
2616 opcode
|= RS3 (mask
);
2623 opcode
|= RD (mask
);
2632 if (strncmp (s
, "%fsr", 4) == 0)
2640 if (strncmp (s
, "%efsr", 5) == 0)
2647 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2648 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2651 case 'l': /* 22 bit PC relative immediate */
2652 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2656 case 'L': /* 30 bit immediate */
2657 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2662 case 'n': /* 22 bit immediate */
2663 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2666 case 'i': /* 13 bit immediate */
2667 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2677 const char *op_arg
= NULL
;
2678 static expressionS op_exp
;
2679 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2681 /* Check for %hi, etc. */
2684 const struct perc_entry
*p
;
2686 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2687 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2688 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2690 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2693 if (s
[p
->len
+ 1] != '(')
2695 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2696 return special_case
;
2700 the_insn
.reloc
= p
->pop
->reloc
;
2702 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2705 /* Note that if the get_expression() fails, we will still
2706 have created U entries in the symbol table for the
2707 'symbols' in the input string. Try not to create U
2708 symbols for registers, etc. */
2710 /* This stuff checks to see if the expression ends in
2711 +%reg. If it does, it removes the register from
2712 the expression, and re-sets 's' to point to the
2719 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2722 else if (*s1
== ')')
2731 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2732 return special_case
;
2736 (void) get_expression (s
);
2740 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2741 return special_case
;
2744 if (*s
== ',' || *s
== ']' || !*s
)
2746 if (*s
!= '+' && *s
!= '-')
2748 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2749 return special_case
;
2753 op_exp
= the_insn
.exp
;
2754 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2757 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2760 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2762 if (s1
[-2] == '%' && s1
[-3] == '+')
2764 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2766 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2773 if (op_arg
&& s1
== s
+ 1)
2774 the_insn
.exp
.X_op
= O_absent
;
2776 (void) get_expression (s
);
2788 (void) get_expression (s
);
2796 the_insn
.exp2
= the_insn
.exp
;
2797 the_insn
.exp
= op_exp
;
2798 if (the_insn
.exp2
.X_op
== O_absent
)
2799 the_insn
.exp2
.X_op
= O_illegal
;
2800 else if (the_insn
.exp
.X_op
== O_absent
)
2802 the_insn
.exp
= the_insn
.exp2
;
2803 the_insn
.exp2
.X_op
= O_illegal
;
2805 else if (the_insn
.exp
.X_op
== O_constant
)
2807 valueT val
= the_insn
.exp
.X_add_number
;
2808 switch (the_insn
.reloc
)
2813 case BFD_RELOC_SPARC_HH22
:
2814 val
= BSR (val
, 32);
2817 case BFD_RELOC_SPARC_LM22
:
2818 case BFD_RELOC_HI22
:
2819 val
= (val
>> 10) & 0x3fffff;
2822 case BFD_RELOC_SPARC_HM10
:
2823 val
= BSR (val
, 32);
2826 case BFD_RELOC_LO10
:
2830 case BFD_RELOC_SPARC_H34
:
2835 case BFD_RELOC_SPARC_H44
:
2840 case BFD_RELOC_SPARC_M44
:
2845 case BFD_RELOC_SPARC_L44
:
2849 case BFD_RELOC_SPARC_HIX22
:
2851 val
= (val
>> 10) & 0x3fffff;
2854 case BFD_RELOC_SPARC_LOX10
:
2855 val
= (val
& 0x3ff) | 0x1c00;
2858 the_insn
.exp
= the_insn
.exp2
;
2859 the_insn
.exp
.X_add_number
+= val
;
2860 the_insn
.exp2
.X_op
= O_illegal
;
2861 the_insn
.reloc
= old_reloc
;
2863 else if (the_insn
.exp2
.X_op
!= O_constant
)
2865 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2866 return special_case
;
2870 if (old_reloc
!= BFD_RELOC_SPARC13
2871 || the_insn
.reloc
!= BFD_RELOC_LO10
2872 || sparc_arch_size
!= 64
2875 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2876 return special_case
;
2878 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2882 /* Check for constants that don't require emitting a reloc. */
2883 if (the_insn
.exp
.X_op
== O_constant
2884 && the_insn
.exp
.X_add_symbol
== 0
2885 && the_insn
.exp
.X_op_symbol
== 0)
2887 /* For pc-relative call instructions, we reject
2888 constants to get better code. */
2890 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2891 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2893 error_message
= _(": PC-relative operand can't be a constant");
2897 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2898 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2900 error_message
= _(": TLS operand can't be a constant");
2904 /* Constants that won't fit are checked in md_apply_fix
2905 and bfd_install_relocation.
2906 ??? It would be preferable to install the constants
2907 into the insn here and save having to create a fixS
2908 for each one. There already exists code to handle
2909 all the various cases (e.g. in md_apply_fix and
2910 bfd_install_relocation) so duplicating all that code
2911 here isn't right. */
2913 /* This is a special case to handle cbcond instructions
2914 properly, which can need two relocations. The first
2915 one is for the 5-bit immediate field and the latter
2916 is going to be for the WDISP10 branch part. We
2917 handle the R_SPARC_5 immediate directly here so that
2918 we don't need to add support for multiple relocations
2919 in one instruction just yet. */
2920 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2922 valueT val
= the_insn
.exp
.X_add_number
;
2924 if (! in_bitfield_range (val
, 0x1f))
2926 error_message
= _(": Immediate value in cbcond is out of range.");
2929 opcode
|= val
& 0x1f;
2930 the_insn
.reloc
= BFD_RELOC_NONE
;
2951 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2953 error_message
= _(": invalid ASI name");
2959 if (! parse_const_expr_arg (&s
, &asi
))
2961 error_message
= _(": invalid ASI expression");
2964 if (asi
< 0 || asi
> 255)
2966 error_message
= _(": invalid ASI number");
2970 opcode
|= ASI (asi
);
2972 } /* Alternate space. */
2975 if (strncmp (s
, "%psr", 4) == 0)
2982 case 'q': /* Floating point queue. */
2983 if (strncmp (s
, "%fq", 3) == 0)
2990 case 'Q': /* Coprocessor queue. */
2991 if (strncmp (s
, "%cq", 3) == 0)
2999 if (strcmp (str
, "set") == 0
3000 || strcmp (str
, "setuw") == 0)
3002 special_case
= SPECIAL_CASE_SET
;
3005 else if (strcmp (str
, "setsw") == 0)
3007 special_case
= SPECIAL_CASE_SETSW
;
3010 else if (strcmp (str
, "setx") == 0)
3012 special_case
= SPECIAL_CASE_SETX
;
3015 else if (strncmp (str
, "fdiv", 4) == 0)
3017 special_case
= SPECIAL_CASE_FDIV
;
3023 if (strncmp (s
, "%asi", 4) != 0)
3029 if (strncmp (s
, "%fprs", 5) != 0)
3035 if (strncmp (s
, "%mcdper",7) != 0)
3041 if (strncmp (s
, "%ccr", 4) != 0)
3047 if (strncmp (s
, "%tbr", 4) != 0)
3053 if (strncmp (s
, "%wim", 4) != 0)
3060 char *push
= input_line_pointer
;
3063 input_line_pointer
= s
;
3065 if (e
.X_op
== O_constant
)
3067 int n
= e
.X_add_number
;
3068 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3069 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3071 opcode
|= e
.X_add_number
<< 5;
3074 as_bad (_("non-immediate OPF operand, ignored"));
3075 s
= input_line_pointer
;
3076 input_line_pointer
= push
;
3081 if (strncmp (s
, "%y", 2) != 0)
3089 /* Parse a sparclet cpreg. */
3091 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3093 error_message
= _(": invalid cpreg name");
3096 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3101 as_fatal (_("failed sanity check."));
3102 } /* switch on arg code. */
3104 /* Break out of for() loop. */
3106 } /* For each arg that we expect. */
3111 /* Args don't match. */
3112 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3113 && (insn
->name
== insn
[1].name
3114 || !strcmp (insn
->name
, insn
[1].name
)))
3122 as_bad (_("Illegal operands%s"), error_message
);
3123 return special_case
;
3128 /* We have a match. Now see if the architecture is OK. */
3129 int needed_arch_mask
= insn
->architecture
;
3131 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3133 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3135 hwcap_seen
|= hwcaps
;
3140 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3141 if (! needed_arch_mask
)
3143 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3146 if (needed_arch_mask
3147 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3150 /* Can we bump up the architecture? */
3151 else if (needed_arch_mask
3152 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3154 enum sparc_opcode_arch_val needed_architecture
=
3155 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3156 & needed_arch_mask
);
3158 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3160 && needed_architecture
> warn_after_architecture
)
3162 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3163 sparc_opcode_archs
[current_architecture
].name
,
3164 sparc_opcode_archs
[needed_architecture
].name
,
3166 warn_after_architecture
= needed_architecture
;
3168 current_architecture
= needed_architecture
;
3169 hwcap_allowed
|= hwcaps
;
3172 /* ??? This seems to be a bit fragile. What if the next entry in
3173 the opcode table is the one we want and it is supported?
3174 It is possible to arrange the table today so that this can't
3175 happen but what about tomorrow? */
3178 int arch
, printed_one_p
= 0;
3180 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3182 /* Create a list of the architectures that support the insn. */
3183 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3185 arch
= sparc_ffs (needed_arch_mask
);
3186 while ((1 << arch
) <= needed_arch_mask
)
3188 if ((1 << arch
) & needed_arch_mask
)
3192 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3199 as_bad (_("Architecture mismatch on \"%s\"."), str
);
3200 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
3202 sparc_opcode_archs
[max_architecture
].name
);
3203 return special_case
;
3206 /* Make sure the hwcaps used by the instruction are
3207 currently enabled. */
3208 if (hwcaps
& ~hwcap_allowed
)
3210 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3212 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3214 return special_case
;
3216 } /* If no match. */
3219 } /* Forever looking for a match. */
3221 the_insn
.opcode
= opcode
;
3222 return special_case
;
3225 /* Parse an argument that can be expressed as a keyword.
3226 (eg: #StoreStore or %ccfr).
3227 The result is a boolean indicating success.
3228 If successful, INPUT_POINTER is updated. */
3231 parse_keyword_arg (int (*lookup_fn
) (const char *),
3232 char **input_pointerP
,
3238 p
= *input_pointerP
;
3239 for (q
= p
+ (*p
== '#' || *p
== '%');
3240 ISALNUM (*q
) || *q
== '_';
3245 value
= (*lookup_fn
) (p
);
3250 *input_pointerP
= q
;
3254 /* Parse an argument that is a constant expression.
3255 The result is a boolean indicating success. */
3258 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3260 char *save
= input_line_pointer
;
3263 input_line_pointer
= *input_pointerP
;
3264 /* The next expression may be something other than a constant
3265 (say if we're not processing the right variant of the insn).
3266 Don't call expression unless we're sure it will succeed as it will
3267 signal an error (which we want to defer until later). */
3268 /* FIXME: It might be better to define md_operand and have it recognize
3269 things like %asi, etc. but continuing that route through to the end
3270 is a lot of work. */
3271 if (*input_line_pointer
== '%')
3273 input_line_pointer
= save
;
3277 *input_pointerP
= input_line_pointer
;
3278 input_line_pointer
= save
;
3279 if (exp
.X_op
!= O_constant
)
3281 *valueP
= exp
.X_add_number
;
3285 /* Subroutine of sparc_ip to parse an expression. */
3288 get_expression (char *str
)
3293 save_in
= input_line_pointer
;
3294 input_line_pointer
= str
;
3295 seg
= expression (&the_insn
.exp
);
3296 if (seg
!= absolute_section
3297 && seg
!= text_section
3298 && seg
!= data_section
3299 && seg
!= bss_section
3300 && seg
!= undefined_section
)
3302 the_insn
.error
= _("bad segment");
3303 expr_end
= input_line_pointer
;
3304 input_line_pointer
= save_in
;
3307 expr_end
= input_line_pointer
;
3308 input_line_pointer
= save_in
;
3312 /* Subroutine of md_assemble to output one insn. */
3315 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3317 char *toP
= frag_more (4);
3319 /* Put out the opcode. */
3320 if (INSN_BIG_ENDIAN
)
3321 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3323 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3325 /* Put out the symbol-dependent stuff. */
3326 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3328 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3329 (toP
- frag_now
->fr_literal
), /* Where. */
3334 /* Turn off overflow checking in fixup_segment. We'll do our
3335 own overflow checking in md_apply_fix. This is necessary because
3336 the insn size is 4 and fixup_segment will signal an overflow for
3337 large 8 byte quantities. */
3338 fixP
->fx_no_overflow
= 1;
3339 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3340 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3344 last_opcode
= theinsn
->opcode
;
3347 dwarf2_emit_insn (4);
3352 md_atof (int type
, char *litP
, int *sizeP
)
3354 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3357 /* Write a value out to the object file, using the appropriate
3361 md_number_to_chars (char *buf
, valueT val
, int n
)
3363 if (target_big_endian
)
3364 number_to_chars_bigendian (buf
, val
, n
);
3365 else if (target_little_endian_data
3366 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3367 /* Output debug words, which are not in allocated sections, as big
3369 number_to_chars_bigendian (buf
, val
, n
);
3370 else if (target_little_endian_data
|| ! target_big_endian
)
3371 number_to_chars_littleendian (buf
, val
, n
);
3374 /* Apply a fixS to the frags, now that we know the value it ought to
3378 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3380 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3381 offsetT val
= * (offsetT
*) valP
;
3384 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3386 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3389 /* SPARC ELF relocations don't use an addend in the data field. */
3390 if (fixP
->fx_addsy
!= NULL
)
3392 switch (fixP
->fx_r_type
)
3394 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3395 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3396 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3397 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3398 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3399 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3400 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3401 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3402 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3403 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3404 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3405 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3406 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3407 case BFD_RELOC_SPARC_TLS_IE_LD
:
3408 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3409 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3410 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3411 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3412 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3413 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3414 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3415 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3416 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3417 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3418 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3428 /* This is a hack. There should be a better way to
3429 handle this. Probably in terms of howto fields, once
3430 we can look at these fixups in terms of howtos. */
3431 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3432 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3435 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3436 generate a reloc, then we just want to let the reloc addend set
3437 the value. We do not want to also stuff the addend into the
3438 object file. Including the addend in the object file works when
3439 doing a static link, because the linker will ignore the object
3440 file contents. However, the dynamic linker does not ignore the
3441 object file contents. */
3442 if (fixP
->fx_addsy
!= NULL
3443 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3446 /* When generating PIC code, we do not want an addend for a reloc
3447 against a local symbol. We adjust fx_addnumber to cancel out the
3448 value already included in val, and to also cancel out the
3449 adjustment which bfd_install_relocation will create. */
3451 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3452 && fixP
->fx_addsy
!= NULL
3453 && ! S_IS_COMMON (fixP
->fx_addsy
)
3454 && symbol_section_p (fixP
->fx_addsy
))
3455 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3457 /* When generating PIC code, we need to fiddle to get
3458 bfd_install_relocation to do the right thing for a PC relative
3459 reloc against a local symbol which we are going to keep. */
3461 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3462 && fixP
->fx_addsy
!= NULL
3463 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3464 || S_IS_WEAK (fixP
->fx_addsy
))
3465 && S_IS_DEFINED (fixP
->fx_addsy
)
3466 && ! S_IS_COMMON (fixP
->fx_addsy
))
3469 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3473 /* If this is a data relocation, just output VAL. */
3475 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3477 md_number_to_chars (buf
, val
, 1);
3479 else if (fixP
->fx_r_type
== BFD_RELOC_16
3480 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3482 md_number_to_chars (buf
, val
, 2);
3484 else if (fixP
->fx_r_type
== BFD_RELOC_32
3485 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3486 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3488 md_number_to_chars (buf
, val
, 4);
3490 else if (fixP
->fx_r_type
== BFD_RELOC_64
3491 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3493 md_number_to_chars (buf
, val
, 8);
3495 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3496 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3503 /* It's a relocation against an instruction. */
3505 if (INSN_BIG_ENDIAN
)
3506 insn
= bfd_getb32 ((unsigned char *) buf
);
3508 insn
= bfd_getl32 ((unsigned char *) buf
);
3510 switch (fixP
->fx_r_type
)
3512 case BFD_RELOC_32_PCREL_S2
:
3514 /* FIXME: This increment-by-one deserves a comment of why it's
3516 if (! sparc_pic_code
3517 || fixP
->fx_addsy
== NULL
3518 || symbol_section_p (fixP
->fx_addsy
))
3521 insn
|= val
& 0x3fffffff;
3523 /* See if we have a delay slot. */
3524 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3528 #define XCC (2 << 20)
3529 #define COND(x) (((x)&0xf)<<25)
3530 #define CONDA COND(0x8)
3531 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3532 #define INSN_BA (F2(0,2) | CONDA)
3533 #define INSN_OR F3(2, 0x2, 0)
3534 #define INSN_NOP F2(0,4)
3538 /* If the instruction is a call with either:
3540 arithmetic instruction with rd == %o7
3541 where rs1 != %o7 and rs2 if it is register != %o7
3542 then we can optimize if the call destination is near
3543 by changing the call into a branch always. */
3544 if (INSN_BIG_ENDIAN
)
3545 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3547 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3548 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3550 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3551 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3552 || ((delay
& RD (~0)) != RD (O7
))))
3554 if ((delay
& RS1 (~0)) == RS1 (O7
)
3555 || ((delay
& F3I (~0)) == 0
3556 && (delay
& RS2 (~0)) == RS2 (O7
)))
3558 /* Ensure the branch will fit into simm22. */
3559 if ((val
& 0x3fe00000)
3560 && (val
& 0x3fe00000) != 0x3fe00000)
3562 /* Check if the arch is v9 and branch will fit
3564 if (((val
& 0x3c0000) == 0
3565 || (val
& 0x3c0000) == 0x3c0000)
3566 && (sparc_arch_size
== 64
3567 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3569 insn
= INSN_BPA
| (val
& 0x7ffff);
3572 insn
= INSN_BA
| (val
& 0x3fffff);
3573 if (fixP
->fx_where
>= 4
3574 && ((delay
& (0xffffffff ^ RS1 (~0)))
3575 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3580 if (INSN_BIG_ENDIAN
)
3581 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3583 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3584 if ((setter
& (0xffffffff ^ RD (~0)))
3585 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3592 If call foo was replaced with ba, replace
3593 or %rN, %g0, %o7 with nop. */
3594 reg
= (delay
& RS1 (~0)) >> 14;
3595 if (reg
!= ((setter
& RD (~0)) >> 25)
3596 || reg
== G0
|| reg
== O7
)
3599 if (INSN_BIG_ENDIAN
)
3600 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3602 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3607 case BFD_RELOC_SPARC_11
:
3608 if (! in_signed_range (val
, 0x7ff))
3609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3610 _("relocation overflow"));
3611 insn
|= val
& 0x7ff;
3614 case BFD_RELOC_SPARC_10
:
3615 if (! in_signed_range (val
, 0x3ff))
3616 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3617 _("relocation overflow"));
3618 insn
|= val
& 0x3ff;
3621 case BFD_RELOC_SPARC_7
:
3622 if (! in_bitfield_range (val
, 0x7f))
3623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3624 _("relocation overflow"));
3628 case BFD_RELOC_SPARC_6
:
3629 if (! in_bitfield_range (val
, 0x3f))
3630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3631 _("relocation overflow"));
3635 case BFD_RELOC_SPARC_5
:
3636 if (! in_bitfield_range (val
, 0x1f))
3637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3638 _("relocation overflow"));
3642 case BFD_RELOC_SPARC_WDISP10
:
3645 || val
<= -(offsetT
) 0x808)
3646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3647 _("relocation overflow"));
3648 /* FIXME: The +1 deserves a comment. */
3649 val
= (val
>> 2) + 1;
3650 insn
|= ((val
& 0x300) << 11)
3651 | ((val
& 0xff) << 5);
3654 case BFD_RELOC_SPARC_WDISP16
:
3657 || val
<= -(offsetT
) 0x20008)
3658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3659 _("relocation overflow"));
3660 /* FIXME: The +1 deserves a comment. */
3661 val
= (val
>> 2) + 1;
3662 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3665 case BFD_RELOC_SPARC_WDISP19
:
3668 || val
<= -(offsetT
) 0x100008)
3669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3670 _("relocation overflow"));
3671 /* FIXME: The +1 deserves a comment. */
3672 val
= (val
>> 2) + 1;
3673 insn
|= val
& 0x7ffff;
3676 case BFD_RELOC_SPARC_HH22
:
3677 val
= BSR (val
, 32);
3680 case BFD_RELOC_SPARC_LM22
:
3681 case BFD_RELOC_HI22
:
3682 if (!fixP
->fx_addsy
)
3683 insn
|= (val
>> 10) & 0x3fffff;
3685 /* FIXME: Need comment explaining why we do this. */
3689 case BFD_RELOC_SPARC22
:
3690 if (val
& ~0x003fffff)
3691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3692 _("relocation overflow"));
3693 insn
|= (val
& 0x3fffff);
3696 case BFD_RELOC_SPARC_HM10
:
3697 val
= BSR (val
, 32);
3700 case BFD_RELOC_LO10
:
3701 if (!fixP
->fx_addsy
)
3702 insn
|= val
& 0x3ff;
3704 /* FIXME: Need comment explaining why we do this. */
3708 case BFD_RELOC_SPARC_OLO10
:
3710 val
+= fixP
->tc_fix_data
;
3713 case BFD_RELOC_SPARC13
:
3714 if (! in_signed_range (val
, 0x1fff))
3715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3716 _("relocation overflow"));
3717 insn
|= val
& 0x1fff;
3720 case BFD_RELOC_SPARC_WDISP22
:
3721 val
= (val
>> 2) + 1;
3723 case BFD_RELOC_SPARC_BASE22
:
3724 insn
|= val
& 0x3fffff;
3727 case BFD_RELOC_SPARC_H34
:
3728 if (!fixP
->fx_addsy
)
3732 insn
|= tval
& 0x3fffff;
3736 case BFD_RELOC_SPARC_H44
:
3737 if (!fixP
->fx_addsy
)
3741 insn
|= tval
& 0x3fffff;
3745 case BFD_RELOC_SPARC_M44
:
3746 if (!fixP
->fx_addsy
)
3747 insn
|= (val
>> 12) & 0x3ff;
3750 case BFD_RELOC_SPARC_L44
:
3751 if (!fixP
->fx_addsy
)
3752 insn
|= val
& 0xfff;
3755 case BFD_RELOC_SPARC_HIX22
:
3756 if (!fixP
->fx_addsy
)
3758 val
^= ~(offsetT
) 0;
3759 insn
|= (val
>> 10) & 0x3fffff;
3763 case BFD_RELOC_SPARC_LOX10
:
3764 if (!fixP
->fx_addsy
)
3765 insn
|= 0x1c00 | (val
& 0x3ff);
3768 case BFD_RELOC_NONE
:
3770 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3771 _("bad or unhandled relocation type: 0x%02x"),
3776 if (INSN_BIG_ENDIAN
)
3777 bfd_putb32 (insn
, (unsigned char *) buf
);
3779 bfd_putl32 (insn
, (unsigned char *) buf
);
3782 /* Are we finished with this relocation now? */
3783 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3787 /* Translate internal representation of relocation info to BFD target
3791 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3793 static arelent
*relocs
[3];
3795 bfd_reloc_code_real_type code
;
3797 relocs
[0] = reloc
= XNEW (arelent
);
3800 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3801 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3802 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3804 switch (fixp
->fx_r_type
)
3808 case BFD_RELOC_HI22
:
3809 case BFD_RELOC_LO10
:
3810 case BFD_RELOC_32_PCREL_S2
:
3811 case BFD_RELOC_SPARC13
:
3812 case BFD_RELOC_SPARC22
:
3813 case BFD_RELOC_SPARC_PC22
:
3814 case BFD_RELOC_SPARC_PC10
:
3815 case BFD_RELOC_SPARC_BASE13
:
3816 case BFD_RELOC_SPARC_WDISP10
:
3817 case BFD_RELOC_SPARC_WDISP16
:
3818 case BFD_RELOC_SPARC_WDISP19
:
3819 case BFD_RELOC_SPARC_WDISP22
:
3821 case BFD_RELOC_SPARC_5
:
3822 case BFD_RELOC_SPARC_6
:
3823 case BFD_RELOC_SPARC_7
:
3824 case BFD_RELOC_SPARC_10
:
3825 case BFD_RELOC_SPARC_11
:
3826 case BFD_RELOC_SPARC_HH22
:
3827 case BFD_RELOC_SPARC_HM10
:
3828 case BFD_RELOC_SPARC_LM22
:
3829 case BFD_RELOC_SPARC_PC_HH22
:
3830 case BFD_RELOC_SPARC_PC_HM10
:
3831 case BFD_RELOC_SPARC_PC_LM22
:
3832 case BFD_RELOC_SPARC_H34
:
3833 case BFD_RELOC_SPARC_H44
:
3834 case BFD_RELOC_SPARC_M44
:
3835 case BFD_RELOC_SPARC_L44
:
3836 case BFD_RELOC_SPARC_HIX22
:
3837 case BFD_RELOC_SPARC_LOX10
:
3838 case BFD_RELOC_SPARC_REV32
:
3839 case BFD_RELOC_SPARC_OLO10
:
3840 case BFD_RELOC_SPARC_UA16
:
3841 case BFD_RELOC_SPARC_UA32
:
3842 case BFD_RELOC_SPARC_UA64
:
3843 case BFD_RELOC_8_PCREL
:
3844 case BFD_RELOC_16_PCREL
:
3845 case BFD_RELOC_32_PCREL
:
3846 case BFD_RELOC_64_PCREL
:
3847 case BFD_RELOC_SPARC_PLT32
:
3848 case BFD_RELOC_SPARC_PLT64
:
3849 case BFD_RELOC_VTABLE_ENTRY
:
3850 case BFD_RELOC_VTABLE_INHERIT
:
3851 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3852 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3853 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3854 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3855 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3856 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3857 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3858 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3859 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3860 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3861 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3862 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3863 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3864 case BFD_RELOC_SPARC_TLS_IE_LD
:
3865 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3866 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3867 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3868 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3869 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3870 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3871 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3872 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3873 case BFD_RELOC_SPARC_GOTDATA_OP
:
3874 code
= fixp
->fx_r_type
;
3881 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3882 /* If we are generating PIC code, we need to generate a different
3886 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3888 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3891 #define GOTT_BASE "__GOTT_BASE__"
3892 #define GOTT_INDEX "__GOTT_INDEX__"
3895 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3901 case BFD_RELOC_32_PCREL_S2
:
3902 if (generic_force_reloc (fixp
))
3903 code
= BFD_RELOC_SPARC_WPLT30
;
3905 case BFD_RELOC_HI22
:
3906 code
= BFD_RELOC_SPARC_GOT22
;
3907 if (fixp
->fx_addsy
!= NULL
)
3909 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3910 code
= BFD_RELOC_SPARC_PC22
;
3912 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3913 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3914 code
= BFD_RELOC_HI22
; /* Unchanged. */
3918 case BFD_RELOC_LO10
:
3919 code
= BFD_RELOC_SPARC_GOT10
;
3920 if (fixp
->fx_addsy
!= NULL
)
3922 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3923 code
= BFD_RELOC_SPARC_PC10
;
3925 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3926 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3927 code
= BFD_RELOC_LO10
; /* Unchanged. */
3931 case BFD_RELOC_SPARC13
:
3932 code
= BFD_RELOC_SPARC_GOT13
;
3938 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3940 /* Nothing is aligned in DWARF debugging sections. */
3941 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3944 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3945 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3946 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3950 if (code
== BFD_RELOC_SPARC_OLO10
)
3951 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3953 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3954 if (reloc
->howto
== 0)
3956 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3957 _("internal error: can't export reloc type %d (`%s')"),
3958 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3964 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3967 if (reloc
->howto
->pc_relative
== 0
3968 || code
== BFD_RELOC_SPARC_PC10
3969 || code
== BFD_RELOC_SPARC_PC22
)
3970 reloc
->addend
= fixp
->fx_addnumber
;
3971 else if (sparc_pic_code
3972 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3973 && fixp
->fx_addsy
!= NULL
3974 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3975 || S_IS_WEAK (fixp
->fx_addsy
))
3976 && S_IS_DEFINED (fixp
->fx_addsy
)
3977 && ! S_IS_COMMON (fixp
->fx_addsy
))
3978 reloc
->addend
= fixp
->fx_addnumber
;
3980 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3982 #else /* elf or coff */
3984 if (code
!= BFD_RELOC_32_PCREL_S2
3985 && code
!= BFD_RELOC_SPARC_WDISP22
3986 && code
!= BFD_RELOC_SPARC_WDISP16
3987 && code
!= BFD_RELOC_SPARC_WDISP19
3988 && code
!= BFD_RELOC_SPARC_WDISP10
3989 && code
!= BFD_RELOC_SPARC_WPLT30
3990 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3991 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3992 reloc
->addend
= fixp
->fx_addnumber
;
3993 else if (symbol_section_p (fixp
->fx_addsy
))
3994 reloc
->addend
= (section
->vma
3995 + fixp
->fx_addnumber
3996 + md_pcrel_from (fixp
));
3998 reloc
->addend
= fixp
->fx_offset
;
4001 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4002 on the same location. */
4003 if (code
== BFD_RELOC_SPARC_OLO10
)
4005 relocs
[1] = reloc
= XNEW (arelent
);
4008 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4010 = symbol_get_bfdsym (section_symbol (absolute_section
));
4011 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4012 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4013 reloc
->addend
= fixp
->tc_fix_data
;
4019 /* We have no need to default values of symbols. */
4022 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4027 /* Round up a section size to the appropriate boundary. */
4030 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4033 /* This is not right for ELF; a.out wants it, and COFF will force
4034 the alignment anyways. */
4035 valueT align
= ((valueT
) 1
4036 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
4039 /* Turn alignment value into a mask. */
4041 newsize
= (size
+ align
) & ~align
;
4048 /* Exactly what point is a PC-relative offset relative TO?
4049 On the sparc, they're relative to the address of the offset, plus
4050 its size. This gets us to the following instruction.
4051 (??? Is this right? FIXME-SOON) */
4053 md_pcrel_from (fixS
*fixP
)
4057 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4058 if (! sparc_pic_code
4059 || fixP
->fx_addsy
== NULL
4060 || symbol_section_p (fixP
->fx_addsy
))
4061 ret
+= fixP
->fx_size
;
4065 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4076 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4079 return (value
== 1) ? shift
: -1;
4082 /* Sort of like s_lcomm. */
4085 static int max_alignment
= 15;
4089 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4099 c
= get_symbol_name (&name
);
4100 p
= input_line_pointer
;
4102 SKIP_WHITESPACE_AFTER_NAME ();
4104 if (*input_line_pointer
!= ',')
4106 as_bad (_("Expected comma after name"));
4107 ignore_rest_of_line ();
4111 ++input_line_pointer
;
4113 if ((size
= get_absolute_expression ()) < 0)
4115 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4116 ignore_rest_of_line ();
4121 symbolP
= symbol_find_or_make (name
);
4124 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4125 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4127 as_bad (_("bad .reserve segment -- expected BSS segment"));
4131 if (input_line_pointer
[2] == '.')
4132 input_line_pointer
+= 7;
4134 input_line_pointer
+= 6;
4137 if (*input_line_pointer
== ',')
4139 ++input_line_pointer
;
4142 if (*input_line_pointer
== '\n')
4144 as_bad (_("missing alignment"));
4145 ignore_rest_of_line ();
4149 align
= (int) get_absolute_expression ();
4152 if (align
> max_alignment
)
4154 align
= max_alignment
;
4155 as_warn (_("alignment too large; assuming %d"), align
);
4161 as_bad (_("negative alignment"));
4162 ignore_rest_of_line ();
4168 temp
= mylog2 (align
);
4171 as_bad (_("alignment not a power of 2"));
4172 ignore_rest_of_line ();
4179 record_alignment (bss_section
, align
);
4184 if (!S_IS_DEFINED (symbolP
)
4186 && S_GET_OTHER (symbolP
) == 0
4187 && S_GET_DESC (symbolP
) == 0
4194 segT current_seg
= now_seg
;
4195 subsegT current_subseg
= now_subseg
;
4197 /* Switch to bss. */
4198 subseg_set (bss_section
, 1);
4202 frag_align (align
, 0, 0);
4204 /* Detach from old frag. */
4205 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4206 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4208 symbol_set_frag (symbolP
, frag_now
);
4209 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4210 (offsetT
) size
, (char *) 0);
4213 S_SET_SEGMENT (symbolP
, bss_section
);
4215 subseg_set (current_seg
, current_subseg
);
4218 S_SET_SIZE (symbolP
, size
);
4224 as_warn (_("Ignoring attempt to re-define symbol %s"),
4225 S_GET_NAME (symbolP
));
4228 demand_empty_rest_of_line ();
4232 s_common (int ignore ATTRIBUTE_UNUSED
)
4240 c
= get_symbol_name (&name
);
4241 /* Just after name is now '\0'. */
4242 p
= input_line_pointer
;
4244 SKIP_WHITESPACE_AFTER_NAME ();
4245 if (*input_line_pointer
!= ',')
4247 as_bad (_("Expected comma after symbol-name"));
4248 ignore_rest_of_line ();
4253 input_line_pointer
++;
4255 if ((temp
= get_absolute_expression ()) < 0)
4257 as_bad (_(".COMMon length (%lu) out of range ignored"),
4258 (unsigned long) temp
);
4259 ignore_rest_of_line ();
4264 symbolP
= symbol_find_or_make (name
);
4266 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4268 as_bad (_("Ignoring attempt to re-define symbol"));
4269 ignore_rest_of_line ();
4272 if (S_GET_VALUE (symbolP
) != 0)
4274 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4276 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4277 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4283 S_SET_VALUE (symbolP
, (valueT
) size
);
4284 S_SET_EXTERNAL (symbolP
);
4287 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4288 if (*input_line_pointer
!= ',')
4290 as_bad (_("Expected comma after common length"));
4291 ignore_rest_of_line ();
4294 input_line_pointer
++;
4296 if (*input_line_pointer
!= '"')
4298 temp
= get_absolute_expression ();
4301 if (temp
> max_alignment
)
4303 temp
= max_alignment
;
4304 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4310 as_bad (_("negative alignment"));
4311 ignore_rest_of_line ();
4316 if (symbol_get_obj (symbolP
)->local
)
4323 old_subsec
= now_subseg
;
4328 align
= mylog2 (temp
);
4332 as_bad (_("alignment not a power of 2"));
4333 ignore_rest_of_line ();
4337 record_alignment (bss_section
, align
);
4338 subseg_set (bss_section
, 0);
4340 frag_align (align
, 0, 0);
4341 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4342 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4343 symbol_set_frag (symbolP
, frag_now
);
4344 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4345 (offsetT
) size
, (char *) 0);
4347 S_SET_SEGMENT (symbolP
, bss_section
);
4348 S_CLEAR_EXTERNAL (symbolP
);
4349 S_SET_SIZE (symbolP
, size
);
4350 subseg_set (old_sec
, old_subsec
);
4353 #endif /* OBJ_ELF */
4356 S_SET_VALUE (symbolP
, (valueT
) size
);
4358 S_SET_ALIGN (symbolP
, temp
);
4359 S_SET_SIZE (symbolP
, size
);
4361 S_SET_EXTERNAL (symbolP
);
4362 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4367 input_line_pointer
++;
4368 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4369 if (*input_line_pointer
== '.')
4370 input_line_pointer
++;
4371 /* @@ Some say data, some say bss. */
4372 if (strncmp (input_line_pointer
, "bss\"", 4)
4373 && strncmp (input_line_pointer
, "data\"", 5))
4375 while (*--input_line_pointer
!= '"')
4377 input_line_pointer
--;
4378 goto bad_common_segment
;
4380 while (*input_line_pointer
++ != '"')
4382 goto allocate_common
;
4385 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4387 demand_empty_rest_of_line ();
4392 p
= input_line_pointer
;
4393 while (*p
&& *p
!= '\n')
4397 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4399 input_line_pointer
= p
;
4400 ignore_rest_of_line ();
4405 /* Handle the .empty pseudo-op. This suppresses the warnings about
4406 invalid delay slot usage. */
4409 s_empty (int ignore ATTRIBUTE_UNUSED
)
4411 /* The easy way to implement is to just forget about the last
4417 s_seg (int ignore ATTRIBUTE_UNUSED
)
4420 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4422 input_line_pointer
+= 6;
4426 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4428 input_line_pointer
+= 6;
4432 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4434 input_line_pointer
+= 7;
4438 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4440 input_line_pointer
+= 5;
4441 /* We only support 2 segments -- text and data -- for now, so
4442 things in the "bss segment" will have to go into data for now.
4443 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4444 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4447 as_bad (_("Unknown segment type"));
4448 demand_empty_rest_of_line ();
4454 subseg_set (data_section
, 1);
4455 demand_empty_rest_of_line ();
4459 s_proc (int ignore ATTRIBUTE_UNUSED
)
4461 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4463 ++input_line_pointer
;
4465 ++input_line_pointer
;
4468 /* This static variable is set by s_uacons to tell sparc_cons_align
4469 that the expression does not need to be aligned. */
4471 static int sparc_no_align_cons
= 0;
4473 /* This handles the unaligned space allocation pseudo-ops, such as
4474 .uaword. .uaword is just like .word, but the value does not need
4478 s_uacons (int bytes
)
4480 /* Tell sparc_cons_align not to align this value. */
4481 sparc_no_align_cons
= 1;
4483 sparc_no_align_cons
= 0;
4486 /* This handles the native word allocation pseudo-op .nword.
4487 For sparc_arch_size 32 it is equivalent to .word, for
4488 sparc_arch_size 64 it is equivalent to .xword. */
4491 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4493 cons (sparc_arch_size
== 32 ? 4 : 8);
4497 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4501 .register %g[2367],{#scratch|symbolname|#ignore}
4505 s_register (int ignore ATTRIBUTE_UNUSED
)
4512 if (input_line_pointer
[0] != '%'
4513 || input_line_pointer
[1] != 'g'
4514 || ((input_line_pointer
[2] & ~1) != '2'
4515 && (input_line_pointer
[2] & ~1) != '6')
4516 || input_line_pointer
[3] != ',')
4517 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4518 reg
= input_line_pointer
[2] - '0';
4519 input_line_pointer
+= 4;
4521 if (*input_line_pointer
== '#')
4523 ++input_line_pointer
;
4524 c
= get_symbol_name (®name
);
4525 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4526 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4527 if (regname
[0] == 'i')
4530 regname
= (char *) "";
4534 c
= get_symbol_name (®name
);
4537 if (sparc_arch_size
== 64)
4541 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4542 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4543 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4544 as_bad (_("redefinition of global register"));
4548 if (regname
== NULL
)
4549 globals
[reg
] = (symbolS
*) 1;
4554 if (symbol_find (regname
))
4555 as_bad (_("Register symbol %s already defined."),
4558 globals
[reg
] = symbol_make (regname
);
4559 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4561 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4562 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4563 flags
|= BSF_GLOBAL
;
4564 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4565 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4566 S_SET_ALIGN (globals
[reg
], reg
);
4567 S_SET_SIZE (globals
[reg
], 0);
4568 /* Although we actually want undefined_section here,
4569 we have to use absolute_section, because otherwise
4570 generic as code will make it a COM section.
4571 We fix this up in sparc_adjust_symtab. */
4572 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4573 S_SET_OTHER (globals
[reg
], 0);
4574 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4575 ->internal_elf_sym
.st_info
=
4576 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4577 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4578 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4583 (void) restore_line_pointer (c
);
4585 demand_empty_rest_of_line ();
4588 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4589 symbols which need it. */
4592 sparc_adjust_symtab (void)
4596 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4598 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4599 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4602 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4603 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4606 S_SET_SEGMENT (sym
, undefined_section
);
4611 /* If the --enforce-aligned-data option is used, we require .word,
4612 et. al., to be aligned correctly. We do it by setting up an
4613 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4614 no unexpected alignment was introduced.
4616 The SunOS and Solaris native assemblers enforce aligned data by
4617 default. We don't want to do that, because gcc can deliberately
4618 generate misaligned data if the packed attribute is used. Instead,
4619 we permit misaligned data by default, and permit the user to set an
4620 option to check for it. */
4623 sparc_cons_align (int nbytes
)
4627 /* Only do this if we are enforcing aligned data. */
4628 if (! enforce_aligned_data
)
4631 /* Don't align if this is an unaligned pseudo-op. */
4632 if (sparc_no_align_cons
)
4635 nalign
= mylog2 (nbytes
);
4639 gas_assert (nalign
> 0);
4641 if (now_seg
== absolute_section
)
4643 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4644 as_bad (_("misaligned data"));
4648 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4649 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4651 record_alignment (now_seg
, nalign
);
4654 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4657 sparc_handle_align (fragS
*fragp
)
4662 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4664 switch (fragp
->fr_type
)
4668 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4672 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4683 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4685 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4686 if (INSN_BIG_ENDIAN
)
4687 number_to_chars_bigendian (p
, wval
, 4);
4689 number_to_chars_littleendian (p
, wval
, 4);
4695 if (INSN_BIG_ENDIAN
)
4696 number_to_chars_bigendian (p
, 0x01000000, 4);
4698 number_to_chars_littleendian (p
, 0x01000000, 4);
4700 fragp
->fr_fix
+= fix
;
4710 /* Some special processing for a Sparc ELF file. */
4713 sparc_elf_final_processing (void)
4715 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4716 sort of BFD interface for this. */
4717 if (sparc_arch_size
== 64)
4719 switch (sparc_memory_model
)
4722 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4725 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4731 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4732 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4733 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4734 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4735 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4736 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4740 sparc_cons (expressionS
*exp
, int size
)
4743 const char *sparc_cons_special_reloc
= NULL
;
4746 save
= input_line_pointer
;
4747 if (input_line_pointer
[0] == '%'
4748 && input_line_pointer
[1] == 'r'
4749 && input_line_pointer
[2] == '_')
4751 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4753 input_line_pointer
+= 7;
4754 sparc_cons_special_reloc
= "disp";
4756 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4758 if (size
!= 4 && size
!= 8)
4759 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4762 input_line_pointer
+= 6;
4763 sparc_cons_special_reloc
= "plt";
4766 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4768 if (size
!= 4 && size
!= 8)
4769 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4772 input_line_pointer
+= 13;
4773 sparc_cons_special_reloc
= "tls_dtpoff";
4776 if (sparc_cons_special_reloc
)
4783 if (*input_line_pointer
!= '8')
4785 input_line_pointer
--;
4788 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4792 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4796 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4806 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4807 sparc_cons_special_reloc
, size
* 8, size
);
4811 input_line_pointer
+= 2;
4812 if (*input_line_pointer
!= '(')
4814 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4815 sparc_cons_special_reloc
, size
* 8);
4822 input_line_pointer
= save
;
4823 sparc_cons_special_reloc
= NULL
;
4828 char *end
= ++input_line_pointer
;
4831 while (! is_end_of_line
[(c
= *end
)])
4845 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4846 sparc_cons_special_reloc
, size
* 8);
4852 if (input_line_pointer
!= end
)
4854 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4855 sparc_cons_special_reloc
, size
* 8);
4859 input_line_pointer
++;
4861 c
= *input_line_pointer
;
4862 if (! is_end_of_line
[c
] && c
!= ',')
4863 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4864 sparc_cons_special_reloc
, size
* 8);
4870 if (sparc_cons_special_reloc
== NULL
)
4872 return sparc_cons_special_reloc
;
4877 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4878 reloc for a cons. We could use the definition there, except that
4879 we want to handle little endian relocs specially. */
4882 cons_fix_new_sparc (fragS
*frag
,
4884 unsigned int nbytes
,
4886 const char *sparc_cons_special_reloc
)
4888 bfd_reloc_code_real_type r
;
4890 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4891 (nbytes
== 2 ? BFD_RELOC_16
:
4892 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4894 if (target_little_endian_data
4896 && now_seg
->flags
& SEC_ALLOC
)
4897 r
= BFD_RELOC_SPARC_REV32
;
4899 if (sparc_cons_special_reloc
)
4901 if (*sparc_cons_special_reloc
== 'd')
4904 case 1: r
= BFD_RELOC_8_PCREL
; break;
4905 case 2: r
= BFD_RELOC_16_PCREL
; break;
4906 case 4: r
= BFD_RELOC_32_PCREL
; break;
4907 case 8: r
= BFD_RELOC_64_PCREL
; break;
4910 else if (*sparc_cons_special_reloc
== 'p')
4913 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4914 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4919 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4920 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4923 else if (sparc_no_align_cons
)
4927 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4928 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4929 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4934 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4938 sparc_cfi_frame_initial_instructions (void)
4940 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4944 sparc_regname_to_dw2regnum (char *regname
)
4954 case 'g': i
= 0; break;
4955 case 'o': i
= 1; break;
4956 case 'l': i
= 2; break;
4957 case 'i': i
= 3; break;
4958 default: i
= -1; break;
4962 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4964 return i
* 8 + regname
[1] - '0';
4966 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4968 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4970 if (regname
[0] == 'f' || regname
[0] == 'r')
4972 unsigned int regnum
;
4974 regnum
= strtoul (regname
+ 1, &q
, 10);
4975 if (q
== NULL
|| *q
)
4977 if (regnum
>= ((regname
[0] == 'f'
4978 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4981 if (regname
[0] == 'f')
4984 if (regnum
>= 64 && (regnum
& 1))
4993 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4995 sparc_no_align_cons
= 1;
4996 emit_expr_with_reloc (exp
, nbytes
, "disp");
4997 sparc_no_align_cons
= 0;