1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static bfd_uint64_t hwcap_seen
;
84 static bfd_uint64_t hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax
;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data
;
106 extern int target_big_endian
;
108 static int target_little_endian_data
;
110 /* Symbols for global registers on v9. */
111 static symbolS
*globals
[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment
;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control
*op_hash
;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons
, 2},
162 {"4byte", s_uacons
, 4},
163 {"8byte", s_uacons
, 8},
164 {"register", s_register
, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars
[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars
[] = "#";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode
;
205 struct nlist
*nlistp
;
209 bfd_reloc_code_real_type reloc
;
212 struct sparc_it the_insn
, set_insn
;
214 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
222 v8plusa
, v9
, v9a
, v9b
, v9_64
};
224 /* Hardware capability sets, used to keep sparc_arch_table easy to
226 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
227 #define HWS_V9 HWS_V8 | HWCAP_POPC
228 #define HWS_VA HWS_V9 | HWCAP_VIS
229 #define HWS_VB HWS_VA | HWCAP_VIS2
230 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
231 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
232 #define HWS_VE HWS_VD \
233 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
234 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
235 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
236 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
237 #define HWS_VM HWS_VV
240 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
241 | HWCAP2_XMPMUL | HWCAP2_XMONT
243 static struct sparc_arch
{
246 enum sparc_arch_types arch_type
;
247 /* Default word size, as specified during configuration.
248 A value of zero means can't be used to specify default architecture. */
249 int default_arch_size
;
250 /* Allowable arg to -A? */
254 } sparc_arch_table
[] = {
255 { "v6", "v6", v6
, 0, 1, 0, 0 },
256 { "v7", "v7", v7
, 0, 1, 0, 0 },
257 { "v8", "v8", v8
, 32, 1, HWS_V8
, 0 },
258 { "v8a", "v8", v8
, 32, 1, HWS_V8
, 0 },
259 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
260 { "sparcvis", "v9a", v9
, 0, 1, HWS_VA
, 0 },
261 { "sparcvis2", "v9b", v9
, 0, 1, HWS_VB
, 0 },
262 { "sparcfmaf", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
, 0 },
263 { "sparcima", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_IMA
, 0 },
264 { "sparcvis3", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
265 { "sparcvis3r", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
267 { "sparc4", "v9b", v9
, 0, 1, HWS_VV
, 0 },
268 { "sparc5", "v9b", v9
, 0, 1, HWS_VM
, HWS2_VM
},
270 { "leon", "leon", leon
, 32, 1, HWS_V8
, 0 },
271 { "sparclet", "sparclet", sparclet
, 32, 1, HWS_V8
, 0 },
272 { "sparclite", "sparclite", sparclite
, 32, 1, HWS_V8
, 0 },
273 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWS_V8
, 0 },
275 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
276 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VA
, 0 },
277 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VB
, 0 },
278 { "v8plusc", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VC
, 0 },
279 { "v8plusd", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VD
, 0 },
280 { "v8pluse", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VE
, 0 },
281 { "v8plusv", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VV
, 0 },
282 { "v8plusm", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VM
, 0 },
284 { "v9", "v9", v9
, 0, 1, HWS_V9
, 0 },
285 { "v9a", "v9a", v9
, 0, 1, HWS_VA
, 0 },
286 { "v9b", "v9b", v9
, 0, 1, HWS_VB
, 0 },
287 { "v9c", "v9b", v9
, 0, 1, HWS_VC
, 0 },
288 { "v9d", "v9b", v9
, 0, 1, HWS_VD
, 0 },
289 { "v9e", "v9b", v9
, 0, 1, HWS_VE
, 0 },
290 { "v9v", "v9b", v9
, 0, 1, HWS_VV
, 0 },
291 { "v9m", "v9b", v9
, 0, 1, HWS_VM
, HWS2_VM
},
293 /* This exists to allow configure.tgt to pass one
294 value to specify both the default machine and default word size. */
295 { "v9-64", "v9", v9
, 64, 0, HWS_V9
, 0 },
296 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
299 /* Variant of default_arch */
300 static enum sparc_arch_types default_arch_type
;
302 static struct sparc_arch
*
303 lookup_arch (char *name
)
305 struct sparc_arch
*sa
;
307 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
308 if (strcmp (sa
->name
, name
) == 0)
310 if (sa
->name
== NULL
)
315 /* Initialize the default opcode arch and word size from the default
316 architecture name. */
319 init_default_arch (void)
321 struct sparc_arch
*sa
= lookup_arch (default_arch
);
324 || sa
->default_arch_size
== 0)
325 as_fatal (_("Invalid default architecture, broken assembler."));
327 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
328 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
329 as_fatal (_("Bad opcode table, broken assembler."));
330 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
332 default_arch_type
= sa
->arch_type
;
335 /* Called by TARGET_FORMAT. */
338 sparc_target_format (void)
340 /* We don't get a chance to initialize anything before we're called,
341 so handle that now. */
342 if (! default_init_p
)
343 init_default_arch ();
347 return "a.out-sparc-netbsd";
350 if (target_big_endian
)
351 return "a.out-sunos-big";
352 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
353 return "a.out-sunos-big";
355 return "a.out-sparc-little";
357 return "a.out-sunos-big";
368 return "coff-sparc-lynx";
375 return "elf32-sparc-vxworks";
379 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
386 * Invocation line includes a switch not recognized by the base assembler.
387 * See if it's a processor-specific option. These are:
390 * Warn on architecture bumps. See also -A.
392 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
393 * Standard 32 bit architectures.
395 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
396 * This used to only mean 64 bits, but properly specifying it
397 * complicated gcc's ASM_SPECs, so now opcode selection is
398 * specified orthogonally to word size (except when specifying
399 * the default, but that is an internal implementation detail).
400 * -Av8plus, -Av8plusa, -Av8plusb
401 * Same as -Av9{,a,b}.
402 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
403 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
405 * -xarch=v9, -xarch=v9a, -xarch=v9b
406 * Same as -Av9{,a,b} -64, for compatibility with Sun's
409 * Select the architecture and possibly the file format.
410 * Instructions or features not supported by the selected
411 * architecture cause fatal errors.
413 * The default is to start at v6, and bump the architecture up
414 * whenever an instruction is seen at a higher level. In 32 bit
415 * environments, v9 is not bumped up to, the user must pass
418 * If -bump is specified, a warning is printing when bumping to
421 * If an architecture is specified, all instructions must match
422 * that architecture. Any higher level instructions are flagged
423 * as errors. Note that in the 32 bit environment specifying
424 * -Av8plus does not automatically create a v8plus object file, a
425 * v9 insn must be seen.
427 * If both an architecture and -bump are specified, the
428 * architecture starts at the specified level, but bumps are
429 * warnings. Note that we can't set `current_architecture' to
430 * the requested level in this case: in the 32 bit environment,
431 * we still must avoid creating v8plus object files unless v9
435 * Bumping between incompatible architectures is always an
436 * error. For example, from sparclite to v9.
440 const char *md_shortopts
= "A:K:VQ:sq";
443 const char *md_shortopts
= "A:k";
445 const char *md_shortopts
= "A:";
448 struct option md_longopts
[] = {
449 #define OPTION_BUMP (OPTION_MD_BASE)
450 {"bump", no_argument
, NULL
, OPTION_BUMP
},
451 #define OPTION_SPARC (OPTION_MD_BASE + 1)
452 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
453 #define OPTION_XARCH (OPTION_MD_BASE + 2)
454 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
456 #define OPTION_32 (OPTION_MD_BASE + 3)
457 {"32", no_argument
, NULL
, OPTION_32
},
458 #define OPTION_64 (OPTION_MD_BASE + 4)
459 {"64", no_argument
, NULL
, OPTION_64
},
460 #define OPTION_TSO (OPTION_MD_BASE + 5)
461 {"TSO", no_argument
, NULL
, OPTION_TSO
},
462 #define OPTION_PSO (OPTION_MD_BASE + 6)
463 {"PSO", no_argument
, NULL
, OPTION_PSO
},
464 #define OPTION_RMO (OPTION_MD_BASE + 7)
465 {"RMO", no_argument
, NULL
, OPTION_RMO
},
467 #ifdef SPARC_BIENDIAN
468 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
469 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
470 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
471 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
473 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
474 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
475 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
476 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
478 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
479 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
480 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
481 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
483 #define OPTION_RELAX (OPTION_MD_BASE + 14)
484 {"relax", no_argument
, NULL
, OPTION_RELAX
},
485 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
486 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
487 {NULL
, no_argument
, NULL
, 0}
490 size_t md_longopts_size
= sizeof (md_longopts
);
493 md_parse_option (int c
, char *arg
)
495 /* We don't get a chance to initialize anything before we're called,
496 so handle that now. */
497 if (! default_init_p
)
498 init_default_arch ();
504 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
509 if (!strncmp (arg
, "v9", 2))
510 md_parse_option (OPTION_64
, NULL
);
513 if (!strncmp (arg
, "v8", 2)
514 || !strncmp (arg
, "v7", 2)
515 || !strncmp (arg
, "v6", 2)
516 || !strcmp (arg
, "sparclet")
517 || !strcmp (arg
, "sparclite")
518 || !strcmp (arg
, "sparc86x"))
519 md_parse_option (OPTION_32
, NULL
);
526 struct sparc_arch
*sa
;
527 enum sparc_opcode_arch_val opcode_arch
;
529 sa
= lookup_arch (arg
);
531 || ! sa
->user_option_p
)
533 if (c
== OPTION_XARCH
)
534 as_bad (_("invalid architecture -xarch=%s"), arg
);
536 as_bad (_("invalid architecture -A%s"), arg
);
540 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
541 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
542 as_fatal (_("Bad opcode table, broken assembler."));
544 if (!architecture_requested
545 || opcode_arch
> max_architecture
)
546 max_architecture
= opcode_arch
;
548 |= (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32) | sa
->hwcap_allowed
;
549 architecture_requested
= 1;
554 /* Ignore -sparc, used by SunOS make default .s.o rule. */
557 case OPTION_ENFORCE_ALIGNED_DATA
:
558 enforce_aligned_data
= 1;
561 #ifdef SPARC_BIENDIAN
562 case OPTION_LITTLE_ENDIAN
:
563 target_big_endian
= 0;
564 if (default_arch_type
!= sparclet
)
565 as_fatal ("This target does not support -EL");
567 case OPTION_LITTLE_ENDIAN_DATA
:
568 target_little_endian_data
= 1;
569 target_big_endian
= 0;
570 if (default_arch_type
!= sparc86x
571 && default_arch_type
!= v9
)
572 as_fatal ("This target does not support --little-endian-data");
574 case OPTION_BIG_ENDIAN
:
575 target_big_endian
= 1;
589 const char **list
, **l
;
591 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
592 list
= bfd_target_list ();
593 for (l
= list
; *l
!= NULL
; l
++)
595 if (sparc_arch_size
== 32)
597 if (CONST_STRNEQ (*l
, "elf32-sparc"))
602 if (CONST_STRNEQ (*l
, "elf64-sparc"))
607 as_fatal (_("No compiled in support for %d bit object file format"),
611 if (sparc_arch_size
== 64
612 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
613 max_architecture
= SPARC_OPCODE_ARCH_V9
;
618 sparc_memory_model
= MM_TSO
;
622 sparc_memory_model
= MM_PSO
;
626 sparc_memory_model
= MM_RMO
;
634 /* Qy - do emit .comment
635 Qn - do not emit .comment. */
639 /* Use .stab instead of .stab.excl. */
643 /* quick -- Native assembler does fewer checks. */
647 if (strcmp (arg
, "PIC") != 0)
648 as_warn (_("Unrecognized option following -K"));
653 case OPTION_NO_UNDECLARED_REGS
:
654 no_undeclared_regs
= 1;
657 case OPTION_UNDECLARED_REGS
:
658 no_undeclared_regs
= 0;
666 case OPTION_NO_RELAX
:
678 md_show_usage (FILE *stream
)
680 const struct sparc_arch
*arch
;
683 /* We don't get a chance to initialize anything before we're called,
684 so handle that now. */
685 if (! default_init_p
)
686 init_default_arch ();
688 fprintf (stream
, _("SPARC options:\n"));
690 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
692 if (!arch
->user_option_p
)
694 if (arch
!= &sparc_arch_table
[0])
695 fprintf (stream
, " | ");
696 if (column
+ strlen (arch
->name
) > 70)
699 fputc ('\n', stream
);
701 column
+= 5 + 2 + strlen (arch
->name
);
702 fprintf (stream
, "-A%s", arch
->name
);
704 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
706 if (!arch
->user_option_p
)
708 fprintf (stream
, " | ");
709 if (column
+ strlen (arch
->name
) > 65)
712 fputc ('\n', stream
);
714 column
+= 5 + 7 + strlen (arch
->name
);
715 fprintf (stream
, "-xarch=%s", arch
->name
);
717 fprintf (stream
, _("\n\
718 specify variant of SPARC architecture\n\
719 -bump warn when assembler switches architectures\n\
721 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
722 -relax relax jumps and branches (default)\n\
723 -no-relax avoid changing any jumps and branches\n"));
725 fprintf (stream
, _("\
726 -k generate PIC\n"));
729 fprintf (stream
, _("\
730 -32 create 32 bit object file\n\
731 -64 create 64 bit object file\n"));
732 fprintf (stream
, _("\
733 [default is %d]\n"), default_arch_size
);
734 fprintf (stream
, _("\
735 -TSO use Total Store Ordering\n\
736 -PSO use Partial Store Ordering\n\
737 -RMO use Relaxed Memory Ordering\n"));
738 fprintf (stream
, _("\
739 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
740 fprintf (stream
, _("\
741 -KPIC generate PIC\n\
742 -V print assembler version number\n\
743 -undeclared-regs ignore application global register usage without\n\
744 appropriate .register directive (default)\n\
745 -no-undeclared-regs force error on application global register usage\n\
746 without appropriate .register directive\n\
751 #ifdef SPARC_BIENDIAN
752 fprintf (stream
, _("\
753 -EL generate code for a little endian machine\n\
754 -EB generate code for a big endian machine\n\
755 --little-endian-data generate code for a machine having big endian\n\
756 instructions and little endian data.\n"));
760 /* Native operand size opcode translation. */
766 } native_op_table
[] =
768 {"ldn", "ld", "ldx"},
769 {"ldna", "lda", "ldxa"},
770 {"stn", "st", "stx"},
771 {"stna", "sta", "stxa"},
772 {"slln", "sll", "sllx"},
773 {"srln", "srl", "srlx"},
774 {"sran", "sra", "srax"},
775 {"casn", "cas", "casx"},
776 {"casna", "casa", "casxa"},
777 {"clrn", "clr", "clrx"},
781 /* sparc64 privileged and hyperprivileged registers. */
783 struct priv_reg_entry
789 struct priv_reg_entry priv_reg_table
[] =
810 {"", -1}, /* End marker. */
813 struct priv_reg_entry hpriv_reg_table
[] =
820 {"hstick_offset", 28},
821 {"hstick_enable", 29},
823 {"", -1}, /* End marker. */
826 /* v9a specific asrs. This table is ordered by initial
827 letter, in reverse. */
829 struct priv_reg_entry v9a_asr_table
[] =
832 {"sys_tick_cmpr", 25},
836 {"softint_clear", 21},
847 {"clear_softint", 21},
848 {"", -1}, /* End marker. */
852 cmp_reg_entry (const void *parg
, const void *qarg
)
854 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
855 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
857 return strcmp (q
->name
, p
->name
);
860 /* This function is called once, at assembler startup time. It should
861 set up all the tables, etc. that the MD part of the assembler will
867 const char *retval
= NULL
;
871 /* We don't get a chance to initialize anything before md_parse_option
872 is called, and it may not be called, so handle default initialization
873 now if not already done. */
874 if (! default_init_p
)
875 init_default_arch ();
877 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
878 op_hash
= hash_new ();
880 while (i
< (unsigned int) sparc_num_opcodes
)
882 const char *name
= sparc_opcodes
[i
].name
;
883 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
886 as_bad (_("Internal error: can't hash `%s': %s\n"),
887 sparc_opcodes
[i
].name
, retval
);
892 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
894 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
895 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
900 while (i
< (unsigned int) sparc_num_opcodes
901 && !strcmp (sparc_opcodes
[i
].name
, name
));
904 for (i
= 0; native_op_table
[i
].name
; i
++)
906 const struct sparc_opcode
*insn
;
907 char *name
= ((sparc_arch_size
== 32)
908 ? native_op_table
[i
].name32
909 : native_op_table
[i
].name64
);
910 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
913 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
914 name
, native_op_table
[i
].name
);
919 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
923 as_bad (_("Internal error: can't hash `%s': %s\n"),
924 sparc_opcodes
[i
].name
, retval
);
931 as_fatal (_("Broken assembler. No assembly attempted."));
933 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
934 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
936 /* If -bump, record the architecture level at which we start issuing
937 warnings. The behaviour is different depending upon whether an
938 architecture was explicitly specified. If it wasn't, we issue warnings
939 for all upwards bumps. If it was, we don't start issuing warnings until
940 we need to bump beyond the requested architecture or when we bump between
941 conflicting architectures. */
944 && architecture_requested
)
946 /* `max_architecture' records the requested architecture.
947 Issue warnings if we go above it. */
948 warn_after_architecture
= max_architecture
;
951 /* Find the highest architecture level that doesn't conflict with
952 the requested one. */
955 || !architecture_requested
)
957 enum sparc_opcode_arch_val current_max_architecture
960 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
961 max_architecture
> warn_after_architecture
;
963 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
964 current_max_architecture
))
969 /* Called after all assembly has been done. */
974 unsigned long mach
= bfd_mach_sparc
;
975 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
979 if (sparc_arch_size
== 64)
980 switch (current_architecture
)
982 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
983 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
984 default: mach
= bfd_mach_sparc_v9
; break;
987 switch (current_architecture
)
989 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
990 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
991 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
992 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
993 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
994 be but for now it is (since that's the way it's always been
998 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1000 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1001 hwcaps
= hwcap_seen
& U0xffffffff
;
1002 hwcaps2
= hwcap_seen
>> 32;
1005 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1007 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1011 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1014 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1018 /* Sign-extend the value from the architecture word size, so that
1019 0xffffffff is always considered -1 on sparc32. */
1020 if (sparc_arch_size
== 32)
1022 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1023 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1032 /* Return non-zero if VAL is in the range 0 to MAX. */
1035 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1042 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1043 (e.g. -15 to +31). */
1046 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1052 if (val
< ~(max
>> 1))
1058 sparc_ffs (unsigned int mask
)
1065 for (i
= 0; (mask
& 1) == 0; ++i
)
1070 /* Implement big shift right. */
1072 BSR (bfd_vma val
, int amount
)
1074 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1075 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1076 return val
>> amount
;
1079 /* For communication between sparc_ip and get_expression. */
1080 static char *expr_end
;
1082 /* Values for `special_case'.
1083 Instructions that require wierd handling because they're longer than
1085 #define SPECIAL_CASE_NONE 0
1086 #define SPECIAL_CASE_SET 1
1087 #define SPECIAL_CASE_SETSW 2
1088 #define SPECIAL_CASE_SETX 3
1089 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1090 #define SPECIAL_CASE_FDIV 4
1092 /* Bit masks of various insns. */
1093 #define NOP_INSN 0x01000000
1094 #define OR_INSN 0x80100000
1095 #define XOR_INSN 0x80180000
1096 #define FMOVS_INSN 0x81A00020
1097 #define SETHI_INSN 0x01000000
1098 #define SLLX_INSN 0x81281000
1099 #define SRA_INSN 0x81380000
1101 /* The last instruction to be assembled. */
1102 static const struct sparc_opcode
*last_insn
;
1103 /* The assembled opcode of `last_insn'. */
1104 static unsigned long last_opcode
;
1106 /* Handle the set and setuw synthetic instructions. */
1109 synthetize_setuw (const struct sparc_opcode
*insn
)
1111 int need_hi22_p
= 0;
1112 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1114 if (the_insn
.exp
.X_op
== O_constant
)
1116 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1118 if (sizeof (offsetT
) > 4
1119 && (the_insn
.exp
.X_add_number
< 0
1120 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1121 as_warn (_("set: number not in 0..4294967295 range"));
1125 if (sizeof (offsetT
) > 4
1126 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1127 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1128 as_warn (_("set: number not in -2147483648..4294967295 range"));
1129 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1133 /* See if operand is absolute and small; skip sethi if so. */
1134 if (the_insn
.exp
.X_op
!= O_constant
1135 || the_insn
.exp
.X_add_number
>= (1 << 12)
1136 || the_insn
.exp
.X_add_number
< -(1 << 12))
1138 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1139 | ((the_insn
.exp
.X_add_number
>> 10)
1140 & (the_insn
.exp
.X_op
== O_constant
1142 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1143 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1144 output_insn (insn
, &the_insn
);
1148 /* See if operand has no low-order bits; skip OR if so. */
1149 if (the_insn
.exp
.X_op
!= O_constant
1150 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1153 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1155 | (the_insn
.exp
.X_add_number
1156 & (the_insn
.exp
.X_op
!= O_constant
1157 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1158 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1159 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1160 output_insn (insn
, &the_insn
);
1164 /* Handle the setsw synthetic instruction. */
1167 synthetize_setsw (const struct sparc_opcode
*insn
)
1171 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1173 if (the_insn
.exp
.X_op
!= O_constant
)
1175 synthetize_setuw (insn
);
1177 /* Need to sign extend it. */
1178 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1179 the_insn
.reloc
= BFD_RELOC_NONE
;
1180 output_insn (insn
, &the_insn
);
1184 if (sizeof (offsetT
) > 4
1185 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1186 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1187 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1189 low32
= the_insn
.exp
.X_add_number
;
1193 synthetize_setuw (insn
);
1199 the_insn
.reloc
= BFD_RELOC_NONE
;
1200 /* See if operand is absolute and small; skip sethi if so. */
1201 if (low32
< -(1 << 12))
1203 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1204 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1205 output_insn (insn
, &the_insn
);
1206 low32
= 0x1c00 | (low32
& 0x3ff);
1207 opc
= RS1 (rd
) | XOR_INSN
;
1210 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1211 | (low32
& 0x1fff));
1212 output_insn (insn
, &the_insn
);
1215 /* Handle the setx synthetic instruction. */
1218 synthetize_setx (const struct sparc_opcode
*insn
)
1220 int upper32
, lower32
;
1221 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1222 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1224 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1225 int need_xor10_p
= 0;
1227 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1228 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1229 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1232 upper_dstreg
= tmpreg
;
1233 /* The tmp reg should not be the dst reg. */
1234 if (tmpreg
== dstreg
)
1235 as_warn (_("setx: temporary register same as destination register"));
1237 /* ??? Obviously there are other optimizations we can do
1238 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1239 doing some of these. Later. If you do change things, try to
1240 change all of this to be table driven as well. */
1241 /* What to output depends on the number if it's constant.
1242 Compute that first, then output what we've decided upon. */
1243 if (the_insn
.exp
.X_op
!= O_constant
)
1245 if (sparc_arch_size
== 32)
1247 /* When arch size is 32, we want setx to be equivalent
1248 to setuw for anything but constants. */
1249 the_insn
.exp
.X_add_number
&= 0xffffffff;
1250 synthetize_setuw (insn
);
1253 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1259 /* Reset X_add_number, we've extracted it as upper32/lower32.
1260 Otherwise fixup_segment will complain about not being able to
1261 write an 8 byte number in a 4 byte field. */
1262 the_insn
.exp
.X_add_number
= 0;
1264 /* Only need hh22 if `or' insn can't handle constant. */
1265 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1268 /* Does bottom part (after sethi) have bits? */
1269 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1270 /* No hh22, but does upper32 still have bits we can't set
1272 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1275 /* If the lower half is all zero, we build the upper half directly
1276 into the dst reg. */
1278 /* Need lower half if number is zero or 0xffffffff00000000. */
1279 || (! need_hh22_p
&& ! need_hm10_p
))
1281 /* No need for sethi if `or' insn can handle constant. */
1282 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1283 /* Note that we can't use a negative constant in the `or'
1284 insn unless the upper 32 bits are all ones. */
1285 || (lower32
< 0 && upper32
!= -1)
1286 || (lower32
>= 0 && upper32
== -1))
1289 if (need_hi22_p
&& upper32
== -1)
1292 /* Does bottom part (after sethi) have bits? */
1293 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1295 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1296 /* Need `or' if we didn't set anything else. */
1297 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1301 /* Output directly to dst reg if lower 32 bits are all zero. */
1302 upper_dstreg
= dstreg
;
1305 if (!upper_dstreg
&& dstreg
)
1306 as_warn (_("setx: illegal temporary register g0"));
1310 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1311 | ((upper32
>> 10) & 0x3fffff));
1312 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1313 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1314 output_insn (insn
, &the_insn
);
1319 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1320 | (((need_xor10_p
? ~lower32
: lower32
)
1321 >> 10) & 0x3fffff));
1322 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1323 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1324 output_insn (insn
, &the_insn
);
1329 the_insn
.opcode
= (OR_INSN
1330 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1333 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1334 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1335 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1336 output_insn (insn
, &the_insn
);
1341 /* FIXME: One nice optimization to do here is to OR the low part
1342 with the highpart if hi22 isn't needed and the low part is
1344 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1347 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1348 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1349 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1350 output_insn (insn
, &the_insn
);
1353 /* If we needed to build the upper part, shift it into place. */
1354 if (need_hh22_p
|| need_hm10_p
)
1356 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1358 the_insn
.reloc
= BFD_RELOC_NONE
;
1359 output_insn (insn
, &the_insn
);
1362 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1365 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1366 | 0x1c00 | (lower32
& 0x3ff));
1367 the_insn
.reloc
= BFD_RELOC_NONE
;
1368 output_insn (insn
, &the_insn
);
1371 /* If we needed to build both upper and lower parts, OR them together. */
1372 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1374 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1376 the_insn
.reloc
= BFD_RELOC_NONE
;
1377 output_insn (insn
, &the_insn
);
1381 /* Main entry point to assemble one instruction. */
1384 md_assemble (char *str
)
1386 const struct sparc_opcode
*insn
;
1390 special_case
= sparc_ip (str
, &insn
);
1394 /* We warn about attempts to put a floating point branch in a delay slot,
1395 unless the delay slot has been annulled. */
1396 if (last_insn
!= NULL
1397 && (insn
->flags
& F_FBR
) != 0
1398 && (last_insn
->flags
& F_DELAYED
) != 0
1399 /* ??? This test isn't completely accurate. We assume anything with
1400 F_{UNBR,CONDBR,FBR} set is annullable. */
1401 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1402 || (last_opcode
& ANNUL
) == 0))
1403 as_warn (_("FP branch in delay slot"));
1405 /* SPARC before v9 requires a nop instruction between a floating
1406 point instruction and a floating point branch. We insert one
1407 automatically, with a warning. */
1408 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1409 && last_insn
!= NULL
1410 && (insn
->flags
& F_FBR
) != 0
1411 && (last_insn
->flags
& F_FLOAT
) != 0)
1413 struct sparc_it nop_insn
;
1415 nop_insn
.opcode
= NOP_INSN
;
1416 nop_insn
.reloc
= BFD_RELOC_NONE
;
1417 output_insn (insn
, &nop_insn
);
1418 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1421 switch (special_case
)
1423 case SPECIAL_CASE_NONE
:
1425 output_insn (insn
, &the_insn
);
1428 case SPECIAL_CASE_SETSW
:
1429 synthetize_setsw (insn
);
1432 case SPECIAL_CASE_SET
:
1433 synthetize_setuw (insn
);
1436 case SPECIAL_CASE_SETX
:
1437 synthetize_setx (insn
);
1440 case SPECIAL_CASE_FDIV
:
1442 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1444 output_insn (insn
, &the_insn
);
1446 /* According to information leaked from Sun, the "fdiv" instructions
1447 on early SPARC machines would produce incorrect results sometimes.
1448 The workaround is to add an fmovs of the destination register to
1449 itself just after the instruction. This was true on machines
1450 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1451 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1452 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1453 output_insn (insn
, &the_insn
);
1458 as_fatal (_("failed special case insn sanity check"));
1463 get_hwcap_name (bfd_uint64_t mask
)
1465 if (mask
& HWCAP_MUL32
)
1467 if (mask
& HWCAP_DIV32
)
1469 if (mask
& HWCAP_FSMULD
)
1471 if (mask
& HWCAP_V8PLUS
)
1473 if (mask
& HWCAP_POPC
)
1475 if (mask
& HWCAP_VIS
)
1477 if (mask
& HWCAP_VIS2
)
1479 if (mask
& HWCAP_ASI_BLK_INIT
)
1480 return "ASIBlkInit";
1481 if (mask
& HWCAP_FMAF
)
1483 if (mask
& HWCAP_VIS3
)
1485 if (mask
& HWCAP_HPC
)
1487 if (mask
& HWCAP_RANDOM
)
1489 if (mask
& HWCAP_TRANS
)
1491 if (mask
& HWCAP_FJFMAU
)
1493 if (mask
& HWCAP_IMA
)
1495 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1497 if (mask
& HWCAP_AES
)
1499 if (mask
& HWCAP_DES
)
1501 if (mask
& HWCAP_KASUMI
)
1503 if (mask
& HWCAP_CAMELLIA
)
1505 if (mask
& HWCAP_MD5
)
1507 if (mask
& HWCAP_SHA1
)
1509 if (mask
& HWCAP_SHA256
)
1511 if (mask
& HWCAP_SHA512
)
1513 if (mask
& HWCAP_MPMUL
)
1515 if (mask
& HWCAP_MONT
)
1517 if (mask
& HWCAP_PAUSE
)
1519 if (mask
& HWCAP_CBCOND
)
1521 if (mask
& HWCAP_CRC32C
)
1525 if (mask
& HWCAP2_FJATHPLUS
)
1527 if (mask
& HWCAP2_VIS3B
)
1529 if (mask
& HWCAP2_ADP
)
1531 if (mask
& HWCAP2_SPARC5
)
1533 if (mask
& HWCAP2_MWAIT
)
1535 if (mask
& HWCAP2_XMPMUL
)
1537 if (mask
& HWCAP2_XMONT
)
1539 if (mask
& HWCAP2_NSEC
)
1545 /* Subroutine of md_assemble to do the actual parsing. */
1548 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1550 char *error_message
= "";
1554 const struct sparc_opcode
*insn
;
1556 unsigned long opcode
;
1557 unsigned int mask
= 0;
1561 int special_case
= SPECIAL_CASE_NONE
;
1568 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1585 as_bad (_("Unknown opcode: `%s'"), str
);
1587 return special_case
;
1589 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1593 as_bad (_("Unknown opcode: `%s'"), str
);
1594 return special_case
;
1604 opcode
= insn
->match
;
1605 memset (&the_insn
, '\0', sizeof (the_insn
));
1606 the_insn
.reloc
= BFD_RELOC_NONE
;
1609 /* Build the opcode, checking as we go to make sure that the
1611 for (args
= insn
->args
;; ++args
)
1619 /* Parse a series of masks. */
1626 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1629 error_message
= _(": invalid membar mask name");
1635 if (*s
== '|' || *s
== '+')
1643 if (! parse_const_expr_arg (&s
, &kmask
))
1645 error_message
= _(": invalid membar mask expression");
1648 if (kmask
< 0 || kmask
> 127)
1650 error_message
= _(": invalid membar mask number");
1655 opcode
|= MEMBAR (kmask
);
1663 if (! parse_const_expr_arg (&s
, &smask
))
1665 error_message
= _(": invalid siam mode expression");
1668 if (smask
< 0 || smask
> 7)
1670 error_message
= _(": invalid siam mode number");
1681 /* Parse a prefetch function. */
1684 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1686 error_message
= _(": invalid prefetch function name");
1692 if (! parse_const_expr_arg (&s
, &fcn
))
1694 error_message
= _(": invalid prefetch function expression");
1697 if (fcn
< 0 || fcn
> 31)
1699 error_message
= _(": invalid prefetch function number");
1709 /* Parse a sparc64 privileged register. */
1712 struct priv_reg_entry
*p
= priv_reg_table
;
1713 unsigned int len
= 9999999; /* Init to make gcc happy. */
1716 while (p
->name
[0] > s
[0])
1718 while (p
->name
[0] == s
[0])
1720 len
= strlen (p
->name
);
1721 if (strncmp (p
->name
, s
, len
) == 0)
1725 if (p
->name
[0] != s
[0])
1727 error_message
= _(": unrecognizable privileged register");
1731 opcode
|= (p
->regnum
<< 14);
1733 opcode
|= (p
->regnum
<< 25);
1739 error_message
= _(": unrecognizable privileged register");
1745 /* Parse a sparc64 hyperprivileged register. */
1748 struct priv_reg_entry
*p
= hpriv_reg_table
;
1749 unsigned int len
= 9999999; /* Init to make gcc happy. */
1752 while (p
->name
[0] > s
[0])
1754 while (p
->name
[0] == s
[0])
1756 len
= strlen (p
->name
);
1757 if (strncmp (p
->name
, s
, len
) == 0)
1761 if (p
->name
[0] != s
[0])
1763 error_message
= _(": unrecognizable hyperprivileged register");
1767 opcode
|= (p
->regnum
<< 14);
1769 opcode
|= (p
->regnum
<< 25);
1775 error_message
= _(": unrecognizable hyperprivileged register");
1781 /* Parse a v9a/v9b ancillary state register. */
1784 struct priv_reg_entry
*p
= v9a_asr_table
;
1785 unsigned int len
= 9999999; /* Init to make gcc happy. */
1788 while (p
->name
[0] > s
[0])
1790 while (p
->name
[0] == s
[0])
1792 len
= strlen (p
->name
);
1793 if (strncmp (p
->name
, s
, len
) == 0)
1797 if (p
->name
[0] != s
[0])
1799 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1802 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1804 error_message
= _(": rd on write only ancillary state register");
1808 && (insn
->architecture
1809 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1811 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1812 error_message
= _(": unrecognizable v9a ancillary state register");
1816 opcode
|= (p
->regnum
<< 14);
1818 opcode
|= (p
->regnum
<< 25);
1824 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1830 if (strncmp (s
, "%asr", 4) == 0)
1838 while (ISDIGIT (*s
))
1840 num
= num
* 10 + *s
- '0';
1844 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1846 if (num
< 16 || 31 < num
)
1848 error_message
= _(": asr number must be between 16 and 31");
1854 if (num
< 0 || 31 < num
)
1856 error_message
= _(": asr number must be between 0 and 31");
1861 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1866 error_message
= _(": expecting %asrN");
1873 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1877 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1883 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
1888 if (s
[0] == '0' && s
[1] == 'x')
1891 while (ISXDIGIT (*s
))
1894 num
|= hex_value (*s
);
1900 while (ISDIGIT (*s
))
1902 num
= num
* 10 + *s
- '0';
1906 if (num
< 0 || num
> 31)
1908 error_message
= _(": crypto immediate must be between 0 and 31");
1912 opcode
|= RS3 (num
);
1917 error_message
= _(": expecting crypto immediate");
1922 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1923 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1924 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1926 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1927 /* These fields are unsigned, but for upward compatibility,
1928 allow negative values as well. */
1932 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1933 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1934 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1936 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1937 /* These fields are unsigned, but for upward compatibility,
1938 allow negative values as well. */
1942 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1947 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
1952 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1957 if (*s
== 'p' && s
[1] == 'n')
1965 if (*s
== 'p' && s
[1] == 't')
1977 if ((strncmp (s
, "%icc", 4) == 0)
1978 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
1990 if ((strncmp (s
, "%xcc", 4) == 0)
1991 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2003 if (strncmp (s
, "%fcc0", 5) == 0)
2015 if (strncmp (s
, "%fcc1", 5) == 0)
2027 if (strncmp (s
, "%fcc2", 5) == 0)
2039 if (strncmp (s
, "%fcc3", 5) == 0)
2047 if (strncmp (s
, "%pc", 3) == 0)
2055 if (strncmp (s
, "%tick", 5) == 0)
2062 case '\0': /* End of args. */
2063 if (s
[0] == ',' && s
[1] == '%')
2065 static const struct ops
2067 /* The name as it appears in assembler. */
2069 /* strlen (name), precomputed for speed */
2071 /* The reloc this pseudo-op translates to. */
2073 /* 1 if tls call. */
2078 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
2079 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
2080 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
2081 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
2082 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
2083 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
2084 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
2085 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
2086 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
2089 const struct ops
*o
;
2093 for (o
= ops
; o
->name
; o
++)
2094 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
2096 if (o
->name
== NULL
)
2099 if (s
[o
->len
+ 2] != '(')
2101 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2102 return special_case
;
2105 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
2107 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2109 return special_case
;
2113 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2114 || the_insn
.exp
.X_add_number
!= 0
2115 || the_insn
.exp
.X_add_symbol
2116 != symbol_find_or_make ("__tls_get_addr")))
2118 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2120 return special_case
;
2123 the_insn
.reloc
= o
->reloc
;
2124 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2127 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2130 else if (*s1
== ')')
2139 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2140 return special_case
;
2144 (void) get_expression (s
);
2164 case '[': /* These must match exactly. */
2172 case '#': /* Must be at least one digit. */
2175 while (ISDIGIT (*s
))
2183 case 'C': /* Coprocessor state register. */
2184 if (strncmp (s
, "%csr", 4) == 0)
2191 case 'b': /* Next operand is a coprocessor register. */
2194 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2199 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2213 opcode
|= mask
<< 14;
2221 opcode
|= mask
<< 25;
2227 case 'r': /* next operand must be a register */
2237 case 'f': /* frame pointer */
2245 case 'g': /* global register */
2254 case 'i': /* in register */
2258 mask
= c
- '0' + 24;
2263 case 'l': /* local register */
2267 mask
= (c
- '0' + 16);
2272 case 'o': /* out register */
2276 mask
= (c
- '0' + 8);
2281 case 's': /* stack pointer */
2289 case 'r': /* any register */
2290 if (!ISDIGIT ((c
= *s
++)))
2307 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2323 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2324 && no_undeclared_regs
&& ! globals
[mask
])
2325 as_bad (_("detected global register use not covered by .register pseudo-op"));
2327 /* Got the register, now figure out where
2328 it goes in the opcode. */
2332 opcode
|= mask
<< 14;
2340 opcode
|= mask
<< 25;
2344 opcode
|= (mask
<< 25) | (mask
<< 14);
2348 opcode
|= (mask
<< 25) | (mask
<< 0);
2354 case 'e': /* next operand is a floating point register */
2373 && ((format
= *s
) == 'f')
2376 for (mask
= 0; ISDIGIT (*s
); ++s
)
2378 mask
= 10 * mask
+ (*s
- '0');
2379 } /* read the number */
2388 } /* register must be even numbered */
2396 } /* register must be multiple of 4 */
2400 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2401 error_message
= _(": There are only 64 f registers; [0-63]");
2403 error_message
= _(": There are only 32 f registers; [0-31]");
2406 else if (mask
>= 32)
2408 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2410 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2413 = _(": There are only 32 single precision f registers; [0-31]");
2417 mask
-= 31; /* wrap high bit */
2421 error_message
= _(": There are only 32 f registers; [0-31]");
2429 } /* if not an 'f' register. */
2431 if (*args
== '}' && mask
!= RS2 (opcode
))
2434 = _(": Instruction requires frs2 and frsd must be the same register");
2443 opcode
|= RS1 (mask
);
2449 opcode
|= RS2 (mask
);
2454 opcode
|= RS3 (mask
);
2461 opcode
|= RD (mask
);
2470 if (strncmp (s
, "%fsr", 4) == 0)
2478 if (strncmp (s
, "%efsr", 5) == 0)
2485 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2486 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2489 case 'l': /* 22 bit PC relative immediate */
2490 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2494 case 'L': /* 30 bit immediate */
2495 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2500 case 'n': /* 22 bit immediate */
2501 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2504 case 'i': /* 13 bit immediate */
2505 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2515 char *op_arg
= NULL
;
2516 static expressionS op_exp
;
2517 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2519 /* Check for %hi, etc. */
2522 static const struct ops
{
2523 /* The name as it appears in assembler. */
2525 /* strlen (name), precomputed for speed */
2527 /* The reloc this pseudo-op translates to. */
2529 /* Non-zero if for v9 only. */
2531 /* Non-zero if can be used in pc-relative contexts. */
2532 int pcrel_p
;/*FIXME:wip*/
2534 /* hix/lox must appear before hi/lo so %hix won't be
2535 mistaken for %hi. */
2536 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2537 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2538 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2539 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2540 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2541 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2542 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2543 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2544 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2545 { "h34", 3, BFD_RELOC_SPARC_H34
, 1, 0 },
2546 { "l34", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2547 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2548 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2549 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2550 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2551 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2552 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2553 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2554 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2555 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2556 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2558 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2560 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2561 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2562 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2563 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2564 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2566 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2568 { NULL
, 0, 0, 0, 0 }
2570 const struct ops
*o
;
2572 for (o
= ops
; o
->name
; o
++)
2573 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2575 if (o
->name
== NULL
)
2578 if (s
[o
->len
+ 1] != '(')
2580 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2581 return special_case
;
2585 the_insn
.reloc
= o
->reloc
;
2590 /* Note that if the get_expression() fails, we will still
2591 have created U entries in the symbol table for the
2592 'symbols' in the input string. Try not to create U
2593 symbols for registers, etc. */
2595 /* This stuff checks to see if the expression ends in
2596 +%reg. If it does, it removes the register from
2597 the expression, and re-sets 's' to point to the
2604 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2607 else if (*s1
== ')')
2616 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2617 return special_case
;
2621 (void) get_expression (s
);
2624 if (*s
== ',' || *s
== ']' || !*s
)
2626 if (*s
!= '+' && *s
!= '-')
2628 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2629 return special_case
;
2633 op_exp
= the_insn
.exp
;
2634 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2637 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2640 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2642 if (s1
[-2] == '%' && s1
[-3] == '+')
2644 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2646 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2653 if (op_arg
&& s1
== s
+ 1)
2654 the_insn
.exp
.X_op
= O_absent
;
2656 (void) get_expression (s
);
2668 (void) get_expression (s
);
2676 the_insn
.exp2
= the_insn
.exp
;
2677 the_insn
.exp
= op_exp
;
2678 if (the_insn
.exp2
.X_op
== O_absent
)
2679 the_insn
.exp2
.X_op
= O_illegal
;
2680 else if (the_insn
.exp
.X_op
== O_absent
)
2682 the_insn
.exp
= the_insn
.exp2
;
2683 the_insn
.exp2
.X_op
= O_illegal
;
2685 else if (the_insn
.exp
.X_op
== O_constant
)
2687 valueT val
= the_insn
.exp
.X_add_number
;
2688 switch (the_insn
.reloc
)
2693 case BFD_RELOC_SPARC_HH22
:
2694 val
= BSR (val
, 32);
2697 case BFD_RELOC_SPARC_LM22
:
2698 case BFD_RELOC_HI22
:
2699 val
= (val
>> 10) & 0x3fffff;
2702 case BFD_RELOC_SPARC_HM10
:
2703 val
= BSR (val
, 32);
2706 case BFD_RELOC_LO10
:
2710 case BFD_RELOC_SPARC_H34
:
2715 case BFD_RELOC_SPARC_H44
:
2720 case BFD_RELOC_SPARC_M44
:
2725 case BFD_RELOC_SPARC_L44
:
2729 case BFD_RELOC_SPARC_HIX22
:
2731 val
= (val
>> 10) & 0x3fffff;
2734 case BFD_RELOC_SPARC_LOX10
:
2735 val
= (val
& 0x3ff) | 0x1c00;
2738 the_insn
.exp
= the_insn
.exp2
;
2739 the_insn
.exp
.X_add_number
+= val
;
2740 the_insn
.exp2
.X_op
= O_illegal
;
2741 the_insn
.reloc
= old_reloc
;
2743 else if (the_insn
.exp2
.X_op
!= O_constant
)
2745 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2746 return special_case
;
2750 if (old_reloc
!= BFD_RELOC_SPARC13
2751 || the_insn
.reloc
!= BFD_RELOC_LO10
2752 || sparc_arch_size
!= 64
2755 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2756 return special_case
;
2758 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2762 /* Check for constants that don't require emitting a reloc. */
2763 if (the_insn
.exp
.X_op
== O_constant
2764 && the_insn
.exp
.X_add_symbol
== 0
2765 && the_insn
.exp
.X_op_symbol
== 0)
2767 /* For pc-relative call instructions, we reject
2768 constants to get better code. */
2770 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2771 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2773 error_message
= _(": PC-relative operand can't be a constant");
2777 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2778 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2780 error_message
= _(": TLS operand can't be a constant");
2784 /* Constants that won't fit are checked in md_apply_fix
2785 and bfd_install_relocation.
2786 ??? It would be preferable to install the constants
2787 into the insn here and save having to create a fixS
2788 for each one. There already exists code to handle
2789 all the various cases (e.g. in md_apply_fix and
2790 bfd_install_relocation) so duplicating all that code
2791 here isn't right. */
2793 /* This is a special case to handle cbcond instructions
2794 properly, which can need two relocations. The first
2795 one is for the 5-bit immediate field and the latter
2796 is going to be for the WDISP10 branch part. We
2797 handle the R_SPARC_5 immediate directly here so that
2798 we don't need to add support for multiple relocations
2799 in one instruction just yet. */
2800 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2802 valueT val
= the_insn
.exp
.X_add_number
;
2804 if (! in_bitfield_range (val
, 0x1f))
2806 error_message
= _(": Immediate value in cbcond is out of range.");
2809 opcode
|= val
& 0x1f;
2810 the_insn
.reloc
= BFD_RELOC_NONE
;
2831 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2833 error_message
= _(": invalid ASI name");
2839 if (! parse_const_expr_arg (&s
, &asi
))
2841 error_message
= _(": invalid ASI expression");
2844 if (asi
< 0 || asi
> 255)
2846 error_message
= _(": invalid ASI number");
2850 opcode
|= ASI (asi
);
2852 } /* Alternate space. */
2855 if (strncmp (s
, "%psr", 4) == 0)
2862 case 'q': /* Floating point queue. */
2863 if (strncmp (s
, "%fq", 3) == 0)
2870 case 'Q': /* Coprocessor queue. */
2871 if (strncmp (s
, "%cq", 3) == 0)
2879 if (strcmp (str
, "set") == 0
2880 || strcmp (str
, "setuw") == 0)
2882 special_case
= SPECIAL_CASE_SET
;
2885 else if (strcmp (str
, "setsw") == 0)
2887 special_case
= SPECIAL_CASE_SETSW
;
2890 else if (strcmp (str
, "setx") == 0)
2892 special_case
= SPECIAL_CASE_SETX
;
2895 else if (strncmp (str
, "fdiv", 4) == 0)
2897 special_case
= SPECIAL_CASE_FDIV
;
2903 if (strncmp (s
, "%asi", 4) != 0)
2909 if (strncmp (s
, "%fprs", 5) != 0)
2915 if (strncmp (s
, "%mcdper",7) != 0)
2921 if (strncmp (s
, "%ccr", 4) != 0)
2927 if (strncmp (s
, "%tbr", 4) != 0)
2933 if (strncmp (s
, "%wim", 4) != 0)
2940 char *push
= input_line_pointer
;
2943 input_line_pointer
= s
;
2945 if (e
.X_op
== O_constant
)
2947 int n
= e
.X_add_number
;
2948 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2949 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2951 opcode
|= e
.X_add_number
<< 5;
2954 as_bad (_("non-immediate OPF operand, ignored"));
2955 s
= input_line_pointer
;
2956 input_line_pointer
= push
;
2961 if (strncmp (s
, "%y", 2) != 0)
2969 /* Parse a sparclet cpreg. */
2971 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2973 error_message
= _(": invalid cpreg name");
2976 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2981 as_fatal (_("failed sanity check."));
2982 } /* switch on arg code. */
2984 /* Break out of for() loop. */
2986 } /* For each arg that we expect. */
2991 /* Args don't match. */
2992 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2993 && (insn
->name
== insn
[1].name
2994 || !strcmp (insn
->name
, insn
[1].name
)))
3002 as_bad (_("Illegal operands%s"), error_message
);
3003 return special_case
;
3008 /* We have a match. Now see if the architecture is OK. */
3009 int needed_arch_mask
= insn
->architecture
;
3011 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3013 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3015 hwcap_seen
|= hwcaps
;
3020 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3021 if (! needed_arch_mask
)
3023 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3026 if (needed_arch_mask
3027 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3030 /* Can we bump up the architecture? */
3031 else if (needed_arch_mask
3032 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3034 enum sparc_opcode_arch_val needed_architecture
=
3035 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3036 & needed_arch_mask
);
3038 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3040 && needed_architecture
> warn_after_architecture
)
3042 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3043 sparc_opcode_archs
[current_architecture
].name
,
3044 sparc_opcode_archs
[needed_architecture
].name
,
3046 warn_after_architecture
= needed_architecture
;
3048 current_architecture
= needed_architecture
;
3049 hwcap_allowed
|= hwcaps
;
3052 /* ??? This seems to be a bit fragile. What if the next entry in
3053 the opcode table is the one we want and it is supported?
3054 It is possible to arrange the table today so that this can't
3055 happen but what about tomorrow? */
3058 int arch
, printed_one_p
= 0;
3060 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3062 /* Create a list of the architectures that support the insn. */
3063 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3065 arch
= sparc_ffs (needed_arch_mask
);
3066 while ((1 << arch
) <= needed_arch_mask
)
3068 if ((1 << arch
) & needed_arch_mask
)
3072 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3079 as_bad (_("Architecture mismatch on \"%s\"."), str
);
3080 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
3082 sparc_opcode_archs
[max_architecture
].name
);
3083 return special_case
;
3086 /* Make sure the hwcaps used by the instruction are
3087 currently enabled. */
3088 if (hwcaps
& ~hwcap_allowed
)
3090 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3092 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3094 return special_case
;
3096 } /* If no match. */
3099 } /* Forever looking for a match. */
3101 the_insn
.opcode
= opcode
;
3102 return special_case
;
3105 /* Parse an argument that can be expressed as a keyword.
3106 (eg: #StoreStore or %ccfr).
3107 The result is a boolean indicating success.
3108 If successful, INPUT_POINTER is updated. */
3111 parse_keyword_arg (int (*lookup_fn
) (const char *),
3112 char **input_pointerP
,
3118 p
= *input_pointerP
;
3119 for (q
= p
+ (*p
== '#' || *p
== '%');
3120 ISALNUM (*q
) || *q
== '_';
3125 value
= (*lookup_fn
) (p
);
3130 *input_pointerP
= q
;
3134 /* Parse an argument that is a constant expression.
3135 The result is a boolean indicating success. */
3138 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3140 char *save
= input_line_pointer
;
3143 input_line_pointer
= *input_pointerP
;
3144 /* The next expression may be something other than a constant
3145 (say if we're not processing the right variant of the insn).
3146 Don't call expression unless we're sure it will succeed as it will
3147 signal an error (which we want to defer until later). */
3148 /* FIXME: It might be better to define md_operand and have it recognize
3149 things like %asi, etc. but continuing that route through to the end
3150 is a lot of work. */
3151 if (*input_line_pointer
== '%')
3153 input_line_pointer
= save
;
3157 *input_pointerP
= input_line_pointer
;
3158 input_line_pointer
= save
;
3159 if (exp
.X_op
!= O_constant
)
3161 *valueP
= exp
.X_add_number
;
3165 /* Subroutine of sparc_ip to parse an expression. */
3168 get_expression (char *str
)
3173 save_in
= input_line_pointer
;
3174 input_line_pointer
= str
;
3175 seg
= expression (&the_insn
.exp
);
3176 if (seg
!= absolute_section
3177 && seg
!= text_section
3178 && seg
!= data_section
3179 && seg
!= bss_section
3180 && seg
!= undefined_section
)
3182 the_insn
.error
= _("bad segment");
3183 expr_end
= input_line_pointer
;
3184 input_line_pointer
= save_in
;
3187 expr_end
= input_line_pointer
;
3188 input_line_pointer
= save_in
;
3192 /* Subroutine of md_assemble to output one insn. */
3195 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3197 char *toP
= frag_more (4);
3199 /* Put out the opcode. */
3200 if (INSN_BIG_ENDIAN
)
3201 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3203 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3205 /* Put out the symbol-dependent stuff. */
3206 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3208 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3209 (toP
- frag_now
->fr_literal
), /* Where. */
3214 /* Turn off overflow checking in fixup_segment. We'll do our
3215 own overflow checking in md_apply_fix. This is necessary because
3216 the insn size is 4 and fixup_segment will signal an overflow for
3217 large 8 byte quantities. */
3218 fixP
->fx_no_overflow
= 1;
3219 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3220 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3224 last_opcode
= theinsn
->opcode
;
3227 dwarf2_emit_insn (4);
3232 md_atof (int type
, char *litP
, int *sizeP
)
3234 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3237 /* Write a value out to the object file, using the appropriate
3241 md_number_to_chars (char *buf
, valueT val
, int n
)
3243 if (target_big_endian
)
3244 number_to_chars_bigendian (buf
, val
, n
);
3245 else if (target_little_endian_data
3246 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3247 /* Output debug words, which are not in allocated sections, as big
3249 number_to_chars_bigendian (buf
, val
, n
);
3250 else if (target_little_endian_data
|| ! target_big_endian
)
3251 number_to_chars_littleendian (buf
, val
, n
);
3254 /* Apply a fixS to the frags, now that we know the value it ought to
3258 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3260 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3261 offsetT val
= * (offsetT
*) valP
;
3264 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3266 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3269 /* SPARC ELF relocations don't use an addend in the data field. */
3270 if (fixP
->fx_addsy
!= NULL
)
3272 switch (fixP
->fx_r_type
)
3274 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3275 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3276 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3277 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3278 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3279 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3280 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3281 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3282 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3283 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3284 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3285 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3286 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3287 case BFD_RELOC_SPARC_TLS_IE_LD
:
3288 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3289 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3290 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3291 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3292 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3293 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3294 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3295 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3296 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3297 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3298 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3308 /* This is a hack. There should be a better way to
3309 handle this. Probably in terms of howto fields, once
3310 we can look at these fixups in terms of howtos. */
3311 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3312 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3315 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3316 generate a reloc, then we just want to let the reloc addend set
3317 the value. We do not want to also stuff the addend into the
3318 object file. Including the addend in the object file works when
3319 doing a static link, because the linker will ignore the object
3320 file contents. However, the dynamic linker does not ignore the
3321 object file contents. */
3322 if (fixP
->fx_addsy
!= NULL
3323 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3326 /* When generating PIC code, we do not want an addend for a reloc
3327 against a local symbol. We adjust fx_addnumber to cancel out the
3328 value already included in val, and to also cancel out the
3329 adjustment which bfd_install_relocation will create. */
3331 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3332 && fixP
->fx_addsy
!= NULL
3333 && ! S_IS_COMMON (fixP
->fx_addsy
)
3334 && symbol_section_p (fixP
->fx_addsy
))
3335 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3337 /* When generating PIC code, we need to fiddle to get
3338 bfd_install_relocation to do the right thing for a PC relative
3339 reloc against a local symbol which we are going to keep. */
3341 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3342 && fixP
->fx_addsy
!= NULL
3343 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3344 || S_IS_WEAK (fixP
->fx_addsy
))
3345 && S_IS_DEFINED (fixP
->fx_addsy
)
3346 && ! S_IS_COMMON (fixP
->fx_addsy
))
3349 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3353 /* If this is a data relocation, just output VAL. */
3355 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3357 md_number_to_chars (buf
, val
, 1);
3359 else if (fixP
->fx_r_type
== BFD_RELOC_16
3360 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3362 md_number_to_chars (buf
, val
, 2);
3364 else if (fixP
->fx_r_type
== BFD_RELOC_32
3365 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3366 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3368 md_number_to_chars (buf
, val
, 4);
3370 else if (fixP
->fx_r_type
== BFD_RELOC_64
3371 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3373 md_number_to_chars (buf
, val
, 8);
3375 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3376 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3383 /* It's a relocation against an instruction. */
3385 if (INSN_BIG_ENDIAN
)
3386 insn
= bfd_getb32 ((unsigned char *) buf
);
3388 insn
= bfd_getl32 ((unsigned char *) buf
);
3390 switch (fixP
->fx_r_type
)
3392 case BFD_RELOC_32_PCREL_S2
:
3394 /* FIXME: This increment-by-one deserves a comment of why it's
3396 if (! sparc_pic_code
3397 || fixP
->fx_addsy
== NULL
3398 || symbol_section_p (fixP
->fx_addsy
))
3401 insn
|= val
& 0x3fffffff;
3403 /* See if we have a delay slot. */
3404 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3408 #define XCC (2 << 20)
3409 #define COND(x) (((x)&0xf)<<25)
3410 #define CONDA COND(0x8)
3411 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3412 #define INSN_BA (F2(0,2) | CONDA)
3413 #define INSN_OR F3(2, 0x2, 0)
3414 #define INSN_NOP F2(0,4)
3418 /* If the instruction is a call with either:
3420 arithmetic instruction with rd == %o7
3421 where rs1 != %o7 and rs2 if it is register != %o7
3422 then we can optimize if the call destination is near
3423 by changing the call into a branch always. */
3424 if (INSN_BIG_ENDIAN
)
3425 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3427 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3428 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3430 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3431 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3432 || ((delay
& RD (~0)) != RD (O7
))))
3434 if ((delay
& RS1 (~0)) == RS1 (O7
)
3435 || ((delay
& F3I (~0)) == 0
3436 && (delay
& RS2 (~0)) == RS2 (O7
)))
3438 /* Ensure the branch will fit into simm22. */
3439 if ((val
& 0x3fe00000)
3440 && (val
& 0x3fe00000) != 0x3fe00000)
3442 /* Check if the arch is v9 and branch will fit
3444 if (((val
& 0x3c0000) == 0
3445 || (val
& 0x3c0000) == 0x3c0000)
3446 && (sparc_arch_size
== 64
3447 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3449 insn
= INSN_BPA
| (val
& 0x7ffff);
3452 insn
= INSN_BA
| (val
& 0x3fffff);
3453 if (fixP
->fx_where
>= 4
3454 && ((delay
& (0xffffffff ^ RS1 (~0)))
3455 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3460 if (INSN_BIG_ENDIAN
)
3461 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3463 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3464 if ((setter
& (0xffffffff ^ RD (~0)))
3465 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3472 If call foo was replaced with ba, replace
3473 or %rN, %g0, %o7 with nop. */
3474 reg
= (delay
& RS1 (~0)) >> 14;
3475 if (reg
!= ((setter
& RD (~0)) >> 25)
3476 || reg
== G0
|| reg
== O7
)
3479 if (INSN_BIG_ENDIAN
)
3480 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3482 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3487 case BFD_RELOC_SPARC_11
:
3488 if (! in_signed_range (val
, 0x7ff))
3489 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3490 _("relocation overflow"));
3491 insn
|= val
& 0x7ff;
3494 case BFD_RELOC_SPARC_10
:
3495 if (! in_signed_range (val
, 0x3ff))
3496 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3497 _("relocation overflow"));
3498 insn
|= val
& 0x3ff;
3501 case BFD_RELOC_SPARC_7
:
3502 if (! in_bitfield_range (val
, 0x7f))
3503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3504 _("relocation overflow"));
3508 case BFD_RELOC_SPARC_6
:
3509 if (! in_bitfield_range (val
, 0x3f))
3510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3511 _("relocation overflow"));
3515 case BFD_RELOC_SPARC_5
:
3516 if (! in_bitfield_range (val
, 0x1f))
3517 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3518 _("relocation overflow"));
3522 case BFD_RELOC_SPARC_WDISP10
:
3525 || val
<= -(offsetT
) 0x808)
3526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3527 _("relocation overflow"));
3528 /* FIXME: The +1 deserves a comment. */
3529 val
= (val
>> 2) + 1;
3530 insn
|= ((val
& 0x300) << 11)
3531 | ((val
& 0xff) << 5);
3534 case BFD_RELOC_SPARC_WDISP16
:
3537 || val
<= -(offsetT
) 0x20008)
3538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3539 _("relocation overflow"));
3540 /* FIXME: The +1 deserves a comment. */
3541 val
= (val
>> 2) + 1;
3542 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3545 case BFD_RELOC_SPARC_WDISP19
:
3548 || val
<= -(offsetT
) 0x100008)
3549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3550 _("relocation overflow"));
3551 /* FIXME: The +1 deserves a comment. */
3552 val
= (val
>> 2) + 1;
3553 insn
|= val
& 0x7ffff;
3556 case BFD_RELOC_SPARC_HH22
:
3557 val
= BSR (val
, 32);
3560 case BFD_RELOC_SPARC_LM22
:
3561 case BFD_RELOC_HI22
:
3562 if (!fixP
->fx_addsy
)
3563 insn
|= (val
>> 10) & 0x3fffff;
3565 /* FIXME: Need comment explaining why we do this. */
3569 case BFD_RELOC_SPARC22
:
3570 if (val
& ~0x003fffff)
3571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3572 _("relocation overflow"));
3573 insn
|= (val
& 0x3fffff);
3576 case BFD_RELOC_SPARC_HM10
:
3577 val
= BSR (val
, 32);
3580 case BFD_RELOC_LO10
:
3581 if (!fixP
->fx_addsy
)
3582 insn
|= val
& 0x3ff;
3584 /* FIXME: Need comment explaining why we do this. */
3588 case BFD_RELOC_SPARC_OLO10
:
3590 val
+= fixP
->tc_fix_data
;
3593 case BFD_RELOC_SPARC13
:
3594 if (! in_signed_range (val
, 0x1fff))
3595 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3596 _("relocation overflow"));
3597 insn
|= val
& 0x1fff;
3600 case BFD_RELOC_SPARC_WDISP22
:
3601 val
= (val
>> 2) + 1;
3603 case BFD_RELOC_SPARC_BASE22
:
3604 insn
|= val
& 0x3fffff;
3607 case BFD_RELOC_SPARC_H34
:
3608 if (!fixP
->fx_addsy
)
3612 insn
|= tval
& 0x3fffff;
3616 case BFD_RELOC_SPARC_H44
:
3617 if (!fixP
->fx_addsy
)
3621 insn
|= tval
& 0x3fffff;
3625 case BFD_RELOC_SPARC_M44
:
3626 if (!fixP
->fx_addsy
)
3627 insn
|= (val
>> 12) & 0x3ff;
3630 case BFD_RELOC_SPARC_L44
:
3631 if (!fixP
->fx_addsy
)
3632 insn
|= val
& 0xfff;
3635 case BFD_RELOC_SPARC_HIX22
:
3636 if (!fixP
->fx_addsy
)
3638 val
^= ~(offsetT
) 0;
3639 insn
|= (val
>> 10) & 0x3fffff;
3643 case BFD_RELOC_SPARC_LOX10
:
3644 if (!fixP
->fx_addsy
)
3645 insn
|= 0x1c00 | (val
& 0x3ff);
3648 case BFD_RELOC_NONE
:
3650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3651 _("bad or unhandled relocation type: 0x%02x"),
3656 if (INSN_BIG_ENDIAN
)
3657 bfd_putb32 (insn
, (unsigned char *) buf
);
3659 bfd_putl32 (insn
, (unsigned char *) buf
);
3662 /* Are we finished with this relocation now? */
3663 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3667 /* Translate internal representation of relocation info to BFD target
3671 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3673 static arelent
*relocs
[3];
3675 bfd_reloc_code_real_type code
;
3677 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3680 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3681 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3682 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3684 switch (fixp
->fx_r_type
)
3688 case BFD_RELOC_HI22
:
3689 case BFD_RELOC_LO10
:
3690 case BFD_RELOC_32_PCREL_S2
:
3691 case BFD_RELOC_SPARC13
:
3692 case BFD_RELOC_SPARC22
:
3693 case BFD_RELOC_SPARC_PC22
:
3694 case BFD_RELOC_SPARC_PC10
:
3695 case BFD_RELOC_SPARC_BASE13
:
3696 case BFD_RELOC_SPARC_WDISP10
:
3697 case BFD_RELOC_SPARC_WDISP16
:
3698 case BFD_RELOC_SPARC_WDISP19
:
3699 case BFD_RELOC_SPARC_WDISP22
:
3701 case BFD_RELOC_SPARC_5
:
3702 case BFD_RELOC_SPARC_6
:
3703 case BFD_RELOC_SPARC_7
:
3704 case BFD_RELOC_SPARC_10
:
3705 case BFD_RELOC_SPARC_11
:
3706 case BFD_RELOC_SPARC_HH22
:
3707 case BFD_RELOC_SPARC_HM10
:
3708 case BFD_RELOC_SPARC_LM22
:
3709 case BFD_RELOC_SPARC_PC_HH22
:
3710 case BFD_RELOC_SPARC_PC_HM10
:
3711 case BFD_RELOC_SPARC_PC_LM22
:
3712 case BFD_RELOC_SPARC_H34
:
3713 case BFD_RELOC_SPARC_H44
:
3714 case BFD_RELOC_SPARC_M44
:
3715 case BFD_RELOC_SPARC_L44
:
3716 case BFD_RELOC_SPARC_HIX22
:
3717 case BFD_RELOC_SPARC_LOX10
:
3718 case BFD_RELOC_SPARC_REV32
:
3719 case BFD_RELOC_SPARC_OLO10
:
3720 case BFD_RELOC_SPARC_UA16
:
3721 case BFD_RELOC_SPARC_UA32
:
3722 case BFD_RELOC_SPARC_UA64
:
3723 case BFD_RELOC_8_PCREL
:
3724 case BFD_RELOC_16_PCREL
:
3725 case BFD_RELOC_32_PCREL
:
3726 case BFD_RELOC_64_PCREL
:
3727 case BFD_RELOC_SPARC_PLT32
:
3728 case BFD_RELOC_SPARC_PLT64
:
3729 case BFD_RELOC_VTABLE_ENTRY
:
3730 case BFD_RELOC_VTABLE_INHERIT
:
3731 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3732 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3733 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3734 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3735 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3736 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3737 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3738 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3739 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3740 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3741 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3742 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3743 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3744 case BFD_RELOC_SPARC_TLS_IE_LD
:
3745 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3746 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3747 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3748 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3749 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3750 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3751 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3752 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3753 case BFD_RELOC_SPARC_GOTDATA_OP
:
3754 code
= fixp
->fx_r_type
;
3761 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3762 /* If we are generating PIC code, we need to generate a different
3766 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3768 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3771 #define GOTT_BASE "__GOTT_BASE__"
3772 #define GOTT_INDEX "__GOTT_INDEX__"
3775 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3781 case BFD_RELOC_32_PCREL_S2
:
3782 if (generic_force_reloc (fixp
))
3783 code
= BFD_RELOC_SPARC_WPLT30
;
3785 case BFD_RELOC_HI22
:
3786 code
= BFD_RELOC_SPARC_GOT22
;
3787 if (fixp
->fx_addsy
!= NULL
)
3789 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3790 code
= BFD_RELOC_SPARC_PC22
;
3792 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3793 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3794 code
= BFD_RELOC_HI22
; /* Unchanged. */
3798 case BFD_RELOC_LO10
:
3799 code
= BFD_RELOC_SPARC_GOT10
;
3800 if (fixp
->fx_addsy
!= NULL
)
3802 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3803 code
= BFD_RELOC_SPARC_PC10
;
3805 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3806 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3807 code
= BFD_RELOC_LO10
; /* Unchanged. */
3811 case BFD_RELOC_SPARC13
:
3812 code
= BFD_RELOC_SPARC_GOT13
;
3818 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3820 /* Nothing is aligned in DWARF debugging sections. */
3821 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3824 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3825 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3826 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3830 if (code
== BFD_RELOC_SPARC_OLO10
)
3831 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3833 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3834 if (reloc
->howto
== 0)
3836 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3837 _("internal error: can't export reloc type %d (`%s')"),
3838 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3844 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3847 if (reloc
->howto
->pc_relative
== 0
3848 || code
== BFD_RELOC_SPARC_PC10
3849 || code
== BFD_RELOC_SPARC_PC22
)
3850 reloc
->addend
= fixp
->fx_addnumber
;
3851 else if (sparc_pic_code
3852 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3853 && fixp
->fx_addsy
!= NULL
3854 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3855 || S_IS_WEAK (fixp
->fx_addsy
))
3856 && S_IS_DEFINED (fixp
->fx_addsy
)
3857 && ! S_IS_COMMON (fixp
->fx_addsy
))
3858 reloc
->addend
= fixp
->fx_addnumber
;
3860 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3862 #else /* elf or coff */
3864 if (code
!= BFD_RELOC_32_PCREL_S2
3865 && code
!= BFD_RELOC_SPARC_WDISP22
3866 && code
!= BFD_RELOC_SPARC_WDISP16
3867 && code
!= BFD_RELOC_SPARC_WDISP19
3868 && code
!= BFD_RELOC_SPARC_WDISP10
3869 && code
!= BFD_RELOC_SPARC_WPLT30
3870 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3871 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3872 reloc
->addend
= fixp
->fx_addnumber
;
3873 else if (symbol_section_p (fixp
->fx_addsy
))
3874 reloc
->addend
= (section
->vma
3875 + fixp
->fx_addnumber
3876 + md_pcrel_from (fixp
));
3878 reloc
->addend
= fixp
->fx_offset
;
3881 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3882 on the same location. */
3883 if (code
== BFD_RELOC_SPARC_OLO10
)
3885 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3888 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3890 = symbol_get_bfdsym (section_symbol (absolute_section
));
3891 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3892 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3893 reloc
->addend
= fixp
->tc_fix_data
;
3899 /* We have no need to default values of symbols. */
3902 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
3907 /* Round up a section size to the appropriate boundary. */
3910 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
3913 /* This is not right for ELF; a.out wants it, and COFF will force
3914 the alignment anyways. */
3915 valueT align
= ((valueT
) 1
3916 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3919 /* Turn alignment value into a mask. */
3921 newsize
= (size
+ align
) & ~align
;
3928 /* Exactly what point is a PC-relative offset relative TO?
3929 On the sparc, they're relative to the address of the offset, plus
3930 its size. This gets us to the following instruction.
3931 (??? Is this right? FIXME-SOON) */
3933 md_pcrel_from (fixS
*fixP
)
3937 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3938 if (! sparc_pic_code
3939 || fixP
->fx_addsy
== NULL
3940 || symbol_section_p (fixP
->fx_addsy
))
3941 ret
+= fixP
->fx_size
;
3945 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3956 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3959 return (value
== 1) ? shift
: -1;
3962 /* Sort of like s_lcomm. */
3965 static int max_alignment
= 15;
3969 s_reserve (int ignore ATTRIBUTE_UNUSED
)
3979 c
= get_symbol_name (&name
);
3980 p
= input_line_pointer
;
3982 SKIP_WHITESPACE_AFTER_NAME ();
3984 if (*input_line_pointer
!= ',')
3986 as_bad (_("Expected comma after name"));
3987 ignore_rest_of_line ();
3991 ++input_line_pointer
;
3993 if ((size
= get_absolute_expression ()) < 0)
3995 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3996 ignore_rest_of_line ();
4001 symbolP
= symbol_find_or_make (name
);
4004 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4005 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4007 as_bad (_("bad .reserve segment -- expected BSS segment"));
4011 if (input_line_pointer
[2] == '.')
4012 input_line_pointer
+= 7;
4014 input_line_pointer
+= 6;
4017 if (*input_line_pointer
== ',')
4019 ++input_line_pointer
;
4022 if (*input_line_pointer
== '\n')
4024 as_bad (_("missing alignment"));
4025 ignore_rest_of_line ();
4029 align
= (int) get_absolute_expression ();
4032 if (align
> max_alignment
)
4034 align
= max_alignment
;
4035 as_warn (_("alignment too large; assuming %d"), align
);
4041 as_bad (_("negative alignment"));
4042 ignore_rest_of_line ();
4048 temp
= mylog2 (align
);
4051 as_bad (_("alignment not a power of 2"));
4052 ignore_rest_of_line ();
4059 record_alignment (bss_section
, align
);
4064 if (!S_IS_DEFINED (symbolP
)
4066 && S_GET_OTHER (symbolP
) == 0
4067 && S_GET_DESC (symbolP
) == 0
4074 segT current_seg
= now_seg
;
4075 subsegT current_subseg
= now_subseg
;
4077 /* Switch to bss. */
4078 subseg_set (bss_section
, 1);
4082 frag_align (align
, 0, 0);
4084 /* Detach from old frag. */
4085 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4086 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4088 symbol_set_frag (symbolP
, frag_now
);
4089 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4090 (offsetT
) size
, (char *) 0);
4093 S_SET_SEGMENT (symbolP
, bss_section
);
4095 subseg_set (current_seg
, current_subseg
);
4098 S_SET_SIZE (symbolP
, size
);
4104 as_warn (_("Ignoring attempt to re-define symbol %s"),
4105 S_GET_NAME (symbolP
));
4108 demand_empty_rest_of_line ();
4112 s_common (int ignore ATTRIBUTE_UNUSED
)
4120 c
= get_symbol_name (&name
);
4121 /* Just after name is now '\0'. */
4122 p
= input_line_pointer
;
4124 SKIP_WHITESPACE_AFTER_NAME ();
4125 if (*input_line_pointer
!= ',')
4127 as_bad (_("Expected comma after symbol-name"));
4128 ignore_rest_of_line ();
4133 input_line_pointer
++;
4135 if ((temp
= get_absolute_expression ()) < 0)
4137 as_bad (_(".COMMon length (%lu) out of range ignored"),
4138 (unsigned long) temp
);
4139 ignore_rest_of_line ();
4144 symbolP
= symbol_find_or_make (name
);
4146 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4148 as_bad (_("Ignoring attempt to re-define symbol"));
4149 ignore_rest_of_line ();
4152 if (S_GET_VALUE (symbolP
) != 0)
4154 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4156 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4157 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4163 S_SET_VALUE (symbolP
, (valueT
) size
);
4164 S_SET_EXTERNAL (symbolP
);
4167 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4168 if (*input_line_pointer
!= ',')
4170 as_bad (_("Expected comma after common length"));
4171 ignore_rest_of_line ();
4174 input_line_pointer
++;
4176 if (*input_line_pointer
!= '"')
4178 temp
= get_absolute_expression ();
4181 if (temp
> max_alignment
)
4183 temp
= max_alignment
;
4184 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4190 as_bad (_("negative alignment"));
4191 ignore_rest_of_line ();
4196 if (symbol_get_obj (symbolP
)->local
)
4203 old_subsec
= now_subseg
;
4208 align
= mylog2 (temp
);
4212 as_bad (_("alignment not a power of 2"));
4213 ignore_rest_of_line ();
4217 record_alignment (bss_section
, align
);
4218 subseg_set (bss_section
, 0);
4220 frag_align (align
, 0, 0);
4221 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4222 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4223 symbol_set_frag (symbolP
, frag_now
);
4224 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4225 (offsetT
) size
, (char *) 0);
4227 S_SET_SEGMENT (symbolP
, bss_section
);
4228 S_CLEAR_EXTERNAL (symbolP
);
4229 S_SET_SIZE (symbolP
, size
);
4230 subseg_set (old_sec
, old_subsec
);
4233 #endif /* OBJ_ELF */
4236 S_SET_VALUE (symbolP
, (valueT
) size
);
4238 S_SET_ALIGN (symbolP
, temp
);
4239 S_SET_SIZE (symbolP
, size
);
4241 S_SET_EXTERNAL (symbolP
);
4242 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4247 input_line_pointer
++;
4248 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4249 if (*input_line_pointer
== '.')
4250 input_line_pointer
++;
4251 /* @@ Some say data, some say bss. */
4252 if (strncmp (input_line_pointer
, "bss\"", 4)
4253 && strncmp (input_line_pointer
, "data\"", 5))
4255 while (*--input_line_pointer
!= '"')
4257 input_line_pointer
--;
4258 goto bad_common_segment
;
4260 while (*input_line_pointer
++ != '"')
4262 goto allocate_common
;
4265 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4267 demand_empty_rest_of_line ();
4272 p
= input_line_pointer
;
4273 while (*p
&& *p
!= '\n')
4277 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4279 input_line_pointer
= p
;
4280 ignore_rest_of_line ();
4285 /* Handle the .empty pseudo-op. This suppresses the warnings about
4286 invalid delay slot usage. */
4289 s_empty (int ignore ATTRIBUTE_UNUSED
)
4291 /* The easy way to implement is to just forget about the last
4297 s_seg (int ignore ATTRIBUTE_UNUSED
)
4300 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4302 input_line_pointer
+= 6;
4306 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4308 input_line_pointer
+= 6;
4312 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4314 input_line_pointer
+= 7;
4318 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4320 input_line_pointer
+= 5;
4321 /* We only support 2 segments -- text and data -- for now, so
4322 things in the "bss segment" will have to go into data for now.
4323 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4324 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4327 as_bad (_("Unknown segment type"));
4328 demand_empty_rest_of_line ();
4334 subseg_set (data_section
, 1);
4335 demand_empty_rest_of_line ();
4339 s_proc (int ignore ATTRIBUTE_UNUSED
)
4341 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4343 ++input_line_pointer
;
4345 ++input_line_pointer
;
4348 /* This static variable is set by s_uacons to tell sparc_cons_align
4349 that the expression does not need to be aligned. */
4351 static int sparc_no_align_cons
= 0;
4353 /* This handles the unaligned space allocation pseudo-ops, such as
4354 .uaword. .uaword is just like .word, but the value does not need
4358 s_uacons (int bytes
)
4360 /* Tell sparc_cons_align not to align this value. */
4361 sparc_no_align_cons
= 1;
4363 sparc_no_align_cons
= 0;
4366 /* This handles the native word allocation pseudo-op .nword.
4367 For sparc_arch_size 32 it is equivalent to .word, for
4368 sparc_arch_size 64 it is equivalent to .xword. */
4371 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4373 cons (sparc_arch_size
== 32 ? 4 : 8);
4377 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4381 .register %g[2367],{#scratch|symbolname|#ignore}
4385 s_register (int ignore ATTRIBUTE_UNUSED
)
4392 if (input_line_pointer
[0] != '%'
4393 || input_line_pointer
[1] != 'g'
4394 || ((input_line_pointer
[2] & ~1) != '2'
4395 && (input_line_pointer
[2] & ~1) != '6')
4396 || input_line_pointer
[3] != ',')
4397 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4398 reg
= input_line_pointer
[2] - '0';
4399 input_line_pointer
+= 4;
4401 if (*input_line_pointer
== '#')
4403 ++input_line_pointer
;
4404 c
= get_symbol_name (®name
);
4405 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4406 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4407 if (regname
[0] == 'i')
4414 c
= get_symbol_name (®name
);
4417 if (sparc_arch_size
== 64)
4421 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4422 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4423 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4424 as_bad (_("redefinition of global register"));
4428 if (regname
== NULL
)
4429 globals
[reg
] = (symbolS
*) 1;
4434 if (symbol_find (regname
))
4435 as_bad (_("Register symbol %s already defined."),
4438 globals
[reg
] = symbol_make (regname
);
4439 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4441 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4442 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4443 flags
|= BSF_GLOBAL
;
4444 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4445 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4446 S_SET_ALIGN (globals
[reg
], reg
);
4447 S_SET_SIZE (globals
[reg
], 0);
4448 /* Although we actually want undefined_section here,
4449 we have to use absolute_section, because otherwise
4450 generic as code will make it a COM section.
4451 We fix this up in sparc_adjust_symtab. */
4452 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4453 S_SET_OTHER (globals
[reg
], 0);
4454 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4455 ->internal_elf_sym
.st_info
=
4456 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4457 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4458 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4463 (void) restore_line_pointer (c
);
4465 demand_empty_rest_of_line ();
4468 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4469 symbols which need it. */
4472 sparc_adjust_symtab (void)
4476 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4478 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4479 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4482 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4483 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4486 S_SET_SEGMENT (sym
, undefined_section
);
4491 /* If the --enforce-aligned-data option is used, we require .word,
4492 et. al., to be aligned correctly. We do it by setting up an
4493 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4494 no unexpected alignment was introduced.
4496 The SunOS and Solaris native assemblers enforce aligned data by
4497 default. We don't want to do that, because gcc can deliberately
4498 generate misaligned data if the packed attribute is used. Instead,
4499 we permit misaligned data by default, and permit the user to set an
4500 option to check for it. */
4503 sparc_cons_align (int nbytes
)
4507 /* Only do this if we are enforcing aligned data. */
4508 if (! enforce_aligned_data
)
4511 /* Don't align if this is an unaligned pseudo-op. */
4512 if (sparc_no_align_cons
)
4515 nalign
= mylog2 (nbytes
);
4519 gas_assert (nalign
> 0);
4521 if (now_seg
== absolute_section
)
4523 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4524 as_bad (_("misaligned data"));
4528 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4529 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4531 record_alignment (now_seg
, nalign
);
4534 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4537 sparc_handle_align (fragS
*fragp
)
4542 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4544 switch (fragp
->fr_type
)
4548 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4552 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4563 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4565 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4566 if (INSN_BIG_ENDIAN
)
4567 number_to_chars_bigendian (p
, wval
, 4);
4569 number_to_chars_littleendian (p
, wval
, 4);
4575 if (INSN_BIG_ENDIAN
)
4576 number_to_chars_bigendian (p
, 0x01000000, 4);
4578 number_to_chars_littleendian (p
, 0x01000000, 4);
4580 fragp
->fr_fix
+= fix
;
4590 /* Some special processing for a Sparc ELF file. */
4593 sparc_elf_final_processing (void)
4595 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4596 sort of BFD interface for this. */
4597 if (sparc_arch_size
== 64)
4599 switch (sparc_memory_model
)
4602 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4605 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4611 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4612 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4613 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4614 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4615 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4616 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4620 sparc_cons (expressionS
*exp
, int size
)
4623 const char *sparc_cons_special_reloc
= NULL
;
4626 save
= input_line_pointer
;
4627 if (input_line_pointer
[0] == '%'
4628 && input_line_pointer
[1] == 'r'
4629 && input_line_pointer
[2] == '_')
4631 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4633 input_line_pointer
+= 7;
4634 sparc_cons_special_reloc
= "disp";
4636 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4638 if (size
!= 4 && size
!= 8)
4639 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4642 input_line_pointer
+= 6;
4643 sparc_cons_special_reloc
= "plt";
4646 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4648 if (size
!= 4 && size
!= 8)
4649 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4652 input_line_pointer
+= 13;
4653 sparc_cons_special_reloc
= "tls_dtpoff";
4656 if (sparc_cons_special_reloc
)
4663 if (*input_line_pointer
!= '8')
4665 input_line_pointer
--;
4668 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4672 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4676 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4686 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4687 sparc_cons_special_reloc
, size
* 8, size
);
4691 input_line_pointer
+= 2;
4692 if (*input_line_pointer
!= '(')
4694 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4695 sparc_cons_special_reloc
, size
* 8);
4702 input_line_pointer
= save
;
4703 sparc_cons_special_reloc
= NULL
;
4708 char *end
= ++input_line_pointer
;
4711 while (! is_end_of_line
[(c
= *end
)])
4725 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4726 sparc_cons_special_reloc
, size
* 8);
4732 if (input_line_pointer
!= end
)
4734 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4735 sparc_cons_special_reloc
, size
* 8);
4739 input_line_pointer
++;
4741 c
= *input_line_pointer
;
4742 if (! is_end_of_line
[c
] && c
!= ',')
4743 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4744 sparc_cons_special_reloc
, size
* 8);
4750 if (sparc_cons_special_reloc
== NULL
)
4752 return sparc_cons_special_reloc
;
4757 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4758 reloc for a cons. We could use the definition there, except that
4759 we want to handle little endian relocs specially. */
4762 cons_fix_new_sparc (fragS
*frag
,
4764 unsigned int nbytes
,
4766 const char *sparc_cons_special_reloc
)
4768 bfd_reloc_code_real_type r
;
4770 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4771 (nbytes
== 2 ? BFD_RELOC_16
:
4772 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4774 if (target_little_endian_data
4776 && now_seg
->flags
& SEC_ALLOC
)
4777 r
= BFD_RELOC_SPARC_REV32
;
4779 if (sparc_cons_special_reloc
)
4781 if (*sparc_cons_special_reloc
== 'd')
4784 case 1: r
= BFD_RELOC_8_PCREL
; break;
4785 case 2: r
= BFD_RELOC_16_PCREL
; break;
4786 case 4: r
= BFD_RELOC_32_PCREL
; break;
4787 case 8: r
= BFD_RELOC_64_PCREL
; break;
4790 else if (*sparc_cons_special_reloc
== 'p')
4793 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4794 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4799 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4800 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4803 else if (sparc_no_align_cons
)
4807 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4808 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4809 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4814 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4818 sparc_cfi_frame_initial_instructions (void)
4820 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4824 sparc_regname_to_dw2regnum (char *regname
)
4832 p
= strchr (q
, regname
[0]);
4835 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4837 return (p
- q
) * 8 + regname
[1] - '0';
4839 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4841 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4843 if (regname
[0] == 'f' || regname
[0] == 'r')
4845 unsigned int regnum
;
4847 regnum
= strtoul (regname
+ 1, &q
, 10);
4850 if (regnum
>= ((regname
[0] == 'f'
4851 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4854 if (regname
[0] == 'f')
4857 if (regnum
>= 64 && (regnum
& 1))
4866 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4868 sparc_no_align_cons
= 1;
4869 emit_expr_with_reloc (exp
, nbytes
, "disp");
4870 sparc_no_align_cons
= 0;