1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 97, 1998 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
26 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
32 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
33 static void init_default_arch
PARAMS ((void));
34 static void sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
35 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
36 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
37 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
38 static int sparc_ffs
PARAMS ((unsigned int));
39 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
40 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
41 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
42 static int parse_const_expr_arg
PARAMS ((char **, int *));
43 static int get_expression
PARAMS ((char *str
));
45 /* Default architecture. */
46 /* ??? The default value should be V8, but sparclite support was added
47 by making it the default. GCC now passes -Asparclite, so maybe sometime in
48 the future we can set this to V8. */
50 #define DEFAULT_ARCH "sparclite"
52 static char *default_arch
= DEFAULT_ARCH
;
54 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 static int default_init_p
;
58 /* Current architecture. We don't bump up unless necessary. */
59 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
61 /* The maximum architecture level we can bump up to.
62 In a 32 bit environment, don't allow bumping up to v9 by default.
63 The native assembler works this way. The user is required to pass
64 an explicit argument before we'll create v9 object files. However, if
65 we don't see any v9 insns, a v8plus object file is not created. */
66 static enum sparc_opcode_arch_val max_architecture
;
68 /* Either 32 or 64, selects file format. */
69 static int sparc_arch_size
;
70 /* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72 static int default_arch_size
;
75 /* The currently selected v9 memory model. Currently only used for
77 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
80 static int architecture_requested
;
81 static int warn_on_bump
;
83 /* If warn_on_bump and the needed architecture is higher than this
84 architecture, issue a warning. */
85 static enum sparc_opcode_arch_val warn_after_architecture
;
87 /* Non-zero if we are generating PIC code. */
90 /* Non-zero if we should give an error when misaligned data is seen. */
91 static int enforce_aligned_data
;
93 extern int target_big_endian
;
95 /* V9 and 86x have big and little endian data, but instructions are always big
96 endian. The sparclet has bi-endian support but both data and insns have
97 the same endianness. Global `target_big_endian' is used for data.
98 The following macro is used for instructions. */
99 #ifndef INSN_BIG_ENDIAN
100 #define INSN_BIG_ENDIAN (target_big_endian \
101 || default_arch_type == sparc86x \
102 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
105 /* handle of the OPCODE hash table */
106 static struct hash_control
*op_hash
;
108 static void s_data1
PARAMS ((void));
109 static void s_seg
PARAMS ((int));
110 static void s_proc
PARAMS ((int));
111 static void s_reserve
PARAMS ((int));
112 static void s_common
PARAMS ((int));
113 static void s_empty
PARAMS ((int));
114 static void s_uacons
PARAMS ((int));
116 const pseudo_typeS md_pseudo_table
[] =
118 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
119 {"common", s_common
, 0},
120 {"empty", s_empty
, 0},
121 {"global", s_globl
, 0},
123 {"optim", s_ignore
, 0},
125 {"reserve", s_reserve
, 0},
127 {"skip", s_space
, 0},
130 {"uahalf", s_uacons
, 2},
131 {"uaword", s_uacons
, 4},
132 {"uaxword", s_uacons
, 8},
134 /* these are specific to sparc/svr4 */
135 {"pushsection", obj_elf_section
, 0},
136 {"popsection", obj_elf_previous
, 0},
137 {"2byte", s_uacons
, 2},
138 {"4byte", s_uacons
, 4},
139 {"8byte", s_uacons
, 8},
144 const int md_reloc_size
= 12; /* Size of relocation record */
146 /* This array holds the chars that always start a comment. If the
147 pre-processor is disabled, these aren't very useful */
148 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
150 /* This array holds the chars that only start a comment at the beginning of
151 a line. If the line seems to have the form '# 123 filename'
152 .line and .file directives will appear in the pre-processed output */
153 /* Note that input_file.c hand checks for '#' at the beginning of the
154 first line of the input file. This is because the compiler outputs
155 #NO_APP at the beginning of its output. */
156 /* Also note that comments started like this one will always
157 work if '/' isn't otherwise defined. */
158 const char line_comment_chars
[] = "#";
160 const char line_separator_chars
[] = "";
162 /* Chars that can be used to separate mant from exp in floating point nums */
163 const char EXP_CHARS
[] = "eE";
165 /* Chars that mean this number is a floating point constant */
168 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
170 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
171 changed in read.c. Ideally it shouldn't have to know about it at all,
172 but nothing is ideal around here. */
174 static unsigned char octal
[256];
175 #define isoctal(c) octal[(unsigned char) (c)]
176 static unsigned char toHex
[256];
181 unsigned long opcode
;
182 struct nlist
*nlistp
;
185 bfd_reloc_code_real_type reloc
;
188 struct sparc_it the_insn
, set_insn
;
190 static void output_insn
191 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
193 /* Table of arguments to -A.
194 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
195 for this use. That table is for opcodes only. This table is for opcodes
198 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
199 v8plusa
, v9
, v9a
, v9_64
};
201 static struct sparc_arch
{
204 enum sparc_arch_types arch_type
;
205 /* Default word size, as specified during configuration.
206 A value of zero means can't be used to specify default architecture. */
207 int default_arch_size
;
208 /* Allowable arg to -A? */
210 } sparc_arch_table
[] = {
211 { "v6", "v6", v6
, 0, 1 },
212 { "v7", "v7", v7
, 0, 1 },
213 { "v8", "v8", v8
, 32, 1 },
214 { "sparclet", "sparclet", sparclet
, 32, 1 },
215 { "sparclite", "sparclite", sparclite
, 32, 1 },
216 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
217 { "v8plus", "v9", v9
, 0, 1 },
218 { "v8plusa", "v9a", v9
, 0, 1 },
219 { "v9", "v9", v9
, 0, 1 },
220 { "v9a", "v9a", v9
, 0, 1 },
221 /* This exists to allow configure.in/Makefile.in to pass one
222 value to specify both the default machine and default word size. */
223 { "v9-64", "v9", v9
, 64, 0 },
224 { NULL
, NULL
, v8
, 0, 0 }
227 /* Variant of default_arch */
228 static enum sparc_arch_types default_arch_type
;
230 static struct sparc_arch
*
234 struct sparc_arch
*sa
;
236 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
237 if (strcmp (sa
->name
, name
) == 0)
239 if (sa
->name
== NULL
)
244 /* Initialize the default opcode arch and word size from the default
245 architecture name. */
250 struct sparc_arch
*sa
= lookup_arch (default_arch
);
253 || sa
->default_arch_size
== 0)
254 as_fatal (_("Invalid default architecture, broken assembler."));
256 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
257 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
258 as_fatal (_("Bad opcode table, broken assembler."));
259 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
261 default_arch_type
= sa
->arch_type
;
264 /* Called by TARGET_FORMAT. */
267 sparc_target_format ()
269 /* We don't get a chance to initialize anything before we're called,
270 so handle that now. */
271 if (! default_init_p
)
272 init_default_arch ();
276 return "a.out-sparc-netbsd";
279 return target_big_endian
? "a.out-sunos-big" : "a.out-sparc-little";
281 return "a.out-sunos-big";
292 return "coff-sparc-lynx";
299 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
307 * Invocation line includes a switch not recognized by the base assembler.
308 * See if it's a processor-specific option. These are:
311 * Warn on architecture bumps. See also -A.
313 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
314 * Standard 32 bit architectures.
315 * -Av8plus, -Av8plusa
316 * Sparc64 in a 32 bit world.
318 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
319 * This used to only mean 64 bits, but properly specifying it
320 * complicated gcc's ASM_SPECs, so now opcode selection is
321 * specified orthogonally to word size (except when specifying
322 * the default, but that is an internal implementation detail).
323 * -xarch=v8plus, -xarch=v8plusa
324 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
326 * Select the architecture and possibly the file format.
327 * Instructions or features not supported by the selected
328 * architecture cause fatal errors.
330 * The default is to start at v6, and bump the architecture up
331 * whenever an instruction is seen at a higher level. In 32 bit
332 * environments, v9 is not bumped up to, the user must pass
335 * If -bump is specified, a warning is printing when bumping to
338 * If an architecture is specified, all instructions must match
339 * that architecture. Any higher level instructions are flagged
340 * as errors. Note that in the 32 bit environment specifying
341 * -Av8plus does not automatically create a v8plus object file, a
342 * v9 insn must be seen.
344 * If both an architecture and -bump are specified, the
345 * architecture starts at the specified level, but bumps are
346 * warnings. Note that we can't set `current_architecture' to
347 * the requested level in this case: in the 32 bit environment,
348 * we still must avoid creating v8plus object files unless v9
352 * Bumping between incompatible architectures is always an
353 * error. For example, from sparclite to v9.
357 CONST
char *md_shortopts
= "A:K:VQ:sq";
360 CONST
char *md_shortopts
= "A:k";
362 CONST
char *md_shortopts
= "A:";
365 struct option md_longopts
[] = {
366 #define OPTION_BUMP (OPTION_MD_BASE)
367 {"bump", no_argument
, NULL
, OPTION_BUMP
},
368 #define OPTION_SPARC (OPTION_MD_BASE + 1)
369 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
370 #define OPTION_XARCH (OPTION_MD_BASE + 2)
371 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
373 #define OPTION_32 (OPTION_MD_BASE + 3)
374 {"32", no_argument
, NULL
, OPTION_32
},
375 #define OPTION_64 (OPTION_MD_BASE + 4)
376 {"64", no_argument
, NULL
, OPTION_64
},
377 #define OPTION_TSO (OPTION_MD_BASE + 5)
378 {"TSO", no_argument
, NULL
, OPTION_TSO
},
379 #define OPTION_PSO (OPTION_MD_BASE + 6)
380 {"PSO", no_argument
, NULL
, OPTION_PSO
},
381 #define OPTION_RMO (OPTION_MD_BASE + 7)
382 {"RMO", no_argument
, NULL
, OPTION_RMO
},
384 #ifdef SPARC_BIENDIAN
385 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
386 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
387 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
388 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
390 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
391 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
392 {NULL
, no_argument
, NULL
, 0}
394 size_t md_longopts_size
= sizeof(md_longopts
);
397 md_parse_option (c
, arg
)
401 /* We don't get a chance to initialize anything before we're called,
402 so handle that now. */
403 if (! default_init_p
)
404 init_default_arch ();
410 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
414 /* This is for compatibility with Sun's assembler. */
415 if (strcmp (arg
, "v8plus") != 0
416 && strcmp (arg
, "v8plusa") != 0)
418 as_bad (_("invalid architecture -xarch=%s"), arg
);
426 struct sparc_arch
*sa
;
427 enum sparc_opcode_arch_val opcode_arch
;
429 sa
= lookup_arch (arg
);
431 || ! sa
->user_option_p
)
433 as_bad (_("invalid architecture -A%s"), arg
);
437 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
438 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
439 as_fatal (_("Bad opcode table, broken assembler."));
441 max_architecture
= opcode_arch
;
442 architecture_requested
= 1;
447 /* Ignore -sparc, used by SunOS make default .s.o rule. */
450 case OPTION_ENFORCE_ALIGNED_DATA
:
451 enforce_aligned_data
= 1;
454 #ifdef SPARC_BIENDIAN
455 case OPTION_LITTLE_ENDIAN
:
456 target_big_endian
= 0;
457 if (default_arch_type
!= sparc86x
458 && default_arch_type
!= sparclet
459 && default_arch_type
!= v9
)
460 as_fatal ("This target does not support -EL");
462 case OPTION_BIG_ENDIAN
:
463 target_big_endian
= 1;
477 const char **list
, **l
;
479 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
480 list
= bfd_target_list ();
481 for (l
= list
; *l
!= NULL
; l
++)
483 if (sparc_arch_size
== 32)
485 if (strcmp (*l
, "elf32-sparc") == 0)
490 if (strcmp (*l
, "elf64-sparc") == 0)
495 as_fatal (_("No compiled in support for %d bit object file format"),
502 sparc_memory_model
= MM_TSO
;
506 sparc_memory_model
= MM_PSO
;
510 sparc_memory_model
= MM_RMO
;
518 /* Qy - do emit .comment
519 Qn - do not emit .comment */
523 /* use .stab instead of .stab.excl */
527 /* quick -- native assembler does fewer checks */
531 if (strcmp (arg
, "PIC") != 0)
532 as_warn (_("Unrecognized option following -K"));
546 md_show_usage (stream
)
549 const struct sparc_arch
*arch
;
551 /* We don't get a chance to initialize anything before we're called,
552 so handle that now. */
553 if (! default_init_p
)
554 init_default_arch ();
556 fprintf(stream
, _("SPARC options:\n"));
557 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
559 if (arch
!= &sparc_arch_table
[0])
560 fprintf (stream
, " | ");
561 if (arch
->user_option_p
)
562 fprintf (stream
, "-A%s", arch
->name
);
564 fprintf (stream
, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
565 fprintf (stream
, _("\
566 specify variant of SPARC architecture\n\
567 -bump warn when assembler switches architectures\n\
569 --enforce-aligned-data force .long, etc., to be aligned correctly\n"));
571 fprintf (stream
, _("\
572 -k generate PIC\n"));
575 fprintf (stream
, _("\
576 -32 create 32 bit object file\n\
577 -64 create 64 bit object file\n"));
578 fprintf (stream
, _("\
579 [default is %d]\n"), default_arch_size
);
580 fprintf (stream
, _("\
581 -TSO use Total Store Ordering\n\
582 -PSO use Partial Store Ordering\n\
583 -RMO use Relaxed Memory Ordering\n"));
584 fprintf (stream
, _("\
585 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
586 fprintf (stream
, _("\
587 -KPIC generate PIC\n\
588 -V print assembler version number\n\
593 #ifdef SPARC_BIENDIAN
594 fprintf (stream
, _("\
595 -EL generate code for a little endian machine\n\
596 -EB generate code for a big endian machine\n"));
600 /* sparc64 priviledged registers */
602 struct priv_reg_entry
608 struct priv_reg_entry priv_reg_table
[] =
627 {"", -1}, /* end marker */
630 /* v9a specific asrs */
632 struct priv_reg_entry v9a_asr_table
[] =
641 {"clear_softint", 21},
642 {"", -1}, /* end marker */
646 cmp_reg_entry (parg
, qarg
)
650 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
651 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
653 return strcmp (q
->name
, p
->name
);
656 /* This function is called once, at assembler startup time. It should
657 set up all the tables, etc. that the MD part of the assembler will need. */
662 register const char *retval
= NULL
;
664 register unsigned int i
= 0;
666 /* We don't get a chance to initialize anything before md_parse_option
667 is called, and it may not be called, so handle default initialization
668 now if not already done. */
669 if (! default_init_p
)
670 init_default_arch ();
672 op_hash
= hash_new ();
674 while (i
< (unsigned int) sparc_num_opcodes
)
676 const char *name
= sparc_opcodes
[i
].name
;
677 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
680 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
681 sparc_opcodes
[i
].name
, retval
);
686 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
688 fprintf (stderr
, _("internal error: losing opcode: `%s' \"%s\"\n"),
689 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
694 while (i
< (unsigned int) sparc_num_opcodes
695 && !strcmp (sparc_opcodes
[i
].name
, name
));
699 as_fatal (_("Broken assembler. No assembly attempted."));
701 for (i
= '0'; i
< '8'; ++i
)
703 for (i
= '0'; i
<= '9'; ++i
)
705 for (i
= 'a'; i
<= 'f'; ++i
)
706 toHex
[i
] = i
+ 10 - 'a';
707 for (i
= 'A'; i
<= 'F'; ++i
)
708 toHex
[i
] = i
+ 10 - 'A';
710 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
711 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
713 /* If -bump, record the architecture level at which we start issuing
714 warnings. The behaviour is different depending upon whether an
715 architecture was explicitly specified. If it wasn't, we issue warnings
716 for all upwards bumps. If it was, we don't start issuing warnings until
717 we need to bump beyond the requested architecture or when we bump between
718 conflicting architectures. */
721 && architecture_requested
)
723 /* `max_architecture' records the requested architecture.
724 Issue warnings if we go above it. */
725 warn_after_architecture
= max_architecture
;
727 /* Find the highest architecture level that doesn't conflict with
728 the requested one. */
729 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
730 max_architecture
> warn_after_architecture
;
732 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
733 warn_after_architecture
))
738 /* Called after all assembly has been done. */
743 if (sparc_arch_size
== 64)
745 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
746 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
748 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
752 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
753 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
754 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
755 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
756 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
757 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
760 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
761 be but for now it is (since that's the way it's always been
763 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
768 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
771 in_signed_range (val
, max
)
772 bfd_signed_vma val
, max
;
783 /* Return non-zero if VAL is in the range 0 to MAX. */
786 in_unsigned_range (val
, max
)
794 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
795 (e.g. -15 to +31). */
798 in_bitfield_range (val
, max
)
799 bfd_signed_vma val
, max
;
805 if (val
< ~(max
>> 1))
819 for (i
= 0; (mask
& 1) == 0; ++i
)
824 /* Implement big shift right. */
830 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
831 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
832 return val
>> amount
;
835 /* For communication between sparc_ip and get_expression. */
836 static char *expr_end
;
838 /* For communication between md_assemble and sparc_ip. */
839 static int special_case
;
841 /* Values for `special_case'.
842 Instructions that require wierd handling because they're longer than
844 #define SPECIAL_CASE_NONE 0
845 #define SPECIAL_CASE_SET 1
846 #define SPECIAL_CASE_SETSW 2
847 #define SPECIAL_CASE_SETX 3
848 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
849 #define SPECIAL_CASE_FDIV 4
851 /* Bit masks of various insns. */
852 #define NOP_INSN 0x01000000
853 #define OR_INSN 0x80100000
854 #define FMOVS_INSN 0x81A00020
855 #define SETHI_INSN 0x01000000
856 #define SLLX_INSN 0x81281000
857 #define SRA_INSN 0x81380000
859 /* The last instruction to be assembled. */
860 static const struct sparc_opcode
*last_insn
;
861 /* The assembled opcode of `last_insn'. */
862 static unsigned long last_opcode
;
864 /* Main entry point to assemble one instruction. */
870 const struct sparc_opcode
*insn
;
873 special_case
= SPECIAL_CASE_NONE
;
874 sparc_ip (str
, &insn
);
876 /* We warn about attempts to put a floating point branch in a delay slot,
877 unless the delay slot has been annulled. */
880 && (insn
->flags
& F_FBR
) != 0
881 && (last_insn
->flags
& F_DELAYED
) != 0
882 /* ??? This test isn't completely accurate. We assume anything with
883 F_{UNBR,CONDBR,FBR} set is annullable. */
884 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
885 || (last_opcode
& ANNUL
) == 0))
886 as_warn (_("FP branch in delay slot"));
888 /* SPARC before v9 requires a nop instruction between a floating
889 point instruction and a floating point branch. We insert one
890 automatically, with a warning. */
891 if (max_architecture
< SPARC_OPCODE_ARCH_V9
894 && (insn
->flags
& F_FBR
) != 0
895 && (last_insn
->flags
& F_FLOAT
) != 0)
897 struct sparc_it nop_insn
;
899 nop_insn
.opcode
= NOP_INSN
;
900 nop_insn
.reloc
= BFD_RELOC_NONE
;
901 output_insn (insn
, &nop_insn
);
902 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
905 switch (special_case
)
907 case SPECIAL_CASE_NONE
:
909 output_insn (insn
, &the_insn
);
912 case SPECIAL_CASE_SET
:
916 /* "set" is not defined for negative numbers in v9: it doesn't yield
917 what you expect it to. */
918 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
)
919 && the_insn
.exp
.X_op
== O_constant
)
921 if (the_insn
.exp
.X_add_number
< 0)
922 as_warn (_("set: used with negative number"));
923 else if (the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff)
924 as_warn (_("set: number larger than 4294967295"));
927 /* See if operand is absolute and small; skip sethi if so. */
928 if (the_insn
.exp
.X_op
!= O_constant
929 || the_insn
.exp
.X_add_number
>= (1 << 12)
930 || the_insn
.exp
.X_add_number
< -(1 << 12))
932 output_insn (insn
, &the_insn
);
935 /* See if operand has no low-order bits; skip OR if so. */
936 if (the_insn
.exp
.X_op
!= O_constant
937 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
940 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
941 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
944 | (the_insn
.exp
.X_add_number
945 & (need_hi22_p
? 0x3ff : 0x1fff)));
946 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
949 output_insn (insn
, &the_insn
);
954 case SPECIAL_CASE_SETSW
:
956 /* FIXME: Not finished. */
960 case SPECIAL_CASE_SETX
:
962 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
963 int upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
964 int lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
966 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
967 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
968 /* Output directly to dst reg if lower 32 bits are all zero. */
969 int upper_dstreg
= (the_insn
.exp
.X_op
== O_constant
970 && lower32
== 0) ? dstreg
: tmpreg
;
971 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
973 /* The tmp reg should not be the dst reg. */
974 if (tmpreg
== dstreg
)
975 as_warn (_("setx: temporary register same as destination register"));
977 /* Reset X_add_number, we've extracted it as upper32/lower32.
978 Otherwise fixup_segment will complain about not being able to
979 write an 8 byte number in a 4 byte field. */
980 the_insn
.exp
.X_add_number
= 0;
982 /* ??? Obviously there are other optimizations we can do
983 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
984 doing some of these. Later. If you do change things, try to
985 change all of this to be table driven as well. */
987 /* What to output depends on the number if it's constant.
988 Compute that first, then output what we've decided upon. */
989 if (the_insn
.exp
.X_op
!= O_constant
)
990 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
993 /* Only need hh22 if `or' insn can't handle constant. */
994 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
997 /* Does bottom part (after sethi) have bits? */
998 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
999 /* No hh22, but does upper32 still have bits we can't set
1003 && (upper32
!= -1 || lower32
>= 0)))
1006 /* If the lower half is all zero, we build the upper half directly
1007 into the dst reg. */
1009 /* Need lower half if number is zero. */
1010 || (! need_hh22_p
&& ! need_hm10_p
))
1012 /* No need for sethi if `or' insn can handle constant. */
1013 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1014 /* Note that we can't use a negative constant in the `or'
1015 insn unless the upper 32 bits are all ones. */
1016 || (lower32
< 0 && upper32
!= -1))
1019 /* Does bottom part (after sethi) have bits? */
1020 if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1022 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1023 /* Need `or' if we didn't set anything else. */
1024 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1031 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1032 | ((upper32
>> 10) & 0x3fffff));
1033 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1034 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1035 output_insn (insn
, &the_insn
);
1040 the_insn
.opcode
= (OR_INSN
1041 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1045 & (need_hh22_p
? 0x3ff : 0x1fff)));
1046 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1047 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1048 output_insn (insn
, &the_insn
);
1053 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1054 | ((lower32
>> 10) & 0x3fffff));
1055 the_insn
.reloc
= BFD_RELOC_HI22
;
1056 output_insn (insn
, &the_insn
);
1061 /* FIXME: One nice optimization to do here is to OR the low part
1062 with the highpart if hi22 isn't needed and the low part is
1064 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1068 & (need_hi22_p
? 0x3ff : 0x1fff)));
1069 the_insn
.reloc
= BFD_RELOC_LO10
;
1070 output_insn (insn
, &the_insn
);
1073 /* If we needed to build the upper part, shift it into place. */
1074 if (need_hh22_p
|| need_hm10_p
)
1076 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1078 the_insn
.reloc
= BFD_RELOC_NONE
;
1079 output_insn (insn
, &the_insn
);
1082 /* If we needed to build both upper and lower parts, OR them together. */
1083 if ((need_hh22_p
|| need_hm10_p
)
1084 && (need_hi22_p
|| need_lo10_p
))
1086 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1088 the_insn
.reloc
= BFD_RELOC_NONE
;
1089 output_insn (insn
, &the_insn
);
1091 /* We didn't need both regs, but we may have to sign extend lower32. */
1092 else if (need_hi22_p
&& upper32
== -1)
1094 the_insn
.opcode
= (SRA_INSN
| RS1 (dstreg
) | RD (dstreg
)
1096 the_insn
.reloc
= BFD_RELOC_NONE
;
1097 output_insn (insn
, &the_insn
);
1102 case SPECIAL_CASE_FDIV
:
1104 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1106 output_insn (insn
, &the_insn
);
1108 /* According to information leaked from Sun, the "fdiv" instructions
1109 on early SPARC machines would produce incorrect results sometimes.
1110 The workaround is to add an fmovs of the destination register to
1111 itself just after the instruction. This was true on machines
1112 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1113 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1114 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1115 output_insn (insn
, &the_insn
);
1120 as_fatal (_("failed special case insn sanity check"));
1124 /* Subroutine of md_assemble to do the actual parsing. */
1127 sparc_ip (str
, pinsn
)
1129 const struct sparc_opcode
**pinsn
;
1131 char *error_message
= "";
1135 const struct sparc_opcode
*insn
;
1137 unsigned long opcode
;
1138 unsigned int mask
= 0;
1143 for (s
= str
; islower ((unsigned char) *s
) || (*s
>= '0' && *s
<= '3'); ++s
)
1161 as_fatal (_("Unknown opcode: `%s'"), str
);
1163 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1167 as_bad (_("Unknown opcode: `%s'"), str
);
1178 opcode
= insn
->match
;
1179 memset (&the_insn
, '\0', sizeof (the_insn
));
1180 the_insn
.reloc
= BFD_RELOC_NONE
;
1184 * Build the opcode, checking as we go to make
1185 * sure that the operands match
1187 for (args
= insn
->args
;; ++args
)
1195 /* Parse a series of masks. */
1202 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1205 error_message
= _(": invalid membar mask name");
1209 while (*s
== ' ') { ++s
; continue; }
1210 if (*s
== '|' || *s
== '+')
1212 while (*s
== ' ') { ++s
; continue; }
1217 if (! parse_const_expr_arg (&s
, &kmask
))
1219 error_message
= _(": invalid membar mask expression");
1222 if (kmask
< 0 || kmask
> 127)
1224 error_message
= _(": invalid membar mask number");
1229 opcode
|= MEMBAR (kmask
);
1237 /* Parse a prefetch function. */
1240 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1242 error_message
= _(": invalid prefetch function name");
1248 if (! parse_const_expr_arg (&s
, &fcn
))
1250 error_message
= _(": invalid prefetch function expression");
1253 if (fcn
< 0 || fcn
> 31)
1255 error_message
= _(": invalid prefetch function number");
1265 /* Parse a sparc64 privileged register. */
1268 struct priv_reg_entry
*p
= priv_reg_table
;
1269 unsigned int len
= 9999999; /* init to make gcc happy */
1272 while (p
->name
[0] > s
[0])
1274 while (p
->name
[0] == s
[0])
1276 len
= strlen (p
->name
);
1277 if (strncmp (p
->name
, s
, len
) == 0)
1281 if (p
->name
[0] != s
[0])
1283 error_message
= _(": unrecognizable privileged register");
1287 opcode
|= (p
->regnum
<< 14);
1289 opcode
|= (p
->regnum
<< 25);
1295 error_message
= _(": unrecognizable privileged register");
1301 /* Parse a v9a ancillary state register. */
1304 struct priv_reg_entry
*p
= v9a_asr_table
;
1305 unsigned int len
= 9999999; /* init to make gcc happy */
1308 while (p
->name
[0] > s
[0])
1310 while (p
->name
[0] == s
[0])
1312 len
= strlen (p
->name
);
1313 if (strncmp (p
->name
, s
, len
) == 0)
1317 if (p
->name
[0] != s
[0])
1319 error_message
= _(": unrecognizable v9a ancillary state register");
1322 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1324 error_message
= _(": rd on write only ancillary state register");
1328 opcode
|= (p
->regnum
<< 14);
1330 opcode
|= (p
->regnum
<< 25);
1336 error_message
= _(": unrecognizable v9a ancillary state register");
1342 if (strncmp (s
, "%asr", 4) == 0)
1346 if (isdigit ((unsigned char) *s
))
1350 while (isdigit ((unsigned char) *s
))
1352 num
= num
* 10 + *s
- '0';
1356 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1358 if (num
< 16 || 31 < num
)
1360 error_message
= _(": asr number must be between 16 and 31");
1366 if (num
< 0 || 31 < num
)
1368 error_message
= _(": asr number must be between 0 and 31");
1373 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1378 error_message
= _(": expecting %asrN");
1385 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1389 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1393 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1394 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1395 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1397 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1398 /* These fields are unsigned, but for upward compatibility,
1399 allow negative values as well. */
1403 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1404 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1405 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1407 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1408 /* These fields are unsigned, but for upward compatibility,
1409 allow negative values as well. */
1413 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1418 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1423 if (*s
== 'p' && s
[1] == 'n')
1431 if (*s
== 'p' && s
[1] == 't')
1443 if (strncmp (s
, "%icc", 4) == 0)
1455 if (strncmp (s
, "%xcc", 4) == 0)
1467 if (strncmp (s
, "%fcc0", 5) == 0)
1479 if (strncmp (s
, "%fcc1", 5) == 0)
1491 if (strncmp (s
, "%fcc2", 5) == 0)
1503 if (strncmp (s
, "%fcc3", 5) == 0)
1511 if (strncmp (s
, "%pc", 3) == 0)
1519 if (strncmp (s
, "%tick", 5) == 0)
1526 case '\0': /* end of args */
1545 case '[': /* these must match exactly */
1553 case '#': /* must be at least one digit */
1554 if (isdigit ((unsigned char) *s
++))
1556 while (isdigit ((unsigned char) *s
))
1564 case 'C': /* coprocessor state register */
1565 if (strncmp (s
, "%csr", 4) == 0)
1572 case 'b': /* next operand is a coprocessor register */
1575 if (*s
++ == '%' && *s
++ == 'c' && isdigit ((unsigned char) *s
))
1578 if (isdigit ((unsigned char) *s
))
1580 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1594 opcode
|= mask
<< 14;
1602 opcode
|= mask
<< 25;
1608 case 'r': /* next operand must be a register */
1618 case 'f': /* frame pointer */
1626 case 'g': /* global register */
1627 if (isoctal (c
= *s
++))
1634 case 'i': /* in register */
1635 if (isoctal (c
= *s
++))
1637 mask
= c
- '0' + 24;
1642 case 'l': /* local register */
1643 if (isoctal (c
= *s
++))
1645 mask
= (c
- '0' + 16);
1650 case 'o': /* out register */
1651 if (isoctal (c
= *s
++))
1653 mask
= (c
- '0' + 8);
1658 case 's': /* stack pointer */
1666 case 'r': /* any register */
1667 if (!isdigit ((unsigned char) (c
= *s
++)))
1682 if (isdigit ((unsigned char) *s
))
1684 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1700 /* Got the register, now figure out where
1701 it goes in the opcode. */
1705 opcode
|= mask
<< 14;
1713 opcode
|= mask
<< 25;
1717 opcode
|= (mask
<< 25) | (mask
<< 14);
1721 opcode
|= (mask
<< 25) | (mask
<< 0);
1727 case 'e': /* next operand is a floating point register */
1742 && ((format
= *s
) == 'f')
1743 && isdigit ((unsigned char) *++s
))
1745 for (mask
= 0; isdigit ((unsigned char) *s
); ++s
)
1747 mask
= 10 * mask
+ (*s
- '0');
1748 } /* read the number */
1756 } /* register must be even numbered */
1764 } /* register must be multiple of 4 */
1768 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1769 error_message
= _(": There are only 64 f registers; [0-63]");
1771 error_message
= _(": There are only 32 f registers; [0-31]");
1774 else if (mask
>= 32)
1776 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1779 mask
-= 31; /* wrap high bit */
1783 error_message
= _(": There are only 32 f registers; [0-31]");
1791 } /* if not an 'f' register. */
1798 opcode
|= RS1 (mask
);
1805 opcode
|= RS2 (mask
);
1811 opcode
|= RD (mask
);
1820 if (strncmp (s
, "%fsr", 4) == 0)
1827 case '0': /* 64 bit immediate (setx insn) */
1828 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
1831 case 'h': /* high 22 bits */
1832 the_insn
.reloc
= BFD_RELOC_HI22
;
1835 case 'l': /* 22 bit PC relative immediate */
1836 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
1840 case 'L': /* 30 bit immediate */
1841 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
1845 case 'n': /* 22 bit immediate */
1846 the_insn
.reloc
= BFD_RELOC_SPARC22
;
1849 case 'i': /* 13 bit immediate */
1850 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1858 /* Check for %hi, etc. */
1862 /* The name as it appears in assembler. */
1864 /* strlen (name), precomputed for speed */
1866 /* The reloc this pseudo-op translates to. */
1868 /* Non-zero if for v9 only. */
1870 /* Non-zero if can be used in pc-relative contexts. */
1871 int pcrel_p
;/*FIXME:wip*/
1873 /* hix/lox must appear before hi/lo so %hix won't be
1874 mistaken for %hi. */
1875 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
1876 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
1877 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
1878 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
1879 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
1880 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
1881 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
1882 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
1883 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
1884 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
1885 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
1886 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
1891 for (o
= ops
; o
->name
; o
++)
1892 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
1894 if (o
->name
== NULL
)
1897 the_insn
.reloc
= o
->reloc
;
1902 /* Note that if the get_expression() fails, we will still
1903 have created U entries in the symbol table for the
1904 'symbols' in the input string. Try not to create U
1905 symbols for registers, etc. */
1907 /* This stuff checks to see if the expression ends in
1908 +%reg. If it does, it removes the register from
1909 the expression, and re-sets 's' to point to the
1914 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
1916 if (s1
!= s
&& isdigit ((unsigned char) s1
[-1]))
1918 if (s1
[-2] == '%' && s1
[-3] == '+')
1922 (void) get_expression (s
);
1927 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
1931 (void) get_expression (s
);
1938 (void) get_expression (s
);
1941 /* Check for constants that don't require emitting a reloc. */
1942 if (the_insn
.exp
.X_op
== O_constant
1943 && the_insn
.exp
.X_add_symbol
== 0
1944 && the_insn
.exp
.X_op_symbol
== 0)
1946 /* For pc-relative call instructions, we reject
1947 constants to get better code. */
1949 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
1950 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
1952 error_message
= _(": PC-relative operand can't be a constant");
1956 /* Constants that won't fit are checked in md_apply_fix3
1957 and bfd_install_relocation.
1958 ??? It would be preferable to install the constants
1959 into the insn here and save having to create a fixS
1960 for each one. There already exists code to handle
1961 all the various cases (e.g. in md_apply_fix3 and
1962 bfd_install_relocation) so duplicating all that code
1963 here isn't right. */
1983 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
1985 error_message
= _(": invalid ASI name");
1991 if (! parse_const_expr_arg (&s
, &asi
))
1993 error_message
= _(": invalid ASI expression");
1996 if (asi
< 0 || asi
> 255)
1998 error_message
= _(": invalid ASI number");
2002 opcode
|= ASI (asi
);
2004 } /* alternate space */
2007 if (strncmp (s
, "%psr", 4) == 0)
2014 case 'q': /* floating point queue */
2015 if (strncmp (s
, "%fq", 3) == 0)
2022 case 'Q': /* coprocessor queue */
2023 if (strncmp (s
, "%cq", 3) == 0)
2031 if (strcmp (str
, "set") == 0
2032 || strcmp (str
, "setuw") == 0)
2034 special_case
= SPECIAL_CASE_SET
;
2037 else if (strcmp (str
, "setsw") == 0)
2039 special_case
= SPECIAL_CASE_SETSW
;
2042 else if (strcmp (str
, "setx") == 0)
2044 special_case
= SPECIAL_CASE_SETX
;
2047 else if (strncmp (str
, "fdiv", 4) == 0)
2049 special_case
= SPECIAL_CASE_FDIV
;
2055 if (strncmp (s
, "%asi", 4) != 0)
2061 if (strncmp (s
, "%fprs", 5) != 0)
2067 if (strncmp (s
, "%ccr", 4) != 0)
2073 if (strncmp (s
, "%tbr", 4) != 0)
2079 if (strncmp (s
, "%wim", 4) != 0)
2086 char *push
= input_line_pointer
;
2089 input_line_pointer
= s
;
2091 if (e
.X_op
== O_constant
)
2093 int n
= e
.X_add_number
;
2094 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2095 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2097 opcode
|= e
.X_add_number
<< 5;
2100 as_bad (_("non-immediate OPF operand, ignored"));
2101 s
= input_line_pointer
;
2102 input_line_pointer
= push
;
2107 if (strncmp (s
, "%y", 2) != 0)
2115 /* Parse a sparclet cpreg. */
2117 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2119 error_message
= _(": invalid cpreg name");
2122 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2127 as_fatal (_("failed sanity check."));
2128 } /* switch on arg code */
2130 /* Break out of for() loop. */
2132 } /* for each arg that we expect */
2137 /* Args don't match. */
2138 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2139 && (insn
->name
== insn
[1].name
2140 || !strcmp (insn
->name
, insn
[1].name
)))
2148 as_bad (_("Illegal operands%s"), error_message
);
2154 /* We have a match. Now see if the architecture is ok. */
2155 int needed_arch_mask
= insn
->architecture
;
2159 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
2160 | (1 << SPARC_OPCODE_ARCH_V9A
));
2161 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2164 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
2166 /* Can we bump up the architecture? */
2167 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
2169 enum sparc_opcode_arch_val needed_architecture
=
2170 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2171 & needed_arch_mask
);
2173 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2175 && needed_architecture
> warn_after_architecture
)
2177 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2178 sparc_opcode_archs
[current_architecture
].name
,
2179 sparc_opcode_archs
[needed_architecture
].name
,
2181 warn_after_architecture
= needed_architecture
;
2183 current_architecture
= needed_architecture
;
2186 /* ??? This seems to be a bit fragile. What if the next entry in
2187 the opcode table is the one we want and it is supported?
2188 It is possible to arrange the table today so that this can't
2189 happen but what about tomorrow? */
2192 int arch
,printed_one_p
= 0;
2194 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2196 /* Create a list of the architectures that support the insn. */
2197 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
2199 arch
= sparc_ffs (needed_arch_mask
);
2200 while ((1 << arch
) <= needed_arch_mask
)
2202 if ((1 << arch
) & needed_arch_mask
)
2206 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2213 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2214 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2216 sparc_opcode_archs
[max_architecture
].name
);
2222 } /* forever looking for a match */
2224 the_insn
.opcode
= opcode
;
2227 /* Parse an argument that can be expressed as a keyword.
2228 (eg: #StoreStore or %ccfr).
2229 The result is a boolean indicating success.
2230 If successful, INPUT_POINTER is updated. */
2233 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2234 int (*lookup_fn
) PARAMS ((const char *));
2235 char **input_pointerP
;
2241 p
= *input_pointerP
;
2242 for (q
= p
+ (*p
== '#' || *p
== '%');
2243 isalnum ((unsigned char) *q
) || *q
== '_';
2248 value
= (*lookup_fn
) (p
);
2253 *input_pointerP
= q
;
2257 /* Parse an argument that is a constant expression.
2258 The result is a boolean indicating success. */
2261 parse_const_expr_arg (input_pointerP
, valueP
)
2262 char **input_pointerP
;
2265 char *save
= input_line_pointer
;
2268 input_line_pointer
= *input_pointerP
;
2269 /* The next expression may be something other than a constant
2270 (say if we're not processing the right variant of the insn).
2271 Don't call expression unless we're sure it will succeed as it will
2272 signal an error (which we want to defer until later). */
2273 /* FIXME: It might be better to define md_operand and have it recognize
2274 things like %asi, etc. but continuing that route through to the end
2275 is a lot of work. */
2276 if (*input_line_pointer
== '%')
2278 input_line_pointer
= save
;
2282 *input_pointerP
= input_line_pointer
;
2283 input_line_pointer
= save
;
2284 if (exp
.X_op
!= O_constant
)
2286 *valueP
= exp
.X_add_number
;
2290 /* Subroutine of sparc_ip to parse an expression. */
2293 get_expression (str
)
2299 save_in
= input_line_pointer
;
2300 input_line_pointer
= str
;
2301 seg
= expression (&the_insn
.exp
);
2302 if (seg
!= absolute_section
2303 && seg
!= text_section
2304 && seg
!= data_section
2305 && seg
!= bss_section
2306 && seg
!= undefined_section
)
2308 the_insn
.error
= _("bad segment");
2309 expr_end
= input_line_pointer
;
2310 input_line_pointer
= save_in
;
2313 expr_end
= input_line_pointer
;
2314 input_line_pointer
= save_in
;
2318 /* Subroutine of md_assemble to output one insn. */
2321 output_insn (insn
, the_insn
)
2322 const struct sparc_opcode
*insn
;
2323 struct sparc_it
*the_insn
;
2325 char *toP
= frag_more (4);
2327 /* put out the opcode */
2328 if (INSN_BIG_ENDIAN
)
2329 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2331 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2333 /* put out the symbol-dependent stuff */
2334 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2336 fixS
*fixP
= fix_new_exp (frag_now
, /* which frag */
2337 (toP
- frag_now
->fr_literal
), /* where */
2342 /* Turn off overflow checking in fixup_segment. We'll do our
2343 own overflow checking in md_apply_fix3. This is necessary because
2344 the insn size is 4 and fixup_segment will signal an overflow for
2345 large 8 byte quantities. */
2346 fixP
->fx_no_overflow
= 1;
2350 last_opcode
= the_insn
->opcode
;
2354 This is identical to the md_atof in m68k.c. I think this is right,
2357 Turn a string in input_line_pointer into a floating point constant of type
2358 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2359 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2362 /* Equal to MAX_PRECISION in atof-ieee.c */
2363 #define MAX_LITTLENUMS 6
2366 md_atof (type
, litP
, sizeP
)
2372 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2403 return _("Bad call to MD_ATOF()");
2406 t
= atof_ieee (input_line_pointer
, type
, words
);
2408 input_line_pointer
= t
;
2409 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2411 if (target_big_endian
)
2413 for (i
= 0; i
< prec
; i
++)
2415 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2416 litP
+= sizeof (LITTLENUM_TYPE
);
2421 for (i
= prec
- 1; i
>= 0; i
--)
2423 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2424 litP
+= sizeof (LITTLENUM_TYPE
);
2431 /* Write a value out to the object file, using the appropriate
2435 md_number_to_chars (buf
, val
, n
)
2440 if (target_big_endian
)
2441 number_to_chars_bigendian (buf
, val
, n
);
2443 number_to_chars_littleendian (buf
, val
, n
);
2446 /* Apply a fixS to the frags, now that we know the value it ought to
2450 md_apply_fix3 (fixP
, value
, segment
)
2455 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2461 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2463 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2466 /* FIXME: SPARC ELF relocations don't use an addend in the data
2467 field itself. This whole approach should be somehow combined
2468 with the calls to bfd_install_relocation. Also, the value passed
2469 in by fixup_segment includes the value of a defined symbol. We
2470 don't want to include the value of an externally visible symbol. */
2471 if (fixP
->fx_addsy
!= NULL
)
2473 if (fixP
->fx_addsy
->sy_used_in_reloc
2474 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2475 || S_IS_WEAK (fixP
->fx_addsy
)
2476 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2477 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2478 && ((bfd_get_section_flags (stdoutput
,
2479 S_GET_SEGMENT (fixP
->fx_addsy
))
2480 & SEC_LINK_ONCE
) != 0
2481 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2483 sizeof ".gnu.linkonce" - 1) == 0)))
2484 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2485 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2486 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2487 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2492 /* This is a hack. There should be a better way to
2493 handle this. Probably in terms of howto fields, once
2494 we can look at these fixups in terms of howtos. */
2495 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2496 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2499 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2500 generate a reloc, then we just want to let the reloc addend set
2501 the value. We do not want to also stuff the addend into the
2502 object file. Including the addend in the object file works when
2503 doing a static link, because the linker will ignore the object
2504 file contents. However, the dynamic linker does not ignore the
2505 object file contents. */
2506 if (fixP
->fx_addsy
!= NULL
2507 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2510 /* When generating PIC code, we do not want an addend for a reloc
2511 against a local symbol. We adjust fx_addnumber to cancel out the
2512 value already included in val, and to also cancel out the
2513 adjustment which bfd_install_relocation will create. */
2515 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2516 && fixP
->fx_addsy
!= NULL
2517 && ! S_IS_COMMON (fixP
->fx_addsy
)
2518 && (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
2519 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2522 /* If this is a data relocation, just output VAL. */
2524 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2526 md_number_to_chars (buf
, val
, 2);
2528 else if (fixP
->fx_r_type
== BFD_RELOC_32
)
2530 md_number_to_chars (buf
, val
, 4);
2532 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2534 md_number_to_chars (buf
, val
, 8);
2538 /* It's a relocation against an instruction. */
2540 if (INSN_BIG_ENDIAN
)
2541 insn
= bfd_getb32 ((unsigned char *) buf
);
2543 insn
= bfd_getl32 ((unsigned char *) buf
);
2545 switch (fixP
->fx_r_type
)
2547 case BFD_RELOC_32_PCREL_S2
:
2549 /* FIXME: This increment-by-one deserves a comment of why it's
2551 if (! sparc_pic_code
2552 || fixP
->fx_addsy
== NULL
2553 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2555 insn
|= val
& 0x3fffffff;
2558 case BFD_RELOC_SPARC_11
:
2559 if (! in_signed_range (val
, 0x7ff))
2560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2561 _("relocation overflow"));
2562 insn
|= val
& 0x7ff;
2565 case BFD_RELOC_SPARC_10
:
2566 if (! in_signed_range (val
, 0x3ff))
2567 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2568 _("relocation overflow"));
2569 insn
|= val
& 0x3ff;
2572 case BFD_RELOC_SPARC_7
:
2573 if (! in_bitfield_range (val
, 0x7f))
2574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2575 _("relocation overflow"));
2579 case BFD_RELOC_SPARC_6
:
2580 if (! in_bitfield_range (val
, 0x3f))
2581 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2582 _("relocation overflow"));
2586 case BFD_RELOC_SPARC_5
:
2587 if (! in_bitfield_range (val
, 0x1f))
2588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2589 _("relocation overflow"));
2593 case BFD_RELOC_SPARC_WDISP16
:
2594 /* FIXME: simplify */
2595 if (((val
> 0) && (val
& ~0x3fffc))
2596 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2597 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2598 _("relocation overflow"));
2599 /* FIXME: The +1 deserves a comment. */
2600 val
= (val
>> 2) + 1;
2601 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2604 case BFD_RELOC_SPARC_WDISP19
:
2605 /* FIXME: simplify */
2606 if (((val
> 0) && (val
& ~0x1ffffc))
2607 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2609 _("relocation overflow"));
2610 /* FIXME: The +1 deserves a comment. */
2611 val
= (val
>> 2) + 1;
2612 insn
|= val
& 0x7ffff;
2615 case BFD_RELOC_SPARC_HH22
:
2616 val
= BSR (val
, 32);
2617 /* intentional fallthrough */
2619 case BFD_RELOC_SPARC_LM22
:
2620 case BFD_RELOC_HI22
:
2621 if (!fixP
->fx_addsy
)
2623 insn
|= (val
>> 10) & 0x3fffff;
2627 /* FIXME: Need comment explaining why we do this. */
2632 case BFD_RELOC_SPARC22
:
2633 if (val
& ~0x003fffff)
2634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2635 _("relocation overflow"));
2636 insn
|= (val
& 0x3fffff);
2639 case BFD_RELOC_SPARC_HM10
:
2640 val
= BSR (val
, 32);
2641 /* intentional fallthrough */
2643 case BFD_RELOC_LO10
:
2644 if (!fixP
->fx_addsy
)
2646 insn
|= val
& 0x3ff;
2650 /* FIXME: Need comment explaining why we do this. */
2655 case BFD_RELOC_SPARC13
:
2656 if (! in_signed_range (val
, 0x1fff))
2657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2658 _("relocation overflow"));
2659 insn
|= val
& 0x1fff;
2662 case BFD_RELOC_SPARC_WDISP22
:
2663 val
= (val
>> 2) + 1;
2665 case BFD_RELOC_SPARC_BASE22
:
2666 insn
|= val
& 0x3fffff;
2669 case BFD_RELOC_SPARC_H44
:
2670 if (!fixP
->fx_addsy
)
2674 insn
|= tval
& 0x3fffff;
2678 case BFD_RELOC_SPARC_M44
:
2679 if (!fixP
->fx_addsy
)
2680 insn
|= (val
>> 12) & 0x3ff;
2683 case BFD_RELOC_SPARC_L44
:
2684 if (!fixP
->fx_addsy
)
2685 insn
|= val
& 0xfff;
2688 case BFD_RELOC_SPARC_HIX22
:
2689 if (!fixP
->fx_addsy
)
2691 val
^= ~ (offsetT
) 0;
2692 insn
|= (val
>> 10) & 0x3fffff;
2696 case BFD_RELOC_SPARC_LOX10
:
2697 if (!fixP
->fx_addsy
)
2698 insn
|= 0x1c00 | (val
& 0x3ff);
2701 case BFD_RELOC_NONE
:
2703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2704 _("bad or unhandled relocation type: 0x%02x"),
2709 if (INSN_BIG_ENDIAN
)
2710 bfd_putb32 (insn
, (unsigned char *) buf
);
2712 bfd_putl32 (insn
, (unsigned char *) buf
);
2715 /* Are we finished with this relocation now? */
2716 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
2722 /* Translate internal representation of relocation info to BFD target
2725 tc_gen_reloc (section
, fixp
)
2730 bfd_reloc_code_real_type code
;
2732 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2734 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
2735 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2737 switch (fixp
->fx_r_type
)
2741 case BFD_RELOC_HI22
:
2742 case BFD_RELOC_LO10
:
2743 case BFD_RELOC_32_PCREL_S2
:
2744 case BFD_RELOC_SPARC13
:
2745 case BFD_RELOC_SPARC_BASE13
:
2746 case BFD_RELOC_SPARC_WDISP16
:
2747 case BFD_RELOC_SPARC_WDISP19
:
2748 case BFD_RELOC_SPARC_WDISP22
:
2750 case BFD_RELOC_SPARC_5
:
2751 case BFD_RELOC_SPARC_6
:
2752 case BFD_RELOC_SPARC_7
:
2753 case BFD_RELOC_SPARC_10
:
2754 case BFD_RELOC_SPARC_11
:
2755 case BFD_RELOC_SPARC_HH22
:
2756 case BFD_RELOC_SPARC_HM10
:
2757 case BFD_RELOC_SPARC_LM22
:
2758 case BFD_RELOC_SPARC_PC_HH22
:
2759 case BFD_RELOC_SPARC_PC_HM10
:
2760 case BFD_RELOC_SPARC_PC_LM22
:
2761 case BFD_RELOC_SPARC_H44
:
2762 case BFD_RELOC_SPARC_M44
:
2763 case BFD_RELOC_SPARC_L44
:
2764 case BFD_RELOC_SPARC_HIX22
:
2765 case BFD_RELOC_SPARC_LOX10
:
2766 code
= fixp
->fx_r_type
;
2773 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2774 /* If we are generating PIC code, we need to generate a different
2778 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2780 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2787 case BFD_RELOC_32_PCREL_S2
:
2788 if (! S_IS_DEFINED (fixp
->fx_addsy
)
2789 || S_IS_COMMON (fixp
->fx_addsy
)
2790 || S_IS_EXTERNAL (fixp
->fx_addsy
)
2791 || S_IS_WEAK (fixp
->fx_addsy
))
2792 code
= BFD_RELOC_SPARC_WPLT30
;
2794 case BFD_RELOC_HI22
:
2795 if (fixp
->fx_addsy
!= NULL
2796 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2797 code
= BFD_RELOC_SPARC_PC22
;
2799 code
= BFD_RELOC_SPARC_GOT22
;
2801 case BFD_RELOC_LO10
:
2802 if (fixp
->fx_addsy
!= NULL
2803 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2804 code
= BFD_RELOC_SPARC_PC10
;
2806 code
= BFD_RELOC_SPARC_GOT10
;
2808 case BFD_RELOC_SPARC13
:
2809 code
= BFD_RELOC_SPARC_GOT13
;
2815 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2817 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2818 if (reloc
->howto
== 0)
2820 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2821 _("internal error: can't export reloc type %d (`%s')"),
2822 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
2826 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2829 if (reloc
->howto
->pc_relative
== 0
2830 || code
== BFD_RELOC_SPARC_PC10
2831 || code
== BFD_RELOC_SPARC_PC22
)
2832 reloc
->addend
= fixp
->fx_addnumber
;
2834 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
2836 #else /* elf or coff */
2838 if (reloc
->howto
->pc_relative
== 0
2839 || code
== BFD_RELOC_SPARC_PC10
2840 || code
== BFD_RELOC_SPARC_PC22
)
2841 reloc
->addend
= fixp
->fx_addnumber
;
2842 else if ((fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2843 reloc
->addend
= (section
->vma
2844 + fixp
->fx_addnumber
2845 + md_pcrel_from (fixp
));
2847 reloc
->addend
= fixp
->fx_offset
;
2853 /* We have no need to default values of symbols. */
2857 md_undefined_symbol (name
)
2861 } /* md_undefined_symbol() */
2863 /* Round up a section size to the appropriate boundary. */
2865 md_section_align (segment
, size
)
2870 /* This is not right for ELF; a.out wants it, and COFF will force
2871 the alignment anyways. */
2872 valueT align
= ((valueT
) 1
2873 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
2875 /* turn alignment value into a mask */
2877 newsize
= (size
+ align
) & ~align
;
2884 /* Exactly what point is a PC-relative offset relative TO?
2885 On the sparc, they're relative to the address of the offset, plus
2886 its size. This gets us to the following instruction.
2887 (??? Is this right? FIXME-SOON) */
2889 md_pcrel_from (fixP
)
2894 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2895 if (! sparc_pic_code
2896 || fixP
->fx_addsy
== NULL
2897 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2898 ret
+= fixP
->fx_size
;
2903 * sort of like s_lcomm
2907 static int max_alignment
= 15;
2922 name
= input_line_pointer
;
2923 c
= get_symbol_end ();
2924 p
= input_line_pointer
;
2928 if (*input_line_pointer
!= ',')
2930 as_bad (_("Expected comma after name"));
2931 ignore_rest_of_line ();
2935 ++input_line_pointer
;
2937 if ((size
= get_absolute_expression ()) < 0)
2939 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
2940 ignore_rest_of_line ();
2945 symbolP
= symbol_find_or_make (name
);
2948 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
2949 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
2951 as_bad (_("bad .reserve segment -- expected BSS segment"));
2955 if (input_line_pointer
[2] == '.')
2956 input_line_pointer
+= 7;
2958 input_line_pointer
+= 6;
2961 if (*input_line_pointer
== ',')
2963 ++input_line_pointer
;
2966 if (*input_line_pointer
== '\n')
2968 as_bad (_("Missing alignment"));
2972 align
= get_absolute_expression ();
2974 if (align
> max_alignment
)
2976 align
= max_alignment
;
2977 as_warn (_("Alignment too large: %d. assumed."), align
);
2983 as_warn (_("Alignment negative. 0 assumed."));
2986 record_alignment (bss_section
, align
);
2988 /* convert to a power of 2 alignment */
2989 for (temp
= 0; (align
& 1) == 0; align
>>= 1, ++temp
);;
2993 as_bad (_("Alignment not a power of 2"));
2994 ignore_rest_of_line ();
2996 } /* not a power of two */
2999 } /* if has optional alignment */
3003 if (!S_IS_DEFINED (symbolP
)
3005 && S_GET_OTHER (symbolP
) == 0
3006 && S_GET_DESC (symbolP
) == 0
3013 segT current_seg
= now_seg
;
3014 subsegT current_subseg
= now_subseg
;
3016 subseg_set (bss_section
, 1); /* switch to bss */
3019 frag_align (align
, 0, 0); /* do alignment */
3021 /* detach from old frag */
3022 if (S_GET_SEGMENT(symbolP
) == bss_section
)
3023 symbolP
->sy_frag
->fr_symbol
= NULL
;
3025 symbolP
->sy_frag
= frag_now
;
3026 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
3027 (offsetT
) size
, (char *)0);
3030 S_SET_SEGMENT (symbolP
, bss_section
);
3032 subseg_set (current_seg
, current_subseg
);
3037 as_warn("Ignoring attempt to re-define symbol %s",
3038 S_GET_NAME (symbolP
));
3039 } /* if not redefining */
3041 demand_empty_rest_of_line ();
3054 name
= input_line_pointer
;
3055 c
= get_symbol_end ();
3056 /* just after name is now '\0' */
3057 p
= input_line_pointer
;
3060 if (*input_line_pointer
!= ',')
3062 as_bad (_("Expected comma after symbol-name"));
3063 ignore_rest_of_line ();
3066 input_line_pointer
++; /* skip ',' */
3067 if ((temp
= get_absolute_expression ()) < 0)
3069 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp
);
3070 ignore_rest_of_line ();
3075 symbolP
= symbol_find_or_make (name
);
3077 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3079 as_bad (_("Ignoring attempt to re-define symbol"));
3080 ignore_rest_of_line ();
3083 if (S_GET_VALUE (symbolP
) != 0)
3085 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3087 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3088 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3094 S_SET_VALUE (symbolP
, (valueT
) size
);
3095 S_SET_EXTERNAL (symbolP
);
3098 know (symbolP
->sy_frag
== &zero_address_frag
);
3099 if (*input_line_pointer
!= ',')
3101 as_bad (_("Expected comma after common length"));
3102 ignore_rest_of_line ();
3105 input_line_pointer
++;
3107 if (*input_line_pointer
!= '"')
3109 temp
= get_absolute_expression ();
3111 if (temp
> max_alignment
)
3113 temp
= max_alignment
;
3114 as_warn (_("Common alignment too large: %d. assumed"), temp
);
3120 as_warn (_("Common alignment negative; 0 assumed"));
3131 old_subsec
= now_subseg
;
3133 record_alignment (bss_section
, align
);
3134 subseg_set (bss_section
, 0);
3136 frag_align (align
, 0, 0);
3137 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3138 symbolP
->sy_frag
->fr_symbol
= 0;
3139 symbolP
->sy_frag
= frag_now
;
3140 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3141 (offsetT
) size
, (char *) 0);
3143 S_SET_SEGMENT (symbolP
, bss_section
);
3144 S_CLEAR_EXTERNAL (symbolP
);
3145 subseg_set (old_sec
, old_subsec
);
3151 S_SET_VALUE (symbolP
, (valueT
) size
);
3153 S_SET_ALIGN (symbolP
, temp
);
3155 S_SET_EXTERNAL (symbolP
);
3156 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3161 input_line_pointer
++;
3162 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3163 if (*input_line_pointer
== '.')
3164 input_line_pointer
++;
3165 /* @@ Some say data, some say bss. */
3166 if (strncmp (input_line_pointer
, "bss\"", 4)
3167 && strncmp (input_line_pointer
, "data\"", 5))
3169 while (*--input_line_pointer
!= '"')
3171 input_line_pointer
--;
3172 goto bad_common_segment
;
3174 while (*input_line_pointer
++ != '"')
3176 goto allocate_common
;
3179 #ifdef BFD_ASSEMBLER
3180 symbolP
->bsym
->flags
|= BSF_OBJECT
;
3183 demand_empty_rest_of_line ();
3188 p
= input_line_pointer
;
3189 while (*p
&& *p
!= '\n')
3193 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3195 input_line_pointer
= p
;
3196 ignore_rest_of_line ();
3201 /* Handle the .empty pseudo-op. This supresses the warnings about
3202 invalid delay slot usage. */
3208 /* The easy way to implement is to just forget about the last
3218 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3220 input_line_pointer
+= 6;
3224 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3226 input_line_pointer
+= 6;
3230 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3232 input_line_pointer
+= 7;
3236 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3238 input_line_pointer
+= 5;
3239 /* We only support 2 segments -- text and data -- for now, so
3240 things in the "bss segment" will have to go into data for now.
3241 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3242 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
3245 as_bad (_("Unknown segment type"));
3246 demand_empty_rest_of_line ();
3252 subseg_set (data_section
, 1);
3253 demand_empty_rest_of_line ();
3260 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3262 ++input_line_pointer
;
3264 ++input_line_pointer
;
3267 /* This static variable is set by s_uacons to tell sparc_cons_align
3268 that the expession does not need to be aligned. */
3270 static int sparc_no_align_cons
= 0;
3272 /* This handles the unaligned space allocation pseudo-ops, such as
3273 .uaword. .uaword is just like .word, but the value does not need
3280 /* Tell sparc_cons_align not to align this value. */
3281 sparc_no_align_cons
= 1;
3285 /* If the --enforce-aligned-data option is used, we require .word,
3286 et. al., to be aligned correctly. We do it by setting up an
3287 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3288 no unexpected alignment was introduced.
3290 The SunOS and Solaris native assemblers enforce aligned data by
3291 default. We don't want to do that, because gcc can deliberately
3292 generate misaligned data if the packed attribute is used. Instead,
3293 we permit misaligned data by default, and permit the user to set an
3294 option to check for it. */
3297 sparc_cons_align (nbytes
)
3303 /* Only do this if we are enforcing aligned data. */
3304 if (! enforce_aligned_data
)
3307 if (sparc_no_align_cons
)
3309 /* This is an unaligned pseudo-op. */
3310 sparc_no_align_cons
= 0;
3315 while ((nbytes
& 1) == 0)
3324 if (now_seg
== absolute_section
)
3326 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
3327 as_bad (_("misaligned data"));
3331 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
3332 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
3334 record_alignment (now_seg
, nalign
);
3337 /* This is where we do the unexpected alignment check.
3338 This is called from HANDLE_ALIGN in tc-sparc.h. */
3341 sparc_handle_align (fragp
)
3344 if (fragp
->fr_type
== rs_align_code
&& !fragp
->fr_subtype
3345 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
3346 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
3347 if (fragp
->fr_type
== rs_align_code
&& fragp
->fr_subtype
== 1024)
3349 int count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
3351 if (count
>= 4 && !(count
& 3) && count
<= 1024 && !((long)(fragp
->fr_literal
+ fragp
->fr_fix
) & 3))
3353 unsigned *p
= (unsigned *)(fragp
->fr_literal
+ fragp
->fr_fix
);
3356 for (i
= 0; i
< count
; i
+= 4)
3357 *p
++ = 0x01000000; /* nop */
3358 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
3359 *(unsigned *)(fragp
->fr_literal
+ fragp
->fr_fix
) =
3360 0x30680000 | (count
>> 2); /* ba,a,pt %xcc, 1f */
3361 fragp
->fr_var
= count
;
3367 /* Some special processing for a Sparc ELF file. */
3370 sparc_elf_final_processing ()
3372 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3373 sort of BFD interface for this. */
3374 if (sparc_arch_size
== 64)
3375 switch (sparc_memory_model
)
3378 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
3381 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
3384 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
3385 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
3386 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
3387 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;