1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
25 #include "safe-ctype.h"
28 #include "opcode/sparc.h"
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
42 static void init_default_arch
PARAMS ((void));
43 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
44 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
45 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
46 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
47 static int sparc_ffs
PARAMS ((unsigned int));
48 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
49 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
50 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
51 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
52 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
53 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
54 static int parse_const_expr_arg
PARAMS ((char **, int *));
55 static int get_expression
PARAMS ((char *str
));
57 /* Default architecture. */
58 /* ??? The default value should be V8, but sparclite support was added
59 by making it the default. GCC now passes -Asparclite, so maybe sometime in
60 the future we can set this to V8. */
62 #define DEFAULT_ARCH "sparclite"
64 static char *default_arch
= DEFAULT_ARCH
;
66 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
68 static int default_init_p
;
70 /* Current architecture. We don't bump up unless necessary. */
71 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
73 /* The maximum architecture level we can bump up to.
74 In a 32 bit environment, don't allow bumping up to v9 by default.
75 The native assembler works this way. The user is required to pass
76 an explicit argument before we'll create v9 object files. However, if
77 we don't see any v9 insns, a v8plus object file is not created. */
78 static enum sparc_opcode_arch_val max_architecture
;
80 /* Either 32 or 64, selects file format. */
81 static int sparc_arch_size
;
82 /* Initial (default) value, recorded separately in case a user option
83 changes the value before md_show_usage is called. */
84 static int default_arch_size
;
87 /* The currently selected v9 memory model. Currently only used for
89 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
92 static int architecture_requested
;
93 static int warn_on_bump
;
95 /* If warn_on_bump and the needed architecture is higher than this
96 architecture, issue a warning. */
97 static enum sparc_opcode_arch_val warn_after_architecture
;
99 /* Non-zero if as should generate error if an undeclared g[23] register
100 has been used in -64. */
101 static int no_undeclared_regs
;
103 /* Non-zero if we should try to relax jumps and calls. */
104 static int sparc_relax
;
106 /* Non-zero if we are generating PIC code. */
109 /* Non-zero if we should give an error when misaligned data is seen. */
110 static int enforce_aligned_data
;
112 extern int target_big_endian
;
114 static int target_little_endian_data
;
116 /* Symbols for global registers on v9. */
117 static symbolS
*globals
[8];
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control
*op_hash
;
132 static int log2
PARAMS ((int));
133 static void s_data1
PARAMS ((void));
134 static void s_seg
PARAMS ((int));
135 static void s_proc
PARAMS ((int));
136 static void s_reserve
PARAMS ((int));
137 static void s_common
PARAMS ((int));
138 static void s_empty
PARAMS ((int));
139 static void s_uacons
PARAMS ((int));
140 static void s_ncons
PARAMS ((int));
142 static void s_register
PARAMS ((int));
145 const pseudo_typeS md_pseudo_table
[] =
147 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
148 {"common", s_common
, 0},
149 {"empty", s_empty
, 0},
150 {"global", s_globl
, 0},
152 {"nword", s_ncons
, 0},
153 {"optim", s_ignore
, 0},
155 {"reserve", s_reserve
, 0},
157 {"skip", s_space
, 0},
160 {"uahalf", s_uacons
, 2},
161 {"uaword", s_uacons
, 4},
162 {"uaxword", s_uacons
, 8},
164 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0},
165 {"loc", dwarf2_directive_loc
, 0},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons
, 2},
168 {"4byte", s_uacons
, 4},
169 {"8byte", s_uacons
, 8},
170 {"register", s_register
, 0},
175 /* Size of relocation record. */
176 const int md_reloc_size
= 12;
178 /* This array holds the chars that always start a comment. If the
179 pre-processor is disabled, these aren't very useful. */
180 const char comment_chars
[] = "!"; /* JF removed '|' from
183 /* This array holds the chars that only start a comment at the beginning of
184 a line. If the line seems to have the form '# 123 filename'
185 .line and .file directives will appear in the pre-processed output. */
186 /* Note that input_file.c hand checks for '#' at the beginning of the
187 first line of the input file. This is because the compiler outputs
188 #NO_APP at the beginning of its output. */
189 /* Also note that comments started like this one will always
190 work if '/' isn't otherwise defined. */
191 const char line_comment_chars
[] = "#";
193 const char line_separator_chars
[] = ";";
195 /* Chars that can be used to separate mant from exp in floating point
197 const char EXP_CHARS
[] = "eE";
199 /* Chars that mean this number is a floating point constant.
202 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
204 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
205 changed in read.c. Ideally it shouldn't have to know about it at all,
206 but nothing is ideal around here. */
208 #define isoctal(c) ((unsigned) ((c) - '0') < '8')
213 unsigned long opcode
;
214 struct nlist
*nlistp
;
218 bfd_reloc_code_real_type reloc
;
221 struct sparc_it the_insn
, set_insn
;
223 static void output_insn
224 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
226 /* Table of arguments to -A.
227 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
228 for this use. That table is for opcodes only. This table is for opcodes
231 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
232 v8plusa
, v9
, v9a
, v9b
, v9_64
};
234 static struct sparc_arch
{
237 enum sparc_arch_types arch_type
;
238 /* Default word size, as specified during configuration.
239 A value of zero means can't be used to specify default architecture. */
240 int default_arch_size
;
241 /* Allowable arg to -A? */
243 } sparc_arch_table
[] = {
244 { "v6", "v6", v6
, 0, 1 },
245 { "v7", "v7", v7
, 0, 1 },
246 { "v8", "v8", v8
, 32, 1 },
247 { "sparclet", "sparclet", sparclet
, 32, 1 },
248 { "sparclite", "sparclite", sparclite
, 32, 1 },
249 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
250 { "v8plus", "v9", v9
, 0, 1 },
251 { "v8plusa", "v9a", v9
, 0, 1 },
252 { "v8plusb", "v9b", v9
, 0, 1 },
253 { "v9", "v9", v9
, 0, 1 },
254 { "v9a", "v9a", v9
, 0, 1 },
255 { "v9b", "v9b", v9
, 0, 1 },
256 /* This exists to allow configure.in/Makefile.in to pass one
257 value to specify both the default machine and default word size. */
258 { "v9-64", "v9", v9
, 64, 0 },
259 { NULL
, NULL
, v8
, 0, 0 }
262 /* Variant of default_arch */
263 static enum sparc_arch_types default_arch_type
;
265 static struct sparc_arch
*
269 struct sparc_arch
*sa
;
271 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
272 if (strcmp (sa
->name
, name
) == 0)
274 if (sa
->name
== NULL
)
279 /* Initialize the default opcode arch and word size from the default
280 architecture name. */
285 struct sparc_arch
*sa
= lookup_arch (default_arch
);
288 || sa
->default_arch_size
== 0)
289 as_fatal (_("Invalid default architecture, broken assembler."));
291 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
292 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
293 as_fatal (_("Bad opcode table, broken assembler."));
294 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
296 default_arch_type
= sa
->arch_type
;
299 /* Called by TARGET_FORMAT. */
302 sparc_target_format ()
304 /* We don't get a chance to initialize anything before we're called,
305 so handle that now. */
306 if (! default_init_p
)
307 init_default_arch ();
311 return "a.out-sparc-netbsd";
314 if (target_big_endian
)
315 return "a.out-sunos-big";
316 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
317 return "a.out-sunos-big";
319 return "a.out-sparc-little";
321 return "a.out-sunos-big";
332 return "coff-sparc-lynx";
339 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
346 * Invocation line includes a switch not recognized by the base assembler.
347 * See if it's a processor-specific option. These are:
350 * Warn on architecture bumps. See also -A.
352 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
353 * Standard 32 bit architectures.
355 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
356 * This used to only mean 64 bits, but properly specifying it
357 * complicated gcc's ASM_SPECs, so now opcode selection is
358 * specified orthogonally to word size (except when specifying
359 * the default, but that is an internal implementation detail).
360 * -Av8plus, -Av8plusa, -Av8plusb
361 * Same as -Av9{,a,b}.
362 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
363 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
365 * -xarch=v9, -xarch=v9a, -xarch=v9b
366 * Same as -Av9{,a,b} -64, for compatibility with Sun's
369 * Select the architecture and possibly the file format.
370 * Instructions or features not supported by the selected
371 * architecture cause fatal errors.
373 * The default is to start at v6, and bump the architecture up
374 * whenever an instruction is seen at a higher level. In 32 bit
375 * environments, v9 is not bumped up to, the user must pass
378 * If -bump is specified, a warning is printing when bumping to
381 * If an architecture is specified, all instructions must match
382 * that architecture. Any higher level instructions are flagged
383 * as errors. Note that in the 32 bit environment specifying
384 * -Av8plus does not automatically create a v8plus object file, a
385 * v9 insn must be seen.
387 * If both an architecture and -bump are specified, the
388 * architecture starts at the specified level, but bumps are
389 * warnings. Note that we can't set `current_architecture' to
390 * the requested level in this case: in the 32 bit environment,
391 * we still must avoid creating v8plus object files unless v9
395 * Bumping between incompatible architectures is always an
396 * error. For example, from sparclite to v9.
400 const char *md_shortopts
= "A:K:VQ:sq";
403 const char *md_shortopts
= "A:k";
405 const char *md_shortopts
= "A:";
408 struct option md_longopts
[] = {
409 #define OPTION_BUMP (OPTION_MD_BASE)
410 {"bump", no_argument
, NULL
, OPTION_BUMP
},
411 #define OPTION_SPARC (OPTION_MD_BASE + 1)
412 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
413 #define OPTION_XARCH (OPTION_MD_BASE + 2)
414 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
416 #define OPTION_32 (OPTION_MD_BASE + 3)
417 {"32", no_argument
, NULL
, OPTION_32
},
418 #define OPTION_64 (OPTION_MD_BASE + 4)
419 {"64", no_argument
, NULL
, OPTION_64
},
420 #define OPTION_TSO (OPTION_MD_BASE + 5)
421 {"TSO", no_argument
, NULL
, OPTION_TSO
},
422 #define OPTION_PSO (OPTION_MD_BASE + 6)
423 {"PSO", no_argument
, NULL
, OPTION_PSO
},
424 #define OPTION_RMO (OPTION_MD_BASE + 7)
425 {"RMO", no_argument
, NULL
, OPTION_RMO
},
427 #ifdef SPARC_BIENDIAN
428 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
429 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
430 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
431 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
433 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
434 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
435 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
436 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
438 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
439 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
440 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
441 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
443 #define OPTION_RELAX (OPTION_MD_BASE + 14)
444 {"relax", no_argument
, NULL
, OPTION_RELAX
},
445 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
446 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
447 {NULL
, no_argument
, NULL
, 0}
450 size_t md_longopts_size
= sizeof (md_longopts
);
453 md_parse_option (c
, arg
)
457 /* We don't get a chance to initialize anything before we're called,
458 so handle that now. */
459 if (! default_init_p
)
460 init_default_arch ();
466 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
471 if (strncmp (arg
, "v9", 2) != 0)
472 md_parse_option (OPTION_32
, NULL
);
474 md_parse_option (OPTION_64
, NULL
);
480 struct sparc_arch
*sa
;
481 enum sparc_opcode_arch_val opcode_arch
;
483 sa
= lookup_arch (arg
);
485 || ! sa
->user_option_p
)
487 if (c
== OPTION_XARCH
)
488 as_bad (_("invalid architecture -xarch=%s"), arg
);
490 as_bad (_("invalid architecture -A%s"), arg
);
494 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
495 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
496 as_fatal (_("Bad opcode table, broken assembler."));
498 max_architecture
= opcode_arch
;
499 architecture_requested
= 1;
504 /* Ignore -sparc, used by SunOS make default .s.o rule. */
507 case OPTION_ENFORCE_ALIGNED_DATA
:
508 enforce_aligned_data
= 1;
511 #ifdef SPARC_BIENDIAN
512 case OPTION_LITTLE_ENDIAN
:
513 target_big_endian
= 0;
514 if (default_arch_type
!= sparclet
)
515 as_fatal ("This target does not support -EL");
517 case OPTION_LITTLE_ENDIAN_DATA
:
518 target_little_endian_data
= 1;
519 target_big_endian
= 0;
520 if (default_arch_type
!= sparc86x
521 && default_arch_type
!= v9
)
522 as_fatal ("This target does not support --little-endian-data");
524 case OPTION_BIG_ENDIAN
:
525 target_big_endian
= 1;
539 const char **list
, **l
;
541 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
542 list
= bfd_target_list ();
543 for (l
= list
; *l
!= NULL
; l
++)
545 if (sparc_arch_size
== 32)
547 if (strcmp (*l
, "elf32-sparc") == 0)
552 if (strcmp (*l
, "elf64-sparc") == 0)
557 as_fatal (_("No compiled in support for %d bit object file format"),
564 sparc_memory_model
= MM_TSO
;
568 sparc_memory_model
= MM_PSO
;
572 sparc_memory_model
= MM_RMO
;
580 /* Qy - do emit .comment
581 Qn - do not emit .comment. */
585 /* Use .stab instead of .stab.excl. */
589 /* quick -- Native assembler does fewer checks. */
593 if (strcmp (arg
, "PIC") != 0)
594 as_warn (_("Unrecognized option following -K"));
599 case OPTION_NO_UNDECLARED_REGS
:
600 no_undeclared_regs
= 1;
603 case OPTION_UNDECLARED_REGS
:
604 no_undeclared_regs
= 0;
612 case OPTION_NO_RELAX
:
624 md_show_usage (stream
)
627 const struct sparc_arch
*arch
;
630 /* We don't get a chance to initialize anything before we're called,
631 so handle that now. */
632 if (! default_init_p
)
633 init_default_arch ();
635 fprintf (stream
, _("SPARC options:\n"));
637 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
639 if (!arch
->user_option_p
)
641 if (arch
!= &sparc_arch_table
[0])
642 fprintf (stream
, " | ");
643 if (column
+ strlen (arch
->name
) > 70)
646 fputc ('\n', stream
);
648 column
+= 5 + 2 + strlen (arch
->name
);
649 fprintf (stream
, "-A%s", arch
->name
);
651 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
653 if (!arch
->user_option_p
)
655 fprintf (stream
, " | ");
656 if (column
+ strlen (arch
->name
) > 65)
659 fputc ('\n', stream
);
661 column
+= 5 + 7 + strlen (arch
->name
);
662 fprintf (stream
, "-xarch=%s", arch
->name
);
664 fprintf (stream
, _("\n\
665 specify variant of SPARC architecture\n\
666 -bump warn when assembler switches architectures\n\
668 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
669 -relax relax jumps and branches (default)\n\
670 -no-relax avoid changing any jumps and branches\n"));
672 fprintf (stream
, _("\
673 -k generate PIC\n"));
676 fprintf (stream
, _("\
677 -32 create 32 bit object file\n\
678 -64 create 64 bit object file\n"));
679 fprintf (stream
, _("\
680 [default is %d]\n"), default_arch_size
);
681 fprintf (stream
, _("\
682 -TSO use Total Store Ordering\n\
683 -PSO use Partial Store Ordering\n\
684 -RMO use Relaxed Memory Ordering\n"));
685 fprintf (stream
, _("\
686 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
687 fprintf (stream
, _("\
688 -KPIC generate PIC\n\
689 -V print assembler version number\n\
690 -undeclared-regs ignore application global register usage without\n\
691 appropriate .register directive (default)\n\
692 -no-undeclared-regs force error on application global register usage\n\
693 without appropriate .register directive\n\
698 #ifdef SPARC_BIENDIAN
699 fprintf (stream
, _("\
700 -EL generate code for a little endian machine\n\
701 -EB generate code for a big endian machine\n\
702 --little-endian-data generate code for a machine having big endian\n\
703 instructions and little endian data.\n"));
707 /* Native operand size opcode translation. */
713 } native_op_table
[] =
715 {"ldn", "ld", "ldx"},
716 {"ldna", "lda", "ldxa"},
717 {"stn", "st", "stx"},
718 {"stna", "sta", "stxa"},
719 {"slln", "sll", "sllx"},
720 {"srln", "srl", "srlx"},
721 {"sran", "sra", "srax"},
722 {"casn", "cas", "casx"},
723 {"casna", "casa", "casxa"},
724 {"clrn", "clr", "clrx"},
728 /* sparc64 priviledged registers. */
730 struct priv_reg_entry
736 struct priv_reg_entry priv_reg_table
[] =
755 {"", -1}, /* End marker. */
758 /* v9a specific asrs. */
760 struct priv_reg_entry v9a_asr_table
[] =
763 {"sys_tick_cmpr", 25},
771 {"clear_softint", 21},
772 {"", -1}, /* End marker. */
776 cmp_reg_entry (parg
, qarg
)
780 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
781 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
783 return strcmp (q
->name
, p
->name
);
786 /* This function is called once, at assembler startup time. It should
787 set up all the tables, etc. that the MD part of the assembler will
793 register const char *retval
= NULL
;
795 register unsigned int i
= 0;
797 /* We don't get a chance to initialize anything before md_parse_option
798 is called, and it may not be called, so handle default initialization
799 now if not already done. */
800 if (! default_init_p
)
801 init_default_arch ();
803 op_hash
= hash_new ();
805 while (i
< (unsigned int) sparc_num_opcodes
)
807 const char *name
= sparc_opcodes
[i
].name
;
808 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
811 as_bad (_("Internal error: can't hash `%s': %s\n"),
812 sparc_opcodes
[i
].name
, retval
);
817 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
819 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
820 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
825 while (i
< (unsigned int) sparc_num_opcodes
826 && !strcmp (sparc_opcodes
[i
].name
, name
));
829 for (i
= 0; native_op_table
[i
].name
; i
++)
831 const struct sparc_opcode
*insn
;
832 char *name
= ((sparc_arch_size
== 32)
833 ? native_op_table
[i
].name32
834 : native_op_table
[i
].name64
);
835 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
838 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
839 name
, native_op_table
[i
].name
);
844 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
847 as_bad (_("Internal error: can't hash `%s': %s\n"),
848 sparc_opcodes
[i
].name
, retval
);
855 as_fatal (_("Broken assembler. No assembly attempted."));
857 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
858 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
860 /* If -bump, record the architecture level at which we start issuing
861 warnings. The behaviour is different depending upon whether an
862 architecture was explicitly specified. If it wasn't, we issue warnings
863 for all upwards bumps. If it was, we don't start issuing warnings until
864 we need to bump beyond the requested architecture or when we bump between
865 conflicting architectures. */
868 && architecture_requested
)
870 /* `max_architecture' records the requested architecture.
871 Issue warnings if we go above it. */
872 warn_after_architecture
= max_architecture
;
874 /* Find the highest architecture level that doesn't conflict with
875 the requested one. */
876 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
877 max_architecture
> warn_after_architecture
;
879 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
880 warn_after_architecture
))
885 /* Called after all assembly has been done. */
890 unsigned long mach
= bfd_mach_sparc
;
892 if (sparc_arch_size
== 64)
893 switch (current_architecture
)
895 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
896 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
897 default: mach
= bfd_mach_sparc_v9
; break;
900 switch (current_architecture
)
902 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
903 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
904 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
905 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
906 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
907 be but for now it is (since that's the way it's always been
911 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
914 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
917 in_signed_range (val
, max
)
918 bfd_signed_vma val
, max
;
922 /* Sign-extend the value from the architecture word size, so that
923 0xffffffff is always considered -1 on sparc32. */
924 if (sparc_arch_size
== 32)
926 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
927 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
936 /* Return non-zero if VAL is in the range 0 to MAX. */
939 in_unsigned_range (val
, max
)
947 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
948 (e.g. -15 to +31). */
951 in_bitfield_range (val
, max
)
952 bfd_signed_vma val
, max
;
958 if (val
< ~(max
>> 1))
972 for (i
= 0; (mask
& 1) == 0; ++i
)
977 /* Implement big shift right. */
983 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
984 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
985 return val
>> amount
;
988 /* For communication between sparc_ip and get_expression. */
989 static char *expr_end
;
991 /* Values for `special_case'.
992 Instructions that require wierd handling because they're longer than
994 #define SPECIAL_CASE_NONE 0
995 #define SPECIAL_CASE_SET 1
996 #define SPECIAL_CASE_SETSW 2
997 #define SPECIAL_CASE_SETX 3
998 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
999 #define SPECIAL_CASE_FDIV 4
1001 /* Bit masks of various insns. */
1002 #define NOP_INSN 0x01000000
1003 #define OR_INSN 0x80100000
1004 #define XOR_INSN 0x80180000
1005 #define FMOVS_INSN 0x81A00020
1006 #define SETHI_INSN 0x01000000
1007 #define SLLX_INSN 0x81281000
1008 #define SRA_INSN 0x81380000
1010 /* The last instruction to be assembled. */
1011 static const struct sparc_opcode
*last_insn
;
1012 /* The assembled opcode of `last_insn'. */
1013 static unsigned long last_opcode
;
1015 /* Handle the set and setuw synthetic instructions. */
1018 synthetize_setuw (insn
)
1019 const struct sparc_opcode
*insn
;
1021 int need_hi22_p
= 0;
1022 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1024 if (the_insn
.exp
.X_op
== O_constant
)
1026 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1028 if (sizeof (offsetT
) > 4
1029 && (the_insn
.exp
.X_add_number
< 0
1030 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1031 as_warn (_("set: number not in 0..4294967295 range"));
1035 if (sizeof (offsetT
) > 4
1036 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1037 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1038 as_warn (_("set: number not in -2147483648..4294967295 range"));
1039 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1043 /* See if operand is absolute and small; skip sethi if so. */
1044 if (the_insn
.exp
.X_op
!= O_constant
1045 || the_insn
.exp
.X_add_number
>= (1 << 12)
1046 || the_insn
.exp
.X_add_number
< -(1 << 12))
1048 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1049 | ((the_insn
.exp
.X_add_number
>> 10)
1050 & (the_insn
.exp
.X_op
== O_constant
1052 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1053 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1054 output_insn (insn
, &the_insn
);
1058 /* See if operand has no low-order bits; skip OR if so. */
1059 if (the_insn
.exp
.X_op
!= O_constant
1060 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1063 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1065 | (the_insn
.exp
.X_add_number
1066 & (the_insn
.exp
.X_op
!= O_constant
1067 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1068 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1069 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1070 output_insn (insn
, &the_insn
);
1074 /* Handle the setsw synthetic instruction. */
1077 synthetize_setsw (insn
)
1078 const struct sparc_opcode
*insn
;
1082 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1084 if (the_insn
.exp
.X_op
!= O_constant
)
1086 synthetize_setuw (insn
);
1088 /* Need to sign extend it. */
1089 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1090 the_insn
.reloc
= BFD_RELOC_NONE
;
1091 output_insn (insn
, &the_insn
);
1095 if (sizeof (offsetT
) > 4
1096 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1097 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1098 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1100 low32
= the_insn
.exp
.X_add_number
;
1104 synthetize_setuw (insn
);
1110 the_insn
.reloc
= BFD_RELOC_NONE
;
1111 /* See if operand is absolute and small; skip sethi if so. */
1112 if (low32
< -(1 << 12))
1114 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1115 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1116 output_insn (insn
, &the_insn
);
1117 low32
= 0x1c00 | (low32
& 0x3ff);
1118 opc
= RS1 (rd
) | XOR_INSN
;
1121 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1122 | (low32
& 0x1fff));
1123 output_insn (insn
, &the_insn
);
1126 /* Handle the setsw synthetic instruction. */
1129 synthetize_setx (insn
)
1130 const struct sparc_opcode
*insn
;
1132 int upper32
, lower32
;
1133 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1134 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1136 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1137 int need_xor10_p
= 0;
1139 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1140 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1141 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1144 upper_dstreg
= tmpreg
;
1145 /* The tmp reg should not be the dst reg. */
1146 if (tmpreg
== dstreg
)
1147 as_warn (_("setx: temporary register same as destination register"));
1149 /* ??? Obviously there are other optimizations we can do
1150 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1151 doing some of these. Later. If you do change things, try to
1152 change all of this to be table driven as well. */
1153 /* What to output depends on the number if it's constant.
1154 Compute that first, then output what we've decided upon. */
1155 if (the_insn
.exp
.X_op
!= O_constant
)
1157 if (sparc_arch_size
== 32)
1159 /* When arch size is 32, we want setx to be equivalent
1160 to setuw for anything but constants. */
1161 the_insn
.exp
.X_add_number
&= 0xffffffff;
1162 synthetize_setuw (insn
);
1165 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1171 /* Reset X_add_number, we've extracted it as upper32/lower32.
1172 Otherwise fixup_segment will complain about not being able to
1173 write an 8 byte number in a 4 byte field. */
1174 the_insn
.exp
.X_add_number
= 0;
1176 /* Only need hh22 if `or' insn can't handle constant. */
1177 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1180 /* Does bottom part (after sethi) have bits? */
1181 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1182 /* No hh22, but does upper32 still have bits we can't set
1184 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1187 /* If the lower half is all zero, we build the upper half directly
1188 into the dst reg. */
1190 /* Need lower half if number is zero or 0xffffffff00000000. */
1191 || (! need_hh22_p
&& ! need_hm10_p
))
1193 /* No need for sethi if `or' insn can handle constant. */
1194 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1195 /* Note that we can't use a negative constant in the `or'
1196 insn unless the upper 32 bits are all ones. */
1197 || (lower32
< 0 && upper32
!= -1)
1198 || (lower32
>= 0 && upper32
== -1))
1201 if (need_hi22_p
&& upper32
== -1)
1204 /* Does bottom part (after sethi) have bits? */
1205 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1207 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1208 /* Need `or' if we didn't set anything else. */
1209 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1213 /* Output directly to dst reg if lower 32 bits are all zero. */
1214 upper_dstreg
= dstreg
;
1217 if (!upper_dstreg
&& dstreg
)
1218 as_warn (_("setx: illegal temporary register g0"));
1222 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1223 | ((upper32
>> 10) & 0x3fffff));
1224 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1225 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1226 output_insn (insn
, &the_insn
);
1231 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1232 | (((need_xor10_p
? ~lower32
: lower32
)
1233 >> 10) & 0x3fffff));
1234 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1235 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1236 output_insn (insn
, &the_insn
);
1241 the_insn
.opcode
= (OR_INSN
1242 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1245 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1246 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1247 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1248 output_insn (insn
, &the_insn
);
1253 /* FIXME: One nice optimization to do here is to OR the low part
1254 with the highpart if hi22 isn't needed and the low part is
1256 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1259 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1260 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1261 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1262 output_insn (insn
, &the_insn
);
1265 /* If we needed to build the upper part, shift it into place. */
1266 if (need_hh22_p
|| need_hm10_p
)
1268 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1270 the_insn
.reloc
= BFD_RELOC_NONE
;
1271 output_insn (insn
, &the_insn
);
1274 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1277 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1278 | 0x1c00 | (lower32
& 0x3ff));
1279 the_insn
.reloc
= BFD_RELOC_NONE
;
1280 output_insn (insn
, &the_insn
);
1283 /* If we needed to build both upper and lower parts, OR them together. */
1284 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1286 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1288 the_insn
.reloc
= BFD_RELOC_NONE
;
1289 output_insn (insn
, &the_insn
);
1293 /* Main entry point to assemble one instruction. */
1299 const struct sparc_opcode
*insn
;
1303 special_case
= sparc_ip (str
, &insn
);
1305 /* We warn about attempts to put a floating point branch in a delay slot,
1306 unless the delay slot has been annulled. */
1308 && last_insn
!= NULL
1309 && (insn
->flags
& F_FBR
) != 0
1310 && (last_insn
->flags
& F_DELAYED
) != 0
1311 /* ??? This test isn't completely accurate. We assume anything with
1312 F_{UNBR,CONDBR,FBR} set is annullable. */
1313 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1314 || (last_opcode
& ANNUL
) == 0))
1315 as_warn (_("FP branch in delay slot"));
1317 /* SPARC before v9 requires a nop instruction between a floating
1318 point instruction and a floating point branch. We insert one
1319 automatically, with a warning. */
1320 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1322 && last_insn
!= NULL
1323 && (insn
->flags
& F_FBR
) != 0
1324 && (last_insn
->flags
& F_FLOAT
) != 0)
1326 struct sparc_it nop_insn
;
1328 nop_insn
.opcode
= NOP_INSN
;
1329 nop_insn
.reloc
= BFD_RELOC_NONE
;
1330 output_insn (insn
, &nop_insn
);
1331 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1334 switch (special_case
)
1336 case SPECIAL_CASE_NONE
:
1338 output_insn (insn
, &the_insn
);
1341 case SPECIAL_CASE_SETSW
:
1342 synthetize_setsw (insn
);
1345 case SPECIAL_CASE_SET
:
1346 synthetize_setuw (insn
);
1349 case SPECIAL_CASE_SETX
:
1350 synthetize_setx (insn
);
1353 case SPECIAL_CASE_FDIV
:
1355 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1357 output_insn (insn
, &the_insn
);
1359 /* According to information leaked from Sun, the "fdiv" instructions
1360 on early SPARC machines would produce incorrect results sometimes.
1361 The workaround is to add an fmovs of the destination register to
1362 itself just after the instruction. This was true on machines
1363 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1364 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1365 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1366 output_insn (insn
, &the_insn
);
1371 as_fatal (_("failed special case insn sanity check"));
1375 /* Subroutine of md_assemble to do the actual parsing. */
1378 sparc_ip (str
, pinsn
)
1380 const struct sparc_opcode
**pinsn
;
1382 char *error_message
= "";
1386 const struct sparc_opcode
*insn
;
1388 unsigned long opcode
;
1389 unsigned int mask
= 0;
1393 int special_case
= SPECIAL_CASE_NONE
;
1400 while (ISLOWER (*s
) || ISDIGIT (*s
));
1417 as_fatal (_("Unknown opcode: `%s'"), str
);
1419 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1423 as_bad (_("Unknown opcode: `%s'"), str
);
1424 return special_case
;
1434 opcode
= insn
->match
;
1435 memset (&the_insn
, '\0', sizeof (the_insn
));
1436 the_insn
.reloc
= BFD_RELOC_NONE
;
1439 /* Build the opcode, checking as we go to make sure that the
1441 for (args
= insn
->args
;; ++args
)
1449 /* Parse a series of masks. */
1456 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1459 error_message
= _(": invalid membar mask name");
1465 if (*s
== '|' || *s
== '+')
1473 if (! parse_const_expr_arg (&s
, &kmask
))
1475 error_message
= _(": invalid membar mask expression");
1478 if (kmask
< 0 || kmask
> 127)
1480 error_message
= _(": invalid membar mask number");
1485 opcode
|= MEMBAR (kmask
);
1493 if (! parse_const_expr_arg (&s
, &smask
))
1495 error_message
= _(": invalid siam mode expression");
1498 if (smask
< 0 || smask
> 7)
1500 error_message
= _(": invalid siam mode number");
1511 /* Parse a prefetch function. */
1514 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1516 error_message
= _(": invalid prefetch function name");
1522 if (! parse_const_expr_arg (&s
, &fcn
))
1524 error_message
= _(": invalid prefetch function expression");
1527 if (fcn
< 0 || fcn
> 31)
1529 error_message
= _(": invalid prefetch function number");
1539 /* Parse a sparc64 privileged register. */
1542 struct priv_reg_entry
*p
= priv_reg_table
;
1543 unsigned int len
= 9999999; /* Init to make gcc happy. */
1546 while (p
->name
[0] > s
[0])
1548 while (p
->name
[0] == s
[0])
1550 len
= strlen (p
->name
);
1551 if (strncmp (p
->name
, s
, len
) == 0)
1555 if (p
->name
[0] != s
[0])
1557 error_message
= _(": unrecognizable privileged register");
1561 opcode
|= (p
->regnum
<< 14);
1563 opcode
|= (p
->regnum
<< 25);
1569 error_message
= _(": unrecognizable privileged register");
1575 /* Parse a v9a/v9b ancillary state register. */
1578 struct priv_reg_entry
*p
= v9a_asr_table
;
1579 unsigned int len
= 9999999; /* Init to make gcc happy. */
1582 while (p
->name
[0] > s
[0])
1584 while (p
->name
[0] == s
[0])
1586 len
= strlen (p
->name
);
1587 if (strncmp (p
->name
, s
, len
) == 0)
1591 if (p
->name
[0] != s
[0])
1593 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1596 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1598 error_message
= _(": rd on write only ancillary state register");
1602 && (insn
->architecture
1603 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1605 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1606 error_message
= _(": unrecognizable v9a ancillary state register");
1610 opcode
|= (p
->regnum
<< 14);
1612 opcode
|= (p
->regnum
<< 25);
1618 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1624 if (strncmp (s
, "%asr", 4) == 0)
1632 while (ISDIGIT (*s
))
1634 num
= num
* 10 + *s
- '0';
1638 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1640 if (num
< 16 || 31 < num
)
1642 error_message
= _(": asr number must be between 16 and 31");
1648 if (num
< 0 || 31 < num
)
1650 error_message
= _(": asr number must be between 0 and 31");
1655 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1660 error_message
= _(": expecting %asrN");
1667 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1671 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1675 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1676 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1677 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1679 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1680 /* These fields are unsigned, but for upward compatibility,
1681 allow negative values as well. */
1685 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1686 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1687 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1689 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1690 /* These fields are unsigned, but for upward compatibility,
1691 allow negative values as well. */
1695 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1700 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1705 if (*s
== 'p' && s
[1] == 'n')
1713 if (*s
== 'p' && s
[1] == 't')
1725 if (strncmp (s
, "%icc", 4) == 0)
1737 if (strncmp (s
, "%xcc", 4) == 0)
1749 if (strncmp (s
, "%fcc0", 5) == 0)
1761 if (strncmp (s
, "%fcc1", 5) == 0)
1773 if (strncmp (s
, "%fcc2", 5) == 0)
1785 if (strncmp (s
, "%fcc3", 5) == 0)
1793 if (strncmp (s
, "%pc", 3) == 0)
1801 if (strncmp (s
, "%tick", 5) == 0)
1808 case '\0': /* End of args. */
1809 if (s
[0] == ',' && s
[1] == '%')
1811 static const struct tls_ops
{
1812 /* The name as it appears in assembler. */
1814 /* strlen (name), precomputed for speed */
1816 /* The reloc this pseudo-op translates to. */
1821 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
1822 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
1823 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
1824 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
1825 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
1826 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
1827 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
1828 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 }
1830 const struct tls_ops
*o
;
1834 for (o
= tls_ops
; o
->name
; o
++)
1835 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
1837 if (o
->name
== NULL
)
1840 if (s
[o
->len
+ 2] != '(')
1842 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1843 return special_case
;
1846 if (! o
->call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
1848 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1850 return special_case
;
1854 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
1855 || the_insn
.exp
.X_add_number
!= 0
1856 || the_insn
.exp
.X_add_symbol
1857 != symbol_find_or_make ("__tls_get_addr")))
1859 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1861 return special_case
;
1864 the_insn
.reloc
= o
->reloc
;
1865 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
1868 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
1871 else if (*s1
== ')')
1880 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1881 return special_case
;
1885 (void) get_expression (s
);
1905 case '[': /* These must match exactly. */
1913 case '#': /* Must be at least one digit. */
1916 while (ISDIGIT (*s
))
1924 case 'C': /* Coprocessor state register. */
1925 if (strncmp (s
, "%csr", 4) == 0)
1932 case 'b': /* Next operand is a coprocessor register. */
1935 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
1940 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1954 opcode
|= mask
<< 14;
1962 opcode
|= mask
<< 25;
1968 case 'r': /* next operand must be a register */
1978 case 'f': /* frame pointer */
1986 case 'g': /* global register */
1995 case 'i': /* in register */
1999 mask
= c
- '0' + 24;
2004 case 'l': /* local register */
2008 mask
= (c
- '0' + 16);
2013 case 'o': /* out register */
2017 mask
= (c
- '0' + 8);
2022 case 's': /* stack pointer */
2030 case 'r': /* any register */
2031 if (!ISDIGIT ((c
= *s
++)))
2048 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2064 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2065 && no_undeclared_regs
&& ! globals
[mask
])
2066 as_bad (_("detected global register use not covered by .register pseudo-op"));
2068 /* Got the register, now figure out where
2069 it goes in the opcode. */
2073 opcode
|= mask
<< 14;
2081 opcode
|= mask
<< 25;
2085 opcode
|= (mask
<< 25) | (mask
<< 14);
2089 opcode
|= (mask
<< 25) | (mask
<< 0);
2095 case 'e': /* next operand is a floating point register */
2110 && ((format
= *s
) == 'f')
2113 for (mask
= 0; ISDIGIT (*s
); ++s
)
2115 mask
= 10 * mask
+ (*s
- '0');
2116 } /* read the number */
2124 } /* register must be even numbered */
2132 } /* register must be multiple of 4 */
2136 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2137 error_message
= _(": There are only 64 f registers; [0-63]");
2139 error_message
= _(": There are only 32 f registers; [0-31]");
2142 else if (mask
>= 32)
2144 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2147 mask
-= 31; /* wrap high bit */
2151 error_message
= _(": There are only 32 f registers; [0-31]");
2159 } /* if not an 'f' register. */
2166 opcode
|= RS1 (mask
);
2172 opcode
|= RS2 (mask
);
2178 opcode
|= RD (mask
);
2187 if (strncmp (s
, "%fsr", 4) == 0)
2194 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2195 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2198 case 'l': /* 22 bit PC relative immediate */
2199 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2203 case 'L': /* 30 bit immediate */
2204 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2209 case 'n': /* 22 bit immediate */
2210 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2213 case 'i': /* 13 bit immediate */
2214 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2224 char *op_arg
= NULL
;
2226 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2228 /* Check for %hi, etc. */
2231 static const struct ops
{
2232 /* The name as it appears in assembler. */
2234 /* strlen (name), precomputed for speed */
2236 /* The reloc this pseudo-op translates to. */
2238 /* Non-zero if for v9 only. */
2240 /* Non-zero if can be used in pc-relative contexts. */
2241 int pcrel_p
;/*FIXME:wip*/
2243 /* hix/lox must appear before hi/lo so %hix won't be
2244 mistaken for %hi. */
2245 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2246 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2247 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2248 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2249 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2250 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2251 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2252 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2253 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2254 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2255 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2256 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2257 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2258 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2259 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2260 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2261 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2263 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2265 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2266 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2267 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2268 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2269 { NULL
, 0, 0, 0, 0 }
2271 const struct ops
*o
;
2273 for (o
= ops
; o
->name
; o
++)
2274 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2276 if (o
->name
== NULL
)
2279 if (s
[o
->len
+ 1] != '(')
2281 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2282 return special_case
;
2286 the_insn
.reloc
= o
->reloc
;
2291 /* Note that if the get_expression() fails, we will still
2292 have created U entries in the symbol table for the
2293 'symbols' in the input string. Try not to create U
2294 symbols for registers, etc. */
2296 /* This stuff checks to see if the expression ends in
2297 +%reg. If it does, it removes the register from
2298 the expression, and re-sets 's' to point to the
2305 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2308 else if (*s1
== ')')
2317 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2318 return special_case
;
2322 (void) get_expression (s
);
2325 if (*s
== ',' || *s
== ']' || !*s
)
2327 if (*s
!= '+' && *s
!= '-')
2329 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2330 return special_case
;
2334 op_exp
= the_insn
.exp
;
2335 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2338 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2341 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2343 if (s1
[-2] == '%' && s1
[-3] == '+')
2345 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2352 if (op_arg
&& s1
== s
+ 1)
2353 the_insn
.exp
.X_op
= O_absent
;
2355 (void) get_expression (s
);
2367 (void) get_expression (s
);
2375 the_insn
.exp2
= the_insn
.exp
;
2376 the_insn
.exp
= op_exp
;
2377 if (the_insn
.exp2
.X_op
== O_absent
)
2378 the_insn
.exp2
.X_op
= O_illegal
;
2379 else if (the_insn
.exp
.X_op
== O_absent
)
2381 the_insn
.exp
= the_insn
.exp2
;
2382 the_insn
.exp2
.X_op
= O_illegal
;
2384 else if (the_insn
.exp
.X_op
== O_constant
)
2386 valueT val
= the_insn
.exp
.X_add_number
;
2387 switch (the_insn
.reloc
)
2392 case BFD_RELOC_SPARC_HH22
:
2393 val
= BSR (val
, 32);
2396 case BFD_RELOC_SPARC_LM22
:
2397 case BFD_RELOC_HI22
:
2398 val
= (val
>> 10) & 0x3fffff;
2401 case BFD_RELOC_SPARC_HM10
:
2402 val
= BSR (val
, 32);
2405 case BFD_RELOC_LO10
:
2409 case BFD_RELOC_SPARC_H44
:
2414 case BFD_RELOC_SPARC_M44
:
2419 case BFD_RELOC_SPARC_L44
:
2423 case BFD_RELOC_SPARC_HIX22
:
2425 val
= (val
>> 10) & 0x3fffff;
2428 case BFD_RELOC_SPARC_LOX10
:
2429 val
= (val
& 0x3ff) | 0x1c00;
2432 the_insn
.exp
= the_insn
.exp2
;
2433 the_insn
.exp
.X_add_number
+= val
;
2434 the_insn
.exp2
.X_op
= O_illegal
;
2435 the_insn
.reloc
= old_reloc
;
2437 else if (the_insn
.exp2
.X_op
!= O_constant
)
2439 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2440 return special_case
;
2444 if (old_reloc
!= BFD_RELOC_SPARC13
2445 || the_insn
.reloc
!= BFD_RELOC_LO10
2446 || sparc_arch_size
!= 64
2449 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2450 return special_case
;
2452 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2456 /* Check for constants that don't require emitting a reloc. */
2457 if (the_insn
.exp
.X_op
== O_constant
2458 && the_insn
.exp
.X_add_symbol
== 0
2459 && the_insn
.exp
.X_op_symbol
== 0)
2461 /* For pc-relative call instructions, we reject
2462 constants to get better code. */
2464 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2465 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2467 error_message
= _(": PC-relative operand can't be a constant");
2471 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2472 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2474 error_message
= _(": TLS operand can't be a constant");
2478 /* Constants that won't fit are checked in md_apply_fix3
2479 and bfd_install_relocation.
2480 ??? It would be preferable to install the constants
2481 into the insn here and save having to create a fixS
2482 for each one. There already exists code to handle
2483 all the various cases (e.g. in md_apply_fix3 and
2484 bfd_install_relocation) so duplicating all that code
2485 here isn't right. */
2505 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2507 error_message
= _(": invalid ASI name");
2513 if (! parse_const_expr_arg (&s
, &asi
))
2515 error_message
= _(": invalid ASI expression");
2518 if (asi
< 0 || asi
> 255)
2520 error_message
= _(": invalid ASI number");
2524 opcode
|= ASI (asi
);
2526 } /* Alternate space. */
2529 if (strncmp (s
, "%psr", 4) == 0)
2536 case 'q': /* Floating point queue. */
2537 if (strncmp (s
, "%fq", 3) == 0)
2544 case 'Q': /* Coprocessor queue. */
2545 if (strncmp (s
, "%cq", 3) == 0)
2553 if (strcmp (str
, "set") == 0
2554 || strcmp (str
, "setuw") == 0)
2556 special_case
= SPECIAL_CASE_SET
;
2559 else if (strcmp (str
, "setsw") == 0)
2561 special_case
= SPECIAL_CASE_SETSW
;
2564 else if (strcmp (str
, "setx") == 0)
2566 special_case
= SPECIAL_CASE_SETX
;
2569 else if (strncmp (str
, "fdiv", 4) == 0)
2571 special_case
= SPECIAL_CASE_FDIV
;
2577 if (strncmp (s
, "%asi", 4) != 0)
2583 if (strncmp (s
, "%fprs", 5) != 0)
2589 if (strncmp (s
, "%ccr", 4) != 0)
2595 if (strncmp (s
, "%tbr", 4) != 0)
2601 if (strncmp (s
, "%wim", 4) != 0)
2608 char *push
= input_line_pointer
;
2611 input_line_pointer
= s
;
2613 if (e
.X_op
== O_constant
)
2615 int n
= e
.X_add_number
;
2616 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2617 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2619 opcode
|= e
.X_add_number
<< 5;
2622 as_bad (_("non-immediate OPF operand, ignored"));
2623 s
= input_line_pointer
;
2624 input_line_pointer
= push
;
2629 if (strncmp (s
, "%y", 2) != 0)
2637 /* Parse a sparclet cpreg. */
2639 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2641 error_message
= _(": invalid cpreg name");
2644 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2649 as_fatal (_("failed sanity check."));
2650 } /* switch on arg code. */
2652 /* Break out of for() loop. */
2654 } /* For each arg that we expect. */
2659 /* Args don't match. */
2660 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2661 && (insn
->name
== insn
[1].name
2662 || !strcmp (insn
->name
, insn
[1].name
)))
2670 as_bad (_("Illegal operands%s"), error_message
);
2671 return special_case
;
2676 /* We have a match. Now see if the architecture is OK. */
2677 int needed_arch_mask
= insn
->architecture
;
2682 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2683 if (! needed_arch_mask
)
2685 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2688 if (needed_arch_mask
2689 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2692 /* Can we bump up the architecture? */
2693 else if (needed_arch_mask
2694 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2696 enum sparc_opcode_arch_val needed_architecture
=
2697 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2698 & needed_arch_mask
);
2700 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2702 && needed_architecture
> warn_after_architecture
)
2704 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2705 sparc_opcode_archs
[current_architecture
].name
,
2706 sparc_opcode_archs
[needed_architecture
].name
,
2708 warn_after_architecture
= needed_architecture
;
2710 current_architecture
= needed_architecture
;
2713 /* ??? This seems to be a bit fragile. What if the next entry in
2714 the opcode table is the one we want and it is supported?
2715 It is possible to arrange the table today so that this can't
2716 happen but what about tomorrow? */
2719 int arch
, printed_one_p
= 0;
2721 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2723 /* Create a list of the architectures that support the insn. */
2724 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2726 arch
= sparc_ffs (needed_arch_mask
);
2727 while ((1 << arch
) <= needed_arch_mask
)
2729 if ((1 << arch
) & needed_arch_mask
)
2733 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2740 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2741 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2743 sparc_opcode_archs
[max_architecture
].name
);
2744 return special_case
;
2746 } /* If no match. */
2749 } /* Forever looking for a match. */
2751 the_insn
.opcode
= opcode
;
2752 return special_case
;
2755 /* Parse an argument that can be expressed as a keyword.
2756 (eg: #StoreStore or %ccfr).
2757 The result is a boolean indicating success.
2758 If successful, INPUT_POINTER is updated. */
2761 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2762 int (*lookup_fn
) PARAMS ((const char *));
2763 char **input_pointerP
;
2769 p
= *input_pointerP
;
2770 for (q
= p
+ (*p
== '#' || *p
== '%');
2771 ISALNUM (*q
) || *q
== '_';
2776 value
= (*lookup_fn
) (p
);
2781 *input_pointerP
= q
;
2785 /* Parse an argument that is a constant expression.
2786 The result is a boolean indicating success. */
2789 parse_const_expr_arg (input_pointerP
, valueP
)
2790 char **input_pointerP
;
2793 char *save
= input_line_pointer
;
2796 input_line_pointer
= *input_pointerP
;
2797 /* The next expression may be something other than a constant
2798 (say if we're not processing the right variant of the insn).
2799 Don't call expression unless we're sure it will succeed as it will
2800 signal an error (which we want to defer until later). */
2801 /* FIXME: It might be better to define md_operand and have it recognize
2802 things like %asi, etc. but continuing that route through to the end
2803 is a lot of work. */
2804 if (*input_line_pointer
== '%')
2806 input_line_pointer
= save
;
2810 *input_pointerP
= input_line_pointer
;
2811 input_line_pointer
= save
;
2812 if (exp
.X_op
!= O_constant
)
2814 *valueP
= exp
.X_add_number
;
2818 /* Subroutine of sparc_ip to parse an expression. */
2821 get_expression (str
)
2827 save_in
= input_line_pointer
;
2828 input_line_pointer
= str
;
2829 seg
= expression (&the_insn
.exp
);
2830 if (seg
!= absolute_section
2831 && seg
!= text_section
2832 && seg
!= data_section
2833 && seg
!= bss_section
2834 && seg
!= undefined_section
)
2836 the_insn
.error
= _("bad segment");
2837 expr_end
= input_line_pointer
;
2838 input_line_pointer
= save_in
;
2841 expr_end
= input_line_pointer
;
2842 input_line_pointer
= save_in
;
2846 /* Subroutine of md_assemble to output one insn. */
2849 output_insn (insn
, the_insn
)
2850 const struct sparc_opcode
*insn
;
2851 struct sparc_it
*the_insn
;
2853 char *toP
= frag_more (4);
2855 /* Put out the opcode. */
2856 if (INSN_BIG_ENDIAN
)
2857 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2859 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2861 /* Put out the symbol-dependent stuff. */
2862 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2864 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2865 (toP
- frag_now
->fr_literal
), /* Where. */
2870 /* Turn off overflow checking in fixup_segment. We'll do our
2871 own overflow checking in md_apply_fix3. This is necessary because
2872 the insn size is 4 and fixup_segment will signal an overflow for
2873 large 8 byte quantities. */
2874 fixP
->fx_no_overflow
= 1;
2875 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2876 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2880 last_opcode
= the_insn
->opcode
;
2883 dwarf2_emit_insn (4);
2887 /* This is identical to the md_atof in m68k.c. I think this is right,
2890 Turn a string in input_line_pointer into a floating point constant
2891 of type TYPE, and store the appropriate bytes in *LITP. The number
2892 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2893 returned, or NULL on OK. */
2895 /* Equal to MAX_PRECISION in atof-ieee.c. */
2896 #define MAX_LITTLENUMS 6
2899 md_atof (type
, litP
, sizeP
)
2905 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2936 return _("Bad call to MD_ATOF()");
2939 t
= atof_ieee (input_line_pointer
, type
, words
);
2941 input_line_pointer
= t
;
2942 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2944 if (target_big_endian
)
2946 for (i
= 0; i
< prec
; i
++)
2948 md_number_to_chars (litP
, (valueT
) words
[i
],
2949 sizeof (LITTLENUM_TYPE
));
2950 litP
+= sizeof (LITTLENUM_TYPE
);
2955 for (i
= prec
- 1; i
>= 0; i
--)
2957 md_number_to_chars (litP
, (valueT
) words
[i
],
2958 sizeof (LITTLENUM_TYPE
));
2959 litP
+= sizeof (LITTLENUM_TYPE
);
2966 /* Write a value out to the object file, using the appropriate
2970 md_number_to_chars (buf
, val
, n
)
2975 if (target_big_endian
)
2976 number_to_chars_bigendian (buf
, val
, n
);
2977 else if (target_little_endian_data
2978 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2979 /* Output debug words, which are not in allocated sections, as big
2981 number_to_chars_bigendian (buf
, val
, n
);
2982 else if (target_little_endian_data
|| ! target_big_endian
)
2983 number_to_chars_littleendian (buf
, val
, n
);
2986 /* Apply a fixS to the frags, now that we know the value it ought to
2990 md_apply_fix3 (fixP
, valP
, segment
)
2993 segT segment ATTRIBUTE_UNUSED
;
2995 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2996 offsetT val
= * (offsetT
*) valP
;
2999 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3001 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3004 /* SPARC ELF relocations don't use an addend in the data field. */
3005 if (fixP
->fx_addsy
!= NULL
)
3009 /* This is a hack. There should be a better way to
3010 handle this. Probably in terms of howto fields, once
3011 we can look at these fixups in terms of howtos. */
3012 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3013 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3016 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3017 generate a reloc, then we just want to let the reloc addend set
3018 the value. We do not want to also stuff the addend into the
3019 object file. Including the addend in the object file works when
3020 doing a static link, because the linker will ignore the object
3021 file contents. However, the dynamic linker does not ignore the
3022 object file contents. */
3023 if (fixP
->fx_addsy
!= NULL
3024 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3027 /* When generating PIC code, we do not want an addend for a reloc
3028 against a local symbol. We adjust fx_addnumber to cancel out the
3029 value already included in val, and to also cancel out the
3030 adjustment which bfd_install_relocation will create. */
3032 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3033 && fixP
->fx_addsy
!= NULL
3034 && ! S_IS_COMMON (fixP
->fx_addsy
)
3035 && symbol_section_p (fixP
->fx_addsy
))
3036 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3038 /* When generating PIC code, we need to fiddle to get
3039 bfd_install_relocation to do the right thing for a PC relative
3040 reloc against a local symbol which we are going to keep. */
3042 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3043 && fixP
->fx_addsy
!= NULL
3044 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3045 || S_IS_WEAK (fixP
->fx_addsy
))
3046 && S_IS_DEFINED (fixP
->fx_addsy
)
3047 && ! S_IS_COMMON (fixP
->fx_addsy
))
3050 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3054 /* If this is a data relocation, just output VAL. */
3056 if (fixP
->fx_r_type
== BFD_RELOC_16
3057 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3059 md_number_to_chars (buf
, val
, 2);
3061 else if (fixP
->fx_r_type
== BFD_RELOC_32
3062 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3063 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3065 md_number_to_chars (buf
, val
, 4);
3067 else if (fixP
->fx_r_type
== BFD_RELOC_64
3068 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3070 md_number_to_chars (buf
, val
, 8);
3072 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3073 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3080 /* It's a relocation against an instruction. */
3082 if (INSN_BIG_ENDIAN
)
3083 insn
= bfd_getb32 ((unsigned char *) buf
);
3085 insn
= bfd_getl32 ((unsigned char *) buf
);
3087 switch (fixP
->fx_r_type
)
3089 case BFD_RELOC_32_PCREL_S2
:
3091 /* FIXME: This increment-by-one deserves a comment of why it's
3093 if (! sparc_pic_code
3094 || fixP
->fx_addsy
== NULL
3095 || symbol_section_p (fixP
->fx_addsy
))
3098 insn
|= val
& 0x3fffffff;
3100 /* See if we have a delay slot. */
3101 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3105 #define XCC (2 << 20)
3106 #define COND(x) (((x)&0xf)<<25)
3107 #define CONDA COND(0x8)
3108 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3109 #define INSN_BA (F2(0,2) | CONDA)
3110 #define INSN_OR F3(2, 0x2, 0)
3111 #define INSN_NOP F2(0,4)
3115 /* If the instruction is a call with either:
3117 arithmetic instruction with rd == %o7
3118 where rs1 != %o7 and rs2 if it is register != %o7
3119 then we can optimize if the call destination is near
3120 by changing the call into a branch always. */
3121 if (INSN_BIG_ENDIAN
)
3122 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3124 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3125 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3127 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3128 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3129 || ((delay
& RD (~0)) != RD (O7
))))
3131 if ((delay
& RS1 (~0)) == RS1 (O7
)
3132 || ((delay
& F3I (~0)) == 0
3133 && (delay
& RS2 (~0)) == RS2 (O7
)))
3135 /* Ensure the branch will fit into simm22. */
3136 if ((val
& 0x3fe00000)
3137 && (val
& 0x3fe00000) != 0x3fe00000)
3139 /* Check if the arch is v9 and branch will fit
3141 if (((val
& 0x3c0000) == 0
3142 || (val
& 0x3c0000) == 0x3c0000)
3143 && (sparc_arch_size
== 64
3144 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3146 insn
= INSN_BPA
| (val
& 0x7ffff);
3149 insn
= INSN_BA
| (val
& 0x3fffff);
3150 if (fixP
->fx_where
>= 4
3151 && ((delay
& (0xffffffff ^ RS1 (~0)))
3152 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3157 if (INSN_BIG_ENDIAN
)
3158 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3160 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3161 if ((setter
& (0xffffffff ^ RD (~0)))
3162 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3169 If call foo was replaced with ba, replace
3170 or %rN, %g0, %o7 with nop. */
3171 reg
= (delay
& RS1 (~0)) >> 14;
3172 if (reg
!= ((setter
& RD (~0)) >> 25)
3173 || reg
== G0
|| reg
== O7
)
3176 if (INSN_BIG_ENDIAN
)
3177 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3179 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3184 case BFD_RELOC_SPARC_11
:
3185 if (! in_signed_range (val
, 0x7ff))
3186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3187 _("relocation overflow"));
3188 insn
|= val
& 0x7ff;
3191 case BFD_RELOC_SPARC_10
:
3192 if (! in_signed_range (val
, 0x3ff))
3193 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3194 _("relocation overflow"));
3195 insn
|= val
& 0x3ff;
3198 case BFD_RELOC_SPARC_7
:
3199 if (! in_bitfield_range (val
, 0x7f))
3200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3201 _("relocation overflow"));
3205 case BFD_RELOC_SPARC_6
:
3206 if (! in_bitfield_range (val
, 0x3f))
3207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3208 _("relocation overflow"));
3212 case BFD_RELOC_SPARC_5
:
3213 if (! in_bitfield_range (val
, 0x1f))
3214 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3215 _("relocation overflow"));
3219 case BFD_RELOC_SPARC_WDISP16
:
3220 /* FIXME: simplify. */
3221 if (((val
> 0) && (val
& ~0x3fffc))
3222 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
3223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3224 _("relocation overflow"));
3225 /* FIXME: The +1 deserves a comment. */
3226 val
= (val
>> 2) + 1;
3227 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3230 case BFD_RELOC_SPARC_WDISP19
:
3231 /* FIXME: simplify. */
3232 if (((val
> 0) && (val
& ~0x1ffffc))
3233 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
3234 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3235 _("relocation overflow"));
3236 /* FIXME: The +1 deserves a comment. */
3237 val
= (val
>> 2) + 1;
3238 insn
|= val
& 0x7ffff;
3241 case BFD_RELOC_SPARC_HH22
:
3242 val
= BSR (val
, 32);
3245 case BFD_RELOC_SPARC_LM22
:
3246 case BFD_RELOC_HI22
:
3247 if (!fixP
->fx_addsy
)
3248 insn
|= (val
>> 10) & 0x3fffff;
3250 /* FIXME: Need comment explaining why we do this. */
3254 case BFD_RELOC_SPARC22
:
3255 if (val
& ~0x003fffff)
3256 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3257 _("relocation overflow"));
3258 insn
|= (val
& 0x3fffff);
3261 case BFD_RELOC_SPARC_HM10
:
3262 val
= BSR (val
, 32);
3265 case BFD_RELOC_LO10
:
3266 if (!fixP
->fx_addsy
)
3267 insn
|= val
& 0x3ff;
3269 /* FIXME: Need comment explaining why we do this. */
3273 case BFD_RELOC_SPARC_OLO10
:
3275 val
+= fixP
->tc_fix_data
;
3278 case BFD_RELOC_SPARC13
:
3279 if (! in_signed_range (val
, 0x1fff))
3280 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3281 _("relocation overflow"));
3282 insn
|= val
& 0x1fff;
3285 case BFD_RELOC_SPARC_WDISP22
:
3286 val
= (val
>> 2) + 1;
3288 case BFD_RELOC_SPARC_BASE22
:
3289 insn
|= val
& 0x3fffff;
3292 case BFD_RELOC_SPARC_H44
:
3293 if (!fixP
->fx_addsy
)
3297 insn
|= tval
& 0x3fffff;
3301 case BFD_RELOC_SPARC_M44
:
3302 if (!fixP
->fx_addsy
)
3303 insn
|= (val
>> 12) & 0x3ff;
3306 case BFD_RELOC_SPARC_L44
:
3307 if (!fixP
->fx_addsy
)
3308 insn
|= val
& 0xfff;
3311 case BFD_RELOC_SPARC_HIX22
:
3312 if (!fixP
->fx_addsy
)
3314 val
^= ~(offsetT
) 0;
3315 insn
|= (val
>> 10) & 0x3fffff;
3319 case BFD_RELOC_SPARC_LOX10
:
3320 if (!fixP
->fx_addsy
)
3321 insn
|= 0x1c00 | (val
& 0x3ff);
3324 case BFD_RELOC_NONE
:
3326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3327 _("bad or unhandled relocation type: 0x%02x"),
3332 if (INSN_BIG_ENDIAN
)
3333 bfd_putb32 (insn
, (unsigned char *) buf
);
3335 bfd_putl32 (insn
, (unsigned char *) buf
);
3338 /* Are we finished with this relocation now? */
3339 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3343 /* Translate internal representation of relocation info to BFD target
3347 tc_gen_reloc (section
, fixp
)
3348 asection
*section ATTRIBUTE_UNUSED
;
3351 static arelent
*relocs
[3];
3353 bfd_reloc_code_real_type code
;
3355 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3358 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3359 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3360 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3362 switch (fixp
->fx_r_type
)
3366 case BFD_RELOC_HI22
:
3367 case BFD_RELOC_LO10
:
3368 case BFD_RELOC_32_PCREL_S2
:
3369 case BFD_RELOC_SPARC13
:
3370 case BFD_RELOC_SPARC22
:
3371 case BFD_RELOC_SPARC_BASE13
:
3372 case BFD_RELOC_SPARC_WDISP16
:
3373 case BFD_RELOC_SPARC_WDISP19
:
3374 case BFD_RELOC_SPARC_WDISP22
:
3376 case BFD_RELOC_SPARC_5
:
3377 case BFD_RELOC_SPARC_6
:
3378 case BFD_RELOC_SPARC_7
:
3379 case BFD_RELOC_SPARC_10
:
3380 case BFD_RELOC_SPARC_11
:
3381 case BFD_RELOC_SPARC_HH22
:
3382 case BFD_RELOC_SPARC_HM10
:
3383 case BFD_RELOC_SPARC_LM22
:
3384 case BFD_RELOC_SPARC_PC_HH22
:
3385 case BFD_RELOC_SPARC_PC_HM10
:
3386 case BFD_RELOC_SPARC_PC_LM22
:
3387 case BFD_RELOC_SPARC_H44
:
3388 case BFD_RELOC_SPARC_M44
:
3389 case BFD_RELOC_SPARC_L44
:
3390 case BFD_RELOC_SPARC_HIX22
:
3391 case BFD_RELOC_SPARC_LOX10
:
3392 case BFD_RELOC_SPARC_REV32
:
3393 case BFD_RELOC_SPARC_OLO10
:
3394 case BFD_RELOC_SPARC_UA16
:
3395 case BFD_RELOC_SPARC_UA32
:
3396 case BFD_RELOC_SPARC_UA64
:
3397 case BFD_RELOC_8_PCREL
:
3398 case BFD_RELOC_16_PCREL
:
3399 case BFD_RELOC_32_PCREL
:
3400 case BFD_RELOC_64_PCREL
:
3401 case BFD_RELOC_SPARC_PLT32
:
3402 case BFD_RELOC_SPARC_PLT64
:
3403 case BFD_RELOC_VTABLE_ENTRY
:
3404 case BFD_RELOC_VTABLE_INHERIT
:
3405 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3406 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3407 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3408 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3409 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3410 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3411 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3412 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3413 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3414 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3415 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3416 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3417 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3418 case BFD_RELOC_SPARC_TLS_IE_LD
:
3419 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3420 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3421 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3422 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3423 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3424 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3425 code
= fixp
->fx_r_type
;
3432 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3433 /* If we are generating PIC code, we need to generate a different
3437 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3439 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3442 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3448 case BFD_RELOC_32_PCREL_S2
:
3449 if (generic_force_reloc (fixp
))
3450 code
= BFD_RELOC_SPARC_WPLT30
;
3452 case BFD_RELOC_HI22
:
3453 if (fixp
->fx_addsy
!= NULL
3454 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3455 code
= BFD_RELOC_SPARC_PC22
;
3457 code
= BFD_RELOC_SPARC_GOT22
;
3459 case BFD_RELOC_LO10
:
3460 if (fixp
->fx_addsy
!= NULL
3461 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3462 code
= BFD_RELOC_SPARC_PC10
;
3464 code
= BFD_RELOC_SPARC_GOT10
;
3466 case BFD_RELOC_SPARC13
:
3467 code
= BFD_RELOC_SPARC_GOT13
;
3473 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3475 if (code
== BFD_RELOC_SPARC_OLO10
)
3476 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3478 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3479 if (reloc
->howto
== 0)
3481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3482 _("internal error: can't export reloc type %d (`%s')"),
3483 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3489 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3492 if (reloc
->howto
->pc_relative
== 0
3493 || code
== BFD_RELOC_SPARC_PC10
3494 || code
== BFD_RELOC_SPARC_PC22
)
3495 reloc
->addend
= fixp
->fx_addnumber
;
3496 else if (sparc_pic_code
3497 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3498 && fixp
->fx_addsy
!= NULL
3499 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3500 || S_IS_WEAK (fixp
->fx_addsy
))
3501 && S_IS_DEFINED (fixp
->fx_addsy
)
3502 && ! S_IS_COMMON (fixp
->fx_addsy
))
3503 reloc
->addend
= fixp
->fx_addnumber
;
3505 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3507 #else /* elf or coff */
3509 if (code
!= BFD_RELOC_32_PCREL_S2
3510 && code
!= BFD_RELOC_SPARC_WDISP22
3511 && code
!= BFD_RELOC_SPARC_WDISP16
3512 && code
!= BFD_RELOC_SPARC_WDISP19
3513 && code
!= BFD_RELOC_SPARC_WPLT30
3514 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3515 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3516 reloc
->addend
= fixp
->fx_addnumber
;
3517 else if (symbol_section_p (fixp
->fx_addsy
))
3518 reloc
->addend
= (section
->vma
3519 + fixp
->fx_addnumber
3520 + md_pcrel_from (fixp
));
3522 reloc
->addend
= fixp
->fx_offset
;
3525 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3526 on the same location. */
3527 if (code
== BFD_RELOC_SPARC_OLO10
)
3529 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3532 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3534 = symbol_get_bfdsym (section_symbol (absolute_section
));
3535 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3536 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3537 reloc
->addend
= fixp
->tc_fix_data
;
3543 /* We have no need to default values of symbols. */
3546 md_undefined_symbol (name
)
3547 char *name ATTRIBUTE_UNUSED
;
3552 /* Round up a section size to the appropriate boundary. */
3555 md_section_align (segment
, size
)
3556 segT segment ATTRIBUTE_UNUSED
;
3560 /* This is not right for ELF; a.out wants it, and COFF will force
3561 the alignment anyways. */
3562 valueT align
= ((valueT
) 1
3563 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3566 /* Turn alignment value into a mask. */
3568 newsize
= (size
+ align
) & ~align
;
3575 /* Exactly what point is a PC-relative offset relative TO?
3576 On the sparc, they're relative to the address of the offset, plus
3577 its size. This gets us to the following instruction.
3578 (??? Is this right? FIXME-SOON) */
3580 md_pcrel_from (fixP
)
3585 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3586 if (! sparc_pic_code
3587 || fixP
->fx_addsy
== NULL
3588 || symbol_section_p (fixP
->fx_addsy
))
3589 ret
+= fixP
->fx_size
;
3593 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3605 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3608 return (value
== 1) ? shift
: -1;
3611 /* Sort of like s_lcomm. */
3614 static int max_alignment
= 15;
3619 int ignore ATTRIBUTE_UNUSED
;
3629 name
= input_line_pointer
;
3630 c
= get_symbol_end ();
3631 p
= input_line_pointer
;
3635 if (*input_line_pointer
!= ',')
3637 as_bad (_("Expected comma after name"));
3638 ignore_rest_of_line ();
3642 ++input_line_pointer
;
3644 if ((size
= get_absolute_expression ()) < 0)
3646 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3647 ignore_rest_of_line ();
3652 symbolP
= symbol_find_or_make (name
);
3655 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3656 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3658 as_bad (_("bad .reserve segment -- expected BSS segment"));
3662 if (input_line_pointer
[2] == '.')
3663 input_line_pointer
+= 7;
3665 input_line_pointer
+= 6;
3668 if (*input_line_pointer
== ',')
3670 ++input_line_pointer
;
3673 if (*input_line_pointer
== '\n')
3675 as_bad (_("missing alignment"));
3676 ignore_rest_of_line ();
3680 align
= (int) get_absolute_expression ();
3683 if (align
> max_alignment
)
3685 align
= max_alignment
;
3686 as_warn (_("alignment too large; assuming %d"), align
);
3692 as_bad (_("negative alignment"));
3693 ignore_rest_of_line ();
3699 temp
= log2 (align
);
3702 as_bad (_("alignment not a power of 2"));
3703 ignore_rest_of_line ();
3710 record_alignment (bss_section
, align
);
3715 if (!S_IS_DEFINED (symbolP
)
3717 && S_GET_OTHER (symbolP
) == 0
3718 && S_GET_DESC (symbolP
) == 0
3725 segT current_seg
= now_seg
;
3726 subsegT current_subseg
= now_subseg
;
3728 /* Switch to bss. */
3729 subseg_set (bss_section
, 1);
3733 frag_align (align
, 0, 0);
3735 /* Detach from old frag. */
3736 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3737 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3739 symbol_set_frag (symbolP
, frag_now
);
3740 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3741 (offsetT
) size
, (char *) 0);
3744 S_SET_SEGMENT (symbolP
, bss_section
);
3746 subseg_set (current_seg
, current_subseg
);
3749 S_SET_SIZE (symbolP
, size
);
3755 as_warn ("Ignoring attempt to re-define symbol %s",
3756 S_GET_NAME (symbolP
));
3757 } /* if not redefining. */
3759 demand_empty_rest_of_line ();
3764 int ignore ATTRIBUTE_UNUSED
;
3772 name
= input_line_pointer
;
3773 c
= get_symbol_end ();
3774 /* Just after name is now '\0'. */
3775 p
= input_line_pointer
;
3778 if (*input_line_pointer
!= ',')
3780 as_bad (_("Expected comma after symbol-name"));
3781 ignore_rest_of_line ();
3786 input_line_pointer
++;
3788 if ((temp
= get_absolute_expression ()) < 0)
3790 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp
);
3791 ignore_rest_of_line ();
3796 symbolP
= symbol_find_or_make (name
);
3798 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3800 as_bad (_("Ignoring attempt to re-define symbol"));
3801 ignore_rest_of_line ();
3804 if (S_GET_VALUE (symbolP
) != 0)
3806 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3808 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3809 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3815 S_SET_VALUE (symbolP
, (valueT
) size
);
3816 S_SET_EXTERNAL (symbolP
);
3819 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3820 if (*input_line_pointer
!= ',')
3822 as_bad (_("Expected comma after common length"));
3823 ignore_rest_of_line ();
3826 input_line_pointer
++;
3828 if (*input_line_pointer
!= '"')
3830 temp
= get_absolute_expression ();
3833 if (temp
> max_alignment
)
3835 temp
= max_alignment
;
3836 as_warn (_("alignment too large; assuming %d"), temp
);
3842 as_bad (_("negative alignment"));
3843 ignore_rest_of_line ();
3848 if (symbol_get_obj (symbolP
)->local
)
3856 old_subsec
= now_subseg
;
3861 align
= log2 (temp
);
3865 as_bad (_("alignment not a power of 2"));
3866 ignore_rest_of_line ();
3870 record_alignment (bss_section
, align
);
3871 subseg_set (bss_section
, 0);
3873 frag_align (align
, 0, 0);
3874 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3875 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3876 symbol_set_frag (symbolP
, frag_now
);
3877 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3878 (offsetT
) size
, (char *) 0);
3880 S_SET_SEGMENT (symbolP
, bss_section
);
3881 S_CLEAR_EXTERNAL (symbolP
);
3882 S_SET_SIZE (symbolP
, size
);
3883 subseg_set (old_sec
, old_subsec
);
3886 #endif /* OBJ_ELF */
3889 S_SET_VALUE (symbolP
, (valueT
) size
);
3891 S_SET_ALIGN (symbolP
, temp
);
3892 S_SET_SIZE (symbolP
, size
);
3894 S_SET_EXTERNAL (symbolP
);
3895 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3900 input_line_pointer
++;
3901 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3902 if (*input_line_pointer
== '.')
3903 input_line_pointer
++;
3904 /* @@ Some say data, some say bss. */
3905 if (strncmp (input_line_pointer
, "bss\"", 4)
3906 && strncmp (input_line_pointer
, "data\"", 5))
3908 while (*--input_line_pointer
!= '"')
3910 input_line_pointer
--;
3911 goto bad_common_segment
;
3913 while (*input_line_pointer
++ != '"')
3915 goto allocate_common
;
3918 #ifdef BFD_ASSEMBLER
3919 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3922 demand_empty_rest_of_line ();
3927 p
= input_line_pointer
;
3928 while (*p
&& *p
!= '\n')
3932 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3934 input_line_pointer
= p
;
3935 ignore_rest_of_line ();
3940 /* Handle the .empty pseudo-op. This supresses the warnings about
3941 invalid delay slot usage. */
3945 int ignore ATTRIBUTE_UNUSED
;
3947 /* The easy way to implement is to just forget about the last
3954 int ignore ATTRIBUTE_UNUSED
;
3957 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3959 input_line_pointer
+= 6;
3963 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3965 input_line_pointer
+= 6;
3969 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3971 input_line_pointer
+= 7;
3975 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3977 input_line_pointer
+= 5;
3978 /* We only support 2 segments -- text and data -- for now, so
3979 things in the "bss segment" will have to go into data for now.
3980 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3981 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
3984 as_bad (_("Unknown segment type"));
3985 demand_empty_rest_of_line ();
3991 subseg_set (data_section
, 1);
3992 demand_empty_rest_of_line ();
3997 int ignore ATTRIBUTE_UNUSED
;
3999 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4001 ++input_line_pointer
;
4003 ++input_line_pointer
;
4006 /* This static variable is set by s_uacons to tell sparc_cons_align
4007 that the expession does not need to be aligned. */
4009 static int sparc_no_align_cons
= 0;
4011 /* This static variable is set by sparc_cons to emit requested types
4012 of relocations in cons_fix_new_sparc. */
4014 static const char *sparc_cons_special_reloc
;
4016 /* This handles the unaligned space allocation pseudo-ops, such as
4017 .uaword. .uaword is just like .word, but the value does not need
4024 /* Tell sparc_cons_align not to align this value. */
4025 sparc_no_align_cons
= 1;
4027 sparc_no_align_cons
= 0;
4030 /* This handles the native word allocation pseudo-op .nword.
4031 For sparc_arch_size 32 it is equivalent to .word, for
4032 sparc_arch_size 64 it is equivalent to .xword. */
4036 int bytes ATTRIBUTE_UNUSED
;
4038 cons (sparc_arch_size
== 32 ? 4 : 8);
4042 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4046 .register %g[2367],{#scratch|symbolname|#ignore}
4051 int ignore ATTRIBUTE_UNUSED
;
4056 const char *regname
;
4058 if (input_line_pointer
[0] != '%'
4059 || input_line_pointer
[1] != 'g'
4060 || ((input_line_pointer
[2] & ~1) != '2'
4061 && (input_line_pointer
[2] & ~1) != '6')
4062 || input_line_pointer
[3] != ',')
4063 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4064 reg
= input_line_pointer
[2] - '0';
4065 input_line_pointer
+= 4;
4067 if (*input_line_pointer
== '#')
4069 ++input_line_pointer
;
4070 regname
= input_line_pointer
;
4071 c
= get_symbol_end ();
4072 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4073 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4074 if (regname
[0] == 'i')
4081 regname
= input_line_pointer
;
4082 c
= get_symbol_end ();
4084 if (sparc_arch_size
== 64)
4088 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4089 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4090 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4091 as_bad (_("redefinition of global register"));
4095 if (regname
== NULL
)
4096 globals
[reg
] = (symbolS
*) 1;
4101 if (symbol_find (regname
))
4102 as_bad (_("Register symbol %s already defined."),
4105 globals
[reg
] = symbol_make (regname
);
4106 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4108 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4109 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4110 flags
|= BSF_GLOBAL
;
4111 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4112 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4113 S_SET_ALIGN (globals
[reg
], reg
);
4114 S_SET_SIZE (globals
[reg
], 0);
4115 /* Although we actually want undefined_section here,
4116 we have to use absolute_section, because otherwise
4117 generic as code will make it a COM section.
4118 We fix this up in sparc_adjust_symtab. */
4119 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4120 S_SET_OTHER (globals
[reg
], 0);
4121 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4122 ->internal_elf_sym
.st_info
=
4123 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4124 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4125 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4130 *input_line_pointer
= c
;
4132 demand_empty_rest_of_line ();
4135 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4136 symbols which need it. */
4139 sparc_adjust_symtab ()
4143 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4145 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4146 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4149 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4150 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4153 S_SET_SEGMENT (sym
, undefined_section
);
4158 /* If the --enforce-aligned-data option is used, we require .word,
4159 et. al., to be aligned correctly. We do it by setting up an
4160 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4161 no unexpected alignment was introduced.
4163 The SunOS and Solaris native assemblers enforce aligned data by
4164 default. We don't want to do that, because gcc can deliberately
4165 generate misaligned data if the packed attribute is used. Instead,
4166 we permit misaligned data by default, and permit the user to set an
4167 option to check for it. */
4170 sparc_cons_align (nbytes
)
4176 /* Only do this if we are enforcing aligned data. */
4177 if (! enforce_aligned_data
)
4180 /* Don't align if this is an unaligned pseudo-op. */
4181 if (sparc_no_align_cons
)
4184 nalign
= log2 (nbytes
);
4188 assert (nalign
> 0);
4190 if (now_seg
== absolute_section
)
4192 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4193 as_bad (_("misaligned data"));
4197 p
= frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4198 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4200 record_alignment (now_seg
, nalign
);
4203 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4206 sparc_handle_align (fragp
)
4212 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4214 switch (fragp
->fr_type
)
4218 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4222 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4233 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4235 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4236 if (INSN_BIG_ENDIAN
)
4237 number_to_chars_bigendian (p
, wval
, 4);
4239 number_to_chars_littleendian (p
, wval
, 4);
4245 if (INSN_BIG_ENDIAN
)
4246 number_to_chars_bigendian (p
, 0x01000000, 4);
4248 number_to_chars_littleendian (p
, 0x01000000, 4);
4250 fragp
->fr_fix
+= fix
;
4260 /* Some special processing for a Sparc ELF file. */
4263 sparc_elf_final_processing ()
4265 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4266 sort of BFD interface for this. */
4267 if (sparc_arch_size
== 64)
4269 switch (sparc_memory_model
)
4272 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4275 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4281 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4282 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4283 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4284 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4285 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4286 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4290 sparc_cons (exp
, size
)
4297 sparc_cons_special_reloc
= NULL
;
4298 save
= input_line_pointer
;
4299 if (input_line_pointer
[0] == '%'
4300 && input_line_pointer
[1] == 'r'
4301 && input_line_pointer
[2] == '_')
4303 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4305 input_line_pointer
+= 7;
4306 sparc_cons_special_reloc
= "disp";
4308 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4310 if (size
!= 4 && size
!= 8)
4311 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4314 input_line_pointer
+= 6;
4315 sparc_cons_special_reloc
= "plt";
4318 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4320 if (size
!= 4 && size
!= 8)
4321 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4324 input_line_pointer
+= 13;
4325 sparc_cons_special_reloc
= "tls_dtpoff";
4328 if (sparc_cons_special_reloc
)
4335 if (*input_line_pointer
!= '8')
4337 input_line_pointer
--;
4340 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4344 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4348 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4358 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4359 sparc_cons_special_reloc
, size
* 8, size
);
4363 input_line_pointer
+= 2;
4364 if (*input_line_pointer
!= '(')
4366 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4367 sparc_cons_special_reloc
, size
* 8);
4374 input_line_pointer
= save
;
4375 sparc_cons_special_reloc
= NULL
;
4380 char *end
= ++input_line_pointer
;
4383 while (! is_end_of_line
[(c
= *end
)])
4397 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4398 sparc_cons_special_reloc
, size
* 8);
4404 if (input_line_pointer
!= end
)
4406 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4407 sparc_cons_special_reloc
, size
* 8);
4411 input_line_pointer
++;
4413 c
= *input_line_pointer
;
4414 if (! is_end_of_line
[c
] && c
!= ',')
4415 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4416 sparc_cons_special_reloc
, size
* 8);
4422 if (sparc_cons_special_reloc
== NULL
)
4428 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4429 reloc for a cons. We could use the definition there, except that
4430 we want to handle little endian relocs specially. */
4433 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
4436 unsigned int nbytes
;
4439 bfd_reloc_code_real_type r
;
4441 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4442 (nbytes
== 2 ? BFD_RELOC_16
:
4443 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4445 if (target_little_endian_data
4447 && now_seg
->flags
& SEC_ALLOC
)
4448 r
= BFD_RELOC_SPARC_REV32
;
4450 if (sparc_cons_special_reloc
)
4452 if (*sparc_cons_special_reloc
== 'd')
4455 case 1: r
= BFD_RELOC_8_PCREL
; break;
4456 case 2: r
= BFD_RELOC_16_PCREL
; break;
4457 case 4: r
= BFD_RELOC_32_PCREL
; break;
4458 case 8: r
= BFD_RELOC_64_PCREL
; break;
4461 else if (*sparc_cons_special_reloc
== 'p')
4464 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4465 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4470 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4471 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4474 else if (sparc_no_align_cons
)
4478 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4479 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4480 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4485 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);