1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
23 #include "safe-ctype.h"
26 #include "opcode/sparc.h"
27 #include "dw2gencfi.h"
30 #include "elf/sparc.h"
31 #include "dwarf2dbg.h"
34 /* Some ancient Sun C compilers would not take such hex constants as
35 unsigned, and would end up sign-extending them to form an offsetT,
36 so use these constants instead. */
37 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
38 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40 static int sparc_ip (char *, const struct sparc_opcode
**);
41 static int parse_keyword_arg (int (*) (const char *), char **, int *);
42 static int parse_const_expr_arg (char **, int *);
43 static int get_expression (char *);
45 /* Default architecture. */
46 /* ??? The default value should be V8, but sparclite support was added
47 by making it the default. GCC now passes -Asparclite, so maybe sometime in
48 the future we can set this to V8. */
50 #define DEFAULT_ARCH "sparclite"
52 static char *default_arch
= DEFAULT_ARCH
;
54 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 static int default_init_p
;
58 /* Current architecture. We don't bump up unless necessary. */
59 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
61 /* The maximum architecture level we can bump up to.
62 In a 32 bit environment, don't allow bumping up to v9 by default.
63 The native assembler works this way. The user is required to pass
64 an explicit argument before we'll create v9 object files. However, if
65 we don't see any v9 insns, a v8plus object file is not created. */
66 static enum sparc_opcode_arch_val max_architecture
;
68 /* Either 32 or 64, selects file format. */
69 static int sparc_arch_size
;
70 /* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72 static int default_arch_size
;
75 /* The currently selected v9 memory model. Currently only used for
77 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
80 static int architecture_requested
;
81 static int warn_on_bump
;
83 /* If warn_on_bump and the needed architecture is higher than this
84 architecture, issue a warning. */
85 static enum sparc_opcode_arch_val warn_after_architecture
;
87 /* Non-zero if as should generate error if an undeclared g[23] register
88 has been used in -64. */
89 static int no_undeclared_regs
;
91 /* Non-zero if we should try to relax jumps and calls. */
92 static int sparc_relax
;
94 /* Non-zero if we are generating PIC code. */
97 /* Non-zero if we should give an error when misaligned data is seen. */
98 static int enforce_aligned_data
;
100 extern int target_big_endian
;
102 static int target_little_endian_data
;
104 /* Symbols for global registers on v9. */
105 static symbolS
*globals
[8];
107 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
108 int sparc_cie_data_alignment
;
110 /* V9 and 86x have big and little endian data, but instructions are always big
111 endian. The sparclet has bi-endian support but both data and insns have
112 the same endianness. Global `target_big_endian' is used for data.
113 The following macro is used for instructions. */
114 #ifndef INSN_BIG_ENDIAN
115 #define INSN_BIG_ENDIAN (target_big_endian \
116 || default_arch_type == sparc86x \
117 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
120 /* Handle of the OPCODE hash table. */
121 static struct hash_control
*op_hash
;
123 static void s_data1 (void);
124 static void s_seg (int);
125 static void s_proc (int);
126 static void s_reserve (int);
127 static void s_common (int);
128 static void s_empty (int);
129 static void s_uacons (int);
130 static void s_ncons (int);
132 static void s_register (int);
135 const pseudo_typeS md_pseudo_table
[] =
137 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
138 {"common", s_common
, 0},
139 {"empty", s_empty
, 0},
140 {"global", s_globl
, 0},
142 {"nword", s_ncons
, 0},
143 {"optim", s_ignore
, 0},
145 {"reserve", s_reserve
, 0},
147 {"skip", s_space
, 0},
150 {"uahalf", s_uacons
, 2},
151 {"uaword", s_uacons
, 4},
152 {"uaxword", s_uacons
, 8},
154 /* These are specific to sparc/svr4. */
155 {"2byte", s_uacons
, 2},
156 {"4byte", s_uacons
, 4},
157 {"8byte", s_uacons
, 8},
158 {"register", s_register
, 0},
163 /* This array holds the chars that always start a comment. If the
164 pre-processor is disabled, these aren't very useful. */
165 const char comment_chars
[] = "!"; /* JF removed '|' from
168 /* This array holds the chars that only start a comment at the beginning of
169 a line. If the line seems to have the form '# 123 filename'
170 .line and .file directives will appear in the pre-processed output. */
171 /* Note that input_file.c hand checks for '#' at the beginning of the
172 first line of the input file. This is because the compiler outputs
173 #NO_APP at the beginning of its output. */
174 /* Also note that comments started like this one will always
175 work if '/' isn't otherwise defined. */
176 const char line_comment_chars
[] = "#";
178 const char line_separator_chars
[] = ";";
180 /* Chars that can be used to separate mant from exp in floating point
182 const char EXP_CHARS
[] = "eE";
184 /* Chars that mean this number is a floating point constant.
187 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
189 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
190 changed in read.c. Ideally it shouldn't have to know about it at all,
191 but nothing is ideal around here. */
193 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
198 unsigned long opcode
;
199 struct nlist
*nlistp
;
203 bfd_reloc_code_real_type reloc
;
206 struct sparc_it the_insn
, set_insn
;
208 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
210 /* Table of arguments to -A.
211 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
212 for this use. That table is for opcodes only. This table is for opcodes
215 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
216 v8plusa
, v9
, v9a
, v9b
, v9_64
};
218 static struct sparc_arch
{
221 enum sparc_arch_types arch_type
;
222 /* Default word size, as specified during configuration.
223 A value of zero means can't be used to specify default architecture. */
224 int default_arch_size
;
225 /* Allowable arg to -A? */
227 } sparc_arch_table
[] = {
228 { "v6", "v6", v6
, 0, 1 },
229 { "v7", "v7", v7
, 0, 1 },
230 { "v8", "v8", v8
, 32, 1 },
231 { "sparclet", "sparclet", sparclet
, 32, 1 },
232 { "sparclite", "sparclite", sparclite
, 32, 1 },
233 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
234 { "v8plus", "v9", v9
, 0, 1 },
235 { "v8plusa", "v9a", v9
, 0, 1 },
236 { "v8plusb", "v9b", v9
, 0, 1 },
237 { "v9", "v9", v9
, 0, 1 },
238 { "v9a", "v9a", v9
, 0, 1 },
239 { "v9b", "v9b", v9
, 0, 1 },
240 /* This exists to allow configure.in/Makefile.in to pass one
241 value to specify both the default machine and default word size. */
242 { "v9-64", "v9", v9
, 64, 0 },
243 { NULL
, NULL
, v8
, 0, 0 }
246 /* Variant of default_arch */
247 static enum sparc_arch_types default_arch_type
;
249 static struct sparc_arch
*
250 lookup_arch (char *name
)
252 struct sparc_arch
*sa
;
254 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
255 if (strcmp (sa
->name
, name
) == 0)
257 if (sa
->name
== NULL
)
262 /* Initialize the default opcode arch and word size from the default
263 architecture name. */
266 init_default_arch (void)
268 struct sparc_arch
*sa
= lookup_arch (default_arch
);
271 || sa
->default_arch_size
== 0)
272 as_fatal (_("Invalid default architecture, broken assembler."));
274 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
275 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
276 as_fatal (_("Bad opcode table, broken assembler."));
277 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
279 default_arch_type
= sa
->arch_type
;
282 /* Called by TARGET_FORMAT. */
285 sparc_target_format (void)
287 /* We don't get a chance to initialize anything before we're called,
288 so handle that now. */
289 if (! default_init_p
)
290 init_default_arch ();
294 return "a.out-sparc-netbsd";
297 if (target_big_endian
)
298 return "a.out-sunos-big";
299 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
300 return "a.out-sunos-big";
302 return "a.out-sparc-little";
304 return "a.out-sunos-big";
315 return "coff-sparc-lynx";
322 return "elf32-sparc-vxworks";
326 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
333 * Invocation line includes a switch not recognized by the base assembler.
334 * See if it's a processor-specific option. These are:
337 * Warn on architecture bumps. See also -A.
339 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
340 * Standard 32 bit architectures.
342 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
343 * This used to only mean 64 bits, but properly specifying it
344 * complicated gcc's ASM_SPECs, so now opcode selection is
345 * specified orthogonally to word size (except when specifying
346 * the default, but that is an internal implementation detail).
347 * -Av8plus, -Av8plusa, -Av8plusb
348 * Same as -Av9{,a,b}.
349 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
350 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
352 * -xarch=v9, -xarch=v9a, -xarch=v9b
353 * Same as -Av9{,a,b} -64, for compatibility with Sun's
356 * Select the architecture and possibly the file format.
357 * Instructions or features not supported by the selected
358 * architecture cause fatal errors.
360 * The default is to start at v6, and bump the architecture up
361 * whenever an instruction is seen at a higher level. In 32 bit
362 * environments, v9 is not bumped up to, the user must pass
365 * If -bump is specified, a warning is printing when bumping to
368 * If an architecture is specified, all instructions must match
369 * that architecture. Any higher level instructions are flagged
370 * as errors. Note that in the 32 bit environment specifying
371 * -Av8plus does not automatically create a v8plus object file, a
372 * v9 insn must be seen.
374 * If both an architecture and -bump are specified, the
375 * architecture starts at the specified level, but bumps are
376 * warnings. Note that we can't set `current_architecture' to
377 * the requested level in this case: in the 32 bit environment,
378 * we still must avoid creating v8plus object files unless v9
382 * Bumping between incompatible architectures is always an
383 * error. For example, from sparclite to v9.
387 const char *md_shortopts
= "A:K:VQ:sq";
390 const char *md_shortopts
= "A:k";
392 const char *md_shortopts
= "A:";
395 struct option md_longopts
[] = {
396 #define OPTION_BUMP (OPTION_MD_BASE)
397 {"bump", no_argument
, NULL
, OPTION_BUMP
},
398 #define OPTION_SPARC (OPTION_MD_BASE + 1)
399 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
400 #define OPTION_XARCH (OPTION_MD_BASE + 2)
401 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
403 #define OPTION_32 (OPTION_MD_BASE + 3)
404 {"32", no_argument
, NULL
, OPTION_32
},
405 #define OPTION_64 (OPTION_MD_BASE + 4)
406 {"64", no_argument
, NULL
, OPTION_64
},
407 #define OPTION_TSO (OPTION_MD_BASE + 5)
408 {"TSO", no_argument
, NULL
, OPTION_TSO
},
409 #define OPTION_PSO (OPTION_MD_BASE + 6)
410 {"PSO", no_argument
, NULL
, OPTION_PSO
},
411 #define OPTION_RMO (OPTION_MD_BASE + 7)
412 {"RMO", no_argument
, NULL
, OPTION_RMO
},
414 #ifdef SPARC_BIENDIAN
415 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
416 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
417 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
418 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
420 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
421 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
422 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
423 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
425 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
426 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
427 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
428 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
430 #define OPTION_RELAX (OPTION_MD_BASE + 14)
431 {"relax", no_argument
, NULL
, OPTION_RELAX
},
432 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
433 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
434 {NULL
, no_argument
, NULL
, 0}
437 size_t md_longopts_size
= sizeof (md_longopts
);
440 md_parse_option (int c
, char *arg
)
442 /* We don't get a chance to initialize anything before we're called,
443 so handle that now. */
444 if (! default_init_p
)
445 init_default_arch ();
451 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
456 if (strncmp (arg
, "v9", 2) != 0)
457 md_parse_option (OPTION_32
, NULL
);
459 md_parse_option (OPTION_64
, NULL
);
465 struct sparc_arch
*sa
;
466 enum sparc_opcode_arch_val opcode_arch
;
468 sa
= lookup_arch (arg
);
470 || ! sa
->user_option_p
)
472 if (c
== OPTION_XARCH
)
473 as_bad (_("invalid architecture -xarch=%s"), arg
);
475 as_bad (_("invalid architecture -A%s"), arg
);
479 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
480 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
481 as_fatal (_("Bad opcode table, broken assembler."));
483 max_architecture
= opcode_arch
;
484 architecture_requested
= 1;
489 /* Ignore -sparc, used by SunOS make default .s.o rule. */
492 case OPTION_ENFORCE_ALIGNED_DATA
:
493 enforce_aligned_data
= 1;
496 #ifdef SPARC_BIENDIAN
497 case OPTION_LITTLE_ENDIAN
:
498 target_big_endian
= 0;
499 if (default_arch_type
!= sparclet
)
500 as_fatal ("This target does not support -EL");
502 case OPTION_LITTLE_ENDIAN_DATA
:
503 target_little_endian_data
= 1;
504 target_big_endian
= 0;
505 if (default_arch_type
!= sparc86x
506 && default_arch_type
!= v9
)
507 as_fatal ("This target does not support --little-endian-data");
509 case OPTION_BIG_ENDIAN
:
510 target_big_endian
= 1;
524 const char **list
, **l
;
526 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
527 list
= bfd_target_list ();
528 for (l
= list
; *l
!= NULL
; l
++)
530 if (sparc_arch_size
== 32)
532 if (CONST_STRNEQ (*l
, "elf32-sparc"))
537 if (CONST_STRNEQ (*l
, "elf64-sparc"))
542 as_fatal (_("No compiled in support for %d bit object file format"),
546 if (sparc_arch_size
== 64
547 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
548 max_architecture
= SPARC_OPCODE_ARCH_V9
;
553 sparc_memory_model
= MM_TSO
;
557 sparc_memory_model
= MM_PSO
;
561 sparc_memory_model
= MM_RMO
;
569 /* Qy - do emit .comment
570 Qn - do not emit .comment. */
574 /* Use .stab instead of .stab.excl. */
578 /* quick -- Native assembler does fewer checks. */
582 if (strcmp (arg
, "PIC") != 0)
583 as_warn (_("Unrecognized option following -K"));
588 case OPTION_NO_UNDECLARED_REGS
:
589 no_undeclared_regs
= 1;
592 case OPTION_UNDECLARED_REGS
:
593 no_undeclared_regs
= 0;
601 case OPTION_NO_RELAX
:
613 md_show_usage (FILE *stream
)
615 const struct sparc_arch
*arch
;
618 /* We don't get a chance to initialize anything before we're called,
619 so handle that now. */
620 if (! default_init_p
)
621 init_default_arch ();
623 fprintf (stream
, _("SPARC options:\n"));
625 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
627 if (!arch
->user_option_p
)
629 if (arch
!= &sparc_arch_table
[0])
630 fprintf (stream
, " | ");
631 if (column
+ strlen (arch
->name
) > 70)
634 fputc ('\n', stream
);
636 column
+= 5 + 2 + strlen (arch
->name
);
637 fprintf (stream
, "-A%s", arch
->name
);
639 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
641 if (!arch
->user_option_p
)
643 fprintf (stream
, " | ");
644 if (column
+ strlen (arch
->name
) > 65)
647 fputc ('\n', stream
);
649 column
+= 5 + 7 + strlen (arch
->name
);
650 fprintf (stream
, "-xarch=%s", arch
->name
);
652 fprintf (stream
, _("\n\
653 specify variant of SPARC architecture\n\
654 -bump warn when assembler switches architectures\n\
656 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
657 -relax relax jumps and branches (default)\n\
658 -no-relax avoid changing any jumps and branches\n"));
660 fprintf (stream
, _("\
661 -k generate PIC\n"));
664 fprintf (stream
, _("\
665 -32 create 32 bit object file\n\
666 -64 create 64 bit object file\n"));
667 fprintf (stream
, _("\
668 [default is %d]\n"), default_arch_size
);
669 fprintf (stream
, _("\
670 -TSO use Total Store Ordering\n\
671 -PSO use Partial Store Ordering\n\
672 -RMO use Relaxed Memory Ordering\n"));
673 fprintf (stream
, _("\
674 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
675 fprintf (stream
, _("\
676 -KPIC generate PIC\n\
677 -V print assembler version number\n\
678 -undeclared-regs ignore application global register usage without\n\
679 appropriate .register directive (default)\n\
680 -no-undeclared-regs force error on application global register usage\n\
681 without appropriate .register directive\n\
686 #ifdef SPARC_BIENDIAN
687 fprintf (stream
, _("\
688 -EL generate code for a little endian machine\n\
689 -EB generate code for a big endian machine\n\
690 --little-endian-data generate code for a machine having big endian\n\
691 instructions and little endian data.\n"));
695 /* Native operand size opcode translation. */
701 } native_op_table
[] =
703 {"ldn", "ld", "ldx"},
704 {"ldna", "lda", "ldxa"},
705 {"stn", "st", "stx"},
706 {"stna", "sta", "stxa"},
707 {"slln", "sll", "sllx"},
708 {"srln", "srl", "srlx"},
709 {"sran", "sra", "srax"},
710 {"casn", "cas", "casx"},
711 {"casna", "casa", "casxa"},
712 {"clrn", "clr", "clrx"},
716 /* sparc64 privileged and hyperprivileged registers. */
718 struct priv_reg_entry
724 struct priv_reg_entry priv_reg_table
[] =
744 {"", -1}, /* End marker. */
747 struct priv_reg_entry hpriv_reg_table
[] =
755 {"", -1}, /* End marker. */
758 /* v9a specific asrs. This table is ordered by initial
759 letter, in reverse. */
761 struct priv_reg_entry v9a_asr_table
[] =
764 {"sys_tick_cmpr", 25},
768 {"softint_clear", 21},
777 {"clear_softint", 21},
778 {"", -1}, /* End marker. */
782 cmp_reg_entry (const void *parg
, const void *qarg
)
784 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
785 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
787 return strcmp (q
->name
, p
->name
);
790 /* This function is called once, at assembler startup time. It should
791 set up all the tables, etc. that the MD part of the assembler will
797 register const char *retval
= NULL
;
799 register unsigned int i
= 0;
801 /* We don't get a chance to initialize anything before md_parse_option
802 is called, and it may not be called, so handle default initialization
803 now if not already done. */
804 if (! default_init_p
)
805 init_default_arch ();
807 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
808 op_hash
= hash_new ();
810 while (i
< (unsigned int) sparc_num_opcodes
)
812 const char *name
= sparc_opcodes
[i
].name
;
813 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
816 as_bad (_("Internal error: can't hash `%s': %s\n"),
817 sparc_opcodes
[i
].name
, retval
);
822 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
824 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
825 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
830 while (i
< (unsigned int) sparc_num_opcodes
831 && !strcmp (sparc_opcodes
[i
].name
, name
));
834 for (i
= 0; native_op_table
[i
].name
; i
++)
836 const struct sparc_opcode
*insn
;
837 char *name
= ((sparc_arch_size
== 32)
838 ? native_op_table
[i
].name32
839 : native_op_table
[i
].name64
);
840 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
843 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
844 name
, native_op_table
[i
].name
);
849 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
853 as_bad (_("Internal error: can't hash `%s': %s\n"),
854 sparc_opcodes
[i
].name
, retval
);
861 as_fatal (_("Broken assembler. No assembly attempted."));
863 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
864 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
866 /* If -bump, record the architecture level at which we start issuing
867 warnings. The behaviour is different depending upon whether an
868 architecture was explicitly specified. If it wasn't, we issue warnings
869 for all upwards bumps. If it was, we don't start issuing warnings until
870 we need to bump beyond the requested architecture or when we bump between
871 conflicting architectures. */
874 && architecture_requested
)
876 /* `max_architecture' records the requested architecture.
877 Issue warnings if we go above it. */
878 warn_after_architecture
= max_architecture
;
880 /* Find the highest architecture level that doesn't conflict with
881 the requested one. */
882 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
883 max_architecture
> warn_after_architecture
;
885 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
886 warn_after_architecture
))
891 /* Called after all assembly has been done. */
896 unsigned long mach
= bfd_mach_sparc
;
898 if (sparc_arch_size
== 64)
899 switch (current_architecture
)
901 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
902 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
903 default: mach
= bfd_mach_sparc_v9
; break;
906 switch (current_architecture
)
908 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
909 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
910 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
911 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
912 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
913 be but for now it is (since that's the way it's always been
917 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
920 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
923 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
927 /* Sign-extend the value from the architecture word size, so that
928 0xffffffff is always considered -1 on sparc32. */
929 if (sparc_arch_size
== 32)
931 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
932 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
941 /* Return non-zero if VAL is in the range 0 to MAX. */
944 in_unsigned_range (bfd_vma val
, bfd_vma max
)
951 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
952 (e.g. -15 to +31). */
955 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
961 if (val
< ~(max
>> 1))
967 sparc_ffs (unsigned int mask
)
974 for (i
= 0; (mask
& 1) == 0; ++i
)
979 /* Implement big shift right. */
981 BSR (bfd_vma val
, int amount
)
983 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
984 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
985 return val
>> amount
;
988 /* For communication between sparc_ip and get_expression. */
989 static char *expr_end
;
991 /* Values for `special_case'.
992 Instructions that require wierd handling because they're longer than
994 #define SPECIAL_CASE_NONE 0
995 #define SPECIAL_CASE_SET 1
996 #define SPECIAL_CASE_SETSW 2
997 #define SPECIAL_CASE_SETX 3
998 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
999 #define SPECIAL_CASE_FDIV 4
1001 /* Bit masks of various insns. */
1002 #define NOP_INSN 0x01000000
1003 #define OR_INSN 0x80100000
1004 #define XOR_INSN 0x80180000
1005 #define FMOVS_INSN 0x81A00020
1006 #define SETHI_INSN 0x01000000
1007 #define SLLX_INSN 0x81281000
1008 #define SRA_INSN 0x81380000
1010 /* The last instruction to be assembled. */
1011 static const struct sparc_opcode
*last_insn
;
1012 /* The assembled opcode of `last_insn'. */
1013 static unsigned long last_opcode
;
1015 /* Handle the set and setuw synthetic instructions. */
1018 synthetize_setuw (const struct sparc_opcode
*insn
)
1020 int need_hi22_p
= 0;
1021 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1023 if (the_insn
.exp
.X_op
== O_constant
)
1025 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1027 if (sizeof (offsetT
) > 4
1028 && (the_insn
.exp
.X_add_number
< 0
1029 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1030 as_warn (_("set: number not in 0..4294967295 range"));
1034 if (sizeof (offsetT
) > 4
1035 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1036 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1037 as_warn (_("set: number not in -2147483648..4294967295 range"));
1038 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1042 /* See if operand is absolute and small; skip sethi if so. */
1043 if (the_insn
.exp
.X_op
!= O_constant
1044 || the_insn
.exp
.X_add_number
>= (1 << 12)
1045 || the_insn
.exp
.X_add_number
< -(1 << 12))
1047 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1048 | ((the_insn
.exp
.X_add_number
>> 10)
1049 & (the_insn
.exp
.X_op
== O_constant
1051 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1052 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1053 output_insn (insn
, &the_insn
);
1057 /* See if operand has no low-order bits; skip OR if so. */
1058 if (the_insn
.exp
.X_op
!= O_constant
1059 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1062 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1064 | (the_insn
.exp
.X_add_number
1065 & (the_insn
.exp
.X_op
!= O_constant
1066 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1067 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1068 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1069 output_insn (insn
, &the_insn
);
1073 /* Handle the setsw synthetic instruction. */
1076 synthetize_setsw (const struct sparc_opcode
*insn
)
1080 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1082 if (the_insn
.exp
.X_op
!= O_constant
)
1084 synthetize_setuw (insn
);
1086 /* Need to sign extend it. */
1087 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1088 the_insn
.reloc
= BFD_RELOC_NONE
;
1089 output_insn (insn
, &the_insn
);
1093 if (sizeof (offsetT
) > 4
1094 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1095 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1096 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1098 low32
= the_insn
.exp
.X_add_number
;
1102 synthetize_setuw (insn
);
1108 the_insn
.reloc
= BFD_RELOC_NONE
;
1109 /* See if operand is absolute and small; skip sethi if so. */
1110 if (low32
< -(1 << 12))
1112 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1113 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1114 output_insn (insn
, &the_insn
);
1115 low32
= 0x1c00 | (low32
& 0x3ff);
1116 opc
= RS1 (rd
) | XOR_INSN
;
1119 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1120 | (low32
& 0x1fff));
1121 output_insn (insn
, &the_insn
);
1124 /* Handle the setsw synthetic instruction. */
1127 synthetize_setx (const struct sparc_opcode
*insn
)
1129 int upper32
, lower32
;
1130 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1131 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1133 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1134 int need_xor10_p
= 0;
1136 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1137 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1138 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1141 upper_dstreg
= tmpreg
;
1142 /* The tmp reg should not be the dst reg. */
1143 if (tmpreg
== dstreg
)
1144 as_warn (_("setx: temporary register same as destination register"));
1146 /* ??? Obviously there are other optimizations we can do
1147 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1148 doing some of these. Later. If you do change things, try to
1149 change all of this to be table driven as well. */
1150 /* What to output depends on the number if it's constant.
1151 Compute that first, then output what we've decided upon. */
1152 if (the_insn
.exp
.X_op
!= O_constant
)
1154 if (sparc_arch_size
== 32)
1156 /* When arch size is 32, we want setx to be equivalent
1157 to setuw for anything but constants. */
1158 the_insn
.exp
.X_add_number
&= 0xffffffff;
1159 synthetize_setuw (insn
);
1162 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1168 /* Reset X_add_number, we've extracted it as upper32/lower32.
1169 Otherwise fixup_segment will complain about not being able to
1170 write an 8 byte number in a 4 byte field. */
1171 the_insn
.exp
.X_add_number
= 0;
1173 /* Only need hh22 if `or' insn can't handle constant. */
1174 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1177 /* Does bottom part (after sethi) have bits? */
1178 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1179 /* No hh22, but does upper32 still have bits we can't set
1181 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1184 /* If the lower half is all zero, we build the upper half directly
1185 into the dst reg. */
1187 /* Need lower half if number is zero or 0xffffffff00000000. */
1188 || (! need_hh22_p
&& ! need_hm10_p
))
1190 /* No need for sethi if `or' insn can handle constant. */
1191 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1192 /* Note that we can't use a negative constant in the `or'
1193 insn unless the upper 32 bits are all ones. */
1194 || (lower32
< 0 && upper32
!= -1)
1195 || (lower32
>= 0 && upper32
== -1))
1198 if (need_hi22_p
&& upper32
== -1)
1201 /* Does bottom part (after sethi) have bits? */
1202 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1204 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1205 /* Need `or' if we didn't set anything else. */
1206 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1210 /* Output directly to dst reg if lower 32 bits are all zero. */
1211 upper_dstreg
= dstreg
;
1214 if (!upper_dstreg
&& dstreg
)
1215 as_warn (_("setx: illegal temporary register g0"));
1219 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1220 | ((upper32
>> 10) & 0x3fffff));
1221 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1222 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1223 output_insn (insn
, &the_insn
);
1228 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1229 | (((need_xor10_p
? ~lower32
: lower32
)
1230 >> 10) & 0x3fffff));
1231 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1232 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1233 output_insn (insn
, &the_insn
);
1238 the_insn
.opcode
= (OR_INSN
1239 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1242 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1243 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1244 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1245 output_insn (insn
, &the_insn
);
1250 /* FIXME: One nice optimization to do here is to OR the low part
1251 with the highpart if hi22 isn't needed and the low part is
1253 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1256 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1257 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1258 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1259 output_insn (insn
, &the_insn
);
1262 /* If we needed to build the upper part, shift it into place. */
1263 if (need_hh22_p
|| need_hm10_p
)
1265 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1267 the_insn
.reloc
= BFD_RELOC_NONE
;
1268 output_insn (insn
, &the_insn
);
1271 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1274 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1275 | 0x1c00 | (lower32
& 0x3ff));
1276 the_insn
.reloc
= BFD_RELOC_NONE
;
1277 output_insn (insn
, &the_insn
);
1280 /* If we needed to build both upper and lower parts, OR them together. */
1281 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1283 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1285 the_insn
.reloc
= BFD_RELOC_NONE
;
1286 output_insn (insn
, &the_insn
);
1290 /* Main entry point to assemble one instruction. */
1293 md_assemble (char *str
)
1295 const struct sparc_opcode
*insn
;
1299 special_case
= sparc_ip (str
, &insn
);
1303 /* We warn about attempts to put a floating point branch in a delay slot,
1304 unless the delay slot has been annulled. */
1305 if (last_insn
!= NULL
1306 && (insn
->flags
& F_FBR
) != 0
1307 && (last_insn
->flags
& F_DELAYED
) != 0
1308 /* ??? This test isn't completely accurate. We assume anything with
1309 F_{UNBR,CONDBR,FBR} set is annullable. */
1310 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1311 || (last_opcode
& ANNUL
) == 0))
1312 as_warn (_("FP branch in delay slot"));
1314 /* SPARC before v9 requires a nop instruction between a floating
1315 point instruction and a floating point branch. We insert one
1316 automatically, with a warning. */
1317 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1318 && last_insn
!= NULL
1319 && (insn
->flags
& F_FBR
) != 0
1320 && (last_insn
->flags
& F_FLOAT
) != 0)
1322 struct sparc_it nop_insn
;
1324 nop_insn
.opcode
= NOP_INSN
;
1325 nop_insn
.reloc
= BFD_RELOC_NONE
;
1326 output_insn (insn
, &nop_insn
);
1327 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1330 switch (special_case
)
1332 case SPECIAL_CASE_NONE
:
1334 output_insn (insn
, &the_insn
);
1337 case SPECIAL_CASE_SETSW
:
1338 synthetize_setsw (insn
);
1341 case SPECIAL_CASE_SET
:
1342 synthetize_setuw (insn
);
1345 case SPECIAL_CASE_SETX
:
1346 synthetize_setx (insn
);
1349 case SPECIAL_CASE_FDIV
:
1351 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1353 output_insn (insn
, &the_insn
);
1355 /* According to information leaked from Sun, the "fdiv" instructions
1356 on early SPARC machines would produce incorrect results sometimes.
1357 The workaround is to add an fmovs of the destination register to
1358 itself just after the instruction. This was true on machines
1359 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1360 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1361 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1362 output_insn (insn
, &the_insn
);
1367 as_fatal (_("failed special case insn sanity check"));
1371 /* Subroutine of md_assemble to do the actual parsing. */
1374 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1376 char *error_message
= "";
1380 const struct sparc_opcode
*insn
;
1382 unsigned long opcode
;
1383 unsigned int mask
= 0;
1387 int special_case
= SPECIAL_CASE_NONE
;
1394 while (ISLOWER (*s
) || ISDIGIT (*s
));
1411 as_bad (_("Unknown opcode: `%s'"), str
);
1413 return special_case
;
1415 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1419 as_bad (_("Unknown opcode: `%s'"), str
);
1420 return special_case
;
1430 opcode
= insn
->match
;
1431 memset (&the_insn
, '\0', sizeof (the_insn
));
1432 the_insn
.reloc
= BFD_RELOC_NONE
;
1435 /* Build the opcode, checking as we go to make sure that the
1437 for (args
= insn
->args
;; ++args
)
1445 /* Parse a series of masks. */
1452 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1455 error_message
= _(": invalid membar mask name");
1461 if (*s
== '|' || *s
== '+')
1469 if (! parse_const_expr_arg (&s
, &kmask
))
1471 error_message
= _(": invalid membar mask expression");
1474 if (kmask
< 0 || kmask
> 127)
1476 error_message
= _(": invalid membar mask number");
1481 opcode
|= MEMBAR (kmask
);
1489 if (! parse_const_expr_arg (&s
, &smask
))
1491 error_message
= _(": invalid siam mode expression");
1494 if (smask
< 0 || smask
> 7)
1496 error_message
= _(": invalid siam mode number");
1507 /* Parse a prefetch function. */
1510 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1512 error_message
= _(": invalid prefetch function name");
1518 if (! parse_const_expr_arg (&s
, &fcn
))
1520 error_message
= _(": invalid prefetch function expression");
1523 if (fcn
< 0 || fcn
> 31)
1525 error_message
= _(": invalid prefetch function number");
1535 /* Parse a sparc64 privileged register. */
1538 struct priv_reg_entry
*p
= priv_reg_table
;
1539 unsigned int len
= 9999999; /* Init to make gcc happy. */
1542 while (p
->name
[0] > s
[0])
1544 while (p
->name
[0] == s
[0])
1546 len
= strlen (p
->name
);
1547 if (strncmp (p
->name
, s
, len
) == 0)
1551 if (p
->name
[0] != s
[0])
1553 error_message
= _(": unrecognizable privileged register");
1557 opcode
|= (p
->regnum
<< 14);
1559 opcode
|= (p
->regnum
<< 25);
1565 error_message
= _(": unrecognizable privileged register");
1571 /* Parse a sparc64 hyperprivileged register. */
1574 struct priv_reg_entry
*p
= hpriv_reg_table
;
1575 unsigned int len
= 9999999; /* Init to make gcc happy. */
1578 while (p
->name
[0] > s
[0])
1580 while (p
->name
[0] == s
[0])
1582 len
= strlen (p
->name
);
1583 if (strncmp (p
->name
, s
, len
) == 0)
1587 if (p
->name
[0] != s
[0])
1589 error_message
= _(": unrecognizable hyperprivileged register");
1593 opcode
|= (p
->regnum
<< 14);
1595 opcode
|= (p
->regnum
<< 25);
1601 error_message
= _(": unrecognizable hyperprivileged register");
1607 /* Parse a v9a/v9b ancillary state register. */
1610 struct priv_reg_entry
*p
= v9a_asr_table
;
1611 unsigned int len
= 9999999; /* Init to make gcc happy. */
1614 while (p
->name
[0] > s
[0])
1616 while (p
->name
[0] == s
[0])
1618 len
= strlen (p
->name
);
1619 if (strncmp (p
->name
, s
, len
) == 0)
1623 if (p
->name
[0] != s
[0])
1625 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1628 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1630 error_message
= _(": rd on write only ancillary state register");
1634 && (insn
->architecture
1635 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1637 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1638 error_message
= _(": unrecognizable v9a ancillary state register");
1642 opcode
|= (p
->regnum
<< 14);
1644 opcode
|= (p
->regnum
<< 25);
1650 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1656 if (strncmp (s
, "%asr", 4) == 0)
1664 while (ISDIGIT (*s
))
1666 num
= num
* 10 + *s
- '0';
1670 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1672 if (num
< 16 || 31 < num
)
1674 error_message
= _(": asr number must be between 16 and 31");
1680 if (num
< 0 || 31 < num
)
1682 error_message
= _(": asr number must be between 0 and 31");
1687 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1692 error_message
= _(": expecting %asrN");
1699 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1703 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1707 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1708 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1709 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1711 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1712 /* These fields are unsigned, but for upward compatibility,
1713 allow negative values as well. */
1717 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1718 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1719 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1721 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1722 /* These fields are unsigned, but for upward compatibility,
1723 allow negative values as well. */
1727 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1732 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1737 if (*s
== 'p' && s
[1] == 'n')
1745 if (*s
== 'p' && s
[1] == 't')
1757 if (strncmp (s
, "%icc", 4) == 0)
1769 if (strncmp (s
, "%xcc", 4) == 0)
1781 if (strncmp (s
, "%fcc0", 5) == 0)
1793 if (strncmp (s
, "%fcc1", 5) == 0)
1805 if (strncmp (s
, "%fcc2", 5) == 0)
1817 if (strncmp (s
, "%fcc3", 5) == 0)
1825 if (strncmp (s
, "%pc", 3) == 0)
1833 if (strncmp (s
, "%tick", 5) == 0)
1840 case '\0': /* End of args. */
1841 if (s
[0] == ',' && s
[1] == '%')
1843 static const struct ops
1845 /* The name as it appears in assembler. */
1847 /* strlen (name), precomputed for speed */
1849 /* The reloc this pseudo-op translates to. */
1851 /* 1 if tls call. */
1856 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
1857 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
1858 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
1859 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
1860 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
1861 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
1862 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
1863 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
1864 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
1867 const struct ops
*o
;
1871 for (o
= ops
; o
->name
; o
++)
1872 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
1874 if (o
->name
== NULL
)
1877 if (s
[o
->len
+ 2] != '(')
1879 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1880 return special_case
;
1883 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
1885 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1887 return special_case
;
1891 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
1892 || the_insn
.exp
.X_add_number
!= 0
1893 || the_insn
.exp
.X_add_symbol
1894 != symbol_find_or_make ("__tls_get_addr")))
1896 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1898 return special_case
;
1901 the_insn
.reloc
= o
->reloc
;
1902 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
1905 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
1908 else if (*s1
== ')')
1917 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1918 return special_case
;
1922 (void) get_expression (s
);
1942 case '[': /* These must match exactly. */
1950 case '#': /* Must be at least one digit. */
1953 while (ISDIGIT (*s
))
1961 case 'C': /* Coprocessor state register. */
1962 if (strncmp (s
, "%csr", 4) == 0)
1969 case 'b': /* Next operand is a coprocessor register. */
1972 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
1977 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1991 opcode
|= mask
<< 14;
1999 opcode
|= mask
<< 25;
2005 case 'r': /* next operand must be a register */
2015 case 'f': /* frame pointer */
2023 case 'g': /* global register */
2032 case 'i': /* in register */
2036 mask
= c
- '0' + 24;
2041 case 'l': /* local register */
2045 mask
= (c
- '0' + 16);
2050 case 'o': /* out register */
2054 mask
= (c
- '0' + 8);
2059 case 's': /* stack pointer */
2067 case 'r': /* any register */
2068 if (!ISDIGIT ((c
= *s
++)))
2085 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2101 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2102 && no_undeclared_regs
&& ! globals
[mask
])
2103 as_bad (_("detected global register use not covered by .register pseudo-op"));
2105 /* Got the register, now figure out where
2106 it goes in the opcode. */
2110 opcode
|= mask
<< 14;
2118 opcode
|= mask
<< 25;
2122 opcode
|= (mask
<< 25) | (mask
<< 14);
2126 opcode
|= (mask
<< 25) | (mask
<< 0);
2132 case 'e': /* next operand is a floating point register */
2150 && ((format
= *s
) == 'f')
2153 for (mask
= 0; ISDIGIT (*s
); ++s
)
2155 mask
= 10 * mask
+ (*s
- '0');
2156 } /* read the number */
2165 } /* register must be even numbered */
2173 } /* register must be multiple of 4 */
2177 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2178 error_message
= _(": There are only 64 f registers; [0-63]");
2180 error_message
= _(": There are only 32 f registers; [0-31]");
2183 else if (mask
>= 32)
2185 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2187 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2190 = _(": There are only 32 single precision f registers; [0-31]");
2194 mask
-= 31; /* wrap high bit */
2198 error_message
= _(": There are only 32 f registers; [0-31]");
2206 } /* if not an 'f' register. */
2213 opcode
|= RS1 (mask
);
2219 opcode
|= RS2 (mask
);
2224 opcode
|= RS3 (mask
);
2230 opcode
|= RD (mask
);
2239 if (strncmp (s
, "%fsr", 4) == 0)
2247 if (strncmp (s
, "%efsr", 5) == 0)
2254 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2255 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2258 case 'l': /* 22 bit PC relative immediate */
2259 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2263 case 'L': /* 30 bit immediate */
2264 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2269 case 'n': /* 22 bit immediate */
2270 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2273 case 'i': /* 13 bit immediate */
2274 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2284 char *op_arg
= NULL
;
2285 static expressionS op_exp
;
2286 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2288 /* Check for %hi, etc. */
2291 static const struct ops
{
2292 /* The name as it appears in assembler. */
2294 /* strlen (name), precomputed for speed */
2296 /* The reloc this pseudo-op translates to. */
2298 /* Non-zero if for v9 only. */
2300 /* Non-zero if can be used in pc-relative contexts. */
2301 int pcrel_p
;/*FIXME:wip*/
2303 /* hix/lox must appear before hi/lo so %hix won't be
2304 mistaken for %hi. */
2305 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2306 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2307 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2308 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2309 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2310 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2311 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2312 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2313 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2314 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2315 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2316 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2317 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2318 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2319 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2320 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2321 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2322 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2323 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2325 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2327 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2328 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2329 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2330 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2331 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2333 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2335 { NULL
, 0, 0, 0, 0 }
2337 const struct ops
*o
;
2339 for (o
= ops
; o
->name
; o
++)
2340 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2342 if (o
->name
== NULL
)
2345 if (s
[o
->len
+ 1] != '(')
2347 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2348 return special_case
;
2352 the_insn
.reloc
= o
->reloc
;
2357 /* Note that if the get_expression() fails, we will still
2358 have created U entries in the symbol table for the
2359 'symbols' in the input string. Try not to create U
2360 symbols for registers, etc. */
2362 /* This stuff checks to see if the expression ends in
2363 +%reg. If it does, it removes the register from
2364 the expression, and re-sets 's' to point to the
2371 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2374 else if (*s1
== ')')
2383 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2384 return special_case
;
2388 (void) get_expression (s
);
2391 if (*s
== ',' || *s
== ']' || !*s
)
2393 if (*s
!= '+' && *s
!= '-')
2395 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2396 return special_case
;
2400 op_exp
= the_insn
.exp
;
2401 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2404 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2407 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2409 if (s1
[-2] == '%' && s1
[-3] == '+')
2411 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2418 if (op_arg
&& s1
== s
+ 1)
2419 the_insn
.exp
.X_op
= O_absent
;
2421 (void) get_expression (s
);
2433 (void) get_expression (s
);
2441 the_insn
.exp2
= the_insn
.exp
;
2442 the_insn
.exp
= op_exp
;
2443 if (the_insn
.exp2
.X_op
== O_absent
)
2444 the_insn
.exp2
.X_op
= O_illegal
;
2445 else if (the_insn
.exp
.X_op
== O_absent
)
2447 the_insn
.exp
= the_insn
.exp2
;
2448 the_insn
.exp2
.X_op
= O_illegal
;
2450 else if (the_insn
.exp
.X_op
== O_constant
)
2452 valueT val
= the_insn
.exp
.X_add_number
;
2453 switch (the_insn
.reloc
)
2458 case BFD_RELOC_SPARC_HH22
:
2459 val
= BSR (val
, 32);
2462 case BFD_RELOC_SPARC_LM22
:
2463 case BFD_RELOC_HI22
:
2464 val
= (val
>> 10) & 0x3fffff;
2467 case BFD_RELOC_SPARC_HM10
:
2468 val
= BSR (val
, 32);
2471 case BFD_RELOC_LO10
:
2475 case BFD_RELOC_SPARC_H44
:
2480 case BFD_RELOC_SPARC_M44
:
2485 case BFD_RELOC_SPARC_L44
:
2489 case BFD_RELOC_SPARC_HIX22
:
2491 val
= (val
>> 10) & 0x3fffff;
2494 case BFD_RELOC_SPARC_LOX10
:
2495 val
= (val
& 0x3ff) | 0x1c00;
2498 the_insn
.exp
= the_insn
.exp2
;
2499 the_insn
.exp
.X_add_number
+= val
;
2500 the_insn
.exp2
.X_op
= O_illegal
;
2501 the_insn
.reloc
= old_reloc
;
2503 else if (the_insn
.exp2
.X_op
!= O_constant
)
2505 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2506 return special_case
;
2510 if (old_reloc
!= BFD_RELOC_SPARC13
2511 || the_insn
.reloc
!= BFD_RELOC_LO10
2512 || sparc_arch_size
!= 64
2515 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2516 return special_case
;
2518 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2522 /* Check for constants that don't require emitting a reloc. */
2523 if (the_insn
.exp
.X_op
== O_constant
2524 && the_insn
.exp
.X_add_symbol
== 0
2525 && the_insn
.exp
.X_op_symbol
== 0)
2527 /* For pc-relative call instructions, we reject
2528 constants to get better code. */
2530 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2531 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2533 error_message
= _(": PC-relative operand can't be a constant");
2537 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2538 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2540 error_message
= _(": TLS operand can't be a constant");
2544 /* Constants that won't fit are checked in md_apply_fix
2545 and bfd_install_relocation.
2546 ??? It would be preferable to install the constants
2547 into the insn here and save having to create a fixS
2548 for each one. There already exists code to handle
2549 all the various cases (e.g. in md_apply_fix and
2550 bfd_install_relocation) so duplicating all that code
2551 here isn't right. */
2571 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2573 error_message
= _(": invalid ASI name");
2579 if (! parse_const_expr_arg (&s
, &asi
))
2581 error_message
= _(": invalid ASI expression");
2584 if (asi
< 0 || asi
> 255)
2586 error_message
= _(": invalid ASI number");
2590 opcode
|= ASI (asi
);
2592 } /* Alternate space. */
2595 if (strncmp (s
, "%psr", 4) == 0)
2602 case 'q': /* Floating point queue. */
2603 if (strncmp (s
, "%fq", 3) == 0)
2610 case 'Q': /* Coprocessor queue. */
2611 if (strncmp (s
, "%cq", 3) == 0)
2619 if (strcmp (str
, "set") == 0
2620 || strcmp (str
, "setuw") == 0)
2622 special_case
= SPECIAL_CASE_SET
;
2625 else if (strcmp (str
, "setsw") == 0)
2627 special_case
= SPECIAL_CASE_SETSW
;
2630 else if (strcmp (str
, "setx") == 0)
2632 special_case
= SPECIAL_CASE_SETX
;
2635 else if (strncmp (str
, "fdiv", 4) == 0)
2637 special_case
= SPECIAL_CASE_FDIV
;
2643 if (strncmp (s
, "%asi", 4) != 0)
2649 if (strncmp (s
, "%fprs", 5) != 0)
2655 if (strncmp (s
, "%ccr", 4) != 0)
2661 if (strncmp (s
, "%tbr", 4) != 0)
2667 if (strncmp (s
, "%wim", 4) != 0)
2674 char *push
= input_line_pointer
;
2677 input_line_pointer
= s
;
2679 if (e
.X_op
== O_constant
)
2681 int n
= e
.X_add_number
;
2682 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2683 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2685 opcode
|= e
.X_add_number
<< 5;
2688 as_bad (_("non-immediate OPF operand, ignored"));
2689 s
= input_line_pointer
;
2690 input_line_pointer
= push
;
2695 if (strncmp (s
, "%y", 2) != 0)
2703 /* Parse a sparclet cpreg. */
2705 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2707 error_message
= _(": invalid cpreg name");
2710 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2715 as_fatal (_("failed sanity check."));
2716 } /* switch on arg code. */
2718 /* Break out of for() loop. */
2720 } /* For each arg that we expect. */
2725 /* Args don't match. */
2726 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2727 && (insn
->name
== insn
[1].name
2728 || !strcmp (insn
->name
, insn
[1].name
)))
2736 as_bad (_("Illegal operands%s"), error_message
);
2737 return special_case
;
2742 /* We have a match. Now see if the architecture is OK. */
2743 int needed_arch_mask
= insn
->architecture
;
2748 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2749 if (! needed_arch_mask
)
2751 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2754 if (needed_arch_mask
2755 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2758 /* Can we bump up the architecture? */
2759 else if (needed_arch_mask
2760 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2762 enum sparc_opcode_arch_val needed_architecture
=
2763 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2764 & needed_arch_mask
);
2766 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2768 && needed_architecture
> warn_after_architecture
)
2770 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2771 sparc_opcode_archs
[current_architecture
].name
,
2772 sparc_opcode_archs
[needed_architecture
].name
,
2774 warn_after_architecture
= needed_architecture
;
2776 current_architecture
= needed_architecture
;
2779 /* ??? This seems to be a bit fragile. What if the next entry in
2780 the opcode table is the one we want and it is supported?
2781 It is possible to arrange the table today so that this can't
2782 happen but what about tomorrow? */
2785 int arch
, printed_one_p
= 0;
2787 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2789 /* Create a list of the architectures that support the insn. */
2790 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2792 arch
= sparc_ffs (needed_arch_mask
);
2793 while ((1 << arch
) <= needed_arch_mask
)
2795 if ((1 << arch
) & needed_arch_mask
)
2799 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2806 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2807 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2809 sparc_opcode_archs
[max_architecture
].name
);
2810 return special_case
;
2812 } /* If no match. */
2815 } /* Forever looking for a match. */
2817 the_insn
.opcode
= opcode
;
2818 return special_case
;
2821 /* Parse an argument that can be expressed as a keyword.
2822 (eg: #StoreStore or %ccfr).
2823 The result is a boolean indicating success.
2824 If successful, INPUT_POINTER is updated. */
2827 parse_keyword_arg (int (*lookup_fn
) (const char *),
2828 char **input_pointerP
,
2834 p
= *input_pointerP
;
2835 for (q
= p
+ (*p
== '#' || *p
== '%');
2836 ISALNUM (*q
) || *q
== '_';
2841 value
= (*lookup_fn
) (p
);
2846 *input_pointerP
= q
;
2850 /* Parse an argument that is a constant expression.
2851 The result is a boolean indicating success. */
2854 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
2856 char *save
= input_line_pointer
;
2859 input_line_pointer
= *input_pointerP
;
2860 /* The next expression may be something other than a constant
2861 (say if we're not processing the right variant of the insn).
2862 Don't call expression unless we're sure it will succeed as it will
2863 signal an error (which we want to defer until later). */
2864 /* FIXME: It might be better to define md_operand and have it recognize
2865 things like %asi, etc. but continuing that route through to the end
2866 is a lot of work. */
2867 if (*input_line_pointer
== '%')
2869 input_line_pointer
= save
;
2873 *input_pointerP
= input_line_pointer
;
2874 input_line_pointer
= save
;
2875 if (exp
.X_op
!= O_constant
)
2877 *valueP
= exp
.X_add_number
;
2881 /* Subroutine of sparc_ip to parse an expression. */
2884 get_expression (char *str
)
2889 save_in
= input_line_pointer
;
2890 input_line_pointer
= str
;
2891 seg
= expression (&the_insn
.exp
);
2892 if (seg
!= absolute_section
2893 && seg
!= text_section
2894 && seg
!= data_section
2895 && seg
!= bss_section
2896 && seg
!= undefined_section
)
2898 the_insn
.error
= _("bad segment");
2899 expr_end
= input_line_pointer
;
2900 input_line_pointer
= save_in
;
2903 expr_end
= input_line_pointer
;
2904 input_line_pointer
= save_in
;
2908 /* Subroutine of md_assemble to output one insn. */
2911 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
2913 char *toP
= frag_more (4);
2915 /* Put out the opcode. */
2916 if (INSN_BIG_ENDIAN
)
2917 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
2919 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
2921 /* Put out the symbol-dependent stuff. */
2922 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
2924 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2925 (toP
- frag_now
->fr_literal
), /* Where. */
2930 /* Turn off overflow checking in fixup_segment. We'll do our
2931 own overflow checking in md_apply_fix. This is necessary because
2932 the insn size is 4 and fixup_segment will signal an overflow for
2933 large 8 byte quantities. */
2934 fixP
->fx_no_overflow
= 1;
2935 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2936 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
2940 last_opcode
= theinsn
->opcode
;
2943 dwarf2_emit_insn (4);
2948 md_atof (int type
, char *litP
, int *sizeP
)
2950 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
2953 /* Write a value out to the object file, using the appropriate
2957 md_number_to_chars (char *buf
, valueT val
, int n
)
2959 if (target_big_endian
)
2960 number_to_chars_bigendian (buf
, val
, n
);
2961 else if (target_little_endian_data
2962 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2963 /* Output debug words, which are not in allocated sections, as big
2965 number_to_chars_bigendian (buf
, val
, n
);
2966 else if (target_little_endian_data
|| ! target_big_endian
)
2967 number_to_chars_littleendian (buf
, val
, n
);
2970 /* Apply a fixS to the frags, now that we know the value it ought to
2974 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
2976 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2977 offsetT val
= * (offsetT
*) valP
;
2980 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2982 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
2985 /* SPARC ELF relocations don't use an addend in the data field. */
2986 if (fixP
->fx_addsy
!= NULL
)
2988 switch (fixP
->fx_r_type
)
2990 case BFD_RELOC_SPARC_TLS_GD_HI22
:
2991 case BFD_RELOC_SPARC_TLS_GD_LO10
:
2992 case BFD_RELOC_SPARC_TLS_GD_ADD
:
2993 case BFD_RELOC_SPARC_TLS_GD_CALL
:
2994 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
2995 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
2996 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
2997 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
2998 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
2999 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3000 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3001 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3002 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3003 case BFD_RELOC_SPARC_TLS_IE_LD
:
3004 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3005 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3006 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3007 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3008 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3009 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3010 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3011 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3012 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3013 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3014 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3024 /* This is a hack. There should be a better way to
3025 handle this. Probably in terms of howto fields, once
3026 we can look at these fixups in terms of howtos. */
3027 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3028 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3031 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3032 generate a reloc, then we just want to let the reloc addend set
3033 the value. We do not want to also stuff the addend into the
3034 object file. Including the addend in the object file works when
3035 doing a static link, because the linker will ignore the object
3036 file contents. However, the dynamic linker does not ignore the
3037 object file contents. */
3038 if (fixP
->fx_addsy
!= NULL
3039 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3042 /* When generating PIC code, we do not want an addend for a reloc
3043 against a local symbol. We adjust fx_addnumber to cancel out the
3044 value already included in val, and to also cancel out the
3045 adjustment which bfd_install_relocation will create. */
3047 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3048 && fixP
->fx_addsy
!= NULL
3049 && ! S_IS_COMMON (fixP
->fx_addsy
)
3050 && symbol_section_p (fixP
->fx_addsy
))
3051 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3053 /* When generating PIC code, we need to fiddle to get
3054 bfd_install_relocation to do the right thing for a PC relative
3055 reloc against a local symbol which we are going to keep. */
3057 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3058 && fixP
->fx_addsy
!= NULL
3059 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3060 || S_IS_WEAK (fixP
->fx_addsy
))
3061 && S_IS_DEFINED (fixP
->fx_addsy
)
3062 && ! S_IS_COMMON (fixP
->fx_addsy
))
3065 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3069 /* If this is a data relocation, just output VAL. */
3071 if (fixP
->fx_r_type
== BFD_RELOC_16
3072 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3074 md_number_to_chars (buf
, val
, 2);
3076 else if (fixP
->fx_r_type
== BFD_RELOC_32
3077 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3078 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3080 md_number_to_chars (buf
, val
, 4);
3082 else if (fixP
->fx_r_type
== BFD_RELOC_64
3083 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3085 md_number_to_chars (buf
, val
, 8);
3087 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3088 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3095 /* It's a relocation against an instruction. */
3097 if (INSN_BIG_ENDIAN
)
3098 insn
= bfd_getb32 ((unsigned char *) buf
);
3100 insn
= bfd_getl32 ((unsigned char *) buf
);
3102 switch (fixP
->fx_r_type
)
3104 case BFD_RELOC_32_PCREL_S2
:
3106 /* FIXME: This increment-by-one deserves a comment of why it's
3108 if (! sparc_pic_code
3109 || fixP
->fx_addsy
== NULL
3110 || symbol_section_p (fixP
->fx_addsy
))
3113 insn
|= val
& 0x3fffffff;
3115 /* See if we have a delay slot. */
3116 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3120 #define XCC (2 << 20)
3121 #define COND(x) (((x)&0xf)<<25)
3122 #define CONDA COND(0x8)
3123 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3124 #define INSN_BA (F2(0,2) | CONDA)
3125 #define INSN_OR F3(2, 0x2, 0)
3126 #define INSN_NOP F2(0,4)
3130 /* If the instruction is a call with either:
3132 arithmetic instruction with rd == %o7
3133 where rs1 != %o7 and rs2 if it is register != %o7
3134 then we can optimize if the call destination is near
3135 by changing the call into a branch always. */
3136 if (INSN_BIG_ENDIAN
)
3137 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3139 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3140 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3142 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3143 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3144 || ((delay
& RD (~0)) != RD (O7
))))
3146 if ((delay
& RS1 (~0)) == RS1 (O7
)
3147 || ((delay
& F3I (~0)) == 0
3148 && (delay
& RS2 (~0)) == RS2 (O7
)))
3150 /* Ensure the branch will fit into simm22. */
3151 if ((val
& 0x3fe00000)
3152 && (val
& 0x3fe00000) != 0x3fe00000)
3154 /* Check if the arch is v9 and branch will fit
3156 if (((val
& 0x3c0000) == 0
3157 || (val
& 0x3c0000) == 0x3c0000)
3158 && (sparc_arch_size
== 64
3159 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3161 insn
= INSN_BPA
| (val
& 0x7ffff);
3164 insn
= INSN_BA
| (val
& 0x3fffff);
3165 if (fixP
->fx_where
>= 4
3166 && ((delay
& (0xffffffff ^ RS1 (~0)))
3167 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3172 if (INSN_BIG_ENDIAN
)
3173 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3175 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3176 if ((setter
& (0xffffffff ^ RD (~0)))
3177 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3184 If call foo was replaced with ba, replace
3185 or %rN, %g0, %o7 with nop. */
3186 reg
= (delay
& RS1 (~0)) >> 14;
3187 if (reg
!= ((setter
& RD (~0)) >> 25)
3188 || reg
== G0
|| reg
== O7
)
3191 if (INSN_BIG_ENDIAN
)
3192 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3194 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3199 case BFD_RELOC_SPARC_11
:
3200 if (! in_signed_range (val
, 0x7ff))
3201 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3202 _("relocation overflow"));
3203 insn
|= val
& 0x7ff;
3206 case BFD_RELOC_SPARC_10
:
3207 if (! in_signed_range (val
, 0x3ff))
3208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3209 _("relocation overflow"));
3210 insn
|= val
& 0x3ff;
3213 case BFD_RELOC_SPARC_7
:
3214 if (! in_bitfield_range (val
, 0x7f))
3215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3216 _("relocation overflow"));
3220 case BFD_RELOC_SPARC_6
:
3221 if (! in_bitfield_range (val
, 0x3f))
3222 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3223 _("relocation overflow"));
3227 case BFD_RELOC_SPARC_5
:
3228 if (! in_bitfield_range (val
, 0x1f))
3229 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3230 _("relocation overflow"));
3234 case BFD_RELOC_SPARC_WDISP16
:
3237 || val
<= -(offsetT
) 0x20008)
3238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3239 _("relocation overflow"));
3240 /* FIXME: The +1 deserves a comment. */
3241 val
= (val
>> 2) + 1;
3242 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3245 case BFD_RELOC_SPARC_WDISP19
:
3248 || val
<= -(offsetT
) 0x100008)
3249 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3250 _("relocation overflow"));
3251 /* FIXME: The +1 deserves a comment. */
3252 val
= (val
>> 2) + 1;
3253 insn
|= val
& 0x7ffff;
3256 case BFD_RELOC_SPARC_HH22
:
3257 val
= BSR (val
, 32);
3260 case BFD_RELOC_SPARC_LM22
:
3261 case BFD_RELOC_HI22
:
3262 if (!fixP
->fx_addsy
)
3263 insn
|= (val
>> 10) & 0x3fffff;
3265 /* FIXME: Need comment explaining why we do this. */
3269 case BFD_RELOC_SPARC22
:
3270 if (val
& ~0x003fffff)
3271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3272 _("relocation overflow"));
3273 insn
|= (val
& 0x3fffff);
3276 case BFD_RELOC_SPARC_HM10
:
3277 val
= BSR (val
, 32);
3280 case BFD_RELOC_LO10
:
3281 if (!fixP
->fx_addsy
)
3282 insn
|= val
& 0x3ff;
3284 /* FIXME: Need comment explaining why we do this. */
3288 case BFD_RELOC_SPARC_OLO10
:
3290 val
+= fixP
->tc_fix_data
;
3293 case BFD_RELOC_SPARC13
:
3294 if (! in_signed_range (val
, 0x1fff))
3295 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3296 _("relocation overflow"));
3297 insn
|= val
& 0x1fff;
3300 case BFD_RELOC_SPARC_WDISP22
:
3301 val
= (val
>> 2) + 1;
3303 case BFD_RELOC_SPARC_BASE22
:
3304 insn
|= val
& 0x3fffff;
3307 case BFD_RELOC_SPARC_H44
:
3308 if (!fixP
->fx_addsy
)
3312 insn
|= tval
& 0x3fffff;
3316 case BFD_RELOC_SPARC_M44
:
3317 if (!fixP
->fx_addsy
)
3318 insn
|= (val
>> 12) & 0x3ff;
3321 case BFD_RELOC_SPARC_L44
:
3322 if (!fixP
->fx_addsy
)
3323 insn
|= val
& 0xfff;
3326 case BFD_RELOC_SPARC_HIX22
:
3327 if (!fixP
->fx_addsy
)
3329 val
^= ~(offsetT
) 0;
3330 insn
|= (val
>> 10) & 0x3fffff;
3334 case BFD_RELOC_SPARC_LOX10
:
3335 if (!fixP
->fx_addsy
)
3336 insn
|= 0x1c00 | (val
& 0x3ff);
3339 case BFD_RELOC_NONE
:
3341 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3342 _("bad or unhandled relocation type: 0x%02x"),
3347 if (INSN_BIG_ENDIAN
)
3348 bfd_putb32 (insn
, (unsigned char *) buf
);
3350 bfd_putl32 (insn
, (unsigned char *) buf
);
3353 /* Are we finished with this relocation now? */
3354 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3358 /* Translate internal representation of relocation info to BFD target
3362 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3364 static arelent
*relocs
[3];
3366 bfd_reloc_code_real_type code
;
3368 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3371 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3372 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3373 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3375 switch (fixp
->fx_r_type
)
3379 case BFD_RELOC_HI22
:
3380 case BFD_RELOC_LO10
:
3381 case BFD_RELOC_32_PCREL_S2
:
3382 case BFD_RELOC_SPARC13
:
3383 case BFD_RELOC_SPARC22
:
3384 case BFD_RELOC_SPARC_PC22
:
3385 case BFD_RELOC_SPARC_PC10
:
3386 case BFD_RELOC_SPARC_BASE13
:
3387 case BFD_RELOC_SPARC_WDISP16
:
3388 case BFD_RELOC_SPARC_WDISP19
:
3389 case BFD_RELOC_SPARC_WDISP22
:
3391 case BFD_RELOC_SPARC_5
:
3392 case BFD_RELOC_SPARC_6
:
3393 case BFD_RELOC_SPARC_7
:
3394 case BFD_RELOC_SPARC_10
:
3395 case BFD_RELOC_SPARC_11
:
3396 case BFD_RELOC_SPARC_HH22
:
3397 case BFD_RELOC_SPARC_HM10
:
3398 case BFD_RELOC_SPARC_LM22
:
3399 case BFD_RELOC_SPARC_PC_HH22
:
3400 case BFD_RELOC_SPARC_PC_HM10
:
3401 case BFD_RELOC_SPARC_PC_LM22
:
3402 case BFD_RELOC_SPARC_H44
:
3403 case BFD_RELOC_SPARC_M44
:
3404 case BFD_RELOC_SPARC_L44
:
3405 case BFD_RELOC_SPARC_HIX22
:
3406 case BFD_RELOC_SPARC_LOX10
:
3407 case BFD_RELOC_SPARC_REV32
:
3408 case BFD_RELOC_SPARC_OLO10
:
3409 case BFD_RELOC_SPARC_UA16
:
3410 case BFD_RELOC_SPARC_UA32
:
3411 case BFD_RELOC_SPARC_UA64
:
3412 case BFD_RELOC_8_PCREL
:
3413 case BFD_RELOC_16_PCREL
:
3414 case BFD_RELOC_32_PCREL
:
3415 case BFD_RELOC_64_PCREL
:
3416 case BFD_RELOC_SPARC_PLT32
:
3417 case BFD_RELOC_SPARC_PLT64
:
3418 case BFD_RELOC_VTABLE_ENTRY
:
3419 case BFD_RELOC_VTABLE_INHERIT
:
3420 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3421 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3422 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3423 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3424 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3425 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3426 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3427 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3428 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3429 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3430 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3431 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3432 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3433 case BFD_RELOC_SPARC_TLS_IE_LD
:
3434 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3435 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3436 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3437 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3438 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3439 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3440 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3441 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3442 case BFD_RELOC_SPARC_GOTDATA_OP
:
3443 code
= fixp
->fx_r_type
;
3450 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3451 /* If we are generating PIC code, we need to generate a different
3455 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3457 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3460 #define GOTT_BASE "__GOTT_BASE__"
3461 #define GOTT_INDEX "__GOTT_INDEX__"
3464 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3470 case BFD_RELOC_32_PCREL_S2
:
3471 if (generic_force_reloc (fixp
))
3472 code
= BFD_RELOC_SPARC_WPLT30
;
3474 case BFD_RELOC_HI22
:
3475 code
= BFD_RELOC_SPARC_GOT22
;
3476 if (fixp
->fx_addsy
!= NULL
)
3478 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3479 code
= BFD_RELOC_SPARC_PC22
;
3481 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3482 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3483 code
= BFD_RELOC_HI22
; /* Unchanged. */
3487 case BFD_RELOC_LO10
:
3488 code
= BFD_RELOC_SPARC_GOT10
;
3489 if (fixp
->fx_addsy
!= NULL
)
3491 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3492 code
= BFD_RELOC_SPARC_PC10
;
3494 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3495 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3496 code
= BFD_RELOC_LO10
; /* Unchanged. */
3500 case BFD_RELOC_SPARC13
:
3501 code
= BFD_RELOC_SPARC_GOT13
;
3507 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3509 /* Nothing is aligned in DWARF debugging sections. */
3510 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3513 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3514 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3515 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3519 if (code
== BFD_RELOC_SPARC_OLO10
)
3520 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3522 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3523 if (reloc
->howto
== 0)
3525 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3526 _("internal error: can't export reloc type %d (`%s')"),
3527 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3533 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3536 if (reloc
->howto
->pc_relative
== 0
3537 || code
== BFD_RELOC_SPARC_PC10
3538 || code
== BFD_RELOC_SPARC_PC22
)
3539 reloc
->addend
= fixp
->fx_addnumber
;
3540 else if (sparc_pic_code
3541 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3542 && fixp
->fx_addsy
!= NULL
3543 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3544 || S_IS_WEAK (fixp
->fx_addsy
))
3545 && S_IS_DEFINED (fixp
->fx_addsy
)
3546 && ! S_IS_COMMON (fixp
->fx_addsy
))
3547 reloc
->addend
= fixp
->fx_addnumber
;
3549 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3551 #else /* elf or coff */
3553 if (code
!= BFD_RELOC_32_PCREL_S2
3554 && code
!= BFD_RELOC_SPARC_WDISP22
3555 && code
!= BFD_RELOC_SPARC_WDISP16
3556 && code
!= BFD_RELOC_SPARC_WDISP19
3557 && code
!= BFD_RELOC_SPARC_WPLT30
3558 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3559 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3560 reloc
->addend
= fixp
->fx_addnumber
;
3561 else if (symbol_section_p (fixp
->fx_addsy
))
3562 reloc
->addend
= (section
->vma
3563 + fixp
->fx_addnumber
3564 + md_pcrel_from (fixp
));
3566 reloc
->addend
= fixp
->fx_offset
;
3569 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3570 on the same location. */
3571 if (code
== BFD_RELOC_SPARC_OLO10
)
3573 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3576 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3578 = symbol_get_bfdsym (section_symbol (absolute_section
));
3579 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3580 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3581 reloc
->addend
= fixp
->tc_fix_data
;
3587 /* We have no need to default values of symbols. */
3590 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
3595 /* Round up a section size to the appropriate boundary. */
3598 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
3601 /* This is not right for ELF; a.out wants it, and COFF will force
3602 the alignment anyways. */
3603 valueT align
= ((valueT
) 1
3604 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3607 /* Turn alignment value into a mask. */
3609 newsize
= (size
+ align
) & ~align
;
3616 /* Exactly what point is a PC-relative offset relative TO?
3617 On the sparc, they're relative to the address of the offset, plus
3618 its size. This gets us to the following instruction.
3619 (??? Is this right? FIXME-SOON) */
3621 md_pcrel_from (fixS
*fixP
)
3625 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3626 if (! sparc_pic_code
3627 || fixP
->fx_addsy
== NULL
3628 || symbol_section_p (fixP
->fx_addsy
))
3629 ret
+= fixP
->fx_size
;
3633 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3644 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3647 return (value
== 1) ? shift
: -1;
3650 /* Sort of like s_lcomm. */
3653 static int max_alignment
= 15;
3657 s_reserve (int ignore ATTRIBUTE_UNUSED
)
3667 name
= input_line_pointer
;
3668 c
= get_symbol_end ();
3669 p
= input_line_pointer
;
3673 if (*input_line_pointer
!= ',')
3675 as_bad (_("Expected comma after name"));
3676 ignore_rest_of_line ();
3680 ++input_line_pointer
;
3682 if ((size
= get_absolute_expression ()) < 0)
3684 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3685 ignore_rest_of_line ();
3690 symbolP
= symbol_find_or_make (name
);
3693 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3694 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3696 as_bad (_("bad .reserve segment -- expected BSS segment"));
3700 if (input_line_pointer
[2] == '.')
3701 input_line_pointer
+= 7;
3703 input_line_pointer
+= 6;
3706 if (*input_line_pointer
== ',')
3708 ++input_line_pointer
;
3711 if (*input_line_pointer
== '\n')
3713 as_bad (_("missing alignment"));
3714 ignore_rest_of_line ();
3718 align
= (int) get_absolute_expression ();
3721 if (align
> max_alignment
)
3723 align
= max_alignment
;
3724 as_warn (_("alignment too large; assuming %d"), align
);
3730 as_bad (_("negative alignment"));
3731 ignore_rest_of_line ();
3737 temp
= mylog2 (align
);
3740 as_bad (_("alignment not a power of 2"));
3741 ignore_rest_of_line ();
3748 record_alignment (bss_section
, align
);
3753 if (!S_IS_DEFINED (symbolP
)
3755 && S_GET_OTHER (symbolP
) == 0
3756 && S_GET_DESC (symbolP
) == 0
3763 segT current_seg
= now_seg
;
3764 subsegT current_subseg
= now_subseg
;
3766 /* Switch to bss. */
3767 subseg_set (bss_section
, 1);
3771 frag_align (align
, 0, 0);
3773 /* Detach from old frag. */
3774 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3775 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3777 symbol_set_frag (symbolP
, frag_now
);
3778 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3779 (offsetT
) size
, (char *) 0);
3782 S_SET_SEGMENT (symbolP
, bss_section
);
3784 subseg_set (current_seg
, current_subseg
);
3787 S_SET_SIZE (symbolP
, size
);
3793 as_warn (_("Ignoring attempt to re-define symbol %s"),
3794 S_GET_NAME (symbolP
));
3797 demand_empty_rest_of_line ();
3801 s_common (int ignore ATTRIBUTE_UNUSED
)
3809 name
= input_line_pointer
;
3810 c
= get_symbol_end ();
3811 /* Just after name is now '\0'. */
3812 p
= input_line_pointer
;
3815 if (*input_line_pointer
!= ',')
3817 as_bad (_("Expected comma after symbol-name"));
3818 ignore_rest_of_line ();
3823 input_line_pointer
++;
3825 if ((temp
= get_absolute_expression ()) < 0)
3827 as_bad (_(".COMMon length (%lu) out of range ignored"),
3828 (unsigned long) temp
);
3829 ignore_rest_of_line ();
3834 symbolP
= symbol_find_or_make (name
);
3836 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3838 as_bad (_("Ignoring attempt to re-define symbol"));
3839 ignore_rest_of_line ();
3842 if (S_GET_VALUE (symbolP
) != 0)
3844 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3846 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3847 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
3853 S_SET_VALUE (symbolP
, (valueT
) size
);
3854 S_SET_EXTERNAL (symbolP
);
3857 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3858 if (*input_line_pointer
!= ',')
3860 as_bad (_("Expected comma after common length"));
3861 ignore_rest_of_line ();
3864 input_line_pointer
++;
3866 if (*input_line_pointer
!= '"')
3868 temp
= get_absolute_expression ();
3871 if (temp
> max_alignment
)
3873 temp
= max_alignment
;
3874 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
3880 as_bad (_("negative alignment"));
3881 ignore_rest_of_line ();
3886 if (symbol_get_obj (symbolP
)->local
)
3893 old_subsec
= now_subseg
;
3898 align
= mylog2 (temp
);
3902 as_bad (_("alignment not a power of 2"));
3903 ignore_rest_of_line ();
3907 record_alignment (bss_section
, align
);
3908 subseg_set (bss_section
, 0);
3910 frag_align (align
, 0, 0);
3911 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3912 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3913 symbol_set_frag (symbolP
, frag_now
);
3914 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3915 (offsetT
) size
, (char *) 0);
3917 S_SET_SEGMENT (symbolP
, bss_section
);
3918 S_CLEAR_EXTERNAL (symbolP
);
3919 S_SET_SIZE (symbolP
, size
);
3920 subseg_set (old_sec
, old_subsec
);
3923 #endif /* OBJ_ELF */
3926 S_SET_VALUE (symbolP
, (valueT
) size
);
3928 S_SET_ALIGN (symbolP
, temp
);
3929 S_SET_SIZE (symbolP
, size
);
3931 S_SET_EXTERNAL (symbolP
);
3932 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3937 input_line_pointer
++;
3938 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3939 if (*input_line_pointer
== '.')
3940 input_line_pointer
++;
3941 /* @@ Some say data, some say bss. */
3942 if (strncmp (input_line_pointer
, "bss\"", 4)
3943 && strncmp (input_line_pointer
, "data\"", 5))
3945 while (*--input_line_pointer
!= '"')
3947 input_line_pointer
--;
3948 goto bad_common_segment
;
3950 while (*input_line_pointer
++ != '"')
3952 goto allocate_common
;
3955 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3957 demand_empty_rest_of_line ();
3962 p
= input_line_pointer
;
3963 while (*p
&& *p
!= '\n')
3967 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3969 input_line_pointer
= p
;
3970 ignore_rest_of_line ();
3975 /* Handle the .empty pseudo-op. This suppresses the warnings about
3976 invalid delay slot usage. */
3979 s_empty (int ignore ATTRIBUTE_UNUSED
)
3981 /* The easy way to implement is to just forget about the last
3987 s_seg (int ignore ATTRIBUTE_UNUSED
)
3990 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3992 input_line_pointer
+= 6;
3996 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3998 input_line_pointer
+= 6;
4002 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4004 input_line_pointer
+= 7;
4008 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4010 input_line_pointer
+= 5;
4011 /* We only support 2 segments -- text and data -- for now, so
4012 things in the "bss segment" will have to go into data for now.
4013 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4014 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4017 as_bad (_("Unknown segment type"));
4018 demand_empty_rest_of_line ();
4024 subseg_set (data_section
, 1);
4025 demand_empty_rest_of_line ();
4029 s_proc (int ignore ATTRIBUTE_UNUSED
)
4031 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4033 ++input_line_pointer
;
4035 ++input_line_pointer
;
4038 /* This static variable is set by s_uacons to tell sparc_cons_align
4039 that the expression does not need to be aligned. */
4041 static int sparc_no_align_cons
= 0;
4043 /* This static variable is set by sparc_cons to emit requested types
4044 of relocations in cons_fix_new_sparc. */
4046 static const char *sparc_cons_special_reloc
;
4048 /* This handles the unaligned space allocation pseudo-ops, such as
4049 .uaword. .uaword is just like .word, but the value does not need
4053 s_uacons (int bytes
)
4055 /* Tell sparc_cons_align not to align this value. */
4056 sparc_no_align_cons
= 1;
4058 sparc_no_align_cons
= 0;
4061 /* This handles the native word allocation pseudo-op .nword.
4062 For sparc_arch_size 32 it is equivalent to .word, for
4063 sparc_arch_size 64 it is equivalent to .xword. */
4066 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4068 cons (sparc_arch_size
== 32 ? 4 : 8);
4072 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4076 .register %g[2367],{#scratch|symbolname|#ignore}
4080 s_register (int ignore ATTRIBUTE_UNUSED
)
4085 const char *regname
;
4087 if (input_line_pointer
[0] != '%'
4088 || input_line_pointer
[1] != 'g'
4089 || ((input_line_pointer
[2] & ~1) != '2'
4090 && (input_line_pointer
[2] & ~1) != '6')
4091 || input_line_pointer
[3] != ',')
4092 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4093 reg
= input_line_pointer
[2] - '0';
4094 input_line_pointer
+= 4;
4096 if (*input_line_pointer
== '#')
4098 ++input_line_pointer
;
4099 regname
= input_line_pointer
;
4100 c
= get_symbol_end ();
4101 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4102 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4103 if (regname
[0] == 'i')
4110 regname
= input_line_pointer
;
4111 c
= get_symbol_end ();
4113 if (sparc_arch_size
== 64)
4117 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4118 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4119 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4120 as_bad (_("redefinition of global register"));
4124 if (regname
== NULL
)
4125 globals
[reg
] = (symbolS
*) 1;
4130 if (symbol_find (regname
))
4131 as_bad (_("Register symbol %s already defined."),
4134 globals
[reg
] = symbol_make (regname
);
4135 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4137 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4138 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4139 flags
|= BSF_GLOBAL
;
4140 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4141 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4142 S_SET_ALIGN (globals
[reg
], reg
);
4143 S_SET_SIZE (globals
[reg
], 0);
4144 /* Although we actually want undefined_section here,
4145 we have to use absolute_section, because otherwise
4146 generic as code will make it a COM section.
4147 We fix this up in sparc_adjust_symtab. */
4148 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4149 S_SET_OTHER (globals
[reg
], 0);
4150 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4151 ->internal_elf_sym
.st_info
=
4152 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4153 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4154 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4159 *input_line_pointer
= c
;
4161 demand_empty_rest_of_line ();
4164 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4165 symbols which need it. */
4168 sparc_adjust_symtab (void)
4172 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4174 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4175 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4178 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4179 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4182 S_SET_SEGMENT (sym
, undefined_section
);
4187 /* If the --enforce-aligned-data option is used, we require .word,
4188 et. al., to be aligned correctly. We do it by setting up an
4189 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4190 no unexpected alignment was introduced.
4192 The SunOS and Solaris native assemblers enforce aligned data by
4193 default. We don't want to do that, because gcc can deliberately
4194 generate misaligned data if the packed attribute is used. Instead,
4195 we permit misaligned data by default, and permit the user to set an
4196 option to check for it. */
4199 sparc_cons_align (int nbytes
)
4203 /* Only do this if we are enforcing aligned data. */
4204 if (! enforce_aligned_data
)
4207 /* Don't align if this is an unaligned pseudo-op. */
4208 if (sparc_no_align_cons
)
4211 nalign
= mylog2 (nbytes
);
4215 gas_assert (nalign
> 0);
4217 if (now_seg
== absolute_section
)
4219 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4220 as_bad (_("misaligned data"));
4224 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4225 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4227 record_alignment (now_seg
, nalign
);
4230 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4233 sparc_handle_align (fragS
*fragp
)
4238 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4240 switch (fragp
->fr_type
)
4244 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4248 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4259 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4261 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4262 if (INSN_BIG_ENDIAN
)
4263 number_to_chars_bigendian (p
, wval
, 4);
4265 number_to_chars_littleendian (p
, wval
, 4);
4271 if (INSN_BIG_ENDIAN
)
4272 number_to_chars_bigendian (p
, 0x01000000, 4);
4274 number_to_chars_littleendian (p
, 0x01000000, 4);
4276 fragp
->fr_fix
+= fix
;
4286 /* Some special processing for a Sparc ELF file. */
4289 sparc_elf_final_processing (void)
4291 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4292 sort of BFD interface for this. */
4293 if (sparc_arch_size
== 64)
4295 switch (sparc_memory_model
)
4298 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4301 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4307 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4308 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4309 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4310 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4311 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4312 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4316 sparc_cons (expressionS
*exp
, int size
)
4321 sparc_cons_special_reloc
= NULL
;
4322 save
= input_line_pointer
;
4323 if (input_line_pointer
[0] == '%'
4324 && input_line_pointer
[1] == 'r'
4325 && input_line_pointer
[2] == '_')
4327 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4329 input_line_pointer
+= 7;
4330 sparc_cons_special_reloc
= "disp";
4332 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4334 if (size
!= 4 && size
!= 8)
4335 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4338 input_line_pointer
+= 6;
4339 sparc_cons_special_reloc
= "plt";
4342 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4344 if (size
!= 4 && size
!= 8)
4345 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4348 input_line_pointer
+= 13;
4349 sparc_cons_special_reloc
= "tls_dtpoff";
4352 if (sparc_cons_special_reloc
)
4359 if (*input_line_pointer
!= '8')
4361 input_line_pointer
--;
4364 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4368 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4372 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4382 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4383 sparc_cons_special_reloc
, size
* 8, size
);
4387 input_line_pointer
+= 2;
4388 if (*input_line_pointer
!= '(')
4390 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4391 sparc_cons_special_reloc
, size
* 8);
4398 input_line_pointer
= save
;
4399 sparc_cons_special_reloc
= NULL
;
4404 char *end
= ++input_line_pointer
;
4407 while (! is_end_of_line
[(c
= *end
)])
4421 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4422 sparc_cons_special_reloc
, size
* 8);
4428 if (input_line_pointer
!= end
)
4430 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4431 sparc_cons_special_reloc
, size
* 8);
4435 input_line_pointer
++;
4437 c
= *input_line_pointer
;
4438 if (! is_end_of_line
[c
] && c
!= ',')
4439 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4440 sparc_cons_special_reloc
, size
* 8);
4446 if (sparc_cons_special_reloc
== NULL
)
4452 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4453 reloc for a cons. We could use the definition there, except that
4454 we want to handle little endian relocs specially. */
4457 cons_fix_new_sparc (fragS
*frag
,
4459 unsigned int nbytes
,
4462 bfd_reloc_code_real_type r
;
4464 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4465 (nbytes
== 2 ? BFD_RELOC_16
:
4466 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4468 if (target_little_endian_data
4470 && now_seg
->flags
& SEC_ALLOC
)
4471 r
= BFD_RELOC_SPARC_REV32
;
4473 if (sparc_cons_special_reloc
)
4475 if (*sparc_cons_special_reloc
== 'd')
4478 case 1: r
= BFD_RELOC_8_PCREL
; break;
4479 case 2: r
= BFD_RELOC_16_PCREL
; break;
4480 case 4: r
= BFD_RELOC_32_PCREL
; break;
4481 case 8: r
= BFD_RELOC_64_PCREL
; break;
4484 else if (*sparc_cons_special_reloc
== 'p')
4487 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4488 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4493 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4494 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4497 else if (sparc_no_align_cons
)
4501 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4502 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4503 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4508 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4509 sparc_cons_special_reloc
= NULL
;
4513 sparc_cfi_frame_initial_instructions (void)
4515 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4519 sparc_regname_to_dw2regnum (char *regname
)
4527 p
= strchr (q
, regname
[0]);
4530 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4532 return (p
- q
) * 8 + regname
[1] - '0';
4534 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4536 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4538 if (regname
[0] == 'f' || regname
[0] == 'r')
4540 unsigned int regnum
;
4542 regnum
= strtoul (regname
+ 1, &q
, 10);
4545 if (regnum
>= ((regname
[0] == 'f'
4546 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4549 if (regname
[0] == 'f')
4552 if (regnum
>= 64 && (regnum
& 1))
4561 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4563 sparc_cons_special_reloc
= "disp";
4564 sparc_no_align_cons
= 1;
4565 emit_expr (exp
, nbytes
);
4566 sparc_no_align_cons
= 0;
4567 sparc_cons_special_reloc
= NULL
;