1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41 static int sparc_ip (char *, const struct sparc_opcode
**);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
51 #define DEFAULT_ARCH "sparclite"
53 static char *default_arch
= DEFAULT_ARCH
;
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
57 static int default_init_p
;
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture
;
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size
;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size
;
76 /* The currently selected v9 memory model. Currently only used for
78 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen
;
87 static int architecture_requested
;
88 static int warn_on_bump
;
90 /* If warn_on_bump and the needed architecture is higher than this
91 architecture, issue a warning. */
92 static enum sparc_opcode_arch_val warn_after_architecture
;
94 /* Non-zero if as should generate error if an undeclared g[23] register
95 has been used in -64. */
96 static int no_undeclared_regs
;
98 /* Non-zero if we should try to relax jumps and calls. */
99 static int sparc_relax
;
101 /* Non-zero if we are generating PIC code. */
104 /* Non-zero if we should give an error when misaligned data is seen. */
105 static int enforce_aligned_data
;
107 extern int target_big_endian
;
109 static int target_little_endian_data
;
111 /* Symbols for global registers on v9. */
112 static symbolS
*globals
[8];
114 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
115 int sparc_cie_data_alignment
;
117 /* V9 and 86x have big and little endian data, but instructions are always big
118 endian. The sparclet has bi-endian support but both data and insns have
119 the same endianness. Global `target_big_endian' is used for data.
120 The following macro is used for instructions. */
121 #ifndef INSN_BIG_ENDIAN
122 #define INSN_BIG_ENDIAN (target_big_endian \
123 || default_arch_type == sparc86x \
124 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127 /* Handle of the OPCODE hash table. */
128 static struct hash_control
*op_hash
;
130 static void s_data1 (void);
131 static void s_seg (int);
132 static void s_proc (int);
133 static void s_reserve (int);
134 static void s_common (int);
135 static void s_empty (int);
136 static void s_uacons (int);
137 static void s_ncons (int);
139 static void s_register (int);
142 const pseudo_typeS md_pseudo_table
[] =
144 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
145 {"common", s_common
, 0},
146 {"empty", s_empty
, 0},
147 {"global", s_globl
, 0},
149 {"nword", s_ncons
, 0},
150 {"optim", s_ignore
, 0},
152 {"reserve", s_reserve
, 0},
154 {"skip", s_space
, 0},
157 {"uahalf", s_uacons
, 2},
158 {"uaword", s_uacons
, 4},
159 {"uaxword", s_uacons
, 8},
161 /* These are specific to sparc/svr4. */
162 {"2byte", s_uacons
, 2},
163 {"4byte", s_uacons
, 4},
164 {"8byte", s_uacons
, 8},
165 {"register", s_register
, 0},
170 /* This array holds the chars that always start a comment. If the
171 pre-processor is disabled, these aren't very useful. */
172 const char comment_chars
[] = "!"; /* JF removed '|' from
175 /* This array holds the chars that only start a comment at the beginning of
176 a line. If the line seems to have the form '# 123 filename'
177 .line and .file directives will appear in the pre-processed output. */
178 /* Note that input_file.c hand checks for '#' at the beginning of the
179 first line of the input file. This is because the compiler outputs
180 #NO_APP at the beginning of its output. */
181 /* Also note that comments started like this one will always
182 work if '/' isn't otherwise defined. */
183 const char line_comment_chars
[] = "#";
185 const char line_separator_chars
[] = ";";
187 /* Chars that can be used to separate mant from exp in floating point
189 const char EXP_CHARS
[] = "eE";
191 /* Chars that mean this number is a floating point constant.
194 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
196 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
197 changed in read.c. Ideally it shouldn't have to know about it at all,
198 but nothing is ideal around here. */
200 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
205 unsigned long opcode
;
206 struct nlist
*nlistp
;
210 bfd_reloc_code_real_type reloc
;
213 struct sparc_it the_insn
, set_insn
;
215 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
217 /* Table of arguments to -A.
218 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
219 for this use. That table is for opcodes only. This table is for opcodes
222 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
223 v8plusa
, v9
, v9a
, v9b
, v9_64
};
225 static struct sparc_arch
{
228 enum sparc_arch_types arch_type
;
229 /* Default word size, as specified during configuration.
230 A value of zero means can't be used to specify default architecture. */
231 int default_arch_size
;
232 /* Allowable arg to -A? */
234 } sparc_arch_table
[] = {
235 { "v6", "v6", v6
, 0, 1 },
236 { "v7", "v7", v7
, 0, 1 },
237 { "v8", "v8", v8
, 32, 1 },
238 { "sparclet", "sparclet", sparclet
, 32, 1 },
239 { "sparclite", "sparclite", sparclite
, 32, 1 },
240 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
241 { "v8plus", "v9", v9
, 0, 1 },
242 { "v8plusa", "v9a", v9
, 0, 1 },
243 { "v8plusb", "v9b", v9
, 0, 1 },
244 { "v9", "v9", v9
, 0, 1 },
245 { "v9a", "v9a", v9
, 0, 1 },
246 { "v9b", "v9b", v9
, 0, 1 },
247 /* This exists to allow configure.in/Makefile.in to pass one
248 value to specify both the default machine and default word size. */
249 { "v9-64", "v9", v9
, 64, 0 },
250 { NULL
, NULL
, v8
, 0, 0 }
253 /* Variant of default_arch */
254 static enum sparc_arch_types default_arch_type
;
256 static struct sparc_arch
*
257 lookup_arch (char *name
)
259 struct sparc_arch
*sa
;
261 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
262 if (strcmp (sa
->name
, name
) == 0)
264 if (sa
->name
== NULL
)
269 /* Initialize the default opcode arch and word size from the default
270 architecture name. */
273 init_default_arch (void)
275 struct sparc_arch
*sa
= lookup_arch (default_arch
);
278 || sa
->default_arch_size
== 0)
279 as_fatal (_("Invalid default architecture, broken assembler."));
281 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
282 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
283 as_fatal (_("Bad opcode table, broken assembler."));
284 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
286 default_arch_type
= sa
->arch_type
;
289 /* Called by TARGET_FORMAT. */
292 sparc_target_format (void)
294 /* We don't get a chance to initialize anything before we're called,
295 so handle that now. */
296 if (! default_init_p
)
297 init_default_arch ();
301 return "a.out-sparc-netbsd";
304 if (target_big_endian
)
305 return "a.out-sunos-big";
306 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
307 return "a.out-sunos-big";
309 return "a.out-sparc-little";
311 return "a.out-sunos-big";
322 return "coff-sparc-lynx";
329 return "elf32-sparc-vxworks";
333 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
340 * Invocation line includes a switch not recognized by the base assembler.
341 * See if it's a processor-specific option. These are:
344 * Warn on architecture bumps. See also -A.
346 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
347 * Standard 32 bit architectures.
349 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
350 * This used to only mean 64 bits, but properly specifying it
351 * complicated gcc's ASM_SPECs, so now opcode selection is
352 * specified orthogonally to word size (except when specifying
353 * the default, but that is an internal implementation detail).
354 * -Av8plus, -Av8plusa, -Av8plusb
355 * Same as -Av9{,a,b}.
356 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
357 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
359 * -xarch=v9, -xarch=v9a, -xarch=v9b
360 * Same as -Av9{,a,b} -64, for compatibility with Sun's
363 * Select the architecture and possibly the file format.
364 * Instructions or features not supported by the selected
365 * architecture cause fatal errors.
367 * The default is to start at v6, and bump the architecture up
368 * whenever an instruction is seen at a higher level. In 32 bit
369 * environments, v9 is not bumped up to, the user must pass
372 * If -bump is specified, a warning is printing when bumping to
375 * If an architecture is specified, all instructions must match
376 * that architecture. Any higher level instructions are flagged
377 * as errors. Note that in the 32 bit environment specifying
378 * -Av8plus does not automatically create a v8plus object file, a
379 * v9 insn must be seen.
381 * If both an architecture and -bump are specified, the
382 * architecture starts at the specified level, but bumps are
383 * warnings. Note that we can't set `current_architecture' to
384 * the requested level in this case: in the 32 bit environment,
385 * we still must avoid creating v8plus object files unless v9
389 * Bumping between incompatible architectures is always an
390 * error. For example, from sparclite to v9.
394 const char *md_shortopts
= "A:K:VQ:sq";
397 const char *md_shortopts
= "A:k";
399 const char *md_shortopts
= "A:";
402 struct option md_longopts
[] = {
403 #define OPTION_BUMP (OPTION_MD_BASE)
404 {"bump", no_argument
, NULL
, OPTION_BUMP
},
405 #define OPTION_SPARC (OPTION_MD_BASE + 1)
406 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
407 #define OPTION_XARCH (OPTION_MD_BASE + 2)
408 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
410 #define OPTION_32 (OPTION_MD_BASE + 3)
411 {"32", no_argument
, NULL
, OPTION_32
},
412 #define OPTION_64 (OPTION_MD_BASE + 4)
413 {"64", no_argument
, NULL
, OPTION_64
},
414 #define OPTION_TSO (OPTION_MD_BASE + 5)
415 {"TSO", no_argument
, NULL
, OPTION_TSO
},
416 #define OPTION_PSO (OPTION_MD_BASE + 6)
417 {"PSO", no_argument
, NULL
, OPTION_PSO
},
418 #define OPTION_RMO (OPTION_MD_BASE + 7)
419 {"RMO", no_argument
, NULL
, OPTION_RMO
},
421 #ifdef SPARC_BIENDIAN
422 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
423 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
424 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
425 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
427 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
428 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
429 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
430 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
432 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
433 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
434 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
435 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
437 #define OPTION_RELAX (OPTION_MD_BASE + 14)
438 {"relax", no_argument
, NULL
, OPTION_RELAX
},
439 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
440 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
441 {NULL
, no_argument
, NULL
, 0}
444 size_t md_longopts_size
= sizeof (md_longopts
);
447 md_parse_option (int c
, char *arg
)
449 /* We don't get a chance to initialize anything before we're called,
450 so handle that now. */
451 if (! default_init_p
)
452 init_default_arch ();
458 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
463 if (strncmp (arg
, "v9", 2) != 0)
464 md_parse_option (OPTION_32
, NULL
);
466 md_parse_option (OPTION_64
, NULL
);
472 struct sparc_arch
*sa
;
473 enum sparc_opcode_arch_val opcode_arch
;
475 sa
= lookup_arch (arg
);
477 || ! sa
->user_option_p
)
479 if (c
== OPTION_XARCH
)
480 as_bad (_("invalid architecture -xarch=%s"), arg
);
482 as_bad (_("invalid architecture -A%s"), arg
);
486 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
487 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
488 as_fatal (_("Bad opcode table, broken assembler."));
490 max_architecture
= opcode_arch
;
491 architecture_requested
= 1;
496 /* Ignore -sparc, used by SunOS make default .s.o rule. */
499 case OPTION_ENFORCE_ALIGNED_DATA
:
500 enforce_aligned_data
= 1;
503 #ifdef SPARC_BIENDIAN
504 case OPTION_LITTLE_ENDIAN
:
505 target_big_endian
= 0;
506 if (default_arch_type
!= sparclet
)
507 as_fatal ("This target does not support -EL");
509 case OPTION_LITTLE_ENDIAN_DATA
:
510 target_little_endian_data
= 1;
511 target_big_endian
= 0;
512 if (default_arch_type
!= sparc86x
513 && default_arch_type
!= v9
)
514 as_fatal ("This target does not support --little-endian-data");
516 case OPTION_BIG_ENDIAN
:
517 target_big_endian
= 1;
531 const char **list
, **l
;
533 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
534 list
= bfd_target_list ();
535 for (l
= list
; *l
!= NULL
; l
++)
537 if (sparc_arch_size
== 32)
539 if (CONST_STRNEQ (*l
, "elf32-sparc"))
544 if (CONST_STRNEQ (*l
, "elf64-sparc"))
549 as_fatal (_("No compiled in support for %d bit object file format"),
553 if (sparc_arch_size
== 64
554 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
555 max_architecture
= SPARC_OPCODE_ARCH_V9
;
560 sparc_memory_model
= MM_TSO
;
564 sparc_memory_model
= MM_PSO
;
568 sparc_memory_model
= MM_RMO
;
576 /* Qy - do emit .comment
577 Qn - do not emit .comment. */
581 /* Use .stab instead of .stab.excl. */
585 /* quick -- Native assembler does fewer checks. */
589 if (strcmp (arg
, "PIC") != 0)
590 as_warn (_("Unrecognized option following -K"));
595 case OPTION_NO_UNDECLARED_REGS
:
596 no_undeclared_regs
= 1;
599 case OPTION_UNDECLARED_REGS
:
600 no_undeclared_regs
= 0;
608 case OPTION_NO_RELAX
:
620 md_show_usage (FILE *stream
)
622 const struct sparc_arch
*arch
;
625 /* We don't get a chance to initialize anything before we're called,
626 so handle that now. */
627 if (! default_init_p
)
628 init_default_arch ();
630 fprintf (stream
, _("SPARC options:\n"));
632 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
634 if (!arch
->user_option_p
)
636 if (arch
!= &sparc_arch_table
[0])
637 fprintf (stream
, " | ");
638 if (column
+ strlen (arch
->name
) > 70)
641 fputc ('\n', stream
);
643 column
+= 5 + 2 + strlen (arch
->name
);
644 fprintf (stream
, "-A%s", arch
->name
);
646 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
648 if (!arch
->user_option_p
)
650 fprintf (stream
, " | ");
651 if (column
+ strlen (arch
->name
) > 65)
654 fputc ('\n', stream
);
656 column
+= 5 + 7 + strlen (arch
->name
);
657 fprintf (stream
, "-xarch=%s", arch
->name
);
659 fprintf (stream
, _("\n\
660 specify variant of SPARC architecture\n\
661 -bump warn when assembler switches architectures\n\
663 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
664 -relax relax jumps and branches (default)\n\
665 -no-relax avoid changing any jumps and branches\n"));
667 fprintf (stream
, _("\
668 -k generate PIC\n"));
671 fprintf (stream
, _("\
672 -32 create 32 bit object file\n\
673 -64 create 64 bit object file\n"));
674 fprintf (stream
, _("\
675 [default is %d]\n"), default_arch_size
);
676 fprintf (stream
, _("\
677 -TSO use Total Store Ordering\n\
678 -PSO use Partial Store Ordering\n\
679 -RMO use Relaxed Memory Ordering\n"));
680 fprintf (stream
, _("\
681 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
682 fprintf (stream
, _("\
683 -KPIC generate PIC\n\
684 -V print assembler version number\n\
685 -undeclared-regs ignore application global register usage without\n\
686 appropriate .register directive (default)\n\
687 -no-undeclared-regs force error on application global register usage\n\
688 without appropriate .register directive\n\
693 #ifdef SPARC_BIENDIAN
694 fprintf (stream
, _("\
695 -EL generate code for a little endian machine\n\
696 -EB generate code for a big endian machine\n\
697 --little-endian-data generate code for a machine having big endian\n\
698 instructions and little endian data.\n"));
702 /* Native operand size opcode translation. */
708 } native_op_table
[] =
710 {"ldn", "ld", "ldx"},
711 {"ldna", "lda", "ldxa"},
712 {"stn", "st", "stx"},
713 {"stna", "sta", "stxa"},
714 {"slln", "sll", "sllx"},
715 {"srln", "srl", "srlx"},
716 {"sran", "sra", "srax"},
717 {"casn", "cas", "casx"},
718 {"casna", "casa", "casxa"},
719 {"clrn", "clr", "clrx"},
723 /* sparc64 privileged and hyperprivileged registers. */
725 struct priv_reg_entry
731 struct priv_reg_entry priv_reg_table
[] =
751 {"", -1}, /* End marker. */
754 struct priv_reg_entry hpriv_reg_table
[] =
762 {"", -1}, /* End marker. */
765 /* v9a specific asrs. This table is ordered by initial
766 letter, in reverse. */
768 struct priv_reg_entry v9a_asr_table
[] =
771 {"sys_tick_cmpr", 25},
775 {"softint_clear", 21},
784 {"clear_softint", 21},
785 {"", -1}, /* End marker. */
789 cmp_reg_entry (const void *parg
, const void *qarg
)
791 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
792 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
794 return strcmp (q
->name
, p
->name
);
797 /* This function is called once, at assembler startup time. It should
798 set up all the tables, etc. that the MD part of the assembler will
804 register const char *retval
= NULL
;
806 register unsigned int i
= 0;
808 /* We don't get a chance to initialize anything before md_parse_option
809 is called, and it may not be called, so handle default initialization
810 now if not already done. */
811 if (! default_init_p
)
812 init_default_arch ();
814 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
815 op_hash
= hash_new ();
817 while (i
< (unsigned int) sparc_num_opcodes
)
819 const char *name
= sparc_opcodes
[i
].name
;
820 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
823 as_bad (_("Internal error: can't hash `%s': %s\n"),
824 sparc_opcodes
[i
].name
, retval
);
829 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
831 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
832 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
837 while (i
< (unsigned int) sparc_num_opcodes
838 && !strcmp (sparc_opcodes
[i
].name
, name
));
841 for (i
= 0; native_op_table
[i
].name
; i
++)
843 const struct sparc_opcode
*insn
;
844 char *name
= ((sparc_arch_size
== 32)
845 ? native_op_table
[i
].name32
846 : native_op_table
[i
].name64
);
847 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
850 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
851 name
, native_op_table
[i
].name
);
856 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
860 as_bad (_("Internal error: can't hash `%s': %s\n"),
861 sparc_opcodes
[i
].name
, retval
);
868 as_fatal (_("Broken assembler. No assembly attempted."));
870 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
871 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
873 /* If -bump, record the architecture level at which we start issuing
874 warnings. The behaviour is different depending upon whether an
875 architecture was explicitly specified. If it wasn't, we issue warnings
876 for all upwards bumps. If it was, we don't start issuing warnings until
877 we need to bump beyond the requested architecture or when we bump between
878 conflicting architectures. */
881 && architecture_requested
)
883 /* `max_architecture' records the requested architecture.
884 Issue warnings if we go above it. */
885 warn_after_architecture
= max_architecture
;
887 /* Find the highest architecture level that doesn't conflict with
888 the requested one. */
889 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
890 max_architecture
> warn_after_architecture
;
892 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
893 warn_after_architecture
))
898 /* Called after all assembly has been done. */
903 unsigned long mach
= bfd_mach_sparc
;
905 if (sparc_arch_size
== 64)
906 switch (current_architecture
)
908 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
909 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
910 default: mach
= bfd_mach_sparc_v9
; break;
913 switch (current_architecture
)
915 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
916 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
917 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
918 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
919 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
920 be but for now it is (since that's the way it's always been
924 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
926 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
931 if (hwcap_seen
& F_MUL32
)
932 bits
|= ELF_SPARC_HWCAP_MUL32
;
933 if (hwcap_seen
& F_DIV32
)
934 bits
|= ELF_SPARC_HWCAP_DIV32
;
935 if (hwcap_seen
& F_FSMULD
)
936 bits
|= ELF_SPARC_HWCAP_FSMULD
;
937 if (hwcap_seen
& F_V8PLUS
)
938 bits
|= ELF_SPARC_HWCAP_V8PLUS
;
939 if (hwcap_seen
& F_POPC
)
940 bits
|= ELF_SPARC_HWCAP_POPC
;
941 if (hwcap_seen
& F_VIS
)
942 bits
|= ELF_SPARC_HWCAP_VIS
;
943 if (hwcap_seen
& F_VIS2
)
944 bits
|= ELF_SPARC_HWCAP_VIS2
;
945 if (hwcap_seen
& F_ASI_BLK_INIT
)
946 bits
|= ELF_SPARC_HWCAP_ASI_BLK_INIT
;
947 if (hwcap_seen
& F_FMAF
)
948 bits
|= ELF_SPARC_HWCAP_FMAF
;
949 if (hwcap_seen
& F_VIS3
)
950 bits
|= ELF_SPARC_HWCAP_VIS3
;
951 if (hwcap_seen
& F_HPC
)
952 bits
|= ELF_SPARC_HWCAP_HPC
;
953 if (hwcap_seen
& F_RANDOM
)
954 bits
|= ELF_SPARC_HWCAP_RANDOM
;
955 if (hwcap_seen
& F_TRANS
)
956 bits
|= ELF_SPARC_HWCAP_TRANS
;
957 if (hwcap_seen
& F_FJFMAU
)
958 bits
|= ELF_SPARC_HWCAP_FJFMAU
;
959 if (hwcap_seen
& F_IMA
)
960 bits
|= ELF_SPARC_HWCAP_IMA
;
961 if (hwcap_seen
& F_ASI_CACHE_SPARING
)
962 bits
|= ELF_SPARC_HWCAP_ASI_CACHE_SPARING
;
964 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, bits
);
969 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
972 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
976 /* Sign-extend the value from the architecture word size, so that
977 0xffffffff is always considered -1 on sparc32. */
978 if (sparc_arch_size
== 32)
980 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
981 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
990 /* Return non-zero if VAL is in the range 0 to MAX. */
993 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1000 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1001 (e.g. -15 to +31). */
1004 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1010 if (val
< ~(max
>> 1))
1016 sparc_ffs (unsigned int mask
)
1023 for (i
= 0; (mask
& 1) == 0; ++i
)
1028 /* Implement big shift right. */
1030 BSR (bfd_vma val
, int amount
)
1032 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1033 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1034 return val
>> amount
;
1037 /* For communication between sparc_ip and get_expression. */
1038 static char *expr_end
;
1040 /* Values for `special_case'.
1041 Instructions that require wierd handling because they're longer than
1043 #define SPECIAL_CASE_NONE 0
1044 #define SPECIAL_CASE_SET 1
1045 #define SPECIAL_CASE_SETSW 2
1046 #define SPECIAL_CASE_SETX 3
1047 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1048 #define SPECIAL_CASE_FDIV 4
1050 /* Bit masks of various insns. */
1051 #define NOP_INSN 0x01000000
1052 #define OR_INSN 0x80100000
1053 #define XOR_INSN 0x80180000
1054 #define FMOVS_INSN 0x81A00020
1055 #define SETHI_INSN 0x01000000
1056 #define SLLX_INSN 0x81281000
1057 #define SRA_INSN 0x81380000
1059 /* The last instruction to be assembled. */
1060 static const struct sparc_opcode
*last_insn
;
1061 /* The assembled opcode of `last_insn'. */
1062 static unsigned long last_opcode
;
1064 /* Handle the set and setuw synthetic instructions. */
1067 synthetize_setuw (const struct sparc_opcode
*insn
)
1069 int need_hi22_p
= 0;
1070 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1072 if (the_insn
.exp
.X_op
== O_constant
)
1074 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1076 if (sizeof (offsetT
) > 4
1077 && (the_insn
.exp
.X_add_number
< 0
1078 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1079 as_warn (_("set: number not in 0..4294967295 range"));
1083 if (sizeof (offsetT
) > 4
1084 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1085 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1086 as_warn (_("set: number not in -2147483648..4294967295 range"));
1087 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1091 /* See if operand is absolute and small; skip sethi if so. */
1092 if (the_insn
.exp
.X_op
!= O_constant
1093 || the_insn
.exp
.X_add_number
>= (1 << 12)
1094 || the_insn
.exp
.X_add_number
< -(1 << 12))
1096 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1097 | ((the_insn
.exp
.X_add_number
>> 10)
1098 & (the_insn
.exp
.X_op
== O_constant
1100 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1101 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1102 output_insn (insn
, &the_insn
);
1106 /* See if operand has no low-order bits; skip OR if so. */
1107 if (the_insn
.exp
.X_op
!= O_constant
1108 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1111 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1113 | (the_insn
.exp
.X_add_number
1114 & (the_insn
.exp
.X_op
!= O_constant
1115 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1116 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1117 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1118 output_insn (insn
, &the_insn
);
1122 /* Handle the setsw synthetic instruction. */
1125 synthetize_setsw (const struct sparc_opcode
*insn
)
1129 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1131 if (the_insn
.exp
.X_op
!= O_constant
)
1133 synthetize_setuw (insn
);
1135 /* Need to sign extend it. */
1136 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1137 the_insn
.reloc
= BFD_RELOC_NONE
;
1138 output_insn (insn
, &the_insn
);
1142 if (sizeof (offsetT
) > 4
1143 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1144 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1145 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1147 low32
= the_insn
.exp
.X_add_number
;
1151 synthetize_setuw (insn
);
1157 the_insn
.reloc
= BFD_RELOC_NONE
;
1158 /* See if operand is absolute and small; skip sethi if so. */
1159 if (low32
< -(1 << 12))
1161 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1162 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1163 output_insn (insn
, &the_insn
);
1164 low32
= 0x1c00 | (low32
& 0x3ff);
1165 opc
= RS1 (rd
) | XOR_INSN
;
1168 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1169 | (low32
& 0x1fff));
1170 output_insn (insn
, &the_insn
);
1173 /* Handle the setsw synthetic instruction. */
1176 synthetize_setx (const struct sparc_opcode
*insn
)
1178 int upper32
, lower32
;
1179 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1180 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1182 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1183 int need_xor10_p
= 0;
1185 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1186 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1187 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1190 upper_dstreg
= tmpreg
;
1191 /* The tmp reg should not be the dst reg. */
1192 if (tmpreg
== dstreg
)
1193 as_warn (_("setx: temporary register same as destination register"));
1195 /* ??? Obviously there are other optimizations we can do
1196 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1197 doing some of these. Later. If you do change things, try to
1198 change all of this to be table driven as well. */
1199 /* What to output depends on the number if it's constant.
1200 Compute that first, then output what we've decided upon. */
1201 if (the_insn
.exp
.X_op
!= O_constant
)
1203 if (sparc_arch_size
== 32)
1205 /* When arch size is 32, we want setx to be equivalent
1206 to setuw for anything but constants. */
1207 the_insn
.exp
.X_add_number
&= 0xffffffff;
1208 synthetize_setuw (insn
);
1211 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1217 /* Reset X_add_number, we've extracted it as upper32/lower32.
1218 Otherwise fixup_segment will complain about not being able to
1219 write an 8 byte number in a 4 byte field. */
1220 the_insn
.exp
.X_add_number
= 0;
1222 /* Only need hh22 if `or' insn can't handle constant. */
1223 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1226 /* Does bottom part (after sethi) have bits? */
1227 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1228 /* No hh22, but does upper32 still have bits we can't set
1230 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1233 /* If the lower half is all zero, we build the upper half directly
1234 into the dst reg. */
1236 /* Need lower half if number is zero or 0xffffffff00000000. */
1237 || (! need_hh22_p
&& ! need_hm10_p
))
1239 /* No need for sethi if `or' insn can handle constant. */
1240 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1241 /* Note that we can't use a negative constant in the `or'
1242 insn unless the upper 32 bits are all ones. */
1243 || (lower32
< 0 && upper32
!= -1)
1244 || (lower32
>= 0 && upper32
== -1))
1247 if (need_hi22_p
&& upper32
== -1)
1250 /* Does bottom part (after sethi) have bits? */
1251 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1253 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1254 /* Need `or' if we didn't set anything else. */
1255 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1259 /* Output directly to dst reg if lower 32 bits are all zero. */
1260 upper_dstreg
= dstreg
;
1263 if (!upper_dstreg
&& dstreg
)
1264 as_warn (_("setx: illegal temporary register g0"));
1268 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1269 | ((upper32
>> 10) & 0x3fffff));
1270 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1271 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1272 output_insn (insn
, &the_insn
);
1277 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1278 | (((need_xor10_p
? ~lower32
: lower32
)
1279 >> 10) & 0x3fffff));
1280 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1281 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1282 output_insn (insn
, &the_insn
);
1287 the_insn
.opcode
= (OR_INSN
1288 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1291 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1292 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1293 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1294 output_insn (insn
, &the_insn
);
1299 /* FIXME: One nice optimization to do here is to OR the low part
1300 with the highpart if hi22 isn't needed and the low part is
1302 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1305 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1306 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1307 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1308 output_insn (insn
, &the_insn
);
1311 /* If we needed to build the upper part, shift it into place. */
1312 if (need_hh22_p
|| need_hm10_p
)
1314 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1316 the_insn
.reloc
= BFD_RELOC_NONE
;
1317 output_insn (insn
, &the_insn
);
1320 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1323 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1324 | 0x1c00 | (lower32
& 0x3ff));
1325 the_insn
.reloc
= BFD_RELOC_NONE
;
1326 output_insn (insn
, &the_insn
);
1329 /* If we needed to build both upper and lower parts, OR them together. */
1330 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1332 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1334 the_insn
.reloc
= BFD_RELOC_NONE
;
1335 output_insn (insn
, &the_insn
);
1339 /* Main entry point to assemble one instruction. */
1342 md_assemble (char *str
)
1344 const struct sparc_opcode
*insn
;
1348 special_case
= sparc_ip (str
, &insn
);
1352 /* We warn about attempts to put a floating point branch in a delay slot,
1353 unless the delay slot has been annulled. */
1354 if (last_insn
!= NULL
1355 && (insn
->flags
& F_FBR
) != 0
1356 && (last_insn
->flags
& F_DELAYED
) != 0
1357 /* ??? This test isn't completely accurate. We assume anything with
1358 F_{UNBR,CONDBR,FBR} set is annullable. */
1359 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1360 || (last_opcode
& ANNUL
) == 0))
1361 as_warn (_("FP branch in delay slot"));
1363 /* SPARC before v9 requires a nop instruction between a floating
1364 point instruction and a floating point branch. We insert one
1365 automatically, with a warning. */
1366 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1367 && last_insn
!= NULL
1368 && (insn
->flags
& F_FBR
) != 0
1369 && (last_insn
->flags
& F_FLOAT
) != 0)
1371 struct sparc_it nop_insn
;
1373 nop_insn
.opcode
= NOP_INSN
;
1374 nop_insn
.reloc
= BFD_RELOC_NONE
;
1375 output_insn (insn
, &nop_insn
);
1376 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1379 switch (special_case
)
1381 case SPECIAL_CASE_NONE
:
1383 output_insn (insn
, &the_insn
);
1386 case SPECIAL_CASE_SETSW
:
1387 synthetize_setsw (insn
);
1390 case SPECIAL_CASE_SET
:
1391 synthetize_setuw (insn
);
1394 case SPECIAL_CASE_SETX
:
1395 synthetize_setx (insn
);
1398 case SPECIAL_CASE_FDIV
:
1400 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1402 output_insn (insn
, &the_insn
);
1404 /* According to information leaked from Sun, the "fdiv" instructions
1405 on early SPARC machines would produce incorrect results sometimes.
1406 The workaround is to add an fmovs of the destination register to
1407 itself just after the instruction. This was true on machines
1408 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1409 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1410 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1411 output_insn (insn
, &the_insn
);
1416 as_fatal (_("failed special case insn sanity check"));
1420 /* Subroutine of md_assemble to do the actual parsing. */
1423 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1425 char *error_message
= "";
1429 const struct sparc_opcode
*insn
;
1431 unsigned long opcode
;
1432 unsigned int mask
= 0;
1436 int special_case
= SPECIAL_CASE_NONE
;
1443 while (ISLOWER (*s
) || ISDIGIT (*s
));
1460 as_bad (_("Unknown opcode: `%s'"), str
);
1462 return special_case
;
1464 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1468 as_bad (_("Unknown opcode: `%s'"), str
);
1469 return special_case
;
1479 opcode
= insn
->match
;
1480 memset (&the_insn
, '\0', sizeof (the_insn
));
1481 the_insn
.reloc
= BFD_RELOC_NONE
;
1484 /* Build the opcode, checking as we go to make sure that the
1486 for (args
= insn
->args
;; ++args
)
1494 /* Parse a series of masks. */
1501 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1504 error_message
= _(": invalid membar mask name");
1510 if (*s
== '|' || *s
== '+')
1518 if (! parse_const_expr_arg (&s
, &kmask
))
1520 error_message
= _(": invalid membar mask expression");
1523 if (kmask
< 0 || kmask
> 127)
1525 error_message
= _(": invalid membar mask number");
1530 opcode
|= MEMBAR (kmask
);
1538 if (! parse_const_expr_arg (&s
, &smask
))
1540 error_message
= _(": invalid siam mode expression");
1543 if (smask
< 0 || smask
> 7)
1545 error_message
= _(": invalid siam mode number");
1556 /* Parse a prefetch function. */
1559 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1561 error_message
= _(": invalid prefetch function name");
1567 if (! parse_const_expr_arg (&s
, &fcn
))
1569 error_message
= _(": invalid prefetch function expression");
1572 if (fcn
< 0 || fcn
> 31)
1574 error_message
= _(": invalid prefetch function number");
1584 /* Parse a sparc64 privileged register. */
1587 struct priv_reg_entry
*p
= priv_reg_table
;
1588 unsigned int len
= 9999999; /* Init to make gcc happy. */
1591 while (p
->name
[0] > s
[0])
1593 while (p
->name
[0] == s
[0])
1595 len
= strlen (p
->name
);
1596 if (strncmp (p
->name
, s
, len
) == 0)
1600 if (p
->name
[0] != s
[0])
1602 error_message
= _(": unrecognizable privileged register");
1606 opcode
|= (p
->regnum
<< 14);
1608 opcode
|= (p
->regnum
<< 25);
1614 error_message
= _(": unrecognizable privileged register");
1620 /* Parse a sparc64 hyperprivileged register. */
1623 struct priv_reg_entry
*p
= hpriv_reg_table
;
1624 unsigned int len
= 9999999; /* Init to make gcc happy. */
1627 while (p
->name
[0] > s
[0])
1629 while (p
->name
[0] == s
[0])
1631 len
= strlen (p
->name
);
1632 if (strncmp (p
->name
, s
, len
) == 0)
1636 if (p
->name
[0] != s
[0])
1638 error_message
= _(": unrecognizable hyperprivileged register");
1642 opcode
|= (p
->regnum
<< 14);
1644 opcode
|= (p
->regnum
<< 25);
1650 error_message
= _(": unrecognizable hyperprivileged register");
1656 /* Parse a v9a/v9b ancillary state register. */
1659 struct priv_reg_entry
*p
= v9a_asr_table
;
1660 unsigned int len
= 9999999; /* Init to make gcc happy. */
1663 while (p
->name
[0] > s
[0])
1665 while (p
->name
[0] == s
[0])
1667 len
= strlen (p
->name
);
1668 if (strncmp (p
->name
, s
, len
) == 0)
1672 if (p
->name
[0] != s
[0])
1674 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1677 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1679 error_message
= _(": rd on write only ancillary state register");
1683 && (insn
->architecture
1684 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1686 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1687 error_message
= _(": unrecognizable v9a ancillary state register");
1691 opcode
|= (p
->regnum
<< 14);
1693 opcode
|= (p
->regnum
<< 25);
1699 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1705 if (strncmp (s
, "%asr", 4) == 0)
1713 while (ISDIGIT (*s
))
1715 num
= num
* 10 + *s
- '0';
1719 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1721 if (num
< 16 || 31 < num
)
1723 error_message
= _(": asr number must be between 16 and 31");
1729 if (num
< 0 || 31 < num
)
1731 error_message
= _(": asr number must be between 0 and 31");
1736 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1741 error_message
= _(": expecting %asrN");
1748 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1752 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1756 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1757 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1758 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1760 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1761 /* These fields are unsigned, but for upward compatibility,
1762 allow negative values as well. */
1766 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1767 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1768 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1770 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1771 /* These fields are unsigned, but for upward compatibility,
1772 allow negative values as well. */
1776 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1781 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1786 if (*s
== 'p' && s
[1] == 'n')
1794 if (*s
== 'p' && s
[1] == 't')
1806 if (strncmp (s
, "%icc", 4) == 0)
1818 if (strncmp (s
, "%xcc", 4) == 0)
1830 if (strncmp (s
, "%fcc0", 5) == 0)
1842 if (strncmp (s
, "%fcc1", 5) == 0)
1854 if (strncmp (s
, "%fcc2", 5) == 0)
1866 if (strncmp (s
, "%fcc3", 5) == 0)
1874 if (strncmp (s
, "%pc", 3) == 0)
1882 if (strncmp (s
, "%tick", 5) == 0)
1889 case '\0': /* End of args. */
1890 if (s
[0] == ',' && s
[1] == '%')
1892 static const struct ops
1894 /* The name as it appears in assembler. */
1896 /* strlen (name), precomputed for speed */
1898 /* The reloc this pseudo-op translates to. */
1900 /* 1 if tls call. */
1905 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
1906 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
1907 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
1908 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
1909 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
1910 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
1911 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
1912 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
1913 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
1916 const struct ops
*o
;
1920 for (o
= ops
; o
->name
; o
++)
1921 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
1923 if (o
->name
== NULL
)
1926 if (s
[o
->len
+ 2] != '(')
1928 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1929 return special_case
;
1932 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
1934 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1936 return special_case
;
1940 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
1941 || the_insn
.exp
.X_add_number
!= 0
1942 || the_insn
.exp
.X_add_symbol
1943 != symbol_find_or_make ("__tls_get_addr")))
1945 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1947 return special_case
;
1950 the_insn
.reloc
= o
->reloc
;
1951 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
1954 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
1957 else if (*s1
== ')')
1966 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1967 return special_case
;
1971 (void) get_expression (s
);
1991 case '[': /* These must match exactly. */
1999 case '#': /* Must be at least one digit. */
2002 while (ISDIGIT (*s
))
2010 case 'C': /* Coprocessor state register. */
2011 if (strncmp (s
, "%csr", 4) == 0)
2018 case 'b': /* Next operand is a coprocessor register. */
2021 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2026 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2040 opcode
|= mask
<< 14;
2048 opcode
|= mask
<< 25;
2054 case 'r': /* next operand must be a register */
2064 case 'f': /* frame pointer */
2072 case 'g': /* global register */
2081 case 'i': /* in register */
2085 mask
= c
- '0' + 24;
2090 case 'l': /* local register */
2094 mask
= (c
- '0' + 16);
2099 case 'o': /* out register */
2103 mask
= (c
- '0' + 8);
2108 case 's': /* stack pointer */
2116 case 'r': /* any register */
2117 if (!ISDIGIT ((c
= *s
++)))
2134 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2150 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2151 && no_undeclared_regs
&& ! globals
[mask
])
2152 as_bad (_("detected global register use not covered by .register pseudo-op"));
2154 /* Got the register, now figure out where
2155 it goes in the opcode. */
2159 opcode
|= mask
<< 14;
2167 opcode
|= mask
<< 25;
2171 opcode
|= (mask
<< 25) | (mask
<< 14);
2175 opcode
|= (mask
<< 25) | (mask
<< 0);
2181 case 'e': /* next operand is a floating point register */
2199 && ((format
= *s
) == 'f')
2202 for (mask
= 0; ISDIGIT (*s
); ++s
)
2204 mask
= 10 * mask
+ (*s
- '0');
2205 } /* read the number */
2214 } /* register must be even numbered */
2222 } /* register must be multiple of 4 */
2226 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2227 error_message
= _(": There are only 64 f registers; [0-63]");
2229 error_message
= _(": There are only 32 f registers; [0-31]");
2232 else if (mask
>= 32)
2234 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2236 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2239 = _(": There are only 32 single precision f registers; [0-31]");
2243 mask
-= 31; /* wrap high bit */
2247 error_message
= _(": There are only 32 f registers; [0-31]");
2255 } /* if not an 'f' register. */
2262 opcode
|= RS1 (mask
);
2268 opcode
|= RS2 (mask
);
2273 opcode
|= RS3 (mask
);
2279 opcode
|= RD (mask
);
2288 if (strncmp (s
, "%fsr", 4) == 0)
2296 if (strncmp (s
, "%efsr", 5) == 0)
2303 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2304 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2307 case 'l': /* 22 bit PC relative immediate */
2308 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2312 case 'L': /* 30 bit immediate */
2313 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2318 case 'n': /* 22 bit immediate */
2319 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2322 case 'i': /* 13 bit immediate */
2323 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2333 char *op_arg
= NULL
;
2334 static expressionS op_exp
;
2335 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2337 /* Check for %hi, etc. */
2340 static const struct ops
{
2341 /* The name as it appears in assembler. */
2343 /* strlen (name), precomputed for speed */
2345 /* The reloc this pseudo-op translates to. */
2347 /* Non-zero if for v9 only. */
2349 /* Non-zero if can be used in pc-relative contexts. */
2350 int pcrel_p
;/*FIXME:wip*/
2352 /* hix/lox must appear before hi/lo so %hix won't be
2353 mistaken for %hi. */
2354 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2355 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2356 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2357 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2358 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2359 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2360 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2361 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2362 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2363 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2364 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2365 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2366 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2367 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2368 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2369 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2370 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2371 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2372 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2374 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2376 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2377 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2378 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2379 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2380 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2382 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2384 { NULL
, 0, 0, 0, 0 }
2386 const struct ops
*o
;
2388 for (o
= ops
; o
->name
; o
++)
2389 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2391 if (o
->name
== NULL
)
2394 if (s
[o
->len
+ 1] != '(')
2396 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2397 return special_case
;
2401 the_insn
.reloc
= o
->reloc
;
2406 /* Note that if the get_expression() fails, we will still
2407 have created U entries in the symbol table for the
2408 'symbols' in the input string. Try not to create U
2409 symbols for registers, etc. */
2411 /* This stuff checks to see if the expression ends in
2412 +%reg. If it does, it removes the register from
2413 the expression, and re-sets 's' to point to the
2420 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2423 else if (*s1
== ')')
2432 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2433 return special_case
;
2437 (void) get_expression (s
);
2440 if (*s
== ',' || *s
== ']' || !*s
)
2442 if (*s
!= '+' && *s
!= '-')
2444 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2445 return special_case
;
2449 op_exp
= the_insn
.exp
;
2450 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2453 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2456 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2458 if (s1
[-2] == '%' && s1
[-3] == '+')
2460 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2462 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2469 if (op_arg
&& s1
== s
+ 1)
2470 the_insn
.exp
.X_op
= O_absent
;
2472 (void) get_expression (s
);
2484 (void) get_expression (s
);
2492 the_insn
.exp2
= the_insn
.exp
;
2493 the_insn
.exp
= op_exp
;
2494 if (the_insn
.exp2
.X_op
== O_absent
)
2495 the_insn
.exp2
.X_op
= O_illegal
;
2496 else if (the_insn
.exp
.X_op
== O_absent
)
2498 the_insn
.exp
= the_insn
.exp2
;
2499 the_insn
.exp2
.X_op
= O_illegal
;
2501 else if (the_insn
.exp
.X_op
== O_constant
)
2503 valueT val
= the_insn
.exp
.X_add_number
;
2504 switch (the_insn
.reloc
)
2509 case BFD_RELOC_SPARC_HH22
:
2510 val
= BSR (val
, 32);
2513 case BFD_RELOC_SPARC_LM22
:
2514 case BFD_RELOC_HI22
:
2515 val
= (val
>> 10) & 0x3fffff;
2518 case BFD_RELOC_SPARC_HM10
:
2519 val
= BSR (val
, 32);
2522 case BFD_RELOC_LO10
:
2526 case BFD_RELOC_SPARC_H44
:
2531 case BFD_RELOC_SPARC_M44
:
2536 case BFD_RELOC_SPARC_L44
:
2540 case BFD_RELOC_SPARC_HIX22
:
2542 val
= (val
>> 10) & 0x3fffff;
2545 case BFD_RELOC_SPARC_LOX10
:
2546 val
= (val
& 0x3ff) | 0x1c00;
2549 the_insn
.exp
= the_insn
.exp2
;
2550 the_insn
.exp
.X_add_number
+= val
;
2551 the_insn
.exp2
.X_op
= O_illegal
;
2552 the_insn
.reloc
= old_reloc
;
2554 else if (the_insn
.exp2
.X_op
!= O_constant
)
2556 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2557 return special_case
;
2561 if (old_reloc
!= BFD_RELOC_SPARC13
2562 || the_insn
.reloc
!= BFD_RELOC_LO10
2563 || sparc_arch_size
!= 64
2566 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2567 return special_case
;
2569 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2573 /* Check for constants that don't require emitting a reloc. */
2574 if (the_insn
.exp
.X_op
== O_constant
2575 && the_insn
.exp
.X_add_symbol
== 0
2576 && the_insn
.exp
.X_op_symbol
== 0)
2578 /* For pc-relative call instructions, we reject
2579 constants to get better code. */
2581 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2582 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2584 error_message
= _(": PC-relative operand can't be a constant");
2588 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2589 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2591 error_message
= _(": TLS operand can't be a constant");
2595 /* Constants that won't fit are checked in md_apply_fix
2596 and bfd_install_relocation.
2597 ??? It would be preferable to install the constants
2598 into the insn here and save having to create a fixS
2599 for each one. There already exists code to handle
2600 all the various cases (e.g. in md_apply_fix and
2601 bfd_install_relocation) so duplicating all that code
2602 here isn't right. */
2622 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2624 error_message
= _(": invalid ASI name");
2630 if (! parse_const_expr_arg (&s
, &asi
))
2632 error_message
= _(": invalid ASI expression");
2635 if (asi
< 0 || asi
> 255)
2637 error_message
= _(": invalid ASI number");
2641 opcode
|= ASI (asi
);
2643 } /* Alternate space. */
2646 if (strncmp (s
, "%psr", 4) == 0)
2653 case 'q': /* Floating point queue. */
2654 if (strncmp (s
, "%fq", 3) == 0)
2661 case 'Q': /* Coprocessor queue. */
2662 if (strncmp (s
, "%cq", 3) == 0)
2670 if (strcmp (str
, "set") == 0
2671 || strcmp (str
, "setuw") == 0)
2673 special_case
= SPECIAL_CASE_SET
;
2676 else if (strcmp (str
, "setsw") == 0)
2678 special_case
= SPECIAL_CASE_SETSW
;
2681 else if (strcmp (str
, "setx") == 0)
2683 special_case
= SPECIAL_CASE_SETX
;
2686 else if (strncmp (str
, "fdiv", 4) == 0)
2688 special_case
= SPECIAL_CASE_FDIV
;
2694 if (strncmp (s
, "%asi", 4) != 0)
2700 if (strncmp (s
, "%fprs", 5) != 0)
2706 if (strncmp (s
, "%ccr", 4) != 0)
2712 if (strncmp (s
, "%tbr", 4) != 0)
2718 if (strncmp (s
, "%wim", 4) != 0)
2725 char *push
= input_line_pointer
;
2728 input_line_pointer
= s
;
2730 if (e
.X_op
== O_constant
)
2732 int n
= e
.X_add_number
;
2733 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2734 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2736 opcode
|= e
.X_add_number
<< 5;
2739 as_bad (_("non-immediate OPF operand, ignored"));
2740 s
= input_line_pointer
;
2741 input_line_pointer
= push
;
2746 if (strncmp (s
, "%y", 2) != 0)
2754 /* Parse a sparclet cpreg. */
2756 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2758 error_message
= _(": invalid cpreg name");
2761 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2766 as_fatal (_("failed sanity check."));
2767 } /* switch on arg code. */
2769 /* Break out of for() loop. */
2771 } /* For each arg that we expect. */
2776 /* Args don't match. */
2777 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2778 && (insn
->name
== insn
[1].name
2779 || !strcmp (insn
->name
, insn
[1].name
)))
2787 as_bad (_("Illegal operands%s"), error_message
);
2788 return special_case
;
2793 /* We have a match. Now see if the architecture is OK. */
2794 int needed_arch_mask
= insn
->architecture
;
2795 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2796 int hwcaps
= insn
->flags
& F_HWCAP_MASK
;
2799 hwcap_seen
|= hwcaps
;
2804 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2805 if (! needed_arch_mask
)
2807 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2810 if (needed_arch_mask
2811 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2814 /* Can we bump up the architecture? */
2815 else if (needed_arch_mask
2816 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2818 enum sparc_opcode_arch_val needed_architecture
=
2819 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2820 & needed_arch_mask
);
2822 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2824 && needed_architecture
> warn_after_architecture
)
2826 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2827 sparc_opcode_archs
[current_architecture
].name
,
2828 sparc_opcode_archs
[needed_architecture
].name
,
2830 warn_after_architecture
= needed_architecture
;
2832 current_architecture
= needed_architecture
;
2835 /* ??? This seems to be a bit fragile. What if the next entry in
2836 the opcode table is the one we want and it is supported?
2837 It is possible to arrange the table today so that this can't
2838 happen but what about tomorrow? */
2841 int arch
, printed_one_p
= 0;
2843 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2845 /* Create a list of the architectures that support the insn. */
2846 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2848 arch
= sparc_ffs (needed_arch_mask
);
2849 while ((1 << arch
) <= needed_arch_mask
)
2851 if ((1 << arch
) & needed_arch_mask
)
2855 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2862 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2863 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2865 sparc_opcode_archs
[max_architecture
].name
);
2866 return special_case
;
2868 } /* If no match. */
2871 } /* Forever looking for a match. */
2873 the_insn
.opcode
= opcode
;
2874 return special_case
;
2877 /* Parse an argument that can be expressed as a keyword.
2878 (eg: #StoreStore or %ccfr).
2879 The result is a boolean indicating success.
2880 If successful, INPUT_POINTER is updated. */
2883 parse_keyword_arg (int (*lookup_fn
) (const char *),
2884 char **input_pointerP
,
2890 p
= *input_pointerP
;
2891 for (q
= p
+ (*p
== '#' || *p
== '%');
2892 ISALNUM (*q
) || *q
== '_';
2897 value
= (*lookup_fn
) (p
);
2902 *input_pointerP
= q
;
2906 /* Parse an argument that is a constant expression.
2907 The result is a boolean indicating success. */
2910 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
2912 char *save
= input_line_pointer
;
2915 input_line_pointer
= *input_pointerP
;
2916 /* The next expression may be something other than a constant
2917 (say if we're not processing the right variant of the insn).
2918 Don't call expression unless we're sure it will succeed as it will
2919 signal an error (which we want to defer until later). */
2920 /* FIXME: It might be better to define md_operand and have it recognize
2921 things like %asi, etc. but continuing that route through to the end
2922 is a lot of work. */
2923 if (*input_line_pointer
== '%')
2925 input_line_pointer
= save
;
2929 *input_pointerP
= input_line_pointer
;
2930 input_line_pointer
= save
;
2931 if (exp
.X_op
!= O_constant
)
2933 *valueP
= exp
.X_add_number
;
2937 /* Subroutine of sparc_ip to parse an expression. */
2940 get_expression (char *str
)
2945 save_in
= input_line_pointer
;
2946 input_line_pointer
= str
;
2947 seg
= expression (&the_insn
.exp
);
2948 if (seg
!= absolute_section
2949 && seg
!= text_section
2950 && seg
!= data_section
2951 && seg
!= bss_section
2952 && seg
!= undefined_section
)
2954 the_insn
.error
= _("bad segment");
2955 expr_end
= input_line_pointer
;
2956 input_line_pointer
= save_in
;
2959 expr_end
= input_line_pointer
;
2960 input_line_pointer
= save_in
;
2964 /* Subroutine of md_assemble to output one insn. */
2967 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
2969 char *toP
= frag_more (4);
2971 /* Put out the opcode. */
2972 if (INSN_BIG_ENDIAN
)
2973 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
2975 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
2977 /* Put out the symbol-dependent stuff. */
2978 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
2980 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2981 (toP
- frag_now
->fr_literal
), /* Where. */
2986 /* Turn off overflow checking in fixup_segment. We'll do our
2987 own overflow checking in md_apply_fix. This is necessary because
2988 the insn size is 4 and fixup_segment will signal an overflow for
2989 large 8 byte quantities. */
2990 fixP
->fx_no_overflow
= 1;
2991 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2992 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
2996 last_opcode
= theinsn
->opcode
;
2999 dwarf2_emit_insn (4);
3004 md_atof (int type
, char *litP
, int *sizeP
)
3006 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3009 /* Write a value out to the object file, using the appropriate
3013 md_number_to_chars (char *buf
, valueT val
, int n
)
3015 if (target_big_endian
)
3016 number_to_chars_bigendian (buf
, val
, n
);
3017 else if (target_little_endian_data
3018 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3019 /* Output debug words, which are not in allocated sections, as big
3021 number_to_chars_bigendian (buf
, val
, n
);
3022 else if (target_little_endian_data
|| ! target_big_endian
)
3023 number_to_chars_littleendian (buf
, val
, n
);
3026 /* Apply a fixS to the frags, now that we know the value it ought to
3030 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3032 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3033 offsetT val
= * (offsetT
*) valP
;
3036 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3038 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3041 /* SPARC ELF relocations don't use an addend in the data field. */
3042 if (fixP
->fx_addsy
!= NULL
)
3044 switch (fixP
->fx_r_type
)
3046 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3047 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3048 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3049 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3050 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3051 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3052 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3053 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3054 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3055 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3056 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3057 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3058 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3059 case BFD_RELOC_SPARC_TLS_IE_LD
:
3060 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3061 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3062 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3063 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3064 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3065 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3066 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3067 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3068 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3069 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3070 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3080 /* This is a hack. There should be a better way to
3081 handle this. Probably in terms of howto fields, once
3082 we can look at these fixups in terms of howtos. */
3083 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3084 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3087 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3088 generate a reloc, then we just want to let the reloc addend set
3089 the value. We do not want to also stuff the addend into the
3090 object file. Including the addend in the object file works when
3091 doing a static link, because the linker will ignore the object
3092 file contents. However, the dynamic linker does not ignore the
3093 object file contents. */
3094 if (fixP
->fx_addsy
!= NULL
3095 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3098 /* When generating PIC code, we do not want an addend for a reloc
3099 against a local symbol. We adjust fx_addnumber to cancel out the
3100 value already included in val, and to also cancel out the
3101 adjustment which bfd_install_relocation will create. */
3103 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3104 && fixP
->fx_addsy
!= NULL
3105 && ! S_IS_COMMON (fixP
->fx_addsy
)
3106 && symbol_section_p (fixP
->fx_addsy
))
3107 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3109 /* When generating PIC code, we need to fiddle to get
3110 bfd_install_relocation to do the right thing for a PC relative
3111 reloc against a local symbol which we are going to keep. */
3113 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3114 && fixP
->fx_addsy
!= NULL
3115 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3116 || S_IS_WEAK (fixP
->fx_addsy
))
3117 && S_IS_DEFINED (fixP
->fx_addsy
)
3118 && ! S_IS_COMMON (fixP
->fx_addsy
))
3121 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3125 /* If this is a data relocation, just output VAL. */
3127 if (fixP
->fx_r_type
== BFD_RELOC_16
3128 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3130 md_number_to_chars (buf
, val
, 2);
3132 else if (fixP
->fx_r_type
== BFD_RELOC_32
3133 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3134 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3136 md_number_to_chars (buf
, val
, 4);
3138 else if (fixP
->fx_r_type
== BFD_RELOC_64
3139 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3141 md_number_to_chars (buf
, val
, 8);
3143 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3144 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3151 /* It's a relocation against an instruction. */
3153 if (INSN_BIG_ENDIAN
)
3154 insn
= bfd_getb32 ((unsigned char *) buf
);
3156 insn
= bfd_getl32 ((unsigned char *) buf
);
3158 switch (fixP
->fx_r_type
)
3160 case BFD_RELOC_32_PCREL_S2
:
3162 /* FIXME: This increment-by-one deserves a comment of why it's
3164 if (! sparc_pic_code
3165 || fixP
->fx_addsy
== NULL
3166 || symbol_section_p (fixP
->fx_addsy
))
3169 insn
|= val
& 0x3fffffff;
3171 /* See if we have a delay slot. */
3172 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3176 #define XCC (2 << 20)
3177 #define COND(x) (((x)&0xf)<<25)
3178 #define CONDA COND(0x8)
3179 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3180 #define INSN_BA (F2(0,2) | CONDA)
3181 #define INSN_OR F3(2, 0x2, 0)
3182 #define INSN_NOP F2(0,4)
3186 /* If the instruction is a call with either:
3188 arithmetic instruction with rd == %o7
3189 where rs1 != %o7 and rs2 if it is register != %o7
3190 then we can optimize if the call destination is near
3191 by changing the call into a branch always. */
3192 if (INSN_BIG_ENDIAN
)
3193 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3195 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3196 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3198 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3199 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3200 || ((delay
& RD (~0)) != RD (O7
))))
3202 if ((delay
& RS1 (~0)) == RS1 (O7
)
3203 || ((delay
& F3I (~0)) == 0
3204 && (delay
& RS2 (~0)) == RS2 (O7
)))
3206 /* Ensure the branch will fit into simm22. */
3207 if ((val
& 0x3fe00000)
3208 && (val
& 0x3fe00000) != 0x3fe00000)
3210 /* Check if the arch is v9 and branch will fit
3212 if (((val
& 0x3c0000) == 0
3213 || (val
& 0x3c0000) == 0x3c0000)
3214 && (sparc_arch_size
== 64
3215 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3217 insn
= INSN_BPA
| (val
& 0x7ffff);
3220 insn
= INSN_BA
| (val
& 0x3fffff);
3221 if (fixP
->fx_where
>= 4
3222 && ((delay
& (0xffffffff ^ RS1 (~0)))
3223 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3228 if (INSN_BIG_ENDIAN
)
3229 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3231 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3232 if ((setter
& (0xffffffff ^ RD (~0)))
3233 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3240 If call foo was replaced with ba, replace
3241 or %rN, %g0, %o7 with nop. */
3242 reg
= (delay
& RS1 (~0)) >> 14;
3243 if (reg
!= ((setter
& RD (~0)) >> 25)
3244 || reg
== G0
|| reg
== O7
)
3247 if (INSN_BIG_ENDIAN
)
3248 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3250 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3255 case BFD_RELOC_SPARC_11
:
3256 if (! in_signed_range (val
, 0x7ff))
3257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3258 _("relocation overflow"));
3259 insn
|= val
& 0x7ff;
3262 case BFD_RELOC_SPARC_10
:
3263 if (! in_signed_range (val
, 0x3ff))
3264 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3265 _("relocation overflow"));
3266 insn
|= val
& 0x3ff;
3269 case BFD_RELOC_SPARC_7
:
3270 if (! in_bitfield_range (val
, 0x7f))
3271 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3272 _("relocation overflow"));
3276 case BFD_RELOC_SPARC_6
:
3277 if (! in_bitfield_range (val
, 0x3f))
3278 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3279 _("relocation overflow"));
3283 case BFD_RELOC_SPARC_5
:
3284 if (! in_bitfield_range (val
, 0x1f))
3285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3286 _("relocation overflow"));
3290 case BFD_RELOC_SPARC_WDISP16
:
3293 || val
<= -(offsetT
) 0x20008)
3294 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3295 _("relocation overflow"));
3296 /* FIXME: The +1 deserves a comment. */
3297 val
= (val
>> 2) + 1;
3298 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3301 case BFD_RELOC_SPARC_WDISP19
:
3304 || val
<= -(offsetT
) 0x100008)
3305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3306 _("relocation overflow"));
3307 /* FIXME: The +1 deserves a comment. */
3308 val
= (val
>> 2) + 1;
3309 insn
|= val
& 0x7ffff;
3312 case BFD_RELOC_SPARC_HH22
:
3313 val
= BSR (val
, 32);
3316 case BFD_RELOC_SPARC_LM22
:
3317 case BFD_RELOC_HI22
:
3318 if (!fixP
->fx_addsy
)
3319 insn
|= (val
>> 10) & 0x3fffff;
3321 /* FIXME: Need comment explaining why we do this. */
3325 case BFD_RELOC_SPARC22
:
3326 if (val
& ~0x003fffff)
3327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3328 _("relocation overflow"));
3329 insn
|= (val
& 0x3fffff);
3332 case BFD_RELOC_SPARC_HM10
:
3333 val
= BSR (val
, 32);
3336 case BFD_RELOC_LO10
:
3337 if (!fixP
->fx_addsy
)
3338 insn
|= val
& 0x3ff;
3340 /* FIXME: Need comment explaining why we do this. */
3344 case BFD_RELOC_SPARC_OLO10
:
3346 val
+= fixP
->tc_fix_data
;
3349 case BFD_RELOC_SPARC13
:
3350 if (! in_signed_range (val
, 0x1fff))
3351 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3352 _("relocation overflow"));
3353 insn
|= val
& 0x1fff;
3356 case BFD_RELOC_SPARC_WDISP22
:
3357 val
= (val
>> 2) + 1;
3359 case BFD_RELOC_SPARC_BASE22
:
3360 insn
|= val
& 0x3fffff;
3363 case BFD_RELOC_SPARC_H44
:
3364 if (!fixP
->fx_addsy
)
3368 insn
|= tval
& 0x3fffff;
3372 case BFD_RELOC_SPARC_M44
:
3373 if (!fixP
->fx_addsy
)
3374 insn
|= (val
>> 12) & 0x3ff;
3377 case BFD_RELOC_SPARC_L44
:
3378 if (!fixP
->fx_addsy
)
3379 insn
|= val
& 0xfff;
3382 case BFD_RELOC_SPARC_HIX22
:
3383 if (!fixP
->fx_addsy
)
3385 val
^= ~(offsetT
) 0;
3386 insn
|= (val
>> 10) & 0x3fffff;
3390 case BFD_RELOC_SPARC_LOX10
:
3391 if (!fixP
->fx_addsy
)
3392 insn
|= 0x1c00 | (val
& 0x3ff);
3395 case BFD_RELOC_NONE
:
3397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3398 _("bad or unhandled relocation type: 0x%02x"),
3403 if (INSN_BIG_ENDIAN
)
3404 bfd_putb32 (insn
, (unsigned char *) buf
);
3406 bfd_putl32 (insn
, (unsigned char *) buf
);
3409 /* Are we finished with this relocation now? */
3410 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3414 /* Translate internal representation of relocation info to BFD target
3418 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3420 static arelent
*relocs
[3];
3422 bfd_reloc_code_real_type code
;
3424 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3427 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3428 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3429 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3431 switch (fixp
->fx_r_type
)
3435 case BFD_RELOC_HI22
:
3436 case BFD_RELOC_LO10
:
3437 case BFD_RELOC_32_PCREL_S2
:
3438 case BFD_RELOC_SPARC13
:
3439 case BFD_RELOC_SPARC22
:
3440 case BFD_RELOC_SPARC_PC22
:
3441 case BFD_RELOC_SPARC_PC10
:
3442 case BFD_RELOC_SPARC_BASE13
:
3443 case BFD_RELOC_SPARC_WDISP16
:
3444 case BFD_RELOC_SPARC_WDISP19
:
3445 case BFD_RELOC_SPARC_WDISP22
:
3447 case BFD_RELOC_SPARC_5
:
3448 case BFD_RELOC_SPARC_6
:
3449 case BFD_RELOC_SPARC_7
:
3450 case BFD_RELOC_SPARC_10
:
3451 case BFD_RELOC_SPARC_11
:
3452 case BFD_RELOC_SPARC_HH22
:
3453 case BFD_RELOC_SPARC_HM10
:
3454 case BFD_RELOC_SPARC_LM22
:
3455 case BFD_RELOC_SPARC_PC_HH22
:
3456 case BFD_RELOC_SPARC_PC_HM10
:
3457 case BFD_RELOC_SPARC_PC_LM22
:
3458 case BFD_RELOC_SPARC_H44
:
3459 case BFD_RELOC_SPARC_M44
:
3460 case BFD_RELOC_SPARC_L44
:
3461 case BFD_RELOC_SPARC_HIX22
:
3462 case BFD_RELOC_SPARC_LOX10
:
3463 case BFD_RELOC_SPARC_REV32
:
3464 case BFD_RELOC_SPARC_OLO10
:
3465 case BFD_RELOC_SPARC_UA16
:
3466 case BFD_RELOC_SPARC_UA32
:
3467 case BFD_RELOC_SPARC_UA64
:
3468 case BFD_RELOC_8_PCREL
:
3469 case BFD_RELOC_16_PCREL
:
3470 case BFD_RELOC_32_PCREL
:
3471 case BFD_RELOC_64_PCREL
:
3472 case BFD_RELOC_SPARC_PLT32
:
3473 case BFD_RELOC_SPARC_PLT64
:
3474 case BFD_RELOC_VTABLE_ENTRY
:
3475 case BFD_RELOC_VTABLE_INHERIT
:
3476 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3477 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3478 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3479 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3480 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3481 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3482 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3483 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3484 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3485 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3486 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3487 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3488 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3489 case BFD_RELOC_SPARC_TLS_IE_LD
:
3490 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3491 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3492 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3493 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3494 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3495 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3496 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3497 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3498 case BFD_RELOC_SPARC_GOTDATA_OP
:
3499 code
= fixp
->fx_r_type
;
3506 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3507 /* If we are generating PIC code, we need to generate a different
3511 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3513 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3516 #define GOTT_BASE "__GOTT_BASE__"
3517 #define GOTT_INDEX "__GOTT_INDEX__"
3520 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3526 case BFD_RELOC_32_PCREL_S2
:
3527 if (generic_force_reloc (fixp
))
3528 code
= BFD_RELOC_SPARC_WPLT30
;
3530 case BFD_RELOC_HI22
:
3531 code
= BFD_RELOC_SPARC_GOT22
;
3532 if (fixp
->fx_addsy
!= NULL
)
3534 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3535 code
= BFD_RELOC_SPARC_PC22
;
3537 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3538 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3539 code
= BFD_RELOC_HI22
; /* Unchanged. */
3543 case BFD_RELOC_LO10
:
3544 code
= BFD_RELOC_SPARC_GOT10
;
3545 if (fixp
->fx_addsy
!= NULL
)
3547 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3548 code
= BFD_RELOC_SPARC_PC10
;
3550 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3551 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3552 code
= BFD_RELOC_LO10
; /* Unchanged. */
3556 case BFD_RELOC_SPARC13
:
3557 code
= BFD_RELOC_SPARC_GOT13
;
3563 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3565 /* Nothing is aligned in DWARF debugging sections. */
3566 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3569 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3570 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3571 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3575 if (code
== BFD_RELOC_SPARC_OLO10
)
3576 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3578 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3579 if (reloc
->howto
== 0)
3581 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3582 _("internal error: can't export reloc type %d (`%s')"),
3583 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3589 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3592 if (reloc
->howto
->pc_relative
== 0
3593 || code
== BFD_RELOC_SPARC_PC10
3594 || code
== BFD_RELOC_SPARC_PC22
)
3595 reloc
->addend
= fixp
->fx_addnumber
;
3596 else if (sparc_pic_code
3597 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3598 && fixp
->fx_addsy
!= NULL
3599 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3600 || S_IS_WEAK (fixp
->fx_addsy
))
3601 && S_IS_DEFINED (fixp
->fx_addsy
)
3602 && ! S_IS_COMMON (fixp
->fx_addsy
))
3603 reloc
->addend
= fixp
->fx_addnumber
;
3605 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3607 #else /* elf or coff */
3609 if (code
!= BFD_RELOC_32_PCREL_S2
3610 && code
!= BFD_RELOC_SPARC_WDISP22
3611 && code
!= BFD_RELOC_SPARC_WDISP16
3612 && code
!= BFD_RELOC_SPARC_WDISP19
3613 && code
!= BFD_RELOC_SPARC_WPLT30
3614 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3615 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3616 reloc
->addend
= fixp
->fx_addnumber
;
3617 else if (symbol_section_p (fixp
->fx_addsy
))
3618 reloc
->addend
= (section
->vma
3619 + fixp
->fx_addnumber
3620 + md_pcrel_from (fixp
));
3622 reloc
->addend
= fixp
->fx_offset
;
3625 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3626 on the same location. */
3627 if (code
== BFD_RELOC_SPARC_OLO10
)
3629 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3632 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3634 = symbol_get_bfdsym (section_symbol (absolute_section
));
3635 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3636 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3637 reloc
->addend
= fixp
->tc_fix_data
;
3643 /* We have no need to default values of symbols. */
3646 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
3651 /* Round up a section size to the appropriate boundary. */
3654 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
3657 /* This is not right for ELF; a.out wants it, and COFF will force
3658 the alignment anyways. */
3659 valueT align
= ((valueT
) 1
3660 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3663 /* Turn alignment value into a mask. */
3665 newsize
= (size
+ align
) & ~align
;
3672 /* Exactly what point is a PC-relative offset relative TO?
3673 On the sparc, they're relative to the address of the offset, plus
3674 its size. This gets us to the following instruction.
3675 (??? Is this right? FIXME-SOON) */
3677 md_pcrel_from (fixS
*fixP
)
3681 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3682 if (! sparc_pic_code
3683 || fixP
->fx_addsy
== NULL
3684 || symbol_section_p (fixP
->fx_addsy
))
3685 ret
+= fixP
->fx_size
;
3689 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3700 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3703 return (value
== 1) ? shift
: -1;
3706 /* Sort of like s_lcomm. */
3709 static int max_alignment
= 15;
3713 s_reserve (int ignore ATTRIBUTE_UNUSED
)
3723 name
= input_line_pointer
;
3724 c
= get_symbol_end ();
3725 p
= input_line_pointer
;
3729 if (*input_line_pointer
!= ',')
3731 as_bad (_("Expected comma after name"));
3732 ignore_rest_of_line ();
3736 ++input_line_pointer
;
3738 if ((size
= get_absolute_expression ()) < 0)
3740 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3741 ignore_rest_of_line ();
3746 symbolP
= symbol_find_or_make (name
);
3749 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3750 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3752 as_bad (_("bad .reserve segment -- expected BSS segment"));
3756 if (input_line_pointer
[2] == '.')
3757 input_line_pointer
+= 7;
3759 input_line_pointer
+= 6;
3762 if (*input_line_pointer
== ',')
3764 ++input_line_pointer
;
3767 if (*input_line_pointer
== '\n')
3769 as_bad (_("missing alignment"));
3770 ignore_rest_of_line ();
3774 align
= (int) get_absolute_expression ();
3777 if (align
> max_alignment
)
3779 align
= max_alignment
;
3780 as_warn (_("alignment too large; assuming %d"), align
);
3786 as_bad (_("negative alignment"));
3787 ignore_rest_of_line ();
3793 temp
= mylog2 (align
);
3796 as_bad (_("alignment not a power of 2"));
3797 ignore_rest_of_line ();
3804 record_alignment (bss_section
, align
);
3809 if (!S_IS_DEFINED (symbolP
)
3811 && S_GET_OTHER (symbolP
) == 0
3812 && S_GET_DESC (symbolP
) == 0
3819 segT current_seg
= now_seg
;
3820 subsegT current_subseg
= now_subseg
;
3822 /* Switch to bss. */
3823 subseg_set (bss_section
, 1);
3827 frag_align (align
, 0, 0);
3829 /* Detach from old frag. */
3830 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3831 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3833 symbol_set_frag (symbolP
, frag_now
);
3834 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3835 (offsetT
) size
, (char *) 0);
3838 S_SET_SEGMENT (symbolP
, bss_section
);
3840 subseg_set (current_seg
, current_subseg
);
3843 S_SET_SIZE (symbolP
, size
);
3849 as_warn (_("Ignoring attempt to re-define symbol %s"),
3850 S_GET_NAME (symbolP
));
3853 demand_empty_rest_of_line ();
3857 s_common (int ignore ATTRIBUTE_UNUSED
)
3865 name
= input_line_pointer
;
3866 c
= get_symbol_end ();
3867 /* Just after name is now '\0'. */
3868 p
= input_line_pointer
;
3871 if (*input_line_pointer
!= ',')
3873 as_bad (_("Expected comma after symbol-name"));
3874 ignore_rest_of_line ();
3879 input_line_pointer
++;
3881 if ((temp
= get_absolute_expression ()) < 0)
3883 as_bad (_(".COMMon length (%lu) out of range ignored"),
3884 (unsigned long) temp
);
3885 ignore_rest_of_line ();
3890 symbolP
= symbol_find_or_make (name
);
3892 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3894 as_bad (_("Ignoring attempt to re-define symbol"));
3895 ignore_rest_of_line ();
3898 if (S_GET_VALUE (symbolP
) != 0)
3900 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3902 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3903 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
3909 S_SET_VALUE (symbolP
, (valueT
) size
);
3910 S_SET_EXTERNAL (symbolP
);
3913 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3914 if (*input_line_pointer
!= ',')
3916 as_bad (_("Expected comma after common length"));
3917 ignore_rest_of_line ();
3920 input_line_pointer
++;
3922 if (*input_line_pointer
!= '"')
3924 temp
= get_absolute_expression ();
3927 if (temp
> max_alignment
)
3929 temp
= max_alignment
;
3930 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
3936 as_bad (_("negative alignment"));
3937 ignore_rest_of_line ();
3942 if (symbol_get_obj (symbolP
)->local
)
3949 old_subsec
= now_subseg
;
3954 align
= mylog2 (temp
);
3958 as_bad (_("alignment not a power of 2"));
3959 ignore_rest_of_line ();
3963 record_alignment (bss_section
, align
);
3964 subseg_set (bss_section
, 0);
3966 frag_align (align
, 0, 0);
3967 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3968 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3969 symbol_set_frag (symbolP
, frag_now
);
3970 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3971 (offsetT
) size
, (char *) 0);
3973 S_SET_SEGMENT (symbolP
, bss_section
);
3974 S_CLEAR_EXTERNAL (symbolP
);
3975 S_SET_SIZE (symbolP
, size
);
3976 subseg_set (old_sec
, old_subsec
);
3979 #endif /* OBJ_ELF */
3982 S_SET_VALUE (symbolP
, (valueT
) size
);
3984 S_SET_ALIGN (symbolP
, temp
);
3985 S_SET_SIZE (symbolP
, size
);
3987 S_SET_EXTERNAL (symbolP
);
3988 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3993 input_line_pointer
++;
3994 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3995 if (*input_line_pointer
== '.')
3996 input_line_pointer
++;
3997 /* @@ Some say data, some say bss. */
3998 if (strncmp (input_line_pointer
, "bss\"", 4)
3999 && strncmp (input_line_pointer
, "data\"", 5))
4001 while (*--input_line_pointer
!= '"')
4003 input_line_pointer
--;
4004 goto bad_common_segment
;
4006 while (*input_line_pointer
++ != '"')
4008 goto allocate_common
;
4011 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4013 demand_empty_rest_of_line ();
4018 p
= input_line_pointer
;
4019 while (*p
&& *p
!= '\n')
4023 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4025 input_line_pointer
= p
;
4026 ignore_rest_of_line ();
4031 /* Handle the .empty pseudo-op. This suppresses the warnings about
4032 invalid delay slot usage. */
4035 s_empty (int ignore ATTRIBUTE_UNUSED
)
4037 /* The easy way to implement is to just forget about the last
4043 s_seg (int ignore ATTRIBUTE_UNUSED
)
4046 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4048 input_line_pointer
+= 6;
4052 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4054 input_line_pointer
+= 6;
4058 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4060 input_line_pointer
+= 7;
4064 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4066 input_line_pointer
+= 5;
4067 /* We only support 2 segments -- text and data -- for now, so
4068 things in the "bss segment" will have to go into data for now.
4069 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4070 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4073 as_bad (_("Unknown segment type"));
4074 demand_empty_rest_of_line ();
4080 subseg_set (data_section
, 1);
4081 demand_empty_rest_of_line ();
4085 s_proc (int ignore ATTRIBUTE_UNUSED
)
4087 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4089 ++input_line_pointer
;
4091 ++input_line_pointer
;
4094 /* This static variable is set by s_uacons to tell sparc_cons_align
4095 that the expression does not need to be aligned. */
4097 static int sparc_no_align_cons
= 0;
4099 /* This static variable is set by sparc_cons to emit requested types
4100 of relocations in cons_fix_new_sparc. */
4102 static const char *sparc_cons_special_reloc
;
4104 /* This handles the unaligned space allocation pseudo-ops, such as
4105 .uaword. .uaword is just like .word, but the value does not need
4109 s_uacons (int bytes
)
4111 /* Tell sparc_cons_align not to align this value. */
4112 sparc_no_align_cons
= 1;
4114 sparc_no_align_cons
= 0;
4117 /* This handles the native word allocation pseudo-op .nword.
4118 For sparc_arch_size 32 it is equivalent to .word, for
4119 sparc_arch_size 64 it is equivalent to .xword. */
4122 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4124 cons (sparc_arch_size
== 32 ? 4 : 8);
4128 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4132 .register %g[2367],{#scratch|symbolname|#ignore}
4136 s_register (int ignore ATTRIBUTE_UNUSED
)
4141 const char *regname
;
4143 if (input_line_pointer
[0] != '%'
4144 || input_line_pointer
[1] != 'g'
4145 || ((input_line_pointer
[2] & ~1) != '2'
4146 && (input_line_pointer
[2] & ~1) != '6')
4147 || input_line_pointer
[3] != ',')
4148 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4149 reg
= input_line_pointer
[2] - '0';
4150 input_line_pointer
+= 4;
4152 if (*input_line_pointer
== '#')
4154 ++input_line_pointer
;
4155 regname
= input_line_pointer
;
4156 c
= get_symbol_end ();
4157 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4158 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4159 if (regname
[0] == 'i')
4166 regname
= input_line_pointer
;
4167 c
= get_symbol_end ();
4169 if (sparc_arch_size
== 64)
4173 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4174 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4175 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4176 as_bad (_("redefinition of global register"));
4180 if (regname
== NULL
)
4181 globals
[reg
] = (symbolS
*) 1;
4186 if (symbol_find (regname
))
4187 as_bad (_("Register symbol %s already defined."),
4190 globals
[reg
] = symbol_make (regname
);
4191 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4193 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4194 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4195 flags
|= BSF_GLOBAL
;
4196 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4197 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4198 S_SET_ALIGN (globals
[reg
], reg
);
4199 S_SET_SIZE (globals
[reg
], 0);
4200 /* Although we actually want undefined_section here,
4201 we have to use absolute_section, because otherwise
4202 generic as code will make it a COM section.
4203 We fix this up in sparc_adjust_symtab. */
4204 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4205 S_SET_OTHER (globals
[reg
], 0);
4206 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4207 ->internal_elf_sym
.st_info
=
4208 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4209 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4210 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4215 *input_line_pointer
= c
;
4217 demand_empty_rest_of_line ();
4220 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4221 symbols which need it. */
4224 sparc_adjust_symtab (void)
4228 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4230 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4231 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4234 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4235 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4238 S_SET_SEGMENT (sym
, undefined_section
);
4243 /* If the --enforce-aligned-data option is used, we require .word,
4244 et. al., to be aligned correctly. We do it by setting up an
4245 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4246 no unexpected alignment was introduced.
4248 The SunOS and Solaris native assemblers enforce aligned data by
4249 default. We don't want to do that, because gcc can deliberately
4250 generate misaligned data if the packed attribute is used. Instead,
4251 we permit misaligned data by default, and permit the user to set an
4252 option to check for it. */
4255 sparc_cons_align (int nbytes
)
4259 /* Only do this if we are enforcing aligned data. */
4260 if (! enforce_aligned_data
)
4263 /* Don't align if this is an unaligned pseudo-op. */
4264 if (sparc_no_align_cons
)
4267 nalign
= mylog2 (nbytes
);
4271 gas_assert (nalign
> 0);
4273 if (now_seg
== absolute_section
)
4275 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4276 as_bad (_("misaligned data"));
4280 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4281 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4283 record_alignment (now_seg
, nalign
);
4286 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4289 sparc_handle_align (fragS
*fragp
)
4294 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4296 switch (fragp
->fr_type
)
4300 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4304 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4315 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4317 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4318 if (INSN_BIG_ENDIAN
)
4319 number_to_chars_bigendian (p
, wval
, 4);
4321 number_to_chars_littleendian (p
, wval
, 4);
4327 if (INSN_BIG_ENDIAN
)
4328 number_to_chars_bigendian (p
, 0x01000000, 4);
4330 number_to_chars_littleendian (p
, 0x01000000, 4);
4332 fragp
->fr_fix
+= fix
;
4342 /* Some special processing for a Sparc ELF file. */
4345 sparc_elf_final_processing (void)
4347 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4348 sort of BFD interface for this. */
4349 if (sparc_arch_size
== 64)
4351 switch (sparc_memory_model
)
4354 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4357 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4363 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4364 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4365 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4366 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4367 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4368 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4372 sparc_cons (expressionS
*exp
, int size
)
4377 sparc_cons_special_reloc
= NULL
;
4378 save
= input_line_pointer
;
4379 if (input_line_pointer
[0] == '%'
4380 && input_line_pointer
[1] == 'r'
4381 && input_line_pointer
[2] == '_')
4383 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4385 input_line_pointer
+= 7;
4386 sparc_cons_special_reloc
= "disp";
4388 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4390 if (size
!= 4 && size
!= 8)
4391 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4394 input_line_pointer
+= 6;
4395 sparc_cons_special_reloc
= "plt";
4398 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4400 if (size
!= 4 && size
!= 8)
4401 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4404 input_line_pointer
+= 13;
4405 sparc_cons_special_reloc
= "tls_dtpoff";
4408 if (sparc_cons_special_reloc
)
4415 if (*input_line_pointer
!= '8')
4417 input_line_pointer
--;
4420 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4424 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4428 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4438 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4439 sparc_cons_special_reloc
, size
* 8, size
);
4443 input_line_pointer
+= 2;
4444 if (*input_line_pointer
!= '(')
4446 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4447 sparc_cons_special_reloc
, size
* 8);
4454 input_line_pointer
= save
;
4455 sparc_cons_special_reloc
= NULL
;
4460 char *end
= ++input_line_pointer
;
4463 while (! is_end_of_line
[(c
= *end
)])
4477 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4478 sparc_cons_special_reloc
, size
* 8);
4484 if (input_line_pointer
!= end
)
4486 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4487 sparc_cons_special_reloc
, size
* 8);
4491 input_line_pointer
++;
4493 c
= *input_line_pointer
;
4494 if (! is_end_of_line
[c
] && c
!= ',')
4495 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4496 sparc_cons_special_reloc
, size
* 8);
4502 if (sparc_cons_special_reloc
== NULL
)
4508 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4509 reloc for a cons. We could use the definition there, except that
4510 we want to handle little endian relocs specially. */
4513 cons_fix_new_sparc (fragS
*frag
,
4515 unsigned int nbytes
,
4518 bfd_reloc_code_real_type r
;
4520 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4521 (nbytes
== 2 ? BFD_RELOC_16
:
4522 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4524 if (target_little_endian_data
4526 && now_seg
->flags
& SEC_ALLOC
)
4527 r
= BFD_RELOC_SPARC_REV32
;
4529 if (sparc_cons_special_reloc
)
4531 if (*sparc_cons_special_reloc
== 'd')
4534 case 1: r
= BFD_RELOC_8_PCREL
; break;
4535 case 2: r
= BFD_RELOC_16_PCREL
; break;
4536 case 4: r
= BFD_RELOC_32_PCREL
; break;
4537 case 8: r
= BFD_RELOC_64_PCREL
; break;
4540 else if (*sparc_cons_special_reloc
== 'p')
4543 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4544 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4549 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4550 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4553 else if (sparc_no_align_cons
)
4557 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4558 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4559 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4564 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4565 sparc_cons_special_reloc
= NULL
;
4569 sparc_cfi_frame_initial_instructions (void)
4571 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4575 sparc_regname_to_dw2regnum (char *regname
)
4583 p
= strchr (q
, regname
[0]);
4586 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4588 return (p
- q
) * 8 + regname
[1] - '0';
4590 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4592 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4594 if (regname
[0] == 'f' || regname
[0] == 'r')
4596 unsigned int regnum
;
4598 regnum
= strtoul (regname
+ 1, &q
, 10);
4601 if (regnum
>= ((regname
[0] == 'f'
4602 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4605 if (regname
[0] == 'f')
4608 if (regnum
>= 64 && (regnum
& 1))
4617 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4619 sparc_cons_special_reloc
= "disp";
4620 sparc_no_align_cons
= 1;
4621 emit_expr (exp
, nbytes
);
4622 sparc_no_align_cons
= 0;
4623 sparc_cons_special_reloc
= NULL
;