1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
27 #include "elf/sparc.h"
28 #include "dwarf2dbg.h"
30 /* Some ancient Sun C compilers would not take such hex constants as
31 unsigned, and would end up sign-extending them to form an offsetT,
32 so use these constants instead. */
33 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
34 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
36 static int sparc_ip (char *, const struct sparc_opcode
**);
37 static int parse_sparc_asi (char **, const sparc_asi
**);
38 static int parse_keyword_arg (int (*) (const char *), char **, int *);
39 static int parse_const_expr_arg (char **, int *);
40 static int get_expression (char *);
42 /* Default architecture. */
43 /* ??? The default value should be V8, but sparclite support was added
44 by making it the default. GCC now passes -Asparclite, so maybe sometime in
45 the future we can set this to V8. */
47 #define DEFAULT_ARCH "sparclite"
49 static const char *default_arch
= DEFAULT_ARCH
;
51 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
53 static int default_init_p
;
55 /* Current architecture. We don't bump up unless necessary. */
56 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
58 /* The maximum architecture level we can bump up to.
59 In a 32 bit environment, don't allow bumping up to v9 by default.
60 The native assembler works this way. The user is required to pass
61 an explicit argument before we'll create v9 object files. However, if
62 we don't see any v9 insns, a v8plus object file is not created. */
63 static enum sparc_opcode_arch_val max_architecture
;
65 /* Either 32 or 64, selects file format. */
66 static int sparc_arch_size
;
67 /* Initial (default) value, recorded separately in case a user option
68 changes the value before md_show_usage is called. */
69 static int default_arch_size
;
71 /* The currently selected v9 memory model. Currently only used for
73 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
76 /* Bitmask of instruction types seen so far, used to populate the
77 GNU attributes section with hwcap information. */
78 static bfd_uint64_t hwcap_seen
;
81 static bfd_uint64_t hwcap_allowed
;
83 static int architecture_requested
;
84 static int warn_on_bump
;
86 /* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88 static enum sparc_opcode_arch_val warn_after_architecture
;
90 /* Non-zero if the assembler should generate error if an undeclared
91 g[23] register has been used in -64. */
92 static int no_undeclared_regs
;
94 /* Non-zero if the assembler should generate a warning if an
95 unpredictable DCTI (delayed control transfer instruction) couple is
97 static int dcti_couples_detect
;
99 /* Non-zero if we should try to relax jumps and calls. */
100 static int sparc_relax
;
102 /* Non-zero if we are generating PIC code. */
105 /* Non-zero if we should give an error when misaligned data is seen. */
106 static int enforce_aligned_data
;
108 extern int target_big_endian
;
110 static int target_little_endian_data
;
112 /* Symbols for global registers on v9. */
113 static symbolS
*globals
[8];
115 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
116 int sparc_cie_data_alignment
;
118 /* V9 and 86x have big and little endian data, but instructions are always big
119 endian. The sparclet has bi-endian support but both data and insns have
120 the same endianness. Global `target_big_endian' is used for data.
121 The following macro is used for instructions. */
122 #ifndef INSN_BIG_ENDIAN
123 #define INSN_BIG_ENDIAN (target_big_endian \
124 || default_arch_type == sparc86x \
125 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
128 /* Handle of the OPCODE hash table. */
129 static struct hash_control
*op_hash
;
131 static void s_data1 (void);
132 static void s_seg (int);
133 static void s_proc (int);
134 static void s_reserve (int);
135 static void s_common (int);
136 static void s_empty (int);
137 static void s_uacons (int);
138 static void s_ncons (int);
139 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
159 /* These are specific to sparc/svr4. */
160 {"2byte", s_uacons
, 2},
161 {"4byte", s_uacons
, 4},
162 {"8byte", s_uacons
, 8},
163 {"register", s_register
, 0},
167 /* This array holds the chars that always start a comment. If the
168 pre-processor is disabled, these aren't very useful. */
169 const char comment_chars
[] = "!"; /* JF removed '|' from
172 /* This array holds the chars that only start a comment at the beginning of
173 a line. If the line seems to have the form '# 123 filename'
174 .line and .file directives will appear in the pre-processed output. */
175 /* Note that input_file.c hand checks for '#' at the beginning of the
176 first line of the input file. This is because the compiler outputs
177 #NO_APP at the beginning of its output. */
178 /* Also note that comments started like this one will always
179 work if '/' isn't otherwise defined. */
180 const char line_comment_chars
[] = "#";
182 const char line_separator_chars
[] = ";";
184 /* Chars that can be used to separate mant from exp in floating point
186 const char EXP_CHARS
[] = "eE";
188 /* Chars that mean this number is a floating point constant.
191 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
193 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
194 changed in read.c. Ideally it shouldn't have to know about it at all,
195 but nothing is ideal around here. */
197 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
202 unsigned long opcode
;
203 struct nlist
*nlistp
;
207 bfd_reloc_code_real_type reloc
;
210 struct sparc_it the_insn
, set_insn
;
212 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
219 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
220 v8plusa
, v9
, v9a
, v9b
, v9_64
};
222 static struct sparc_arch
{
224 const char *opcode_arch
;
225 enum sparc_arch_types arch_type
;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size
;
229 /* Allowable arg to -A? */
231 /* Extra hardware capabilities allowed. These are added to the
232 hardware capabilities associated with the opcode
236 } sparc_arch_table
[] = {
237 { "v6", "v6", v6
, 0, 1, 0, 0 },
238 { "v7", "v7", v7
, 0, 1, 0, 0 },
239 { "v8", "v8", v8
, 32, 1, 0, 0 },
240 { "v8a", "v8", v8
, 32, 1, 0, 0 },
241 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
242 { "sparcvis", "v9a", v9
, 0, 1, 0, 0 },
243 { "sparcvis2", "v9b", v9
, 0, 1, 0, 0 },
244 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_FMAF
, 0 },
245 { "sparcima", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_IMA
, 0 },
246 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
247 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
249 { "sparc4", "v9v", v9
, 0, 1, 0, 0 },
250 { "sparc5", "v9m", v9
, 0, 1, 0, 0 },
251 { "sparc6", "m8", v9
, 0, 1, 0, 0 },
253 { "leon", "leon", leon
, 32, 1, 0, 0 },
254 { "sparclet", "sparclet", sparclet
, 32, 1, 0, 0 },
255 { "sparclite", "sparclite", sparclite
, 32, 1, 0, 0 },
256 { "sparc86x", "sparclite", sparc86x
, 32, 1, 0, 0 },
258 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
259 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
260 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
261 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
262 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
263 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
264 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
265 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
266 { "v8plusm8", "m8", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
268 { "v9", "v9", v9
, 0, 1, 0, 0 },
269 { "v9a", "v9a", v9
, 0, 1, 0, 0 },
270 { "v9b", "v9b", v9
, 0, 1, 0, 0 },
271 { "v9c", "v9c", v9
, 0, 1, 0, 0 },
272 { "v9d", "v9d", v9
, 0, 1, 0, 0 },
273 { "v9e", "v9e", v9
, 0, 1, 0, 0 },
274 { "v9v", "v9v", v9
, 0, 1, 0, 0 },
275 { "v9m", "v9m", v9
, 0, 1, 0, 0 },
276 { "v9m8", "m8", v9
, 0, 1, 0, 0 },
278 /* This exists to allow configure.tgt to pass one
279 value to specify both the default machine and default word size. */
280 { "v9-64", "v9", v9
, 64, 0, 0, 0 },
281 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
284 /* Variant of default_arch */
285 static enum sparc_arch_types default_arch_type
;
287 static struct sparc_arch
*
288 lookup_arch (const char *name
)
290 struct sparc_arch
*sa
;
292 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
293 if (strcmp (sa
->name
, name
) == 0)
295 if (sa
->name
== NULL
)
300 /* Initialize the default opcode arch and word size from the default
301 architecture name. */
304 init_default_arch (void)
306 struct sparc_arch
*sa
= lookup_arch (default_arch
);
309 || sa
->default_arch_size
== 0)
310 as_fatal (_("Invalid default architecture, broken assembler."));
312 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
313 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
314 as_fatal (_("Bad opcode table, broken assembler."));
315 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
317 default_arch_type
= sa
->arch_type
;
320 /* Called by TARGET_MACH. */
325 /* We don't get a chance to initialize anything before we're called,
326 so handle that now. */
327 if (! default_init_p
)
328 init_default_arch ();
330 return sparc_arch_size
== 64 ? bfd_mach_sparc_v9
: bfd_mach_sparc
;
333 /* Called by TARGET_FORMAT. */
336 sparc_target_format (void)
338 /* We don't get a chance to initialize anything before we're called,
339 so handle that now. */
340 if (! default_init_p
)
341 init_default_arch ();
344 return "elf32-sparc-vxworks";
347 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
351 * Invocation line includes a switch not recognized by the base assembler.
352 * See if it's a processor-specific option. These are:
355 * Warn on architecture bumps. See also -A.
357 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
358 * Standard 32 bit architectures.
360 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
361 * This used to only mean 64 bits, but properly specifying it
362 * complicated gcc's ASM_SPECs, so now opcode selection is
363 * specified orthogonally to word size (except when specifying
364 * the default, but that is an internal implementation detail).
365 * -Av8plus, -Av8plusa, -Av8plusb
366 * Same as -Av9{,a,b}.
367 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
368 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
370 * -xarch=v9, -xarch=v9a, -xarch=v9b
371 * Same as -Av9{,a,b} -64, for compatibility with Sun's
374 * Select the architecture and possibly the file format.
375 * Instructions or features not supported by the selected
376 * architecture cause fatal errors.
378 * The default is to start at v6, and bump the architecture up
379 * whenever an instruction is seen at a higher level. In 32 bit
380 * environments, v9 is not bumped up to, the user must pass
383 * If -bump is specified, a warning is printing when bumping to
386 * If an architecture is specified, all instructions must match
387 * that architecture. Any higher level instructions are flagged
388 * as errors. Note that in the 32 bit environment specifying
389 * -Av8plus does not automatically create a v8plus object file, a
390 * v9 insn must be seen.
392 * If both an architecture and -bump are specified, the
393 * architecture starts at the specified level, but bumps are
394 * warnings. Note that we can't set `current_architecture' to
395 * the requested level in this case: in the 32 bit environment,
396 * we still must avoid creating v8plus object files unless v9
400 * Bumping between incompatible architectures is always an
401 * error. For example, from sparclite to v9.
404 const char *md_shortopts
= "A:K:VQ:sq";
405 struct option md_longopts
[] = {
406 #define OPTION_BUMP (OPTION_MD_BASE)
407 {"bump", no_argument
, NULL
, OPTION_BUMP
},
408 #define OPTION_SPARC (OPTION_MD_BASE + 1)
409 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
410 #define OPTION_XARCH (OPTION_MD_BASE + 2)
411 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
412 #define OPTION_32 (OPTION_MD_BASE + 3)
413 {"32", no_argument
, NULL
, OPTION_32
},
414 #define OPTION_64 (OPTION_MD_BASE + 4)
415 {"64", no_argument
, NULL
, OPTION_64
},
416 #define OPTION_TSO (OPTION_MD_BASE + 5)
417 {"TSO", no_argument
, NULL
, OPTION_TSO
},
418 #define OPTION_PSO (OPTION_MD_BASE + 6)
419 {"PSO", no_argument
, NULL
, OPTION_PSO
},
420 #define OPTION_RMO (OPTION_MD_BASE + 7)
421 {"RMO", no_argument
, NULL
, OPTION_RMO
},
422 #ifdef SPARC_BIENDIAN
423 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
424 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
425 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
426 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
428 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
429 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
430 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
431 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
432 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
433 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
434 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
435 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
436 #define OPTION_RELAX (OPTION_MD_BASE + 14)
437 {"relax", no_argument
, NULL
, OPTION_RELAX
},
438 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
439 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
440 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
441 {"dcti-couples-detect", no_argument
, NULL
, OPTION_DCTI_COUPLES_DETECT
},
442 {NULL
, no_argument
, NULL
, 0}
445 size_t md_longopts_size
= sizeof (md_longopts
);
448 md_parse_option (int c
, const char *arg
)
450 /* We don't get a chance to initialize anything before we're called,
451 so handle that now. */
452 if (! default_init_p
)
453 init_default_arch ();
459 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
463 if (!strncmp (arg
, "v9", 2))
464 md_parse_option (OPTION_64
, NULL
);
467 if (!strncmp (arg
, "v8", 2)
468 || !strncmp (arg
, "v7", 2)
469 || !strncmp (arg
, "v6", 2)
470 || !strcmp (arg
, "sparclet")
471 || !strcmp (arg
, "sparclite")
472 || !strcmp (arg
, "sparc86x"))
473 md_parse_option (OPTION_32
, NULL
);
479 struct sparc_arch
*sa
;
480 enum sparc_opcode_arch_val opcode_arch
;
482 sa
= lookup_arch (arg
);
484 || ! sa
->user_option_p
)
486 if (c
== OPTION_XARCH
)
487 as_bad (_("invalid architecture -xarch=%s"), arg
);
489 as_bad (_("invalid architecture -A%s"), arg
);
493 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
494 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
495 as_fatal (_("Bad opcode table, broken assembler."));
497 if (!architecture_requested
498 || opcode_arch
> max_architecture
)
499 max_architecture
= opcode_arch
;
501 /* The allowed hardware capabilities are the implied by the
502 opcodes arch plus any extra capabilities defined in the GAS
506 | (((bfd_uint64_t
) sparc_opcode_archs
[opcode_arch
].hwcaps2
) << 32)
507 | (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32)
508 | sparc_opcode_archs
[opcode_arch
].hwcaps
509 | sa
->hwcap_allowed
);
510 architecture_requested
= 1;
515 /* Ignore -sparc, used by SunOS make default .s.o rule. */
518 case OPTION_ENFORCE_ALIGNED_DATA
:
519 enforce_aligned_data
= 1;
522 #ifdef SPARC_BIENDIAN
523 case OPTION_LITTLE_ENDIAN
:
524 target_big_endian
= 0;
525 if (default_arch_type
!= sparclet
)
526 as_fatal ("This target does not support -EL");
528 case OPTION_LITTLE_ENDIAN_DATA
:
529 target_little_endian_data
= 1;
530 target_big_endian
= 0;
531 if (default_arch_type
!= sparc86x
532 && default_arch_type
!= v9
)
533 as_fatal ("This target does not support --little-endian-data");
535 case OPTION_BIG_ENDIAN
:
536 target_big_endian
= 1;
543 const char **list
, **l
;
545 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
546 list
= bfd_target_list ();
547 for (l
= list
; *l
!= NULL
; l
++)
549 if (sparc_arch_size
== 32)
551 if (CONST_STRNEQ (*l
, "elf32-sparc"))
556 if (CONST_STRNEQ (*l
, "elf64-sparc"))
561 as_fatal (_("No compiled in support for %d bit object file format"),
565 if (sparc_arch_size
== 64
566 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
567 max_architecture
= SPARC_OPCODE_ARCH_V9
;
572 sparc_memory_model
= MM_TSO
;
576 sparc_memory_model
= MM_PSO
;
580 sparc_memory_model
= MM_RMO
;
588 /* Qy - do emit .comment
589 Qn - do not emit .comment. */
593 /* Use .stab instead of .stab.excl. */
597 /* quick -- Native assembler does fewer checks. */
601 if (strcmp (arg
, "PIC") != 0)
602 as_warn (_("Unrecognized option following -K"));
607 case OPTION_NO_UNDECLARED_REGS
:
608 no_undeclared_regs
= 1;
611 case OPTION_UNDECLARED_REGS
:
612 no_undeclared_regs
= 0;
619 case OPTION_NO_RELAX
:
623 case OPTION_DCTI_COUPLES_DETECT
:
624 dcti_couples_detect
= 1;
635 md_show_usage (FILE *stream
)
637 const struct sparc_arch
*arch
;
640 /* We don't get a chance to initialize anything before we're called,
641 so handle that now. */
642 if (! default_init_p
)
643 init_default_arch ();
645 fprintf (stream
, _("SPARC options:\n"));
647 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
649 if (!arch
->user_option_p
)
651 if (arch
!= &sparc_arch_table
[0])
652 fprintf (stream
, " | ");
653 if (column
+ strlen (arch
->name
) > 70)
656 fputc ('\n', stream
);
658 column
+= 5 + 2 + strlen (arch
->name
);
659 fprintf (stream
, "-A%s", arch
->name
);
661 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
663 if (!arch
->user_option_p
)
665 fprintf (stream
, " | ");
666 if (column
+ strlen (arch
->name
) > 65)
669 fputc ('\n', stream
);
671 column
+= 5 + 7 + strlen (arch
->name
);
672 fprintf (stream
, "-xarch=%s", arch
->name
);
674 fprintf (stream
, _("\n\
675 specify variant of SPARC architecture\n\
676 -bump warn when assembler switches architectures\n\
678 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
679 -relax relax jumps and branches (default)\n\
680 -no-relax avoid changing any jumps and branches\n"));
681 fprintf (stream
, _("\
682 -32 create 32 bit object file\n\
683 -64 create 64 bit object file\n"));
684 fprintf (stream
, _("\
685 [default is %d]\n"), default_arch_size
);
686 fprintf (stream
, _("\
687 -TSO use Total Store Ordering\n\
688 -PSO use Partial Store Ordering\n\
689 -RMO use Relaxed Memory Ordering\n"));
690 fprintf (stream
, _("\
691 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
692 fprintf (stream
, _("\
693 -KPIC generate PIC\n\
694 -V print assembler version number\n\
695 -undeclared-regs ignore application global register usage without\n\
696 appropriate .register directive (default)\n\
697 -no-undeclared-regs force error on application global register usage\n\
698 without appropriate .register directive\n\
699 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
703 #ifdef SPARC_BIENDIAN
704 fprintf (stream
, _("\
705 -EL generate code for a little endian machine\n\
706 -EB generate code for a big endian machine\n\
707 --little-endian-data generate code for a machine having big endian\n\
708 instructions and little endian data.\n"));
712 /* Native operand size opcode translation. */
718 } native_op_table
[] =
720 {"ldn", "ld", "ldx"},
721 {"ldna", "lda", "ldxa"},
722 {"stn", "st", "stx"},
723 {"stna", "sta", "stxa"},
724 {"slln", "sll", "sllx"},
725 {"srln", "srl", "srlx"},
726 {"sran", "sra", "srax"},
727 {"casn", "cas", "casx"},
728 {"casna", "casa", "casxa"},
729 {"clrn", "clr", "clrx"},
733 /* sparc64 privileged and hyperprivileged registers. */
735 struct priv_reg_entry
741 struct priv_reg_entry priv_reg_table
[] =
762 {NULL
, -1}, /* End marker. */
765 struct priv_reg_entry hpriv_reg_table
[] =
775 {"hstick_offset", 28},
776 {"hstick_enable", 29},
778 {NULL
, -1}, /* End marker. */
781 /* v9a or later specific ancillary state registers. */
783 struct priv_reg_entry v9a_asr_table
[] =
786 {"sys_tick_cmpr", 25},
790 {"softint_clear", 21},
801 {"clear_softint", 21},
802 {NULL
, -1}, /* End marker. */
806 cmp_reg_entry (const void *parg
, const void *qarg
)
808 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
809 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
811 if (p
->name
== q
->name
)
813 else if (p
->name
== NULL
)
815 else if (q
->name
== NULL
)
818 return strcmp (q
->name
, p
->name
);
821 /* sparc %-pseudo-operations. */
824 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
825 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
827 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
828 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
830 instruction. (Generally they can appear
831 anywhere an immediate operand is
835 /* The name as it appears in assembler. */
837 /* The reloc this pseudo-op translates to. */
838 bfd_reloc_code_real_type reloc
;
839 /* Flags. See F_POP_* above. */
843 struct pop_entry pop_table
[] =
845 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
846 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
847 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
848 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
849 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
850 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
851 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
852 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
853 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
854 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
855 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
856 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
857 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
858 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
859 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
860 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
861 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
862 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
863 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
864 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
865 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
866 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
867 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
868 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
869 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
870 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
871 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
872 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
873 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
874 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
875 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
876 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
877 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
878 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
879 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
880 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
881 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
884 /* Table of %-names that can appear in a sparc assembly program. This
885 table is initialized in md_begin and contains entries for each
886 privileged/hyperprivileged/alternate register and %-pseudo-op. */
899 enum perc_entry_type type
;
900 /* Name of the %-entity. */
904 /* Value. Either a pop or a reg depending on type.*/
907 struct pop_entry
*pop
;
908 struct priv_reg_entry
*reg
;
912 #define NUM_PERC_ENTRIES \
913 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
914 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
915 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
916 + ARRAY_SIZE (pop_table) \
919 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
922 cmp_perc_entry (const void *parg
, const void *qarg
)
924 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
925 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
927 if (p
->name
== q
->name
)
929 else if (p
->name
== NULL
)
931 else if (q
->name
== NULL
)
934 return strcmp (q
->name
, p
->name
);
937 /* This function is called once, at assembler startup time. It should
938 set up all the tables, etc. that the MD part of the assembler will
944 const char *retval
= NULL
;
948 /* We don't get a chance to initialize anything before md_parse_option
949 is called, and it may not be called, so handle default initialization
950 now if not already done. */
951 if (! default_init_p
)
952 init_default_arch ();
954 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
955 op_hash
= hash_new ();
957 while (i
< (unsigned int) sparc_num_opcodes
)
959 const char *name
= sparc_opcodes
[i
].name
;
960 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
963 as_bad (_("Internal error: can't hash `%s': %s\n"),
964 sparc_opcodes
[i
].name
, retval
);
969 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
971 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
972 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
977 while (i
< (unsigned int) sparc_num_opcodes
978 && !strcmp (sparc_opcodes
[i
].name
, name
));
981 for (i
= 0; native_op_table
[i
].name
; i
++)
983 const struct sparc_opcode
*insn
;
984 const char *name
= ((sparc_arch_size
== 32)
985 ? native_op_table
[i
].name32
986 : native_op_table
[i
].name64
);
987 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
990 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
991 name
, native_op_table
[i
].name
);
996 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1000 as_bad (_("Internal error: can't hash `%s': %s\n"),
1001 sparc_opcodes
[i
].name
, retval
);
1008 as_fatal (_("Broken assembler. No assembly attempted."));
1010 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1011 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1012 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1013 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1014 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1015 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1017 /* If -bump, record the architecture level at which we start issuing
1018 warnings. The behaviour is different depending upon whether an
1019 architecture was explicitly specified. If it wasn't, we issue warnings
1020 for all upwards bumps. If it was, we don't start issuing warnings until
1021 we need to bump beyond the requested architecture or when we bump between
1022 conflicting architectures. */
1025 && architecture_requested
)
1027 /* `max_architecture' records the requested architecture.
1028 Issue warnings if we go above it. */
1029 warn_after_architecture
= max_architecture
;
1032 /* Find the highest architecture level that doesn't conflict with
1033 the requested one. */
1036 || !architecture_requested
)
1038 enum sparc_opcode_arch_val current_max_architecture
1041 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1042 max_architecture
> warn_after_architecture
;
1044 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1045 current_max_architecture
))
1049 /* Prepare the tables of %-pseudo-ops. */
1051 struct priv_reg_entry
*reg_tables
[]
1052 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1053 struct priv_reg_entry
**reg_table
;
1056 /* Add registers. */
1057 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1059 struct priv_reg_entry
*reg
;
1060 for (reg
= *reg_table
; reg
->name
; reg
++)
1062 struct perc_entry
*p
= &perc_table
[entry
++];
1063 p
->type
= perc_entry_reg
;
1064 p
->name
= reg
->name
;
1065 p
->len
= strlen (reg
->name
);
1070 /* Add %-pseudo-ops. */
1071 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1073 struct perc_entry
*p
= &perc_table
[entry
++];
1074 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1075 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1076 p
->name
= pop_table
[i
].name
;
1077 p
->len
= strlen (pop_table
[i
].name
);
1078 p
->pop
= &pop_table
[i
];
1081 /* Last entry is the sentinel. */
1082 perc_table
[entry
].type
= perc_entry_none
;
1084 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1085 sizeof (perc_table
[0]), cmp_perc_entry
);
1090 /* Called after all assembly has been done. */
1097 int hwcaps
, hwcaps2
;
1100 if (sparc_arch_size
== 64)
1101 switch (current_architecture
)
1103 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1104 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1105 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1106 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1107 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1108 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1109 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1110 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v9m8
; break;
1111 default: mach
= bfd_mach_sparc_v9
; break;
1114 switch (current_architecture
)
1116 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1117 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1118 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1119 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1120 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1121 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1122 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1123 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1124 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1125 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v8plusm8
; break;
1126 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1127 be but for now it is (since that's the way it's always been
1129 default: mach
= bfd_mach_sparc
; break;
1131 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1134 hwcaps
= hwcap_seen
& U0xffffffff
;
1135 hwcaps2
= hwcap_seen
>> 32;
1138 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1140 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1144 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1147 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1151 /* Sign-extend the value from the architecture word size, so that
1152 0xffffffff is always considered -1 on sparc32. */
1153 if (sparc_arch_size
== 32)
1155 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1156 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1165 /* Return non-zero if VAL is in the range 0 to MAX. */
1168 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1175 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1176 (e.g. -15 to +31). */
1179 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1185 if (val
< ~(max
>> 1))
1191 sparc_ffs (unsigned int mask
)
1198 for (i
= 0; (mask
& 1) == 0; ++i
)
1203 /* Implement big shift right. */
1205 BSR (bfd_vma val
, int amount
)
1207 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1208 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1209 return val
>> amount
;
1212 /* For communication between sparc_ip and get_expression. */
1213 static char *expr_end
;
1215 /* Values for `special_case'.
1216 Instructions that require weird handling because they're longer than
1218 #define SPECIAL_CASE_NONE 0
1219 #define SPECIAL_CASE_SET 1
1220 #define SPECIAL_CASE_SETSW 2
1221 #define SPECIAL_CASE_SETX 3
1222 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1223 #define SPECIAL_CASE_FDIV 4
1225 /* Bit masks of various insns. */
1226 #define NOP_INSN 0x01000000
1227 #define OR_INSN 0x80100000
1228 #define XOR_INSN 0x80180000
1229 #define FMOVS_INSN 0x81A00020
1230 #define SETHI_INSN 0x01000000
1231 #define SLLX_INSN 0x81281000
1232 #define SRA_INSN 0x81380000
1234 /* The last instruction to be assembled. */
1235 static const struct sparc_opcode
*last_insn
;
1236 /* The assembled opcode of `last_insn'. */
1237 static unsigned long last_opcode
;
1239 /* Handle the set and setuw synthetic instructions. */
1242 synthetize_setuw (const struct sparc_opcode
*insn
)
1244 int need_hi22_p
= 0;
1245 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1247 if (the_insn
.exp
.X_op
== O_constant
)
1249 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1251 if (sizeof (offsetT
) > 4
1252 && (the_insn
.exp
.X_add_number
< 0
1253 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1254 as_warn (_("set: number not in 0..4294967295 range"));
1258 if (sizeof (offsetT
) > 4
1259 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1260 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1261 as_warn (_("set: number not in -2147483648..4294967295 range"));
1262 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1266 /* See if operand is absolute and small; skip sethi if so. */
1267 if (the_insn
.exp
.X_op
!= O_constant
1268 || the_insn
.exp
.X_add_number
>= (1 << 12)
1269 || the_insn
.exp
.X_add_number
< -(1 << 12))
1271 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1272 | ((the_insn
.exp
.X_add_number
>> 10)
1273 & (the_insn
.exp
.X_op
== O_constant
1275 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1276 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1277 output_insn (insn
, &the_insn
);
1281 /* See if operand has no low-order bits; skip OR if so. */
1282 if (the_insn
.exp
.X_op
!= O_constant
1283 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1286 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1288 | (the_insn
.exp
.X_add_number
1289 & (the_insn
.exp
.X_op
!= O_constant
1290 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1291 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1292 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1293 output_insn (insn
, &the_insn
);
1297 /* Handle the setsw synthetic instruction. */
1300 synthetize_setsw (const struct sparc_opcode
*insn
)
1304 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1306 if (the_insn
.exp
.X_op
!= O_constant
)
1308 synthetize_setuw (insn
);
1310 /* Need to sign extend it. */
1311 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1312 the_insn
.reloc
= BFD_RELOC_NONE
;
1313 output_insn (insn
, &the_insn
);
1317 if (sizeof (offsetT
) > 4
1318 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1319 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1320 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1322 low32
= the_insn
.exp
.X_add_number
;
1326 synthetize_setuw (insn
);
1332 the_insn
.reloc
= BFD_RELOC_NONE
;
1333 /* See if operand is absolute and small; skip sethi if so. */
1334 if (low32
< -(1 << 12))
1336 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1337 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1338 output_insn (insn
, &the_insn
);
1339 low32
= 0x1c00 | (low32
& 0x3ff);
1340 opc
= RS1 (rd
) | XOR_INSN
;
1343 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1344 | (low32
& 0x1fff));
1345 output_insn (insn
, &the_insn
);
1348 /* Handle the setx synthetic instruction. */
1351 synthetize_setx (const struct sparc_opcode
*insn
)
1353 int upper32
, lower32
;
1354 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1355 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1357 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1358 int need_xor10_p
= 0;
1360 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1361 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1362 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1365 upper_dstreg
= tmpreg
;
1366 /* The tmp reg should not be the dst reg. */
1367 if (tmpreg
== dstreg
)
1368 as_warn (_("setx: temporary register same as destination register"));
1370 /* ??? Obviously there are other optimizations we can do
1371 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1372 doing some of these. Later. If you do change things, try to
1373 change all of this to be table driven as well. */
1374 /* What to output depends on the number if it's constant.
1375 Compute that first, then output what we've decided upon. */
1376 if (the_insn
.exp
.X_op
!= O_constant
)
1378 if (sparc_arch_size
== 32)
1380 /* When arch size is 32, we want setx to be equivalent
1381 to setuw for anything but constants. */
1382 the_insn
.exp
.X_add_number
&= 0xffffffff;
1383 synthetize_setuw (insn
);
1386 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1392 /* Reset X_add_number, we've extracted it as upper32/lower32.
1393 Otherwise fixup_segment will complain about not being able to
1394 write an 8 byte number in a 4 byte field. */
1395 the_insn
.exp
.X_add_number
= 0;
1397 /* Only need hh22 if `or' insn can't handle constant. */
1398 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1401 /* Does bottom part (after sethi) have bits? */
1402 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1403 /* No hh22, but does upper32 still have bits we can't set
1405 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1408 /* If the lower half is all zero, we build the upper half directly
1409 into the dst reg. */
1411 /* Need lower half if number is zero or 0xffffffff00000000. */
1412 || (! need_hh22_p
&& ! need_hm10_p
))
1414 /* No need for sethi if `or' insn can handle constant. */
1415 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1416 /* Note that we can't use a negative constant in the `or'
1417 insn unless the upper 32 bits are all ones. */
1418 || (lower32
< 0 && upper32
!= -1)
1419 || (lower32
>= 0 && upper32
== -1))
1422 if (need_hi22_p
&& upper32
== -1)
1425 /* Does bottom part (after sethi) have bits? */
1426 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1428 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1429 /* Need `or' if we didn't set anything else. */
1430 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1434 /* Output directly to dst reg if lower 32 bits are all zero. */
1435 upper_dstreg
= dstreg
;
1438 if (!upper_dstreg
&& dstreg
)
1439 as_warn (_("setx: illegal temporary register g0"));
1443 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1444 | ((upper32
>> 10) & 0x3fffff));
1445 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1446 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1447 output_insn (insn
, &the_insn
);
1452 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1453 | (((need_xor10_p
? ~lower32
: lower32
)
1454 >> 10) & 0x3fffff));
1455 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1456 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1457 output_insn (insn
, &the_insn
);
1462 the_insn
.opcode
= (OR_INSN
1463 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1466 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1467 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1468 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1469 output_insn (insn
, &the_insn
);
1474 /* FIXME: One nice optimization to do here is to OR the low part
1475 with the highpart if hi22 isn't needed and the low part is
1477 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1480 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1481 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1482 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1483 output_insn (insn
, &the_insn
);
1486 /* If we needed to build the upper part, shift it into place. */
1487 if (need_hh22_p
|| need_hm10_p
)
1489 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1491 the_insn
.reloc
= BFD_RELOC_NONE
;
1492 output_insn (insn
, &the_insn
);
1495 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1498 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1499 | 0x1c00 | (lower32
& 0x3ff));
1500 the_insn
.reloc
= BFD_RELOC_NONE
;
1501 output_insn (insn
, &the_insn
);
1504 /* If we needed to build both upper and lower parts, OR them together. */
1505 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1507 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1509 the_insn
.reloc
= BFD_RELOC_NONE
;
1510 output_insn (insn
, &the_insn
);
1514 /* Main entry point to assemble one instruction. */
1517 md_assemble (char *str
)
1519 const struct sparc_opcode
*insn
;
1523 special_case
= sparc_ip (str
, &insn
);
1527 /* Certain instructions may not appear on delay slots. Check for
1528 these situations. */
1529 if (last_insn
!= NULL
1530 && (last_insn
->flags
& F_DELAYED
) != 0)
1532 /* Before SPARC V9 the effect of having a delayed branch
1533 instruction in the delay slot of a conditional delayed branch
1536 In SPARC V9 DCTI couples are well defined.
1538 However, starting with the UltraSPARC Architecture 2005, DCTI
1539 couples (of all kind) are deprecated and should not be used,
1540 as they may be slow or behave differently to what the
1541 programmer expects. */
1542 if (dcti_couples_detect
1543 && (insn
->flags
& F_DELAYED
) != 0
1544 && ((max_architecture
< SPARC_OPCODE_ARCH_V9
1545 && (last_insn
->flags
& F_CONDBR
) != 0)
1546 || max_architecture
>= SPARC_OPCODE_ARCH_V9C
))
1547 as_warn (_("unpredictable DCTI couple"));
1550 /* We warn about attempts to put a floating point branch in a
1551 delay slot, unless the delay slot has been annulled. */
1552 if ((insn
->flags
& F_FBR
) != 0
1553 /* ??? This test isn't completely accurate. We assume anything with
1554 F_{UNBR,CONDBR,FBR} set is annullable. */
1555 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1556 || (last_opcode
& ANNUL
) == 0))
1557 as_warn (_("FP branch in delay slot"));
1560 /* SPARC before v9 requires a nop instruction between a floating
1561 point instruction and a floating point branch. We insert one
1562 automatically, with a warning. */
1563 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1564 && last_insn
!= NULL
1565 && (insn
->flags
& F_FBR
) != 0
1566 && (last_insn
->flags
& F_FLOAT
) != 0)
1568 struct sparc_it nop_insn
;
1570 nop_insn
.opcode
= NOP_INSN
;
1571 nop_insn
.reloc
= BFD_RELOC_NONE
;
1572 output_insn (insn
, &nop_insn
);
1573 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1576 switch (special_case
)
1578 case SPECIAL_CASE_NONE
:
1580 output_insn (insn
, &the_insn
);
1583 case SPECIAL_CASE_SETSW
:
1584 synthetize_setsw (insn
);
1587 case SPECIAL_CASE_SET
:
1588 synthetize_setuw (insn
);
1591 case SPECIAL_CASE_SETX
:
1592 synthetize_setx (insn
);
1595 case SPECIAL_CASE_FDIV
:
1597 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1599 output_insn (insn
, &the_insn
);
1601 /* According to information leaked from Sun, the "fdiv" instructions
1602 on early SPARC machines would produce incorrect results sometimes.
1603 The workaround is to add an fmovs of the destination register to
1604 itself just after the instruction. This was true on machines
1605 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1606 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1607 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1608 output_insn (insn
, &the_insn
);
1613 as_fatal (_("failed special case insn sanity check"));
1618 get_hwcap_name (bfd_uint64_t mask
)
1620 if (mask
& HWCAP_MUL32
)
1622 if (mask
& HWCAP_DIV32
)
1624 if (mask
& HWCAP_FSMULD
)
1626 if (mask
& HWCAP_V8PLUS
)
1628 if (mask
& HWCAP_POPC
)
1630 if (mask
& HWCAP_VIS
)
1632 if (mask
& HWCAP_VIS2
)
1634 if (mask
& HWCAP_ASI_BLK_INIT
)
1635 return "ASIBlkInit";
1636 if (mask
& HWCAP_FMAF
)
1638 if (mask
& HWCAP_VIS3
)
1640 if (mask
& HWCAP_HPC
)
1642 if (mask
& HWCAP_RANDOM
)
1644 if (mask
& HWCAP_TRANS
)
1646 if (mask
& HWCAP_FJFMAU
)
1648 if (mask
& HWCAP_IMA
)
1650 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1652 if (mask
& HWCAP_AES
)
1654 if (mask
& HWCAP_DES
)
1656 if (mask
& HWCAP_KASUMI
)
1658 if (mask
& HWCAP_CAMELLIA
)
1660 if (mask
& HWCAP_MD5
)
1662 if (mask
& HWCAP_SHA1
)
1664 if (mask
& HWCAP_SHA256
)
1666 if (mask
& HWCAP_SHA512
)
1668 if (mask
& HWCAP_MPMUL
)
1670 if (mask
& HWCAP_MONT
)
1672 if (mask
& HWCAP_PAUSE
)
1674 if (mask
& HWCAP_CBCOND
)
1676 if (mask
& HWCAP_CRC32C
)
1680 if (mask
& HWCAP2_FJATHPLUS
)
1682 if (mask
& HWCAP2_VIS3B
)
1684 if (mask
& HWCAP2_ADP
)
1686 if (mask
& HWCAP2_SPARC5
)
1688 if (mask
& HWCAP2_MWAIT
)
1690 if (mask
& HWCAP2_XMPMUL
)
1692 if (mask
& HWCAP2_XMONT
)
1694 if (mask
& HWCAP2_NSEC
)
1696 if (mask
& HWCAP2_SPARC6
)
1698 if (mask
& HWCAP2_ONADDSUB
)
1700 if (mask
& HWCAP2_ONMUL
)
1702 if (mask
& HWCAP2_ONDIV
)
1704 if (mask
& HWCAP2_DICTUNP
)
1706 if (mask
& HWCAP2_FPCMPSHL
)
1708 if (mask
& HWCAP2_RLE
)
1710 if (mask
& HWCAP2_SHA3
)
1716 /* Subroutine of md_assemble to do the actual parsing. */
1719 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1721 const char *error_message
= "";
1725 const struct sparc_opcode
*insn
;
1727 unsigned long opcode
;
1728 unsigned int mask
= 0;
1732 int special_case
= SPECIAL_CASE_NONE
;
1733 const sparc_asi
*sasi
= NULL
;
1740 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1757 as_bad (_("Unknown opcode: `%s'"), str
);
1759 return special_case
;
1761 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1765 as_bad (_("Unknown opcode: `%s'"), str
);
1766 return special_case
;
1776 opcode
= insn
->match
;
1777 memset (&the_insn
, '\0', sizeof (the_insn
));
1778 the_insn
.reloc
= BFD_RELOC_NONE
;
1781 /* Build the opcode, checking as we go to make sure that the
1783 for (args
= insn
->args
;; ++args
)
1791 /* Parse a series of masks. */
1798 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1801 error_message
= _(": invalid membar mask name");
1807 if (*s
== '|' || *s
== '+')
1815 if (! parse_const_expr_arg (&s
, &kmask
))
1817 error_message
= _(": invalid membar mask expression");
1820 if (kmask
< 0 || kmask
> 127)
1822 error_message
= _(": invalid membar mask number");
1827 opcode
|= MEMBAR (kmask
);
1835 if (! parse_const_expr_arg (&s
, &smask
))
1837 error_message
= _(": invalid siam mode expression");
1840 if (smask
< 0 || smask
> 7)
1842 error_message
= _(": invalid siam mode number");
1853 /* Parse a prefetch function. */
1856 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1858 error_message
= _(": invalid prefetch function name");
1864 if (! parse_const_expr_arg (&s
, &fcn
))
1866 error_message
= _(": invalid prefetch function expression");
1869 if (fcn
< 0 || fcn
> 31)
1871 error_message
= _(": invalid prefetch function number");
1881 /* Parse a sparc64 privileged register. */
1884 struct priv_reg_entry
*p
;
1885 unsigned int len
= 9999999; /* Init to make gcc happy. */
1888 for (p
= priv_reg_table
; p
->name
; p
++)
1889 if (p
->name
[0] == s
[0])
1891 len
= strlen (p
->name
);
1892 if (strncmp (p
->name
, s
, len
) == 0)
1898 error_message
= _(": unrecognizable privileged register");
1902 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1904 error_message
= _(": unrecognizable privileged register");
1913 error_message
= _(": unrecognizable privileged register");
1919 /* Parse a sparc64 hyperprivileged register. */
1922 struct priv_reg_entry
*p
;
1923 unsigned int len
= 9999999; /* Init to make gcc happy. */
1926 for (p
= hpriv_reg_table
; p
->name
; p
++)
1927 if (p
->name
[0] == s
[0])
1929 len
= strlen (p
->name
);
1930 if (strncmp (p
->name
, s
, len
) == 0)
1936 error_message
= _(": unrecognizable hyperprivileged register");
1940 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1942 error_message
= _(": unrecognizable hyperprivileged register");
1951 error_message
= _(": unrecognizable hyperprivileged register");
1957 /* Parse a v9a or later ancillary state register. */
1960 struct priv_reg_entry
*p
;
1961 unsigned int len
= 9999999; /* Init to make gcc happy. */
1964 for (p
= v9a_asr_table
; p
->name
; p
++)
1965 if (p
->name
[0] == s
[0])
1967 len
= strlen (p
->name
);
1968 if (strncmp (p
->name
, s
, len
) == 0)
1974 error_message
= _(": unrecognizable ancillary state register");
1978 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1980 error_message
= _(": unrecognizable ancillary state register");
1989 error_message
= _(": unrecognizable ancillary state register");
1995 if (strncmp (s
, "%asr", 4) == 0)
2003 while (ISDIGIT (*s
))
2005 num
= num
* 10 + *s
- '0';
2009 /* We used to check here for the asr number to
2010 be between 16 and 31 in V9 and later, as
2011 mandated by the section C.1.1 "Register
2012 Names" in the SPARC spec. However, we
2013 decided to remove this restriction as a) it
2014 introduces problems when new V9 asr registers
2015 are introduced, b) the Solaris assembler
2016 doesn't implement this restriction and c) the
2017 restriction will go away in future revisions
2018 of the Oracle SPARC Architecture. */
2020 if (num
< 0 || 31 < num
)
2022 error_message
= _(": asr number must be between 0 and 31");
2026 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2031 error_message
= _(": expecting %asrN");
2038 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2042 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2048 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2053 if (s
[0] == '0' && s
[1] == 'x')
2056 while (ISXDIGIT (*s
))
2059 num
|= hex_value (*s
);
2065 while (ISDIGIT (*s
))
2067 num
= num
* 10 + *s
- '0';
2071 if (num
< 0 || num
> 31)
2073 error_message
= _(": crypto immediate must be between 0 and 31");
2077 opcode
|= RS3 (num
);
2082 error_message
= _(": expecting crypto immediate");
2087 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2088 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2089 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2091 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2092 /* These fields are unsigned, but for upward compatibility,
2093 allow negative values as well. */
2097 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2098 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2099 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2101 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2102 /* These fields are unsigned, but for upward compatibility,
2103 allow negative values as well. */
2107 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2112 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2117 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2122 if (*s
== 'p' && s
[1] == 'n')
2130 if (*s
== 'p' && s
[1] == 't')
2142 if ((strncmp (s
, "%icc", 4) == 0)
2143 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2155 if ((strncmp (s
, "%xcc", 4) == 0)
2156 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2168 if (strncmp (s
, "%fcc0", 5) == 0)
2180 if (strncmp (s
, "%fcc1", 5) == 0)
2192 if (strncmp (s
, "%fcc2", 5) == 0)
2204 if (strncmp (s
, "%fcc3", 5) == 0)
2212 if (strncmp (s
, "%pc", 3) == 0)
2220 if (strncmp (s
, "%tick", 5) == 0)
2227 case '\0': /* End of args. */
2228 if (s
[0] == ',' && s
[1] == '%')
2232 const struct perc_entry
*p
;
2234 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2235 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2236 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2238 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2241 if (s
[p
->len
+ 2] != '(')
2243 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2244 return special_case
;
2247 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2248 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2250 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2252 return special_case
;
2255 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2256 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2257 || the_insn
.exp
.X_add_number
!= 0
2258 || the_insn
.exp
.X_add_symbol
2259 != symbol_find_or_make ("__tls_get_addr")))
2261 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2263 return special_case
;
2266 the_insn
.reloc
= p
->pop
->reloc
;
2267 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2270 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2273 else if (*s1
== ')')
2282 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2283 return special_case
;
2287 (void) get_expression (s
);
2307 case '[': /* These must match exactly. */
2315 case '#': /* Must be at least one digit. */
2318 while (ISDIGIT (*s
))
2326 case 'C': /* Coprocessor state register. */
2327 if (strncmp (s
, "%csr", 4) == 0)
2334 case 'b': /* Next operand is a coprocessor register. */
2337 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2342 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2356 opcode
|= mask
<< 14;
2364 opcode
|= mask
<< 25;
2370 case 'r': /* next operand must be a register */
2380 case 'f': /* frame pointer */
2388 case 'g': /* global register */
2397 case 'i': /* in register */
2401 mask
= c
- '0' + 24;
2406 case 'l': /* local register */
2410 mask
= (c
- '0' + 16);
2415 case 'o': /* out register */
2419 mask
= (c
- '0' + 8);
2424 case 's': /* stack pointer */
2432 case 'r': /* any register */
2433 if (!ISDIGIT ((c
= *s
++)))
2450 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2466 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2467 && no_undeclared_regs
&& ! globals
[mask
])
2468 as_bad (_("detected global register use not covered by .register pseudo-op"));
2470 /* Got the register, now figure out where
2471 it goes in the opcode. */
2475 opcode
|= mask
<< 14;
2483 opcode
|= mask
<< 25;
2487 opcode
|= (mask
<< 25) | (mask
<< 14);
2491 opcode
|= (mask
<< 25) | (mask
<< 0);
2497 case 'e': /* next operand is a floating point register */
2520 && ((format
= *s
) == 'f'
2525 for (mask
= 0; ISDIGIT (*s
); ++s
)
2527 mask
= 10 * mask
+ (*s
- '0');
2528 } /* read the number */
2538 /* register must be even numbered */
2548 /* register must be multiple of 4 */
2557 /* register must be multiple of 8 */
2561 if (*args
== '\'' && mask
< 48)
2563 /* register must be higher or equal than %f48 */
2569 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2570 error_message
= _(": There are only 64 f registers; [0-63]");
2572 error_message
= _(": There are only 32 f registers; [0-31]");
2575 else if (mask
>= 32)
2577 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2579 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2582 = _(": There are only 32 single precision f registers; [0-31]");
2586 mask
-= 31; /* wrap high bit */
2590 error_message
= _(": There are only 32 f registers; [0-31]");
2598 } /* if not an 'f' register. */
2600 if (*args
== '}' && mask
!= RS2 (opcode
))
2603 = _(": Instruction requires frs2 and frsd must be the same register");
2613 opcode
|= RS1 (mask
);
2620 opcode
|= RS2 (mask
);
2624 opcode
|= RS2 (mask
& 0xe);
2629 opcode
|= RS3 (mask
);
2637 opcode
|= RD (mask
);
2646 if (strncmp (s
, "%fsr", 4) == 0)
2654 if (strncmp (s
, "%efsr", 5) == 0)
2661 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2662 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2665 case 'l': /* 22 bit PC relative immediate */
2666 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2670 case 'L': /* 30 bit immediate */
2671 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2676 case 'n': /* 22 bit immediate */
2677 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2680 case 'i': /* 13 bit immediate */
2681 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2691 const char *op_arg
= NULL
;
2692 static expressionS op_exp
;
2693 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2695 /* Check for %hi, etc. */
2698 const struct perc_entry
*p
;
2700 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2701 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2702 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2704 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2707 if (s
[p
->len
+ 1] != '(')
2709 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2710 return special_case
;
2714 the_insn
.reloc
= p
->pop
->reloc
;
2716 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2719 /* Note that if the get_expression() fails, we will still
2720 have created U entries in the symbol table for the
2721 'symbols' in the input string. Try not to create U
2722 symbols for registers, etc. */
2724 /* This stuff checks to see if the expression ends in
2725 +%reg. If it does, it removes the register from
2726 the expression, and re-sets 's' to point to the
2733 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2736 else if (*s1
== ')')
2745 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2746 return special_case
;
2750 (void) get_expression (s
);
2754 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2755 return special_case
;
2758 if (*s
== ',' || *s
== ']' || !*s
)
2760 if (*s
!= '+' && *s
!= '-')
2762 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2763 return special_case
;
2767 op_exp
= the_insn
.exp
;
2768 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2771 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2774 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2776 if (s1
[-2] == '%' && s1
[-3] == '+')
2778 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2780 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2787 if (op_arg
&& s1
== s
+ 1)
2788 the_insn
.exp
.X_op
= O_absent
;
2790 (void) get_expression (s
);
2802 (void) get_expression (s
);
2810 the_insn
.exp2
= the_insn
.exp
;
2811 the_insn
.exp
= op_exp
;
2812 if (the_insn
.exp2
.X_op
== O_absent
)
2813 the_insn
.exp2
.X_op
= O_illegal
;
2814 else if (the_insn
.exp
.X_op
== O_absent
)
2816 the_insn
.exp
= the_insn
.exp2
;
2817 the_insn
.exp2
.X_op
= O_illegal
;
2819 else if (the_insn
.exp
.X_op
== O_constant
)
2821 valueT val
= the_insn
.exp
.X_add_number
;
2822 switch (the_insn
.reloc
)
2827 case BFD_RELOC_SPARC_HH22
:
2828 val
= BSR (val
, 32);
2831 case BFD_RELOC_SPARC_LM22
:
2832 case BFD_RELOC_HI22
:
2833 val
= (val
>> 10) & 0x3fffff;
2836 case BFD_RELOC_SPARC_HM10
:
2837 val
= BSR (val
, 32);
2840 case BFD_RELOC_LO10
:
2844 case BFD_RELOC_SPARC_H34
:
2849 case BFD_RELOC_SPARC_H44
:
2854 case BFD_RELOC_SPARC_M44
:
2859 case BFD_RELOC_SPARC_L44
:
2863 case BFD_RELOC_SPARC_HIX22
:
2865 val
= (val
>> 10) & 0x3fffff;
2868 case BFD_RELOC_SPARC_LOX10
:
2869 val
= (val
& 0x3ff) | 0x1c00;
2872 the_insn
.exp
= the_insn
.exp2
;
2873 the_insn
.exp
.X_add_number
+= val
;
2874 the_insn
.exp2
.X_op
= O_illegal
;
2875 the_insn
.reloc
= old_reloc
;
2877 else if (the_insn
.exp2
.X_op
!= O_constant
)
2879 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2880 return special_case
;
2884 if (old_reloc
!= BFD_RELOC_SPARC13
2885 || the_insn
.reloc
!= BFD_RELOC_LO10
2886 || sparc_arch_size
!= 64
2889 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2890 return special_case
;
2892 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2896 /* Check for constants that don't require emitting a reloc. */
2897 if (the_insn
.exp
.X_op
== O_constant
2898 && the_insn
.exp
.X_add_symbol
== 0
2899 && the_insn
.exp
.X_op_symbol
== 0)
2901 /* For pc-relative call instructions, we reject
2902 constants to get better code. */
2904 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2905 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2907 error_message
= _(": PC-relative operand can't be a constant");
2911 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2912 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2914 error_message
= _(": TLS operand can't be a constant");
2918 /* Constants that won't fit are checked in md_apply_fix
2919 and bfd_install_relocation.
2920 ??? It would be preferable to install the constants
2921 into the insn here and save having to create a fixS
2922 for each one. There already exists code to handle
2923 all the various cases (e.g. in md_apply_fix and
2924 bfd_install_relocation) so duplicating all that code
2925 here isn't right. */
2927 /* This is a special case to handle cbcond instructions
2928 properly, which can need two relocations. The first
2929 one is for the 5-bit immediate field and the latter
2930 is going to be for the WDISP10 branch part. We
2931 handle the R_SPARC_5 immediate directly here so that
2932 we don't need to add support for multiple relocations
2933 in one instruction just yet. */
2934 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
2935 && ((insn
->match
& OP(0x3)) == 0))
2937 valueT val
= the_insn
.exp
.X_add_number
;
2939 the_insn
.reloc
= BFD_RELOC_NONE
;
2940 if (! in_bitfield_range (val
, 0x1f))
2942 error_message
= _(": Immediate value in cbcond is out of range.");
2945 opcode
|= val
& 0x1f;
2966 if (! parse_sparc_asi (&s
, &sasi
))
2968 error_message
= _(": invalid ASI name");
2975 if (! parse_const_expr_arg (&s
, &asi
))
2977 error_message
= _(": invalid ASI expression");
2980 if (asi
< 0 || asi
> 255)
2982 error_message
= _(": invalid ASI number");
2986 opcode
|= ASI (asi
);
2988 } /* Alternate space. */
2991 if (strncmp (s
, "%psr", 4) == 0)
2998 case 'q': /* Floating point queue. */
2999 if (strncmp (s
, "%fq", 3) == 0)
3006 case 'Q': /* Coprocessor queue. */
3007 if (strncmp (s
, "%cq", 3) == 0)
3015 if (strcmp (str
, "set") == 0
3016 || strcmp (str
, "setuw") == 0)
3018 special_case
= SPECIAL_CASE_SET
;
3021 else if (strcmp (str
, "setsw") == 0)
3023 special_case
= SPECIAL_CASE_SETSW
;
3026 else if (strcmp (str
, "setx") == 0)
3028 special_case
= SPECIAL_CASE_SETX
;
3031 else if (strncmp (str
, "fdiv", 4) == 0)
3033 special_case
= SPECIAL_CASE_FDIV
;
3039 if (strncmp (s
, "%asi", 4) != 0)
3045 if (strncmp (s
, "%fprs", 5) != 0)
3051 if (strncmp (s
, "%mcdper",7) != 0)
3057 if (strncmp (s
, "%entropy", 8) != 0)
3063 if (strncmp (s
, "%ccr", 4) != 0)
3069 if (strncmp (s
, "%tbr", 4) != 0)
3075 if (strncmp (s
, "%wim", 4) != 0)
3084 /* Parse a 2-bit immediate. */
3085 if (! parse_const_expr_arg (&s
, &imm2
))
3087 error_message
= _(": non-immdiate imm2 operand");
3090 if ((imm2
& ~0x3) != 0)
3092 error_message
= _(": imm2 immediate operand out of range (0-3)");
3096 opcode
|= ((imm2
& 0x2) << 3) | (imm2
& 0x1);
3102 char *push
= input_line_pointer
;
3105 input_line_pointer
= s
;
3107 if (e
.X_op
== O_constant
)
3109 int n
= e
.X_add_number
;
3110 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3111 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3113 opcode
|= e
.X_add_number
<< 5;
3116 as_bad (_("non-immediate OPF operand, ignored"));
3117 s
= input_line_pointer
;
3118 input_line_pointer
= push
;
3123 if (strncmp (s
, "%y", 2) != 0)
3131 /* Parse a sparclet cpreg. */
3133 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3135 error_message
= _(": invalid cpreg name");
3138 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3143 as_fatal (_("failed sanity check."));
3144 } /* switch on arg code. */
3146 /* Break out of for() loop. */
3148 } /* For each arg that we expect. */
3153 /* Args don't match. */
3154 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3155 && (insn
->name
== insn
[1].name
3156 || !strcmp (insn
->name
, insn
[1].name
)))
3164 as_bad (_("Illegal operands%s"), error_message
);
3165 return special_case
;
3170 /* We have a match. Now see if the architecture is OK. */
3171 /* String to use in case of architecture warning. */
3172 const char *msg_str
= str
;
3173 int needed_arch_mask
= insn
->architecture
;
3175 /* Include the ASI architecture needed as well */
3176 if (sasi
&& needed_arch_mask
> sasi
->architecture
)
3178 needed_arch_mask
= sasi
->architecture
;
3179 msg_str
= sasi
->name
;
3183 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3187 hwcap_seen
|= hwcaps
;
3192 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3193 if (! needed_arch_mask
)
3195 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3198 if (needed_arch_mask
3199 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3202 /* Can we bump up the architecture? */
3203 else if (needed_arch_mask
3204 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3206 enum sparc_opcode_arch_val needed_architecture
=
3207 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3208 & needed_arch_mask
);
3210 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3212 && needed_architecture
> warn_after_architecture
)
3214 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3215 sparc_opcode_archs
[current_architecture
].name
,
3216 sparc_opcode_archs
[needed_architecture
].name
,
3218 warn_after_architecture
= needed_architecture
;
3220 current_architecture
= needed_architecture
;
3224 | (((bfd_uint64_t
) sparc_opcode_archs
[current_architecture
].hwcaps2
) << 32)
3225 | sparc_opcode_archs
[current_architecture
].hwcaps
);
3228 /* ??? This seems to be a bit fragile. What if the next entry in
3229 the opcode table is the one we want and it is supported?
3230 It is possible to arrange the table today so that this can't
3231 happen but what about tomorrow? */
3234 int arch
, printed_one_p
= 0;
3236 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3238 /* Create a list of the architectures that support the insn. */
3239 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3241 arch
= sparc_ffs (needed_arch_mask
);
3242 while ((1 << arch
) <= needed_arch_mask
)
3244 if ((1 << arch
) & needed_arch_mask
)
3248 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3255 as_bad (_("Architecture mismatch on \"%s %s\"."), str
, argsStart
);
3256 as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
3258 sparc_opcode_archs
[max_architecture
].name
);
3259 return special_case
;
3262 /* Make sure the hwcaps used by the instruction are
3263 currently enabled. */
3264 if (hwcaps
& ~hwcap_allowed
)
3266 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3268 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3270 return special_case
;
3272 } /* If no match. */
3275 } /* Forever looking for a match. */
3277 the_insn
.opcode
= opcode
;
3278 return special_case
;
3282 skip_over_keyword (char *q
)
3284 for (q
= q
+ (*q
== '#' || *q
== '%');
3285 ISALNUM (*q
) || *q
== '_';
3292 parse_sparc_asi (char **input_pointer_p
, const sparc_asi
**value_p
)
3294 const sparc_asi
*value
;
3297 p
= *input_pointer_p
;
3298 q
= skip_over_keyword(p
);
3301 value
= sparc_encode_asi (p
);
3306 *input_pointer_p
= q
;
3310 /* Parse an argument that can be expressed as a keyword.
3311 (eg: #StoreStore or %ccfr).
3312 The result is a boolean indicating success.
3313 If successful, INPUT_POINTER is updated. */
3316 parse_keyword_arg (int (*lookup_fn
) (const char *),
3317 char **input_pointerP
,
3323 p
= *input_pointerP
;
3324 q
= skip_over_keyword(p
);
3327 value
= (*lookup_fn
) (p
);
3332 *input_pointerP
= q
;
3336 /* Parse an argument that is a constant expression.
3337 The result is a boolean indicating success. */
3340 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3342 char *save
= input_line_pointer
;
3345 input_line_pointer
= *input_pointerP
;
3346 /* The next expression may be something other than a constant
3347 (say if we're not processing the right variant of the insn).
3348 Don't call expression unless we're sure it will succeed as it will
3349 signal an error (which we want to defer until later). */
3350 /* FIXME: It might be better to define md_operand and have it recognize
3351 things like %asi, etc. but continuing that route through to the end
3352 is a lot of work. */
3353 if (*input_line_pointer
== '%')
3355 input_line_pointer
= save
;
3359 *input_pointerP
= input_line_pointer
;
3360 input_line_pointer
= save
;
3361 if (exp
.X_op
!= O_constant
)
3363 *valueP
= exp
.X_add_number
;
3367 /* Subroutine of sparc_ip to parse an expression. */
3370 get_expression (char *str
)
3375 save_in
= input_line_pointer
;
3376 input_line_pointer
= str
;
3377 seg
= expression (&the_insn
.exp
);
3378 if (seg
!= absolute_section
3379 && seg
!= text_section
3380 && seg
!= data_section
3381 && seg
!= bss_section
3382 && seg
!= undefined_section
)
3384 the_insn
.error
= _("bad segment");
3385 expr_end
= input_line_pointer
;
3386 input_line_pointer
= save_in
;
3389 expr_end
= input_line_pointer
;
3390 input_line_pointer
= save_in
;
3394 /* Subroutine of md_assemble to output one insn. */
3397 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3399 char *toP
= frag_more (4);
3401 /* Put out the opcode. */
3402 if (INSN_BIG_ENDIAN
)
3403 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3405 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3407 /* Put out the symbol-dependent stuff. */
3408 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3410 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3411 (toP
- frag_now
->fr_literal
), /* Where. */
3416 /* Turn off overflow checking in fixup_segment. We'll do our
3417 own overflow checking in md_apply_fix. This is necessary because
3418 the insn size is 4 and fixup_segment will signal an overflow for
3419 large 8 byte quantities. */
3420 fixP
->fx_no_overflow
= 1;
3421 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3422 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3426 last_opcode
= theinsn
->opcode
;
3428 dwarf2_emit_insn (4);
3432 md_atof (int type
, char *litP
, int *sizeP
)
3434 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3437 /* Write a value out to the object file, using the appropriate
3441 md_number_to_chars (char *buf
, valueT val
, int n
)
3443 if (target_big_endian
)
3444 number_to_chars_bigendian (buf
, val
, n
);
3445 else if (target_little_endian_data
3446 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3447 /* Output debug words, which are not in allocated sections, as big
3449 number_to_chars_bigendian (buf
, val
, n
);
3450 else if (target_little_endian_data
|| ! target_big_endian
)
3451 number_to_chars_littleendian (buf
, val
, n
);
3454 /* Apply a fixS to the frags, now that we know the value it ought to
3458 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3460 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3461 offsetT val
= * (offsetT
*) valP
;
3464 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3466 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3468 /* SPARC ELF relocations don't use an addend in the data field. */
3469 if (fixP
->fx_addsy
!= NULL
)
3471 switch (fixP
->fx_r_type
)
3473 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3474 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3475 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3476 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3477 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3478 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3479 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3480 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3481 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3482 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3483 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3484 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3485 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3486 case BFD_RELOC_SPARC_TLS_IE_LD
:
3487 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3488 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3489 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3490 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3491 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3492 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3493 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3494 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3495 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3496 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3497 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3506 /* This is a hack. There should be a better way to
3507 handle this. Probably in terms of howto fields, once
3508 we can look at these fixups in terms of howtos. */
3509 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3510 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3512 /* If this is a data relocation, just output VAL. */
3514 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3516 md_number_to_chars (buf
, val
, 1);
3518 else if (fixP
->fx_r_type
== BFD_RELOC_16
3519 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3521 md_number_to_chars (buf
, val
, 2);
3523 else if (fixP
->fx_r_type
== BFD_RELOC_32
3524 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3525 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3527 md_number_to_chars (buf
, val
, 4);
3529 else if (fixP
->fx_r_type
== BFD_RELOC_64
3530 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3532 md_number_to_chars (buf
, val
, 8);
3534 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3535 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3542 /* It's a relocation against an instruction. */
3544 if (INSN_BIG_ENDIAN
)
3545 insn
= bfd_getb32 ((unsigned char *) buf
);
3547 insn
= bfd_getl32 ((unsigned char *) buf
);
3549 switch (fixP
->fx_r_type
)
3551 case BFD_RELOC_32_PCREL_S2
:
3553 /* FIXME: This increment-by-one deserves a comment of why it's
3555 if (! sparc_pic_code
3556 || fixP
->fx_addsy
== NULL
3557 || symbol_section_p (fixP
->fx_addsy
))
3560 insn
|= val
& 0x3fffffff;
3562 /* See if we have a delay slot. In that case we attempt to
3563 optimize several cases transforming CALL instructions
3564 into branches. But we can only do that if the relocation
3565 can be completely resolved here, i.e. if no undefined
3566 symbol is associated with it. */
3567 if (sparc_relax
&& fixP
->fx_addsy
== NULL
3568 && fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3572 #define XCC (2 << 20)
3573 #define COND(x) (((x)&0xf)<<25)
3574 #define CONDA COND(0x8)
3575 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3576 #define INSN_BA (F2(0,2) | CONDA)
3577 #define INSN_OR F3(2, 0x2, 0)
3578 #define INSN_NOP F2(0,4)
3582 /* If the instruction is a call with either:
3584 arithmetic instruction with rd == %o7
3585 where rs1 != %o7 and rs2 if it is register != %o7
3586 then we can optimize if the call destination is near
3587 by changing the call into a branch always. */
3588 if (INSN_BIG_ENDIAN
)
3589 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3591 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3592 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3594 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3595 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3596 || ((delay
& RD (~0)) != RD (O7
))))
3598 if ((delay
& RS1 (~0)) == RS1 (O7
)
3599 || ((delay
& F3I (~0)) == 0
3600 && (delay
& RS2 (~0)) == RS2 (O7
)))
3602 /* Ensure the branch will fit into simm22. */
3603 if ((val
& 0x3fe00000)
3604 && (val
& 0x3fe00000) != 0x3fe00000)
3606 /* Check if the arch is v9 and branch will fit
3608 if (((val
& 0x3c0000) == 0
3609 || (val
& 0x3c0000) == 0x3c0000)
3610 && (sparc_arch_size
== 64
3611 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3613 insn
= INSN_BPA
| (val
& 0x7ffff);
3616 insn
= INSN_BA
| (val
& 0x3fffff);
3617 if (fixP
->fx_where
>= 4
3618 && ((delay
& (0xffffffff ^ RS1 (~0)))
3619 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3624 if (INSN_BIG_ENDIAN
)
3625 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3627 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3628 if ((setter
& (0xffffffff ^ RD (~0)))
3629 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3636 If call foo was replaced with ba, replace
3637 or %rN, %g0, %o7 with nop. */
3638 reg
= (delay
& RS1 (~0)) >> 14;
3639 if (reg
!= ((setter
& RD (~0)) >> 25)
3640 || reg
== G0
|| reg
== O7
)
3643 if (INSN_BIG_ENDIAN
)
3644 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3646 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3651 case BFD_RELOC_SPARC_11
:
3652 if (! in_signed_range (val
, 0x7ff))
3653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3654 _("relocation overflow"));
3655 insn
|= val
& 0x7ff;
3658 case BFD_RELOC_SPARC_10
:
3659 if (! in_signed_range (val
, 0x3ff))
3660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3661 _("relocation overflow"));
3662 insn
|= val
& 0x3ff;
3665 case BFD_RELOC_SPARC_7
:
3666 if (! in_bitfield_range (val
, 0x7f))
3667 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3668 _("relocation overflow"));
3672 case BFD_RELOC_SPARC_6
:
3673 if (! in_bitfield_range (val
, 0x3f))
3674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3675 _("relocation overflow"));
3679 case BFD_RELOC_SPARC_5
:
3680 if (! in_bitfield_range (val
, 0x1f))
3681 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3682 _("relocation overflow"));
3686 case BFD_RELOC_SPARC_WDISP10
:
3689 || val
<= -(offsetT
) 0x808)
3690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3691 _("relocation overflow"));
3692 /* FIXME: The +1 deserves a comment. */
3693 val
= (val
>> 2) + 1;
3694 insn
|= ((val
& 0x300) << 11)
3695 | ((val
& 0xff) << 5);
3698 case BFD_RELOC_SPARC_WDISP16
:
3701 || val
<= -(offsetT
) 0x20008)
3702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3703 _("relocation overflow"));
3704 /* FIXME: The +1 deserves a comment. */
3705 val
= (val
>> 2) + 1;
3706 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3709 case BFD_RELOC_SPARC_WDISP19
:
3712 || val
<= -(offsetT
) 0x100008)
3713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3714 _("relocation overflow"));
3715 /* FIXME: The +1 deserves a comment. */
3716 val
= (val
>> 2) + 1;
3717 insn
|= val
& 0x7ffff;
3720 case BFD_RELOC_SPARC_HH22
:
3721 val
= BSR (val
, 32);
3724 case BFD_RELOC_SPARC_LM22
:
3725 case BFD_RELOC_HI22
:
3726 if (!fixP
->fx_addsy
)
3727 insn
|= (val
>> 10) & 0x3fffff;
3729 /* FIXME: Need comment explaining why we do this. */
3733 case BFD_RELOC_SPARC22
:
3734 if (val
& ~0x003fffff)
3735 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3736 _("relocation overflow"));
3737 insn
|= (val
& 0x3fffff);
3740 case BFD_RELOC_SPARC_HM10
:
3741 val
= BSR (val
, 32);
3744 case BFD_RELOC_LO10
:
3745 if (!fixP
->fx_addsy
)
3746 insn
|= val
& 0x3ff;
3748 /* FIXME: Need comment explaining why we do this. */
3752 case BFD_RELOC_SPARC_OLO10
:
3754 val
+= fixP
->tc_fix_data
;
3757 case BFD_RELOC_SPARC13
:
3758 if (! in_signed_range (val
, 0x1fff))
3759 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3760 _("relocation overflow"));
3761 insn
|= val
& 0x1fff;
3764 case BFD_RELOC_SPARC_WDISP22
:
3765 val
= (val
>> 2) + 1;
3767 case BFD_RELOC_SPARC_BASE22
:
3768 insn
|= val
& 0x3fffff;
3771 case BFD_RELOC_SPARC_H34
:
3772 if (!fixP
->fx_addsy
)
3776 insn
|= tval
& 0x3fffff;
3780 case BFD_RELOC_SPARC_H44
:
3781 if (!fixP
->fx_addsy
)
3785 insn
|= tval
& 0x3fffff;
3789 case BFD_RELOC_SPARC_M44
:
3790 if (!fixP
->fx_addsy
)
3791 insn
|= (val
>> 12) & 0x3ff;
3794 case BFD_RELOC_SPARC_L44
:
3795 if (!fixP
->fx_addsy
)
3796 insn
|= val
& 0xfff;
3799 case BFD_RELOC_SPARC_HIX22
:
3800 if (!fixP
->fx_addsy
)
3802 val
^= ~(offsetT
) 0;
3803 insn
|= (val
>> 10) & 0x3fffff;
3807 case BFD_RELOC_SPARC_LOX10
:
3808 if (!fixP
->fx_addsy
)
3809 insn
|= 0x1c00 | (val
& 0x3ff);
3812 case BFD_RELOC_NONE
:
3814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3815 _("bad or unhandled relocation type: 0x%02x"),
3820 if (INSN_BIG_ENDIAN
)
3821 bfd_putb32 (insn
, (unsigned char *) buf
);
3823 bfd_putl32 (insn
, (unsigned char *) buf
);
3826 /* Are we finished with this relocation now? */
3827 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3831 /* Translate internal representation of relocation info to BFD target
3835 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3837 static arelent
*relocs
[3];
3839 bfd_reloc_code_real_type code
;
3841 relocs
[0] = reloc
= XNEW (arelent
);
3844 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3845 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3846 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3848 switch (fixp
->fx_r_type
)
3856 switch (fixp
->fx_size
)
3859 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3860 _("can not do %d byte pc-relative relocation"),
3862 code
= fixp
->fx_r_type
;
3865 case 1: code
= BFD_RELOC_8_PCREL
; break;
3866 case 2: code
= BFD_RELOC_16_PCREL
; break;
3867 case 4: code
= BFD_RELOC_32_PCREL
; break;
3869 case 8: code
= BFD_RELOC_64_PCREL
; break;
3873 fixp
->fx_addnumber
= fixp
->fx_offset
;
3877 case BFD_RELOC_HI22
:
3878 case BFD_RELOC_LO10
:
3879 case BFD_RELOC_32_PCREL_S2
:
3880 case BFD_RELOC_SPARC13
:
3881 case BFD_RELOC_SPARC22
:
3882 case BFD_RELOC_SPARC_PC22
:
3883 case BFD_RELOC_SPARC_PC10
:
3884 case BFD_RELOC_SPARC_BASE13
:
3885 case BFD_RELOC_SPARC_WDISP10
:
3886 case BFD_RELOC_SPARC_WDISP16
:
3887 case BFD_RELOC_SPARC_WDISP19
:
3888 case BFD_RELOC_SPARC_WDISP22
:
3889 case BFD_RELOC_SPARC_5
:
3890 case BFD_RELOC_SPARC_6
:
3891 case BFD_RELOC_SPARC_7
:
3892 case BFD_RELOC_SPARC_10
:
3893 case BFD_RELOC_SPARC_11
:
3894 case BFD_RELOC_SPARC_HH22
:
3895 case BFD_RELOC_SPARC_HM10
:
3896 case BFD_RELOC_SPARC_LM22
:
3897 case BFD_RELOC_SPARC_PC_HH22
:
3898 case BFD_RELOC_SPARC_PC_HM10
:
3899 case BFD_RELOC_SPARC_PC_LM22
:
3900 case BFD_RELOC_SPARC_H34
:
3901 case BFD_RELOC_SPARC_H44
:
3902 case BFD_RELOC_SPARC_M44
:
3903 case BFD_RELOC_SPARC_L44
:
3904 case BFD_RELOC_SPARC_HIX22
:
3905 case BFD_RELOC_SPARC_LOX10
:
3906 case BFD_RELOC_SPARC_REV32
:
3907 case BFD_RELOC_SPARC_OLO10
:
3908 case BFD_RELOC_SPARC_UA16
:
3909 case BFD_RELOC_SPARC_UA32
:
3910 case BFD_RELOC_SPARC_UA64
:
3911 case BFD_RELOC_8_PCREL
:
3912 case BFD_RELOC_16_PCREL
:
3913 case BFD_RELOC_32_PCREL
:
3914 case BFD_RELOC_64_PCREL
:
3915 case BFD_RELOC_SPARC_PLT32
:
3916 case BFD_RELOC_SPARC_PLT64
:
3917 case BFD_RELOC_VTABLE_ENTRY
:
3918 case BFD_RELOC_VTABLE_INHERIT
:
3919 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3920 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3921 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3922 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3923 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3924 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3925 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3926 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3927 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3928 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3929 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3930 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3931 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3932 case BFD_RELOC_SPARC_TLS_IE_LD
:
3933 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3934 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3935 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3936 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3937 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3938 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3939 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3940 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3941 case BFD_RELOC_SPARC_GOTDATA_OP
:
3942 code
= fixp
->fx_r_type
;
3949 /* If we are generating PIC code, we need to generate a different
3952 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3954 #define GOTT_BASE "__GOTT_BASE__"
3955 #define GOTT_INDEX "__GOTT_INDEX__"
3958 /* This code must be parallel to tc_fix_adjustable. */
3964 case BFD_RELOC_32_PCREL_S2
:
3965 if (generic_force_reloc (fixp
))
3966 code
= BFD_RELOC_SPARC_WPLT30
;
3968 case BFD_RELOC_HI22
:
3969 code
= BFD_RELOC_SPARC_GOT22
;
3970 if (fixp
->fx_addsy
!= NULL
)
3972 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3973 code
= BFD_RELOC_SPARC_PC22
;
3975 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3976 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3977 code
= BFD_RELOC_HI22
; /* Unchanged. */
3981 case BFD_RELOC_LO10
:
3982 code
= BFD_RELOC_SPARC_GOT10
;
3983 if (fixp
->fx_addsy
!= NULL
)
3985 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3986 code
= BFD_RELOC_SPARC_PC10
;
3988 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3989 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3990 code
= BFD_RELOC_LO10
; /* Unchanged. */
3994 case BFD_RELOC_SPARC13
:
3995 code
= BFD_RELOC_SPARC_GOT13
;
4002 /* Nothing is aligned in DWARF debugging sections. */
4003 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
4006 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
4007 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
4008 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
4012 if (code
== BFD_RELOC_SPARC_OLO10
)
4013 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
4015 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4016 if (reloc
->howto
== 0)
4018 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4019 _("internal error: can't export reloc type %d (`%s')"),
4020 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
4026 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
4027 if (code
!= BFD_RELOC_32_PCREL_S2
4028 && code
!= BFD_RELOC_SPARC_WDISP22
4029 && code
!= BFD_RELOC_SPARC_WDISP16
4030 && code
!= BFD_RELOC_SPARC_WDISP19
4031 && code
!= BFD_RELOC_SPARC_WDISP10
4032 && code
!= BFD_RELOC_SPARC_WPLT30
4033 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
4034 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
4035 reloc
->addend
= fixp
->fx_addnumber
;
4036 else if (symbol_section_p (fixp
->fx_addsy
))
4037 reloc
->addend
= (section
->vma
4038 + fixp
->fx_addnumber
4039 + md_pcrel_from (fixp
));
4041 reloc
->addend
= fixp
->fx_offset
;
4043 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4044 on the same location. */
4045 if (code
== BFD_RELOC_SPARC_OLO10
)
4047 relocs
[1] = reloc
= XNEW (arelent
);
4050 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4052 = symbol_get_bfdsym (section_symbol (absolute_section
));
4053 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4054 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4055 reloc
->addend
= fixp
->tc_fix_data
;
4061 /* We have no need to default values of symbols. */
4064 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4069 /* Round up a section size to the appropriate boundary. */
4072 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4077 /* Exactly what point is a PC-relative offset relative TO?
4078 On the sparc, they're relative to the address of the offset, plus
4079 its size. This gets us to the following instruction.
4080 (??? Is this right? FIXME-SOON) */
4082 md_pcrel_from (fixS
*fixP
)
4086 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4087 if (! sparc_pic_code
4088 || fixP
->fx_addsy
== NULL
4089 || symbol_section_p (fixP
->fx_addsy
))
4090 ret
+= fixP
->fx_size
;
4094 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4105 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4108 return (value
== 1) ? shift
: -1;
4111 /* Sort of like s_lcomm. */
4114 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4124 c
= get_symbol_name (&name
);
4125 p
= input_line_pointer
;
4127 SKIP_WHITESPACE_AFTER_NAME ();
4129 if (*input_line_pointer
!= ',')
4131 as_bad (_("Expected comma after name"));
4132 ignore_rest_of_line ();
4136 ++input_line_pointer
;
4138 if ((size
= get_absolute_expression ()) < 0)
4140 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4141 ignore_rest_of_line ();
4146 symbolP
= symbol_find_or_make (name
);
4149 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4150 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4152 as_bad (_("bad .reserve segment -- expected BSS segment"));
4156 if (input_line_pointer
[2] == '.')
4157 input_line_pointer
+= 7;
4159 input_line_pointer
+= 6;
4162 if (*input_line_pointer
== ',')
4164 ++input_line_pointer
;
4167 if (*input_line_pointer
== '\n')
4169 as_bad (_("missing alignment"));
4170 ignore_rest_of_line ();
4174 align
= (int) get_absolute_expression ();
4178 as_bad (_("negative alignment"));
4179 ignore_rest_of_line ();
4185 temp
= mylog2 (align
);
4188 as_bad (_("alignment not a power of 2"));
4189 ignore_rest_of_line ();
4196 record_alignment (bss_section
, align
);
4201 if (!S_IS_DEFINED (symbolP
))
4206 segT current_seg
= now_seg
;
4207 subsegT current_subseg
= now_subseg
;
4209 /* Switch to bss. */
4210 subseg_set (bss_section
, 1);
4214 frag_align (align
, 0, 0);
4216 /* Detach from old frag. */
4217 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4218 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4220 symbol_set_frag (symbolP
, frag_now
);
4221 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4222 (offsetT
) size
, (char *) 0);
4225 S_SET_SEGMENT (symbolP
, bss_section
);
4227 subseg_set (current_seg
, current_subseg
);
4229 S_SET_SIZE (symbolP
, size
);
4234 as_warn (_("Ignoring attempt to re-define symbol %s"),
4235 S_GET_NAME (symbolP
));
4238 demand_empty_rest_of_line ();
4242 s_common (int ignore ATTRIBUTE_UNUSED
)
4250 c
= get_symbol_name (&name
);
4251 /* Just after name is now '\0'. */
4252 p
= input_line_pointer
;
4254 SKIP_WHITESPACE_AFTER_NAME ();
4255 if (*input_line_pointer
!= ',')
4257 as_bad (_("Expected comma after symbol-name"));
4258 ignore_rest_of_line ();
4263 input_line_pointer
++;
4265 if ((temp
= get_absolute_expression ()) < 0)
4267 as_bad (_(".COMMon length (%lu) out of range ignored"),
4268 (unsigned long) temp
);
4269 ignore_rest_of_line ();
4274 symbolP
= symbol_find_or_make (name
);
4276 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4278 as_bad (_("Ignoring attempt to re-define symbol"));
4279 ignore_rest_of_line ();
4282 if (S_GET_VALUE (symbolP
) != 0)
4284 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4286 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4287 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4290 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4291 if (*input_line_pointer
!= ',')
4293 as_bad (_("Expected comma after common length"));
4294 ignore_rest_of_line ();
4297 input_line_pointer
++;
4299 if (*input_line_pointer
!= '"')
4301 temp
= get_absolute_expression ();
4305 as_bad (_("negative alignment"));
4306 ignore_rest_of_line ();
4310 if (symbol_get_obj (symbolP
)->local
)
4317 old_subsec
= now_subseg
;
4322 align
= mylog2 (temp
);
4326 as_bad (_("alignment not a power of 2"));
4327 ignore_rest_of_line ();
4331 record_alignment (bss_section
, align
);
4332 subseg_set (bss_section
, 0);
4334 frag_align (align
, 0, 0);
4335 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4336 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4337 symbol_set_frag (symbolP
, frag_now
);
4338 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4339 (offsetT
) size
, (char *) 0);
4341 S_SET_SEGMENT (symbolP
, bss_section
);
4342 S_CLEAR_EXTERNAL (symbolP
);
4343 S_SET_SIZE (symbolP
, size
);
4344 subseg_set (old_sec
, old_subsec
);
4349 S_SET_VALUE (symbolP
, (valueT
) size
);
4350 S_SET_ALIGN (symbolP
, temp
);
4351 S_SET_SIZE (symbolP
, size
);
4352 S_SET_EXTERNAL (symbolP
);
4353 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4358 input_line_pointer
++;
4359 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4360 if (*input_line_pointer
== '.')
4361 input_line_pointer
++;
4362 /* @@ Some say data, some say bss. */
4363 if (strncmp (input_line_pointer
, "bss\"", 4)
4364 && strncmp (input_line_pointer
, "data\"", 5))
4366 while (*--input_line_pointer
!= '"')
4368 input_line_pointer
--;
4369 goto bad_common_segment
;
4371 while (*input_line_pointer
++ != '"')
4373 goto allocate_common
;
4376 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4378 demand_empty_rest_of_line ();
4383 p
= input_line_pointer
;
4384 while (*p
&& *p
!= '\n')
4388 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4390 input_line_pointer
= p
;
4391 ignore_rest_of_line ();
4396 /* Handle the .empty pseudo-op. This suppresses the warnings about
4397 invalid delay slot usage. */
4400 s_empty (int ignore ATTRIBUTE_UNUSED
)
4402 /* The easy way to implement is to just forget about the last
4408 s_seg (int ignore ATTRIBUTE_UNUSED
)
4411 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4413 input_line_pointer
+= 6;
4417 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4419 input_line_pointer
+= 6;
4423 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4425 input_line_pointer
+= 7;
4429 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4431 input_line_pointer
+= 5;
4432 /* We only support 2 segments -- text and data -- for now, so
4433 things in the "bss segment" will have to go into data for now.
4434 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4435 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4438 as_bad (_("Unknown segment type"));
4439 demand_empty_rest_of_line ();
4445 subseg_set (data_section
, 1);
4446 demand_empty_rest_of_line ();
4450 s_proc (int ignore ATTRIBUTE_UNUSED
)
4452 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4454 ++input_line_pointer
;
4456 ++input_line_pointer
;
4459 /* This static variable is set by s_uacons to tell sparc_cons_align
4460 that the expression does not need to be aligned. */
4462 static int sparc_no_align_cons
= 0;
4464 /* This handles the unaligned space allocation pseudo-ops, such as
4465 .uaword. .uaword is just like .word, but the value does not need
4469 s_uacons (int bytes
)
4471 /* Tell sparc_cons_align not to align this value. */
4472 sparc_no_align_cons
= 1;
4474 sparc_no_align_cons
= 0;
4477 /* This handles the native word allocation pseudo-op .nword.
4478 For sparc_arch_size 32 it is equivalent to .word, for
4479 sparc_arch_size 64 it is equivalent to .xword. */
4482 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4484 cons (sparc_arch_size
== 32 ? 4 : 8);
4487 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4491 .register %g[2367],{#scratch|symbolname|#ignore}
4495 s_register (int ignore ATTRIBUTE_UNUSED
)
4502 if (input_line_pointer
[0] != '%'
4503 || input_line_pointer
[1] != 'g'
4504 || ((input_line_pointer
[2] & ~1) != '2'
4505 && (input_line_pointer
[2] & ~1) != '6')
4506 || input_line_pointer
[3] != ',')
4507 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4508 reg
= input_line_pointer
[2] - '0';
4509 input_line_pointer
+= 4;
4511 if (*input_line_pointer
== '#')
4513 ++input_line_pointer
;
4514 c
= get_symbol_name (®name
);
4515 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4516 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4517 if (regname
[0] == 'i')
4520 regname
= (char *) "";
4524 c
= get_symbol_name (®name
);
4527 if (sparc_arch_size
== 64)
4531 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4532 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4533 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4534 as_bad (_("redefinition of global register"));
4538 if (regname
== NULL
)
4539 globals
[reg
] = (symbolS
*) 1;
4544 if (symbol_find (regname
))
4545 as_bad (_("Register symbol %s already defined."),
4548 globals
[reg
] = symbol_make (regname
);
4549 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4551 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4552 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4553 flags
|= BSF_GLOBAL
;
4554 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4555 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4556 S_SET_ALIGN (globals
[reg
], reg
);
4557 S_SET_SIZE (globals
[reg
], 0);
4558 /* Although we actually want undefined_section here,
4559 we have to use absolute_section, because otherwise
4560 generic as code will make it a COM section.
4561 We fix this up in sparc_adjust_symtab. */
4562 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4563 S_SET_OTHER (globals
[reg
], 0);
4564 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4565 ->internal_elf_sym
.st_info
=
4566 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4567 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4568 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4573 (void) restore_line_pointer (c
);
4575 demand_empty_rest_of_line ();
4578 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4579 symbols which need it. */
4582 sparc_adjust_symtab (void)
4586 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4588 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4589 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4592 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4593 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4596 S_SET_SEGMENT (sym
, undefined_section
);
4600 /* If the --enforce-aligned-data option is used, we require .word,
4601 et. al., to be aligned correctly. We do it by setting up an
4602 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4603 no unexpected alignment was introduced.
4605 The SunOS and Solaris native assemblers enforce aligned data by
4606 default. We don't want to do that, because gcc can deliberately
4607 generate misaligned data if the packed attribute is used. Instead,
4608 we permit misaligned data by default, and permit the user to set an
4609 option to check for it. */
4612 sparc_cons_align (int nbytes
)
4616 /* Only do this if we are enforcing aligned data. */
4617 if (! enforce_aligned_data
)
4620 /* Don't align if this is an unaligned pseudo-op. */
4621 if (sparc_no_align_cons
)
4624 nalign
= mylog2 (nbytes
);
4628 gas_assert (nalign
> 0);
4630 if (now_seg
== absolute_section
)
4632 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4633 as_bad (_("misaligned data"));
4637 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4638 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4640 record_alignment (now_seg
, nalign
);
4643 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4646 sparc_handle_align (fragS
*fragp
)
4651 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4653 switch (fragp
->fr_type
)
4657 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4661 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4672 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4674 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4675 if (INSN_BIG_ENDIAN
)
4676 number_to_chars_bigendian (p
, wval
, 4);
4678 number_to_chars_littleendian (p
, wval
, 4);
4684 if (INSN_BIG_ENDIAN
)
4685 number_to_chars_bigendian (p
, 0x01000000, 4);
4687 number_to_chars_littleendian (p
, 0x01000000, 4);
4689 fragp
->fr_fix
+= fix
;
4698 /* Some special processing for a Sparc ELF file. */
4701 sparc_elf_final_processing (void)
4703 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4704 sort of BFD interface for this. */
4705 if (sparc_arch_size
== 64)
4707 switch (sparc_memory_model
)
4710 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4713 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4719 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4720 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4721 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4722 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4723 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4724 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4728 sparc_cons (expressionS
*exp
, int size
)
4731 const char *sparc_cons_special_reloc
= NULL
;
4734 save
= input_line_pointer
;
4735 if (input_line_pointer
[0] == '%'
4736 && input_line_pointer
[1] == 'r'
4737 && input_line_pointer
[2] == '_')
4739 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4741 input_line_pointer
+= 7;
4742 sparc_cons_special_reloc
= "disp";
4744 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4746 if (size
!= 4 && size
!= 8)
4747 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4750 input_line_pointer
+= 6;
4751 sparc_cons_special_reloc
= "plt";
4754 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4756 if (size
!= 4 && size
!= 8)
4757 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4760 input_line_pointer
+= 13;
4761 sparc_cons_special_reloc
= "tls_dtpoff";
4764 if (sparc_cons_special_reloc
)
4771 if (*input_line_pointer
!= '8')
4773 input_line_pointer
--;
4776 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4780 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4784 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4794 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4795 sparc_cons_special_reloc
, size
* 8, size
);
4799 input_line_pointer
+= 2;
4800 if (*input_line_pointer
!= '(')
4802 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4803 sparc_cons_special_reloc
, size
* 8);
4810 input_line_pointer
= save
;
4811 sparc_cons_special_reloc
= NULL
;
4816 char *end
= ++input_line_pointer
;
4819 while (! is_end_of_line
[(c
= *end
)])
4833 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4834 sparc_cons_special_reloc
, size
* 8);
4840 if (input_line_pointer
!= end
)
4842 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4843 sparc_cons_special_reloc
, size
* 8);
4847 input_line_pointer
++;
4849 c
= *input_line_pointer
;
4850 if (! is_end_of_line
[c
] && c
!= ',')
4851 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4852 sparc_cons_special_reloc
, size
* 8);
4858 if (sparc_cons_special_reloc
== NULL
)
4860 return sparc_cons_special_reloc
;
4863 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4864 reloc for a cons. We could use the definition there, except that
4865 we want to handle little endian relocs specially. */
4868 cons_fix_new_sparc (fragS
*frag
,
4870 unsigned int nbytes
,
4872 const char *sparc_cons_special_reloc
)
4874 bfd_reloc_code_real_type r
;
4876 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4877 (nbytes
== 2 ? BFD_RELOC_16
:
4878 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4880 if (target_little_endian_data
4882 && now_seg
->flags
& SEC_ALLOC
)
4883 r
= BFD_RELOC_SPARC_REV32
;
4886 /* The Solaris linker does not allow R_SPARC_UA64
4887 relocations for 32-bit executables. */
4888 if (!target_little_endian_data
4889 && sparc_arch_size
!= 64
4890 && r
== BFD_RELOC_64
)
4894 if (sparc_cons_special_reloc
)
4896 if (*sparc_cons_special_reloc
== 'd')
4899 case 1: r
= BFD_RELOC_8_PCREL
; break;
4900 case 2: r
= BFD_RELOC_16_PCREL
; break;
4901 case 4: r
= BFD_RELOC_32_PCREL
; break;
4902 case 8: r
= BFD_RELOC_64_PCREL
; break;
4905 else if (*sparc_cons_special_reloc
== 'p')
4908 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4909 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4914 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4915 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4918 else if (sparc_no_align_cons
4919 || /* PR 20803 - relocs in the .eh_frame section
4920 need to support unaligned access. */
4921 strcmp (now_seg
->name
, ".eh_frame") == 0)
4925 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4926 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4928 /* The Solaris linker does not allow R_SPARC_UA64
4929 relocations for 32-bit executables. */
4930 case 8: r
= sparc_arch_size
== 64 ?
4931 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
4933 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4939 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4943 sparc_cfi_frame_initial_instructions (void)
4945 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4949 sparc_regname_to_dw2regnum (char *regname
)
4959 case 'g': i
= 0; break;
4960 case 'o': i
= 1; break;
4961 case 'l': i
= 2; break;
4962 case 'i': i
= 3; break;
4963 default: i
= -1; break;
4967 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4969 return i
* 8 + regname
[1] - '0';
4971 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4973 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4975 if (regname
[0] == 'f' || regname
[0] == 'r')
4977 unsigned int regnum
;
4979 regnum
= strtoul (regname
+ 1, &q
, 10);
4980 if (q
== NULL
|| *q
)
4982 if (regnum
>= ((regname
[0] == 'f'
4983 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4986 if (regname
[0] == 'f')
4989 if (regnum
>= 64 && (regnum
& 1))
4998 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
5000 sparc_no_align_cons
= 1;
5001 emit_expr_with_reloc (exp
, nbytes
, "disp");
5002 sparc_no_align_cons
= 0;