1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989-2013 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static int hwcap_seen
;
84 static int hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax
;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data
;
106 extern int target_big_endian
;
108 static int target_little_endian_data
;
110 /* Symbols for global registers on v9. */
111 static symbolS
*globals
[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment
;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control
*op_hash
;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons
, 2},
162 {"4byte", s_uacons
, 4},
163 {"8byte", s_uacons
, 8},
164 {"register", s_register
, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars
[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars
[] = "#";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode
;
205 struct nlist
*nlistp
;
209 bfd_reloc_code_real_type reloc
;
212 struct sparc_it the_insn
, set_insn
;
214 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
222 v8plusa
, v9
, v9a
, v9b
, v9_64
};
224 static struct sparc_arch
{
227 enum sparc_arch_types arch_type
;
228 /* Default word size, as specified during configuration.
229 A value of zero means can't be used to specify default architecture. */
230 int default_arch_size
;
231 /* Allowable arg to -A? */
234 } sparc_arch_table
[] = {
235 { "v6", "v6", v6
, 0, 1, 0 },
236 { "v7", "v7", v7
, 0, 1, 0 },
237 { "v8", "v8", v8
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
238 { "v8a", "v8", v8
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
239 { "sparc", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
},
240 { "sparcvis", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
},
241 { "sparcvis2", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
},
242 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
},
243 { "sparcima", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_IMA
},
244 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
245 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
},
246 { "sparc4", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
247 { "leon", "leon", leon
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
248 { "sparclet", "sparclet", sparclet
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
249 { "sparclite", "sparclite", sparclite
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
250 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
251 { "v8plus", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
},
252 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
},
253 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
},
254 { "v8plusc", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
},
255 { "v8plusd", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
256 { "v8pluse", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
257 { "v8plusv", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_IMA
|HWCAP_ASI_CACHE_SPARING
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
258 { "v9", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
},
259 { "v9a", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
},
260 { "v9b", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
},
261 { "v9c", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
},
262 { "v9d", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
263 { "v9e", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
264 { "v9v", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_IMA
|HWCAP_ASI_CACHE_SPARING
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
265 /* This exists to allow configure.in/Makefile.in to pass one
266 value to specify both the default machine and default word size. */
267 { "v9-64", "v9", v9
, 64, 0, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
},
268 { NULL
, NULL
, v8
, 0, 0, 0 }
271 /* Variant of default_arch */
272 static enum sparc_arch_types default_arch_type
;
274 static struct sparc_arch
*
275 lookup_arch (char *name
)
277 struct sparc_arch
*sa
;
279 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
280 if (strcmp (sa
->name
, name
) == 0)
282 if (sa
->name
== NULL
)
287 /* Initialize the default opcode arch and word size from the default
288 architecture name. */
291 init_default_arch (void)
293 struct sparc_arch
*sa
= lookup_arch (default_arch
);
296 || sa
->default_arch_size
== 0)
297 as_fatal (_("Invalid default architecture, broken assembler."));
299 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
300 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
301 as_fatal (_("Bad opcode table, broken assembler."));
302 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
304 default_arch_type
= sa
->arch_type
;
307 /* Called by TARGET_FORMAT. */
310 sparc_target_format (void)
312 /* We don't get a chance to initialize anything before we're called,
313 so handle that now. */
314 if (! default_init_p
)
315 init_default_arch ();
319 return "a.out-sparc-netbsd";
322 if (target_big_endian
)
323 return "a.out-sunos-big";
324 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
325 return "a.out-sunos-big";
327 return "a.out-sparc-little";
329 return "a.out-sunos-big";
340 return "coff-sparc-lynx";
347 return "elf32-sparc-vxworks";
351 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
358 * Invocation line includes a switch not recognized by the base assembler.
359 * See if it's a processor-specific option. These are:
362 * Warn on architecture bumps. See also -A.
364 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
365 * Standard 32 bit architectures.
367 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
368 * This used to only mean 64 bits, but properly specifying it
369 * complicated gcc's ASM_SPECs, so now opcode selection is
370 * specified orthogonally to word size (except when specifying
371 * the default, but that is an internal implementation detail).
372 * -Av8plus, -Av8plusa, -Av8plusb
373 * Same as -Av9{,a,b}.
374 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
375 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
377 * -xarch=v9, -xarch=v9a, -xarch=v9b
378 * Same as -Av9{,a,b} -64, for compatibility with Sun's
381 * Select the architecture and possibly the file format.
382 * Instructions or features not supported by the selected
383 * architecture cause fatal errors.
385 * The default is to start at v6, and bump the architecture up
386 * whenever an instruction is seen at a higher level. In 32 bit
387 * environments, v9 is not bumped up to, the user must pass
390 * If -bump is specified, a warning is printing when bumping to
393 * If an architecture is specified, all instructions must match
394 * that architecture. Any higher level instructions are flagged
395 * as errors. Note that in the 32 bit environment specifying
396 * -Av8plus does not automatically create a v8plus object file, a
397 * v9 insn must be seen.
399 * If both an architecture and -bump are specified, the
400 * architecture starts at the specified level, but bumps are
401 * warnings. Note that we can't set `current_architecture' to
402 * the requested level in this case: in the 32 bit environment,
403 * we still must avoid creating v8plus object files unless v9
407 * Bumping between incompatible architectures is always an
408 * error. For example, from sparclite to v9.
412 const char *md_shortopts
= "A:K:VQ:sq";
415 const char *md_shortopts
= "A:k";
417 const char *md_shortopts
= "A:";
420 struct option md_longopts
[] = {
421 #define OPTION_BUMP (OPTION_MD_BASE)
422 {"bump", no_argument
, NULL
, OPTION_BUMP
},
423 #define OPTION_SPARC (OPTION_MD_BASE + 1)
424 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
425 #define OPTION_XARCH (OPTION_MD_BASE + 2)
426 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
428 #define OPTION_32 (OPTION_MD_BASE + 3)
429 {"32", no_argument
, NULL
, OPTION_32
},
430 #define OPTION_64 (OPTION_MD_BASE + 4)
431 {"64", no_argument
, NULL
, OPTION_64
},
432 #define OPTION_TSO (OPTION_MD_BASE + 5)
433 {"TSO", no_argument
, NULL
, OPTION_TSO
},
434 #define OPTION_PSO (OPTION_MD_BASE + 6)
435 {"PSO", no_argument
, NULL
, OPTION_PSO
},
436 #define OPTION_RMO (OPTION_MD_BASE + 7)
437 {"RMO", no_argument
, NULL
, OPTION_RMO
},
439 #ifdef SPARC_BIENDIAN
440 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
441 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
442 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
443 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
445 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
446 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
447 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
448 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
450 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
451 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
452 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
453 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
455 #define OPTION_RELAX (OPTION_MD_BASE + 14)
456 {"relax", no_argument
, NULL
, OPTION_RELAX
},
457 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
458 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
459 {NULL
, no_argument
, NULL
, 0}
462 size_t md_longopts_size
= sizeof (md_longopts
);
465 md_parse_option (int c
, char *arg
)
467 /* We don't get a chance to initialize anything before we're called,
468 so handle that now. */
469 if (! default_init_p
)
470 init_default_arch ();
476 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
481 if (!strncmp (arg
, "v9", 2))
482 md_parse_option (OPTION_64
, NULL
);
485 if (!strncmp (arg
, "v8", 2)
486 || !strncmp (arg
, "v7", 2)
487 || !strncmp (arg
, "v6", 2)
488 || !strcmp (arg
, "sparclet")
489 || !strcmp (arg
, "sparclite")
490 || !strcmp (arg
, "sparc86x"))
491 md_parse_option (OPTION_32
, NULL
);
498 struct sparc_arch
*sa
;
499 enum sparc_opcode_arch_val opcode_arch
;
501 sa
= lookup_arch (arg
);
503 || ! sa
->user_option_p
)
505 if (c
== OPTION_XARCH
)
506 as_bad (_("invalid architecture -xarch=%s"), arg
);
508 as_bad (_("invalid architecture -A%s"), arg
);
512 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
513 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
514 as_fatal (_("Bad opcode table, broken assembler."));
516 if (!architecture_requested
517 || opcode_arch
> max_architecture
)
518 max_architecture
= opcode_arch
;
519 hwcap_allowed
|= sa
->hwcap_allowed
;
520 architecture_requested
= 1;
525 /* Ignore -sparc, used by SunOS make default .s.o rule. */
528 case OPTION_ENFORCE_ALIGNED_DATA
:
529 enforce_aligned_data
= 1;
532 #ifdef SPARC_BIENDIAN
533 case OPTION_LITTLE_ENDIAN
:
534 target_big_endian
= 0;
535 if (default_arch_type
!= sparclet
)
536 as_fatal ("This target does not support -EL");
538 case OPTION_LITTLE_ENDIAN_DATA
:
539 target_little_endian_data
= 1;
540 target_big_endian
= 0;
541 if (default_arch_type
!= sparc86x
542 && default_arch_type
!= v9
)
543 as_fatal ("This target does not support --little-endian-data");
545 case OPTION_BIG_ENDIAN
:
546 target_big_endian
= 1;
560 const char **list
, **l
;
562 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
563 list
= bfd_target_list ();
564 for (l
= list
; *l
!= NULL
; l
++)
566 if (sparc_arch_size
== 32)
568 if (CONST_STRNEQ (*l
, "elf32-sparc"))
573 if (CONST_STRNEQ (*l
, "elf64-sparc"))
578 as_fatal (_("No compiled in support for %d bit object file format"),
582 if (sparc_arch_size
== 64
583 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
584 max_architecture
= SPARC_OPCODE_ARCH_V9
;
589 sparc_memory_model
= MM_TSO
;
593 sparc_memory_model
= MM_PSO
;
597 sparc_memory_model
= MM_RMO
;
605 /* Qy - do emit .comment
606 Qn - do not emit .comment. */
610 /* Use .stab instead of .stab.excl. */
614 /* quick -- Native assembler does fewer checks. */
618 if (strcmp (arg
, "PIC") != 0)
619 as_warn (_("Unrecognized option following -K"));
624 case OPTION_NO_UNDECLARED_REGS
:
625 no_undeclared_regs
= 1;
628 case OPTION_UNDECLARED_REGS
:
629 no_undeclared_regs
= 0;
637 case OPTION_NO_RELAX
:
649 md_show_usage (FILE *stream
)
651 const struct sparc_arch
*arch
;
654 /* We don't get a chance to initialize anything before we're called,
655 so handle that now. */
656 if (! default_init_p
)
657 init_default_arch ();
659 fprintf (stream
, _("SPARC options:\n"));
661 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
663 if (!arch
->user_option_p
)
665 if (arch
!= &sparc_arch_table
[0])
666 fprintf (stream
, " | ");
667 if (column
+ strlen (arch
->name
) > 70)
670 fputc ('\n', stream
);
672 column
+= 5 + 2 + strlen (arch
->name
);
673 fprintf (stream
, "-A%s", arch
->name
);
675 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
677 if (!arch
->user_option_p
)
679 fprintf (stream
, " | ");
680 if (column
+ strlen (arch
->name
) > 65)
683 fputc ('\n', stream
);
685 column
+= 5 + 7 + strlen (arch
->name
);
686 fprintf (stream
, "-xarch=%s", arch
->name
);
688 fprintf (stream
, _("\n\
689 specify variant of SPARC architecture\n\
690 -bump warn when assembler switches architectures\n\
692 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
693 -relax relax jumps and branches (default)\n\
694 -no-relax avoid changing any jumps and branches\n"));
696 fprintf (stream
, _("\
697 -k generate PIC\n"));
700 fprintf (stream
, _("\
701 -32 create 32 bit object file\n\
702 -64 create 64 bit object file\n"));
703 fprintf (stream
, _("\
704 [default is %d]\n"), default_arch_size
);
705 fprintf (stream
, _("\
706 -TSO use Total Store Ordering\n\
707 -PSO use Partial Store Ordering\n\
708 -RMO use Relaxed Memory Ordering\n"));
709 fprintf (stream
, _("\
710 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
711 fprintf (stream
, _("\
712 -KPIC generate PIC\n\
713 -V print assembler version number\n\
714 -undeclared-regs ignore application global register usage without\n\
715 appropriate .register directive (default)\n\
716 -no-undeclared-regs force error on application global register usage\n\
717 without appropriate .register directive\n\
722 #ifdef SPARC_BIENDIAN
723 fprintf (stream
, _("\
724 -EL generate code for a little endian machine\n\
725 -EB generate code for a big endian machine\n\
726 --little-endian-data generate code for a machine having big endian\n\
727 instructions and little endian data.\n"));
731 /* Native operand size opcode translation. */
737 } native_op_table
[] =
739 {"ldn", "ld", "ldx"},
740 {"ldna", "lda", "ldxa"},
741 {"stn", "st", "stx"},
742 {"stna", "sta", "stxa"},
743 {"slln", "sll", "sllx"},
744 {"srln", "srl", "srlx"},
745 {"sran", "sra", "srax"},
746 {"casn", "cas", "casx"},
747 {"casna", "casa", "casxa"},
748 {"clrn", "clr", "clrx"},
752 /* sparc64 privileged and hyperprivileged registers. */
754 struct priv_reg_entry
760 struct priv_reg_entry priv_reg_table
[] =
780 {"", -1}, /* End marker. */
783 struct priv_reg_entry hpriv_reg_table
[] =
791 {"", -1}, /* End marker. */
794 /* v9a specific asrs. This table is ordered by initial
795 letter, in reverse. */
797 struct priv_reg_entry v9a_asr_table
[] =
800 {"sys_tick_cmpr", 25},
804 {"softint_clear", 21},
815 {"clear_softint", 21},
816 {"", -1}, /* End marker. */
820 cmp_reg_entry (const void *parg
, const void *qarg
)
822 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
823 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
825 return strcmp (q
->name
, p
->name
);
828 /* This function is called once, at assembler startup time. It should
829 set up all the tables, etc. that the MD part of the assembler will
835 register const char *retval
= NULL
;
837 register unsigned int i
= 0;
839 /* We don't get a chance to initialize anything before md_parse_option
840 is called, and it may not be called, so handle default initialization
841 now if not already done. */
842 if (! default_init_p
)
843 init_default_arch ();
845 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
846 op_hash
= hash_new ();
848 while (i
< (unsigned int) sparc_num_opcodes
)
850 const char *name
= sparc_opcodes
[i
].name
;
851 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
854 as_bad (_("Internal error: can't hash `%s': %s\n"),
855 sparc_opcodes
[i
].name
, retval
);
860 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
862 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
863 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
868 while (i
< (unsigned int) sparc_num_opcodes
869 && !strcmp (sparc_opcodes
[i
].name
, name
));
872 for (i
= 0; native_op_table
[i
].name
; i
++)
874 const struct sparc_opcode
*insn
;
875 char *name
= ((sparc_arch_size
== 32)
876 ? native_op_table
[i
].name32
877 : native_op_table
[i
].name64
);
878 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
881 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
882 name
, native_op_table
[i
].name
);
887 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
891 as_bad (_("Internal error: can't hash `%s': %s\n"),
892 sparc_opcodes
[i
].name
, retval
);
899 as_fatal (_("Broken assembler. No assembly attempted."));
901 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
902 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
904 /* If -bump, record the architecture level at which we start issuing
905 warnings. The behaviour is different depending upon whether an
906 architecture was explicitly specified. If it wasn't, we issue warnings
907 for all upwards bumps. If it was, we don't start issuing warnings until
908 we need to bump beyond the requested architecture or when we bump between
909 conflicting architectures. */
912 && architecture_requested
)
914 /* `max_architecture' records the requested architecture.
915 Issue warnings if we go above it. */
916 warn_after_architecture
= max_architecture
;
918 /* Find the highest architecture level that doesn't conflict with
919 the requested one. */
920 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
921 max_architecture
> warn_after_architecture
;
923 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
924 warn_after_architecture
))
929 /* Called after all assembly has been done. */
934 unsigned long mach
= bfd_mach_sparc
;
936 if (sparc_arch_size
== 64)
937 switch (current_architecture
)
939 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
940 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
941 default: mach
= bfd_mach_sparc_v9
; break;
944 switch (current_architecture
)
946 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
947 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
948 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
949 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
950 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
951 be but for now it is (since that's the way it's always been
955 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
957 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
959 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcap_seen
);
963 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
966 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
970 /* Sign-extend the value from the architecture word size, so that
971 0xffffffff is always considered -1 on sparc32. */
972 if (sparc_arch_size
== 32)
974 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
975 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
984 /* Return non-zero if VAL is in the range 0 to MAX. */
987 in_unsigned_range (bfd_vma val
, bfd_vma max
)
994 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
995 (e.g. -15 to +31). */
998 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1004 if (val
< ~(max
>> 1))
1010 sparc_ffs (unsigned int mask
)
1017 for (i
= 0; (mask
& 1) == 0; ++i
)
1022 /* Implement big shift right. */
1024 BSR (bfd_vma val
, int amount
)
1026 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1027 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1028 return val
>> amount
;
1031 /* For communication between sparc_ip and get_expression. */
1032 static char *expr_end
;
1034 /* Values for `special_case'.
1035 Instructions that require wierd handling because they're longer than
1037 #define SPECIAL_CASE_NONE 0
1038 #define SPECIAL_CASE_SET 1
1039 #define SPECIAL_CASE_SETSW 2
1040 #define SPECIAL_CASE_SETX 3
1041 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1042 #define SPECIAL_CASE_FDIV 4
1044 /* Bit masks of various insns. */
1045 #define NOP_INSN 0x01000000
1046 #define OR_INSN 0x80100000
1047 #define XOR_INSN 0x80180000
1048 #define FMOVS_INSN 0x81A00020
1049 #define SETHI_INSN 0x01000000
1050 #define SLLX_INSN 0x81281000
1051 #define SRA_INSN 0x81380000
1053 /* The last instruction to be assembled. */
1054 static const struct sparc_opcode
*last_insn
;
1055 /* The assembled opcode of `last_insn'. */
1056 static unsigned long last_opcode
;
1058 /* Handle the set and setuw synthetic instructions. */
1061 synthetize_setuw (const struct sparc_opcode
*insn
)
1063 int need_hi22_p
= 0;
1064 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1066 if (the_insn
.exp
.X_op
== O_constant
)
1068 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1070 if (sizeof (offsetT
) > 4
1071 && (the_insn
.exp
.X_add_number
< 0
1072 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1073 as_warn (_("set: number not in 0..4294967295 range"));
1077 if (sizeof (offsetT
) > 4
1078 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1079 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1080 as_warn (_("set: number not in -2147483648..4294967295 range"));
1081 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1085 /* See if operand is absolute and small; skip sethi if so. */
1086 if (the_insn
.exp
.X_op
!= O_constant
1087 || the_insn
.exp
.X_add_number
>= (1 << 12)
1088 || the_insn
.exp
.X_add_number
< -(1 << 12))
1090 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1091 | ((the_insn
.exp
.X_add_number
>> 10)
1092 & (the_insn
.exp
.X_op
== O_constant
1094 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1095 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1096 output_insn (insn
, &the_insn
);
1100 /* See if operand has no low-order bits; skip OR if so. */
1101 if (the_insn
.exp
.X_op
!= O_constant
1102 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1105 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1107 | (the_insn
.exp
.X_add_number
1108 & (the_insn
.exp
.X_op
!= O_constant
1109 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1110 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1111 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1112 output_insn (insn
, &the_insn
);
1116 /* Handle the setsw synthetic instruction. */
1119 synthetize_setsw (const struct sparc_opcode
*insn
)
1123 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1125 if (the_insn
.exp
.X_op
!= O_constant
)
1127 synthetize_setuw (insn
);
1129 /* Need to sign extend it. */
1130 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1131 the_insn
.reloc
= BFD_RELOC_NONE
;
1132 output_insn (insn
, &the_insn
);
1136 if (sizeof (offsetT
) > 4
1137 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1138 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1139 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1141 low32
= the_insn
.exp
.X_add_number
;
1145 synthetize_setuw (insn
);
1151 the_insn
.reloc
= BFD_RELOC_NONE
;
1152 /* See if operand is absolute and small; skip sethi if so. */
1153 if (low32
< -(1 << 12))
1155 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1156 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1157 output_insn (insn
, &the_insn
);
1158 low32
= 0x1c00 | (low32
& 0x3ff);
1159 opc
= RS1 (rd
) | XOR_INSN
;
1162 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1163 | (low32
& 0x1fff));
1164 output_insn (insn
, &the_insn
);
1167 /* Handle the setsw synthetic instruction. */
1170 synthetize_setx (const struct sparc_opcode
*insn
)
1172 int upper32
, lower32
;
1173 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1174 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1176 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1177 int need_xor10_p
= 0;
1179 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1180 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1181 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1184 upper_dstreg
= tmpreg
;
1185 /* The tmp reg should not be the dst reg. */
1186 if (tmpreg
== dstreg
)
1187 as_warn (_("setx: temporary register same as destination register"));
1189 /* ??? Obviously there are other optimizations we can do
1190 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1191 doing some of these. Later. If you do change things, try to
1192 change all of this to be table driven as well. */
1193 /* What to output depends on the number if it's constant.
1194 Compute that first, then output what we've decided upon. */
1195 if (the_insn
.exp
.X_op
!= O_constant
)
1197 if (sparc_arch_size
== 32)
1199 /* When arch size is 32, we want setx to be equivalent
1200 to setuw for anything but constants. */
1201 the_insn
.exp
.X_add_number
&= 0xffffffff;
1202 synthetize_setuw (insn
);
1205 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1211 /* Reset X_add_number, we've extracted it as upper32/lower32.
1212 Otherwise fixup_segment will complain about not being able to
1213 write an 8 byte number in a 4 byte field. */
1214 the_insn
.exp
.X_add_number
= 0;
1216 /* Only need hh22 if `or' insn can't handle constant. */
1217 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1220 /* Does bottom part (after sethi) have bits? */
1221 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1222 /* No hh22, but does upper32 still have bits we can't set
1224 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1227 /* If the lower half is all zero, we build the upper half directly
1228 into the dst reg. */
1230 /* Need lower half if number is zero or 0xffffffff00000000. */
1231 || (! need_hh22_p
&& ! need_hm10_p
))
1233 /* No need for sethi if `or' insn can handle constant. */
1234 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1235 /* Note that we can't use a negative constant in the `or'
1236 insn unless the upper 32 bits are all ones. */
1237 || (lower32
< 0 && upper32
!= -1)
1238 || (lower32
>= 0 && upper32
== -1))
1241 if (need_hi22_p
&& upper32
== -1)
1244 /* Does bottom part (after sethi) have bits? */
1245 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1247 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1248 /* Need `or' if we didn't set anything else. */
1249 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1253 /* Output directly to dst reg if lower 32 bits are all zero. */
1254 upper_dstreg
= dstreg
;
1257 if (!upper_dstreg
&& dstreg
)
1258 as_warn (_("setx: illegal temporary register g0"));
1262 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1263 | ((upper32
>> 10) & 0x3fffff));
1264 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1265 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1266 output_insn (insn
, &the_insn
);
1271 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1272 | (((need_xor10_p
? ~lower32
: lower32
)
1273 >> 10) & 0x3fffff));
1274 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1275 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1276 output_insn (insn
, &the_insn
);
1281 the_insn
.opcode
= (OR_INSN
1282 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1285 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1286 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1287 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1288 output_insn (insn
, &the_insn
);
1293 /* FIXME: One nice optimization to do here is to OR the low part
1294 with the highpart if hi22 isn't needed and the low part is
1296 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1299 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1300 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1301 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1302 output_insn (insn
, &the_insn
);
1305 /* If we needed to build the upper part, shift it into place. */
1306 if (need_hh22_p
|| need_hm10_p
)
1308 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1310 the_insn
.reloc
= BFD_RELOC_NONE
;
1311 output_insn (insn
, &the_insn
);
1314 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1317 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1318 | 0x1c00 | (lower32
& 0x3ff));
1319 the_insn
.reloc
= BFD_RELOC_NONE
;
1320 output_insn (insn
, &the_insn
);
1323 /* If we needed to build both upper and lower parts, OR them together. */
1324 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1326 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1328 the_insn
.reloc
= BFD_RELOC_NONE
;
1329 output_insn (insn
, &the_insn
);
1333 /* Main entry point to assemble one instruction. */
1336 md_assemble (char *str
)
1338 const struct sparc_opcode
*insn
;
1342 special_case
= sparc_ip (str
, &insn
);
1346 /* We warn about attempts to put a floating point branch in a delay slot,
1347 unless the delay slot has been annulled. */
1348 if (last_insn
!= NULL
1349 && (insn
->flags
& F_FBR
) != 0
1350 && (last_insn
->flags
& F_DELAYED
) != 0
1351 /* ??? This test isn't completely accurate. We assume anything with
1352 F_{UNBR,CONDBR,FBR} set is annullable. */
1353 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1354 || (last_opcode
& ANNUL
) == 0))
1355 as_warn (_("FP branch in delay slot"));
1357 /* SPARC before v9 requires a nop instruction between a floating
1358 point instruction and a floating point branch. We insert one
1359 automatically, with a warning. */
1360 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1361 && last_insn
!= NULL
1362 && (insn
->flags
& F_FBR
) != 0
1363 && (last_insn
->flags
& F_FLOAT
) != 0)
1365 struct sparc_it nop_insn
;
1367 nop_insn
.opcode
= NOP_INSN
;
1368 nop_insn
.reloc
= BFD_RELOC_NONE
;
1369 output_insn (insn
, &nop_insn
);
1370 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1373 switch (special_case
)
1375 case SPECIAL_CASE_NONE
:
1377 output_insn (insn
, &the_insn
);
1380 case SPECIAL_CASE_SETSW
:
1381 synthetize_setsw (insn
);
1384 case SPECIAL_CASE_SET
:
1385 synthetize_setuw (insn
);
1388 case SPECIAL_CASE_SETX
:
1389 synthetize_setx (insn
);
1392 case SPECIAL_CASE_FDIV
:
1394 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1396 output_insn (insn
, &the_insn
);
1398 /* According to information leaked from Sun, the "fdiv" instructions
1399 on early SPARC machines would produce incorrect results sometimes.
1400 The workaround is to add an fmovs of the destination register to
1401 itself just after the instruction. This was true on machines
1402 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1403 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1404 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1405 output_insn (insn
, &the_insn
);
1410 as_fatal (_("failed special case insn sanity check"));
1415 get_hwcap_name (int mask
)
1417 if (mask
& HWCAP_MUL32
)
1419 if (mask
& HWCAP_DIV32
)
1421 if (mask
& HWCAP_FSMULD
)
1423 if (mask
& HWCAP_V8PLUS
)
1425 if (mask
& HWCAP_POPC
)
1427 if (mask
& HWCAP_VIS
)
1429 if (mask
& HWCAP_VIS2
)
1431 if (mask
& HWCAP_ASI_BLK_INIT
)
1432 return "ASIBlkInit";
1433 if (mask
& HWCAP_FMAF
)
1435 if (mask
& HWCAP_VIS3
)
1437 if (mask
& HWCAP_HPC
)
1439 if (mask
& HWCAP_RANDOM
)
1441 if (mask
& HWCAP_TRANS
)
1443 if (mask
& HWCAP_FJFMAU
)
1445 if (mask
& HWCAP_IMA
)
1447 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1449 if (mask
& HWCAP_AES
)
1451 if (mask
& HWCAP_DES
)
1453 if (mask
& HWCAP_KASUMI
)
1455 if (mask
& HWCAP_CAMELLIA
)
1457 if (mask
& HWCAP_MD5
)
1459 if (mask
& HWCAP_SHA1
)
1461 if (mask
& HWCAP_SHA256
)
1463 if (mask
& HWCAP_SHA512
)
1465 if (mask
& HWCAP_MPMUL
)
1467 if (mask
& HWCAP_MONT
)
1469 if (mask
& HWCAP_PAUSE
)
1471 if (mask
& HWCAP_CBCOND
)
1473 if (mask
& HWCAP_CRC32C
)
1478 /* Subroutine of md_assemble to do the actual parsing. */
1481 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1483 char *error_message
= "";
1487 const struct sparc_opcode
*insn
;
1489 unsigned long opcode
;
1490 unsigned int mask
= 0;
1494 int special_case
= SPECIAL_CASE_NONE
;
1501 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1518 as_bad (_("Unknown opcode: `%s'"), str
);
1520 return special_case
;
1522 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1526 as_bad (_("Unknown opcode: `%s'"), str
);
1527 return special_case
;
1537 opcode
= insn
->match
;
1538 memset (&the_insn
, '\0', sizeof (the_insn
));
1539 the_insn
.reloc
= BFD_RELOC_NONE
;
1542 /* Build the opcode, checking as we go to make sure that the
1544 for (args
= insn
->args
;; ++args
)
1552 /* Parse a series of masks. */
1559 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1562 error_message
= _(": invalid membar mask name");
1568 if (*s
== '|' || *s
== '+')
1576 if (! parse_const_expr_arg (&s
, &kmask
))
1578 error_message
= _(": invalid membar mask expression");
1581 if (kmask
< 0 || kmask
> 127)
1583 error_message
= _(": invalid membar mask number");
1588 opcode
|= MEMBAR (kmask
);
1596 if (! parse_const_expr_arg (&s
, &smask
))
1598 error_message
= _(": invalid siam mode expression");
1601 if (smask
< 0 || smask
> 7)
1603 error_message
= _(": invalid siam mode number");
1614 /* Parse a prefetch function. */
1617 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1619 error_message
= _(": invalid prefetch function name");
1625 if (! parse_const_expr_arg (&s
, &fcn
))
1627 error_message
= _(": invalid prefetch function expression");
1630 if (fcn
< 0 || fcn
> 31)
1632 error_message
= _(": invalid prefetch function number");
1642 /* Parse a sparc64 privileged register. */
1645 struct priv_reg_entry
*p
= priv_reg_table
;
1646 unsigned int len
= 9999999; /* Init to make gcc happy. */
1649 while (p
->name
[0] > s
[0])
1651 while (p
->name
[0] == s
[0])
1653 len
= strlen (p
->name
);
1654 if (strncmp (p
->name
, s
, len
) == 0)
1658 if (p
->name
[0] != s
[0])
1660 error_message
= _(": unrecognizable privileged register");
1664 opcode
|= (p
->regnum
<< 14);
1666 opcode
|= (p
->regnum
<< 25);
1672 error_message
= _(": unrecognizable privileged register");
1678 /* Parse a sparc64 hyperprivileged register. */
1681 struct priv_reg_entry
*p
= hpriv_reg_table
;
1682 unsigned int len
= 9999999; /* Init to make gcc happy. */
1685 while (p
->name
[0] > s
[0])
1687 while (p
->name
[0] == s
[0])
1689 len
= strlen (p
->name
);
1690 if (strncmp (p
->name
, s
, len
) == 0)
1694 if (p
->name
[0] != s
[0])
1696 error_message
= _(": unrecognizable hyperprivileged register");
1700 opcode
|= (p
->regnum
<< 14);
1702 opcode
|= (p
->regnum
<< 25);
1708 error_message
= _(": unrecognizable hyperprivileged register");
1714 /* Parse a v9a/v9b ancillary state register. */
1717 struct priv_reg_entry
*p
= v9a_asr_table
;
1718 unsigned int len
= 9999999; /* Init to make gcc happy. */
1721 while (p
->name
[0] > s
[0])
1723 while (p
->name
[0] == s
[0])
1725 len
= strlen (p
->name
);
1726 if (strncmp (p
->name
, s
, len
) == 0)
1730 if (p
->name
[0] != s
[0])
1732 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1735 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1737 error_message
= _(": rd on write only ancillary state register");
1741 && (insn
->architecture
1742 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1744 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1745 error_message
= _(": unrecognizable v9a ancillary state register");
1749 opcode
|= (p
->regnum
<< 14);
1751 opcode
|= (p
->regnum
<< 25);
1757 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1763 if (strncmp (s
, "%asr", 4) == 0)
1771 while (ISDIGIT (*s
))
1773 num
= num
* 10 + *s
- '0';
1777 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1779 if (num
< 16 || 31 < num
)
1781 error_message
= _(": asr number must be between 16 and 31");
1787 if (num
< 0 || 31 < num
)
1789 error_message
= _(": asr number must be between 0 and 31");
1794 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1799 error_message
= _(": expecting %asrN");
1806 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1810 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1816 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
1821 if (s
[0] == '0' && s
[1] == 'x')
1824 while (ISXDIGIT (*s
))
1827 num
|= hex_value (*s
);
1833 while (ISDIGIT (*s
))
1835 num
= num
* 10 + *s
- '0';
1839 if (num
< 0 || num
> 31)
1841 error_message
= _(": crypto immediate must be between 0 and 31");
1845 opcode
|= RS3 (num
);
1850 error_message
= _(": expecting crypto immediate");
1855 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1856 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1857 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1859 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1860 /* These fields are unsigned, but for upward compatibility,
1861 allow negative values as well. */
1865 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1866 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1867 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1869 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1870 /* These fields are unsigned, but for upward compatibility,
1871 allow negative values as well. */
1875 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1880 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
1885 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1890 if (*s
== 'p' && s
[1] == 'n')
1898 if (*s
== 'p' && s
[1] == 't')
1910 if (strncmp (s
, "%icc", 4) == 0)
1922 if (strncmp (s
, "%xcc", 4) == 0)
1934 if (strncmp (s
, "%fcc0", 5) == 0)
1946 if (strncmp (s
, "%fcc1", 5) == 0)
1958 if (strncmp (s
, "%fcc2", 5) == 0)
1970 if (strncmp (s
, "%fcc3", 5) == 0)
1978 if (strncmp (s
, "%pc", 3) == 0)
1986 if (strncmp (s
, "%tick", 5) == 0)
1993 case '\0': /* End of args. */
1994 if (s
[0] == ',' && s
[1] == '%')
1996 static const struct ops
1998 /* The name as it appears in assembler. */
2000 /* strlen (name), precomputed for speed */
2002 /* The reloc this pseudo-op translates to. */
2004 /* 1 if tls call. */
2009 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
2010 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
2011 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
2012 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
2013 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
2014 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
2015 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
2016 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
2017 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
2020 const struct ops
*o
;
2024 for (o
= ops
; o
->name
; o
++)
2025 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
2027 if (o
->name
== NULL
)
2030 if (s
[o
->len
+ 2] != '(')
2032 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2033 return special_case
;
2036 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
2038 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2040 return special_case
;
2044 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2045 || the_insn
.exp
.X_add_number
!= 0
2046 || the_insn
.exp
.X_add_symbol
2047 != symbol_find_or_make ("__tls_get_addr")))
2049 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2051 return special_case
;
2054 the_insn
.reloc
= o
->reloc
;
2055 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2058 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2061 else if (*s1
== ')')
2070 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2071 return special_case
;
2075 (void) get_expression (s
);
2095 case '[': /* These must match exactly. */
2103 case '#': /* Must be at least one digit. */
2106 while (ISDIGIT (*s
))
2114 case 'C': /* Coprocessor state register. */
2115 if (strncmp (s
, "%csr", 4) == 0)
2122 case 'b': /* Next operand is a coprocessor register. */
2125 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2130 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2144 opcode
|= mask
<< 14;
2152 opcode
|= mask
<< 25;
2158 case 'r': /* next operand must be a register */
2168 case 'f': /* frame pointer */
2176 case 'g': /* global register */
2185 case 'i': /* in register */
2189 mask
= c
- '0' + 24;
2194 case 'l': /* local register */
2198 mask
= (c
- '0' + 16);
2203 case 'o': /* out register */
2207 mask
= (c
- '0' + 8);
2212 case 's': /* stack pointer */
2220 case 'r': /* any register */
2221 if (!ISDIGIT ((c
= *s
++)))
2238 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2254 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2255 && no_undeclared_regs
&& ! globals
[mask
])
2256 as_bad (_("detected global register use not covered by .register pseudo-op"));
2258 /* Got the register, now figure out where
2259 it goes in the opcode. */
2263 opcode
|= mask
<< 14;
2271 opcode
|= mask
<< 25;
2275 opcode
|= (mask
<< 25) | (mask
<< 14);
2279 opcode
|= (mask
<< 25) | (mask
<< 0);
2285 case 'e': /* next operand is a floating point register */
2303 && ((format
= *s
) == 'f')
2306 for (mask
= 0; ISDIGIT (*s
); ++s
)
2308 mask
= 10 * mask
+ (*s
- '0');
2309 } /* read the number */
2318 } /* register must be even numbered */
2326 } /* register must be multiple of 4 */
2330 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2331 error_message
= _(": There are only 64 f registers; [0-63]");
2333 error_message
= _(": There are only 32 f registers; [0-31]");
2336 else if (mask
>= 32)
2338 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2340 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2343 = _(": There are only 32 single precision f registers; [0-31]");
2347 mask
-= 31; /* wrap high bit */
2351 error_message
= _(": There are only 32 f registers; [0-31]");
2359 } /* if not an 'f' register. */
2366 opcode
|= RS1 (mask
);
2372 opcode
|= RS2 (mask
);
2377 opcode
|= RS3 (mask
);
2383 opcode
|= RD (mask
);
2392 if (strncmp (s
, "%fsr", 4) == 0)
2400 if (strncmp (s
, "%efsr", 5) == 0)
2407 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2408 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2411 case 'l': /* 22 bit PC relative immediate */
2412 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2416 case 'L': /* 30 bit immediate */
2417 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2422 case 'n': /* 22 bit immediate */
2423 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2426 case 'i': /* 13 bit immediate */
2427 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2437 char *op_arg
= NULL
;
2438 static expressionS op_exp
;
2439 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2441 /* Check for %hi, etc. */
2444 static const struct ops
{
2445 /* The name as it appears in assembler. */
2447 /* strlen (name), precomputed for speed */
2449 /* The reloc this pseudo-op translates to. */
2451 /* Non-zero if for v9 only. */
2453 /* Non-zero if can be used in pc-relative contexts. */
2454 int pcrel_p
;/*FIXME:wip*/
2456 /* hix/lox must appear before hi/lo so %hix won't be
2457 mistaken for %hi. */
2458 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2459 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2460 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2461 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2462 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2463 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2464 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2465 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2466 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2467 { "h34", 3, BFD_RELOC_SPARC_H34
, 1, 0 },
2468 { "l34", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2469 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2470 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2471 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2472 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2473 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2474 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2475 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2476 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2477 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2478 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2480 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2482 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2483 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2484 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2485 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2486 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2488 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2490 { NULL
, 0, 0, 0, 0 }
2492 const struct ops
*o
;
2494 for (o
= ops
; o
->name
; o
++)
2495 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2497 if (o
->name
== NULL
)
2500 if (s
[o
->len
+ 1] != '(')
2502 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2503 return special_case
;
2507 the_insn
.reloc
= o
->reloc
;
2512 /* Note that if the get_expression() fails, we will still
2513 have created U entries in the symbol table for the
2514 'symbols' in the input string. Try not to create U
2515 symbols for registers, etc. */
2517 /* This stuff checks to see if the expression ends in
2518 +%reg. If it does, it removes the register from
2519 the expression, and re-sets 's' to point to the
2526 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2529 else if (*s1
== ')')
2538 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2539 return special_case
;
2543 (void) get_expression (s
);
2546 if (*s
== ',' || *s
== ']' || !*s
)
2548 if (*s
!= '+' && *s
!= '-')
2550 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2551 return special_case
;
2555 op_exp
= the_insn
.exp
;
2556 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2559 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2562 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2564 if (s1
[-2] == '%' && s1
[-3] == '+')
2566 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2568 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2575 if (op_arg
&& s1
== s
+ 1)
2576 the_insn
.exp
.X_op
= O_absent
;
2578 (void) get_expression (s
);
2590 (void) get_expression (s
);
2598 the_insn
.exp2
= the_insn
.exp
;
2599 the_insn
.exp
= op_exp
;
2600 if (the_insn
.exp2
.X_op
== O_absent
)
2601 the_insn
.exp2
.X_op
= O_illegal
;
2602 else if (the_insn
.exp
.X_op
== O_absent
)
2604 the_insn
.exp
= the_insn
.exp2
;
2605 the_insn
.exp2
.X_op
= O_illegal
;
2607 else if (the_insn
.exp
.X_op
== O_constant
)
2609 valueT val
= the_insn
.exp
.X_add_number
;
2610 switch (the_insn
.reloc
)
2615 case BFD_RELOC_SPARC_HH22
:
2616 val
= BSR (val
, 32);
2619 case BFD_RELOC_SPARC_LM22
:
2620 case BFD_RELOC_HI22
:
2621 val
= (val
>> 10) & 0x3fffff;
2624 case BFD_RELOC_SPARC_HM10
:
2625 val
= BSR (val
, 32);
2628 case BFD_RELOC_LO10
:
2632 case BFD_RELOC_SPARC_H34
:
2637 case BFD_RELOC_SPARC_H44
:
2642 case BFD_RELOC_SPARC_M44
:
2647 case BFD_RELOC_SPARC_L44
:
2651 case BFD_RELOC_SPARC_HIX22
:
2653 val
= (val
>> 10) & 0x3fffff;
2656 case BFD_RELOC_SPARC_LOX10
:
2657 val
= (val
& 0x3ff) | 0x1c00;
2660 the_insn
.exp
= the_insn
.exp2
;
2661 the_insn
.exp
.X_add_number
+= val
;
2662 the_insn
.exp2
.X_op
= O_illegal
;
2663 the_insn
.reloc
= old_reloc
;
2665 else if (the_insn
.exp2
.X_op
!= O_constant
)
2667 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2668 return special_case
;
2672 if (old_reloc
!= BFD_RELOC_SPARC13
2673 || the_insn
.reloc
!= BFD_RELOC_LO10
2674 || sparc_arch_size
!= 64
2677 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2678 return special_case
;
2680 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2684 /* Check for constants that don't require emitting a reloc. */
2685 if (the_insn
.exp
.X_op
== O_constant
2686 && the_insn
.exp
.X_add_symbol
== 0
2687 && the_insn
.exp
.X_op_symbol
== 0)
2689 /* For pc-relative call instructions, we reject
2690 constants to get better code. */
2692 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2693 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2695 error_message
= _(": PC-relative operand can't be a constant");
2699 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2700 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2702 error_message
= _(": TLS operand can't be a constant");
2706 /* Constants that won't fit are checked in md_apply_fix
2707 and bfd_install_relocation.
2708 ??? It would be preferable to install the constants
2709 into the insn here and save having to create a fixS
2710 for each one. There already exists code to handle
2711 all the various cases (e.g. in md_apply_fix and
2712 bfd_install_relocation) so duplicating all that code
2713 here isn't right. */
2715 /* This is a special case to handle cbcond instructions
2716 properly, which can need two relocations. The first
2717 one is for the 5-bit immediate field and the latter
2718 is going to be for the WDISP10 branch part. We
2719 handle the R_SPARC_5 immediate directly here so that
2720 we don't need to add support for multiple relocations
2721 in one instruction just yet. */
2722 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2724 valueT val
= the_insn
.exp
.X_add_number
;
2726 if (! in_bitfield_range (val
, 0x1f))
2728 error_message
= _(": Immediate value in cbcond is out of range.");
2731 opcode
|= val
& 0x1f;
2732 the_insn
.reloc
= BFD_RELOC_NONE
;
2753 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2755 error_message
= _(": invalid ASI name");
2761 if (! parse_const_expr_arg (&s
, &asi
))
2763 error_message
= _(": invalid ASI expression");
2766 if (asi
< 0 || asi
> 255)
2768 error_message
= _(": invalid ASI number");
2772 opcode
|= ASI (asi
);
2774 } /* Alternate space. */
2777 if (strncmp (s
, "%psr", 4) == 0)
2784 case 'q': /* Floating point queue. */
2785 if (strncmp (s
, "%fq", 3) == 0)
2792 case 'Q': /* Coprocessor queue. */
2793 if (strncmp (s
, "%cq", 3) == 0)
2801 if (strcmp (str
, "set") == 0
2802 || strcmp (str
, "setuw") == 0)
2804 special_case
= SPECIAL_CASE_SET
;
2807 else if (strcmp (str
, "setsw") == 0)
2809 special_case
= SPECIAL_CASE_SETSW
;
2812 else if (strcmp (str
, "setx") == 0)
2814 special_case
= SPECIAL_CASE_SETX
;
2817 else if (strncmp (str
, "fdiv", 4) == 0)
2819 special_case
= SPECIAL_CASE_FDIV
;
2825 if (strncmp (s
, "%asi", 4) != 0)
2831 if (strncmp (s
, "%fprs", 5) != 0)
2837 if (strncmp (s
, "%ccr", 4) != 0)
2843 if (strncmp (s
, "%tbr", 4) != 0)
2849 if (strncmp (s
, "%wim", 4) != 0)
2856 char *push
= input_line_pointer
;
2859 input_line_pointer
= s
;
2861 if (e
.X_op
== O_constant
)
2863 int n
= e
.X_add_number
;
2864 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2865 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2867 opcode
|= e
.X_add_number
<< 5;
2870 as_bad (_("non-immediate OPF operand, ignored"));
2871 s
= input_line_pointer
;
2872 input_line_pointer
= push
;
2877 if (strncmp (s
, "%y", 2) != 0)
2885 /* Parse a sparclet cpreg. */
2887 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2889 error_message
= _(": invalid cpreg name");
2892 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2897 as_fatal (_("failed sanity check."));
2898 } /* switch on arg code. */
2900 /* Break out of for() loop. */
2902 } /* For each arg that we expect. */
2907 /* Args don't match. */
2908 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2909 && (insn
->name
== insn
[1].name
2910 || !strcmp (insn
->name
, insn
[1].name
)))
2918 as_bad (_("Illegal operands%s"), error_message
);
2919 return special_case
;
2924 /* We have a match. Now see if the architecture is OK. */
2925 int needed_arch_mask
= insn
->architecture
;
2926 int hwcaps
= insn
->hwcaps
;
2928 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2930 hwcap_seen
|= hwcaps
;
2935 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2936 if (! needed_arch_mask
)
2938 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2941 if (needed_arch_mask
2942 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2945 /* Can we bump up the architecture? */
2946 else if (needed_arch_mask
2947 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2949 enum sparc_opcode_arch_val needed_architecture
=
2950 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2951 & needed_arch_mask
);
2953 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2955 && needed_architecture
> warn_after_architecture
)
2957 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2958 sparc_opcode_archs
[current_architecture
].name
,
2959 sparc_opcode_archs
[needed_architecture
].name
,
2961 warn_after_architecture
= needed_architecture
;
2963 current_architecture
= needed_architecture
;
2966 /* ??? This seems to be a bit fragile. What if the next entry in
2967 the opcode table is the one we want and it is supported?
2968 It is possible to arrange the table today so that this can't
2969 happen but what about tomorrow? */
2972 int arch
, printed_one_p
= 0;
2974 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2976 /* Create a list of the architectures that support the insn. */
2977 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2979 arch
= sparc_ffs (needed_arch_mask
);
2980 while ((1 << arch
) <= needed_arch_mask
)
2982 if ((1 << arch
) & needed_arch_mask
)
2986 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2993 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2994 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2996 sparc_opcode_archs
[max_architecture
].name
);
2997 return special_case
;
3000 /* Make sure the hwcaps used by the instruction are
3001 currently enabled. */
3002 if (hwcaps
& ~hwcap_allowed
)
3004 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3006 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3008 return special_case
;
3010 } /* If no match. */
3013 } /* Forever looking for a match. */
3015 the_insn
.opcode
= opcode
;
3016 return special_case
;
3019 /* Parse an argument that can be expressed as a keyword.
3020 (eg: #StoreStore or %ccfr).
3021 The result is a boolean indicating success.
3022 If successful, INPUT_POINTER is updated. */
3025 parse_keyword_arg (int (*lookup_fn
) (const char *),
3026 char **input_pointerP
,
3032 p
= *input_pointerP
;
3033 for (q
= p
+ (*p
== '#' || *p
== '%');
3034 ISALNUM (*q
) || *q
== '_';
3039 value
= (*lookup_fn
) (p
);
3044 *input_pointerP
= q
;
3048 /* Parse an argument that is a constant expression.
3049 The result is a boolean indicating success. */
3052 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3054 char *save
= input_line_pointer
;
3057 input_line_pointer
= *input_pointerP
;
3058 /* The next expression may be something other than a constant
3059 (say if we're not processing the right variant of the insn).
3060 Don't call expression unless we're sure it will succeed as it will
3061 signal an error (which we want to defer until later). */
3062 /* FIXME: It might be better to define md_operand and have it recognize
3063 things like %asi, etc. but continuing that route through to the end
3064 is a lot of work. */
3065 if (*input_line_pointer
== '%')
3067 input_line_pointer
= save
;
3071 *input_pointerP
= input_line_pointer
;
3072 input_line_pointer
= save
;
3073 if (exp
.X_op
!= O_constant
)
3075 *valueP
= exp
.X_add_number
;
3079 /* Subroutine of sparc_ip to parse an expression. */
3082 get_expression (char *str
)
3087 save_in
= input_line_pointer
;
3088 input_line_pointer
= str
;
3089 seg
= expression (&the_insn
.exp
);
3090 if (seg
!= absolute_section
3091 && seg
!= text_section
3092 && seg
!= data_section
3093 && seg
!= bss_section
3094 && seg
!= undefined_section
)
3096 the_insn
.error
= _("bad segment");
3097 expr_end
= input_line_pointer
;
3098 input_line_pointer
= save_in
;
3101 expr_end
= input_line_pointer
;
3102 input_line_pointer
= save_in
;
3106 /* Subroutine of md_assemble to output one insn. */
3109 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3111 char *toP
= frag_more (4);
3113 /* Put out the opcode. */
3114 if (INSN_BIG_ENDIAN
)
3115 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3117 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3119 /* Put out the symbol-dependent stuff. */
3120 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3122 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3123 (toP
- frag_now
->fr_literal
), /* Where. */
3128 /* Turn off overflow checking in fixup_segment. We'll do our
3129 own overflow checking in md_apply_fix. This is necessary because
3130 the insn size is 4 and fixup_segment will signal an overflow for
3131 large 8 byte quantities. */
3132 fixP
->fx_no_overflow
= 1;
3133 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3134 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3138 last_opcode
= theinsn
->opcode
;
3141 dwarf2_emit_insn (4);
3146 md_atof (int type
, char *litP
, int *sizeP
)
3148 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3151 /* Write a value out to the object file, using the appropriate
3155 md_number_to_chars (char *buf
, valueT val
, int n
)
3157 if (target_big_endian
)
3158 number_to_chars_bigendian (buf
, val
, n
);
3159 else if (target_little_endian_data
3160 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3161 /* Output debug words, which are not in allocated sections, as big
3163 number_to_chars_bigendian (buf
, val
, n
);
3164 else if (target_little_endian_data
|| ! target_big_endian
)
3165 number_to_chars_littleendian (buf
, val
, n
);
3168 /* Apply a fixS to the frags, now that we know the value it ought to
3172 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3174 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3175 offsetT val
= * (offsetT
*) valP
;
3178 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3180 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3183 /* SPARC ELF relocations don't use an addend in the data field. */
3184 if (fixP
->fx_addsy
!= NULL
)
3186 switch (fixP
->fx_r_type
)
3188 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3189 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3190 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3191 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3192 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3193 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3194 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3195 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3196 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3197 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3198 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3199 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3200 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3201 case BFD_RELOC_SPARC_TLS_IE_LD
:
3202 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3203 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3204 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3205 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3206 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3207 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3208 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3209 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3210 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3211 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3212 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3222 /* This is a hack. There should be a better way to
3223 handle this. Probably in terms of howto fields, once
3224 we can look at these fixups in terms of howtos. */
3225 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3226 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3229 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3230 generate a reloc, then we just want to let the reloc addend set
3231 the value. We do not want to also stuff the addend into the
3232 object file. Including the addend in the object file works when
3233 doing a static link, because the linker will ignore the object
3234 file contents. However, the dynamic linker does not ignore the
3235 object file contents. */
3236 if (fixP
->fx_addsy
!= NULL
3237 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3240 /* When generating PIC code, we do not want an addend for a reloc
3241 against a local symbol. We adjust fx_addnumber to cancel out the
3242 value already included in val, and to also cancel out the
3243 adjustment which bfd_install_relocation will create. */
3245 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3246 && fixP
->fx_addsy
!= NULL
3247 && ! S_IS_COMMON (fixP
->fx_addsy
)
3248 && symbol_section_p (fixP
->fx_addsy
))
3249 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3251 /* When generating PIC code, we need to fiddle to get
3252 bfd_install_relocation to do the right thing for a PC relative
3253 reloc against a local symbol which we are going to keep. */
3255 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3256 && fixP
->fx_addsy
!= NULL
3257 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3258 || S_IS_WEAK (fixP
->fx_addsy
))
3259 && S_IS_DEFINED (fixP
->fx_addsy
)
3260 && ! S_IS_COMMON (fixP
->fx_addsy
))
3263 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3267 /* If this is a data relocation, just output VAL. */
3269 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3271 md_number_to_chars (buf
, val
, 1);
3273 else if (fixP
->fx_r_type
== BFD_RELOC_16
3274 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3276 md_number_to_chars (buf
, val
, 2);
3278 else if (fixP
->fx_r_type
== BFD_RELOC_32
3279 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3280 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3282 md_number_to_chars (buf
, val
, 4);
3284 else if (fixP
->fx_r_type
== BFD_RELOC_64
3285 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3287 md_number_to_chars (buf
, val
, 8);
3289 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3290 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3297 /* It's a relocation against an instruction. */
3299 if (INSN_BIG_ENDIAN
)
3300 insn
= bfd_getb32 ((unsigned char *) buf
);
3302 insn
= bfd_getl32 ((unsigned char *) buf
);
3304 switch (fixP
->fx_r_type
)
3306 case BFD_RELOC_32_PCREL_S2
:
3308 /* FIXME: This increment-by-one deserves a comment of why it's
3310 if (! sparc_pic_code
3311 || fixP
->fx_addsy
== NULL
3312 || symbol_section_p (fixP
->fx_addsy
))
3315 insn
|= val
& 0x3fffffff;
3317 /* See if we have a delay slot. */
3318 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3322 #define XCC (2 << 20)
3323 #define COND(x) (((x)&0xf)<<25)
3324 #define CONDA COND(0x8)
3325 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3326 #define INSN_BA (F2(0,2) | CONDA)
3327 #define INSN_OR F3(2, 0x2, 0)
3328 #define INSN_NOP F2(0,4)
3332 /* If the instruction is a call with either:
3334 arithmetic instruction with rd == %o7
3335 where rs1 != %o7 and rs2 if it is register != %o7
3336 then we can optimize if the call destination is near
3337 by changing the call into a branch always. */
3338 if (INSN_BIG_ENDIAN
)
3339 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3341 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3342 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3344 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3345 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3346 || ((delay
& RD (~0)) != RD (O7
))))
3348 if ((delay
& RS1 (~0)) == RS1 (O7
)
3349 || ((delay
& F3I (~0)) == 0
3350 && (delay
& RS2 (~0)) == RS2 (O7
)))
3352 /* Ensure the branch will fit into simm22. */
3353 if ((val
& 0x3fe00000)
3354 && (val
& 0x3fe00000) != 0x3fe00000)
3356 /* Check if the arch is v9 and branch will fit
3358 if (((val
& 0x3c0000) == 0
3359 || (val
& 0x3c0000) == 0x3c0000)
3360 && (sparc_arch_size
== 64
3361 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3363 insn
= INSN_BPA
| (val
& 0x7ffff);
3366 insn
= INSN_BA
| (val
& 0x3fffff);
3367 if (fixP
->fx_where
>= 4
3368 && ((delay
& (0xffffffff ^ RS1 (~0)))
3369 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3374 if (INSN_BIG_ENDIAN
)
3375 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3377 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3378 if ((setter
& (0xffffffff ^ RD (~0)))
3379 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3386 If call foo was replaced with ba, replace
3387 or %rN, %g0, %o7 with nop. */
3388 reg
= (delay
& RS1 (~0)) >> 14;
3389 if (reg
!= ((setter
& RD (~0)) >> 25)
3390 || reg
== G0
|| reg
== O7
)
3393 if (INSN_BIG_ENDIAN
)
3394 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3396 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3401 case BFD_RELOC_SPARC_11
:
3402 if (! in_signed_range (val
, 0x7ff))
3403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3404 _("relocation overflow"));
3405 insn
|= val
& 0x7ff;
3408 case BFD_RELOC_SPARC_10
:
3409 if (! in_signed_range (val
, 0x3ff))
3410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3411 _("relocation overflow"));
3412 insn
|= val
& 0x3ff;
3415 case BFD_RELOC_SPARC_7
:
3416 if (! in_bitfield_range (val
, 0x7f))
3417 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3418 _("relocation overflow"));
3422 case BFD_RELOC_SPARC_6
:
3423 if (! in_bitfield_range (val
, 0x3f))
3424 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3425 _("relocation overflow"));
3429 case BFD_RELOC_SPARC_5
:
3430 if (! in_bitfield_range (val
, 0x1f))
3431 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3432 _("relocation overflow"));
3436 case BFD_RELOC_SPARC_WDISP10
:
3439 || val
<= -(offsetT
) 0x808)
3440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3441 _("relocation overflow"));
3442 /* FIXME: The +1 deserves a comment. */
3443 val
= (val
>> 2) + 1;
3444 insn
|= ((val
& 0x300) << 11)
3445 | ((val
& 0xff) << 5);
3448 case BFD_RELOC_SPARC_WDISP16
:
3451 || val
<= -(offsetT
) 0x20008)
3452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3453 _("relocation overflow"));
3454 /* FIXME: The +1 deserves a comment. */
3455 val
= (val
>> 2) + 1;
3456 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3459 case BFD_RELOC_SPARC_WDISP19
:
3462 || val
<= -(offsetT
) 0x100008)
3463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3464 _("relocation overflow"));
3465 /* FIXME: The +1 deserves a comment. */
3466 val
= (val
>> 2) + 1;
3467 insn
|= val
& 0x7ffff;
3470 case BFD_RELOC_SPARC_HH22
:
3471 val
= BSR (val
, 32);
3474 case BFD_RELOC_SPARC_LM22
:
3475 case BFD_RELOC_HI22
:
3476 if (!fixP
->fx_addsy
)
3477 insn
|= (val
>> 10) & 0x3fffff;
3479 /* FIXME: Need comment explaining why we do this. */
3483 case BFD_RELOC_SPARC22
:
3484 if (val
& ~0x003fffff)
3485 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3486 _("relocation overflow"));
3487 insn
|= (val
& 0x3fffff);
3490 case BFD_RELOC_SPARC_HM10
:
3491 val
= BSR (val
, 32);
3494 case BFD_RELOC_LO10
:
3495 if (!fixP
->fx_addsy
)
3496 insn
|= val
& 0x3ff;
3498 /* FIXME: Need comment explaining why we do this. */
3502 case BFD_RELOC_SPARC_OLO10
:
3504 val
+= fixP
->tc_fix_data
;
3507 case BFD_RELOC_SPARC13
:
3508 if (! in_signed_range (val
, 0x1fff))
3509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3510 _("relocation overflow"));
3511 insn
|= val
& 0x1fff;
3514 case BFD_RELOC_SPARC_WDISP22
:
3515 val
= (val
>> 2) + 1;
3517 case BFD_RELOC_SPARC_BASE22
:
3518 insn
|= val
& 0x3fffff;
3521 case BFD_RELOC_SPARC_H34
:
3522 if (!fixP
->fx_addsy
)
3526 insn
|= tval
& 0x3fffff;
3530 case BFD_RELOC_SPARC_H44
:
3531 if (!fixP
->fx_addsy
)
3535 insn
|= tval
& 0x3fffff;
3539 case BFD_RELOC_SPARC_M44
:
3540 if (!fixP
->fx_addsy
)
3541 insn
|= (val
>> 12) & 0x3ff;
3544 case BFD_RELOC_SPARC_L44
:
3545 if (!fixP
->fx_addsy
)
3546 insn
|= val
& 0xfff;
3549 case BFD_RELOC_SPARC_HIX22
:
3550 if (!fixP
->fx_addsy
)
3552 val
^= ~(offsetT
) 0;
3553 insn
|= (val
>> 10) & 0x3fffff;
3557 case BFD_RELOC_SPARC_LOX10
:
3558 if (!fixP
->fx_addsy
)
3559 insn
|= 0x1c00 | (val
& 0x3ff);
3562 case BFD_RELOC_NONE
:
3564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3565 _("bad or unhandled relocation type: 0x%02x"),
3570 if (INSN_BIG_ENDIAN
)
3571 bfd_putb32 (insn
, (unsigned char *) buf
);
3573 bfd_putl32 (insn
, (unsigned char *) buf
);
3576 /* Are we finished with this relocation now? */
3577 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3581 /* Translate internal representation of relocation info to BFD target
3585 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3587 static arelent
*relocs
[3];
3589 bfd_reloc_code_real_type code
;
3591 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3594 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3595 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3596 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3598 switch (fixp
->fx_r_type
)
3602 case BFD_RELOC_HI22
:
3603 case BFD_RELOC_LO10
:
3604 case BFD_RELOC_32_PCREL_S2
:
3605 case BFD_RELOC_SPARC13
:
3606 case BFD_RELOC_SPARC22
:
3607 case BFD_RELOC_SPARC_PC22
:
3608 case BFD_RELOC_SPARC_PC10
:
3609 case BFD_RELOC_SPARC_BASE13
:
3610 case BFD_RELOC_SPARC_WDISP10
:
3611 case BFD_RELOC_SPARC_WDISP16
:
3612 case BFD_RELOC_SPARC_WDISP19
:
3613 case BFD_RELOC_SPARC_WDISP22
:
3615 case BFD_RELOC_SPARC_5
:
3616 case BFD_RELOC_SPARC_6
:
3617 case BFD_RELOC_SPARC_7
:
3618 case BFD_RELOC_SPARC_10
:
3619 case BFD_RELOC_SPARC_11
:
3620 case BFD_RELOC_SPARC_HH22
:
3621 case BFD_RELOC_SPARC_HM10
:
3622 case BFD_RELOC_SPARC_LM22
:
3623 case BFD_RELOC_SPARC_PC_HH22
:
3624 case BFD_RELOC_SPARC_PC_HM10
:
3625 case BFD_RELOC_SPARC_PC_LM22
:
3626 case BFD_RELOC_SPARC_H34
:
3627 case BFD_RELOC_SPARC_H44
:
3628 case BFD_RELOC_SPARC_M44
:
3629 case BFD_RELOC_SPARC_L44
:
3630 case BFD_RELOC_SPARC_HIX22
:
3631 case BFD_RELOC_SPARC_LOX10
:
3632 case BFD_RELOC_SPARC_REV32
:
3633 case BFD_RELOC_SPARC_OLO10
:
3634 case BFD_RELOC_SPARC_UA16
:
3635 case BFD_RELOC_SPARC_UA32
:
3636 case BFD_RELOC_SPARC_UA64
:
3637 case BFD_RELOC_8_PCREL
:
3638 case BFD_RELOC_16_PCREL
:
3639 case BFD_RELOC_32_PCREL
:
3640 case BFD_RELOC_64_PCREL
:
3641 case BFD_RELOC_SPARC_PLT32
:
3642 case BFD_RELOC_SPARC_PLT64
:
3643 case BFD_RELOC_VTABLE_ENTRY
:
3644 case BFD_RELOC_VTABLE_INHERIT
:
3645 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3646 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3647 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3648 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3649 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3650 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3651 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3652 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3653 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3654 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3655 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3656 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3657 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3658 case BFD_RELOC_SPARC_TLS_IE_LD
:
3659 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3660 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3661 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3662 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3663 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3664 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3665 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3666 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3667 case BFD_RELOC_SPARC_GOTDATA_OP
:
3668 code
= fixp
->fx_r_type
;
3675 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3676 /* If we are generating PIC code, we need to generate a different
3680 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3682 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3685 #define GOTT_BASE "__GOTT_BASE__"
3686 #define GOTT_INDEX "__GOTT_INDEX__"
3689 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3695 case BFD_RELOC_32_PCREL_S2
:
3696 if (generic_force_reloc (fixp
))
3697 code
= BFD_RELOC_SPARC_WPLT30
;
3699 case BFD_RELOC_HI22
:
3700 code
= BFD_RELOC_SPARC_GOT22
;
3701 if (fixp
->fx_addsy
!= NULL
)
3703 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3704 code
= BFD_RELOC_SPARC_PC22
;
3706 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3707 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3708 code
= BFD_RELOC_HI22
; /* Unchanged. */
3712 case BFD_RELOC_LO10
:
3713 code
= BFD_RELOC_SPARC_GOT10
;
3714 if (fixp
->fx_addsy
!= NULL
)
3716 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3717 code
= BFD_RELOC_SPARC_PC10
;
3719 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3720 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3721 code
= BFD_RELOC_LO10
; /* Unchanged. */
3725 case BFD_RELOC_SPARC13
:
3726 code
= BFD_RELOC_SPARC_GOT13
;
3732 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3734 /* Nothing is aligned in DWARF debugging sections. */
3735 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3738 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3739 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3740 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3744 if (code
== BFD_RELOC_SPARC_OLO10
)
3745 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3747 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3748 if (reloc
->howto
== 0)
3750 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3751 _("internal error: can't export reloc type %d (`%s')"),
3752 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3758 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3761 if (reloc
->howto
->pc_relative
== 0
3762 || code
== BFD_RELOC_SPARC_PC10
3763 || code
== BFD_RELOC_SPARC_PC22
)
3764 reloc
->addend
= fixp
->fx_addnumber
;
3765 else if (sparc_pic_code
3766 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3767 && fixp
->fx_addsy
!= NULL
3768 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3769 || S_IS_WEAK (fixp
->fx_addsy
))
3770 && S_IS_DEFINED (fixp
->fx_addsy
)
3771 && ! S_IS_COMMON (fixp
->fx_addsy
))
3772 reloc
->addend
= fixp
->fx_addnumber
;
3774 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3776 #else /* elf or coff */
3778 if (code
!= BFD_RELOC_32_PCREL_S2
3779 && code
!= BFD_RELOC_SPARC_WDISP22
3780 && code
!= BFD_RELOC_SPARC_WDISP16
3781 && code
!= BFD_RELOC_SPARC_WDISP19
3782 && code
!= BFD_RELOC_SPARC_WDISP10
3783 && code
!= BFD_RELOC_SPARC_WPLT30
3784 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3785 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3786 reloc
->addend
= fixp
->fx_addnumber
;
3787 else if (symbol_section_p (fixp
->fx_addsy
))
3788 reloc
->addend
= (section
->vma
3789 + fixp
->fx_addnumber
3790 + md_pcrel_from (fixp
));
3792 reloc
->addend
= fixp
->fx_offset
;
3795 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3796 on the same location. */
3797 if (code
== BFD_RELOC_SPARC_OLO10
)
3799 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3802 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3804 = symbol_get_bfdsym (section_symbol (absolute_section
));
3805 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3806 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3807 reloc
->addend
= fixp
->tc_fix_data
;
3813 /* We have no need to default values of symbols. */
3816 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
3821 /* Round up a section size to the appropriate boundary. */
3824 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
3827 /* This is not right for ELF; a.out wants it, and COFF will force
3828 the alignment anyways. */
3829 valueT align
= ((valueT
) 1
3830 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3833 /* Turn alignment value into a mask. */
3835 newsize
= (size
+ align
) & ~align
;
3842 /* Exactly what point is a PC-relative offset relative TO?
3843 On the sparc, they're relative to the address of the offset, plus
3844 its size. This gets us to the following instruction.
3845 (??? Is this right? FIXME-SOON) */
3847 md_pcrel_from (fixS
*fixP
)
3851 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3852 if (! sparc_pic_code
3853 || fixP
->fx_addsy
== NULL
3854 || symbol_section_p (fixP
->fx_addsy
))
3855 ret
+= fixP
->fx_size
;
3859 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3870 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3873 return (value
== 1) ? shift
: -1;
3876 /* Sort of like s_lcomm. */
3879 static int max_alignment
= 15;
3883 s_reserve (int ignore ATTRIBUTE_UNUSED
)
3893 name
= input_line_pointer
;
3894 c
= get_symbol_end ();
3895 p
= input_line_pointer
;
3899 if (*input_line_pointer
!= ',')
3901 as_bad (_("Expected comma after name"));
3902 ignore_rest_of_line ();
3906 ++input_line_pointer
;
3908 if ((size
= get_absolute_expression ()) < 0)
3910 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3911 ignore_rest_of_line ();
3916 symbolP
= symbol_find_or_make (name
);
3919 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3920 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3922 as_bad (_("bad .reserve segment -- expected BSS segment"));
3926 if (input_line_pointer
[2] == '.')
3927 input_line_pointer
+= 7;
3929 input_line_pointer
+= 6;
3932 if (*input_line_pointer
== ',')
3934 ++input_line_pointer
;
3937 if (*input_line_pointer
== '\n')
3939 as_bad (_("missing alignment"));
3940 ignore_rest_of_line ();
3944 align
= (int) get_absolute_expression ();
3947 if (align
> max_alignment
)
3949 align
= max_alignment
;
3950 as_warn (_("alignment too large; assuming %d"), align
);
3956 as_bad (_("negative alignment"));
3957 ignore_rest_of_line ();
3963 temp
= mylog2 (align
);
3966 as_bad (_("alignment not a power of 2"));
3967 ignore_rest_of_line ();
3974 record_alignment (bss_section
, align
);
3979 if (!S_IS_DEFINED (symbolP
)
3981 && S_GET_OTHER (symbolP
) == 0
3982 && S_GET_DESC (symbolP
) == 0
3989 segT current_seg
= now_seg
;
3990 subsegT current_subseg
= now_subseg
;
3992 /* Switch to bss. */
3993 subseg_set (bss_section
, 1);
3997 frag_align (align
, 0, 0);
3999 /* Detach from old frag. */
4000 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4001 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4003 symbol_set_frag (symbolP
, frag_now
);
4004 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4005 (offsetT
) size
, (char *) 0);
4008 S_SET_SEGMENT (symbolP
, bss_section
);
4010 subseg_set (current_seg
, current_subseg
);
4013 S_SET_SIZE (symbolP
, size
);
4019 as_warn (_("Ignoring attempt to re-define symbol %s"),
4020 S_GET_NAME (symbolP
));
4023 demand_empty_rest_of_line ();
4027 s_common (int ignore ATTRIBUTE_UNUSED
)
4035 name
= input_line_pointer
;
4036 c
= get_symbol_end ();
4037 /* Just after name is now '\0'. */
4038 p
= input_line_pointer
;
4041 if (*input_line_pointer
!= ',')
4043 as_bad (_("Expected comma after symbol-name"));
4044 ignore_rest_of_line ();
4049 input_line_pointer
++;
4051 if ((temp
= get_absolute_expression ()) < 0)
4053 as_bad (_(".COMMon length (%lu) out of range ignored"),
4054 (unsigned long) temp
);
4055 ignore_rest_of_line ();
4060 symbolP
= symbol_find_or_make (name
);
4062 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4064 as_bad (_("Ignoring attempt to re-define symbol"));
4065 ignore_rest_of_line ();
4068 if (S_GET_VALUE (symbolP
) != 0)
4070 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4072 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4073 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4079 S_SET_VALUE (symbolP
, (valueT
) size
);
4080 S_SET_EXTERNAL (symbolP
);
4083 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4084 if (*input_line_pointer
!= ',')
4086 as_bad (_("Expected comma after common length"));
4087 ignore_rest_of_line ();
4090 input_line_pointer
++;
4092 if (*input_line_pointer
!= '"')
4094 temp
= get_absolute_expression ();
4097 if (temp
> max_alignment
)
4099 temp
= max_alignment
;
4100 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4106 as_bad (_("negative alignment"));
4107 ignore_rest_of_line ();
4112 if (symbol_get_obj (symbolP
)->local
)
4119 old_subsec
= now_subseg
;
4124 align
= mylog2 (temp
);
4128 as_bad (_("alignment not a power of 2"));
4129 ignore_rest_of_line ();
4133 record_alignment (bss_section
, align
);
4134 subseg_set (bss_section
, 0);
4136 frag_align (align
, 0, 0);
4137 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4138 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4139 symbol_set_frag (symbolP
, frag_now
);
4140 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4141 (offsetT
) size
, (char *) 0);
4143 S_SET_SEGMENT (symbolP
, bss_section
);
4144 S_CLEAR_EXTERNAL (symbolP
);
4145 S_SET_SIZE (symbolP
, size
);
4146 subseg_set (old_sec
, old_subsec
);
4149 #endif /* OBJ_ELF */
4152 S_SET_VALUE (symbolP
, (valueT
) size
);
4154 S_SET_ALIGN (symbolP
, temp
);
4155 S_SET_SIZE (symbolP
, size
);
4157 S_SET_EXTERNAL (symbolP
);
4158 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4163 input_line_pointer
++;
4164 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4165 if (*input_line_pointer
== '.')
4166 input_line_pointer
++;
4167 /* @@ Some say data, some say bss. */
4168 if (strncmp (input_line_pointer
, "bss\"", 4)
4169 && strncmp (input_line_pointer
, "data\"", 5))
4171 while (*--input_line_pointer
!= '"')
4173 input_line_pointer
--;
4174 goto bad_common_segment
;
4176 while (*input_line_pointer
++ != '"')
4178 goto allocate_common
;
4181 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4183 demand_empty_rest_of_line ();
4188 p
= input_line_pointer
;
4189 while (*p
&& *p
!= '\n')
4193 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4195 input_line_pointer
= p
;
4196 ignore_rest_of_line ();
4201 /* Handle the .empty pseudo-op. This suppresses the warnings about
4202 invalid delay slot usage. */
4205 s_empty (int ignore ATTRIBUTE_UNUSED
)
4207 /* The easy way to implement is to just forget about the last
4213 s_seg (int ignore ATTRIBUTE_UNUSED
)
4216 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4218 input_line_pointer
+= 6;
4222 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4224 input_line_pointer
+= 6;
4228 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4230 input_line_pointer
+= 7;
4234 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4236 input_line_pointer
+= 5;
4237 /* We only support 2 segments -- text and data -- for now, so
4238 things in the "bss segment" will have to go into data for now.
4239 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4240 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4243 as_bad (_("Unknown segment type"));
4244 demand_empty_rest_of_line ();
4250 subseg_set (data_section
, 1);
4251 demand_empty_rest_of_line ();
4255 s_proc (int ignore ATTRIBUTE_UNUSED
)
4257 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4259 ++input_line_pointer
;
4261 ++input_line_pointer
;
4264 /* This static variable is set by s_uacons to tell sparc_cons_align
4265 that the expression does not need to be aligned. */
4267 static int sparc_no_align_cons
= 0;
4269 /* This static variable is set by sparc_cons to emit requested types
4270 of relocations in cons_fix_new_sparc. */
4272 static const char *sparc_cons_special_reloc
;
4274 /* This handles the unaligned space allocation pseudo-ops, such as
4275 .uaword. .uaword is just like .word, but the value does not need
4279 s_uacons (int bytes
)
4281 /* Tell sparc_cons_align not to align this value. */
4282 sparc_no_align_cons
= 1;
4284 sparc_no_align_cons
= 0;
4287 /* This handles the native word allocation pseudo-op .nword.
4288 For sparc_arch_size 32 it is equivalent to .word, for
4289 sparc_arch_size 64 it is equivalent to .xword. */
4292 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4294 cons (sparc_arch_size
== 32 ? 4 : 8);
4298 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4302 .register %g[2367],{#scratch|symbolname|#ignore}
4306 s_register (int ignore ATTRIBUTE_UNUSED
)
4311 const char *regname
;
4313 if (input_line_pointer
[0] != '%'
4314 || input_line_pointer
[1] != 'g'
4315 || ((input_line_pointer
[2] & ~1) != '2'
4316 && (input_line_pointer
[2] & ~1) != '6')
4317 || input_line_pointer
[3] != ',')
4318 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4319 reg
= input_line_pointer
[2] - '0';
4320 input_line_pointer
+= 4;
4322 if (*input_line_pointer
== '#')
4324 ++input_line_pointer
;
4325 regname
= input_line_pointer
;
4326 c
= get_symbol_end ();
4327 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4328 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4329 if (regname
[0] == 'i')
4336 regname
= input_line_pointer
;
4337 c
= get_symbol_end ();
4339 if (sparc_arch_size
== 64)
4343 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4344 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4345 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4346 as_bad (_("redefinition of global register"));
4350 if (regname
== NULL
)
4351 globals
[reg
] = (symbolS
*) 1;
4356 if (symbol_find (regname
))
4357 as_bad (_("Register symbol %s already defined."),
4360 globals
[reg
] = symbol_make (regname
);
4361 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4363 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4364 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4365 flags
|= BSF_GLOBAL
;
4366 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4367 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4368 S_SET_ALIGN (globals
[reg
], reg
);
4369 S_SET_SIZE (globals
[reg
], 0);
4370 /* Although we actually want undefined_section here,
4371 we have to use absolute_section, because otherwise
4372 generic as code will make it a COM section.
4373 We fix this up in sparc_adjust_symtab. */
4374 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4375 S_SET_OTHER (globals
[reg
], 0);
4376 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4377 ->internal_elf_sym
.st_info
=
4378 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4379 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4380 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4385 *input_line_pointer
= c
;
4387 demand_empty_rest_of_line ();
4390 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4391 symbols which need it. */
4394 sparc_adjust_symtab (void)
4398 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4400 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4401 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4404 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4405 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4408 S_SET_SEGMENT (sym
, undefined_section
);
4413 /* If the --enforce-aligned-data option is used, we require .word,
4414 et. al., to be aligned correctly. We do it by setting up an
4415 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4416 no unexpected alignment was introduced.
4418 The SunOS and Solaris native assemblers enforce aligned data by
4419 default. We don't want to do that, because gcc can deliberately
4420 generate misaligned data if the packed attribute is used. Instead,
4421 we permit misaligned data by default, and permit the user to set an
4422 option to check for it. */
4425 sparc_cons_align (int nbytes
)
4429 /* Only do this if we are enforcing aligned data. */
4430 if (! enforce_aligned_data
)
4433 /* Don't align if this is an unaligned pseudo-op. */
4434 if (sparc_no_align_cons
)
4437 nalign
= mylog2 (nbytes
);
4441 gas_assert (nalign
> 0);
4443 if (now_seg
== absolute_section
)
4445 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4446 as_bad (_("misaligned data"));
4450 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4451 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4453 record_alignment (now_seg
, nalign
);
4456 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4459 sparc_handle_align (fragS
*fragp
)
4464 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4466 switch (fragp
->fr_type
)
4470 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4474 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4485 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4487 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4488 if (INSN_BIG_ENDIAN
)
4489 number_to_chars_bigendian (p
, wval
, 4);
4491 number_to_chars_littleendian (p
, wval
, 4);
4497 if (INSN_BIG_ENDIAN
)
4498 number_to_chars_bigendian (p
, 0x01000000, 4);
4500 number_to_chars_littleendian (p
, 0x01000000, 4);
4502 fragp
->fr_fix
+= fix
;
4512 /* Some special processing for a Sparc ELF file. */
4515 sparc_elf_final_processing (void)
4517 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4518 sort of BFD interface for this. */
4519 if (sparc_arch_size
== 64)
4521 switch (sparc_memory_model
)
4524 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4527 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4533 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4534 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4535 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4536 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4537 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4538 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4542 sparc_cons (expressionS
*exp
, int size
)
4547 sparc_cons_special_reloc
= NULL
;
4548 save
= input_line_pointer
;
4549 if (input_line_pointer
[0] == '%'
4550 && input_line_pointer
[1] == 'r'
4551 && input_line_pointer
[2] == '_')
4553 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4555 input_line_pointer
+= 7;
4556 sparc_cons_special_reloc
= "disp";
4558 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4560 if (size
!= 4 && size
!= 8)
4561 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4564 input_line_pointer
+= 6;
4565 sparc_cons_special_reloc
= "plt";
4568 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4570 if (size
!= 4 && size
!= 8)
4571 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4574 input_line_pointer
+= 13;
4575 sparc_cons_special_reloc
= "tls_dtpoff";
4578 if (sparc_cons_special_reloc
)
4585 if (*input_line_pointer
!= '8')
4587 input_line_pointer
--;
4590 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4594 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4598 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4608 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4609 sparc_cons_special_reloc
, size
* 8, size
);
4613 input_line_pointer
+= 2;
4614 if (*input_line_pointer
!= '(')
4616 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4617 sparc_cons_special_reloc
, size
* 8);
4624 input_line_pointer
= save
;
4625 sparc_cons_special_reloc
= NULL
;
4630 char *end
= ++input_line_pointer
;
4633 while (! is_end_of_line
[(c
= *end
)])
4647 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4648 sparc_cons_special_reloc
, size
* 8);
4654 if (input_line_pointer
!= end
)
4656 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4657 sparc_cons_special_reloc
, size
* 8);
4661 input_line_pointer
++;
4663 c
= *input_line_pointer
;
4664 if (! is_end_of_line
[c
] && c
!= ',')
4665 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4666 sparc_cons_special_reloc
, size
* 8);
4672 if (sparc_cons_special_reloc
== NULL
)
4678 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4679 reloc for a cons. We could use the definition there, except that
4680 we want to handle little endian relocs specially. */
4683 cons_fix_new_sparc (fragS
*frag
,
4685 unsigned int nbytes
,
4688 bfd_reloc_code_real_type r
;
4690 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4691 (nbytes
== 2 ? BFD_RELOC_16
:
4692 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4694 if (target_little_endian_data
4696 && now_seg
->flags
& SEC_ALLOC
)
4697 r
= BFD_RELOC_SPARC_REV32
;
4699 if (sparc_cons_special_reloc
)
4701 if (*sparc_cons_special_reloc
== 'd')
4704 case 1: r
= BFD_RELOC_8_PCREL
; break;
4705 case 2: r
= BFD_RELOC_16_PCREL
; break;
4706 case 4: r
= BFD_RELOC_32_PCREL
; break;
4707 case 8: r
= BFD_RELOC_64_PCREL
; break;
4710 else if (*sparc_cons_special_reloc
== 'p')
4713 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4714 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4719 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4720 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4723 else if (sparc_no_align_cons
)
4727 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4728 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4729 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4734 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4735 sparc_cons_special_reloc
= NULL
;
4739 sparc_cfi_frame_initial_instructions (void)
4741 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4745 sparc_regname_to_dw2regnum (char *regname
)
4753 p
= strchr (q
, regname
[0]);
4756 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4758 return (p
- q
) * 8 + regname
[1] - '0';
4760 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4762 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4764 if (regname
[0] == 'f' || regname
[0] == 'r')
4766 unsigned int regnum
;
4768 regnum
= strtoul (regname
+ 1, &q
, 10);
4771 if (regnum
>= ((regname
[0] == 'f'
4772 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4775 if (regname
[0] == 'f')
4778 if (regnum
>= 64 && (regnum
& 1))
4787 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4789 sparc_cons_special_reloc
= "disp";
4790 sparc_no_align_cons
= 1;
4791 emit_expr (exp
, nbytes
);
4792 sparc_no_align_cons
= 0;
4793 sparc_cons_special_reloc
= NULL
;