1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_sparc_asi (char **, const sparc_asi
**);
40 static int parse_keyword_arg (int (*) (const char *), char **, int *);
41 static int parse_const_expr_arg (char **, int *);
42 static int get_expression (char *);
44 /* Default architecture. */
45 /* ??? The default value should be V8, but sparclite support was added
46 by making it the default. GCC now passes -Asparclite, so maybe sometime in
47 the future we can set this to V8. */
49 #define DEFAULT_ARCH "sparclite"
51 static const char *default_arch
= DEFAULT_ARCH
;
53 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 static int default_init_p
;
57 /* Current architecture. We don't bump up unless necessary. */
58 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
60 /* The maximum architecture level we can bump up to.
61 In a 32 bit environment, don't allow bumping up to v9 by default.
62 The native assembler works this way. The user is required to pass
63 an explicit argument before we'll create v9 object files. However, if
64 we don't see any v9 insns, a v8plus object file is not created. */
65 static enum sparc_opcode_arch_val max_architecture
;
67 /* Either 32 or 64, selects file format. */
68 static int sparc_arch_size
;
69 /* Initial (default) value, recorded separately in case a user option
70 changes the value before md_show_usage is called. */
71 static int default_arch_size
;
74 /* The currently selected v9 memory model. Currently only used for
76 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
79 /* Bitmask of instruction types seen so far, used to populate the
80 GNU attributes section with hwcap information. */
81 static bfd_uint64_t hwcap_seen
;
85 static bfd_uint64_t hwcap_allowed
;
87 static int architecture_requested
;
88 static int warn_on_bump
;
90 /* If warn_on_bump and the needed architecture is higher than this
91 architecture, issue a warning. */
92 static enum sparc_opcode_arch_val warn_after_architecture
;
94 /* Non-zero if the assembler should generate error if an undeclared
95 g[23] register has been used in -64. */
96 static int no_undeclared_regs
;
98 /* Non-zero if the assembler should generate a warning if an
99 unpredictable DCTI (delayed control transfer instruction) couple is
101 static int dcti_couples_detect
;
103 /* Non-zero if we should try to relax jumps and calls. */
104 static int sparc_relax
;
106 /* Non-zero if we are generating PIC code. */
109 /* Non-zero if we should give an error when misaligned data is seen. */
110 static int enforce_aligned_data
;
112 extern int target_big_endian
;
114 static int target_little_endian_data
;
116 /* Symbols for global registers on v9. */
117 static symbolS
*globals
[8];
119 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
120 int sparc_cie_data_alignment
;
122 /* V9 and 86x have big and little endian data, but instructions are always big
123 endian. The sparclet has bi-endian support but both data and insns have
124 the same endianness. Global `target_big_endian' is used for data.
125 The following macro is used for instructions. */
126 #ifndef INSN_BIG_ENDIAN
127 #define INSN_BIG_ENDIAN (target_big_endian \
128 || default_arch_type == sparc86x \
129 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
132 /* Handle of the OPCODE hash table. */
133 static struct hash_control
*op_hash
;
135 static void s_data1 (void);
136 static void s_seg (int);
137 static void s_proc (int);
138 static void s_reserve (int);
139 static void s_common (int);
140 static void s_empty (int);
141 static void s_uacons (int);
142 static void s_ncons (int);
144 static void s_register (int);
147 const pseudo_typeS md_pseudo_table
[] =
149 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
150 {"common", s_common
, 0},
151 {"empty", s_empty
, 0},
152 {"global", s_globl
, 0},
154 {"nword", s_ncons
, 0},
155 {"optim", s_ignore
, 0},
157 {"reserve", s_reserve
, 0},
159 {"skip", s_space
, 0},
162 {"uahalf", s_uacons
, 2},
163 {"uaword", s_uacons
, 4},
164 {"uaxword", s_uacons
, 8},
166 /* These are specific to sparc/svr4. */
167 {"2byte", s_uacons
, 2},
168 {"4byte", s_uacons
, 4},
169 {"8byte", s_uacons
, 8},
170 {"register", s_register
, 0},
175 /* This array holds the chars that always start a comment. If the
176 pre-processor is disabled, these aren't very useful. */
177 const char comment_chars
[] = "!"; /* JF removed '|' from
180 /* This array holds the chars that only start a comment at the beginning of
181 a line. If the line seems to have the form '# 123 filename'
182 .line and .file directives will appear in the pre-processed output. */
183 /* Note that input_file.c hand checks for '#' at the beginning of the
184 first line of the input file. This is because the compiler outputs
185 #NO_APP at the beginning of its output. */
186 /* Also note that comments started like this one will always
187 work if '/' isn't otherwise defined. */
188 const char line_comment_chars
[] = "#";
190 const char line_separator_chars
[] = ";";
192 /* Chars that can be used to separate mant from exp in floating point
194 const char EXP_CHARS
[] = "eE";
196 /* Chars that mean this number is a floating point constant.
199 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
201 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
202 changed in read.c. Ideally it shouldn't have to know about it at all,
203 but nothing is ideal around here. */
205 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
210 unsigned long opcode
;
211 struct nlist
*nlistp
;
215 bfd_reloc_code_real_type reloc
;
218 struct sparc_it the_insn
, set_insn
;
220 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
222 /* Table of arguments to -A.
223 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
224 for this use. That table is for opcodes only. This table is for opcodes
227 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
228 v8plusa
, v9
, v9a
, v9b
, v9_64
};
230 static struct sparc_arch
{
232 const char *opcode_arch
;
233 enum sparc_arch_types arch_type
;
234 /* Default word size, as specified during configuration.
235 A value of zero means can't be used to specify default architecture. */
236 int default_arch_size
;
237 /* Allowable arg to -A? */
239 /* Extra hardware capabilities allowed. These are added to the
240 hardware capabilities associated with the opcode
244 } sparc_arch_table
[] = {
245 { "v6", "v6", v6
, 0, 1, 0, 0 },
246 { "v7", "v7", v7
, 0, 1, 0, 0 },
247 { "v8", "v8", v8
, 32, 1, 0, 0 },
248 { "v8a", "v8", v8
, 32, 1, 0, 0 },
249 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
250 { "sparcvis", "v9a", v9
, 0, 1, 0, 0 },
251 { "sparcvis2", "v9b", v9
, 0, 1, 0, 0 },
252 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_FMAF
, 0 },
253 { "sparcima", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_IMA
, 0 },
254 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
255 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
257 { "sparc4", "v9v", v9
, 0, 1, 0, 0 },
258 { "sparc5", "v9m", v9
, 0, 1, 0, 0 },
259 { "sparc6", "m8", v9
, 0, 1, 0, 0 },
261 { "leon", "leon", leon
, 32, 1, 0, 0 },
262 { "sparclet", "sparclet", sparclet
, 32, 1, 0, 0 },
263 { "sparclite", "sparclite", sparclite
, 32, 1, 0, 0 },
264 { "sparc86x", "sparclite", sparc86x
, 32, 1, 0, 0 },
266 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
267 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
268 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
269 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
270 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
271 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
272 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
273 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
274 { "v8plusm8", "m8", v9
, 0, 1, HWCAP_V8PLUS
, 0 },
276 { "v9", "v9", v9
, 0, 1, 0, 0 },
277 { "v9a", "v9a", v9
, 0, 1, 0, 0 },
278 { "v9b", "v9b", v9
, 0, 1, 0, 0 },
279 { "v9c", "v9c", v9
, 0, 1, 0, 0 },
280 { "v9d", "v9d", v9
, 0, 1, 0, 0 },
281 { "v9e", "v9e", v9
, 0, 1, 0, 0 },
282 { "v9v", "v9v", v9
, 0, 1, 0, 0 },
283 { "v9m", "v9m", v9
, 0, 1, 0, 0 },
284 { "v9m8", "m8", v9
, 0, 1, 0, 0 },
286 /* This exists to allow configure.tgt to pass one
287 value to specify both the default machine and default word size. */
288 { "v9-64", "v9", v9
, 64, 0, 0, 0 },
289 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
292 /* Variant of default_arch */
293 static enum sparc_arch_types default_arch_type
;
295 static struct sparc_arch
*
296 lookup_arch (const char *name
)
298 struct sparc_arch
*sa
;
300 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
301 if (strcmp (sa
->name
, name
) == 0)
303 if (sa
->name
== NULL
)
308 /* Initialize the default opcode arch and word size from the default
309 architecture name. */
312 init_default_arch (void)
314 struct sparc_arch
*sa
= lookup_arch (default_arch
);
317 || sa
->default_arch_size
== 0)
318 as_fatal (_("Invalid default architecture, broken assembler."));
320 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
321 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
322 as_fatal (_("Bad opcode table, broken assembler."));
323 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
325 default_arch_type
= sa
->arch_type
;
328 /* Called by TARGET_MACH. */
333 /* We don't get a chance to initialize anything before we're called,
334 so handle that now. */
335 if (! default_init_p
)
336 init_default_arch ();
338 return sparc_arch_size
== 64 ? bfd_mach_sparc_v9
: bfd_mach_sparc
;
341 /* Called by TARGET_FORMAT. */
344 sparc_target_format (void)
346 /* We don't get a chance to initialize anything before we're called,
347 so handle that now. */
348 if (! default_init_p
)
349 init_default_arch ();
353 return "a.out-sparc-netbsd";
356 if (target_big_endian
)
357 return "a.out-sunos-big";
358 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
359 return "a.out-sunos-big";
361 return "a.out-sparc-little";
363 return "a.out-sunos-big";
374 return "coff-sparc-lynx";
381 return "elf32-sparc-vxworks";
385 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
392 * Invocation line includes a switch not recognized by the base assembler.
393 * See if it's a processor-specific option. These are:
396 * Warn on architecture bumps. See also -A.
398 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
399 * Standard 32 bit architectures.
401 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
402 * This used to only mean 64 bits, but properly specifying it
403 * complicated gcc's ASM_SPECs, so now opcode selection is
404 * specified orthogonally to word size (except when specifying
405 * the default, but that is an internal implementation detail).
406 * -Av8plus, -Av8plusa, -Av8plusb
407 * Same as -Av9{,a,b}.
408 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
409 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
411 * -xarch=v9, -xarch=v9a, -xarch=v9b
412 * Same as -Av9{,a,b} -64, for compatibility with Sun's
415 * Select the architecture and possibly the file format.
416 * Instructions or features not supported by the selected
417 * architecture cause fatal errors.
419 * The default is to start at v6, and bump the architecture up
420 * whenever an instruction is seen at a higher level. In 32 bit
421 * environments, v9 is not bumped up to, the user must pass
424 * If -bump is specified, a warning is printing when bumping to
427 * If an architecture is specified, all instructions must match
428 * that architecture. Any higher level instructions are flagged
429 * as errors. Note that in the 32 bit environment specifying
430 * -Av8plus does not automatically create a v8plus object file, a
431 * v9 insn must be seen.
433 * If both an architecture and -bump are specified, the
434 * architecture starts at the specified level, but bumps are
435 * warnings. Note that we can't set `current_architecture' to
436 * the requested level in this case: in the 32 bit environment,
437 * we still must avoid creating v8plus object files unless v9
441 * Bumping between incompatible architectures is always an
442 * error. For example, from sparclite to v9.
446 const char *md_shortopts
= "A:K:VQ:sq";
449 const char *md_shortopts
= "A:k";
451 const char *md_shortopts
= "A:";
454 struct option md_longopts
[] = {
455 #define OPTION_BUMP (OPTION_MD_BASE)
456 {"bump", no_argument
, NULL
, OPTION_BUMP
},
457 #define OPTION_SPARC (OPTION_MD_BASE + 1)
458 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
459 #define OPTION_XARCH (OPTION_MD_BASE + 2)
460 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
462 #define OPTION_32 (OPTION_MD_BASE + 3)
463 {"32", no_argument
, NULL
, OPTION_32
},
464 #define OPTION_64 (OPTION_MD_BASE + 4)
465 {"64", no_argument
, NULL
, OPTION_64
},
466 #define OPTION_TSO (OPTION_MD_BASE + 5)
467 {"TSO", no_argument
, NULL
, OPTION_TSO
},
468 #define OPTION_PSO (OPTION_MD_BASE + 6)
469 {"PSO", no_argument
, NULL
, OPTION_PSO
},
470 #define OPTION_RMO (OPTION_MD_BASE + 7)
471 {"RMO", no_argument
, NULL
, OPTION_RMO
},
473 #ifdef SPARC_BIENDIAN
474 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
475 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
476 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
477 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
479 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
480 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
481 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
482 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
484 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
485 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
486 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
487 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
489 #define OPTION_RELAX (OPTION_MD_BASE + 14)
490 {"relax", no_argument
, NULL
, OPTION_RELAX
},
491 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
492 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
493 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
494 {"dcti-couples-detect", no_argument
, NULL
, OPTION_DCTI_COUPLES_DETECT
},
495 {NULL
, no_argument
, NULL
, 0}
498 size_t md_longopts_size
= sizeof (md_longopts
);
501 md_parse_option (int c
, const char *arg
)
503 /* We don't get a chance to initialize anything before we're called,
504 so handle that now. */
505 if (! default_init_p
)
506 init_default_arch ();
512 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
517 if (!strncmp (arg
, "v9", 2))
518 md_parse_option (OPTION_64
, NULL
);
521 if (!strncmp (arg
, "v8", 2)
522 || !strncmp (arg
, "v7", 2)
523 || !strncmp (arg
, "v6", 2)
524 || !strcmp (arg
, "sparclet")
525 || !strcmp (arg
, "sparclite")
526 || !strcmp (arg
, "sparc86x"))
527 md_parse_option (OPTION_32
, NULL
);
534 struct sparc_arch
*sa
;
535 enum sparc_opcode_arch_val opcode_arch
;
537 sa
= lookup_arch (arg
);
539 || ! sa
->user_option_p
)
541 if (c
== OPTION_XARCH
)
542 as_bad (_("invalid architecture -xarch=%s"), arg
);
544 as_bad (_("invalid architecture -A%s"), arg
);
548 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
549 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
550 as_fatal (_("Bad opcode table, broken assembler."));
552 if (!architecture_requested
553 || opcode_arch
> max_architecture
)
554 max_architecture
= opcode_arch
;
556 /* The allowed hardware capabilities are the implied by the
557 opcodes arch plus any extra capabilities defined in the GAS
561 | (((bfd_uint64_t
) sparc_opcode_archs
[opcode_arch
].hwcaps2
) << 32)
562 | (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32)
563 | sparc_opcode_archs
[opcode_arch
].hwcaps
564 | sa
->hwcap_allowed
);
565 architecture_requested
= 1;
570 /* Ignore -sparc, used by SunOS make default .s.o rule. */
573 case OPTION_ENFORCE_ALIGNED_DATA
:
574 enforce_aligned_data
= 1;
577 #ifdef SPARC_BIENDIAN
578 case OPTION_LITTLE_ENDIAN
:
579 target_big_endian
= 0;
580 if (default_arch_type
!= sparclet
)
581 as_fatal ("This target does not support -EL");
583 case OPTION_LITTLE_ENDIAN_DATA
:
584 target_little_endian_data
= 1;
585 target_big_endian
= 0;
586 if (default_arch_type
!= sparc86x
587 && default_arch_type
!= v9
)
588 as_fatal ("This target does not support --little-endian-data");
590 case OPTION_BIG_ENDIAN
:
591 target_big_endian
= 1;
605 const char **list
, **l
;
607 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
608 list
= bfd_target_list ();
609 for (l
= list
; *l
!= NULL
; l
++)
611 if (sparc_arch_size
== 32)
613 if (CONST_STRNEQ (*l
, "elf32-sparc"))
618 if (CONST_STRNEQ (*l
, "elf64-sparc"))
623 as_fatal (_("No compiled in support for %d bit object file format"),
627 if (sparc_arch_size
== 64
628 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
629 max_architecture
= SPARC_OPCODE_ARCH_V9
;
634 sparc_memory_model
= MM_TSO
;
638 sparc_memory_model
= MM_PSO
;
642 sparc_memory_model
= MM_RMO
;
650 /* Qy - do emit .comment
651 Qn - do not emit .comment. */
655 /* Use .stab instead of .stab.excl. */
659 /* quick -- Native assembler does fewer checks. */
663 if (strcmp (arg
, "PIC") != 0)
664 as_warn (_("Unrecognized option following -K"));
669 case OPTION_NO_UNDECLARED_REGS
:
670 no_undeclared_regs
= 1;
673 case OPTION_UNDECLARED_REGS
:
674 no_undeclared_regs
= 0;
682 case OPTION_NO_RELAX
:
686 case OPTION_DCTI_COUPLES_DETECT
:
687 dcti_couples_detect
= 1;
698 md_show_usage (FILE *stream
)
700 const struct sparc_arch
*arch
;
703 /* We don't get a chance to initialize anything before we're called,
704 so handle that now. */
705 if (! default_init_p
)
706 init_default_arch ();
708 fprintf (stream
, _("SPARC options:\n"));
710 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
712 if (!arch
->user_option_p
)
714 if (arch
!= &sparc_arch_table
[0])
715 fprintf (stream
, " | ");
716 if (column
+ strlen (arch
->name
) > 70)
719 fputc ('\n', stream
);
721 column
+= 5 + 2 + strlen (arch
->name
);
722 fprintf (stream
, "-A%s", arch
->name
);
724 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
726 if (!arch
->user_option_p
)
728 fprintf (stream
, " | ");
729 if (column
+ strlen (arch
->name
) > 65)
732 fputc ('\n', stream
);
734 column
+= 5 + 7 + strlen (arch
->name
);
735 fprintf (stream
, "-xarch=%s", arch
->name
);
737 fprintf (stream
, _("\n\
738 specify variant of SPARC architecture\n\
739 -bump warn when assembler switches architectures\n\
741 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
742 -relax relax jumps and branches (default)\n\
743 -no-relax avoid changing any jumps and branches\n"));
745 fprintf (stream
, _("\
746 -k generate PIC\n"));
749 fprintf (stream
, _("\
750 -32 create 32 bit object file\n\
751 -64 create 64 bit object file\n"));
752 fprintf (stream
, _("\
753 [default is %d]\n"), default_arch_size
);
754 fprintf (stream
, _("\
755 -TSO use Total Store Ordering\n\
756 -PSO use Partial Store Ordering\n\
757 -RMO use Relaxed Memory Ordering\n"));
758 fprintf (stream
, _("\
759 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
760 fprintf (stream
, _("\
761 -KPIC generate PIC\n\
762 -V print assembler version number\n\
763 -undeclared-regs ignore application global register usage without\n\
764 appropriate .register directive (default)\n\
765 -no-undeclared-regs force error on application global register usage\n\
766 without appropriate .register directive\n\
767 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
772 #ifdef SPARC_BIENDIAN
773 fprintf (stream
, _("\
774 -EL generate code for a little endian machine\n\
775 -EB generate code for a big endian machine\n\
776 --little-endian-data generate code for a machine having big endian\n\
777 instructions and little endian data.\n"));
781 /* Native operand size opcode translation. */
787 } native_op_table
[] =
789 {"ldn", "ld", "ldx"},
790 {"ldna", "lda", "ldxa"},
791 {"stn", "st", "stx"},
792 {"stna", "sta", "stxa"},
793 {"slln", "sll", "sllx"},
794 {"srln", "srl", "srlx"},
795 {"sran", "sra", "srax"},
796 {"casn", "cas", "casx"},
797 {"casna", "casa", "casxa"},
798 {"clrn", "clr", "clrx"},
802 /* sparc64 privileged and hyperprivileged registers. */
804 struct priv_reg_entry
810 struct priv_reg_entry priv_reg_table
[] =
831 {NULL
, -1}, /* End marker. */
834 struct priv_reg_entry hpriv_reg_table
[] =
844 {"hstick_offset", 28},
845 {"hstick_enable", 29},
847 {NULL
, -1}, /* End marker. */
850 /* v9a or later specific ancillary state registers. */
852 struct priv_reg_entry v9a_asr_table
[] =
855 {"sys_tick_cmpr", 25},
859 {"softint_clear", 21},
870 {"clear_softint", 21},
871 {NULL
, -1}, /* End marker. */
875 cmp_reg_entry (const void *parg
, const void *qarg
)
877 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
878 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
880 if (p
->name
== q
->name
)
882 else if (p
->name
== NULL
)
884 else if (q
->name
== NULL
)
887 return strcmp (q
->name
, p
->name
);
890 /* sparc %-pseudo-operations. */
893 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
894 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
896 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
897 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
899 instruction. (Generally they can appear
900 anywhere an immediate operand is
904 /* The name as it appears in assembler. */
906 /* The reloc this pseudo-op translates to. */
907 bfd_reloc_code_real_type reloc
;
908 /* Flags. See F_POP_* above. */
912 struct pop_entry pop_table
[] =
914 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
915 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
916 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
917 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
918 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
919 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
920 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
921 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
922 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
923 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
924 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
925 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
926 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
927 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
928 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
929 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
930 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
931 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
932 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
933 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
934 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
935 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
936 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
937 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
938 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
939 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
940 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
941 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
942 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
943 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
944 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
945 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
946 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
947 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
948 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
949 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
950 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
953 /* Table of %-names that can appear in a sparc assembly program. This
954 table is initialized in md_begin and contains entries for each
955 privileged/hyperprivileged/alternate register and %-pseudo-op. */
968 enum perc_entry_type type
;
969 /* Name of the %-entity. */
973 /* Value. Either a pop or a reg depending on type.*/
976 struct pop_entry
*pop
;
977 struct priv_reg_entry
*reg
;
981 #define NUM_PERC_ENTRIES \
982 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
983 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
984 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
985 + ARRAY_SIZE (pop_table) \
988 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
991 cmp_perc_entry (const void *parg
, const void *qarg
)
993 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
994 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
996 if (p
->name
== q
->name
)
998 else if (p
->name
== NULL
)
1000 else if (q
->name
== NULL
)
1003 return strcmp (q
->name
, p
->name
);
1006 /* This function is called once, at assembler startup time. It should
1007 set up all the tables, etc. that the MD part of the assembler will
1013 const char *retval
= NULL
;
1017 /* We don't get a chance to initialize anything before md_parse_option
1018 is called, and it may not be called, so handle default initialization
1019 now if not already done. */
1020 if (! default_init_p
)
1021 init_default_arch ();
1023 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
1024 op_hash
= hash_new ();
1026 while (i
< (unsigned int) sparc_num_opcodes
)
1028 const char *name
= sparc_opcodes
[i
].name
;
1029 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
1032 as_bad (_("Internal error: can't hash `%s': %s\n"),
1033 sparc_opcodes
[i
].name
, retval
);
1038 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
1040 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1041 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
1046 while (i
< (unsigned int) sparc_num_opcodes
1047 && !strcmp (sparc_opcodes
[i
].name
, name
));
1050 for (i
= 0; native_op_table
[i
].name
; i
++)
1052 const struct sparc_opcode
*insn
;
1053 const char *name
= ((sparc_arch_size
== 32)
1054 ? native_op_table
[i
].name32
1055 : native_op_table
[i
].name64
);
1056 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
1059 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1060 name
, native_op_table
[i
].name
);
1065 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1069 as_bad (_("Internal error: can't hash `%s': %s\n"),
1070 sparc_opcodes
[i
].name
, retval
);
1077 as_fatal (_("Broken assembler. No assembly attempted."));
1079 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1080 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1081 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1082 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1083 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1084 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1086 /* If -bump, record the architecture level at which we start issuing
1087 warnings. The behaviour is different depending upon whether an
1088 architecture was explicitly specified. If it wasn't, we issue warnings
1089 for all upwards bumps. If it was, we don't start issuing warnings until
1090 we need to bump beyond the requested architecture or when we bump between
1091 conflicting architectures. */
1094 && architecture_requested
)
1096 /* `max_architecture' records the requested architecture.
1097 Issue warnings if we go above it. */
1098 warn_after_architecture
= max_architecture
;
1101 /* Find the highest architecture level that doesn't conflict with
1102 the requested one. */
1105 || !architecture_requested
)
1107 enum sparc_opcode_arch_val current_max_architecture
1110 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1111 max_architecture
> warn_after_architecture
;
1113 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1114 current_max_architecture
))
1118 /* Prepare the tables of %-pseudo-ops. */
1120 struct priv_reg_entry
*reg_tables
[]
1121 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1122 struct priv_reg_entry
**reg_table
;
1125 /* Add registers. */
1126 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1128 struct priv_reg_entry
*reg
;
1129 for (reg
= *reg_table
; reg
->name
; reg
++)
1131 struct perc_entry
*p
= &perc_table
[entry
++];
1132 p
->type
= perc_entry_reg
;
1133 p
->name
= reg
->name
;
1134 p
->len
= strlen (reg
->name
);
1139 /* Add %-pseudo-ops. */
1140 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1142 struct perc_entry
*p
= &perc_table
[entry
++];
1143 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1144 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1145 p
->name
= pop_table
[i
].name
;
1146 p
->len
= strlen (pop_table
[i
].name
);
1147 p
->pop
= &pop_table
[i
];
1150 /* Last entry is the sentinel. */
1151 perc_table
[entry
].type
= perc_entry_none
;
1153 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1154 sizeof (perc_table
[0]), cmp_perc_entry
);
1159 /* Called after all assembly has been done. */
1165 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1166 int hwcaps
, hwcaps2
;
1169 if (sparc_arch_size
== 64)
1170 switch (current_architecture
)
1172 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1173 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1174 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1175 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1176 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1177 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1178 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1179 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v9m8
; break;
1180 default: mach
= bfd_mach_sparc_v9
; break;
1183 switch (current_architecture
)
1185 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1186 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1187 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1188 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1189 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1190 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1191 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1192 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1193 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1194 case SPARC_OPCODE_ARCH_M8
: mach
= bfd_mach_sparc_v8plusm8
; break;
1195 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1196 be but for now it is (since that's the way it's always been
1198 default: mach
= bfd_mach_sparc
; break;
1200 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1202 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1203 hwcaps
= hwcap_seen
& U0xffffffff
;
1204 hwcaps2
= hwcap_seen
>> 32;
1207 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1209 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1213 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1216 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1220 /* Sign-extend the value from the architecture word size, so that
1221 0xffffffff is always considered -1 on sparc32. */
1222 if (sparc_arch_size
== 32)
1224 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1225 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1234 /* Return non-zero if VAL is in the range 0 to MAX. */
1237 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1244 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1245 (e.g. -15 to +31). */
1248 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1254 if (val
< ~(max
>> 1))
1260 sparc_ffs (unsigned int mask
)
1267 for (i
= 0; (mask
& 1) == 0; ++i
)
1272 /* Implement big shift right. */
1274 BSR (bfd_vma val
, int amount
)
1276 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1277 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1278 return val
>> amount
;
1281 /* For communication between sparc_ip and get_expression. */
1282 static char *expr_end
;
1284 /* Values for `special_case'.
1285 Instructions that require weird handling because they're longer than
1287 #define SPECIAL_CASE_NONE 0
1288 #define SPECIAL_CASE_SET 1
1289 #define SPECIAL_CASE_SETSW 2
1290 #define SPECIAL_CASE_SETX 3
1291 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1292 #define SPECIAL_CASE_FDIV 4
1294 /* Bit masks of various insns. */
1295 #define NOP_INSN 0x01000000
1296 #define OR_INSN 0x80100000
1297 #define XOR_INSN 0x80180000
1298 #define FMOVS_INSN 0x81A00020
1299 #define SETHI_INSN 0x01000000
1300 #define SLLX_INSN 0x81281000
1301 #define SRA_INSN 0x81380000
1303 /* The last instruction to be assembled. */
1304 static const struct sparc_opcode
*last_insn
;
1305 /* The assembled opcode of `last_insn'. */
1306 static unsigned long last_opcode
;
1308 /* Handle the set and setuw synthetic instructions. */
1311 synthetize_setuw (const struct sparc_opcode
*insn
)
1313 int need_hi22_p
= 0;
1314 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1316 if (the_insn
.exp
.X_op
== O_constant
)
1318 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1320 if (sizeof (offsetT
) > 4
1321 && (the_insn
.exp
.X_add_number
< 0
1322 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1323 as_warn (_("set: number not in 0..4294967295 range"));
1327 if (sizeof (offsetT
) > 4
1328 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1329 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1330 as_warn (_("set: number not in -2147483648..4294967295 range"));
1331 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1335 /* See if operand is absolute and small; skip sethi if so. */
1336 if (the_insn
.exp
.X_op
!= O_constant
1337 || the_insn
.exp
.X_add_number
>= (1 << 12)
1338 || the_insn
.exp
.X_add_number
< -(1 << 12))
1340 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1341 | ((the_insn
.exp
.X_add_number
>> 10)
1342 & (the_insn
.exp
.X_op
== O_constant
1344 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1345 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1346 output_insn (insn
, &the_insn
);
1350 /* See if operand has no low-order bits; skip OR if so. */
1351 if (the_insn
.exp
.X_op
!= O_constant
1352 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1355 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1357 | (the_insn
.exp
.X_add_number
1358 & (the_insn
.exp
.X_op
!= O_constant
1359 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1360 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1361 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1362 output_insn (insn
, &the_insn
);
1366 /* Handle the setsw synthetic instruction. */
1369 synthetize_setsw (const struct sparc_opcode
*insn
)
1373 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1375 if (the_insn
.exp
.X_op
!= O_constant
)
1377 synthetize_setuw (insn
);
1379 /* Need to sign extend it. */
1380 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1381 the_insn
.reloc
= BFD_RELOC_NONE
;
1382 output_insn (insn
, &the_insn
);
1386 if (sizeof (offsetT
) > 4
1387 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1388 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1389 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1391 low32
= the_insn
.exp
.X_add_number
;
1395 synthetize_setuw (insn
);
1401 the_insn
.reloc
= BFD_RELOC_NONE
;
1402 /* See if operand is absolute and small; skip sethi if so. */
1403 if (low32
< -(1 << 12))
1405 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1406 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1407 output_insn (insn
, &the_insn
);
1408 low32
= 0x1c00 | (low32
& 0x3ff);
1409 opc
= RS1 (rd
) | XOR_INSN
;
1412 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1413 | (low32
& 0x1fff));
1414 output_insn (insn
, &the_insn
);
1417 /* Handle the setx synthetic instruction. */
1420 synthetize_setx (const struct sparc_opcode
*insn
)
1422 int upper32
, lower32
;
1423 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1424 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1426 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1427 int need_xor10_p
= 0;
1429 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1430 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1431 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1434 upper_dstreg
= tmpreg
;
1435 /* The tmp reg should not be the dst reg. */
1436 if (tmpreg
== dstreg
)
1437 as_warn (_("setx: temporary register same as destination register"));
1439 /* ??? Obviously there are other optimizations we can do
1440 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1441 doing some of these. Later. If you do change things, try to
1442 change all of this to be table driven as well. */
1443 /* What to output depends on the number if it's constant.
1444 Compute that first, then output what we've decided upon. */
1445 if (the_insn
.exp
.X_op
!= O_constant
)
1447 if (sparc_arch_size
== 32)
1449 /* When arch size is 32, we want setx to be equivalent
1450 to setuw for anything but constants. */
1451 the_insn
.exp
.X_add_number
&= 0xffffffff;
1452 synthetize_setuw (insn
);
1455 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1461 /* Reset X_add_number, we've extracted it as upper32/lower32.
1462 Otherwise fixup_segment will complain about not being able to
1463 write an 8 byte number in a 4 byte field. */
1464 the_insn
.exp
.X_add_number
= 0;
1466 /* Only need hh22 if `or' insn can't handle constant. */
1467 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1470 /* Does bottom part (after sethi) have bits? */
1471 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1472 /* No hh22, but does upper32 still have bits we can't set
1474 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1477 /* If the lower half is all zero, we build the upper half directly
1478 into the dst reg. */
1480 /* Need lower half if number is zero or 0xffffffff00000000. */
1481 || (! need_hh22_p
&& ! need_hm10_p
))
1483 /* No need for sethi if `or' insn can handle constant. */
1484 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1485 /* Note that we can't use a negative constant in the `or'
1486 insn unless the upper 32 bits are all ones. */
1487 || (lower32
< 0 && upper32
!= -1)
1488 || (lower32
>= 0 && upper32
== -1))
1491 if (need_hi22_p
&& upper32
== -1)
1494 /* Does bottom part (after sethi) have bits? */
1495 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1497 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1498 /* Need `or' if we didn't set anything else. */
1499 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1503 /* Output directly to dst reg if lower 32 bits are all zero. */
1504 upper_dstreg
= dstreg
;
1507 if (!upper_dstreg
&& dstreg
)
1508 as_warn (_("setx: illegal temporary register g0"));
1512 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1513 | ((upper32
>> 10) & 0x3fffff));
1514 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1515 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1516 output_insn (insn
, &the_insn
);
1521 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1522 | (((need_xor10_p
? ~lower32
: lower32
)
1523 >> 10) & 0x3fffff));
1524 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1525 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1526 output_insn (insn
, &the_insn
);
1531 the_insn
.opcode
= (OR_INSN
1532 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1535 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1536 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1537 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1538 output_insn (insn
, &the_insn
);
1543 /* FIXME: One nice optimization to do here is to OR the low part
1544 with the highpart if hi22 isn't needed and the low part is
1546 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1549 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1550 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1551 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1552 output_insn (insn
, &the_insn
);
1555 /* If we needed to build the upper part, shift it into place. */
1556 if (need_hh22_p
|| need_hm10_p
)
1558 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1560 the_insn
.reloc
= BFD_RELOC_NONE
;
1561 output_insn (insn
, &the_insn
);
1564 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1567 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1568 | 0x1c00 | (lower32
& 0x3ff));
1569 the_insn
.reloc
= BFD_RELOC_NONE
;
1570 output_insn (insn
, &the_insn
);
1573 /* If we needed to build both upper and lower parts, OR them together. */
1574 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1576 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1578 the_insn
.reloc
= BFD_RELOC_NONE
;
1579 output_insn (insn
, &the_insn
);
1583 /* Main entry point to assemble one instruction. */
1586 md_assemble (char *str
)
1588 const struct sparc_opcode
*insn
;
1592 special_case
= sparc_ip (str
, &insn
);
1596 /* Certain instructions may not appear on delay slots. Check for
1597 these situations. */
1598 if (last_insn
!= NULL
1599 && (last_insn
->flags
& F_DELAYED
) != 0)
1601 /* Before SPARC V9 the effect of having a delayed branch
1602 instruction in the delay slot of a conditional delayed branch
1605 In SPARC V9 DCTI couples are well defined.
1607 However, starting with the UltraSPARC Architecture 2005, DCTI
1608 couples (of all kind) are deprecated and should not be used,
1609 as they may be slow or behave differently to what the
1610 programmer expects. */
1611 if (dcti_couples_detect
1612 && (insn
->flags
& F_DELAYED
) != 0
1613 && ((max_architecture
< SPARC_OPCODE_ARCH_V9
1614 && (last_insn
->flags
& F_CONDBR
) != 0)
1615 || max_architecture
>= SPARC_OPCODE_ARCH_V9C
))
1616 as_warn (_("unpredictable DCTI couple"));
1619 /* We warn about attempts to put a floating point branch in a
1620 delay slot, unless the delay slot has been annulled. */
1621 if ((insn
->flags
& F_FBR
) != 0
1622 /* ??? This test isn't completely accurate. We assume anything with
1623 F_{UNBR,CONDBR,FBR} set is annullable. */
1624 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1625 || (last_opcode
& ANNUL
) == 0))
1626 as_warn (_("FP branch in delay slot"));
1629 /* SPARC before v9 requires a nop instruction between a floating
1630 point instruction and a floating point branch. We insert one
1631 automatically, with a warning. */
1632 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1633 && last_insn
!= NULL
1634 && (insn
->flags
& F_FBR
) != 0
1635 && (last_insn
->flags
& F_FLOAT
) != 0)
1637 struct sparc_it nop_insn
;
1639 nop_insn
.opcode
= NOP_INSN
;
1640 nop_insn
.reloc
= BFD_RELOC_NONE
;
1641 output_insn (insn
, &nop_insn
);
1642 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1645 switch (special_case
)
1647 case SPECIAL_CASE_NONE
:
1649 output_insn (insn
, &the_insn
);
1652 case SPECIAL_CASE_SETSW
:
1653 synthetize_setsw (insn
);
1656 case SPECIAL_CASE_SET
:
1657 synthetize_setuw (insn
);
1660 case SPECIAL_CASE_SETX
:
1661 synthetize_setx (insn
);
1664 case SPECIAL_CASE_FDIV
:
1666 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1668 output_insn (insn
, &the_insn
);
1670 /* According to information leaked from Sun, the "fdiv" instructions
1671 on early SPARC machines would produce incorrect results sometimes.
1672 The workaround is to add an fmovs of the destination register to
1673 itself just after the instruction. This was true on machines
1674 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1675 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1676 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1677 output_insn (insn
, &the_insn
);
1682 as_fatal (_("failed special case insn sanity check"));
1687 get_hwcap_name (bfd_uint64_t mask
)
1689 if (mask
& HWCAP_MUL32
)
1691 if (mask
& HWCAP_DIV32
)
1693 if (mask
& HWCAP_FSMULD
)
1695 if (mask
& HWCAP_V8PLUS
)
1697 if (mask
& HWCAP_POPC
)
1699 if (mask
& HWCAP_VIS
)
1701 if (mask
& HWCAP_VIS2
)
1703 if (mask
& HWCAP_ASI_BLK_INIT
)
1704 return "ASIBlkInit";
1705 if (mask
& HWCAP_FMAF
)
1707 if (mask
& HWCAP_VIS3
)
1709 if (mask
& HWCAP_HPC
)
1711 if (mask
& HWCAP_RANDOM
)
1713 if (mask
& HWCAP_TRANS
)
1715 if (mask
& HWCAP_FJFMAU
)
1717 if (mask
& HWCAP_IMA
)
1719 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1721 if (mask
& HWCAP_AES
)
1723 if (mask
& HWCAP_DES
)
1725 if (mask
& HWCAP_KASUMI
)
1727 if (mask
& HWCAP_CAMELLIA
)
1729 if (mask
& HWCAP_MD5
)
1731 if (mask
& HWCAP_SHA1
)
1733 if (mask
& HWCAP_SHA256
)
1735 if (mask
& HWCAP_SHA512
)
1737 if (mask
& HWCAP_MPMUL
)
1739 if (mask
& HWCAP_MONT
)
1741 if (mask
& HWCAP_PAUSE
)
1743 if (mask
& HWCAP_CBCOND
)
1745 if (mask
& HWCAP_CRC32C
)
1749 if (mask
& HWCAP2_FJATHPLUS
)
1751 if (mask
& HWCAP2_VIS3B
)
1753 if (mask
& HWCAP2_ADP
)
1755 if (mask
& HWCAP2_SPARC5
)
1757 if (mask
& HWCAP2_MWAIT
)
1759 if (mask
& HWCAP2_XMPMUL
)
1761 if (mask
& HWCAP2_XMONT
)
1763 if (mask
& HWCAP2_NSEC
)
1765 if (mask
& HWCAP2_SPARC6
)
1767 if (mask
& HWCAP2_ONADDSUB
)
1769 if (mask
& HWCAP2_ONMUL
)
1771 if (mask
& HWCAP2_ONDIV
)
1773 if (mask
& HWCAP2_DICTUNP
)
1775 if (mask
& HWCAP2_FPCMPSHL
)
1777 if (mask
& HWCAP2_RLE
)
1779 if (mask
& HWCAP2_SHA3
)
1785 /* Subroutine of md_assemble to do the actual parsing. */
1788 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1790 const char *error_message
= "";
1794 const struct sparc_opcode
*insn
;
1796 unsigned long opcode
;
1797 unsigned int mask
= 0;
1801 int special_case
= SPECIAL_CASE_NONE
;
1802 const sparc_asi
*sasi
= NULL
;
1809 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1826 as_bad (_("Unknown opcode: `%s'"), str
);
1828 return special_case
;
1830 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1834 as_bad (_("Unknown opcode: `%s'"), str
);
1835 return special_case
;
1845 opcode
= insn
->match
;
1846 memset (&the_insn
, '\0', sizeof (the_insn
));
1847 the_insn
.reloc
= BFD_RELOC_NONE
;
1850 /* Build the opcode, checking as we go to make sure that the
1852 for (args
= insn
->args
;; ++args
)
1860 /* Parse a series of masks. */
1867 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1870 error_message
= _(": invalid membar mask name");
1876 if (*s
== '|' || *s
== '+')
1884 if (! parse_const_expr_arg (&s
, &kmask
))
1886 error_message
= _(": invalid membar mask expression");
1889 if (kmask
< 0 || kmask
> 127)
1891 error_message
= _(": invalid membar mask number");
1896 opcode
|= MEMBAR (kmask
);
1904 if (! parse_const_expr_arg (&s
, &smask
))
1906 error_message
= _(": invalid siam mode expression");
1909 if (smask
< 0 || smask
> 7)
1911 error_message
= _(": invalid siam mode number");
1922 /* Parse a prefetch function. */
1925 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1927 error_message
= _(": invalid prefetch function name");
1933 if (! parse_const_expr_arg (&s
, &fcn
))
1935 error_message
= _(": invalid prefetch function expression");
1938 if (fcn
< 0 || fcn
> 31)
1940 error_message
= _(": invalid prefetch function number");
1950 /* Parse a sparc64 privileged register. */
1953 struct priv_reg_entry
*p
;
1954 unsigned int len
= 9999999; /* Init to make gcc happy. */
1957 for (p
= priv_reg_table
; p
->name
; p
++)
1958 if (p
->name
[0] == s
[0])
1960 len
= strlen (p
->name
);
1961 if (strncmp (p
->name
, s
, len
) == 0)
1967 error_message
= _(": unrecognizable privileged register");
1971 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1973 error_message
= _(": unrecognizable privileged register");
1982 error_message
= _(": unrecognizable privileged register");
1988 /* Parse a sparc64 hyperprivileged register. */
1991 struct priv_reg_entry
*p
;
1992 unsigned int len
= 9999999; /* Init to make gcc happy. */
1995 for (p
= hpriv_reg_table
; p
->name
; p
++)
1996 if (p
->name
[0] == s
[0])
1998 len
= strlen (p
->name
);
1999 if (strncmp (p
->name
, s
, len
) == 0)
2005 error_message
= _(": unrecognizable hyperprivileged register");
2009 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
2011 error_message
= _(": unrecognizable hyperprivileged register");
2020 error_message
= _(": unrecognizable hyperprivileged register");
2026 /* Parse a v9a or later ancillary state register. */
2029 struct priv_reg_entry
*p
;
2030 unsigned int len
= 9999999; /* Init to make gcc happy. */
2033 for (p
= v9a_asr_table
; p
->name
; p
++)
2034 if (p
->name
[0] == s
[0])
2036 len
= strlen (p
->name
);
2037 if (strncmp (p
->name
, s
, len
) == 0)
2043 error_message
= _(": unrecognizable ancillary state register");
2047 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
2049 error_message
= _(": unrecognizable ancillary state register");
2058 error_message
= _(": unrecognizable ancillary state register");
2064 if (strncmp (s
, "%asr", 4) == 0)
2072 while (ISDIGIT (*s
))
2074 num
= num
* 10 + *s
- '0';
2078 /* We used to check here for the asr number to
2079 be between 16 and 31 in V9 and later, as
2080 mandated by the section C.1.1 "Register
2081 Names" in the SPARC spec. However, we
2082 decided to remove this restriction as a) it
2083 introduces problems when new V9 asr registers
2084 are introduced, b) the Solaris assembler
2085 doesn't implement this restriction and c) the
2086 restriction will go away in future revisions
2087 of the Oracle SPARC Architecture. */
2089 if (num
< 0 || 31 < num
)
2091 error_message
= _(": asr number must be between 0 and 31");
2095 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2100 error_message
= _(": expecting %asrN");
2107 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2111 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2117 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2122 if (s
[0] == '0' && s
[1] == 'x')
2125 while (ISXDIGIT (*s
))
2128 num
|= hex_value (*s
);
2134 while (ISDIGIT (*s
))
2136 num
= num
* 10 + *s
- '0';
2140 if (num
< 0 || num
> 31)
2142 error_message
= _(": crypto immediate must be between 0 and 31");
2146 opcode
|= RS3 (num
);
2151 error_message
= _(": expecting crypto immediate");
2156 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2157 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2158 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2160 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2161 /* These fields are unsigned, but for upward compatibility,
2162 allow negative values as well. */
2166 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2167 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2168 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2170 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2171 /* These fields are unsigned, but for upward compatibility,
2172 allow negative values as well. */
2176 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2181 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2186 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2191 if (*s
== 'p' && s
[1] == 'n')
2199 if (*s
== 'p' && s
[1] == 't')
2211 if ((strncmp (s
, "%icc", 4) == 0)
2212 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2224 if ((strncmp (s
, "%xcc", 4) == 0)
2225 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2237 if (strncmp (s
, "%fcc0", 5) == 0)
2249 if (strncmp (s
, "%fcc1", 5) == 0)
2261 if (strncmp (s
, "%fcc2", 5) == 0)
2273 if (strncmp (s
, "%fcc3", 5) == 0)
2281 if (strncmp (s
, "%pc", 3) == 0)
2289 if (strncmp (s
, "%tick", 5) == 0)
2296 case '\0': /* End of args. */
2297 if (s
[0] == ',' && s
[1] == '%')
2301 const struct perc_entry
*p
;
2303 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2304 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2305 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2307 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2310 if (s
[p
->len
+ 2] != '(')
2312 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2313 return special_case
;
2316 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2317 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2319 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2321 return special_case
;
2324 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2325 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2326 || the_insn
.exp
.X_add_number
!= 0
2327 || the_insn
.exp
.X_add_symbol
2328 != symbol_find_or_make ("__tls_get_addr")))
2330 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2332 return special_case
;
2335 the_insn
.reloc
= p
->pop
->reloc
;
2336 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2339 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2342 else if (*s1
== ')')
2351 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2352 return special_case
;
2356 (void) get_expression (s
);
2376 case '[': /* These must match exactly. */
2384 case '#': /* Must be at least one digit. */
2387 while (ISDIGIT (*s
))
2395 case 'C': /* Coprocessor state register. */
2396 if (strncmp (s
, "%csr", 4) == 0)
2403 case 'b': /* Next operand is a coprocessor register. */
2406 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2411 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2425 opcode
|= mask
<< 14;
2433 opcode
|= mask
<< 25;
2439 case 'r': /* next operand must be a register */
2449 case 'f': /* frame pointer */
2457 case 'g': /* global register */
2466 case 'i': /* in register */
2470 mask
= c
- '0' + 24;
2475 case 'l': /* local register */
2479 mask
= (c
- '0' + 16);
2484 case 'o': /* out register */
2488 mask
= (c
- '0' + 8);
2493 case 's': /* stack pointer */
2501 case 'r': /* any register */
2502 if (!ISDIGIT ((c
= *s
++)))
2519 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2535 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2536 && no_undeclared_regs
&& ! globals
[mask
])
2537 as_bad (_("detected global register use not covered by .register pseudo-op"));
2539 /* Got the register, now figure out where
2540 it goes in the opcode. */
2544 opcode
|= mask
<< 14;
2552 opcode
|= mask
<< 25;
2556 opcode
|= (mask
<< 25) | (mask
<< 14);
2560 opcode
|= (mask
<< 25) | (mask
<< 0);
2566 case 'e': /* next operand is a floating point register */
2589 && ((format
= *s
) == 'f'
2594 for (mask
= 0; ISDIGIT (*s
); ++s
)
2596 mask
= 10 * mask
+ (*s
- '0');
2597 } /* read the number */
2607 /* register must be even numbered */
2617 /* register must be multiple of 4 */
2626 /* register must be multiple of 8 */
2630 if (*args
== '\'' && mask
< 48)
2632 /* register must be higher or equal than %f48 */
2638 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2639 error_message
= _(": There are only 64 f registers; [0-63]");
2641 error_message
= _(": There are only 32 f registers; [0-31]");
2644 else if (mask
>= 32)
2646 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2648 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2651 = _(": There are only 32 single precision f registers; [0-31]");
2655 mask
-= 31; /* wrap high bit */
2659 error_message
= _(": There are only 32 f registers; [0-31]");
2667 } /* if not an 'f' register. */
2669 if (*args
== '}' && mask
!= RS2 (opcode
))
2672 = _(": Instruction requires frs2 and frsd must be the same register");
2682 opcode
|= RS1 (mask
);
2689 opcode
|= RS2 (mask
);
2693 opcode
|= RS2 (mask
& 0xe);
2698 opcode
|= RS3 (mask
);
2706 opcode
|= RD (mask
);
2715 if (strncmp (s
, "%fsr", 4) == 0)
2723 if (strncmp (s
, "%efsr", 5) == 0)
2730 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2731 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2734 case 'l': /* 22 bit PC relative immediate */
2735 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2739 case 'L': /* 30 bit immediate */
2740 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2745 case 'n': /* 22 bit immediate */
2746 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2749 case 'i': /* 13 bit immediate */
2750 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2760 const char *op_arg
= NULL
;
2761 static expressionS op_exp
;
2762 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2764 /* Check for %hi, etc. */
2767 const struct perc_entry
*p
;
2769 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2770 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2771 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2773 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2776 if (s
[p
->len
+ 1] != '(')
2778 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2779 return special_case
;
2783 the_insn
.reloc
= p
->pop
->reloc
;
2785 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2788 /* Note that if the get_expression() fails, we will still
2789 have created U entries in the symbol table for the
2790 'symbols' in the input string. Try not to create U
2791 symbols for registers, etc. */
2793 /* This stuff checks to see if the expression ends in
2794 +%reg. If it does, it removes the register from
2795 the expression, and re-sets 's' to point to the
2802 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2805 else if (*s1
== ')')
2814 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2815 return special_case
;
2819 (void) get_expression (s
);
2823 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2824 return special_case
;
2827 if (*s
== ',' || *s
== ']' || !*s
)
2829 if (*s
!= '+' && *s
!= '-')
2831 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2832 return special_case
;
2836 op_exp
= the_insn
.exp
;
2837 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2840 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2843 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2845 if (s1
[-2] == '%' && s1
[-3] == '+')
2847 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2849 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2856 if (op_arg
&& s1
== s
+ 1)
2857 the_insn
.exp
.X_op
= O_absent
;
2859 (void) get_expression (s
);
2871 (void) get_expression (s
);
2879 the_insn
.exp2
= the_insn
.exp
;
2880 the_insn
.exp
= op_exp
;
2881 if (the_insn
.exp2
.X_op
== O_absent
)
2882 the_insn
.exp2
.X_op
= O_illegal
;
2883 else if (the_insn
.exp
.X_op
== O_absent
)
2885 the_insn
.exp
= the_insn
.exp2
;
2886 the_insn
.exp2
.X_op
= O_illegal
;
2888 else if (the_insn
.exp
.X_op
== O_constant
)
2890 valueT val
= the_insn
.exp
.X_add_number
;
2891 switch (the_insn
.reloc
)
2896 case BFD_RELOC_SPARC_HH22
:
2897 val
= BSR (val
, 32);
2900 case BFD_RELOC_SPARC_LM22
:
2901 case BFD_RELOC_HI22
:
2902 val
= (val
>> 10) & 0x3fffff;
2905 case BFD_RELOC_SPARC_HM10
:
2906 val
= BSR (val
, 32);
2909 case BFD_RELOC_LO10
:
2913 case BFD_RELOC_SPARC_H34
:
2918 case BFD_RELOC_SPARC_H44
:
2923 case BFD_RELOC_SPARC_M44
:
2928 case BFD_RELOC_SPARC_L44
:
2932 case BFD_RELOC_SPARC_HIX22
:
2934 val
= (val
>> 10) & 0x3fffff;
2937 case BFD_RELOC_SPARC_LOX10
:
2938 val
= (val
& 0x3ff) | 0x1c00;
2941 the_insn
.exp
= the_insn
.exp2
;
2942 the_insn
.exp
.X_add_number
+= val
;
2943 the_insn
.exp2
.X_op
= O_illegal
;
2944 the_insn
.reloc
= old_reloc
;
2946 else if (the_insn
.exp2
.X_op
!= O_constant
)
2948 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2949 return special_case
;
2953 if (old_reloc
!= BFD_RELOC_SPARC13
2954 || the_insn
.reloc
!= BFD_RELOC_LO10
2955 || sparc_arch_size
!= 64
2958 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2959 return special_case
;
2961 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2965 /* Check for constants that don't require emitting a reloc. */
2966 if (the_insn
.exp
.X_op
== O_constant
2967 && the_insn
.exp
.X_add_symbol
== 0
2968 && the_insn
.exp
.X_op_symbol
== 0)
2970 /* For pc-relative call instructions, we reject
2971 constants to get better code. */
2973 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2974 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2976 error_message
= _(": PC-relative operand can't be a constant");
2980 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2981 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2983 error_message
= _(": TLS operand can't be a constant");
2987 /* Constants that won't fit are checked in md_apply_fix
2988 and bfd_install_relocation.
2989 ??? It would be preferable to install the constants
2990 into the insn here and save having to create a fixS
2991 for each one. There already exists code to handle
2992 all the various cases (e.g. in md_apply_fix and
2993 bfd_install_relocation) so duplicating all that code
2994 here isn't right. */
2996 /* This is a special case to handle cbcond instructions
2997 properly, which can need two relocations. The first
2998 one is for the 5-bit immediate field and the latter
2999 is going to be for the WDISP10 branch part. We
3000 handle the R_SPARC_5 immediate directly here so that
3001 we don't need to add support for multiple relocations
3002 in one instruction just yet. */
3003 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
3004 && ((insn
->match
& OP(0x3)) == 0))
3006 valueT val
= the_insn
.exp
.X_add_number
;
3008 the_insn
.reloc
= BFD_RELOC_NONE
;
3009 if (! in_bitfield_range (val
, 0x1f))
3011 error_message
= _(": Immediate value in cbcond is out of range.");
3014 opcode
|= val
& 0x1f;
3035 if (! parse_sparc_asi (&s
, &sasi
))
3037 error_message
= _(": invalid ASI name");
3044 if (! parse_const_expr_arg (&s
, &asi
))
3046 error_message
= _(": invalid ASI expression");
3049 if (asi
< 0 || asi
> 255)
3051 error_message
= _(": invalid ASI number");
3055 opcode
|= ASI (asi
);
3057 } /* Alternate space. */
3060 if (strncmp (s
, "%psr", 4) == 0)
3067 case 'q': /* Floating point queue. */
3068 if (strncmp (s
, "%fq", 3) == 0)
3075 case 'Q': /* Coprocessor queue. */
3076 if (strncmp (s
, "%cq", 3) == 0)
3084 if (strcmp (str
, "set") == 0
3085 || strcmp (str
, "setuw") == 0)
3087 special_case
= SPECIAL_CASE_SET
;
3090 else if (strcmp (str
, "setsw") == 0)
3092 special_case
= SPECIAL_CASE_SETSW
;
3095 else if (strcmp (str
, "setx") == 0)
3097 special_case
= SPECIAL_CASE_SETX
;
3100 else if (strncmp (str
, "fdiv", 4) == 0)
3102 special_case
= SPECIAL_CASE_FDIV
;
3108 if (strncmp (s
, "%asi", 4) != 0)
3114 if (strncmp (s
, "%fprs", 5) != 0)
3120 if (strncmp (s
, "%mcdper",7) != 0)
3126 if (strncmp (s
, "%entropy", 8) != 0)
3132 if (strncmp (s
, "%ccr", 4) != 0)
3138 if (strncmp (s
, "%tbr", 4) != 0)
3144 if (strncmp (s
, "%wim", 4) != 0)
3153 /* Parse a 2-bit immediate. */
3154 if (! parse_const_expr_arg (&s
, &imm2
))
3156 error_message
= _(": non-immdiate imm2 operand");
3159 if ((imm2
& ~0x3) != 0)
3161 error_message
= _(": imm2 immediate operand out of range (0-3)");
3165 opcode
|= ((imm2
& 0x2) << 3) | (imm2
& 0x1);
3171 char *push
= input_line_pointer
;
3174 input_line_pointer
= s
;
3176 if (e
.X_op
== O_constant
)
3178 int n
= e
.X_add_number
;
3179 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3180 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3182 opcode
|= e
.X_add_number
<< 5;
3185 as_bad (_("non-immediate OPF operand, ignored"));
3186 s
= input_line_pointer
;
3187 input_line_pointer
= push
;
3192 if (strncmp (s
, "%y", 2) != 0)
3200 /* Parse a sparclet cpreg. */
3202 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3204 error_message
= _(": invalid cpreg name");
3207 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3212 as_fatal (_("failed sanity check."));
3213 } /* switch on arg code. */
3215 /* Break out of for() loop. */
3217 } /* For each arg that we expect. */
3222 /* Args don't match. */
3223 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3224 && (insn
->name
== insn
[1].name
3225 || !strcmp (insn
->name
, insn
[1].name
)))
3233 as_bad (_("Illegal operands%s"), error_message
);
3234 return special_case
;
3239 /* We have a match. Now see if the architecture is OK. */
3240 /* String to use in case of architecture warning. */
3241 const char *msg_str
= str
;
3242 int needed_arch_mask
= insn
->architecture
;
3244 /* Include the ASI architecture needed as well */
3245 if (sasi
&& needed_arch_mask
> sasi
->architecture
)
3247 needed_arch_mask
= sasi
->architecture
;
3248 msg_str
= sasi
->name
;
3252 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3254 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3256 hwcap_seen
|= hwcaps
;
3261 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3262 if (! needed_arch_mask
)
3264 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3267 if (needed_arch_mask
3268 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3271 /* Can we bump up the architecture? */
3272 else if (needed_arch_mask
3273 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3275 enum sparc_opcode_arch_val needed_architecture
=
3276 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3277 & needed_arch_mask
);
3279 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3281 && needed_architecture
> warn_after_architecture
)
3283 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3284 sparc_opcode_archs
[current_architecture
].name
,
3285 sparc_opcode_archs
[needed_architecture
].name
,
3287 warn_after_architecture
= needed_architecture
;
3289 current_architecture
= needed_architecture
;
3293 | (((bfd_uint64_t
) sparc_opcode_archs
[current_architecture
].hwcaps2
) << 32)
3294 | sparc_opcode_archs
[current_architecture
].hwcaps
);
3297 /* ??? This seems to be a bit fragile. What if the next entry in
3298 the opcode table is the one we want and it is supported?
3299 It is possible to arrange the table today so that this can't
3300 happen but what about tomorrow? */
3303 int arch
, printed_one_p
= 0;
3305 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3307 /* Create a list of the architectures that support the insn. */
3308 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3310 arch
= sparc_ffs (needed_arch_mask
);
3311 while ((1 << arch
) <= needed_arch_mask
)
3313 if ((1 << arch
) & needed_arch_mask
)
3317 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3324 as_bad (_("Architecture mismatch on \"%s %s\"."), str
, argsStart
);
3325 as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
3327 sparc_opcode_archs
[max_architecture
].name
);
3328 return special_case
;
3331 /* Make sure the hwcaps used by the instruction are
3332 currently enabled. */
3333 if (hwcaps
& ~hwcap_allowed
)
3335 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3337 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3339 return special_case
;
3341 } /* If no match. */
3344 } /* Forever looking for a match. */
3346 the_insn
.opcode
= opcode
;
3347 return special_case
;
3351 skip_over_keyword (char *q
)
3353 for (q
= q
+ (*q
== '#' || *q
== '%');
3354 ISALNUM (*q
) || *q
== '_';
3361 parse_sparc_asi (char **input_pointer_p
, const sparc_asi
**value_p
)
3363 const sparc_asi
*value
;
3366 p
= *input_pointer_p
;
3367 q
= skip_over_keyword(p
);
3370 value
= sparc_encode_asi (p
);
3375 *input_pointer_p
= q
;
3379 /* Parse an argument that can be expressed as a keyword.
3380 (eg: #StoreStore or %ccfr).
3381 The result is a boolean indicating success.
3382 If successful, INPUT_POINTER is updated. */
3385 parse_keyword_arg (int (*lookup_fn
) (const char *),
3386 char **input_pointerP
,
3392 p
= *input_pointerP
;
3393 q
= skip_over_keyword(p
);
3396 value
= (*lookup_fn
) (p
);
3401 *input_pointerP
= q
;
3405 /* Parse an argument that is a constant expression.
3406 The result is a boolean indicating success. */
3409 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3411 char *save
= input_line_pointer
;
3414 input_line_pointer
= *input_pointerP
;
3415 /* The next expression may be something other than a constant
3416 (say if we're not processing the right variant of the insn).
3417 Don't call expression unless we're sure it will succeed as it will
3418 signal an error (which we want to defer until later). */
3419 /* FIXME: It might be better to define md_operand and have it recognize
3420 things like %asi, etc. but continuing that route through to the end
3421 is a lot of work. */
3422 if (*input_line_pointer
== '%')
3424 input_line_pointer
= save
;
3428 *input_pointerP
= input_line_pointer
;
3429 input_line_pointer
= save
;
3430 if (exp
.X_op
!= O_constant
)
3432 *valueP
= exp
.X_add_number
;
3436 /* Subroutine of sparc_ip to parse an expression. */
3439 get_expression (char *str
)
3444 save_in
= input_line_pointer
;
3445 input_line_pointer
= str
;
3446 seg
= expression (&the_insn
.exp
);
3447 if (seg
!= absolute_section
3448 && seg
!= text_section
3449 && seg
!= data_section
3450 && seg
!= bss_section
3451 && seg
!= undefined_section
)
3453 the_insn
.error
= _("bad segment");
3454 expr_end
= input_line_pointer
;
3455 input_line_pointer
= save_in
;
3458 expr_end
= input_line_pointer
;
3459 input_line_pointer
= save_in
;
3463 /* Subroutine of md_assemble to output one insn. */
3466 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3468 char *toP
= frag_more (4);
3470 /* Put out the opcode. */
3471 if (INSN_BIG_ENDIAN
)
3472 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3474 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3476 /* Put out the symbol-dependent stuff. */
3477 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3479 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3480 (toP
- frag_now
->fr_literal
), /* Where. */
3485 /* Turn off overflow checking in fixup_segment. We'll do our
3486 own overflow checking in md_apply_fix. This is necessary because
3487 the insn size is 4 and fixup_segment will signal an overflow for
3488 large 8 byte quantities. */
3489 fixP
->fx_no_overflow
= 1;
3490 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3491 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3495 last_opcode
= theinsn
->opcode
;
3498 dwarf2_emit_insn (4);
3503 md_atof (int type
, char *litP
, int *sizeP
)
3505 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3508 /* Write a value out to the object file, using the appropriate
3512 md_number_to_chars (char *buf
, valueT val
, int n
)
3514 if (target_big_endian
)
3515 number_to_chars_bigendian (buf
, val
, n
);
3516 else if (target_little_endian_data
3517 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3518 /* Output debug words, which are not in allocated sections, as big
3520 number_to_chars_bigendian (buf
, val
, n
);
3521 else if (target_little_endian_data
|| ! target_big_endian
)
3522 number_to_chars_littleendian (buf
, val
, n
);
3525 /* Apply a fixS to the frags, now that we know the value it ought to
3529 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3531 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3532 offsetT val
= * (offsetT
*) valP
;
3535 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3537 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3540 /* SPARC ELF relocations don't use an addend in the data field. */
3541 if (fixP
->fx_addsy
!= NULL
)
3543 switch (fixP
->fx_r_type
)
3545 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3546 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3547 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3548 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3549 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3550 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3551 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3552 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3553 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3554 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3555 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3556 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3557 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3558 case BFD_RELOC_SPARC_TLS_IE_LD
:
3559 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3560 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3561 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3562 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3563 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3564 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3565 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3566 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3567 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3568 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3569 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3579 /* This is a hack. There should be a better way to
3580 handle this. Probably in terms of howto fields, once
3581 we can look at these fixups in terms of howtos. */
3582 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3583 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3586 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3587 generate a reloc, then we just want to let the reloc addend set
3588 the value. We do not want to also stuff the addend into the
3589 object file. Including the addend in the object file works when
3590 doing a static link, because the linker will ignore the object
3591 file contents. However, the dynamic linker does not ignore the
3592 object file contents. */
3593 if (fixP
->fx_addsy
!= NULL
3594 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3597 /* When generating PIC code, we do not want an addend for a reloc
3598 against a local symbol. We adjust fx_addnumber to cancel out the
3599 value already included in val, and to also cancel out the
3600 adjustment which bfd_install_relocation will create. */
3602 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3603 && fixP
->fx_addsy
!= NULL
3604 && ! S_IS_COMMON (fixP
->fx_addsy
)
3605 && symbol_section_p (fixP
->fx_addsy
))
3606 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3608 /* When generating PIC code, we need to fiddle to get
3609 bfd_install_relocation to do the right thing for a PC relative
3610 reloc against a local symbol which we are going to keep. */
3612 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3613 && fixP
->fx_addsy
!= NULL
3614 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3615 || S_IS_WEAK (fixP
->fx_addsy
))
3616 && S_IS_DEFINED (fixP
->fx_addsy
)
3617 && ! S_IS_COMMON (fixP
->fx_addsy
))
3620 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3624 /* If this is a data relocation, just output VAL. */
3626 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3628 md_number_to_chars (buf
, val
, 1);
3630 else if (fixP
->fx_r_type
== BFD_RELOC_16
3631 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3633 md_number_to_chars (buf
, val
, 2);
3635 else if (fixP
->fx_r_type
== BFD_RELOC_32
3636 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3637 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3639 md_number_to_chars (buf
, val
, 4);
3641 else if (fixP
->fx_r_type
== BFD_RELOC_64
3642 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3644 md_number_to_chars (buf
, val
, 8);
3646 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3647 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3654 /* It's a relocation against an instruction. */
3656 if (INSN_BIG_ENDIAN
)
3657 insn
= bfd_getb32 ((unsigned char *) buf
);
3659 insn
= bfd_getl32 ((unsigned char *) buf
);
3661 switch (fixP
->fx_r_type
)
3663 case BFD_RELOC_32_PCREL_S2
:
3665 /* FIXME: This increment-by-one deserves a comment of why it's
3667 if (! sparc_pic_code
3668 || fixP
->fx_addsy
== NULL
3669 || symbol_section_p (fixP
->fx_addsy
))
3672 insn
|= val
& 0x3fffffff;
3674 /* See if we have a delay slot. In that case we attempt to
3675 optimize several cases transforming CALL instructions
3676 into branches. But we can only do that if the relocation
3677 can be completely resolved here, i.e. if no undefined
3678 symbol is associated with it. */
3679 if (sparc_relax
&& fixP
->fx_addsy
== NULL
3680 && fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3684 #define XCC (2 << 20)
3685 #define COND(x) (((x)&0xf)<<25)
3686 #define CONDA COND(0x8)
3687 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3688 #define INSN_BA (F2(0,2) | CONDA)
3689 #define INSN_OR F3(2, 0x2, 0)
3690 #define INSN_NOP F2(0,4)
3694 /* If the instruction is a call with either:
3696 arithmetic instruction with rd == %o7
3697 where rs1 != %o7 and rs2 if it is register != %o7
3698 then we can optimize if the call destination is near
3699 by changing the call into a branch always. */
3700 if (INSN_BIG_ENDIAN
)
3701 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3703 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3704 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3706 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3707 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3708 || ((delay
& RD (~0)) != RD (O7
))))
3710 if ((delay
& RS1 (~0)) == RS1 (O7
)
3711 || ((delay
& F3I (~0)) == 0
3712 && (delay
& RS2 (~0)) == RS2 (O7
)))
3714 /* Ensure the branch will fit into simm22. */
3715 if ((val
& 0x3fe00000)
3716 && (val
& 0x3fe00000) != 0x3fe00000)
3718 /* Check if the arch is v9 and branch will fit
3720 if (((val
& 0x3c0000) == 0
3721 || (val
& 0x3c0000) == 0x3c0000)
3722 && (sparc_arch_size
== 64
3723 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3725 insn
= INSN_BPA
| (val
& 0x7ffff);
3728 insn
= INSN_BA
| (val
& 0x3fffff);
3729 if (fixP
->fx_where
>= 4
3730 && ((delay
& (0xffffffff ^ RS1 (~0)))
3731 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3736 if (INSN_BIG_ENDIAN
)
3737 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3739 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3740 if ((setter
& (0xffffffff ^ RD (~0)))
3741 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3748 If call foo was replaced with ba, replace
3749 or %rN, %g0, %o7 with nop. */
3750 reg
= (delay
& RS1 (~0)) >> 14;
3751 if (reg
!= ((setter
& RD (~0)) >> 25)
3752 || reg
== G0
|| reg
== O7
)
3755 if (INSN_BIG_ENDIAN
)
3756 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3758 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3763 case BFD_RELOC_SPARC_11
:
3764 if (! in_signed_range (val
, 0x7ff))
3765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3766 _("relocation overflow"));
3767 insn
|= val
& 0x7ff;
3770 case BFD_RELOC_SPARC_10
:
3771 if (! in_signed_range (val
, 0x3ff))
3772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3773 _("relocation overflow"));
3774 insn
|= val
& 0x3ff;
3777 case BFD_RELOC_SPARC_7
:
3778 if (! in_bitfield_range (val
, 0x7f))
3779 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3780 _("relocation overflow"));
3784 case BFD_RELOC_SPARC_6
:
3785 if (! in_bitfield_range (val
, 0x3f))
3786 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3787 _("relocation overflow"));
3791 case BFD_RELOC_SPARC_5
:
3792 if (! in_bitfield_range (val
, 0x1f))
3793 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3794 _("relocation overflow"));
3798 case BFD_RELOC_SPARC_WDISP10
:
3801 || val
<= -(offsetT
) 0x808)
3802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3803 _("relocation overflow"));
3804 /* FIXME: The +1 deserves a comment. */
3805 val
= (val
>> 2) + 1;
3806 insn
|= ((val
& 0x300) << 11)
3807 | ((val
& 0xff) << 5);
3810 case BFD_RELOC_SPARC_WDISP16
:
3813 || val
<= -(offsetT
) 0x20008)
3814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3815 _("relocation overflow"));
3816 /* FIXME: The +1 deserves a comment. */
3817 val
= (val
>> 2) + 1;
3818 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3821 case BFD_RELOC_SPARC_WDISP19
:
3824 || val
<= -(offsetT
) 0x100008)
3825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3826 _("relocation overflow"));
3827 /* FIXME: The +1 deserves a comment. */
3828 val
= (val
>> 2) + 1;
3829 insn
|= val
& 0x7ffff;
3832 case BFD_RELOC_SPARC_HH22
:
3833 val
= BSR (val
, 32);
3836 case BFD_RELOC_SPARC_LM22
:
3837 case BFD_RELOC_HI22
:
3838 if (!fixP
->fx_addsy
)
3839 insn
|= (val
>> 10) & 0x3fffff;
3841 /* FIXME: Need comment explaining why we do this. */
3845 case BFD_RELOC_SPARC22
:
3846 if (val
& ~0x003fffff)
3847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3848 _("relocation overflow"));
3849 insn
|= (val
& 0x3fffff);
3852 case BFD_RELOC_SPARC_HM10
:
3853 val
= BSR (val
, 32);
3856 case BFD_RELOC_LO10
:
3857 if (!fixP
->fx_addsy
)
3858 insn
|= val
& 0x3ff;
3860 /* FIXME: Need comment explaining why we do this. */
3864 case BFD_RELOC_SPARC_OLO10
:
3866 val
+= fixP
->tc_fix_data
;
3869 case BFD_RELOC_SPARC13
:
3870 if (! in_signed_range (val
, 0x1fff))
3871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3872 _("relocation overflow"));
3873 insn
|= val
& 0x1fff;
3876 case BFD_RELOC_SPARC_WDISP22
:
3877 val
= (val
>> 2) + 1;
3879 case BFD_RELOC_SPARC_BASE22
:
3880 insn
|= val
& 0x3fffff;
3883 case BFD_RELOC_SPARC_H34
:
3884 if (!fixP
->fx_addsy
)
3888 insn
|= tval
& 0x3fffff;
3892 case BFD_RELOC_SPARC_H44
:
3893 if (!fixP
->fx_addsy
)
3897 insn
|= tval
& 0x3fffff;
3901 case BFD_RELOC_SPARC_M44
:
3902 if (!fixP
->fx_addsy
)
3903 insn
|= (val
>> 12) & 0x3ff;
3906 case BFD_RELOC_SPARC_L44
:
3907 if (!fixP
->fx_addsy
)
3908 insn
|= val
& 0xfff;
3911 case BFD_RELOC_SPARC_HIX22
:
3912 if (!fixP
->fx_addsy
)
3914 val
^= ~(offsetT
) 0;
3915 insn
|= (val
>> 10) & 0x3fffff;
3919 case BFD_RELOC_SPARC_LOX10
:
3920 if (!fixP
->fx_addsy
)
3921 insn
|= 0x1c00 | (val
& 0x3ff);
3924 case BFD_RELOC_NONE
:
3926 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3927 _("bad or unhandled relocation type: 0x%02x"),
3932 if (INSN_BIG_ENDIAN
)
3933 bfd_putb32 (insn
, (unsigned char *) buf
);
3935 bfd_putl32 (insn
, (unsigned char *) buf
);
3938 /* Are we finished with this relocation now? */
3939 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3943 /* Translate internal representation of relocation info to BFD target
3947 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3949 static arelent
*relocs
[3];
3951 bfd_reloc_code_real_type code
;
3953 relocs
[0] = reloc
= XNEW (arelent
);
3956 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3957 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3958 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3960 switch (fixp
->fx_r_type
)
3968 switch (fixp
->fx_size
)
3971 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3972 _("can not do %d byte pc-relative relocation"),
3974 code
= fixp
->fx_r_type
;
3977 case 1: code
= BFD_RELOC_8_PCREL
; break;
3978 case 2: code
= BFD_RELOC_16_PCREL
; break;
3979 case 4: code
= BFD_RELOC_32_PCREL
; break;
3981 case 8: code
= BFD_RELOC_64_PCREL
; break;
3985 fixp
->fx_addnumber
= fixp
->fx_offset
;
3989 case BFD_RELOC_HI22
:
3990 case BFD_RELOC_LO10
:
3991 case BFD_RELOC_32_PCREL_S2
:
3992 case BFD_RELOC_SPARC13
:
3993 case BFD_RELOC_SPARC22
:
3994 case BFD_RELOC_SPARC_PC22
:
3995 case BFD_RELOC_SPARC_PC10
:
3996 case BFD_RELOC_SPARC_BASE13
:
3997 case BFD_RELOC_SPARC_WDISP10
:
3998 case BFD_RELOC_SPARC_WDISP16
:
3999 case BFD_RELOC_SPARC_WDISP19
:
4000 case BFD_RELOC_SPARC_WDISP22
:
4001 case BFD_RELOC_SPARC_5
:
4002 case BFD_RELOC_SPARC_6
:
4003 case BFD_RELOC_SPARC_7
:
4004 case BFD_RELOC_SPARC_10
:
4005 case BFD_RELOC_SPARC_11
:
4006 case BFD_RELOC_SPARC_HH22
:
4007 case BFD_RELOC_SPARC_HM10
:
4008 case BFD_RELOC_SPARC_LM22
:
4009 case BFD_RELOC_SPARC_PC_HH22
:
4010 case BFD_RELOC_SPARC_PC_HM10
:
4011 case BFD_RELOC_SPARC_PC_LM22
:
4012 case BFD_RELOC_SPARC_H34
:
4013 case BFD_RELOC_SPARC_H44
:
4014 case BFD_RELOC_SPARC_M44
:
4015 case BFD_RELOC_SPARC_L44
:
4016 case BFD_RELOC_SPARC_HIX22
:
4017 case BFD_RELOC_SPARC_LOX10
:
4018 case BFD_RELOC_SPARC_REV32
:
4019 case BFD_RELOC_SPARC_OLO10
:
4020 case BFD_RELOC_SPARC_UA16
:
4021 case BFD_RELOC_SPARC_UA32
:
4022 case BFD_RELOC_SPARC_UA64
:
4023 case BFD_RELOC_8_PCREL
:
4024 case BFD_RELOC_16_PCREL
:
4025 case BFD_RELOC_32_PCREL
:
4026 case BFD_RELOC_64_PCREL
:
4027 case BFD_RELOC_SPARC_PLT32
:
4028 case BFD_RELOC_SPARC_PLT64
:
4029 case BFD_RELOC_VTABLE_ENTRY
:
4030 case BFD_RELOC_VTABLE_INHERIT
:
4031 case BFD_RELOC_SPARC_TLS_GD_HI22
:
4032 case BFD_RELOC_SPARC_TLS_GD_LO10
:
4033 case BFD_RELOC_SPARC_TLS_GD_ADD
:
4034 case BFD_RELOC_SPARC_TLS_GD_CALL
:
4035 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
4036 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
4037 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
4038 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
4039 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
4040 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
4041 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
4042 case BFD_RELOC_SPARC_TLS_IE_HI22
:
4043 case BFD_RELOC_SPARC_TLS_IE_LO10
:
4044 case BFD_RELOC_SPARC_TLS_IE_LD
:
4045 case BFD_RELOC_SPARC_TLS_IE_LDX
:
4046 case BFD_RELOC_SPARC_TLS_IE_ADD
:
4047 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
4048 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
4049 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
4050 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
4051 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
4052 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
4053 case BFD_RELOC_SPARC_GOTDATA_OP
:
4054 code
= fixp
->fx_r_type
;
4061 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
4062 /* If we are generating PIC code, we need to generate a different
4066 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
4068 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
4071 #define GOTT_BASE "__GOTT_BASE__"
4072 #define GOTT_INDEX "__GOTT_INDEX__"
4075 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
4081 case BFD_RELOC_32_PCREL_S2
:
4082 if (generic_force_reloc (fixp
))
4083 code
= BFD_RELOC_SPARC_WPLT30
;
4085 case BFD_RELOC_HI22
:
4086 code
= BFD_RELOC_SPARC_GOT22
;
4087 if (fixp
->fx_addsy
!= NULL
)
4089 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
4090 code
= BFD_RELOC_SPARC_PC22
;
4092 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
4093 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
4094 code
= BFD_RELOC_HI22
; /* Unchanged. */
4098 case BFD_RELOC_LO10
:
4099 code
= BFD_RELOC_SPARC_GOT10
;
4100 if (fixp
->fx_addsy
!= NULL
)
4102 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
4103 code
= BFD_RELOC_SPARC_PC10
;
4105 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
4106 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
4107 code
= BFD_RELOC_LO10
; /* Unchanged. */
4111 case BFD_RELOC_SPARC13
:
4112 code
= BFD_RELOC_SPARC_GOT13
;
4118 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
4120 /* Nothing is aligned in DWARF debugging sections. */
4121 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
4124 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
4125 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
4126 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
4130 if (code
== BFD_RELOC_SPARC_OLO10
)
4131 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
4133 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4134 if (reloc
->howto
== 0)
4136 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4137 _("internal error: can't export reloc type %d (`%s')"),
4138 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
4144 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
4147 if (reloc
->howto
->pc_relative
== 0
4148 || code
== BFD_RELOC_SPARC_PC10
4149 || code
== BFD_RELOC_SPARC_PC22
)
4150 reloc
->addend
= fixp
->fx_addnumber
;
4151 else if (sparc_pic_code
4152 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
4153 && fixp
->fx_addsy
!= NULL
4154 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
4155 || S_IS_WEAK (fixp
->fx_addsy
))
4156 && S_IS_DEFINED (fixp
->fx_addsy
)
4157 && ! S_IS_COMMON (fixp
->fx_addsy
))
4158 reloc
->addend
= fixp
->fx_addnumber
;
4160 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
4162 #else /* elf or coff */
4164 if (code
!= BFD_RELOC_32_PCREL_S2
4165 && code
!= BFD_RELOC_SPARC_WDISP22
4166 && code
!= BFD_RELOC_SPARC_WDISP16
4167 && code
!= BFD_RELOC_SPARC_WDISP19
4168 && code
!= BFD_RELOC_SPARC_WDISP10
4169 && code
!= BFD_RELOC_SPARC_WPLT30
4170 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
4171 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
4172 reloc
->addend
= fixp
->fx_addnumber
;
4173 else if (symbol_section_p (fixp
->fx_addsy
))
4174 reloc
->addend
= (section
->vma
4175 + fixp
->fx_addnumber
4176 + md_pcrel_from (fixp
));
4178 reloc
->addend
= fixp
->fx_offset
;
4181 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4182 on the same location. */
4183 if (code
== BFD_RELOC_SPARC_OLO10
)
4185 relocs
[1] = reloc
= XNEW (arelent
);
4188 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4190 = symbol_get_bfdsym (section_symbol (absolute_section
));
4191 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4192 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4193 reloc
->addend
= fixp
->tc_fix_data
;
4199 /* We have no need to default values of symbols. */
4202 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4207 /* Round up a section size to the appropriate boundary. */
4210 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4213 /* This is not right for ELF; a.out wants it, and COFF will force
4214 the alignment anyways. */
4215 valueT align
= ((valueT
) 1
4216 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
4219 /* Turn alignment value into a mask. */
4221 newsize
= (size
+ align
) & ~align
;
4228 /* Exactly what point is a PC-relative offset relative TO?
4229 On the sparc, they're relative to the address of the offset, plus
4230 its size. This gets us to the following instruction.
4231 (??? Is this right? FIXME-SOON) */
4233 md_pcrel_from (fixS
*fixP
)
4237 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4238 if (! sparc_pic_code
4239 || fixP
->fx_addsy
== NULL
4240 || symbol_section_p (fixP
->fx_addsy
))
4241 ret
+= fixP
->fx_size
;
4245 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4256 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4259 return (value
== 1) ? shift
: -1;
4262 /* Sort of like s_lcomm. */
4265 static int max_alignment
= 15;
4269 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4279 c
= get_symbol_name (&name
);
4280 p
= input_line_pointer
;
4282 SKIP_WHITESPACE_AFTER_NAME ();
4284 if (*input_line_pointer
!= ',')
4286 as_bad (_("Expected comma after name"));
4287 ignore_rest_of_line ();
4291 ++input_line_pointer
;
4293 if ((size
= get_absolute_expression ()) < 0)
4295 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4296 ignore_rest_of_line ();
4301 symbolP
= symbol_find_or_make (name
);
4304 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4305 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4307 as_bad (_("bad .reserve segment -- expected BSS segment"));
4311 if (input_line_pointer
[2] == '.')
4312 input_line_pointer
+= 7;
4314 input_line_pointer
+= 6;
4317 if (*input_line_pointer
== ',')
4319 ++input_line_pointer
;
4322 if (*input_line_pointer
== '\n')
4324 as_bad (_("missing alignment"));
4325 ignore_rest_of_line ();
4329 align
= (int) get_absolute_expression ();
4332 if (align
> max_alignment
)
4334 align
= max_alignment
;
4335 as_warn (_("alignment too large; assuming %d"), align
);
4341 as_bad (_("negative alignment"));
4342 ignore_rest_of_line ();
4348 temp
= mylog2 (align
);
4351 as_bad (_("alignment not a power of 2"));
4352 ignore_rest_of_line ();
4359 record_alignment (bss_section
, align
);
4364 if (!S_IS_DEFINED (symbolP
)
4366 && S_GET_OTHER (symbolP
) == 0
4367 && S_GET_DESC (symbolP
) == 0
4374 segT current_seg
= now_seg
;
4375 subsegT current_subseg
= now_subseg
;
4377 /* Switch to bss. */
4378 subseg_set (bss_section
, 1);
4382 frag_align (align
, 0, 0);
4384 /* Detach from old frag. */
4385 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4386 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4388 symbol_set_frag (symbolP
, frag_now
);
4389 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4390 (offsetT
) size
, (char *) 0);
4393 S_SET_SEGMENT (symbolP
, bss_section
);
4395 subseg_set (current_seg
, current_subseg
);
4398 S_SET_SIZE (symbolP
, size
);
4404 as_warn (_("Ignoring attempt to re-define symbol %s"),
4405 S_GET_NAME (symbolP
));
4408 demand_empty_rest_of_line ();
4412 s_common (int ignore ATTRIBUTE_UNUSED
)
4420 c
= get_symbol_name (&name
);
4421 /* Just after name is now '\0'. */
4422 p
= input_line_pointer
;
4424 SKIP_WHITESPACE_AFTER_NAME ();
4425 if (*input_line_pointer
!= ',')
4427 as_bad (_("Expected comma after symbol-name"));
4428 ignore_rest_of_line ();
4433 input_line_pointer
++;
4435 if ((temp
= get_absolute_expression ()) < 0)
4437 as_bad (_(".COMMon length (%lu) out of range ignored"),
4438 (unsigned long) temp
);
4439 ignore_rest_of_line ();
4444 symbolP
= symbol_find_or_make (name
);
4446 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4448 as_bad (_("Ignoring attempt to re-define symbol"));
4449 ignore_rest_of_line ();
4452 if (S_GET_VALUE (symbolP
) != 0)
4454 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4456 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4457 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4463 S_SET_VALUE (symbolP
, (valueT
) size
);
4464 S_SET_EXTERNAL (symbolP
);
4467 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4468 if (*input_line_pointer
!= ',')
4470 as_bad (_("Expected comma after common length"));
4471 ignore_rest_of_line ();
4474 input_line_pointer
++;
4476 if (*input_line_pointer
!= '"')
4478 temp
= get_absolute_expression ();
4481 if (temp
> max_alignment
)
4483 temp
= max_alignment
;
4484 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4490 as_bad (_("negative alignment"));
4491 ignore_rest_of_line ();
4496 if (symbol_get_obj (symbolP
)->local
)
4503 old_subsec
= now_subseg
;
4508 align
= mylog2 (temp
);
4512 as_bad (_("alignment not a power of 2"));
4513 ignore_rest_of_line ();
4517 record_alignment (bss_section
, align
);
4518 subseg_set (bss_section
, 0);
4520 frag_align (align
, 0, 0);
4521 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4522 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4523 symbol_set_frag (symbolP
, frag_now
);
4524 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4525 (offsetT
) size
, (char *) 0);
4527 S_SET_SEGMENT (symbolP
, bss_section
);
4528 S_CLEAR_EXTERNAL (symbolP
);
4529 S_SET_SIZE (symbolP
, size
);
4530 subseg_set (old_sec
, old_subsec
);
4533 #endif /* OBJ_ELF */
4536 S_SET_VALUE (symbolP
, (valueT
) size
);
4538 S_SET_ALIGN (symbolP
, temp
);
4539 S_SET_SIZE (symbolP
, size
);
4541 S_SET_EXTERNAL (symbolP
);
4542 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4547 input_line_pointer
++;
4548 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4549 if (*input_line_pointer
== '.')
4550 input_line_pointer
++;
4551 /* @@ Some say data, some say bss. */
4552 if (strncmp (input_line_pointer
, "bss\"", 4)
4553 && strncmp (input_line_pointer
, "data\"", 5))
4555 while (*--input_line_pointer
!= '"')
4557 input_line_pointer
--;
4558 goto bad_common_segment
;
4560 while (*input_line_pointer
++ != '"')
4562 goto allocate_common
;
4565 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4567 demand_empty_rest_of_line ();
4572 p
= input_line_pointer
;
4573 while (*p
&& *p
!= '\n')
4577 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4579 input_line_pointer
= p
;
4580 ignore_rest_of_line ();
4585 /* Handle the .empty pseudo-op. This suppresses the warnings about
4586 invalid delay slot usage. */
4589 s_empty (int ignore ATTRIBUTE_UNUSED
)
4591 /* The easy way to implement is to just forget about the last
4597 s_seg (int ignore ATTRIBUTE_UNUSED
)
4600 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4602 input_line_pointer
+= 6;
4606 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4608 input_line_pointer
+= 6;
4612 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4614 input_line_pointer
+= 7;
4618 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4620 input_line_pointer
+= 5;
4621 /* We only support 2 segments -- text and data -- for now, so
4622 things in the "bss segment" will have to go into data for now.
4623 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4624 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4627 as_bad (_("Unknown segment type"));
4628 demand_empty_rest_of_line ();
4634 subseg_set (data_section
, 1);
4635 demand_empty_rest_of_line ();
4639 s_proc (int ignore ATTRIBUTE_UNUSED
)
4641 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4643 ++input_line_pointer
;
4645 ++input_line_pointer
;
4648 /* This static variable is set by s_uacons to tell sparc_cons_align
4649 that the expression does not need to be aligned. */
4651 static int sparc_no_align_cons
= 0;
4653 /* This handles the unaligned space allocation pseudo-ops, such as
4654 .uaword. .uaword is just like .word, but the value does not need
4658 s_uacons (int bytes
)
4660 /* Tell sparc_cons_align not to align this value. */
4661 sparc_no_align_cons
= 1;
4663 sparc_no_align_cons
= 0;
4666 /* This handles the native word allocation pseudo-op .nword.
4667 For sparc_arch_size 32 it is equivalent to .word, for
4668 sparc_arch_size 64 it is equivalent to .xword. */
4671 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4673 cons (sparc_arch_size
== 32 ? 4 : 8);
4677 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4681 .register %g[2367],{#scratch|symbolname|#ignore}
4685 s_register (int ignore ATTRIBUTE_UNUSED
)
4692 if (input_line_pointer
[0] != '%'
4693 || input_line_pointer
[1] != 'g'
4694 || ((input_line_pointer
[2] & ~1) != '2'
4695 && (input_line_pointer
[2] & ~1) != '6')
4696 || input_line_pointer
[3] != ',')
4697 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4698 reg
= input_line_pointer
[2] - '0';
4699 input_line_pointer
+= 4;
4701 if (*input_line_pointer
== '#')
4703 ++input_line_pointer
;
4704 c
= get_symbol_name (®name
);
4705 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4706 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4707 if (regname
[0] == 'i')
4710 regname
= (char *) "";
4714 c
= get_symbol_name (®name
);
4717 if (sparc_arch_size
== 64)
4721 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4722 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4723 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4724 as_bad (_("redefinition of global register"));
4728 if (regname
== NULL
)
4729 globals
[reg
] = (symbolS
*) 1;
4734 if (symbol_find (regname
))
4735 as_bad (_("Register symbol %s already defined."),
4738 globals
[reg
] = symbol_make (regname
);
4739 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4741 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4742 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4743 flags
|= BSF_GLOBAL
;
4744 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4745 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4746 S_SET_ALIGN (globals
[reg
], reg
);
4747 S_SET_SIZE (globals
[reg
], 0);
4748 /* Although we actually want undefined_section here,
4749 we have to use absolute_section, because otherwise
4750 generic as code will make it a COM section.
4751 We fix this up in sparc_adjust_symtab. */
4752 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4753 S_SET_OTHER (globals
[reg
], 0);
4754 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4755 ->internal_elf_sym
.st_info
=
4756 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4757 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4758 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4763 (void) restore_line_pointer (c
);
4765 demand_empty_rest_of_line ();
4768 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4769 symbols which need it. */
4772 sparc_adjust_symtab (void)
4776 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4778 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4779 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4782 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4783 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4786 S_SET_SEGMENT (sym
, undefined_section
);
4791 /* If the --enforce-aligned-data option is used, we require .word,
4792 et. al., to be aligned correctly. We do it by setting up an
4793 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4794 no unexpected alignment was introduced.
4796 The SunOS and Solaris native assemblers enforce aligned data by
4797 default. We don't want to do that, because gcc can deliberately
4798 generate misaligned data if the packed attribute is used. Instead,
4799 we permit misaligned data by default, and permit the user to set an
4800 option to check for it. */
4803 sparc_cons_align (int nbytes
)
4807 /* Only do this if we are enforcing aligned data. */
4808 if (! enforce_aligned_data
)
4811 /* Don't align if this is an unaligned pseudo-op. */
4812 if (sparc_no_align_cons
)
4815 nalign
= mylog2 (nbytes
);
4819 gas_assert (nalign
> 0);
4821 if (now_seg
== absolute_section
)
4823 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4824 as_bad (_("misaligned data"));
4828 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4829 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4831 record_alignment (now_seg
, nalign
);
4834 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4837 sparc_handle_align (fragS
*fragp
)
4842 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4844 switch (fragp
->fr_type
)
4848 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4852 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4863 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4865 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4866 if (INSN_BIG_ENDIAN
)
4867 number_to_chars_bigendian (p
, wval
, 4);
4869 number_to_chars_littleendian (p
, wval
, 4);
4875 if (INSN_BIG_ENDIAN
)
4876 number_to_chars_bigendian (p
, 0x01000000, 4);
4878 number_to_chars_littleendian (p
, 0x01000000, 4);
4880 fragp
->fr_fix
+= fix
;
4890 /* Some special processing for a Sparc ELF file. */
4893 sparc_elf_final_processing (void)
4895 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4896 sort of BFD interface for this. */
4897 if (sparc_arch_size
== 64)
4899 switch (sparc_memory_model
)
4902 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4905 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4911 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4912 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4913 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4914 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4915 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4916 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4920 sparc_cons (expressionS
*exp
, int size
)
4923 const char *sparc_cons_special_reloc
= NULL
;
4926 save
= input_line_pointer
;
4927 if (input_line_pointer
[0] == '%'
4928 && input_line_pointer
[1] == 'r'
4929 && input_line_pointer
[2] == '_')
4931 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4933 input_line_pointer
+= 7;
4934 sparc_cons_special_reloc
= "disp";
4936 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4938 if (size
!= 4 && size
!= 8)
4939 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4942 input_line_pointer
+= 6;
4943 sparc_cons_special_reloc
= "plt";
4946 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4948 if (size
!= 4 && size
!= 8)
4949 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4952 input_line_pointer
+= 13;
4953 sparc_cons_special_reloc
= "tls_dtpoff";
4956 if (sparc_cons_special_reloc
)
4963 if (*input_line_pointer
!= '8')
4965 input_line_pointer
--;
4968 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4972 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4976 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4986 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4987 sparc_cons_special_reloc
, size
* 8, size
);
4991 input_line_pointer
+= 2;
4992 if (*input_line_pointer
!= '(')
4994 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4995 sparc_cons_special_reloc
, size
* 8);
5002 input_line_pointer
= save
;
5003 sparc_cons_special_reloc
= NULL
;
5008 char *end
= ++input_line_pointer
;
5011 while (! is_end_of_line
[(c
= *end
)])
5025 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
5026 sparc_cons_special_reloc
, size
* 8);
5032 if (input_line_pointer
!= end
)
5034 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
5035 sparc_cons_special_reloc
, size
* 8);
5039 input_line_pointer
++;
5041 c
= *input_line_pointer
;
5042 if (! is_end_of_line
[c
] && c
!= ',')
5043 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
5044 sparc_cons_special_reloc
, size
* 8);
5050 if (sparc_cons_special_reloc
== NULL
)
5052 return sparc_cons_special_reloc
;
5057 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5058 reloc for a cons. We could use the definition there, except that
5059 we want to handle little endian relocs specially. */
5062 cons_fix_new_sparc (fragS
*frag
,
5064 unsigned int nbytes
,
5066 const char *sparc_cons_special_reloc
)
5068 bfd_reloc_code_real_type r
;
5070 r
= (nbytes
== 1 ? BFD_RELOC_8
:
5071 (nbytes
== 2 ? BFD_RELOC_16
:
5072 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
5074 if (target_little_endian_data
5076 && now_seg
->flags
& SEC_ALLOC
)
5077 r
= BFD_RELOC_SPARC_REV32
;
5080 /* The Solaris linker does not allow R_SPARC_UA64
5081 relocations for 32-bit executables. */
5082 if (!target_little_endian_data
5083 && sparc_arch_size
!= 64
5084 && r
== BFD_RELOC_64
)
5088 if (sparc_cons_special_reloc
)
5090 if (*sparc_cons_special_reloc
== 'd')
5093 case 1: r
= BFD_RELOC_8_PCREL
; break;
5094 case 2: r
= BFD_RELOC_16_PCREL
; break;
5095 case 4: r
= BFD_RELOC_32_PCREL
; break;
5096 case 8: r
= BFD_RELOC_64_PCREL
; break;
5099 else if (*sparc_cons_special_reloc
== 'p')
5102 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
5103 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
5108 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
5109 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
5112 else if (sparc_no_align_cons
5113 || /* PR 20803 - relocs in the .eh_frame section
5114 need to support unaligned access. */
5115 strcmp (now_seg
->name
, ".eh_frame") == 0)
5119 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
5120 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
5122 /* The Solaris linker does not allow R_SPARC_UA64
5123 relocations for 32-bit executables. */
5124 case 8: r
= sparc_arch_size
== 64 ?
5125 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
5127 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
5133 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
5137 sparc_cfi_frame_initial_instructions (void)
5139 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
5143 sparc_regname_to_dw2regnum (char *regname
)
5153 case 'g': i
= 0; break;
5154 case 'o': i
= 1; break;
5155 case 'l': i
= 2; break;
5156 case 'i': i
= 3; break;
5157 default: i
= -1; break;
5161 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
5163 return i
* 8 + regname
[1] - '0';
5165 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
5167 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
5169 if (regname
[0] == 'f' || regname
[0] == 'r')
5171 unsigned int regnum
;
5173 regnum
= strtoul (regname
+ 1, &q
, 10);
5174 if (q
== NULL
|| *q
)
5176 if (regnum
>= ((regname
[0] == 'f'
5177 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
5180 if (regname
[0] == 'f')
5183 if (regnum
>= 64 && (regnum
& 1))
5192 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
5194 sparc_no_align_cons
= 1;
5195 emit_expr_with_reloc (exp
, nbytes
, "disp");
5196 sparc_no_align_cons
= 0;