1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with GAS; see the file COPYING. If not, write
19 to the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
25 #include "safe-ctype.h"
28 #include "opcode/sparc.h"
29 #include "dw2gencfi.h"
32 #include "elf/sparc.h"
33 #include "dwarf2dbg.h"
36 /* Some ancient Sun C compilers would not take such hex constants as
37 unsigned, and would end up sign-extending them to form an offsetT,
38 so use these constants instead. */
39 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
40 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
42 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
43 static void init_default_arch
PARAMS ((void));
44 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
45 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
46 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
47 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
48 static int sparc_ffs
PARAMS ((unsigned int));
49 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
50 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
51 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
52 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
53 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
54 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
55 static int parse_const_expr_arg
PARAMS ((char **, int *));
56 static int get_expression
PARAMS ((char *str
));
58 /* Default architecture. */
59 /* ??? The default value should be V8, but sparclite support was added
60 by making it the default. GCC now passes -Asparclite, so maybe sometime in
61 the future we can set this to V8. */
63 #define DEFAULT_ARCH "sparclite"
65 static char *default_arch
= DEFAULT_ARCH
;
67 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
69 static int default_init_p
;
71 /* Current architecture. We don't bump up unless necessary. */
72 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
74 /* The maximum architecture level we can bump up to.
75 In a 32 bit environment, don't allow bumping up to v9 by default.
76 The native assembler works this way. The user is required to pass
77 an explicit argument before we'll create v9 object files. However, if
78 we don't see any v9 insns, a v8plus object file is not created. */
79 static enum sparc_opcode_arch_val max_architecture
;
81 /* Either 32 or 64, selects file format. */
82 static int sparc_arch_size
;
83 /* Initial (default) value, recorded separately in case a user option
84 changes the value before md_show_usage is called. */
85 static int default_arch_size
;
88 /* The currently selected v9 memory model. Currently only used for
90 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
93 static int architecture_requested
;
94 static int warn_on_bump
;
96 /* If warn_on_bump and the needed architecture is higher than this
97 architecture, issue a warning. */
98 static enum sparc_opcode_arch_val warn_after_architecture
;
100 /* Non-zero if as should generate error if an undeclared g[23] register
101 has been used in -64. */
102 static int no_undeclared_regs
;
104 /* Non-zero if we should try to relax jumps and calls. */
105 static int sparc_relax
;
107 /* Non-zero if we are generating PIC code. */
110 /* Non-zero if we should give an error when misaligned data is seen. */
111 static int enforce_aligned_data
;
113 extern int target_big_endian
;
115 static int target_little_endian_data
;
117 /* Symbols for global registers on v9. */
118 static symbolS
*globals
[8];
120 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
121 int sparc_cie_data_alignment
;
123 /* V9 and 86x have big and little endian data, but instructions are always big
124 endian. The sparclet has bi-endian support but both data and insns have
125 the same endianness. Global `target_big_endian' is used for data.
126 The following macro is used for instructions. */
127 #ifndef INSN_BIG_ENDIAN
128 #define INSN_BIG_ENDIAN (target_big_endian \
129 || default_arch_type == sparc86x \
130 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
133 /* Handle of the OPCODE hash table. */
134 static struct hash_control
*op_hash
;
136 static int log2
PARAMS ((int));
137 static void s_data1
PARAMS ((void));
138 static void s_seg
PARAMS ((int));
139 static void s_proc
PARAMS ((int));
140 static void s_reserve
PARAMS ((int));
141 static void s_common
PARAMS ((int));
142 static void s_empty
PARAMS ((int));
143 static void s_uacons
PARAMS ((int));
144 static void s_ncons
PARAMS ((int));
146 static void s_register
PARAMS ((int));
149 const pseudo_typeS md_pseudo_table
[] =
151 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
152 {"common", s_common
, 0},
153 {"empty", s_empty
, 0},
154 {"global", s_globl
, 0},
156 {"nword", s_ncons
, 0},
157 {"optim", s_ignore
, 0},
159 {"reserve", s_reserve
, 0},
161 {"skip", s_space
, 0},
164 {"uahalf", s_uacons
, 2},
165 {"uaword", s_uacons
, 4},
166 {"uaxword", s_uacons
, 8},
168 /* These are specific to sparc/svr4. */
169 {"2byte", s_uacons
, 2},
170 {"4byte", s_uacons
, 4},
171 {"8byte", s_uacons
, 8},
172 {"register", s_register
, 0},
177 /* Size of relocation record. */
178 const int md_reloc_size
= 12;
180 /* This array holds the chars that always start a comment. If the
181 pre-processor is disabled, these aren't very useful. */
182 const char comment_chars
[] = "!"; /* JF removed '|' from
185 /* This array holds the chars that only start a comment at the beginning of
186 a line. If the line seems to have the form '# 123 filename'
187 .line and .file directives will appear in the pre-processed output. */
188 /* Note that input_file.c hand checks for '#' at the beginning of the
189 first line of the input file. This is because the compiler outputs
190 #NO_APP at the beginning of its output. */
191 /* Also note that comments started like this one will always
192 work if '/' isn't otherwise defined. */
193 const char line_comment_chars
[] = "#";
195 const char line_separator_chars
[] = ";";
197 /* Chars that can be used to separate mant from exp in floating point
199 const char EXP_CHARS
[] = "eE";
201 /* Chars that mean this number is a floating point constant.
204 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
206 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
207 changed in read.c. Ideally it shouldn't have to know about it at all,
208 but nothing is ideal around here. */
210 #define isoctal(c) ((unsigned) ((c) - '0') < '8')
215 unsigned long opcode
;
216 struct nlist
*nlistp
;
220 bfd_reloc_code_real_type reloc
;
223 struct sparc_it the_insn
, set_insn
;
225 static void output_insn
226 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
228 /* Table of arguments to -A.
229 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
230 for this use. That table is for opcodes only. This table is for opcodes
233 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
234 v8plusa
, v9
, v9a
, v9b
, v9_64
};
236 static struct sparc_arch
{
239 enum sparc_arch_types arch_type
;
240 /* Default word size, as specified during configuration.
241 A value of zero means can't be used to specify default architecture. */
242 int default_arch_size
;
243 /* Allowable arg to -A? */
245 } sparc_arch_table
[] = {
246 { "v6", "v6", v6
, 0, 1 },
247 { "v7", "v7", v7
, 0, 1 },
248 { "v8", "v8", v8
, 32, 1 },
249 { "sparclet", "sparclet", sparclet
, 32, 1 },
250 { "sparclite", "sparclite", sparclite
, 32, 1 },
251 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
252 { "v8plus", "v9", v9
, 0, 1 },
253 { "v8plusa", "v9a", v9
, 0, 1 },
254 { "v8plusb", "v9b", v9
, 0, 1 },
255 { "v9", "v9", v9
, 0, 1 },
256 { "v9a", "v9a", v9
, 0, 1 },
257 { "v9b", "v9b", v9
, 0, 1 },
258 /* This exists to allow configure.in/Makefile.in to pass one
259 value to specify both the default machine and default word size. */
260 { "v9-64", "v9", v9
, 64, 0 },
261 { NULL
, NULL
, v8
, 0, 0 }
264 /* Variant of default_arch */
265 static enum sparc_arch_types default_arch_type
;
267 static struct sparc_arch
*
271 struct sparc_arch
*sa
;
273 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
274 if (strcmp (sa
->name
, name
) == 0)
276 if (sa
->name
== NULL
)
281 /* Initialize the default opcode arch and word size from the default
282 architecture name. */
287 struct sparc_arch
*sa
= lookup_arch (default_arch
);
290 || sa
->default_arch_size
== 0)
291 as_fatal (_("Invalid default architecture, broken assembler."));
293 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
294 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
295 as_fatal (_("Bad opcode table, broken assembler."));
296 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
298 default_arch_type
= sa
->arch_type
;
301 /* Called by TARGET_FORMAT. */
304 sparc_target_format ()
306 /* We don't get a chance to initialize anything before we're called,
307 so handle that now. */
308 if (! default_init_p
)
309 init_default_arch ();
313 return "a.out-sparc-netbsd";
316 if (target_big_endian
)
317 return "a.out-sunos-big";
318 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
319 return "a.out-sunos-big";
321 return "a.out-sparc-little";
323 return "a.out-sunos-big";
334 return "coff-sparc-lynx";
341 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
348 * Invocation line includes a switch not recognized by the base assembler.
349 * See if it's a processor-specific option. These are:
352 * Warn on architecture bumps. See also -A.
354 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
355 * Standard 32 bit architectures.
357 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
358 * This used to only mean 64 bits, but properly specifying it
359 * complicated gcc's ASM_SPECs, so now opcode selection is
360 * specified orthogonally to word size (except when specifying
361 * the default, but that is an internal implementation detail).
362 * -Av8plus, -Av8plusa, -Av8plusb
363 * Same as -Av9{,a,b}.
364 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
365 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
367 * -xarch=v9, -xarch=v9a, -xarch=v9b
368 * Same as -Av9{,a,b} -64, for compatibility with Sun's
371 * Select the architecture and possibly the file format.
372 * Instructions or features not supported by the selected
373 * architecture cause fatal errors.
375 * The default is to start at v6, and bump the architecture up
376 * whenever an instruction is seen at a higher level. In 32 bit
377 * environments, v9 is not bumped up to, the user must pass
380 * If -bump is specified, a warning is printing when bumping to
383 * If an architecture is specified, all instructions must match
384 * that architecture. Any higher level instructions are flagged
385 * as errors. Note that in the 32 bit environment specifying
386 * -Av8plus does not automatically create a v8plus object file, a
387 * v9 insn must be seen.
389 * If both an architecture and -bump are specified, the
390 * architecture starts at the specified level, but bumps are
391 * warnings. Note that we can't set `current_architecture' to
392 * the requested level in this case: in the 32 bit environment,
393 * we still must avoid creating v8plus object files unless v9
397 * Bumping between incompatible architectures is always an
398 * error. For example, from sparclite to v9.
402 const char *md_shortopts
= "A:K:VQ:sq";
405 const char *md_shortopts
= "A:k";
407 const char *md_shortopts
= "A:";
410 struct option md_longopts
[] = {
411 #define OPTION_BUMP (OPTION_MD_BASE)
412 {"bump", no_argument
, NULL
, OPTION_BUMP
},
413 #define OPTION_SPARC (OPTION_MD_BASE + 1)
414 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
415 #define OPTION_XARCH (OPTION_MD_BASE + 2)
416 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
418 #define OPTION_32 (OPTION_MD_BASE + 3)
419 {"32", no_argument
, NULL
, OPTION_32
},
420 #define OPTION_64 (OPTION_MD_BASE + 4)
421 {"64", no_argument
, NULL
, OPTION_64
},
422 #define OPTION_TSO (OPTION_MD_BASE + 5)
423 {"TSO", no_argument
, NULL
, OPTION_TSO
},
424 #define OPTION_PSO (OPTION_MD_BASE + 6)
425 {"PSO", no_argument
, NULL
, OPTION_PSO
},
426 #define OPTION_RMO (OPTION_MD_BASE + 7)
427 {"RMO", no_argument
, NULL
, OPTION_RMO
},
429 #ifdef SPARC_BIENDIAN
430 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
431 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
432 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
433 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
435 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
436 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
437 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
438 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
440 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
441 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
442 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
443 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
445 #define OPTION_RELAX (OPTION_MD_BASE + 14)
446 {"relax", no_argument
, NULL
, OPTION_RELAX
},
447 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
448 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
449 {NULL
, no_argument
, NULL
, 0}
452 size_t md_longopts_size
= sizeof (md_longopts
);
455 md_parse_option (c
, arg
)
459 /* We don't get a chance to initialize anything before we're called,
460 so handle that now. */
461 if (! default_init_p
)
462 init_default_arch ();
468 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
473 if (strncmp (arg
, "v9", 2) != 0)
474 md_parse_option (OPTION_32
, NULL
);
476 md_parse_option (OPTION_64
, NULL
);
482 struct sparc_arch
*sa
;
483 enum sparc_opcode_arch_val opcode_arch
;
485 sa
= lookup_arch (arg
);
487 || ! sa
->user_option_p
)
489 if (c
== OPTION_XARCH
)
490 as_bad (_("invalid architecture -xarch=%s"), arg
);
492 as_bad (_("invalid architecture -A%s"), arg
);
496 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
497 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
498 as_fatal (_("Bad opcode table, broken assembler."));
500 max_architecture
= opcode_arch
;
501 architecture_requested
= 1;
506 /* Ignore -sparc, used by SunOS make default .s.o rule. */
509 case OPTION_ENFORCE_ALIGNED_DATA
:
510 enforce_aligned_data
= 1;
513 #ifdef SPARC_BIENDIAN
514 case OPTION_LITTLE_ENDIAN
:
515 target_big_endian
= 0;
516 if (default_arch_type
!= sparclet
)
517 as_fatal ("This target does not support -EL");
519 case OPTION_LITTLE_ENDIAN_DATA
:
520 target_little_endian_data
= 1;
521 target_big_endian
= 0;
522 if (default_arch_type
!= sparc86x
523 && default_arch_type
!= v9
)
524 as_fatal ("This target does not support --little-endian-data");
526 case OPTION_BIG_ENDIAN
:
527 target_big_endian
= 1;
541 const char **list
, **l
;
543 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
544 list
= bfd_target_list ();
545 for (l
= list
; *l
!= NULL
; l
++)
547 if (sparc_arch_size
== 32)
549 if (strcmp (*l
, "elf32-sparc") == 0)
554 if (strcmp (*l
, "elf64-sparc") == 0)
559 as_fatal (_("No compiled in support for %d bit object file format"),
566 sparc_memory_model
= MM_TSO
;
570 sparc_memory_model
= MM_PSO
;
574 sparc_memory_model
= MM_RMO
;
582 /* Qy - do emit .comment
583 Qn - do not emit .comment. */
587 /* Use .stab instead of .stab.excl. */
591 /* quick -- Native assembler does fewer checks. */
595 if (strcmp (arg
, "PIC") != 0)
596 as_warn (_("Unrecognized option following -K"));
601 case OPTION_NO_UNDECLARED_REGS
:
602 no_undeclared_regs
= 1;
605 case OPTION_UNDECLARED_REGS
:
606 no_undeclared_regs
= 0;
614 case OPTION_NO_RELAX
:
626 md_show_usage (stream
)
629 const struct sparc_arch
*arch
;
632 /* We don't get a chance to initialize anything before we're called,
633 so handle that now. */
634 if (! default_init_p
)
635 init_default_arch ();
637 fprintf (stream
, _("SPARC options:\n"));
639 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
641 if (!arch
->user_option_p
)
643 if (arch
!= &sparc_arch_table
[0])
644 fprintf (stream
, " | ");
645 if (column
+ strlen (arch
->name
) > 70)
648 fputc ('\n', stream
);
650 column
+= 5 + 2 + strlen (arch
->name
);
651 fprintf (stream
, "-A%s", arch
->name
);
653 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
655 if (!arch
->user_option_p
)
657 fprintf (stream
, " | ");
658 if (column
+ strlen (arch
->name
) > 65)
661 fputc ('\n', stream
);
663 column
+= 5 + 7 + strlen (arch
->name
);
664 fprintf (stream
, "-xarch=%s", arch
->name
);
666 fprintf (stream
, _("\n\
667 specify variant of SPARC architecture\n\
668 -bump warn when assembler switches architectures\n\
670 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
671 -relax relax jumps and branches (default)\n\
672 -no-relax avoid changing any jumps and branches\n"));
674 fprintf (stream
, _("\
675 -k generate PIC\n"));
678 fprintf (stream
, _("\
679 -32 create 32 bit object file\n\
680 -64 create 64 bit object file\n"));
681 fprintf (stream
, _("\
682 [default is %d]\n"), default_arch_size
);
683 fprintf (stream
, _("\
684 -TSO use Total Store Ordering\n\
685 -PSO use Partial Store Ordering\n\
686 -RMO use Relaxed Memory Ordering\n"));
687 fprintf (stream
, _("\
688 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
689 fprintf (stream
, _("\
690 -KPIC generate PIC\n\
691 -V print assembler version number\n\
692 -undeclared-regs ignore application global register usage without\n\
693 appropriate .register directive (default)\n\
694 -no-undeclared-regs force error on application global register usage\n\
695 without appropriate .register directive\n\
700 #ifdef SPARC_BIENDIAN
701 fprintf (stream
, _("\
702 -EL generate code for a little endian machine\n\
703 -EB generate code for a big endian machine\n\
704 --little-endian-data generate code for a machine having big endian\n\
705 instructions and little endian data.\n"));
709 /* Native operand size opcode translation. */
715 } native_op_table
[] =
717 {"ldn", "ld", "ldx"},
718 {"ldna", "lda", "ldxa"},
719 {"stn", "st", "stx"},
720 {"stna", "sta", "stxa"},
721 {"slln", "sll", "sllx"},
722 {"srln", "srl", "srlx"},
723 {"sran", "sra", "srax"},
724 {"casn", "cas", "casx"},
725 {"casna", "casa", "casxa"},
726 {"clrn", "clr", "clrx"},
730 /* sparc64 privileged registers. */
732 struct priv_reg_entry
738 struct priv_reg_entry priv_reg_table
[] =
757 {"", -1}, /* End marker. */
760 /* v9a specific asrs. */
762 struct priv_reg_entry v9a_asr_table
[] =
765 {"sys_tick_cmpr", 25},
773 {"clear_softint", 21},
774 {"", -1}, /* End marker. */
778 cmp_reg_entry (parg
, qarg
)
782 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
783 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
785 return strcmp (q
->name
, p
->name
);
788 /* This function is called once, at assembler startup time. It should
789 set up all the tables, etc. that the MD part of the assembler will
795 register const char *retval
= NULL
;
797 register unsigned int i
= 0;
799 /* We don't get a chance to initialize anything before md_parse_option
800 is called, and it may not be called, so handle default initialization
801 now if not already done. */
802 if (! default_init_p
)
803 init_default_arch ();
805 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
806 op_hash
= hash_new ();
808 while (i
< (unsigned int) sparc_num_opcodes
)
810 const char *name
= sparc_opcodes
[i
].name
;
811 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
814 as_bad (_("Internal error: can't hash `%s': %s\n"),
815 sparc_opcodes
[i
].name
, retval
);
820 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
822 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
823 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
828 while (i
< (unsigned int) sparc_num_opcodes
829 && !strcmp (sparc_opcodes
[i
].name
, name
));
832 for (i
= 0; native_op_table
[i
].name
; i
++)
834 const struct sparc_opcode
*insn
;
835 char *name
= ((sparc_arch_size
== 32)
836 ? native_op_table
[i
].name32
837 : native_op_table
[i
].name64
);
838 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
841 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
842 name
, native_op_table
[i
].name
);
847 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
850 as_bad (_("Internal error: can't hash `%s': %s\n"),
851 sparc_opcodes
[i
].name
, retval
);
858 as_fatal (_("Broken assembler. No assembly attempted."));
860 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
861 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
863 /* If -bump, record the architecture level at which we start issuing
864 warnings. The behaviour is different depending upon whether an
865 architecture was explicitly specified. If it wasn't, we issue warnings
866 for all upwards bumps. If it was, we don't start issuing warnings until
867 we need to bump beyond the requested architecture or when we bump between
868 conflicting architectures. */
871 && architecture_requested
)
873 /* `max_architecture' records the requested architecture.
874 Issue warnings if we go above it. */
875 warn_after_architecture
= max_architecture
;
877 /* Find the highest architecture level that doesn't conflict with
878 the requested one. */
879 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
880 max_architecture
> warn_after_architecture
;
882 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
883 warn_after_architecture
))
888 /* Called after all assembly has been done. */
893 unsigned long mach
= bfd_mach_sparc
;
895 if (sparc_arch_size
== 64)
896 switch (current_architecture
)
898 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
899 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
900 default: mach
= bfd_mach_sparc_v9
; break;
903 switch (current_architecture
)
905 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
906 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
907 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
908 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
909 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
910 be but for now it is (since that's the way it's always been
914 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
917 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
920 in_signed_range (val
, max
)
921 bfd_signed_vma val
, max
;
925 /* Sign-extend the value from the architecture word size, so that
926 0xffffffff is always considered -1 on sparc32. */
927 if (sparc_arch_size
== 32)
929 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
930 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
939 /* Return non-zero if VAL is in the range 0 to MAX. */
942 in_unsigned_range (val
, max
)
950 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
951 (e.g. -15 to +31). */
954 in_bitfield_range (val
, max
)
955 bfd_signed_vma val
, max
;
961 if (val
< ~(max
>> 1))
975 for (i
= 0; (mask
& 1) == 0; ++i
)
980 /* Implement big shift right. */
986 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
987 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
988 return val
>> amount
;
991 /* For communication between sparc_ip and get_expression. */
992 static char *expr_end
;
994 /* Values for `special_case'.
995 Instructions that require wierd handling because they're longer than
997 #define SPECIAL_CASE_NONE 0
998 #define SPECIAL_CASE_SET 1
999 #define SPECIAL_CASE_SETSW 2
1000 #define SPECIAL_CASE_SETX 3
1001 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1002 #define SPECIAL_CASE_FDIV 4
1004 /* Bit masks of various insns. */
1005 #define NOP_INSN 0x01000000
1006 #define OR_INSN 0x80100000
1007 #define XOR_INSN 0x80180000
1008 #define FMOVS_INSN 0x81A00020
1009 #define SETHI_INSN 0x01000000
1010 #define SLLX_INSN 0x81281000
1011 #define SRA_INSN 0x81380000
1013 /* The last instruction to be assembled. */
1014 static const struct sparc_opcode
*last_insn
;
1015 /* The assembled opcode of `last_insn'. */
1016 static unsigned long last_opcode
;
1018 /* Handle the set and setuw synthetic instructions. */
1021 synthetize_setuw (insn
)
1022 const struct sparc_opcode
*insn
;
1024 int need_hi22_p
= 0;
1025 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1027 if (the_insn
.exp
.X_op
== O_constant
)
1029 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1031 if (sizeof (offsetT
) > 4
1032 && (the_insn
.exp
.X_add_number
< 0
1033 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1034 as_warn (_("set: number not in 0..4294967295 range"));
1038 if (sizeof (offsetT
) > 4
1039 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1040 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1041 as_warn (_("set: number not in -2147483648..4294967295 range"));
1042 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1046 /* See if operand is absolute and small; skip sethi if so. */
1047 if (the_insn
.exp
.X_op
!= O_constant
1048 || the_insn
.exp
.X_add_number
>= (1 << 12)
1049 || the_insn
.exp
.X_add_number
< -(1 << 12))
1051 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1052 | ((the_insn
.exp
.X_add_number
>> 10)
1053 & (the_insn
.exp
.X_op
== O_constant
1055 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1056 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1057 output_insn (insn
, &the_insn
);
1061 /* See if operand has no low-order bits; skip OR if so. */
1062 if (the_insn
.exp
.X_op
!= O_constant
1063 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1066 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1068 | (the_insn
.exp
.X_add_number
1069 & (the_insn
.exp
.X_op
!= O_constant
1070 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1071 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1072 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1073 output_insn (insn
, &the_insn
);
1077 /* Handle the setsw synthetic instruction. */
1080 synthetize_setsw (insn
)
1081 const struct sparc_opcode
*insn
;
1085 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1087 if (the_insn
.exp
.X_op
!= O_constant
)
1089 synthetize_setuw (insn
);
1091 /* Need to sign extend it. */
1092 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1093 the_insn
.reloc
= BFD_RELOC_NONE
;
1094 output_insn (insn
, &the_insn
);
1098 if (sizeof (offsetT
) > 4
1099 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1100 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1101 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1103 low32
= the_insn
.exp
.X_add_number
;
1107 synthetize_setuw (insn
);
1113 the_insn
.reloc
= BFD_RELOC_NONE
;
1114 /* See if operand is absolute and small; skip sethi if so. */
1115 if (low32
< -(1 << 12))
1117 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1118 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1119 output_insn (insn
, &the_insn
);
1120 low32
= 0x1c00 | (low32
& 0x3ff);
1121 opc
= RS1 (rd
) | XOR_INSN
;
1124 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1125 | (low32
& 0x1fff));
1126 output_insn (insn
, &the_insn
);
1129 /* Handle the setsw synthetic instruction. */
1132 synthetize_setx (insn
)
1133 const struct sparc_opcode
*insn
;
1135 int upper32
, lower32
;
1136 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1137 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1139 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1140 int need_xor10_p
= 0;
1142 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1143 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1144 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1147 upper_dstreg
= tmpreg
;
1148 /* The tmp reg should not be the dst reg. */
1149 if (tmpreg
== dstreg
)
1150 as_warn (_("setx: temporary register same as destination register"));
1152 /* ??? Obviously there are other optimizations we can do
1153 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1154 doing some of these. Later. If you do change things, try to
1155 change all of this to be table driven as well. */
1156 /* What to output depends on the number if it's constant.
1157 Compute that first, then output what we've decided upon. */
1158 if (the_insn
.exp
.X_op
!= O_constant
)
1160 if (sparc_arch_size
== 32)
1162 /* When arch size is 32, we want setx to be equivalent
1163 to setuw for anything but constants. */
1164 the_insn
.exp
.X_add_number
&= 0xffffffff;
1165 synthetize_setuw (insn
);
1168 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1174 /* Reset X_add_number, we've extracted it as upper32/lower32.
1175 Otherwise fixup_segment will complain about not being able to
1176 write an 8 byte number in a 4 byte field. */
1177 the_insn
.exp
.X_add_number
= 0;
1179 /* Only need hh22 if `or' insn can't handle constant. */
1180 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1183 /* Does bottom part (after sethi) have bits? */
1184 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1185 /* No hh22, but does upper32 still have bits we can't set
1187 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1190 /* If the lower half is all zero, we build the upper half directly
1191 into the dst reg. */
1193 /* Need lower half if number is zero or 0xffffffff00000000. */
1194 || (! need_hh22_p
&& ! need_hm10_p
))
1196 /* No need for sethi if `or' insn can handle constant. */
1197 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1198 /* Note that we can't use a negative constant in the `or'
1199 insn unless the upper 32 bits are all ones. */
1200 || (lower32
< 0 && upper32
!= -1)
1201 || (lower32
>= 0 && upper32
== -1))
1204 if (need_hi22_p
&& upper32
== -1)
1207 /* Does bottom part (after sethi) have bits? */
1208 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1210 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1211 /* Need `or' if we didn't set anything else. */
1212 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1216 /* Output directly to dst reg if lower 32 bits are all zero. */
1217 upper_dstreg
= dstreg
;
1220 if (!upper_dstreg
&& dstreg
)
1221 as_warn (_("setx: illegal temporary register g0"));
1225 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1226 | ((upper32
>> 10) & 0x3fffff));
1227 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1228 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1229 output_insn (insn
, &the_insn
);
1234 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1235 | (((need_xor10_p
? ~lower32
: lower32
)
1236 >> 10) & 0x3fffff));
1237 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1238 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1239 output_insn (insn
, &the_insn
);
1244 the_insn
.opcode
= (OR_INSN
1245 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1248 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1249 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1250 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1251 output_insn (insn
, &the_insn
);
1256 /* FIXME: One nice optimization to do here is to OR the low part
1257 with the highpart if hi22 isn't needed and the low part is
1259 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1262 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1263 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1264 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1265 output_insn (insn
, &the_insn
);
1268 /* If we needed to build the upper part, shift it into place. */
1269 if (need_hh22_p
|| need_hm10_p
)
1271 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1273 the_insn
.reloc
= BFD_RELOC_NONE
;
1274 output_insn (insn
, &the_insn
);
1277 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1280 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1281 | 0x1c00 | (lower32
& 0x3ff));
1282 the_insn
.reloc
= BFD_RELOC_NONE
;
1283 output_insn (insn
, &the_insn
);
1286 /* If we needed to build both upper and lower parts, OR them together. */
1287 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1289 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1291 the_insn
.reloc
= BFD_RELOC_NONE
;
1292 output_insn (insn
, &the_insn
);
1296 /* Main entry point to assemble one instruction. */
1302 const struct sparc_opcode
*insn
;
1306 special_case
= sparc_ip (str
, &insn
);
1308 /* We warn about attempts to put a floating point branch in a delay slot,
1309 unless the delay slot has been annulled. */
1311 && last_insn
!= NULL
1312 && (insn
->flags
& F_FBR
) != 0
1313 && (last_insn
->flags
& F_DELAYED
) != 0
1314 /* ??? This test isn't completely accurate. We assume anything with
1315 F_{UNBR,CONDBR,FBR} set is annullable. */
1316 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1317 || (last_opcode
& ANNUL
) == 0))
1318 as_warn (_("FP branch in delay slot"));
1320 /* SPARC before v9 requires a nop instruction between a floating
1321 point instruction and a floating point branch. We insert one
1322 automatically, with a warning. */
1323 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1325 && last_insn
!= NULL
1326 && (insn
->flags
& F_FBR
) != 0
1327 && (last_insn
->flags
& F_FLOAT
) != 0)
1329 struct sparc_it nop_insn
;
1331 nop_insn
.opcode
= NOP_INSN
;
1332 nop_insn
.reloc
= BFD_RELOC_NONE
;
1333 output_insn (insn
, &nop_insn
);
1334 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1337 switch (special_case
)
1339 case SPECIAL_CASE_NONE
:
1341 output_insn (insn
, &the_insn
);
1344 case SPECIAL_CASE_SETSW
:
1345 synthetize_setsw (insn
);
1348 case SPECIAL_CASE_SET
:
1349 synthetize_setuw (insn
);
1352 case SPECIAL_CASE_SETX
:
1353 synthetize_setx (insn
);
1356 case SPECIAL_CASE_FDIV
:
1358 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1360 output_insn (insn
, &the_insn
);
1362 /* According to information leaked from Sun, the "fdiv" instructions
1363 on early SPARC machines would produce incorrect results sometimes.
1364 The workaround is to add an fmovs of the destination register to
1365 itself just after the instruction. This was true on machines
1366 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1367 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1368 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1369 output_insn (insn
, &the_insn
);
1374 as_fatal (_("failed special case insn sanity check"));
1378 /* Subroutine of md_assemble to do the actual parsing. */
1381 sparc_ip (str
, pinsn
)
1383 const struct sparc_opcode
**pinsn
;
1385 char *error_message
= "";
1389 const struct sparc_opcode
*insn
;
1391 unsigned long opcode
;
1392 unsigned int mask
= 0;
1396 int special_case
= SPECIAL_CASE_NONE
;
1403 while (ISLOWER (*s
) || ISDIGIT (*s
));
1420 as_fatal (_("Unknown opcode: `%s'"), str
);
1422 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1426 as_bad (_("Unknown opcode: `%s'"), str
);
1427 return special_case
;
1437 opcode
= insn
->match
;
1438 memset (&the_insn
, '\0', sizeof (the_insn
));
1439 the_insn
.reloc
= BFD_RELOC_NONE
;
1442 /* Build the opcode, checking as we go to make sure that the
1444 for (args
= insn
->args
;; ++args
)
1452 /* Parse a series of masks. */
1459 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1462 error_message
= _(": invalid membar mask name");
1468 if (*s
== '|' || *s
== '+')
1476 if (! parse_const_expr_arg (&s
, &kmask
))
1478 error_message
= _(": invalid membar mask expression");
1481 if (kmask
< 0 || kmask
> 127)
1483 error_message
= _(": invalid membar mask number");
1488 opcode
|= MEMBAR (kmask
);
1496 if (! parse_const_expr_arg (&s
, &smask
))
1498 error_message
= _(": invalid siam mode expression");
1501 if (smask
< 0 || smask
> 7)
1503 error_message
= _(": invalid siam mode number");
1514 /* Parse a prefetch function. */
1517 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1519 error_message
= _(": invalid prefetch function name");
1525 if (! parse_const_expr_arg (&s
, &fcn
))
1527 error_message
= _(": invalid prefetch function expression");
1530 if (fcn
< 0 || fcn
> 31)
1532 error_message
= _(": invalid prefetch function number");
1542 /* Parse a sparc64 privileged register. */
1545 struct priv_reg_entry
*p
= priv_reg_table
;
1546 unsigned int len
= 9999999; /* Init to make gcc happy. */
1549 while (p
->name
[0] > s
[0])
1551 while (p
->name
[0] == s
[0])
1553 len
= strlen (p
->name
);
1554 if (strncmp (p
->name
, s
, len
) == 0)
1558 if (p
->name
[0] != s
[0])
1560 error_message
= _(": unrecognizable privileged register");
1564 opcode
|= (p
->regnum
<< 14);
1566 opcode
|= (p
->regnum
<< 25);
1572 error_message
= _(": unrecognizable privileged register");
1578 /* Parse a v9a/v9b ancillary state register. */
1581 struct priv_reg_entry
*p
= v9a_asr_table
;
1582 unsigned int len
= 9999999; /* Init to make gcc happy. */
1585 while (p
->name
[0] > s
[0])
1587 while (p
->name
[0] == s
[0])
1589 len
= strlen (p
->name
);
1590 if (strncmp (p
->name
, s
, len
) == 0)
1594 if (p
->name
[0] != s
[0])
1596 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1599 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1601 error_message
= _(": rd on write only ancillary state register");
1605 && (insn
->architecture
1606 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1608 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1609 error_message
= _(": unrecognizable v9a ancillary state register");
1613 opcode
|= (p
->regnum
<< 14);
1615 opcode
|= (p
->regnum
<< 25);
1621 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1627 if (strncmp (s
, "%asr", 4) == 0)
1635 while (ISDIGIT (*s
))
1637 num
= num
* 10 + *s
- '0';
1641 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1643 if (num
< 16 || 31 < num
)
1645 error_message
= _(": asr number must be between 16 and 31");
1651 if (num
< 0 || 31 < num
)
1653 error_message
= _(": asr number must be between 0 and 31");
1658 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1663 error_message
= _(": expecting %asrN");
1670 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1674 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1678 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1679 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1680 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1682 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1683 /* These fields are unsigned, but for upward compatibility,
1684 allow negative values as well. */
1688 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1689 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1690 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1692 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1693 /* These fields are unsigned, but for upward compatibility,
1694 allow negative values as well. */
1698 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1703 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1708 if (*s
== 'p' && s
[1] == 'n')
1716 if (*s
== 'p' && s
[1] == 't')
1728 if (strncmp (s
, "%icc", 4) == 0)
1740 if (strncmp (s
, "%xcc", 4) == 0)
1752 if (strncmp (s
, "%fcc0", 5) == 0)
1764 if (strncmp (s
, "%fcc1", 5) == 0)
1776 if (strncmp (s
, "%fcc2", 5) == 0)
1788 if (strncmp (s
, "%fcc3", 5) == 0)
1796 if (strncmp (s
, "%pc", 3) == 0)
1804 if (strncmp (s
, "%tick", 5) == 0)
1811 case '\0': /* End of args. */
1812 if (s
[0] == ',' && s
[1] == '%')
1814 static const struct tls_ops
{
1815 /* The name as it appears in assembler. */
1817 /* strlen (name), precomputed for speed */
1819 /* The reloc this pseudo-op translates to. */
1824 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
1825 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
1826 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
1827 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
1828 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
1829 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
1830 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
1831 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 }
1833 const struct tls_ops
*o
;
1837 for (o
= tls_ops
; o
->name
; o
++)
1838 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
1840 if (o
->name
== NULL
)
1843 if (s
[o
->len
+ 2] != '(')
1845 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1846 return special_case
;
1849 if (! o
->call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
1851 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
1853 return special_case
;
1857 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
1858 || the_insn
.exp
.X_add_number
!= 0
1859 || the_insn
.exp
.X_add_symbol
1860 != symbol_find_or_make ("__tls_get_addr")))
1862 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
1864 return special_case
;
1867 the_insn
.reloc
= o
->reloc
;
1868 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
1871 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
1874 else if (*s1
== ')')
1883 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
1884 return special_case
;
1888 (void) get_expression (s
);
1908 case '[': /* These must match exactly. */
1916 case '#': /* Must be at least one digit. */
1919 while (ISDIGIT (*s
))
1927 case 'C': /* Coprocessor state register. */
1928 if (strncmp (s
, "%csr", 4) == 0)
1935 case 'b': /* Next operand is a coprocessor register. */
1938 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
1943 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1957 opcode
|= mask
<< 14;
1965 opcode
|= mask
<< 25;
1971 case 'r': /* next operand must be a register */
1981 case 'f': /* frame pointer */
1989 case 'g': /* global register */
1998 case 'i': /* in register */
2002 mask
= c
- '0' + 24;
2007 case 'l': /* local register */
2011 mask
= (c
- '0' + 16);
2016 case 'o': /* out register */
2020 mask
= (c
- '0' + 8);
2025 case 's': /* stack pointer */
2033 case 'r': /* any register */
2034 if (!ISDIGIT ((c
= *s
++)))
2051 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2067 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2068 && no_undeclared_regs
&& ! globals
[mask
])
2069 as_bad (_("detected global register use not covered by .register pseudo-op"));
2071 /* Got the register, now figure out where
2072 it goes in the opcode. */
2076 opcode
|= mask
<< 14;
2084 opcode
|= mask
<< 25;
2088 opcode
|= (mask
<< 25) | (mask
<< 14);
2092 opcode
|= (mask
<< 25) | (mask
<< 0);
2098 case 'e': /* next operand is a floating point register */
2113 && ((format
= *s
) == 'f')
2116 for (mask
= 0; ISDIGIT (*s
); ++s
)
2118 mask
= 10 * mask
+ (*s
- '0');
2119 } /* read the number */
2127 } /* register must be even numbered */
2135 } /* register must be multiple of 4 */
2139 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2140 error_message
= _(": There are only 64 f registers; [0-63]");
2142 error_message
= _(": There are only 32 f registers; [0-31]");
2145 else if (mask
>= 32)
2147 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2150 mask
-= 31; /* wrap high bit */
2154 error_message
= _(": There are only 32 f registers; [0-31]");
2162 } /* if not an 'f' register. */
2169 opcode
|= RS1 (mask
);
2175 opcode
|= RS2 (mask
);
2181 opcode
|= RD (mask
);
2190 if (strncmp (s
, "%fsr", 4) == 0)
2197 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2198 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2201 case 'l': /* 22 bit PC relative immediate */
2202 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2206 case 'L': /* 30 bit immediate */
2207 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2212 case 'n': /* 22 bit immediate */
2213 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2216 case 'i': /* 13 bit immediate */
2217 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2227 char *op_arg
= NULL
;
2229 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2231 /* Check for %hi, etc. */
2234 static const struct ops
{
2235 /* The name as it appears in assembler. */
2237 /* strlen (name), precomputed for speed */
2239 /* The reloc this pseudo-op translates to. */
2241 /* Non-zero if for v9 only. */
2243 /* Non-zero if can be used in pc-relative contexts. */
2244 int pcrel_p
;/*FIXME:wip*/
2246 /* hix/lox must appear before hi/lo so %hix won't be
2247 mistaken for %hi. */
2248 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2249 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2250 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2251 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2252 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2253 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2254 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2255 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2256 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2257 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2258 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2259 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2260 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2261 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2262 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2263 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2264 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2266 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2268 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2269 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2270 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2271 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2272 { NULL
, 0, 0, 0, 0 }
2274 const struct ops
*o
;
2276 for (o
= ops
; o
->name
; o
++)
2277 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2279 if (o
->name
== NULL
)
2282 if (s
[o
->len
+ 1] != '(')
2284 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2285 return special_case
;
2289 the_insn
.reloc
= o
->reloc
;
2294 /* Note that if the get_expression() fails, we will still
2295 have created U entries in the symbol table for the
2296 'symbols' in the input string. Try not to create U
2297 symbols for registers, etc. */
2299 /* This stuff checks to see if the expression ends in
2300 +%reg. If it does, it removes the register from
2301 the expression, and re-sets 's' to point to the
2308 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2311 else if (*s1
== ')')
2320 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2321 return special_case
;
2325 (void) get_expression (s
);
2328 if (*s
== ',' || *s
== ']' || !*s
)
2330 if (*s
!= '+' && *s
!= '-')
2332 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2333 return special_case
;
2337 op_exp
= the_insn
.exp
;
2338 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2341 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2344 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2346 if (s1
[-2] == '%' && s1
[-3] == '+')
2348 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2355 if (op_arg
&& s1
== s
+ 1)
2356 the_insn
.exp
.X_op
= O_absent
;
2358 (void) get_expression (s
);
2370 (void) get_expression (s
);
2378 the_insn
.exp2
= the_insn
.exp
;
2379 the_insn
.exp
= op_exp
;
2380 if (the_insn
.exp2
.X_op
== O_absent
)
2381 the_insn
.exp2
.X_op
= O_illegal
;
2382 else if (the_insn
.exp
.X_op
== O_absent
)
2384 the_insn
.exp
= the_insn
.exp2
;
2385 the_insn
.exp2
.X_op
= O_illegal
;
2387 else if (the_insn
.exp
.X_op
== O_constant
)
2389 valueT val
= the_insn
.exp
.X_add_number
;
2390 switch (the_insn
.reloc
)
2395 case BFD_RELOC_SPARC_HH22
:
2396 val
= BSR (val
, 32);
2399 case BFD_RELOC_SPARC_LM22
:
2400 case BFD_RELOC_HI22
:
2401 val
= (val
>> 10) & 0x3fffff;
2404 case BFD_RELOC_SPARC_HM10
:
2405 val
= BSR (val
, 32);
2408 case BFD_RELOC_LO10
:
2412 case BFD_RELOC_SPARC_H44
:
2417 case BFD_RELOC_SPARC_M44
:
2422 case BFD_RELOC_SPARC_L44
:
2426 case BFD_RELOC_SPARC_HIX22
:
2428 val
= (val
>> 10) & 0x3fffff;
2431 case BFD_RELOC_SPARC_LOX10
:
2432 val
= (val
& 0x3ff) | 0x1c00;
2435 the_insn
.exp
= the_insn
.exp2
;
2436 the_insn
.exp
.X_add_number
+= val
;
2437 the_insn
.exp2
.X_op
= O_illegal
;
2438 the_insn
.reloc
= old_reloc
;
2440 else if (the_insn
.exp2
.X_op
!= O_constant
)
2442 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2443 return special_case
;
2447 if (old_reloc
!= BFD_RELOC_SPARC13
2448 || the_insn
.reloc
!= BFD_RELOC_LO10
2449 || sparc_arch_size
!= 64
2452 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2453 return special_case
;
2455 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2459 /* Check for constants that don't require emitting a reloc. */
2460 if (the_insn
.exp
.X_op
== O_constant
2461 && the_insn
.exp
.X_add_symbol
== 0
2462 && the_insn
.exp
.X_op_symbol
== 0)
2464 /* For pc-relative call instructions, we reject
2465 constants to get better code. */
2467 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2468 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2470 error_message
= _(": PC-relative operand can't be a constant");
2474 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2475 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2477 error_message
= _(": TLS operand can't be a constant");
2481 /* Constants that won't fit are checked in md_apply_fix3
2482 and bfd_install_relocation.
2483 ??? It would be preferable to install the constants
2484 into the insn here and save having to create a fixS
2485 for each one. There already exists code to handle
2486 all the various cases (e.g. in md_apply_fix3 and
2487 bfd_install_relocation) so duplicating all that code
2488 here isn't right. */
2508 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2510 error_message
= _(": invalid ASI name");
2516 if (! parse_const_expr_arg (&s
, &asi
))
2518 error_message
= _(": invalid ASI expression");
2521 if (asi
< 0 || asi
> 255)
2523 error_message
= _(": invalid ASI number");
2527 opcode
|= ASI (asi
);
2529 } /* Alternate space. */
2532 if (strncmp (s
, "%psr", 4) == 0)
2539 case 'q': /* Floating point queue. */
2540 if (strncmp (s
, "%fq", 3) == 0)
2547 case 'Q': /* Coprocessor queue. */
2548 if (strncmp (s
, "%cq", 3) == 0)
2556 if (strcmp (str
, "set") == 0
2557 || strcmp (str
, "setuw") == 0)
2559 special_case
= SPECIAL_CASE_SET
;
2562 else if (strcmp (str
, "setsw") == 0)
2564 special_case
= SPECIAL_CASE_SETSW
;
2567 else if (strcmp (str
, "setx") == 0)
2569 special_case
= SPECIAL_CASE_SETX
;
2572 else if (strncmp (str
, "fdiv", 4) == 0)
2574 special_case
= SPECIAL_CASE_FDIV
;
2580 if (strncmp (s
, "%asi", 4) != 0)
2586 if (strncmp (s
, "%fprs", 5) != 0)
2592 if (strncmp (s
, "%ccr", 4) != 0)
2598 if (strncmp (s
, "%tbr", 4) != 0)
2604 if (strncmp (s
, "%wim", 4) != 0)
2611 char *push
= input_line_pointer
;
2614 input_line_pointer
= s
;
2616 if (e
.X_op
== O_constant
)
2618 int n
= e
.X_add_number
;
2619 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2620 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2622 opcode
|= e
.X_add_number
<< 5;
2625 as_bad (_("non-immediate OPF operand, ignored"));
2626 s
= input_line_pointer
;
2627 input_line_pointer
= push
;
2632 if (strncmp (s
, "%y", 2) != 0)
2640 /* Parse a sparclet cpreg. */
2642 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2644 error_message
= _(": invalid cpreg name");
2647 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2652 as_fatal (_("failed sanity check."));
2653 } /* switch on arg code. */
2655 /* Break out of for() loop. */
2657 } /* For each arg that we expect. */
2662 /* Args don't match. */
2663 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2664 && (insn
->name
== insn
[1].name
2665 || !strcmp (insn
->name
, insn
[1].name
)))
2673 as_bad (_("Illegal operands%s"), error_message
);
2674 return special_case
;
2679 /* We have a match. Now see if the architecture is OK. */
2680 int needed_arch_mask
= insn
->architecture
;
2685 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2686 if (! needed_arch_mask
)
2688 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2691 if (needed_arch_mask
2692 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2695 /* Can we bump up the architecture? */
2696 else if (needed_arch_mask
2697 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2699 enum sparc_opcode_arch_val needed_architecture
=
2700 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2701 & needed_arch_mask
);
2703 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2705 && needed_architecture
> warn_after_architecture
)
2707 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2708 sparc_opcode_archs
[current_architecture
].name
,
2709 sparc_opcode_archs
[needed_architecture
].name
,
2711 warn_after_architecture
= needed_architecture
;
2713 current_architecture
= needed_architecture
;
2716 /* ??? This seems to be a bit fragile. What if the next entry in
2717 the opcode table is the one we want and it is supported?
2718 It is possible to arrange the table today so that this can't
2719 happen but what about tomorrow? */
2722 int arch
, printed_one_p
= 0;
2724 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2726 /* Create a list of the architectures that support the insn. */
2727 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2729 arch
= sparc_ffs (needed_arch_mask
);
2730 while ((1 << arch
) <= needed_arch_mask
)
2732 if ((1 << arch
) & needed_arch_mask
)
2736 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2743 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2744 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2746 sparc_opcode_archs
[max_architecture
].name
);
2747 return special_case
;
2749 } /* If no match. */
2752 } /* Forever looking for a match. */
2754 the_insn
.opcode
= opcode
;
2755 return special_case
;
2758 /* Parse an argument that can be expressed as a keyword.
2759 (eg: #StoreStore or %ccfr).
2760 The result is a boolean indicating success.
2761 If successful, INPUT_POINTER is updated. */
2764 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2765 int (*lookup_fn
) PARAMS ((const char *));
2766 char **input_pointerP
;
2772 p
= *input_pointerP
;
2773 for (q
= p
+ (*p
== '#' || *p
== '%');
2774 ISALNUM (*q
) || *q
== '_';
2779 value
= (*lookup_fn
) (p
);
2784 *input_pointerP
= q
;
2788 /* Parse an argument that is a constant expression.
2789 The result is a boolean indicating success. */
2792 parse_const_expr_arg (input_pointerP
, valueP
)
2793 char **input_pointerP
;
2796 char *save
= input_line_pointer
;
2799 input_line_pointer
= *input_pointerP
;
2800 /* The next expression may be something other than a constant
2801 (say if we're not processing the right variant of the insn).
2802 Don't call expression unless we're sure it will succeed as it will
2803 signal an error (which we want to defer until later). */
2804 /* FIXME: It might be better to define md_operand and have it recognize
2805 things like %asi, etc. but continuing that route through to the end
2806 is a lot of work. */
2807 if (*input_line_pointer
== '%')
2809 input_line_pointer
= save
;
2813 *input_pointerP
= input_line_pointer
;
2814 input_line_pointer
= save
;
2815 if (exp
.X_op
!= O_constant
)
2817 *valueP
= exp
.X_add_number
;
2821 /* Subroutine of sparc_ip to parse an expression. */
2824 get_expression (str
)
2830 save_in
= input_line_pointer
;
2831 input_line_pointer
= str
;
2832 seg
= expression (&the_insn
.exp
);
2833 if (seg
!= absolute_section
2834 && seg
!= text_section
2835 && seg
!= data_section
2836 && seg
!= bss_section
2837 && seg
!= undefined_section
)
2839 the_insn
.error
= _("bad segment");
2840 expr_end
= input_line_pointer
;
2841 input_line_pointer
= save_in
;
2844 expr_end
= input_line_pointer
;
2845 input_line_pointer
= save_in
;
2849 /* Subroutine of md_assemble to output one insn. */
2852 output_insn (insn
, the_insn
)
2853 const struct sparc_opcode
*insn
;
2854 struct sparc_it
*the_insn
;
2856 char *toP
= frag_more (4);
2858 /* Put out the opcode. */
2859 if (INSN_BIG_ENDIAN
)
2860 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2862 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2864 /* Put out the symbol-dependent stuff. */
2865 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2867 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2868 (toP
- frag_now
->fr_literal
), /* Where. */
2873 /* Turn off overflow checking in fixup_segment. We'll do our
2874 own overflow checking in md_apply_fix3. This is necessary because
2875 the insn size is 4 and fixup_segment will signal an overflow for
2876 large 8 byte quantities. */
2877 fixP
->fx_no_overflow
= 1;
2878 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2879 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2883 last_opcode
= the_insn
->opcode
;
2886 dwarf2_emit_insn (4);
2890 /* This is identical to the md_atof in m68k.c. I think this is right,
2893 Turn a string in input_line_pointer into a floating point constant
2894 of type TYPE, and store the appropriate bytes in *LITP. The number
2895 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2896 returned, or NULL on OK. */
2898 /* Equal to MAX_PRECISION in atof-ieee.c. */
2899 #define MAX_LITTLENUMS 6
2902 md_atof (type
, litP
, sizeP
)
2908 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2939 return _("Bad call to MD_ATOF()");
2942 t
= atof_ieee (input_line_pointer
, type
, words
);
2944 input_line_pointer
= t
;
2945 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2947 if (target_big_endian
)
2949 for (i
= 0; i
< prec
; i
++)
2951 md_number_to_chars (litP
, (valueT
) words
[i
],
2952 sizeof (LITTLENUM_TYPE
));
2953 litP
+= sizeof (LITTLENUM_TYPE
);
2958 for (i
= prec
- 1; i
>= 0; i
--)
2960 md_number_to_chars (litP
, (valueT
) words
[i
],
2961 sizeof (LITTLENUM_TYPE
));
2962 litP
+= sizeof (LITTLENUM_TYPE
);
2969 /* Write a value out to the object file, using the appropriate
2973 md_number_to_chars (buf
, val
, n
)
2978 if (target_big_endian
)
2979 number_to_chars_bigendian (buf
, val
, n
);
2980 else if (target_little_endian_data
2981 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2982 /* Output debug words, which are not in allocated sections, as big
2984 number_to_chars_bigendian (buf
, val
, n
);
2985 else if (target_little_endian_data
|| ! target_big_endian
)
2986 number_to_chars_littleendian (buf
, val
, n
);
2989 /* Apply a fixS to the frags, now that we know the value it ought to
2993 md_apply_fix3 (fixP
, valP
, segment
)
2996 segT segment ATTRIBUTE_UNUSED
;
2998 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2999 offsetT val
= * (offsetT
*) valP
;
3002 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3004 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3007 /* SPARC ELF relocations don't use an addend in the data field. */
3008 if (fixP
->fx_addsy
!= NULL
)
3012 /* This is a hack. There should be a better way to
3013 handle this. Probably in terms of howto fields, once
3014 we can look at these fixups in terms of howtos. */
3015 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3016 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3019 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3020 generate a reloc, then we just want to let the reloc addend set
3021 the value. We do not want to also stuff the addend into the
3022 object file. Including the addend in the object file works when
3023 doing a static link, because the linker will ignore the object
3024 file contents. However, the dynamic linker does not ignore the
3025 object file contents. */
3026 if (fixP
->fx_addsy
!= NULL
3027 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3030 /* When generating PIC code, we do not want an addend for a reloc
3031 against a local symbol. We adjust fx_addnumber to cancel out the
3032 value already included in val, and to also cancel out the
3033 adjustment which bfd_install_relocation will create. */
3035 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3036 && fixP
->fx_addsy
!= NULL
3037 && ! S_IS_COMMON (fixP
->fx_addsy
)
3038 && symbol_section_p (fixP
->fx_addsy
))
3039 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3041 /* When generating PIC code, we need to fiddle to get
3042 bfd_install_relocation to do the right thing for a PC relative
3043 reloc against a local symbol which we are going to keep. */
3045 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3046 && fixP
->fx_addsy
!= NULL
3047 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3048 || S_IS_WEAK (fixP
->fx_addsy
))
3049 && S_IS_DEFINED (fixP
->fx_addsy
)
3050 && ! S_IS_COMMON (fixP
->fx_addsy
))
3053 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3057 /* If this is a data relocation, just output VAL. */
3059 if (fixP
->fx_r_type
== BFD_RELOC_16
3060 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3062 md_number_to_chars (buf
, val
, 2);
3064 else if (fixP
->fx_r_type
== BFD_RELOC_32
3065 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3066 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3068 md_number_to_chars (buf
, val
, 4);
3070 else if (fixP
->fx_r_type
== BFD_RELOC_64
3071 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3073 md_number_to_chars (buf
, val
, 8);
3075 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3076 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3083 /* It's a relocation against an instruction. */
3085 if (INSN_BIG_ENDIAN
)
3086 insn
= bfd_getb32 ((unsigned char *) buf
);
3088 insn
= bfd_getl32 ((unsigned char *) buf
);
3090 switch (fixP
->fx_r_type
)
3092 case BFD_RELOC_32_PCREL_S2
:
3094 /* FIXME: This increment-by-one deserves a comment of why it's
3096 if (! sparc_pic_code
3097 || fixP
->fx_addsy
== NULL
3098 || symbol_section_p (fixP
->fx_addsy
))
3101 insn
|= val
& 0x3fffffff;
3103 /* See if we have a delay slot. */
3104 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3108 #define XCC (2 << 20)
3109 #define COND(x) (((x)&0xf)<<25)
3110 #define CONDA COND(0x8)
3111 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3112 #define INSN_BA (F2(0,2) | CONDA)
3113 #define INSN_OR F3(2, 0x2, 0)
3114 #define INSN_NOP F2(0,4)
3118 /* If the instruction is a call with either:
3120 arithmetic instruction with rd == %o7
3121 where rs1 != %o7 and rs2 if it is register != %o7
3122 then we can optimize if the call destination is near
3123 by changing the call into a branch always. */
3124 if (INSN_BIG_ENDIAN
)
3125 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3127 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3128 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3130 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3131 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3132 || ((delay
& RD (~0)) != RD (O7
))))
3134 if ((delay
& RS1 (~0)) == RS1 (O7
)
3135 || ((delay
& F3I (~0)) == 0
3136 && (delay
& RS2 (~0)) == RS2 (O7
)))
3138 /* Ensure the branch will fit into simm22. */
3139 if ((val
& 0x3fe00000)
3140 && (val
& 0x3fe00000) != 0x3fe00000)
3142 /* Check if the arch is v9 and branch will fit
3144 if (((val
& 0x3c0000) == 0
3145 || (val
& 0x3c0000) == 0x3c0000)
3146 && (sparc_arch_size
== 64
3147 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3149 insn
= INSN_BPA
| (val
& 0x7ffff);
3152 insn
= INSN_BA
| (val
& 0x3fffff);
3153 if (fixP
->fx_where
>= 4
3154 && ((delay
& (0xffffffff ^ RS1 (~0)))
3155 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3160 if (INSN_BIG_ENDIAN
)
3161 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3163 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3164 if ((setter
& (0xffffffff ^ RD (~0)))
3165 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3172 If call foo was replaced with ba, replace
3173 or %rN, %g0, %o7 with nop. */
3174 reg
= (delay
& RS1 (~0)) >> 14;
3175 if (reg
!= ((setter
& RD (~0)) >> 25)
3176 || reg
== G0
|| reg
== O7
)
3179 if (INSN_BIG_ENDIAN
)
3180 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3182 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3187 case BFD_RELOC_SPARC_11
:
3188 if (! in_signed_range (val
, 0x7ff))
3189 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3190 _("relocation overflow"));
3191 insn
|= val
& 0x7ff;
3194 case BFD_RELOC_SPARC_10
:
3195 if (! in_signed_range (val
, 0x3ff))
3196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3197 _("relocation overflow"));
3198 insn
|= val
& 0x3ff;
3201 case BFD_RELOC_SPARC_7
:
3202 if (! in_bitfield_range (val
, 0x7f))
3203 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3204 _("relocation overflow"));
3208 case BFD_RELOC_SPARC_6
:
3209 if (! in_bitfield_range (val
, 0x3f))
3210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3211 _("relocation overflow"));
3215 case BFD_RELOC_SPARC_5
:
3216 if (! in_bitfield_range (val
, 0x1f))
3217 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3218 _("relocation overflow"));
3222 case BFD_RELOC_SPARC_WDISP16
:
3223 /* FIXME: simplify. */
3224 if (((val
> 0) && (val
& ~0x3fffc))
3225 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
3226 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3227 _("relocation overflow"));
3228 /* FIXME: The +1 deserves a comment. */
3229 val
= (val
>> 2) + 1;
3230 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3233 case BFD_RELOC_SPARC_WDISP19
:
3234 /* FIXME: simplify. */
3235 if (((val
> 0) && (val
& ~0x1ffffc))
3236 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
3237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3238 _("relocation overflow"));
3239 /* FIXME: The +1 deserves a comment. */
3240 val
= (val
>> 2) + 1;
3241 insn
|= val
& 0x7ffff;
3244 case BFD_RELOC_SPARC_HH22
:
3245 val
= BSR (val
, 32);
3248 case BFD_RELOC_SPARC_LM22
:
3249 case BFD_RELOC_HI22
:
3250 if (!fixP
->fx_addsy
)
3251 insn
|= (val
>> 10) & 0x3fffff;
3253 /* FIXME: Need comment explaining why we do this. */
3257 case BFD_RELOC_SPARC22
:
3258 if (val
& ~0x003fffff)
3259 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3260 _("relocation overflow"));
3261 insn
|= (val
& 0x3fffff);
3264 case BFD_RELOC_SPARC_HM10
:
3265 val
= BSR (val
, 32);
3268 case BFD_RELOC_LO10
:
3269 if (!fixP
->fx_addsy
)
3270 insn
|= val
& 0x3ff;
3272 /* FIXME: Need comment explaining why we do this. */
3276 case BFD_RELOC_SPARC_OLO10
:
3278 val
+= fixP
->tc_fix_data
;
3281 case BFD_RELOC_SPARC13
:
3282 if (! in_signed_range (val
, 0x1fff))
3283 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3284 _("relocation overflow"));
3285 insn
|= val
& 0x1fff;
3288 case BFD_RELOC_SPARC_WDISP22
:
3289 val
= (val
>> 2) + 1;
3291 case BFD_RELOC_SPARC_BASE22
:
3292 insn
|= val
& 0x3fffff;
3295 case BFD_RELOC_SPARC_H44
:
3296 if (!fixP
->fx_addsy
)
3300 insn
|= tval
& 0x3fffff;
3304 case BFD_RELOC_SPARC_M44
:
3305 if (!fixP
->fx_addsy
)
3306 insn
|= (val
>> 12) & 0x3ff;
3309 case BFD_RELOC_SPARC_L44
:
3310 if (!fixP
->fx_addsy
)
3311 insn
|= val
& 0xfff;
3314 case BFD_RELOC_SPARC_HIX22
:
3315 if (!fixP
->fx_addsy
)
3317 val
^= ~(offsetT
) 0;
3318 insn
|= (val
>> 10) & 0x3fffff;
3322 case BFD_RELOC_SPARC_LOX10
:
3323 if (!fixP
->fx_addsy
)
3324 insn
|= 0x1c00 | (val
& 0x3ff);
3327 case BFD_RELOC_NONE
:
3329 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3330 _("bad or unhandled relocation type: 0x%02x"),
3335 if (INSN_BIG_ENDIAN
)
3336 bfd_putb32 (insn
, (unsigned char *) buf
);
3338 bfd_putl32 (insn
, (unsigned char *) buf
);
3341 /* Are we finished with this relocation now? */
3342 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3346 /* Translate internal representation of relocation info to BFD target
3350 tc_gen_reloc (section
, fixp
)
3351 asection
*section ATTRIBUTE_UNUSED
;
3354 static arelent
*relocs
[3];
3356 bfd_reloc_code_real_type code
;
3358 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3361 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3362 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3363 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3365 switch (fixp
->fx_r_type
)
3369 case BFD_RELOC_HI22
:
3370 case BFD_RELOC_LO10
:
3371 case BFD_RELOC_32_PCREL_S2
:
3372 case BFD_RELOC_SPARC13
:
3373 case BFD_RELOC_SPARC22
:
3374 case BFD_RELOC_SPARC_BASE13
:
3375 case BFD_RELOC_SPARC_WDISP16
:
3376 case BFD_RELOC_SPARC_WDISP19
:
3377 case BFD_RELOC_SPARC_WDISP22
:
3379 case BFD_RELOC_SPARC_5
:
3380 case BFD_RELOC_SPARC_6
:
3381 case BFD_RELOC_SPARC_7
:
3382 case BFD_RELOC_SPARC_10
:
3383 case BFD_RELOC_SPARC_11
:
3384 case BFD_RELOC_SPARC_HH22
:
3385 case BFD_RELOC_SPARC_HM10
:
3386 case BFD_RELOC_SPARC_LM22
:
3387 case BFD_RELOC_SPARC_PC_HH22
:
3388 case BFD_RELOC_SPARC_PC_HM10
:
3389 case BFD_RELOC_SPARC_PC_LM22
:
3390 case BFD_RELOC_SPARC_H44
:
3391 case BFD_RELOC_SPARC_M44
:
3392 case BFD_RELOC_SPARC_L44
:
3393 case BFD_RELOC_SPARC_HIX22
:
3394 case BFD_RELOC_SPARC_LOX10
:
3395 case BFD_RELOC_SPARC_REV32
:
3396 case BFD_RELOC_SPARC_OLO10
:
3397 case BFD_RELOC_SPARC_UA16
:
3398 case BFD_RELOC_SPARC_UA32
:
3399 case BFD_RELOC_SPARC_UA64
:
3400 case BFD_RELOC_8_PCREL
:
3401 case BFD_RELOC_16_PCREL
:
3402 case BFD_RELOC_32_PCREL
:
3403 case BFD_RELOC_64_PCREL
:
3404 case BFD_RELOC_SPARC_PLT32
:
3405 case BFD_RELOC_SPARC_PLT64
:
3406 case BFD_RELOC_VTABLE_ENTRY
:
3407 case BFD_RELOC_VTABLE_INHERIT
:
3408 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3409 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3410 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3411 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3412 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3413 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3414 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3415 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3416 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3417 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3418 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3419 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3420 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3421 case BFD_RELOC_SPARC_TLS_IE_LD
:
3422 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3423 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3424 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3425 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3426 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3427 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3428 code
= fixp
->fx_r_type
;
3435 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3436 /* If we are generating PIC code, we need to generate a different
3440 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3442 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3445 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3451 case BFD_RELOC_32_PCREL_S2
:
3452 if (generic_force_reloc (fixp
))
3453 code
= BFD_RELOC_SPARC_WPLT30
;
3455 case BFD_RELOC_HI22
:
3456 if (fixp
->fx_addsy
!= NULL
3457 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3458 code
= BFD_RELOC_SPARC_PC22
;
3460 code
= BFD_RELOC_SPARC_GOT22
;
3462 case BFD_RELOC_LO10
:
3463 if (fixp
->fx_addsy
!= NULL
3464 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3465 code
= BFD_RELOC_SPARC_PC10
;
3467 code
= BFD_RELOC_SPARC_GOT10
;
3469 case BFD_RELOC_SPARC13
:
3470 code
= BFD_RELOC_SPARC_GOT13
;
3476 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3478 if (code
== BFD_RELOC_SPARC_OLO10
)
3479 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3481 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3482 if (reloc
->howto
== 0)
3484 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3485 _("internal error: can't export reloc type %d (`%s')"),
3486 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3492 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3495 if (reloc
->howto
->pc_relative
== 0
3496 || code
== BFD_RELOC_SPARC_PC10
3497 || code
== BFD_RELOC_SPARC_PC22
)
3498 reloc
->addend
= fixp
->fx_addnumber
;
3499 else if (sparc_pic_code
3500 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3501 && fixp
->fx_addsy
!= NULL
3502 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3503 || S_IS_WEAK (fixp
->fx_addsy
))
3504 && S_IS_DEFINED (fixp
->fx_addsy
)
3505 && ! S_IS_COMMON (fixp
->fx_addsy
))
3506 reloc
->addend
= fixp
->fx_addnumber
;
3508 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3510 #else /* elf or coff */
3512 if (code
!= BFD_RELOC_32_PCREL_S2
3513 && code
!= BFD_RELOC_SPARC_WDISP22
3514 && code
!= BFD_RELOC_SPARC_WDISP16
3515 && code
!= BFD_RELOC_SPARC_WDISP19
3516 && code
!= BFD_RELOC_SPARC_WPLT30
3517 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3518 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3519 reloc
->addend
= fixp
->fx_addnumber
;
3520 else if (symbol_section_p (fixp
->fx_addsy
))
3521 reloc
->addend
= (section
->vma
3522 + fixp
->fx_addnumber
3523 + md_pcrel_from (fixp
));
3525 reloc
->addend
= fixp
->fx_offset
;
3528 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3529 on the same location. */
3530 if (code
== BFD_RELOC_SPARC_OLO10
)
3532 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3535 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3537 = symbol_get_bfdsym (section_symbol (absolute_section
));
3538 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3539 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3540 reloc
->addend
= fixp
->tc_fix_data
;
3546 /* We have no need to default values of symbols. */
3549 md_undefined_symbol (name
)
3550 char *name ATTRIBUTE_UNUSED
;
3555 /* Round up a section size to the appropriate boundary. */
3558 md_section_align (segment
, size
)
3559 segT segment ATTRIBUTE_UNUSED
;
3563 /* This is not right for ELF; a.out wants it, and COFF will force
3564 the alignment anyways. */
3565 valueT align
= ((valueT
) 1
3566 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3569 /* Turn alignment value into a mask. */
3571 newsize
= (size
+ align
) & ~align
;
3578 /* Exactly what point is a PC-relative offset relative TO?
3579 On the sparc, they're relative to the address of the offset, plus
3580 its size. This gets us to the following instruction.
3581 (??? Is this right? FIXME-SOON) */
3583 md_pcrel_from (fixP
)
3588 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3589 if (! sparc_pic_code
3590 || fixP
->fx_addsy
== NULL
3591 || symbol_section_p (fixP
->fx_addsy
))
3592 ret
+= fixP
->fx_size
;
3596 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3608 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3611 return (value
== 1) ? shift
: -1;
3614 /* Sort of like s_lcomm. */
3617 static int max_alignment
= 15;
3622 int ignore ATTRIBUTE_UNUSED
;
3632 name
= input_line_pointer
;
3633 c
= get_symbol_end ();
3634 p
= input_line_pointer
;
3638 if (*input_line_pointer
!= ',')
3640 as_bad (_("Expected comma after name"));
3641 ignore_rest_of_line ();
3645 ++input_line_pointer
;
3647 if ((size
= get_absolute_expression ()) < 0)
3649 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3650 ignore_rest_of_line ();
3655 symbolP
= symbol_find_or_make (name
);
3658 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3659 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3661 as_bad (_("bad .reserve segment -- expected BSS segment"));
3665 if (input_line_pointer
[2] == '.')
3666 input_line_pointer
+= 7;
3668 input_line_pointer
+= 6;
3671 if (*input_line_pointer
== ',')
3673 ++input_line_pointer
;
3676 if (*input_line_pointer
== '\n')
3678 as_bad (_("missing alignment"));
3679 ignore_rest_of_line ();
3683 align
= (int) get_absolute_expression ();
3686 if (align
> max_alignment
)
3688 align
= max_alignment
;
3689 as_warn (_("alignment too large; assuming %d"), align
);
3695 as_bad (_("negative alignment"));
3696 ignore_rest_of_line ();
3702 temp
= log2 (align
);
3705 as_bad (_("alignment not a power of 2"));
3706 ignore_rest_of_line ();
3713 record_alignment (bss_section
, align
);
3718 if (!S_IS_DEFINED (symbolP
)
3720 && S_GET_OTHER (symbolP
) == 0
3721 && S_GET_DESC (symbolP
) == 0
3728 segT current_seg
= now_seg
;
3729 subsegT current_subseg
= now_subseg
;
3731 /* Switch to bss. */
3732 subseg_set (bss_section
, 1);
3736 frag_align (align
, 0, 0);
3738 /* Detach from old frag. */
3739 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3740 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3742 symbol_set_frag (symbolP
, frag_now
);
3743 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3744 (offsetT
) size
, (char *) 0);
3747 S_SET_SEGMENT (symbolP
, bss_section
);
3749 subseg_set (current_seg
, current_subseg
);
3752 S_SET_SIZE (symbolP
, size
);
3758 as_warn ("Ignoring attempt to re-define symbol %s",
3759 S_GET_NAME (symbolP
));
3760 } /* if not redefining. */
3762 demand_empty_rest_of_line ();
3767 int ignore ATTRIBUTE_UNUSED
;
3775 name
= input_line_pointer
;
3776 c
= get_symbol_end ();
3777 /* Just after name is now '\0'. */
3778 p
= input_line_pointer
;
3781 if (*input_line_pointer
!= ',')
3783 as_bad (_("Expected comma after symbol-name"));
3784 ignore_rest_of_line ();
3789 input_line_pointer
++;
3791 if ((temp
= get_absolute_expression ()) < 0)
3793 as_bad (_(".COMMon length (%lu) out of range ignored"),
3794 (unsigned long) temp
);
3795 ignore_rest_of_line ();
3800 symbolP
= symbol_find_or_make (name
);
3802 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3804 as_bad (_("Ignoring attempt to re-define symbol"));
3805 ignore_rest_of_line ();
3808 if (S_GET_VALUE (symbolP
) != 0)
3810 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3812 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
3813 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
3819 S_SET_VALUE (symbolP
, (valueT
) size
);
3820 S_SET_EXTERNAL (symbolP
);
3823 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3824 if (*input_line_pointer
!= ',')
3826 as_bad (_("Expected comma after common length"));
3827 ignore_rest_of_line ();
3830 input_line_pointer
++;
3832 if (*input_line_pointer
!= '"')
3834 temp
= get_absolute_expression ();
3837 if (temp
> max_alignment
)
3839 temp
= max_alignment
;
3840 as_warn (_("alignment too large; assuming %d"), temp
);
3846 as_bad (_("negative alignment"));
3847 ignore_rest_of_line ();
3852 if (symbol_get_obj (symbolP
)->local
)
3860 old_subsec
= now_subseg
;
3865 align
= log2 (temp
);
3869 as_bad (_("alignment not a power of 2"));
3870 ignore_rest_of_line ();
3874 record_alignment (bss_section
, align
);
3875 subseg_set (bss_section
, 0);
3877 frag_align (align
, 0, 0);
3878 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3879 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3880 symbol_set_frag (symbolP
, frag_now
);
3881 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3882 (offsetT
) size
, (char *) 0);
3884 S_SET_SEGMENT (symbolP
, bss_section
);
3885 S_CLEAR_EXTERNAL (symbolP
);
3886 S_SET_SIZE (symbolP
, size
);
3887 subseg_set (old_sec
, old_subsec
);
3890 #endif /* OBJ_ELF */
3893 S_SET_VALUE (symbolP
, (valueT
) size
);
3895 S_SET_ALIGN (symbolP
, temp
);
3896 S_SET_SIZE (symbolP
, size
);
3898 S_SET_EXTERNAL (symbolP
);
3899 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3904 input_line_pointer
++;
3905 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3906 if (*input_line_pointer
== '.')
3907 input_line_pointer
++;
3908 /* @@ Some say data, some say bss. */
3909 if (strncmp (input_line_pointer
, "bss\"", 4)
3910 && strncmp (input_line_pointer
, "data\"", 5))
3912 while (*--input_line_pointer
!= '"')
3914 input_line_pointer
--;
3915 goto bad_common_segment
;
3917 while (*input_line_pointer
++ != '"')
3919 goto allocate_common
;
3922 #ifdef BFD_ASSEMBLER
3923 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3926 demand_empty_rest_of_line ();
3931 p
= input_line_pointer
;
3932 while (*p
&& *p
!= '\n')
3936 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3938 input_line_pointer
= p
;
3939 ignore_rest_of_line ();
3944 /* Handle the .empty pseudo-op. This suppresses the warnings about
3945 invalid delay slot usage. */
3949 int ignore ATTRIBUTE_UNUSED
;
3951 /* The easy way to implement is to just forget about the last
3958 int ignore ATTRIBUTE_UNUSED
;
3961 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3963 input_line_pointer
+= 6;
3967 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3969 input_line_pointer
+= 6;
3973 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3975 input_line_pointer
+= 7;
3979 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3981 input_line_pointer
+= 5;
3982 /* We only support 2 segments -- text and data -- for now, so
3983 things in the "bss segment" will have to go into data for now.
3984 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3985 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
3988 as_bad (_("Unknown segment type"));
3989 demand_empty_rest_of_line ();
3995 subseg_set (data_section
, 1);
3996 demand_empty_rest_of_line ();
4001 int ignore ATTRIBUTE_UNUSED
;
4003 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4005 ++input_line_pointer
;
4007 ++input_line_pointer
;
4010 /* This static variable is set by s_uacons to tell sparc_cons_align
4011 that the expression does not need to be aligned. */
4013 static int sparc_no_align_cons
= 0;
4015 /* This static variable is set by sparc_cons to emit requested types
4016 of relocations in cons_fix_new_sparc. */
4018 static const char *sparc_cons_special_reloc
;
4020 /* This handles the unaligned space allocation pseudo-ops, such as
4021 .uaword. .uaword is just like .word, but the value does not need
4028 /* Tell sparc_cons_align not to align this value. */
4029 sparc_no_align_cons
= 1;
4031 sparc_no_align_cons
= 0;
4034 /* This handles the native word allocation pseudo-op .nword.
4035 For sparc_arch_size 32 it is equivalent to .word, for
4036 sparc_arch_size 64 it is equivalent to .xword. */
4040 int bytes ATTRIBUTE_UNUSED
;
4042 cons (sparc_arch_size
== 32 ? 4 : 8);
4046 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4050 .register %g[2367],{#scratch|symbolname|#ignore}
4055 int ignore ATTRIBUTE_UNUSED
;
4060 const char *regname
;
4062 if (input_line_pointer
[0] != '%'
4063 || input_line_pointer
[1] != 'g'
4064 || ((input_line_pointer
[2] & ~1) != '2'
4065 && (input_line_pointer
[2] & ~1) != '6')
4066 || input_line_pointer
[3] != ',')
4067 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4068 reg
= input_line_pointer
[2] - '0';
4069 input_line_pointer
+= 4;
4071 if (*input_line_pointer
== '#')
4073 ++input_line_pointer
;
4074 regname
= input_line_pointer
;
4075 c
= get_symbol_end ();
4076 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4077 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4078 if (regname
[0] == 'i')
4085 regname
= input_line_pointer
;
4086 c
= get_symbol_end ();
4088 if (sparc_arch_size
== 64)
4092 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4093 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4094 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4095 as_bad (_("redefinition of global register"));
4099 if (regname
== NULL
)
4100 globals
[reg
] = (symbolS
*) 1;
4105 if (symbol_find (regname
))
4106 as_bad (_("Register symbol %s already defined."),
4109 globals
[reg
] = symbol_make (regname
);
4110 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4112 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4113 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4114 flags
|= BSF_GLOBAL
;
4115 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4116 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4117 S_SET_ALIGN (globals
[reg
], reg
);
4118 S_SET_SIZE (globals
[reg
], 0);
4119 /* Although we actually want undefined_section here,
4120 we have to use absolute_section, because otherwise
4121 generic as code will make it a COM section.
4122 We fix this up in sparc_adjust_symtab. */
4123 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4124 S_SET_OTHER (globals
[reg
], 0);
4125 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4126 ->internal_elf_sym
.st_info
=
4127 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4128 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4129 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4134 *input_line_pointer
= c
;
4136 demand_empty_rest_of_line ();
4139 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4140 symbols which need it. */
4143 sparc_adjust_symtab ()
4147 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4149 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4150 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4153 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4154 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4157 S_SET_SEGMENT (sym
, undefined_section
);
4162 /* If the --enforce-aligned-data option is used, we require .word,
4163 et. al., to be aligned correctly. We do it by setting up an
4164 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4165 no unexpected alignment was introduced.
4167 The SunOS and Solaris native assemblers enforce aligned data by
4168 default. We don't want to do that, because gcc can deliberately
4169 generate misaligned data if the packed attribute is used. Instead,
4170 we permit misaligned data by default, and permit the user to set an
4171 option to check for it. */
4174 sparc_cons_align (nbytes
)
4180 /* Only do this if we are enforcing aligned data. */
4181 if (! enforce_aligned_data
)
4184 /* Don't align if this is an unaligned pseudo-op. */
4185 if (sparc_no_align_cons
)
4188 nalign
= log2 (nbytes
);
4192 assert (nalign
> 0);
4194 if (now_seg
== absolute_section
)
4196 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4197 as_bad (_("misaligned data"));
4201 p
= frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4202 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4204 record_alignment (now_seg
, nalign
);
4207 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4210 sparc_handle_align (fragp
)
4216 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4218 switch (fragp
->fr_type
)
4222 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4226 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4237 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4239 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4240 if (INSN_BIG_ENDIAN
)
4241 number_to_chars_bigendian (p
, wval
, 4);
4243 number_to_chars_littleendian (p
, wval
, 4);
4249 if (INSN_BIG_ENDIAN
)
4250 number_to_chars_bigendian (p
, 0x01000000, 4);
4252 number_to_chars_littleendian (p
, 0x01000000, 4);
4254 fragp
->fr_fix
+= fix
;
4264 /* Some special processing for a Sparc ELF file. */
4267 sparc_elf_final_processing ()
4269 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4270 sort of BFD interface for this. */
4271 if (sparc_arch_size
== 64)
4273 switch (sparc_memory_model
)
4276 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4279 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4285 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4286 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4287 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4288 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4289 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4290 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4294 sparc_cons (exp
, size
)
4301 sparc_cons_special_reloc
= NULL
;
4302 save
= input_line_pointer
;
4303 if (input_line_pointer
[0] == '%'
4304 && input_line_pointer
[1] == 'r'
4305 && input_line_pointer
[2] == '_')
4307 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4309 input_line_pointer
+= 7;
4310 sparc_cons_special_reloc
= "disp";
4312 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4314 if (size
!= 4 && size
!= 8)
4315 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4318 input_line_pointer
+= 6;
4319 sparc_cons_special_reloc
= "plt";
4322 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4324 if (size
!= 4 && size
!= 8)
4325 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4328 input_line_pointer
+= 13;
4329 sparc_cons_special_reloc
= "tls_dtpoff";
4332 if (sparc_cons_special_reloc
)
4339 if (*input_line_pointer
!= '8')
4341 input_line_pointer
--;
4344 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4348 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4352 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4362 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4363 sparc_cons_special_reloc
, size
* 8, size
);
4367 input_line_pointer
+= 2;
4368 if (*input_line_pointer
!= '(')
4370 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4371 sparc_cons_special_reloc
, size
* 8);
4378 input_line_pointer
= save
;
4379 sparc_cons_special_reloc
= NULL
;
4384 char *end
= ++input_line_pointer
;
4387 while (! is_end_of_line
[(c
= *end
)])
4401 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4402 sparc_cons_special_reloc
, size
* 8);
4408 if (input_line_pointer
!= end
)
4410 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4411 sparc_cons_special_reloc
, size
* 8);
4415 input_line_pointer
++;
4417 c
= *input_line_pointer
;
4418 if (! is_end_of_line
[c
] && c
!= ',')
4419 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4420 sparc_cons_special_reloc
, size
* 8);
4426 if (sparc_cons_special_reloc
== NULL
)
4432 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4433 reloc for a cons. We could use the definition there, except that
4434 we want to handle little endian relocs specially. */
4437 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
4440 unsigned int nbytes
;
4443 bfd_reloc_code_real_type r
;
4445 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4446 (nbytes
== 2 ? BFD_RELOC_16
:
4447 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4449 if (target_little_endian_data
4451 && now_seg
->flags
& SEC_ALLOC
)
4452 r
= BFD_RELOC_SPARC_REV32
;
4454 if (sparc_cons_special_reloc
)
4456 if (*sparc_cons_special_reloc
== 'd')
4459 case 1: r
= BFD_RELOC_8_PCREL
; break;
4460 case 2: r
= BFD_RELOC_16_PCREL
; break;
4461 case 4: r
= BFD_RELOC_32_PCREL
; break;
4462 case 8: r
= BFD_RELOC_64_PCREL
; break;
4465 else if (*sparc_cons_special_reloc
== 'p')
4468 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4469 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4474 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4475 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4478 else if (sparc_no_align_cons
)
4482 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4483 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4484 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4489 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4490 sparc_cons_special_reloc
= NULL
;
4494 sparc_cfi_frame_initial_instructions ()
4496 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4500 sparc_regname_to_dw2regnum (const char *regname
)
4508 p
= strchr (q
, regname
[0]);
4511 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4513 return (p
- q
) * 8 + regname
[1] - '0';
4515 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4517 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4519 if (regname
[0] == 'f' || regname
[0] == 'r')
4521 unsigned int regnum
;
4523 regnum
= strtoul (regname
+ 1, &q
, 10);
4526 if (regnum
>= ((regname
[0] == 'f'
4527 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4530 if (regname
[0] == 'f')
4533 if (regnum
>= 64 && (regnum
& 1))
4542 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4544 sparc_cons_special_reloc
= "disp";
4545 sparc_no_align_cons
= 1;
4546 emit_expr (exp
, nbytes
);
4547 sparc_no_align_cons
= 0;
4548 sparc_cons_special_reloc
= NULL
;