1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
30 #include "elf/sparc.h"
33 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
34 static void init_default_arch
PARAMS ((void));
35 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
36 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
37 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
38 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
39 static int sparc_ffs
PARAMS ((unsigned int));
40 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
41 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
42 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
43 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
44 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
45 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
46 static int parse_const_expr_arg
PARAMS ((char **, int *));
47 static int get_expression
PARAMS ((char *str
));
49 /* Default architecture. */
50 /* ??? The default value should be V8, but sparclite support was added
51 by making it the default. GCC now passes -Asparclite, so maybe sometime in
52 the future we can set this to V8. */
54 #define DEFAULT_ARCH "sparclite"
56 static char *default_arch
= DEFAULT_ARCH
;
58 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
60 static int default_init_p
;
62 /* Current architecture. We don't bump up unless necessary. */
63 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
65 /* The maximum architecture level we can bump up to.
66 In a 32 bit environment, don't allow bumping up to v9 by default.
67 The native assembler works this way. The user is required to pass
68 an explicit argument before we'll create v9 object files. However, if
69 we don't see any v9 insns, a v8plus object file is not created. */
70 static enum sparc_opcode_arch_val max_architecture
;
72 /* Either 32 or 64, selects file format. */
73 static int sparc_arch_size
;
74 /* Initial (default) value, recorded separately in case a user option
75 changes the value before md_show_usage is called. */
76 static int default_arch_size
;
79 /* The currently selected v9 memory model. Currently only used for
81 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
84 static int architecture_requested
;
85 static int warn_on_bump
;
87 /* If warn_on_bump and the needed architecture is higher than this
88 architecture, issue a warning. */
89 static enum sparc_opcode_arch_val warn_after_architecture
;
91 /* Non-zero if as should generate error if an undeclared g[23] register
92 has been used in -64. */
93 static int no_undeclared_regs
;
95 /* Non-zero if we should try to relax jumps and calls. */
96 static int sparc_relax
;
98 /* Non-zero if we are generating PIC code. */
101 /* Non-zero if we should give an error when misaligned data is seen. */
102 static int enforce_aligned_data
;
104 extern int target_big_endian
;
106 static int target_little_endian_data
;
108 /* Symbols for global registers on v9. */
109 static symbolS
*globals
[8];
111 /* V9 and 86x have big and little endian data, but instructions are always big
112 endian. The sparclet has bi-endian support but both data and insns have
113 the same endianness. Global `target_big_endian' is used for data.
114 The following macro is used for instructions. */
115 #ifndef INSN_BIG_ENDIAN
116 #define INSN_BIG_ENDIAN (target_big_endian \
117 || default_arch_type == sparc86x \
118 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
121 /* Handle of the OPCODE hash table. */
122 static struct hash_control
*op_hash
;
124 static int log2
PARAMS ((int));
125 static void s_data1
PARAMS ((void));
126 static void s_seg
PARAMS ((int));
127 static void s_proc
PARAMS ((int));
128 static void s_reserve
PARAMS ((int));
129 static void s_common
PARAMS ((int));
130 static void s_empty
PARAMS ((int));
131 static void s_uacons
PARAMS ((int));
132 static void s_ncons
PARAMS ((int));
133 static void s_register
PARAMS ((int));
135 const pseudo_typeS md_pseudo_table
[] =
137 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
138 {"common", s_common
, 0},
139 {"empty", s_empty
, 0},
140 {"global", s_globl
, 0},
142 {"nword", s_ncons
, 0},
143 {"optim", s_ignore
, 0},
145 {"reserve", s_reserve
, 0},
147 {"skip", s_space
, 0},
150 {"uahalf", s_uacons
, 2},
151 {"uaword", s_uacons
, 4},
152 {"uaxword", s_uacons
, 8},
154 /* These are specific to sparc/svr4. */
155 {"2byte", s_uacons
, 2},
156 {"4byte", s_uacons
, 4},
157 {"8byte", s_uacons
, 8},
158 {"register", s_register
, 0},
163 /* Size of relocation record. */
164 const int md_reloc_size
= 12;
166 /* This array holds the chars that always start a comment. If the
167 pre-processor is disabled, these aren't very useful. */
168 const char comment_chars
[] = "!"; /* JF removed '|' from
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output. */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that comments started like this one will always
178 work if '/' isn't otherwise defined. */
179 const char line_comment_chars
[] = "#";
181 const char line_separator_chars
[] = ";";
183 /* Chars that can be used to separate mant from exp in floating point
185 const char EXP_CHARS
[] = "eE";
187 /* Chars that mean this number is a floating point constant.
190 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
192 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
193 changed in read.c. Ideally it shouldn't have to know about it at all,
194 but nothing is ideal around here. */
196 #define isoctal(c) ((unsigned)((c) - '0') < '8')
201 unsigned long opcode
;
202 struct nlist
*nlistp
;
206 bfd_reloc_code_real_type reloc
;
209 struct sparc_it the_insn
, set_insn
;
211 static void output_insn
212 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
214 /* Table of arguments to -A.
215 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
216 for this use. That table is for opcodes only. This table is for opcodes
219 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
220 v8plusa
, v9
, v9a
, v9_64
};
222 static struct sparc_arch
{
225 enum sparc_arch_types arch_type
;
226 /* Default word size, as specified during configuration.
227 A value of zero means can't be used to specify default architecture. */
228 int default_arch_size
;
229 /* Allowable arg to -A? */
231 } sparc_arch_table
[] = {
232 { "v6", "v6", v6
, 0, 1 },
233 { "v7", "v7", v7
, 0, 1 },
234 { "v8", "v8", v8
, 32, 1 },
235 { "sparclet", "sparclet", sparclet
, 32, 1 },
236 { "sparclite", "sparclite", sparclite
, 32, 1 },
237 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
238 { "v8plus", "v9", v9
, 0, 1 },
239 { "v8plusa", "v9a", v9
, 0, 1 },
240 { "v9", "v9", v9
, 0, 1 },
241 { "v9a", "v9a", v9
, 0, 1 },
242 /* This exists to allow configure.in/Makefile.in to pass one
243 value to specify both the default machine and default word size. */
244 { "v9-64", "v9", v9
, 64, 0 },
245 { NULL
, NULL
, v8
, 0, 0 }
248 /* Variant of default_arch */
249 static enum sparc_arch_types default_arch_type
;
251 static struct sparc_arch
*
255 struct sparc_arch
*sa
;
257 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
258 if (strcmp (sa
->name
, name
) == 0)
260 if (sa
->name
== NULL
)
265 /* Initialize the default opcode arch and word size from the default
266 architecture name. */
271 struct sparc_arch
*sa
= lookup_arch (default_arch
);
274 || sa
->default_arch_size
== 0)
275 as_fatal (_("Invalid default architecture, broken assembler."));
277 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
278 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
279 as_fatal (_("Bad opcode table, broken assembler."));
280 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
282 default_arch_type
= sa
->arch_type
;
285 /* Called by TARGET_FORMAT. */
288 sparc_target_format ()
290 /* We don't get a chance to initialize anything before we're called,
291 so handle that now. */
292 if (! default_init_p
)
293 init_default_arch ();
297 return "a.out-sparc-netbsd";
300 if (target_big_endian
)
301 return "a.out-sunos-big";
302 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
303 return "a.out-sunos-big";
304 else return "a.out-sparc-little";
306 return "a.out-sunos-big";
317 return "coff-sparc-lynx";
324 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
331 * Invocation line includes a switch not recognized by the base assembler.
332 * See if it's a processor-specific option. These are:
335 * Warn on architecture bumps. See also -A.
337 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
338 * Standard 32 bit architectures.
339 * -Av8plus, -Av8plusa
340 * Sparc64 in a 32 bit world.
342 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
343 * This used to only mean 64 bits, but properly specifying it
344 * complicated gcc's ASM_SPECs, so now opcode selection is
345 * specified orthogonally to word size (except when specifying
346 * the default, but that is an internal implementation detail).
347 * -xarch=v8plus, -xarch=v8plusa
348 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
350 * Select the architecture and possibly the file format.
351 * Instructions or features not supported by the selected
352 * architecture cause fatal errors.
354 * The default is to start at v6, and bump the architecture up
355 * whenever an instruction is seen at a higher level. In 32 bit
356 * environments, v9 is not bumped up to, the user must pass
359 * If -bump is specified, a warning is printing when bumping to
362 * If an architecture is specified, all instructions must match
363 * that architecture. Any higher level instructions are flagged
364 * as errors. Note that in the 32 bit environment specifying
365 * -Av8plus does not automatically create a v8plus object file, a
366 * v9 insn must be seen.
368 * If both an architecture and -bump are specified, the
369 * architecture starts at the specified level, but bumps are
370 * warnings. Note that we can't set `current_architecture' to
371 * the requested level in this case: in the 32 bit environment,
372 * we still must avoid creating v8plus object files unless v9
376 * Bumping between incompatible architectures is always an
377 * error. For example, from sparclite to v9.
381 CONST
char *md_shortopts
= "A:K:VQ:sq";
384 CONST
char *md_shortopts
= "A:k";
386 CONST
char *md_shortopts
= "A:";
389 struct option md_longopts
[] = {
390 #define OPTION_BUMP (OPTION_MD_BASE)
391 {"bump", no_argument
, NULL
, OPTION_BUMP
},
392 #define OPTION_SPARC (OPTION_MD_BASE + 1)
393 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
394 #define OPTION_XARCH (OPTION_MD_BASE + 2)
395 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
397 #define OPTION_32 (OPTION_MD_BASE + 3)
398 {"32", no_argument
, NULL
, OPTION_32
},
399 #define OPTION_64 (OPTION_MD_BASE + 4)
400 {"64", no_argument
, NULL
, OPTION_64
},
401 #define OPTION_TSO (OPTION_MD_BASE + 5)
402 {"TSO", no_argument
, NULL
, OPTION_TSO
},
403 #define OPTION_PSO (OPTION_MD_BASE + 6)
404 {"PSO", no_argument
, NULL
, OPTION_PSO
},
405 #define OPTION_RMO (OPTION_MD_BASE + 7)
406 {"RMO", no_argument
, NULL
, OPTION_RMO
},
408 #ifdef SPARC_BIENDIAN
409 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
410 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
411 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
412 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
414 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
415 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
416 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
417 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
419 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
420 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
421 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
422 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
424 #define OPTION_RELAX (OPTION_MD_BASE + 14)
425 {"relax", no_argument
, NULL
, OPTION_RELAX
},
426 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
427 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
428 {NULL
, no_argument
, NULL
, 0}
431 size_t md_longopts_size
= sizeof (md_longopts
);
434 md_parse_option (c
, arg
)
438 /* We don't get a chance to initialize anything before we're called,
439 so handle that now. */
440 if (! default_init_p
)
441 init_default_arch ();
447 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
451 /* This is for compatibility with Sun's assembler. */
452 if (strcmp (arg
, "v8plus") != 0
453 && strcmp (arg
, "v8plusa") != 0)
455 as_bad (_("invalid architecture -xarch=%s"), arg
);
462 struct sparc_arch
*sa
;
463 enum sparc_opcode_arch_val opcode_arch
;
465 sa
= lookup_arch (arg
);
467 || ! sa
->user_option_p
)
469 as_bad (_("invalid architecture -A%s"), arg
);
473 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
474 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
475 as_fatal (_("Bad opcode table, broken assembler."));
477 max_architecture
= opcode_arch
;
478 architecture_requested
= 1;
483 /* Ignore -sparc, used by SunOS make default .s.o rule. */
486 case OPTION_ENFORCE_ALIGNED_DATA
:
487 enforce_aligned_data
= 1;
490 #ifdef SPARC_BIENDIAN
491 case OPTION_LITTLE_ENDIAN
:
492 target_big_endian
= 0;
493 if (default_arch_type
!= sparclet
)
494 as_fatal ("This target does not support -EL");
496 case OPTION_LITTLE_ENDIAN_DATA
:
497 target_little_endian_data
= 1;
498 target_big_endian
= 0;
499 if (default_arch_type
!= sparc86x
500 && default_arch_type
!= v9
)
501 as_fatal ("This target does not support --little-endian-data");
503 case OPTION_BIG_ENDIAN
:
504 target_big_endian
= 1;
518 const char **list
, **l
;
520 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
521 list
= bfd_target_list ();
522 for (l
= list
; *l
!= NULL
; l
++)
524 if (sparc_arch_size
== 32)
526 if (strcmp (*l
, "elf32-sparc") == 0)
531 if (strcmp (*l
, "elf64-sparc") == 0)
536 as_fatal (_("No compiled in support for %d bit object file format"),
543 sparc_memory_model
= MM_TSO
;
547 sparc_memory_model
= MM_PSO
;
551 sparc_memory_model
= MM_RMO
;
559 /* Qy - do emit .comment
560 Qn - do not emit .comment. */
564 /* Use .stab instead of .stab.excl. */
568 /* quick -- Native assembler does fewer checks. */
572 if (strcmp (arg
, "PIC") != 0)
573 as_warn (_("Unrecognized option following -K"));
578 case OPTION_NO_UNDECLARED_REGS
:
579 no_undeclared_regs
= 1;
582 case OPTION_UNDECLARED_REGS
:
583 no_undeclared_regs
= 0;
591 case OPTION_NO_RELAX
:
603 md_show_usage (stream
)
606 const struct sparc_arch
*arch
;
608 /* We don't get a chance to initialize anything before we're called,
609 so handle that now. */
610 if (! default_init_p
)
611 init_default_arch ();
613 fprintf (stream
, _("SPARC options:\n"));
614 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
616 if (arch
!= &sparc_arch_table
[0])
617 fprintf (stream
, " | ");
618 if (arch
->user_option_p
)
619 fprintf (stream
, "-A%s", arch
->name
);
621 fprintf (stream
, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
622 fprintf (stream
, _("\
623 specify variant of SPARC architecture\n\
624 -bump warn when assembler switches architectures\n\
626 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
627 -relax relax jumps and branches (default)\n\
628 -no-relax avoid changing any jumps and branches\n"));
630 fprintf (stream
, _("\
631 -k generate PIC\n"));
634 fprintf (stream
, _("\
635 -32 create 32 bit object file\n\
636 -64 create 64 bit object file\n"));
637 fprintf (stream
, _("\
638 [default is %d]\n"), default_arch_size
);
639 fprintf (stream
, _("\
640 -TSO use Total Store Ordering\n\
641 -PSO use Partial Store Ordering\n\
642 -RMO use Relaxed Memory Ordering\n"));
643 fprintf (stream
, _("\
644 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
645 fprintf (stream
, _("\
646 -KPIC generate PIC\n\
647 -V print assembler version number\n\
648 -undeclared-regs ignore application global register usage without\n\
649 appropriate .register directive (default)\n\
650 -no-undeclared-regs force error on application global register usage\n\
651 without appropriate .register directive\n\
656 #ifdef SPARC_BIENDIAN
657 fprintf (stream
, _("\
658 -EL generate code for a little endian machine\n\
659 -EB generate code for a big endian machine\n\
660 --little-endian-data generate code for a machine having big endian\n\
661 instructions and little endian data.\n"));
665 /* Native operand size opcode translation. */
671 } native_op_table
[] =
673 {"ldn", "ld", "ldx"},
674 {"ldna", "lda", "ldxa"},
675 {"stn", "st", "stx"},
676 {"stna", "sta", "stxa"},
677 {"slln", "sll", "sllx"},
678 {"srln", "srl", "srlx"},
679 {"sran", "sra", "srax"},
680 {"casn", "cas", "casx"},
681 {"casna", "casa", "casxa"},
682 {"clrn", "clr", "clrx"},
686 /* sparc64 priviledged registers. */
688 struct priv_reg_entry
694 struct priv_reg_entry priv_reg_table
[] =
713 {"", -1}, /* End marker. */
716 /* v9a specific asrs. */
718 struct priv_reg_entry v9a_asr_table
[] =
727 {"clear_softint", 21},
728 {"", -1}, /* End marker. */
732 cmp_reg_entry (parg
, qarg
)
736 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
737 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
739 return strcmp (q
->name
, p
->name
);
742 /* This function is called once, at assembler startup time. It should
743 set up all the tables, etc. that the MD part of the assembler will
749 register const char *retval
= NULL
;
751 register unsigned int i
= 0;
753 /* We don't get a chance to initialize anything before md_parse_option
754 is called, and it may not be called, so handle default initialization
755 now if not already done. */
756 if (! default_init_p
)
757 init_default_arch ();
759 op_hash
= hash_new ();
761 while (i
< (unsigned int) sparc_num_opcodes
)
763 const char *name
= sparc_opcodes
[i
].name
;
764 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
767 as_bad (_("Internal error: can't hash `%s': %s\n"),
768 sparc_opcodes
[i
].name
, retval
);
773 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
775 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
776 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
781 while (i
< (unsigned int) sparc_num_opcodes
782 && !strcmp (sparc_opcodes
[i
].name
, name
));
785 for (i
= 0; native_op_table
[i
].name
; i
++)
787 const struct sparc_opcode
*insn
;
788 char *name
= sparc_arch_size
== 32 ? native_op_table
[i
].name32
:
789 native_op_table
[i
].name64
;
790 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
793 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
794 name
, native_op_table
[i
].name
);
799 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
802 as_bad (_("Internal error: can't hash `%s': %s\n"),
803 sparc_opcodes
[i
].name
, retval
);
810 as_fatal (_("Broken assembler. No assembly attempted."));
812 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
813 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
815 /* If -bump, record the architecture level at which we start issuing
816 warnings. The behaviour is different depending upon whether an
817 architecture was explicitly specified. If it wasn't, we issue warnings
818 for all upwards bumps. If it was, we don't start issuing warnings until
819 we need to bump beyond the requested architecture or when we bump between
820 conflicting architectures. */
823 && architecture_requested
)
825 /* `max_architecture' records the requested architecture.
826 Issue warnings if we go above it. */
827 warn_after_architecture
= max_architecture
;
829 /* Find the highest architecture level that doesn't conflict with
830 the requested one. */
831 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
832 max_architecture
> warn_after_architecture
;
834 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
835 warn_after_architecture
))
840 /* Called after all assembly has been done. */
845 if (sparc_arch_size
== 64)
847 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
848 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
850 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
854 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
855 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
856 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
857 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
858 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
859 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
860 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
861 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclite_le
);
864 /* The sparclite is treated like a normal sparc. Perhaps it
865 shouldn't be but for now it is (since that's the way it's
866 always been treated). */
867 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
872 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
875 in_signed_range (val
, max
)
876 bfd_signed_vma val
, max
;
880 /* Sign-extend the value from the architecture word size, so that
881 0xffffffff is always considered -1 on sparc32. */
882 if (sparc_arch_size
== 32)
884 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
885 val
= ((val
& 0xffffffff) ^ sign
) - sign
;
894 /* Return non-zero if VAL is in the range 0 to MAX. */
897 in_unsigned_range (val
, max
)
905 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
906 (e.g. -15 to +31). */
909 in_bitfield_range (val
, max
)
910 bfd_signed_vma val
, max
;
916 if (val
< ~(max
>> 1))
930 for (i
= 0; (mask
& 1) == 0; ++i
)
935 /* Implement big shift right. */
941 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
942 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
943 return val
>> amount
;
946 /* For communication between sparc_ip and get_expression. */
947 static char *expr_end
;
949 /* Values for `special_case'.
950 Instructions that require wierd handling because they're longer than
952 #define SPECIAL_CASE_NONE 0
953 #define SPECIAL_CASE_SET 1
954 #define SPECIAL_CASE_SETSW 2
955 #define SPECIAL_CASE_SETX 3
956 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
957 #define SPECIAL_CASE_FDIV 4
959 /* Bit masks of various insns. */
960 #define NOP_INSN 0x01000000
961 #define OR_INSN 0x80100000
962 #define XOR_INSN 0x80180000
963 #define FMOVS_INSN 0x81A00020
964 #define SETHI_INSN 0x01000000
965 #define SLLX_INSN 0x81281000
966 #define SRA_INSN 0x81380000
968 /* The last instruction to be assembled. */
969 static const struct sparc_opcode
*last_insn
;
970 /* The assembled opcode of `last_insn'. */
971 static unsigned long last_opcode
;
973 /* Handle the set and setuw synthetic instructions. */
976 synthetize_setuw (insn
)
977 const struct sparc_opcode
*insn
;
980 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
982 if (the_insn
.exp
.X_op
== O_constant
)
984 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
986 if (sizeof (offsetT
) > 4
987 && (the_insn
.exp
.X_add_number
< 0
988 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
989 as_warn (_("set: number not in 0..4294967295 range"));
993 if (sizeof (offsetT
) > 4
994 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
995 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
996 as_warn (_("set: number not in -2147483648..4294967295 range"));
997 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1001 /* See if operand is absolute and small; skip sethi if so. */
1002 if (the_insn
.exp
.X_op
!= O_constant
1003 || the_insn
.exp
.X_add_number
>= (1 << 12)
1004 || the_insn
.exp
.X_add_number
< -(1 << 12))
1006 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1007 | ((the_insn
.exp
.X_add_number
>> 10)
1008 & (the_insn
.exp
.X_op
== O_constant
? 0x3fffff : 0)));
1009 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1012 output_insn (insn
, &the_insn
);
1016 /* See if operand has no low-order bits; skip OR if so. */
1017 if (the_insn
.exp
.X_op
!= O_constant
1018 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1021 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1023 | (the_insn
.exp
.X_add_number
1024 & (the_insn
.exp
.X_op
!= O_constant
? 0 :
1025 need_hi22_p
? 0x3ff : 0x1fff)));
1026 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1029 output_insn (insn
, &the_insn
);
1033 /* Handle the setsw synthetic instruction. */
1036 synthetize_setsw (insn
)
1037 const struct sparc_opcode
*insn
;
1041 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1043 if (the_insn
.exp
.X_op
!= O_constant
)
1045 synthetize_setuw (insn
);
1047 /* Need to sign extend it. */
1048 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1049 the_insn
.reloc
= BFD_RELOC_NONE
;
1050 output_insn (insn
, &the_insn
);
1054 if (sizeof (offsetT
) > 4
1055 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
1056 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
1057 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1059 low32
= the_insn
.exp
.X_add_number
;
1063 synthetize_setuw (insn
);
1069 the_insn
.reloc
= BFD_RELOC_NONE
;
1070 /* See if operand is absolute and small; skip sethi if so. */
1071 if (low32
< -(1 << 12))
1073 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1074 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1075 output_insn (insn
, &the_insn
);
1076 low32
= 0x1c00 | (low32
& 0x3ff);
1077 opc
= RS1 (rd
) | XOR_INSN
;
1080 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1081 | (low32
& 0x1fff));
1082 output_insn (insn
, &the_insn
);
1085 /* Handle the setsw synthetic instruction. */
1088 synthetize_setx (insn
)
1089 const struct sparc_opcode
*insn
;
1091 int upper32
, lower32
;
1092 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1093 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1095 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1096 int need_xor10_p
= 0;
1098 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1099 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1100 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1103 upper_dstreg
= tmpreg
;
1104 /* The tmp reg should not be the dst reg. */
1105 if (tmpreg
== dstreg
)
1106 as_warn (_("setx: temporary register same as destination register"));
1108 /* ??? Obviously there are other optimizations we can do
1109 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1110 doing some of these. Later. If you do change things, try to
1111 change all of this to be table driven as well. */
1112 /* What to output depends on the number if it's constant.
1113 Compute that first, then output what we've decided upon. */
1114 if (the_insn
.exp
.X_op
!= O_constant
)
1116 if (sparc_arch_size
== 32)
1118 /* When arch size is 32, we want setx to be equivalent
1119 to setuw for anything but constants. */
1120 the_insn
.exp
.X_add_number
&= 0xffffffff;
1121 synthetize_setuw (insn
);
1124 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1125 lower32
= 0; upper32
= 0;
1129 /* Reset X_add_number, we've extracted it as upper32/lower32.
1130 Otherwise fixup_segment will complain about not being able to
1131 write an 8 byte number in a 4 byte field. */
1132 the_insn
.exp
.X_add_number
= 0;
1134 /* Only need hh22 if `or' insn can't handle constant. */
1135 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1138 /* Does bottom part (after sethi) have bits? */
1139 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1140 /* No hh22, but does upper32 still have bits we can't set
1142 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1145 /* If the lower half is all zero, we build the upper half directly
1146 into the dst reg. */
1148 /* Need lower half if number is zero or 0xffffffff00000000. */
1149 || (! need_hh22_p
&& ! need_hm10_p
))
1151 /* No need for sethi if `or' insn can handle constant. */
1152 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1153 /* Note that we can't use a negative constant in the `or'
1154 insn unless the upper 32 bits are all ones. */
1155 || (lower32
< 0 && upper32
!= -1)
1156 || (lower32
>= 0 && upper32
== -1))
1159 if (need_hi22_p
&& upper32
== -1)
1162 /* Does bottom part (after sethi) have bits? */
1163 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1165 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1166 /* Need `or' if we didn't set anything else. */
1167 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1171 /* Output directly to dst reg if lower 32 bits are all zero. */
1172 upper_dstreg
= dstreg
;
1175 if (!upper_dstreg
&& dstreg
)
1176 as_warn (_("setx: illegal temporary register g0"));
1180 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1181 | ((upper32
>> 10) & 0x3fffff));
1182 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1183 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1184 output_insn (insn
, &the_insn
);
1189 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1190 | (((need_xor10_p
? ~lower32
: lower32
)
1191 >> 10) & 0x3fffff));
1192 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1193 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1194 output_insn (insn
, &the_insn
);
1199 the_insn
.opcode
= (OR_INSN
1200 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1203 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1204 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1205 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1206 output_insn (insn
, &the_insn
);
1211 /* FIXME: One nice optimization to do here is to OR the low part
1212 with the highpart if hi22 isn't needed and the low part is
1214 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1217 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1218 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1219 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1220 output_insn (insn
, &the_insn
);
1223 /* If we needed to build the upper part, shift it into place. */
1224 if (need_hh22_p
|| need_hm10_p
)
1226 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1228 the_insn
.reloc
= BFD_RELOC_NONE
;
1229 output_insn (insn
, &the_insn
);
1232 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1235 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1236 | 0x1c00 | (lower32
& 0x3ff));
1237 the_insn
.reloc
= BFD_RELOC_NONE
;
1238 output_insn (insn
, &the_insn
);
1241 /* If we needed to build both upper and lower parts, OR them together. */
1242 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1244 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1246 the_insn
.reloc
= BFD_RELOC_NONE
;
1247 output_insn (insn
, &the_insn
);
1251 /* Main entry point to assemble one instruction. */
1257 const struct sparc_opcode
*insn
;
1261 special_case
= sparc_ip (str
, &insn
);
1263 /* We warn about attempts to put a floating point branch in a delay slot,
1264 unless the delay slot has been annulled. */
1266 && last_insn
!= NULL
1267 && (insn
->flags
& F_FBR
) != 0
1268 && (last_insn
->flags
& F_DELAYED
) != 0
1269 /* ??? This test isn't completely accurate. We assume anything with
1270 F_{UNBR,CONDBR,FBR} set is annullable. */
1271 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1272 || (last_opcode
& ANNUL
) == 0))
1273 as_warn (_("FP branch in delay slot"));
1275 /* SPARC before v9 requires a nop instruction between a floating
1276 point instruction and a floating point branch. We insert one
1277 automatically, with a warning. */
1278 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1280 && last_insn
!= NULL
1281 && (insn
->flags
& F_FBR
) != 0
1282 && (last_insn
->flags
& F_FLOAT
) != 0)
1284 struct sparc_it nop_insn
;
1286 nop_insn
.opcode
= NOP_INSN
;
1287 nop_insn
.reloc
= BFD_RELOC_NONE
;
1288 output_insn (insn
, &nop_insn
);
1289 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1292 switch (special_case
)
1294 case SPECIAL_CASE_NONE
:
1296 output_insn (insn
, &the_insn
);
1299 case SPECIAL_CASE_SETSW
:
1300 synthetize_setsw (insn
);
1303 case SPECIAL_CASE_SET
:
1304 synthetize_setuw (insn
);
1307 case SPECIAL_CASE_SETX
:
1308 synthetize_setx (insn
);
1311 case SPECIAL_CASE_FDIV
:
1313 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1315 output_insn (insn
, &the_insn
);
1317 /* According to information leaked from Sun, the "fdiv" instructions
1318 on early SPARC machines would produce incorrect results sometimes.
1319 The workaround is to add an fmovs of the destination register to
1320 itself just after the instruction. This was true on machines
1321 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1322 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1323 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1324 output_insn (insn
, &the_insn
);
1329 as_fatal (_("failed special case insn sanity check"));
1333 /* Subroutine of md_assemble to do the actual parsing. */
1336 sparc_ip (str
, pinsn
)
1338 const struct sparc_opcode
**pinsn
;
1340 char *error_message
= "";
1344 const struct sparc_opcode
*insn
;
1346 unsigned long opcode
;
1347 unsigned int mask
= 0;
1351 int special_case
= SPECIAL_CASE_NONE
;
1354 if (islower ((unsigned char) *s
))
1358 while (islower ((unsigned char) *s
) || isdigit ((unsigned char) *s
));
1375 as_fatal (_("Unknown opcode: `%s'"), str
);
1377 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1381 as_bad (_("Unknown opcode: `%s'"), str
);
1382 return special_case
;
1392 opcode
= insn
->match
;
1393 memset (&the_insn
, '\0', sizeof (the_insn
));
1394 the_insn
.reloc
= BFD_RELOC_NONE
;
1397 /* Build the opcode, checking as we go to make sure that the
1399 for (args
= insn
->args
;; ++args
)
1407 /* Parse a series of masks. */
1414 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1417 error_message
= _(": invalid membar mask name");
1421 while (*s
== ' ') { ++s
; continue; }
1422 if (*s
== '|' || *s
== '+')
1424 while (*s
== ' ') { ++s
; continue; }
1429 if (! parse_const_expr_arg (&s
, &kmask
))
1431 error_message
= _(": invalid membar mask expression");
1434 if (kmask
< 0 || kmask
> 127)
1436 error_message
= _(": invalid membar mask number");
1441 opcode
|= MEMBAR (kmask
);
1449 /* Parse a prefetch function. */
1452 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1454 error_message
= _(": invalid prefetch function name");
1460 if (! parse_const_expr_arg (&s
, &fcn
))
1462 error_message
= _(": invalid prefetch function expression");
1465 if (fcn
< 0 || fcn
> 31)
1467 error_message
= _(": invalid prefetch function number");
1477 /* Parse a sparc64 privileged register. */
1480 struct priv_reg_entry
*p
= priv_reg_table
;
1481 unsigned int len
= 9999999; /* Init to make gcc happy. */
1484 while (p
->name
[0] > s
[0])
1486 while (p
->name
[0] == s
[0])
1488 len
= strlen (p
->name
);
1489 if (strncmp (p
->name
, s
, len
) == 0)
1493 if (p
->name
[0] != s
[0])
1495 error_message
= _(": unrecognizable privileged register");
1499 opcode
|= (p
->regnum
<< 14);
1501 opcode
|= (p
->regnum
<< 25);
1507 error_message
= _(": unrecognizable privileged register");
1513 /* Parse a v9a ancillary state register. */
1516 struct priv_reg_entry
*p
= v9a_asr_table
;
1517 unsigned int len
= 9999999; /* Init to make gcc happy. */
1520 while (p
->name
[0] > s
[0])
1522 while (p
->name
[0] == s
[0])
1524 len
= strlen (p
->name
);
1525 if (strncmp (p
->name
, s
, len
) == 0)
1529 if (p
->name
[0] != s
[0])
1531 error_message
= _(": unrecognizable v9a ancillary state register");
1534 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1536 error_message
= _(": rd on write only ancillary state register");
1540 opcode
|= (p
->regnum
<< 14);
1542 opcode
|= (p
->regnum
<< 25);
1548 error_message
= _(": unrecognizable v9a ancillary state register");
1554 if (strncmp (s
, "%asr", 4) == 0)
1558 if (isdigit ((unsigned char) *s
))
1562 while (isdigit ((unsigned char) *s
))
1564 num
= num
* 10 + *s
- '0';
1568 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1570 if (num
< 16 || 31 < num
)
1572 error_message
= _(": asr number must be between 16 and 31");
1578 if (num
< 0 || 31 < num
)
1580 error_message
= _(": asr number must be between 0 and 31");
1585 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1590 error_message
= _(": expecting %asrN");
1597 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1601 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1605 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1606 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1607 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1609 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1610 /* These fields are unsigned, but for upward compatibility,
1611 allow negative values as well. */
1615 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1616 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1617 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1619 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1620 /* These fields are unsigned, but for upward compatibility,
1621 allow negative values as well. */
1625 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1630 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1635 if (*s
== 'p' && s
[1] == 'n')
1643 if (*s
== 'p' && s
[1] == 't')
1655 if (strncmp (s
, "%icc", 4) == 0)
1667 if (strncmp (s
, "%xcc", 4) == 0)
1679 if (strncmp (s
, "%fcc0", 5) == 0)
1691 if (strncmp (s
, "%fcc1", 5) == 0)
1703 if (strncmp (s
, "%fcc2", 5) == 0)
1715 if (strncmp (s
, "%fcc3", 5) == 0)
1723 if (strncmp (s
, "%pc", 3) == 0)
1731 if (strncmp (s
, "%tick", 5) == 0)
1738 case '\0': /* End of args. */
1757 case '[': /* These must match exactly. */
1765 case '#': /* Must be at least one digit. */
1766 if (isdigit ((unsigned char) *s
++))
1768 while (isdigit ((unsigned char) *s
))
1776 case 'C': /* Coprocessor state register. */
1777 if (strncmp (s
, "%csr", 4) == 0)
1784 case 'b': /* Next operand is a coprocessor register. */
1787 if (*s
++ == '%' && *s
++ == 'c' && isdigit ((unsigned char) *s
))
1790 if (isdigit ((unsigned char) *s
))
1792 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1806 opcode
|= mask
<< 14;
1814 opcode
|= mask
<< 25;
1820 case 'r': /* next operand must be a register */
1830 case 'f': /* frame pointer */
1838 case 'g': /* global register */
1847 case 'i': /* in register */
1851 mask
= c
- '0' + 24;
1856 case 'l': /* local register */
1860 mask
= (c
- '0' + 16);
1865 case 'o': /* out register */
1869 mask
= (c
- '0' + 8);
1874 case 's': /* stack pointer */
1882 case 'r': /* any register */
1883 if (!isdigit ((unsigned char) (c
= *s
++)))
1898 if (isdigit ((unsigned char) *s
))
1900 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1916 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
1917 && no_undeclared_regs
&& ! globals
[mask
])
1918 as_bad (_("detected global register use not covered by .register pseudo-op"));
1920 /* Got the register, now figure out where
1921 it goes in the opcode. */
1925 opcode
|= mask
<< 14;
1933 opcode
|= mask
<< 25;
1937 opcode
|= (mask
<< 25) | (mask
<< 14);
1941 opcode
|= (mask
<< 25) | (mask
<< 0);
1947 case 'e': /* next operand is a floating point register */
1962 && ((format
= *s
) == 'f')
1963 && isdigit ((unsigned char) *++s
))
1965 for (mask
= 0; isdigit ((unsigned char) *s
); ++s
)
1967 mask
= 10 * mask
+ (*s
- '0');
1968 } /* read the number */
1976 } /* register must be even numbered */
1984 } /* register must be multiple of 4 */
1988 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1989 error_message
= _(": There are only 64 f registers; [0-63]");
1991 error_message
= _(": There are only 32 f registers; [0-31]");
1994 else if (mask
>= 32)
1996 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1999 mask
-= 31; /* wrap high bit */
2003 error_message
= _(": There are only 32 f registers; [0-31]");
2011 } /* if not an 'f' register. */
2018 opcode
|= RS1 (mask
);
2024 opcode
|= RS2 (mask
);
2030 opcode
|= RD (mask
);
2039 if (strncmp (s
, "%fsr", 4) == 0)
2046 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2047 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2050 case 'l': /* 22 bit PC relative immediate */
2051 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2055 case 'L': /* 30 bit immediate */
2056 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2061 case 'n': /* 22 bit immediate */
2062 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2065 case 'i': /* 13 bit immediate */
2066 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2076 char *op_arg
= NULL
;
2078 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2080 /* Check for %hi, etc. */
2083 static const struct ops
{
2084 /* The name as it appears in assembler. */
2086 /* strlen (name), precomputed for speed */
2088 /* The reloc this pseudo-op translates to. */
2090 /* Non-zero if for v9 only. */
2092 /* Non-zero if can be used in pc-relative contexts. */
2093 int pcrel_p
;/*FIXME:wip*/
2095 /* hix/lox must appear before hi/lo so %hix won't be
2096 mistaken for %hi. */
2097 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2098 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2099 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2100 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2101 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2102 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2103 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2104 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2105 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2106 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2107 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2108 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2111 const struct ops
*o
;
2113 for (o
= ops
; o
->name
; o
++)
2114 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2116 if (o
->name
== NULL
)
2119 if (s
[o
->len
+ 1] != '(')
2121 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2122 return special_case
;
2126 the_insn
.reloc
= o
->reloc
;
2131 /* Note that if the get_expression() fails, we will still
2132 have created U entries in the symbol table for the
2133 'symbols' in the input string. Try not to create U
2134 symbols for registers, etc. */
2136 /* This stuff checks to see if the expression ends in
2137 +%reg. If it does, it removes the register from
2138 the expression, and re-sets 's' to point to the
2145 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2148 else if (*s1
== ')')
2157 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2158 return special_case
;
2162 (void) get_expression (s
);
2165 if (*s
== ',' || *s
== ']' || !*s
)
2167 if (*s
!= '+' && *s
!= '-')
2169 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2170 return special_case
;
2174 op_exp
= the_insn
.exp
;
2175 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2178 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2181 if (s1
!= s
&& isdigit ((unsigned char) s1
[-1]))
2183 if (s1
[-2] == '%' && s1
[-3] == '+')
2185 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2192 if (op_arg
&& s1
== s
+ 1)
2193 the_insn
.exp
.X_op
= O_absent
;
2195 (void) get_expression (s
);
2207 (void) get_expression (s
);
2215 the_insn
.exp2
= the_insn
.exp
;
2216 the_insn
.exp
= op_exp
;
2217 if (the_insn
.exp2
.X_op
== O_absent
)
2218 the_insn
.exp2
.X_op
= O_illegal
;
2219 else if (the_insn
.exp
.X_op
== O_absent
)
2221 the_insn
.exp
= the_insn
.exp2
;
2222 the_insn
.exp2
.X_op
= O_illegal
;
2224 else if (the_insn
.exp
.X_op
== O_constant
)
2226 valueT val
= the_insn
.exp
.X_add_number
;
2227 switch (the_insn
.reloc
)
2232 case BFD_RELOC_SPARC_HH22
:
2233 val
= BSR (val
, 32);
2236 case BFD_RELOC_SPARC_LM22
:
2237 case BFD_RELOC_HI22
:
2238 val
= (val
>> 10) & 0x3fffff;
2241 case BFD_RELOC_SPARC_HM10
:
2242 val
= BSR (val
, 32);
2245 case BFD_RELOC_LO10
:
2249 case BFD_RELOC_SPARC_H44
:
2254 case BFD_RELOC_SPARC_M44
:
2259 case BFD_RELOC_SPARC_L44
:
2263 case BFD_RELOC_SPARC_HIX22
:
2265 val
= (val
>> 10) & 0x3fffff;
2268 case BFD_RELOC_SPARC_LOX10
:
2269 val
= (val
& 0x3ff) | 0x1c00;
2272 the_insn
.exp
= the_insn
.exp2
;
2273 the_insn
.exp
.X_add_number
+= val
;
2274 the_insn
.exp2
.X_op
= O_illegal
;
2275 the_insn
.reloc
= old_reloc
;
2277 else if (the_insn
.exp2
.X_op
!= O_constant
)
2279 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2280 return special_case
;
2284 if (old_reloc
!= BFD_RELOC_SPARC13
2285 || the_insn
.reloc
!= BFD_RELOC_LO10
2286 || sparc_arch_size
!= 64
2289 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2290 return special_case
;
2292 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2296 /* Check for constants that don't require emitting a reloc. */
2297 if (the_insn
.exp
.X_op
== O_constant
2298 && the_insn
.exp
.X_add_symbol
== 0
2299 && the_insn
.exp
.X_op_symbol
== 0)
2301 /* For pc-relative call instructions, we reject
2302 constants to get better code. */
2304 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2305 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2307 error_message
= _(": PC-relative operand can't be a constant");
2311 /* Constants that won't fit are checked in md_apply_fix3
2312 and bfd_install_relocation.
2313 ??? It would be preferable to install the constants
2314 into the insn here and save having to create a fixS
2315 for each one. There already exists code to handle
2316 all the various cases (e.g. in md_apply_fix3 and
2317 bfd_install_relocation) so duplicating all that code
2318 here isn't right. */
2338 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2340 error_message
= _(": invalid ASI name");
2346 if (! parse_const_expr_arg (&s
, &asi
))
2348 error_message
= _(": invalid ASI expression");
2351 if (asi
< 0 || asi
> 255)
2353 error_message
= _(": invalid ASI number");
2357 opcode
|= ASI (asi
);
2359 } /* Alternate space. */
2362 if (strncmp (s
, "%psr", 4) == 0)
2369 case 'q': /* Floating point queue. */
2370 if (strncmp (s
, "%fq", 3) == 0)
2377 case 'Q': /* Coprocessor queue. */
2378 if (strncmp (s
, "%cq", 3) == 0)
2386 if (strcmp (str
, "set") == 0
2387 || strcmp (str
, "setuw") == 0)
2389 special_case
= SPECIAL_CASE_SET
;
2392 else if (strcmp (str
, "setsw") == 0)
2394 special_case
= SPECIAL_CASE_SETSW
;
2397 else if (strcmp (str
, "setx") == 0)
2399 special_case
= SPECIAL_CASE_SETX
;
2402 else if (strncmp (str
, "fdiv", 4) == 0)
2404 special_case
= SPECIAL_CASE_FDIV
;
2410 if (strncmp (s
, "%asi", 4) != 0)
2416 if (strncmp (s
, "%fprs", 5) != 0)
2422 if (strncmp (s
, "%ccr", 4) != 0)
2428 if (strncmp (s
, "%tbr", 4) != 0)
2434 if (strncmp (s
, "%wim", 4) != 0)
2441 char *push
= input_line_pointer
;
2444 input_line_pointer
= s
;
2446 if (e
.X_op
== O_constant
)
2448 int n
= e
.X_add_number
;
2449 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2450 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2452 opcode
|= e
.X_add_number
<< 5;
2455 as_bad (_("non-immediate OPF operand, ignored"));
2456 s
= input_line_pointer
;
2457 input_line_pointer
= push
;
2462 if (strncmp (s
, "%y", 2) != 0)
2470 /* Parse a sparclet cpreg. */
2472 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2474 error_message
= _(": invalid cpreg name");
2477 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2482 as_fatal (_("failed sanity check."));
2483 } /* switch on arg code. */
2485 /* Break out of for() loop. */
2487 } /* For each arg that we expect. */
2492 /* Args don't match. */
2493 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2494 && (insn
->name
== insn
[1].name
2495 || !strcmp (insn
->name
, insn
[1].name
)))
2503 as_bad (_("Illegal operands%s"), error_message
);
2504 return special_case
;
2509 /* We have a match. Now see if the architecture is OK. */
2510 int needed_arch_mask
= insn
->architecture
;
2514 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
2515 | (1 << SPARC_OPCODE_ARCH_V9A
));
2516 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2519 if (needed_arch_mask
2520 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2523 /* Can we bump up the architecture? */
2524 else if (needed_arch_mask
2525 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2527 enum sparc_opcode_arch_val needed_architecture
=
2528 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2529 & needed_arch_mask
);
2531 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2533 && needed_architecture
> warn_after_architecture
)
2535 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2536 sparc_opcode_archs
[current_architecture
].name
,
2537 sparc_opcode_archs
[needed_architecture
].name
,
2539 warn_after_architecture
= needed_architecture
;
2541 current_architecture
= needed_architecture
;
2544 /* ??? This seems to be a bit fragile. What if the next entry in
2545 the opcode table is the one we want and it is supported?
2546 It is possible to arrange the table today so that this can't
2547 happen but what about tomorrow? */
2550 int arch
, printed_one_p
= 0;
2552 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2554 /* Create a list of the architectures that support the insn. */
2555 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2557 arch
= sparc_ffs (needed_arch_mask
);
2558 while ((1 << arch
) <= needed_arch_mask
)
2560 if ((1 << arch
) & needed_arch_mask
)
2564 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2571 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2572 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2574 sparc_opcode_archs
[max_architecture
].name
);
2575 return special_case
;
2577 } /* If no match. */
2580 } /* Forever looking for a match. */
2582 the_insn
.opcode
= opcode
;
2583 return special_case
;
2586 /* Parse an argument that can be expressed as a keyword.
2587 (eg: #StoreStore or %ccfr).
2588 The result is a boolean indicating success.
2589 If successful, INPUT_POINTER is updated. */
2592 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2593 int (*lookup_fn
) PARAMS ((const char *));
2594 char **input_pointerP
;
2600 p
= *input_pointerP
;
2601 for (q
= p
+ (*p
== '#' || *p
== '%');
2602 isalnum ((unsigned char) *q
) || *q
== '_';
2607 value
= (*lookup_fn
) (p
);
2612 *input_pointerP
= q
;
2616 /* Parse an argument that is a constant expression.
2617 The result is a boolean indicating success. */
2620 parse_const_expr_arg (input_pointerP
, valueP
)
2621 char **input_pointerP
;
2624 char *save
= input_line_pointer
;
2627 input_line_pointer
= *input_pointerP
;
2628 /* The next expression may be something other than a constant
2629 (say if we're not processing the right variant of the insn).
2630 Don't call expression unless we're sure it will succeed as it will
2631 signal an error (which we want to defer until later). */
2632 /* FIXME: It might be better to define md_operand and have it recognize
2633 things like %asi, etc. but continuing that route through to the end
2634 is a lot of work. */
2635 if (*input_line_pointer
== '%')
2637 input_line_pointer
= save
;
2641 *input_pointerP
= input_line_pointer
;
2642 input_line_pointer
= save
;
2643 if (exp
.X_op
!= O_constant
)
2645 *valueP
= exp
.X_add_number
;
2649 /* Subroutine of sparc_ip to parse an expression. */
2652 get_expression (str
)
2658 save_in
= input_line_pointer
;
2659 input_line_pointer
= str
;
2660 seg
= expression (&the_insn
.exp
);
2661 if (seg
!= absolute_section
2662 && seg
!= text_section
2663 && seg
!= data_section
2664 && seg
!= bss_section
2665 && seg
!= undefined_section
)
2667 the_insn
.error
= _("bad segment");
2668 expr_end
= input_line_pointer
;
2669 input_line_pointer
= save_in
;
2672 expr_end
= input_line_pointer
;
2673 input_line_pointer
= save_in
;
2677 /* Subroutine of md_assemble to output one insn. */
2680 output_insn (insn
, the_insn
)
2681 const struct sparc_opcode
*insn
;
2682 struct sparc_it
*the_insn
;
2684 char *toP
= frag_more (4);
2686 /* Put out the opcode. */
2687 if (INSN_BIG_ENDIAN
)
2688 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2690 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2692 /* Put out the symbol-dependent stuff. */
2693 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2695 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
2696 (toP
- frag_now
->fr_literal
), /* Where. */
2701 /* Turn off overflow checking in fixup_segment. We'll do our
2702 own overflow checking in md_apply_fix3. This is necessary because
2703 the insn size is 4 and fixup_segment will signal an overflow for
2704 large 8 byte quantities. */
2705 fixP
->fx_no_overflow
= 1;
2706 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2707 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2711 last_opcode
= the_insn
->opcode
;
2714 /* This is identical to the md_atof in m68k.c. I think this is right,
2717 Turn a string in input_line_pointer into a floating point constant
2718 of type TYPE, and store the appropriate bytes in *LITP. The number
2719 of LITTLENUMS emitted is stored in *SIZEP. An error message is
2720 returned, or NULL on OK. */
2722 /* Equal to MAX_PRECISION in atof-ieee.c. */
2723 #define MAX_LITTLENUMS 6
2726 md_atof (type
, litP
, sizeP
)
2732 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2763 return _("Bad call to MD_ATOF()");
2766 t
= atof_ieee (input_line_pointer
, type
, words
);
2768 input_line_pointer
= t
;
2769 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2771 if (target_big_endian
)
2773 for (i
= 0; i
< prec
; i
++)
2775 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2776 litP
+= sizeof (LITTLENUM_TYPE
);
2781 for (i
= prec
- 1; i
>= 0; i
--)
2783 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2784 litP
+= sizeof (LITTLENUM_TYPE
);
2791 /* Write a value out to the object file, using the appropriate
2795 md_number_to_chars (buf
, val
, n
)
2800 if (target_big_endian
)
2801 number_to_chars_bigendian (buf
, val
, n
);
2802 else if (target_little_endian_data
2803 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2804 /* Output debug words, which are not in allocated sections, as big
2806 number_to_chars_bigendian (buf
, val
, n
);
2807 else if (target_little_endian_data
|| ! target_big_endian
)
2808 number_to_chars_littleendian (buf
, val
, n
);
2811 /* Apply a fixS to the frags, now that we know the value it ought to
2815 md_apply_fix3 (fixP
, value
, segment
)
2820 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2826 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2828 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
2831 /* FIXME: SPARC ELF relocations don't use an addend in the data
2832 field itself. This whole approach should be somehow combined
2833 with the calls to bfd_install_relocation. Also, the value passed
2834 in by fixup_segment includes the value of a defined symbol. We
2835 don't want to include the value of an externally visible symbol. */
2836 if (fixP
->fx_addsy
!= NULL
)
2838 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
2839 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2840 || S_IS_WEAK (fixP
->fx_addsy
)
2841 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2842 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2843 && ((bfd_get_section_flags (stdoutput
,
2844 S_GET_SEGMENT (fixP
->fx_addsy
))
2845 & SEC_LINK_ONCE
) != 0
2846 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2848 sizeof ".gnu.linkonce" - 1) == 0)))
2849 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2850 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2851 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2852 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2857 /* This is a hack. There should be a better way to
2858 handle this. Probably in terms of howto fields, once
2859 we can look at these fixups in terms of howtos. */
2860 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2861 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2864 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2865 generate a reloc, then we just want to let the reloc addend set
2866 the value. We do not want to also stuff the addend into the
2867 object file. Including the addend in the object file works when
2868 doing a static link, because the linker will ignore the object
2869 file contents. However, the dynamic linker does not ignore the
2870 object file contents. */
2871 if (fixP
->fx_addsy
!= NULL
2872 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2875 /* When generating PIC code, we do not want an addend for a reloc
2876 against a local symbol. We adjust fx_addnumber to cancel out the
2877 value already included in val, and to also cancel out the
2878 adjustment which bfd_install_relocation will create. */
2880 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2881 && fixP
->fx_addsy
!= NULL
2882 && ! S_IS_COMMON (fixP
->fx_addsy
)
2883 && symbol_section_p (fixP
->fx_addsy
))
2884 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2886 /* When generating PIC code, we need to fiddle to get
2887 bfd_install_relocation to do the right thing for a PC relative
2888 reloc against a local symbol which we are going to keep. */
2890 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
2891 && fixP
->fx_addsy
!= NULL
2892 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2893 || S_IS_WEAK (fixP
->fx_addsy
))
2894 && S_IS_DEFINED (fixP
->fx_addsy
)
2895 && ! S_IS_COMMON (fixP
->fx_addsy
))
2898 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2902 /* If this is a data relocation, just output VAL. */
2904 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2906 md_number_to_chars (buf
, val
, 2);
2908 else if (fixP
->fx_r_type
== BFD_RELOC_32
2909 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
2911 md_number_to_chars (buf
, val
, 4);
2913 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2915 md_number_to_chars (buf
, val
, 8);
2917 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2918 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2925 /* It's a relocation against an instruction. */
2927 if (INSN_BIG_ENDIAN
)
2928 insn
= bfd_getb32 ((unsigned char *) buf
);
2930 insn
= bfd_getl32 ((unsigned char *) buf
);
2932 switch (fixP
->fx_r_type
)
2934 case BFD_RELOC_32_PCREL_S2
:
2936 /* FIXME: This increment-by-one deserves a comment of why it's
2938 if (! sparc_pic_code
2939 || fixP
->fx_addsy
== NULL
2940 || symbol_section_p (fixP
->fx_addsy
))
2943 insn
|= val
& 0x3fffffff;
2945 /* See if we have a delay slot. */
2946 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
2950 #define XCC (2 << 20)
2951 #define COND(x) (((x)&0xf)<<25)
2952 #define CONDA COND(0x8)
2953 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
2954 #define INSN_BA (F2(0,2) | CONDA)
2955 #define INSN_OR F3(2, 0x2, 0)
2956 #define INSN_NOP F2(0,4)
2960 /* If the instruction is a call with either:
2962 arithmetic instruction with rd == %o7
2963 where rs1 != %o7 and rs2 if it is register != %o7
2964 then we can optimize if the call destination is near
2965 by changing the call into a branch always. */
2966 if (INSN_BIG_ENDIAN
)
2967 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
2969 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
2970 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
2972 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
2973 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
2974 || ((delay
& RD (~0)) != RD (O7
))))
2976 if ((delay
& RS1 (~0)) == RS1 (O7
)
2977 || ((delay
& F3I (~0)) == 0
2978 && (delay
& RS2 (~0)) == RS2 (O7
)))
2980 /* Ensure the branch will fit into simm22. */
2981 if ((val
& 0x3fe00000)
2982 && (val
& 0x3fe00000) != 0x3fe00000)
2984 /* Check if the arch is v9 and branch will fit
2986 if (((val
& 0x3c0000) == 0
2987 || (val
& 0x3c0000) == 0x3c0000)
2988 && (sparc_arch_size
== 64
2989 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
2991 insn
= INSN_BPA
| (val
& 0x7ffff);
2994 insn
= INSN_BA
| (val
& 0x3fffff);
2995 if (fixP
->fx_where
>= 4
2996 && ((delay
& (0xffffffff ^ RS1 (~0)))
2997 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3002 if (INSN_BIG_ENDIAN
)
3003 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3005 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3006 if ((setter
& (0xffffffff ^ RD (~0)))
3007 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3014 If call foo was replaced with ba, replace
3015 or %rN, %g0, %o7 with nop. */
3016 reg
= (delay
& RS1 (~0)) >> 14;
3017 if (reg
!= ((setter
& RD (~0)) >> 25)
3018 || reg
== G0
|| reg
== O7
)
3021 if (INSN_BIG_ENDIAN
)
3022 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3024 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3029 case BFD_RELOC_SPARC_11
:
3030 if (! in_signed_range (val
, 0x7ff))
3031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3032 _("relocation overflow"));
3033 insn
|= val
& 0x7ff;
3036 case BFD_RELOC_SPARC_10
:
3037 if (! in_signed_range (val
, 0x3ff))
3038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3039 _("relocation overflow"));
3040 insn
|= val
& 0x3ff;
3043 case BFD_RELOC_SPARC_7
:
3044 if (! in_bitfield_range (val
, 0x7f))
3045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3046 _("relocation overflow"));
3050 case BFD_RELOC_SPARC_6
:
3051 if (! in_bitfield_range (val
, 0x3f))
3052 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3053 _("relocation overflow"));
3057 case BFD_RELOC_SPARC_5
:
3058 if (! in_bitfield_range (val
, 0x1f))
3059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3060 _("relocation overflow"));
3064 case BFD_RELOC_SPARC_WDISP16
:
3065 /* FIXME: simplify. */
3066 if (((val
> 0) && (val
& ~0x3fffc))
3067 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
3068 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3069 _("relocation overflow"));
3070 /* FIXME: The +1 deserves a comment. */
3071 val
= (val
>> 2) + 1;
3072 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3075 case BFD_RELOC_SPARC_WDISP19
:
3076 /* FIXME: simplify. */
3077 if (((val
> 0) && (val
& ~0x1ffffc))
3078 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
3079 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3080 _("relocation overflow"));
3081 /* FIXME: The +1 deserves a comment. */
3082 val
= (val
>> 2) + 1;
3083 insn
|= val
& 0x7ffff;
3086 case BFD_RELOC_SPARC_HH22
:
3087 val
= BSR (val
, 32);
3090 case BFD_RELOC_SPARC_LM22
:
3091 case BFD_RELOC_HI22
:
3092 if (!fixP
->fx_addsy
)
3094 insn
|= (val
>> 10) & 0x3fffff;
3098 /* FIXME: Need comment explaining why we do this. */
3103 case BFD_RELOC_SPARC22
:
3104 if (val
& ~0x003fffff)
3105 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3106 _("relocation overflow"));
3107 insn
|= (val
& 0x3fffff);
3110 case BFD_RELOC_SPARC_HM10
:
3111 val
= BSR (val
, 32);
3114 case BFD_RELOC_LO10
:
3115 if (!fixP
->fx_addsy
)
3117 insn
|= val
& 0x3ff;
3121 /* FIXME: Need comment explaining why we do this. */
3126 case BFD_RELOC_SPARC_OLO10
:
3128 val
+= fixP
->tc_fix_data
;
3131 case BFD_RELOC_SPARC13
:
3132 if (! in_signed_range (val
, 0x1fff))
3133 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3134 _("relocation overflow"));
3135 insn
|= val
& 0x1fff;
3138 case BFD_RELOC_SPARC_WDISP22
:
3139 val
= (val
>> 2) + 1;
3141 case BFD_RELOC_SPARC_BASE22
:
3142 insn
|= val
& 0x3fffff;
3145 case BFD_RELOC_SPARC_H44
:
3146 if (!fixP
->fx_addsy
)
3150 insn
|= tval
& 0x3fffff;
3154 case BFD_RELOC_SPARC_M44
:
3155 if (!fixP
->fx_addsy
)
3156 insn
|= (val
>> 12) & 0x3ff;
3159 case BFD_RELOC_SPARC_L44
:
3160 if (!fixP
->fx_addsy
)
3161 insn
|= val
& 0xfff;
3164 case BFD_RELOC_SPARC_HIX22
:
3165 if (!fixP
->fx_addsy
)
3167 val
^= ~ (offsetT
) 0;
3168 insn
|= (val
>> 10) & 0x3fffff;
3172 case BFD_RELOC_SPARC_LOX10
:
3173 if (!fixP
->fx_addsy
)
3174 insn
|= 0x1c00 | (val
& 0x3ff);
3177 case BFD_RELOC_NONE
:
3179 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3180 _("bad or unhandled relocation type: 0x%02x"),
3185 if (INSN_BIG_ENDIAN
)
3186 bfd_putb32 (insn
, (unsigned char *) buf
);
3188 bfd_putl32 (insn
, (unsigned char *) buf
);
3191 /* Are we finished with this relocation now? */
3192 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3198 /* Translate internal representation of relocation info to BFD target
3202 tc_gen_reloc (section
, fixp
)
3206 static arelent
*relocs
[3];
3208 bfd_reloc_code_real_type code
;
3210 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3213 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3214 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3215 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3217 switch (fixp
->fx_r_type
)
3221 case BFD_RELOC_HI22
:
3222 case BFD_RELOC_LO10
:
3223 case BFD_RELOC_32_PCREL_S2
:
3224 case BFD_RELOC_SPARC13
:
3225 case BFD_RELOC_SPARC22
:
3226 case BFD_RELOC_SPARC_BASE13
:
3227 case BFD_RELOC_SPARC_WDISP16
:
3228 case BFD_RELOC_SPARC_WDISP19
:
3229 case BFD_RELOC_SPARC_WDISP22
:
3231 case BFD_RELOC_SPARC_5
:
3232 case BFD_RELOC_SPARC_6
:
3233 case BFD_RELOC_SPARC_7
:
3234 case BFD_RELOC_SPARC_10
:
3235 case BFD_RELOC_SPARC_11
:
3236 case BFD_RELOC_SPARC_HH22
:
3237 case BFD_RELOC_SPARC_HM10
:
3238 case BFD_RELOC_SPARC_LM22
:
3239 case BFD_RELOC_SPARC_PC_HH22
:
3240 case BFD_RELOC_SPARC_PC_HM10
:
3241 case BFD_RELOC_SPARC_PC_LM22
:
3242 case BFD_RELOC_SPARC_H44
:
3243 case BFD_RELOC_SPARC_M44
:
3244 case BFD_RELOC_SPARC_L44
:
3245 case BFD_RELOC_SPARC_HIX22
:
3246 case BFD_RELOC_SPARC_LOX10
:
3247 case BFD_RELOC_SPARC_REV32
:
3248 case BFD_RELOC_SPARC_OLO10
:
3249 case BFD_RELOC_VTABLE_ENTRY
:
3250 case BFD_RELOC_VTABLE_INHERIT
:
3251 code
= fixp
->fx_r_type
;
3258 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3259 /* If we are generating PIC code, we need to generate a different
3263 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3265 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3268 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3274 case BFD_RELOC_32_PCREL_S2
:
3275 if (! S_IS_DEFINED (fixp
->fx_addsy
)
3276 || S_IS_COMMON (fixp
->fx_addsy
)
3277 || S_IS_EXTERNAL (fixp
->fx_addsy
)
3278 || S_IS_WEAK (fixp
->fx_addsy
))
3279 code
= BFD_RELOC_SPARC_WPLT30
;
3281 case BFD_RELOC_HI22
:
3282 if (fixp
->fx_addsy
!= NULL
3283 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3284 code
= BFD_RELOC_SPARC_PC22
;
3286 code
= BFD_RELOC_SPARC_GOT22
;
3288 case BFD_RELOC_LO10
:
3289 if (fixp
->fx_addsy
!= NULL
3290 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3291 code
= BFD_RELOC_SPARC_PC10
;
3293 code
= BFD_RELOC_SPARC_GOT10
;
3295 case BFD_RELOC_SPARC13
:
3296 code
= BFD_RELOC_SPARC_GOT13
;
3302 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3304 if (code
== BFD_RELOC_SPARC_OLO10
)
3305 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3307 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3308 if (reloc
->howto
== 0)
3310 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3311 _("internal error: can't export reloc type %d (`%s')"),
3312 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3318 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3321 if (reloc
->howto
->pc_relative
== 0
3322 || code
== BFD_RELOC_SPARC_PC10
3323 || code
== BFD_RELOC_SPARC_PC22
)
3324 reloc
->addend
= fixp
->fx_addnumber
;
3325 else if (sparc_pic_code
3326 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3327 && fixp
->fx_addsy
!= NULL
3328 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3329 || S_IS_WEAK (fixp
->fx_addsy
))
3330 && S_IS_DEFINED (fixp
->fx_addsy
)
3331 && ! S_IS_COMMON (fixp
->fx_addsy
))
3332 reloc
->addend
= fixp
->fx_addnumber
;
3334 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3336 #else /* elf or coff */
3338 if (reloc
->howto
->pc_relative
== 0
3339 || code
== BFD_RELOC_SPARC_PC10
3340 || code
== BFD_RELOC_SPARC_PC22
)
3341 reloc
->addend
= fixp
->fx_addnumber
;
3342 else if (symbol_section_p (fixp
->fx_addsy
))
3343 reloc
->addend
= (section
->vma
3344 + fixp
->fx_addnumber
3345 + md_pcrel_from (fixp
));
3347 reloc
->addend
= fixp
->fx_offset
;
3350 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3351 on the same location. */
3352 if (code
== BFD_RELOC_SPARC_OLO10
)
3354 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3357 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3358 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (section_symbol (absolute_section
));
3359 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3360 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3361 reloc
->addend
= fixp
->tc_fix_data
;
3367 /* We have no need to default values of symbols. */
3370 md_undefined_symbol (name
)
3376 /* Round up a section size to the appropriate boundary. */
3379 md_section_align (segment
, size
)
3384 /* This is not right for ELF; a.out wants it, and COFF will force
3385 the alignment anyways. */
3386 valueT align
= ((valueT
) 1
3387 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3390 /* Turn alignment value into a mask. */
3392 newsize
= (size
+ align
) & ~align
;
3399 /* Exactly what point is a PC-relative offset relative TO?
3400 On the sparc, they're relative to the address of the offset, plus
3401 its size. This gets us to the following instruction.
3402 (??? Is this right? FIXME-SOON) */
3404 md_pcrel_from (fixP
)
3409 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3410 if (! sparc_pic_code
3411 || fixP
->fx_addsy
== NULL
3412 || symbol_section_p (fixP
->fx_addsy
))
3413 ret
+= fixP
->fx_size
;
3417 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3429 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3432 return (value
== 1) ? shift
: -1;
3435 /* Sort of like s_lcomm. */
3438 static int max_alignment
= 15;
3453 name
= input_line_pointer
;
3454 c
= get_symbol_end ();
3455 p
= input_line_pointer
;
3459 if (*input_line_pointer
!= ',')
3461 as_bad (_("Expected comma after name"));
3462 ignore_rest_of_line ();
3466 ++input_line_pointer
;
3468 if ((size
= get_absolute_expression ()) < 0)
3470 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3471 ignore_rest_of_line ();
3476 symbolP
= symbol_find_or_make (name
);
3479 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3480 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3482 as_bad (_("bad .reserve segment -- expected BSS segment"));
3486 if (input_line_pointer
[2] == '.')
3487 input_line_pointer
+= 7;
3489 input_line_pointer
+= 6;
3492 if (*input_line_pointer
== ',')
3494 ++input_line_pointer
;
3497 if (*input_line_pointer
== '\n')
3499 as_bad (_("missing alignment"));
3500 ignore_rest_of_line ();
3504 align
= (int) get_absolute_expression ();
3507 if (align
> max_alignment
)
3509 align
= max_alignment
;
3510 as_warn (_("alignment too large; assuming %d"), align
);
3516 as_bad (_("negative alignment"));
3517 ignore_rest_of_line ();
3523 temp
= log2 (align
);
3526 as_bad (_("alignment not a power of 2"));
3527 ignore_rest_of_line ();
3534 record_alignment (bss_section
, align
);
3539 if (!S_IS_DEFINED (symbolP
)
3541 && S_GET_OTHER (symbolP
) == 0
3542 && S_GET_DESC (symbolP
) == 0
3549 segT current_seg
= now_seg
;
3550 subsegT current_subseg
= now_subseg
;
3552 /* Switch to bss. */
3553 subseg_set (bss_section
, 1);
3557 frag_align (align
, 0, 0);
3559 /* Detach from old frag. */
3560 if (S_GET_SEGMENT(symbolP
) == bss_section
)
3561 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3563 symbol_set_frag (symbolP
, frag_now
);
3564 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3565 (offsetT
) size
, (char *) 0);
3568 S_SET_SEGMENT (symbolP
, bss_section
);
3570 subseg_set (current_seg
, current_subseg
);
3573 S_SET_SIZE (symbolP
, size
);
3579 as_warn("Ignoring attempt to re-define symbol %s",
3580 S_GET_NAME (symbolP
));
3581 } /* if not redefining. */
3583 demand_empty_rest_of_line ();
3596 name
= input_line_pointer
;
3597 c
= get_symbol_end ();
3598 /* Just after name is now '\0'. */
3599 p
= input_line_pointer
;
3602 if (*input_line_pointer
!= ',')
3604 as_bad (_("Expected comma after symbol-name"));
3605 ignore_rest_of_line ();
3610 input_line_pointer
++;
3612 if ((temp
= get_absolute_expression ()) < 0)
3614 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp
);
3615 ignore_rest_of_line ();
3620 symbolP
= symbol_find_or_make (name
);
3622 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3624 as_bad (_("Ignoring attempt to re-define symbol"));
3625 ignore_rest_of_line ();
3628 if (S_GET_VALUE (symbolP
) != 0)
3630 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3632 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3633 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3639 S_SET_VALUE (symbolP
, (valueT
) size
);
3640 S_SET_EXTERNAL (symbolP
);
3643 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3644 if (*input_line_pointer
!= ',')
3646 as_bad (_("Expected comma after common length"));
3647 ignore_rest_of_line ();
3650 input_line_pointer
++;
3652 if (*input_line_pointer
!= '"')
3654 temp
= get_absolute_expression ();
3657 if (temp
> max_alignment
)
3659 temp
= max_alignment
;
3660 as_warn (_("alignment too large; assuming %d"), temp
);
3666 as_bad (_("negative alignment"));
3667 ignore_rest_of_line ();
3672 if (symbol_get_obj (symbolP
)->local
)
3680 old_subsec
= now_subseg
;
3685 align
= log2 (temp
);
3689 as_bad (_("alignment not a power of 2"));
3690 ignore_rest_of_line ();
3694 record_alignment (bss_section
, align
);
3695 subseg_set (bss_section
, 0);
3697 frag_align (align
, 0, 0);
3698 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3699 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3700 symbol_set_frag (symbolP
, frag_now
);
3701 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3702 (offsetT
) size
, (char *) 0);
3704 S_SET_SEGMENT (symbolP
, bss_section
);
3705 S_CLEAR_EXTERNAL (symbolP
);
3706 S_SET_SIZE (symbolP
, size
);
3707 subseg_set (old_sec
, old_subsec
);
3710 #endif /* OBJ_ELF */
3713 S_SET_VALUE (symbolP
, (valueT
) size
);
3715 S_SET_ALIGN (symbolP
, temp
);
3716 S_SET_SIZE (symbolP
, size
);
3718 S_SET_EXTERNAL (symbolP
);
3719 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3724 input_line_pointer
++;
3725 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3726 if (*input_line_pointer
== '.')
3727 input_line_pointer
++;
3728 /* @@ Some say data, some say bss. */
3729 if (strncmp (input_line_pointer
, "bss\"", 4)
3730 && strncmp (input_line_pointer
, "data\"", 5))
3732 while (*--input_line_pointer
!= '"')
3734 input_line_pointer
--;
3735 goto bad_common_segment
;
3737 while (*input_line_pointer
++ != '"')
3739 goto allocate_common
;
3742 #ifdef BFD_ASSEMBLER
3743 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3746 demand_empty_rest_of_line ();
3751 p
= input_line_pointer
;
3752 while (*p
&& *p
!= '\n')
3756 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3758 input_line_pointer
= p
;
3759 ignore_rest_of_line ();
3764 /* Handle the .empty pseudo-op. This supresses the warnings about
3765 invalid delay slot usage. */
3771 /* The easy way to implement is to just forget about the last
3781 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3783 input_line_pointer
+= 6;
3787 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3789 input_line_pointer
+= 6;
3793 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3795 input_line_pointer
+= 7;
3799 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3801 input_line_pointer
+= 5;
3802 /* We only support 2 segments -- text and data -- for now, so
3803 things in the "bss segment" will have to go into data for now.
3804 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3805 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
3808 as_bad (_("Unknown segment type"));
3809 demand_empty_rest_of_line ();
3815 subseg_set (data_section
, 1);
3816 demand_empty_rest_of_line ();
3823 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3825 ++input_line_pointer
;
3827 ++input_line_pointer
;
3830 /* This static variable is set by s_uacons to tell sparc_cons_align
3831 that the expession does not need to be aligned. */
3833 static int sparc_no_align_cons
= 0;
3835 /* This handles the unaligned space allocation pseudo-ops, such as
3836 .uaword. .uaword is just like .word, but the value does not need
3843 /* Tell sparc_cons_align not to align this value. */
3844 sparc_no_align_cons
= 1;
3848 /* This handles the native word allocation pseudo-op .nword.
3849 For sparc_arch_size 32 it is equivalent to .word, for
3850 sparc_arch_size 64 it is equivalent to .xword. */
3856 cons (sparc_arch_size
== 32 ? 4 : 8);
3860 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3864 .register %g[2367],{#scratch|symbolname|#ignore}
3874 const char *regname
;
3876 if (input_line_pointer
[0] != '%'
3877 || input_line_pointer
[1] != 'g'
3878 || ((input_line_pointer
[2] & ~1) != '2'
3879 && (input_line_pointer
[2] & ~1) != '6')
3880 || input_line_pointer
[3] != ',')
3881 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3882 reg
= input_line_pointer
[2] - '0';
3883 input_line_pointer
+= 4;
3885 if (*input_line_pointer
== '#')
3887 ++input_line_pointer
;
3888 regname
= input_line_pointer
;
3889 c
= get_symbol_end ();
3890 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
3891 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3892 if (regname
[0] == 'i')
3899 regname
= input_line_pointer
;
3900 c
= get_symbol_end ();
3902 if (sparc_arch_size
== 64)
3906 if ((regname
&& globals
[reg
] != (symbolS
*) 1
3907 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
3908 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
3909 as_bad (_("redefinition of global register"));
3913 if (regname
== NULL
)
3914 globals
[reg
] = (symbolS
*) 1;
3919 if (symbol_find (regname
))
3920 as_bad (_("Register symbol %s already defined."),
3923 globals
[reg
] = symbol_make (regname
);
3924 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
3926 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
3927 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
3928 flags
|= BSF_GLOBAL
;
3929 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
3930 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
3931 S_SET_ALIGN (globals
[reg
], reg
);
3932 S_SET_SIZE (globals
[reg
], 0);
3933 /* Although we actually want undefined_section here,
3934 we have to use absolute_section, because otherwise
3935 generic as code will make it a COM section.
3936 We fix this up in sparc_adjust_symtab. */
3937 S_SET_SEGMENT (globals
[reg
], absolute_section
);
3938 S_SET_OTHER (globals
[reg
], 0);
3939 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
3940 ->internal_elf_sym
.st_info
=
3941 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
3942 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
3943 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
3948 *input_line_pointer
= c
;
3950 demand_empty_rest_of_line ();
3953 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
3954 symbols which need it. */
3957 sparc_adjust_symtab ()
3961 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
3963 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
3964 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
3967 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
3968 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
3971 S_SET_SEGMENT (sym
, undefined_section
);
3976 /* If the --enforce-aligned-data option is used, we require .word,
3977 et. al., to be aligned correctly. We do it by setting up an
3978 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3979 no unexpected alignment was introduced.
3981 The SunOS and Solaris native assemblers enforce aligned data by
3982 default. We don't want to do that, because gcc can deliberately
3983 generate misaligned data if the packed attribute is used. Instead,
3984 we permit misaligned data by default, and permit the user to set an
3985 option to check for it. */
3988 sparc_cons_align (nbytes
)
3994 /* Only do this if we are enforcing aligned data. */
3995 if (! enforce_aligned_data
)
3998 if (sparc_no_align_cons
)
4000 /* This is an unaligned pseudo-op. */
4001 sparc_no_align_cons
= 0;
4005 nalign
= log2 (nbytes
);
4009 assert (nalign
> 0);
4011 if (now_seg
== absolute_section
)
4013 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4014 as_bad (_("misaligned data"));
4018 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
4019 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4021 record_alignment (now_seg
, nalign
);
4024 /* This is where we do the unexpected alignment check.
4025 This is called from HANDLE_ALIGN in tc-sparc.h. */
4028 sparc_handle_align (fragp
)
4031 if (fragp
->fr_type
== rs_align_code
&& !fragp
->fr_subtype
4032 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
4033 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4034 if (fragp
->fr_type
== rs_align_code
&& fragp
->fr_subtype
== 1024)
4036 int count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4041 && !((long) (fragp
->fr_literal
+ fragp
->fr_fix
) & 3))
4043 unsigned *p
= (unsigned *) (fragp
->fr_literal
+ fragp
->fr_fix
);
4046 for (i
= 0; i
< count
; i
+= 4, p
++)
4047 if (INSN_BIG_ENDIAN
)
4049 number_to_chars_bigendian ((char *) p
, 0x01000000, 4);
4051 number_to_chars_littleendian ((char *) p
, 0x10000000, 4);
4053 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4055 char *waddr
= &fragp
->fr_literal
[fragp
->fr_fix
];
4056 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4057 if (INSN_BIG_ENDIAN
)
4058 number_to_chars_bigendian (waddr
, wval
, 4);
4060 number_to_chars_littleendian (waddr
, wval
, 4);
4062 fragp
->fr_var
= count
;
4068 /* Some special processing for a Sparc ELF file. */
4071 sparc_elf_final_processing ()
4073 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4074 sort of BFD interface for this. */
4075 if (sparc_arch_size
== 64)
4077 switch (sparc_memory_model
)
4080 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4083 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4089 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4090 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4091 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4092 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4096 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4097 reloc for a cons. We could use the definition there, except that
4098 we want to handle little endian relocs specially. */
4101 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
4104 unsigned int nbytes
;
4107 bfd_reloc_code_real_type r
;
4109 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4110 (nbytes
== 2 ? BFD_RELOC_16
:
4111 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4113 if (target_little_endian_data
&& nbytes
== 4
4114 && now_seg
->flags
& SEC_ALLOC
)
4115 r
= BFD_RELOC_SPARC_REV32
;
4116 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4121 elf32_sparc_force_relocation (fixp
)
4124 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4125 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)