1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static int hwcap_seen
;
84 static int hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if as should generate error if an undeclared g[23] register
94 has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if we should try to relax jumps and calls. */
98 static int sparc_relax
;
100 /* Non-zero if we are generating PIC code. */
103 /* Non-zero if we should give an error when misaligned data is seen. */
104 static int enforce_aligned_data
;
106 extern int target_big_endian
;
108 static int target_little_endian_data
;
110 /* Symbols for global registers on v9. */
111 static symbolS
*globals
[8];
113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
114 int sparc_cie_data_alignment
;
116 /* V9 and 86x have big and little endian data, but instructions are always big
117 endian. The sparclet has bi-endian support but both data and insns have
118 the same endianness. Global `target_big_endian' is used for data.
119 The following macro is used for instructions. */
120 #ifndef INSN_BIG_ENDIAN
121 #define INSN_BIG_ENDIAN (target_big_endian \
122 || default_arch_type == sparc86x \
123 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
126 /* Handle of the OPCODE hash table. */
127 static struct hash_control
*op_hash
;
129 static void s_data1 (void);
130 static void s_seg (int);
131 static void s_proc (int);
132 static void s_reserve (int);
133 static void s_common (int);
134 static void s_empty (int);
135 static void s_uacons (int);
136 static void s_ncons (int);
138 static void s_register (int);
141 const pseudo_typeS md_pseudo_table
[] =
143 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
144 {"common", s_common
, 0},
145 {"empty", s_empty
, 0},
146 {"global", s_globl
, 0},
148 {"nword", s_ncons
, 0},
149 {"optim", s_ignore
, 0},
151 {"reserve", s_reserve
, 0},
153 {"skip", s_space
, 0},
156 {"uahalf", s_uacons
, 2},
157 {"uaword", s_uacons
, 4},
158 {"uaxword", s_uacons
, 8},
160 /* These are specific to sparc/svr4. */
161 {"2byte", s_uacons
, 2},
162 {"4byte", s_uacons
, 4},
163 {"8byte", s_uacons
, 8},
164 {"register", s_register
, 0},
169 /* This array holds the chars that always start a comment. If the
170 pre-processor is disabled, these aren't very useful. */
171 const char comment_chars
[] = "!"; /* JF removed '|' from
174 /* This array holds the chars that only start a comment at the beginning of
175 a line. If the line seems to have the form '# 123 filename'
176 .line and .file directives will appear in the pre-processed output. */
177 /* Note that input_file.c hand checks for '#' at the beginning of the
178 first line of the input file. This is because the compiler outputs
179 #NO_APP at the beginning of its output. */
180 /* Also note that comments started like this one will always
181 work if '/' isn't otherwise defined. */
182 const char line_comment_chars
[] = "#";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant.
193 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
196 changed in read.c. Ideally it shouldn't have to know about it at all,
197 but nothing is ideal around here. */
199 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
204 unsigned long opcode
;
205 struct nlist
*nlistp
;
209 bfd_reloc_code_real_type reloc
;
212 struct sparc_it the_insn
, set_insn
;
214 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
216 /* Table of arguments to -A.
217 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
218 for this use. That table is for opcodes only. This table is for opcodes
221 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
222 v8plusa
, v9
, v9a
, v9b
, v9_64
};
224 static struct sparc_arch
{
227 enum sparc_arch_types arch_type
;
228 /* Default word size, as specified during configuration.
229 A value of zero means can't be used to specify default architecture. */
230 int default_arch_size
;
231 /* Allowable arg to -A? */
234 } sparc_arch_table
[] = {
235 { "v6", "v6", v6
, 0, 1, 0 },
236 { "v7", "v7", v7
, 0, 1, 0 },
237 { "v8", "v8", v8
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
238 { "v8a", "v8", v8
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
239 { "sparc", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
},
240 { "sparcvis", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
},
241 { "sparcvis2", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
},
242 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
},
243 { "sparcima", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_IMA
},
244 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
245 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
},
246 { "sparc4", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
247 { "leon", "leon", leon
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
248 { "sparclet", "sparclet", sparclet
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
249 { "sparclite", "sparclite", sparclite
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
250 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
251 { "v8plus", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
},
252 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
},
253 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
},
254 { "v8plusc", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
},
255 { "v8plusd", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
256 { "v8pluse", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
257 { "v8plusv", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_IMA
|HWCAP_ASI_CACHE_SPARING
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
258 { "v9", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
},
259 { "v9a", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
},
260 { "v9b", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
},
261 { "v9c", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
},
262 { "v9d", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
263 { "v9e", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
264 { "v9v", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_IMA
|HWCAP_ASI_CACHE_SPARING
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
265 /* This exists to allow configure.in/Makefile.in to pass one
266 value to specify both the default machine and default word size. */
267 { "v9-64", "v9", v9
, 64, 0, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
},
268 { NULL
, NULL
, v8
, 0, 0, 0 }
271 /* Variant of default_arch */
272 static enum sparc_arch_types default_arch_type
;
274 static struct sparc_arch
*
275 lookup_arch (char *name
)
277 struct sparc_arch
*sa
;
279 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
280 if (strcmp (sa
->name
, name
) == 0)
282 if (sa
->name
== NULL
)
287 /* Initialize the default opcode arch and word size from the default
288 architecture name. */
291 init_default_arch (void)
293 struct sparc_arch
*sa
= lookup_arch (default_arch
);
296 || sa
->default_arch_size
== 0)
297 as_fatal (_("Invalid default architecture, broken assembler."));
299 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
300 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
301 as_fatal (_("Bad opcode table, broken assembler."));
302 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
304 default_arch_type
= sa
->arch_type
;
307 /* Called by TARGET_FORMAT. */
310 sparc_target_format (void)
312 /* We don't get a chance to initialize anything before we're called,
313 so handle that now. */
314 if (! default_init_p
)
315 init_default_arch ();
319 return "a.out-sparc-netbsd";
322 if (target_big_endian
)
323 return "a.out-sunos-big";
324 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
325 return "a.out-sunos-big";
327 return "a.out-sparc-little";
329 return "a.out-sunos-big";
340 return "coff-sparc-lynx";
347 return "elf32-sparc-vxworks";
351 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
358 * Invocation line includes a switch not recognized by the base assembler.
359 * See if it's a processor-specific option. These are:
362 * Warn on architecture bumps. See also -A.
364 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
365 * Standard 32 bit architectures.
367 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
368 * This used to only mean 64 bits, but properly specifying it
369 * complicated gcc's ASM_SPECs, so now opcode selection is
370 * specified orthogonally to word size (except when specifying
371 * the default, but that is an internal implementation detail).
372 * -Av8plus, -Av8plusa, -Av8plusb
373 * Same as -Av9{,a,b}.
374 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
375 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
377 * -xarch=v9, -xarch=v9a, -xarch=v9b
378 * Same as -Av9{,a,b} -64, for compatibility with Sun's
381 * Select the architecture and possibly the file format.
382 * Instructions or features not supported by the selected
383 * architecture cause fatal errors.
385 * The default is to start at v6, and bump the architecture up
386 * whenever an instruction is seen at a higher level. In 32 bit
387 * environments, v9 is not bumped up to, the user must pass
390 * If -bump is specified, a warning is printing when bumping to
393 * If an architecture is specified, all instructions must match
394 * that architecture. Any higher level instructions are flagged
395 * as errors. Note that in the 32 bit environment specifying
396 * -Av8plus does not automatically create a v8plus object file, a
397 * v9 insn must be seen.
399 * If both an architecture and -bump are specified, the
400 * architecture starts at the specified level, but bumps are
401 * warnings. Note that we can't set `current_architecture' to
402 * the requested level in this case: in the 32 bit environment,
403 * we still must avoid creating v8plus object files unless v9
407 * Bumping between incompatible architectures is always an
408 * error. For example, from sparclite to v9.
412 const char *md_shortopts
= "A:K:VQ:sq";
415 const char *md_shortopts
= "A:k";
417 const char *md_shortopts
= "A:";
420 struct option md_longopts
[] = {
421 #define OPTION_BUMP (OPTION_MD_BASE)
422 {"bump", no_argument
, NULL
, OPTION_BUMP
},
423 #define OPTION_SPARC (OPTION_MD_BASE + 1)
424 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
425 #define OPTION_XARCH (OPTION_MD_BASE + 2)
426 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
428 #define OPTION_32 (OPTION_MD_BASE + 3)
429 {"32", no_argument
, NULL
, OPTION_32
},
430 #define OPTION_64 (OPTION_MD_BASE + 4)
431 {"64", no_argument
, NULL
, OPTION_64
},
432 #define OPTION_TSO (OPTION_MD_BASE + 5)
433 {"TSO", no_argument
, NULL
, OPTION_TSO
},
434 #define OPTION_PSO (OPTION_MD_BASE + 6)
435 {"PSO", no_argument
, NULL
, OPTION_PSO
},
436 #define OPTION_RMO (OPTION_MD_BASE + 7)
437 {"RMO", no_argument
, NULL
, OPTION_RMO
},
439 #ifdef SPARC_BIENDIAN
440 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
441 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
442 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
443 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
445 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
446 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
447 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
448 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
450 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
451 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
452 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
453 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
455 #define OPTION_RELAX (OPTION_MD_BASE + 14)
456 {"relax", no_argument
, NULL
, OPTION_RELAX
},
457 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
458 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
459 {NULL
, no_argument
, NULL
, 0}
462 size_t md_longopts_size
= sizeof (md_longopts
);
465 md_parse_option (int c
, char *arg
)
467 /* We don't get a chance to initialize anything before we're called,
468 so handle that now. */
469 if (! default_init_p
)
470 init_default_arch ();
476 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
481 if (!strncmp (arg
, "v9", 2))
482 md_parse_option (OPTION_64
, NULL
);
485 if (!strncmp (arg
, "v8", 2)
486 || !strncmp (arg
, "v7", 2)
487 || !strncmp (arg
, "v6", 2)
488 || !strcmp (arg
, "sparclet")
489 || !strcmp (arg
, "sparclite")
490 || !strcmp (arg
, "sparc86x"))
491 md_parse_option (OPTION_32
, NULL
);
498 struct sparc_arch
*sa
;
499 enum sparc_opcode_arch_val opcode_arch
;
501 sa
= lookup_arch (arg
);
503 || ! sa
->user_option_p
)
505 if (c
== OPTION_XARCH
)
506 as_bad (_("invalid architecture -xarch=%s"), arg
);
508 as_bad (_("invalid architecture -A%s"), arg
);
512 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
513 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
514 as_fatal (_("Bad opcode table, broken assembler."));
516 if (!architecture_requested
517 || opcode_arch
> max_architecture
)
518 max_architecture
= opcode_arch
;
519 hwcap_allowed
|= sa
->hwcap_allowed
;
520 architecture_requested
= 1;
525 /* Ignore -sparc, used by SunOS make default .s.o rule. */
528 case OPTION_ENFORCE_ALIGNED_DATA
:
529 enforce_aligned_data
= 1;
532 #ifdef SPARC_BIENDIAN
533 case OPTION_LITTLE_ENDIAN
:
534 target_big_endian
= 0;
535 if (default_arch_type
!= sparclet
)
536 as_fatal ("This target does not support -EL");
538 case OPTION_LITTLE_ENDIAN_DATA
:
539 target_little_endian_data
= 1;
540 target_big_endian
= 0;
541 if (default_arch_type
!= sparc86x
542 && default_arch_type
!= v9
)
543 as_fatal ("This target does not support --little-endian-data");
545 case OPTION_BIG_ENDIAN
:
546 target_big_endian
= 1;
560 const char **list
, **l
;
562 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
563 list
= bfd_target_list ();
564 for (l
= list
; *l
!= NULL
; l
++)
566 if (sparc_arch_size
== 32)
568 if (CONST_STRNEQ (*l
, "elf32-sparc"))
573 if (CONST_STRNEQ (*l
, "elf64-sparc"))
578 as_fatal (_("No compiled in support for %d bit object file format"),
582 if (sparc_arch_size
== 64
583 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
584 max_architecture
= SPARC_OPCODE_ARCH_V9
;
589 sparc_memory_model
= MM_TSO
;
593 sparc_memory_model
= MM_PSO
;
597 sparc_memory_model
= MM_RMO
;
605 /* Qy - do emit .comment
606 Qn - do not emit .comment. */
610 /* Use .stab instead of .stab.excl. */
614 /* quick -- Native assembler does fewer checks. */
618 if (strcmp (arg
, "PIC") != 0)
619 as_warn (_("Unrecognized option following -K"));
624 case OPTION_NO_UNDECLARED_REGS
:
625 no_undeclared_regs
= 1;
628 case OPTION_UNDECLARED_REGS
:
629 no_undeclared_regs
= 0;
637 case OPTION_NO_RELAX
:
649 md_show_usage (FILE *stream
)
651 const struct sparc_arch
*arch
;
654 /* We don't get a chance to initialize anything before we're called,
655 so handle that now. */
656 if (! default_init_p
)
657 init_default_arch ();
659 fprintf (stream
, _("SPARC options:\n"));
661 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
663 if (!arch
->user_option_p
)
665 if (arch
!= &sparc_arch_table
[0])
666 fprintf (stream
, " | ");
667 if (column
+ strlen (arch
->name
) > 70)
670 fputc ('\n', stream
);
672 column
+= 5 + 2 + strlen (arch
->name
);
673 fprintf (stream
, "-A%s", arch
->name
);
675 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
677 if (!arch
->user_option_p
)
679 fprintf (stream
, " | ");
680 if (column
+ strlen (arch
->name
) > 65)
683 fputc ('\n', stream
);
685 column
+= 5 + 7 + strlen (arch
->name
);
686 fprintf (stream
, "-xarch=%s", arch
->name
);
688 fprintf (stream
, _("\n\
689 specify variant of SPARC architecture\n\
690 -bump warn when assembler switches architectures\n\
692 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
693 -relax relax jumps and branches (default)\n\
694 -no-relax avoid changing any jumps and branches\n"));
696 fprintf (stream
, _("\
697 -k generate PIC\n"));
700 fprintf (stream
, _("\
701 -32 create 32 bit object file\n\
702 -64 create 64 bit object file\n"));
703 fprintf (stream
, _("\
704 [default is %d]\n"), default_arch_size
);
705 fprintf (stream
, _("\
706 -TSO use Total Store Ordering\n\
707 -PSO use Partial Store Ordering\n\
708 -RMO use Relaxed Memory Ordering\n"));
709 fprintf (stream
, _("\
710 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
711 fprintf (stream
, _("\
712 -KPIC generate PIC\n\
713 -V print assembler version number\n\
714 -undeclared-regs ignore application global register usage without\n\
715 appropriate .register directive (default)\n\
716 -no-undeclared-regs force error on application global register usage\n\
717 without appropriate .register directive\n\
722 #ifdef SPARC_BIENDIAN
723 fprintf (stream
, _("\
724 -EL generate code for a little endian machine\n\
725 -EB generate code for a big endian machine\n\
726 --little-endian-data generate code for a machine having big endian\n\
727 instructions and little endian data.\n"));
731 /* Native operand size opcode translation. */
737 } native_op_table
[] =
739 {"ldn", "ld", "ldx"},
740 {"ldna", "lda", "ldxa"},
741 {"stn", "st", "stx"},
742 {"stna", "sta", "stxa"},
743 {"slln", "sll", "sllx"},
744 {"srln", "srl", "srlx"},
745 {"sran", "sra", "srax"},
746 {"casn", "cas", "casx"},
747 {"casna", "casa", "casxa"},
748 {"clrn", "clr", "clrx"},
752 /* sparc64 privileged and hyperprivileged registers. */
754 struct priv_reg_entry
760 struct priv_reg_entry priv_reg_table
[] =
780 {"", -1}, /* End marker. */
783 struct priv_reg_entry hpriv_reg_table
[] =
790 {"hstick_offset", 28},
791 {"hstick_enable", 29},
793 {"", -1}, /* End marker. */
796 /* v9a specific asrs. This table is ordered by initial
797 letter, in reverse. */
799 struct priv_reg_entry v9a_asr_table
[] =
802 {"sys_tick_cmpr", 25},
806 {"softint_clear", 21},
817 {"clear_softint", 21},
818 {"", -1}, /* End marker. */
822 cmp_reg_entry (const void *parg
, const void *qarg
)
824 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
825 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
827 return strcmp (q
->name
, p
->name
);
830 /* This function is called once, at assembler startup time. It should
831 set up all the tables, etc. that the MD part of the assembler will
837 register const char *retval
= NULL
;
839 register unsigned int i
= 0;
841 /* We don't get a chance to initialize anything before md_parse_option
842 is called, and it may not be called, so handle default initialization
843 now if not already done. */
844 if (! default_init_p
)
845 init_default_arch ();
847 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
848 op_hash
= hash_new ();
850 while (i
< (unsigned int) sparc_num_opcodes
)
852 const char *name
= sparc_opcodes
[i
].name
;
853 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
856 as_bad (_("Internal error: can't hash `%s': %s\n"),
857 sparc_opcodes
[i
].name
, retval
);
862 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
864 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
865 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
870 while (i
< (unsigned int) sparc_num_opcodes
871 && !strcmp (sparc_opcodes
[i
].name
, name
));
874 for (i
= 0; native_op_table
[i
].name
; i
++)
876 const struct sparc_opcode
*insn
;
877 char *name
= ((sparc_arch_size
== 32)
878 ? native_op_table
[i
].name32
879 : native_op_table
[i
].name64
);
880 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
883 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
884 name
, native_op_table
[i
].name
);
889 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
893 as_bad (_("Internal error: can't hash `%s': %s\n"),
894 sparc_opcodes
[i
].name
, retval
);
901 as_fatal (_("Broken assembler. No assembly attempted."));
903 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
904 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
906 /* If -bump, record the architecture level at which we start issuing
907 warnings. The behaviour is different depending upon whether an
908 architecture was explicitly specified. If it wasn't, we issue warnings
909 for all upwards bumps. If it was, we don't start issuing warnings until
910 we need to bump beyond the requested architecture or when we bump between
911 conflicting architectures. */
914 && architecture_requested
)
916 /* `max_architecture' records the requested architecture.
917 Issue warnings if we go above it. */
918 warn_after_architecture
= max_architecture
;
920 /* Find the highest architecture level that doesn't conflict with
921 the requested one. */
922 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
923 max_architecture
> warn_after_architecture
;
925 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
926 warn_after_architecture
))
931 /* Called after all assembly has been done. */
936 unsigned long mach
= bfd_mach_sparc
;
938 if (sparc_arch_size
== 64)
939 switch (current_architecture
)
941 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
942 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
943 default: mach
= bfd_mach_sparc_v9
; break;
946 switch (current_architecture
)
948 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
949 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
950 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
951 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
952 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
953 be but for now it is (since that's the way it's always been
957 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
959 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
961 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcap_seen
);
965 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
968 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
972 /* Sign-extend the value from the architecture word size, so that
973 0xffffffff is always considered -1 on sparc32. */
974 if (sparc_arch_size
== 32)
976 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
977 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
986 /* Return non-zero if VAL is in the range 0 to MAX. */
989 in_unsigned_range (bfd_vma val
, bfd_vma max
)
996 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
997 (e.g. -15 to +31). */
1000 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1006 if (val
< ~(max
>> 1))
1012 sparc_ffs (unsigned int mask
)
1019 for (i
= 0; (mask
& 1) == 0; ++i
)
1024 /* Implement big shift right. */
1026 BSR (bfd_vma val
, int amount
)
1028 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1029 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1030 return val
>> amount
;
1033 /* For communication between sparc_ip and get_expression. */
1034 static char *expr_end
;
1036 /* Values for `special_case'.
1037 Instructions that require wierd handling because they're longer than
1039 #define SPECIAL_CASE_NONE 0
1040 #define SPECIAL_CASE_SET 1
1041 #define SPECIAL_CASE_SETSW 2
1042 #define SPECIAL_CASE_SETX 3
1043 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1044 #define SPECIAL_CASE_FDIV 4
1046 /* Bit masks of various insns. */
1047 #define NOP_INSN 0x01000000
1048 #define OR_INSN 0x80100000
1049 #define XOR_INSN 0x80180000
1050 #define FMOVS_INSN 0x81A00020
1051 #define SETHI_INSN 0x01000000
1052 #define SLLX_INSN 0x81281000
1053 #define SRA_INSN 0x81380000
1055 /* The last instruction to be assembled. */
1056 static const struct sparc_opcode
*last_insn
;
1057 /* The assembled opcode of `last_insn'. */
1058 static unsigned long last_opcode
;
1060 /* Handle the set and setuw synthetic instructions. */
1063 synthetize_setuw (const struct sparc_opcode
*insn
)
1065 int need_hi22_p
= 0;
1066 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1068 if (the_insn
.exp
.X_op
== O_constant
)
1070 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1072 if (sizeof (offsetT
) > 4
1073 && (the_insn
.exp
.X_add_number
< 0
1074 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1075 as_warn (_("set: number not in 0..4294967295 range"));
1079 if (sizeof (offsetT
) > 4
1080 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1081 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1082 as_warn (_("set: number not in -2147483648..4294967295 range"));
1083 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1087 /* See if operand is absolute and small; skip sethi if so. */
1088 if (the_insn
.exp
.X_op
!= O_constant
1089 || the_insn
.exp
.X_add_number
>= (1 << 12)
1090 || the_insn
.exp
.X_add_number
< -(1 << 12))
1092 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1093 | ((the_insn
.exp
.X_add_number
>> 10)
1094 & (the_insn
.exp
.X_op
== O_constant
1096 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1097 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1098 output_insn (insn
, &the_insn
);
1102 /* See if operand has no low-order bits; skip OR if so. */
1103 if (the_insn
.exp
.X_op
!= O_constant
1104 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1107 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1109 | (the_insn
.exp
.X_add_number
1110 & (the_insn
.exp
.X_op
!= O_constant
1111 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1112 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1113 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1114 output_insn (insn
, &the_insn
);
1118 /* Handle the setsw synthetic instruction. */
1121 synthetize_setsw (const struct sparc_opcode
*insn
)
1125 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1127 if (the_insn
.exp
.X_op
!= O_constant
)
1129 synthetize_setuw (insn
);
1131 /* Need to sign extend it. */
1132 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1133 the_insn
.reloc
= BFD_RELOC_NONE
;
1134 output_insn (insn
, &the_insn
);
1138 if (sizeof (offsetT
) > 4
1139 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1140 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1141 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1143 low32
= the_insn
.exp
.X_add_number
;
1147 synthetize_setuw (insn
);
1153 the_insn
.reloc
= BFD_RELOC_NONE
;
1154 /* See if operand is absolute and small; skip sethi if so. */
1155 if (low32
< -(1 << 12))
1157 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1158 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1159 output_insn (insn
, &the_insn
);
1160 low32
= 0x1c00 | (low32
& 0x3ff);
1161 opc
= RS1 (rd
) | XOR_INSN
;
1164 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1165 | (low32
& 0x1fff));
1166 output_insn (insn
, &the_insn
);
1169 /* Handle the setsw synthetic instruction. */
1172 synthetize_setx (const struct sparc_opcode
*insn
)
1174 int upper32
, lower32
;
1175 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1176 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1178 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1179 int need_xor10_p
= 0;
1181 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1182 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1183 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1186 upper_dstreg
= tmpreg
;
1187 /* The tmp reg should not be the dst reg. */
1188 if (tmpreg
== dstreg
)
1189 as_warn (_("setx: temporary register same as destination register"));
1191 /* ??? Obviously there are other optimizations we can do
1192 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1193 doing some of these. Later. If you do change things, try to
1194 change all of this to be table driven as well. */
1195 /* What to output depends on the number if it's constant.
1196 Compute that first, then output what we've decided upon. */
1197 if (the_insn
.exp
.X_op
!= O_constant
)
1199 if (sparc_arch_size
== 32)
1201 /* When arch size is 32, we want setx to be equivalent
1202 to setuw for anything but constants. */
1203 the_insn
.exp
.X_add_number
&= 0xffffffff;
1204 synthetize_setuw (insn
);
1207 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1213 /* Reset X_add_number, we've extracted it as upper32/lower32.
1214 Otherwise fixup_segment will complain about not being able to
1215 write an 8 byte number in a 4 byte field. */
1216 the_insn
.exp
.X_add_number
= 0;
1218 /* Only need hh22 if `or' insn can't handle constant. */
1219 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1222 /* Does bottom part (after sethi) have bits? */
1223 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1224 /* No hh22, but does upper32 still have bits we can't set
1226 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1229 /* If the lower half is all zero, we build the upper half directly
1230 into the dst reg. */
1232 /* Need lower half if number is zero or 0xffffffff00000000. */
1233 || (! need_hh22_p
&& ! need_hm10_p
))
1235 /* No need for sethi if `or' insn can handle constant. */
1236 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1237 /* Note that we can't use a negative constant in the `or'
1238 insn unless the upper 32 bits are all ones. */
1239 || (lower32
< 0 && upper32
!= -1)
1240 || (lower32
>= 0 && upper32
== -1))
1243 if (need_hi22_p
&& upper32
== -1)
1246 /* Does bottom part (after sethi) have bits? */
1247 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1249 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1250 /* Need `or' if we didn't set anything else. */
1251 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1255 /* Output directly to dst reg if lower 32 bits are all zero. */
1256 upper_dstreg
= dstreg
;
1259 if (!upper_dstreg
&& dstreg
)
1260 as_warn (_("setx: illegal temporary register g0"));
1264 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1265 | ((upper32
>> 10) & 0x3fffff));
1266 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1267 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1268 output_insn (insn
, &the_insn
);
1273 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1274 | (((need_xor10_p
? ~lower32
: lower32
)
1275 >> 10) & 0x3fffff));
1276 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1277 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1278 output_insn (insn
, &the_insn
);
1283 the_insn
.opcode
= (OR_INSN
1284 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1287 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1288 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1289 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1290 output_insn (insn
, &the_insn
);
1295 /* FIXME: One nice optimization to do here is to OR the low part
1296 with the highpart if hi22 isn't needed and the low part is
1298 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1301 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1302 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1303 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1304 output_insn (insn
, &the_insn
);
1307 /* If we needed to build the upper part, shift it into place. */
1308 if (need_hh22_p
|| need_hm10_p
)
1310 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1312 the_insn
.reloc
= BFD_RELOC_NONE
;
1313 output_insn (insn
, &the_insn
);
1316 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1319 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1320 | 0x1c00 | (lower32
& 0x3ff));
1321 the_insn
.reloc
= BFD_RELOC_NONE
;
1322 output_insn (insn
, &the_insn
);
1325 /* If we needed to build both upper and lower parts, OR them together. */
1326 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1328 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1330 the_insn
.reloc
= BFD_RELOC_NONE
;
1331 output_insn (insn
, &the_insn
);
1335 /* Main entry point to assemble one instruction. */
1338 md_assemble (char *str
)
1340 const struct sparc_opcode
*insn
;
1344 special_case
= sparc_ip (str
, &insn
);
1348 /* We warn about attempts to put a floating point branch in a delay slot,
1349 unless the delay slot has been annulled. */
1350 if (last_insn
!= NULL
1351 && (insn
->flags
& F_FBR
) != 0
1352 && (last_insn
->flags
& F_DELAYED
) != 0
1353 /* ??? This test isn't completely accurate. We assume anything with
1354 F_{UNBR,CONDBR,FBR} set is annullable. */
1355 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1356 || (last_opcode
& ANNUL
) == 0))
1357 as_warn (_("FP branch in delay slot"));
1359 /* SPARC before v9 requires a nop instruction between a floating
1360 point instruction and a floating point branch. We insert one
1361 automatically, with a warning. */
1362 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1363 && last_insn
!= NULL
1364 && (insn
->flags
& F_FBR
) != 0
1365 && (last_insn
->flags
& F_FLOAT
) != 0)
1367 struct sparc_it nop_insn
;
1369 nop_insn
.opcode
= NOP_INSN
;
1370 nop_insn
.reloc
= BFD_RELOC_NONE
;
1371 output_insn (insn
, &nop_insn
);
1372 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1375 switch (special_case
)
1377 case SPECIAL_CASE_NONE
:
1379 output_insn (insn
, &the_insn
);
1382 case SPECIAL_CASE_SETSW
:
1383 synthetize_setsw (insn
);
1386 case SPECIAL_CASE_SET
:
1387 synthetize_setuw (insn
);
1390 case SPECIAL_CASE_SETX
:
1391 synthetize_setx (insn
);
1394 case SPECIAL_CASE_FDIV
:
1396 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1398 output_insn (insn
, &the_insn
);
1400 /* According to information leaked from Sun, the "fdiv" instructions
1401 on early SPARC machines would produce incorrect results sometimes.
1402 The workaround is to add an fmovs of the destination register to
1403 itself just after the instruction. This was true on machines
1404 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1405 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1406 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1407 output_insn (insn
, &the_insn
);
1412 as_fatal (_("failed special case insn sanity check"));
1417 get_hwcap_name (int mask
)
1419 if (mask
& HWCAP_MUL32
)
1421 if (mask
& HWCAP_DIV32
)
1423 if (mask
& HWCAP_FSMULD
)
1425 if (mask
& HWCAP_V8PLUS
)
1427 if (mask
& HWCAP_POPC
)
1429 if (mask
& HWCAP_VIS
)
1431 if (mask
& HWCAP_VIS2
)
1433 if (mask
& HWCAP_ASI_BLK_INIT
)
1434 return "ASIBlkInit";
1435 if (mask
& HWCAP_FMAF
)
1437 if (mask
& HWCAP_VIS3
)
1439 if (mask
& HWCAP_HPC
)
1441 if (mask
& HWCAP_RANDOM
)
1443 if (mask
& HWCAP_TRANS
)
1445 if (mask
& HWCAP_FJFMAU
)
1447 if (mask
& HWCAP_IMA
)
1449 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1451 if (mask
& HWCAP_AES
)
1453 if (mask
& HWCAP_DES
)
1455 if (mask
& HWCAP_KASUMI
)
1457 if (mask
& HWCAP_CAMELLIA
)
1459 if (mask
& HWCAP_MD5
)
1461 if (mask
& HWCAP_SHA1
)
1463 if (mask
& HWCAP_SHA256
)
1465 if (mask
& HWCAP_SHA512
)
1467 if (mask
& HWCAP_MPMUL
)
1469 if (mask
& HWCAP_MONT
)
1471 if (mask
& HWCAP_PAUSE
)
1473 if (mask
& HWCAP_CBCOND
)
1475 if (mask
& HWCAP_CRC32C
)
1480 /* Subroutine of md_assemble to do the actual parsing. */
1483 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1485 char *error_message
= "";
1489 const struct sparc_opcode
*insn
;
1491 unsigned long opcode
;
1492 unsigned int mask
= 0;
1496 int special_case
= SPECIAL_CASE_NONE
;
1503 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1520 as_bad (_("Unknown opcode: `%s'"), str
);
1522 return special_case
;
1524 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1528 as_bad (_("Unknown opcode: `%s'"), str
);
1529 return special_case
;
1539 opcode
= insn
->match
;
1540 memset (&the_insn
, '\0', sizeof (the_insn
));
1541 the_insn
.reloc
= BFD_RELOC_NONE
;
1544 /* Build the opcode, checking as we go to make sure that the
1546 for (args
= insn
->args
;; ++args
)
1554 /* Parse a series of masks. */
1561 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1564 error_message
= _(": invalid membar mask name");
1570 if (*s
== '|' || *s
== '+')
1578 if (! parse_const_expr_arg (&s
, &kmask
))
1580 error_message
= _(": invalid membar mask expression");
1583 if (kmask
< 0 || kmask
> 127)
1585 error_message
= _(": invalid membar mask number");
1590 opcode
|= MEMBAR (kmask
);
1598 if (! parse_const_expr_arg (&s
, &smask
))
1600 error_message
= _(": invalid siam mode expression");
1603 if (smask
< 0 || smask
> 7)
1605 error_message
= _(": invalid siam mode number");
1616 /* Parse a prefetch function. */
1619 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1621 error_message
= _(": invalid prefetch function name");
1627 if (! parse_const_expr_arg (&s
, &fcn
))
1629 error_message
= _(": invalid prefetch function expression");
1632 if (fcn
< 0 || fcn
> 31)
1634 error_message
= _(": invalid prefetch function number");
1644 /* Parse a sparc64 privileged register. */
1647 struct priv_reg_entry
*p
= priv_reg_table
;
1648 unsigned int len
= 9999999; /* Init to make gcc happy. */
1651 while (p
->name
[0] > s
[0])
1653 while (p
->name
[0] == s
[0])
1655 len
= strlen (p
->name
);
1656 if (strncmp (p
->name
, s
, len
) == 0)
1660 if (p
->name
[0] != s
[0])
1662 error_message
= _(": unrecognizable privileged register");
1666 opcode
|= (p
->regnum
<< 14);
1668 opcode
|= (p
->regnum
<< 25);
1674 error_message
= _(": unrecognizable privileged register");
1680 /* Parse a sparc64 hyperprivileged register. */
1683 struct priv_reg_entry
*p
= hpriv_reg_table
;
1684 unsigned int len
= 9999999; /* Init to make gcc happy. */
1687 while (p
->name
[0] > s
[0])
1689 while (p
->name
[0] == s
[0])
1691 len
= strlen (p
->name
);
1692 if (strncmp (p
->name
, s
, len
) == 0)
1696 if (p
->name
[0] != s
[0])
1698 error_message
= _(": unrecognizable hyperprivileged register");
1702 opcode
|= (p
->regnum
<< 14);
1704 opcode
|= (p
->regnum
<< 25);
1710 error_message
= _(": unrecognizable hyperprivileged register");
1716 /* Parse a v9a/v9b ancillary state register. */
1719 struct priv_reg_entry
*p
= v9a_asr_table
;
1720 unsigned int len
= 9999999; /* Init to make gcc happy. */
1723 while (p
->name
[0] > s
[0])
1725 while (p
->name
[0] == s
[0])
1727 len
= strlen (p
->name
);
1728 if (strncmp (p
->name
, s
, len
) == 0)
1732 if (p
->name
[0] != s
[0])
1734 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1737 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1739 error_message
= _(": rd on write only ancillary state register");
1743 && (insn
->architecture
1744 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1746 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1747 error_message
= _(": unrecognizable v9a ancillary state register");
1751 opcode
|= (p
->regnum
<< 14);
1753 opcode
|= (p
->regnum
<< 25);
1759 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1765 if (strncmp (s
, "%asr", 4) == 0)
1773 while (ISDIGIT (*s
))
1775 num
= num
* 10 + *s
- '0';
1779 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1781 if (num
< 16 || 31 < num
)
1783 error_message
= _(": asr number must be between 16 and 31");
1789 if (num
< 0 || 31 < num
)
1791 error_message
= _(": asr number must be between 0 and 31");
1796 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1801 error_message
= _(": expecting %asrN");
1808 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1812 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1818 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
1823 if (s
[0] == '0' && s
[1] == 'x')
1826 while (ISXDIGIT (*s
))
1829 num
|= hex_value (*s
);
1835 while (ISDIGIT (*s
))
1837 num
= num
* 10 + *s
- '0';
1841 if (num
< 0 || num
> 31)
1843 error_message
= _(": crypto immediate must be between 0 and 31");
1847 opcode
|= RS3 (num
);
1852 error_message
= _(": expecting crypto immediate");
1857 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1858 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1859 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1861 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1862 /* These fields are unsigned, but for upward compatibility,
1863 allow negative values as well. */
1867 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1868 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1869 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1871 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1872 /* These fields are unsigned, but for upward compatibility,
1873 allow negative values as well. */
1877 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1882 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
1887 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1892 if (*s
== 'p' && s
[1] == 'n')
1900 if (*s
== 'p' && s
[1] == 't')
1912 if (strncmp (s
, "%icc", 4) == 0)
1924 if (strncmp (s
, "%xcc", 4) == 0)
1936 if (strncmp (s
, "%fcc0", 5) == 0)
1948 if (strncmp (s
, "%fcc1", 5) == 0)
1960 if (strncmp (s
, "%fcc2", 5) == 0)
1972 if (strncmp (s
, "%fcc3", 5) == 0)
1980 if (strncmp (s
, "%pc", 3) == 0)
1988 if (strncmp (s
, "%tick", 5) == 0)
1995 case '\0': /* End of args. */
1996 if (s
[0] == ',' && s
[1] == '%')
1998 static const struct ops
2000 /* The name as it appears in assembler. */
2002 /* strlen (name), precomputed for speed */
2004 /* The reloc this pseudo-op translates to. */
2006 /* 1 if tls call. */
2011 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
2012 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
2013 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
2014 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
2015 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
2016 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
2017 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
2018 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
2019 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
2022 const struct ops
*o
;
2026 for (o
= ops
; o
->name
; o
++)
2027 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
2029 if (o
->name
== NULL
)
2032 if (s
[o
->len
+ 2] != '(')
2034 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2035 return special_case
;
2038 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
2040 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2042 return special_case
;
2046 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2047 || the_insn
.exp
.X_add_number
!= 0
2048 || the_insn
.exp
.X_add_symbol
2049 != symbol_find_or_make ("__tls_get_addr")))
2051 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2053 return special_case
;
2056 the_insn
.reloc
= o
->reloc
;
2057 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2060 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2063 else if (*s1
== ')')
2072 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2073 return special_case
;
2077 (void) get_expression (s
);
2097 case '[': /* These must match exactly. */
2105 case '#': /* Must be at least one digit. */
2108 while (ISDIGIT (*s
))
2116 case 'C': /* Coprocessor state register. */
2117 if (strncmp (s
, "%csr", 4) == 0)
2124 case 'b': /* Next operand is a coprocessor register. */
2127 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2132 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2146 opcode
|= mask
<< 14;
2154 opcode
|= mask
<< 25;
2160 case 'r': /* next operand must be a register */
2170 case 'f': /* frame pointer */
2178 case 'g': /* global register */
2187 case 'i': /* in register */
2191 mask
= c
- '0' + 24;
2196 case 'l': /* local register */
2200 mask
= (c
- '0' + 16);
2205 case 'o': /* out register */
2209 mask
= (c
- '0' + 8);
2214 case 's': /* stack pointer */
2222 case 'r': /* any register */
2223 if (!ISDIGIT ((c
= *s
++)))
2240 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2256 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2257 && no_undeclared_regs
&& ! globals
[mask
])
2258 as_bad (_("detected global register use not covered by .register pseudo-op"));
2260 /* Got the register, now figure out where
2261 it goes in the opcode. */
2265 opcode
|= mask
<< 14;
2273 opcode
|= mask
<< 25;
2277 opcode
|= (mask
<< 25) | (mask
<< 14);
2281 opcode
|= (mask
<< 25) | (mask
<< 0);
2287 case 'e': /* next operand is a floating point register */
2305 && ((format
= *s
) == 'f')
2308 for (mask
= 0; ISDIGIT (*s
); ++s
)
2310 mask
= 10 * mask
+ (*s
- '0');
2311 } /* read the number */
2320 } /* register must be even numbered */
2328 } /* register must be multiple of 4 */
2332 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2333 error_message
= _(": There are only 64 f registers; [0-63]");
2335 error_message
= _(": There are only 32 f registers; [0-31]");
2338 else if (mask
>= 32)
2340 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2342 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2345 = _(": There are only 32 single precision f registers; [0-31]");
2349 mask
-= 31; /* wrap high bit */
2353 error_message
= _(": There are only 32 f registers; [0-31]");
2361 } /* if not an 'f' register. */
2368 opcode
|= RS1 (mask
);
2374 opcode
|= RS2 (mask
);
2379 opcode
|= RS3 (mask
);
2385 opcode
|= RD (mask
);
2394 if (strncmp (s
, "%fsr", 4) == 0)
2402 if (strncmp (s
, "%efsr", 5) == 0)
2409 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2410 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2413 case 'l': /* 22 bit PC relative immediate */
2414 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2418 case 'L': /* 30 bit immediate */
2419 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2424 case 'n': /* 22 bit immediate */
2425 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2428 case 'i': /* 13 bit immediate */
2429 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2439 char *op_arg
= NULL
;
2440 static expressionS op_exp
;
2441 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2443 /* Check for %hi, etc. */
2446 static const struct ops
{
2447 /* The name as it appears in assembler. */
2449 /* strlen (name), precomputed for speed */
2451 /* The reloc this pseudo-op translates to. */
2453 /* Non-zero if for v9 only. */
2455 /* Non-zero if can be used in pc-relative contexts. */
2456 int pcrel_p
;/*FIXME:wip*/
2458 /* hix/lox must appear before hi/lo so %hix won't be
2459 mistaken for %hi. */
2460 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2461 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2462 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2463 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2464 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2465 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2466 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2467 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2468 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2469 { "h34", 3, BFD_RELOC_SPARC_H34
, 1, 0 },
2470 { "l34", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2471 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2472 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2473 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2474 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2475 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2476 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2477 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2478 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2479 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2480 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2482 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2484 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2485 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2486 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2487 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2488 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2490 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2492 { NULL
, 0, 0, 0, 0 }
2494 const struct ops
*o
;
2496 for (o
= ops
; o
->name
; o
++)
2497 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2499 if (o
->name
== NULL
)
2502 if (s
[o
->len
+ 1] != '(')
2504 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2505 return special_case
;
2509 the_insn
.reloc
= o
->reloc
;
2514 /* Note that if the get_expression() fails, we will still
2515 have created U entries in the symbol table for the
2516 'symbols' in the input string. Try not to create U
2517 symbols for registers, etc. */
2519 /* This stuff checks to see if the expression ends in
2520 +%reg. If it does, it removes the register from
2521 the expression, and re-sets 's' to point to the
2528 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2531 else if (*s1
== ')')
2540 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2541 return special_case
;
2545 (void) get_expression (s
);
2548 if (*s
== ',' || *s
== ']' || !*s
)
2550 if (*s
!= '+' && *s
!= '-')
2552 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2553 return special_case
;
2557 op_exp
= the_insn
.exp
;
2558 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2561 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2564 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2566 if (s1
[-2] == '%' && s1
[-3] == '+')
2568 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2570 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2577 if (op_arg
&& s1
== s
+ 1)
2578 the_insn
.exp
.X_op
= O_absent
;
2580 (void) get_expression (s
);
2592 (void) get_expression (s
);
2600 the_insn
.exp2
= the_insn
.exp
;
2601 the_insn
.exp
= op_exp
;
2602 if (the_insn
.exp2
.X_op
== O_absent
)
2603 the_insn
.exp2
.X_op
= O_illegal
;
2604 else if (the_insn
.exp
.X_op
== O_absent
)
2606 the_insn
.exp
= the_insn
.exp2
;
2607 the_insn
.exp2
.X_op
= O_illegal
;
2609 else if (the_insn
.exp
.X_op
== O_constant
)
2611 valueT val
= the_insn
.exp
.X_add_number
;
2612 switch (the_insn
.reloc
)
2617 case BFD_RELOC_SPARC_HH22
:
2618 val
= BSR (val
, 32);
2621 case BFD_RELOC_SPARC_LM22
:
2622 case BFD_RELOC_HI22
:
2623 val
= (val
>> 10) & 0x3fffff;
2626 case BFD_RELOC_SPARC_HM10
:
2627 val
= BSR (val
, 32);
2630 case BFD_RELOC_LO10
:
2634 case BFD_RELOC_SPARC_H34
:
2639 case BFD_RELOC_SPARC_H44
:
2644 case BFD_RELOC_SPARC_M44
:
2649 case BFD_RELOC_SPARC_L44
:
2653 case BFD_RELOC_SPARC_HIX22
:
2655 val
= (val
>> 10) & 0x3fffff;
2658 case BFD_RELOC_SPARC_LOX10
:
2659 val
= (val
& 0x3ff) | 0x1c00;
2662 the_insn
.exp
= the_insn
.exp2
;
2663 the_insn
.exp
.X_add_number
+= val
;
2664 the_insn
.exp2
.X_op
= O_illegal
;
2665 the_insn
.reloc
= old_reloc
;
2667 else if (the_insn
.exp2
.X_op
!= O_constant
)
2669 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2670 return special_case
;
2674 if (old_reloc
!= BFD_RELOC_SPARC13
2675 || the_insn
.reloc
!= BFD_RELOC_LO10
2676 || sparc_arch_size
!= 64
2679 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2680 return special_case
;
2682 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2686 /* Check for constants that don't require emitting a reloc. */
2687 if (the_insn
.exp
.X_op
== O_constant
2688 && the_insn
.exp
.X_add_symbol
== 0
2689 && the_insn
.exp
.X_op_symbol
== 0)
2691 /* For pc-relative call instructions, we reject
2692 constants to get better code. */
2694 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2695 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2697 error_message
= _(": PC-relative operand can't be a constant");
2701 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2702 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2704 error_message
= _(": TLS operand can't be a constant");
2708 /* Constants that won't fit are checked in md_apply_fix
2709 and bfd_install_relocation.
2710 ??? It would be preferable to install the constants
2711 into the insn here and save having to create a fixS
2712 for each one. There already exists code to handle
2713 all the various cases (e.g. in md_apply_fix and
2714 bfd_install_relocation) so duplicating all that code
2715 here isn't right. */
2717 /* This is a special case to handle cbcond instructions
2718 properly, which can need two relocations. The first
2719 one is for the 5-bit immediate field and the latter
2720 is going to be for the WDISP10 branch part. We
2721 handle the R_SPARC_5 immediate directly here so that
2722 we don't need to add support for multiple relocations
2723 in one instruction just yet. */
2724 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2726 valueT val
= the_insn
.exp
.X_add_number
;
2728 if (! in_bitfield_range (val
, 0x1f))
2730 error_message
= _(": Immediate value in cbcond is out of range.");
2733 opcode
|= val
& 0x1f;
2734 the_insn
.reloc
= BFD_RELOC_NONE
;
2755 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2757 error_message
= _(": invalid ASI name");
2763 if (! parse_const_expr_arg (&s
, &asi
))
2765 error_message
= _(": invalid ASI expression");
2768 if (asi
< 0 || asi
> 255)
2770 error_message
= _(": invalid ASI number");
2774 opcode
|= ASI (asi
);
2776 } /* Alternate space. */
2779 if (strncmp (s
, "%psr", 4) == 0)
2786 case 'q': /* Floating point queue. */
2787 if (strncmp (s
, "%fq", 3) == 0)
2794 case 'Q': /* Coprocessor queue. */
2795 if (strncmp (s
, "%cq", 3) == 0)
2803 if (strcmp (str
, "set") == 0
2804 || strcmp (str
, "setuw") == 0)
2806 special_case
= SPECIAL_CASE_SET
;
2809 else if (strcmp (str
, "setsw") == 0)
2811 special_case
= SPECIAL_CASE_SETSW
;
2814 else if (strcmp (str
, "setx") == 0)
2816 special_case
= SPECIAL_CASE_SETX
;
2819 else if (strncmp (str
, "fdiv", 4) == 0)
2821 special_case
= SPECIAL_CASE_FDIV
;
2827 if (strncmp (s
, "%asi", 4) != 0)
2833 if (strncmp (s
, "%fprs", 5) != 0)
2839 if (strncmp (s
, "%ccr", 4) != 0)
2845 if (strncmp (s
, "%tbr", 4) != 0)
2851 if (strncmp (s
, "%wim", 4) != 0)
2858 char *push
= input_line_pointer
;
2861 input_line_pointer
= s
;
2863 if (e
.X_op
== O_constant
)
2865 int n
= e
.X_add_number
;
2866 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2867 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2869 opcode
|= e
.X_add_number
<< 5;
2872 as_bad (_("non-immediate OPF operand, ignored"));
2873 s
= input_line_pointer
;
2874 input_line_pointer
= push
;
2879 if (strncmp (s
, "%y", 2) != 0)
2887 /* Parse a sparclet cpreg. */
2889 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2891 error_message
= _(": invalid cpreg name");
2894 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2899 as_fatal (_("failed sanity check."));
2900 } /* switch on arg code. */
2902 /* Break out of for() loop. */
2904 } /* For each arg that we expect. */
2909 /* Args don't match. */
2910 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2911 && (insn
->name
== insn
[1].name
2912 || !strcmp (insn
->name
, insn
[1].name
)))
2920 as_bad (_("Illegal operands%s"), error_message
);
2921 return special_case
;
2926 /* We have a match. Now see if the architecture is OK. */
2927 int needed_arch_mask
= insn
->architecture
;
2928 int hwcaps
= insn
->hwcaps
;
2930 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2932 hwcap_seen
|= hwcaps
;
2937 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2938 if (! needed_arch_mask
)
2940 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2943 if (needed_arch_mask
2944 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2947 /* Can we bump up the architecture? */
2948 else if (needed_arch_mask
2949 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2951 enum sparc_opcode_arch_val needed_architecture
=
2952 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2953 & needed_arch_mask
);
2955 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2957 && needed_architecture
> warn_after_architecture
)
2959 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2960 sparc_opcode_archs
[current_architecture
].name
,
2961 sparc_opcode_archs
[needed_architecture
].name
,
2963 warn_after_architecture
= needed_architecture
;
2965 current_architecture
= needed_architecture
;
2968 /* ??? This seems to be a bit fragile. What if the next entry in
2969 the opcode table is the one we want and it is supported?
2970 It is possible to arrange the table today so that this can't
2971 happen but what about tomorrow? */
2974 int arch
, printed_one_p
= 0;
2976 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2978 /* Create a list of the architectures that support the insn. */
2979 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2981 arch
= sparc_ffs (needed_arch_mask
);
2982 while ((1 << arch
) <= needed_arch_mask
)
2984 if ((1 << arch
) & needed_arch_mask
)
2988 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2995 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2996 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2998 sparc_opcode_archs
[max_architecture
].name
);
2999 return special_case
;
3002 /* Make sure the hwcaps used by the instruction are
3003 currently enabled. */
3004 if (hwcaps
& ~hwcap_allowed
)
3006 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3008 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3010 return special_case
;
3012 } /* If no match. */
3015 } /* Forever looking for a match. */
3017 the_insn
.opcode
= opcode
;
3018 return special_case
;
3021 /* Parse an argument that can be expressed as a keyword.
3022 (eg: #StoreStore or %ccfr).
3023 The result is a boolean indicating success.
3024 If successful, INPUT_POINTER is updated. */
3027 parse_keyword_arg (int (*lookup_fn
) (const char *),
3028 char **input_pointerP
,
3034 p
= *input_pointerP
;
3035 for (q
= p
+ (*p
== '#' || *p
== '%');
3036 ISALNUM (*q
) || *q
== '_';
3041 value
= (*lookup_fn
) (p
);
3046 *input_pointerP
= q
;
3050 /* Parse an argument that is a constant expression.
3051 The result is a boolean indicating success. */
3054 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3056 char *save
= input_line_pointer
;
3059 input_line_pointer
= *input_pointerP
;
3060 /* The next expression may be something other than a constant
3061 (say if we're not processing the right variant of the insn).
3062 Don't call expression unless we're sure it will succeed as it will
3063 signal an error (which we want to defer until later). */
3064 /* FIXME: It might be better to define md_operand and have it recognize
3065 things like %asi, etc. but continuing that route through to the end
3066 is a lot of work. */
3067 if (*input_line_pointer
== '%')
3069 input_line_pointer
= save
;
3073 *input_pointerP
= input_line_pointer
;
3074 input_line_pointer
= save
;
3075 if (exp
.X_op
!= O_constant
)
3077 *valueP
= exp
.X_add_number
;
3081 /* Subroutine of sparc_ip to parse an expression. */
3084 get_expression (char *str
)
3089 save_in
= input_line_pointer
;
3090 input_line_pointer
= str
;
3091 seg
= expression (&the_insn
.exp
);
3092 if (seg
!= absolute_section
3093 && seg
!= text_section
3094 && seg
!= data_section
3095 && seg
!= bss_section
3096 && seg
!= undefined_section
)
3098 the_insn
.error
= _("bad segment");
3099 expr_end
= input_line_pointer
;
3100 input_line_pointer
= save_in
;
3103 expr_end
= input_line_pointer
;
3104 input_line_pointer
= save_in
;
3108 /* Subroutine of md_assemble to output one insn. */
3111 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3113 char *toP
= frag_more (4);
3115 /* Put out the opcode. */
3116 if (INSN_BIG_ENDIAN
)
3117 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3119 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3121 /* Put out the symbol-dependent stuff. */
3122 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3124 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3125 (toP
- frag_now
->fr_literal
), /* Where. */
3130 /* Turn off overflow checking in fixup_segment. We'll do our
3131 own overflow checking in md_apply_fix. This is necessary because
3132 the insn size is 4 and fixup_segment will signal an overflow for
3133 large 8 byte quantities. */
3134 fixP
->fx_no_overflow
= 1;
3135 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3136 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3140 last_opcode
= theinsn
->opcode
;
3143 dwarf2_emit_insn (4);
3148 md_atof (int type
, char *litP
, int *sizeP
)
3150 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3153 /* Write a value out to the object file, using the appropriate
3157 md_number_to_chars (char *buf
, valueT val
, int n
)
3159 if (target_big_endian
)
3160 number_to_chars_bigendian (buf
, val
, n
);
3161 else if (target_little_endian_data
3162 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3163 /* Output debug words, which are not in allocated sections, as big
3165 number_to_chars_bigendian (buf
, val
, n
);
3166 else if (target_little_endian_data
|| ! target_big_endian
)
3167 number_to_chars_littleendian (buf
, val
, n
);
3170 /* Apply a fixS to the frags, now that we know the value it ought to
3174 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3176 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3177 offsetT val
= * (offsetT
*) valP
;
3180 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3182 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3185 /* SPARC ELF relocations don't use an addend in the data field. */
3186 if (fixP
->fx_addsy
!= NULL
)
3188 switch (fixP
->fx_r_type
)
3190 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3191 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3192 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3193 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3194 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3195 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3196 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3197 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3198 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3199 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3200 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3201 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3202 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3203 case BFD_RELOC_SPARC_TLS_IE_LD
:
3204 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3205 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3206 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3207 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3208 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3209 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3210 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3211 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3212 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3213 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3214 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3224 /* This is a hack. There should be a better way to
3225 handle this. Probably in terms of howto fields, once
3226 we can look at these fixups in terms of howtos. */
3227 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3228 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3231 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3232 generate a reloc, then we just want to let the reloc addend set
3233 the value. We do not want to also stuff the addend into the
3234 object file. Including the addend in the object file works when
3235 doing a static link, because the linker will ignore the object
3236 file contents. However, the dynamic linker does not ignore the
3237 object file contents. */
3238 if (fixP
->fx_addsy
!= NULL
3239 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3242 /* When generating PIC code, we do not want an addend for a reloc
3243 against a local symbol. We adjust fx_addnumber to cancel out the
3244 value already included in val, and to also cancel out the
3245 adjustment which bfd_install_relocation will create. */
3247 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3248 && fixP
->fx_addsy
!= NULL
3249 && ! S_IS_COMMON (fixP
->fx_addsy
)
3250 && symbol_section_p (fixP
->fx_addsy
))
3251 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3253 /* When generating PIC code, we need to fiddle to get
3254 bfd_install_relocation to do the right thing for a PC relative
3255 reloc against a local symbol which we are going to keep. */
3257 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3258 && fixP
->fx_addsy
!= NULL
3259 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3260 || S_IS_WEAK (fixP
->fx_addsy
))
3261 && S_IS_DEFINED (fixP
->fx_addsy
)
3262 && ! S_IS_COMMON (fixP
->fx_addsy
))
3265 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3269 /* If this is a data relocation, just output VAL. */
3271 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3273 md_number_to_chars (buf
, val
, 1);
3275 else if (fixP
->fx_r_type
== BFD_RELOC_16
3276 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3278 md_number_to_chars (buf
, val
, 2);
3280 else if (fixP
->fx_r_type
== BFD_RELOC_32
3281 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3282 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3284 md_number_to_chars (buf
, val
, 4);
3286 else if (fixP
->fx_r_type
== BFD_RELOC_64
3287 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3289 md_number_to_chars (buf
, val
, 8);
3291 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3292 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3299 /* It's a relocation against an instruction. */
3301 if (INSN_BIG_ENDIAN
)
3302 insn
= bfd_getb32 ((unsigned char *) buf
);
3304 insn
= bfd_getl32 ((unsigned char *) buf
);
3306 switch (fixP
->fx_r_type
)
3308 case BFD_RELOC_32_PCREL_S2
:
3310 /* FIXME: This increment-by-one deserves a comment of why it's
3312 if (! sparc_pic_code
3313 || fixP
->fx_addsy
== NULL
3314 || symbol_section_p (fixP
->fx_addsy
))
3317 insn
|= val
& 0x3fffffff;
3319 /* See if we have a delay slot. */
3320 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3324 #define XCC (2 << 20)
3325 #define COND(x) (((x)&0xf)<<25)
3326 #define CONDA COND(0x8)
3327 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3328 #define INSN_BA (F2(0,2) | CONDA)
3329 #define INSN_OR F3(2, 0x2, 0)
3330 #define INSN_NOP F2(0,4)
3334 /* If the instruction is a call with either:
3336 arithmetic instruction with rd == %o7
3337 where rs1 != %o7 and rs2 if it is register != %o7
3338 then we can optimize if the call destination is near
3339 by changing the call into a branch always. */
3340 if (INSN_BIG_ENDIAN
)
3341 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3343 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3344 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3346 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3347 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3348 || ((delay
& RD (~0)) != RD (O7
))))
3350 if ((delay
& RS1 (~0)) == RS1 (O7
)
3351 || ((delay
& F3I (~0)) == 0
3352 && (delay
& RS2 (~0)) == RS2 (O7
)))
3354 /* Ensure the branch will fit into simm22. */
3355 if ((val
& 0x3fe00000)
3356 && (val
& 0x3fe00000) != 0x3fe00000)
3358 /* Check if the arch is v9 and branch will fit
3360 if (((val
& 0x3c0000) == 0
3361 || (val
& 0x3c0000) == 0x3c0000)
3362 && (sparc_arch_size
== 64
3363 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3365 insn
= INSN_BPA
| (val
& 0x7ffff);
3368 insn
= INSN_BA
| (val
& 0x3fffff);
3369 if (fixP
->fx_where
>= 4
3370 && ((delay
& (0xffffffff ^ RS1 (~0)))
3371 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3376 if (INSN_BIG_ENDIAN
)
3377 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3379 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3380 if ((setter
& (0xffffffff ^ RD (~0)))
3381 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3388 If call foo was replaced with ba, replace
3389 or %rN, %g0, %o7 with nop. */
3390 reg
= (delay
& RS1 (~0)) >> 14;
3391 if (reg
!= ((setter
& RD (~0)) >> 25)
3392 || reg
== G0
|| reg
== O7
)
3395 if (INSN_BIG_ENDIAN
)
3396 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3398 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3403 case BFD_RELOC_SPARC_11
:
3404 if (! in_signed_range (val
, 0x7ff))
3405 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3406 _("relocation overflow"));
3407 insn
|= val
& 0x7ff;
3410 case BFD_RELOC_SPARC_10
:
3411 if (! in_signed_range (val
, 0x3ff))
3412 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3413 _("relocation overflow"));
3414 insn
|= val
& 0x3ff;
3417 case BFD_RELOC_SPARC_7
:
3418 if (! in_bitfield_range (val
, 0x7f))
3419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3420 _("relocation overflow"));
3424 case BFD_RELOC_SPARC_6
:
3425 if (! in_bitfield_range (val
, 0x3f))
3426 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3427 _("relocation overflow"));
3431 case BFD_RELOC_SPARC_5
:
3432 if (! in_bitfield_range (val
, 0x1f))
3433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3434 _("relocation overflow"));
3438 case BFD_RELOC_SPARC_WDISP10
:
3441 || val
<= -(offsetT
) 0x808)
3442 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3443 _("relocation overflow"));
3444 /* FIXME: The +1 deserves a comment. */
3445 val
= (val
>> 2) + 1;
3446 insn
|= ((val
& 0x300) << 11)
3447 | ((val
& 0xff) << 5);
3450 case BFD_RELOC_SPARC_WDISP16
:
3453 || val
<= -(offsetT
) 0x20008)
3454 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3455 _("relocation overflow"));
3456 /* FIXME: The +1 deserves a comment. */
3457 val
= (val
>> 2) + 1;
3458 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3461 case BFD_RELOC_SPARC_WDISP19
:
3464 || val
<= -(offsetT
) 0x100008)
3465 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3466 _("relocation overflow"));
3467 /* FIXME: The +1 deserves a comment. */
3468 val
= (val
>> 2) + 1;
3469 insn
|= val
& 0x7ffff;
3472 case BFD_RELOC_SPARC_HH22
:
3473 val
= BSR (val
, 32);
3476 case BFD_RELOC_SPARC_LM22
:
3477 case BFD_RELOC_HI22
:
3478 if (!fixP
->fx_addsy
)
3479 insn
|= (val
>> 10) & 0x3fffff;
3481 /* FIXME: Need comment explaining why we do this. */
3485 case BFD_RELOC_SPARC22
:
3486 if (val
& ~0x003fffff)
3487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3488 _("relocation overflow"));
3489 insn
|= (val
& 0x3fffff);
3492 case BFD_RELOC_SPARC_HM10
:
3493 val
= BSR (val
, 32);
3496 case BFD_RELOC_LO10
:
3497 if (!fixP
->fx_addsy
)
3498 insn
|= val
& 0x3ff;
3500 /* FIXME: Need comment explaining why we do this. */
3504 case BFD_RELOC_SPARC_OLO10
:
3506 val
+= fixP
->tc_fix_data
;
3509 case BFD_RELOC_SPARC13
:
3510 if (! in_signed_range (val
, 0x1fff))
3511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3512 _("relocation overflow"));
3513 insn
|= val
& 0x1fff;
3516 case BFD_RELOC_SPARC_WDISP22
:
3517 val
= (val
>> 2) + 1;
3519 case BFD_RELOC_SPARC_BASE22
:
3520 insn
|= val
& 0x3fffff;
3523 case BFD_RELOC_SPARC_H34
:
3524 if (!fixP
->fx_addsy
)
3528 insn
|= tval
& 0x3fffff;
3532 case BFD_RELOC_SPARC_H44
:
3533 if (!fixP
->fx_addsy
)
3537 insn
|= tval
& 0x3fffff;
3541 case BFD_RELOC_SPARC_M44
:
3542 if (!fixP
->fx_addsy
)
3543 insn
|= (val
>> 12) & 0x3ff;
3546 case BFD_RELOC_SPARC_L44
:
3547 if (!fixP
->fx_addsy
)
3548 insn
|= val
& 0xfff;
3551 case BFD_RELOC_SPARC_HIX22
:
3552 if (!fixP
->fx_addsy
)
3554 val
^= ~(offsetT
) 0;
3555 insn
|= (val
>> 10) & 0x3fffff;
3559 case BFD_RELOC_SPARC_LOX10
:
3560 if (!fixP
->fx_addsy
)
3561 insn
|= 0x1c00 | (val
& 0x3ff);
3564 case BFD_RELOC_NONE
:
3566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3567 _("bad or unhandled relocation type: 0x%02x"),
3572 if (INSN_BIG_ENDIAN
)
3573 bfd_putb32 (insn
, (unsigned char *) buf
);
3575 bfd_putl32 (insn
, (unsigned char *) buf
);
3578 /* Are we finished with this relocation now? */
3579 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3583 /* Translate internal representation of relocation info to BFD target
3587 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3589 static arelent
*relocs
[3];
3591 bfd_reloc_code_real_type code
;
3593 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3596 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3597 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3598 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3600 switch (fixp
->fx_r_type
)
3604 case BFD_RELOC_HI22
:
3605 case BFD_RELOC_LO10
:
3606 case BFD_RELOC_32_PCREL_S2
:
3607 case BFD_RELOC_SPARC13
:
3608 case BFD_RELOC_SPARC22
:
3609 case BFD_RELOC_SPARC_PC22
:
3610 case BFD_RELOC_SPARC_PC10
:
3611 case BFD_RELOC_SPARC_BASE13
:
3612 case BFD_RELOC_SPARC_WDISP10
:
3613 case BFD_RELOC_SPARC_WDISP16
:
3614 case BFD_RELOC_SPARC_WDISP19
:
3615 case BFD_RELOC_SPARC_WDISP22
:
3617 case BFD_RELOC_SPARC_5
:
3618 case BFD_RELOC_SPARC_6
:
3619 case BFD_RELOC_SPARC_7
:
3620 case BFD_RELOC_SPARC_10
:
3621 case BFD_RELOC_SPARC_11
:
3622 case BFD_RELOC_SPARC_HH22
:
3623 case BFD_RELOC_SPARC_HM10
:
3624 case BFD_RELOC_SPARC_LM22
:
3625 case BFD_RELOC_SPARC_PC_HH22
:
3626 case BFD_RELOC_SPARC_PC_HM10
:
3627 case BFD_RELOC_SPARC_PC_LM22
:
3628 case BFD_RELOC_SPARC_H34
:
3629 case BFD_RELOC_SPARC_H44
:
3630 case BFD_RELOC_SPARC_M44
:
3631 case BFD_RELOC_SPARC_L44
:
3632 case BFD_RELOC_SPARC_HIX22
:
3633 case BFD_RELOC_SPARC_LOX10
:
3634 case BFD_RELOC_SPARC_REV32
:
3635 case BFD_RELOC_SPARC_OLO10
:
3636 case BFD_RELOC_SPARC_UA16
:
3637 case BFD_RELOC_SPARC_UA32
:
3638 case BFD_RELOC_SPARC_UA64
:
3639 case BFD_RELOC_8_PCREL
:
3640 case BFD_RELOC_16_PCREL
:
3641 case BFD_RELOC_32_PCREL
:
3642 case BFD_RELOC_64_PCREL
:
3643 case BFD_RELOC_SPARC_PLT32
:
3644 case BFD_RELOC_SPARC_PLT64
:
3645 case BFD_RELOC_VTABLE_ENTRY
:
3646 case BFD_RELOC_VTABLE_INHERIT
:
3647 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3648 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3649 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3650 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3651 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3652 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3653 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3654 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3655 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3656 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3657 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3658 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3659 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3660 case BFD_RELOC_SPARC_TLS_IE_LD
:
3661 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3662 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3663 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3664 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3665 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3666 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3667 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3668 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3669 case BFD_RELOC_SPARC_GOTDATA_OP
:
3670 code
= fixp
->fx_r_type
;
3677 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3678 /* If we are generating PIC code, we need to generate a different
3682 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3684 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3687 #define GOTT_BASE "__GOTT_BASE__"
3688 #define GOTT_INDEX "__GOTT_INDEX__"
3691 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3697 case BFD_RELOC_32_PCREL_S2
:
3698 if (generic_force_reloc (fixp
))
3699 code
= BFD_RELOC_SPARC_WPLT30
;
3701 case BFD_RELOC_HI22
:
3702 code
= BFD_RELOC_SPARC_GOT22
;
3703 if (fixp
->fx_addsy
!= NULL
)
3705 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3706 code
= BFD_RELOC_SPARC_PC22
;
3708 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3709 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3710 code
= BFD_RELOC_HI22
; /* Unchanged. */
3714 case BFD_RELOC_LO10
:
3715 code
= BFD_RELOC_SPARC_GOT10
;
3716 if (fixp
->fx_addsy
!= NULL
)
3718 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3719 code
= BFD_RELOC_SPARC_PC10
;
3721 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3722 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3723 code
= BFD_RELOC_LO10
; /* Unchanged. */
3727 case BFD_RELOC_SPARC13
:
3728 code
= BFD_RELOC_SPARC_GOT13
;
3734 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3736 /* Nothing is aligned in DWARF debugging sections. */
3737 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3740 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3741 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3742 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3746 if (code
== BFD_RELOC_SPARC_OLO10
)
3747 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3749 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3750 if (reloc
->howto
== 0)
3752 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3753 _("internal error: can't export reloc type %d (`%s')"),
3754 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3760 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3763 if (reloc
->howto
->pc_relative
== 0
3764 || code
== BFD_RELOC_SPARC_PC10
3765 || code
== BFD_RELOC_SPARC_PC22
)
3766 reloc
->addend
= fixp
->fx_addnumber
;
3767 else if (sparc_pic_code
3768 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3769 && fixp
->fx_addsy
!= NULL
3770 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3771 || S_IS_WEAK (fixp
->fx_addsy
))
3772 && S_IS_DEFINED (fixp
->fx_addsy
)
3773 && ! S_IS_COMMON (fixp
->fx_addsy
))
3774 reloc
->addend
= fixp
->fx_addnumber
;
3776 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3778 #else /* elf or coff */
3780 if (code
!= BFD_RELOC_32_PCREL_S2
3781 && code
!= BFD_RELOC_SPARC_WDISP22
3782 && code
!= BFD_RELOC_SPARC_WDISP16
3783 && code
!= BFD_RELOC_SPARC_WDISP19
3784 && code
!= BFD_RELOC_SPARC_WDISP10
3785 && code
!= BFD_RELOC_SPARC_WPLT30
3786 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3787 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3788 reloc
->addend
= fixp
->fx_addnumber
;
3789 else if (symbol_section_p (fixp
->fx_addsy
))
3790 reloc
->addend
= (section
->vma
3791 + fixp
->fx_addnumber
3792 + md_pcrel_from (fixp
));
3794 reloc
->addend
= fixp
->fx_offset
;
3797 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3798 on the same location. */
3799 if (code
== BFD_RELOC_SPARC_OLO10
)
3801 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3804 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3806 = symbol_get_bfdsym (section_symbol (absolute_section
));
3807 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3808 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3809 reloc
->addend
= fixp
->tc_fix_data
;
3815 /* We have no need to default values of symbols. */
3818 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
3823 /* Round up a section size to the appropriate boundary. */
3826 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
3829 /* This is not right for ELF; a.out wants it, and COFF will force
3830 the alignment anyways. */
3831 valueT align
= ((valueT
) 1
3832 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3835 /* Turn alignment value into a mask. */
3837 newsize
= (size
+ align
) & ~align
;
3844 /* Exactly what point is a PC-relative offset relative TO?
3845 On the sparc, they're relative to the address of the offset, plus
3846 its size. This gets us to the following instruction.
3847 (??? Is this right? FIXME-SOON) */
3849 md_pcrel_from (fixS
*fixP
)
3853 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3854 if (! sparc_pic_code
3855 || fixP
->fx_addsy
== NULL
3856 || symbol_section_p (fixP
->fx_addsy
))
3857 ret
+= fixP
->fx_size
;
3861 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3872 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3875 return (value
== 1) ? shift
: -1;
3878 /* Sort of like s_lcomm. */
3881 static int max_alignment
= 15;
3885 s_reserve (int ignore ATTRIBUTE_UNUSED
)
3895 name
= input_line_pointer
;
3896 c
= get_symbol_end ();
3897 p
= input_line_pointer
;
3901 if (*input_line_pointer
!= ',')
3903 as_bad (_("Expected comma after name"));
3904 ignore_rest_of_line ();
3908 ++input_line_pointer
;
3910 if ((size
= get_absolute_expression ()) < 0)
3912 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3913 ignore_rest_of_line ();
3918 symbolP
= symbol_find_or_make (name
);
3921 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3922 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3924 as_bad (_("bad .reserve segment -- expected BSS segment"));
3928 if (input_line_pointer
[2] == '.')
3929 input_line_pointer
+= 7;
3931 input_line_pointer
+= 6;
3934 if (*input_line_pointer
== ',')
3936 ++input_line_pointer
;
3939 if (*input_line_pointer
== '\n')
3941 as_bad (_("missing alignment"));
3942 ignore_rest_of_line ();
3946 align
= (int) get_absolute_expression ();
3949 if (align
> max_alignment
)
3951 align
= max_alignment
;
3952 as_warn (_("alignment too large; assuming %d"), align
);
3958 as_bad (_("negative alignment"));
3959 ignore_rest_of_line ();
3965 temp
= mylog2 (align
);
3968 as_bad (_("alignment not a power of 2"));
3969 ignore_rest_of_line ();
3976 record_alignment (bss_section
, align
);
3981 if (!S_IS_DEFINED (symbolP
)
3983 && S_GET_OTHER (symbolP
) == 0
3984 && S_GET_DESC (symbolP
) == 0
3991 segT current_seg
= now_seg
;
3992 subsegT current_subseg
= now_subseg
;
3994 /* Switch to bss. */
3995 subseg_set (bss_section
, 1);
3999 frag_align (align
, 0, 0);
4001 /* Detach from old frag. */
4002 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4003 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4005 symbol_set_frag (symbolP
, frag_now
);
4006 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4007 (offsetT
) size
, (char *) 0);
4010 S_SET_SEGMENT (symbolP
, bss_section
);
4012 subseg_set (current_seg
, current_subseg
);
4015 S_SET_SIZE (symbolP
, size
);
4021 as_warn (_("Ignoring attempt to re-define symbol %s"),
4022 S_GET_NAME (symbolP
));
4025 demand_empty_rest_of_line ();
4029 s_common (int ignore ATTRIBUTE_UNUSED
)
4037 name
= input_line_pointer
;
4038 c
= get_symbol_end ();
4039 /* Just after name is now '\0'. */
4040 p
= input_line_pointer
;
4043 if (*input_line_pointer
!= ',')
4045 as_bad (_("Expected comma after symbol-name"));
4046 ignore_rest_of_line ();
4051 input_line_pointer
++;
4053 if ((temp
= get_absolute_expression ()) < 0)
4055 as_bad (_(".COMMon length (%lu) out of range ignored"),
4056 (unsigned long) temp
);
4057 ignore_rest_of_line ();
4062 symbolP
= symbol_find_or_make (name
);
4064 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4066 as_bad (_("Ignoring attempt to re-define symbol"));
4067 ignore_rest_of_line ();
4070 if (S_GET_VALUE (symbolP
) != 0)
4072 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4074 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4075 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4081 S_SET_VALUE (symbolP
, (valueT
) size
);
4082 S_SET_EXTERNAL (symbolP
);
4085 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4086 if (*input_line_pointer
!= ',')
4088 as_bad (_("Expected comma after common length"));
4089 ignore_rest_of_line ();
4092 input_line_pointer
++;
4094 if (*input_line_pointer
!= '"')
4096 temp
= get_absolute_expression ();
4099 if (temp
> max_alignment
)
4101 temp
= max_alignment
;
4102 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4108 as_bad (_("negative alignment"));
4109 ignore_rest_of_line ();
4114 if (symbol_get_obj (symbolP
)->local
)
4121 old_subsec
= now_subseg
;
4126 align
= mylog2 (temp
);
4130 as_bad (_("alignment not a power of 2"));
4131 ignore_rest_of_line ();
4135 record_alignment (bss_section
, align
);
4136 subseg_set (bss_section
, 0);
4138 frag_align (align
, 0, 0);
4139 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4140 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4141 symbol_set_frag (symbolP
, frag_now
);
4142 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4143 (offsetT
) size
, (char *) 0);
4145 S_SET_SEGMENT (symbolP
, bss_section
);
4146 S_CLEAR_EXTERNAL (symbolP
);
4147 S_SET_SIZE (symbolP
, size
);
4148 subseg_set (old_sec
, old_subsec
);
4151 #endif /* OBJ_ELF */
4154 S_SET_VALUE (symbolP
, (valueT
) size
);
4156 S_SET_ALIGN (symbolP
, temp
);
4157 S_SET_SIZE (symbolP
, size
);
4159 S_SET_EXTERNAL (symbolP
);
4160 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4165 input_line_pointer
++;
4166 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4167 if (*input_line_pointer
== '.')
4168 input_line_pointer
++;
4169 /* @@ Some say data, some say bss. */
4170 if (strncmp (input_line_pointer
, "bss\"", 4)
4171 && strncmp (input_line_pointer
, "data\"", 5))
4173 while (*--input_line_pointer
!= '"')
4175 input_line_pointer
--;
4176 goto bad_common_segment
;
4178 while (*input_line_pointer
++ != '"')
4180 goto allocate_common
;
4183 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4185 demand_empty_rest_of_line ();
4190 p
= input_line_pointer
;
4191 while (*p
&& *p
!= '\n')
4195 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4197 input_line_pointer
= p
;
4198 ignore_rest_of_line ();
4203 /* Handle the .empty pseudo-op. This suppresses the warnings about
4204 invalid delay slot usage. */
4207 s_empty (int ignore ATTRIBUTE_UNUSED
)
4209 /* The easy way to implement is to just forget about the last
4215 s_seg (int ignore ATTRIBUTE_UNUSED
)
4218 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4220 input_line_pointer
+= 6;
4224 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4226 input_line_pointer
+= 6;
4230 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4232 input_line_pointer
+= 7;
4236 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4238 input_line_pointer
+= 5;
4239 /* We only support 2 segments -- text and data -- for now, so
4240 things in the "bss segment" will have to go into data for now.
4241 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4242 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4245 as_bad (_("Unknown segment type"));
4246 demand_empty_rest_of_line ();
4252 subseg_set (data_section
, 1);
4253 demand_empty_rest_of_line ();
4257 s_proc (int ignore ATTRIBUTE_UNUSED
)
4259 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4261 ++input_line_pointer
;
4263 ++input_line_pointer
;
4266 /* This static variable is set by s_uacons to tell sparc_cons_align
4267 that the expression does not need to be aligned. */
4269 static int sparc_no_align_cons
= 0;
4271 /* This static variable is set by sparc_cons to emit requested types
4272 of relocations in cons_fix_new_sparc. */
4274 static const char *sparc_cons_special_reloc
;
4276 /* This handles the unaligned space allocation pseudo-ops, such as
4277 .uaword. .uaword is just like .word, but the value does not need
4281 s_uacons (int bytes
)
4283 /* Tell sparc_cons_align not to align this value. */
4284 sparc_no_align_cons
= 1;
4286 sparc_no_align_cons
= 0;
4289 /* This handles the native word allocation pseudo-op .nword.
4290 For sparc_arch_size 32 it is equivalent to .word, for
4291 sparc_arch_size 64 it is equivalent to .xword. */
4294 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4296 cons (sparc_arch_size
== 32 ? 4 : 8);
4300 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4304 .register %g[2367],{#scratch|symbolname|#ignore}
4308 s_register (int ignore ATTRIBUTE_UNUSED
)
4313 const char *regname
;
4315 if (input_line_pointer
[0] != '%'
4316 || input_line_pointer
[1] != 'g'
4317 || ((input_line_pointer
[2] & ~1) != '2'
4318 && (input_line_pointer
[2] & ~1) != '6')
4319 || input_line_pointer
[3] != ',')
4320 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4321 reg
= input_line_pointer
[2] - '0';
4322 input_line_pointer
+= 4;
4324 if (*input_line_pointer
== '#')
4326 ++input_line_pointer
;
4327 regname
= input_line_pointer
;
4328 c
= get_symbol_end ();
4329 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4330 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4331 if (regname
[0] == 'i')
4338 regname
= input_line_pointer
;
4339 c
= get_symbol_end ();
4341 if (sparc_arch_size
== 64)
4345 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4346 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4347 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4348 as_bad (_("redefinition of global register"));
4352 if (regname
== NULL
)
4353 globals
[reg
] = (symbolS
*) 1;
4358 if (symbol_find (regname
))
4359 as_bad (_("Register symbol %s already defined."),
4362 globals
[reg
] = symbol_make (regname
);
4363 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4365 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4366 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4367 flags
|= BSF_GLOBAL
;
4368 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4369 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4370 S_SET_ALIGN (globals
[reg
], reg
);
4371 S_SET_SIZE (globals
[reg
], 0);
4372 /* Although we actually want undefined_section here,
4373 we have to use absolute_section, because otherwise
4374 generic as code will make it a COM section.
4375 We fix this up in sparc_adjust_symtab. */
4376 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4377 S_SET_OTHER (globals
[reg
], 0);
4378 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4379 ->internal_elf_sym
.st_info
=
4380 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4381 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4382 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4387 *input_line_pointer
= c
;
4389 demand_empty_rest_of_line ();
4392 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4393 symbols which need it. */
4396 sparc_adjust_symtab (void)
4400 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4402 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4403 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4406 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4407 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4410 S_SET_SEGMENT (sym
, undefined_section
);
4415 /* If the --enforce-aligned-data option is used, we require .word,
4416 et. al., to be aligned correctly. We do it by setting up an
4417 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4418 no unexpected alignment was introduced.
4420 The SunOS and Solaris native assemblers enforce aligned data by
4421 default. We don't want to do that, because gcc can deliberately
4422 generate misaligned data if the packed attribute is used. Instead,
4423 we permit misaligned data by default, and permit the user to set an
4424 option to check for it. */
4427 sparc_cons_align (int nbytes
)
4431 /* Only do this if we are enforcing aligned data. */
4432 if (! enforce_aligned_data
)
4435 /* Don't align if this is an unaligned pseudo-op. */
4436 if (sparc_no_align_cons
)
4439 nalign
= mylog2 (nbytes
);
4443 gas_assert (nalign
> 0);
4445 if (now_seg
== absolute_section
)
4447 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4448 as_bad (_("misaligned data"));
4452 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4453 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4455 record_alignment (now_seg
, nalign
);
4458 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4461 sparc_handle_align (fragS
*fragp
)
4466 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4468 switch (fragp
->fr_type
)
4472 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4476 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4487 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4489 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4490 if (INSN_BIG_ENDIAN
)
4491 number_to_chars_bigendian (p
, wval
, 4);
4493 number_to_chars_littleendian (p
, wval
, 4);
4499 if (INSN_BIG_ENDIAN
)
4500 number_to_chars_bigendian (p
, 0x01000000, 4);
4502 number_to_chars_littleendian (p
, 0x01000000, 4);
4504 fragp
->fr_fix
+= fix
;
4514 /* Some special processing for a Sparc ELF file. */
4517 sparc_elf_final_processing (void)
4519 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4520 sort of BFD interface for this. */
4521 if (sparc_arch_size
== 64)
4523 switch (sparc_memory_model
)
4526 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4529 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4535 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4536 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4537 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4538 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4539 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4540 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4544 sparc_cons (expressionS
*exp
, int size
)
4549 sparc_cons_special_reloc
= NULL
;
4550 save
= input_line_pointer
;
4551 if (input_line_pointer
[0] == '%'
4552 && input_line_pointer
[1] == 'r'
4553 && input_line_pointer
[2] == '_')
4555 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4557 input_line_pointer
+= 7;
4558 sparc_cons_special_reloc
= "disp";
4560 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4562 if (size
!= 4 && size
!= 8)
4563 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4566 input_line_pointer
+= 6;
4567 sparc_cons_special_reloc
= "plt";
4570 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4572 if (size
!= 4 && size
!= 8)
4573 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4576 input_line_pointer
+= 13;
4577 sparc_cons_special_reloc
= "tls_dtpoff";
4580 if (sparc_cons_special_reloc
)
4587 if (*input_line_pointer
!= '8')
4589 input_line_pointer
--;
4592 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4596 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4600 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4610 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4611 sparc_cons_special_reloc
, size
* 8, size
);
4615 input_line_pointer
+= 2;
4616 if (*input_line_pointer
!= '(')
4618 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4619 sparc_cons_special_reloc
, size
* 8);
4626 input_line_pointer
= save
;
4627 sparc_cons_special_reloc
= NULL
;
4632 char *end
= ++input_line_pointer
;
4635 while (! is_end_of_line
[(c
= *end
)])
4649 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4650 sparc_cons_special_reloc
, size
* 8);
4656 if (input_line_pointer
!= end
)
4658 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4659 sparc_cons_special_reloc
, size
* 8);
4663 input_line_pointer
++;
4665 c
= *input_line_pointer
;
4666 if (! is_end_of_line
[c
] && c
!= ',')
4667 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4668 sparc_cons_special_reloc
, size
* 8);
4674 if (sparc_cons_special_reloc
== NULL
)
4680 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4681 reloc for a cons. We could use the definition there, except that
4682 we want to handle little endian relocs specially. */
4685 cons_fix_new_sparc (fragS
*frag
,
4687 unsigned int nbytes
,
4690 bfd_reloc_code_real_type r
;
4692 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4693 (nbytes
== 2 ? BFD_RELOC_16
:
4694 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4696 if (target_little_endian_data
4698 && now_seg
->flags
& SEC_ALLOC
)
4699 r
= BFD_RELOC_SPARC_REV32
;
4701 if (sparc_cons_special_reloc
)
4703 if (*sparc_cons_special_reloc
== 'd')
4706 case 1: r
= BFD_RELOC_8_PCREL
; break;
4707 case 2: r
= BFD_RELOC_16_PCREL
; break;
4708 case 4: r
= BFD_RELOC_32_PCREL
; break;
4709 case 8: r
= BFD_RELOC_64_PCREL
; break;
4712 else if (*sparc_cons_special_reloc
== 'p')
4715 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4716 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4721 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4722 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4725 else if (sparc_no_align_cons
)
4729 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4730 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4731 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4736 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4737 sparc_cons_special_reloc
= NULL
;
4741 sparc_cfi_frame_initial_instructions (void)
4743 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4747 sparc_regname_to_dw2regnum (char *regname
)
4755 p
= strchr (q
, regname
[0]);
4758 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4760 return (p
- q
) * 8 + regname
[1] - '0';
4762 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4764 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4766 if (regname
[0] == 'f' || regname
[0] == 'r')
4768 unsigned int regnum
;
4770 regnum
= strtoul (regname
+ 1, &q
, 10);
4773 if (regnum
>= ((regname
[0] == 'f'
4774 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4777 if (regname
[0] == 'f')
4780 if (regnum
>= 64 && (regnum
& 1))
4789 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4791 sparc_cons_special_reloc
= "disp";
4792 sparc_no_align_cons
= 1;
4793 emit_expr (exp
, nbytes
);
4794 sparc_no_align_cons
= 0;
4795 sparc_cons_special_reloc
= NULL
;