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2012-11-09 Nick Clifton <nickc@redhat.com>
[deliverable/binutils-gdb.git] / gas / config / tc-sparc.c
1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
22
23 #include "as.h"
24 #include "safe-ctype.h"
25 #include "subsegs.h"
26
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
29
30 #ifdef OBJ_ELF
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
33 #endif
34
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
40
41 static int sparc_ip (char *, const struct sparc_opcode **);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
45
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
50 #ifndef DEFAULT_ARCH
51 #define DEFAULT_ARCH "sparclite"
52 #endif
53 static char *default_arch = DEFAULT_ARCH;
54
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
56 have been set. */
57 static int default_init_p;
58
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6;
61
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture;
68
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size;
74
75 #ifdef OBJ_ELF
76 /* The currently selected v9 memory model. Currently only used for
77 ELF. */
78 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO;
79
80 #ifndef TE_SOLARIS
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen;
84 #endif
85 #endif
86
87 static int hwcap_allowed;
88
89 static int architecture_requested;
90 static int warn_on_bump;
91
92 /* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94 static enum sparc_opcode_arch_val warn_after_architecture;
95
96 /* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98 static int no_undeclared_regs;
99
100 /* Non-zero if we should try to relax jumps and calls. */
101 static int sparc_relax;
102
103 /* Non-zero if we are generating PIC code. */
104 int sparc_pic_code;
105
106 /* Non-zero if we should give an error when misaligned data is seen. */
107 static int enforce_aligned_data;
108
109 extern int target_big_endian;
110
111 static int target_little_endian_data;
112
113 /* Symbols for global registers on v9. */
114 static symbolS *globals[8];
115
116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117 int sparc_cie_data_alignment;
118
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
127 #endif
128
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control *op_hash;
131
132 static void s_data1 (void);
133 static void s_seg (int);
134 static void s_proc (int);
135 static void s_reserve (int);
136 static void s_common (int);
137 static void s_empty (int);
138 static void s_uacons (int);
139 static void s_ncons (int);
140 #ifdef OBJ_ELF
141 static void s_register (int);
142 #endif
143
144 const pseudo_typeS md_pseudo_table[] =
145 {
146 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */
147 {"common", s_common, 0},
148 {"empty", s_empty, 0},
149 {"global", s_globl, 0},
150 {"half", cons, 2},
151 {"nword", s_ncons, 0},
152 {"optim", s_ignore, 0},
153 {"proc", s_proc, 0},
154 {"reserve", s_reserve, 0},
155 {"seg", s_seg, 0},
156 {"skip", s_space, 0},
157 {"word", cons, 4},
158 {"xword", cons, 8},
159 {"uahalf", s_uacons, 2},
160 {"uaword", s_uacons, 4},
161 {"uaxword", s_uacons, 8},
162 #ifdef OBJ_ELF
163 /* These are specific to sparc/svr4. */
164 {"2byte", s_uacons, 2},
165 {"4byte", s_uacons, 4},
166 {"8byte", s_uacons, 8},
167 {"register", s_register, 0},
168 #endif
169 {NULL, 0, 0},
170 };
171
172 /* This array holds the chars that always start a comment. If the
173 pre-processor is disabled, these aren't very useful. */
174 const char comment_chars[] = "!"; /* JF removed '|' from
175 comment_chars. */
176
177 /* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
179 .line and .file directives will appear in the pre-processed output. */
180 /* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
182 #NO_APP at the beginning of its output. */
183 /* Also note that comments started like this one will always
184 work if '/' isn't otherwise defined. */
185 const char line_comment_chars[] = "#";
186
187 const char line_separator_chars[] = ";";
188
189 /* Chars that can be used to separate mant from exp in floating point
190 nums. */
191 const char EXP_CHARS[] = "eE";
192
193 /* Chars that mean this number is a floating point constant.
194 As in 0f12.456
195 or 0d1.2345e12 */
196 const char FLT_CHARS[] = "rRsSfFdDxXpP";
197
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
201
202 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
203
204 struct sparc_it
205 {
206 char *error;
207 unsigned long opcode;
208 struct nlist *nlistp;
209 expressionS exp;
210 expressionS exp2;
211 int pcrel;
212 bfd_reloc_code_real_type reloc;
213 };
214
215 struct sparc_it the_insn, set_insn;
216
217 static void output_insn (const struct sparc_opcode *, struct sparc_it *);
218 \f
219 /* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
222 and file formats. */
223
224 enum sparc_arch_types {v6, v7, v8, sparclet, sparclite, sparc86x, v8plus,
225 v8plusa, v9, v9a, v9b, v9_64};
226
227 static struct sparc_arch {
228 char *name;
229 char *opcode_arch;
230 enum sparc_arch_types arch_type;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size;
234 /* Allowable arg to -A? */
235 int user_option_p;
236 int hwcap_allowed;
237 } sparc_arch_table[] = {
238 { "v6", "v6", v6, 0, 1, 0 },
239 { "v7", "v7", v7, 0, 1, 0 },
240 { "v8", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
241 { "v8a", "v8", v8, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
242 { "sparc", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
243 { "sparcvis", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
244 { "sparcvis2", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
245 { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF },
246 { "sparcima", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_IMA },
247 { "sparcvis3", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
248 { "sparc4", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
249 { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU },
250 { "sparclet", "sparclet", sparclet, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
251 { "sparclite", "sparclite", sparclite, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
252 { "sparc86x", "sparclite", sparc86x, 32, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD },
253 { "v8plus", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS },
254 { "v8plusa", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS },
255 { "v8plusb", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2 },
256 { "v8plusc", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
257 { "v8plusd", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
258 { "v8pluse", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
259 { "v8plusv", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_V8PLUS|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
260 { "v9", "v9", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
261 { "v9a", "v9a", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS },
262 { "v9b", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2 },
263 { "v9c", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT },
264 { "v9d", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC },
265 { "v9e", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
266 { "v9v", "v9b", v9, 0, 1, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC|HWCAP_VIS|HWCAP_VIS2|HWCAP_ASI_BLK_INIT|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_RANDOM|HWCAP_TRANS|HWCAP_FJFMAU|HWCAP_IMA|HWCAP_ASI_CACHE_SPARING|HWCAP_AES|HWCAP_DES|HWCAP_KASUMI|HWCAP_CAMELLIA|HWCAP_MD5|HWCAP_SHA1|HWCAP_SHA256|HWCAP_SHA512|HWCAP_MPMUL|HWCAP_MONT|HWCAP_CRC32C|HWCAP_CBCOND|HWCAP_PAUSE },
267 /* This exists to allow configure.in/Makefile.in to pass one
268 value to specify both the default machine and default word size. */
269 { "v9-64", "v9", v9, 64, 0, HWCAP_MUL32|HWCAP_DIV32|HWCAP_FSMULD|HWCAP_POPC },
270 { NULL, NULL, v8, 0, 0, 0 }
271 };
272
273 /* Variant of default_arch */
274 static enum sparc_arch_types default_arch_type;
275
276 static struct sparc_arch *
277 lookup_arch (char *name)
278 {
279 struct sparc_arch *sa;
280
281 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++)
282 if (strcmp (sa->name, name) == 0)
283 break;
284 if (sa->name == NULL)
285 return NULL;
286 return sa;
287 }
288
289 /* Initialize the default opcode arch and word size from the default
290 architecture name. */
291
292 static void
293 init_default_arch (void)
294 {
295 struct sparc_arch *sa = lookup_arch (default_arch);
296
297 if (sa == NULL
298 || sa->default_arch_size == 0)
299 as_fatal (_("Invalid default architecture, broken assembler."));
300
301 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch);
302 if (max_architecture == SPARC_OPCODE_ARCH_BAD)
303 as_fatal (_("Bad opcode table, broken assembler."));
304 default_arch_size = sparc_arch_size = sa->default_arch_size;
305 default_init_p = 1;
306 default_arch_type = sa->arch_type;
307 }
308
309 /* Called by TARGET_FORMAT. */
310
311 const char *
312 sparc_target_format (void)
313 {
314 /* We don't get a chance to initialize anything before we're called,
315 so handle that now. */
316 if (! default_init_p)
317 init_default_arch ();
318
319 #ifdef OBJ_AOUT
320 #ifdef TE_NetBSD
321 return "a.out-sparc-netbsd";
322 #else
323 #ifdef TE_SPARCAOUT
324 if (target_big_endian)
325 return "a.out-sunos-big";
326 else if (default_arch_type == sparc86x && target_little_endian_data)
327 return "a.out-sunos-big";
328 else
329 return "a.out-sparc-little";
330 #else
331 return "a.out-sunos-big";
332 #endif
333 #endif
334 #endif
335
336 #ifdef OBJ_BOUT
337 return "b.out.big";
338 #endif
339
340 #ifdef OBJ_COFF
341 #ifdef TE_LYNX
342 return "coff-sparc-lynx";
343 #else
344 return "coff-sparc";
345 #endif
346 #endif
347
348 #ifdef TE_VXWORKS
349 return "elf32-sparc-vxworks";
350 #endif
351
352 #ifdef OBJ_ELF
353 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT;
354 #endif
355
356 abort ();
357 }
358 \f
359 /* md_parse_option
360 * Invocation line includes a switch not recognized by the base assembler.
361 * See if it's a processor-specific option. These are:
362 *
363 * -bump
364 * Warn on architecture bumps. See also -A.
365 *
366 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
367 * Standard 32 bit architectures.
368 * -Av9, -Av9a, -Av9b
369 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
370 * This used to only mean 64 bits, but properly specifying it
371 * complicated gcc's ASM_SPECs, so now opcode selection is
372 * specified orthogonally to word size (except when specifying
373 * the default, but that is an internal implementation detail).
374 * -Av8plus, -Av8plusa, -Av8plusb
375 * Same as -Av9{,a,b}.
376 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
377 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
378 * assembler.
379 * -xarch=v9, -xarch=v9a, -xarch=v9b
380 * Same as -Av9{,a,b} -64, for compatibility with Sun's
381 * assembler.
382 *
383 * Select the architecture and possibly the file format.
384 * Instructions or features not supported by the selected
385 * architecture cause fatal errors.
386 *
387 * The default is to start at v6, and bump the architecture up
388 * whenever an instruction is seen at a higher level. In 32 bit
389 * environments, v9 is not bumped up to, the user must pass
390 * -Av8plus{,a,b}.
391 *
392 * If -bump is specified, a warning is printing when bumping to
393 * higher levels.
394 *
395 * If an architecture is specified, all instructions must match
396 * that architecture. Any higher level instructions are flagged
397 * as errors. Note that in the 32 bit environment specifying
398 * -Av8plus does not automatically create a v8plus object file, a
399 * v9 insn must be seen.
400 *
401 * If both an architecture and -bump are specified, the
402 * architecture starts at the specified level, but bumps are
403 * warnings. Note that we can't set `current_architecture' to
404 * the requested level in this case: in the 32 bit environment,
405 * we still must avoid creating v8plus object files unless v9
406 * insns are seen.
407 *
408 * Note:
409 * Bumping between incompatible architectures is always an
410 * error. For example, from sparclite to v9.
411 */
412
413 #ifdef OBJ_ELF
414 const char *md_shortopts = "A:K:VQ:sq";
415 #else
416 #ifdef OBJ_AOUT
417 const char *md_shortopts = "A:k";
418 #else
419 const char *md_shortopts = "A:";
420 #endif
421 #endif
422 struct option md_longopts[] = {
423 #define OPTION_BUMP (OPTION_MD_BASE)
424 {"bump", no_argument, NULL, OPTION_BUMP},
425 #define OPTION_SPARC (OPTION_MD_BASE + 1)
426 {"sparc", no_argument, NULL, OPTION_SPARC},
427 #define OPTION_XARCH (OPTION_MD_BASE + 2)
428 {"xarch", required_argument, NULL, OPTION_XARCH},
429 #ifdef OBJ_ELF
430 #define OPTION_32 (OPTION_MD_BASE + 3)
431 {"32", no_argument, NULL, OPTION_32},
432 #define OPTION_64 (OPTION_MD_BASE + 4)
433 {"64", no_argument, NULL, OPTION_64},
434 #define OPTION_TSO (OPTION_MD_BASE + 5)
435 {"TSO", no_argument, NULL, OPTION_TSO},
436 #define OPTION_PSO (OPTION_MD_BASE + 6)
437 {"PSO", no_argument, NULL, OPTION_PSO},
438 #define OPTION_RMO (OPTION_MD_BASE + 7)
439 {"RMO", no_argument, NULL, OPTION_RMO},
440 #endif
441 #ifdef SPARC_BIENDIAN
442 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
443 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN},
444 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
445 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN},
446 #endif
447 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
448 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA},
449 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
450 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA},
451 #ifdef OBJ_ELF
452 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
453 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS},
454 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
455 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS},
456 #endif
457 #define OPTION_RELAX (OPTION_MD_BASE + 14)
458 {"relax", no_argument, NULL, OPTION_RELAX},
459 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
460 {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
461 {NULL, no_argument, NULL, 0}
462 };
463
464 size_t md_longopts_size = sizeof (md_longopts);
465
466 int
467 md_parse_option (int c, char *arg)
468 {
469 /* We don't get a chance to initialize anything before we're called,
470 so handle that now. */
471 if (! default_init_p)
472 init_default_arch ();
473
474 switch (c)
475 {
476 case OPTION_BUMP:
477 warn_on_bump = 1;
478 warn_after_architecture = SPARC_OPCODE_ARCH_V6;
479 break;
480
481 case OPTION_XARCH:
482 #ifdef OBJ_ELF
483 if (strncmp (arg, "v9", 2) != 0)
484 md_parse_option (OPTION_32, NULL);
485 else
486 md_parse_option (OPTION_64, NULL);
487 #endif
488 /* Fall through. */
489
490 case 'A':
491 {
492 struct sparc_arch *sa;
493 enum sparc_opcode_arch_val opcode_arch;
494
495 sa = lookup_arch (arg);
496 if (sa == NULL
497 || ! sa->user_option_p)
498 {
499 if (c == OPTION_XARCH)
500 as_bad (_("invalid architecture -xarch=%s"), arg);
501 else
502 as_bad (_("invalid architecture -A%s"), arg);
503 return 0;
504 }
505
506 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch);
507 if (opcode_arch == SPARC_OPCODE_ARCH_BAD)
508 as_fatal (_("Bad opcode table, broken assembler."));
509
510 if (!architecture_requested
511 || opcode_arch > max_architecture)
512 max_architecture = opcode_arch;
513 hwcap_allowed |= sa->hwcap_allowed;
514 architecture_requested = 1;
515 }
516 break;
517
518 case OPTION_SPARC:
519 /* Ignore -sparc, used by SunOS make default .s.o rule. */
520 break;
521
522 case OPTION_ENFORCE_ALIGNED_DATA:
523 enforce_aligned_data = 1;
524 break;
525
526 #ifdef SPARC_BIENDIAN
527 case OPTION_LITTLE_ENDIAN:
528 target_big_endian = 0;
529 if (default_arch_type != sparclet)
530 as_fatal ("This target does not support -EL");
531 break;
532 case OPTION_LITTLE_ENDIAN_DATA:
533 target_little_endian_data = 1;
534 target_big_endian = 0;
535 if (default_arch_type != sparc86x
536 && default_arch_type != v9)
537 as_fatal ("This target does not support --little-endian-data");
538 break;
539 case OPTION_BIG_ENDIAN:
540 target_big_endian = 1;
541 break;
542 #endif
543
544 #ifdef OBJ_AOUT
545 case 'k':
546 sparc_pic_code = 1;
547 break;
548 #endif
549
550 #ifdef OBJ_ELF
551 case OPTION_32:
552 case OPTION_64:
553 {
554 const char **list, **l;
555
556 sparc_arch_size = c == OPTION_32 ? 32 : 64;
557 list = bfd_target_list ();
558 for (l = list; *l != NULL; l++)
559 {
560 if (sparc_arch_size == 32)
561 {
562 if (CONST_STRNEQ (*l, "elf32-sparc"))
563 break;
564 }
565 else
566 {
567 if (CONST_STRNEQ (*l, "elf64-sparc"))
568 break;
569 }
570 }
571 if (*l == NULL)
572 as_fatal (_("No compiled in support for %d bit object file format"),
573 sparc_arch_size);
574 free (list);
575
576 if (sparc_arch_size == 64
577 && max_architecture < SPARC_OPCODE_ARCH_V9)
578 max_architecture = SPARC_OPCODE_ARCH_V9;
579 }
580 break;
581
582 case OPTION_TSO:
583 sparc_memory_model = MM_TSO;
584 break;
585
586 case OPTION_PSO:
587 sparc_memory_model = MM_PSO;
588 break;
589
590 case OPTION_RMO:
591 sparc_memory_model = MM_RMO;
592 break;
593
594 case 'V':
595 print_version_id ();
596 break;
597
598 case 'Q':
599 /* Qy - do emit .comment
600 Qn - do not emit .comment. */
601 break;
602
603 case 's':
604 /* Use .stab instead of .stab.excl. */
605 break;
606
607 case 'q':
608 /* quick -- Native assembler does fewer checks. */
609 break;
610
611 case 'K':
612 if (strcmp (arg, "PIC") != 0)
613 as_warn (_("Unrecognized option following -K"));
614 else
615 sparc_pic_code = 1;
616 break;
617
618 case OPTION_NO_UNDECLARED_REGS:
619 no_undeclared_regs = 1;
620 break;
621
622 case OPTION_UNDECLARED_REGS:
623 no_undeclared_regs = 0;
624 break;
625 #endif
626
627 case OPTION_RELAX:
628 sparc_relax = 1;
629 break;
630
631 case OPTION_NO_RELAX:
632 sparc_relax = 0;
633 break;
634
635 default:
636 return 0;
637 }
638
639 return 1;
640 }
641
642 void
643 md_show_usage (FILE *stream)
644 {
645 const struct sparc_arch *arch;
646 int column;
647
648 /* We don't get a chance to initialize anything before we're called,
649 so handle that now. */
650 if (! default_init_p)
651 init_default_arch ();
652
653 fprintf (stream, _("SPARC options:\n"));
654 column = 0;
655 for (arch = &sparc_arch_table[0]; arch->name; arch++)
656 {
657 if (!arch->user_option_p)
658 continue;
659 if (arch != &sparc_arch_table[0])
660 fprintf (stream, " | ");
661 if (column + strlen (arch->name) > 70)
662 {
663 column = 0;
664 fputc ('\n', stream);
665 }
666 column += 5 + 2 + strlen (arch->name);
667 fprintf (stream, "-A%s", arch->name);
668 }
669 for (arch = &sparc_arch_table[0]; arch->name; arch++)
670 {
671 if (!arch->user_option_p)
672 continue;
673 fprintf (stream, " | ");
674 if (column + strlen (arch->name) > 65)
675 {
676 column = 0;
677 fputc ('\n', stream);
678 }
679 column += 5 + 7 + strlen (arch->name);
680 fprintf (stream, "-xarch=%s", arch->name);
681 }
682 fprintf (stream, _("\n\
683 specify variant of SPARC architecture\n\
684 -bump warn when assembler switches architectures\n\
685 -sparc ignored\n\
686 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
687 -relax relax jumps and branches (default)\n\
688 -no-relax avoid changing any jumps and branches\n"));
689 #ifdef OBJ_AOUT
690 fprintf (stream, _("\
691 -k generate PIC\n"));
692 #endif
693 #ifdef OBJ_ELF
694 fprintf (stream, _("\
695 -32 create 32 bit object file\n\
696 -64 create 64 bit object file\n"));
697 fprintf (stream, _("\
698 [default is %d]\n"), default_arch_size);
699 fprintf (stream, _("\
700 -TSO use Total Store Ordering\n\
701 -PSO use Partial Store Ordering\n\
702 -RMO use Relaxed Memory Ordering\n"));
703 fprintf (stream, _("\
704 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO");
705 fprintf (stream, _("\
706 -KPIC generate PIC\n\
707 -V print assembler version number\n\
708 -undeclared-regs ignore application global register usage without\n\
709 appropriate .register directive (default)\n\
710 -no-undeclared-regs force error on application global register usage\n\
711 without appropriate .register directive\n\
712 -q ignored\n\
713 -Qy, -Qn ignored\n\
714 -s ignored\n"));
715 #endif
716 #ifdef SPARC_BIENDIAN
717 fprintf (stream, _("\
718 -EL generate code for a little endian machine\n\
719 -EB generate code for a big endian machine\n\
720 --little-endian-data generate code for a machine having big endian\n\
721 instructions and little endian data.\n"));
722 #endif
723 }
724 \f
725 /* Native operand size opcode translation. */
726 struct
727 {
728 char *name;
729 char *name32;
730 char *name64;
731 } native_op_table[] =
732 {
733 {"ldn", "ld", "ldx"},
734 {"ldna", "lda", "ldxa"},
735 {"stn", "st", "stx"},
736 {"stna", "sta", "stxa"},
737 {"slln", "sll", "sllx"},
738 {"srln", "srl", "srlx"},
739 {"sran", "sra", "srax"},
740 {"casn", "cas", "casx"},
741 {"casna", "casa", "casxa"},
742 {"clrn", "clr", "clrx"},
743 {NULL, NULL, NULL},
744 };
745 \f
746 /* sparc64 privileged and hyperprivileged registers. */
747
748 struct priv_reg_entry
749 {
750 char *name;
751 int regnum;
752 };
753
754 struct priv_reg_entry priv_reg_table[] =
755 {
756 {"tpc", 0},
757 {"tnpc", 1},
758 {"tstate", 2},
759 {"tt", 3},
760 {"tick", 4},
761 {"tba", 5},
762 {"pstate", 6},
763 {"tl", 7},
764 {"pil", 8},
765 {"cwp", 9},
766 {"cansave", 10},
767 {"canrestore", 11},
768 {"cleanwin", 12},
769 {"otherwin", 13},
770 {"wstate", 14},
771 {"fq", 15},
772 {"gl", 16},
773 {"ver", 31},
774 {"", -1}, /* End marker. */
775 };
776
777 struct priv_reg_entry hpriv_reg_table[] =
778 {
779 {"hpstate", 0},
780 {"htstate", 1},
781 {"hintp", 3},
782 {"htba", 5},
783 {"hver", 6},
784 {"hstick_cmpr", 31},
785 {"", -1}, /* End marker. */
786 };
787
788 /* v9a specific asrs. This table is ordered by initial
789 letter, in reverse. */
790
791 struct priv_reg_entry v9a_asr_table[] =
792 {
793 {"tick_cmpr", 23},
794 {"sys_tick_cmpr", 25},
795 {"sys_tick", 24},
796 {"stick_cmpr", 25},
797 {"stick", 24},
798 {"softint_clear", 21},
799 {"softint_set", 20},
800 {"softint", 22},
801 {"set_softint", 20},
802 {"pause", 27},
803 {"pic", 17},
804 {"pcr", 16},
805 {"gsr", 19},
806 {"dcr", 18},
807 {"cps", 28},
808 {"cfr", 26},
809 {"clear_softint", 21},
810 {"", -1}, /* End marker. */
811 };
812
813 static int
814 cmp_reg_entry (const void *parg, const void *qarg)
815 {
816 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg;
817 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg;
818
819 return strcmp (q->name, p->name);
820 }
821 \f
822 /* This function is called once, at assembler startup time. It should
823 set up all the tables, etc. that the MD part of the assembler will
824 need. */
825
826 void
827 md_begin (void)
828 {
829 register const char *retval = NULL;
830 int lose = 0;
831 register unsigned int i = 0;
832
833 /* We don't get a chance to initialize anything before md_parse_option
834 is called, and it may not be called, so handle default initialization
835 now if not already done. */
836 if (! default_init_p)
837 init_default_arch ();
838
839 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4;
840 op_hash = hash_new ();
841
842 while (i < (unsigned int) sparc_num_opcodes)
843 {
844 const char *name = sparc_opcodes[i].name;
845 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]);
846 if (retval != NULL)
847 {
848 as_bad (_("Internal error: can't hash `%s': %s\n"),
849 sparc_opcodes[i].name, retval);
850 lose = 1;
851 }
852 do
853 {
854 if (sparc_opcodes[i].match & sparc_opcodes[i].lose)
855 {
856 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
857 sparc_opcodes[i].name, sparc_opcodes[i].args);
858 lose = 1;
859 }
860 ++i;
861 }
862 while (i < (unsigned int) sparc_num_opcodes
863 && !strcmp (sparc_opcodes[i].name, name));
864 }
865
866 for (i = 0; native_op_table[i].name; i++)
867 {
868 const struct sparc_opcode *insn;
869 char *name = ((sparc_arch_size == 32)
870 ? native_op_table[i].name32
871 : native_op_table[i].name64);
872 insn = (struct sparc_opcode *) hash_find (op_hash, name);
873 if (insn == NULL)
874 {
875 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
876 name, native_op_table[i].name);
877 lose = 1;
878 }
879 else
880 {
881 retval = hash_insert (op_hash, native_op_table[i].name,
882 (void *) insn);
883 if (retval != NULL)
884 {
885 as_bad (_("Internal error: can't hash `%s': %s\n"),
886 sparc_opcodes[i].name, retval);
887 lose = 1;
888 }
889 }
890 }
891
892 if (lose)
893 as_fatal (_("Broken assembler. No assembly attempted."));
894
895 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]),
896 sizeof (priv_reg_table[0]), cmp_reg_entry);
897
898 /* If -bump, record the architecture level at which we start issuing
899 warnings. The behaviour is different depending upon whether an
900 architecture was explicitly specified. If it wasn't, we issue warnings
901 for all upwards bumps. If it was, we don't start issuing warnings until
902 we need to bump beyond the requested architecture or when we bump between
903 conflicting architectures. */
904
905 if (warn_on_bump
906 && architecture_requested)
907 {
908 /* `max_architecture' records the requested architecture.
909 Issue warnings if we go above it. */
910 warn_after_architecture = max_architecture;
911
912 /* Find the highest architecture level that doesn't conflict with
913 the requested one. */
914 for (max_architecture = SPARC_OPCODE_ARCH_MAX;
915 max_architecture > warn_after_architecture;
916 --max_architecture)
917 if (! SPARC_OPCODE_CONFLICT_P (max_architecture,
918 warn_after_architecture))
919 break;
920 }
921 }
922
923 /* Called after all assembly has been done. */
924
925 void
926 sparc_md_end (void)
927 {
928 unsigned long mach = bfd_mach_sparc;
929
930 if (sparc_arch_size == 64)
931 switch (current_architecture)
932 {
933 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break;
934 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break;
935 default: mach = bfd_mach_sparc_v9; break;
936 }
937 else
938 switch (current_architecture)
939 {
940 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break;
941 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break;
942 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break;
943 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break;
944 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
945 be but for now it is (since that's the way it's always been
946 treated). */
947 default: break;
948 }
949 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach);
950
951 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
952 if (hwcap_seen)
953 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcap_seen);
954 #endif
955 }
956 \f
957 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
958
959 static inline int
960 in_signed_range (bfd_signed_vma val, bfd_signed_vma max)
961 {
962 if (max <= 0)
963 abort ();
964 /* Sign-extend the value from the architecture word size, so that
965 0xffffffff is always considered -1 on sparc32. */
966 if (sparc_arch_size == 32)
967 {
968 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31;
969 val = ((val & U0xffffffff) ^ sign) - sign;
970 }
971 if (val > max)
972 return 0;
973 if (val < ~max)
974 return 0;
975 return 1;
976 }
977
978 /* Return non-zero if VAL is in the range 0 to MAX. */
979
980 static inline int
981 in_unsigned_range (bfd_vma val, bfd_vma max)
982 {
983 if (val > max)
984 return 0;
985 return 1;
986 }
987
988 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
989 (e.g. -15 to +31). */
990
991 static inline int
992 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max)
993 {
994 if (max <= 0)
995 abort ();
996 if (val > max)
997 return 0;
998 if (val < ~(max >> 1))
999 return 0;
1000 return 1;
1001 }
1002
1003 static int
1004 sparc_ffs (unsigned int mask)
1005 {
1006 int i;
1007
1008 if (mask == 0)
1009 return -1;
1010
1011 for (i = 0; (mask & 1) == 0; ++i)
1012 mask >>= 1;
1013 return i;
1014 }
1015
1016 /* Implement big shift right. */
1017 static bfd_vma
1018 BSR (bfd_vma val, int amount)
1019 {
1020 if (sizeof (bfd_vma) <= 4 && amount >= 32)
1021 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1022 return val >> amount;
1023 }
1024 \f
1025 /* For communication between sparc_ip and get_expression. */
1026 static char *expr_end;
1027
1028 /* Values for `special_case'.
1029 Instructions that require wierd handling because they're longer than
1030 4 bytes. */
1031 #define SPECIAL_CASE_NONE 0
1032 #define SPECIAL_CASE_SET 1
1033 #define SPECIAL_CASE_SETSW 2
1034 #define SPECIAL_CASE_SETX 3
1035 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1036 #define SPECIAL_CASE_FDIV 4
1037
1038 /* Bit masks of various insns. */
1039 #define NOP_INSN 0x01000000
1040 #define OR_INSN 0x80100000
1041 #define XOR_INSN 0x80180000
1042 #define FMOVS_INSN 0x81A00020
1043 #define SETHI_INSN 0x01000000
1044 #define SLLX_INSN 0x81281000
1045 #define SRA_INSN 0x81380000
1046
1047 /* The last instruction to be assembled. */
1048 static const struct sparc_opcode *last_insn;
1049 /* The assembled opcode of `last_insn'. */
1050 static unsigned long last_opcode;
1051 \f
1052 /* Handle the set and setuw synthetic instructions. */
1053
1054 static void
1055 synthetize_setuw (const struct sparc_opcode *insn)
1056 {
1057 int need_hi22_p = 0;
1058 int rd = (the_insn.opcode & RD (~0)) >> 25;
1059
1060 if (the_insn.exp.X_op == O_constant)
1061 {
1062 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1063 {
1064 if (sizeof (offsetT) > 4
1065 && (the_insn.exp.X_add_number < 0
1066 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1067 as_warn (_("set: number not in 0..4294967295 range"));
1068 }
1069 else
1070 {
1071 if (sizeof (offsetT) > 4
1072 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1073 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1074 as_warn (_("set: number not in -2147483648..4294967295 range"));
1075 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number;
1076 }
1077 }
1078
1079 /* See if operand is absolute and small; skip sethi if so. */
1080 if (the_insn.exp.X_op != O_constant
1081 || the_insn.exp.X_add_number >= (1 << 12)
1082 || the_insn.exp.X_add_number < -(1 << 12))
1083 {
1084 the_insn.opcode = (SETHI_INSN | RD (rd)
1085 | ((the_insn.exp.X_add_number >> 10)
1086 & (the_insn.exp.X_op == O_constant
1087 ? 0x3fffff : 0)));
1088 the_insn.reloc = (the_insn.exp.X_op != O_constant
1089 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
1090 output_insn (insn, &the_insn);
1091 need_hi22_p = 1;
1092 }
1093
1094 /* See if operand has no low-order bits; skip OR if so. */
1095 if (the_insn.exp.X_op != O_constant
1096 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0)
1097 || ! need_hi22_p)
1098 {
1099 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
1100 | RD (rd) | IMMED
1101 | (the_insn.exp.X_add_number
1102 & (the_insn.exp.X_op != O_constant
1103 ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
1104 the_insn.reloc = (the_insn.exp.X_op != O_constant
1105 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1106 output_insn (insn, &the_insn);
1107 }
1108 }
1109
1110 /* Handle the setsw synthetic instruction. */
1111
1112 static void
1113 synthetize_setsw (const struct sparc_opcode *insn)
1114 {
1115 int low32, rd, opc;
1116
1117 rd = (the_insn.opcode & RD (~0)) >> 25;
1118
1119 if (the_insn.exp.X_op != O_constant)
1120 {
1121 synthetize_setuw (insn);
1122
1123 /* Need to sign extend it. */
1124 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd));
1125 the_insn.reloc = BFD_RELOC_NONE;
1126 output_insn (insn, &the_insn);
1127 return;
1128 }
1129
1130 if (sizeof (offsetT) > 4
1131 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000
1132 || the_insn.exp.X_add_number > (offsetT) U0xffffffff))
1133 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1134
1135 low32 = the_insn.exp.X_add_number;
1136
1137 if (low32 >= 0)
1138 {
1139 synthetize_setuw (insn);
1140 return;
1141 }
1142
1143 opc = OR_INSN;
1144
1145 the_insn.reloc = BFD_RELOC_NONE;
1146 /* See if operand is absolute and small; skip sethi if so. */
1147 if (low32 < -(1 << 12))
1148 {
1149 the_insn.opcode = (SETHI_INSN | RD (rd)
1150 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff));
1151 output_insn (insn, &the_insn);
1152 low32 = 0x1c00 | (low32 & 0x3ff);
1153 opc = RS1 (rd) | XOR_INSN;
1154 }
1155
1156 the_insn.opcode = (opc | RD (rd) | IMMED
1157 | (low32 & 0x1fff));
1158 output_insn (insn, &the_insn);
1159 }
1160
1161 /* Handle the setsw synthetic instruction. */
1162
1163 static void
1164 synthetize_setx (const struct sparc_opcode *insn)
1165 {
1166 int upper32, lower32;
1167 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14;
1168 int dstreg = (the_insn.opcode & RD (~0)) >> 25;
1169 int upper_dstreg;
1170 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0;
1171 int need_xor10_p = 0;
1172
1173 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1174 lower32 = SIGNEXT32 (the_insn.exp.X_add_number);
1175 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32));
1176 #undef SIGNEXT32
1177
1178 upper_dstreg = tmpreg;
1179 /* The tmp reg should not be the dst reg. */
1180 if (tmpreg == dstreg)
1181 as_warn (_("setx: temporary register same as destination register"));
1182
1183 /* ??? Obviously there are other optimizations we can do
1184 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1185 doing some of these. Later. If you do change things, try to
1186 change all of this to be table driven as well. */
1187 /* What to output depends on the number if it's constant.
1188 Compute that first, then output what we've decided upon. */
1189 if (the_insn.exp.X_op != O_constant)
1190 {
1191 if (sparc_arch_size == 32)
1192 {
1193 /* When arch size is 32, we want setx to be equivalent
1194 to setuw for anything but constants. */
1195 the_insn.exp.X_add_number &= 0xffffffff;
1196 synthetize_setuw (insn);
1197 return;
1198 }
1199 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
1200 lower32 = 0;
1201 upper32 = 0;
1202 }
1203 else
1204 {
1205 /* Reset X_add_number, we've extracted it as upper32/lower32.
1206 Otherwise fixup_segment will complain about not being able to
1207 write an 8 byte number in a 4 byte field. */
1208 the_insn.exp.X_add_number = 0;
1209
1210 /* Only need hh22 if `or' insn can't handle constant. */
1211 if (upper32 < -(1 << 12) || upper32 >= (1 << 12))
1212 need_hh22_p = 1;
1213
1214 /* Does bottom part (after sethi) have bits? */
1215 if ((need_hh22_p && (upper32 & 0x3ff) != 0)
1216 /* No hh22, but does upper32 still have bits we can't set
1217 from lower32? */
1218 || (! need_hh22_p && upper32 != 0 && upper32 != -1))
1219 need_hm10_p = 1;
1220
1221 /* If the lower half is all zero, we build the upper half directly
1222 into the dst reg. */
1223 if (lower32 != 0
1224 /* Need lower half if number is zero or 0xffffffff00000000. */
1225 || (! need_hh22_p && ! need_hm10_p))
1226 {
1227 /* No need for sethi if `or' insn can handle constant. */
1228 if (lower32 < -(1 << 12) || lower32 >= (1 << 12)
1229 /* Note that we can't use a negative constant in the `or'
1230 insn unless the upper 32 bits are all ones. */
1231 || (lower32 < 0 && upper32 != -1)
1232 || (lower32 >= 0 && upper32 == -1))
1233 need_hi22_p = 1;
1234
1235 if (need_hi22_p && upper32 == -1)
1236 need_xor10_p = 1;
1237
1238 /* Does bottom part (after sethi) have bits? */
1239 else if ((need_hi22_p && (lower32 & 0x3ff) != 0)
1240 /* No sethi. */
1241 || (! need_hi22_p && (lower32 & 0x1fff) != 0)
1242 /* Need `or' if we didn't set anything else. */
1243 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p))
1244 need_lo10_p = 1;
1245 }
1246 else
1247 /* Output directly to dst reg if lower 32 bits are all zero. */
1248 upper_dstreg = dstreg;
1249 }
1250
1251 if (!upper_dstreg && dstreg)
1252 as_warn (_("setx: illegal temporary register g0"));
1253
1254 if (need_hh22_p)
1255 {
1256 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg)
1257 | ((upper32 >> 10) & 0x3fffff));
1258 the_insn.reloc = (the_insn.exp.X_op != O_constant
1259 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE);
1260 output_insn (insn, &the_insn);
1261 }
1262
1263 if (need_hi22_p)
1264 {
1265 the_insn.opcode = (SETHI_INSN | RD (dstreg)
1266 | (((need_xor10_p ? ~lower32 : lower32)
1267 >> 10) & 0x3fffff));
1268 the_insn.reloc = (the_insn.exp.X_op != O_constant
1269 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
1270 output_insn (insn, &the_insn);
1271 }
1272
1273 if (need_hm10_p)
1274 {
1275 the_insn.opcode = (OR_INSN
1276 | (need_hh22_p ? RS1 (upper_dstreg) : 0)
1277 | RD (upper_dstreg)
1278 | IMMED
1279 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff)));
1280 the_insn.reloc = (the_insn.exp.X_op != O_constant
1281 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE);
1282 output_insn (insn, &the_insn);
1283 }
1284
1285 if (need_lo10_p)
1286 {
1287 /* FIXME: One nice optimization to do here is to OR the low part
1288 with the highpart if hi22 isn't needed and the low part is
1289 positive. */
1290 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0)
1291 | RD (dstreg)
1292 | IMMED
1293 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff)));
1294 the_insn.reloc = (the_insn.exp.X_op != O_constant
1295 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
1296 output_insn (insn, &the_insn);
1297 }
1298
1299 /* If we needed to build the upper part, shift it into place. */
1300 if (need_hh22_p || need_hm10_p)
1301 {
1302 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg)
1303 | IMMED | 32);
1304 the_insn.reloc = BFD_RELOC_NONE;
1305 output_insn (insn, &the_insn);
1306 }
1307
1308 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1309 if (need_xor10_p)
1310 {
1311 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED
1312 | 0x1c00 | (lower32 & 0x3ff));
1313 the_insn.reloc = BFD_RELOC_NONE;
1314 output_insn (insn, &the_insn);
1315 }
1316
1317 /* If we needed to build both upper and lower parts, OR them together. */
1318 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p))
1319 {
1320 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg)
1321 | RD (dstreg));
1322 the_insn.reloc = BFD_RELOC_NONE;
1323 output_insn (insn, &the_insn);
1324 }
1325 }
1326 \f
1327 /* Main entry point to assemble one instruction. */
1328
1329 void
1330 md_assemble (char *str)
1331 {
1332 const struct sparc_opcode *insn;
1333 int special_case;
1334
1335 know (str);
1336 special_case = sparc_ip (str, &insn);
1337 if (insn == NULL)
1338 return;
1339
1340 /* We warn about attempts to put a floating point branch in a delay slot,
1341 unless the delay slot has been annulled. */
1342 if (last_insn != NULL
1343 && (insn->flags & F_FBR) != 0
1344 && (last_insn->flags & F_DELAYED) != 0
1345 /* ??? This test isn't completely accurate. We assume anything with
1346 F_{UNBR,CONDBR,FBR} set is annullable. */
1347 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0
1348 || (last_opcode & ANNUL) == 0))
1349 as_warn (_("FP branch in delay slot"));
1350
1351 /* SPARC before v9 requires a nop instruction between a floating
1352 point instruction and a floating point branch. We insert one
1353 automatically, with a warning. */
1354 if (max_architecture < SPARC_OPCODE_ARCH_V9
1355 && last_insn != NULL
1356 && (insn->flags & F_FBR) != 0
1357 && (last_insn->flags & F_FLOAT) != 0)
1358 {
1359 struct sparc_it nop_insn;
1360
1361 nop_insn.opcode = NOP_INSN;
1362 nop_insn.reloc = BFD_RELOC_NONE;
1363 output_insn (insn, &nop_insn);
1364 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1365 }
1366
1367 switch (special_case)
1368 {
1369 case SPECIAL_CASE_NONE:
1370 /* Normal insn. */
1371 output_insn (insn, &the_insn);
1372 break;
1373
1374 case SPECIAL_CASE_SETSW:
1375 synthetize_setsw (insn);
1376 break;
1377
1378 case SPECIAL_CASE_SET:
1379 synthetize_setuw (insn);
1380 break;
1381
1382 case SPECIAL_CASE_SETX:
1383 synthetize_setx (insn);
1384 break;
1385
1386 case SPECIAL_CASE_FDIV:
1387 {
1388 int rd = (the_insn.opcode >> 25) & 0x1f;
1389
1390 output_insn (insn, &the_insn);
1391
1392 /* According to information leaked from Sun, the "fdiv" instructions
1393 on early SPARC machines would produce incorrect results sometimes.
1394 The workaround is to add an fmovs of the destination register to
1395 itself just after the instruction. This was true on machines
1396 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1397 gas_assert (the_insn.reloc == BFD_RELOC_NONE);
1398 the_insn.opcode = FMOVS_INSN | rd | RD (rd);
1399 output_insn (insn, &the_insn);
1400 return;
1401 }
1402
1403 default:
1404 as_fatal (_("failed special case insn sanity check"));
1405 }
1406 }
1407
1408 static const char *
1409 get_hwcap_name (int mask)
1410 {
1411 if (mask & HWCAP_MUL32)
1412 return "mul32";
1413 if (mask & HWCAP_DIV32)
1414 return "div32";
1415 if (mask & HWCAP_FSMULD)
1416 return "fsmuld";
1417 if (mask & HWCAP_V8PLUS)
1418 return "v8plus";
1419 if (mask & HWCAP_POPC)
1420 return "popc";
1421 if (mask & HWCAP_VIS)
1422 return "vis";
1423 if (mask & HWCAP_VIS2)
1424 return "vis2";
1425 if (mask & HWCAP_ASI_BLK_INIT)
1426 return "ASIBlkInit";
1427 if (mask & HWCAP_FMAF)
1428 return "fmaf";
1429 if (mask & HWCAP_VIS3)
1430 return "vis3";
1431 if (mask & HWCAP_HPC)
1432 return "hpc";
1433 if (mask & HWCAP_RANDOM)
1434 return "random";
1435 if (mask & HWCAP_TRANS)
1436 return "trans";
1437 if (mask & HWCAP_FJFMAU)
1438 return "fjfmau";
1439 if (mask & HWCAP_IMA)
1440 return "ima";
1441 if (mask & HWCAP_ASI_CACHE_SPARING)
1442 return "cspare";
1443 if (mask & HWCAP_AES)
1444 return "aes";
1445 if (mask & HWCAP_DES)
1446 return "des";
1447 if (mask & HWCAP_KASUMI)
1448 return "kasumi";
1449 if (mask & HWCAP_CAMELLIA)
1450 return "camellia";
1451 if (mask & HWCAP_MD5)
1452 return "md5";
1453 if (mask & HWCAP_SHA1)
1454 return "sha1";
1455 if (mask & HWCAP_SHA256)
1456 return "sha256";
1457 if (mask & HWCAP_SHA512)
1458 return "sha512";
1459 if (mask & HWCAP_MPMUL)
1460 return "mpmul";
1461 if (mask & HWCAP_MONT)
1462 return "mont";
1463 if (mask & HWCAP_PAUSE)
1464 return "pause";
1465 if (mask & HWCAP_CBCOND)
1466 return "cbcond";
1467 if (mask & HWCAP_CRC32C)
1468 return "crc32c";
1469 return "UNKNOWN";
1470 }
1471
1472 /* Subroutine of md_assemble to do the actual parsing. */
1473
1474 static int
1475 sparc_ip (char *str, const struct sparc_opcode **pinsn)
1476 {
1477 char *error_message = "";
1478 char *s;
1479 const char *args;
1480 char c;
1481 const struct sparc_opcode *insn;
1482 char *argsStart;
1483 unsigned long opcode;
1484 unsigned int mask = 0;
1485 int match = 0;
1486 int comma = 0;
1487 int v9_arg_p;
1488 int special_case = SPECIAL_CASE_NONE;
1489
1490 s = str;
1491 if (ISLOWER (*s))
1492 {
1493 do
1494 ++s;
1495 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_');
1496 }
1497
1498 switch (*s)
1499 {
1500 case '\0':
1501 break;
1502
1503 case ',':
1504 comma = 1;
1505 /* Fall through. */
1506
1507 case ' ':
1508 *s++ = '\0';
1509 break;
1510
1511 default:
1512 as_bad (_("Unknown opcode: `%s'"), str);
1513 *pinsn = NULL;
1514 return special_case;
1515 }
1516 insn = (struct sparc_opcode *) hash_find (op_hash, str);
1517 *pinsn = insn;
1518 if (insn == NULL)
1519 {
1520 as_bad (_("Unknown opcode: `%s'"), str);
1521 return special_case;
1522 }
1523 if (comma)
1524 {
1525 *--s = ',';
1526 }
1527
1528 argsStart = s;
1529 for (;;)
1530 {
1531 opcode = insn->match;
1532 memset (&the_insn, '\0', sizeof (the_insn));
1533 the_insn.reloc = BFD_RELOC_NONE;
1534 v9_arg_p = 0;
1535
1536 /* Build the opcode, checking as we go to make sure that the
1537 operands match. */
1538 for (args = insn->args;; ++args)
1539 {
1540 switch (*args)
1541 {
1542 case 'K':
1543 {
1544 int kmask = 0;
1545
1546 /* Parse a series of masks. */
1547 if (*s == '#')
1548 {
1549 while (*s == '#')
1550 {
1551 int jmask;
1552
1553 if (! parse_keyword_arg (sparc_encode_membar, &s,
1554 &jmask))
1555 {
1556 error_message = _(": invalid membar mask name");
1557 goto error;
1558 }
1559 kmask |= jmask;
1560 while (*s == ' ')
1561 ++s;
1562 if (*s == '|' || *s == '+')
1563 ++s;
1564 while (*s == ' ')
1565 ++s;
1566 }
1567 }
1568 else
1569 {
1570 if (! parse_const_expr_arg (&s, &kmask))
1571 {
1572 error_message = _(": invalid membar mask expression");
1573 goto error;
1574 }
1575 if (kmask < 0 || kmask > 127)
1576 {
1577 error_message = _(": invalid membar mask number");
1578 goto error;
1579 }
1580 }
1581
1582 opcode |= MEMBAR (kmask);
1583 continue;
1584 }
1585
1586 case '3':
1587 {
1588 int smask = 0;
1589
1590 if (! parse_const_expr_arg (&s, &smask))
1591 {
1592 error_message = _(": invalid siam mode expression");
1593 goto error;
1594 }
1595 if (smask < 0 || smask > 7)
1596 {
1597 error_message = _(": invalid siam mode number");
1598 goto error;
1599 }
1600 opcode |= smask;
1601 continue;
1602 }
1603
1604 case '*':
1605 {
1606 int fcn = 0;
1607
1608 /* Parse a prefetch function. */
1609 if (*s == '#')
1610 {
1611 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn))
1612 {
1613 error_message = _(": invalid prefetch function name");
1614 goto error;
1615 }
1616 }
1617 else
1618 {
1619 if (! parse_const_expr_arg (&s, &fcn))
1620 {
1621 error_message = _(": invalid prefetch function expression");
1622 goto error;
1623 }
1624 if (fcn < 0 || fcn > 31)
1625 {
1626 error_message = _(": invalid prefetch function number");
1627 goto error;
1628 }
1629 }
1630 opcode |= RD (fcn);
1631 continue;
1632 }
1633
1634 case '!':
1635 case '?':
1636 /* Parse a sparc64 privileged register. */
1637 if (*s == '%')
1638 {
1639 struct priv_reg_entry *p = priv_reg_table;
1640 unsigned int len = 9999999; /* Init to make gcc happy. */
1641
1642 s += 1;
1643 while (p->name[0] > s[0])
1644 p++;
1645 while (p->name[0] == s[0])
1646 {
1647 len = strlen (p->name);
1648 if (strncmp (p->name, s, len) == 0)
1649 break;
1650 p++;
1651 }
1652 if (p->name[0] != s[0])
1653 {
1654 error_message = _(": unrecognizable privileged register");
1655 goto error;
1656 }
1657 if (*args == '?')
1658 opcode |= (p->regnum << 14);
1659 else
1660 opcode |= (p->regnum << 25);
1661 s += len;
1662 continue;
1663 }
1664 else
1665 {
1666 error_message = _(": unrecognizable privileged register");
1667 goto error;
1668 }
1669
1670 case '$':
1671 case '%':
1672 /* Parse a sparc64 hyperprivileged register. */
1673 if (*s == '%')
1674 {
1675 struct priv_reg_entry *p = hpriv_reg_table;
1676 unsigned int len = 9999999; /* Init to make gcc happy. */
1677
1678 s += 1;
1679 while (p->name[0] > s[0])
1680 p++;
1681 while (p->name[0] == s[0])
1682 {
1683 len = strlen (p->name);
1684 if (strncmp (p->name, s, len) == 0)
1685 break;
1686 p++;
1687 }
1688 if (p->name[0] != s[0])
1689 {
1690 error_message = _(": unrecognizable hyperprivileged register");
1691 goto error;
1692 }
1693 if (*args == '$')
1694 opcode |= (p->regnum << 14);
1695 else
1696 opcode |= (p->regnum << 25);
1697 s += len;
1698 continue;
1699 }
1700 else
1701 {
1702 error_message = _(": unrecognizable hyperprivileged register");
1703 goto error;
1704 }
1705
1706 case '_':
1707 case '/':
1708 /* Parse a v9a/v9b ancillary state register. */
1709 if (*s == '%')
1710 {
1711 struct priv_reg_entry *p = v9a_asr_table;
1712 unsigned int len = 9999999; /* Init to make gcc happy. */
1713
1714 s += 1;
1715 while (p->name[0] > s[0])
1716 p++;
1717 while (p->name[0] == s[0])
1718 {
1719 len = strlen (p->name);
1720 if (strncmp (p->name, s, len) == 0)
1721 break;
1722 p++;
1723 }
1724 if (p->name[0] != s[0])
1725 {
1726 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1727 goto error;
1728 }
1729 if (*args == '/' && (p->regnum == 20 || p->regnum == 21))
1730 {
1731 error_message = _(": rd on write only ancillary state register");
1732 goto error;
1733 }
1734 if (p->regnum >= 24
1735 && (insn->architecture
1736 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)))
1737 {
1738 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1739 error_message = _(": unrecognizable v9a ancillary state register");
1740 goto error;
1741 }
1742 if (*args == '/')
1743 opcode |= (p->regnum << 14);
1744 else
1745 opcode |= (p->regnum << 25);
1746 s += len;
1747 continue;
1748 }
1749 else
1750 {
1751 error_message = _(": unrecognizable v9a or v9b ancillary state register");
1752 goto error;
1753 }
1754
1755 case 'M':
1756 case 'm':
1757 if (strncmp (s, "%asr", 4) == 0)
1758 {
1759 s += 4;
1760
1761 if (ISDIGIT (*s))
1762 {
1763 long num = 0;
1764
1765 while (ISDIGIT (*s))
1766 {
1767 num = num * 10 + *s - '0';
1768 ++s;
1769 }
1770
1771 if (current_architecture >= SPARC_OPCODE_ARCH_V9)
1772 {
1773 if (num < 16 || 31 < num)
1774 {
1775 error_message = _(": asr number must be between 16 and 31");
1776 goto error;
1777 }
1778 }
1779 else
1780 {
1781 if (num < 0 || 31 < num)
1782 {
1783 error_message = _(": asr number must be between 0 and 31");
1784 goto error;
1785 }
1786 }
1787
1788 opcode |= (*args == 'M' ? RS1 (num) : RD (num));
1789 continue;
1790 }
1791 else
1792 {
1793 error_message = _(": expecting %asrN");
1794 goto error;
1795 }
1796 } /* if %asr */
1797 break;
1798
1799 case 'I':
1800 the_insn.reloc = BFD_RELOC_SPARC_11;
1801 goto immediate;
1802
1803 case 'j':
1804 the_insn.reloc = BFD_RELOC_SPARC_10;
1805 goto immediate;
1806
1807 case ')':
1808 if (*s == ' ')
1809 s++;
1810 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2]))
1811 || ISDIGIT (*s))
1812 {
1813 long num = 0;
1814
1815 if (s[0] == '0' && s[1] == 'x')
1816 {
1817 s += 2;
1818 while (ISXDIGIT (*s))
1819 {
1820 num <<= 4;
1821 num |= hex_value (*s);
1822 ++s;
1823 }
1824 }
1825 else
1826 {
1827 while (ISDIGIT (*s))
1828 {
1829 num = num * 10 + *s - '0';
1830 ++s;
1831 }
1832 }
1833 if (num < 0 || num > 31)
1834 {
1835 error_message = _(": crypto immediate must be between 0 and 31");
1836 goto error;
1837 }
1838
1839 opcode |= RS3 (num);
1840 continue;
1841 }
1842 else
1843 {
1844 error_message = _(": expecting crypto immediate");
1845 goto error;
1846 }
1847
1848 case 'X':
1849 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1850 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1851 the_insn.reloc = BFD_RELOC_SPARC_5;
1852 else
1853 the_insn.reloc = BFD_RELOC_SPARC13;
1854 /* These fields are unsigned, but for upward compatibility,
1855 allow negative values as well. */
1856 goto immediate;
1857
1858 case 'Y':
1859 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1860 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
1861 the_insn.reloc = BFD_RELOC_SPARC_6;
1862 else
1863 the_insn.reloc = BFD_RELOC_SPARC13;
1864 /* These fields are unsigned, but for upward compatibility,
1865 allow negative values as well. */
1866 goto immediate;
1867
1868 case 'k':
1869 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16;
1870 the_insn.pcrel = 1;
1871 goto immediate;
1872
1873 case '=':
1874 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10;
1875 the_insn.pcrel = 1;
1876 goto immediate;
1877
1878 case 'G':
1879 the_insn.reloc = BFD_RELOC_SPARC_WDISP19;
1880 the_insn.pcrel = 1;
1881 goto immediate;
1882
1883 case 'N':
1884 if (*s == 'p' && s[1] == 'n')
1885 {
1886 s += 2;
1887 continue;
1888 }
1889 break;
1890
1891 case 'T':
1892 if (*s == 'p' && s[1] == 't')
1893 {
1894 s += 2;
1895 continue;
1896 }
1897 break;
1898
1899 case 'z':
1900 if (*s == ' ')
1901 {
1902 ++s;
1903 }
1904 if (strncmp (s, "%icc", 4) == 0)
1905 {
1906 s += 4;
1907 continue;
1908 }
1909 break;
1910
1911 case 'Z':
1912 if (*s == ' ')
1913 {
1914 ++s;
1915 }
1916 if (strncmp (s, "%xcc", 4) == 0)
1917 {
1918 s += 4;
1919 continue;
1920 }
1921 break;
1922
1923 case '6':
1924 if (*s == ' ')
1925 {
1926 ++s;
1927 }
1928 if (strncmp (s, "%fcc0", 5) == 0)
1929 {
1930 s += 5;
1931 continue;
1932 }
1933 break;
1934
1935 case '7':
1936 if (*s == ' ')
1937 {
1938 ++s;
1939 }
1940 if (strncmp (s, "%fcc1", 5) == 0)
1941 {
1942 s += 5;
1943 continue;
1944 }
1945 break;
1946
1947 case '8':
1948 if (*s == ' ')
1949 {
1950 ++s;
1951 }
1952 if (strncmp (s, "%fcc2", 5) == 0)
1953 {
1954 s += 5;
1955 continue;
1956 }
1957 break;
1958
1959 case '9':
1960 if (*s == ' ')
1961 {
1962 ++s;
1963 }
1964 if (strncmp (s, "%fcc3", 5) == 0)
1965 {
1966 s += 5;
1967 continue;
1968 }
1969 break;
1970
1971 case 'P':
1972 if (strncmp (s, "%pc", 3) == 0)
1973 {
1974 s += 3;
1975 continue;
1976 }
1977 break;
1978
1979 case 'W':
1980 if (strncmp (s, "%tick", 5) == 0)
1981 {
1982 s += 5;
1983 continue;
1984 }
1985 break;
1986
1987 case '\0': /* End of args. */
1988 if (s[0] == ',' && s[1] == '%')
1989 {
1990 static const struct ops
1991 {
1992 /* The name as it appears in assembler. */
1993 char *name;
1994 /* strlen (name), precomputed for speed */
1995 int len;
1996 /* The reloc this pseudo-op translates to. */
1997 int reloc;
1998 /* 1 if tls call. */
1999 int tls_call;
2000 }
2001 ops[] =
2002 {
2003 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 },
2004 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 },
2005 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 },
2006 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 },
2007 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 },
2008 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 },
2009 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 },
2010 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 },
2011 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 },
2012 { NULL, 0, 0, 0 }
2013 };
2014 const struct ops *o;
2015 char *s1;
2016 int npar = 0;
2017
2018 for (o = ops; o->name; o++)
2019 if (strncmp (s + 2, o->name, o->len) == 0)
2020 break;
2021 if (o->name == NULL)
2022 break;
2023
2024 if (s[o->len + 2] != '(')
2025 {
2026 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2027 return special_case;
2028 }
2029
2030 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE)
2031 {
2032 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2033 o->name);
2034 return special_case;
2035 }
2036
2037 if (o->tls_call
2038 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2
2039 || the_insn.exp.X_add_number != 0
2040 || the_insn.exp.X_add_symbol
2041 != symbol_find_or_make ("__tls_get_addr")))
2042 {
2043 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2044 o->name);
2045 return special_case;
2046 }
2047
2048 the_insn.reloc = o->reloc;
2049 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2050 s += o->len + 3;
2051
2052 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2053 if (*s1 == '(')
2054 npar++;
2055 else if (*s1 == ')')
2056 {
2057 if (!npar)
2058 break;
2059 npar--;
2060 }
2061
2062 if (*s1 != ')')
2063 {
2064 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2065 return special_case;
2066 }
2067
2068 *s1 = '\0';
2069 (void) get_expression (s);
2070 *s1 = ')';
2071 s = s1 + 1;
2072 }
2073 if (*s == '\0')
2074 match = 1;
2075 break;
2076
2077 case '+':
2078 if (*s == '+')
2079 {
2080 ++s;
2081 continue;
2082 }
2083 if (*s == '-')
2084 {
2085 continue;
2086 }
2087 break;
2088
2089 case '[': /* These must match exactly. */
2090 case ']':
2091 case ',':
2092 case ' ':
2093 if (*s++ == *args)
2094 continue;
2095 break;
2096
2097 case '#': /* Must be at least one digit. */
2098 if (ISDIGIT (*s++))
2099 {
2100 while (ISDIGIT (*s))
2101 {
2102 ++s;
2103 }
2104 continue;
2105 }
2106 break;
2107
2108 case 'C': /* Coprocessor state register. */
2109 if (strncmp (s, "%csr", 4) == 0)
2110 {
2111 s += 4;
2112 continue;
2113 }
2114 break;
2115
2116 case 'b': /* Next operand is a coprocessor register. */
2117 case 'c':
2118 case 'D':
2119 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s))
2120 {
2121 mask = *s++;
2122 if (ISDIGIT (*s))
2123 {
2124 mask = 10 * (mask - '0') + (*s++ - '0');
2125 if (mask >= 32)
2126 {
2127 break;
2128 }
2129 }
2130 else
2131 {
2132 mask -= '0';
2133 }
2134 switch (*args)
2135 {
2136
2137 case 'b':
2138 opcode |= mask << 14;
2139 continue;
2140
2141 case 'c':
2142 opcode |= mask;
2143 continue;
2144
2145 case 'D':
2146 opcode |= mask << 25;
2147 continue;
2148 }
2149 }
2150 break;
2151
2152 case 'r': /* next operand must be a register */
2153 case 'O':
2154 case '1':
2155 case '2':
2156 case 'd':
2157 if (*s++ == '%')
2158 {
2159 switch (c = *s++)
2160 {
2161
2162 case 'f': /* frame pointer */
2163 if (*s++ == 'p')
2164 {
2165 mask = 0x1e;
2166 break;
2167 }
2168 goto error;
2169
2170 case 'g': /* global register */
2171 c = *s++;
2172 if (isoctal (c))
2173 {
2174 mask = c - '0';
2175 break;
2176 }
2177 goto error;
2178
2179 case 'i': /* in register */
2180 c = *s++;
2181 if (isoctal (c))
2182 {
2183 mask = c - '0' + 24;
2184 break;
2185 }
2186 goto error;
2187
2188 case 'l': /* local register */
2189 c = *s++;
2190 if (isoctal (c))
2191 {
2192 mask = (c - '0' + 16);
2193 break;
2194 }
2195 goto error;
2196
2197 case 'o': /* out register */
2198 c = *s++;
2199 if (isoctal (c))
2200 {
2201 mask = (c - '0' + 8);
2202 break;
2203 }
2204 goto error;
2205
2206 case 's': /* stack pointer */
2207 if (*s++ == 'p')
2208 {
2209 mask = 0xe;
2210 break;
2211 }
2212 goto error;
2213
2214 case 'r': /* any register */
2215 if (!ISDIGIT ((c = *s++)))
2216 {
2217 goto error;
2218 }
2219 /* FALLTHROUGH */
2220 case '0':
2221 case '1':
2222 case '2':
2223 case '3':
2224 case '4':
2225 case '5':
2226 case '6':
2227 case '7':
2228 case '8':
2229 case '9':
2230 if (ISDIGIT (*s))
2231 {
2232 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32)
2233 {
2234 goto error;
2235 }
2236 }
2237 else
2238 {
2239 c -= '0';
2240 }
2241 mask = c;
2242 break;
2243
2244 default:
2245 goto error;
2246 }
2247
2248 if ((mask & ~1) == 2 && sparc_arch_size == 64
2249 && no_undeclared_regs && ! globals[mask])
2250 as_bad (_("detected global register use not covered by .register pseudo-op"));
2251
2252 /* Got the register, now figure out where
2253 it goes in the opcode. */
2254 switch (*args)
2255 {
2256 case '1':
2257 opcode |= mask << 14;
2258 continue;
2259
2260 case '2':
2261 opcode |= mask;
2262 continue;
2263
2264 case 'd':
2265 opcode |= mask << 25;
2266 continue;
2267
2268 case 'r':
2269 opcode |= (mask << 25) | (mask << 14);
2270 continue;
2271
2272 case 'O':
2273 opcode |= (mask << 25) | (mask << 0);
2274 continue;
2275 }
2276 }
2277 break;
2278
2279 case 'e': /* next operand is a floating point register */
2280 case 'v':
2281 case 'V':
2282
2283 case 'f':
2284 case 'B':
2285 case 'R':
2286
2287 case '4':
2288 case '5':
2289
2290 case 'g':
2291 case 'H':
2292 case 'J':
2293 {
2294 char format;
2295
2296 if (*s++ == '%'
2297 && ((format = *s) == 'f')
2298 && ISDIGIT (*++s))
2299 {
2300 for (mask = 0; ISDIGIT (*s); ++s)
2301 {
2302 mask = 10 * mask + (*s - '0');
2303 } /* read the number */
2304
2305 if ((*args == 'v'
2306 || *args == 'B'
2307 || *args == '5'
2308 || *args == 'H')
2309 && (mask & 1))
2310 {
2311 break;
2312 } /* register must be even numbered */
2313
2314 if ((*args == 'V'
2315 || *args == 'R'
2316 || *args == 'J')
2317 && (mask & 3))
2318 {
2319 break;
2320 } /* register must be multiple of 4 */
2321
2322 if (mask >= 64)
2323 {
2324 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2325 error_message = _(": There are only 64 f registers; [0-63]");
2326 else
2327 error_message = _(": There are only 32 f registers; [0-31]");
2328 goto error;
2329 } /* on error */
2330 else if (mask >= 32)
2331 {
2332 if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
2333 {
2334 if (*args == 'e' || *args == 'f' || *args == 'g')
2335 {
2336 error_message
2337 = _(": There are only 32 single precision f registers; [0-31]");
2338 goto error;
2339 }
2340 v9_arg_p = 1;
2341 mask -= 31; /* wrap high bit */
2342 }
2343 else
2344 {
2345 error_message = _(": There are only 32 f registers; [0-31]");
2346 goto error;
2347 }
2348 }
2349 }
2350 else
2351 {
2352 break;
2353 } /* if not an 'f' register. */
2354
2355 switch (*args)
2356 {
2357 case 'v':
2358 case 'V':
2359 case 'e':
2360 opcode |= RS1 (mask);
2361 continue;
2362
2363 case 'f':
2364 case 'B':
2365 case 'R':
2366 opcode |= RS2 (mask);
2367 continue;
2368
2369 case '4':
2370 case '5':
2371 opcode |= RS3 (mask);
2372 continue;
2373
2374 case 'g':
2375 case 'H':
2376 case 'J':
2377 opcode |= RD (mask);
2378 continue;
2379 } /* Pack it in. */
2380
2381 know (0);
2382 break;
2383 } /* float arg */
2384
2385 case 'F':
2386 if (strncmp (s, "%fsr", 4) == 0)
2387 {
2388 s += 4;
2389 continue;
2390 }
2391 break;
2392
2393 case '(':
2394 if (strncmp (s, "%efsr", 5) == 0)
2395 {
2396 s += 5;
2397 continue;
2398 }
2399 break;
2400
2401 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2402 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
2403 goto immediate;
2404
2405 case 'l': /* 22 bit PC relative immediate */
2406 the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
2407 the_insn.pcrel = 1;
2408 goto immediate;
2409
2410 case 'L': /* 30 bit immediate */
2411 the_insn.reloc = BFD_RELOC_32_PCREL_S2;
2412 the_insn.pcrel = 1;
2413 goto immediate;
2414
2415 case 'h':
2416 case 'n': /* 22 bit immediate */
2417 the_insn.reloc = BFD_RELOC_SPARC22;
2418 goto immediate;
2419
2420 case 'i': /* 13 bit immediate */
2421 the_insn.reloc = BFD_RELOC_SPARC13;
2422
2423 /* fallthrough */
2424
2425 immediate:
2426 if (*s == ' ')
2427 s++;
2428
2429 {
2430 char *s1;
2431 char *op_arg = NULL;
2432 static expressionS op_exp;
2433 bfd_reloc_code_real_type old_reloc = the_insn.reloc;
2434
2435 /* Check for %hi, etc. */
2436 if (*s == '%')
2437 {
2438 static const struct ops {
2439 /* The name as it appears in assembler. */
2440 char *name;
2441 /* strlen (name), precomputed for speed */
2442 int len;
2443 /* The reloc this pseudo-op translates to. */
2444 int reloc;
2445 /* Non-zero if for v9 only. */
2446 int v9_p;
2447 /* Non-zero if can be used in pc-relative contexts. */
2448 int pcrel_p;/*FIXME:wip*/
2449 } ops[] = {
2450 /* hix/lox must appear before hi/lo so %hix won't be
2451 mistaken for %hi. */
2452 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 },
2453 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 },
2454 { "hi", 2, BFD_RELOC_HI22, 0, 1 },
2455 { "lo", 2, BFD_RELOC_LO10, 0, 1 },
2456 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 },
2457 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 },
2458 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 },
2459 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 },
2460 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 },
2461 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 },
2462 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2463 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 },
2464 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 },
2465 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 },
2466 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 },
2467 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 },
2468 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 },
2469 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 },
2470 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 },
2471 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 },
2472 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0,
2473 0 },
2474 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0,
2475 0 },
2476 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 },
2477 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 },
2478 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 },
2479 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 },
2480 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22,
2481 0, 0 },
2482 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10,
2483 0, 0 },
2484 { NULL, 0, 0, 0, 0 }
2485 };
2486 const struct ops *o;
2487
2488 for (o = ops; o->name; o++)
2489 if (strncmp (s + 1, o->name, o->len) == 0)
2490 break;
2491 if (o->name == NULL)
2492 break;
2493
2494 if (s[o->len + 1] != '(')
2495 {
2496 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name);
2497 return special_case;
2498 }
2499
2500 op_arg = o->name;
2501 the_insn.reloc = o->reloc;
2502 s += o->len + 2;
2503 v9_arg_p = o->v9_p;
2504 }
2505
2506 /* Note that if the get_expression() fails, we will still
2507 have created U entries in the symbol table for the
2508 'symbols' in the input string. Try not to create U
2509 symbols for registers, etc. */
2510
2511 /* This stuff checks to see if the expression ends in
2512 +%reg. If it does, it removes the register from
2513 the expression, and re-sets 's' to point to the
2514 right place. */
2515
2516 if (op_arg)
2517 {
2518 int npar = 0;
2519
2520 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2521 if (*s1 == '(')
2522 npar++;
2523 else if (*s1 == ')')
2524 {
2525 if (!npar)
2526 break;
2527 npar--;
2528 }
2529
2530 if (*s1 != ')')
2531 {
2532 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg);
2533 return special_case;
2534 }
2535
2536 *s1 = '\0';
2537 (void) get_expression (s);
2538 *s1 = ')';
2539 s = s1 + 1;
2540 if (*s == ',' || *s == ']' || !*s)
2541 continue;
2542 if (*s != '+' && *s != '-')
2543 {
2544 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg);
2545 return special_case;
2546 }
2547 *s1 = '0';
2548 s = s1;
2549 op_exp = the_insn.exp;
2550 memset (&the_insn.exp, 0, sizeof (the_insn.exp));
2551 }
2552
2553 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++)
2554 ;
2555
2556 if (s1 != s && ISDIGIT (s1[-1]))
2557 {
2558 if (s1[-2] == '%' && s1[-3] == '+')
2559 s1 -= 3;
2560 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+')
2561 s1 -= 4;
2562 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+')
2563 s1 -= 5;
2564 else
2565 s1 = NULL;
2566 if (s1)
2567 {
2568 *s1 = '\0';
2569 if (op_arg && s1 == s + 1)
2570 the_insn.exp.X_op = O_absent;
2571 else
2572 (void) get_expression (s);
2573 *s1 = '+';
2574 if (op_arg)
2575 *s = ')';
2576 s = s1;
2577 }
2578 }
2579 else
2580 s1 = NULL;
2581
2582 if (!s1)
2583 {
2584 (void) get_expression (s);
2585 if (op_arg)
2586 *s = ')';
2587 s = expr_end;
2588 }
2589
2590 if (op_arg)
2591 {
2592 the_insn.exp2 = the_insn.exp;
2593 the_insn.exp = op_exp;
2594 if (the_insn.exp2.X_op == O_absent)
2595 the_insn.exp2.X_op = O_illegal;
2596 else if (the_insn.exp.X_op == O_absent)
2597 {
2598 the_insn.exp = the_insn.exp2;
2599 the_insn.exp2.X_op = O_illegal;
2600 }
2601 else if (the_insn.exp.X_op == O_constant)
2602 {
2603 valueT val = the_insn.exp.X_add_number;
2604 switch (the_insn.reloc)
2605 {
2606 default:
2607 break;
2608
2609 case BFD_RELOC_SPARC_HH22:
2610 val = BSR (val, 32);
2611 /* Fall through. */
2612
2613 case BFD_RELOC_SPARC_LM22:
2614 case BFD_RELOC_HI22:
2615 val = (val >> 10) & 0x3fffff;
2616 break;
2617
2618 case BFD_RELOC_SPARC_HM10:
2619 val = BSR (val, 32);
2620 /* Fall through. */
2621
2622 case BFD_RELOC_LO10:
2623 val &= 0x3ff;
2624 break;
2625
2626 case BFD_RELOC_SPARC_H34:
2627 val >>= 12;
2628 val &= 0x3fffff;
2629 break;
2630
2631 case BFD_RELOC_SPARC_H44:
2632 val >>= 22;
2633 val &= 0x3fffff;
2634 break;
2635
2636 case BFD_RELOC_SPARC_M44:
2637 val >>= 12;
2638 val &= 0x3ff;
2639 break;
2640
2641 case BFD_RELOC_SPARC_L44:
2642 val &= 0xfff;
2643 break;
2644
2645 case BFD_RELOC_SPARC_HIX22:
2646 val = ~val;
2647 val = (val >> 10) & 0x3fffff;
2648 break;
2649
2650 case BFD_RELOC_SPARC_LOX10:
2651 val = (val & 0x3ff) | 0x1c00;
2652 break;
2653 }
2654 the_insn.exp = the_insn.exp2;
2655 the_insn.exp.X_add_number += val;
2656 the_insn.exp2.X_op = O_illegal;
2657 the_insn.reloc = old_reloc;
2658 }
2659 else if (the_insn.exp2.X_op != O_constant)
2660 {
2661 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg);
2662 return special_case;
2663 }
2664 else
2665 {
2666 if (old_reloc != BFD_RELOC_SPARC13
2667 || the_insn.reloc != BFD_RELOC_LO10
2668 || sparc_arch_size != 64
2669 || sparc_pic_code)
2670 {
2671 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg);
2672 return special_case;
2673 }
2674 the_insn.reloc = BFD_RELOC_SPARC_OLO10;
2675 }
2676 }
2677 }
2678 /* Check for constants that don't require emitting a reloc. */
2679 if (the_insn.exp.X_op == O_constant
2680 && the_insn.exp.X_add_symbol == 0
2681 && the_insn.exp.X_op_symbol == 0)
2682 {
2683 /* For pc-relative call instructions, we reject
2684 constants to get better code. */
2685 if (the_insn.pcrel
2686 && the_insn.reloc == BFD_RELOC_32_PCREL_S2
2687 && in_signed_range (the_insn.exp.X_add_number, 0x3fff))
2688 {
2689 error_message = _(": PC-relative operand can't be a constant");
2690 goto error;
2691 }
2692
2693 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22
2694 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64)
2695 {
2696 error_message = _(": TLS operand can't be a constant");
2697 goto error;
2698 }
2699
2700 /* Constants that won't fit are checked in md_apply_fix
2701 and bfd_install_relocation.
2702 ??? It would be preferable to install the constants
2703 into the insn here and save having to create a fixS
2704 for each one. There already exists code to handle
2705 all the various cases (e.g. in md_apply_fix and
2706 bfd_install_relocation) so duplicating all that code
2707 here isn't right. */
2708
2709 /* This is a special case to handle cbcond instructions
2710 properly, which can need two relocations. The first
2711 one is for the 5-bit immediate field and the latter
2712 is going to be for the WDISP10 branch part. We
2713 handle the R_SPARC_5 immediate directly here so that
2714 we don't need to add support for multiple relocations
2715 in one instruction just yet. */
2716 if (the_insn.reloc == BFD_RELOC_SPARC_5)
2717 {
2718 valueT val = the_insn.exp.X_add_number;
2719
2720 if (! in_bitfield_range (val, 0x1f))
2721 {
2722 error_message = _(": Immediate value in cbcond is out of range.");
2723 goto error;
2724 }
2725 opcode |= val & 0x1f;
2726 the_insn.reloc = BFD_RELOC_NONE;
2727 }
2728 }
2729
2730 continue;
2731
2732 case 'a':
2733 if (*s++ == 'a')
2734 {
2735 opcode |= ANNUL;
2736 continue;
2737 }
2738 break;
2739
2740 case 'A':
2741 {
2742 int asi = 0;
2743
2744 /* Parse an asi. */
2745 if (*s == '#')
2746 {
2747 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi))
2748 {
2749 error_message = _(": invalid ASI name");
2750 goto error;
2751 }
2752 }
2753 else
2754 {
2755 if (! parse_const_expr_arg (&s, &asi))
2756 {
2757 error_message = _(": invalid ASI expression");
2758 goto error;
2759 }
2760 if (asi < 0 || asi > 255)
2761 {
2762 error_message = _(": invalid ASI number");
2763 goto error;
2764 }
2765 }
2766 opcode |= ASI (asi);
2767 continue;
2768 } /* Alternate space. */
2769
2770 case 'p':
2771 if (strncmp (s, "%psr", 4) == 0)
2772 {
2773 s += 4;
2774 continue;
2775 }
2776 break;
2777
2778 case 'q': /* Floating point queue. */
2779 if (strncmp (s, "%fq", 3) == 0)
2780 {
2781 s += 3;
2782 continue;
2783 }
2784 break;
2785
2786 case 'Q': /* Coprocessor queue. */
2787 if (strncmp (s, "%cq", 3) == 0)
2788 {
2789 s += 3;
2790 continue;
2791 }
2792 break;
2793
2794 case 'S':
2795 if (strcmp (str, "set") == 0
2796 || strcmp (str, "setuw") == 0)
2797 {
2798 special_case = SPECIAL_CASE_SET;
2799 continue;
2800 }
2801 else if (strcmp (str, "setsw") == 0)
2802 {
2803 special_case = SPECIAL_CASE_SETSW;
2804 continue;
2805 }
2806 else if (strcmp (str, "setx") == 0)
2807 {
2808 special_case = SPECIAL_CASE_SETX;
2809 continue;
2810 }
2811 else if (strncmp (str, "fdiv", 4) == 0)
2812 {
2813 special_case = SPECIAL_CASE_FDIV;
2814 continue;
2815 }
2816 break;
2817
2818 case 'o':
2819 if (strncmp (s, "%asi", 4) != 0)
2820 break;
2821 s += 4;
2822 continue;
2823
2824 case 's':
2825 if (strncmp (s, "%fprs", 5) != 0)
2826 break;
2827 s += 5;
2828 continue;
2829
2830 case 'E':
2831 if (strncmp (s, "%ccr", 4) != 0)
2832 break;
2833 s += 4;
2834 continue;
2835
2836 case 't':
2837 if (strncmp (s, "%tbr", 4) != 0)
2838 break;
2839 s += 4;
2840 continue;
2841
2842 case 'w':
2843 if (strncmp (s, "%wim", 4) != 0)
2844 break;
2845 s += 4;
2846 continue;
2847
2848 case 'x':
2849 {
2850 char *push = input_line_pointer;
2851 expressionS e;
2852
2853 input_line_pointer = s;
2854 expression (&e);
2855 if (e.X_op == O_constant)
2856 {
2857 int n = e.X_add_number;
2858 if (n != e.X_add_number || (n & ~0x1ff) != 0)
2859 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2860 else
2861 opcode |= e.X_add_number << 5;
2862 }
2863 else
2864 as_bad (_("non-immediate OPF operand, ignored"));
2865 s = input_line_pointer;
2866 input_line_pointer = push;
2867 continue;
2868 }
2869
2870 case 'y':
2871 if (strncmp (s, "%y", 2) != 0)
2872 break;
2873 s += 2;
2874 continue;
2875
2876 case 'u':
2877 case 'U':
2878 {
2879 /* Parse a sparclet cpreg. */
2880 int cpreg;
2881 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg))
2882 {
2883 error_message = _(": invalid cpreg name");
2884 goto error;
2885 }
2886 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg));
2887 continue;
2888 }
2889
2890 default:
2891 as_fatal (_("failed sanity check."));
2892 } /* switch on arg code. */
2893
2894 /* Break out of for() loop. */
2895 break;
2896 } /* For each arg that we expect. */
2897
2898 error:
2899 if (match == 0)
2900 {
2901 /* Args don't match. */
2902 if (&insn[1] - sparc_opcodes < sparc_num_opcodes
2903 && (insn->name == insn[1].name
2904 || !strcmp (insn->name, insn[1].name)))
2905 {
2906 ++insn;
2907 s = argsStart;
2908 continue;
2909 }
2910 else
2911 {
2912 as_bad (_("Illegal operands%s"), error_message);
2913 return special_case;
2914 }
2915 }
2916 else
2917 {
2918 /* We have a match. Now see if the architecture is OK. */
2919 int needed_arch_mask = insn->architecture;
2920 int hwcaps = insn->hwcaps;
2921
2922 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2923 if (hwcaps)
2924 hwcap_seen |= hwcaps;
2925 #endif
2926 if (v9_arg_p)
2927 {
2928 needed_arch_mask &=
2929 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1);
2930 if (! needed_arch_mask)
2931 needed_arch_mask =
2932 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2933 }
2934
2935 if (needed_arch_mask
2936 & SPARC_OPCODE_SUPPORTED (current_architecture))
2937 /* OK. */
2938 ;
2939 /* Can we bump up the architecture? */
2940 else if (needed_arch_mask
2941 & SPARC_OPCODE_SUPPORTED (max_architecture))
2942 {
2943 enum sparc_opcode_arch_val needed_architecture =
2944 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture)
2945 & needed_arch_mask);
2946
2947 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX);
2948 if (warn_on_bump
2949 && needed_architecture > warn_after_architecture)
2950 {
2951 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2952 sparc_opcode_archs[current_architecture].name,
2953 sparc_opcode_archs[needed_architecture].name,
2954 str);
2955 warn_after_architecture = needed_architecture;
2956 }
2957 current_architecture = needed_architecture;
2958 }
2959 /* Conflict. */
2960 /* ??? This seems to be a bit fragile. What if the next entry in
2961 the opcode table is the one we want and it is supported?
2962 It is possible to arrange the table today so that this can't
2963 happen but what about tomorrow? */
2964 else
2965 {
2966 int arch, printed_one_p = 0;
2967 char *p;
2968 char required_archs[SPARC_OPCODE_ARCH_MAX * 16];
2969
2970 /* Create a list of the architectures that support the insn. */
2971 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture);
2972 p = required_archs;
2973 arch = sparc_ffs (needed_arch_mask);
2974 while ((1 << arch) <= needed_arch_mask)
2975 {
2976 if ((1 << arch) & needed_arch_mask)
2977 {
2978 if (printed_one_p)
2979 *p++ = '|';
2980 strcpy (p, sparc_opcode_archs[arch].name);
2981 p += strlen (p);
2982 printed_one_p = 1;
2983 }
2984 ++arch;
2985 }
2986
2987 as_bad (_("Architecture mismatch on \"%s\"."), str);
2988 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2989 required_archs,
2990 sparc_opcode_archs[max_architecture].name);
2991 return special_case;
2992 }
2993
2994 /* Make sure the the hwcaps used by the instruction are
2995 currently enabled. */
2996 if (hwcaps & ~hwcap_allowed)
2997 {
2998 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed);
2999
3000 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3001 hwcap_name, str);
3002 return special_case;
3003 }
3004 } /* If no match. */
3005
3006 break;
3007 } /* Forever looking for a match. */
3008
3009 the_insn.opcode = opcode;
3010 return special_case;
3011 }
3012
3013 /* Parse an argument that can be expressed as a keyword.
3014 (eg: #StoreStore or %ccfr).
3015 The result is a boolean indicating success.
3016 If successful, INPUT_POINTER is updated. */
3017
3018 static int
3019 parse_keyword_arg (int (*lookup_fn) (const char *),
3020 char **input_pointerP,
3021 int *valueP)
3022 {
3023 int value;
3024 char c, *p, *q;
3025
3026 p = *input_pointerP;
3027 for (q = p + (*p == '#' || *p == '%');
3028 ISALNUM (*q) || *q == '_';
3029 ++q)
3030 continue;
3031 c = *q;
3032 *q = 0;
3033 value = (*lookup_fn) (p);
3034 *q = c;
3035 if (value == -1)
3036 return 0;
3037 *valueP = value;
3038 *input_pointerP = q;
3039 return 1;
3040 }
3041
3042 /* Parse an argument that is a constant expression.
3043 The result is a boolean indicating success. */
3044
3045 static int
3046 parse_const_expr_arg (char **input_pointerP, int *valueP)
3047 {
3048 char *save = input_line_pointer;
3049 expressionS exp;
3050
3051 input_line_pointer = *input_pointerP;
3052 /* The next expression may be something other than a constant
3053 (say if we're not processing the right variant of the insn).
3054 Don't call expression unless we're sure it will succeed as it will
3055 signal an error (which we want to defer until later). */
3056 /* FIXME: It might be better to define md_operand and have it recognize
3057 things like %asi, etc. but continuing that route through to the end
3058 is a lot of work. */
3059 if (*input_line_pointer == '%')
3060 {
3061 input_line_pointer = save;
3062 return 0;
3063 }
3064 expression (&exp);
3065 *input_pointerP = input_line_pointer;
3066 input_line_pointer = save;
3067 if (exp.X_op != O_constant)
3068 return 0;
3069 *valueP = exp.X_add_number;
3070 return 1;
3071 }
3072
3073 /* Subroutine of sparc_ip to parse an expression. */
3074
3075 static int
3076 get_expression (char *str)
3077 {
3078 char *save_in;
3079 segT seg;
3080
3081 save_in = input_line_pointer;
3082 input_line_pointer = str;
3083 seg = expression (&the_insn.exp);
3084 if (seg != absolute_section
3085 && seg != text_section
3086 && seg != data_section
3087 && seg != bss_section
3088 && seg != undefined_section)
3089 {
3090 the_insn.error = _("bad segment");
3091 expr_end = input_line_pointer;
3092 input_line_pointer = save_in;
3093 return 1;
3094 }
3095 expr_end = input_line_pointer;
3096 input_line_pointer = save_in;
3097 return 0;
3098 }
3099
3100 /* Subroutine of md_assemble to output one insn. */
3101
3102 static void
3103 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn)
3104 {
3105 char *toP = frag_more (4);
3106
3107 /* Put out the opcode. */
3108 if (INSN_BIG_ENDIAN)
3109 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4);
3110 else
3111 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4);
3112
3113 /* Put out the symbol-dependent stuff. */
3114 if (theinsn->reloc != BFD_RELOC_NONE)
3115 {
3116 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */
3117 (toP - frag_now->fr_literal), /* Where. */
3118 4, /* Size. */
3119 &theinsn->exp,
3120 theinsn->pcrel,
3121 theinsn->reloc);
3122 /* Turn off overflow checking in fixup_segment. We'll do our
3123 own overflow checking in md_apply_fix. This is necessary because
3124 the insn size is 4 and fixup_segment will signal an overflow for
3125 large 8 byte quantities. */
3126 fixP->fx_no_overflow = 1;
3127 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10)
3128 fixP->tc_fix_data = theinsn->exp2.X_add_number;
3129 }
3130
3131 last_insn = insn;
3132 last_opcode = theinsn->opcode;
3133
3134 #ifdef OBJ_ELF
3135 dwarf2_emit_insn (4);
3136 #endif
3137 }
3138 \f
3139 char *
3140 md_atof (int type, char *litP, int *sizeP)
3141 {
3142 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3143 }
3144
3145 /* Write a value out to the object file, using the appropriate
3146 endianness. */
3147
3148 void
3149 md_number_to_chars (char *buf, valueT val, int n)
3150 {
3151 if (target_big_endian)
3152 number_to_chars_bigendian (buf, val, n);
3153 else if (target_little_endian_data
3154 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC))
3155 /* Output debug words, which are not in allocated sections, as big
3156 endian. */
3157 number_to_chars_bigendian (buf, val, n);
3158 else if (target_little_endian_data || ! target_big_endian)
3159 number_to_chars_littleendian (buf, val, n);
3160 }
3161 \f
3162 /* Apply a fixS to the frags, now that we know the value it ought to
3163 hold. */
3164
3165 void
3166 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
3167 {
3168 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
3169 offsetT val = * (offsetT *) valP;
3170 long insn;
3171
3172 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
3173
3174 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
3175
3176 #ifdef OBJ_ELF
3177 /* SPARC ELF relocations don't use an addend in the data field. */
3178 if (fixP->fx_addsy != NULL)
3179 {
3180 switch (fixP->fx_r_type)
3181 {
3182 case BFD_RELOC_SPARC_TLS_GD_HI22:
3183 case BFD_RELOC_SPARC_TLS_GD_LO10:
3184 case BFD_RELOC_SPARC_TLS_GD_ADD:
3185 case BFD_RELOC_SPARC_TLS_GD_CALL:
3186 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3187 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3188 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3189 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3190 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3191 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3192 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3193 case BFD_RELOC_SPARC_TLS_IE_HI22:
3194 case BFD_RELOC_SPARC_TLS_IE_LO10:
3195 case BFD_RELOC_SPARC_TLS_IE_LD:
3196 case BFD_RELOC_SPARC_TLS_IE_LDX:
3197 case BFD_RELOC_SPARC_TLS_IE_ADD:
3198 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3199 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3200 case BFD_RELOC_SPARC_TLS_DTPMOD32:
3201 case BFD_RELOC_SPARC_TLS_DTPMOD64:
3202 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3203 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3204 case BFD_RELOC_SPARC_TLS_TPOFF32:
3205 case BFD_RELOC_SPARC_TLS_TPOFF64:
3206 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3207
3208 default:
3209 break;
3210 }
3211
3212 return;
3213 }
3214 #endif
3215
3216 /* This is a hack. There should be a better way to
3217 handle this. Probably in terms of howto fields, once
3218 we can look at these fixups in terms of howtos. */
3219 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy)
3220 val += fixP->fx_where + fixP->fx_frag->fr_address;
3221
3222 #ifdef OBJ_AOUT
3223 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3224 generate a reloc, then we just want to let the reloc addend set
3225 the value. We do not want to also stuff the addend into the
3226 object file. Including the addend in the object file works when
3227 doing a static link, because the linker will ignore the object
3228 file contents. However, the dynamic linker does not ignore the
3229 object file contents. */
3230 if (fixP->fx_addsy != NULL
3231 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2)
3232 val = 0;
3233
3234 /* When generating PIC code, we do not want an addend for a reloc
3235 against a local symbol. We adjust fx_addnumber to cancel out the
3236 value already included in val, and to also cancel out the
3237 adjustment which bfd_install_relocation will create. */
3238 if (sparc_pic_code
3239 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2
3240 && fixP->fx_addsy != NULL
3241 && ! S_IS_COMMON (fixP->fx_addsy)
3242 && symbol_section_p (fixP->fx_addsy))
3243 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3244
3245 /* When generating PIC code, we need to fiddle to get
3246 bfd_install_relocation to do the right thing for a PC relative
3247 reloc against a local symbol which we are going to keep. */
3248 if (sparc_pic_code
3249 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2
3250 && fixP->fx_addsy != NULL
3251 && (S_IS_EXTERNAL (fixP->fx_addsy)
3252 || S_IS_WEAK (fixP->fx_addsy))
3253 && S_IS_DEFINED (fixP->fx_addsy)
3254 && ! S_IS_COMMON (fixP->fx_addsy))
3255 {
3256 val = 0;
3257 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy);
3258 }
3259 #endif
3260
3261 /* If this is a data relocation, just output VAL. */
3262
3263 if (fixP->fx_r_type == BFD_RELOC_8)
3264 {
3265 md_number_to_chars (buf, val, 1);
3266 }
3267 else if (fixP->fx_r_type == BFD_RELOC_16
3268 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16)
3269 {
3270 md_number_to_chars (buf, val, 2);
3271 }
3272 else if (fixP->fx_r_type == BFD_RELOC_32
3273 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32
3274 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32)
3275 {
3276 md_number_to_chars (buf, val, 4);
3277 }
3278 else if (fixP->fx_r_type == BFD_RELOC_64
3279 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64)
3280 {
3281 md_number_to_chars (buf, val, 8);
3282 }
3283 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3284 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3285 {
3286 fixP->fx_done = 0;
3287 return;
3288 }
3289 else
3290 {
3291 /* It's a relocation against an instruction. */
3292
3293 if (INSN_BIG_ENDIAN)
3294 insn = bfd_getb32 ((unsigned char *) buf);
3295 else
3296 insn = bfd_getl32 ((unsigned char *) buf);
3297
3298 switch (fixP->fx_r_type)
3299 {
3300 case BFD_RELOC_32_PCREL_S2:
3301 val = val >> 2;
3302 /* FIXME: This increment-by-one deserves a comment of why it's
3303 being done! */
3304 if (! sparc_pic_code
3305 || fixP->fx_addsy == NULL
3306 || symbol_section_p (fixP->fx_addsy))
3307 ++val;
3308
3309 insn |= val & 0x3fffffff;
3310
3311 /* See if we have a delay slot. */
3312 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix)
3313 {
3314 #define G0 0
3315 #define O7 15
3316 #define XCC (2 << 20)
3317 #define COND(x) (((x)&0xf)<<25)
3318 #define CONDA COND(0x8)
3319 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3320 #define INSN_BA (F2(0,2) | CONDA)
3321 #define INSN_OR F3(2, 0x2, 0)
3322 #define INSN_NOP F2(0,4)
3323
3324 long delay;
3325
3326 /* If the instruction is a call with either:
3327 restore
3328 arithmetic instruction with rd == %o7
3329 where rs1 != %o7 and rs2 if it is register != %o7
3330 then we can optimize if the call destination is near
3331 by changing the call into a branch always. */
3332 if (INSN_BIG_ENDIAN)
3333 delay = bfd_getb32 ((unsigned char *) buf + 4);
3334 else
3335 delay = bfd_getl32 ((unsigned char *) buf + 4);
3336 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2))
3337 break;
3338 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */
3339 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */
3340 || ((delay & RD (~0)) != RD (O7))))
3341 break;
3342 if ((delay & RS1 (~0)) == RS1 (O7)
3343 || ((delay & F3I (~0)) == 0
3344 && (delay & RS2 (~0)) == RS2 (O7)))
3345 break;
3346 /* Ensure the branch will fit into simm22. */
3347 if ((val & 0x3fe00000)
3348 && (val & 0x3fe00000) != 0x3fe00000)
3349 break;
3350 /* Check if the arch is v9 and branch will fit
3351 into simm19. */
3352 if (((val & 0x3c0000) == 0
3353 || (val & 0x3c0000) == 0x3c0000)
3354 && (sparc_arch_size == 64
3355 || current_architecture >= SPARC_OPCODE_ARCH_V9))
3356 /* ba,pt %xcc */
3357 insn = INSN_BPA | (val & 0x7ffff);
3358 else
3359 /* ba */
3360 insn = INSN_BA | (val & 0x3fffff);
3361 if (fixP->fx_where >= 4
3362 && ((delay & (0xffffffff ^ RS1 (~0)))
3363 == (INSN_OR | RD (O7) | RS2 (G0))))
3364 {
3365 long setter;
3366 int reg;
3367
3368 if (INSN_BIG_ENDIAN)
3369 setter = bfd_getb32 ((unsigned char *) buf - 4);
3370 else
3371 setter = bfd_getl32 ((unsigned char *) buf - 4);
3372 if ((setter & (0xffffffff ^ RD (~0)))
3373 != (INSN_OR | RS1 (O7) | RS2 (G0)))
3374 break;
3375 /* The sequence was
3376 or %o7, %g0, %rN
3377 call foo
3378 or %rN, %g0, %o7
3379
3380 If call foo was replaced with ba, replace
3381 or %rN, %g0, %o7 with nop. */
3382 reg = (delay & RS1 (~0)) >> 14;
3383 if (reg != ((setter & RD (~0)) >> 25)
3384 || reg == G0 || reg == O7)
3385 break;
3386
3387 if (INSN_BIG_ENDIAN)
3388 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4);
3389 else
3390 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4);
3391 }
3392 }
3393 break;
3394
3395 case BFD_RELOC_SPARC_11:
3396 if (! in_signed_range (val, 0x7ff))
3397 as_bad_where (fixP->fx_file, fixP->fx_line,
3398 _("relocation overflow"));
3399 insn |= val & 0x7ff;
3400 break;
3401
3402 case BFD_RELOC_SPARC_10:
3403 if (! in_signed_range (val, 0x3ff))
3404 as_bad_where (fixP->fx_file, fixP->fx_line,
3405 _("relocation overflow"));
3406 insn |= val & 0x3ff;
3407 break;
3408
3409 case BFD_RELOC_SPARC_7:
3410 if (! in_bitfield_range (val, 0x7f))
3411 as_bad_where (fixP->fx_file, fixP->fx_line,
3412 _("relocation overflow"));
3413 insn |= val & 0x7f;
3414 break;
3415
3416 case BFD_RELOC_SPARC_6:
3417 if (! in_bitfield_range (val, 0x3f))
3418 as_bad_where (fixP->fx_file, fixP->fx_line,
3419 _("relocation overflow"));
3420 insn |= val & 0x3f;
3421 break;
3422
3423 case BFD_RELOC_SPARC_5:
3424 if (! in_bitfield_range (val, 0x1f))
3425 as_bad_where (fixP->fx_file, fixP->fx_line,
3426 _("relocation overflow"));
3427 insn |= val & 0x1f;
3428 break;
3429
3430 case BFD_RELOC_SPARC_WDISP10:
3431 if ((val & 3)
3432 || val >= 0x007fc
3433 || val <= -(offsetT) 0x808)
3434 as_bad_where (fixP->fx_file, fixP->fx_line,
3435 _("relocation overflow"));
3436 /* FIXME: The +1 deserves a comment. */
3437 val = (val >> 2) + 1;
3438 insn |= ((val & 0x300) << 11)
3439 | ((val & 0xff) << 5);
3440 break;
3441
3442 case BFD_RELOC_SPARC_WDISP16:
3443 if ((val & 3)
3444 || val >= 0x1fffc
3445 || val <= -(offsetT) 0x20008)
3446 as_bad_where (fixP->fx_file, fixP->fx_line,
3447 _("relocation overflow"));
3448 /* FIXME: The +1 deserves a comment. */
3449 val = (val >> 2) + 1;
3450 insn |= ((val & 0xc000) << 6) | (val & 0x3fff);
3451 break;
3452
3453 case BFD_RELOC_SPARC_WDISP19:
3454 if ((val & 3)
3455 || val >= 0xffffc
3456 || val <= -(offsetT) 0x100008)
3457 as_bad_where (fixP->fx_file, fixP->fx_line,
3458 _("relocation overflow"));
3459 /* FIXME: The +1 deserves a comment. */
3460 val = (val >> 2) + 1;
3461 insn |= val & 0x7ffff;
3462 break;
3463
3464 case BFD_RELOC_SPARC_HH22:
3465 val = BSR (val, 32);
3466 /* Fall through. */
3467
3468 case BFD_RELOC_SPARC_LM22:
3469 case BFD_RELOC_HI22:
3470 if (!fixP->fx_addsy)
3471 insn |= (val >> 10) & 0x3fffff;
3472 else
3473 /* FIXME: Need comment explaining why we do this. */
3474 insn &= ~0xffff;
3475 break;
3476
3477 case BFD_RELOC_SPARC22:
3478 if (val & ~0x003fffff)
3479 as_bad_where (fixP->fx_file, fixP->fx_line,
3480 _("relocation overflow"));
3481 insn |= (val & 0x3fffff);
3482 break;
3483
3484 case BFD_RELOC_SPARC_HM10:
3485 val = BSR (val, 32);
3486 /* Fall through. */
3487
3488 case BFD_RELOC_LO10:
3489 if (!fixP->fx_addsy)
3490 insn |= val & 0x3ff;
3491 else
3492 /* FIXME: Need comment explaining why we do this. */
3493 insn &= ~0xff;
3494 break;
3495
3496 case BFD_RELOC_SPARC_OLO10:
3497 val &= 0x3ff;
3498 val += fixP->tc_fix_data;
3499 /* Fall through. */
3500
3501 case BFD_RELOC_SPARC13:
3502 if (! in_signed_range (val, 0x1fff))
3503 as_bad_where (fixP->fx_file, fixP->fx_line,
3504 _("relocation overflow"));
3505 insn |= val & 0x1fff;
3506 break;
3507
3508 case BFD_RELOC_SPARC_WDISP22:
3509 val = (val >> 2) + 1;
3510 /* Fall through. */
3511 case BFD_RELOC_SPARC_BASE22:
3512 insn |= val & 0x3fffff;
3513 break;
3514
3515 case BFD_RELOC_SPARC_H34:
3516 if (!fixP->fx_addsy)
3517 {
3518 bfd_vma tval = val;
3519 tval >>= 12;
3520 insn |= tval & 0x3fffff;
3521 }
3522 break;
3523
3524 case BFD_RELOC_SPARC_H44:
3525 if (!fixP->fx_addsy)
3526 {
3527 bfd_vma tval = val;
3528 tval >>= 22;
3529 insn |= tval & 0x3fffff;
3530 }
3531 break;
3532
3533 case BFD_RELOC_SPARC_M44:
3534 if (!fixP->fx_addsy)
3535 insn |= (val >> 12) & 0x3ff;
3536 break;
3537
3538 case BFD_RELOC_SPARC_L44:
3539 if (!fixP->fx_addsy)
3540 insn |= val & 0xfff;
3541 break;
3542
3543 case BFD_RELOC_SPARC_HIX22:
3544 if (!fixP->fx_addsy)
3545 {
3546 val ^= ~(offsetT) 0;
3547 insn |= (val >> 10) & 0x3fffff;
3548 }
3549 break;
3550
3551 case BFD_RELOC_SPARC_LOX10:
3552 if (!fixP->fx_addsy)
3553 insn |= 0x1c00 | (val & 0x3ff);
3554 break;
3555
3556 case BFD_RELOC_NONE:
3557 default:
3558 as_bad_where (fixP->fx_file, fixP->fx_line,
3559 _("bad or unhandled relocation type: 0x%02x"),
3560 fixP->fx_r_type);
3561 break;
3562 }
3563
3564 if (INSN_BIG_ENDIAN)
3565 bfd_putb32 (insn, (unsigned char *) buf);
3566 else
3567 bfd_putl32 (insn, (unsigned char *) buf);
3568 }
3569
3570 /* Are we finished with this relocation now? */
3571 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
3572 fixP->fx_done = 1;
3573 }
3574
3575 /* Translate internal representation of relocation info to BFD target
3576 format. */
3577
3578 arelent **
3579 tc_gen_reloc (asection *section, fixS *fixp)
3580 {
3581 static arelent *relocs[3];
3582 arelent *reloc;
3583 bfd_reloc_code_real_type code;
3584
3585 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent));
3586 relocs[1] = NULL;
3587
3588 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3589 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
3590 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3591
3592 switch (fixp->fx_r_type)
3593 {
3594 case BFD_RELOC_16:
3595 case BFD_RELOC_32:
3596 case BFD_RELOC_HI22:
3597 case BFD_RELOC_LO10:
3598 case BFD_RELOC_32_PCREL_S2:
3599 case BFD_RELOC_SPARC13:
3600 case BFD_RELOC_SPARC22:
3601 case BFD_RELOC_SPARC_PC22:
3602 case BFD_RELOC_SPARC_PC10:
3603 case BFD_RELOC_SPARC_BASE13:
3604 case BFD_RELOC_SPARC_WDISP10:
3605 case BFD_RELOC_SPARC_WDISP16:
3606 case BFD_RELOC_SPARC_WDISP19:
3607 case BFD_RELOC_SPARC_WDISP22:
3608 case BFD_RELOC_64:
3609 case BFD_RELOC_SPARC_5:
3610 case BFD_RELOC_SPARC_6:
3611 case BFD_RELOC_SPARC_7:
3612 case BFD_RELOC_SPARC_10:
3613 case BFD_RELOC_SPARC_11:
3614 case BFD_RELOC_SPARC_HH22:
3615 case BFD_RELOC_SPARC_HM10:
3616 case BFD_RELOC_SPARC_LM22:
3617 case BFD_RELOC_SPARC_PC_HH22:
3618 case BFD_RELOC_SPARC_PC_HM10:
3619 case BFD_RELOC_SPARC_PC_LM22:
3620 case BFD_RELOC_SPARC_H34:
3621 case BFD_RELOC_SPARC_H44:
3622 case BFD_RELOC_SPARC_M44:
3623 case BFD_RELOC_SPARC_L44:
3624 case BFD_RELOC_SPARC_HIX22:
3625 case BFD_RELOC_SPARC_LOX10:
3626 case BFD_RELOC_SPARC_REV32:
3627 case BFD_RELOC_SPARC_OLO10:
3628 case BFD_RELOC_SPARC_UA16:
3629 case BFD_RELOC_SPARC_UA32:
3630 case BFD_RELOC_SPARC_UA64:
3631 case BFD_RELOC_8_PCREL:
3632 case BFD_RELOC_16_PCREL:
3633 case BFD_RELOC_32_PCREL:
3634 case BFD_RELOC_64_PCREL:
3635 case BFD_RELOC_SPARC_PLT32:
3636 case BFD_RELOC_SPARC_PLT64:
3637 case BFD_RELOC_VTABLE_ENTRY:
3638 case BFD_RELOC_VTABLE_INHERIT:
3639 case BFD_RELOC_SPARC_TLS_GD_HI22:
3640 case BFD_RELOC_SPARC_TLS_GD_LO10:
3641 case BFD_RELOC_SPARC_TLS_GD_ADD:
3642 case BFD_RELOC_SPARC_TLS_GD_CALL:
3643 case BFD_RELOC_SPARC_TLS_LDM_HI22:
3644 case BFD_RELOC_SPARC_TLS_LDM_LO10:
3645 case BFD_RELOC_SPARC_TLS_LDM_ADD:
3646 case BFD_RELOC_SPARC_TLS_LDM_CALL:
3647 case BFD_RELOC_SPARC_TLS_LDO_HIX22:
3648 case BFD_RELOC_SPARC_TLS_LDO_LOX10:
3649 case BFD_RELOC_SPARC_TLS_LDO_ADD:
3650 case BFD_RELOC_SPARC_TLS_IE_HI22:
3651 case BFD_RELOC_SPARC_TLS_IE_LO10:
3652 case BFD_RELOC_SPARC_TLS_IE_LD:
3653 case BFD_RELOC_SPARC_TLS_IE_LDX:
3654 case BFD_RELOC_SPARC_TLS_IE_ADD:
3655 case BFD_RELOC_SPARC_TLS_LE_HIX22:
3656 case BFD_RELOC_SPARC_TLS_LE_LOX10:
3657 case BFD_RELOC_SPARC_TLS_DTPOFF32:
3658 case BFD_RELOC_SPARC_TLS_DTPOFF64:
3659 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22:
3660 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10:
3661 case BFD_RELOC_SPARC_GOTDATA_OP:
3662 code = fixp->fx_r_type;
3663 break;
3664 default:
3665 abort ();
3666 return NULL;
3667 }
3668
3669 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3670 /* If we are generating PIC code, we need to generate a different
3671 set of relocs. */
3672
3673 #ifdef OBJ_ELF
3674 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3675 #else
3676 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3677 #endif
3678 #ifdef TE_VXWORKS
3679 #define GOTT_BASE "__GOTT_BASE__"
3680 #define GOTT_INDEX "__GOTT_INDEX__"
3681 #endif
3682
3683 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3684
3685 if (sparc_pic_code)
3686 {
3687 switch (code)
3688 {
3689 case BFD_RELOC_32_PCREL_S2:
3690 if (generic_force_reloc (fixp))
3691 code = BFD_RELOC_SPARC_WPLT30;
3692 break;
3693 case BFD_RELOC_HI22:
3694 code = BFD_RELOC_SPARC_GOT22;
3695 if (fixp->fx_addsy != NULL)
3696 {
3697 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3698 code = BFD_RELOC_SPARC_PC22;
3699 #ifdef TE_VXWORKS
3700 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3701 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3702 code = BFD_RELOC_HI22; /* Unchanged. */
3703 #endif
3704 }
3705 break;
3706 case BFD_RELOC_LO10:
3707 code = BFD_RELOC_SPARC_GOT10;
3708 if (fixp->fx_addsy != NULL)
3709 {
3710 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
3711 code = BFD_RELOC_SPARC_PC10;
3712 #ifdef TE_VXWORKS
3713 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
3714 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
3715 code = BFD_RELOC_LO10; /* Unchanged. */
3716 #endif
3717 }
3718 break;
3719 case BFD_RELOC_SPARC13:
3720 code = BFD_RELOC_SPARC_GOT13;
3721 break;
3722 default:
3723 break;
3724 }
3725 }
3726 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3727
3728 /* Nothing is aligned in DWARF debugging sections. */
3729 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING)
3730 switch (code)
3731 {
3732 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break;
3733 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break;
3734 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break;
3735 default: break;
3736 }
3737
3738 if (code == BFD_RELOC_SPARC_OLO10)
3739 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10);
3740 else
3741 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3742 if (reloc->howto == 0)
3743 {
3744 as_bad_where (fixp->fx_file, fixp->fx_line,
3745 _("internal error: can't export reloc type %d (`%s')"),
3746 fixp->fx_r_type, bfd_get_reloc_code_name (code));
3747 xfree (reloc);
3748 relocs[0] = NULL;
3749 return relocs;
3750 }
3751
3752 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3753 #ifdef OBJ_AOUT
3754
3755 if (reloc->howto->pc_relative == 0
3756 || code == BFD_RELOC_SPARC_PC10
3757 || code == BFD_RELOC_SPARC_PC22)
3758 reloc->addend = fixp->fx_addnumber;
3759 else if (sparc_pic_code
3760 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2
3761 && fixp->fx_addsy != NULL
3762 && (S_IS_EXTERNAL (fixp->fx_addsy)
3763 || S_IS_WEAK (fixp->fx_addsy))
3764 && S_IS_DEFINED (fixp->fx_addsy)
3765 && ! S_IS_COMMON (fixp->fx_addsy))
3766 reloc->addend = fixp->fx_addnumber;
3767 else
3768 reloc->addend = fixp->fx_offset - reloc->address;
3769
3770 #else /* elf or coff */
3771
3772 if (code != BFD_RELOC_32_PCREL_S2
3773 && code != BFD_RELOC_SPARC_WDISP22
3774 && code != BFD_RELOC_SPARC_WDISP16
3775 && code != BFD_RELOC_SPARC_WDISP19
3776 && code != BFD_RELOC_SPARC_WDISP10
3777 && code != BFD_RELOC_SPARC_WPLT30
3778 && code != BFD_RELOC_SPARC_TLS_GD_CALL
3779 && code != BFD_RELOC_SPARC_TLS_LDM_CALL)
3780 reloc->addend = fixp->fx_addnumber;
3781 else if (symbol_section_p (fixp->fx_addsy))
3782 reloc->addend = (section->vma
3783 + fixp->fx_addnumber
3784 + md_pcrel_from (fixp));
3785 else
3786 reloc->addend = fixp->fx_offset;
3787 #endif
3788
3789 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3790 on the same location. */
3791 if (code == BFD_RELOC_SPARC_OLO10)
3792 {
3793 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent));
3794 relocs[2] = NULL;
3795
3796 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3797 *reloc->sym_ptr_ptr
3798 = symbol_get_bfdsym (section_symbol (absolute_section));
3799 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
3800 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
3801 reloc->addend = fixp->tc_fix_data;
3802 }
3803
3804 return relocs;
3805 }
3806 \f
3807 /* We have no need to default values of symbols. */
3808
3809 symbolS *
3810 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
3811 {
3812 return 0;
3813 }
3814
3815 /* Round up a section size to the appropriate boundary. */
3816
3817 valueT
3818 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
3819 {
3820 #ifndef OBJ_ELF
3821 /* This is not right for ELF; a.out wants it, and COFF will force
3822 the alignment anyways. */
3823 valueT align = ((valueT) 1
3824 << (valueT) bfd_get_section_alignment (stdoutput, segment));
3825 valueT newsize;
3826
3827 /* Turn alignment value into a mask. */
3828 align--;
3829 newsize = (size + align) & ~align;
3830 return newsize;
3831 #else
3832 return size;
3833 #endif
3834 }
3835
3836 /* Exactly what point is a PC-relative offset relative TO?
3837 On the sparc, they're relative to the address of the offset, plus
3838 its size. This gets us to the following instruction.
3839 (??? Is this right? FIXME-SOON) */
3840 long
3841 md_pcrel_from (fixS *fixP)
3842 {
3843 long ret;
3844
3845 ret = fixP->fx_where + fixP->fx_frag->fr_address;
3846 if (! sparc_pic_code
3847 || fixP->fx_addsy == NULL
3848 || symbol_section_p (fixP->fx_addsy))
3849 ret += fixP->fx_size;
3850 return ret;
3851 }
3852 \f
3853 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3854 of two. */
3855
3856 static int
3857 mylog2 (int value)
3858 {
3859 int shift;
3860
3861 if (value <= 0)
3862 return -1;
3863
3864 for (shift = 0; (value & 1) == 0; value >>= 1)
3865 ++shift;
3866
3867 return (value == 1) ? shift : -1;
3868 }
3869
3870 /* Sort of like s_lcomm. */
3871
3872 #ifndef OBJ_ELF
3873 static int max_alignment = 15;
3874 #endif
3875
3876 static void
3877 s_reserve (int ignore ATTRIBUTE_UNUSED)
3878 {
3879 char *name;
3880 char *p;
3881 char c;
3882 int align;
3883 int size;
3884 int temp;
3885 symbolS *symbolP;
3886
3887 name = input_line_pointer;
3888 c = get_symbol_end ();
3889 p = input_line_pointer;
3890 *p = c;
3891 SKIP_WHITESPACE ();
3892
3893 if (*input_line_pointer != ',')
3894 {
3895 as_bad (_("Expected comma after name"));
3896 ignore_rest_of_line ();
3897 return;
3898 }
3899
3900 ++input_line_pointer;
3901
3902 if ((size = get_absolute_expression ()) < 0)
3903 {
3904 as_bad (_("BSS length (%d.) <0! Ignored."), size);
3905 ignore_rest_of_line ();
3906 return;
3907 } /* Bad length. */
3908
3909 *p = 0;
3910 symbolP = symbol_find_or_make (name);
3911 *p = c;
3912
3913 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0
3914 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0)
3915 {
3916 as_bad (_("bad .reserve segment -- expected BSS segment"));
3917 return;
3918 }
3919
3920 if (input_line_pointer[2] == '.')
3921 input_line_pointer += 7;
3922 else
3923 input_line_pointer += 6;
3924 SKIP_WHITESPACE ();
3925
3926 if (*input_line_pointer == ',')
3927 {
3928 ++input_line_pointer;
3929
3930 SKIP_WHITESPACE ();
3931 if (*input_line_pointer == '\n')
3932 {
3933 as_bad (_("missing alignment"));
3934 ignore_rest_of_line ();
3935 return;
3936 }
3937
3938 align = (int) get_absolute_expression ();
3939
3940 #ifndef OBJ_ELF
3941 if (align > max_alignment)
3942 {
3943 align = max_alignment;
3944 as_warn (_("alignment too large; assuming %d"), align);
3945 }
3946 #endif
3947
3948 if (align < 0)
3949 {
3950 as_bad (_("negative alignment"));
3951 ignore_rest_of_line ();
3952 return;
3953 }
3954
3955 if (align != 0)
3956 {
3957 temp = mylog2 (align);
3958 if (temp < 0)
3959 {
3960 as_bad (_("alignment not a power of 2"));
3961 ignore_rest_of_line ();
3962 return;
3963 }
3964
3965 align = temp;
3966 }
3967
3968 record_alignment (bss_section, align);
3969 }
3970 else
3971 align = 0;
3972
3973 if (!S_IS_DEFINED (symbolP)
3974 #ifdef OBJ_AOUT
3975 && S_GET_OTHER (symbolP) == 0
3976 && S_GET_DESC (symbolP) == 0
3977 #endif
3978 )
3979 {
3980 if (! need_pass_2)
3981 {
3982 char *pfrag;
3983 segT current_seg = now_seg;
3984 subsegT current_subseg = now_subseg;
3985
3986 /* Switch to bss. */
3987 subseg_set (bss_section, 1);
3988
3989 if (align)
3990 /* Do alignment. */
3991 frag_align (align, 0, 0);
3992
3993 /* Detach from old frag. */
3994 if (S_GET_SEGMENT (symbolP) == bss_section)
3995 symbol_get_frag (symbolP)->fr_symbol = NULL;
3996
3997 symbol_set_frag (symbolP, frag_now);
3998 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
3999 (offsetT) size, (char *) 0);
4000 *pfrag = 0;
4001
4002 S_SET_SEGMENT (symbolP, bss_section);
4003
4004 subseg_set (current_seg, current_subseg);
4005
4006 #ifdef OBJ_ELF
4007 S_SET_SIZE (symbolP, size);
4008 #endif
4009 }
4010 }
4011 else
4012 {
4013 as_warn (_("Ignoring attempt to re-define symbol %s"),
4014 S_GET_NAME (symbolP));
4015 }
4016
4017 demand_empty_rest_of_line ();
4018 }
4019
4020 static void
4021 s_common (int ignore ATTRIBUTE_UNUSED)
4022 {
4023 char *name;
4024 char c;
4025 char *p;
4026 offsetT temp, size;
4027 symbolS *symbolP;
4028
4029 name = input_line_pointer;
4030 c = get_symbol_end ();
4031 /* Just after name is now '\0'. */
4032 p = input_line_pointer;
4033 *p = c;
4034 SKIP_WHITESPACE ();
4035 if (*input_line_pointer != ',')
4036 {
4037 as_bad (_("Expected comma after symbol-name"));
4038 ignore_rest_of_line ();
4039 return;
4040 }
4041
4042 /* Skip ','. */
4043 input_line_pointer++;
4044
4045 if ((temp = get_absolute_expression ()) < 0)
4046 {
4047 as_bad (_(".COMMon length (%lu) out of range ignored"),
4048 (unsigned long) temp);
4049 ignore_rest_of_line ();
4050 return;
4051 }
4052 size = temp;
4053 *p = 0;
4054 symbolP = symbol_find_or_make (name);
4055 *p = c;
4056 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP))
4057 {
4058 as_bad (_("Ignoring attempt to re-define symbol"));
4059 ignore_rest_of_line ();
4060 return;
4061 }
4062 if (S_GET_VALUE (symbolP) != 0)
4063 {
4064 if (S_GET_VALUE (symbolP) != (valueT) size)
4065 {
4066 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4067 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size);
4068 }
4069 }
4070 else
4071 {
4072 #ifndef OBJ_ELF
4073 S_SET_VALUE (symbolP, (valueT) size);
4074 S_SET_EXTERNAL (symbolP);
4075 #endif
4076 }
4077 know (symbol_get_frag (symbolP) == &zero_address_frag);
4078 if (*input_line_pointer != ',')
4079 {
4080 as_bad (_("Expected comma after common length"));
4081 ignore_rest_of_line ();
4082 return;
4083 }
4084 input_line_pointer++;
4085 SKIP_WHITESPACE ();
4086 if (*input_line_pointer != '"')
4087 {
4088 temp = get_absolute_expression ();
4089
4090 #ifndef OBJ_ELF
4091 if (temp > max_alignment)
4092 {
4093 temp = max_alignment;
4094 as_warn (_("alignment too large; assuming %ld"), (long) temp);
4095 }
4096 #endif
4097
4098 if (temp < 0)
4099 {
4100 as_bad (_("negative alignment"));
4101 ignore_rest_of_line ();
4102 return;
4103 }
4104
4105 #ifdef OBJ_ELF
4106 if (symbol_get_obj (symbolP)->local)
4107 {
4108 segT old_sec;
4109 int old_subsec;
4110 int align;
4111
4112 old_sec = now_seg;
4113 old_subsec = now_subseg;
4114
4115 if (temp == 0)
4116 align = 0;
4117 else
4118 align = mylog2 (temp);
4119
4120 if (align < 0)
4121 {
4122 as_bad (_("alignment not a power of 2"));
4123 ignore_rest_of_line ();
4124 return;
4125 }
4126
4127 record_alignment (bss_section, align);
4128 subseg_set (bss_section, 0);
4129 if (align)
4130 frag_align (align, 0, 0);
4131 if (S_GET_SEGMENT (symbolP) == bss_section)
4132 symbol_get_frag (symbolP)->fr_symbol = 0;
4133 symbol_set_frag (symbolP, frag_now);
4134 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP,
4135 (offsetT) size, (char *) 0);
4136 *p = 0;
4137 S_SET_SEGMENT (symbolP, bss_section);
4138 S_CLEAR_EXTERNAL (symbolP);
4139 S_SET_SIZE (symbolP, size);
4140 subseg_set (old_sec, old_subsec);
4141 }
4142 else
4143 #endif /* OBJ_ELF */
4144 {
4145 allocate_common:
4146 S_SET_VALUE (symbolP, (valueT) size);
4147 #ifdef OBJ_ELF
4148 S_SET_ALIGN (symbolP, temp);
4149 S_SET_SIZE (symbolP, size);
4150 #endif
4151 S_SET_EXTERNAL (symbolP);
4152 S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
4153 }
4154 }
4155 else
4156 {
4157 input_line_pointer++;
4158 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4159 if (*input_line_pointer == '.')
4160 input_line_pointer++;
4161 /* @@ Some say data, some say bss. */
4162 if (strncmp (input_line_pointer, "bss\"", 4)
4163 && strncmp (input_line_pointer, "data\"", 5))
4164 {
4165 while (*--input_line_pointer != '"')
4166 ;
4167 input_line_pointer--;
4168 goto bad_common_segment;
4169 }
4170 while (*input_line_pointer++ != '"')
4171 ;
4172 goto allocate_common;
4173 }
4174
4175 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
4176
4177 demand_empty_rest_of_line ();
4178 return;
4179
4180 {
4181 bad_common_segment:
4182 p = input_line_pointer;
4183 while (*p && *p != '\n')
4184 p++;
4185 c = *p;
4186 *p = '\0';
4187 as_bad (_("bad .common segment %s"), input_line_pointer + 1);
4188 *p = c;
4189 input_line_pointer = p;
4190 ignore_rest_of_line ();
4191 return;
4192 }
4193 }
4194
4195 /* Handle the .empty pseudo-op. This suppresses the warnings about
4196 invalid delay slot usage. */
4197
4198 static void
4199 s_empty (int ignore ATTRIBUTE_UNUSED)
4200 {
4201 /* The easy way to implement is to just forget about the last
4202 instruction. */
4203 last_insn = NULL;
4204 }
4205
4206 static void
4207 s_seg (int ignore ATTRIBUTE_UNUSED)
4208 {
4209
4210 if (strncmp (input_line_pointer, "\"text\"", 6) == 0)
4211 {
4212 input_line_pointer += 6;
4213 s_text (0);
4214 return;
4215 }
4216 if (strncmp (input_line_pointer, "\"data\"", 6) == 0)
4217 {
4218 input_line_pointer += 6;
4219 s_data (0);
4220 return;
4221 }
4222 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0)
4223 {
4224 input_line_pointer += 7;
4225 s_data1 ();
4226 return;
4227 }
4228 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0)
4229 {
4230 input_line_pointer += 5;
4231 /* We only support 2 segments -- text and data -- for now, so
4232 things in the "bss segment" will have to go into data for now.
4233 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4234 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */
4235 return;
4236 }
4237 as_bad (_("Unknown segment type"));
4238 demand_empty_rest_of_line ();
4239 }
4240
4241 static void
4242 s_data1 (void)
4243 {
4244 subseg_set (data_section, 1);
4245 demand_empty_rest_of_line ();
4246 }
4247
4248 static void
4249 s_proc (int ignore ATTRIBUTE_UNUSED)
4250 {
4251 while (!is_end_of_line[(unsigned char) *input_line_pointer])
4252 {
4253 ++input_line_pointer;
4254 }
4255 ++input_line_pointer;
4256 }
4257
4258 /* This static variable is set by s_uacons to tell sparc_cons_align
4259 that the expression does not need to be aligned. */
4260
4261 static int sparc_no_align_cons = 0;
4262
4263 /* This static variable is set by sparc_cons to emit requested types
4264 of relocations in cons_fix_new_sparc. */
4265
4266 static const char *sparc_cons_special_reloc;
4267
4268 /* This handles the unaligned space allocation pseudo-ops, such as
4269 .uaword. .uaword is just like .word, but the value does not need
4270 to be aligned. */
4271
4272 static void
4273 s_uacons (int bytes)
4274 {
4275 /* Tell sparc_cons_align not to align this value. */
4276 sparc_no_align_cons = 1;
4277 cons (bytes);
4278 sparc_no_align_cons = 0;
4279 }
4280
4281 /* This handles the native word allocation pseudo-op .nword.
4282 For sparc_arch_size 32 it is equivalent to .word, for
4283 sparc_arch_size 64 it is equivalent to .xword. */
4284
4285 static void
4286 s_ncons (int bytes ATTRIBUTE_UNUSED)
4287 {
4288 cons (sparc_arch_size == 32 ? 4 : 8);
4289 }
4290
4291 #ifdef OBJ_ELF
4292 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4293 global register.
4294 The syntax is:
4295
4296 .register %g[2367],{#scratch|symbolname|#ignore}
4297 */
4298
4299 static void
4300 s_register (int ignore ATTRIBUTE_UNUSED)
4301 {
4302 char c;
4303 int reg;
4304 int flags;
4305 const char *regname;
4306
4307 if (input_line_pointer[0] != '%'
4308 || input_line_pointer[1] != 'g'
4309 || ((input_line_pointer[2] & ~1) != '2'
4310 && (input_line_pointer[2] & ~1) != '6')
4311 || input_line_pointer[3] != ',')
4312 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4313 reg = input_line_pointer[2] - '0';
4314 input_line_pointer += 4;
4315
4316 if (*input_line_pointer == '#')
4317 {
4318 ++input_line_pointer;
4319 regname = input_line_pointer;
4320 c = get_symbol_end ();
4321 if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
4322 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4323 if (regname[0] == 'i')
4324 regname = NULL;
4325 else
4326 regname = "";
4327 }
4328 else
4329 {
4330 regname = input_line_pointer;
4331 c = get_symbol_end ();
4332 }
4333 if (sparc_arch_size == 64)
4334 {
4335 if (globals[reg])
4336 {
4337 if ((regname && globals[reg] != (symbolS *) 1
4338 && strcmp (S_GET_NAME (globals[reg]), regname))
4339 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1)))
4340 as_bad (_("redefinition of global register"));
4341 }
4342 else
4343 {
4344 if (regname == NULL)
4345 globals[reg] = (symbolS *) 1;
4346 else
4347 {
4348 if (*regname)
4349 {
4350 if (symbol_find (regname))
4351 as_bad (_("Register symbol %s already defined."),
4352 regname);
4353 }
4354 globals[reg] = symbol_make (regname);
4355 flags = symbol_get_bfdsym (globals[reg])->flags;
4356 if (! *regname)
4357 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK);
4358 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK)))
4359 flags |= BSF_GLOBAL;
4360 symbol_get_bfdsym (globals[reg])->flags = flags;
4361 S_SET_VALUE (globals[reg], (valueT) reg);
4362 S_SET_ALIGN (globals[reg], reg);
4363 S_SET_SIZE (globals[reg], 0);
4364 /* Although we actually want undefined_section here,
4365 we have to use absolute_section, because otherwise
4366 generic as code will make it a COM section.
4367 We fix this up in sparc_adjust_symtab. */
4368 S_SET_SEGMENT (globals[reg], absolute_section);
4369 S_SET_OTHER (globals[reg], 0);
4370 elf_symbol (symbol_get_bfdsym (globals[reg]))
4371 ->internal_elf_sym.st_info =
4372 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER);
4373 elf_symbol (symbol_get_bfdsym (globals[reg]))
4374 ->internal_elf_sym.st_shndx = SHN_UNDEF;
4375 }
4376 }
4377 }
4378
4379 *input_line_pointer = c;
4380
4381 demand_empty_rest_of_line ();
4382 }
4383
4384 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4385 symbols which need it. */
4386
4387 void
4388 sparc_adjust_symtab (void)
4389 {
4390 symbolS *sym;
4391
4392 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4393 {
4394 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4395 ->internal_elf_sym.st_info) != STT_REGISTER)
4396 continue;
4397
4398 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym))
4399 ->internal_elf_sym.st_shndx != SHN_UNDEF))
4400 continue;
4401
4402 S_SET_SEGMENT (sym, undefined_section);
4403 }
4404 }
4405 #endif
4406
4407 /* If the --enforce-aligned-data option is used, we require .word,
4408 et. al., to be aligned correctly. We do it by setting up an
4409 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4410 no unexpected alignment was introduced.
4411
4412 The SunOS and Solaris native assemblers enforce aligned data by
4413 default. We don't want to do that, because gcc can deliberately
4414 generate misaligned data if the packed attribute is used. Instead,
4415 we permit misaligned data by default, and permit the user to set an
4416 option to check for it. */
4417
4418 void
4419 sparc_cons_align (int nbytes)
4420 {
4421 int nalign;
4422
4423 /* Only do this if we are enforcing aligned data. */
4424 if (! enforce_aligned_data)
4425 return;
4426
4427 /* Don't align if this is an unaligned pseudo-op. */
4428 if (sparc_no_align_cons)
4429 return;
4430
4431 nalign = mylog2 (nbytes);
4432 if (nalign == 0)
4433 return;
4434
4435 gas_assert (nalign > 0);
4436
4437 if (now_seg == absolute_section)
4438 {
4439 if ((abs_section_offset & ((1 << nalign) - 1)) != 0)
4440 as_bad (_("misaligned data"));
4441 return;
4442 }
4443
4444 frag_var (rs_align_test, 1, 1, (relax_substateT) 0,
4445 (symbolS *) NULL, (offsetT) nalign, (char *) NULL);
4446
4447 record_alignment (now_seg, nalign);
4448 }
4449
4450 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4451
4452 void
4453 sparc_handle_align (fragS *fragp)
4454 {
4455 int count, fix;
4456 char *p;
4457
4458 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
4459
4460 switch (fragp->fr_type)
4461 {
4462 case rs_align_test:
4463 if (count != 0)
4464 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
4465 break;
4466
4467 case rs_align_code:
4468 p = fragp->fr_literal + fragp->fr_fix;
4469 fix = 0;
4470
4471 if (count & 3)
4472 {
4473 fix = count & 3;
4474 memset (p, 0, fix);
4475 p += fix;
4476 count -= fix;
4477 }
4478
4479 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8)
4480 {
4481 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */
4482 if (INSN_BIG_ENDIAN)
4483 number_to_chars_bigendian (p, wval, 4);
4484 else
4485 number_to_chars_littleendian (p, wval, 4);
4486 p += 4;
4487 count -= 4;
4488 fix += 4;
4489 }
4490
4491 if (INSN_BIG_ENDIAN)
4492 number_to_chars_bigendian (p, 0x01000000, 4);
4493 else
4494 number_to_chars_littleendian (p, 0x01000000, 4);
4495
4496 fragp->fr_fix += fix;
4497 fragp->fr_var = 4;
4498 break;
4499
4500 default:
4501 break;
4502 }
4503 }
4504
4505 #ifdef OBJ_ELF
4506 /* Some special processing for a Sparc ELF file. */
4507
4508 void
4509 sparc_elf_final_processing (void)
4510 {
4511 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4512 sort of BFD interface for this. */
4513 if (sparc_arch_size == 64)
4514 {
4515 switch (sparc_memory_model)
4516 {
4517 case MM_RMO:
4518 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO;
4519 break;
4520 case MM_PSO:
4521 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO;
4522 break;
4523 default:
4524 break;
4525 }
4526 }
4527 else if (current_architecture >= SPARC_OPCODE_ARCH_V9)
4528 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS;
4529 if (current_architecture == SPARC_OPCODE_ARCH_V9A)
4530 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1;
4531 else if (current_architecture == SPARC_OPCODE_ARCH_V9B)
4532 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3;
4533 }
4534
4535 void
4536 sparc_cons (expressionS *exp, int size)
4537 {
4538 char *save;
4539
4540 SKIP_WHITESPACE ();
4541 sparc_cons_special_reloc = NULL;
4542 save = input_line_pointer;
4543 if (input_line_pointer[0] == '%'
4544 && input_line_pointer[1] == 'r'
4545 && input_line_pointer[2] == '_')
4546 {
4547 if (strncmp (input_line_pointer + 3, "disp", 4) == 0)
4548 {
4549 input_line_pointer += 7;
4550 sparc_cons_special_reloc = "disp";
4551 }
4552 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0)
4553 {
4554 if (size != 4 && size != 8)
4555 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size);
4556 else
4557 {
4558 input_line_pointer += 6;
4559 sparc_cons_special_reloc = "plt";
4560 }
4561 }
4562 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0)
4563 {
4564 if (size != 4 && size != 8)
4565 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size);
4566 else
4567 {
4568 input_line_pointer += 13;
4569 sparc_cons_special_reloc = "tls_dtpoff";
4570 }
4571 }
4572 if (sparc_cons_special_reloc)
4573 {
4574 int bad = 0;
4575
4576 switch (size)
4577 {
4578 case 1:
4579 if (*input_line_pointer != '8')
4580 bad = 1;
4581 input_line_pointer--;
4582 break;
4583 case 2:
4584 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6')
4585 bad = 1;
4586 break;
4587 case 4:
4588 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2')
4589 bad = 1;
4590 break;
4591 case 8:
4592 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4')
4593 bad = 1;
4594 break;
4595 default:
4596 bad = 1;
4597 break;
4598 }
4599
4600 if (bad)
4601 {
4602 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4603 sparc_cons_special_reloc, size * 8, size);
4604 }
4605 else
4606 {
4607 input_line_pointer += 2;
4608 if (*input_line_pointer != '(')
4609 {
4610 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4611 sparc_cons_special_reloc, size * 8);
4612 bad = 1;
4613 }
4614 }
4615
4616 if (bad)
4617 {
4618 input_line_pointer = save;
4619 sparc_cons_special_reloc = NULL;
4620 }
4621 else
4622 {
4623 int c;
4624 char *end = ++input_line_pointer;
4625 int npar = 0;
4626
4627 while (! is_end_of_line[(c = *end)])
4628 {
4629 if (c == '(')
4630 npar++;
4631 else if (c == ')')
4632 {
4633 if (!npar)
4634 break;
4635 npar--;
4636 }
4637 end++;
4638 }
4639
4640 if (c != ')')
4641 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4642 sparc_cons_special_reloc, size * 8);
4643 else
4644 {
4645 *end = '\0';
4646 expression (exp);
4647 *end = c;
4648 if (input_line_pointer != end)
4649 {
4650 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4651 sparc_cons_special_reloc, size * 8);
4652 }
4653 else
4654 {
4655 input_line_pointer++;
4656 SKIP_WHITESPACE ();
4657 c = *input_line_pointer;
4658 if (! is_end_of_line[c] && c != ',')
4659 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4660 sparc_cons_special_reloc, size * 8);
4661 }
4662 }
4663 }
4664 }
4665 }
4666 if (sparc_cons_special_reloc == NULL)
4667 expression (exp);
4668 }
4669
4670 #endif
4671
4672 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4673 reloc for a cons. We could use the definition there, except that
4674 we want to handle little endian relocs specially. */
4675
4676 void
4677 cons_fix_new_sparc (fragS *frag,
4678 int where,
4679 unsigned int nbytes,
4680 expressionS *exp)
4681 {
4682 bfd_reloc_code_real_type r;
4683
4684 r = (nbytes == 1 ? BFD_RELOC_8 :
4685 (nbytes == 2 ? BFD_RELOC_16 :
4686 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64)));
4687
4688 if (target_little_endian_data
4689 && nbytes == 4
4690 && now_seg->flags & SEC_ALLOC)
4691 r = BFD_RELOC_SPARC_REV32;
4692
4693 if (sparc_cons_special_reloc)
4694 {
4695 if (*sparc_cons_special_reloc == 'd')
4696 switch (nbytes)
4697 {
4698 case 1: r = BFD_RELOC_8_PCREL; break;
4699 case 2: r = BFD_RELOC_16_PCREL; break;
4700 case 4: r = BFD_RELOC_32_PCREL; break;
4701 case 8: r = BFD_RELOC_64_PCREL; break;
4702 default: abort ();
4703 }
4704 else if (*sparc_cons_special_reloc == 'p')
4705 switch (nbytes)
4706 {
4707 case 4: r = BFD_RELOC_SPARC_PLT32; break;
4708 case 8: r = BFD_RELOC_SPARC_PLT64; break;
4709 }
4710 else
4711 switch (nbytes)
4712 {
4713 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break;
4714 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break;
4715 }
4716 }
4717 else if (sparc_no_align_cons)
4718 {
4719 switch (nbytes)
4720 {
4721 case 2: r = BFD_RELOC_SPARC_UA16; break;
4722 case 4: r = BFD_RELOC_SPARC_UA32; break;
4723 case 8: r = BFD_RELOC_SPARC_UA64; break;
4724 default: abort ();
4725 }
4726 }
4727
4728 fix_new_exp (frag, where, (int) nbytes, exp, 0, r);
4729 sparc_cons_special_reloc = NULL;
4730 }
4731
4732 void
4733 sparc_cfi_frame_initial_instructions (void)
4734 {
4735 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0);
4736 }
4737
4738 int
4739 sparc_regname_to_dw2regnum (char *regname)
4740 {
4741 char *p, *q;
4742
4743 if (!regname[0])
4744 return -1;
4745
4746 q = "goli";
4747 p = strchr (q, regname[0]);
4748 if (p)
4749 {
4750 if (regname[1] < '0' || regname[1] > '8' || regname[2])
4751 return -1;
4752 return (p - q) * 8 + regname[1] - '0';
4753 }
4754 if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
4755 return 14;
4756 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
4757 return 30;
4758 if (regname[0] == 'f' || regname[0] == 'r')
4759 {
4760 unsigned int regnum;
4761
4762 regnum = strtoul (regname + 1, &q, 10);
4763 if (p == q || *q)
4764 return -1;
4765 if (regnum >= ((regname[0] == 'f'
4766 && SPARC_OPCODE_ARCH_V9_P (max_architecture))
4767 ? 64 : 32))
4768 return -1;
4769 if (regname[0] == 'f')
4770 {
4771 regnum += 32;
4772 if (regnum >= 64 && (regnum & 1))
4773 return -1;
4774 }
4775 return regnum;
4776 }
4777 return -1;
4778 }
4779
4780 void
4781 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes)
4782 {
4783 sparc_cons_special_reloc = "disp";
4784 sparc_no_align_cons = 1;
4785 emit_expr (exp, nbytes);
4786 sparc_no_align_cons = 0;
4787 sparc_cons_special_reloc = NULL;
4788 }
GDB Binutils - Deliverables
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