1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public
19 License along with GAS; see the file COPYING. If not, write
20 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
27 #include "opcode/sparc.h"
28 #include "dw2gencfi.h"
31 #include "elf/sparc.h"
32 #include "dwarf2dbg.h"
35 /* Some ancient Sun C compilers would not take such hex constants as
36 unsigned, and would end up sign-extending them to form an offsetT,
37 so use these constants instead. */
38 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
39 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
41 static int sparc_ip (char *, const struct sparc_opcode
**);
42 static int parse_keyword_arg (int (*) (const char *), char **, int *);
43 static int parse_const_expr_arg (char **, int *);
44 static int get_expression (char *);
46 /* Default architecture. */
47 /* ??? The default value should be V8, but sparclite support was added
48 by making it the default. GCC now passes -Asparclite, so maybe sometime in
49 the future we can set this to V8. */
51 #define DEFAULT_ARCH "sparclite"
53 static char *default_arch
= DEFAULT_ARCH
;
55 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
57 static int default_init_p
;
59 /* Current architecture. We don't bump up unless necessary. */
60 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
62 /* The maximum architecture level we can bump up to.
63 In a 32 bit environment, don't allow bumping up to v9 by default.
64 The native assembler works this way. The user is required to pass
65 an explicit argument before we'll create v9 object files. However, if
66 we don't see any v9 insns, a v8plus object file is not created. */
67 static enum sparc_opcode_arch_val max_architecture
;
69 /* Either 32 or 64, selects file format. */
70 static int sparc_arch_size
;
71 /* Initial (default) value, recorded separately in case a user option
72 changes the value before md_show_usage is called. */
73 static int default_arch_size
;
76 /* The currently selected v9 memory model. Currently only used for
78 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
81 /* Bitmask of instruction types seen so far, used to populate the
82 GNU attributes section with hwcap information. */
83 static int hwcap_seen
;
87 static int hwcap_allowed
;
89 static int architecture_requested
;
90 static int warn_on_bump
;
92 /* If warn_on_bump and the needed architecture is higher than this
93 architecture, issue a warning. */
94 static enum sparc_opcode_arch_val warn_after_architecture
;
96 /* Non-zero if as should generate error if an undeclared g[23] register
97 has been used in -64. */
98 static int no_undeclared_regs
;
100 /* Non-zero if we should try to relax jumps and calls. */
101 static int sparc_relax
;
103 /* Non-zero if we are generating PIC code. */
106 /* Non-zero if we should give an error when misaligned data is seen. */
107 static int enforce_aligned_data
;
109 extern int target_big_endian
;
111 static int target_little_endian_data
;
113 /* Symbols for global registers on v9. */
114 static symbolS
*globals
[8];
116 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
117 int sparc_cie_data_alignment
;
119 /* V9 and 86x have big and little endian data, but instructions are always big
120 endian. The sparclet has bi-endian support but both data and insns have
121 the same endianness. Global `target_big_endian' is used for data.
122 The following macro is used for instructions. */
123 #ifndef INSN_BIG_ENDIAN
124 #define INSN_BIG_ENDIAN (target_big_endian \
125 || default_arch_type == sparc86x \
126 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
129 /* Handle of the OPCODE hash table. */
130 static struct hash_control
*op_hash
;
132 static void s_data1 (void);
133 static void s_seg (int);
134 static void s_proc (int);
135 static void s_reserve (int);
136 static void s_common (int);
137 static void s_empty (int);
138 static void s_uacons (int);
139 static void s_ncons (int);
141 static void s_register (int);
144 const pseudo_typeS md_pseudo_table
[] =
146 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
147 {"common", s_common
, 0},
148 {"empty", s_empty
, 0},
149 {"global", s_globl
, 0},
151 {"nword", s_ncons
, 0},
152 {"optim", s_ignore
, 0},
154 {"reserve", s_reserve
, 0},
156 {"skip", s_space
, 0},
159 {"uahalf", s_uacons
, 2},
160 {"uaword", s_uacons
, 4},
161 {"uaxword", s_uacons
, 8},
163 /* These are specific to sparc/svr4. */
164 {"2byte", s_uacons
, 2},
165 {"4byte", s_uacons
, 4},
166 {"8byte", s_uacons
, 8},
167 {"register", s_register
, 0},
172 /* This array holds the chars that always start a comment. If the
173 pre-processor is disabled, these aren't very useful. */
174 const char comment_chars
[] = "!"; /* JF removed '|' from
177 /* This array holds the chars that only start a comment at the beginning of
178 a line. If the line seems to have the form '# 123 filename'
179 .line and .file directives will appear in the pre-processed output. */
180 /* Note that input_file.c hand checks for '#' at the beginning of the
181 first line of the input file. This is because the compiler outputs
182 #NO_APP at the beginning of its output. */
183 /* Also note that comments started like this one will always
184 work if '/' isn't otherwise defined. */
185 const char line_comment_chars
[] = "#";
187 const char line_separator_chars
[] = ";";
189 /* Chars that can be used to separate mant from exp in floating point
191 const char EXP_CHARS
[] = "eE";
193 /* Chars that mean this number is a floating point constant.
196 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
198 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
199 changed in read.c. Ideally it shouldn't have to know about it at all,
200 but nothing is ideal around here. */
202 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
207 unsigned long opcode
;
208 struct nlist
*nlistp
;
212 bfd_reloc_code_real_type reloc
;
215 struct sparc_it the_insn
, set_insn
;
217 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
219 /* Table of arguments to -A.
220 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
221 for this use. That table is for opcodes only. This table is for opcodes
224 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
225 v8plusa
, v9
, v9a
, v9b
, v9_64
};
227 static struct sparc_arch
{
230 enum sparc_arch_types arch_type
;
231 /* Default word size, as specified during configuration.
232 A value of zero means can't be used to specify default architecture. */
233 int default_arch_size
;
234 /* Allowable arg to -A? */
237 } sparc_arch_table
[] = {
238 { "v6", "v6", v6
, 0, 1, 0 },
239 { "v7", "v7", v7
, 0, 1, 0 },
240 { "v8", "v8", v8
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
241 { "v8a", "v8", v8
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
242 { "sparc", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
},
243 { "sparcvis", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
},
244 { "sparcvis2", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
},
245 { "sparcfmaf", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
},
246 { "sparcima", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_IMA
},
247 { "sparcvis3", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
248 { "sparc4", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
249 { "sparcvis3r", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
},
250 { "sparclet", "sparclet", sparclet
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
251 { "sparclite", "sparclite", sparclite
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
252 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
},
253 { "v8plus", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
},
254 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
},
255 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
},
256 { "v8plusc", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
},
257 { "v8plusd", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
258 { "v8pluse", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
259 { "v8plusv", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_V8PLUS
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_IMA
|HWCAP_ASI_CACHE_SPARING
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
260 { "v9", "v9", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
},
261 { "v9a", "v9a", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
},
262 { "v9b", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
},
263 { "v9c", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
},
264 { "v9d", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
},
265 { "v9e", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
266 { "v9v", "v9b", v9
, 0, 1, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
|HWCAP_VIS
|HWCAP_VIS2
|HWCAP_ASI_BLK_INIT
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_RANDOM
|HWCAP_TRANS
|HWCAP_FJFMAU
|HWCAP_IMA
|HWCAP_ASI_CACHE_SPARING
|HWCAP_AES
|HWCAP_DES
|HWCAP_KASUMI
|HWCAP_CAMELLIA
|HWCAP_MD5
|HWCAP_SHA1
|HWCAP_SHA256
|HWCAP_SHA512
|HWCAP_MPMUL
|HWCAP_MONT
|HWCAP_CRC32C
|HWCAP_CBCOND
|HWCAP_PAUSE
},
267 /* This exists to allow configure.in/Makefile.in to pass one
268 value to specify both the default machine and default word size. */
269 { "v9-64", "v9", v9
, 64, 0, HWCAP_MUL32
|HWCAP_DIV32
|HWCAP_FSMULD
|HWCAP_POPC
},
270 { NULL
, NULL
, v8
, 0, 0, 0 }
273 /* Variant of default_arch */
274 static enum sparc_arch_types default_arch_type
;
276 static struct sparc_arch
*
277 lookup_arch (char *name
)
279 struct sparc_arch
*sa
;
281 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
282 if (strcmp (sa
->name
, name
) == 0)
284 if (sa
->name
== NULL
)
289 /* Initialize the default opcode arch and word size from the default
290 architecture name. */
293 init_default_arch (void)
295 struct sparc_arch
*sa
= lookup_arch (default_arch
);
298 || sa
->default_arch_size
== 0)
299 as_fatal (_("Invalid default architecture, broken assembler."));
301 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
302 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
303 as_fatal (_("Bad opcode table, broken assembler."));
304 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
306 default_arch_type
= sa
->arch_type
;
309 /* Called by TARGET_FORMAT. */
312 sparc_target_format (void)
314 /* We don't get a chance to initialize anything before we're called,
315 so handle that now. */
316 if (! default_init_p
)
317 init_default_arch ();
321 return "a.out-sparc-netbsd";
324 if (target_big_endian
)
325 return "a.out-sunos-big";
326 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
327 return "a.out-sunos-big";
329 return "a.out-sparc-little";
331 return "a.out-sunos-big";
342 return "coff-sparc-lynx";
349 return "elf32-sparc-vxworks";
353 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
360 * Invocation line includes a switch not recognized by the base assembler.
361 * See if it's a processor-specific option. These are:
364 * Warn on architecture bumps. See also -A.
366 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
367 * Standard 32 bit architectures.
369 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
370 * This used to only mean 64 bits, but properly specifying it
371 * complicated gcc's ASM_SPECs, so now opcode selection is
372 * specified orthogonally to word size (except when specifying
373 * the default, but that is an internal implementation detail).
374 * -Av8plus, -Av8plusa, -Av8plusb
375 * Same as -Av9{,a,b}.
376 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
377 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
379 * -xarch=v9, -xarch=v9a, -xarch=v9b
380 * Same as -Av9{,a,b} -64, for compatibility with Sun's
383 * Select the architecture and possibly the file format.
384 * Instructions or features not supported by the selected
385 * architecture cause fatal errors.
387 * The default is to start at v6, and bump the architecture up
388 * whenever an instruction is seen at a higher level. In 32 bit
389 * environments, v9 is not bumped up to, the user must pass
392 * If -bump is specified, a warning is printing when bumping to
395 * If an architecture is specified, all instructions must match
396 * that architecture. Any higher level instructions are flagged
397 * as errors. Note that in the 32 bit environment specifying
398 * -Av8plus does not automatically create a v8plus object file, a
399 * v9 insn must be seen.
401 * If both an architecture and -bump are specified, the
402 * architecture starts at the specified level, but bumps are
403 * warnings. Note that we can't set `current_architecture' to
404 * the requested level in this case: in the 32 bit environment,
405 * we still must avoid creating v8plus object files unless v9
409 * Bumping between incompatible architectures is always an
410 * error. For example, from sparclite to v9.
414 const char *md_shortopts
= "A:K:VQ:sq";
417 const char *md_shortopts
= "A:k";
419 const char *md_shortopts
= "A:";
422 struct option md_longopts
[] = {
423 #define OPTION_BUMP (OPTION_MD_BASE)
424 {"bump", no_argument
, NULL
, OPTION_BUMP
},
425 #define OPTION_SPARC (OPTION_MD_BASE + 1)
426 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
427 #define OPTION_XARCH (OPTION_MD_BASE + 2)
428 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
430 #define OPTION_32 (OPTION_MD_BASE + 3)
431 {"32", no_argument
, NULL
, OPTION_32
},
432 #define OPTION_64 (OPTION_MD_BASE + 4)
433 {"64", no_argument
, NULL
, OPTION_64
},
434 #define OPTION_TSO (OPTION_MD_BASE + 5)
435 {"TSO", no_argument
, NULL
, OPTION_TSO
},
436 #define OPTION_PSO (OPTION_MD_BASE + 6)
437 {"PSO", no_argument
, NULL
, OPTION_PSO
},
438 #define OPTION_RMO (OPTION_MD_BASE + 7)
439 {"RMO", no_argument
, NULL
, OPTION_RMO
},
441 #ifdef SPARC_BIENDIAN
442 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
443 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
444 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
445 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
447 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
448 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
449 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
450 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
452 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
453 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
454 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
455 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
457 #define OPTION_RELAX (OPTION_MD_BASE + 14)
458 {"relax", no_argument
, NULL
, OPTION_RELAX
},
459 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
460 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
461 {NULL
, no_argument
, NULL
, 0}
464 size_t md_longopts_size
= sizeof (md_longopts
);
467 md_parse_option (int c
, char *arg
)
469 /* We don't get a chance to initialize anything before we're called,
470 so handle that now. */
471 if (! default_init_p
)
472 init_default_arch ();
478 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
483 if (strncmp (arg
, "v9", 2) != 0)
484 md_parse_option (OPTION_32
, NULL
);
486 md_parse_option (OPTION_64
, NULL
);
492 struct sparc_arch
*sa
;
493 enum sparc_opcode_arch_val opcode_arch
;
495 sa
= lookup_arch (arg
);
497 || ! sa
->user_option_p
)
499 if (c
== OPTION_XARCH
)
500 as_bad (_("invalid architecture -xarch=%s"), arg
);
502 as_bad (_("invalid architecture -A%s"), arg
);
506 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
507 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
508 as_fatal (_("Bad opcode table, broken assembler."));
510 if (!architecture_requested
511 || opcode_arch
> max_architecture
)
512 max_architecture
= opcode_arch
;
513 hwcap_allowed
|= sa
->hwcap_allowed
;
514 architecture_requested
= 1;
519 /* Ignore -sparc, used by SunOS make default .s.o rule. */
522 case OPTION_ENFORCE_ALIGNED_DATA
:
523 enforce_aligned_data
= 1;
526 #ifdef SPARC_BIENDIAN
527 case OPTION_LITTLE_ENDIAN
:
528 target_big_endian
= 0;
529 if (default_arch_type
!= sparclet
)
530 as_fatal ("This target does not support -EL");
532 case OPTION_LITTLE_ENDIAN_DATA
:
533 target_little_endian_data
= 1;
534 target_big_endian
= 0;
535 if (default_arch_type
!= sparc86x
536 && default_arch_type
!= v9
)
537 as_fatal ("This target does not support --little-endian-data");
539 case OPTION_BIG_ENDIAN
:
540 target_big_endian
= 1;
554 const char **list
, **l
;
556 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
557 list
= bfd_target_list ();
558 for (l
= list
; *l
!= NULL
; l
++)
560 if (sparc_arch_size
== 32)
562 if (CONST_STRNEQ (*l
, "elf32-sparc"))
567 if (CONST_STRNEQ (*l
, "elf64-sparc"))
572 as_fatal (_("No compiled in support for %d bit object file format"),
576 if (sparc_arch_size
== 64
577 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
578 max_architecture
= SPARC_OPCODE_ARCH_V9
;
583 sparc_memory_model
= MM_TSO
;
587 sparc_memory_model
= MM_PSO
;
591 sparc_memory_model
= MM_RMO
;
599 /* Qy - do emit .comment
600 Qn - do not emit .comment. */
604 /* Use .stab instead of .stab.excl. */
608 /* quick -- Native assembler does fewer checks. */
612 if (strcmp (arg
, "PIC") != 0)
613 as_warn (_("Unrecognized option following -K"));
618 case OPTION_NO_UNDECLARED_REGS
:
619 no_undeclared_regs
= 1;
622 case OPTION_UNDECLARED_REGS
:
623 no_undeclared_regs
= 0;
631 case OPTION_NO_RELAX
:
643 md_show_usage (FILE *stream
)
645 const struct sparc_arch
*arch
;
648 /* We don't get a chance to initialize anything before we're called,
649 so handle that now. */
650 if (! default_init_p
)
651 init_default_arch ();
653 fprintf (stream
, _("SPARC options:\n"));
655 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
657 if (!arch
->user_option_p
)
659 if (arch
!= &sparc_arch_table
[0])
660 fprintf (stream
, " | ");
661 if (column
+ strlen (arch
->name
) > 70)
664 fputc ('\n', stream
);
666 column
+= 5 + 2 + strlen (arch
->name
);
667 fprintf (stream
, "-A%s", arch
->name
);
669 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
671 if (!arch
->user_option_p
)
673 fprintf (stream
, " | ");
674 if (column
+ strlen (arch
->name
) > 65)
677 fputc ('\n', stream
);
679 column
+= 5 + 7 + strlen (arch
->name
);
680 fprintf (stream
, "-xarch=%s", arch
->name
);
682 fprintf (stream
, _("\n\
683 specify variant of SPARC architecture\n\
684 -bump warn when assembler switches architectures\n\
686 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
687 -relax relax jumps and branches (default)\n\
688 -no-relax avoid changing any jumps and branches\n"));
690 fprintf (stream
, _("\
691 -k generate PIC\n"));
694 fprintf (stream
, _("\
695 -32 create 32 bit object file\n\
696 -64 create 64 bit object file\n"));
697 fprintf (stream
, _("\
698 [default is %d]\n"), default_arch_size
);
699 fprintf (stream
, _("\
700 -TSO use Total Store Ordering\n\
701 -PSO use Partial Store Ordering\n\
702 -RMO use Relaxed Memory Ordering\n"));
703 fprintf (stream
, _("\
704 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
705 fprintf (stream
, _("\
706 -KPIC generate PIC\n\
707 -V print assembler version number\n\
708 -undeclared-regs ignore application global register usage without\n\
709 appropriate .register directive (default)\n\
710 -no-undeclared-regs force error on application global register usage\n\
711 without appropriate .register directive\n\
716 #ifdef SPARC_BIENDIAN
717 fprintf (stream
, _("\
718 -EL generate code for a little endian machine\n\
719 -EB generate code for a big endian machine\n\
720 --little-endian-data generate code for a machine having big endian\n\
721 instructions and little endian data.\n"));
725 /* Native operand size opcode translation. */
731 } native_op_table
[] =
733 {"ldn", "ld", "ldx"},
734 {"ldna", "lda", "ldxa"},
735 {"stn", "st", "stx"},
736 {"stna", "sta", "stxa"},
737 {"slln", "sll", "sllx"},
738 {"srln", "srl", "srlx"},
739 {"sran", "sra", "srax"},
740 {"casn", "cas", "casx"},
741 {"casna", "casa", "casxa"},
742 {"clrn", "clr", "clrx"},
746 /* sparc64 privileged and hyperprivileged registers. */
748 struct priv_reg_entry
754 struct priv_reg_entry priv_reg_table
[] =
774 {"", -1}, /* End marker. */
777 struct priv_reg_entry hpriv_reg_table
[] =
785 {"", -1}, /* End marker. */
788 /* v9a specific asrs. This table is ordered by initial
789 letter, in reverse. */
791 struct priv_reg_entry v9a_asr_table
[] =
794 {"sys_tick_cmpr", 25},
798 {"softint_clear", 21},
809 {"clear_softint", 21},
810 {"", -1}, /* End marker. */
814 cmp_reg_entry (const void *parg
, const void *qarg
)
816 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
817 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
819 return strcmp (q
->name
, p
->name
);
822 /* This function is called once, at assembler startup time. It should
823 set up all the tables, etc. that the MD part of the assembler will
829 register const char *retval
= NULL
;
831 register unsigned int i
= 0;
833 /* We don't get a chance to initialize anything before md_parse_option
834 is called, and it may not be called, so handle default initialization
835 now if not already done. */
836 if (! default_init_p
)
837 init_default_arch ();
839 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
840 op_hash
= hash_new ();
842 while (i
< (unsigned int) sparc_num_opcodes
)
844 const char *name
= sparc_opcodes
[i
].name
;
845 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
848 as_bad (_("Internal error: can't hash `%s': %s\n"),
849 sparc_opcodes
[i
].name
, retval
);
854 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
856 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
857 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
862 while (i
< (unsigned int) sparc_num_opcodes
863 && !strcmp (sparc_opcodes
[i
].name
, name
));
866 for (i
= 0; native_op_table
[i
].name
; i
++)
868 const struct sparc_opcode
*insn
;
869 char *name
= ((sparc_arch_size
== 32)
870 ? native_op_table
[i
].name32
871 : native_op_table
[i
].name64
);
872 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
875 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
876 name
, native_op_table
[i
].name
);
881 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
885 as_bad (_("Internal error: can't hash `%s': %s\n"),
886 sparc_opcodes
[i
].name
, retval
);
893 as_fatal (_("Broken assembler. No assembly attempted."));
895 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
896 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
898 /* If -bump, record the architecture level at which we start issuing
899 warnings. The behaviour is different depending upon whether an
900 architecture was explicitly specified. If it wasn't, we issue warnings
901 for all upwards bumps. If it was, we don't start issuing warnings until
902 we need to bump beyond the requested architecture or when we bump between
903 conflicting architectures. */
906 && architecture_requested
)
908 /* `max_architecture' records the requested architecture.
909 Issue warnings if we go above it. */
910 warn_after_architecture
= max_architecture
;
912 /* Find the highest architecture level that doesn't conflict with
913 the requested one. */
914 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
915 max_architecture
> warn_after_architecture
;
917 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
918 warn_after_architecture
))
923 /* Called after all assembly has been done. */
928 unsigned long mach
= bfd_mach_sparc
;
930 if (sparc_arch_size
== 64)
931 switch (current_architecture
)
933 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
934 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
935 default: mach
= bfd_mach_sparc_v9
; break;
938 switch (current_architecture
)
940 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
941 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
942 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
943 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
944 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
945 be but for now it is (since that's the way it's always been
949 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
951 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
953 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcap_seen
);
957 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
960 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
964 /* Sign-extend the value from the architecture word size, so that
965 0xffffffff is always considered -1 on sparc32. */
966 if (sparc_arch_size
== 32)
968 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
969 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
978 /* Return non-zero if VAL is in the range 0 to MAX. */
981 in_unsigned_range (bfd_vma val
, bfd_vma max
)
988 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
989 (e.g. -15 to +31). */
992 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
998 if (val
< ~(max
>> 1))
1004 sparc_ffs (unsigned int mask
)
1011 for (i
= 0; (mask
& 1) == 0; ++i
)
1016 /* Implement big shift right. */
1018 BSR (bfd_vma val
, int amount
)
1020 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1021 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1022 return val
>> amount
;
1025 /* For communication between sparc_ip and get_expression. */
1026 static char *expr_end
;
1028 /* Values for `special_case'.
1029 Instructions that require wierd handling because they're longer than
1031 #define SPECIAL_CASE_NONE 0
1032 #define SPECIAL_CASE_SET 1
1033 #define SPECIAL_CASE_SETSW 2
1034 #define SPECIAL_CASE_SETX 3
1035 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1036 #define SPECIAL_CASE_FDIV 4
1038 /* Bit masks of various insns. */
1039 #define NOP_INSN 0x01000000
1040 #define OR_INSN 0x80100000
1041 #define XOR_INSN 0x80180000
1042 #define FMOVS_INSN 0x81A00020
1043 #define SETHI_INSN 0x01000000
1044 #define SLLX_INSN 0x81281000
1045 #define SRA_INSN 0x81380000
1047 /* The last instruction to be assembled. */
1048 static const struct sparc_opcode
*last_insn
;
1049 /* The assembled opcode of `last_insn'. */
1050 static unsigned long last_opcode
;
1052 /* Handle the set and setuw synthetic instructions. */
1055 synthetize_setuw (const struct sparc_opcode
*insn
)
1057 int need_hi22_p
= 0;
1058 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1060 if (the_insn
.exp
.X_op
== O_constant
)
1062 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1064 if (sizeof (offsetT
) > 4
1065 && (the_insn
.exp
.X_add_number
< 0
1066 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1067 as_warn (_("set: number not in 0..4294967295 range"));
1071 if (sizeof (offsetT
) > 4
1072 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1073 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1074 as_warn (_("set: number not in -2147483648..4294967295 range"));
1075 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1079 /* See if operand is absolute and small; skip sethi if so. */
1080 if (the_insn
.exp
.X_op
!= O_constant
1081 || the_insn
.exp
.X_add_number
>= (1 << 12)
1082 || the_insn
.exp
.X_add_number
< -(1 << 12))
1084 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1085 | ((the_insn
.exp
.X_add_number
>> 10)
1086 & (the_insn
.exp
.X_op
== O_constant
1088 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1089 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1090 output_insn (insn
, &the_insn
);
1094 /* See if operand has no low-order bits; skip OR if so. */
1095 if (the_insn
.exp
.X_op
!= O_constant
1096 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1099 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1101 | (the_insn
.exp
.X_add_number
1102 & (the_insn
.exp
.X_op
!= O_constant
1103 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1104 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1105 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1106 output_insn (insn
, &the_insn
);
1110 /* Handle the setsw synthetic instruction. */
1113 synthetize_setsw (const struct sparc_opcode
*insn
)
1117 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1119 if (the_insn
.exp
.X_op
!= O_constant
)
1121 synthetize_setuw (insn
);
1123 /* Need to sign extend it. */
1124 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1125 the_insn
.reloc
= BFD_RELOC_NONE
;
1126 output_insn (insn
, &the_insn
);
1130 if (sizeof (offsetT
) > 4
1131 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1132 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1133 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1135 low32
= the_insn
.exp
.X_add_number
;
1139 synthetize_setuw (insn
);
1145 the_insn
.reloc
= BFD_RELOC_NONE
;
1146 /* See if operand is absolute and small; skip sethi if so. */
1147 if (low32
< -(1 << 12))
1149 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1150 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1151 output_insn (insn
, &the_insn
);
1152 low32
= 0x1c00 | (low32
& 0x3ff);
1153 opc
= RS1 (rd
) | XOR_INSN
;
1156 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1157 | (low32
& 0x1fff));
1158 output_insn (insn
, &the_insn
);
1161 /* Handle the setsw synthetic instruction. */
1164 synthetize_setx (const struct sparc_opcode
*insn
)
1166 int upper32
, lower32
;
1167 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1168 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1170 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1171 int need_xor10_p
= 0;
1173 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1174 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1175 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1178 upper_dstreg
= tmpreg
;
1179 /* The tmp reg should not be the dst reg. */
1180 if (tmpreg
== dstreg
)
1181 as_warn (_("setx: temporary register same as destination register"));
1183 /* ??? Obviously there are other optimizations we can do
1184 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1185 doing some of these. Later. If you do change things, try to
1186 change all of this to be table driven as well. */
1187 /* What to output depends on the number if it's constant.
1188 Compute that first, then output what we've decided upon. */
1189 if (the_insn
.exp
.X_op
!= O_constant
)
1191 if (sparc_arch_size
== 32)
1193 /* When arch size is 32, we want setx to be equivalent
1194 to setuw for anything but constants. */
1195 the_insn
.exp
.X_add_number
&= 0xffffffff;
1196 synthetize_setuw (insn
);
1199 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1205 /* Reset X_add_number, we've extracted it as upper32/lower32.
1206 Otherwise fixup_segment will complain about not being able to
1207 write an 8 byte number in a 4 byte field. */
1208 the_insn
.exp
.X_add_number
= 0;
1210 /* Only need hh22 if `or' insn can't handle constant. */
1211 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1214 /* Does bottom part (after sethi) have bits? */
1215 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1216 /* No hh22, but does upper32 still have bits we can't set
1218 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1221 /* If the lower half is all zero, we build the upper half directly
1222 into the dst reg. */
1224 /* Need lower half if number is zero or 0xffffffff00000000. */
1225 || (! need_hh22_p
&& ! need_hm10_p
))
1227 /* No need for sethi if `or' insn can handle constant. */
1228 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1229 /* Note that we can't use a negative constant in the `or'
1230 insn unless the upper 32 bits are all ones. */
1231 || (lower32
< 0 && upper32
!= -1)
1232 || (lower32
>= 0 && upper32
== -1))
1235 if (need_hi22_p
&& upper32
== -1)
1238 /* Does bottom part (after sethi) have bits? */
1239 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1241 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1242 /* Need `or' if we didn't set anything else. */
1243 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1247 /* Output directly to dst reg if lower 32 bits are all zero. */
1248 upper_dstreg
= dstreg
;
1251 if (!upper_dstreg
&& dstreg
)
1252 as_warn (_("setx: illegal temporary register g0"));
1256 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1257 | ((upper32
>> 10) & 0x3fffff));
1258 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1259 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1260 output_insn (insn
, &the_insn
);
1265 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1266 | (((need_xor10_p
? ~lower32
: lower32
)
1267 >> 10) & 0x3fffff));
1268 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1269 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1270 output_insn (insn
, &the_insn
);
1275 the_insn
.opcode
= (OR_INSN
1276 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1279 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1280 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1281 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1282 output_insn (insn
, &the_insn
);
1287 /* FIXME: One nice optimization to do here is to OR the low part
1288 with the highpart if hi22 isn't needed and the low part is
1290 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1293 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1294 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1295 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1296 output_insn (insn
, &the_insn
);
1299 /* If we needed to build the upper part, shift it into place. */
1300 if (need_hh22_p
|| need_hm10_p
)
1302 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1304 the_insn
.reloc
= BFD_RELOC_NONE
;
1305 output_insn (insn
, &the_insn
);
1308 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1311 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1312 | 0x1c00 | (lower32
& 0x3ff));
1313 the_insn
.reloc
= BFD_RELOC_NONE
;
1314 output_insn (insn
, &the_insn
);
1317 /* If we needed to build both upper and lower parts, OR them together. */
1318 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1320 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1322 the_insn
.reloc
= BFD_RELOC_NONE
;
1323 output_insn (insn
, &the_insn
);
1327 /* Main entry point to assemble one instruction. */
1330 md_assemble (char *str
)
1332 const struct sparc_opcode
*insn
;
1336 special_case
= sparc_ip (str
, &insn
);
1340 /* We warn about attempts to put a floating point branch in a delay slot,
1341 unless the delay slot has been annulled. */
1342 if (last_insn
!= NULL
1343 && (insn
->flags
& F_FBR
) != 0
1344 && (last_insn
->flags
& F_DELAYED
) != 0
1345 /* ??? This test isn't completely accurate. We assume anything with
1346 F_{UNBR,CONDBR,FBR} set is annullable. */
1347 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1348 || (last_opcode
& ANNUL
) == 0))
1349 as_warn (_("FP branch in delay slot"));
1351 /* SPARC before v9 requires a nop instruction between a floating
1352 point instruction and a floating point branch. We insert one
1353 automatically, with a warning. */
1354 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1355 && last_insn
!= NULL
1356 && (insn
->flags
& F_FBR
) != 0
1357 && (last_insn
->flags
& F_FLOAT
) != 0)
1359 struct sparc_it nop_insn
;
1361 nop_insn
.opcode
= NOP_INSN
;
1362 nop_insn
.reloc
= BFD_RELOC_NONE
;
1363 output_insn (insn
, &nop_insn
);
1364 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1367 switch (special_case
)
1369 case SPECIAL_CASE_NONE
:
1371 output_insn (insn
, &the_insn
);
1374 case SPECIAL_CASE_SETSW
:
1375 synthetize_setsw (insn
);
1378 case SPECIAL_CASE_SET
:
1379 synthetize_setuw (insn
);
1382 case SPECIAL_CASE_SETX
:
1383 synthetize_setx (insn
);
1386 case SPECIAL_CASE_FDIV
:
1388 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1390 output_insn (insn
, &the_insn
);
1392 /* According to information leaked from Sun, the "fdiv" instructions
1393 on early SPARC machines would produce incorrect results sometimes.
1394 The workaround is to add an fmovs of the destination register to
1395 itself just after the instruction. This was true on machines
1396 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1397 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1398 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1399 output_insn (insn
, &the_insn
);
1404 as_fatal (_("failed special case insn sanity check"));
1409 get_hwcap_name (int mask
)
1411 if (mask
& HWCAP_MUL32
)
1413 if (mask
& HWCAP_DIV32
)
1415 if (mask
& HWCAP_FSMULD
)
1417 if (mask
& HWCAP_V8PLUS
)
1419 if (mask
& HWCAP_POPC
)
1421 if (mask
& HWCAP_VIS
)
1423 if (mask
& HWCAP_VIS2
)
1425 if (mask
& HWCAP_ASI_BLK_INIT
)
1426 return "ASIBlkInit";
1427 if (mask
& HWCAP_FMAF
)
1429 if (mask
& HWCAP_VIS3
)
1431 if (mask
& HWCAP_HPC
)
1433 if (mask
& HWCAP_RANDOM
)
1435 if (mask
& HWCAP_TRANS
)
1437 if (mask
& HWCAP_FJFMAU
)
1439 if (mask
& HWCAP_IMA
)
1441 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1443 if (mask
& HWCAP_AES
)
1445 if (mask
& HWCAP_DES
)
1447 if (mask
& HWCAP_KASUMI
)
1449 if (mask
& HWCAP_CAMELLIA
)
1451 if (mask
& HWCAP_MD5
)
1453 if (mask
& HWCAP_SHA1
)
1455 if (mask
& HWCAP_SHA256
)
1457 if (mask
& HWCAP_SHA512
)
1459 if (mask
& HWCAP_MPMUL
)
1461 if (mask
& HWCAP_MONT
)
1463 if (mask
& HWCAP_PAUSE
)
1465 if (mask
& HWCAP_CBCOND
)
1467 if (mask
& HWCAP_CRC32C
)
1472 /* Subroutine of md_assemble to do the actual parsing. */
1475 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1477 char *error_message
= "";
1481 const struct sparc_opcode
*insn
;
1483 unsigned long opcode
;
1484 unsigned int mask
= 0;
1488 int special_case
= SPECIAL_CASE_NONE
;
1495 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1512 as_bad (_("Unknown opcode: `%s'"), str
);
1514 return special_case
;
1516 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1520 as_bad (_("Unknown opcode: `%s'"), str
);
1521 return special_case
;
1531 opcode
= insn
->match
;
1532 memset (&the_insn
, '\0', sizeof (the_insn
));
1533 the_insn
.reloc
= BFD_RELOC_NONE
;
1536 /* Build the opcode, checking as we go to make sure that the
1538 for (args
= insn
->args
;; ++args
)
1546 /* Parse a series of masks. */
1553 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1556 error_message
= _(": invalid membar mask name");
1562 if (*s
== '|' || *s
== '+')
1570 if (! parse_const_expr_arg (&s
, &kmask
))
1572 error_message
= _(": invalid membar mask expression");
1575 if (kmask
< 0 || kmask
> 127)
1577 error_message
= _(": invalid membar mask number");
1582 opcode
|= MEMBAR (kmask
);
1590 if (! parse_const_expr_arg (&s
, &smask
))
1592 error_message
= _(": invalid siam mode expression");
1595 if (smask
< 0 || smask
> 7)
1597 error_message
= _(": invalid siam mode number");
1608 /* Parse a prefetch function. */
1611 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1613 error_message
= _(": invalid prefetch function name");
1619 if (! parse_const_expr_arg (&s
, &fcn
))
1621 error_message
= _(": invalid prefetch function expression");
1624 if (fcn
< 0 || fcn
> 31)
1626 error_message
= _(": invalid prefetch function number");
1636 /* Parse a sparc64 privileged register. */
1639 struct priv_reg_entry
*p
= priv_reg_table
;
1640 unsigned int len
= 9999999; /* Init to make gcc happy. */
1643 while (p
->name
[0] > s
[0])
1645 while (p
->name
[0] == s
[0])
1647 len
= strlen (p
->name
);
1648 if (strncmp (p
->name
, s
, len
) == 0)
1652 if (p
->name
[0] != s
[0])
1654 error_message
= _(": unrecognizable privileged register");
1658 opcode
|= (p
->regnum
<< 14);
1660 opcode
|= (p
->regnum
<< 25);
1666 error_message
= _(": unrecognizable privileged register");
1672 /* Parse a sparc64 hyperprivileged register. */
1675 struct priv_reg_entry
*p
= hpriv_reg_table
;
1676 unsigned int len
= 9999999; /* Init to make gcc happy. */
1679 while (p
->name
[0] > s
[0])
1681 while (p
->name
[0] == s
[0])
1683 len
= strlen (p
->name
);
1684 if (strncmp (p
->name
, s
, len
) == 0)
1688 if (p
->name
[0] != s
[0])
1690 error_message
= _(": unrecognizable hyperprivileged register");
1694 opcode
|= (p
->regnum
<< 14);
1696 opcode
|= (p
->regnum
<< 25);
1702 error_message
= _(": unrecognizable hyperprivileged register");
1708 /* Parse a v9a/v9b ancillary state register. */
1711 struct priv_reg_entry
*p
= v9a_asr_table
;
1712 unsigned int len
= 9999999; /* Init to make gcc happy. */
1715 while (p
->name
[0] > s
[0])
1717 while (p
->name
[0] == s
[0])
1719 len
= strlen (p
->name
);
1720 if (strncmp (p
->name
, s
, len
) == 0)
1724 if (p
->name
[0] != s
[0])
1726 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1729 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1731 error_message
= _(": rd on write only ancillary state register");
1735 && (insn
->architecture
1736 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A
)))
1738 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
1739 error_message
= _(": unrecognizable v9a ancillary state register");
1743 opcode
|= (p
->regnum
<< 14);
1745 opcode
|= (p
->regnum
<< 25);
1751 error_message
= _(": unrecognizable v9a or v9b ancillary state register");
1757 if (strncmp (s
, "%asr", 4) == 0)
1765 while (ISDIGIT (*s
))
1767 num
= num
* 10 + *s
- '0';
1771 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1773 if (num
< 16 || 31 < num
)
1775 error_message
= _(": asr number must be between 16 and 31");
1781 if (num
< 0 || 31 < num
)
1783 error_message
= _(": asr number must be between 0 and 31");
1788 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1793 error_message
= _(": expecting %asrN");
1800 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1804 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1810 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
1815 if (s
[0] == '0' && s
[1] == 'x')
1818 while (ISXDIGIT (*s
))
1821 num
|= hex_value (*s
);
1827 while (ISDIGIT (*s
))
1829 num
= num
* 10 + *s
- '0';
1833 if (num
< 0 || num
> 31)
1835 error_message
= _(": crypto immediate must be between 0 and 31");
1839 opcode
|= RS3 (num
);
1844 error_message
= _(": expecting crypto immediate");
1849 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1850 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1851 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1853 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1854 /* These fields are unsigned, but for upward compatibility,
1855 allow negative values as well. */
1859 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1860 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1861 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1863 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1864 /* These fields are unsigned, but for upward compatibility,
1865 allow negative values as well. */
1869 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1874 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
1879 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1884 if (*s
== 'p' && s
[1] == 'n')
1892 if (*s
== 'p' && s
[1] == 't')
1904 if (strncmp (s
, "%icc", 4) == 0)
1916 if (strncmp (s
, "%xcc", 4) == 0)
1928 if (strncmp (s
, "%fcc0", 5) == 0)
1940 if (strncmp (s
, "%fcc1", 5) == 0)
1952 if (strncmp (s
, "%fcc2", 5) == 0)
1964 if (strncmp (s
, "%fcc3", 5) == 0)
1972 if (strncmp (s
, "%pc", 3) == 0)
1980 if (strncmp (s
, "%tick", 5) == 0)
1987 case '\0': /* End of args. */
1988 if (s
[0] == ',' && s
[1] == '%')
1990 static const struct ops
1992 /* The name as it appears in assembler. */
1994 /* strlen (name), precomputed for speed */
1996 /* The reloc this pseudo-op translates to. */
1998 /* 1 if tls call. */
2003 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD
, 0 },
2004 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL
, 1 },
2005 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD
, 0 },
2006 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL
, 1 },
2007 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD
, 0 },
2008 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX
, 0 },
2009 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD
, 0 },
2010 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD
, 0 },
2011 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP
, 0 },
2014 const struct ops
*o
;
2018 for (o
= ops
; o
->name
; o
++)
2019 if (strncmp (s
+ 2, o
->name
, o
->len
) == 0)
2021 if (o
->name
== NULL
)
2024 if (s
[o
->len
+ 2] != '(')
2026 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2027 return special_case
;
2030 if (! o
->tls_call
&& the_insn
.reloc
!= BFD_RELOC_NONE
)
2032 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2034 return special_case
;
2038 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2039 || the_insn
.exp
.X_add_number
!= 0
2040 || the_insn
.exp
.X_add_symbol
2041 != symbol_find_or_make ("__tls_get_addr")))
2043 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2045 return special_case
;
2048 the_insn
.reloc
= o
->reloc
;
2049 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2052 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2055 else if (*s1
== ')')
2064 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2065 return special_case
;
2069 (void) get_expression (s
);
2089 case '[': /* These must match exactly. */
2097 case '#': /* Must be at least one digit. */
2100 while (ISDIGIT (*s
))
2108 case 'C': /* Coprocessor state register. */
2109 if (strncmp (s
, "%csr", 4) == 0)
2116 case 'b': /* Next operand is a coprocessor register. */
2119 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2124 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2138 opcode
|= mask
<< 14;
2146 opcode
|= mask
<< 25;
2152 case 'r': /* next operand must be a register */
2162 case 'f': /* frame pointer */
2170 case 'g': /* global register */
2179 case 'i': /* in register */
2183 mask
= c
- '0' + 24;
2188 case 'l': /* local register */
2192 mask
= (c
- '0' + 16);
2197 case 'o': /* out register */
2201 mask
= (c
- '0' + 8);
2206 case 's': /* stack pointer */
2214 case 'r': /* any register */
2215 if (!ISDIGIT ((c
= *s
++)))
2232 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2248 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2249 && no_undeclared_regs
&& ! globals
[mask
])
2250 as_bad (_("detected global register use not covered by .register pseudo-op"));
2252 /* Got the register, now figure out where
2253 it goes in the opcode. */
2257 opcode
|= mask
<< 14;
2265 opcode
|= mask
<< 25;
2269 opcode
|= (mask
<< 25) | (mask
<< 14);
2273 opcode
|= (mask
<< 25) | (mask
<< 0);
2279 case 'e': /* next operand is a floating point register */
2297 && ((format
= *s
) == 'f')
2300 for (mask
= 0; ISDIGIT (*s
); ++s
)
2302 mask
= 10 * mask
+ (*s
- '0');
2303 } /* read the number */
2312 } /* register must be even numbered */
2320 } /* register must be multiple of 4 */
2324 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2325 error_message
= _(": There are only 64 f registers; [0-63]");
2327 error_message
= _(": There are only 32 f registers; [0-31]");
2330 else if (mask
>= 32)
2332 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2334 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2337 = _(": There are only 32 single precision f registers; [0-31]");
2341 mask
-= 31; /* wrap high bit */
2345 error_message
= _(": There are only 32 f registers; [0-31]");
2353 } /* if not an 'f' register. */
2360 opcode
|= RS1 (mask
);
2366 opcode
|= RS2 (mask
);
2371 opcode
|= RS3 (mask
);
2377 opcode
|= RD (mask
);
2386 if (strncmp (s
, "%fsr", 4) == 0)
2394 if (strncmp (s
, "%efsr", 5) == 0)
2401 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2402 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2405 case 'l': /* 22 bit PC relative immediate */
2406 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2410 case 'L': /* 30 bit immediate */
2411 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2416 case 'n': /* 22 bit immediate */
2417 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2420 case 'i': /* 13 bit immediate */
2421 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2431 char *op_arg
= NULL
;
2432 static expressionS op_exp
;
2433 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2435 /* Check for %hi, etc. */
2438 static const struct ops
{
2439 /* The name as it appears in assembler. */
2441 /* strlen (name), precomputed for speed */
2443 /* The reloc this pseudo-op translates to. */
2445 /* Non-zero if for v9 only. */
2447 /* Non-zero if can be used in pc-relative contexts. */
2448 int pcrel_p
;/*FIXME:wip*/
2450 /* hix/lox must appear before hi/lo so %hix won't be
2451 mistaken for %hi. */
2452 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2453 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2454 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2455 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2456 { "pc22", 4, BFD_RELOC_SPARC_PC22
, 0, 1 },
2457 { "pc10", 4, BFD_RELOC_SPARC_PC10
, 0, 1 },
2458 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2459 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2460 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2461 { "h34", 3, BFD_RELOC_SPARC_H34
, 1, 0 },
2462 { "l34", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2463 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2464 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2465 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2466 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2467 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2468 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22
, 0, 0 },
2469 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10
, 0, 0 },
2470 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22
, 0, 0 },
2471 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10
, 0, 0 },
2472 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0,
2474 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0,
2476 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22
, 0, 0 },
2477 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10
, 0, 0 },
2478 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22
, 0, 0 },
2479 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10
, 0, 0 },
2480 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22
,
2482 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10
,
2484 { NULL
, 0, 0, 0, 0 }
2486 const struct ops
*o
;
2488 for (o
= ops
; o
->name
; o
++)
2489 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2491 if (o
->name
== NULL
)
2494 if (s
[o
->len
+ 1] != '(')
2496 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2497 return special_case
;
2501 the_insn
.reloc
= o
->reloc
;
2506 /* Note that if the get_expression() fails, we will still
2507 have created U entries in the symbol table for the
2508 'symbols' in the input string. Try not to create U
2509 symbols for registers, etc. */
2511 /* This stuff checks to see if the expression ends in
2512 +%reg. If it does, it removes the register from
2513 the expression, and re-sets 's' to point to the
2520 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2523 else if (*s1
== ')')
2532 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2533 return special_case
;
2537 (void) get_expression (s
);
2540 if (*s
== ',' || *s
== ']' || !*s
)
2542 if (*s
!= '+' && *s
!= '-')
2544 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2545 return special_case
;
2549 op_exp
= the_insn
.exp
;
2550 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2553 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2556 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2558 if (s1
[-2] == '%' && s1
[-3] == '+')
2560 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2562 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2569 if (op_arg
&& s1
== s
+ 1)
2570 the_insn
.exp
.X_op
= O_absent
;
2572 (void) get_expression (s
);
2584 (void) get_expression (s
);
2592 the_insn
.exp2
= the_insn
.exp
;
2593 the_insn
.exp
= op_exp
;
2594 if (the_insn
.exp2
.X_op
== O_absent
)
2595 the_insn
.exp2
.X_op
= O_illegal
;
2596 else if (the_insn
.exp
.X_op
== O_absent
)
2598 the_insn
.exp
= the_insn
.exp2
;
2599 the_insn
.exp2
.X_op
= O_illegal
;
2601 else if (the_insn
.exp
.X_op
== O_constant
)
2603 valueT val
= the_insn
.exp
.X_add_number
;
2604 switch (the_insn
.reloc
)
2609 case BFD_RELOC_SPARC_HH22
:
2610 val
= BSR (val
, 32);
2613 case BFD_RELOC_SPARC_LM22
:
2614 case BFD_RELOC_HI22
:
2615 val
= (val
>> 10) & 0x3fffff;
2618 case BFD_RELOC_SPARC_HM10
:
2619 val
= BSR (val
, 32);
2622 case BFD_RELOC_LO10
:
2626 case BFD_RELOC_SPARC_H34
:
2631 case BFD_RELOC_SPARC_H44
:
2636 case BFD_RELOC_SPARC_M44
:
2641 case BFD_RELOC_SPARC_L44
:
2645 case BFD_RELOC_SPARC_HIX22
:
2647 val
= (val
>> 10) & 0x3fffff;
2650 case BFD_RELOC_SPARC_LOX10
:
2651 val
= (val
& 0x3ff) | 0x1c00;
2654 the_insn
.exp
= the_insn
.exp2
;
2655 the_insn
.exp
.X_add_number
+= val
;
2656 the_insn
.exp2
.X_op
= O_illegal
;
2657 the_insn
.reloc
= old_reloc
;
2659 else if (the_insn
.exp2
.X_op
!= O_constant
)
2661 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2662 return special_case
;
2666 if (old_reloc
!= BFD_RELOC_SPARC13
2667 || the_insn
.reloc
!= BFD_RELOC_LO10
2668 || sparc_arch_size
!= 64
2671 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2672 return special_case
;
2674 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2678 /* Check for constants that don't require emitting a reloc. */
2679 if (the_insn
.exp
.X_op
== O_constant
2680 && the_insn
.exp
.X_add_symbol
== 0
2681 && the_insn
.exp
.X_op_symbol
== 0)
2683 /* For pc-relative call instructions, we reject
2684 constants to get better code. */
2686 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2687 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2689 error_message
= _(": PC-relative operand can't be a constant");
2693 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2694 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2696 error_message
= _(": TLS operand can't be a constant");
2700 /* Constants that won't fit are checked in md_apply_fix
2701 and bfd_install_relocation.
2702 ??? It would be preferable to install the constants
2703 into the insn here and save having to create a fixS
2704 for each one. There already exists code to handle
2705 all the various cases (e.g. in md_apply_fix and
2706 bfd_install_relocation) so duplicating all that code
2707 here isn't right. */
2709 /* This is a special case to handle cbcond instructions
2710 properly, which can need two relocations. The first
2711 one is for the 5-bit immediate field and the latter
2712 is going to be for the WDISP10 branch part. We
2713 handle the R_SPARC_5 immediate directly here so that
2714 we don't need to add support for multiple relocations
2715 in one instruction just yet. */
2716 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2718 valueT val
= the_insn
.exp
.X_add_number
;
2720 if (! in_bitfield_range (val
, 0x1f))
2722 error_message
= _(": Immediate value in cbcond is out of range.");
2725 opcode
|= val
& 0x1f;
2726 the_insn
.reloc
= BFD_RELOC_NONE
;
2747 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2749 error_message
= _(": invalid ASI name");
2755 if (! parse_const_expr_arg (&s
, &asi
))
2757 error_message
= _(": invalid ASI expression");
2760 if (asi
< 0 || asi
> 255)
2762 error_message
= _(": invalid ASI number");
2766 opcode
|= ASI (asi
);
2768 } /* Alternate space. */
2771 if (strncmp (s
, "%psr", 4) == 0)
2778 case 'q': /* Floating point queue. */
2779 if (strncmp (s
, "%fq", 3) == 0)
2786 case 'Q': /* Coprocessor queue. */
2787 if (strncmp (s
, "%cq", 3) == 0)
2795 if (strcmp (str
, "set") == 0
2796 || strcmp (str
, "setuw") == 0)
2798 special_case
= SPECIAL_CASE_SET
;
2801 else if (strcmp (str
, "setsw") == 0)
2803 special_case
= SPECIAL_CASE_SETSW
;
2806 else if (strcmp (str
, "setx") == 0)
2808 special_case
= SPECIAL_CASE_SETX
;
2811 else if (strncmp (str
, "fdiv", 4) == 0)
2813 special_case
= SPECIAL_CASE_FDIV
;
2819 if (strncmp (s
, "%asi", 4) != 0)
2825 if (strncmp (s
, "%fprs", 5) != 0)
2831 if (strncmp (s
, "%ccr", 4) != 0)
2837 if (strncmp (s
, "%tbr", 4) != 0)
2843 if (strncmp (s
, "%wim", 4) != 0)
2850 char *push
= input_line_pointer
;
2853 input_line_pointer
= s
;
2855 if (e
.X_op
== O_constant
)
2857 int n
= e
.X_add_number
;
2858 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2859 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2861 opcode
|= e
.X_add_number
<< 5;
2864 as_bad (_("non-immediate OPF operand, ignored"));
2865 s
= input_line_pointer
;
2866 input_line_pointer
= push
;
2871 if (strncmp (s
, "%y", 2) != 0)
2879 /* Parse a sparclet cpreg. */
2881 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2883 error_message
= _(": invalid cpreg name");
2886 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2891 as_fatal (_("failed sanity check."));
2892 } /* switch on arg code. */
2894 /* Break out of for() loop. */
2896 } /* For each arg that we expect. */
2901 /* Args don't match. */
2902 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2903 && (insn
->name
== insn
[1].name
2904 || !strcmp (insn
->name
, insn
[1].name
)))
2912 as_bad (_("Illegal operands%s"), error_message
);
2913 return special_case
;
2918 /* We have a match. Now see if the architecture is OK. */
2919 int needed_arch_mask
= insn
->architecture
;
2920 int hwcaps
= insn
->hwcaps
;
2922 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
2924 hwcap_seen
|= hwcaps
;
2929 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
2930 if (! needed_arch_mask
)
2932 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
2935 if (needed_arch_mask
2936 & SPARC_OPCODE_SUPPORTED (current_architecture
))
2939 /* Can we bump up the architecture? */
2940 else if (needed_arch_mask
2941 & SPARC_OPCODE_SUPPORTED (max_architecture
))
2943 enum sparc_opcode_arch_val needed_architecture
=
2944 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2945 & needed_arch_mask
);
2947 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2949 && needed_architecture
> warn_after_architecture
)
2951 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2952 sparc_opcode_archs
[current_architecture
].name
,
2953 sparc_opcode_archs
[needed_architecture
].name
,
2955 warn_after_architecture
= needed_architecture
;
2957 current_architecture
= needed_architecture
;
2960 /* ??? This seems to be a bit fragile. What if the next entry in
2961 the opcode table is the one we want and it is supported?
2962 It is possible to arrange the table today so that this can't
2963 happen but what about tomorrow? */
2966 int arch
, printed_one_p
= 0;
2968 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2970 /* Create a list of the architectures that support the insn. */
2971 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
2973 arch
= sparc_ffs (needed_arch_mask
);
2974 while ((1 << arch
) <= needed_arch_mask
)
2976 if ((1 << arch
) & needed_arch_mask
)
2980 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2987 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2988 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2990 sparc_opcode_archs
[max_architecture
].name
);
2991 return special_case
;
2994 /* Make sure the the hwcaps used by the instruction are
2995 currently enabled. */
2996 if (hwcaps
& ~hwcap_allowed
)
2998 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3000 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3002 return special_case
;
3004 } /* If no match. */
3007 } /* Forever looking for a match. */
3009 the_insn
.opcode
= opcode
;
3010 return special_case
;
3013 /* Parse an argument that can be expressed as a keyword.
3014 (eg: #StoreStore or %ccfr).
3015 The result is a boolean indicating success.
3016 If successful, INPUT_POINTER is updated. */
3019 parse_keyword_arg (int (*lookup_fn
) (const char *),
3020 char **input_pointerP
,
3026 p
= *input_pointerP
;
3027 for (q
= p
+ (*p
== '#' || *p
== '%');
3028 ISALNUM (*q
) || *q
== '_';
3033 value
= (*lookup_fn
) (p
);
3038 *input_pointerP
= q
;
3042 /* Parse an argument that is a constant expression.
3043 The result is a boolean indicating success. */
3046 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3048 char *save
= input_line_pointer
;
3051 input_line_pointer
= *input_pointerP
;
3052 /* The next expression may be something other than a constant
3053 (say if we're not processing the right variant of the insn).
3054 Don't call expression unless we're sure it will succeed as it will
3055 signal an error (which we want to defer until later). */
3056 /* FIXME: It might be better to define md_operand and have it recognize
3057 things like %asi, etc. but continuing that route through to the end
3058 is a lot of work. */
3059 if (*input_line_pointer
== '%')
3061 input_line_pointer
= save
;
3065 *input_pointerP
= input_line_pointer
;
3066 input_line_pointer
= save
;
3067 if (exp
.X_op
!= O_constant
)
3069 *valueP
= exp
.X_add_number
;
3073 /* Subroutine of sparc_ip to parse an expression. */
3076 get_expression (char *str
)
3081 save_in
= input_line_pointer
;
3082 input_line_pointer
= str
;
3083 seg
= expression (&the_insn
.exp
);
3084 if (seg
!= absolute_section
3085 && seg
!= text_section
3086 && seg
!= data_section
3087 && seg
!= bss_section
3088 && seg
!= undefined_section
)
3090 the_insn
.error
= _("bad segment");
3091 expr_end
= input_line_pointer
;
3092 input_line_pointer
= save_in
;
3095 expr_end
= input_line_pointer
;
3096 input_line_pointer
= save_in
;
3100 /* Subroutine of md_assemble to output one insn. */
3103 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3105 char *toP
= frag_more (4);
3107 /* Put out the opcode. */
3108 if (INSN_BIG_ENDIAN
)
3109 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3111 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3113 /* Put out the symbol-dependent stuff. */
3114 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3116 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3117 (toP
- frag_now
->fr_literal
), /* Where. */
3122 /* Turn off overflow checking in fixup_segment. We'll do our
3123 own overflow checking in md_apply_fix. This is necessary because
3124 the insn size is 4 and fixup_segment will signal an overflow for
3125 large 8 byte quantities. */
3126 fixP
->fx_no_overflow
= 1;
3127 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3128 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3132 last_opcode
= theinsn
->opcode
;
3135 dwarf2_emit_insn (4);
3140 md_atof (int type
, char *litP
, int *sizeP
)
3142 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3145 /* Write a value out to the object file, using the appropriate
3149 md_number_to_chars (char *buf
, valueT val
, int n
)
3151 if (target_big_endian
)
3152 number_to_chars_bigendian (buf
, val
, n
);
3153 else if (target_little_endian_data
3154 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3155 /* Output debug words, which are not in allocated sections, as big
3157 number_to_chars_bigendian (buf
, val
, n
);
3158 else if (target_little_endian_data
|| ! target_big_endian
)
3159 number_to_chars_littleendian (buf
, val
, n
);
3162 /* Apply a fixS to the frags, now that we know the value it ought to
3166 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3168 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3169 offsetT val
= * (offsetT
*) valP
;
3172 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3174 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3177 /* SPARC ELF relocations don't use an addend in the data field. */
3178 if (fixP
->fx_addsy
!= NULL
)
3180 switch (fixP
->fx_r_type
)
3182 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3183 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3184 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3185 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3186 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3187 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3188 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3189 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3190 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3191 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3192 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3193 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3194 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3195 case BFD_RELOC_SPARC_TLS_IE_LD
:
3196 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3197 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3198 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3199 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3200 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3201 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3202 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3203 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3204 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3205 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3206 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3216 /* This is a hack. There should be a better way to
3217 handle this. Probably in terms of howto fields, once
3218 we can look at these fixups in terms of howtos. */
3219 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3220 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3223 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3224 generate a reloc, then we just want to let the reloc addend set
3225 the value. We do not want to also stuff the addend into the
3226 object file. Including the addend in the object file works when
3227 doing a static link, because the linker will ignore the object
3228 file contents. However, the dynamic linker does not ignore the
3229 object file contents. */
3230 if (fixP
->fx_addsy
!= NULL
3231 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3234 /* When generating PIC code, we do not want an addend for a reloc
3235 against a local symbol. We adjust fx_addnumber to cancel out the
3236 value already included in val, and to also cancel out the
3237 adjustment which bfd_install_relocation will create. */
3239 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3240 && fixP
->fx_addsy
!= NULL
3241 && ! S_IS_COMMON (fixP
->fx_addsy
)
3242 && symbol_section_p (fixP
->fx_addsy
))
3243 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3245 /* When generating PIC code, we need to fiddle to get
3246 bfd_install_relocation to do the right thing for a PC relative
3247 reloc against a local symbol which we are going to keep. */
3249 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3250 && fixP
->fx_addsy
!= NULL
3251 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3252 || S_IS_WEAK (fixP
->fx_addsy
))
3253 && S_IS_DEFINED (fixP
->fx_addsy
)
3254 && ! S_IS_COMMON (fixP
->fx_addsy
))
3257 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3261 /* If this is a data relocation, just output VAL. */
3263 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3265 md_number_to_chars (buf
, val
, 1);
3267 else if (fixP
->fx_r_type
== BFD_RELOC_16
3268 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3270 md_number_to_chars (buf
, val
, 2);
3272 else if (fixP
->fx_r_type
== BFD_RELOC_32
3273 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3274 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3276 md_number_to_chars (buf
, val
, 4);
3278 else if (fixP
->fx_r_type
== BFD_RELOC_64
3279 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3281 md_number_to_chars (buf
, val
, 8);
3283 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3284 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3291 /* It's a relocation against an instruction. */
3293 if (INSN_BIG_ENDIAN
)
3294 insn
= bfd_getb32 ((unsigned char *) buf
);
3296 insn
= bfd_getl32 ((unsigned char *) buf
);
3298 switch (fixP
->fx_r_type
)
3300 case BFD_RELOC_32_PCREL_S2
:
3302 /* FIXME: This increment-by-one deserves a comment of why it's
3304 if (! sparc_pic_code
3305 || fixP
->fx_addsy
== NULL
3306 || symbol_section_p (fixP
->fx_addsy
))
3309 insn
|= val
& 0x3fffffff;
3311 /* See if we have a delay slot. */
3312 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3316 #define XCC (2 << 20)
3317 #define COND(x) (((x)&0xf)<<25)
3318 #define CONDA COND(0x8)
3319 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3320 #define INSN_BA (F2(0,2) | CONDA)
3321 #define INSN_OR F3(2, 0x2, 0)
3322 #define INSN_NOP F2(0,4)
3326 /* If the instruction is a call with either:
3328 arithmetic instruction with rd == %o7
3329 where rs1 != %o7 and rs2 if it is register != %o7
3330 then we can optimize if the call destination is near
3331 by changing the call into a branch always. */
3332 if (INSN_BIG_ENDIAN
)
3333 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3335 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3336 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3338 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3339 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3340 || ((delay
& RD (~0)) != RD (O7
))))
3342 if ((delay
& RS1 (~0)) == RS1 (O7
)
3343 || ((delay
& F3I (~0)) == 0
3344 && (delay
& RS2 (~0)) == RS2 (O7
)))
3346 /* Ensure the branch will fit into simm22. */
3347 if ((val
& 0x3fe00000)
3348 && (val
& 0x3fe00000) != 0x3fe00000)
3350 /* Check if the arch is v9 and branch will fit
3352 if (((val
& 0x3c0000) == 0
3353 || (val
& 0x3c0000) == 0x3c0000)
3354 && (sparc_arch_size
== 64
3355 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3357 insn
= INSN_BPA
| (val
& 0x7ffff);
3360 insn
= INSN_BA
| (val
& 0x3fffff);
3361 if (fixP
->fx_where
>= 4
3362 && ((delay
& (0xffffffff ^ RS1 (~0)))
3363 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3368 if (INSN_BIG_ENDIAN
)
3369 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3371 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3372 if ((setter
& (0xffffffff ^ RD (~0)))
3373 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3380 If call foo was replaced with ba, replace
3381 or %rN, %g0, %o7 with nop. */
3382 reg
= (delay
& RS1 (~0)) >> 14;
3383 if (reg
!= ((setter
& RD (~0)) >> 25)
3384 || reg
== G0
|| reg
== O7
)
3387 if (INSN_BIG_ENDIAN
)
3388 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3390 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3395 case BFD_RELOC_SPARC_11
:
3396 if (! in_signed_range (val
, 0x7ff))
3397 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3398 _("relocation overflow"));
3399 insn
|= val
& 0x7ff;
3402 case BFD_RELOC_SPARC_10
:
3403 if (! in_signed_range (val
, 0x3ff))
3404 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3405 _("relocation overflow"));
3406 insn
|= val
& 0x3ff;
3409 case BFD_RELOC_SPARC_7
:
3410 if (! in_bitfield_range (val
, 0x7f))
3411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3412 _("relocation overflow"));
3416 case BFD_RELOC_SPARC_6
:
3417 if (! in_bitfield_range (val
, 0x3f))
3418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3419 _("relocation overflow"));
3423 case BFD_RELOC_SPARC_5
:
3424 if (! in_bitfield_range (val
, 0x1f))
3425 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3426 _("relocation overflow"));
3430 case BFD_RELOC_SPARC_WDISP10
:
3433 || val
<= -(offsetT
) 0x808)
3434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3435 _("relocation overflow"));
3436 /* FIXME: The +1 deserves a comment. */
3437 val
= (val
>> 2) + 1;
3438 insn
|= ((val
& 0x300) << 11)
3439 | ((val
& 0xff) << 5);
3442 case BFD_RELOC_SPARC_WDISP16
:
3445 || val
<= -(offsetT
) 0x20008)
3446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3447 _("relocation overflow"));
3448 /* FIXME: The +1 deserves a comment. */
3449 val
= (val
>> 2) + 1;
3450 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3453 case BFD_RELOC_SPARC_WDISP19
:
3456 || val
<= -(offsetT
) 0x100008)
3457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3458 _("relocation overflow"));
3459 /* FIXME: The +1 deserves a comment. */
3460 val
= (val
>> 2) + 1;
3461 insn
|= val
& 0x7ffff;
3464 case BFD_RELOC_SPARC_HH22
:
3465 val
= BSR (val
, 32);
3468 case BFD_RELOC_SPARC_LM22
:
3469 case BFD_RELOC_HI22
:
3470 if (!fixP
->fx_addsy
)
3471 insn
|= (val
>> 10) & 0x3fffff;
3473 /* FIXME: Need comment explaining why we do this. */
3477 case BFD_RELOC_SPARC22
:
3478 if (val
& ~0x003fffff)
3479 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3480 _("relocation overflow"));
3481 insn
|= (val
& 0x3fffff);
3484 case BFD_RELOC_SPARC_HM10
:
3485 val
= BSR (val
, 32);
3488 case BFD_RELOC_LO10
:
3489 if (!fixP
->fx_addsy
)
3490 insn
|= val
& 0x3ff;
3492 /* FIXME: Need comment explaining why we do this. */
3496 case BFD_RELOC_SPARC_OLO10
:
3498 val
+= fixP
->tc_fix_data
;
3501 case BFD_RELOC_SPARC13
:
3502 if (! in_signed_range (val
, 0x1fff))
3503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3504 _("relocation overflow"));
3505 insn
|= val
& 0x1fff;
3508 case BFD_RELOC_SPARC_WDISP22
:
3509 val
= (val
>> 2) + 1;
3511 case BFD_RELOC_SPARC_BASE22
:
3512 insn
|= val
& 0x3fffff;
3515 case BFD_RELOC_SPARC_H34
:
3516 if (!fixP
->fx_addsy
)
3520 insn
|= tval
& 0x3fffff;
3524 case BFD_RELOC_SPARC_H44
:
3525 if (!fixP
->fx_addsy
)
3529 insn
|= tval
& 0x3fffff;
3533 case BFD_RELOC_SPARC_M44
:
3534 if (!fixP
->fx_addsy
)
3535 insn
|= (val
>> 12) & 0x3ff;
3538 case BFD_RELOC_SPARC_L44
:
3539 if (!fixP
->fx_addsy
)
3540 insn
|= val
& 0xfff;
3543 case BFD_RELOC_SPARC_HIX22
:
3544 if (!fixP
->fx_addsy
)
3546 val
^= ~(offsetT
) 0;
3547 insn
|= (val
>> 10) & 0x3fffff;
3551 case BFD_RELOC_SPARC_LOX10
:
3552 if (!fixP
->fx_addsy
)
3553 insn
|= 0x1c00 | (val
& 0x3ff);
3556 case BFD_RELOC_NONE
:
3558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3559 _("bad or unhandled relocation type: 0x%02x"),
3564 if (INSN_BIG_ENDIAN
)
3565 bfd_putb32 (insn
, (unsigned char *) buf
);
3567 bfd_putl32 (insn
, (unsigned char *) buf
);
3570 /* Are we finished with this relocation now? */
3571 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3575 /* Translate internal representation of relocation info to BFD target
3579 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3581 static arelent
*relocs
[3];
3583 bfd_reloc_code_real_type code
;
3585 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3588 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3589 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3590 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3592 switch (fixp
->fx_r_type
)
3596 case BFD_RELOC_HI22
:
3597 case BFD_RELOC_LO10
:
3598 case BFD_RELOC_32_PCREL_S2
:
3599 case BFD_RELOC_SPARC13
:
3600 case BFD_RELOC_SPARC22
:
3601 case BFD_RELOC_SPARC_PC22
:
3602 case BFD_RELOC_SPARC_PC10
:
3603 case BFD_RELOC_SPARC_BASE13
:
3604 case BFD_RELOC_SPARC_WDISP10
:
3605 case BFD_RELOC_SPARC_WDISP16
:
3606 case BFD_RELOC_SPARC_WDISP19
:
3607 case BFD_RELOC_SPARC_WDISP22
:
3609 case BFD_RELOC_SPARC_5
:
3610 case BFD_RELOC_SPARC_6
:
3611 case BFD_RELOC_SPARC_7
:
3612 case BFD_RELOC_SPARC_10
:
3613 case BFD_RELOC_SPARC_11
:
3614 case BFD_RELOC_SPARC_HH22
:
3615 case BFD_RELOC_SPARC_HM10
:
3616 case BFD_RELOC_SPARC_LM22
:
3617 case BFD_RELOC_SPARC_PC_HH22
:
3618 case BFD_RELOC_SPARC_PC_HM10
:
3619 case BFD_RELOC_SPARC_PC_LM22
:
3620 case BFD_RELOC_SPARC_H34
:
3621 case BFD_RELOC_SPARC_H44
:
3622 case BFD_RELOC_SPARC_M44
:
3623 case BFD_RELOC_SPARC_L44
:
3624 case BFD_RELOC_SPARC_HIX22
:
3625 case BFD_RELOC_SPARC_LOX10
:
3626 case BFD_RELOC_SPARC_REV32
:
3627 case BFD_RELOC_SPARC_OLO10
:
3628 case BFD_RELOC_SPARC_UA16
:
3629 case BFD_RELOC_SPARC_UA32
:
3630 case BFD_RELOC_SPARC_UA64
:
3631 case BFD_RELOC_8_PCREL
:
3632 case BFD_RELOC_16_PCREL
:
3633 case BFD_RELOC_32_PCREL
:
3634 case BFD_RELOC_64_PCREL
:
3635 case BFD_RELOC_SPARC_PLT32
:
3636 case BFD_RELOC_SPARC_PLT64
:
3637 case BFD_RELOC_VTABLE_ENTRY
:
3638 case BFD_RELOC_VTABLE_INHERIT
:
3639 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3640 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3641 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3642 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3643 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3644 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3645 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3646 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3647 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3648 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3649 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3650 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3651 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3652 case BFD_RELOC_SPARC_TLS_IE_LD
:
3653 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3654 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3655 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3656 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3657 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3658 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3659 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3660 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3661 case BFD_RELOC_SPARC_GOTDATA_OP
:
3662 code
= fixp
->fx_r_type
;
3669 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3670 /* If we are generating PIC code, we need to generate a different
3674 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3676 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3679 #define GOTT_BASE "__GOTT_BASE__"
3680 #define GOTT_INDEX "__GOTT_INDEX__"
3683 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3689 case BFD_RELOC_32_PCREL_S2
:
3690 if (generic_force_reloc (fixp
))
3691 code
= BFD_RELOC_SPARC_WPLT30
;
3693 case BFD_RELOC_HI22
:
3694 code
= BFD_RELOC_SPARC_GOT22
;
3695 if (fixp
->fx_addsy
!= NULL
)
3697 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3698 code
= BFD_RELOC_SPARC_PC22
;
3700 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3701 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3702 code
= BFD_RELOC_HI22
; /* Unchanged. */
3706 case BFD_RELOC_LO10
:
3707 code
= BFD_RELOC_SPARC_GOT10
;
3708 if (fixp
->fx_addsy
!= NULL
)
3710 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3711 code
= BFD_RELOC_SPARC_PC10
;
3713 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3714 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3715 code
= BFD_RELOC_LO10
; /* Unchanged. */
3719 case BFD_RELOC_SPARC13
:
3720 code
= BFD_RELOC_SPARC_GOT13
;
3726 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3728 /* Nothing is aligned in DWARF debugging sections. */
3729 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3732 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3733 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3734 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3738 if (code
== BFD_RELOC_SPARC_OLO10
)
3739 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3741 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3742 if (reloc
->howto
== 0)
3744 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3745 _("internal error: can't export reloc type %d (`%s')"),
3746 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3752 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3755 if (reloc
->howto
->pc_relative
== 0
3756 || code
== BFD_RELOC_SPARC_PC10
3757 || code
== BFD_RELOC_SPARC_PC22
)
3758 reloc
->addend
= fixp
->fx_addnumber
;
3759 else if (sparc_pic_code
3760 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3761 && fixp
->fx_addsy
!= NULL
3762 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3763 || S_IS_WEAK (fixp
->fx_addsy
))
3764 && S_IS_DEFINED (fixp
->fx_addsy
)
3765 && ! S_IS_COMMON (fixp
->fx_addsy
))
3766 reloc
->addend
= fixp
->fx_addnumber
;
3768 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3770 #else /* elf or coff */
3772 if (code
!= BFD_RELOC_32_PCREL_S2
3773 && code
!= BFD_RELOC_SPARC_WDISP22
3774 && code
!= BFD_RELOC_SPARC_WDISP16
3775 && code
!= BFD_RELOC_SPARC_WDISP19
3776 && code
!= BFD_RELOC_SPARC_WDISP10
3777 && code
!= BFD_RELOC_SPARC_WPLT30
3778 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
3779 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
3780 reloc
->addend
= fixp
->fx_addnumber
;
3781 else if (symbol_section_p (fixp
->fx_addsy
))
3782 reloc
->addend
= (section
->vma
3783 + fixp
->fx_addnumber
3784 + md_pcrel_from (fixp
));
3786 reloc
->addend
= fixp
->fx_offset
;
3789 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3790 on the same location. */
3791 if (code
== BFD_RELOC_SPARC_OLO10
)
3793 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3796 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3798 = symbol_get_bfdsym (section_symbol (absolute_section
));
3799 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3800 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3801 reloc
->addend
= fixp
->tc_fix_data
;
3807 /* We have no need to default values of symbols. */
3810 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
3815 /* Round up a section size to the appropriate boundary. */
3818 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
3821 /* This is not right for ELF; a.out wants it, and COFF will force
3822 the alignment anyways. */
3823 valueT align
= ((valueT
) 1
3824 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3827 /* Turn alignment value into a mask. */
3829 newsize
= (size
+ align
) & ~align
;
3836 /* Exactly what point is a PC-relative offset relative TO?
3837 On the sparc, they're relative to the address of the offset, plus
3838 its size. This gets us to the following instruction.
3839 (??? Is this right? FIXME-SOON) */
3841 md_pcrel_from (fixS
*fixP
)
3845 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3846 if (! sparc_pic_code
3847 || fixP
->fx_addsy
== NULL
3848 || symbol_section_p (fixP
->fx_addsy
))
3849 ret
+= fixP
->fx_size
;
3853 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3864 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3867 return (value
== 1) ? shift
: -1;
3870 /* Sort of like s_lcomm. */
3873 static int max_alignment
= 15;
3877 s_reserve (int ignore ATTRIBUTE_UNUSED
)
3887 name
= input_line_pointer
;
3888 c
= get_symbol_end ();
3889 p
= input_line_pointer
;
3893 if (*input_line_pointer
!= ',')
3895 as_bad (_("Expected comma after name"));
3896 ignore_rest_of_line ();
3900 ++input_line_pointer
;
3902 if ((size
= get_absolute_expression ()) < 0)
3904 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3905 ignore_rest_of_line ();
3910 symbolP
= symbol_find_or_make (name
);
3913 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3914 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3916 as_bad (_("bad .reserve segment -- expected BSS segment"));
3920 if (input_line_pointer
[2] == '.')
3921 input_line_pointer
+= 7;
3923 input_line_pointer
+= 6;
3926 if (*input_line_pointer
== ',')
3928 ++input_line_pointer
;
3931 if (*input_line_pointer
== '\n')
3933 as_bad (_("missing alignment"));
3934 ignore_rest_of_line ();
3938 align
= (int) get_absolute_expression ();
3941 if (align
> max_alignment
)
3943 align
= max_alignment
;
3944 as_warn (_("alignment too large; assuming %d"), align
);
3950 as_bad (_("negative alignment"));
3951 ignore_rest_of_line ();
3957 temp
= mylog2 (align
);
3960 as_bad (_("alignment not a power of 2"));
3961 ignore_rest_of_line ();
3968 record_alignment (bss_section
, align
);
3973 if (!S_IS_DEFINED (symbolP
)
3975 && S_GET_OTHER (symbolP
) == 0
3976 && S_GET_DESC (symbolP
) == 0
3983 segT current_seg
= now_seg
;
3984 subsegT current_subseg
= now_subseg
;
3986 /* Switch to bss. */
3987 subseg_set (bss_section
, 1);
3991 frag_align (align
, 0, 0);
3993 /* Detach from old frag. */
3994 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3995 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3997 symbol_set_frag (symbolP
, frag_now
);
3998 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3999 (offsetT
) size
, (char *) 0);
4002 S_SET_SEGMENT (symbolP
, bss_section
);
4004 subseg_set (current_seg
, current_subseg
);
4007 S_SET_SIZE (symbolP
, size
);
4013 as_warn (_("Ignoring attempt to re-define symbol %s"),
4014 S_GET_NAME (symbolP
));
4017 demand_empty_rest_of_line ();
4021 s_common (int ignore ATTRIBUTE_UNUSED
)
4029 name
= input_line_pointer
;
4030 c
= get_symbol_end ();
4031 /* Just after name is now '\0'. */
4032 p
= input_line_pointer
;
4035 if (*input_line_pointer
!= ',')
4037 as_bad (_("Expected comma after symbol-name"));
4038 ignore_rest_of_line ();
4043 input_line_pointer
++;
4045 if ((temp
= get_absolute_expression ()) < 0)
4047 as_bad (_(".COMMon length (%lu) out of range ignored"),
4048 (unsigned long) temp
);
4049 ignore_rest_of_line ();
4054 symbolP
= symbol_find_or_make (name
);
4056 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4058 as_bad (_("Ignoring attempt to re-define symbol"));
4059 ignore_rest_of_line ();
4062 if (S_GET_VALUE (symbolP
) != 0)
4064 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4066 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4067 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4073 S_SET_VALUE (symbolP
, (valueT
) size
);
4074 S_SET_EXTERNAL (symbolP
);
4077 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4078 if (*input_line_pointer
!= ',')
4080 as_bad (_("Expected comma after common length"));
4081 ignore_rest_of_line ();
4084 input_line_pointer
++;
4086 if (*input_line_pointer
!= '"')
4088 temp
= get_absolute_expression ();
4091 if (temp
> max_alignment
)
4093 temp
= max_alignment
;
4094 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4100 as_bad (_("negative alignment"));
4101 ignore_rest_of_line ();
4106 if (symbol_get_obj (symbolP
)->local
)
4113 old_subsec
= now_subseg
;
4118 align
= mylog2 (temp
);
4122 as_bad (_("alignment not a power of 2"));
4123 ignore_rest_of_line ();
4127 record_alignment (bss_section
, align
);
4128 subseg_set (bss_section
, 0);
4130 frag_align (align
, 0, 0);
4131 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4132 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4133 symbol_set_frag (symbolP
, frag_now
);
4134 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4135 (offsetT
) size
, (char *) 0);
4137 S_SET_SEGMENT (symbolP
, bss_section
);
4138 S_CLEAR_EXTERNAL (symbolP
);
4139 S_SET_SIZE (symbolP
, size
);
4140 subseg_set (old_sec
, old_subsec
);
4143 #endif /* OBJ_ELF */
4146 S_SET_VALUE (symbolP
, (valueT
) size
);
4148 S_SET_ALIGN (symbolP
, temp
);
4149 S_SET_SIZE (symbolP
, size
);
4151 S_SET_EXTERNAL (symbolP
);
4152 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4157 input_line_pointer
++;
4158 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4159 if (*input_line_pointer
== '.')
4160 input_line_pointer
++;
4161 /* @@ Some say data, some say bss. */
4162 if (strncmp (input_line_pointer
, "bss\"", 4)
4163 && strncmp (input_line_pointer
, "data\"", 5))
4165 while (*--input_line_pointer
!= '"')
4167 input_line_pointer
--;
4168 goto bad_common_segment
;
4170 while (*input_line_pointer
++ != '"')
4172 goto allocate_common
;
4175 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4177 demand_empty_rest_of_line ();
4182 p
= input_line_pointer
;
4183 while (*p
&& *p
!= '\n')
4187 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4189 input_line_pointer
= p
;
4190 ignore_rest_of_line ();
4195 /* Handle the .empty pseudo-op. This suppresses the warnings about
4196 invalid delay slot usage. */
4199 s_empty (int ignore ATTRIBUTE_UNUSED
)
4201 /* The easy way to implement is to just forget about the last
4207 s_seg (int ignore ATTRIBUTE_UNUSED
)
4210 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4212 input_line_pointer
+= 6;
4216 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4218 input_line_pointer
+= 6;
4222 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4224 input_line_pointer
+= 7;
4228 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4230 input_line_pointer
+= 5;
4231 /* We only support 2 segments -- text and data -- for now, so
4232 things in the "bss segment" will have to go into data for now.
4233 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4234 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4237 as_bad (_("Unknown segment type"));
4238 demand_empty_rest_of_line ();
4244 subseg_set (data_section
, 1);
4245 demand_empty_rest_of_line ();
4249 s_proc (int ignore ATTRIBUTE_UNUSED
)
4251 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4253 ++input_line_pointer
;
4255 ++input_line_pointer
;
4258 /* This static variable is set by s_uacons to tell sparc_cons_align
4259 that the expression does not need to be aligned. */
4261 static int sparc_no_align_cons
= 0;
4263 /* This static variable is set by sparc_cons to emit requested types
4264 of relocations in cons_fix_new_sparc. */
4266 static const char *sparc_cons_special_reloc
;
4268 /* This handles the unaligned space allocation pseudo-ops, such as
4269 .uaword. .uaword is just like .word, but the value does not need
4273 s_uacons (int bytes
)
4275 /* Tell sparc_cons_align not to align this value. */
4276 sparc_no_align_cons
= 1;
4278 sparc_no_align_cons
= 0;
4281 /* This handles the native word allocation pseudo-op .nword.
4282 For sparc_arch_size 32 it is equivalent to .word, for
4283 sparc_arch_size 64 it is equivalent to .xword. */
4286 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4288 cons (sparc_arch_size
== 32 ? 4 : 8);
4292 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4296 .register %g[2367],{#scratch|symbolname|#ignore}
4300 s_register (int ignore ATTRIBUTE_UNUSED
)
4305 const char *regname
;
4307 if (input_line_pointer
[0] != '%'
4308 || input_line_pointer
[1] != 'g'
4309 || ((input_line_pointer
[2] & ~1) != '2'
4310 && (input_line_pointer
[2] & ~1) != '6')
4311 || input_line_pointer
[3] != ',')
4312 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4313 reg
= input_line_pointer
[2] - '0';
4314 input_line_pointer
+= 4;
4316 if (*input_line_pointer
== '#')
4318 ++input_line_pointer
;
4319 regname
= input_line_pointer
;
4320 c
= get_symbol_end ();
4321 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4322 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4323 if (regname
[0] == 'i')
4330 regname
= input_line_pointer
;
4331 c
= get_symbol_end ();
4333 if (sparc_arch_size
== 64)
4337 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4338 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4339 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4340 as_bad (_("redefinition of global register"));
4344 if (regname
== NULL
)
4345 globals
[reg
] = (symbolS
*) 1;
4350 if (symbol_find (regname
))
4351 as_bad (_("Register symbol %s already defined."),
4354 globals
[reg
] = symbol_make (regname
);
4355 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4357 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4358 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4359 flags
|= BSF_GLOBAL
;
4360 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4361 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4362 S_SET_ALIGN (globals
[reg
], reg
);
4363 S_SET_SIZE (globals
[reg
], 0);
4364 /* Although we actually want undefined_section here,
4365 we have to use absolute_section, because otherwise
4366 generic as code will make it a COM section.
4367 We fix this up in sparc_adjust_symtab. */
4368 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4369 S_SET_OTHER (globals
[reg
], 0);
4370 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4371 ->internal_elf_sym
.st_info
=
4372 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4373 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4374 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4379 *input_line_pointer
= c
;
4381 demand_empty_rest_of_line ();
4384 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4385 symbols which need it. */
4388 sparc_adjust_symtab (void)
4392 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4394 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4395 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4398 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4399 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4402 S_SET_SEGMENT (sym
, undefined_section
);
4407 /* If the --enforce-aligned-data option is used, we require .word,
4408 et. al., to be aligned correctly. We do it by setting up an
4409 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4410 no unexpected alignment was introduced.
4412 The SunOS and Solaris native assemblers enforce aligned data by
4413 default. We don't want to do that, because gcc can deliberately
4414 generate misaligned data if the packed attribute is used. Instead,
4415 we permit misaligned data by default, and permit the user to set an
4416 option to check for it. */
4419 sparc_cons_align (int nbytes
)
4423 /* Only do this if we are enforcing aligned data. */
4424 if (! enforce_aligned_data
)
4427 /* Don't align if this is an unaligned pseudo-op. */
4428 if (sparc_no_align_cons
)
4431 nalign
= mylog2 (nbytes
);
4435 gas_assert (nalign
> 0);
4437 if (now_seg
== absolute_section
)
4439 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4440 as_bad (_("misaligned data"));
4444 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4445 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4447 record_alignment (now_seg
, nalign
);
4450 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4453 sparc_handle_align (fragS
*fragp
)
4458 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4460 switch (fragp
->fr_type
)
4464 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4468 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4479 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4481 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4482 if (INSN_BIG_ENDIAN
)
4483 number_to_chars_bigendian (p
, wval
, 4);
4485 number_to_chars_littleendian (p
, wval
, 4);
4491 if (INSN_BIG_ENDIAN
)
4492 number_to_chars_bigendian (p
, 0x01000000, 4);
4494 number_to_chars_littleendian (p
, 0x01000000, 4);
4496 fragp
->fr_fix
+= fix
;
4506 /* Some special processing for a Sparc ELF file. */
4509 sparc_elf_final_processing (void)
4511 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4512 sort of BFD interface for this. */
4513 if (sparc_arch_size
== 64)
4515 switch (sparc_memory_model
)
4518 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4521 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4527 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4528 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4529 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4530 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4531 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4532 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4536 sparc_cons (expressionS
*exp
, int size
)
4541 sparc_cons_special_reloc
= NULL
;
4542 save
= input_line_pointer
;
4543 if (input_line_pointer
[0] == '%'
4544 && input_line_pointer
[1] == 'r'
4545 && input_line_pointer
[2] == '_')
4547 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4549 input_line_pointer
+= 7;
4550 sparc_cons_special_reloc
= "disp";
4552 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4554 if (size
!= 4 && size
!= 8)
4555 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4558 input_line_pointer
+= 6;
4559 sparc_cons_special_reloc
= "plt";
4562 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4564 if (size
!= 4 && size
!= 8)
4565 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4568 input_line_pointer
+= 13;
4569 sparc_cons_special_reloc
= "tls_dtpoff";
4572 if (sparc_cons_special_reloc
)
4579 if (*input_line_pointer
!= '8')
4581 input_line_pointer
--;
4584 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4588 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4592 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4602 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4603 sparc_cons_special_reloc
, size
* 8, size
);
4607 input_line_pointer
+= 2;
4608 if (*input_line_pointer
!= '(')
4610 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4611 sparc_cons_special_reloc
, size
* 8);
4618 input_line_pointer
= save
;
4619 sparc_cons_special_reloc
= NULL
;
4624 char *end
= ++input_line_pointer
;
4627 while (! is_end_of_line
[(c
= *end
)])
4641 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4642 sparc_cons_special_reloc
, size
* 8);
4648 if (input_line_pointer
!= end
)
4650 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4651 sparc_cons_special_reloc
, size
* 8);
4655 input_line_pointer
++;
4657 c
= *input_line_pointer
;
4658 if (! is_end_of_line
[c
] && c
!= ',')
4659 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4660 sparc_cons_special_reloc
, size
* 8);
4666 if (sparc_cons_special_reloc
== NULL
)
4672 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4673 reloc for a cons. We could use the definition there, except that
4674 we want to handle little endian relocs specially. */
4677 cons_fix_new_sparc (fragS
*frag
,
4679 unsigned int nbytes
,
4682 bfd_reloc_code_real_type r
;
4684 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4685 (nbytes
== 2 ? BFD_RELOC_16
:
4686 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4688 if (target_little_endian_data
4690 && now_seg
->flags
& SEC_ALLOC
)
4691 r
= BFD_RELOC_SPARC_REV32
;
4693 if (sparc_cons_special_reloc
)
4695 if (*sparc_cons_special_reloc
== 'd')
4698 case 1: r
= BFD_RELOC_8_PCREL
; break;
4699 case 2: r
= BFD_RELOC_16_PCREL
; break;
4700 case 4: r
= BFD_RELOC_32_PCREL
; break;
4701 case 8: r
= BFD_RELOC_64_PCREL
; break;
4704 else if (*sparc_cons_special_reloc
== 'p')
4707 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4708 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4713 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4714 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4717 else if (sparc_no_align_cons
)
4721 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4722 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4723 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4728 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4729 sparc_cons_special_reloc
= NULL
;
4733 sparc_cfi_frame_initial_instructions (void)
4735 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4739 sparc_regname_to_dw2regnum (char *regname
)
4747 p
= strchr (q
, regname
[0]);
4750 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
4752 return (p
- q
) * 8 + regname
[1] - '0';
4754 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
4756 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
4758 if (regname
[0] == 'f' || regname
[0] == 'r')
4760 unsigned int regnum
;
4762 regnum
= strtoul (regname
+ 1, &q
, 10);
4765 if (regnum
>= ((regname
[0] == 'f'
4766 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
4769 if (regname
[0] == 'f')
4772 if (regnum
>= 64 && (regnum
& 1))
4781 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
4783 sparc_cons_special_reloc
= "disp";
4784 sparc_no_align_cons
= 1;
4785 emit_expr (exp
, nbytes
);
4786 sparc_no_align_cons
= 0;
4787 sparc_cons_special_reloc
= NULL
;