1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 97, 98, 1999 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 59 Temple Place - Suite 330,
18 Boston, MA 02111-1307, USA. */
26 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
32 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
33 static void init_default_arch
PARAMS ((void));
34 static int sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
35 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
36 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
37 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
38 static int sparc_ffs
PARAMS ((unsigned int));
39 static void synthetize_setuw
PARAMS ((const struct sparc_opcode
*));
40 static void synthetize_setsw
PARAMS ((const struct sparc_opcode
*));
41 static void synthetize_setx
PARAMS ((const struct sparc_opcode
*));
42 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
43 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
44 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
45 static int parse_const_expr_arg
PARAMS ((char **, int *));
46 static int get_expression
PARAMS ((char *str
));
48 /* Default architecture. */
49 /* ??? The default value should be V8, but sparclite support was added
50 by making it the default. GCC now passes -Asparclite, so maybe sometime in
51 the future we can set this to V8. */
53 #define DEFAULT_ARCH "sparclite"
55 static char *default_arch
= DEFAULT_ARCH
;
57 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
59 static int default_init_p
;
61 /* Current architecture. We don't bump up unless necessary. */
62 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
64 /* The maximum architecture level we can bump up to.
65 In a 32 bit environment, don't allow bumping up to v9 by default.
66 The native assembler works this way. The user is required to pass
67 an explicit argument before we'll create v9 object files. However, if
68 we don't see any v9 insns, a v8plus object file is not created. */
69 static enum sparc_opcode_arch_val max_architecture
;
71 /* Either 32 or 64, selects file format. */
72 static int sparc_arch_size
;
73 /* Initial (default) value, recorded separately in case a user option
74 changes the value before md_show_usage is called. */
75 static int default_arch_size
;
78 /* The currently selected v9 memory model. Currently only used for
80 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
83 static int architecture_requested
;
84 static int warn_on_bump
;
86 /* If warn_on_bump and the needed architecture is higher than this
87 architecture, issue a warning. */
88 static enum sparc_opcode_arch_val warn_after_architecture
;
90 /* Non-zero if as should generate error if an undeclared g[23] register
91 has been used in -64. */
92 static int no_undeclared_regs
;
94 /* Non-zero if we are generating PIC code. */
97 /* Non-zero if we should give an error when misaligned data is seen. */
98 static int enforce_aligned_data
;
100 extern int target_big_endian
;
102 static int target_little_endian_data
;
104 /* Symbols for global registers on v9. */
105 static symbolS
*globals
[8];
107 /* V9 and 86x have big and little endian data, but instructions are always big
108 endian. The sparclet has bi-endian support but both data and insns have
109 the same endianness. Global `target_big_endian' is used for data.
110 The following macro is used for instructions. */
111 #ifndef INSN_BIG_ENDIAN
112 #define INSN_BIG_ENDIAN (target_big_endian \
113 || default_arch_type == sparc86x \
114 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
117 /* handle of the OPCODE hash table */
118 static struct hash_control
*op_hash
;
120 static int log2
PARAMS ((int));
121 static void s_data1
PARAMS ((void));
122 static void s_seg
PARAMS ((int));
123 static void s_proc
PARAMS ((int));
124 static void s_reserve
PARAMS ((int));
125 static void s_common
PARAMS ((int));
126 static void s_empty
PARAMS ((int));
127 static void s_uacons
PARAMS ((int));
128 static void s_ncons
PARAMS ((int));
129 static void s_register
PARAMS ((int));
131 const pseudo_typeS md_pseudo_table
[] =
133 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
134 {"common", s_common
, 0},
135 {"empty", s_empty
, 0},
136 {"global", s_globl
, 0},
138 {"nword", s_ncons
, 0},
139 {"optim", s_ignore
, 0},
141 {"reserve", s_reserve
, 0},
143 {"skip", s_space
, 0},
146 {"uahalf", s_uacons
, 2},
147 {"uaword", s_uacons
, 4},
148 {"uaxword", s_uacons
, 8},
150 /* these are specific to sparc/svr4 */
151 {"2byte", s_uacons
, 2},
152 {"4byte", s_uacons
, 4},
153 {"8byte", s_uacons
, 8},
154 {"register", s_register
, 0},
159 const int md_reloc_size
= 12; /* Size of relocation record */
161 /* This array holds the chars that always start a comment. If the
162 pre-processor is disabled, these aren't very useful */
163 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
165 /* This array holds the chars that only start a comment at the beginning of
166 a line. If the line seems to have the form '# 123 filename'
167 .line and .file directives will appear in the pre-processed output */
168 /* Note that input_file.c hand checks for '#' at the beginning of the
169 first line of the input file. This is because the compiler outputs
170 #NO_APP at the beginning of its output. */
171 /* Also note that comments started like this one will always
172 work if '/' isn't otherwise defined. */
173 const char line_comment_chars
[] = "#";
175 const char line_separator_chars
[] = "";
177 /* Chars that can be used to separate mant from exp in floating point nums */
178 const char EXP_CHARS
[] = "eE";
180 /* Chars that mean this number is a floating point constant */
183 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
185 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
186 changed in read.c. Ideally it shouldn't have to know about it at all,
187 but nothing is ideal around here. */
189 #define isoctal(c) ((unsigned)((c) - '0') < '8')
194 unsigned long opcode
;
195 struct nlist
*nlistp
;
199 bfd_reloc_code_real_type reloc
;
202 struct sparc_it the_insn
, set_insn
;
204 static void output_insn
205 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
207 /* Table of arguments to -A.
208 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
209 for this use. That table is for opcodes only. This table is for opcodes
212 enum sparc_arch_types
{v6
, v7
, v8
, sparclet
, sparclite
, sparc86x
, v8plus
,
213 v8plusa
, v9
, v9a
, v9_64
};
215 static struct sparc_arch
{
218 enum sparc_arch_types arch_type
;
219 /* Default word size, as specified during configuration.
220 A value of zero means can't be used to specify default architecture. */
221 int default_arch_size
;
222 /* Allowable arg to -A? */
224 } sparc_arch_table
[] = {
225 { "v6", "v6", v6
, 0, 1 },
226 { "v7", "v7", v7
, 0, 1 },
227 { "v8", "v8", v8
, 32, 1 },
228 { "sparclet", "sparclet", sparclet
, 32, 1 },
229 { "sparclite", "sparclite", sparclite
, 32, 1 },
230 { "sparc86x", "sparclite", sparc86x
, 32, 1 },
231 { "v8plus", "v9", v9
, 0, 1 },
232 { "v8plusa", "v9a", v9
, 0, 1 },
233 { "v9", "v9", v9
, 0, 1 },
234 { "v9a", "v9a", v9
, 0, 1 },
235 /* This exists to allow configure.in/Makefile.in to pass one
236 value to specify both the default machine and default word size. */
237 { "v9-64", "v9", v9
, 64, 0 },
238 { NULL
, NULL
, v8
, 0, 0 }
241 /* Variant of default_arch */
242 static enum sparc_arch_types default_arch_type
;
244 static struct sparc_arch
*
248 struct sparc_arch
*sa
;
250 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
251 if (strcmp (sa
->name
, name
) == 0)
253 if (sa
->name
== NULL
)
258 /* Initialize the default opcode arch and word size from the default
259 architecture name. */
264 struct sparc_arch
*sa
= lookup_arch (default_arch
);
267 || sa
->default_arch_size
== 0)
268 as_fatal (_("Invalid default architecture, broken assembler."));
270 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
271 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
272 as_fatal (_("Bad opcode table, broken assembler."));
273 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
275 default_arch_type
= sa
->arch_type
;
278 /* Called by TARGET_FORMAT. */
281 sparc_target_format ()
283 /* We don't get a chance to initialize anything before we're called,
284 so handle that now. */
285 if (! default_init_p
)
286 init_default_arch ();
290 return "a.out-sparc-netbsd";
293 if (target_big_endian
)
294 return "a.out-sunos-big";
295 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
296 return "a.out-sunos-big";
297 else return "a.out-sparc-little";
299 return "a.out-sunos-big";
310 return "coff-sparc-lynx";
317 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
325 * Invocation line includes a switch not recognized by the base assembler.
326 * See if it's a processor-specific option. These are:
329 * Warn on architecture bumps. See also -A.
331 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
332 * Standard 32 bit architectures.
333 * -Av8plus, -Av8plusa
334 * Sparc64 in a 32 bit world.
336 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
337 * This used to only mean 64 bits, but properly specifying it
338 * complicated gcc's ASM_SPECs, so now opcode selection is
339 * specified orthogonally to word size (except when specifying
340 * the default, but that is an internal implementation detail).
341 * -xarch=v8plus, -xarch=v8plusa
342 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
344 * Select the architecture and possibly the file format.
345 * Instructions or features not supported by the selected
346 * architecture cause fatal errors.
348 * The default is to start at v6, and bump the architecture up
349 * whenever an instruction is seen at a higher level. In 32 bit
350 * environments, v9 is not bumped up to, the user must pass
353 * If -bump is specified, a warning is printing when bumping to
356 * If an architecture is specified, all instructions must match
357 * that architecture. Any higher level instructions are flagged
358 * as errors. Note that in the 32 bit environment specifying
359 * -Av8plus does not automatically create a v8plus object file, a
360 * v9 insn must be seen.
362 * If both an architecture and -bump are specified, the
363 * architecture starts at the specified level, but bumps are
364 * warnings. Note that we can't set `current_architecture' to
365 * the requested level in this case: in the 32 bit environment,
366 * we still must avoid creating v8plus object files unless v9
370 * Bumping between incompatible architectures is always an
371 * error. For example, from sparclite to v9.
375 CONST
char *md_shortopts
= "A:K:VQ:sq";
378 CONST
char *md_shortopts
= "A:k";
380 CONST
char *md_shortopts
= "A:";
383 struct option md_longopts
[] = {
384 #define OPTION_BUMP (OPTION_MD_BASE)
385 {"bump", no_argument
, NULL
, OPTION_BUMP
},
386 #define OPTION_SPARC (OPTION_MD_BASE + 1)
387 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
388 #define OPTION_XARCH (OPTION_MD_BASE + 2)
389 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
391 #define OPTION_32 (OPTION_MD_BASE + 3)
392 {"32", no_argument
, NULL
, OPTION_32
},
393 #define OPTION_64 (OPTION_MD_BASE + 4)
394 {"64", no_argument
, NULL
, OPTION_64
},
395 #define OPTION_TSO (OPTION_MD_BASE + 5)
396 {"TSO", no_argument
, NULL
, OPTION_TSO
},
397 #define OPTION_PSO (OPTION_MD_BASE + 6)
398 {"PSO", no_argument
, NULL
, OPTION_PSO
},
399 #define OPTION_RMO (OPTION_MD_BASE + 7)
400 {"RMO", no_argument
, NULL
, OPTION_RMO
},
402 #ifdef SPARC_BIENDIAN
403 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
404 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
405 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
406 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
408 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
409 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
410 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
411 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
413 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
414 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
416 {NULL
, no_argument
, NULL
, 0}
418 size_t md_longopts_size
= sizeof(md_longopts
);
421 md_parse_option (c
, arg
)
425 /* We don't get a chance to initialize anything before we're called,
426 so handle that now. */
427 if (! default_init_p
)
428 init_default_arch ();
434 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
438 /* This is for compatibility with Sun's assembler. */
439 if (strcmp (arg
, "v8plus") != 0
440 && strcmp (arg
, "v8plusa") != 0)
442 as_bad (_("invalid architecture -xarch=%s"), arg
);
450 struct sparc_arch
*sa
;
451 enum sparc_opcode_arch_val opcode_arch
;
453 sa
= lookup_arch (arg
);
455 || ! sa
->user_option_p
)
457 as_bad (_("invalid architecture -A%s"), arg
);
461 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
462 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
463 as_fatal (_("Bad opcode table, broken assembler."));
465 max_architecture
= opcode_arch
;
466 architecture_requested
= 1;
471 /* Ignore -sparc, used by SunOS make default .s.o rule. */
474 case OPTION_ENFORCE_ALIGNED_DATA
:
475 enforce_aligned_data
= 1;
478 #ifdef SPARC_BIENDIAN
479 case OPTION_LITTLE_ENDIAN
:
480 target_big_endian
= 0;
481 if (default_arch_type
!= sparclet
)
482 as_fatal ("This target does not support -EL");
484 case OPTION_LITTLE_ENDIAN_DATA
:
485 target_little_endian_data
= 1;
486 target_big_endian
= 0;
487 if (default_arch_type
!= sparc86x
488 && default_arch_type
!= v9
)
489 as_fatal ("This target does not support --little-endian-data");
491 case OPTION_BIG_ENDIAN
:
492 target_big_endian
= 1;
506 const char **list
, **l
;
508 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
509 list
= bfd_target_list ();
510 for (l
= list
; *l
!= NULL
; l
++)
512 if (sparc_arch_size
== 32)
514 if (strcmp (*l
, "elf32-sparc") == 0)
519 if (strcmp (*l
, "elf64-sparc") == 0)
524 as_fatal (_("No compiled in support for %d bit object file format"),
531 sparc_memory_model
= MM_TSO
;
535 sparc_memory_model
= MM_PSO
;
539 sparc_memory_model
= MM_RMO
;
547 /* Qy - do emit .comment
548 Qn - do not emit .comment */
552 /* use .stab instead of .stab.excl */
556 /* quick -- native assembler does fewer checks */
560 if (strcmp (arg
, "PIC") != 0)
561 as_warn (_("Unrecognized option following -K"));
566 case OPTION_NO_UNDECLARED_REGS
:
567 no_undeclared_regs
= 1;
579 md_show_usage (stream
)
582 const struct sparc_arch
*arch
;
584 /* We don't get a chance to initialize anything before we're called,
585 so handle that now. */
586 if (! default_init_p
)
587 init_default_arch ();
589 fprintf(stream
, _("SPARC options:\n"));
590 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
592 if (arch
!= &sparc_arch_table
[0])
593 fprintf (stream
, " | ");
594 if (arch
->user_option_p
)
595 fprintf (stream
, "-A%s", arch
->name
);
597 fprintf (stream
, _("\n-xarch=v8plus | -xarch=v8plusa\n"));
598 fprintf (stream
, _("\
599 specify variant of SPARC architecture\n\
600 -bump warn when assembler switches architectures\n\
602 --enforce-aligned-data force .long, etc., to be aligned correctly\n"));
604 fprintf (stream
, _("\
605 -k generate PIC\n"));
608 fprintf (stream
, _("\
609 -32 create 32 bit object file\n\
610 -64 create 64 bit object file\n"));
611 fprintf (stream
, _("\
612 [default is %d]\n"), default_arch_size
);
613 fprintf (stream
, _("\
614 -TSO use Total Store Ordering\n\
615 -PSO use Partial Store Ordering\n\
616 -RMO use Relaxed Memory Ordering\n"));
617 fprintf (stream
, _("\
618 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
619 fprintf (stream
, _("\
620 -KPIC generate PIC\n\
621 -V print assembler version number\n\
626 #ifdef SPARC_BIENDIAN
627 fprintf (stream
, _("\
628 -EL generate code for a little endian machine\n\
629 -EB generate code for a big endian machine\n\
630 --little-endian-data generate code for a machine having big endian\n\
631 instructions and little endian data."));
635 /* native operand size opcode translation */
641 } native_op_table
[] =
643 {"ldn", "ld", "ldx"},
644 {"ldna", "lda", "ldxa"},
645 {"stn", "st", "stx"},
646 {"stna", "sta", "stxa"},
647 {"slln", "sll", "sllx"},
648 {"srln", "srl", "srlx"},
649 {"sran", "sra", "srax"},
650 {"casn", "cas", "casx"},
651 {"casna", "casa", "casxa"},
652 {"clrn", "clr", "clrx"},
656 /* sparc64 priviledged registers */
658 struct priv_reg_entry
664 struct priv_reg_entry priv_reg_table
[] =
683 {"", -1}, /* end marker */
686 /* v9a specific asrs */
688 struct priv_reg_entry v9a_asr_table
[] =
697 {"clear_softint", 21},
698 {"", -1}, /* end marker */
702 cmp_reg_entry (parg
, qarg
)
706 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
707 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
709 return strcmp (q
->name
, p
->name
);
712 /* This function is called once, at assembler startup time. It should
713 set up all the tables, etc. that the MD part of the assembler will need. */
718 register const char *retval
= NULL
;
720 register unsigned int i
= 0;
722 /* We don't get a chance to initialize anything before md_parse_option
723 is called, and it may not be called, so handle default initialization
724 now if not already done. */
725 if (! default_init_p
)
726 init_default_arch ();
728 op_hash
= hash_new ();
730 while (i
< (unsigned int) sparc_num_opcodes
)
732 const char *name
= sparc_opcodes
[i
].name
;
733 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
736 as_bad (_("Internal error: can't hash `%s': %s\n"),
737 sparc_opcodes
[i
].name
, retval
);
742 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
744 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
745 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
750 while (i
< (unsigned int) sparc_num_opcodes
751 && !strcmp (sparc_opcodes
[i
].name
, name
));
754 for (i
= 0; native_op_table
[i
].name
; i
++)
756 const struct sparc_opcode
*insn
;
757 char *name
= sparc_arch_size
== 32 ? native_op_table
[i
].name32
:
758 native_op_table
[i
].name64
;
759 insn
= (struct sparc_opcode
*)hash_find (op_hash
, name
);
762 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
763 name
, native_op_table
[i
].name
);
768 retval
= hash_insert (op_hash
, native_op_table
[i
].name
, (PTR
) insn
);
771 as_bad (_("Internal error: can't hash `%s': %s\n"),
772 sparc_opcodes
[i
].name
, retval
);
779 as_fatal (_("Broken assembler. No assembly attempted."));
781 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
782 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
784 /* If -bump, record the architecture level at which we start issuing
785 warnings. The behaviour is different depending upon whether an
786 architecture was explicitly specified. If it wasn't, we issue warnings
787 for all upwards bumps. If it was, we don't start issuing warnings until
788 we need to bump beyond the requested architecture or when we bump between
789 conflicting architectures. */
792 && architecture_requested
)
794 /* `max_architecture' records the requested architecture.
795 Issue warnings if we go above it. */
796 warn_after_architecture
= max_architecture
;
798 /* Find the highest architecture level that doesn't conflict with
799 the requested one. */
800 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
801 max_architecture
> warn_after_architecture
;
803 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
804 warn_after_architecture
))
809 /* Called after all assembly has been done. */
814 if (sparc_arch_size
== 64)
816 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
817 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
819 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
823 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
824 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
825 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
826 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
827 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
828 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
829 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
830 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclite_le
);
833 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
834 be but for now it is (since that's the way it's always been
836 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
841 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
844 in_signed_range (val
, max
)
845 bfd_signed_vma val
, max
;
849 /* Sign-extend the value from the architecture word size, so that
850 0xffffffff is always considered -1 on sparc32. */
851 if (sparc_arch_size
== 32)
853 bfd_signed_vma sign
= (bfd_signed_vma
)1 << 31;
854 val
= ((val
& 0xffffffff) ^ sign
) - sign
;
863 /* Return non-zero if VAL is in the range 0 to MAX. */
866 in_unsigned_range (val
, max
)
874 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
875 (e.g. -15 to +31). */
878 in_bitfield_range (val
, max
)
879 bfd_signed_vma val
, max
;
885 if (val
< ~(max
>> 1))
899 for (i
= 0; (mask
& 1) == 0; ++i
)
904 /* Implement big shift right. */
910 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
911 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
912 return val
>> amount
;
915 /* For communication between sparc_ip and get_expression. */
916 static char *expr_end
;
918 /* Values for `special_case'.
919 Instructions that require wierd handling because they're longer than
921 #define SPECIAL_CASE_NONE 0
922 #define SPECIAL_CASE_SET 1
923 #define SPECIAL_CASE_SETSW 2
924 #define SPECIAL_CASE_SETX 3
925 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
926 #define SPECIAL_CASE_FDIV 4
928 /* Bit masks of various insns. */
929 #define NOP_INSN 0x01000000
930 #define OR_INSN 0x80100000
931 #define XOR_INSN 0x80180000
932 #define FMOVS_INSN 0x81A00020
933 #define SETHI_INSN 0x01000000
934 #define SLLX_INSN 0x81281000
935 #define SRA_INSN 0x81380000
937 /* The last instruction to be assembled. */
938 static const struct sparc_opcode
*last_insn
;
939 /* The assembled opcode of `last_insn'. */
940 static unsigned long last_opcode
;
942 /* Handle the set and setuw synthetic instructions. */
944 synthetize_setuw (insn
)
945 const struct sparc_opcode
*insn
;
948 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
950 if (the_insn
.exp
.X_op
== O_constant
)
952 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
954 if (sizeof(offsetT
) > 4
955 && (the_insn
.exp
.X_add_number
< 0
956 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
957 as_warn (_("set: number not in 0..4294967295 range"));
961 if (sizeof(offsetT
) > 4
962 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
963 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
964 as_warn (_("set: number not in -2147483648..4294967295 range"));
965 the_insn
.exp
.X_add_number
= (int)the_insn
.exp
.X_add_number
;
969 /* See if operand is absolute and small; skip sethi if so. */
970 if (the_insn
.exp
.X_op
!= O_constant
971 || the_insn
.exp
.X_add_number
>= (1 << 12)
972 || the_insn
.exp
.X_add_number
< -(1 << 12))
974 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
975 | ((the_insn
.exp
.X_add_number
>> 10)
976 & (the_insn
.exp
.X_op
== O_constant
? 0x3fffff : 0)));
977 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
980 output_insn (insn
, &the_insn
);
984 /* See if operand has no low-order bits; skip OR if so. */
985 if (the_insn
.exp
.X_op
!= O_constant
986 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
989 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
991 | (the_insn
.exp
.X_add_number
992 & (the_insn
.exp
.X_op
!= O_constant
? 0 :
993 need_hi22_p
? 0x3ff : 0x1fff)));
994 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
997 output_insn (insn
, &the_insn
);
1001 /* Handle the setsw synthetic instruction. */
1003 synthetize_setsw (insn
)
1004 const struct sparc_opcode
*insn
;
1008 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1010 if (the_insn
.exp
.X_op
!= O_constant
)
1012 synthetize_setuw (insn
);
1014 /* Need to sign extend it. */
1015 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1016 the_insn
.reloc
= BFD_RELOC_NONE
;
1017 output_insn (insn
, &the_insn
);
1021 if (sizeof(offsetT
) > 4
1022 && (the_insn
.exp
.X_add_number
< -(offsetT
) 0x80000000
1023 || the_insn
.exp
.X_add_number
> (offsetT
) 0xffffffff))
1024 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1026 low32
= the_insn
.exp
.X_add_number
;
1030 synthetize_setuw (insn
);
1036 the_insn
.reloc
= BFD_RELOC_NONE
;
1037 /* See if operand is absolute and small; skip sethi if so. */
1038 if (low32
< -(1 << 12))
1040 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1041 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1042 output_insn (insn
, &the_insn
);
1043 low32
= 0x1c00 | (low32
& 0x3ff);
1044 opc
= RS1 (rd
) | XOR_INSN
;
1047 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1048 | (low32
& 0x1fff));
1049 output_insn (insn
, &the_insn
);
1052 /* Handle the setsw synthetic instruction. */
1054 synthetize_setx (insn
)
1055 const struct sparc_opcode
*insn
;
1057 int upper32
, lower32
;
1058 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1059 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1061 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1062 int need_xor10_p
= 0;
1064 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
1065 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1066 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1069 upper_dstreg
= tmpreg
;
1070 /* The tmp reg should not be the dst reg. */
1071 if (tmpreg
== dstreg
)
1072 as_warn (_("setx: temporary register same as destination register"));
1074 /* ??? Obviously there are other optimizations we can do
1075 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1076 doing some of these. Later. If you do change things, try to
1077 change all of this to be table driven as well. */
1078 /* What to output depends on the number if it's constant.
1079 Compute that first, then output what we've decided upon. */
1080 if (the_insn
.exp
.X_op
!= O_constant
)
1082 if (sparc_arch_size
== 32)
1084 /* When arch size is 32, we want setx to be equivalent
1085 to setuw for anything but constants. */
1086 the_insn
.exp
.X_add_number
&= 0xffffffff;
1087 synthetize_setuw (insn
);
1090 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1091 lower32
= 0; upper32
= 0;
1095 /* Reset X_add_number, we've extracted it as upper32/lower32.
1096 Otherwise fixup_segment will complain about not being able to
1097 write an 8 byte number in a 4 byte field. */
1098 the_insn
.exp
.X_add_number
= 0;
1100 /* Only need hh22 if `or' insn can't handle constant. */
1101 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1104 /* Does bottom part (after sethi) have bits? */
1105 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1106 /* No hh22, but does upper32 still have bits we can't set
1108 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1111 /* If the lower half is all zero, we build the upper half directly
1112 into the dst reg. */
1114 /* Need lower half if number is zero or 0xffffffff00000000. */
1115 || (! need_hh22_p
&& ! need_hm10_p
))
1117 /* No need for sethi if `or' insn can handle constant. */
1118 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1119 /* Note that we can't use a negative constant in the `or'
1120 insn unless the upper 32 bits are all ones. */
1121 || (lower32
< 0 && upper32
!= -1)
1122 || (lower32
>= 0 && upper32
== -1))
1125 if (need_hi22_p
&& upper32
== -1)
1128 /* Does bottom part (after sethi) have bits? */
1129 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1131 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1132 /* Need `or' if we didn't set anything else. */
1133 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1137 /* Output directly to dst reg if lower 32 bits are all zero. */
1138 upper_dstreg
= dstreg
;
1141 if (!upper_dstreg
&& dstreg
)
1142 as_warn (_("setx: illegal temporary register g0"));
1146 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1147 | ((upper32
>> 10) & 0x3fffff));
1148 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1149 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1150 output_insn (insn
, &the_insn
);
1155 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1156 | (((need_xor10_p
? ~lower32
: lower32
)
1157 >> 10) & 0x3fffff));
1158 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1159 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1160 output_insn (insn
, &the_insn
);
1165 the_insn
.opcode
= (OR_INSN
1166 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1169 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1170 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1171 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1172 output_insn (insn
, &the_insn
);
1177 /* FIXME: One nice optimization to do here is to OR the low part
1178 with the highpart if hi22 isn't needed and the low part is
1180 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1183 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1184 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1185 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1186 output_insn (insn
, &the_insn
);
1189 /* If we needed to build the upper part, shift it into place. */
1190 if (need_hh22_p
|| need_hm10_p
)
1192 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1194 the_insn
.reloc
= BFD_RELOC_NONE
;
1195 output_insn (insn
, &the_insn
);
1198 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1201 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1202 | 0x1c00 | (lower32
& 0x3ff));
1203 the_insn
.reloc
= BFD_RELOC_NONE
;
1204 output_insn (insn
, &the_insn
);
1207 /* If we needed to build both upper and lower parts, OR them together. */
1208 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1210 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1212 the_insn
.reloc
= BFD_RELOC_NONE
;
1213 output_insn (insn
, &the_insn
);
1217 /* Main entry point to assemble one instruction. */
1223 const struct sparc_opcode
*insn
;
1227 special_case
= sparc_ip (str
, &insn
);
1229 /* We warn about attempts to put a floating point branch in a delay slot,
1230 unless the delay slot has been annulled. */
1232 && last_insn
!= NULL
1233 && (insn
->flags
& F_FBR
) != 0
1234 && (last_insn
->flags
& F_DELAYED
) != 0
1235 /* ??? This test isn't completely accurate. We assume anything with
1236 F_{UNBR,CONDBR,FBR} set is annullable. */
1237 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1238 || (last_opcode
& ANNUL
) == 0))
1239 as_warn (_("FP branch in delay slot"));
1241 /* SPARC before v9 requires a nop instruction between a floating
1242 point instruction and a floating point branch. We insert one
1243 automatically, with a warning. */
1244 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1246 && last_insn
!= NULL
1247 && (insn
->flags
& F_FBR
) != 0
1248 && (last_insn
->flags
& F_FLOAT
) != 0)
1250 struct sparc_it nop_insn
;
1252 nop_insn
.opcode
= NOP_INSN
;
1253 nop_insn
.reloc
= BFD_RELOC_NONE
;
1254 output_insn (insn
, &nop_insn
);
1255 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1258 switch (special_case
)
1260 case SPECIAL_CASE_NONE
:
1262 output_insn (insn
, &the_insn
);
1265 case SPECIAL_CASE_SETSW
:
1266 synthetize_setsw (insn
);
1269 case SPECIAL_CASE_SET
:
1270 synthetize_setuw (insn
);
1273 case SPECIAL_CASE_SETX
:
1274 synthetize_setx (insn
);
1277 case SPECIAL_CASE_FDIV
:
1279 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1281 output_insn (insn
, &the_insn
);
1283 /* According to information leaked from Sun, the "fdiv" instructions
1284 on early SPARC machines would produce incorrect results sometimes.
1285 The workaround is to add an fmovs of the destination register to
1286 itself just after the instruction. This was true on machines
1287 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1288 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1289 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1290 output_insn (insn
, &the_insn
);
1295 as_fatal (_("failed special case insn sanity check"));
1299 /* Subroutine of md_assemble to do the actual parsing. */
1302 sparc_ip (str
, pinsn
)
1304 const struct sparc_opcode
**pinsn
;
1306 char *error_message
= "";
1310 const struct sparc_opcode
*insn
;
1312 unsigned long opcode
;
1313 unsigned int mask
= 0;
1317 int special_case
= SPECIAL_CASE_NONE
;
1320 if (islower ((unsigned char) *s
))
1324 while (islower ((unsigned char) *s
) || isdigit ((unsigned char) *s
));
1342 as_fatal (_("Unknown opcode: `%s'"), str
);
1344 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1348 as_bad (_("Unknown opcode: `%s'"), str
);
1349 return special_case
;
1359 opcode
= insn
->match
;
1360 memset (&the_insn
, '\0', sizeof (the_insn
));
1361 the_insn
.reloc
= BFD_RELOC_NONE
;
1365 * Build the opcode, checking as we go to make
1366 * sure that the operands match
1368 for (args
= insn
->args
;; ++args
)
1376 /* Parse a series of masks. */
1383 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1386 error_message
= _(": invalid membar mask name");
1390 while (*s
== ' ') { ++s
; continue; }
1391 if (*s
== '|' || *s
== '+')
1393 while (*s
== ' ') { ++s
; continue; }
1398 if (! parse_const_expr_arg (&s
, &kmask
))
1400 error_message
= _(": invalid membar mask expression");
1403 if (kmask
< 0 || kmask
> 127)
1405 error_message
= _(": invalid membar mask number");
1410 opcode
|= MEMBAR (kmask
);
1418 /* Parse a prefetch function. */
1421 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1423 error_message
= _(": invalid prefetch function name");
1429 if (! parse_const_expr_arg (&s
, &fcn
))
1431 error_message
= _(": invalid prefetch function expression");
1434 if (fcn
< 0 || fcn
> 31)
1436 error_message
= _(": invalid prefetch function number");
1446 /* Parse a sparc64 privileged register. */
1449 struct priv_reg_entry
*p
= priv_reg_table
;
1450 unsigned int len
= 9999999; /* init to make gcc happy */
1453 while (p
->name
[0] > s
[0])
1455 while (p
->name
[0] == s
[0])
1457 len
= strlen (p
->name
);
1458 if (strncmp (p
->name
, s
, len
) == 0)
1462 if (p
->name
[0] != s
[0])
1464 error_message
= _(": unrecognizable privileged register");
1468 opcode
|= (p
->regnum
<< 14);
1470 opcode
|= (p
->regnum
<< 25);
1476 error_message
= _(": unrecognizable privileged register");
1482 /* Parse a v9a ancillary state register. */
1485 struct priv_reg_entry
*p
= v9a_asr_table
;
1486 unsigned int len
= 9999999; /* init to make gcc happy */
1489 while (p
->name
[0] > s
[0])
1491 while (p
->name
[0] == s
[0])
1493 len
= strlen (p
->name
);
1494 if (strncmp (p
->name
, s
, len
) == 0)
1498 if (p
->name
[0] != s
[0])
1500 error_message
= _(": unrecognizable v9a ancillary state register");
1503 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1505 error_message
= _(": rd on write only ancillary state register");
1509 opcode
|= (p
->regnum
<< 14);
1511 opcode
|= (p
->regnum
<< 25);
1517 error_message
= _(": unrecognizable v9a ancillary state register");
1523 if (strncmp (s
, "%asr", 4) == 0)
1527 if (isdigit ((unsigned char) *s
))
1531 while (isdigit ((unsigned char) *s
))
1533 num
= num
* 10 + *s
- '0';
1537 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1539 if (num
< 16 || 31 < num
)
1541 error_message
= _(": asr number must be between 16 and 31");
1547 if (num
< 0 || 31 < num
)
1549 error_message
= _(": asr number must be between 0 and 31");
1554 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1559 error_message
= _(": expecting %asrN");
1566 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1570 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1574 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1575 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1576 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1578 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1579 /* These fields are unsigned, but for upward compatibility,
1580 allow negative values as well. */
1584 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1585 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1586 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1588 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1589 /* These fields are unsigned, but for upward compatibility,
1590 allow negative values as well. */
1594 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1599 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1604 if (*s
== 'p' && s
[1] == 'n')
1612 if (*s
== 'p' && s
[1] == 't')
1624 if (strncmp (s
, "%icc", 4) == 0)
1636 if (strncmp (s
, "%xcc", 4) == 0)
1648 if (strncmp (s
, "%fcc0", 5) == 0)
1660 if (strncmp (s
, "%fcc1", 5) == 0)
1672 if (strncmp (s
, "%fcc2", 5) == 0)
1684 if (strncmp (s
, "%fcc3", 5) == 0)
1692 if (strncmp (s
, "%pc", 3) == 0)
1700 if (strncmp (s
, "%tick", 5) == 0)
1707 case '\0': /* end of args */
1726 case '[': /* these must match exactly */
1734 case '#': /* must be at least one digit */
1735 if (isdigit ((unsigned char) *s
++))
1737 while (isdigit ((unsigned char) *s
))
1745 case 'C': /* coprocessor state register */
1746 if (strncmp (s
, "%csr", 4) == 0)
1753 case 'b': /* next operand is a coprocessor register */
1756 if (*s
++ == '%' && *s
++ == 'c' && isdigit ((unsigned char) *s
))
1759 if (isdigit ((unsigned char) *s
))
1761 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1775 opcode
|= mask
<< 14;
1783 opcode
|= mask
<< 25;
1789 case 'r': /* next operand must be a register */
1799 case 'f': /* frame pointer */
1807 case 'g': /* global register */
1816 case 'i': /* in register */
1820 mask
= c
- '0' + 24;
1825 case 'l': /* local register */
1829 mask
= (c
- '0' + 16);
1834 case 'o': /* out register */
1838 mask
= (c
- '0' + 8);
1843 case 's': /* stack pointer */
1851 case 'r': /* any register */
1852 if (!isdigit ((unsigned char) (c
= *s
++)))
1867 if (isdigit ((unsigned char) *s
))
1869 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1885 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
1886 && no_undeclared_regs
&& ! globals
[mask
])
1887 as_bad (_("detected global register use not "
1888 "covered by .register pseudo-op"));
1890 /* Got the register, now figure out where
1891 it goes in the opcode. */
1895 opcode
|= mask
<< 14;
1903 opcode
|= mask
<< 25;
1907 opcode
|= (mask
<< 25) | (mask
<< 14);
1911 opcode
|= (mask
<< 25) | (mask
<< 0);
1917 case 'e': /* next operand is a floating point register */
1932 && ((format
= *s
) == 'f')
1933 && isdigit ((unsigned char) *++s
))
1935 for (mask
= 0; isdigit ((unsigned char) *s
); ++s
)
1937 mask
= 10 * mask
+ (*s
- '0');
1938 } /* read the number */
1946 } /* register must be even numbered */
1954 } /* register must be multiple of 4 */
1958 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1959 error_message
= _(": There are only 64 f registers; [0-63]");
1961 error_message
= _(": There are only 32 f registers; [0-31]");
1964 else if (mask
>= 32)
1966 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1969 mask
-= 31; /* wrap high bit */
1973 error_message
= _(": There are only 32 f registers; [0-31]");
1981 } /* if not an 'f' register. */
1988 opcode
|= RS1 (mask
);
1995 opcode
|= RS2 (mask
);
2001 opcode
|= RD (mask
);
2010 if (strncmp (s
, "%fsr", 4) == 0)
2017 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2018 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2021 case 'l': /* 22 bit PC relative immediate */
2022 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2026 case 'L': /* 30 bit immediate */
2027 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2032 case 'n': /* 22 bit immediate */
2033 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2036 case 'i': /* 13 bit immediate */
2037 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2047 char *op_arg
= NULL
;
2049 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2051 /* Check for %hi, etc. */
2054 static const struct ops
{
2055 /* The name as it appears in assembler. */
2057 /* strlen (name), precomputed for speed */
2059 /* The reloc this pseudo-op translates to. */
2061 /* Non-zero if for v9 only. */
2063 /* Non-zero if can be used in pc-relative contexts. */
2064 int pcrel_p
;/*FIXME:wip*/
2066 /* hix/lox must appear before hi/lo so %hix won't be
2067 mistaken for %hi. */
2068 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
2069 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
2070 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
2071 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
2072 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
2073 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
2074 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
2075 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
2076 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
2077 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
2078 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
2079 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
2082 const struct ops
*o
;
2084 for (o
= ops
; o
->name
; o
++)
2085 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
2087 if (o
->name
== NULL
)
2090 if (s
[o
->len
+ 1] != '(')
2092 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o
->name
);
2093 return special_case
;
2097 the_insn
.reloc
= o
->reloc
;
2102 /* Note that if the get_expression() fails, we will still
2103 have created U entries in the symbol table for the
2104 'symbols' in the input string. Try not to create U
2105 symbols for registers, etc. */
2107 /* This stuff checks to see if the expression ends in
2108 +%reg. If it does, it removes the register from
2109 the expression, and re-sets 's' to point to the
2116 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2119 else if (*s1
== ')')
2128 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2129 return special_case
;
2133 (void) get_expression (s
);
2136 if (*s
== ',' || *s
== ']' || !*s
)
2138 if (*s
!= '+' && *s
!= '-')
2140 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2141 return special_case
;
2145 op_exp
= the_insn
.exp
;
2146 memset (&the_insn
.exp
, 0, sizeof(the_insn
.exp
));
2149 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
2151 if (s1
!= s
&& isdigit ((unsigned char) s1
[-1]))
2153 if (s1
[-2] == '%' && s1
[-3] == '+')
2155 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2162 (void) get_expression (s
);
2174 (void) get_expression (s
);
2182 the_insn
.exp2
= the_insn
.exp
;
2183 the_insn
.exp
= op_exp
;
2184 if (the_insn
.exp2
.X_op
== O_absent
)
2185 the_insn
.exp2
.X_op
= O_illegal
;
2186 else if (the_insn
.exp
.X_op
== O_absent
)
2188 the_insn
.exp
= the_insn
.exp2
;
2189 the_insn
.exp2
.X_op
= O_illegal
;
2191 else if (the_insn
.exp
.X_op
== O_constant
)
2193 valueT val
= the_insn
.exp
.X_add_number
;
2194 switch (the_insn
.reloc
)
2199 case BFD_RELOC_SPARC_HH22
:
2200 val
= BSR (val
, 32);
2201 /* intentional fallthrough */
2203 case BFD_RELOC_SPARC_LM22
:
2204 case BFD_RELOC_HI22
:
2205 val
= (val
>> 10) & 0x3fffff;
2208 case BFD_RELOC_SPARC_HM10
:
2209 val
= BSR (val
, 32);
2210 /* intentional fallthrough */
2212 case BFD_RELOC_LO10
:
2216 case BFD_RELOC_SPARC_H44
:
2221 case BFD_RELOC_SPARC_M44
:
2226 case BFD_RELOC_SPARC_L44
:
2230 case BFD_RELOC_SPARC_HIX22
:
2232 val
= (val
>> 10) & 0x3fffff;
2235 case BFD_RELOC_SPARC_LOX10
:
2236 val
= (val
& 0x3ff) | 0x1c00;
2239 the_insn
.exp
= the_insn
.exp2
;
2240 the_insn
.exp
.X_add_number
+= val
;
2241 the_insn
.exp2
.X_op
= O_illegal
;
2242 the_insn
.reloc
= old_reloc
;
2244 else if (the_insn
.exp2
.X_op
!= O_constant
)
2246 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2247 return special_case
;
2251 if (old_reloc
!= BFD_RELOC_SPARC13
2252 || the_insn
.reloc
!= BFD_RELOC_LO10
2253 || sparc_arch_size
!= 64
2256 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2257 return special_case
;
2259 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2263 /* Check for constants that don't require emitting a reloc. */
2264 if (the_insn
.exp
.X_op
== O_constant
2265 && the_insn
.exp
.X_add_symbol
== 0
2266 && the_insn
.exp
.X_op_symbol
== 0)
2268 /* For pc-relative call instructions, we reject
2269 constants to get better code. */
2271 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2272 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2274 error_message
= _(": PC-relative operand can't be a constant");
2278 /* Constants that won't fit are checked in md_apply_fix3
2279 and bfd_install_relocation.
2280 ??? It would be preferable to install the constants
2281 into the insn here and save having to create a fixS
2282 for each one. There already exists code to handle
2283 all the various cases (e.g. in md_apply_fix3 and
2284 bfd_install_relocation) so duplicating all that code
2285 here isn't right. */
2305 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2307 error_message
= _(": invalid ASI name");
2313 if (! parse_const_expr_arg (&s
, &asi
))
2315 error_message
= _(": invalid ASI expression");
2318 if (asi
< 0 || asi
> 255)
2320 error_message
= _(": invalid ASI number");
2324 opcode
|= ASI (asi
);
2326 } /* alternate space */
2329 if (strncmp (s
, "%psr", 4) == 0)
2336 case 'q': /* floating point queue */
2337 if (strncmp (s
, "%fq", 3) == 0)
2344 case 'Q': /* coprocessor queue */
2345 if (strncmp (s
, "%cq", 3) == 0)
2353 if (strcmp (str
, "set") == 0
2354 || strcmp (str
, "setuw") == 0)
2356 special_case
= SPECIAL_CASE_SET
;
2359 else if (strcmp (str
, "setsw") == 0)
2361 special_case
= SPECIAL_CASE_SETSW
;
2364 else if (strcmp (str
, "setx") == 0)
2366 special_case
= SPECIAL_CASE_SETX
;
2369 else if (strncmp (str
, "fdiv", 4) == 0)
2371 special_case
= SPECIAL_CASE_FDIV
;
2377 if (strncmp (s
, "%asi", 4) != 0)
2383 if (strncmp (s
, "%fprs", 5) != 0)
2389 if (strncmp (s
, "%ccr", 4) != 0)
2395 if (strncmp (s
, "%tbr", 4) != 0)
2401 if (strncmp (s
, "%wim", 4) != 0)
2408 char *push
= input_line_pointer
;
2411 input_line_pointer
= s
;
2413 if (e
.X_op
== O_constant
)
2415 int n
= e
.X_add_number
;
2416 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2417 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
2419 opcode
|= e
.X_add_number
<< 5;
2422 as_bad (_("non-immediate OPF operand, ignored"));
2423 s
= input_line_pointer
;
2424 input_line_pointer
= push
;
2429 if (strncmp (s
, "%y", 2) != 0)
2437 /* Parse a sparclet cpreg. */
2439 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2441 error_message
= _(": invalid cpreg name");
2444 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2449 as_fatal (_("failed sanity check."));
2450 } /* switch on arg code */
2452 /* Break out of for() loop. */
2454 } /* for each arg that we expect */
2459 /* Args don't match. */
2460 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
2461 && (insn
->name
== insn
[1].name
2462 || !strcmp (insn
->name
, insn
[1].name
)))
2470 as_bad (_("Illegal operands%s"), error_message
);
2471 return special_case
;
2476 /* We have a match. Now see if the architecture is ok. */
2477 int needed_arch_mask
= insn
->architecture
;
2481 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
2482 | (1 << SPARC_OPCODE_ARCH_V9A
));
2483 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2486 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
2488 /* Can we bump up the architecture? */
2489 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
2491 enum sparc_opcode_arch_val needed_architecture
=
2492 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2493 & needed_arch_mask
);
2495 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2497 && needed_architecture
> warn_after_architecture
)
2499 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
2500 sparc_opcode_archs
[current_architecture
].name
,
2501 sparc_opcode_archs
[needed_architecture
].name
,
2503 warn_after_architecture
= needed_architecture
;
2505 current_architecture
= needed_architecture
;
2508 /* ??? This seems to be a bit fragile. What if the next entry in
2509 the opcode table is the one we want and it is supported?
2510 It is possible to arrange the table today so that this can't
2511 happen but what about tomorrow? */
2514 int arch
,printed_one_p
= 0;
2516 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2518 /* Create a list of the architectures that support the insn. */
2519 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
2521 arch
= sparc_ffs (needed_arch_mask
);
2522 while ((1 << arch
) <= needed_arch_mask
)
2524 if ((1 << arch
) & needed_arch_mask
)
2528 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2535 as_bad (_("Architecture mismatch on \"%s\"."), str
);
2536 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
2538 sparc_opcode_archs
[max_architecture
].name
);
2539 return special_case
;
2544 } /* forever looking for a match */
2546 the_insn
.opcode
= opcode
;
2547 return special_case
;
2550 /* Parse an argument that can be expressed as a keyword.
2551 (eg: #StoreStore or %ccfr).
2552 The result is a boolean indicating success.
2553 If successful, INPUT_POINTER is updated. */
2556 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2557 int (*lookup_fn
) PARAMS ((const char *));
2558 char **input_pointerP
;
2564 p
= *input_pointerP
;
2565 for (q
= p
+ (*p
== '#' || *p
== '%');
2566 isalnum ((unsigned char) *q
) || *q
== '_';
2571 value
= (*lookup_fn
) (p
);
2576 *input_pointerP
= q
;
2580 /* Parse an argument that is a constant expression.
2581 The result is a boolean indicating success. */
2584 parse_const_expr_arg (input_pointerP
, valueP
)
2585 char **input_pointerP
;
2588 char *save
= input_line_pointer
;
2591 input_line_pointer
= *input_pointerP
;
2592 /* The next expression may be something other than a constant
2593 (say if we're not processing the right variant of the insn).
2594 Don't call expression unless we're sure it will succeed as it will
2595 signal an error (which we want to defer until later). */
2596 /* FIXME: It might be better to define md_operand and have it recognize
2597 things like %asi, etc. but continuing that route through to the end
2598 is a lot of work. */
2599 if (*input_line_pointer
== '%')
2601 input_line_pointer
= save
;
2605 *input_pointerP
= input_line_pointer
;
2606 input_line_pointer
= save
;
2607 if (exp
.X_op
!= O_constant
)
2609 *valueP
= exp
.X_add_number
;
2613 /* Subroutine of sparc_ip to parse an expression. */
2616 get_expression (str
)
2622 save_in
= input_line_pointer
;
2623 input_line_pointer
= str
;
2624 seg
= expression (&the_insn
.exp
);
2625 if (seg
!= absolute_section
2626 && seg
!= text_section
2627 && seg
!= data_section
2628 && seg
!= bss_section
2629 && seg
!= undefined_section
)
2631 the_insn
.error
= _("bad segment");
2632 expr_end
= input_line_pointer
;
2633 input_line_pointer
= save_in
;
2636 expr_end
= input_line_pointer
;
2637 input_line_pointer
= save_in
;
2641 /* Subroutine of md_assemble to output one insn. */
2644 output_insn (insn
, the_insn
)
2645 const struct sparc_opcode
*insn
;
2646 struct sparc_it
*the_insn
;
2648 char *toP
= frag_more (4);
2650 /* put out the opcode */
2651 if (INSN_BIG_ENDIAN
)
2652 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2654 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2656 /* put out the symbol-dependent stuff */
2657 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2659 fixS
*fixP
= fix_new_exp (frag_now
, /* which frag */
2660 (toP
- frag_now
->fr_literal
), /* where */
2665 /* Turn off overflow checking in fixup_segment. We'll do our
2666 own overflow checking in md_apply_fix3. This is necessary because
2667 the insn size is 4 and fixup_segment will signal an overflow for
2668 large 8 byte quantities. */
2669 fixP
->fx_no_overflow
= 1;
2670 if (the_insn
->reloc
== BFD_RELOC_SPARC_OLO10
)
2671 fixP
->tc_fix_data
= the_insn
->exp2
.X_add_number
;
2675 last_opcode
= the_insn
->opcode
;
2679 This is identical to the md_atof in m68k.c. I think this is right,
2682 Turn a string in input_line_pointer into a floating point constant of type
2683 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2684 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2687 /* Equal to MAX_PRECISION in atof-ieee.c */
2688 #define MAX_LITTLENUMS 6
2691 md_atof (type
, litP
, sizeP
)
2697 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2728 return _("Bad call to MD_ATOF()");
2731 t
= atof_ieee (input_line_pointer
, type
, words
);
2733 input_line_pointer
= t
;
2734 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2736 if (target_big_endian
)
2738 for (i
= 0; i
< prec
; i
++)
2740 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2741 litP
+= sizeof (LITTLENUM_TYPE
);
2746 for (i
= prec
- 1; i
>= 0; i
--)
2748 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2749 litP
+= sizeof (LITTLENUM_TYPE
);
2756 /* Write a value out to the object file, using the appropriate
2760 md_number_to_chars (buf
, val
, n
)
2765 if (target_big_endian
)
2766 number_to_chars_bigendian (buf
, val
, n
);
2767 else if (target_little_endian_data
2768 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
2769 /* Output debug words, which are not in allocated sections, as big endian */
2770 number_to_chars_bigendian (buf
, val
, n
);
2771 else if (target_little_endian_data
|| ! target_big_endian
)
2772 number_to_chars_littleendian (buf
, val
, n
);
2775 /* Apply a fixS to the frags, now that we know the value it ought to
2779 md_apply_fix3 (fixP
, value
, segment
)
2784 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2790 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2792 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2795 /* FIXME: SPARC ELF relocations don't use an addend in the data
2796 field itself. This whole approach should be somehow combined
2797 with the calls to bfd_install_relocation. Also, the value passed
2798 in by fixup_segment includes the value of a defined symbol. We
2799 don't want to include the value of an externally visible symbol. */
2800 if (fixP
->fx_addsy
!= NULL
)
2802 if (symbol_used_in_reloc_p (fixP
->fx_addsy
)
2803 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2804 || S_IS_WEAK (fixP
->fx_addsy
)
2805 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2806 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2807 && ((bfd_get_section_flags (stdoutput
,
2808 S_GET_SEGMENT (fixP
->fx_addsy
))
2809 & SEC_LINK_ONCE
) != 0
2810 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2812 sizeof ".gnu.linkonce" - 1) == 0)))
2813 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2814 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2815 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2816 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2821 /* This is a hack. There should be a better way to
2822 handle this. Probably in terms of howto fields, once
2823 we can look at these fixups in terms of howtos. */
2824 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2825 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2828 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2829 generate a reloc, then we just want to let the reloc addend set
2830 the value. We do not want to also stuff the addend into the
2831 object file. Including the addend in the object file works when
2832 doing a static link, because the linker will ignore the object
2833 file contents. However, the dynamic linker does not ignore the
2834 object file contents. */
2835 if (fixP
->fx_addsy
!= NULL
2836 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2839 /* When generating PIC code, we do not want an addend for a reloc
2840 against a local symbol. We adjust fx_addnumber to cancel out the
2841 value already included in val, and to also cancel out the
2842 adjustment which bfd_install_relocation will create. */
2844 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2845 && fixP
->fx_addsy
!= NULL
2846 && ! S_IS_COMMON (fixP
->fx_addsy
)
2847 && symbol_section_p (fixP
->fx_addsy
))
2848 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2850 /* When generating PIC code, we need to fiddle to get
2851 bfd_install_relocation to do the right thing for a PC relative
2852 reloc against a local symbol which we are going to keep. */
2854 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
2855 && fixP
->fx_addsy
!= NULL
2856 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2857 || S_IS_WEAK (fixP
->fx_addsy
))
2858 && S_IS_DEFINED (fixP
->fx_addsy
)
2859 && ! S_IS_COMMON (fixP
->fx_addsy
))
2862 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2866 /* If this is a data relocation, just output VAL. */
2868 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2870 md_number_to_chars (buf
, val
, 2);
2872 else if (fixP
->fx_r_type
== BFD_RELOC_32
2873 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
2875 md_number_to_chars (buf
, val
, 4);
2877 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2879 md_number_to_chars (buf
, val
, 8);
2881 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2882 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2889 /* It's a relocation against an instruction. */
2891 if (INSN_BIG_ENDIAN
)
2892 insn
= bfd_getb32 ((unsigned char *) buf
);
2894 insn
= bfd_getl32 ((unsigned char *) buf
);
2896 switch (fixP
->fx_r_type
)
2898 case BFD_RELOC_32_PCREL_S2
:
2900 /* FIXME: This increment-by-one deserves a comment of why it's
2902 if (! sparc_pic_code
2903 || fixP
->fx_addsy
== NULL
2904 || symbol_section_p (fixP
->fx_addsy
))
2906 insn
|= val
& 0x3fffffff;
2909 case BFD_RELOC_SPARC_11
:
2910 if (! in_signed_range (val
, 0x7ff))
2911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2912 _("relocation overflow"));
2913 insn
|= val
& 0x7ff;
2916 case BFD_RELOC_SPARC_10
:
2917 if (! in_signed_range (val
, 0x3ff))
2918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2919 _("relocation overflow"));
2920 insn
|= val
& 0x3ff;
2923 case BFD_RELOC_SPARC_7
:
2924 if (! in_bitfield_range (val
, 0x7f))
2925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2926 _("relocation overflow"));
2930 case BFD_RELOC_SPARC_6
:
2931 if (! in_bitfield_range (val
, 0x3f))
2932 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2933 _("relocation overflow"));
2937 case BFD_RELOC_SPARC_5
:
2938 if (! in_bitfield_range (val
, 0x1f))
2939 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2940 _("relocation overflow"));
2944 case BFD_RELOC_SPARC_WDISP16
:
2945 /* FIXME: simplify */
2946 if (((val
> 0) && (val
& ~0x3fffc))
2947 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2949 _("relocation overflow"));
2950 /* FIXME: The +1 deserves a comment. */
2951 val
= (val
>> 2) + 1;
2952 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2955 case BFD_RELOC_SPARC_WDISP19
:
2956 /* FIXME: simplify */
2957 if (((val
> 0) && (val
& ~0x1ffffc))
2958 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2959 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2960 _("relocation overflow"));
2961 /* FIXME: The +1 deserves a comment. */
2962 val
= (val
>> 2) + 1;
2963 insn
|= val
& 0x7ffff;
2966 case BFD_RELOC_SPARC_HH22
:
2967 val
= BSR (val
, 32);
2968 /* intentional fallthrough */
2970 case BFD_RELOC_SPARC_LM22
:
2971 case BFD_RELOC_HI22
:
2972 if (!fixP
->fx_addsy
)
2974 insn
|= (val
>> 10) & 0x3fffff;
2978 /* FIXME: Need comment explaining why we do this. */
2983 case BFD_RELOC_SPARC22
:
2984 if (val
& ~0x003fffff)
2985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2986 _("relocation overflow"));
2987 insn
|= (val
& 0x3fffff);
2990 case BFD_RELOC_SPARC_HM10
:
2991 val
= BSR (val
, 32);
2992 /* intentional fallthrough */
2994 case BFD_RELOC_LO10
:
2995 if (!fixP
->fx_addsy
)
2997 insn
|= val
& 0x3ff;
3001 /* FIXME: Need comment explaining why we do this. */
3006 case BFD_RELOC_SPARC_OLO10
:
3008 val
+= fixP
->tc_fix_data
;
3009 /* intentional fallthrough */
3011 case BFD_RELOC_SPARC13
:
3012 if (! in_signed_range (val
, 0x1fff))
3013 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3014 _("relocation overflow"));
3015 insn
|= val
& 0x1fff;
3018 case BFD_RELOC_SPARC_WDISP22
:
3019 val
= (val
>> 2) + 1;
3021 case BFD_RELOC_SPARC_BASE22
:
3022 insn
|= val
& 0x3fffff;
3025 case BFD_RELOC_SPARC_H44
:
3026 if (!fixP
->fx_addsy
)
3030 insn
|= tval
& 0x3fffff;
3034 case BFD_RELOC_SPARC_M44
:
3035 if (!fixP
->fx_addsy
)
3036 insn
|= (val
>> 12) & 0x3ff;
3039 case BFD_RELOC_SPARC_L44
:
3040 if (!fixP
->fx_addsy
)
3041 insn
|= val
& 0xfff;
3044 case BFD_RELOC_SPARC_HIX22
:
3045 if (!fixP
->fx_addsy
)
3047 val
^= ~ (offsetT
) 0;
3048 insn
|= (val
>> 10) & 0x3fffff;
3052 case BFD_RELOC_SPARC_LOX10
:
3053 if (!fixP
->fx_addsy
)
3054 insn
|= 0x1c00 | (val
& 0x3ff);
3057 case BFD_RELOC_NONE
:
3059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3060 _("bad or unhandled relocation type: 0x%02x"),
3065 if (INSN_BIG_ENDIAN
)
3066 bfd_putb32 (insn
, (unsigned char *) buf
);
3068 bfd_putl32 (insn
, (unsigned char *) buf
);
3071 /* Are we finished with this relocation now? */
3072 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3078 /* Translate internal representation of relocation info to BFD target
3081 tc_gen_reloc (section
, fixp
)
3085 static arelent
*relocs
[3];
3087 bfd_reloc_code_real_type code
;
3089 relocs
[0] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3092 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3093 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3094 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3096 switch (fixp
->fx_r_type
)
3100 case BFD_RELOC_HI22
:
3101 case BFD_RELOC_LO10
:
3102 case BFD_RELOC_32_PCREL_S2
:
3103 case BFD_RELOC_SPARC13
:
3104 case BFD_RELOC_SPARC22
:
3105 case BFD_RELOC_SPARC_BASE13
:
3106 case BFD_RELOC_SPARC_WDISP16
:
3107 case BFD_RELOC_SPARC_WDISP19
:
3108 case BFD_RELOC_SPARC_WDISP22
:
3110 case BFD_RELOC_SPARC_5
:
3111 case BFD_RELOC_SPARC_6
:
3112 case BFD_RELOC_SPARC_7
:
3113 case BFD_RELOC_SPARC_10
:
3114 case BFD_RELOC_SPARC_11
:
3115 case BFD_RELOC_SPARC_HH22
:
3116 case BFD_RELOC_SPARC_HM10
:
3117 case BFD_RELOC_SPARC_LM22
:
3118 case BFD_RELOC_SPARC_PC_HH22
:
3119 case BFD_RELOC_SPARC_PC_HM10
:
3120 case BFD_RELOC_SPARC_PC_LM22
:
3121 case BFD_RELOC_SPARC_H44
:
3122 case BFD_RELOC_SPARC_M44
:
3123 case BFD_RELOC_SPARC_L44
:
3124 case BFD_RELOC_SPARC_HIX22
:
3125 case BFD_RELOC_SPARC_LOX10
:
3126 case BFD_RELOC_SPARC_REV32
:
3127 case BFD_RELOC_SPARC_OLO10
:
3128 case BFD_RELOC_VTABLE_ENTRY
:
3129 case BFD_RELOC_VTABLE_INHERIT
:
3130 code
= fixp
->fx_r_type
;
3137 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3138 /* If we are generating PIC code, we need to generate a different
3142 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3144 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3151 case BFD_RELOC_32_PCREL_S2
:
3152 if (! S_IS_DEFINED (fixp
->fx_addsy
)
3153 || S_IS_COMMON (fixp
->fx_addsy
)
3154 || S_IS_EXTERNAL (fixp
->fx_addsy
)
3155 || S_IS_WEAK (fixp
->fx_addsy
))
3156 code
= BFD_RELOC_SPARC_WPLT30
;
3158 case BFD_RELOC_HI22
:
3159 if (fixp
->fx_addsy
!= NULL
3160 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3161 code
= BFD_RELOC_SPARC_PC22
;
3163 code
= BFD_RELOC_SPARC_GOT22
;
3165 case BFD_RELOC_LO10
:
3166 if (fixp
->fx_addsy
!= NULL
3167 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3168 code
= BFD_RELOC_SPARC_PC10
;
3170 code
= BFD_RELOC_SPARC_GOT10
;
3172 case BFD_RELOC_SPARC13
:
3173 code
= BFD_RELOC_SPARC_GOT13
;
3179 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3181 if (code
== BFD_RELOC_SPARC_OLO10
)
3182 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3184 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3185 if (reloc
->howto
== 0)
3187 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3188 _("internal error: can't export reloc type %d (`%s')"),
3189 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3195 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3198 if (reloc
->howto
->pc_relative
== 0
3199 || code
== BFD_RELOC_SPARC_PC10
3200 || code
== BFD_RELOC_SPARC_PC22
)
3201 reloc
->addend
= fixp
->fx_addnumber
;
3202 else if (sparc_pic_code
3203 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3204 && fixp
->fx_addsy
!= NULL
3205 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
3206 || S_IS_WEAK (fixp
->fx_addsy
))
3207 && S_IS_DEFINED (fixp
->fx_addsy
)
3208 && ! S_IS_COMMON (fixp
->fx_addsy
))
3209 reloc
->addend
= fixp
->fx_addnumber
;
3211 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
3213 #else /* elf or coff */
3215 if (reloc
->howto
->pc_relative
== 0
3216 || code
== BFD_RELOC_SPARC_PC10
3217 || code
== BFD_RELOC_SPARC_PC22
)
3218 reloc
->addend
= fixp
->fx_addnumber
;
3219 else if (symbol_section_p (fixp
->fx_addsy
))
3220 reloc
->addend
= (section
->vma
3221 + fixp
->fx_addnumber
3222 + md_pcrel_from (fixp
));
3224 reloc
->addend
= fixp
->fx_offset
;
3227 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
3228 on the same location. */
3229 if (code
== BFD_RELOC_SPARC_OLO10
)
3231 relocs
[1] = reloc
= (arelent
*) xmalloc (sizeof (arelent
));
3234 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
3235 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (section_symbol (absolute_section
));
3236 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3237 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
3238 reloc
->addend
= fixp
->tc_fix_data
;
3244 /* We have no need to default values of symbols. */
3248 md_undefined_symbol (name
)
3252 } /* md_undefined_symbol() */
3254 /* Round up a section size to the appropriate boundary. */
3256 md_section_align (segment
, size
)
3261 /* This is not right for ELF; a.out wants it, and COFF will force
3262 the alignment anyways. */
3263 valueT align
= ((valueT
) 1
3264 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
3266 /* turn alignment value into a mask */
3268 newsize
= (size
+ align
) & ~align
;
3275 /* Exactly what point is a PC-relative offset relative TO?
3276 On the sparc, they're relative to the address of the offset, plus
3277 its size. This gets us to the following instruction.
3278 (??? Is this right? FIXME-SOON) */
3280 md_pcrel_from (fixP
)
3285 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3286 if (! sparc_pic_code
3287 || fixP
->fx_addsy
== NULL
3288 || symbol_section_p (fixP
->fx_addsy
))
3289 ret
+= fixP
->fx_size
;
3293 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
3305 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
3308 return (value
== 1) ? shift
: -1;
3312 * sort of like s_lcomm
3316 static int max_alignment
= 15;
3331 name
= input_line_pointer
;
3332 c
= get_symbol_end ();
3333 p
= input_line_pointer
;
3337 if (*input_line_pointer
!= ',')
3339 as_bad (_("Expected comma after name"));
3340 ignore_rest_of_line ();
3344 ++input_line_pointer
;
3346 if ((size
= get_absolute_expression ()) < 0)
3348 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
3349 ignore_rest_of_line ();
3354 symbolP
= symbol_find_or_make (name
);
3357 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
3358 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
3360 as_bad (_("bad .reserve segment -- expected BSS segment"));
3364 if (input_line_pointer
[2] == '.')
3365 input_line_pointer
+= 7;
3367 input_line_pointer
+= 6;
3370 if (*input_line_pointer
== ',')
3372 ++input_line_pointer
;
3375 if (*input_line_pointer
== '\n')
3377 as_bad (_("missing alignment"));
3378 ignore_rest_of_line ();
3382 align
= (int) get_absolute_expression ();
3385 if (align
> max_alignment
)
3387 align
= max_alignment
;
3388 as_warn (_("alignment too large; assuming %d"), align
);
3394 as_bad (_("negative alignment"));
3395 ignore_rest_of_line ();
3401 temp
= log2 (align
);
3404 as_bad (_("alignment not a power of 2"));
3405 ignore_rest_of_line ();
3412 record_alignment (bss_section
, align
);
3417 if (!S_IS_DEFINED (symbolP
)
3419 && S_GET_OTHER (symbolP
) == 0
3420 && S_GET_DESC (symbolP
) == 0
3427 segT current_seg
= now_seg
;
3428 subsegT current_subseg
= now_subseg
;
3430 subseg_set (bss_section
, 1); /* switch to bss */
3433 frag_align (align
, 0, 0); /* do alignment */
3435 /* detach from old frag */
3436 if (S_GET_SEGMENT(symbolP
) == bss_section
)
3437 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
3439 symbol_set_frag (symbolP
, frag_now
);
3440 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
3441 (offsetT
) size
, (char *)0);
3444 S_SET_SEGMENT (symbolP
, bss_section
);
3446 subseg_set (current_seg
, current_subseg
);
3449 S_SET_SIZE (symbolP
, size
);
3455 as_warn("Ignoring attempt to re-define symbol %s",
3456 S_GET_NAME (symbolP
));
3457 } /* if not redefining */
3459 demand_empty_rest_of_line ();
3472 name
= input_line_pointer
;
3473 c
= get_symbol_end ();
3474 /* just after name is now '\0' */
3475 p
= input_line_pointer
;
3478 if (*input_line_pointer
!= ',')
3480 as_bad (_("Expected comma after symbol-name"));
3481 ignore_rest_of_line ();
3484 input_line_pointer
++; /* skip ',' */
3485 if ((temp
= get_absolute_expression ()) < 0)
3487 as_bad (_(".COMMon length (%d.) <0! Ignored."), temp
);
3488 ignore_rest_of_line ();
3493 symbolP
= symbol_find_or_make (name
);
3495 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3497 as_bad (_("Ignoring attempt to re-define symbol"));
3498 ignore_rest_of_line ();
3501 if (S_GET_VALUE (symbolP
) != 0)
3503 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
3505 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
3506 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3512 S_SET_VALUE (symbolP
, (valueT
) size
);
3513 S_SET_EXTERNAL (symbolP
);
3516 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
3517 if (*input_line_pointer
!= ',')
3519 as_bad (_("Expected comma after common length"));
3520 ignore_rest_of_line ();
3523 input_line_pointer
++;
3525 if (*input_line_pointer
!= '"')
3527 temp
= get_absolute_expression ();
3530 if (temp
> max_alignment
)
3532 temp
= max_alignment
;
3533 as_warn (_("alignment too large; assuming %d"), temp
);
3539 as_bad (_("negative alignment"));
3540 ignore_rest_of_line ();
3545 if (symbol_get_obj (symbolP
)->local
)
3553 old_subsec
= now_subseg
;
3558 align
= log2 (temp
);
3562 as_bad (_("alignment not a power of 2"));
3563 ignore_rest_of_line ();
3567 record_alignment (bss_section
, align
);
3568 subseg_set (bss_section
, 0);
3570 frag_align (align
, 0, 0);
3571 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3572 symbol_get_frag (symbolP
)->fr_symbol
= 0;
3573 symbol_set_frag (symbolP
, frag_now
);
3574 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3575 (offsetT
) size
, (char *) 0);
3577 S_SET_SEGMENT (symbolP
, bss_section
);
3578 S_CLEAR_EXTERNAL (symbolP
);
3579 S_SET_SIZE (symbolP
, size
);
3580 subseg_set (old_sec
, old_subsec
);
3583 #endif /* OBJ_ELF */
3586 S_SET_VALUE (symbolP
, (valueT
) size
);
3588 S_SET_ALIGN (symbolP
, temp
);
3589 S_SET_SIZE (symbolP
, size
);
3591 S_SET_EXTERNAL (symbolP
);
3592 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3597 input_line_pointer
++;
3598 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3599 if (*input_line_pointer
== '.')
3600 input_line_pointer
++;
3601 /* @@ Some say data, some say bss. */
3602 if (strncmp (input_line_pointer
, "bss\"", 4)
3603 && strncmp (input_line_pointer
, "data\"", 5))
3605 while (*--input_line_pointer
!= '"')
3607 input_line_pointer
--;
3608 goto bad_common_segment
;
3610 while (*input_line_pointer
++ != '"')
3612 goto allocate_common
;
3615 #ifdef BFD_ASSEMBLER
3616 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
3619 demand_empty_rest_of_line ();
3624 p
= input_line_pointer
;
3625 while (*p
&& *p
!= '\n')
3629 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
3631 input_line_pointer
= p
;
3632 ignore_rest_of_line ();
3637 /* Handle the .empty pseudo-op. This supresses the warnings about
3638 invalid delay slot usage. */
3644 /* The easy way to implement is to just forget about the last
3654 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3656 input_line_pointer
+= 6;
3660 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3662 input_line_pointer
+= 6;
3666 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3668 input_line_pointer
+= 7;
3672 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3674 input_line_pointer
+= 5;
3675 /* We only support 2 segments -- text and data -- for now, so
3676 things in the "bss segment" will have to go into data for now.
3677 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3678 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
3681 as_bad (_("Unknown segment type"));
3682 demand_empty_rest_of_line ();
3688 subseg_set (data_section
, 1);
3689 demand_empty_rest_of_line ();
3696 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3698 ++input_line_pointer
;
3700 ++input_line_pointer
;
3703 /* This static variable is set by s_uacons to tell sparc_cons_align
3704 that the expession does not need to be aligned. */
3706 static int sparc_no_align_cons
= 0;
3708 /* This handles the unaligned space allocation pseudo-ops, such as
3709 .uaword. .uaword is just like .word, but the value does not need
3716 /* Tell sparc_cons_align not to align this value. */
3717 sparc_no_align_cons
= 1;
3721 /* This handles the native word allocation pseudo-op .nword.
3722 For sparc_arch_size 32 it is equivalent to .word, for
3723 sparc_arch_size 64 it is equivalent to .xword. */
3729 cons (sparc_arch_size
== 32 ? 4 : 8);
3733 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
3737 .register %g[2367],{#scratch|symbolname|#ignore}
3747 const char *regname
;
3749 if (input_line_pointer
[0] != '%'
3750 || input_line_pointer
[1] != 'g'
3751 || ((input_line_pointer
[2] & ~1) != '2'
3752 && (input_line_pointer
[2] & ~1) != '6')
3753 || input_line_pointer
[3] != ',')
3754 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3755 reg
= input_line_pointer
[2] - '0';
3756 input_line_pointer
+= 4;
3758 if (*input_line_pointer
== '#')
3760 ++input_line_pointer
;
3761 regname
= input_line_pointer
;
3762 c
= get_symbol_end ();
3763 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
3764 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
3765 if (regname
[0] == 'i')
3772 regname
= input_line_pointer
;
3773 c
= get_symbol_end ();
3775 if (sparc_arch_size
== 64)
3779 if ((regname
&& globals
[reg
] != (symbolS
*)1
3780 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
3781 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*)1)))
3782 as_bad (_("redefinition of global register"));
3786 if (regname
== NULL
)
3787 globals
[reg
] = (symbolS
*)1;
3792 if (symbol_find (regname
))
3793 as_bad (_("Register symbol %s already defined."),
3796 globals
[reg
] = symbol_make (regname
);
3797 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
3799 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
3800 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
3801 flags
|= BSF_GLOBAL
;
3802 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
3803 S_SET_VALUE (globals
[reg
], (valueT
)reg
);
3804 S_SET_ALIGN (globals
[reg
], reg
);
3805 S_SET_SIZE (globals
[reg
], 0);
3806 /* Although we actually want undefined_section here,
3807 we have to use absolute_section, because otherwise
3808 generic as code will make it a COM section.
3809 We fix this up in sparc_adjust_symtab. */
3810 S_SET_SEGMENT (globals
[reg
], absolute_section
);
3811 S_SET_OTHER (globals
[reg
], 0);
3812 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
3813 ->internal_elf_sym
.st_info
=
3814 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
3815 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
3816 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
3821 *input_line_pointer
= c
;
3823 demand_empty_rest_of_line ();
3826 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
3827 symbols which need it. */
3830 sparc_adjust_symtab ()
3834 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
3836 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
3837 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
3840 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
3841 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
3844 S_SET_SEGMENT (sym
, undefined_section
);
3849 /* If the --enforce-aligned-data option is used, we require .word,
3850 et. al., to be aligned correctly. We do it by setting up an
3851 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3852 no unexpected alignment was introduced.
3854 The SunOS and Solaris native assemblers enforce aligned data by
3855 default. We don't want to do that, because gcc can deliberately
3856 generate misaligned data if the packed attribute is used. Instead,
3857 we permit misaligned data by default, and permit the user to set an
3858 option to check for it. */
3861 sparc_cons_align (nbytes
)
3867 /* Only do this if we are enforcing aligned data. */
3868 if (! enforce_aligned_data
)
3871 if (sparc_no_align_cons
)
3873 /* This is an unaligned pseudo-op. */
3874 sparc_no_align_cons
= 0;
3878 nalign
= log2 (nbytes
);
3882 assert (nalign
> 0);
3884 if (now_seg
== absolute_section
)
3886 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
3887 as_bad (_("misaligned data"));
3891 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
3892 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
3894 record_alignment (now_seg
, nalign
);
3897 /* This is where we do the unexpected alignment check.
3898 This is called from HANDLE_ALIGN in tc-sparc.h. */
3901 sparc_handle_align (fragp
)
3904 if (fragp
->fr_type
== rs_align_code
&& !fragp
->fr_subtype
3905 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
3906 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
3907 if (fragp
->fr_type
== rs_align_code
&& fragp
->fr_subtype
== 1024)
3909 int count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
3914 && !((long)(fragp
->fr_literal
+ fragp
->fr_fix
) & 3))
3916 unsigned *p
= (unsigned *)(fragp
->fr_literal
+ fragp
->fr_fix
);
3919 for (i
= 0; i
< count
; i
+= 4, p
++)
3920 if (INSN_BIG_ENDIAN
)
3921 number_to_chars_bigendian ((char *)p
, 0x01000000, 4); /* emit nops */
3923 number_to_chars_littleendian ((char *)p
, 0x10000000, 4);
3925 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
3927 char *waddr
= &fragp
->fr_literal
[fragp
->fr_fix
];
3928 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
3929 if (INSN_BIG_ENDIAN
)
3930 number_to_chars_bigendian (waddr
, wval
, 4);
3932 number_to_chars_littleendian (waddr
, wval
, 4);
3934 fragp
->fr_var
= count
;
3940 /* Some special processing for a Sparc ELF file. */
3943 sparc_elf_final_processing ()
3945 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3946 sort of BFD interface for this. */
3947 if (sparc_arch_size
== 64)
3949 switch (sparc_memory_model
)
3952 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
3955 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
3961 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
3962 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
3963 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
3964 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
3968 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
3969 reloc for a cons. We could use the definition there, except that
3970 we want to handle little endian relocs specially. */
3973 cons_fix_new_sparc (frag
, where
, nbytes
, exp
)
3976 unsigned int nbytes
;
3979 bfd_reloc_code_real_type r
;
3981 r
= (nbytes
== 1 ? BFD_RELOC_8
:
3982 (nbytes
== 2 ? BFD_RELOC_16
:
3983 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
3985 if (target_little_endian_data
&& nbytes
== 4
3986 && now_seg
->flags
& SEC_ALLOC
)
3987 r
= BFD_RELOC_SPARC_REV32
;
3988 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
3993 elf32_sparc_force_relocation (fixp
)
3996 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3997 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)