1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 This file is part of GAS, the GNU Assembler.
5 GAS is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 3, or (at your option)
10 GAS is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public
16 License along with GAS; see the file COPYING. If not, write
17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
18 Boston, MA 02110-1301, USA. */
21 #include "safe-ctype.h"
24 #include "opcode/sparc.h"
25 #include "dw2gencfi.h"
28 #include "elf/sparc.h"
29 #include "dwarf2dbg.h"
32 /* Some ancient Sun C compilers would not take such hex constants as
33 unsigned, and would end up sign-extending them to form an offsetT,
34 so use these constants instead. */
35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1)
36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15))
38 static int sparc_ip (char *, const struct sparc_opcode
**);
39 static int parse_keyword_arg (int (*) (const char *), char **, int *);
40 static int parse_const_expr_arg (char **, int *);
41 static int get_expression (char *);
43 /* Default architecture. */
44 /* ??? The default value should be V8, but sparclite support was added
45 by making it the default. GCC now passes -Asparclite, so maybe sometime in
46 the future we can set this to V8. */
48 #define DEFAULT_ARCH "sparclite"
50 static const char *default_arch
= DEFAULT_ARCH
;
52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
54 static int default_init_p
;
56 /* Current architecture. We don't bump up unless necessary. */
57 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
59 /* The maximum architecture level we can bump up to.
60 In a 32 bit environment, don't allow bumping up to v9 by default.
61 The native assembler works this way. The user is required to pass
62 an explicit argument before we'll create v9 object files. However, if
63 we don't see any v9 insns, a v8plus object file is not created. */
64 static enum sparc_opcode_arch_val max_architecture
;
66 /* Either 32 or 64, selects file format. */
67 static int sparc_arch_size
;
68 /* Initial (default) value, recorded separately in case a user option
69 changes the value before md_show_usage is called. */
70 static int default_arch_size
;
73 /* The currently selected v9 memory model. Currently only used for
75 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
78 /* Bitmask of instruction types seen so far, used to populate the
79 GNU attributes section with hwcap information. */
80 static bfd_uint64_t hwcap_seen
;
84 static bfd_uint64_t hwcap_allowed
;
86 static int architecture_requested
;
87 static int warn_on_bump
;
89 /* If warn_on_bump and the needed architecture is higher than this
90 architecture, issue a warning. */
91 static enum sparc_opcode_arch_val warn_after_architecture
;
93 /* Non-zero if the assembler should generate error if an undeclared
94 g[23] register has been used in -64. */
95 static int no_undeclared_regs
;
97 /* Non-zero if the assembler should generate a warning if an
98 unpredictable DCTI (delayed control transfer instruction) couple is
100 static int dcti_couples_detect
;
102 /* Non-zero if we should try to relax jumps and calls. */
103 static int sparc_relax
;
105 /* Non-zero if we are generating PIC code. */
108 /* Non-zero if we should give an error when misaligned data is seen. */
109 static int enforce_aligned_data
;
111 extern int target_big_endian
;
113 static int target_little_endian_data
;
115 /* Symbols for global registers on v9. */
116 static symbolS
*globals
[8];
118 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
119 int sparc_cie_data_alignment
;
121 /* V9 and 86x have big and little endian data, but instructions are always big
122 endian. The sparclet has bi-endian support but both data and insns have
123 the same endianness. Global `target_big_endian' is used for data.
124 The following macro is used for instructions. */
125 #ifndef INSN_BIG_ENDIAN
126 #define INSN_BIG_ENDIAN (target_big_endian \
127 || default_arch_type == sparc86x \
128 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
131 /* Handle of the OPCODE hash table. */
132 static struct hash_control
*op_hash
;
134 static void s_data1 (void);
135 static void s_seg (int);
136 static void s_proc (int);
137 static void s_reserve (int);
138 static void s_common (int);
139 static void s_empty (int);
140 static void s_uacons (int);
141 static void s_ncons (int);
143 static void s_register (int);
146 const pseudo_typeS md_pseudo_table
[] =
148 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0). */
149 {"common", s_common
, 0},
150 {"empty", s_empty
, 0},
151 {"global", s_globl
, 0},
153 {"nword", s_ncons
, 0},
154 {"optim", s_ignore
, 0},
156 {"reserve", s_reserve
, 0},
158 {"skip", s_space
, 0},
161 {"uahalf", s_uacons
, 2},
162 {"uaword", s_uacons
, 4},
163 {"uaxword", s_uacons
, 8},
165 /* These are specific to sparc/svr4. */
166 {"2byte", s_uacons
, 2},
167 {"4byte", s_uacons
, 4},
168 {"8byte", s_uacons
, 8},
169 {"register", s_register
, 0},
174 /* This array holds the chars that always start a comment. If the
175 pre-processor is disabled, these aren't very useful. */
176 const char comment_chars
[] = "!"; /* JF removed '|' from
179 /* This array holds the chars that only start a comment at the beginning of
180 a line. If the line seems to have the form '# 123 filename'
181 .line and .file directives will appear in the pre-processed output. */
182 /* Note that input_file.c hand checks for '#' at the beginning of the
183 first line of the input file. This is because the compiler outputs
184 #NO_APP at the beginning of its output. */
185 /* Also note that comments started like this one will always
186 work if '/' isn't otherwise defined. */
187 const char line_comment_chars
[] = "#";
189 const char line_separator_chars
[] = ";";
191 /* Chars that can be used to separate mant from exp in floating point
193 const char EXP_CHARS
[] = "eE";
195 /* Chars that mean this number is a floating point constant.
198 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
200 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
201 changed in read.c. Ideally it shouldn't have to know about it at all,
202 but nothing is ideal around here. */
204 #define isoctal(c) ((unsigned) ((c) - '0') < 8)
209 unsigned long opcode
;
210 struct nlist
*nlistp
;
214 bfd_reloc_code_real_type reloc
;
217 struct sparc_it the_insn
, set_insn
;
219 static void output_insn (const struct sparc_opcode
*, struct sparc_it
*);
221 /* Table of arguments to -A.
222 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
223 for this use. That table is for opcodes only. This table is for opcodes
226 enum sparc_arch_types
{v6
, v7
, v8
, leon
, sparclet
, sparclite
, sparc86x
, v8plus
,
227 v8plusa
, v9
, v9a
, v9b
, v9_64
};
229 /* Hardware capability sets, used to keep sparc_arch_table easy to
231 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
232 #define HWS_V9 HWS_V8 | HWCAP_POPC
233 #define HWS_VA HWS_V9 | HWCAP_VIS
234 #define HWS_VB HWS_VA | HWCAP_VIS2
235 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
236 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
237 #define HWS_VE HWS_VD \
238 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
239 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
240 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
241 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
242 #define HWS_VM HWS_VV
245 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
246 | HWCAP2_XMPMUL | HWCAP2_XMONT
248 static struct sparc_arch
{
250 const char *opcode_arch
;
251 enum sparc_arch_types arch_type
;
252 /* Default word size, as specified during configuration.
253 A value of zero means can't be used to specify default architecture. */
254 int default_arch_size
;
255 /* Allowable arg to -A? */
259 } sparc_arch_table
[] = {
260 { "v6", "v6", v6
, 0, 1, 0, 0 },
261 { "v7", "v7", v7
, 0, 1, 0, 0 },
262 { "v8", "v8", v8
, 32, 1, HWS_V8
, 0 },
263 { "v8a", "v8", v8
, 32, 1, HWS_V8
, 0 },
264 { "sparc", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
265 { "sparcvis", "v9a", v9
, 0, 1, HWS_VA
, 0 },
266 { "sparcvis2", "v9b", v9
, 0, 1, HWS_VB
, 0 },
267 { "sparcfmaf", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
, 0 },
268 { "sparcima", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_IMA
, 0 },
269 { "sparcvis3", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
, 0 },
270 { "sparcvis3r", "v9b", v9
, 0, 1, HWS_VB
|HWCAP_FMAF
|HWCAP_VIS3
|HWCAP_HPC
|HWCAP_FJFMAU
, 0 },
272 { "sparc4", "v9v", v9
, 0, 1, HWS_VV
, 0 },
273 { "sparc5", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
275 { "leon", "leon", leon
, 32, 1, HWS_V8
, 0 },
276 { "sparclet", "sparclet", sparclet
, 32, 1, HWS_V8
, 0 },
277 { "sparclite", "sparclite", sparclite
, 32, 1, HWS_V8
, 0 },
278 { "sparc86x", "sparclite", sparc86x
, 32, 1, HWS_V8
, 0 },
280 { "v8plus", "v9", v9
, 0, 1, HWCAP_V8PLUS
|HWS_V9
, 0 },
281 { "v8plusa", "v9a", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VA
, 0 },
282 { "v8plusb", "v9b", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VB
, 0 },
283 { "v8plusc", "v9c", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VC
, 0 },
284 { "v8plusd", "v9d", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VD
, 0 },
285 { "v8pluse", "v9e", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VE
, 0 },
286 { "v8plusv", "v9v", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VV
, 0 },
287 { "v8plusm", "v9m", v9
, 0, 1, HWCAP_V8PLUS
|HWS_VM
, 0 },
289 { "v9", "v9", v9
, 0, 1, HWS_V9
, 0 },
290 { "v9a", "v9a", v9
, 0, 1, HWS_VA
, 0 },
291 { "v9b", "v9b", v9
, 0, 1, HWS_VB
, 0 },
292 { "v9c", "v9c", v9
, 0, 1, HWS_VC
, 0 },
293 { "v9d", "v9d", v9
, 0, 1, HWS_VD
, 0 },
294 { "v9e", "v9e", v9
, 0, 1, HWS_VE
, 0 },
295 { "v9v", "v9v", v9
, 0, 1, HWS_VV
, 0 },
296 { "v9m", "v9m", v9
, 0, 1, HWS_VM
, HWS2_VM
},
298 /* This exists to allow configure.tgt to pass one
299 value to specify both the default machine and default word size. */
300 { "v9-64", "v9", v9
, 64, 0, HWS_V9
, 0 },
301 { NULL
, NULL
, v8
, 0, 0, 0, 0 }
304 /* Variant of default_arch */
305 static enum sparc_arch_types default_arch_type
;
307 static struct sparc_arch
*
308 lookup_arch (const char *name
)
310 struct sparc_arch
*sa
;
312 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
313 if (strcmp (sa
->name
, name
) == 0)
315 if (sa
->name
== NULL
)
320 /* Initialize the default opcode arch and word size from the default
321 architecture name. */
324 init_default_arch (void)
326 struct sparc_arch
*sa
= lookup_arch (default_arch
);
329 || sa
->default_arch_size
== 0)
330 as_fatal (_("Invalid default architecture, broken assembler."));
332 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
333 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
334 as_fatal (_("Bad opcode table, broken assembler."));
335 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
337 default_arch_type
= sa
->arch_type
;
340 /* Called by TARGET_FORMAT. */
343 sparc_target_format (void)
345 /* We don't get a chance to initialize anything before we're called,
346 so handle that now. */
347 if (! default_init_p
)
348 init_default_arch ();
352 return "a.out-sparc-netbsd";
355 if (target_big_endian
)
356 return "a.out-sunos-big";
357 else if (default_arch_type
== sparc86x
&& target_little_endian_data
)
358 return "a.out-sunos-big";
360 return "a.out-sparc-little";
362 return "a.out-sunos-big";
373 return "coff-sparc-lynx";
380 return "elf32-sparc-vxworks";
384 return sparc_arch_size
== 64 ? ELF64_TARGET_FORMAT
: ELF_TARGET_FORMAT
;
391 * Invocation line includes a switch not recognized by the base assembler.
392 * See if it's a processor-specific option. These are:
395 * Warn on architecture bumps. See also -A.
397 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet
398 * Standard 32 bit architectures.
400 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
401 * This used to only mean 64 bits, but properly specifying it
402 * complicated gcc's ASM_SPECs, so now opcode selection is
403 * specified orthogonally to word size (except when specifying
404 * the default, but that is an internal implementation detail).
405 * -Av8plus, -Av8plusa, -Av8plusb
406 * Same as -Av9{,a,b}.
407 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb
408 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's
410 * -xarch=v9, -xarch=v9a, -xarch=v9b
411 * Same as -Av9{,a,b} -64, for compatibility with Sun's
414 * Select the architecture and possibly the file format.
415 * Instructions or features not supported by the selected
416 * architecture cause fatal errors.
418 * The default is to start at v6, and bump the architecture up
419 * whenever an instruction is seen at a higher level. In 32 bit
420 * environments, v9 is not bumped up to, the user must pass
423 * If -bump is specified, a warning is printing when bumping to
426 * If an architecture is specified, all instructions must match
427 * that architecture. Any higher level instructions are flagged
428 * as errors. Note that in the 32 bit environment specifying
429 * -Av8plus does not automatically create a v8plus object file, a
430 * v9 insn must be seen.
432 * If both an architecture and -bump are specified, the
433 * architecture starts at the specified level, but bumps are
434 * warnings. Note that we can't set `current_architecture' to
435 * the requested level in this case: in the 32 bit environment,
436 * we still must avoid creating v8plus object files unless v9
440 * Bumping between incompatible architectures is always an
441 * error. For example, from sparclite to v9.
445 const char *md_shortopts
= "A:K:VQ:sq";
448 const char *md_shortopts
= "A:k";
450 const char *md_shortopts
= "A:";
453 struct option md_longopts
[] = {
454 #define OPTION_BUMP (OPTION_MD_BASE)
455 {"bump", no_argument
, NULL
, OPTION_BUMP
},
456 #define OPTION_SPARC (OPTION_MD_BASE + 1)
457 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
458 #define OPTION_XARCH (OPTION_MD_BASE + 2)
459 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
461 #define OPTION_32 (OPTION_MD_BASE + 3)
462 {"32", no_argument
, NULL
, OPTION_32
},
463 #define OPTION_64 (OPTION_MD_BASE + 4)
464 {"64", no_argument
, NULL
, OPTION_64
},
465 #define OPTION_TSO (OPTION_MD_BASE + 5)
466 {"TSO", no_argument
, NULL
, OPTION_TSO
},
467 #define OPTION_PSO (OPTION_MD_BASE + 6)
468 {"PSO", no_argument
, NULL
, OPTION_PSO
},
469 #define OPTION_RMO (OPTION_MD_BASE + 7)
470 {"RMO", no_argument
, NULL
, OPTION_RMO
},
472 #ifdef SPARC_BIENDIAN
473 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
474 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
475 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
476 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
478 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
479 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
480 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11)
481 {"little-endian-data", no_argument
, NULL
, OPTION_LITTLE_ENDIAN_DATA
},
483 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12)
484 {"no-undeclared-regs", no_argument
, NULL
, OPTION_NO_UNDECLARED_REGS
},
485 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13)
486 {"undeclared-regs", no_argument
, NULL
, OPTION_UNDECLARED_REGS
},
488 #define OPTION_RELAX (OPTION_MD_BASE + 14)
489 {"relax", no_argument
, NULL
, OPTION_RELAX
},
490 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15)
491 {"no-relax", no_argument
, NULL
, OPTION_NO_RELAX
},
492 #define OPTION_DCTI_COUPLES_DETECT (OPTION_MD_BASE + 16)
493 {"dcti-couples-detect", no_argument
, NULL
, OPTION_DCTI_COUPLES_DETECT
},
494 {NULL
, no_argument
, NULL
, 0}
497 size_t md_longopts_size
= sizeof (md_longopts
);
500 md_parse_option (int c
, const char *arg
)
502 /* We don't get a chance to initialize anything before we're called,
503 so handle that now. */
504 if (! default_init_p
)
505 init_default_arch ();
511 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
516 if (!strncmp (arg
, "v9", 2))
517 md_parse_option (OPTION_64
, NULL
);
520 if (!strncmp (arg
, "v8", 2)
521 || !strncmp (arg
, "v7", 2)
522 || !strncmp (arg
, "v6", 2)
523 || !strcmp (arg
, "sparclet")
524 || !strcmp (arg
, "sparclite")
525 || !strcmp (arg
, "sparc86x"))
526 md_parse_option (OPTION_32
, NULL
);
533 struct sparc_arch
*sa
;
534 enum sparc_opcode_arch_val opcode_arch
;
536 sa
= lookup_arch (arg
);
538 || ! sa
->user_option_p
)
540 if (c
== OPTION_XARCH
)
541 as_bad (_("invalid architecture -xarch=%s"), arg
);
543 as_bad (_("invalid architecture -A%s"), arg
);
547 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
548 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
549 as_fatal (_("Bad opcode table, broken assembler."));
551 if (!architecture_requested
552 || opcode_arch
> max_architecture
)
553 max_architecture
= opcode_arch
;
555 |= (((bfd_uint64_t
) sa
->hwcap2_allowed
) << 32) | sa
->hwcap_allowed
;
556 architecture_requested
= 1;
561 /* Ignore -sparc, used by SunOS make default .s.o rule. */
564 case OPTION_ENFORCE_ALIGNED_DATA
:
565 enforce_aligned_data
= 1;
568 #ifdef SPARC_BIENDIAN
569 case OPTION_LITTLE_ENDIAN
:
570 target_big_endian
= 0;
571 if (default_arch_type
!= sparclet
)
572 as_fatal ("This target does not support -EL");
574 case OPTION_LITTLE_ENDIAN_DATA
:
575 target_little_endian_data
= 1;
576 target_big_endian
= 0;
577 if (default_arch_type
!= sparc86x
578 && default_arch_type
!= v9
)
579 as_fatal ("This target does not support --little-endian-data");
581 case OPTION_BIG_ENDIAN
:
582 target_big_endian
= 1;
596 const char **list
, **l
;
598 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
599 list
= bfd_target_list ();
600 for (l
= list
; *l
!= NULL
; l
++)
602 if (sparc_arch_size
== 32)
604 if (CONST_STRNEQ (*l
, "elf32-sparc"))
609 if (CONST_STRNEQ (*l
, "elf64-sparc"))
614 as_fatal (_("No compiled in support for %d bit object file format"),
618 if (sparc_arch_size
== 64
619 && max_architecture
< SPARC_OPCODE_ARCH_V9
)
620 max_architecture
= SPARC_OPCODE_ARCH_V9
;
625 sparc_memory_model
= MM_TSO
;
629 sparc_memory_model
= MM_PSO
;
633 sparc_memory_model
= MM_RMO
;
641 /* Qy - do emit .comment
642 Qn - do not emit .comment. */
646 /* Use .stab instead of .stab.excl. */
650 /* quick -- Native assembler does fewer checks. */
654 if (strcmp (arg
, "PIC") != 0)
655 as_warn (_("Unrecognized option following -K"));
660 case OPTION_NO_UNDECLARED_REGS
:
661 no_undeclared_regs
= 1;
664 case OPTION_UNDECLARED_REGS
:
665 no_undeclared_regs
= 0;
673 case OPTION_NO_RELAX
:
677 case OPTION_DCTI_COUPLES_DETECT
:
678 dcti_couples_detect
= 1;
689 md_show_usage (FILE *stream
)
691 const struct sparc_arch
*arch
;
694 /* We don't get a chance to initialize anything before we're called,
695 so handle that now. */
696 if (! default_init_p
)
697 init_default_arch ();
699 fprintf (stream
, _("SPARC options:\n"));
701 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
703 if (!arch
->user_option_p
)
705 if (arch
!= &sparc_arch_table
[0])
706 fprintf (stream
, " | ");
707 if (column
+ strlen (arch
->name
) > 70)
710 fputc ('\n', stream
);
712 column
+= 5 + 2 + strlen (arch
->name
);
713 fprintf (stream
, "-A%s", arch
->name
);
715 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
717 if (!arch
->user_option_p
)
719 fprintf (stream
, " | ");
720 if (column
+ strlen (arch
->name
) > 65)
723 fputc ('\n', stream
);
725 column
+= 5 + 7 + strlen (arch
->name
);
726 fprintf (stream
, "-xarch=%s", arch
->name
);
728 fprintf (stream
, _("\n\
729 specify variant of SPARC architecture\n\
730 -bump warn when assembler switches architectures\n\
732 --enforce-aligned-data force .long, etc., to be aligned correctly\n\
733 -relax relax jumps and branches (default)\n\
734 -no-relax avoid changing any jumps and branches\n"));
736 fprintf (stream
, _("\
737 -k generate PIC\n"));
740 fprintf (stream
, _("\
741 -32 create 32 bit object file\n\
742 -64 create 64 bit object file\n"));
743 fprintf (stream
, _("\
744 [default is %d]\n"), default_arch_size
);
745 fprintf (stream
, _("\
746 -TSO use Total Store Ordering\n\
747 -PSO use Partial Store Ordering\n\
748 -RMO use Relaxed Memory Ordering\n"));
749 fprintf (stream
, _("\
750 [default is %s]\n"), (default_arch_size
== 64) ? "RMO" : "TSO");
751 fprintf (stream
, _("\
752 -KPIC generate PIC\n\
753 -V print assembler version number\n\
754 -undeclared-regs ignore application global register usage without\n\
755 appropriate .register directive (default)\n\
756 -no-undeclared-regs force error on application global register usage\n\
757 without appropriate .register directive\n\
758 --dcti-couples-detect warn when an unpredictable DCTI couple is found\n\
763 #ifdef SPARC_BIENDIAN
764 fprintf (stream
, _("\
765 -EL generate code for a little endian machine\n\
766 -EB generate code for a big endian machine\n\
767 --little-endian-data generate code for a machine having big endian\n\
768 instructions and little endian data.\n"));
772 /* Native operand size opcode translation. */
778 } native_op_table
[] =
780 {"ldn", "ld", "ldx"},
781 {"ldna", "lda", "ldxa"},
782 {"stn", "st", "stx"},
783 {"stna", "sta", "stxa"},
784 {"slln", "sll", "sllx"},
785 {"srln", "srl", "srlx"},
786 {"sran", "sra", "srax"},
787 {"casn", "cas", "casx"},
788 {"casna", "casa", "casxa"},
789 {"clrn", "clr", "clrx"},
793 /* sparc64 privileged and hyperprivileged registers. */
795 struct priv_reg_entry
801 struct priv_reg_entry priv_reg_table
[] =
822 {NULL
, -1}, /* End marker. */
825 struct priv_reg_entry hpriv_reg_table
[] =
835 {"hstick_offset", 28},
836 {"hstick_enable", 29},
838 {NULL
, -1}, /* End marker. */
841 /* v9a or later specific ancillary state registers. */
843 struct priv_reg_entry v9a_asr_table
[] =
846 {"sys_tick_cmpr", 25},
850 {"softint_clear", 21},
861 {"clear_softint", 21},
862 {NULL
, -1}, /* End marker. */
866 cmp_reg_entry (const void *parg
, const void *qarg
)
868 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
869 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
871 if (p
->name
== q
->name
)
873 else if (p
->name
== NULL
)
875 else if (q
->name
== NULL
)
878 return strcmp (q
->name
, p
->name
);
881 /* sparc %-pseudo-operations. */
884 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */
885 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative
887 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */
888 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the
890 instruction. (Generally they can appear
891 anywhere an immediate operand is
895 /* The name as it appears in assembler. */
897 /* The reloc this pseudo-op translates to. */
898 bfd_reloc_code_real_type reloc
;
899 /* Flags. See F_POP_* above. */
903 struct pop_entry pop_table
[] =
905 { "hix", BFD_RELOC_SPARC_HIX22
, F_POP_V9
},
906 { "lox", BFD_RELOC_SPARC_LOX10
, F_POP_V9
},
907 { "hi", BFD_RELOC_HI22
, F_POP_PCREL
},
908 { "lo", BFD_RELOC_LO10
, F_POP_PCREL
},
909 { "pc22", BFD_RELOC_SPARC_PC22
, F_POP_PCREL
},
910 { "pc10", BFD_RELOC_SPARC_PC10
, F_POP_PCREL
},
911 { "hh", BFD_RELOC_SPARC_HH22
, F_POP_V9
|F_POP_PCREL
},
912 { "hm", BFD_RELOC_SPARC_HM10
, F_POP_V9
|F_POP_PCREL
},
913 { "lm", BFD_RELOC_SPARC_LM22
, F_POP_V9
|F_POP_PCREL
},
914 { "h34", BFD_RELOC_SPARC_H34
, F_POP_V9
},
915 { "l34", BFD_RELOC_SPARC_L44
, F_POP_V9
},
916 { "h44", BFD_RELOC_SPARC_H44
, F_POP_V9
},
917 { "m44", BFD_RELOC_SPARC_M44
, F_POP_V9
},
918 { "l44", BFD_RELOC_SPARC_L44
, F_POP_V9
},
919 { "uhi", BFD_RELOC_SPARC_HH22
, F_POP_V9
},
920 { "ulo", BFD_RELOC_SPARC_HM10
, F_POP_V9
},
921 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22
, 0 },
922 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10
, 0 },
923 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22
, 0 },
924 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10
, 0 },
925 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22
, 0 },
926 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10
, 0 },
927 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22
, 0 },
928 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10
, 0 },
929 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22
, 0 },
930 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10
, 0 },
931 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22
, 0 },
932 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10
, 0 },
933 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD
, F_POP_POSTFIX
},
934 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
935 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD
, F_POP_POSTFIX
},
936 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL
, F_POP_POSTFIX
|F_POP_TLS_CALL
},
937 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD
, F_POP_POSTFIX
},
938 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX
, F_POP_POSTFIX
},
939 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD
, F_POP_POSTFIX
},
940 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD
, F_POP_POSTFIX
},
941 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP
, F_POP_POSTFIX
}
944 /* Table of %-names that can appear in a sparc assembly program. This
945 table is initialized in md_begin and contains entries for each
946 privileged/hyperprivileged/alternate register and %-pseudo-op. */
959 enum perc_entry_type type
;
960 /* Name of the %-entity. */
964 /* Value. Either a pop or a reg depending on type.*/
967 struct pop_entry
*pop
;
968 struct priv_reg_entry
*reg
;
972 #define NUM_PERC_ENTRIES \
973 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \
974 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \
975 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \
976 + ARRAY_SIZE (pop_table) \
979 struct perc_entry perc_table
[NUM_PERC_ENTRIES
];
982 cmp_perc_entry (const void *parg
, const void *qarg
)
984 const struct perc_entry
*p
= (const struct perc_entry
*) parg
;
985 const struct perc_entry
*q
= (const struct perc_entry
*) qarg
;
987 if (p
->name
== q
->name
)
989 else if (p
->name
== NULL
)
991 else if (q
->name
== NULL
)
994 return strcmp (q
->name
, p
->name
);
997 /* This function is called once, at assembler startup time. It should
998 set up all the tables, etc. that the MD part of the assembler will
1004 const char *retval
= NULL
;
1008 /* We don't get a chance to initialize anything before md_parse_option
1009 is called, and it may not be called, so handle default initialization
1010 now if not already done. */
1011 if (! default_init_p
)
1012 init_default_arch ();
1014 sparc_cie_data_alignment
= sparc_arch_size
== 64 ? -8 : -4;
1015 op_hash
= hash_new ();
1017 while (i
< (unsigned int) sparc_num_opcodes
)
1019 const char *name
= sparc_opcodes
[i
].name
;
1020 retval
= hash_insert (op_hash
, name
, (void *) &sparc_opcodes
[i
]);
1023 as_bad (_("Internal error: can't hash `%s': %s\n"),
1024 sparc_opcodes
[i
].name
, retval
);
1029 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
1031 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"),
1032 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
1037 while (i
< (unsigned int) sparc_num_opcodes
1038 && !strcmp (sparc_opcodes
[i
].name
, name
));
1041 for (i
= 0; native_op_table
[i
].name
; i
++)
1043 const struct sparc_opcode
*insn
;
1044 const char *name
= ((sparc_arch_size
== 32)
1045 ? native_op_table
[i
].name32
1046 : native_op_table
[i
].name64
);
1047 insn
= (struct sparc_opcode
*) hash_find (op_hash
, name
);
1050 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"),
1051 name
, native_op_table
[i
].name
);
1056 retval
= hash_insert (op_hash
, native_op_table
[i
].name
,
1060 as_bad (_("Internal error: can't hash `%s': %s\n"),
1061 sparc_opcodes
[i
].name
, retval
);
1068 as_fatal (_("Broken assembler. No assembly attempted."));
1070 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
1071 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
1072 qsort (hpriv_reg_table
, sizeof (hpriv_reg_table
) / sizeof (hpriv_reg_table
[0]),
1073 sizeof (hpriv_reg_table
[0]), cmp_reg_entry
);
1074 qsort (v9a_asr_table
, sizeof (v9a_asr_table
) / sizeof (v9a_asr_table
[0]),
1075 sizeof (v9a_asr_table
[0]), cmp_reg_entry
);
1077 /* If -bump, record the architecture level at which we start issuing
1078 warnings. The behaviour is different depending upon whether an
1079 architecture was explicitly specified. If it wasn't, we issue warnings
1080 for all upwards bumps. If it was, we don't start issuing warnings until
1081 we need to bump beyond the requested architecture or when we bump between
1082 conflicting architectures. */
1085 && architecture_requested
)
1087 /* `max_architecture' records the requested architecture.
1088 Issue warnings if we go above it. */
1089 warn_after_architecture
= max_architecture
;
1092 /* Find the highest architecture level that doesn't conflict with
1093 the requested one. */
1096 || !architecture_requested
)
1098 enum sparc_opcode_arch_val current_max_architecture
1101 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
1102 max_architecture
> warn_after_architecture
;
1104 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
1105 current_max_architecture
))
1109 /* Prepare the tables of %-pseudo-ops. */
1111 struct priv_reg_entry
*reg_tables
[]
1112 = {priv_reg_table
, hpriv_reg_table
, v9a_asr_table
, NULL
};
1113 struct priv_reg_entry
**reg_table
;
1116 /* Add registers. */
1117 for (reg_table
= reg_tables
; reg_table
[0]; reg_table
++)
1119 struct priv_reg_entry
*reg
;
1120 for (reg
= *reg_table
; reg
->name
; reg
++)
1122 struct perc_entry
*p
= &perc_table
[entry
++];
1123 p
->type
= perc_entry_reg
;
1124 p
->name
= reg
->name
;
1125 p
->len
= strlen (reg
->name
);
1130 /* Add %-pseudo-ops. */
1131 for (i
= 0; i
< ARRAY_SIZE (pop_table
); i
++)
1133 struct perc_entry
*p
= &perc_table
[entry
++];
1134 p
->type
= (pop_table
[i
].flags
& F_POP_POSTFIX
1135 ? perc_entry_post_pop
: perc_entry_imm_pop
);
1136 p
->name
= pop_table
[i
].name
;
1137 p
->len
= strlen (pop_table
[i
].name
);
1138 p
->pop
= &pop_table
[i
];
1141 /* Last entry is the centinel. */
1142 perc_table
[entry
].type
= perc_entry_none
;
1144 qsort (perc_table
, sizeof (perc_table
) / sizeof (perc_table
[0]),
1145 sizeof (perc_table
[0]), cmp_perc_entry
);
1150 /* Called after all assembly has been done. */
1155 unsigned long mach
= bfd_mach_sparc
;
1156 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1157 int hwcaps
, hwcaps2
;
1160 if (sparc_arch_size
== 64)
1161 switch (current_architecture
)
1163 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v9a
; break;
1164 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v9b
; break;
1165 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v9c
; break;
1166 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v9d
; break;
1167 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v9e
; break;
1168 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v9v
; break;
1169 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v9m
; break;
1170 default: mach
= bfd_mach_sparc_v9
; break;
1173 switch (current_architecture
)
1175 case SPARC_OPCODE_ARCH_SPARCLET
: mach
= bfd_mach_sparc_sparclet
; break;
1176 case SPARC_OPCODE_ARCH_V9
: mach
= bfd_mach_sparc_v8plus
; break;
1177 case SPARC_OPCODE_ARCH_V9A
: mach
= bfd_mach_sparc_v8plusa
; break;
1178 case SPARC_OPCODE_ARCH_V9B
: mach
= bfd_mach_sparc_v8plusb
; break;
1179 case SPARC_OPCODE_ARCH_V9C
: mach
= bfd_mach_sparc_v8plusc
; break;
1180 case SPARC_OPCODE_ARCH_V9D
: mach
= bfd_mach_sparc_v8plusd
; break;
1181 case SPARC_OPCODE_ARCH_V9E
: mach
= bfd_mach_sparc_v8pluse
; break;
1182 case SPARC_OPCODE_ARCH_V9V
: mach
= bfd_mach_sparc_v8plusv
; break;
1183 case SPARC_OPCODE_ARCH_V9M
: mach
= bfd_mach_sparc_v8plusm
; break;
1184 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
1185 be but for now it is (since that's the way it's always been
1189 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, mach
);
1191 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
1192 hwcaps
= hwcap_seen
& U0xffffffff
;
1193 hwcaps2
= hwcap_seen
>> 32;
1196 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS
, hwcaps
);
1198 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, Tag_GNU_Sparc_HWCAPS2
, hwcaps2
);
1202 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
1205 in_signed_range (bfd_signed_vma val
, bfd_signed_vma max
)
1209 /* Sign-extend the value from the architecture word size, so that
1210 0xffffffff is always considered -1 on sparc32. */
1211 if (sparc_arch_size
== 32)
1213 bfd_signed_vma sign
= (bfd_signed_vma
) 1 << 31;
1214 val
= ((val
& U0xffffffff
) ^ sign
) - sign
;
1223 /* Return non-zero if VAL is in the range 0 to MAX. */
1226 in_unsigned_range (bfd_vma val
, bfd_vma max
)
1233 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
1234 (e.g. -15 to +31). */
1237 in_bitfield_range (bfd_signed_vma val
, bfd_signed_vma max
)
1243 if (val
< ~(max
>> 1))
1249 sparc_ffs (unsigned int mask
)
1256 for (i
= 0; (mask
& 1) == 0; ++i
)
1261 /* Implement big shift right. */
1263 BSR (bfd_vma val
, int amount
)
1265 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
1266 as_fatal (_("Support for 64-bit arithmetic not compiled in."));
1267 return val
>> amount
;
1270 /* For communication between sparc_ip and get_expression. */
1271 static char *expr_end
;
1273 /* Values for `special_case'.
1274 Instructions that require wierd handling because they're longer than
1276 #define SPECIAL_CASE_NONE 0
1277 #define SPECIAL_CASE_SET 1
1278 #define SPECIAL_CASE_SETSW 2
1279 #define SPECIAL_CASE_SETX 3
1280 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
1281 #define SPECIAL_CASE_FDIV 4
1283 /* Bit masks of various insns. */
1284 #define NOP_INSN 0x01000000
1285 #define OR_INSN 0x80100000
1286 #define XOR_INSN 0x80180000
1287 #define FMOVS_INSN 0x81A00020
1288 #define SETHI_INSN 0x01000000
1289 #define SLLX_INSN 0x81281000
1290 #define SRA_INSN 0x81380000
1292 /* The last instruction to be assembled. */
1293 static const struct sparc_opcode
*last_insn
;
1294 /* The assembled opcode of `last_insn'. */
1295 static unsigned long last_opcode
;
1297 /* Handle the set and setuw synthetic instructions. */
1300 synthetize_setuw (const struct sparc_opcode
*insn
)
1302 int need_hi22_p
= 0;
1303 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1305 if (the_insn
.exp
.X_op
== O_constant
)
1307 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1309 if (sizeof (offsetT
) > 4
1310 && (the_insn
.exp
.X_add_number
< 0
1311 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1312 as_warn (_("set: number not in 0..4294967295 range"));
1316 if (sizeof (offsetT
) > 4
1317 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1318 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1319 as_warn (_("set: number not in -2147483648..4294967295 range"));
1320 the_insn
.exp
.X_add_number
= (int) the_insn
.exp
.X_add_number
;
1324 /* See if operand is absolute and small; skip sethi if so. */
1325 if (the_insn
.exp
.X_op
!= O_constant
1326 || the_insn
.exp
.X_add_number
>= (1 << 12)
1327 || the_insn
.exp
.X_add_number
< -(1 << 12))
1329 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1330 | ((the_insn
.exp
.X_add_number
>> 10)
1331 & (the_insn
.exp
.X_op
== O_constant
1333 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1334 ? BFD_RELOC_HI22
: BFD_RELOC_NONE
);
1335 output_insn (insn
, &the_insn
);
1339 /* See if operand has no low-order bits; skip OR if so. */
1340 if (the_insn
.exp
.X_op
!= O_constant
1341 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
1344 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
1346 | (the_insn
.exp
.X_add_number
1347 & (the_insn
.exp
.X_op
!= O_constant
1348 ? 0 : need_hi22_p
? 0x3ff : 0x1fff)));
1349 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1350 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1351 output_insn (insn
, &the_insn
);
1355 /* Handle the setsw synthetic instruction. */
1358 synthetize_setsw (const struct sparc_opcode
*insn
)
1362 rd
= (the_insn
.opcode
& RD (~0)) >> 25;
1364 if (the_insn
.exp
.X_op
!= O_constant
)
1366 synthetize_setuw (insn
);
1368 /* Need to sign extend it. */
1369 the_insn
.opcode
= (SRA_INSN
| RS1 (rd
) | RD (rd
));
1370 the_insn
.reloc
= BFD_RELOC_NONE
;
1371 output_insn (insn
, &the_insn
);
1375 if (sizeof (offsetT
) > 4
1376 && (the_insn
.exp
.X_add_number
< -(offsetT
) U0x80000000
1377 || the_insn
.exp
.X_add_number
> (offsetT
) U0xffffffff
))
1378 as_warn (_("setsw: number not in -2147483648..4294967295 range"));
1380 low32
= the_insn
.exp
.X_add_number
;
1384 synthetize_setuw (insn
);
1390 the_insn
.reloc
= BFD_RELOC_NONE
;
1391 /* See if operand is absolute and small; skip sethi if so. */
1392 if (low32
< -(1 << 12))
1394 the_insn
.opcode
= (SETHI_INSN
| RD (rd
)
1395 | (((~the_insn
.exp
.X_add_number
) >> 10) & 0x3fffff));
1396 output_insn (insn
, &the_insn
);
1397 low32
= 0x1c00 | (low32
& 0x3ff);
1398 opc
= RS1 (rd
) | XOR_INSN
;
1401 the_insn
.opcode
= (opc
| RD (rd
) | IMMED
1402 | (low32
& 0x1fff));
1403 output_insn (insn
, &the_insn
);
1406 /* Handle the setx synthetic instruction. */
1409 synthetize_setx (const struct sparc_opcode
*insn
)
1411 int upper32
, lower32
;
1412 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
1413 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
1415 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
1416 int need_xor10_p
= 0;
1418 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000)
1419 lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
1420 upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
1423 upper_dstreg
= tmpreg
;
1424 /* The tmp reg should not be the dst reg. */
1425 if (tmpreg
== dstreg
)
1426 as_warn (_("setx: temporary register same as destination register"));
1428 /* ??? Obviously there are other optimizations we can do
1429 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
1430 doing some of these. Later. If you do change things, try to
1431 change all of this to be table driven as well. */
1432 /* What to output depends on the number if it's constant.
1433 Compute that first, then output what we've decided upon. */
1434 if (the_insn
.exp
.X_op
!= O_constant
)
1436 if (sparc_arch_size
== 32)
1438 /* When arch size is 32, we want setx to be equivalent
1439 to setuw for anything but constants. */
1440 the_insn
.exp
.X_add_number
&= 0xffffffff;
1441 synthetize_setuw (insn
);
1444 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
1450 /* Reset X_add_number, we've extracted it as upper32/lower32.
1451 Otherwise fixup_segment will complain about not being able to
1452 write an 8 byte number in a 4 byte field. */
1453 the_insn
.exp
.X_add_number
= 0;
1455 /* Only need hh22 if `or' insn can't handle constant. */
1456 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
1459 /* Does bottom part (after sethi) have bits? */
1460 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
1461 /* No hh22, but does upper32 still have bits we can't set
1463 || (! need_hh22_p
&& upper32
!= 0 && upper32
!= -1))
1466 /* If the lower half is all zero, we build the upper half directly
1467 into the dst reg. */
1469 /* Need lower half if number is zero or 0xffffffff00000000. */
1470 || (! need_hh22_p
&& ! need_hm10_p
))
1472 /* No need for sethi if `or' insn can handle constant. */
1473 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
1474 /* Note that we can't use a negative constant in the `or'
1475 insn unless the upper 32 bits are all ones. */
1476 || (lower32
< 0 && upper32
!= -1)
1477 || (lower32
>= 0 && upper32
== -1))
1480 if (need_hi22_p
&& upper32
== -1)
1483 /* Does bottom part (after sethi) have bits? */
1484 else if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1486 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1487 /* Need `or' if we didn't set anything else. */
1488 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1492 /* Output directly to dst reg if lower 32 bits are all zero. */
1493 upper_dstreg
= dstreg
;
1496 if (!upper_dstreg
&& dstreg
)
1497 as_warn (_("setx: illegal temporary register g0"));
1501 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1502 | ((upper32
>> 10) & 0x3fffff));
1503 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1504 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1505 output_insn (insn
, &the_insn
);
1510 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1511 | (((need_xor10_p
? ~lower32
: lower32
)
1512 >> 10) & 0x3fffff));
1513 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1514 ? BFD_RELOC_SPARC_LM22
: BFD_RELOC_NONE
);
1515 output_insn (insn
, &the_insn
);
1520 the_insn
.opcode
= (OR_INSN
1521 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1524 | (upper32
& (need_hh22_p
? 0x3ff : 0x1fff)));
1525 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1526 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1527 output_insn (insn
, &the_insn
);
1532 /* FIXME: One nice optimization to do here is to OR the low part
1533 with the highpart if hi22 isn't needed and the low part is
1535 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1538 | (lower32
& (need_hi22_p
? 0x3ff : 0x1fff)));
1539 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1540 ? BFD_RELOC_LO10
: BFD_RELOC_NONE
);
1541 output_insn (insn
, &the_insn
);
1544 /* If we needed to build the upper part, shift it into place. */
1545 if (need_hh22_p
|| need_hm10_p
)
1547 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1549 the_insn
.reloc
= BFD_RELOC_NONE
;
1550 output_insn (insn
, &the_insn
);
1553 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */
1556 the_insn
.opcode
= (XOR_INSN
| RS1 (dstreg
) | RD (dstreg
) | IMMED
1557 | 0x1c00 | (lower32
& 0x3ff));
1558 the_insn
.reloc
= BFD_RELOC_NONE
;
1559 output_insn (insn
, &the_insn
);
1562 /* If we needed to build both upper and lower parts, OR them together. */
1563 else if ((need_hh22_p
|| need_hm10_p
) && (need_hi22_p
|| need_lo10_p
))
1565 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1567 the_insn
.reloc
= BFD_RELOC_NONE
;
1568 output_insn (insn
, &the_insn
);
1572 /* Main entry point to assemble one instruction. */
1575 md_assemble (char *str
)
1577 const struct sparc_opcode
*insn
;
1581 special_case
= sparc_ip (str
, &insn
);
1585 /* Certain instructions may not appear on delay slots. Check for
1586 these situations. */
1587 if (last_insn
!= NULL
1588 && (last_insn
->flags
& F_DELAYED
) != 0)
1590 /* Before SPARC V9 the effect of having a delayed branch
1591 instruction in the delay slot of a conditional delayed branch
1594 In SPARC V9 DCTI couples are well defined.
1596 However, starting with the UltraSPARC Architecture 2005, DCTI
1597 couples (of all kind) are deprecated and should not be used,
1598 as they may be slow or behave differently to what the
1599 programmer expects. */
1600 if (dcti_couples_detect
1601 && (insn
->flags
& F_DELAYED
) != 0
1602 && ((max_architecture
< SPARC_OPCODE_ARCH_V9
1603 && (last_insn
->flags
& F_CONDBR
) != 0)
1604 || max_architecture
>= SPARC_OPCODE_ARCH_V9C
))
1605 as_warn (_("unpredictable DCTI couple"));
1608 /* We warn about attempts to put a floating point branch in a
1609 delay slot, unless the delay slot has been annulled. */
1610 if ((insn
->flags
& F_FBR
) != 0
1611 /* ??? This test isn't completely accurate. We assume anything with
1612 F_{UNBR,CONDBR,FBR} set is annullable. */
1613 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
1614 || (last_opcode
& ANNUL
) == 0))
1615 as_warn (_("FP branch in delay slot"));
1618 /* SPARC before v9 requires a nop instruction between a floating
1619 point instruction and a floating point branch. We insert one
1620 automatically, with a warning. */
1621 if (max_architecture
< SPARC_OPCODE_ARCH_V9
1622 && last_insn
!= NULL
1623 && (insn
->flags
& F_FBR
) != 0
1624 && (last_insn
->flags
& F_FLOAT
) != 0)
1626 struct sparc_it nop_insn
;
1628 nop_insn
.opcode
= NOP_INSN
;
1629 nop_insn
.reloc
= BFD_RELOC_NONE
;
1630 output_insn (insn
, &nop_insn
);
1631 as_warn (_("FP branch preceded by FP instruction; NOP inserted"));
1634 switch (special_case
)
1636 case SPECIAL_CASE_NONE
:
1638 output_insn (insn
, &the_insn
);
1641 case SPECIAL_CASE_SETSW
:
1642 synthetize_setsw (insn
);
1645 case SPECIAL_CASE_SET
:
1646 synthetize_setuw (insn
);
1649 case SPECIAL_CASE_SETX
:
1650 synthetize_setx (insn
);
1653 case SPECIAL_CASE_FDIV
:
1655 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1657 output_insn (insn
, &the_insn
);
1659 /* According to information leaked from Sun, the "fdiv" instructions
1660 on early SPARC machines would produce incorrect results sometimes.
1661 The workaround is to add an fmovs of the destination register to
1662 itself just after the instruction. This was true on machines
1663 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1664 gas_assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1665 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1666 output_insn (insn
, &the_insn
);
1671 as_fatal (_("failed special case insn sanity check"));
1676 get_hwcap_name (bfd_uint64_t mask
)
1678 if (mask
& HWCAP_MUL32
)
1680 if (mask
& HWCAP_DIV32
)
1682 if (mask
& HWCAP_FSMULD
)
1684 if (mask
& HWCAP_V8PLUS
)
1686 if (mask
& HWCAP_POPC
)
1688 if (mask
& HWCAP_VIS
)
1690 if (mask
& HWCAP_VIS2
)
1692 if (mask
& HWCAP_ASI_BLK_INIT
)
1693 return "ASIBlkInit";
1694 if (mask
& HWCAP_FMAF
)
1696 if (mask
& HWCAP_VIS3
)
1698 if (mask
& HWCAP_HPC
)
1700 if (mask
& HWCAP_RANDOM
)
1702 if (mask
& HWCAP_TRANS
)
1704 if (mask
& HWCAP_FJFMAU
)
1706 if (mask
& HWCAP_IMA
)
1708 if (mask
& HWCAP_ASI_CACHE_SPARING
)
1710 if (mask
& HWCAP_AES
)
1712 if (mask
& HWCAP_DES
)
1714 if (mask
& HWCAP_KASUMI
)
1716 if (mask
& HWCAP_CAMELLIA
)
1718 if (mask
& HWCAP_MD5
)
1720 if (mask
& HWCAP_SHA1
)
1722 if (mask
& HWCAP_SHA256
)
1724 if (mask
& HWCAP_SHA512
)
1726 if (mask
& HWCAP_MPMUL
)
1728 if (mask
& HWCAP_MONT
)
1730 if (mask
& HWCAP_PAUSE
)
1732 if (mask
& HWCAP_CBCOND
)
1734 if (mask
& HWCAP_CRC32C
)
1738 if (mask
& HWCAP2_FJATHPLUS
)
1740 if (mask
& HWCAP2_VIS3B
)
1742 if (mask
& HWCAP2_ADP
)
1744 if (mask
& HWCAP2_SPARC5
)
1746 if (mask
& HWCAP2_MWAIT
)
1748 if (mask
& HWCAP2_XMPMUL
)
1750 if (mask
& HWCAP2_XMONT
)
1752 if (mask
& HWCAP2_NSEC
)
1758 /* Subroutine of md_assemble to do the actual parsing. */
1761 sparc_ip (char *str
, const struct sparc_opcode
**pinsn
)
1763 const char *error_message
= "";
1767 const struct sparc_opcode
*insn
;
1769 unsigned long opcode
;
1770 unsigned int mask
= 0;
1774 int special_case
= SPECIAL_CASE_NONE
;
1781 while (ISLOWER (*s
) || ISDIGIT (*s
) || *s
== '_');
1798 as_bad (_("Unknown opcode: `%s'"), str
);
1800 return special_case
;
1802 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1806 as_bad (_("Unknown opcode: `%s'"), str
);
1807 return special_case
;
1817 opcode
= insn
->match
;
1818 memset (&the_insn
, '\0', sizeof (the_insn
));
1819 the_insn
.reloc
= BFD_RELOC_NONE
;
1822 /* Build the opcode, checking as we go to make sure that the
1824 for (args
= insn
->args
;; ++args
)
1832 /* Parse a series of masks. */
1839 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1842 error_message
= _(": invalid membar mask name");
1848 if (*s
== '|' || *s
== '+')
1856 if (! parse_const_expr_arg (&s
, &kmask
))
1858 error_message
= _(": invalid membar mask expression");
1861 if (kmask
< 0 || kmask
> 127)
1863 error_message
= _(": invalid membar mask number");
1868 opcode
|= MEMBAR (kmask
);
1876 if (! parse_const_expr_arg (&s
, &smask
))
1878 error_message
= _(": invalid siam mode expression");
1881 if (smask
< 0 || smask
> 7)
1883 error_message
= _(": invalid siam mode number");
1894 /* Parse a prefetch function. */
1897 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1899 error_message
= _(": invalid prefetch function name");
1905 if (! parse_const_expr_arg (&s
, &fcn
))
1907 error_message
= _(": invalid prefetch function expression");
1910 if (fcn
< 0 || fcn
> 31)
1912 error_message
= _(": invalid prefetch function number");
1922 /* Parse a sparc64 privileged register. */
1925 struct priv_reg_entry
*p
;
1926 unsigned int len
= 9999999; /* Init to make gcc happy. */
1929 for (p
= priv_reg_table
; p
->name
; p
++)
1930 if (p
->name
[0] == s
[0])
1932 len
= strlen (p
->name
);
1933 if (strncmp (p
->name
, s
, len
) == 0)
1939 error_message
= _(": unrecognizable privileged register");
1943 if (((opcode
>> (*args
== '?' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1945 error_message
= _(": unrecognizable privileged register");
1954 error_message
= _(": unrecognizable privileged register");
1960 /* Parse a sparc64 hyperprivileged register. */
1963 struct priv_reg_entry
*p
;
1964 unsigned int len
= 9999999; /* Init to make gcc happy. */
1967 for (p
= hpriv_reg_table
; p
->name
; p
++)
1968 if (p
->name
[0] == s
[0])
1970 len
= strlen (p
->name
);
1971 if (strncmp (p
->name
, s
, len
) == 0)
1977 error_message
= _(": unrecognizable hyperprivileged register");
1981 if (((opcode
>> (*args
== '$' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
1983 error_message
= _(": unrecognizable hyperprivileged register");
1992 error_message
= _(": unrecognizable hyperprivileged register");
1998 /* Parse a v9a or later ancillary state register. */
2001 struct priv_reg_entry
*p
;
2002 unsigned int len
= 9999999; /* Init to make gcc happy. */
2005 for (p
= v9a_asr_table
; p
->name
; p
++)
2006 if (p
->name
[0] == s
[0])
2008 len
= strlen (p
->name
);
2009 if (strncmp (p
->name
, s
, len
) == 0)
2015 error_message
= _(": unrecognizable ancillary state register");
2019 if (((opcode
>> (*args
== '/' ? 14 : 25)) & 0x1f) != (unsigned) p
->regnum
)
2021 error_message
= _(": unrecognizable ancillary state register");
2030 error_message
= _(": unrecognizable ancillary state register");
2036 if (strncmp (s
, "%asr", 4) == 0)
2044 while (ISDIGIT (*s
))
2046 num
= num
* 10 + *s
- '0';
2050 /* We used to check here for the asr number to
2051 be between 16 and 31 in V9 and later, as
2052 mandated by the section C.1.1 "Register
2053 Names" in the SPARC spec. However, we
2054 decided to remove this restriction as a) it
2055 introduces problems when new V9 asr registers
2056 are introduced, b) the Solaris assembler
2057 doesn't implement this restriction and c) the
2058 restriction will go away in future revisions
2059 of the Oracle SPARC Architecture. */
2061 if (num
< 0 || 31 < num
)
2063 error_message
= _(": asr number must be between 0 and 31");
2067 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
2072 error_message
= _(": expecting %asrN");
2079 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
2083 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
2089 if ((s
[0] == '0' && s
[1] == 'x' && ISXDIGIT (s
[2]))
2094 if (s
[0] == '0' && s
[1] == 'x')
2097 while (ISXDIGIT (*s
))
2100 num
|= hex_value (*s
);
2106 while (ISDIGIT (*s
))
2108 num
= num
* 10 + *s
- '0';
2112 if (num
< 0 || num
> 31)
2114 error_message
= _(": crypto immediate must be between 0 and 31");
2118 opcode
|= RS3 (num
);
2123 error_message
= _(": expecting crypto immediate");
2128 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
2129 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2130 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
2132 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2133 /* These fields are unsigned, but for upward compatibility,
2134 allow negative values as well. */
2138 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
2139 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2140 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
2142 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2143 /* These fields are unsigned, but for upward compatibility,
2144 allow negative values as well. */
2148 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
2153 the_insn
.reloc
= /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10
;
2158 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
2163 if (*s
== 'p' && s
[1] == 'n')
2171 if (*s
== 'p' && s
[1] == 't')
2183 if ((strncmp (s
, "%icc", 4) == 0)
2184 || (sparc_arch_size
== 32 && strncmp (s
, "%ncc", 4) == 0))
2196 if ((strncmp (s
, "%xcc", 4) == 0)
2197 || (sparc_arch_size
== 64 && strncmp (s
, "%ncc", 4) == 0))
2209 if (strncmp (s
, "%fcc0", 5) == 0)
2221 if (strncmp (s
, "%fcc1", 5) == 0)
2233 if (strncmp (s
, "%fcc2", 5) == 0)
2245 if (strncmp (s
, "%fcc3", 5) == 0)
2253 if (strncmp (s
, "%pc", 3) == 0)
2261 if (strncmp (s
, "%tick", 5) == 0)
2268 case '\0': /* End of args. */
2269 if (s
[0] == ',' && s
[1] == '%')
2273 const struct perc_entry
*p
;
2275 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2276 if ((p
->type
== perc_entry_post_pop
|| p
->type
== perc_entry_reg
)
2277 && strncmp (s
+ 2, p
->name
, p
->len
) == 0)
2279 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2282 if (s
[p
->len
+ 2] != '(')
2284 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2285 return special_case
;
2288 if (! (p
->pop
->flags
& F_POP_TLS_CALL
)
2289 && the_insn
.reloc
!= BFD_RELOC_NONE
)
2291 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"),
2293 return special_case
;
2296 if ((p
->pop
->flags
& F_POP_TLS_CALL
)
2297 && (the_insn
.reloc
!= BFD_RELOC_32_PCREL_S2
2298 || the_insn
.exp
.X_add_number
!= 0
2299 || the_insn
.exp
.X_add_symbol
2300 != symbol_find_or_make ("__tls_get_addr")))
2302 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"),
2304 return special_case
;
2307 the_insn
.reloc
= p
->pop
->reloc
;
2308 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2311 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2314 else if (*s1
== ')')
2323 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2324 return special_case
;
2328 (void) get_expression (s
);
2348 case '[': /* These must match exactly. */
2356 case '#': /* Must be at least one digit. */
2359 while (ISDIGIT (*s
))
2367 case 'C': /* Coprocessor state register. */
2368 if (strncmp (s
, "%csr", 4) == 0)
2375 case 'b': /* Next operand is a coprocessor register. */
2378 if (*s
++ == '%' && *s
++ == 'c' && ISDIGIT (*s
))
2383 mask
= 10 * (mask
- '0') + (*s
++ - '0');
2397 opcode
|= mask
<< 14;
2405 opcode
|= mask
<< 25;
2411 case 'r': /* next operand must be a register */
2421 case 'f': /* frame pointer */
2429 case 'g': /* global register */
2438 case 'i': /* in register */
2442 mask
= c
- '0' + 24;
2447 case 'l': /* local register */
2451 mask
= (c
- '0' + 16);
2456 case 'o': /* out register */
2460 mask
= (c
- '0' + 8);
2465 case 's': /* stack pointer */
2473 case 'r': /* any register */
2474 if (!ISDIGIT ((c
= *s
++)))
2491 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
2507 if ((mask
& ~1) == 2 && sparc_arch_size
== 64
2508 && no_undeclared_regs
&& ! globals
[mask
])
2509 as_bad (_("detected global register use not covered by .register pseudo-op"));
2511 /* Got the register, now figure out where
2512 it goes in the opcode. */
2516 opcode
|= mask
<< 14;
2524 opcode
|= mask
<< 25;
2528 opcode
|= (mask
<< 25) | (mask
<< 14);
2532 opcode
|= (mask
<< 25) | (mask
<< 0);
2538 case 'e': /* next operand is a floating point register */
2557 && ((format
= *s
) == 'f'
2562 for (mask
= 0; ISDIGIT (*s
); ++s
)
2564 mask
= 10 * mask
+ (*s
- '0');
2565 } /* read the number */
2574 /* register must be even numbered */
2584 /* register must be multiple of 4 */
2590 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2591 error_message
= _(": There are only 64 f registers; [0-63]");
2593 error_message
= _(": There are only 32 f registers; [0-31]");
2596 else if (mask
>= 32)
2598 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
2600 if (*args
== 'e' || *args
== 'f' || *args
== 'g')
2603 = _(": There are only 32 single precision f registers; [0-31]");
2607 mask
-= 31; /* wrap high bit */
2611 error_message
= _(": There are only 32 f registers; [0-31]");
2619 } /* if not an 'f' register. */
2621 if (*args
== '}' && mask
!= RS2 (opcode
))
2624 = _(": Instruction requires frs2 and frsd must be the same register");
2633 opcode
|= RS1 (mask
);
2639 opcode
|= RS2 (mask
);
2644 opcode
|= RS3 (mask
);
2651 opcode
|= RD (mask
);
2660 if (strncmp (s
, "%fsr", 4) == 0)
2668 if (strncmp (s
, "%efsr", 5) == 0)
2675 case '0': /* 64 bit immediate (set, setsw, setx insn) */
2676 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
2679 case 'l': /* 22 bit PC relative immediate */
2680 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
2684 case 'L': /* 30 bit immediate */
2685 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
2690 case 'n': /* 22 bit immediate */
2691 the_insn
.reloc
= BFD_RELOC_SPARC22
;
2694 case 'i': /* 13 bit immediate */
2695 the_insn
.reloc
= BFD_RELOC_SPARC13
;
2705 const char *op_arg
= NULL
;
2706 static expressionS op_exp
;
2707 bfd_reloc_code_real_type old_reloc
= the_insn
.reloc
;
2709 /* Check for %hi, etc. */
2712 const struct perc_entry
*p
;
2714 for (p
= perc_table
; p
->type
!= perc_entry_none
; p
++)
2715 if ((p
->type
== perc_entry_imm_pop
|| p
->type
== perc_entry_reg
)
2716 && strncmp (s
+ 1, p
->name
, p
->len
) == 0)
2718 if (p
->type
== perc_entry_none
|| p
->type
== perc_entry_reg
)
2721 if (s
[p
->len
+ 1] != '(')
2723 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p
->name
);
2724 return special_case
;
2728 the_insn
.reloc
= p
->pop
->reloc
;
2730 v9_arg_p
= p
->pop
->flags
& F_POP_V9
;
2733 /* Note that if the get_expression() fails, we will still
2734 have created U entries in the symbol table for the
2735 'symbols' in the input string. Try not to create U
2736 symbols for registers, etc. */
2738 /* This stuff checks to see if the expression ends in
2739 +%reg. If it does, it removes the register from
2740 the expression, and re-sets 's' to point to the
2747 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2750 else if (*s1
== ')')
2759 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg
);
2760 return special_case
;
2764 (void) get_expression (s
);
2768 as_bad (_("Expression inside %%%s could not be parsed"), op_arg
);
2769 return special_case
;
2772 if (*s
== ',' || *s
== ']' || !*s
)
2774 if (*s
!= '+' && *s
!= '-')
2776 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg
);
2777 return special_case
;
2781 op_exp
= the_insn
.exp
;
2782 memset (&the_insn
.exp
, 0, sizeof (the_insn
.exp
));
2785 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++)
2788 if (s1
!= s
&& ISDIGIT (s1
[-1]))
2790 if (s1
[-2] == '%' && s1
[-3] == '+')
2792 else if (strchr ("golir0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
2794 else if (s1
[-3] == 'r' && s1
[-4] == '%' && s1
[-5] == '+')
2801 if (op_arg
&& s1
== s
+ 1)
2802 the_insn
.exp
.X_op
= O_absent
;
2804 (void) get_expression (s
);
2816 (void) get_expression (s
);
2824 the_insn
.exp2
= the_insn
.exp
;
2825 the_insn
.exp
= op_exp
;
2826 if (the_insn
.exp2
.X_op
== O_absent
)
2827 the_insn
.exp2
.X_op
= O_illegal
;
2828 else if (the_insn
.exp
.X_op
== O_absent
)
2830 the_insn
.exp
= the_insn
.exp2
;
2831 the_insn
.exp2
.X_op
= O_illegal
;
2833 else if (the_insn
.exp
.X_op
== O_constant
)
2835 valueT val
= the_insn
.exp
.X_add_number
;
2836 switch (the_insn
.reloc
)
2841 case BFD_RELOC_SPARC_HH22
:
2842 val
= BSR (val
, 32);
2845 case BFD_RELOC_SPARC_LM22
:
2846 case BFD_RELOC_HI22
:
2847 val
= (val
>> 10) & 0x3fffff;
2850 case BFD_RELOC_SPARC_HM10
:
2851 val
= BSR (val
, 32);
2854 case BFD_RELOC_LO10
:
2858 case BFD_RELOC_SPARC_H34
:
2863 case BFD_RELOC_SPARC_H44
:
2868 case BFD_RELOC_SPARC_M44
:
2873 case BFD_RELOC_SPARC_L44
:
2877 case BFD_RELOC_SPARC_HIX22
:
2879 val
= (val
>> 10) & 0x3fffff;
2882 case BFD_RELOC_SPARC_LOX10
:
2883 val
= (val
& 0x3ff) | 0x1c00;
2886 the_insn
.exp
= the_insn
.exp2
;
2887 the_insn
.exp
.X_add_number
+= val
;
2888 the_insn
.exp2
.X_op
= O_illegal
;
2889 the_insn
.reloc
= old_reloc
;
2891 else if (the_insn
.exp2
.X_op
!= O_constant
)
2893 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg
);
2894 return special_case
;
2898 if (old_reloc
!= BFD_RELOC_SPARC13
2899 || the_insn
.reloc
!= BFD_RELOC_LO10
2900 || sparc_arch_size
!= 64
2903 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg
);
2904 return special_case
;
2906 the_insn
.reloc
= BFD_RELOC_SPARC_OLO10
;
2910 /* Check for constants that don't require emitting a reloc. */
2911 if (the_insn
.exp
.X_op
== O_constant
2912 && the_insn
.exp
.X_add_symbol
== 0
2913 && the_insn
.exp
.X_op_symbol
== 0)
2915 /* For pc-relative call instructions, we reject
2916 constants to get better code. */
2918 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
2919 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
2921 error_message
= _(": PC-relative operand can't be a constant");
2925 if (the_insn
.reloc
>= BFD_RELOC_SPARC_TLS_GD_HI22
2926 && the_insn
.reloc
<= BFD_RELOC_SPARC_TLS_TPOFF64
)
2928 error_message
= _(": TLS operand can't be a constant");
2932 /* Constants that won't fit are checked in md_apply_fix
2933 and bfd_install_relocation.
2934 ??? It would be preferable to install the constants
2935 into the insn here and save having to create a fixS
2936 for each one. There already exists code to handle
2937 all the various cases (e.g. in md_apply_fix and
2938 bfd_install_relocation) so duplicating all that code
2939 here isn't right. */
2941 /* This is a special case to handle cbcond instructions
2942 properly, which can need two relocations. The first
2943 one is for the 5-bit immediate field and the latter
2944 is going to be for the WDISP10 branch part. We
2945 handle the R_SPARC_5 immediate directly here so that
2946 we don't need to add support for multiple relocations
2947 in one instruction just yet. */
2948 if (the_insn
.reloc
== BFD_RELOC_SPARC_5
)
2950 valueT val
= the_insn
.exp
.X_add_number
;
2952 if (! in_bitfield_range (val
, 0x1f))
2954 error_message
= _(": Immediate value in cbcond is out of range.");
2957 opcode
|= val
& 0x1f;
2958 the_insn
.reloc
= BFD_RELOC_NONE
;
2979 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
2981 error_message
= _(": invalid ASI name");
2987 if (! parse_const_expr_arg (&s
, &asi
))
2989 error_message
= _(": invalid ASI expression");
2992 if (asi
< 0 || asi
> 255)
2994 error_message
= _(": invalid ASI number");
2998 opcode
|= ASI (asi
);
3000 } /* Alternate space. */
3003 if (strncmp (s
, "%psr", 4) == 0)
3010 case 'q': /* Floating point queue. */
3011 if (strncmp (s
, "%fq", 3) == 0)
3018 case 'Q': /* Coprocessor queue. */
3019 if (strncmp (s
, "%cq", 3) == 0)
3027 if (strcmp (str
, "set") == 0
3028 || strcmp (str
, "setuw") == 0)
3030 special_case
= SPECIAL_CASE_SET
;
3033 else if (strcmp (str
, "setsw") == 0)
3035 special_case
= SPECIAL_CASE_SETSW
;
3038 else if (strcmp (str
, "setx") == 0)
3040 special_case
= SPECIAL_CASE_SETX
;
3043 else if (strncmp (str
, "fdiv", 4) == 0)
3045 special_case
= SPECIAL_CASE_FDIV
;
3051 if (strncmp (s
, "%asi", 4) != 0)
3057 if (strncmp (s
, "%fprs", 5) != 0)
3063 if (strncmp (s
, "%mcdper",7) != 0)
3069 if (strncmp (s
, "%ccr", 4) != 0)
3075 if (strncmp (s
, "%tbr", 4) != 0)
3081 if (strncmp (s
, "%wim", 4) != 0)
3088 char *push
= input_line_pointer
;
3091 input_line_pointer
= s
;
3093 if (e
.X_op
== O_constant
)
3095 int n
= e
.X_add_number
;
3096 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
3097 as_bad (_("OPF immediate operand out of range (0-0x1ff)"));
3099 opcode
|= e
.X_add_number
<< 5;
3102 as_bad (_("non-immediate OPF operand, ignored"));
3103 s
= input_line_pointer
;
3104 input_line_pointer
= push
;
3109 if (strncmp (s
, "%y", 2) != 0)
3117 /* Parse a sparclet cpreg. */
3119 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
3121 error_message
= _(": invalid cpreg name");
3124 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
3129 as_fatal (_("failed sanity check."));
3130 } /* switch on arg code. */
3132 /* Break out of for() loop. */
3134 } /* For each arg that we expect. */
3139 /* Args don't match. */
3140 if (&insn
[1] - sparc_opcodes
< sparc_num_opcodes
3141 && (insn
->name
== insn
[1].name
3142 || !strcmp (insn
->name
, insn
[1].name
)))
3150 as_bad (_("Illegal operands%s"), error_message
);
3151 return special_case
;
3156 /* We have a match. Now see if the architecture is OK. */
3157 int needed_arch_mask
= insn
->architecture
;
3159 = (((bfd_uint64_t
) insn
->hwcaps2
) << 32) | insn
->hwcaps
;
3161 #if defined(OBJ_ELF) && !defined(TE_SOLARIS)
3163 hwcap_seen
|= hwcaps
;
3168 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
) - 1);
3169 if (! needed_arch_mask
)
3171 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9
);
3174 if (needed_arch_mask
3175 & SPARC_OPCODE_SUPPORTED (current_architecture
))
3178 /* Can we bump up the architecture? */
3179 else if (needed_arch_mask
3180 & SPARC_OPCODE_SUPPORTED (max_architecture
))
3182 enum sparc_opcode_arch_val needed_architecture
=
3183 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
3184 & needed_arch_mask
);
3186 gas_assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
3188 && needed_architecture
> warn_after_architecture
)
3190 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""),
3191 sparc_opcode_archs
[current_architecture
].name
,
3192 sparc_opcode_archs
[needed_architecture
].name
,
3194 warn_after_architecture
= needed_architecture
;
3196 current_architecture
= needed_architecture
;
3197 hwcap_allowed
|= hwcaps
;
3200 /* ??? This seems to be a bit fragile. What if the next entry in
3201 the opcode table is the one we want and it is supported?
3202 It is possible to arrange the table today so that this can't
3203 happen but what about tomorrow? */
3206 int arch
, printed_one_p
= 0;
3208 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
3210 /* Create a list of the architectures that support the insn. */
3211 needed_arch_mask
&= ~SPARC_OPCODE_SUPPORTED (max_architecture
);
3213 arch
= sparc_ffs (needed_arch_mask
);
3214 while ((1 << arch
) <= needed_arch_mask
)
3216 if ((1 << arch
) & needed_arch_mask
)
3220 strcpy (p
, sparc_opcode_archs
[arch
].name
);
3227 as_bad (_("Architecture mismatch on \"%s\"."), str
);
3228 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
3230 sparc_opcode_archs
[max_architecture
].name
);
3231 return special_case
;
3234 /* Make sure the hwcaps used by the instruction are
3235 currently enabled. */
3236 if (hwcaps
& ~hwcap_allowed
)
3238 const char *hwcap_name
= get_hwcap_name(hwcaps
& ~hwcap_allowed
);
3240 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."),
3242 return special_case
;
3244 } /* If no match. */
3247 } /* Forever looking for a match. */
3249 the_insn
.opcode
= opcode
;
3250 return special_case
;
3253 /* Parse an argument that can be expressed as a keyword.
3254 (eg: #StoreStore or %ccfr).
3255 The result is a boolean indicating success.
3256 If successful, INPUT_POINTER is updated. */
3259 parse_keyword_arg (int (*lookup_fn
) (const char *),
3260 char **input_pointerP
,
3266 p
= *input_pointerP
;
3267 for (q
= p
+ (*p
== '#' || *p
== '%');
3268 ISALNUM (*q
) || *q
== '_';
3273 value
= (*lookup_fn
) (p
);
3278 *input_pointerP
= q
;
3282 /* Parse an argument that is a constant expression.
3283 The result is a boolean indicating success. */
3286 parse_const_expr_arg (char **input_pointerP
, int *valueP
)
3288 char *save
= input_line_pointer
;
3291 input_line_pointer
= *input_pointerP
;
3292 /* The next expression may be something other than a constant
3293 (say if we're not processing the right variant of the insn).
3294 Don't call expression unless we're sure it will succeed as it will
3295 signal an error (which we want to defer until later). */
3296 /* FIXME: It might be better to define md_operand and have it recognize
3297 things like %asi, etc. but continuing that route through to the end
3298 is a lot of work. */
3299 if (*input_line_pointer
== '%')
3301 input_line_pointer
= save
;
3305 *input_pointerP
= input_line_pointer
;
3306 input_line_pointer
= save
;
3307 if (exp
.X_op
!= O_constant
)
3309 *valueP
= exp
.X_add_number
;
3313 /* Subroutine of sparc_ip to parse an expression. */
3316 get_expression (char *str
)
3321 save_in
= input_line_pointer
;
3322 input_line_pointer
= str
;
3323 seg
= expression (&the_insn
.exp
);
3324 if (seg
!= absolute_section
3325 && seg
!= text_section
3326 && seg
!= data_section
3327 && seg
!= bss_section
3328 && seg
!= undefined_section
)
3330 the_insn
.error
= _("bad segment");
3331 expr_end
= input_line_pointer
;
3332 input_line_pointer
= save_in
;
3335 expr_end
= input_line_pointer
;
3336 input_line_pointer
= save_in
;
3340 /* Subroutine of md_assemble to output one insn. */
3343 output_insn (const struct sparc_opcode
*insn
, struct sparc_it
*theinsn
)
3345 char *toP
= frag_more (4);
3347 /* Put out the opcode. */
3348 if (INSN_BIG_ENDIAN
)
3349 number_to_chars_bigendian (toP
, (valueT
) theinsn
->opcode
, 4);
3351 number_to_chars_littleendian (toP
, (valueT
) theinsn
->opcode
, 4);
3353 /* Put out the symbol-dependent stuff. */
3354 if (theinsn
->reloc
!= BFD_RELOC_NONE
)
3356 fixS
*fixP
= fix_new_exp (frag_now
, /* Which frag. */
3357 (toP
- frag_now
->fr_literal
), /* Where. */
3362 /* Turn off overflow checking in fixup_segment. We'll do our
3363 own overflow checking in md_apply_fix. This is necessary because
3364 the insn size is 4 and fixup_segment will signal an overflow for
3365 large 8 byte quantities. */
3366 fixP
->fx_no_overflow
= 1;
3367 if (theinsn
->reloc
== BFD_RELOC_SPARC_OLO10
)
3368 fixP
->tc_fix_data
= theinsn
->exp2
.X_add_number
;
3372 last_opcode
= theinsn
->opcode
;
3375 dwarf2_emit_insn (4);
3380 md_atof (int type
, char *litP
, int *sizeP
)
3382 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
3385 /* Write a value out to the object file, using the appropriate
3389 md_number_to_chars (char *buf
, valueT val
, int n
)
3391 if (target_big_endian
)
3392 number_to_chars_bigendian (buf
, val
, n
);
3393 else if (target_little_endian_data
3394 && ((n
== 4 || n
== 2) && ~now_seg
->flags
& SEC_ALLOC
))
3395 /* Output debug words, which are not in allocated sections, as big
3397 number_to_chars_bigendian (buf
, val
, n
);
3398 else if (target_little_endian_data
|| ! target_big_endian
)
3399 number_to_chars_littleendian (buf
, val
, n
);
3402 /* Apply a fixS to the frags, now that we know the value it ought to
3406 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT segment ATTRIBUTE_UNUSED
)
3408 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3409 offsetT val
= * (offsetT
*) valP
;
3412 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
3414 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
3417 /* SPARC ELF relocations don't use an addend in the data field. */
3418 if (fixP
->fx_addsy
!= NULL
)
3420 switch (fixP
->fx_r_type
)
3422 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3423 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3424 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3425 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3426 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3427 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3428 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3429 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3430 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3431 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3432 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3433 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3434 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3435 case BFD_RELOC_SPARC_TLS_IE_LD
:
3436 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3437 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3438 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3439 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3440 case BFD_RELOC_SPARC_TLS_DTPMOD32
:
3441 case BFD_RELOC_SPARC_TLS_DTPMOD64
:
3442 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3443 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3444 case BFD_RELOC_SPARC_TLS_TPOFF32
:
3445 case BFD_RELOC_SPARC_TLS_TPOFF64
:
3446 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
3456 /* This is a hack. There should be a better way to
3457 handle this. Probably in terms of howto fields, once
3458 we can look at these fixups in terms of howtos. */
3459 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
3460 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3463 /* FIXME: More ridiculous gas reloc hacking. If we are going to
3464 generate a reloc, then we just want to let the reloc addend set
3465 the value. We do not want to also stuff the addend into the
3466 object file. Including the addend in the object file works when
3467 doing a static link, because the linker will ignore the object
3468 file contents. However, the dynamic linker does not ignore the
3469 object file contents. */
3470 if (fixP
->fx_addsy
!= NULL
3471 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
3474 /* When generating PIC code, we do not want an addend for a reloc
3475 against a local symbol. We adjust fx_addnumber to cancel out the
3476 value already included in val, and to also cancel out the
3477 adjustment which bfd_install_relocation will create. */
3479 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
3480 && fixP
->fx_addsy
!= NULL
3481 && ! S_IS_COMMON (fixP
->fx_addsy
)
3482 && symbol_section_p (fixP
->fx_addsy
))
3483 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3485 /* When generating PIC code, we need to fiddle to get
3486 bfd_install_relocation to do the right thing for a PC relative
3487 reloc against a local symbol which we are going to keep. */
3489 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
3490 && fixP
->fx_addsy
!= NULL
3491 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
3492 || S_IS_WEAK (fixP
->fx_addsy
))
3493 && S_IS_DEFINED (fixP
->fx_addsy
)
3494 && ! S_IS_COMMON (fixP
->fx_addsy
))
3497 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
3501 /* If this is a data relocation, just output VAL. */
3503 if (fixP
->fx_r_type
== BFD_RELOC_8
)
3505 md_number_to_chars (buf
, val
, 1);
3507 else if (fixP
->fx_r_type
== BFD_RELOC_16
3508 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA16
)
3510 md_number_to_chars (buf
, val
, 2);
3512 else if (fixP
->fx_r_type
== BFD_RELOC_32
3513 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA32
3514 || fixP
->fx_r_type
== BFD_RELOC_SPARC_REV32
)
3516 md_number_to_chars (buf
, val
, 4);
3518 else if (fixP
->fx_r_type
== BFD_RELOC_64
3519 || fixP
->fx_r_type
== BFD_RELOC_SPARC_UA64
)
3521 md_number_to_chars (buf
, val
, 8);
3523 else if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3524 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3531 /* It's a relocation against an instruction. */
3533 if (INSN_BIG_ENDIAN
)
3534 insn
= bfd_getb32 ((unsigned char *) buf
);
3536 insn
= bfd_getl32 ((unsigned char *) buf
);
3538 switch (fixP
->fx_r_type
)
3540 case BFD_RELOC_32_PCREL_S2
:
3542 /* FIXME: This increment-by-one deserves a comment of why it's
3544 if (! sparc_pic_code
3545 || fixP
->fx_addsy
== NULL
3546 || symbol_section_p (fixP
->fx_addsy
))
3549 insn
|= val
& 0x3fffffff;
3551 /* See if we have a delay slot. */
3552 if (sparc_relax
&& fixP
->fx_where
+ 8 <= fixP
->fx_frag
->fr_fix
)
3556 #define XCC (2 << 20)
3557 #define COND(x) (((x)&0xf)<<25)
3558 #define CONDA COND(0x8)
3559 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC)
3560 #define INSN_BA (F2(0,2) | CONDA)
3561 #define INSN_OR F3(2, 0x2, 0)
3562 #define INSN_NOP F2(0,4)
3566 /* If the instruction is a call with either:
3568 arithmetic instruction with rd == %o7
3569 where rs1 != %o7 and rs2 if it is register != %o7
3570 then we can optimize if the call destination is near
3571 by changing the call into a branch always. */
3572 if (INSN_BIG_ENDIAN
)
3573 delay
= bfd_getb32 ((unsigned char *) buf
+ 4);
3575 delay
= bfd_getl32 ((unsigned char *) buf
+ 4);
3576 if ((insn
& OP (~0)) != OP (1) || (delay
& OP (~0)) != OP (2))
3578 if ((delay
& OP3 (~0)) != OP3 (0x3d) /* Restore. */
3579 && ((delay
& OP3 (0x28)) != 0 /* Arithmetic. */
3580 || ((delay
& RD (~0)) != RD (O7
))))
3582 if ((delay
& RS1 (~0)) == RS1 (O7
)
3583 || ((delay
& F3I (~0)) == 0
3584 && (delay
& RS2 (~0)) == RS2 (O7
)))
3586 /* Ensure the branch will fit into simm22. */
3587 if ((val
& 0x3fe00000)
3588 && (val
& 0x3fe00000) != 0x3fe00000)
3590 /* Check if the arch is v9 and branch will fit
3592 if (((val
& 0x3c0000) == 0
3593 || (val
& 0x3c0000) == 0x3c0000)
3594 && (sparc_arch_size
== 64
3595 || current_architecture
>= SPARC_OPCODE_ARCH_V9
))
3597 insn
= INSN_BPA
| (val
& 0x7ffff);
3600 insn
= INSN_BA
| (val
& 0x3fffff);
3601 if (fixP
->fx_where
>= 4
3602 && ((delay
& (0xffffffff ^ RS1 (~0)))
3603 == (INSN_OR
| RD (O7
) | RS2 (G0
))))
3608 if (INSN_BIG_ENDIAN
)
3609 setter
= bfd_getb32 ((unsigned char *) buf
- 4);
3611 setter
= bfd_getl32 ((unsigned char *) buf
- 4);
3612 if ((setter
& (0xffffffff ^ RD (~0)))
3613 != (INSN_OR
| RS1 (O7
) | RS2 (G0
)))
3620 If call foo was replaced with ba, replace
3621 or %rN, %g0, %o7 with nop. */
3622 reg
= (delay
& RS1 (~0)) >> 14;
3623 if (reg
!= ((setter
& RD (~0)) >> 25)
3624 || reg
== G0
|| reg
== O7
)
3627 if (INSN_BIG_ENDIAN
)
3628 bfd_putb32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3630 bfd_putl32 (INSN_NOP
, (unsigned char *) buf
+ 4);
3635 case BFD_RELOC_SPARC_11
:
3636 if (! in_signed_range (val
, 0x7ff))
3637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3638 _("relocation overflow"));
3639 insn
|= val
& 0x7ff;
3642 case BFD_RELOC_SPARC_10
:
3643 if (! in_signed_range (val
, 0x3ff))
3644 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3645 _("relocation overflow"));
3646 insn
|= val
& 0x3ff;
3649 case BFD_RELOC_SPARC_7
:
3650 if (! in_bitfield_range (val
, 0x7f))
3651 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3652 _("relocation overflow"));
3656 case BFD_RELOC_SPARC_6
:
3657 if (! in_bitfield_range (val
, 0x3f))
3658 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3659 _("relocation overflow"));
3663 case BFD_RELOC_SPARC_5
:
3664 if (! in_bitfield_range (val
, 0x1f))
3665 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3666 _("relocation overflow"));
3670 case BFD_RELOC_SPARC_WDISP10
:
3673 || val
<= -(offsetT
) 0x808)
3674 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3675 _("relocation overflow"));
3676 /* FIXME: The +1 deserves a comment. */
3677 val
= (val
>> 2) + 1;
3678 insn
|= ((val
& 0x300) << 11)
3679 | ((val
& 0xff) << 5);
3682 case BFD_RELOC_SPARC_WDISP16
:
3685 || val
<= -(offsetT
) 0x20008)
3686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3687 _("relocation overflow"));
3688 /* FIXME: The +1 deserves a comment. */
3689 val
= (val
>> 2) + 1;
3690 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
3693 case BFD_RELOC_SPARC_WDISP19
:
3696 || val
<= -(offsetT
) 0x100008)
3697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3698 _("relocation overflow"));
3699 /* FIXME: The +1 deserves a comment. */
3700 val
= (val
>> 2) + 1;
3701 insn
|= val
& 0x7ffff;
3704 case BFD_RELOC_SPARC_HH22
:
3705 val
= BSR (val
, 32);
3708 case BFD_RELOC_SPARC_LM22
:
3709 case BFD_RELOC_HI22
:
3710 if (!fixP
->fx_addsy
)
3711 insn
|= (val
>> 10) & 0x3fffff;
3713 /* FIXME: Need comment explaining why we do this. */
3717 case BFD_RELOC_SPARC22
:
3718 if (val
& ~0x003fffff)
3719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3720 _("relocation overflow"));
3721 insn
|= (val
& 0x3fffff);
3724 case BFD_RELOC_SPARC_HM10
:
3725 val
= BSR (val
, 32);
3728 case BFD_RELOC_LO10
:
3729 if (!fixP
->fx_addsy
)
3730 insn
|= val
& 0x3ff;
3732 /* FIXME: Need comment explaining why we do this. */
3736 case BFD_RELOC_SPARC_OLO10
:
3738 val
+= fixP
->tc_fix_data
;
3741 case BFD_RELOC_SPARC13
:
3742 if (! in_signed_range (val
, 0x1fff))
3743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3744 _("relocation overflow"));
3745 insn
|= val
& 0x1fff;
3748 case BFD_RELOC_SPARC_WDISP22
:
3749 val
= (val
>> 2) + 1;
3751 case BFD_RELOC_SPARC_BASE22
:
3752 insn
|= val
& 0x3fffff;
3755 case BFD_RELOC_SPARC_H34
:
3756 if (!fixP
->fx_addsy
)
3760 insn
|= tval
& 0x3fffff;
3764 case BFD_RELOC_SPARC_H44
:
3765 if (!fixP
->fx_addsy
)
3769 insn
|= tval
& 0x3fffff;
3773 case BFD_RELOC_SPARC_M44
:
3774 if (!fixP
->fx_addsy
)
3775 insn
|= (val
>> 12) & 0x3ff;
3778 case BFD_RELOC_SPARC_L44
:
3779 if (!fixP
->fx_addsy
)
3780 insn
|= val
& 0xfff;
3783 case BFD_RELOC_SPARC_HIX22
:
3784 if (!fixP
->fx_addsy
)
3786 val
^= ~(offsetT
) 0;
3787 insn
|= (val
>> 10) & 0x3fffff;
3791 case BFD_RELOC_SPARC_LOX10
:
3792 if (!fixP
->fx_addsy
)
3793 insn
|= 0x1c00 | (val
& 0x3ff);
3796 case BFD_RELOC_NONE
:
3798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3799 _("bad or unhandled relocation type: 0x%02x"),
3804 if (INSN_BIG_ENDIAN
)
3805 bfd_putb32 (insn
, (unsigned char *) buf
);
3807 bfd_putl32 (insn
, (unsigned char *) buf
);
3810 /* Are we finished with this relocation now? */
3811 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
3815 /* Translate internal representation of relocation info to BFD target
3819 tc_gen_reloc (asection
*section
, fixS
*fixp
)
3821 static arelent
*relocs
[3];
3823 bfd_reloc_code_real_type code
;
3825 relocs
[0] = reloc
= XNEW (arelent
);
3828 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3829 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3830 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3832 switch (fixp
->fx_r_type
)
3836 case BFD_RELOC_HI22
:
3837 case BFD_RELOC_LO10
:
3838 case BFD_RELOC_32_PCREL_S2
:
3839 case BFD_RELOC_SPARC13
:
3840 case BFD_RELOC_SPARC22
:
3841 case BFD_RELOC_SPARC_PC22
:
3842 case BFD_RELOC_SPARC_PC10
:
3843 case BFD_RELOC_SPARC_BASE13
:
3844 case BFD_RELOC_SPARC_WDISP10
:
3845 case BFD_RELOC_SPARC_WDISP16
:
3846 case BFD_RELOC_SPARC_WDISP19
:
3847 case BFD_RELOC_SPARC_WDISP22
:
3849 case BFD_RELOC_SPARC_5
:
3850 case BFD_RELOC_SPARC_6
:
3851 case BFD_RELOC_SPARC_7
:
3852 case BFD_RELOC_SPARC_10
:
3853 case BFD_RELOC_SPARC_11
:
3854 case BFD_RELOC_SPARC_HH22
:
3855 case BFD_RELOC_SPARC_HM10
:
3856 case BFD_RELOC_SPARC_LM22
:
3857 case BFD_RELOC_SPARC_PC_HH22
:
3858 case BFD_RELOC_SPARC_PC_HM10
:
3859 case BFD_RELOC_SPARC_PC_LM22
:
3860 case BFD_RELOC_SPARC_H34
:
3861 case BFD_RELOC_SPARC_H44
:
3862 case BFD_RELOC_SPARC_M44
:
3863 case BFD_RELOC_SPARC_L44
:
3864 case BFD_RELOC_SPARC_HIX22
:
3865 case BFD_RELOC_SPARC_LOX10
:
3866 case BFD_RELOC_SPARC_REV32
:
3867 case BFD_RELOC_SPARC_OLO10
:
3868 case BFD_RELOC_SPARC_UA16
:
3869 case BFD_RELOC_SPARC_UA32
:
3870 case BFD_RELOC_SPARC_UA64
:
3871 case BFD_RELOC_8_PCREL
:
3872 case BFD_RELOC_16_PCREL
:
3873 case BFD_RELOC_32_PCREL
:
3874 case BFD_RELOC_64_PCREL
:
3875 case BFD_RELOC_SPARC_PLT32
:
3876 case BFD_RELOC_SPARC_PLT64
:
3877 case BFD_RELOC_VTABLE_ENTRY
:
3878 case BFD_RELOC_VTABLE_INHERIT
:
3879 case BFD_RELOC_SPARC_TLS_GD_HI22
:
3880 case BFD_RELOC_SPARC_TLS_GD_LO10
:
3881 case BFD_RELOC_SPARC_TLS_GD_ADD
:
3882 case BFD_RELOC_SPARC_TLS_GD_CALL
:
3883 case BFD_RELOC_SPARC_TLS_LDM_HI22
:
3884 case BFD_RELOC_SPARC_TLS_LDM_LO10
:
3885 case BFD_RELOC_SPARC_TLS_LDM_ADD
:
3886 case BFD_RELOC_SPARC_TLS_LDM_CALL
:
3887 case BFD_RELOC_SPARC_TLS_LDO_HIX22
:
3888 case BFD_RELOC_SPARC_TLS_LDO_LOX10
:
3889 case BFD_RELOC_SPARC_TLS_LDO_ADD
:
3890 case BFD_RELOC_SPARC_TLS_IE_HI22
:
3891 case BFD_RELOC_SPARC_TLS_IE_LO10
:
3892 case BFD_RELOC_SPARC_TLS_IE_LD
:
3893 case BFD_RELOC_SPARC_TLS_IE_LDX
:
3894 case BFD_RELOC_SPARC_TLS_IE_ADD
:
3895 case BFD_RELOC_SPARC_TLS_LE_HIX22
:
3896 case BFD_RELOC_SPARC_TLS_LE_LOX10
:
3897 case BFD_RELOC_SPARC_TLS_DTPOFF32
:
3898 case BFD_RELOC_SPARC_TLS_DTPOFF64
:
3899 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22
:
3900 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10
:
3901 case BFD_RELOC_SPARC_GOTDATA_OP
:
3902 code
= fixp
->fx_r_type
;
3909 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
3910 /* If we are generating PIC code, we need to generate a different
3914 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
3916 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
3919 #define GOTT_BASE "__GOTT_BASE__"
3920 #define GOTT_INDEX "__GOTT_INDEX__"
3923 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */
3929 case BFD_RELOC_32_PCREL_S2
:
3930 if (generic_force_reloc (fixp
))
3931 code
= BFD_RELOC_SPARC_WPLT30
;
3933 case BFD_RELOC_HI22
:
3934 code
= BFD_RELOC_SPARC_GOT22
;
3935 if (fixp
->fx_addsy
!= NULL
)
3937 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3938 code
= BFD_RELOC_SPARC_PC22
;
3940 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3941 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3942 code
= BFD_RELOC_HI22
; /* Unchanged. */
3946 case BFD_RELOC_LO10
:
3947 code
= BFD_RELOC_SPARC_GOT10
;
3948 if (fixp
->fx_addsy
!= NULL
)
3950 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
3951 code
= BFD_RELOC_SPARC_PC10
;
3953 if (strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_BASE
) == 0
3954 || strcmp (S_GET_NAME (fixp
->fx_addsy
), GOTT_INDEX
) == 0)
3955 code
= BFD_RELOC_LO10
; /* Unchanged. */
3959 case BFD_RELOC_SPARC13
:
3960 code
= BFD_RELOC_SPARC_GOT13
;
3966 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
3968 /* Nothing is aligned in DWARF debugging sections. */
3969 if (bfd_get_section_flags (stdoutput
, section
) & SEC_DEBUGGING
)
3972 case BFD_RELOC_16
: code
= BFD_RELOC_SPARC_UA16
; break;
3973 case BFD_RELOC_32
: code
= BFD_RELOC_SPARC_UA32
; break;
3974 case BFD_RELOC_64
: code
= BFD_RELOC_SPARC_UA64
; break;
3978 if (code
== BFD_RELOC_SPARC_OLO10
)
3979 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO10
);
3981 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
3982 if (reloc
->howto
== 0)
3984 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3985 _("internal error: can't export reloc type %d (`%s')"),
3986 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
3992 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
3995 if (reloc
->howto
->pc_relative
== 0
3996 || code
== BFD_RELOC_SPARC_PC10
3997 || code
== BFD_RELOC_SPARC_PC22
)
3998 reloc
->addend
= fixp
->fx_addnumber
;
3999 else if (sparc_pic_code
4000 && fixp
->fx_r_type
== BFD_RELOC_32_PCREL_S2
4001 && fixp
->fx_addsy
!= NULL
4002 && (S_IS_EXTERNAL (fixp
->fx_addsy
)
4003 || S_IS_WEAK (fixp
->fx_addsy
))
4004 && S_IS_DEFINED (fixp
->fx_addsy
)
4005 && ! S_IS_COMMON (fixp
->fx_addsy
))
4006 reloc
->addend
= fixp
->fx_addnumber
;
4008 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
4010 #else /* elf or coff */
4012 if (code
!= BFD_RELOC_32_PCREL_S2
4013 && code
!= BFD_RELOC_SPARC_WDISP22
4014 && code
!= BFD_RELOC_SPARC_WDISP16
4015 && code
!= BFD_RELOC_SPARC_WDISP19
4016 && code
!= BFD_RELOC_SPARC_WDISP10
4017 && code
!= BFD_RELOC_SPARC_WPLT30
4018 && code
!= BFD_RELOC_SPARC_TLS_GD_CALL
4019 && code
!= BFD_RELOC_SPARC_TLS_LDM_CALL
)
4020 reloc
->addend
= fixp
->fx_addnumber
;
4021 else if (symbol_section_p (fixp
->fx_addsy
))
4022 reloc
->addend
= (section
->vma
4023 + fixp
->fx_addnumber
4024 + md_pcrel_from (fixp
));
4026 reloc
->addend
= fixp
->fx_offset
;
4029 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13
4030 on the same location. */
4031 if (code
== BFD_RELOC_SPARC_OLO10
)
4033 relocs
[1] = reloc
= XNEW (arelent
);
4036 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
4038 = symbol_get_bfdsym (section_symbol (absolute_section
));
4039 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4040 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_SPARC13
);
4041 reloc
->addend
= fixp
->tc_fix_data
;
4047 /* We have no need to default values of symbols. */
4050 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
4055 /* Round up a section size to the appropriate boundary. */
4058 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
4061 /* This is not right for ELF; a.out wants it, and COFF will force
4062 the alignment anyways. */
4063 valueT align
= ((valueT
) 1
4064 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
4067 /* Turn alignment value into a mask. */
4069 newsize
= (size
+ align
) & ~align
;
4076 /* Exactly what point is a PC-relative offset relative TO?
4077 On the sparc, they're relative to the address of the offset, plus
4078 its size. This gets us to the following instruction.
4079 (??? Is this right? FIXME-SOON) */
4081 md_pcrel_from (fixS
*fixP
)
4085 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4086 if (! sparc_pic_code
4087 || fixP
->fx_addsy
== NULL
4088 || symbol_section_p (fixP
->fx_addsy
))
4089 ret
+= fixP
->fx_size
;
4093 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power
4104 for (shift
= 0; (value
& 1) == 0; value
>>= 1)
4107 return (value
== 1) ? shift
: -1;
4110 /* Sort of like s_lcomm. */
4113 static int max_alignment
= 15;
4117 s_reserve (int ignore ATTRIBUTE_UNUSED
)
4127 c
= get_symbol_name (&name
);
4128 p
= input_line_pointer
;
4130 SKIP_WHITESPACE_AFTER_NAME ();
4132 if (*input_line_pointer
!= ',')
4134 as_bad (_("Expected comma after name"));
4135 ignore_rest_of_line ();
4139 ++input_line_pointer
;
4141 if ((size
= get_absolute_expression ()) < 0)
4143 as_bad (_("BSS length (%d.) <0! Ignored."), size
);
4144 ignore_rest_of_line ();
4149 symbolP
= symbol_find_or_make (name
);
4152 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
4153 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
4155 as_bad (_("bad .reserve segment -- expected BSS segment"));
4159 if (input_line_pointer
[2] == '.')
4160 input_line_pointer
+= 7;
4162 input_line_pointer
+= 6;
4165 if (*input_line_pointer
== ',')
4167 ++input_line_pointer
;
4170 if (*input_line_pointer
== '\n')
4172 as_bad (_("missing alignment"));
4173 ignore_rest_of_line ();
4177 align
= (int) get_absolute_expression ();
4180 if (align
> max_alignment
)
4182 align
= max_alignment
;
4183 as_warn (_("alignment too large; assuming %d"), align
);
4189 as_bad (_("negative alignment"));
4190 ignore_rest_of_line ();
4196 temp
= mylog2 (align
);
4199 as_bad (_("alignment not a power of 2"));
4200 ignore_rest_of_line ();
4207 record_alignment (bss_section
, align
);
4212 if (!S_IS_DEFINED (symbolP
)
4214 && S_GET_OTHER (symbolP
) == 0
4215 && S_GET_DESC (symbolP
) == 0
4222 segT current_seg
= now_seg
;
4223 subsegT current_subseg
= now_subseg
;
4225 /* Switch to bss. */
4226 subseg_set (bss_section
, 1);
4230 frag_align (align
, 0, 0);
4232 /* Detach from old frag. */
4233 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4234 symbol_get_frag (symbolP
)->fr_symbol
= NULL
;
4236 symbol_set_frag (symbolP
, frag_now
);
4237 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4238 (offsetT
) size
, (char *) 0);
4241 S_SET_SEGMENT (symbolP
, bss_section
);
4243 subseg_set (current_seg
, current_subseg
);
4246 S_SET_SIZE (symbolP
, size
);
4252 as_warn (_("Ignoring attempt to re-define symbol %s"),
4253 S_GET_NAME (symbolP
));
4256 demand_empty_rest_of_line ();
4260 s_common (int ignore ATTRIBUTE_UNUSED
)
4268 c
= get_symbol_name (&name
);
4269 /* Just after name is now '\0'. */
4270 p
= input_line_pointer
;
4272 SKIP_WHITESPACE_AFTER_NAME ();
4273 if (*input_line_pointer
!= ',')
4275 as_bad (_("Expected comma after symbol-name"));
4276 ignore_rest_of_line ();
4281 input_line_pointer
++;
4283 if ((temp
= get_absolute_expression ()) < 0)
4285 as_bad (_(".COMMon length (%lu) out of range ignored"),
4286 (unsigned long) temp
);
4287 ignore_rest_of_line ();
4292 symbolP
= symbol_find_or_make (name
);
4294 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
4296 as_bad (_("Ignoring attempt to re-define symbol"));
4297 ignore_rest_of_line ();
4300 if (S_GET_VALUE (symbolP
) != 0)
4302 if (S_GET_VALUE (symbolP
) != (valueT
) size
)
4304 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."),
4305 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), (long) size
);
4311 S_SET_VALUE (symbolP
, (valueT
) size
);
4312 S_SET_EXTERNAL (symbolP
);
4315 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
4316 if (*input_line_pointer
!= ',')
4318 as_bad (_("Expected comma after common length"));
4319 ignore_rest_of_line ();
4322 input_line_pointer
++;
4324 if (*input_line_pointer
!= '"')
4326 temp
= get_absolute_expression ();
4329 if (temp
> max_alignment
)
4331 temp
= max_alignment
;
4332 as_warn (_("alignment too large; assuming %ld"), (long) temp
);
4338 as_bad (_("negative alignment"));
4339 ignore_rest_of_line ();
4344 if (symbol_get_obj (symbolP
)->local
)
4351 old_subsec
= now_subseg
;
4356 align
= mylog2 (temp
);
4360 as_bad (_("alignment not a power of 2"));
4361 ignore_rest_of_line ();
4365 record_alignment (bss_section
, align
);
4366 subseg_set (bss_section
, 0);
4368 frag_align (align
, 0, 0);
4369 if (S_GET_SEGMENT (symbolP
) == bss_section
)
4370 symbol_get_frag (symbolP
)->fr_symbol
= 0;
4371 symbol_set_frag (symbolP
, frag_now
);
4372 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
4373 (offsetT
) size
, (char *) 0);
4375 S_SET_SEGMENT (symbolP
, bss_section
);
4376 S_CLEAR_EXTERNAL (symbolP
);
4377 S_SET_SIZE (symbolP
, size
);
4378 subseg_set (old_sec
, old_subsec
);
4381 #endif /* OBJ_ELF */
4384 S_SET_VALUE (symbolP
, (valueT
) size
);
4386 S_SET_ALIGN (symbolP
, temp
);
4387 S_SET_SIZE (symbolP
, size
);
4389 S_SET_EXTERNAL (symbolP
);
4390 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
4395 input_line_pointer
++;
4396 /* @@ Some use the dot, some don't. Can we get some consistency?? */
4397 if (*input_line_pointer
== '.')
4398 input_line_pointer
++;
4399 /* @@ Some say data, some say bss. */
4400 if (strncmp (input_line_pointer
, "bss\"", 4)
4401 && strncmp (input_line_pointer
, "data\"", 5))
4403 while (*--input_line_pointer
!= '"')
4405 input_line_pointer
--;
4406 goto bad_common_segment
;
4408 while (*input_line_pointer
++ != '"')
4410 goto allocate_common
;
4413 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
4415 demand_empty_rest_of_line ();
4420 p
= input_line_pointer
;
4421 while (*p
&& *p
!= '\n')
4425 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
4427 input_line_pointer
= p
;
4428 ignore_rest_of_line ();
4433 /* Handle the .empty pseudo-op. This suppresses the warnings about
4434 invalid delay slot usage. */
4437 s_empty (int ignore ATTRIBUTE_UNUSED
)
4439 /* The easy way to implement is to just forget about the last
4445 s_seg (int ignore ATTRIBUTE_UNUSED
)
4448 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
4450 input_line_pointer
+= 6;
4454 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
4456 input_line_pointer
+= 6;
4460 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
4462 input_line_pointer
+= 7;
4466 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
4468 input_line_pointer
+= 5;
4469 /* We only support 2 segments -- text and data -- for now, so
4470 things in the "bss segment" will have to go into data for now.
4471 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
4472 subseg_set (data_section
, 255); /* FIXME-SOMEDAY. */
4475 as_bad (_("Unknown segment type"));
4476 demand_empty_rest_of_line ();
4482 subseg_set (data_section
, 1);
4483 demand_empty_rest_of_line ();
4487 s_proc (int ignore ATTRIBUTE_UNUSED
)
4489 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4491 ++input_line_pointer
;
4493 ++input_line_pointer
;
4496 /* This static variable is set by s_uacons to tell sparc_cons_align
4497 that the expression does not need to be aligned. */
4499 static int sparc_no_align_cons
= 0;
4501 /* This handles the unaligned space allocation pseudo-ops, such as
4502 .uaword. .uaword is just like .word, but the value does not need
4506 s_uacons (int bytes
)
4508 /* Tell sparc_cons_align not to align this value. */
4509 sparc_no_align_cons
= 1;
4511 sparc_no_align_cons
= 0;
4514 /* This handles the native word allocation pseudo-op .nword.
4515 For sparc_arch_size 32 it is equivalent to .word, for
4516 sparc_arch_size 64 it is equivalent to .xword. */
4519 s_ncons (int bytes ATTRIBUTE_UNUSED
)
4521 cons (sparc_arch_size
== 32 ? 4 : 8);
4525 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a
4529 .register %g[2367],{#scratch|symbolname|#ignore}
4533 s_register (int ignore ATTRIBUTE_UNUSED
)
4540 if (input_line_pointer
[0] != '%'
4541 || input_line_pointer
[1] != 'g'
4542 || ((input_line_pointer
[2] & ~1) != '2'
4543 && (input_line_pointer
[2] & ~1) != '6')
4544 || input_line_pointer
[3] != ',')
4545 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4546 reg
= input_line_pointer
[2] - '0';
4547 input_line_pointer
+= 4;
4549 if (*input_line_pointer
== '#')
4551 ++input_line_pointer
;
4552 c
= get_symbol_name (®name
);
4553 if (strcmp (regname
, "scratch") && strcmp (regname
, "ignore"))
4554 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
4555 if (regname
[0] == 'i')
4558 regname
= (char *) "";
4562 c
= get_symbol_name (®name
);
4565 if (sparc_arch_size
== 64)
4569 if ((regname
&& globals
[reg
] != (symbolS
*) 1
4570 && strcmp (S_GET_NAME (globals
[reg
]), regname
))
4571 || ((regname
!= NULL
) ^ (globals
[reg
] != (symbolS
*) 1)))
4572 as_bad (_("redefinition of global register"));
4576 if (regname
== NULL
)
4577 globals
[reg
] = (symbolS
*) 1;
4582 if (symbol_find (regname
))
4583 as_bad (_("Register symbol %s already defined."),
4586 globals
[reg
] = symbol_make (regname
);
4587 flags
= symbol_get_bfdsym (globals
[reg
])->flags
;
4589 flags
= flags
& ~(BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
);
4590 if (! (flags
& (BSF_GLOBAL
|BSF_LOCAL
|BSF_WEAK
)))
4591 flags
|= BSF_GLOBAL
;
4592 symbol_get_bfdsym (globals
[reg
])->flags
= flags
;
4593 S_SET_VALUE (globals
[reg
], (valueT
) reg
);
4594 S_SET_ALIGN (globals
[reg
], reg
);
4595 S_SET_SIZE (globals
[reg
], 0);
4596 /* Although we actually want undefined_section here,
4597 we have to use absolute_section, because otherwise
4598 generic as code will make it a COM section.
4599 We fix this up in sparc_adjust_symtab. */
4600 S_SET_SEGMENT (globals
[reg
], absolute_section
);
4601 S_SET_OTHER (globals
[reg
], 0);
4602 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4603 ->internal_elf_sym
.st_info
=
4604 ELF_ST_INFO(STB_GLOBAL
, STT_REGISTER
);
4605 elf_symbol (symbol_get_bfdsym (globals
[reg
]))
4606 ->internal_elf_sym
.st_shndx
= SHN_UNDEF
;
4611 (void) restore_line_pointer (c
);
4613 demand_empty_rest_of_line ();
4616 /* Adjust the symbol table. We set undefined sections for STT_REGISTER
4617 symbols which need it. */
4620 sparc_adjust_symtab (void)
4624 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
4626 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4627 ->internal_elf_sym
.st_info
) != STT_REGISTER
)
4630 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym
))
4631 ->internal_elf_sym
.st_shndx
!= SHN_UNDEF
))
4634 S_SET_SEGMENT (sym
, undefined_section
);
4639 /* If the --enforce-aligned-data option is used, we require .word,
4640 et. al., to be aligned correctly. We do it by setting up an
4641 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
4642 no unexpected alignment was introduced.
4644 The SunOS and Solaris native assemblers enforce aligned data by
4645 default. We don't want to do that, because gcc can deliberately
4646 generate misaligned data if the packed attribute is used. Instead,
4647 we permit misaligned data by default, and permit the user to set an
4648 option to check for it. */
4651 sparc_cons_align (int nbytes
)
4655 /* Only do this if we are enforcing aligned data. */
4656 if (! enforce_aligned_data
)
4659 /* Don't align if this is an unaligned pseudo-op. */
4660 if (sparc_no_align_cons
)
4663 nalign
= mylog2 (nbytes
);
4667 gas_assert (nalign
> 0);
4669 if (now_seg
== absolute_section
)
4671 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
4672 as_bad (_("misaligned data"));
4676 frag_var (rs_align_test
, 1, 1, (relax_substateT
) 0,
4677 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
4679 record_alignment (now_seg
, nalign
);
4682 /* This is called from HANDLE_ALIGN in tc-sparc.h. */
4685 sparc_handle_align (fragS
*fragp
)
4690 count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
4692 switch (fragp
->fr_type
)
4696 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("misaligned data"));
4700 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
4711 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
4713 unsigned wval
= (0x30680000 | count
>> 2); /* ba,a,pt %xcc, 1f */
4714 if (INSN_BIG_ENDIAN
)
4715 number_to_chars_bigendian (p
, wval
, 4);
4717 number_to_chars_littleendian (p
, wval
, 4);
4723 if (INSN_BIG_ENDIAN
)
4724 number_to_chars_bigendian (p
, 0x01000000, 4);
4726 number_to_chars_littleendian (p
, 0x01000000, 4);
4728 fragp
->fr_fix
+= fix
;
4738 /* Some special processing for a Sparc ELF file. */
4741 sparc_elf_final_processing (void)
4743 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
4744 sort of BFD interface for this. */
4745 if (sparc_arch_size
== 64)
4747 switch (sparc_memory_model
)
4750 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
4753 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
4759 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
4760 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
4761 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
4762 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;
4763 else if (current_architecture
== SPARC_OPCODE_ARCH_V9B
)
4764 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
|EF_SPARC_SUN_US3
;
4768 sparc_cons (expressionS
*exp
, int size
)
4771 const char *sparc_cons_special_reloc
= NULL
;
4774 save
= input_line_pointer
;
4775 if (input_line_pointer
[0] == '%'
4776 && input_line_pointer
[1] == 'r'
4777 && input_line_pointer
[2] == '_')
4779 if (strncmp (input_line_pointer
+ 3, "disp", 4) == 0)
4781 input_line_pointer
+= 7;
4782 sparc_cons_special_reloc
= "disp";
4784 else if (strncmp (input_line_pointer
+ 3, "plt", 3) == 0)
4786 if (size
!= 4 && size
!= 8)
4787 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size
);
4790 input_line_pointer
+= 6;
4791 sparc_cons_special_reloc
= "plt";
4794 else if (strncmp (input_line_pointer
+ 3, "tls_dtpoff", 10) == 0)
4796 if (size
!= 4 && size
!= 8)
4797 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size
);
4800 input_line_pointer
+= 13;
4801 sparc_cons_special_reloc
= "tls_dtpoff";
4804 if (sparc_cons_special_reloc
)
4811 if (*input_line_pointer
!= '8')
4813 input_line_pointer
--;
4816 if (input_line_pointer
[0] != '1' || input_line_pointer
[1] != '6')
4820 if (input_line_pointer
[0] != '3' || input_line_pointer
[1] != '2')
4824 if (input_line_pointer
[0] != '6' || input_line_pointer
[1] != '4')
4834 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"),
4835 sparc_cons_special_reloc
, size
* 8, size
);
4839 input_line_pointer
+= 2;
4840 if (*input_line_pointer
!= '(')
4842 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4843 sparc_cons_special_reloc
, size
* 8);
4850 input_line_pointer
= save
;
4851 sparc_cons_special_reloc
= NULL
;
4856 char *end
= ++input_line_pointer
;
4859 while (! is_end_of_line
[(c
= *end
)])
4873 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4874 sparc_cons_special_reloc
, size
* 8);
4880 if (input_line_pointer
!= end
)
4882 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"),
4883 sparc_cons_special_reloc
, size
* 8);
4887 input_line_pointer
++;
4889 c
= *input_line_pointer
;
4890 if (! is_end_of_line
[c
] && c
!= ',')
4891 as_bad (_("Illegal operands: garbage after %%r_%s%d()"),
4892 sparc_cons_special_reloc
, size
* 8);
4898 if (sparc_cons_special_reloc
== NULL
)
4900 return sparc_cons_special_reloc
;
4905 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4906 reloc for a cons. We could use the definition there, except that
4907 we want to handle little endian relocs specially. */
4910 cons_fix_new_sparc (fragS
*frag
,
4912 unsigned int nbytes
,
4914 const char *sparc_cons_special_reloc
)
4916 bfd_reloc_code_real_type r
;
4918 r
= (nbytes
== 1 ? BFD_RELOC_8
:
4919 (nbytes
== 2 ? BFD_RELOC_16
:
4920 (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
4922 if (target_little_endian_data
4924 && now_seg
->flags
& SEC_ALLOC
)
4925 r
= BFD_RELOC_SPARC_REV32
;
4928 /* The Solaris linker does not allow R_SPARC_UA64
4929 relocations for 32-bit executables. */
4930 if (!target_little_endian_data
4931 && sparc_arch_size
!= 64
4932 && r
== BFD_RELOC_64
)
4936 if (sparc_cons_special_reloc
)
4938 if (*sparc_cons_special_reloc
== 'd')
4941 case 1: r
= BFD_RELOC_8_PCREL
; break;
4942 case 2: r
= BFD_RELOC_16_PCREL
; break;
4943 case 4: r
= BFD_RELOC_32_PCREL
; break;
4944 case 8: r
= BFD_RELOC_64_PCREL
; break;
4947 else if (*sparc_cons_special_reloc
== 'p')
4950 case 4: r
= BFD_RELOC_SPARC_PLT32
; break;
4951 case 8: r
= BFD_RELOC_SPARC_PLT64
; break;
4956 case 4: r
= BFD_RELOC_SPARC_TLS_DTPOFF32
; break;
4957 case 8: r
= BFD_RELOC_SPARC_TLS_DTPOFF64
; break;
4960 else if (sparc_no_align_cons
)
4964 case 2: r
= BFD_RELOC_SPARC_UA16
; break;
4965 case 4: r
= BFD_RELOC_SPARC_UA32
; break;
4967 /* The Solaris linker does not allow R_SPARC_UA64
4968 relocations for 32-bit executables. */
4969 case 8: r
= sparc_arch_size
== 64 ?
4970 BFD_RELOC_SPARC_UA64
: BFD_RELOC_SPARC_UA32
; break;
4972 case 8: r
= BFD_RELOC_SPARC_UA64
; break;
4978 fix_new_exp (frag
, where
, (int) nbytes
, exp
, 0, r
);
4982 sparc_cfi_frame_initial_instructions (void)
4984 cfi_add_CFA_def_cfa (14, sparc_arch_size
== 64 ? 0x7ff : 0);
4988 sparc_regname_to_dw2regnum (char *regname
)
4998 case 'g': i
= 0; break;
4999 case 'o': i
= 1; break;
5000 case 'l': i
= 2; break;
5001 case 'i': i
= 3; break;
5002 default: i
= -1; break;
5006 if (regname
[1] < '0' || regname
[1] > '8' || regname
[2])
5008 return i
* 8 + regname
[1] - '0';
5010 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
5012 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
5014 if (regname
[0] == 'f' || regname
[0] == 'r')
5016 unsigned int regnum
;
5018 regnum
= strtoul (regname
+ 1, &q
, 10);
5019 if (q
== NULL
|| *q
)
5021 if (regnum
>= ((regname
[0] == 'f'
5022 && SPARC_OPCODE_ARCH_V9_P (max_architecture
))
5025 if (regname
[0] == 'f')
5028 if (regnum
>= 64 && (regnum
& 1))
5037 sparc_cfi_emit_pcrel_expr (expressionS
*exp
, unsigned int nbytes
)
5039 sparc_no_align_cons
= 1;
5040 emit_expr_with_reloc (exp
, nbytes
, "disp");
5041 sparc_no_align_cons
= 0;