1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 1997 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
29 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
30 static void init_default_arch
PARAMS ((void));
31 static void sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
32 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
33 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
34 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
35 static int sparc_ffs
PARAMS ((unsigned int));
36 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
37 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
38 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
39 static int parse_const_expr_arg
PARAMS ((char **, int *));
40 static int get_expression
PARAMS ((char *str
));
42 /* Default architecture. */
43 /* ??? The default value should be V8, but sparclite support was added
44 by making it the default. GCC now passes -Asparclite, so maybe sometime in
45 the future we can set this to V8. */
47 #define DEFAULT_ARCH "sparclite"
49 static char *default_arch
= DEFAULT_ARCH
;
51 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
53 static int default_init_p
;
55 /* Current architecture. We don't bump up unless necessary. */
56 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
58 /* The maximum architecture level we can bump up to.
59 In a 32 bit environment, don't allow bumping up to v9 by default.
60 The native assembler works this way. The user is required to pass
61 an explicit argument before we'll create v9 object files. However, if
62 we don't see any v9 insns, a v8plus object file is not created. */
63 static enum sparc_opcode_arch_val max_architecture
;
65 /* Either 32 or 64, selects file format. */
66 static int sparc_arch_size
;
68 static int architecture_requested
;
69 static int warn_on_bump
;
71 /* If warn_on_bump and the needed architecture is higher than this
72 architecture, issue a warning. */
73 static enum sparc_opcode_arch_val warn_after_architecture
;
75 /* Non-zero if we are generating PIC code. */
78 /* Non-zero if we should give an error when misaligned data is seen. */
79 static int enforce_aligned_data
;
81 extern int target_big_endian
;
83 /* V9 has big and little endian data, but instructions are always big endian.
84 The sparclet has bi-endian support but both data and insns have the same
85 endianness. Global `target_big_endian' is used for data. The following
86 macro is used for instructions. */
87 #define INSN_BIG_ENDIAN (target_big_endian \
88 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
90 /* handle of the OPCODE hash table */
91 static struct hash_control
*op_hash
;
93 static void s_data1
PARAMS ((void));
94 static void s_seg
PARAMS ((int));
95 static void s_proc
PARAMS ((int));
96 static void s_reserve
PARAMS ((int));
97 static void s_common
PARAMS ((int));
98 static void s_empty
PARAMS ((int));
99 static void s_uacons
PARAMS ((int));
101 const pseudo_typeS md_pseudo_table
[] =
103 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
104 {"common", s_common
, 0},
105 {"empty", s_empty
, 0},
106 {"global", s_globl
, 0},
108 {"optim", s_ignore
, 0},
110 {"reserve", s_reserve
, 0},
112 {"skip", s_space
, 0},
115 {"uahalf", s_uacons
, 2},
116 {"uaword", s_uacons
, 4},
117 {"uaxword", s_uacons
, 8},
119 /* these are specific to sparc/svr4 */
120 {"pushsection", obj_elf_section
, 0},
121 {"popsection", obj_elf_previous
, 0},
122 {"2byte", s_uacons
, 2},
123 {"4byte", s_uacons
, 4},
124 {"8byte", s_uacons
, 8},
129 const int md_reloc_size
= 12; /* Size of relocation record */
131 /* This array holds the chars that always start a comment. If the
132 pre-processor is disabled, these aren't very useful */
133 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
135 /* This array holds the chars that only start a comment at the beginning of
136 a line. If the line seems to have the form '# 123 filename'
137 .line and .file directives will appear in the pre-processed output */
138 /* Note that input_file.c hand checks for '#' at the beginning of the
139 first line of the input file. This is because the compiler outputs
140 #NO_APP at the beginning of its output. */
141 /* Also note that comments started like this one will always
142 work if '/' isn't otherwise defined. */
143 const char line_comment_chars
[] = "#";
145 const char line_separator_chars
[] = "";
147 /* Chars that can be used to separate mant from exp in floating point nums */
148 const char EXP_CHARS
[] = "eE";
150 /* Chars that mean this number is a floating point constant */
153 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
155 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
156 changed in read.c. Ideally it shouldn't have to know about it at all,
157 but nothing is ideal around here. */
159 static unsigned char octal
[256];
160 #define isoctal(c) octal[(unsigned char) (c)]
161 static unsigned char toHex
[256];
166 unsigned long opcode
;
167 struct nlist
*nlistp
;
170 bfd_reloc_code_real_type reloc
;
173 struct sparc_it the_insn
, set_insn
;
175 static void output_insn
176 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
178 /* Table of arguments to -A.
179 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
180 for this use. That table is for opcodes only. This table is for opcodes
183 static struct sparc_arch
{
187 } sparc_arch_table
[] = {
191 { "sparclet", "sparclet", 32 },
192 { "sparclite", "sparclite", 32 },
193 { "v8plus", "v9", 32 },
194 { "v8plusa", "v9a", 32 },
197 { "v9a", "v9a", 64 },
202 static struct sparc_arch
*
206 struct sparc_arch
*sa
;
208 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
209 if (strcmp (sa
->name
, name
) == 0)
211 if (sa
->name
== NULL
)
216 /* Initialize the default opcode arch and word size from the default
217 architecture name. */
222 struct sparc_arch
*sa
= lookup_arch (default_arch
);
225 as_fatal ("Invalid default architecture, broken assembler.");
227 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
228 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
229 as_fatal ("Bad opcode table, broken assembler.");
230 sparc_arch_size
= sa
->arch_size
;
234 /* Called by TARGET_FORMAT. */
237 sparc_target_format ()
239 /* We don't get a chance to initialize anything before we're called,
240 so handle that now. */
241 if (! default_init_p
)
242 init_default_arch ();
246 return "a.out-sparc-netbsd";
249 return target_big_endian
? "a.out-sunos-big" : "a.out-sparc-little";
251 return "a.out-sunos-big";
262 return "coff-sparc-lynx";
269 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
277 * Invocation line includes a switch not recognized by the base assembler.
278 * See if it's a processor-specific option. These are:
281 * Warn on architecture bumps. See also -A.
283 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
284 * Standard 32 bit architectures.
285 * -Av8plus, -Av8plusa
286 * Sparc64 in a 32 bit world.
288 * Sparc64 in a 64 bit world.
289 * -xarch=v8plus, -xarch=v8plusa
290 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
292 * Select the architecture and possibly the file format.
293 * Instructions or features not supported by the selected
294 * architecture cause fatal errors.
296 * The default is to start at v6, and bump the architecture up
297 * whenever an instruction is seen at a higher level. In 32 bit
298 * environments, v9 is not bumped up to, the user must pass
301 * If -bump is specified, a warning is printing when bumping to
304 * If an architecture is specified, all instructions must match
305 * that architecture. Any higher level instructions are flagged
306 * as errors. Note that in the 32 bit environment specifying
307 * -Av8plus does not automatically create a v8plus object file, a
308 * v9 insn must be seen.
310 * If both an architecture and -bump are specified, the
311 * architecture starts at the specified level, but bumps are
312 * warnings. Note that we can't set `current_architecture' to
313 * the requested level in this case: in the 32 bit environment,
314 * we still must avoid creating v8plus object files unless v9
318 * Bumping between incompatible architectures is always an
319 * error. For example, from sparclite to v9.
323 CONST
char *md_shortopts
= "A:K:VQ:sq";
326 CONST
char *md_shortopts
= "A:k";
328 CONST
char *md_shortopts
= "A:";
331 struct option md_longopts
[] = {
332 #define OPTION_BUMP (OPTION_MD_BASE)
333 {"bump", no_argument
, NULL
, OPTION_BUMP
},
334 #define OPTION_SPARC (OPTION_MD_BASE + 1)
335 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
336 #define OPTION_XARCH (OPTION_MD_BASE + 2)
337 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
338 #ifdef SPARC_BIENDIAN
339 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 3)
340 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
341 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 4)
342 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
344 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 5)
345 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
346 {NULL
, no_argument
, NULL
, 0}
348 size_t md_longopts_size
= sizeof(md_longopts
);
351 md_parse_option (c
, arg
)
355 /* We don't get a chance to initialize anything before we're called,
356 so handle that now. */
357 if (! default_init_p
)
358 init_default_arch ();
364 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
368 /* This is for compatibility with Sun's assembler. */
369 if (strcmp (arg
, "v8plus") != 0
370 && strcmp (arg
, "v8plusa") != 0)
372 as_bad ("invalid architecture -xarch=%s", arg
);
380 struct sparc_arch
*sa
;
381 enum sparc_opcode_arch_val opcode_arch
;
383 sa
= lookup_arch (arg
);
386 as_bad ("invalid architecture -A%s", arg
);
390 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
391 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
392 as_fatal ("Bad opcode table, broken assembler.");
394 max_architecture
= opcode_arch
;
395 sparc_arch_size
= sa
->arch_size
;
396 architecture_requested
= 1;
401 /* Ignore -sparc, used by SunOS make default .s.o rule. */
404 case OPTION_ENFORCE_ALIGNED_DATA
:
405 enforce_aligned_data
= 1;
408 #ifdef SPARC_BIENDIAN
409 case OPTION_LITTLE_ENDIAN
:
410 target_big_endian
= 0;
412 case OPTION_BIG_ENDIAN
:
413 target_big_endian
= 1;
429 /* Qy - do emit .comment
430 Qn - do not emit .comment */
434 /* use .stab instead of .stab.excl */
438 /* quick -- native assembler does fewer checks */
442 if (strcmp (arg
, "PIC") != 0)
443 as_warn ("Unrecognized option following -K");
457 md_show_usage (stream
)
460 const struct sparc_arch
*arch
;
462 fprintf(stream
, "SPARC options:\n");
463 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
465 if (arch
!= &sparc_arch_table
[0])
466 fprintf (stream
, " | ");
467 fprintf (stream
, "-A%s", arch
->name
);
469 fprintf (stream
, "\n-xarch=v8plus | -xarch=v8plusa\n");
471 specify variant of SPARC architecture\n\
472 -bump warn when assembler switches architectures\n\
474 --enforce-aligned-data force .long, etc., to be aligned correctly\n");
481 -KPIC generate PIC\n\
482 -V print assembler version number\n\
487 #ifdef SPARC_BIENDIAN
489 -EL generate code for a little endian machine\n\
490 -EB generate code for a big endian machine\n");
494 /* sparc64 priviledged registers */
496 struct priv_reg_entry
502 struct priv_reg_entry priv_reg_table
[] =
521 {"", -1}, /* end marker */
525 cmp_reg_entry (parg
, qarg
)
529 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
530 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
532 return strcmp (q
->name
, p
->name
);
535 /* This function is called once, at assembler startup time. It should
536 set up all the tables, etc. that the MD part of the assembler will need. */
541 register const char *retval
= NULL
;
543 register unsigned int i
= 0;
545 /* We don't get a chance to initialize anything before md_parse_option
546 is called, and it may not be called, so handle default initialization
547 now if not already done. */
548 if (! default_init_p
)
549 init_default_arch ();
551 op_hash
= hash_new ();
553 while (i
< sparc_num_opcodes
)
555 const char *name
= sparc_opcodes
[i
].name
;
556 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
559 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
560 sparc_opcodes
[i
].name
, retval
);
565 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
567 fprintf (stderr
, "internal error: losing opcode: `%s' \"%s\"\n",
568 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
573 while (i
< sparc_num_opcodes
574 && !strcmp (sparc_opcodes
[i
].name
, name
));
578 as_fatal ("Broken assembler. No assembly attempted.");
580 for (i
= '0'; i
< '8'; ++i
)
582 for (i
= '0'; i
<= '9'; ++i
)
584 for (i
= 'a'; i
<= 'f'; ++i
)
585 toHex
[i
] = i
+ 10 - 'a';
586 for (i
= 'A'; i
<= 'F'; ++i
)
587 toHex
[i
] = i
+ 10 - 'A';
589 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
590 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
592 /* If -bump, record the architecture level at which we start issuing
593 warnings. The behaviour is different depending upon whether an
594 architecture was explicitly specified. If it wasn't, we issue warnings
595 for all upwards bumps. If it was, we don't start issuing warnings until
596 we need to bump beyond the requested architecture or when we bump between
597 conflicting architectures. */
600 && architecture_requested
)
602 /* `max_architecture' records the requested architecture.
603 Issue warnings if we go above it. */
604 warn_after_architecture
= max_architecture
;
606 /* Find the highest architecture level that doesn't conflict with
607 the requested one. */
608 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
609 max_architecture
> warn_after_architecture
;
611 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
612 warn_after_architecture
))
617 /* Called after all assembly has been done. */
622 if (sparc_arch_size
== 64)
624 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
625 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
627 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
631 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
632 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
633 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
634 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
635 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
636 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
639 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
640 be but for now it is (since that's the way it's always been
642 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
647 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
650 in_signed_range (val
, max
)
651 bfd_signed_vma val
, max
;
662 /* Return non-zero if VAL is in the range 0 to MAX. */
665 in_unsigned_range (val
, max
)
673 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
674 (e.g. -15 to +31). */
677 in_bitfield_range (val
, max
)
678 bfd_signed_vma val
, max
;
684 if (val
< ~(max
>> 1))
698 for (i
= 0; (mask
& 1) == 0; ++i
)
703 /* Implement big shift right. */
709 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
710 as_fatal ("Support for 64-bit arithmetic not compiled in.");
711 return val
>> amount
;
714 /* For communication between sparc_ip and get_expression. */
715 static char *expr_end
;
717 /* For communication between md_assemble and sparc_ip. */
718 static int special_case
;
720 /* Values for `special_case'.
721 Instructions that require wierd handling because they're longer than
723 #define SPECIAL_CASE_NONE 0
724 #define SPECIAL_CASE_SET 1
725 #define SPECIAL_CASE_SETSW 2
726 #define SPECIAL_CASE_SETX 3
727 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
728 #define SPECIAL_CASE_FDIV 4
730 /* Bit masks of various insns. */
731 #define NOP_INSN 0x01000000
732 #define OR_INSN 0x80100000
733 #define FMOVS_INSN 0x81A00020
734 #define SETHI_INSN 0x01000000
735 #define SLLX_INSN 0x81281000
736 #define SRA_INSN 0x81380000
738 /* The last instruction to be assembled. */
739 static const struct sparc_opcode
*last_insn
;
740 /* The assembled opcode of `last_insn'. */
741 static unsigned long last_opcode
;
743 /* Main entry point to assemble one instruction. */
749 const struct sparc_opcode
*insn
;
752 special_case
= SPECIAL_CASE_NONE
;
753 sparc_ip (str
, &insn
);
755 /* We warn about attempts to put a floating point branch in a delay slot,
756 unless the delay slot has been annulled. */
759 && (insn
->flags
& F_FBR
) != 0
760 && (last_insn
->flags
& F_DELAYED
) != 0
761 /* ??? This test isn't completely accurate. We assume anything with
762 F_{UNBR,CONDBR,FBR} set is annullable. */
763 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
764 || (last_opcode
& ANNUL
) == 0))
765 as_warn ("FP branch in delay slot");
767 /* SPARC before v9 requires a nop instruction between a floating
768 point instruction and a floating point branch. We insert one
769 automatically, with a warning. */
770 if (max_architecture
< SPARC_OPCODE_ARCH_V9
773 && (insn
->flags
& F_FBR
) != 0
774 && (last_insn
->flags
& F_FLOAT
) != 0)
776 struct sparc_it nop_insn
;
778 nop_insn
.opcode
= NOP_INSN
;
779 nop_insn
.reloc
= BFD_RELOC_NONE
;
780 output_insn (insn
, &nop_insn
);
781 as_warn ("FP branch preceded by FP instruction; NOP inserted");
784 switch (special_case
)
786 case SPECIAL_CASE_NONE
:
788 output_insn (insn
, &the_insn
);
791 case SPECIAL_CASE_SET
:
795 /* "set" is not defined for negative numbers in v9: it doesn't yield
796 what you expect it to. */
797 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
)
798 && the_insn
.exp
.X_op
== O_constant
)
800 if (the_insn
.exp
.X_add_number
< 0)
801 as_warn ("set: used with negative number");
802 else if (the_insn
.exp
.X_add_number
> 0xffffffff)
803 as_warn ("set: number larger than 4294967295");
806 /* See if operand is absolute and small; skip sethi if so. */
807 if (the_insn
.exp
.X_op
!= O_constant
808 || the_insn
.exp
.X_add_number
>= (1 << 12)
809 || the_insn
.exp
.X_add_number
< -(1 << 12))
811 output_insn (insn
, &the_insn
);
814 /* See if operand has no low-order bits; skip OR if so. */
815 if (the_insn
.exp
.X_op
!= O_constant
816 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
819 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
820 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
823 | (the_insn
.exp
.X_add_number
824 & (need_hi22_p
? 0x3ff : 0x1fff)));
825 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
828 output_insn (insn
, &the_insn
);
833 case SPECIAL_CASE_SETSW
:
835 /* FIXME: Not finished. */
839 case SPECIAL_CASE_SETX
:
841 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
842 int upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
843 int lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
845 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
846 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
847 /* Output directly to dst reg if lower 32 bits are all zero. */
848 int upper_dstreg
= (the_insn
.exp
.X_op
== O_constant
849 && lower32
== 0) ? dstreg
: tmpreg
;
850 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
852 /* The tmp reg should not be the dst reg. */
853 if (tmpreg
== dstreg
)
854 as_warn ("setx: temporary register same as destination register");
856 /* Reset X_add_number, we've extracted it as upper32/lower32.
857 Otherwise fixup_segment will complain about not being able to
858 write an 8 byte number in a 4 byte field. */
859 the_insn
.exp
.X_add_number
= 0;
861 /* ??? Obviously there are other optimizations we can do
862 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
863 doing some of these. Later. If you do change things, try to
864 change all of this to be table driven as well. */
866 /* What to output depends on the number if it's constant.
867 Compute that first, then output what we've decided upon. */
868 if (the_insn
.exp
.X_op
!= O_constant
)
869 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
872 /* Only need hh22 if `or' insn can't handle constant. */
873 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
876 /* Does bottom part (after sethi) have bits? */
877 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
878 /* No hh22, but does upper32 still have bits we can't set
882 && (upper32
!= -1 || lower32
>= 0)))
885 /* If the lower half is all zero, we build the upper half directly
888 /* Need lower half if number is zero. */
889 || (! need_hh22_p
&& ! need_hm10_p
))
891 /* No need for sethi if `or' insn can handle constant. */
892 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
893 /* Note that we can't use a negative constant in the `or'
894 insn unless the upper 32 bits are all ones. */
895 || (lower32
< 0 && upper32
!= -1))
898 /* Does bottom part (after sethi) have bits? */
899 if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
901 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
902 /* Need `or' if we didn't set anything else. */
903 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
910 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
911 | ((upper32
>> 10) & 0x3fffff));
912 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
913 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
914 output_insn (insn
, &the_insn
);
919 the_insn
.opcode
= (OR_INSN
920 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
924 & (need_hh22_p
? 0x3ff : 0x1fff)));
925 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
926 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
927 output_insn (insn
, &the_insn
);
932 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
933 | ((lower32
>> 10) & 0x3fffff));
934 the_insn
.reloc
= BFD_RELOC_HI22
;
935 output_insn (insn
, &the_insn
);
940 /* FIXME: One nice optimization to do here is to OR the low part
941 with the highpart if hi22 isn't needed and the low part is
943 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
947 & (need_hi22_p
? 0x3ff : 0x1fff)));
948 the_insn
.reloc
= BFD_RELOC_LO10
;
949 output_insn (insn
, &the_insn
);
952 /* If we needed to build the upper part, shift it into place. */
953 if (need_hh22_p
|| need_hm10_p
)
955 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
957 the_insn
.reloc
= BFD_RELOC_NONE
;
958 output_insn (insn
, &the_insn
);
961 /* If we needed to build both upper and lower parts, OR them together. */
962 if ((need_hh22_p
|| need_hm10_p
)
963 && (need_hi22_p
|| need_lo10_p
))
965 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
967 the_insn
.reloc
= BFD_RELOC_NONE
;
968 output_insn (insn
, &the_insn
);
970 /* We didn't need both regs, but we may have to sign extend lower32. */
971 else if (need_hi22_p
&& upper32
== -1)
973 the_insn
.opcode
= (SRA_INSN
| RS1 (dstreg
) | RD (dstreg
)
975 the_insn
.reloc
= BFD_RELOC_NONE
;
976 output_insn (insn
, &the_insn
);
981 case SPECIAL_CASE_FDIV
:
983 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
985 output_insn (insn
, &the_insn
);
987 /* According to information leaked from Sun, the "fdiv" instructions
988 on early SPARC machines would produce incorrect results sometimes.
989 The workaround is to add an fmovs of the destination register to
990 itself just after the instruction. This was true on machines
991 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
992 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
993 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
994 output_insn (insn
, &the_insn
);
999 as_fatal ("failed special case insn sanity check");
1003 /* Subroutine of md_assemble to do the actual parsing. */
1006 sparc_ip (str
, pinsn
)
1008 const struct sparc_opcode
**pinsn
;
1010 char *error_message
= "";
1014 const struct sparc_opcode
*insn
;
1016 unsigned long opcode
;
1017 unsigned int mask
= 0;
1022 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3'); ++s
)
1040 as_fatal ("Unknown opcode: `%s'", str
);
1042 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1046 as_bad ("Unknown opcode: `%s'", str
);
1057 opcode
= insn
->match
;
1058 memset (&the_insn
, '\0', sizeof (the_insn
));
1059 the_insn
.reloc
= BFD_RELOC_NONE
;
1063 * Build the opcode, checking as we go to make
1064 * sure that the operands match
1066 for (args
= insn
->args
;; ++args
)
1074 /* Parse a series of masks. */
1081 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1084 error_message
= ": invalid membar mask name";
1088 while (*s
== ' ') { ++s
; continue; }
1089 if (*s
== '|' || *s
== '+')
1091 while (*s
== ' ') { ++s
; continue; }
1096 if (! parse_const_expr_arg (&s
, &kmask
))
1098 error_message
= ": invalid membar mask expression";
1101 if (kmask
< 0 || kmask
> 127)
1103 error_message
= ": invalid membar mask number";
1108 opcode
|= MEMBAR (kmask
);
1116 /* Parse a prefetch function. */
1119 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1121 error_message
= ": invalid prefetch function name";
1127 if (! parse_const_expr_arg (&s
, &fcn
))
1129 error_message
= ": invalid prefetch function expression";
1132 if (fcn
< 0 || fcn
> 31)
1134 error_message
= ": invalid prefetch function number";
1144 /* Parse a sparc64 privileged register. */
1147 struct priv_reg_entry
*p
= priv_reg_table
;
1148 unsigned int len
= 9999999; /* init to make gcc happy */
1151 while (p
->name
[0] > s
[0])
1153 while (p
->name
[0] == s
[0])
1155 len
= strlen (p
->name
);
1156 if (strncmp (p
->name
, s
, len
) == 0)
1160 if (p
->name
[0] != s
[0])
1162 error_message
= ": unrecognizable privileged register";
1166 opcode
|= (p
->regnum
<< 14);
1168 opcode
|= (p
->regnum
<< 25);
1174 error_message
= ": unrecognizable privileged register";
1180 if (strncmp (s
, "%asr", 4) == 0)
1188 while (isdigit (*s
))
1190 num
= num
* 10 + *s
- '0';
1194 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1196 if (num
< 16 || 31 < num
)
1198 error_message
= ": asr number must be between 16 and 31";
1204 if (num
< 0 || 31 < num
)
1206 error_message
= ": asr number must be between 0 and 31";
1211 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1216 error_message
= ": expecting %asrN";
1223 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1227 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1231 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1232 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1233 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1235 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1236 /* These fields are unsigned, but for upward compatibility,
1237 allow negative values as well. */
1241 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1242 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1243 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1245 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1246 /* These fields are unsigned, but for upward compatibility,
1247 allow negative values as well. */
1251 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1256 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1261 if (*s
== 'p' && s
[1] == 'n')
1269 if (*s
== 'p' && s
[1] == 't')
1281 if (strncmp (s
, "%icc", 4) == 0)
1293 if (strncmp (s
, "%xcc", 4) == 0)
1305 if (strncmp (s
, "%fcc0", 5) == 0)
1317 if (strncmp (s
, "%fcc1", 5) == 0)
1329 if (strncmp (s
, "%fcc2", 5) == 0)
1341 if (strncmp (s
, "%fcc3", 5) == 0)
1349 if (strncmp (s
, "%pc", 3) == 0)
1357 if (strncmp (s
, "%tick", 5) == 0)
1364 case '\0': /* end of args */
1383 case '[': /* these must match exactly */
1391 case '#': /* must be at least one digit */
1394 while (isdigit (*s
))
1402 case 'C': /* coprocessor state register */
1403 if (strncmp (s
, "%csr", 4) == 0)
1410 case 'b': /* next operand is a coprocessor register */
1413 if (*s
++ == '%' && *s
++ == 'c' && isdigit (*s
))
1418 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1432 opcode
|= mask
<< 14;
1440 opcode
|= mask
<< 25;
1446 case 'r': /* next operand must be a register */
1456 case 'f': /* frame pointer */
1464 case 'g': /* global register */
1465 if (isoctal (c
= *s
++))
1472 case 'i': /* in register */
1473 if (isoctal (c
= *s
++))
1475 mask
= c
- '0' + 24;
1480 case 'l': /* local register */
1481 if (isoctal (c
= *s
++))
1483 mask
= (c
- '0' + 16);
1488 case 'o': /* out register */
1489 if (isoctal (c
= *s
++))
1491 mask
= (c
- '0' + 8);
1496 case 's': /* stack pointer */
1504 case 'r': /* any register */
1505 if (!isdigit (c
= *s
++))
1522 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1538 /* Got the register, now figure out where
1539 it goes in the opcode. */
1543 opcode
|= mask
<< 14;
1551 opcode
|= mask
<< 25;
1555 opcode
|= (mask
<< 25) | (mask
<< 14);
1559 opcode
|= (mask
<< 25) | (mask
<< 0);
1565 case 'e': /* next operand is a floating point register */
1580 && ((format
= *s
) == 'f')
1583 for (mask
= 0; isdigit (*s
); ++s
)
1585 mask
= 10 * mask
+ (*s
- '0');
1586 } /* read the number */
1594 } /* register must be even numbered */
1602 } /* register must be multiple of 4 */
1606 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1607 error_message
= ": There are only 64 f registers; [0-63]";
1609 error_message
= ": There are only 32 f registers; [0-31]";
1612 else if (mask
>= 32)
1614 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1617 mask
-= 31; /* wrap high bit */
1621 error_message
= ": There are only 32 f registers; [0-31]";
1629 } /* if not an 'f' register. */
1636 opcode
|= RS1 (mask
);
1643 opcode
|= RS2 (mask
);
1649 opcode
|= RD (mask
);
1658 if (strncmp (s
, "%fsr", 4) == 0)
1665 case '0': /* 64 bit immediate (setx insn) */
1666 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
1669 case 'h': /* high 22 bits */
1670 the_insn
.reloc
= BFD_RELOC_HI22
;
1673 case 'l': /* 22 bit PC relative immediate */
1674 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
1678 case 'L': /* 30 bit immediate */
1679 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
1683 case 'n': /* 22 bit immediate */
1684 the_insn
.reloc
= BFD_RELOC_SPARC22
;
1687 case 'i': /* 13 bit immediate */
1688 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1696 /* Check for %hi, etc. */
1700 /* The name as it appears in assembler. */
1702 /* strlen (name), precomputed for speed */
1704 /* The reloc this pseudo-op translates to. */
1706 /* Non-zero if for v9 only. */
1708 /* Non-zero if can be used in pc-relative contexts. */
1709 int pcrel_p
;/*FIXME:wip*/
1711 /* hix/lox must appear before hi/lo so %hix won't be
1712 mistaken for %hi. */
1713 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
1714 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
1715 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
1716 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
1717 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
1718 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
1719 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
1720 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
1721 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
1722 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
1723 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
1724 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
1729 for (o
= ops
; o
->name
; o
++)
1730 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
1732 if (o
->name
== NULL
)
1735 the_insn
.reloc
= o
->reloc
;
1740 /* Note that if the get_expression() fails, we will still
1741 have created U entries in the symbol table for the
1742 'symbols' in the input string. Try not to create U
1743 symbols for registers, etc. */
1745 /* This stuff checks to see if the expression ends in
1746 +%reg. If it does, it removes the register from
1747 the expression, and re-sets 's' to point to the
1752 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
1754 if (s1
!= s
&& isdigit (s1
[-1]))
1756 if (s1
[-2] == '%' && s1
[-3] == '+')
1760 (void) get_expression (s
);
1765 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
1769 (void) get_expression (s
);
1776 (void) get_expression (s
);
1779 /* Check for constants that don't require emitting a reloc. */
1780 if (the_insn
.exp
.X_op
== O_constant
1781 && the_insn
.exp
.X_add_symbol
== 0
1782 && the_insn
.exp
.X_op_symbol
== 0)
1784 /* For pc-relative call instructions, we reject
1785 constants to get better code. */
1787 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
1788 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
1790 error_message
= ": PC-relative operand can't be a constant";
1794 /* Constants that won't fit are checked in md_apply_fix3
1795 and bfd_install_relocation.
1796 ??? It would be preferable to install the constants
1797 into the insn here and save having to create a fixS
1798 for each one. There already exists code to handle
1799 all the various cases (e.g. in md_apply_fix3 and
1800 bfd_install_relocation) so duplicating all that code
1801 here isn't right. */
1821 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
1823 error_message
= ": invalid ASI name";
1829 if (! parse_const_expr_arg (&s
, &asi
))
1831 error_message
= ": invalid ASI expression";
1834 if (asi
< 0 || asi
> 255)
1836 error_message
= ": invalid ASI number";
1840 opcode
|= ASI (asi
);
1842 } /* alternate space */
1845 if (strncmp (s
, "%psr", 4) == 0)
1852 case 'q': /* floating point queue */
1853 if (strncmp (s
, "%fq", 3) == 0)
1860 case 'Q': /* coprocessor queue */
1861 if (strncmp (s
, "%cq", 3) == 0)
1869 if (strcmp (str
, "set") == 0
1870 || strcmp (str
, "setuw") == 0)
1872 special_case
= SPECIAL_CASE_SET
;
1875 else if (strcmp (str
, "setsw") == 0)
1877 special_case
= SPECIAL_CASE_SETSW
;
1880 else if (strcmp (str
, "setx") == 0)
1882 special_case
= SPECIAL_CASE_SETX
;
1885 else if (strncmp (str
, "fdiv", 4) == 0)
1887 special_case
= SPECIAL_CASE_FDIV
;
1893 if (strncmp (s
, "%asi", 4) != 0)
1899 if (strncmp (s
, "%fprs", 5) != 0)
1905 if (strncmp (s
, "%ccr", 4) != 0)
1911 if (strncmp (s
, "%tbr", 4) != 0)
1917 if (strncmp (s
, "%wim", 4) != 0)
1924 char *push
= input_line_pointer
;
1927 input_line_pointer
= s
;
1929 if (e
.X_op
== O_constant
)
1931 int n
= e
.X_add_number
;
1932 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
1933 as_bad ("OPF immediate operand out of range (0-0x1ff)");
1935 opcode
|= e
.X_add_number
<< 5;
1938 as_bad ("non-immediate OPF operand, ignored");
1939 s
= input_line_pointer
;
1940 input_line_pointer
= push
;
1945 if (strncmp (s
, "%y", 2) != 0)
1953 /* Parse a sparclet cpreg. */
1955 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
1957 error_message
= ": invalid cpreg name";
1960 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
1965 as_fatal ("failed sanity check.");
1966 } /* switch on arg code */
1968 /* Break out of for() loop. */
1970 } /* for each arg that we expect */
1975 /* Args don't match. */
1976 if (((unsigned) (&insn
[1] - sparc_opcodes
)) < sparc_num_opcodes
1977 && (insn
->name
== insn
[1].name
1978 || !strcmp (insn
->name
, insn
[1].name
)))
1986 as_bad ("Illegal operands%s", error_message
);
1992 /* We have a match. Now see if the architecture is ok. */
1993 int needed_arch_mask
= insn
->architecture
;
1997 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
1998 | (1 << SPARC_OPCODE_ARCH_V9A
));
1999 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2002 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
2004 /* Can we bump up the architecture? */
2005 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
2007 enum sparc_opcode_arch_val needed_architecture
=
2008 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2009 & needed_arch_mask
);
2011 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2013 && needed_architecture
> warn_after_architecture
)
2015 as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
2016 sparc_opcode_archs
[current_architecture
].name
,
2017 sparc_opcode_archs
[needed_architecture
].name
,
2019 warn_after_architecture
= needed_architecture
;
2021 current_architecture
= needed_architecture
;
2024 /* ??? This seems to be a bit fragile. What if the next entry in
2025 the opcode table is the one we want and it is supported?
2026 It is possible to arrange the table today so that this can't
2027 happen but what about tomorrow? */
2030 int arch
,printed_one_p
= 0;
2032 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2034 /* Create a list of the architectures that support the insn. */
2035 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
2037 arch
= sparc_ffs (needed_arch_mask
);
2038 while ((1 << arch
) <= needed_arch_mask
)
2040 if ((1 << arch
) & needed_arch_mask
)
2044 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2051 as_bad ("Architecture mismatch on \"%s\".", str
);
2052 as_tsktsk (" (Requires %s; requested architecture is %s.)",
2054 sparc_opcode_archs
[max_architecture
].name
);
2060 } /* forever looking for a match */
2062 the_insn
.opcode
= opcode
;
2065 /* Parse an argument that can be expressed as a keyword.
2066 (eg: #StoreStore or %ccfr).
2067 The result is a boolean indicating success.
2068 If successful, INPUT_POINTER is updated. */
2071 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2072 int (*lookup_fn
) PARAMS ((const char *));
2073 char **input_pointerP
;
2079 p
= *input_pointerP
;
2080 for (q
= p
+ (*p
== '#' || *p
== '%'); isalnum (*q
) || *q
== '_'; ++q
)
2084 value
= (*lookup_fn
) (p
);
2089 *input_pointerP
= q
;
2093 /* Parse an argument that is a constant expression.
2094 The result is a boolean indicating success. */
2097 parse_const_expr_arg (input_pointerP
, valueP
)
2098 char **input_pointerP
;
2101 char *save
= input_line_pointer
;
2104 input_line_pointer
= *input_pointerP
;
2105 /* The next expression may be something other than a constant
2106 (say if we're not processing the right variant of the insn).
2107 Don't call expression unless we're sure it will succeed as it will
2108 signal an error (which we want to defer until later). */
2109 /* FIXME: It might be better to define md_operand and have it recognize
2110 things like %asi, etc. but continuing that route through to the end
2111 is a lot of work. */
2112 if (*input_line_pointer
== '%')
2114 input_line_pointer
= save
;
2118 *input_pointerP
= input_line_pointer
;
2119 input_line_pointer
= save
;
2120 if (exp
.X_op
!= O_constant
)
2122 *valueP
= exp
.X_add_number
;
2126 /* Subroutine of sparc_ip to parse an expression. */
2129 get_expression (str
)
2135 save_in
= input_line_pointer
;
2136 input_line_pointer
= str
;
2137 seg
= expression (&the_insn
.exp
);
2138 if (seg
!= absolute_section
2139 && seg
!= text_section
2140 && seg
!= data_section
2141 && seg
!= bss_section
2142 && seg
!= undefined_section
)
2144 the_insn
.error
= "bad segment";
2145 expr_end
= input_line_pointer
;
2146 input_line_pointer
= save_in
;
2149 expr_end
= input_line_pointer
;
2150 input_line_pointer
= save_in
;
2154 /* Subroutine of md_assemble to output one insn. */
2157 output_insn (insn
, the_insn
)
2158 const struct sparc_opcode
*insn
;
2159 struct sparc_it
*the_insn
;
2161 char *toP
= frag_more (4);
2163 /* put out the opcode */
2164 if (INSN_BIG_ENDIAN
)
2165 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2167 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2169 /* put out the symbol-dependent stuff */
2170 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2172 fixS
*fixP
= fix_new_exp (frag_now
, /* which frag */
2173 (toP
- frag_now
->fr_literal
), /* where */
2178 /* Turn off overflow checking in fixup_segment. We'll do our
2179 own overflow checking in md_apply_fix3. This is necessary because
2180 the insn size is 4 and fixup_segment will signal an overflow for
2181 large 8 byte quantities. */
2182 fixP
->fx_no_overflow
= 1;
2186 last_opcode
= the_insn
->opcode
;
2190 This is identical to the md_atof in m68k.c. I think this is right,
2193 Turn a string in input_line_pointer into a floating point constant of type
2194 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2195 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2198 /* Equal to MAX_PRECISION in atof-ieee.c */
2199 #define MAX_LITTLENUMS 6
2202 md_atof (type
, litP
, sizeP
)
2208 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2239 return "Bad call to MD_ATOF()";
2242 t
= atof_ieee (input_line_pointer
, type
, words
);
2244 input_line_pointer
= t
;
2245 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2247 if (target_big_endian
)
2249 for (i
= 0; i
< prec
; i
++)
2251 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2252 litP
+= sizeof (LITTLENUM_TYPE
);
2257 for (i
= prec
- 1; i
>= 0; i
--)
2259 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2260 litP
+= sizeof (LITTLENUM_TYPE
);
2267 /* Write a value out to the object file, using the appropriate
2271 md_number_to_chars (buf
, val
, n
)
2276 if (target_big_endian
)
2277 number_to_chars_bigendian (buf
, val
, n
);
2279 number_to_chars_littleendian (buf
, val
, n
);
2282 /* Apply a fixS to the frags, now that we know the value it ought to
2286 md_apply_fix3 (fixP
, value
, segment
)
2291 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2297 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2299 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2302 /* FIXME: SPARC ELF relocations don't use an addend in the data
2303 field itself. This whole approach should be somehow combined
2304 with the calls to bfd_install_relocation. Also, the value passed
2305 in by fixup_segment includes the value of a defined symbol. We
2306 don't want to include the value of an externally visible symbol. */
2307 if (fixP
->fx_addsy
!= NULL
)
2309 if (fixP
->fx_addsy
->sy_used_in_reloc
2310 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2311 || S_IS_WEAK (fixP
->fx_addsy
)
2312 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2313 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2314 && ((bfd_get_section_flags (stdoutput
,
2315 S_GET_SEGMENT (fixP
->fx_addsy
))
2316 & SEC_LINK_ONCE
) != 0
2317 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2319 sizeof ".gnu.linkonce" - 1) == 0)))
2320 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2321 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2322 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2323 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2328 /* This is a hack. There should be a better way to
2329 handle this. Probably in terms of howto fields, once
2330 we can look at these fixups in terms of howtos. */
2331 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2332 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2335 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2336 generate a reloc, then we just want to let the reloc addend set
2337 the value. We do not want to also stuff the addend into the
2338 object file. Including the addend in the object file works when
2339 doing a static link, because the linker will ignore the object
2340 file contents. However, the dynamic linker does not ignore the
2341 object file contents. */
2342 if (fixP
->fx_addsy
!= NULL
2343 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2346 /* When generating PIC code, we do not want an addend for a reloc
2347 against a local symbol. We adjust fx_addnumber to cancel out the
2348 value already included in val, and to also cancel out the
2349 adjustment which bfd_install_relocation will create. */
2351 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2352 && fixP
->fx_addsy
!= NULL
2353 && ! S_IS_COMMON (fixP
->fx_addsy
)
2354 && (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
2355 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2358 /* If this is a data relocation, just output VAL. */
2360 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2362 md_number_to_chars (buf
, val
, 2);
2364 else if (fixP
->fx_r_type
== BFD_RELOC_32
)
2366 md_number_to_chars (buf
, val
, 4);
2368 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2370 md_number_to_chars (buf
, val
, 8);
2374 /* It's a relocation against an instruction. */
2376 if (INSN_BIG_ENDIAN
)
2377 insn
= bfd_getb32 ((unsigned char *) buf
);
2379 insn
= bfd_getl32 ((unsigned char *) buf
);
2381 switch (fixP
->fx_r_type
)
2383 case BFD_RELOC_32_PCREL_S2
:
2385 /* FIXME: This increment-by-one deserves a comment of why it's
2387 if (! sparc_pic_code
2388 || fixP
->fx_addsy
== NULL
2389 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2391 insn
|= val
& 0x3fffffff;
2394 case BFD_RELOC_SPARC_11
:
2395 if (! in_signed_range (val
, 0x7ff))
2396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2397 insn
|= val
& 0x7ff;
2400 case BFD_RELOC_SPARC_10
:
2401 if (! in_signed_range (val
, 0x3ff))
2402 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2403 insn
|= val
& 0x3ff;
2406 case BFD_RELOC_SPARC_7
:
2407 if (! in_bitfield_range (val
, 0x7f))
2408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2412 case BFD_RELOC_SPARC_6
:
2413 if (! in_bitfield_range (val
, 0x3f))
2414 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2418 case BFD_RELOC_SPARC_5
:
2419 if (! in_bitfield_range (val
, 0x1f))
2420 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2424 case BFD_RELOC_SPARC_WDISP16
:
2425 /* FIXME: simplify */
2426 if (((val
> 0) && (val
& ~0x3fffc))
2427 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2428 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2429 /* FIXME: The +1 deserves a comment. */
2430 val
= (val
>> 2) + 1;
2431 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2434 case BFD_RELOC_SPARC_WDISP19
:
2435 /* FIXME: simplify */
2436 if (((val
> 0) && (val
& ~0x1ffffc))
2437 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2439 /* FIXME: The +1 deserves a comment. */
2440 val
= (val
>> 2) + 1;
2441 insn
|= val
& 0x7ffff;
2444 case BFD_RELOC_SPARC_HH22
:
2445 val
= BSR (val
, 32);
2446 /* intentional fallthrough */
2448 case BFD_RELOC_SPARC_LM22
:
2449 case BFD_RELOC_HI22
:
2450 /* FIXME: HI22 should signal overflow for 64 bit ABI. */
2451 if (!fixP
->fx_addsy
)
2453 insn
|= (val
>> 10) & 0x3fffff;
2457 /* FIXME: Need comment explaining why we do this. */
2462 case BFD_RELOC_SPARC22
:
2463 if (val
& ~0x003fffff)
2464 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2465 insn
|= (val
& 0x3fffff);
2468 case BFD_RELOC_SPARC_HM10
:
2469 val
= BSR (val
, 32);
2470 /* intentional fallthrough */
2472 case BFD_RELOC_LO10
:
2473 if (!fixP
->fx_addsy
)
2475 insn
|= val
& 0x3ff;
2479 /* FIXME: Need comment explaining why we do this. */
2484 case BFD_RELOC_SPARC13
:
2485 if (! in_signed_range (val
, 0x1fff))
2486 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2487 insn
|= val
& 0x1fff;
2490 case BFD_RELOC_SPARC_WDISP22
:
2491 val
= (val
>> 2) + 1;
2493 case BFD_RELOC_SPARC_BASE22
:
2494 insn
|= val
& 0x3fffff;
2497 case BFD_RELOC_SPARC_H44
:
2498 if (!fixP
->fx_addsy
)
2502 if (! in_unsigned_range (tval
, 0x3fffff))
2503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2504 "relocation overflow");
2505 insn
|= tval
& 0x3fffff;
2509 case BFD_RELOC_SPARC_M44
:
2510 if (!fixP
->fx_addsy
)
2511 insn
|= (val
>> 12) & 0x3ff;
2514 case BFD_RELOC_SPARC_L44
:
2515 if (!fixP
->fx_addsy
)
2516 insn
|= val
& 0xfff;
2519 case BFD_RELOC_SPARC_HIX22
:
2520 if (!fixP
->fx_addsy
)
2522 val
^= ~ (offsetT
) 0;
2523 if ((val
& ~ (offsetT
) 0xffffffff) != 0)
2524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2525 "relocation overflow");
2526 insn
|= (val
>> 10) & 0x3fffff;
2530 case BFD_RELOC_SPARC_LOX10
:
2531 if (!fixP
->fx_addsy
)
2532 insn
|= 0x1c00 | (val
& 0x3ff);
2535 case BFD_RELOC_NONE
:
2537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2538 "bad or unhandled relocation type: 0x%02x",
2543 if (INSN_BIG_ENDIAN
)
2544 bfd_putb32 (insn
, (unsigned char *) buf
);
2546 bfd_putl32 (insn
, (unsigned char *) buf
);
2549 /* Are we finished with this relocation now? */
2550 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
2556 /* Translate internal representation of relocation info to BFD target
2559 tc_gen_reloc (section
, fixp
)
2564 bfd_reloc_code_real_type code
;
2566 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2568 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
2569 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2571 switch (fixp
->fx_r_type
)
2575 case BFD_RELOC_HI22
:
2576 case BFD_RELOC_LO10
:
2577 case BFD_RELOC_32_PCREL_S2
:
2578 case BFD_RELOC_SPARC13
:
2579 case BFD_RELOC_SPARC_BASE13
:
2580 case BFD_RELOC_SPARC_WDISP16
:
2581 case BFD_RELOC_SPARC_WDISP19
:
2582 case BFD_RELOC_SPARC_WDISP22
:
2584 case BFD_RELOC_SPARC_5
:
2585 case BFD_RELOC_SPARC_6
:
2586 case BFD_RELOC_SPARC_7
:
2587 case BFD_RELOC_SPARC_10
:
2588 case BFD_RELOC_SPARC_11
:
2589 case BFD_RELOC_SPARC_HH22
:
2590 case BFD_RELOC_SPARC_HM10
:
2591 case BFD_RELOC_SPARC_LM22
:
2592 case BFD_RELOC_SPARC_PC_HH22
:
2593 case BFD_RELOC_SPARC_PC_HM10
:
2594 case BFD_RELOC_SPARC_PC_LM22
:
2595 case BFD_RELOC_SPARC_H44
:
2596 case BFD_RELOC_SPARC_M44
:
2597 case BFD_RELOC_SPARC_L44
:
2598 case BFD_RELOC_SPARC_HIX22
:
2599 case BFD_RELOC_SPARC_LOX10
:
2600 code
= fixp
->fx_r_type
;
2606 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2607 /* If we are generating PIC code, we need to generate a different
2611 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2613 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2620 case BFD_RELOC_32_PCREL_S2
:
2621 if (! S_IS_DEFINED (fixp
->fx_addsy
)
2622 || S_IS_COMMON (fixp
->fx_addsy
)
2623 || S_IS_EXTERNAL (fixp
->fx_addsy
)
2624 || S_IS_WEAK (fixp
->fx_addsy
))
2625 code
= BFD_RELOC_SPARC_WPLT30
;
2627 case BFD_RELOC_HI22
:
2628 if (fixp
->fx_addsy
!= NULL
2629 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2630 code
= BFD_RELOC_SPARC_PC22
;
2632 code
= BFD_RELOC_SPARC_GOT22
;
2634 case BFD_RELOC_LO10
:
2635 if (fixp
->fx_addsy
!= NULL
2636 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2637 code
= BFD_RELOC_SPARC_PC10
;
2639 code
= BFD_RELOC_SPARC_GOT10
;
2641 case BFD_RELOC_SPARC13
:
2642 code
= BFD_RELOC_SPARC_GOT13
;
2648 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2650 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2651 if (reloc
->howto
== 0)
2653 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2654 "internal error: can't export reloc type %d (`%s')",
2655 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
2659 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2662 if (reloc
->howto
->pc_relative
== 0
2663 || code
== BFD_RELOC_SPARC_PC10
2664 || code
== BFD_RELOC_SPARC_PC22
)
2665 reloc
->addend
= fixp
->fx_addnumber
;
2667 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
2669 #else /* elf or coff */
2671 if (reloc
->howto
->pc_relative
== 0
2672 || code
== BFD_RELOC_SPARC_PC10
2673 || code
== BFD_RELOC_SPARC_PC22
)
2674 reloc
->addend
= fixp
->fx_addnumber
;
2675 else if ((fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2676 reloc
->addend
= (section
->vma
2677 + fixp
->fx_addnumber
2678 + md_pcrel_from (fixp
));
2680 reloc
->addend
= fixp
->fx_offset
;
2686 /* We have no need to default values of symbols. */
2690 md_undefined_symbol (name
)
2694 } /* md_undefined_symbol() */
2696 /* Round up a section size to the appropriate boundary. */
2698 md_section_align (segment
, size
)
2703 /* This is not right for ELF; a.out wants it, and COFF will force
2704 the alignment anyways. */
2705 valueT align
= ((valueT
) 1
2706 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
2708 /* turn alignment value into a mask */
2710 newsize
= (size
+ align
) & ~align
;
2717 /* Exactly what point is a PC-relative offset relative TO?
2718 On the sparc, they're relative to the address of the offset, plus
2719 its size. This gets us to the following instruction.
2720 (??? Is this right? FIXME-SOON) */
2722 md_pcrel_from (fixP
)
2727 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2728 if (! sparc_pic_code
2729 || fixP
->fx_addsy
== NULL
2730 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2731 ret
+= fixP
->fx_size
;
2736 * sort of like s_lcomm
2740 static int max_alignment
= 15;
2755 name
= input_line_pointer
;
2756 c
= get_symbol_end ();
2757 p
= input_line_pointer
;
2761 if (*input_line_pointer
!= ',')
2763 as_bad ("Expected comma after name");
2764 ignore_rest_of_line ();
2768 ++input_line_pointer
;
2770 if ((size
= get_absolute_expression ()) < 0)
2772 as_bad ("BSS length (%d.) <0! Ignored.", size
);
2773 ignore_rest_of_line ();
2778 symbolP
= symbol_find_or_make (name
);
2781 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
2782 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
2784 as_bad ("bad .reserve segment -- expected BSS segment");
2788 if (input_line_pointer
[2] == '.')
2789 input_line_pointer
+= 7;
2791 input_line_pointer
+= 6;
2794 if (*input_line_pointer
== ',')
2796 ++input_line_pointer
;
2799 if (*input_line_pointer
== '\n')
2801 as_bad ("Missing alignment");
2805 align
= get_absolute_expression ();
2807 if (align
> max_alignment
)
2809 align
= max_alignment
;
2810 as_warn ("Alignment too large: %d. assumed.", align
);
2816 as_warn ("Alignment negative. 0 assumed.");
2819 record_alignment (bss_section
, align
);
2821 /* convert to a power of 2 alignment */
2822 for (temp
= 0; (align
& 1) == 0; align
>>= 1, ++temp
);;
2826 as_bad ("Alignment not a power of 2");
2827 ignore_rest_of_line ();
2829 } /* not a power of two */
2832 } /* if has optional alignment */
2836 if (!S_IS_DEFINED (symbolP
)
2838 && S_GET_OTHER (symbolP
) == 0
2839 && S_GET_DESC (symbolP
) == 0
2846 segT current_seg
= now_seg
;
2847 subsegT current_subseg
= now_subseg
;
2849 subseg_set (bss_section
, 1); /* switch to bss */
2852 frag_align (align
, 0, 0); /* do alignment */
2854 /* detach from old frag */
2855 if (S_GET_SEGMENT(symbolP
) == bss_section
)
2856 symbolP
->sy_frag
->fr_symbol
= NULL
;
2858 symbolP
->sy_frag
= frag_now
;
2859 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
2860 (offsetT
) size
, (char *)0);
2863 S_SET_SEGMENT (symbolP
, bss_section
);
2865 subseg_set (current_seg
, current_subseg
);
2870 as_warn("Ignoring attempt to re-define symbol %s",
2871 S_GET_NAME (symbolP
));
2872 } /* if not redefining */
2874 demand_empty_rest_of_line ();
2887 name
= input_line_pointer
;
2888 c
= get_symbol_end ();
2889 /* just after name is now '\0' */
2890 p
= input_line_pointer
;
2893 if (*input_line_pointer
!= ',')
2895 as_bad ("Expected comma after symbol-name");
2896 ignore_rest_of_line ();
2899 input_line_pointer
++; /* skip ',' */
2900 if ((temp
= get_absolute_expression ()) < 0)
2902 as_bad (".COMMon length (%d.) <0! Ignored.", temp
);
2903 ignore_rest_of_line ();
2908 symbolP
= symbol_find_or_make (name
);
2910 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
2912 as_bad ("Ignoring attempt to re-define symbol");
2913 ignore_rest_of_line ();
2916 if (S_GET_VALUE (symbolP
) != 0)
2918 if (S_GET_VALUE (symbolP
) != size
)
2920 as_warn ("Length of .comm \"%s\" is already %ld. Not changed to %d.",
2921 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
2927 S_SET_VALUE (symbolP
, (valueT
) size
);
2928 S_SET_EXTERNAL (symbolP
);
2931 know (symbolP
->sy_frag
== &zero_address_frag
);
2932 if (*input_line_pointer
!= ',')
2934 as_bad ("Expected comma after common length");
2935 ignore_rest_of_line ();
2938 input_line_pointer
++;
2940 if (*input_line_pointer
!= '"')
2942 temp
= get_absolute_expression ();
2944 if (temp
> max_alignment
)
2946 temp
= max_alignment
;
2947 as_warn ("Common alignment too large: %d. assumed", temp
);
2953 as_warn ("Common alignment negative; 0 assumed");
2964 old_subsec
= now_subseg
;
2966 record_alignment (bss_section
, align
);
2967 subseg_set (bss_section
, 0);
2969 frag_align (align
, 0, 0);
2970 if (S_GET_SEGMENT (symbolP
) == bss_section
)
2971 symbolP
->sy_frag
->fr_symbol
= 0;
2972 symbolP
->sy_frag
= frag_now
;
2973 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
2974 (offsetT
) size
, (char *) 0);
2976 S_SET_SEGMENT (symbolP
, bss_section
);
2977 S_CLEAR_EXTERNAL (symbolP
);
2978 subseg_set (old_sec
, old_subsec
);
2984 S_SET_VALUE (symbolP
, (valueT
) size
);
2986 S_SET_ALIGN (symbolP
, temp
);
2988 S_SET_EXTERNAL (symbolP
);
2989 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
2994 input_line_pointer
++;
2995 /* @@ Some use the dot, some don't. Can we get some consistency?? */
2996 if (*input_line_pointer
== '.')
2997 input_line_pointer
++;
2998 /* @@ Some say data, some say bss. */
2999 if (strncmp (input_line_pointer
, "bss\"", 4)
3000 && strncmp (input_line_pointer
, "data\"", 5))
3002 while (*--input_line_pointer
!= '"')
3004 input_line_pointer
--;
3005 goto bad_common_segment
;
3007 while (*input_line_pointer
++ != '"')
3009 goto allocate_common
;
3012 #ifdef BFD_ASSEMBLER
3013 symbolP
->bsym
->flags
|= BSF_OBJECT
;
3016 demand_empty_rest_of_line ();
3021 p
= input_line_pointer
;
3022 while (*p
&& *p
!= '\n')
3026 as_bad ("bad .common segment %s", input_line_pointer
+ 1);
3028 input_line_pointer
= p
;
3029 ignore_rest_of_line ();
3034 /* Handle the .empty pseudo-op. This supresses the warnings about
3035 invalid delay slot usage. */
3041 /* The easy way to implement is to just forget about the last
3051 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3053 input_line_pointer
+= 6;
3057 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3059 input_line_pointer
+= 6;
3063 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3065 input_line_pointer
+= 7;
3069 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3071 input_line_pointer
+= 5;
3072 /* We only support 2 segments -- text and data -- for now, so
3073 things in the "bss segment" will have to go into data for now.
3074 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3075 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
3078 as_bad ("Unknown segment type");
3079 demand_empty_rest_of_line ();
3085 subseg_set (data_section
, 1);
3086 demand_empty_rest_of_line ();
3093 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3095 ++input_line_pointer
;
3097 ++input_line_pointer
;
3100 /* This static variable is set by s_uacons to tell sparc_cons_align
3101 that the expession does not need to be aligned. */
3103 static int sparc_no_align_cons
= 0;
3105 /* This handles the unaligned space allocation pseudo-ops, such as
3106 .uaword. .uaword is just like .word, but the value does not need
3113 /* Tell sparc_cons_align not to align this value. */
3114 sparc_no_align_cons
= 1;
3118 /* If the --enforce-aligned-data option is used, we require .word,
3119 et. al., to be aligned correctly. We do it by setting up an
3120 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3121 no unexpected alignment was introduced.
3123 The SunOS and Solaris native assemblers enforce aligned data by
3124 default. We don't want to do that, because gcc can deliberately
3125 generate misaligned data if the packed attribute is used. Instead,
3126 we permit misaligned data by default, and permit the user to set an
3127 option to check for it. */
3130 sparc_cons_align (nbytes
)
3136 /* Only do this if we are enforcing aligned data. */
3137 if (! enforce_aligned_data
)
3140 if (sparc_no_align_cons
)
3142 /* This is an unaligned pseudo-op. */
3143 sparc_no_align_cons
= 0;
3148 while ((nbytes
& 1) == 0)
3157 if (now_seg
== absolute_section
)
3159 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
3160 as_bad ("misaligned data");
3164 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
3165 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
3167 record_alignment (now_seg
, nalign
);
3170 /* This is where we do the unexpected alignment check.
3171 This is called from HANDLE_ALIGN in tc-sparc.h. */
3174 sparc_handle_align (fragp
)
3177 if (fragp
->fr_type
== rs_align_code
3178 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
3179 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "misaligned data");