1 /* tc-sparc.c -- Assemble for the SPARC
2 Copyright (C) 1989, 90-96, 1997 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public
17 License along with GAS; see the file COPYING. If not, write
18 to the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
27 #include "opcode/sparc.h"
29 #include "elf/sparc.h"
31 static struct sparc_arch
*lookup_arch
PARAMS ((char *));
32 static void init_default_arch
PARAMS ((void));
33 static void sparc_ip
PARAMS ((char *, const struct sparc_opcode
**));
34 static int in_signed_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
35 static int in_unsigned_range
PARAMS ((bfd_vma
, bfd_vma
));
36 static int in_bitfield_range
PARAMS ((bfd_signed_vma
, bfd_signed_vma
));
37 static int sparc_ffs
PARAMS ((unsigned int));
38 static bfd_vma BSR
PARAMS ((bfd_vma
, int));
39 static int cmp_reg_entry
PARAMS ((const PTR
, const PTR
));
40 static int parse_keyword_arg
PARAMS ((int (*) (const char *), char **, int *));
41 static int parse_const_expr_arg
PARAMS ((char **, int *));
42 static int get_expression
PARAMS ((char *str
));
44 /* Default architecture. */
45 /* ??? The default value should be V8, but sparclite support was added
46 by making it the default. GCC now passes -Asparclite, so maybe sometime in
47 the future we can set this to V8. */
49 #define DEFAULT_ARCH "sparclite"
51 static char *default_arch
= DEFAULT_ARCH
;
53 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size'
55 static int default_init_p
;
57 /* Current architecture. We don't bump up unless necessary. */
58 static enum sparc_opcode_arch_val current_architecture
= SPARC_OPCODE_ARCH_V6
;
60 /* The maximum architecture level we can bump up to.
61 In a 32 bit environment, don't allow bumping up to v9 by default.
62 The native assembler works this way. The user is required to pass
63 an explicit argument before we'll create v9 object files. However, if
64 we don't see any v9 insns, a v8plus object file is not created. */
65 static enum sparc_opcode_arch_val max_architecture
;
67 /* Either 32 or 64, selects file format. */
68 static int sparc_arch_size
;
69 static enum { MM_TSO
, MM_PSO
, MM_RMO
} sparc_memory_model
= MM_RMO
;
70 /* Initial (default) value, recorded separately in case a user option
71 changes the value before md_show_usage is called. */
72 static int default_arch_size
;
74 static int architecture_requested
;
75 static int warn_on_bump
;
77 /* If warn_on_bump and the needed architecture is higher than this
78 architecture, issue a warning. */
79 static enum sparc_opcode_arch_val warn_after_architecture
;
81 /* Non-zero if we are generating PIC code. */
84 /* Non-zero if we should give an error when misaligned data is seen. */
85 static int enforce_aligned_data
;
87 extern int target_big_endian
;
89 /* V9 has big and little endian data, but instructions are always big endian.
90 The sparclet has bi-endian support but both data and insns have the same
91 endianness. Global `target_big_endian' is used for data. The following
92 macro is used for instructions. */
93 #define INSN_BIG_ENDIAN (target_big_endian \
94 || SPARC_OPCODE_ARCH_V9_P (max_architecture))
96 /* handle of the OPCODE hash table */
97 static struct hash_control
*op_hash
;
99 static void s_data1
PARAMS ((void));
100 static void s_seg
PARAMS ((int));
101 static void s_proc
PARAMS ((int));
102 static void s_reserve
PARAMS ((int));
103 static void s_common
PARAMS ((int));
104 static void s_empty
PARAMS ((int));
105 static void s_uacons
PARAMS ((int));
107 const pseudo_typeS md_pseudo_table
[] =
109 {"align", s_align_bytes
, 0}, /* Defaulting is invalid (0) */
110 {"common", s_common
, 0},
111 {"empty", s_empty
, 0},
112 {"global", s_globl
, 0},
114 {"optim", s_ignore
, 0},
116 {"reserve", s_reserve
, 0},
118 {"skip", s_space
, 0},
121 {"uahalf", s_uacons
, 2},
122 {"uaword", s_uacons
, 4},
123 {"uaxword", s_uacons
, 8},
125 /* these are specific to sparc/svr4 */
126 {"pushsection", obj_elf_section
, 0},
127 {"popsection", obj_elf_previous
, 0},
128 {"2byte", s_uacons
, 2},
129 {"4byte", s_uacons
, 4},
130 {"8byte", s_uacons
, 8},
135 const int md_reloc_size
= 12; /* Size of relocation record */
137 /* This array holds the chars that always start a comment. If the
138 pre-processor is disabled, these aren't very useful */
139 const char comment_chars
[] = "!"; /* JF removed '|' from comment_chars */
141 /* This array holds the chars that only start a comment at the beginning of
142 a line. If the line seems to have the form '# 123 filename'
143 .line and .file directives will appear in the pre-processed output */
144 /* Note that input_file.c hand checks for '#' at the beginning of the
145 first line of the input file. This is because the compiler outputs
146 #NO_APP at the beginning of its output. */
147 /* Also note that comments started like this one will always
148 work if '/' isn't otherwise defined. */
149 const char line_comment_chars
[] = "#";
151 const char line_separator_chars
[] = "";
153 /* Chars that can be used to separate mant from exp in floating point nums */
154 const char EXP_CHARS
[] = "eE";
156 /* Chars that mean this number is a floating point constant */
159 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
161 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
162 changed in read.c. Ideally it shouldn't have to know about it at all,
163 but nothing is ideal around here. */
165 static unsigned char octal
[256];
166 #define isoctal(c) octal[(unsigned char) (c)]
167 static unsigned char toHex
[256];
172 unsigned long opcode
;
173 struct nlist
*nlistp
;
176 bfd_reloc_code_real_type reloc
;
179 struct sparc_it the_insn
, set_insn
;
181 static void output_insn
182 PARAMS ((const struct sparc_opcode
*, struct sparc_it
*));
184 /* Table of arguments to -A.
185 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect
186 for this use. That table is for opcodes only. This table is for opcodes
189 static struct sparc_arch
{
192 /* Default word size, as specified during configuration.
193 A value of zero means can't be used to specify default architecture. */
194 int default_arch_size
;
195 /* Allowable arg to -A? */
197 } sparc_arch_table
[] = {
198 { "v6", "v6", 0, 1 },
199 { "v7", "v7", 0, 1 },
200 { "v8", "v8", 32, 1 },
201 { "sparclet", "sparclet", 32, 1 },
202 { "sparclite", "sparclite", 32, 1 },
203 { "v8plus", "v9", 0, 1 },
204 { "v8plusa", "v9a", 0, 1 },
205 { "v9", "v9", 0, 1 },
206 { "v9a", "v9a", 0, 1 },
207 /* This exists to allow configure.in/Makefile.in to pass one
208 value to specify both the default machine and default word size. */
209 { "v9-64", "v9", 64, 0 },
213 static struct sparc_arch
*
217 struct sparc_arch
*sa
;
219 for (sa
= &sparc_arch_table
[0]; sa
->name
!= NULL
; sa
++)
220 if (strcmp (sa
->name
, name
) == 0)
222 if (sa
->name
== NULL
)
227 /* Initialize the default opcode arch and word size from the default
228 architecture name. */
233 struct sparc_arch
*sa
= lookup_arch (default_arch
);
236 || sa
->default_arch_size
== 0)
237 as_fatal ("Invalid default architecture, broken assembler.");
239 max_architecture
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
240 if (max_architecture
== SPARC_OPCODE_ARCH_BAD
)
241 as_fatal ("Bad opcode table, broken assembler.");
242 default_arch_size
= sparc_arch_size
= sa
->default_arch_size
;
246 /* Called by TARGET_FORMAT. */
249 sparc_target_format ()
251 /* We don't get a chance to initialize anything before we're called,
252 so handle that now. */
253 if (! default_init_p
)
254 init_default_arch ();
258 return "a.out-sparc-netbsd";
261 return target_big_endian
? "a.out-sunos-big" : "a.out-sparc-little";
263 return "a.out-sunos-big";
274 return "coff-sparc-lynx";
281 return sparc_arch_size
== 64 ? "elf64-sparc" : "elf32-sparc";
289 * Invocation line includes a switch not recognized by the base assembler.
290 * See if it's a processor-specific option. These are:
293 * Warn on architecture bumps. See also -A.
295 * -Av6, -Av7, -Av8, -Asparclite, -Asparclet
296 * Standard 32 bit architectures.
297 * -Av8plus, -Av8plusa
298 * Sparc64 in a 32 bit world.
300 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which).
301 * This used to only mean 64 bits, but properly specifying it
302 * complicated gcc's ASM_SPECs, so now opcode selection is
303 * specified orthogonally to word size (except when specifying
304 * the default, but that is an internal implementation detail).
305 * -xarch=v8plus, -xarch=v8plusa
306 * Same as -Av8plus{,a}, for compatibility with Sun's assembler.
308 * Select the architecture and possibly the file format.
309 * Instructions or features not supported by the selected
310 * architecture cause fatal errors.
312 * The default is to start at v6, and bump the architecture up
313 * whenever an instruction is seen at a higher level. In 32 bit
314 * environments, v9 is not bumped up to, the user must pass
317 * If -bump is specified, a warning is printing when bumping to
320 * If an architecture is specified, all instructions must match
321 * that architecture. Any higher level instructions are flagged
322 * as errors. Note that in the 32 bit environment specifying
323 * -Av8plus does not automatically create a v8plus object file, a
324 * v9 insn must be seen.
326 * If both an architecture and -bump are specified, the
327 * architecture starts at the specified level, but bumps are
328 * warnings. Note that we can't set `current_architecture' to
329 * the requested level in this case: in the 32 bit environment,
330 * we still must avoid creating v8plus object files unless v9
334 * Bumping between incompatible architectures is always an
335 * error. For example, from sparclite to v9.
339 CONST
char *md_shortopts
= "A:K:VQ:sq";
342 CONST
char *md_shortopts
= "A:k";
344 CONST
char *md_shortopts
= "A:";
347 struct option md_longopts
[] = {
348 #define OPTION_BUMP (OPTION_MD_BASE)
349 {"bump", no_argument
, NULL
, OPTION_BUMP
},
350 #define OPTION_SPARC (OPTION_MD_BASE + 1)
351 {"sparc", no_argument
, NULL
, OPTION_SPARC
},
352 #define OPTION_XARCH (OPTION_MD_BASE + 2)
353 {"xarch", required_argument
, NULL
, OPTION_XARCH
},
355 #define OPTION_32 (OPTION_MD_BASE + 3)
356 {"32", no_argument
, NULL
, OPTION_32
},
357 #define OPTION_64 (OPTION_MD_BASE + 4)
358 {"64", no_argument
, NULL
, OPTION_64
},
359 #define OPTION_TSO (OPTION_MD_BASE + 5)
360 {"TSO", no_argument
, NULL
, OPTION_TSO
},
361 #define OPTION_PSO (OPTION_MD_BASE + 6)
362 {"PSO", no_argument
, NULL
, OPTION_PSO
},
363 #define OPTION_RMO (OPTION_MD_BASE + 7)
364 {"RMO", no_argument
, NULL
, OPTION_RMO
},
366 #ifdef SPARC_BIENDIAN
367 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8)
368 {"EL", no_argument
, NULL
, OPTION_LITTLE_ENDIAN
},
369 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9)
370 {"EB", no_argument
, NULL
, OPTION_BIG_ENDIAN
},
372 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10)
373 {"enforce-aligned-data", no_argument
, NULL
, OPTION_ENFORCE_ALIGNED_DATA
},
374 {NULL
, no_argument
, NULL
, 0}
376 size_t md_longopts_size
= sizeof(md_longopts
);
379 md_parse_option (c
, arg
)
383 /* We don't get a chance to initialize anything before we're called,
384 so handle that now. */
385 if (! default_init_p
)
386 init_default_arch ();
392 warn_after_architecture
= SPARC_OPCODE_ARCH_V6
;
396 /* This is for compatibility with Sun's assembler. */
397 if (strcmp (arg
, "v8plus") != 0
398 && strcmp (arg
, "v8plusa") != 0)
400 as_bad ("invalid architecture -xarch=%s", arg
);
408 struct sparc_arch
*sa
;
409 enum sparc_opcode_arch_val opcode_arch
;
411 sa
= lookup_arch (arg
);
413 || ! sa
->user_option_p
)
415 as_bad ("invalid architecture -A%s", arg
);
419 opcode_arch
= sparc_opcode_lookup_arch (sa
->opcode_arch
);
420 if (opcode_arch
== SPARC_OPCODE_ARCH_BAD
)
421 as_fatal ("Bad opcode table, broken assembler.");
423 max_architecture
= opcode_arch
;
424 architecture_requested
= 1;
429 /* Ignore -sparc, used by SunOS make default .s.o rule. */
432 case OPTION_ENFORCE_ALIGNED_DATA
:
433 enforce_aligned_data
= 1;
436 #ifdef SPARC_BIENDIAN
437 case OPTION_LITTLE_ENDIAN
:
438 target_big_endian
= 0;
440 case OPTION_BIG_ENDIAN
:
441 target_big_endian
= 1;
455 const char **list
, **l
;
457 sparc_arch_size
= c
== OPTION_32
? 32 : 64;
458 list
= bfd_target_list ();
459 for (l
= list
; *l
!= NULL
; l
++)
461 if (sparc_arch_size
== 32)
463 if (strcmp (*l
, "elf32-sparc") == 0)
468 if (strcmp (*l
, "elf64-sparc") == 0)
473 as_fatal ("No compiled in support for %d bit object file format",
480 sparc_memory_model
= MM_TSO
;
484 sparc_memory_model
= MM_PSO
;
488 sparc_memory_model
= MM_RMO
;
496 /* Qy - do emit .comment
497 Qn - do not emit .comment */
501 /* use .stab instead of .stab.excl */
505 /* quick -- native assembler does fewer checks */
509 if (strcmp (arg
, "PIC") != 0)
510 as_warn ("Unrecognized option following -K");
524 md_show_usage (stream
)
527 const struct sparc_arch
*arch
;
529 /* We don't get a chance to initialize anything before we're called,
530 so handle that now. */
531 if (! default_init_p
)
532 init_default_arch ();
534 fprintf(stream
, "SPARC options:\n");
535 for (arch
= &sparc_arch_table
[0]; arch
->name
; arch
++)
537 if (arch
!= &sparc_arch_table
[0])
538 fprintf (stream
, " | ");
539 if (arch
->user_option_p
)
540 fprintf (stream
, "-A%s", arch
->name
);
542 fprintf (stream
, "\n-xarch=v8plus | -xarch=v8plusa\n");
544 specify variant of SPARC architecture\n\
545 -bump warn when assembler switches architectures\n\
547 --enforce-aligned-data force .long, etc., to be aligned correctly\n");
554 -32 create 32 bit object file\n\
555 -64 create 64 bit object file\n");
557 [default is %d]\n", default_arch_size
);
559 -TSO use Total Store Ordering\n\
560 -PSO use Partial Store Ordering\n\
561 -RMO use Relaxed Memory Ordering\n");
563 [default is %s]\n", (default_arch_size
== 64) ? "RMO" : "TSO");
565 -KPIC generate PIC\n\
566 -V print assembler version number\n\
571 #ifdef SPARC_BIENDIAN
573 -EL generate code for a little endian machine\n\
574 -EB generate code for a big endian machine\n");
578 /* sparc64 priviledged registers */
580 struct priv_reg_entry
586 struct priv_reg_entry priv_reg_table
[] =
605 {"", -1}, /* end marker */
608 /* v9a specific asrs */
610 struct priv_reg_entry v9a_asr_table
[] =
619 {"clear_softint", 21},
620 {"", -1}, /* end marker */
624 cmp_reg_entry (parg
, qarg
)
628 const struct priv_reg_entry
*p
= (const struct priv_reg_entry
*) parg
;
629 const struct priv_reg_entry
*q
= (const struct priv_reg_entry
*) qarg
;
631 return strcmp (q
->name
, p
->name
);
634 /* This function is called once, at assembler startup time. It should
635 set up all the tables, etc. that the MD part of the assembler will need. */
640 register const char *retval
= NULL
;
642 register unsigned int i
= 0;
644 /* We don't get a chance to initialize anything before md_parse_option
645 is called, and it may not be called, so handle default initialization
646 now if not already done. */
647 if (! default_init_p
)
648 init_default_arch ();
650 op_hash
= hash_new ();
652 while (i
< sparc_num_opcodes
)
654 const char *name
= sparc_opcodes
[i
].name
;
655 retval
= hash_insert (op_hash
, name
, (PTR
) &sparc_opcodes
[i
]);
658 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
659 sparc_opcodes
[i
].name
, retval
);
664 if (sparc_opcodes
[i
].match
& sparc_opcodes
[i
].lose
)
666 fprintf (stderr
, "internal error: losing opcode: `%s' \"%s\"\n",
667 sparc_opcodes
[i
].name
, sparc_opcodes
[i
].args
);
672 while (i
< sparc_num_opcodes
673 && !strcmp (sparc_opcodes
[i
].name
, name
));
677 as_fatal ("Broken assembler. No assembly attempted.");
679 for (i
= '0'; i
< '8'; ++i
)
681 for (i
= '0'; i
<= '9'; ++i
)
683 for (i
= 'a'; i
<= 'f'; ++i
)
684 toHex
[i
] = i
+ 10 - 'a';
685 for (i
= 'A'; i
<= 'F'; ++i
)
686 toHex
[i
] = i
+ 10 - 'A';
688 qsort (priv_reg_table
, sizeof (priv_reg_table
) / sizeof (priv_reg_table
[0]),
689 sizeof (priv_reg_table
[0]), cmp_reg_entry
);
691 /* If -bump, record the architecture level at which we start issuing
692 warnings. The behaviour is different depending upon whether an
693 architecture was explicitly specified. If it wasn't, we issue warnings
694 for all upwards bumps. If it was, we don't start issuing warnings until
695 we need to bump beyond the requested architecture or when we bump between
696 conflicting architectures. */
699 && architecture_requested
)
701 /* `max_architecture' records the requested architecture.
702 Issue warnings if we go above it. */
703 warn_after_architecture
= max_architecture
;
705 /* Find the highest architecture level that doesn't conflict with
706 the requested one. */
707 for (max_architecture
= SPARC_OPCODE_ARCH_MAX
;
708 max_architecture
> warn_after_architecture
;
710 if (! SPARC_OPCODE_CONFLICT_P (max_architecture
,
711 warn_after_architecture
))
716 /* Called after all assembly has been done. */
721 if (sparc_arch_size
== 64)
723 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
724 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9a
);
726 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v9
);
730 if (current_architecture
== SPARC_OPCODE_ARCH_V9
)
731 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plus
);
732 else if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
733 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_v8plusa
);
734 else if (current_architecture
== SPARC_OPCODE_ARCH_SPARCLET
)
735 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc_sparclet
);
738 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't
739 be but for now it is (since that's the way it's always been
741 bfd_set_arch_mach (stdoutput
, bfd_arch_sparc
, bfd_mach_sparc
);
746 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */
749 in_signed_range (val
, max
)
750 bfd_signed_vma val
, max
;
761 /* Return non-zero if VAL is in the range 0 to MAX. */
764 in_unsigned_range (val
, max
)
772 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX.
773 (e.g. -15 to +31). */
776 in_bitfield_range (val
, max
)
777 bfd_signed_vma val
, max
;
783 if (val
< ~(max
>> 1))
797 for (i
= 0; (mask
& 1) == 0; ++i
)
802 /* Implement big shift right. */
808 if (sizeof (bfd_vma
) <= 4 && amount
>= 32)
809 as_fatal ("Support for 64-bit arithmetic not compiled in.");
810 return val
>> amount
;
813 /* For communication between sparc_ip and get_expression. */
814 static char *expr_end
;
816 /* For communication between md_assemble and sparc_ip. */
817 static int special_case
;
819 /* Values for `special_case'.
820 Instructions that require wierd handling because they're longer than
822 #define SPECIAL_CASE_NONE 0
823 #define SPECIAL_CASE_SET 1
824 #define SPECIAL_CASE_SETSW 2
825 #define SPECIAL_CASE_SETX 3
826 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */
827 #define SPECIAL_CASE_FDIV 4
829 /* Bit masks of various insns. */
830 #define NOP_INSN 0x01000000
831 #define OR_INSN 0x80100000
832 #define FMOVS_INSN 0x81A00020
833 #define SETHI_INSN 0x01000000
834 #define SLLX_INSN 0x81281000
835 #define SRA_INSN 0x81380000
837 /* The last instruction to be assembled. */
838 static const struct sparc_opcode
*last_insn
;
839 /* The assembled opcode of `last_insn'. */
840 static unsigned long last_opcode
;
842 /* Main entry point to assemble one instruction. */
848 const struct sparc_opcode
*insn
;
851 special_case
= SPECIAL_CASE_NONE
;
852 sparc_ip (str
, &insn
);
854 /* We warn about attempts to put a floating point branch in a delay slot,
855 unless the delay slot has been annulled. */
858 && (insn
->flags
& F_FBR
) != 0
859 && (last_insn
->flags
& F_DELAYED
) != 0
860 /* ??? This test isn't completely accurate. We assume anything with
861 F_{UNBR,CONDBR,FBR} set is annullable. */
862 && ((last_insn
->flags
& (F_UNBR
| F_CONDBR
| F_FBR
)) == 0
863 || (last_opcode
& ANNUL
) == 0))
864 as_warn ("FP branch in delay slot");
866 /* SPARC before v9 requires a nop instruction between a floating
867 point instruction and a floating point branch. We insert one
868 automatically, with a warning. */
869 if (max_architecture
< SPARC_OPCODE_ARCH_V9
872 && (insn
->flags
& F_FBR
) != 0
873 && (last_insn
->flags
& F_FLOAT
) != 0)
875 struct sparc_it nop_insn
;
877 nop_insn
.opcode
= NOP_INSN
;
878 nop_insn
.reloc
= BFD_RELOC_NONE
;
879 output_insn (insn
, &nop_insn
);
880 as_warn ("FP branch preceded by FP instruction; NOP inserted");
883 switch (special_case
)
885 case SPECIAL_CASE_NONE
:
887 output_insn (insn
, &the_insn
);
890 case SPECIAL_CASE_SET
:
894 /* "set" is not defined for negative numbers in v9: it doesn't yield
895 what you expect it to. */
896 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
)
897 && the_insn
.exp
.X_op
== O_constant
)
899 if (the_insn
.exp
.X_add_number
< 0)
900 as_warn ("set: used with negative number");
901 else if (the_insn
.exp
.X_add_number
> 0xffffffff)
902 as_warn ("set: number larger than 4294967295");
905 /* See if operand is absolute and small; skip sethi if so. */
906 if (the_insn
.exp
.X_op
!= O_constant
907 || the_insn
.exp
.X_add_number
>= (1 << 12)
908 || the_insn
.exp
.X_add_number
< -(1 << 12))
910 output_insn (insn
, &the_insn
);
913 /* See if operand has no low-order bits; skip OR if so. */
914 if (the_insn
.exp
.X_op
!= O_constant
915 || (need_hi22_p
&& (the_insn
.exp
.X_add_number
& 0x3FF) != 0)
918 int rd
= (the_insn
.opcode
& RD (~0)) >> 25;
919 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (rd
) : 0)
922 | (the_insn
.exp
.X_add_number
923 & (need_hi22_p
? 0x3ff : 0x1fff)));
924 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
927 output_insn (insn
, &the_insn
);
932 case SPECIAL_CASE_SETSW
:
934 /* FIXME: Not finished. */
938 case SPECIAL_CASE_SETX
:
940 #define SIGNEXT32(x) ((((x) & 0xffffffff) ^ 0x80000000) - 0x80000000)
941 int upper32
= SIGNEXT32 (BSR (the_insn
.exp
.X_add_number
, 32));
942 int lower32
= SIGNEXT32 (the_insn
.exp
.X_add_number
);
944 int tmpreg
= (the_insn
.opcode
& RS1 (~0)) >> 14;
945 int dstreg
= (the_insn
.opcode
& RD (~0)) >> 25;
946 /* Output directly to dst reg if lower 32 bits are all zero. */
947 int upper_dstreg
= (the_insn
.exp
.X_op
== O_constant
948 && lower32
== 0) ? dstreg
: tmpreg
;
949 int need_hh22_p
= 0, need_hm10_p
= 0, need_hi22_p
= 0, need_lo10_p
= 0;
951 /* The tmp reg should not be the dst reg. */
952 if (tmpreg
== dstreg
)
953 as_warn ("setx: temporary register same as destination register");
955 /* Reset X_add_number, we've extracted it as upper32/lower32.
956 Otherwise fixup_segment will complain about not being able to
957 write an 8 byte number in a 4 byte field. */
958 the_insn
.exp
.X_add_number
= 0;
960 /* ??? Obviously there are other optimizations we can do
961 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be
962 doing some of these. Later. If you do change things, try to
963 change all of this to be table driven as well. */
965 /* What to output depends on the number if it's constant.
966 Compute that first, then output what we've decided upon. */
967 if (the_insn
.exp
.X_op
!= O_constant
)
968 need_hh22_p
= need_hm10_p
= need_hi22_p
= need_lo10_p
= 1;
971 /* Only need hh22 if `or' insn can't handle constant. */
972 if (upper32
< -(1 << 12) || upper32
>= (1 << 12))
975 /* Does bottom part (after sethi) have bits? */
976 if ((need_hh22_p
&& (upper32
& 0x3ff) != 0)
977 /* No hh22, but does upper32 still have bits we can't set
981 && (upper32
!= -1 || lower32
>= 0)))
984 /* If the lower half is all zero, we build the upper half directly
987 /* Need lower half if number is zero. */
988 || (! need_hh22_p
&& ! need_hm10_p
))
990 /* No need for sethi if `or' insn can handle constant. */
991 if (lower32
< -(1 << 12) || lower32
>= (1 << 12)
992 /* Note that we can't use a negative constant in the `or'
993 insn unless the upper 32 bits are all ones. */
994 || (lower32
< 0 && upper32
!= -1))
997 /* Does bottom part (after sethi) have bits? */
998 if ((need_hi22_p
&& (lower32
& 0x3ff) != 0)
1000 || (! need_hi22_p
&& (lower32
& 0x1fff) != 0)
1001 /* Need `or' if we didn't set anything else. */
1002 || (! need_hi22_p
&& ! need_hh22_p
&& ! need_hm10_p
))
1009 the_insn
.opcode
= (SETHI_INSN
| RD (upper_dstreg
)
1010 | ((upper32
>> 10) & 0x3fffff));
1011 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1012 ? BFD_RELOC_SPARC_HH22
: BFD_RELOC_NONE
);
1013 output_insn (insn
, &the_insn
);
1018 the_insn
.opcode
= (OR_INSN
1019 | (need_hh22_p
? RS1 (upper_dstreg
) : 0)
1023 & (need_hh22_p
? 0x3ff : 0x1fff)));
1024 the_insn
.reloc
= (the_insn
.exp
.X_op
!= O_constant
1025 ? BFD_RELOC_SPARC_HM10
: BFD_RELOC_NONE
);
1026 output_insn (insn
, &the_insn
);
1031 the_insn
.opcode
= (SETHI_INSN
| RD (dstreg
)
1032 | ((lower32
>> 10) & 0x3fffff));
1033 the_insn
.reloc
= BFD_RELOC_HI22
;
1034 output_insn (insn
, &the_insn
);
1039 /* FIXME: One nice optimization to do here is to OR the low part
1040 with the highpart if hi22 isn't needed and the low part is
1042 the_insn
.opcode
= (OR_INSN
| (need_hi22_p
? RS1 (dstreg
) : 0)
1046 & (need_hi22_p
? 0x3ff : 0x1fff)));
1047 the_insn
.reloc
= BFD_RELOC_LO10
;
1048 output_insn (insn
, &the_insn
);
1051 /* If we needed to build the upper part, shift it into place. */
1052 if (need_hh22_p
|| need_hm10_p
)
1054 the_insn
.opcode
= (SLLX_INSN
| RS1 (upper_dstreg
) | RD (upper_dstreg
)
1056 the_insn
.reloc
= BFD_RELOC_NONE
;
1057 output_insn (insn
, &the_insn
);
1060 /* If we needed to build both upper and lower parts, OR them together. */
1061 if ((need_hh22_p
|| need_hm10_p
)
1062 && (need_hi22_p
|| need_lo10_p
))
1064 the_insn
.opcode
= (OR_INSN
| RS1 (dstreg
) | RS2 (upper_dstreg
)
1066 the_insn
.reloc
= BFD_RELOC_NONE
;
1067 output_insn (insn
, &the_insn
);
1069 /* We didn't need both regs, but we may have to sign extend lower32. */
1070 else if (need_hi22_p
&& upper32
== -1)
1072 the_insn
.opcode
= (SRA_INSN
| RS1 (dstreg
) | RD (dstreg
)
1074 the_insn
.reloc
= BFD_RELOC_NONE
;
1075 output_insn (insn
, &the_insn
);
1080 case SPECIAL_CASE_FDIV
:
1082 int rd
= (the_insn
.opcode
>> 25) & 0x1f;
1084 output_insn (insn
, &the_insn
);
1086 /* According to information leaked from Sun, the "fdiv" instructions
1087 on early SPARC machines would produce incorrect results sometimes.
1088 The workaround is to add an fmovs of the destination register to
1089 itself just after the instruction. This was true on machines
1090 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */
1091 assert (the_insn
.reloc
== BFD_RELOC_NONE
);
1092 the_insn
.opcode
= FMOVS_INSN
| rd
| RD (rd
);
1093 output_insn (insn
, &the_insn
);
1098 as_fatal ("failed special case insn sanity check");
1102 /* Subroutine of md_assemble to do the actual parsing. */
1105 sparc_ip (str
, pinsn
)
1107 const struct sparc_opcode
**pinsn
;
1109 char *error_message
= "";
1113 const struct sparc_opcode
*insn
;
1115 unsigned long opcode
;
1116 unsigned int mask
= 0;
1121 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3'); ++s
)
1139 as_fatal ("Unknown opcode: `%s'", str
);
1141 insn
= (struct sparc_opcode
*) hash_find (op_hash
, str
);
1145 as_bad ("Unknown opcode: `%s'", str
);
1156 opcode
= insn
->match
;
1157 memset (&the_insn
, '\0', sizeof (the_insn
));
1158 the_insn
.reloc
= BFD_RELOC_NONE
;
1162 * Build the opcode, checking as we go to make
1163 * sure that the operands match
1165 for (args
= insn
->args
;; ++args
)
1173 /* Parse a series of masks. */
1180 if (! parse_keyword_arg (sparc_encode_membar
, &s
,
1183 error_message
= ": invalid membar mask name";
1187 while (*s
== ' ') { ++s
; continue; }
1188 if (*s
== '|' || *s
== '+')
1190 while (*s
== ' ') { ++s
; continue; }
1195 if (! parse_const_expr_arg (&s
, &kmask
))
1197 error_message
= ": invalid membar mask expression";
1200 if (kmask
< 0 || kmask
> 127)
1202 error_message
= ": invalid membar mask number";
1207 opcode
|= MEMBAR (kmask
);
1215 /* Parse a prefetch function. */
1218 if (! parse_keyword_arg (sparc_encode_prefetch
, &s
, &fcn
))
1220 error_message
= ": invalid prefetch function name";
1226 if (! parse_const_expr_arg (&s
, &fcn
))
1228 error_message
= ": invalid prefetch function expression";
1231 if (fcn
< 0 || fcn
> 31)
1233 error_message
= ": invalid prefetch function number";
1243 /* Parse a sparc64 privileged register. */
1246 struct priv_reg_entry
*p
= priv_reg_table
;
1247 unsigned int len
= 9999999; /* init to make gcc happy */
1250 while (p
->name
[0] > s
[0])
1252 while (p
->name
[0] == s
[0])
1254 len
= strlen (p
->name
);
1255 if (strncmp (p
->name
, s
, len
) == 0)
1259 if (p
->name
[0] != s
[0])
1261 error_message
= ": unrecognizable privileged register";
1265 opcode
|= (p
->regnum
<< 14);
1267 opcode
|= (p
->regnum
<< 25);
1273 error_message
= ": unrecognizable privileged register";
1279 /* Parse a v9a ancillary state register. */
1282 struct priv_reg_entry
*p
= v9a_asr_table
;
1283 unsigned int len
= 9999999; /* init to make gcc happy */
1286 while (p
->name
[0] > s
[0])
1288 while (p
->name
[0] == s
[0])
1290 len
= strlen (p
->name
);
1291 if (strncmp (p
->name
, s
, len
) == 0)
1295 if (p
->name
[0] != s
[0])
1297 error_message
= ": unrecognizable v9a ancillary state register";
1300 if (*args
== '/' && (p
->regnum
== 20 || p
->regnum
== 21))
1302 error_message
= ": rd on write only ancillary state register";
1306 opcode
|= (p
->regnum
<< 14);
1308 opcode
|= (p
->regnum
<< 25);
1314 error_message
= ": unrecognizable v9a ancillary state register";
1320 if (strncmp (s
, "%asr", 4) == 0)
1328 while (isdigit (*s
))
1330 num
= num
* 10 + *s
- '0';
1334 if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
1336 if (num
< 16 || 31 < num
)
1338 error_message
= ": asr number must be between 16 and 31";
1344 if (num
< 0 || 31 < num
)
1346 error_message
= ": asr number must be between 0 and 31";
1351 opcode
|= (*args
== 'M' ? RS1 (num
) : RD (num
));
1356 error_message
= ": expecting %asrN";
1363 the_insn
.reloc
= BFD_RELOC_SPARC_11
;
1367 the_insn
.reloc
= BFD_RELOC_SPARC_10
;
1371 /* V8 systems don't understand BFD_RELOC_SPARC_5. */
1372 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1373 the_insn
.reloc
= BFD_RELOC_SPARC_5
;
1375 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1376 /* These fields are unsigned, but for upward compatibility,
1377 allow negative values as well. */
1381 /* V8 systems don't understand BFD_RELOC_SPARC_6. */
1382 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1383 the_insn
.reloc
= BFD_RELOC_SPARC_6
;
1385 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1386 /* These fields are unsigned, but for upward compatibility,
1387 allow negative values as well. */
1391 the_insn
.reloc
= /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16
;
1396 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP19
;
1401 if (*s
== 'p' && s
[1] == 'n')
1409 if (*s
== 'p' && s
[1] == 't')
1421 if (strncmp (s
, "%icc", 4) == 0)
1433 if (strncmp (s
, "%xcc", 4) == 0)
1445 if (strncmp (s
, "%fcc0", 5) == 0)
1457 if (strncmp (s
, "%fcc1", 5) == 0)
1469 if (strncmp (s
, "%fcc2", 5) == 0)
1481 if (strncmp (s
, "%fcc3", 5) == 0)
1489 if (strncmp (s
, "%pc", 3) == 0)
1497 if (strncmp (s
, "%tick", 5) == 0)
1504 case '\0': /* end of args */
1523 case '[': /* these must match exactly */
1531 case '#': /* must be at least one digit */
1534 while (isdigit (*s
))
1542 case 'C': /* coprocessor state register */
1543 if (strncmp (s
, "%csr", 4) == 0)
1550 case 'b': /* next operand is a coprocessor register */
1553 if (*s
++ == '%' && *s
++ == 'c' && isdigit (*s
))
1558 mask
= 10 * (mask
- '0') + (*s
++ - '0');
1572 opcode
|= mask
<< 14;
1580 opcode
|= mask
<< 25;
1586 case 'r': /* next operand must be a register */
1596 case 'f': /* frame pointer */
1604 case 'g': /* global register */
1605 if (isoctal (c
= *s
++))
1612 case 'i': /* in register */
1613 if (isoctal (c
= *s
++))
1615 mask
= c
- '0' + 24;
1620 case 'l': /* local register */
1621 if (isoctal (c
= *s
++))
1623 mask
= (c
- '0' + 16);
1628 case 'o': /* out register */
1629 if (isoctal (c
= *s
++))
1631 mask
= (c
- '0' + 8);
1636 case 's': /* stack pointer */
1644 case 'r': /* any register */
1645 if (!isdigit (c
= *s
++))
1662 if ((c
= 10 * (c
- '0') + (*s
++ - '0')) >= 32)
1678 /* Got the register, now figure out where
1679 it goes in the opcode. */
1683 opcode
|= mask
<< 14;
1691 opcode
|= mask
<< 25;
1695 opcode
|= (mask
<< 25) | (mask
<< 14);
1699 opcode
|= (mask
<< 25) | (mask
<< 0);
1705 case 'e': /* next operand is a floating point register */
1720 && ((format
= *s
) == 'f')
1723 for (mask
= 0; isdigit (*s
); ++s
)
1725 mask
= 10 * mask
+ (*s
- '0');
1726 } /* read the number */
1734 } /* register must be even numbered */
1742 } /* register must be multiple of 4 */
1746 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1747 error_message
= ": There are only 64 f registers; [0-63]";
1749 error_message
= ": There are only 32 f registers; [0-31]";
1752 else if (mask
>= 32)
1754 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
))
1757 mask
-= 31; /* wrap high bit */
1761 error_message
= ": There are only 32 f registers; [0-31]";
1769 } /* if not an 'f' register. */
1776 opcode
|= RS1 (mask
);
1783 opcode
|= RS2 (mask
);
1789 opcode
|= RD (mask
);
1798 if (strncmp (s
, "%fsr", 4) == 0)
1805 case '0': /* 64 bit immediate (setx insn) */
1806 the_insn
.reloc
= BFD_RELOC_NONE
; /* reloc handled elsewhere */
1809 case 'h': /* high 22 bits */
1810 the_insn
.reloc
= BFD_RELOC_HI22
;
1813 case 'l': /* 22 bit PC relative immediate */
1814 the_insn
.reloc
= BFD_RELOC_SPARC_WDISP22
;
1818 case 'L': /* 30 bit immediate */
1819 the_insn
.reloc
= BFD_RELOC_32_PCREL_S2
;
1823 case 'n': /* 22 bit immediate */
1824 the_insn
.reloc
= BFD_RELOC_SPARC22
;
1827 case 'i': /* 13 bit immediate */
1828 the_insn
.reloc
= BFD_RELOC_SPARC13
;
1836 /* Check for %hi, etc. */
1840 /* The name as it appears in assembler. */
1842 /* strlen (name), precomputed for speed */
1844 /* The reloc this pseudo-op translates to. */
1846 /* Non-zero if for v9 only. */
1848 /* Non-zero if can be used in pc-relative contexts. */
1849 int pcrel_p
;/*FIXME:wip*/
1851 /* hix/lox must appear before hi/lo so %hix won't be
1852 mistaken for %hi. */
1853 { "hix", 3, BFD_RELOC_SPARC_HIX22
, 1, 0 },
1854 { "lox", 3, BFD_RELOC_SPARC_LOX10
, 1, 0 },
1855 { "hi", 2, BFD_RELOC_HI22
, 0, 1 },
1856 { "lo", 2, BFD_RELOC_LO10
, 0, 1 },
1857 { "hh", 2, BFD_RELOC_SPARC_HH22
, 1, 1 },
1858 { "hm", 2, BFD_RELOC_SPARC_HM10
, 1, 1 },
1859 { "lm", 2, BFD_RELOC_SPARC_LM22
, 1, 1 },
1860 { "h44", 3, BFD_RELOC_SPARC_H44
, 1, 0 },
1861 { "m44", 3, BFD_RELOC_SPARC_M44
, 1, 0 },
1862 { "l44", 3, BFD_RELOC_SPARC_L44
, 1, 0 },
1863 { "uhi", 3, BFD_RELOC_SPARC_HH22
, 1, 0 },
1864 { "ulo", 3, BFD_RELOC_SPARC_HM10
, 1, 0 },
1869 for (o
= ops
; o
->name
; o
++)
1870 if (strncmp (s
+ 1, o
->name
, o
->len
) == 0)
1872 if (o
->name
== NULL
)
1875 the_insn
.reloc
= o
->reloc
;
1880 /* Note that if the get_expression() fails, we will still
1881 have created U entries in the symbol table for the
1882 'symbols' in the input string. Try not to create U
1883 symbols for registers, etc. */
1885 /* This stuff checks to see if the expression ends in
1886 +%reg. If it does, it removes the register from
1887 the expression, and re-sets 's' to point to the
1892 for (s1
= s
; *s1
&& *s1
!= ',' && *s1
!= ']'; s1
++) ;
1894 if (s1
!= s
&& isdigit (s1
[-1]))
1896 if (s1
[-2] == '%' && s1
[-3] == '+')
1900 (void) get_expression (s
);
1905 else if (strchr ("goli0123456789", s1
[-2]) && s1
[-3] == '%' && s1
[-4] == '+')
1909 (void) get_expression (s
);
1916 (void) get_expression (s
);
1919 /* Check for constants that don't require emitting a reloc. */
1920 if (the_insn
.exp
.X_op
== O_constant
1921 && the_insn
.exp
.X_add_symbol
== 0
1922 && the_insn
.exp
.X_op_symbol
== 0)
1924 /* For pc-relative call instructions, we reject
1925 constants to get better code. */
1927 && the_insn
.reloc
== BFD_RELOC_32_PCREL_S2
1928 && in_signed_range (the_insn
.exp
.X_add_number
, 0x3fff))
1930 error_message
= ": PC-relative operand can't be a constant";
1934 /* Constants that won't fit are checked in md_apply_fix3
1935 and bfd_install_relocation.
1936 ??? It would be preferable to install the constants
1937 into the insn here and save having to create a fixS
1938 for each one. There already exists code to handle
1939 all the various cases (e.g. in md_apply_fix3 and
1940 bfd_install_relocation) so duplicating all that code
1941 here isn't right. */
1961 if (! parse_keyword_arg (sparc_encode_asi
, &s
, &asi
))
1963 error_message
= ": invalid ASI name";
1969 if (! parse_const_expr_arg (&s
, &asi
))
1971 error_message
= ": invalid ASI expression";
1974 if (asi
< 0 || asi
> 255)
1976 error_message
= ": invalid ASI number";
1980 opcode
|= ASI (asi
);
1982 } /* alternate space */
1985 if (strncmp (s
, "%psr", 4) == 0)
1992 case 'q': /* floating point queue */
1993 if (strncmp (s
, "%fq", 3) == 0)
2000 case 'Q': /* coprocessor queue */
2001 if (strncmp (s
, "%cq", 3) == 0)
2009 if (strcmp (str
, "set") == 0
2010 || strcmp (str
, "setuw") == 0)
2012 special_case
= SPECIAL_CASE_SET
;
2015 else if (strcmp (str
, "setsw") == 0)
2017 special_case
= SPECIAL_CASE_SETSW
;
2020 else if (strcmp (str
, "setx") == 0)
2022 special_case
= SPECIAL_CASE_SETX
;
2025 else if (strncmp (str
, "fdiv", 4) == 0)
2027 special_case
= SPECIAL_CASE_FDIV
;
2033 if (strncmp (s
, "%asi", 4) != 0)
2039 if (strncmp (s
, "%fprs", 5) != 0)
2045 if (strncmp (s
, "%ccr", 4) != 0)
2051 if (strncmp (s
, "%tbr", 4) != 0)
2057 if (strncmp (s
, "%wim", 4) != 0)
2064 char *push
= input_line_pointer
;
2067 input_line_pointer
= s
;
2069 if (e
.X_op
== O_constant
)
2071 int n
= e
.X_add_number
;
2072 if (n
!= e
.X_add_number
|| (n
& ~0x1ff) != 0)
2073 as_bad ("OPF immediate operand out of range (0-0x1ff)");
2075 opcode
|= e
.X_add_number
<< 5;
2078 as_bad ("non-immediate OPF operand, ignored");
2079 s
= input_line_pointer
;
2080 input_line_pointer
= push
;
2085 if (strncmp (s
, "%y", 2) != 0)
2093 /* Parse a sparclet cpreg. */
2095 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg
, &s
, &cpreg
))
2097 error_message
= ": invalid cpreg name";
2100 opcode
|= (*args
== 'U' ? RS1 (cpreg
) : RD (cpreg
));
2105 as_fatal ("failed sanity check.");
2106 } /* switch on arg code */
2108 /* Break out of for() loop. */
2110 } /* for each arg that we expect */
2115 /* Args don't match. */
2116 if (((unsigned) (&insn
[1] - sparc_opcodes
)) < sparc_num_opcodes
2117 && (insn
->name
== insn
[1].name
2118 || !strcmp (insn
->name
, insn
[1].name
)))
2126 as_bad ("Illegal operands%s", error_message
);
2132 /* We have a match. Now see if the architecture is ok. */
2133 int needed_arch_mask
= insn
->architecture
;
2137 needed_arch_mask
&= ~ ((1 << SPARC_OPCODE_ARCH_V9
)
2138 | (1 << SPARC_OPCODE_ARCH_V9A
));
2139 needed_arch_mask
|= (1 << SPARC_OPCODE_ARCH_V9
);
2142 if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (current_architecture
))
2144 /* Can we bump up the architecture? */
2145 else if (needed_arch_mask
& SPARC_OPCODE_SUPPORTED (max_architecture
))
2147 enum sparc_opcode_arch_val needed_architecture
=
2148 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture
)
2149 & needed_arch_mask
);
2151 assert (needed_architecture
<= SPARC_OPCODE_ARCH_MAX
);
2153 && needed_architecture
> warn_after_architecture
)
2155 as_warn ("architecture bumped from \"%s\" to \"%s\" on \"%s\"",
2156 sparc_opcode_archs
[current_architecture
].name
,
2157 sparc_opcode_archs
[needed_architecture
].name
,
2159 warn_after_architecture
= needed_architecture
;
2161 current_architecture
= needed_architecture
;
2164 /* ??? This seems to be a bit fragile. What if the next entry in
2165 the opcode table is the one we want and it is supported?
2166 It is possible to arrange the table today so that this can't
2167 happen but what about tomorrow? */
2170 int arch
,printed_one_p
= 0;
2172 char required_archs
[SPARC_OPCODE_ARCH_MAX
* 16];
2174 /* Create a list of the architectures that support the insn. */
2175 needed_arch_mask
&= ~ SPARC_OPCODE_SUPPORTED (max_architecture
);
2177 arch
= sparc_ffs (needed_arch_mask
);
2178 while ((1 << arch
) <= needed_arch_mask
)
2180 if ((1 << arch
) & needed_arch_mask
)
2184 strcpy (p
, sparc_opcode_archs
[arch
].name
);
2191 as_bad ("Architecture mismatch on \"%s\".", str
);
2192 as_tsktsk (" (Requires %s; requested architecture is %s.)",
2194 sparc_opcode_archs
[max_architecture
].name
);
2200 } /* forever looking for a match */
2202 the_insn
.opcode
= opcode
;
2205 /* Parse an argument that can be expressed as a keyword.
2206 (eg: #StoreStore or %ccfr).
2207 The result is a boolean indicating success.
2208 If successful, INPUT_POINTER is updated. */
2211 parse_keyword_arg (lookup_fn
, input_pointerP
, valueP
)
2212 int (*lookup_fn
) PARAMS ((const char *));
2213 char **input_pointerP
;
2219 p
= *input_pointerP
;
2220 for (q
= p
+ (*p
== '#' || *p
== '%'); isalnum (*q
) || *q
== '_'; ++q
)
2224 value
= (*lookup_fn
) (p
);
2229 *input_pointerP
= q
;
2233 /* Parse an argument that is a constant expression.
2234 The result is a boolean indicating success. */
2237 parse_const_expr_arg (input_pointerP
, valueP
)
2238 char **input_pointerP
;
2241 char *save
= input_line_pointer
;
2244 input_line_pointer
= *input_pointerP
;
2245 /* The next expression may be something other than a constant
2246 (say if we're not processing the right variant of the insn).
2247 Don't call expression unless we're sure it will succeed as it will
2248 signal an error (which we want to defer until later). */
2249 /* FIXME: It might be better to define md_operand and have it recognize
2250 things like %asi, etc. but continuing that route through to the end
2251 is a lot of work. */
2252 if (*input_line_pointer
== '%')
2254 input_line_pointer
= save
;
2258 *input_pointerP
= input_line_pointer
;
2259 input_line_pointer
= save
;
2260 if (exp
.X_op
!= O_constant
)
2262 *valueP
= exp
.X_add_number
;
2266 /* Subroutine of sparc_ip to parse an expression. */
2269 get_expression (str
)
2275 save_in
= input_line_pointer
;
2276 input_line_pointer
= str
;
2277 seg
= expression (&the_insn
.exp
);
2278 if (seg
!= absolute_section
2279 && seg
!= text_section
2280 && seg
!= data_section
2281 && seg
!= bss_section
2282 && seg
!= undefined_section
)
2284 the_insn
.error
= "bad segment";
2285 expr_end
= input_line_pointer
;
2286 input_line_pointer
= save_in
;
2289 expr_end
= input_line_pointer
;
2290 input_line_pointer
= save_in
;
2294 /* Subroutine of md_assemble to output one insn. */
2297 output_insn (insn
, the_insn
)
2298 const struct sparc_opcode
*insn
;
2299 struct sparc_it
*the_insn
;
2301 char *toP
= frag_more (4);
2303 /* put out the opcode */
2304 if (INSN_BIG_ENDIAN
)
2305 number_to_chars_bigendian (toP
, (valueT
) the_insn
->opcode
, 4);
2307 number_to_chars_littleendian (toP
, (valueT
) the_insn
->opcode
, 4);
2309 /* put out the symbol-dependent stuff */
2310 if (the_insn
->reloc
!= BFD_RELOC_NONE
)
2312 fixS
*fixP
= fix_new_exp (frag_now
, /* which frag */
2313 (toP
- frag_now
->fr_literal
), /* where */
2318 /* Turn off overflow checking in fixup_segment. We'll do our
2319 own overflow checking in md_apply_fix3. This is necessary because
2320 the insn size is 4 and fixup_segment will signal an overflow for
2321 large 8 byte quantities. */
2322 fixP
->fx_no_overflow
= 1;
2326 last_opcode
= the_insn
->opcode
;
2330 This is identical to the md_atof in m68k.c. I think this is right,
2333 Turn a string in input_line_pointer into a floating point constant of type
2334 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
2335 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
2338 /* Equal to MAX_PRECISION in atof-ieee.c */
2339 #define MAX_LITTLENUMS 6
2342 md_atof (type
, litP
, sizeP
)
2348 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2379 return "Bad call to MD_ATOF()";
2382 t
= atof_ieee (input_line_pointer
, type
, words
);
2384 input_line_pointer
= t
;
2385 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
2387 if (target_big_endian
)
2389 for (i
= 0; i
< prec
; i
++)
2391 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2392 litP
+= sizeof (LITTLENUM_TYPE
);
2397 for (i
= prec
- 1; i
>= 0; i
--)
2399 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
2400 litP
+= sizeof (LITTLENUM_TYPE
);
2407 /* Write a value out to the object file, using the appropriate
2411 md_number_to_chars (buf
, val
, n
)
2416 if (target_big_endian
)
2417 number_to_chars_bigendian (buf
, val
, n
);
2419 number_to_chars_littleendian (buf
, val
, n
);
2422 /* Apply a fixS to the frags, now that we know the value it ought to
2426 md_apply_fix3 (fixP
, value
, segment
)
2431 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
2437 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
2439 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc */
2442 /* FIXME: SPARC ELF relocations don't use an addend in the data
2443 field itself. This whole approach should be somehow combined
2444 with the calls to bfd_install_relocation. Also, the value passed
2445 in by fixup_segment includes the value of a defined symbol. We
2446 don't want to include the value of an externally visible symbol. */
2447 if (fixP
->fx_addsy
!= NULL
)
2449 if (fixP
->fx_addsy
->sy_used_in_reloc
2450 && (S_IS_EXTERNAL (fixP
->fx_addsy
)
2451 || S_IS_WEAK (fixP
->fx_addsy
)
2452 || (sparc_pic_code
&& ! fixP
->fx_pcrel
)
2453 || (S_GET_SEGMENT (fixP
->fx_addsy
) != segment
2454 && ((bfd_get_section_flags (stdoutput
,
2455 S_GET_SEGMENT (fixP
->fx_addsy
))
2456 & SEC_LINK_ONCE
) != 0
2457 || strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
2459 sizeof ".gnu.linkonce" - 1) == 0)))
2460 && S_GET_SEGMENT (fixP
->fx_addsy
) != absolute_section
2461 && S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
2462 && ! bfd_is_com_section (S_GET_SEGMENT (fixP
->fx_addsy
)))
2463 fixP
->fx_addnumber
-= S_GET_VALUE (fixP
->fx_addsy
);
2468 /* This is a hack. There should be a better way to
2469 handle this. Probably in terms of howto fields, once
2470 we can look at these fixups in terms of howtos. */
2471 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL_S2
&& fixP
->fx_addsy
)
2472 val
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2475 /* FIXME: More ridiculous gas reloc hacking. If we are going to
2476 generate a reloc, then we just want to let the reloc addend set
2477 the value. We do not want to also stuff the addend into the
2478 object file. Including the addend in the object file works when
2479 doing a static link, because the linker will ignore the object
2480 file contents. However, the dynamic linker does not ignore the
2481 object file contents. */
2482 if (fixP
->fx_addsy
!= NULL
2483 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
)
2486 /* When generating PIC code, we do not want an addend for a reloc
2487 against a local symbol. We adjust fx_addnumber to cancel out the
2488 value already included in val, and to also cancel out the
2489 adjustment which bfd_install_relocation will create. */
2491 && fixP
->fx_r_type
!= BFD_RELOC_32_PCREL_S2
2492 && fixP
->fx_addsy
!= NULL
2493 && ! S_IS_COMMON (fixP
->fx_addsy
)
2494 && (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
2495 fixP
->fx_addnumber
-= 2 * S_GET_VALUE (fixP
->fx_addsy
);
2498 /* If this is a data relocation, just output VAL. */
2500 if (fixP
->fx_r_type
== BFD_RELOC_16
)
2502 md_number_to_chars (buf
, val
, 2);
2504 else if (fixP
->fx_r_type
== BFD_RELOC_32
)
2506 md_number_to_chars (buf
, val
, 4);
2508 else if (fixP
->fx_r_type
== BFD_RELOC_64
)
2510 md_number_to_chars (buf
, val
, 8);
2514 /* It's a relocation against an instruction. */
2516 if (INSN_BIG_ENDIAN
)
2517 insn
= bfd_getb32 ((unsigned char *) buf
);
2519 insn
= bfd_getl32 ((unsigned char *) buf
);
2521 switch (fixP
->fx_r_type
)
2523 case BFD_RELOC_32_PCREL_S2
:
2525 /* FIXME: This increment-by-one deserves a comment of why it's
2527 if (! sparc_pic_code
2528 || fixP
->fx_addsy
== NULL
2529 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2531 insn
|= val
& 0x3fffffff;
2534 case BFD_RELOC_SPARC_11
:
2535 if (! in_signed_range (val
, 0x7ff))
2536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2537 insn
|= val
& 0x7ff;
2540 case BFD_RELOC_SPARC_10
:
2541 if (! in_signed_range (val
, 0x3ff))
2542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2543 insn
|= val
& 0x3ff;
2546 case BFD_RELOC_SPARC_7
:
2547 if (! in_bitfield_range (val
, 0x7f))
2548 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2552 case BFD_RELOC_SPARC_6
:
2553 if (! in_bitfield_range (val
, 0x3f))
2554 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2558 case BFD_RELOC_SPARC_5
:
2559 if (! in_bitfield_range (val
, 0x1f))
2560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2564 case BFD_RELOC_SPARC_WDISP16
:
2565 /* FIXME: simplify */
2566 if (((val
> 0) && (val
& ~0x3fffc))
2567 || ((val
< 0) && (~(val
- 1) & ~0x3fffc)))
2568 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2569 /* FIXME: The +1 deserves a comment. */
2570 val
= (val
>> 2) + 1;
2571 insn
|= ((val
& 0xc000) << 6) | (val
& 0x3fff);
2574 case BFD_RELOC_SPARC_WDISP19
:
2575 /* FIXME: simplify */
2576 if (((val
> 0) && (val
& ~0x1ffffc))
2577 || ((val
< 0) && (~(val
- 1) & ~0x1ffffc)))
2578 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2579 /* FIXME: The +1 deserves a comment. */
2580 val
= (val
>> 2) + 1;
2581 insn
|= val
& 0x7ffff;
2584 case BFD_RELOC_SPARC_HH22
:
2585 val
= BSR (val
, 32);
2586 /* intentional fallthrough */
2588 case BFD_RELOC_SPARC_LM22
:
2589 case BFD_RELOC_HI22
:
2590 if (!fixP
->fx_addsy
)
2592 insn
|= (val
>> 10) & 0x3fffff;
2596 /* FIXME: Need comment explaining why we do this. */
2601 case BFD_RELOC_SPARC22
:
2602 if (val
& ~0x003fffff)
2603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2604 insn
|= (val
& 0x3fffff);
2607 case BFD_RELOC_SPARC_HM10
:
2608 val
= BSR (val
, 32);
2609 /* intentional fallthrough */
2611 case BFD_RELOC_LO10
:
2612 if (!fixP
->fx_addsy
)
2614 insn
|= val
& 0x3ff;
2618 /* FIXME: Need comment explaining why we do this. */
2623 case BFD_RELOC_SPARC13
:
2624 if (! in_signed_range (val
, 0x1fff))
2625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "relocation overflow");
2626 insn
|= val
& 0x1fff;
2629 case BFD_RELOC_SPARC_WDISP22
:
2630 val
= (val
>> 2) + 1;
2632 case BFD_RELOC_SPARC_BASE22
:
2633 insn
|= val
& 0x3fffff;
2636 case BFD_RELOC_SPARC_H44
:
2637 if (!fixP
->fx_addsy
)
2641 insn
|= tval
& 0x3fffff;
2645 case BFD_RELOC_SPARC_M44
:
2646 if (!fixP
->fx_addsy
)
2647 insn
|= (val
>> 12) & 0x3ff;
2650 case BFD_RELOC_SPARC_L44
:
2651 if (!fixP
->fx_addsy
)
2652 insn
|= val
& 0xfff;
2655 case BFD_RELOC_SPARC_HIX22
:
2656 if (!fixP
->fx_addsy
)
2658 val
^= ~ (offsetT
) 0;
2659 insn
|= (val
>> 10) & 0x3fffff;
2663 case BFD_RELOC_SPARC_LOX10
:
2664 if (!fixP
->fx_addsy
)
2665 insn
|= 0x1c00 | (val
& 0x3ff);
2668 case BFD_RELOC_NONE
:
2670 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
2671 "bad or unhandled relocation type: 0x%02x",
2676 if (INSN_BIG_ENDIAN
)
2677 bfd_putb32 (insn
, (unsigned char *) buf
);
2679 bfd_putl32 (insn
, (unsigned char *) buf
);
2682 /* Are we finished with this relocation now? */
2683 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
2689 /* Translate internal representation of relocation info to BFD target
2692 tc_gen_reloc (section
, fixp
)
2697 bfd_reloc_code_real_type code
;
2699 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
2701 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
2702 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
2704 switch (fixp
->fx_r_type
)
2708 case BFD_RELOC_HI22
:
2709 case BFD_RELOC_LO10
:
2710 case BFD_RELOC_32_PCREL_S2
:
2711 case BFD_RELOC_SPARC13
:
2712 case BFD_RELOC_SPARC_BASE13
:
2713 case BFD_RELOC_SPARC_WDISP16
:
2714 case BFD_RELOC_SPARC_WDISP19
:
2715 case BFD_RELOC_SPARC_WDISP22
:
2717 case BFD_RELOC_SPARC_5
:
2718 case BFD_RELOC_SPARC_6
:
2719 case BFD_RELOC_SPARC_7
:
2720 case BFD_RELOC_SPARC_10
:
2721 case BFD_RELOC_SPARC_11
:
2722 case BFD_RELOC_SPARC_HH22
:
2723 case BFD_RELOC_SPARC_HM10
:
2724 case BFD_RELOC_SPARC_LM22
:
2725 case BFD_RELOC_SPARC_PC_HH22
:
2726 case BFD_RELOC_SPARC_PC_HM10
:
2727 case BFD_RELOC_SPARC_PC_LM22
:
2728 case BFD_RELOC_SPARC_H44
:
2729 case BFD_RELOC_SPARC_M44
:
2730 case BFD_RELOC_SPARC_L44
:
2731 case BFD_RELOC_SPARC_HIX22
:
2732 case BFD_RELOC_SPARC_LOX10
:
2733 code
= fixp
->fx_r_type
;
2739 #if defined (OBJ_ELF) || defined (OBJ_AOUT)
2740 /* If we are generating PIC code, we need to generate a different
2744 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
2746 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
2753 case BFD_RELOC_32_PCREL_S2
:
2754 if (! S_IS_DEFINED (fixp
->fx_addsy
)
2755 || S_IS_COMMON (fixp
->fx_addsy
)
2756 || S_IS_EXTERNAL (fixp
->fx_addsy
)
2757 || S_IS_WEAK (fixp
->fx_addsy
))
2758 code
= BFD_RELOC_SPARC_WPLT30
;
2760 case BFD_RELOC_HI22
:
2761 if (fixp
->fx_addsy
!= NULL
2762 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2763 code
= BFD_RELOC_SPARC_PC22
;
2765 code
= BFD_RELOC_SPARC_GOT22
;
2767 case BFD_RELOC_LO10
:
2768 if (fixp
->fx_addsy
!= NULL
2769 && strcmp (S_GET_NAME (fixp
->fx_addsy
), GOT_NAME
) == 0)
2770 code
= BFD_RELOC_SPARC_PC10
;
2772 code
= BFD_RELOC_SPARC_GOT10
;
2774 case BFD_RELOC_SPARC13
:
2775 code
= BFD_RELOC_SPARC_GOT13
;
2781 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */
2783 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
2784 if (reloc
->howto
== 0)
2786 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
2787 "internal error: can't export reloc type %d (`%s')",
2788 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
2792 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
2795 if (reloc
->howto
->pc_relative
== 0
2796 || code
== BFD_RELOC_SPARC_PC10
2797 || code
== BFD_RELOC_SPARC_PC22
)
2798 reloc
->addend
= fixp
->fx_addnumber
;
2800 reloc
->addend
= fixp
->fx_offset
- reloc
->address
;
2802 #else /* elf or coff */
2804 if (reloc
->howto
->pc_relative
== 0
2805 || code
== BFD_RELOC_SPARC_PC10
2806 || code
== BFD_RELOC_SPARC_PC22
)
2807 reloc
->addend
= fixp
->fx_addnumber
;
2808 else if ((fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2809 reloc
->addend
= (section
->vma
2810 + fixp
->fx_addnumber
2811 + md_pcrel_from (fixp
));
2813 reloc
->addend
= fixp
->fx_offset
;
2819 /* We have no need to default values of symbols. */
2823 md_undefined_symbol (name
)
2827 } /* md_undefined_symbol() */
2829 /* Round up a section size to the appropriate boundary. */
2831 md_section_align (segment
, size
)
2836 /* This is not right for ELF; a.out wants it, and COFF will force
2837 the alignment anyways. */
2838 valueT align
= ((valueT
) 1
2839 << (valueT
) bfd_get_section_alignment (stdoutput
, segment
));
2841 /* turn alignment value into a mask */
2843 newsize
= (size
+ align
) & ~align
;
2850 /* Exactly what point is a PC-relative offset relative TO?
2851 On the sparc, they're relative to the address of the offset, plus
2852 its size. This gets us to the following instruction.
2853 (??? Is this right? FIXME-SOON) */
2855 md_pcrel_from (fixP
)
2860 ret
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
2861 if (! sparc_pic_code
2862 || fixP
->fx_addsy
== NULL
2863 || (fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) != 0)
2864 ret
+= fixP
->fx_size
;
2869 * sort of like s_lcomm
2873 static int max_alignment
= 15;
2888 name
= input_line_pointer
;
2889 c
= get_symbol_end ();
2890 p
= input_line_pointer
;
2894 if (*input_line_pointer
!= ',')
2896 as_bad ("Expected comma after name");
2897 ignore_rest_of_line ();
2901 ++input_line_pointer
;
2903 if ((size
= get_absolute_expression ()) < 0)
2905 as_bad ("BSS length (%d.) <0! Ignored.", size
);
2906 ignore_rest_of_line ();
2911 symbolP
= symbol_find_or_make (name
);
2914 if (strncmp (input_line_pointer
, ",\"bss\"", 6) != 0
2915 && strncmp (input_line_pointer
, ",\".bss\"", 7) != 0)
2917 as_bad ("bad .reserve segment -- expected BSS segment");
2921 if (input_line_pointer
[2] == '.')
2922 input_line_pointer
+= 7;
2924 input_line_pointer
+= 6;
2927 if (*input_line_pointer
== ',')
2929 ++input_line_pointer
;
2932 if (*input_line_pointer
== '\n')
2934 as_bad ("Missing alignment");
2938 align
= get_absolute_expression ();
2940 if (align
> max_alignment
)
2942 align
= max_alignment
;
2943 as_warn ("Alignment too large: %d. assumed.", align
);
2949 as_warn ("Alignment negative. 0 assumed.");
2952 record_alignment (bss_section
, align
);
2954 /* convert to a power of 2 alignment */
2955 for (temp
= 0; (align
& 1) == 0; align
>>= 1, ++temp
);;
2959 as_bad ("Alignment not a power of 2");
2960 ignore_rest_of_line ();
2962 } /* not a power of two */
2965 } /* if has optional alignment */
2969 if (!S_IS_DEFINED (symbolP
)
2971 && S_GET_OTHER (symbolP
) == 0
2972 && S_GET_DESC (symbolP
) == 0
2979 segT current_seg
= now_seg
;
2980 subsegT current_subseg
= now_subseg
;
2982 subseg_set (bss_section
, 1); /* switch to bss */
2985 frag_align (align
, 0, 0); /* do alignment */
2987 /* detach from old frag */
2988 if (S_GET_SEGMENT(symbolP
) == bss_section
)
2989 symbolP
->sy_frag
->fr_symbol
= NULL
;
2991 symbolP
->sy_frag
= frag_now
;
2992 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, symbolP
,
2993 (offsetT
) size
, (char *)0);
2996 S_SET_SEGMENT (symbolP
, bss_section
);
2998 subseg_set (current_seg
, current_subseg
);
3003 as_warn("Ignoring attempt to re-define symbol %s",
3004 S_GET_NAME (symbolP
));
3005 } /* if not redefining */
3007 demand_empty_rest_of_line ();
3020 name
= input_line_pointer
;
3021 c
= get_symbol_end ();
3022 /* just after name is now '\0' */
3023 p
= input_line_pointer
;
3026 if (*input_line_pointer
!= ',')
3028 as_bad ("Expected comma after symbol-name");
3029 ignore_rest_of_line ();
3032 input_line_pointer
++; /* skip ',' */
3033 if ((temp
= get_absolute_expression ()) < 0)
3035 as_bad (".COMMon length (%d.) <0! Ignored.", temp
);
3036 ignore_rest_of_line ();
3041 symbolP
= symbol_find_or_make (name
);
3043 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
3045 as_bad ("Ignoring attempt to re-define symbol");
3046 ignore_rest_of_line ();
3049 if (S_GET_VALUE (symbolP
) != 0)
3051 if (S_GET_VALUE (symbolP
) != size
)
3053 as_warn ("Length of .comm \"%s\" is already %ld. Not changed to %d.",
3054 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
3060 S_SET_VALUE (symbolP
, (valueT
) size
);
3061 S_SET_EXTERNAL (symbolP
);
3064 know (symbolP
->sy_frag
== &zero_address_frag
);
3065 if (*input_line_pointer
!= ',')
3067 as_bad ("Expected comma after common length");
3068 ignore_rest_of_line ();
3071 input_line_pointer
++;
3073 if (*input_line_pointer
!= '"')
3075 temp
= get_absolute_expression ();
3077 if (temp
> max_alignment
)
3079 temp
= max_alignment
;
3080 as_warn ("Common alignment too large: %d. assumed", temp
);
3086 as_warn ("Common alignment negative; 0 assumed");
3097 old_subsec
= now_subseg
;
3099 record_alignment (bss_section
, align
);
3100 subseg_set (bss_section
, 0);
3102 frag_align (align
, 0, 0);
3103 if (S_GET_SEGMENT (symbolP
) == bss_section
)
3104 symbolP
->sy_frag
->fr_symbol
= 0;
3105 symbolP
->sy_frag
= frag_now
;
3106 p
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
3107 (offsetT
) size
, (char *) 0);
3109 S_SET_SEGMENT (symbolP
, bss_section
);
3110 S_CLEAR_EXTERNAL (symbolP
);
3111 subseg_set (old_sec
, old_subsec
);
3117 S_SET_VALUE (symbolP
, (valueT
) size
);
3119 S_SET_ALIGN (symbolP
, temp
);
3121 S_SET_EXTERNAL (symbolP
);
3122 S_SET_SEGMENT (symbolP
, bfd_com_section_ptr
);
3127 input_line_pointer
++;
3128 /* @@ Some use the dot, some don't. Can we get some consistency?? */
3129 if (*input_line_pointer
== '.')
3130 input_line_pointer
++;
3131 /* @@ Some say data, some say bss. */
3132 if (strncmp (input_line_pointer
, "bss\"", 4)
3133 && strncmp (input_line_pointer
, "data\"", 5))
3135 while (*--input_line_pointer
!= '"')
3137 input_line_pointer
--;
3138 goto bad_common_segment
;
3140 while (*input_line_pointer
++ != '"')
3142 goto allocate_common
;
3145 #ifdef BFD_ASSEMBLER
3146 symbolP
->bsym
->flags
|= BSF_OBJECT
;
3149 demand_empty_rest_of_line ();
3154 p
= input_line_pointer
;
3155 while (*p
&& *p
!= '\n')
3159 as_bad ("bad .common segment %s", input_line_pointer
+ 1);
3161 input_line_pointer
= p
;
3162 ignore_rest_of_line ();
3167 /* Handle the .empty pseudo-op. This supresses the warnings about
3168 invalid delay slot usage. */
3174 /* The easy way to implement is to just forget about the last
3184 if (strncmp (input_line_pointer
, "\"text\"", 6) == 0)
3186 input_line_pointer
+= 6;
3190 if (strncmp (input_line_pointer
, "\"data\"", 6) == 0)
3192 input_line_pointer
+= 6;
3196 if (strncmp (input_line_pointer
, "\"data1\"", 7) == 0)
3198 input_line_pointer
+= 7;
3202 if (strncmp (input_line_pointer
, "\"bss\"", 5) == 0)
3204 input_line_pointer
+= 5;
3205 /* We only support 2 segments -- text and data -- for now, so
3206 things in the "bss segment" will have to go into data for now.
3207 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */
3208 subseg_set (data_section
, 255); /* FIXME-SOMEDAY */
3211 as_bad ("Unknown segment type");
3212 demand_empty_rest_of_line ();
3218 subseg_set (data_section
, 1);
3219 demand_empty_rest_of_line ();
3226 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3228 ++input_line_pointer
;
3230 ++input_line_pointer
;
3233 /* This static variable is set by s_uacons to tell sparc_cons_align
3234 that the expession does not need to be aligned. */
3236 static int sparc_no_align_cons
= 0;
3238 /* This handles the unaligned space allocation pseudo-ops, such as
3239 .uaword. .uaword is just like .word, but the value does not need
3246 /* Tell sparc_cons_align not to align this value. */
3247 sparc_no_align_cons
= 1;
3251 /* If the --enforce-aligned-data option is used, we require .word,
3252 et. al., to be aligned correctly. We do it by setting up an
3253 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that
3254 no unexpected alignment was introduced.
3256 The SunOS and Solaris native assemblers enforce aligned data by
3257 default. We don't want to do that, because gcc can deliberately
3258 generate misaligned data if the packed attribute is used. Instead,
3259 we permit misaligned data by default, and permit the user to set an
3260 option to check for it. */
3263 sparc_cons_align (nbytes
)
3269 /* Only do this if we are enforcing aligned data. */
3270 if (! enforce_aligned_data
)
3273 if (sparc_no_align_cons
)
3275 /* This is an unaligned pseudo-op. */
3276 sparc_no_align_cons
= 0;
3281 while ((nbytes
& 1) == 0)
3290 if (now_seg
== absolute_section
)
3292 if ((abs_section_offset
& ((1 << nalign
) - 1)) != 0)
3293 as_bad ("misaligned data");
3297 p
= frag_var (rs_align_code
, 1, 1, (relax_substateT
) 0,
3298 (symbolS
*) NULL
, (offsetT
) nalign
, (char *) NULL
);
3300 record_alignment (now_seg
, nalign
);
3303 /* This is where we do the unexpected alignment check.
3304 This is called from HANDLE_ALIGN in tc-sparc.h. */
3307 sparc_handle_align (fragp
)
3310 if (fragp
->fr_type
== rs_align_code
&& !fragp
->fr_subtype
3311 && fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
!= 0)
3312 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "misaligned data");
3313 if (fragp
->fr_type
== rs_align_code
&& fragp
->fr_subtype
== 1024)
3315 int count
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
3317 if (count
>= 4 && !(count
& 3) && count
<= 1024 && !((long)(fragp
->fr_literal
+ fragp
->fr_fix
) & 3))
3319 unsigned *p
= (unsigned *)(fragp
->fr_literal
+ fragp
->fr_fix
);
3322 for (i
= 0; i
< count
; i
+= 4)
3323 *p
++ = 0x01000000; /* nop */
3324 if (SPARC_OPCODE_ARCH_V9_P (max_architecture
) && count
> 8)
3325 *(unsigned *)(fragp
->fr_literal
+ fragp
->fr_fix
) =
3326 0x30680000 | (count
>> 2); /* ba,a,pt %xcc, 1f */
3327 fragp
->fr_var
= count
;
3333 /* Some special processing for a Sparc ELF file. */
3336 sparc_elf_final_processing ()
3338 /* Set the Sparc ELF flag bits. FIXME: There should probably be some
3339 sort of BFD interface for this. */
3340 if (sparc_arch_size
== 64)
3341 switch (sparc_memory_model
)
3344 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_RMO
;
3347 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARCV9_PSO
;
3350 else if (current_architecture
>= SPARC_OPCODE_ARCH_V9
)
3351 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_32PLUS
;
3352 if (current_architecture
== SPARC_OPCODE_ARCH_V9A
)
3353 elf_elfheader (stdoutput
)->e_flags
|= EF_SPARC_SUN_US1
;