1 /* tc-v850.c -- Assembler code for the NEC V850
2 Copyright (C) 1996-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
22 #include "safe-ctype.h"
24 #include "opcode/v850.h"
25 #include "dwarf2dbg.h"
27 /* Sign-extend a 16-bit number. */
28 #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000)
30 /* Set to TRUE if we want to be pedantic about signed overflows. */
31 static bfd_boolean warn_signed_overflows
= FALSE
;
32 static bfd_boolean warn_unsigned_overflows
= FALSE
;
34 /* Non-zero if floating point insns are not being used. */
35 static signed int soft_float
= -1;
37 /* Indicates the target BFD machine number. */
38 static int machine
= -1;
41 /* Indiciates the target BFD architecture. */
42 int v850_target_arch
= bfd_arch_v850_rh850
;
43 const char * v850_target_format
= "elf32-v850-rh850";
44 static flagword v850_e_flags
= 0;
46 /* Indicates the target processor(s) for the assemble. */
47 static int processor_mask
= 0;
49 /* Structure to hold information about predefined registers. */
54 unsigned int processors
;
57 /* Generic assembler global variables which must be defined by all
60 /* Characters which always start a comment. */
61 const char comment_chars
[] = "#";
63 /* Characters which start a comment at the beginning of a line. */
64 const char line_comment_chars
[] = ";#";
66 /* Characters which may be used to separate multiple commands on a
68 const char line_separator_chars
[] = ";";
70 /* Characters which are used to indicate an exponent in a floating
72 const char EXP_CHARS
[] = "eE";
74 /* Characters which mean that a number is a floating point constant,
76 const char FLT_CHARS
[] = "dD";
78 const relax_typeS md_relax_table
[] =
80 /* Conditional branches.(V850/V850E, max 22bit) */
81 #define SUBYPTE_COND_9_22 0
82 {0xfe, -0x100, 2, SUBYPTE_COND_9_22
+ 1},
83 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
84 /* Conditional branches.(V850/V850E, max 22bit) */
85 #define SUBYPTE_SA_9_22 2
86 {0xfe, -0x100, 2, SUBYPTE_SA_9_22
+ 1},
87 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
88 /* Unconditional branches.(V850/V850E, max 22bit) */
89 #define SUBYPTE_UNCOND_9_22 4
90 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22
+ 1},
91 {0x1ffffe, -0x200000, 4, 0},
92 /* Conditional branches.(V850E2, max 32bit) */
93 #define SUBYPTE_COND_9_22_32 6
94 {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32
+ 1},
95 {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32
+ 2},
96 {0x7ffffffe, -0x80000000, 8, 0},
97 /* Conditional branches.(V850E2, max 32bit) */
98 #define SUBYPTE_SA_9_22_32 9
99 {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32
+ 1},
100 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32
+ 2},
101 {0x7ffffffe, -0x80000000, 10, 0},
102 /* Unconditional branches.(V850E2, max 32bit) */
103 #define SUBYPTE_UNCOND_9_22_32 12
104 {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32
+ 1},
105 {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32
+ 2},
106 {0x7ffffffe, -0x80000000, 6, 0},
107 /* Conditional branches.(V850E2R max 22bit) */
108 #define SUBYPTE_COND_9_17_22 15
109 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22
+ 1},
110 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22
+ 2},
111 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
112 /* Conditional branches.(V850E2R max 22bit) */
113 #define SUBYPTE_SA_9_17_22 18
114 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22
+ 1},
115 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22
+ 2},
116 {0x1ffffe + 4, -0x200000 + 4, 8, 0},
117 /* Conditional branches.(V850E2R max 32bit) */
118 #define SUBYPTE_COND_9_17_22_32 21
119 {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32
+ 1},
120 {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32
+ 2},
121 {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32
+ 3},
122 {0x7ffffffe, -0x80000000, 8, 0},
123 /* Conditional branches.(V850E2R max 32bit) */
124 #define SUBYPTE_SA_9_17_22_32 25
125 {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32
+ 1},
126 {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32
+ 2},
127 {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32
+ 3},
128 {0x7ffffffe, -0x80000000, 10, 0},
129 /* Loop. (V850E2V4_UP, max 22-bit). */
130 #define SUBYPTE_LOOP_16_22 29
131 {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22
+ 1},
132 {0x1ffffe + 2, -0x200000 + 2, 6, 0},
135 static int v850_relax
= 0;
137 /* Default branch disp size 22 or 32. */
138 static int default_disp_size
= 22;
140 /* Default no using bcond17. */
141 static int no_bcond17
= 0;
143 /* Default no using ld/st 23bit offset. */
144 static int no_stld23
= 0;
147 #define MAX_INSN_FIXUPS 5
153 bfd_reloc_code_real_type reloc
;
156 struct v850_fixup fixups
[MAX_INSN_FIXUPS
];
159 struct v850_seg_entry
166 struct v850_seg_entry v850_seg_table
[] =
169 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
| SEC_HAS_CONTENTS
172 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
| SEC_HAS_CONTENTS
},
174 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
| SEC_HAS_CONTENTS
},
176 SEC_ALLOC
| SEC_SMALL_DATA
},
182 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_READONLY
| SEC_DATA
183 | SEC_HAS_CONTENTS
| SEC_SMALL_DATA
},
185 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_READONLY
| SEC_DATA
186 | SEC_HAS_CONTENTS
},
188 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
| SEC_HAS_CONTENTS
189 | SEC_SMALL_DATA
| SEC_IS_COMMON
},
191 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
| SEC_HAS_CONTENTS
194 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
| SEC_HAS_CONTENTS
196 { NULL
, ".call_table_data",
197 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
| SEC_HAS_CONTENTS
},
198 { NULL
, ".call_table_text",
199 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_READONLY
| SEC_CODE
205 #define SDATA_SECTION 0
206 #define TDATA_SECTION 1
207 #define ZDATA_SECTION 2
208 #define SBSS_SECTION 3
209 #define TBSS_SECTION 4
210 #define ZBSS_SECTION 5
211 #define ROSDATA_SECTION 6
212 #define ROZDATA_SECTION 7
213 #define SCOMMON_SECTION 8
214 #define TCOMMON_SECTION 9
215 #define ZCOMMON_SECTION 10
216 #define CALL_TABLE_DATA_SECTION 11
217 #define CALL_TABLE_TEXT_SECTION 12
218 #define BSS_SECTION 13
221 do_v850_seg (int i
, subsegT sub
)
223 struct v850_seg_entry
*seg
= v850_seg_table
+ i
;
225 obj_elf_section_change_hook ();
228 subseg_set (seg
->s
, sub
);
231 seg
->s
= subseg_new (seg
->name
, sub
);
232 bfd_set_section_flags (stdoutput
, seg
->s
, seg
->flags
);
233 if ((seg
->flags
& SEC_LOAD
) == 0)
234 seg_info (seg
->s
)->bss
= 1;
241 subsegT sub
= get_absolute_expression ();
243 do_v850_seg (i
, sub
);
244 demand_empty_rest_of_line ();
248 v850_offset (int ignore ATTRIBUTE_UNUSED
)
251 int temp
= get_absolute_expression ();
253 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
)0, (symbolS
*)0,
254 (offsetT
) temp
, (char *) 0);
257 demand_empty_rest_of_line ();
260 /* Copied from obj_elf_common() in gas/config/obj-elf.c. */
273 name
= input_line_pointer
;
274 c
= get_symbol_end ();
276 /* Just after name is now '\0'. */
277 p
= input_line_pointer
;
282 if (*input_line_pointer
!= ',')
284 as_bad (_("Expected comma after symbol-name"));
285 ignore_rest_of_line ();
290 input_line_pointer
++;
292 if ((temp
= get_absolute_expression ()) < 0)
294 /* xgettext:c-format */
295 as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp
);
296 ignore_rest_of_line ();
302 symbolP
= symbol_find_or_make (name
);
305 if (S_IS_DEFINED (symbolP
) && ! S_IS_COMMON (symbolP
))
307 as_bad (_("Ignoring attempt to re-define symbol"));
308 ignore_rest_of_line ();
312 if (S_GET_VALUE (symbolP
) != 0)
314 if (S_GET_VALUE (symbolP
) != size
)
315 /* xgettext:c-format */
316 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
317 S_GET_NAME (symbolP
), (long) S_GET_VALUE (symbolP
), size
);
320 know (symbol_get_frag (symbolP
) == &zero_address_frag
);
322 if (*input_line_pointer
!= ',')
327 input_line_pointer
++;
331 if (! have_align
|| *input_line_pointer
!= '"')
337 temp
= get_absolute_expression ();
342 as_warn (_("Common alignment negative; 0 assumed"));
346 if (symbol_get_obj (symbolP
)->local
)
355 old_subsec
= now_subseg
;
357 applicable
= bfd_applicable_section_flags (stdoutput
);
359 applicable
&= SEC_ALLOC
;
363 case SCOMMON_SECTION
:
364 do_v850_seg (SBSS_SECTION
, 0);
367 case ZCOMMON_SECTION
:
368 do_v850_seg (ZBSS_SECTION
, 0);
371 case TCOMMON_SECTION
:
372 do_v850_seg (TBSS_SECTION
, 0);
378 /* Convert to a power of 2 alignment. */
379 for (align
= 0; (temp
& 1) == 0; temp
>>= 1, ++align
)
384 as_bad (_("Common alignment not a power of 2"));
385 ignore_rest_of_line ();
392 record_alignment (now_seg
, align
);
395 frag_align (align
, 0, 0);
399 case SCOMMON_SECTION
:
400 if (S_GET_SEGMENT (symbolP
) == v850_seg_table
[SBSS_SECTION
].s
)
401 symbol_get_frag (symbolP
)->fr_symbol
= 0;
404 case ZCOMMON_SECTION
:
405 if (S_GET_SEGMENT (symbolP
) == v850_seg_table
[ZBSS_SECTION
].s
)
406 symbol_get_frag (symbolP
)->fr_symbol
= 0;
409 case TCOMMON_SECTION
:
410 if (S_GET_SEGMENT (symbolP
) == v850_seg_table
[TBSS_SECTION
].s
)
411 symbol_get_frag (symbolP
)->fr_symbol
= 0;
418 symbol_set_frag (symbolP
, frag_now
);
419 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
,
420 (offsetT
) size
, (char *) 0);
422 S_SET_SIZE (symbolP
, size
);
426 case SCOMMON_SECTION
:
427 S_SET_SEGMENT (symbolP
, v850_seg_table
[SBSS_SECTION
].s
);
430 case ZCOMMON_SECTION
:
431 S_SET_SEGMENT (symbolP
, v850_seg_table
[ZBSS_SECTION
].s
);
434 case TCOMMON_SECTION
:
435 S_SET_SEGMENT (symbolP
, v850_seg_table
[TBSS_SECTION
].s
);
442 S_CLEAR_EXTERNAL (symbolP
);
443 obj_elf_section_change_hook ();
444 subseg_set (old_sec
, old_subsec
);
453 old_subsec
= now_subseg
;
455 S_SET_VALUE (symbolP
, (valueT
) size
);
456 S_SET_ALIGN (symbolP
, temp
);
457 S_SET_EXTERNAL (symbolP
);
461 case SCOMMON_SECTION
:
462 case ZCOMMON_SECTION
:
463 case TCOMMON_SECTION
:
464 do_v850_seg (area
, 0);
465 S_SET_SEGMENT (symbolP
, v850_seg_table
[area
].s
);
472 obj_elf_section_change_hook ();
473 subseg_set (old_sec
, old_subsec
);
478 input_line_pointer
++;
480 /* @@ Some use the dot, some don't. Can we get some consistency?? */
481 if (*input_line_pointer
== '.')
482 input_line_pointer
++;
484 /* @@ Some say data, some say bss. */
485 if (strncmp (input_line_pointer
, "bss\"", 4)
486 && strncmp (input_line_pointer
, "data\"", 5))
488 while (*--input_line_pointer
!= '"')
490 input_line_pointer
--;
491 goto bad_common_segment
;
494 while (*input_line_pointer
++ != '"')
497 goto allocate_common
;
500 symbol_get_bfdsym (symbolP
)->flags
|= BSF_OBJECT
;
502 demand_empty_rest_of_line ();
507 p
= input_line_pointer
;
508 while (*p
&& *p
!= '\n')
512 as_bad (_("bad .common segment %s"), input_line_pointer
+ 1);
514 input_line_pointer
= p
;
515 ignore_rest_of_line ();
521 set_machine (int number
)
524 bfd_set_arch_mach (stdoutput
, v850_target_arch
, machine
);
528 case 0: SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850
); break;
529 case bfd_mach_v850
: SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850
); break;
530 case bfd_mach_v850e
: SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E
); break;
531 case bfd_mach_v850e1
: SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E
); break;
532 case bfd_mach_v850e2
: SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E2
); break;
533 case bfd_mach_v850e2v3
:SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E2V3
); break;
534 case bfd_mach_v850e3v5
: SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E3V5
); break;
539 v850_longcode (int type
)
546 as_warn (_(".longcall pseudo-op seen when not relaxing"));
548 as_warn (_(".longjump pseudo-op seen when not relaxing"));
553 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
555 as_bad (_("bad .longcall format"));
556 ignore_rest_of_line ();
562 fix_new_exp (frag_now
, frag_now_fix (), 4, & ex
, 1,
563 BFD_RELOC_V850_LONGCALL
);
565 fix_new_exp (frag_now
, frag_now_fix (), 4, & ex
, 1,
566 BFD_RELOC_V850_LONGJUMP
);
568 demand_empty_rest_of_line ();
571 /* The target specific pseudo-ops which we support. */
572 const pseudo_typeS md_pseudo_table
[] =
574 { "sdata", v850_seg
, SDATA_SECTION
},
575 { "tdata", v850_seg
, TDATA_SECTION
},
576 { "zdata", v850_seg
, ZDATA_SECTION
},
577 { "sbss", v850_seg
, SBSS_SECTION
},
578 { "tbss", v850_seg
, TBSS_SECTION
},
579 { "zbss", v850_seg
, ZBSS_SECTION
},
580 { "rosdata", v850_seg
, ROSDATA_SECTION
},
581 { "rozdata", v850_seg
, ROZDATA_SECTION
},
582 { "bss", v850_seg
, BSS_SECTION
},
583 { "offset", v850_offset
, 0 },
585 { "zcomm", v850_comm
, ZCOMMON_SECTION
},
586 { "scomm", v850_comm
, SCOMMON_SECTION
},
587 { "tcomm", v850_comm
, TCOMMON_SECTION
},
588 { "v850", set_machine
, 0 },
589 { "call_table_data", v850_seg
, CALL_TABLE_DATA_SECTION
},
590 { "call_table_text", v850_seg
, CALL_TABLE_TEXT_SECTION
},
591 { "v850e", set_machine
, bfd_mach_v850e
},
592 { "v850e1", set_machine
, bfd_mach_v850e1
},
593 { "v850e2", set_machine
, bfd_mach_v850e2
},
594 { "v850e2v3", set_machine
, bfd_mach_v850e2v3
},
595 { "v850e2v4", set_machine
, bfd_mach_v850e3v5
},
596 { "v850e3v5", set_machine
, bfd_mach_v850e3v5
},
597 { "longcall", v850_longcode
, 1 },
598 { "longjump", v850_longcode
, 2 },
602 /* Opcode hash table. */
603 static struct hash_control
*v850_hash
;
605 /* This table is sorted. Suitable for searching by a binary search. */
606 static const struct reg_name pre_defined_registers
[] =
608 { "ep", 30, PROCESSOR_ALL
}, /* ep - element ptr. */
609 { "gp", 4, PROCESSOR_ALL
}, /* gp - global ptr. */
610 { "hp", 2, PROCESSOR_ALL
}, /* hp - handler stack ptr. */
611 { "lp", 31, PROCESSOR_ALL
}, /* lp - link ptr. */
612 { "r0", 0, PROCESSOR_ALL
},
613 { "r1", 1, PROCESSOR_ALL
},
614 { "r10", 10, PROCESSOR_ALL
},
615 { "r11", 11, PROCESSOR_ALL
},
616 { "r12", 12, PROCESSOR_ALL
},
617 { "r13", 13, PROCESSOR_ALL
},
618 { "r14", 14, PROCESSOR_ALL
},
619 { "r15", 15, PROCESSOR_ALL
},
620 { "r16", 16, PROCESSOR_ALL
},
621 { "r17", 17, PROCESSOR_ALL
},
622 { "r18", 18, PROCESSOR_ALL
},
623 { "r19", 19, PROCESSOR_ALL
},
624 { "r2", 2, PROCESSOR_ALL
},
625 { "r20", 20, PROCESSOR_ALL
},
626 { "r21", 21, PROCESSOR_ALL
},
627 { "r22", 22, PROCESSOR_ALL
},
628 { "r23", 23, PROCESSOR_ALL
},
629 { "r24", 24, PROCESSOR_ALL
},
630 { "r25", 25, PROCESSOR_ALL
},
631 { "r26", 26, PROCESSOR_ALL
},
632 { "r27", 27, PROCESSOR_ALL
},
633 { "r28", 28, PROCESSOR_ALL
},
634 { "r29", 29, PROCESSOR_ALL
},
635 { "r3", 3, PROCESSOR_ALL
},
636 { "r30", 30, PROCESSOR_ALL
},
637 { "r31", 31, PROCESSOR_ALL
},
638 { "r4", 4, PROCESSOR_ALL
},
639 { "r5", 5, PROCESSOR_ALL
},
640 { "r6", 6, PROCESSOR_ALL
},
641 { "r7", 7, PROCESSOR_ALL
},
642 { "r8", 8, PROCESSOR_ALL
},
643 { "r9", 9, PROCESSOR_ALL
},
644 { "sp", 3, PROCESSOR_ALL
}, /* sp - stack ptr. */
645 { "tp", 5, PROCESSOR_ALL
}, /* tp - text ptr. */
646 { "zero", 0, PROCESSOR_ALL
},
649 #define REG_NAME_CNT \
650 (sizeof (pre_defined_registers) / sizeof (struct reg_name))
652 static const struct reg_name system_registers
[] =
654 { "asid", 23, PROCESSOR_NOT_V850
},
655 { "bpam", 25, PROCESSOR_NOT_V850
},
656 { "bpav", 24, PROCESSOR_NOT_V850
},
657 { "bpc", 22, PROCESSOR_NOT_V850
},
658 { "bpdm", 27, PROCESSOR_NOT_V850
},
659 { "bpdv", 26, PROCESSOR_NOT_V850
},
660 { "bsel", 31, PROCESSOR_V850E2_UP
},
661 { "cfg", 7, PROCESSOR_V850E2V3_UP
},
662 { "ctbp", 20, PROCESSOR_NOT_V850
},
663 { "ctpc", 16, PROCESSOR_NOT_V850
},
664 { "ctpsw", 17, PROCESSOR_NOT_V850
},
665 { "dbic", 15, PROCESSOR_V850E2_UP
},
666 { "dbpc", 18, PROCESSOR_NOT_V850
},
667 { "dbpsw", 19, PROCESSOR_NOT_V850
},
668 { "dbwr", 30, PROCESSOR_V850E2_UP
},
669 { "dir", 21, PROCESSOR_NOT_V850
},
670 { "dpa0l", 16, PROCESSOR_V850E2V3_UP
},
671 { "dpa0u", 17, PROCESSOR_V850E2V3_UP
},
672 { "dpa1l", 18, PROCESSOR_V850E2V3_UP
},
673 { "dpa1u", 19, PROCESSOR_V850E2V3_UP
},
674 { "dpa2l", 20, PROCESSOR_V850E2V3_UP
},
675 { "dpa2u", 21, PROCESSOR_V850E2V3_UP
},
676 { "dpa3l", 22, PROCESSOR_V850E2V3_UP
},
677 { "dpa3u", 23, PROCESSOR_V850E2V3_UP
},
678 { "dpa4l", 24, PROCESSOR_V850E2V3_UP
},
679 { "dpa4u", 25, PROCESSOR_V850E2V3_UP
},
680 { "dpa5l", 26, PROCESSOR_V850E2V3_UP
},
681 { "dpa5u", 27, PROCESSOR_V850E2V3_UP
},
682 { "ecr", 4, PROCESSOR_ALL
},
683 { "eh_base", 3, PROCESSOR_V850E2V3_UP
},
684 { "eh_cfg", 1, PROCESSOR_V850E2V3_UP
},
685 { "eh_reset", 2, PROCESSOR_V850E2V3_UP
},
686 { "eiic", 13, PROCESSOR_V850E2_UP
},
687 { "eipc", 0, PROCESSOR_ALL
},
688 { "eipsw", 1, PROCESSOR_ALL
},
689 { "eiwr", 28, PROCESSOR_V850E2_UP
},
690 { "feic", 14, PROCESSOR_V850E2_UP
},
691 { "fepc", 2, PROCESSOR_ALL
},
692 { "fepsw", 3, PROCESSOR_ALL
},
693 { "fewr", 29, PROCESSOR_V850E2_UP
},
694 { "fpcc", 9, PROCESSOR_V850E2V3_UP
},
695 { "fpcfg", 10, PROCESSOR_V850E2V3_UP
},
696 { "fpec", 11, PROCESSOR_V850E2V3_UP
},
697 { "fpepc", 7, PROCESSOR_V850E2V3_UP
},
698 { "fpspc", 27, PROCESSOR_V850E2V3_UP
},
699 { "fpsr", 6, PROCESSOR_V850E2V3_UP
},
700 { "fpst", 8, PROCESSOR_V850E2V3_UP
},
701 { "ipa0l", 6, PROCESSOR_V850E2V3_UP
},
702 { "ipa0u", 7, PROCESSOR_V850E2V3_UP
},
703 { "ipa1l", 8, PROCESSOR_V850E2V3_UP
},
704 { "ipa1u", 9, PROCESSOR_V850E2V3_UP
},
705 { "ipa2l", 10, PROCESSOR_V850E2V3_UP
},
706 { "ipa2u", 11, PROCESSOR_V850E2V3_UP
},
707 { "ipa3l", 12, PROCESSOR_V850E2V3_UP
},
708 { "ipa3u", 13, PROCESSOR_V850E2V3_UP
},
709 { "ipa4l", 14, PROCESSOR_V850E2V3_UP
},
710 { "ipa4u", 15, PROCESSOR_V850E2V3_UP
},
711 { "mca", 24, PROCESSOR_V850E2V3_UP
},
712 { "mcc", 26, PROCESSOR_V850E2V3_UP
},
713 { "mcr", 27, PROCESSOR_V850E2V3_UP
},
714 { "mcs", 25, PROCESSOR_V850E2V3_UP
},
715 { "mpc", 1, PROCESSOR_V850E2V3_UP
},
716 { "mpm", 0, PROCESSOR_V850E2V3_UP
},
717 { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP
},
718 { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP
},
719 { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP
},
720 { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP
},
721 { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP
},
722 { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP
},
723 { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP
},
724 { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP
},
725 { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP
},
726 { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP
},
727 { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP
},
728 { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP
},
729 { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP
},
730 { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP
},
731 { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP
},
732 { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP
},
733 { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP
},
734 { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP
},
735 { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP
},
736 { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP
},
737 { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP
},
738 { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP
},
739 { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP
},
740 { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP
},
741 { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP
},
742 { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP
},
743 { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP
},
744 { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP
},
745 { "pid", 6, PROCESSOR_V850E2V3_UP
},
746 { "pmcr0", 4, PROCESSOR_V850E2V3_UP
},
747 { "pmis2", 14, PROCESSOR_V850E2V3_UP
},
748 { "psw", 5, PROCESSOR_ALL
},
749 { "scbp", 12, PROCESSOR_V850E2V3_UP
},
750 { "sccfg", 11, PROCESSOR_V850E2V3_UP
},
751 { "sr0", 0, PROCESSOR_ALL
},
752 { "sr1", 1, PROCESSOR_ALL
},
753 { "sr10", 10, PROCESSOR_ALL
},
754 { "sr11", 11, PROCESSOR_ALL
},
755 { "sr12", 12, PROCESSOR_ALL
},
756 { "sr13", 13, PROCESSOR_ALL
},
757 { "sr14", 14, PROCESSOR_ALL
},
758 { "sr15", 15, PROCESSOR_ALL
},
759 { "sr16", 16, PROCESSOR_ALL
},
760 { "sr17", 17, PROCESSOR_ALL
},
761 { "sr18", 18, PROCESSOR_ALL
},
762 { "sr19", 19, PROCESSOR_ALL
},
763 { "sr2", 2, PROCESSOR_ALL
},
764 { "sr20", 20, PROCESSOR_ALL
},
765 { "sr21", 21, PROCESSOR_ALL
},
766 { "sr22", 22, PROCESSOR_ALL
},
767 { "sr23", 23, PROCESSOR_ALL
},
768 { "sr24", 24, PROCESSOR_ALL
},
769 { "sr25", 25, PROCESSOR_ALL
},
770 { "sr26", 26, PROCESSOR_ALL
},
771 { "sr27", 27, PROCESSOR_ALL
},
772 { "sr28", 28, PROCESSOR_ALL
},
773 { "sr29", 29, PROCESSOR_ALL
},
774 { "sr3", 3, PROCESSOR_ALL
},
775 { "sr30", 30, PROCESSOR_ALL
},
776 { "sr31", 31, PROCESSOR_ALL
},
777 { "sr4", 4, PROCESSOR_ALL
},
778 { "sr5", 5, PROCESSOR_ALL
},
779 { "sr6", 6, PROCESSOR_ALL
},
780 { "sr7", 7, PROCESSOR_ALL
},
781 { "sr8", 8, PROCESSOR_ALL
},
782 { "sr9", 9, PROCESSOR_ALL
},
783 { "sw_base", 3, PROCESSOR_V850E2V3_UP
},
784 { "sw_cfg", 1, PROCESSOR_V850E2V3_UP
},
785 { "sw_ctl", 0, PROCESSOR_V850E2V3_UP
},
786 { "tid", 2, PROCESSOR_V850E2V3_UP
},
787 { "vmadr", 6, PROCESSOR_V850E2V3_UP
},
788 { "vmecr", 4, PROCESSOR_V850E2V3_UP
},
789 { "vmtid", 5, PROCESSOR_V850E2V3_UP
},
790 { "vsadr", 2, PROCESSOR_V850E2V3_UP
},
791 { "vsecr", 0, PROCESSOR_V850E2V3_UP
},
792 { "vstid", 1, PROCESSOR_V850E2V3_UP
},
795 #define SYSREG_NAME_CNT \
796 (sizeof (system_registers) / sizeof (struct reg_name))
799 static const struct reg_name cc_names
[] =
801 { "c", 0x1, PROCESSOR_ALL
},
802 { "e", 0x2, PROCESSOR_ALL
},
803 { "ge", 0xe, PROCESSOR_ALL
},
804 { "gt", 0xf, PROCESSOR_ALL
},
805 { "h", 0xb, PROCESSOR_ALL
},
806 { "l", 0x1, PROCESSOR_ALL
},
807 { "le", 0x7, PROCESSOR_ALL
},
808 { "lt", 0x6, PROCESSOR_ALL
},
809 { "n", 0x4, PROCESSOR_ALL
},
810 { "nc", 0x9, PROCESSOR_ALL
},
811 { "ne", 0xa, PROCESSOR_ALL
},
812 { "nh", 0x3, PROCESSOR_ALL
},
813 { "nl", 0x9, PROCESSOR_ALL
},
814 { "ns", 0xc, PROCESSOR_ALL
},
815 { "nv", 0x8, PROCESSOR_ALL
},
816 { "nz", 0xa, PROCESSOR_ALL
},
817 { "p", 0xc, PROCESSOR_ALL
},
818 { "s", 0x4, PROCESSOR_ALL
},
819 #define COND_SA_NUM 0xd
820 { "sa", COND_SA_NUM
, PROCESSOR_ALL
},
821 { "t", 0x5, PROCESSOR_ALL
},
822 { "v", 0x0, PROCESSOR_ALL
},
823 { "z", 0x2, PROCESSOR_ALL
},
826 #define CC_NAME_CNT \
827 (sizeof (cc_names) / sizeof (struct reg_name))
829 static const struct reg_name float_cc_names
[] =
831 { "eq", 0x2, PROCESSOR_V850E2V3_UP
}, /* true. */
832 { "f", 0x0, PROCESSOR_V850E2V3_UP
}, /* true. */
833 { "ge", 0xd, PROCESSOR_V850E2V3_UP
}, /* false. */
834 { "gl", 0xb, PROCESSOR_V850E2V3_UP
}, /* false. */
835 { "gle", 0x9, PROCESSOR_V850E2V3_UP
}, /* false. */
836 { "gt", 0xf, PROCESSOR_V850E2V3_UP
}, /* false. */
837 { "le", 0xe, PROCESSOR_V850E2V3_UP
}, /* true. */
838 { "lt", 0xc, PROCESSOR_V850E2V3_UP
}, /* true. */
839 { "neq", 0x2, PROCESSOR_V850E2V3_UP
}, /* false. */
840 { "nge", 0xd, PROCESSOR_V850E2V3_UP
}, /* true. */
841 { "ngl", 0xb, PROCESSOR_V850E2V3_UP
}, /* true. */
842 { "ngle",0x9, PROCESSOR_V850E2V3_UP
}, /* true. */
843 { "ngt", 0xf, PROCESSOR_V850E2V3_UP
}, /* true. */
844 { "nle", 0xe, PROCESSOR_V850E2V3_UP
}, /* false. */
845 { "nlt", 0xc, PROCESSOR_V850E2V3_UP
}, /* false. */
846 { "oge", 0x5, PROCESSOR_V850E2V3_UP
}, /* false. */
847 { "ogl", 0x3, PROCESSOR_V850E2V3_UP
}, /* false. */
848 { "ogt", 0x7, PROCESSOR_V850E2V3_UP
}, /* false. */
849 { "ole", 0x6, PROCESSOR_V850E2V3_UP
}, /* true. */
850 { "olt", 0x4, PROCESSOR_V850E2V3_UP
}, /* true. */
851 { "or", 0x1, PROCESSOR_V850E2V3_UP
}, /* false. */
852 { "seq", 0xa, PROCESSOR_V850E2V3_UP
}, /* true. */
853 { "sf", 0x8, PROCESSOR_V850E2V3_UP
}, /* true. */
854 { "sne", 0xa, PROCESSOR_V850E2V3_UP
}, /* false. */
855 { "st", 0x8, PROCESSOR_V850E2V3_UP
}, /* false. */
856 { "t", 0x0, PROCESSOR_V850E2V3_UP
}, /* false. */
857 { "ueq", 0x3, PROCESSOR_V850E2V3_UP
}, /* true. */
858 { "uge", 0x4, PROCESSOR_V850E2V3_UP
}, /* false. */
859 { "ugt", 0x6, PROCESSOR_V850E2V3_UP
}, /* false. */
860 { "ule", 0x7, PROCESSOR_V850E2V3_UP
}, /* true. */
861 { "ult", 0x5, PROCESSOR_V850E2V3_UP
}, /* true. */
862 { "un", 0x1, PROCESSOR_V850E2V3_UP
}, /* true. */
865 #define FLOAT_CC_NAME_CNT \
866 (sizeof (float_cc_names) / sizeof (struct reg_name))
869 static const struct reg_name cacheop_names
[] =
871 { "cfald", 0x44, PROCESSOR_V850E3V5_UP
},
872 { "cfali", 0x40, PROCESSOR_V850E3V5_UP
},
873 { "chbid", 0x04, PROCESSOR_V850E3V5_UP
},
874 { "chbii", 0x00, PROCESSOR_V850E3V5_UP
},
875 { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP
},
876 { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP
},
877 { "cibid", 0x24, PROCESSOR_V850E3V5_UP
},
878 { "cibii", 0x20, PROCESSOR_V850E3V5_UP
},
879 { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP
},
880 { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP
},
881 { "cildd", 0x65, PROCESSOR_V850E3V5_UP
},
882 { "cildi", 0x61, PROCESSOR_V850E3V5_UP
},
883 { "cistd", 0x64, PROCESSOR_V850E3V5_UP
},
884 { "cisti", 0x60, PROCESSOR_V850E3V5_UP
},
887 #define CACHEOP_NAME_CNT \
888 (sizeof (cacheop_names) / sizeof (struct reg_name))
890 static const struct reg_name prefop_names
[] =
892 { "prefd", 0x04, PROCESSOR_V850E3V5_UP
},
893 { "prefi", 0x00, PROCESSOR_V850E3V5_UP
},
896 #define PREFOP_NAME_CNT \
897 (sizeof (prefop_names) / sizeof (struct reg_name))
899 static const struct reg_name vector_registers
[] =
901 { "vr0", 0, PROCESSOR_V850E3V5_UP
},
902 { "vr1", 1, PROCESSOR_V850E3V5_UP
},
903 { "vr10", 10, PROCESSOR_V850E3V5_UP
},
904 { "vr11", 11, PROCESSOR_V850E3V5_UP
},
905 { "vr12", 12, PROCESSOR_V850E3V5_UP
},
906 { "vr13", 13, PROCESSOR_V850E3V5_UP
},
907 { "vr14", 14, PROCESSOR_V850E3V5_UP
},
908 { "vr15", 15, PROCESSOR_V850E3V5_UP
},
909 { "vr16", 16, PROCESSOR_V850E3V5_UP
},
910 { "vr17", 17, PROCESSOR_V850E3V5_UP
},
911 { "vr18", 18, PROCESSOR_V850E3V5_UP
},
912 { "vr19", 19, PROCESSOR_V850E3V5_UP
},
913 { "vr2", 2, PROCESSOR_V850E3V5_UP
},
914 { "vr20", 20, PROCESSOR_V850E3V5_UP
},
915 { "vr21", 21, PROCESSOR_V850E3V5_UP
},
916 { "vr22", 22, PROCESSOR_V850E3V5_UP
},
917 { "vr23", 23, PROCESSOR_V850E3V5_UP
},
918 { "vr24", 24, PROCESSOR_V850E3V5_UP
},
919 { "vr25", 25, PROCESSOR_V850E3V5_UP
},
920 { "vr26", 26, PROCESSOR_V850E3V5_UP
},
921 { "vr27", 27, PROCESSOR_V850E3V5_UP
},
922 { "vr28", 28, PROCESSOR_V850E3V5_UP
},
923 { "vr29", 29, PROCESSOR_V850E3V5_UP
},
924 { "vr3", 3, PROCESSOR_V850E3V5_UP
},
925 { "vr30", 30, PROCESSOR_V850E3V5_UP
},
926 { "vr31", 31, PROCESSOR_V850E3V5_UP
},
927 { "vr4", 4, PROCESSOR_V850E3V5_UP
},
928 { "vr5", 5, PROCESSOR_V850E3V5_UP
},
929 { "vr6", 6, PROCESSOR_V850E3V5_UP
},
930 { "vr7", 7, PROCESSOR_V850E3V5_UP
},
931 { "vr8", 8, PROCESSOR_V850E3V5_UP
},
932 { "vr9", 9, PROCESSOR_V850E3V5_UP
},
935 #define VREG_NAME_CNT \
936 (sizeof (vector_registers) / sizeof (struct reg_name))
938 /* Do a binary search of the given register table to see if NAME is a
939 valid regiter name. Return the register number from the array on
940 success, or -1 on failure. */
943 reg_name_search (const struct reg_name
*regs
,
946 bfd_boolean accept_numbers
)
948 int middle
, low
, high
;
952 /* If the register name is a symbol, then evaluate it. */
953 if ((symbolP
= symbol_find (name
)) != NULL
)
955 /* If the symbol is an alias for another name then use that.
956 If the symbol is an alias for a number, then return the number. */
957 if (symbol_equated_p (symbolP
))
959 = S_GET_NAME (symbol_get_value_expression (symbolP
)->X_add_symbol
);
960 else if (accept_numbers
)
962 int reg
= S_GET_VALUE (symbolP
);
966 /* Otherwise drop through and try parsing name normally. */
974 middle
= (low
+ high
) / 2;
975 cmp
= strcasecmp (name
, regs
[middle
].name
);
981 return ((regs
[middle
].processors
& processor_mask
)
989 /* Summary of register_name().
991 in: Input_line_pointer points to 1st char of operand.
994 The operand may have been a register: in this case, X_op == O_register,
995 X_add_number is set to the register number, and truth is returned.
996 Input_line_pointer->(next non-blank) char after operand, or is in
997 its original state. */
1000 register_name (expressionS
*expressionP
)
1007 /* Find the spelling of the operand. */
1008 start
= name
= input_line_pointer
;
1010 c
= get_symbol_end ();
1012 reg_number
= reg_name_search (pre_defined_registers
, REG_NAME_CNT
,
1015 /* Put back the delimiting char. */
1016 *input_line_pointer
= c
;
1018 expressionP
->X_add_symbol
= NULL
;
1019 expressionP
->X_op_symbol
= NULL
;
1021 /* Look to see if it's in the register table. */
1022 if (reg_number
>= 0)
1024 expressionP
->X_op
= O_register
;
1025 expressionP
->X_add_number
= reg_number
;
1030 /* Reset the line as if we had not done anything. */
1031 input_line_pointer
= start
;
1033 expressionP
->X_op
= O_illegal
;
1038 /* Summary of system_register_name().
1040 in: INPUT_LINE_POINTER points to 1st char of operand.
1041 EXPRESSIONP points to an expression structure to be filled in.
1042 ACCEPT_NUMBERS is true iff numerical register names may be used.
1044 out: An expressionS structure in expressionP.
1045 The operand may have been a register: in this case, X_op == O_register,
1046 X_add_number is set to the register number, and truth is returned.
1047 Input_line_pointer->(next non-blank) char after operand, or is in
1048 its original state. */
1051 system_register_name (expressionS
*expressionP
,
1052 bfd_boolean accept_numbers
)
1059 /* Find the spelling of the operand. */
1060 start
= name
= input_line_pointer
;
1062 c
= get_symbol_end ();
1063 reg_number
= reg_name_search (system_registers
, SYSREG_NAME_CNT
, name
,
1066 /* Put back the delimiting char. */
1067 *input_line_pointer
= c
;
1072 /* Reset input_line pointer. */
1073 input_line_pointer
= start
;
1075 if (ISDIGIT (*input_line_pointer
))
1077 reg_number
= strtol (input_line_pointer
, &input_line_pointer
, 0);
1081 expressionP
->X_add_symbol
= NULL
;
1082 expressionP
->X_op_symbol
= NULL
;
1084 /* Look to see if it's in the register table. */
1085 if (reg_number
>= 0)
1087 expressionP
->X_op
= O_register
;
1088 expressionP
->X_add_number
= reg_number
;
1093 /* Reset the line as if we had not done anything. */
1094 input_line_pointer
= start
;
1096 expressionP
->X_op
= O_illegal
;
1101 /* Summary of cc_name().
1103 in: INPUT_LINE_POINTER points to 1st char of operand.
1105 out: An expressionS.
1106 The operand may have been a register: in this case, X_op == O_register,
1107 X_add_number is set to the register number, and truth is returned.
1108 Input_line_pointer->(next non-blank) char after operand, or is in
1109 its original state. */
1112 cc_name (expressionS
*expressionP
,
1113 bfd_boolean accept_numbers
)
1120 /* Find the spelling of the operand. */
1121 start
= name
= input_line_pointer
;
1123 c
= get_symbol_end ();
1124 reg_number
= reg_name_search (cc_names
, CC_NAME_CNT
, name
, accept_numbers
);
1126 /* Put back the delimiting char. */
1127 *input_line_pointer
= c
;
1132 /* Reset input_line pointer. */
1133 input_line_pointer
= start
;
1135 if (ISDIGIT (*input_line_pointer
))
1137 reg_number
= strtol (input_line_pointer
, &input_line_pointer
, 0);
1141 expressionP
->X_add_symbol
= NULL
;
1142 expressionP
->X_op_symbol
= NULL
;
1144 /* Look to see if it's in the register table. */
1145 if (reg_number
>= 0)
1147 expressionP
->X_op
= O_constant
;
1148 expressionP
->X_add_number
= reg_number
;
1153 /* Reset the line as if we had not done anything. */
1154 input_line_pointer
= start
;
1156 expressionP
->X_op
= O_illegal
;
1157 expressionP
->X_add_number
= 0;
1163 float_cc_name (expressionS
*expressionP
,
1164 bfd_boolean accept_numbers
)
1171 /* Find the spelling of the operand. */
1172 start
= name
= input_line_pointer
;
1174 c
= get_symbol_end ();
1175 reg_number
= reg_name_search (float_cc_names
, FLOAT_CC_NAME_CNT
, name
, accept_numbers
);
1177 /* Put back the delimiting char. */
1178 *input_line_pointer
= c
;
1183 /* Reset input_line pointer. */
1184 input_line_pointer
= start
;
1186 if (ISDIGIT (*input_line_pointer
))
1188 reg_number
= strtol (input_line_pointer
, &input_line_pointer
, 0);
1192 expressionP
->X_add_symbol
= NULL
;
1193 expressionP
->X_op_symbol
= NULL
;
1195 /* Look to see if it's in the register table. */
1196 if (reg_number
>= 0)
1198 expressionP
->X_op
= O_constant
;
1199 expressionP
->X_add_number
= reg_number
;
1204 /* Reset the line as if we had not done anything. */
1205 input_line_pointer
= start
;
1207 expressionP
->X_op
= O_illegal
;
1208 expressionP
->X_add_number
= 0;
1214 cacheop_name (expressionS
* expressionP
,
1215 bfd_boolean accept_numbers
)
1222 /* Find the spelling of the operand. */
1223 start
= name
= input_line_pointer
;
1225 c
= get_symbol_end ();
1226 reg_number
= reg_name_search (cacheop_names
, CACHEOP_NAME_CNT
, name
, accept_numbers
);
1228 /* Put back the delimiting char. */
1229 *input_line_pointer
= c
;
1234 /* Reset input_line pointer. */
1235 input_line_pointer
= start
;
1237 if (ISDIGIT (*input_line_pointer
))
1238 reg_number
= strtol (input_line_pointer
, &input_line_pointer
, 0);
1241 expressionP
->X_add_symbol
= NULL
;
1242 expressionP
->X_op_symbol
= NULL
;
1244 /* Look to see if it's in the register table. */
1245 if (reg_number
>= 0)
1247 expressionP
->X_op
= O_constant
;
1248 expressionP
->X_add_number
= reg_number
;
1253 /* Reset the line as if we had not done anything. */
1254 input_line_pointer
= start
;
1256 expressionP
->X_op
= O_illegal
;
1257 expressionP
->X_add_number
= 0;
1263 prefop_name (expressionS
* expressionP
,
1264 bfd_boolean accept_numbers
)
1271 /* Find the spelling of the operand. */
1272 start
= name
= input_line_pointer
;
1274 c
= get_symbol_end ();
1275 reg_number
= reg_name_search (prefop_names
, PREFOP_NAME_CNT
, name
, accept_numbers
);
1277 /* Put back the delimiting char. */
1278 *input_line_pointer
= c
;
1283 /* Reset input_line pointer. */
1284 input_line_pointer
= start
;
1286 if (ISDIGIT (*input_line_pointer
))
1287 reg_number
= strtol (input_line_pointer
, &input_line_pointer
, 0);
1290 expressionP
->X_add_symbol
= NULL
;
1291 expressionP
->X_op_symbol
= NULL
;
1293 /* Look to see if it's in the register table. */
1294 if (reg_number
>= 0)
1296 expressionP
->X_op
= O_constant
;
1297 expressionP
->X_add_number
= reg_number
;
1302 /* Reset the line as if we had not done anything. */
1303 input_line_pointer
= start
;
1305 expressionP
->X_op
= O_illegal
;
1306 expressionP
->X_add_number
= 0;
1312 vector_register_name (expressionS
*expressionP
)
1319 /* Find the spelling of the operand. */
1320 start
= name
= input_line_pointer
;
1322 c
= get_symbol_end ();
1324 reg_number
= reg_name_search (vector_registers
, VREG_NAME_CNT
,
1327 /* Put back the delimiting char. */
1328 *input_line_pointer
= c
;
1330 expressionP
->X_add_symbol
= NULL
;
1331 expressionP
->X_op_symbol
= NULL
;
1333 /* Look to see if it's in the register table. */
1334 if (reg_number
>= 0)
1336 expressionP
->X_op
= O_register
;
1337 expressionP
->X_add_number
= reg_number
;
1342 /* Reset the line as if we had not done anything. */
1343 input_line_pointer
= start
;
1345 expressionP
->X_op
= O_illegal
;
1351 skip_white_space (void)
1353 while (*input_line_pointer
== ' '
1354 || *input_line_pointer
== '\t')
1355 ++input_line_pointer
;
1358 /* Summary of parse_register_list ().
1360 in: INPUT_LINE_POINTER points to 1st char of a list of registers.
1361 INSN is the partially constructed instruction.
1362 OPERAND is the operand being inserted.
1364 out: NULL if the parse completed successfully, otherwise a
1365 pointer to an error message is returned. If the parse
1366 completes the correct bit fields in the instruction
1369 Parses register lists with the syntax:
1377 and also parses constant expressions whoes bits indicate the
1378 registers in the lists. The LSB in the expression refers to
1379 the lowest numbered permissible register in the register list,
1380 and so on upwards. System registers are considered to be very
1384 parse_register_list (unsigned long *insn
,
1385 const struct v850_operand
*operand
)
1387 static int type1_regs
[32] =
1389 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1390 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
1396 /* Select a register array to parse. */
1397 switch (operand
->shift
)
1399 case 0xffe00001: regs
= type1_regs
; break;
1401 as_bad (_("unknown operand shift: %x\n"), operand
->shift
);
1402 return _("internal failure in parse_register_list");
1405 skip_white_space ();
1407 /* If the expression starts with a curly brace it is a register list.
1408 Otherwise it is a constant expression, whoes bits indicate which
1409 registers are to be included in the list. */
1410 if (*input_line_pointer
!= '{')
1417 if (exp
.X_op
!= O_constant
)
1418 return _("constant expression or register list expected");
1420 if (regs
== type1_regs
)
1422 if (exp
.X_add_number
& 0xFFFFF000)
1423 return _("high bits set in register list expression");
1425 for (reg
= 20; reg
< 32; reg
++)
1426 if (exp
.X_add_number
& (1 << (reg
- 20)))
1428 for (i
= 0; i
< 32; i
++)
1437 input_line_pointer
++;
1439 /* Parse the register list until a terminator (closing curly brace or
1440 new-line) is found. */
1443 skip_white_space ();
1445 if (register_name (&exp
))
1449 /* Locate the given register in the list, and if it is there,
1450 insert the corresponding bit into the instruction. */
1451 for (i
= 0; i
< 32; i
++)
1453 if (regs
[i
] == exp
.X_add_number
)
1461 return _("illegal register included in list");
1463 else if (system_register_name (&exp
, TRUE
))
1465 if (regs
== type1_regs
)
1467 return _("system registers cannot be included in list");
1471 if (*input_line_pointer
== '}')
1473 input_line_pointer
++;
1476 else if (*input_line_pointer
== ',')
1478 input_line_pointer
++;
1481 else if (*input_line_pointer
== '-')
1483 /* We have encountered a range of registers: rX - rY. */
1487 /* Skip the dash. */
1488 ++input_line_pointer
;
1490 /* Get the second register in the range. */
1491 if (! register_name (&exp2
))
1493 return _("second register should follow dash in register list");
1496 if (exp
.X_add_number
> exp2
.X_add_number
)
1498 return _("second register should be greater than first register");
1501 /* Add the rest of the registers in the range. */
1502 for (j
= exp
.X_add_number
+ 1; j
<= exp2
.X_add_number
; j
++)
1506 /* Locate the given register in the list, and if it is there,
1507 insert the corresponding bit into the instruction. */
1508 for (i
= 0; i
< 32; i
++)
1518 return _("illegal register included in list");
1530 const char *md_shortopts
= "m:";
1532 struct option md_longopts
[] =
1534 #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE)
1535 {"disp-size-default-22", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_22
},
1536 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1)
1537 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
1538 {NULL
, no_argument
, NULL
, 0}
1541 size_t md_longopts_size
= sizeof (md_longopts
);
1543 static bfd_boolean v850_data_8
= FALSE
;
1546 md_show_usage (FILE *stream
)
1548 fprintf (stream
, _(" V850 options:\n"));
1549 fprintf (stream
, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n"));
1550 fprintf (stream
, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
1551 fprintf (stream
, _(" -mv850 The code is targeted at the v850\n"));
1552 fprintf (stream
, _(" -mv850e The code is targeted at the v850e\n"));
1553 fprintf (stream
, _(" -mv850e1 The code is targeted at the v850e1\n"));
1554 fprintf (stream
, _(" -mv850e2 The code is targeted at the v850e2\n"));
1555 fprintf (stream
, _(" -mv850e2v3 The code is targeted at the v850e2v3\n"));
1556 fprintf (stream
, _(" -mv850e2v4 Alias for -mv850e3v5\n"));
1557 fprintf (stream
, _(" -mv850e3v5 The code is targeted at the v850e3v5\n"));
1558 fprintf (stream
, _(" -mrelax Enable relaxation\n"));
1559 fprintf (stream
, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n"));
1560 fprintf (stream
, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n"));
1561 fprintf (stream
, _(" -mextension enable extension opcode support\n"));
1562 fprintf (stream
, _(" -mno-bcond17 disable b<cond> disp17 instruction\n"));
1563 fprintf (stream
, _(" -mno-stld23 disable st/ld offset23 instruction\n"));
1564 fprintf (stream
, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n"));
1565 fprintf (stream
, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n"));
1566 fprintf (stream
, _(" -m8byte-align Mark the binary as using 64-bit alignment\n"));
1567 fprintf (stream
, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n"));
1568 fprintf (stream
, _(" -msoft-float Mark the binary as not using FP insns (default for pre e2v3)\n"));
1569 fprintf (stream
, _(" -mhard-float Mark the binary as using FP insns (default for e2v3 and up)\n"));
1573 md_parse_option (int c
, char *arg
)
1579 case OPTION_DISP_SIZE_DEFAULT_22
:
1580 default_disp_size
= 22;
1583 case OPTION_DISP_SIZE_DEFAULT_32
:
1584 default_disp_size
= 32;
1590 if (strcmp (arg
, "warn-signed-overflow") == 0)
1591 warn_signed_overflows
= TRUE
;
1593 else if (strcmp (arg
, "warn-unsigned-overflow") == 0)
1594 warn_unsigned_overflows
= TRUE
;
1596 else if (strcmp (arg
, "v850") == 0)
1599 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850
);
1601 else if (strcmp (arg
, "v850e") == 0)
1603 machine
= bfd_mach_v850e
;
1604 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E
);
1606 else if (strcmp (arg
, "v850e1") == 0)
1608 machine
= bfd_mach_v850e1
;
1609 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E1
);
1611 else if (strcmp (arg
, "v850e2") == 0)
1613 machine
= bfd_mach_v850e2
;
1614 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E2
);
1616 else if (strcmp (arg
, "v850e2v3") == 0)
1618 machine
= bfd_mach_v850e2v3
;
1619 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E2V3
);
1621 else if (strcmp (arg
, "v850e2v4") == 0)
1623 machine
= bfd_mach_v850e3v5
;
1624 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E3V5
);
1626 else if (strcmp (arg
, "v850e3v5") == 0)
1628 machine
= bfd_mach_v850e3v5
;
1629 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E3V5
);
1631 else if (strcmp (arg
, "extension") == 0)
1633 processor_mask
|= PROCESSOR_OPTION_EXTENSION
| PROCESSOR_OPTION_ALIAS
;
1635 else if (strcmp (arg
, "no-bcond17") == 0)
1639 else if (strcmp (arg
, "no-stld23") == 0)
1643 else if (strcmp (arg
, "relax") == 0)
1645 else if (strcmp (arg
, "gcc-abi") == 0)
1647 v850_target_arch
= bfd_arch_v850
;
1648 v850_target_format
= "elf32-v850";
1650 else if (strcmp (arg
, "rh850-abi") == 0)
1652 v850_target_arch
= bfd_arch_v850_rh850
;
1653 v850_target_format
= "elf32-v850-rh850";
1655 else if (strcmp (arg
, "8byte-align") == 0)
1658 v850_e_flags
|= EF_RH850_DATA_ALIGN8
;
1660 else if (strcmp (arg
, "4byte-align") == 0)
1662 v850_data_8
= FALSE
;
1663 v850_e_flags
&= ~ EF_RH850_DATA_ALIGN8
;
1665 else if (strcmp (arg
, "soft-float") == 0)
1667 else if (strcmp (arg
, "hard-float") == 0)
1676 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
1682 md_atof (int type
, char *litp
, int *sizep
)
1684 return ieee_md_atof (type
, litp
, sizep
, FALSE
);
1690 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
1696 bfd_reloc_code_real_type fx_r_type
;
1700 subseg_change (sec
, 0);
1702 opcode_converter
.fr_opcode
= fragP
->fr_opcode
;
1704 subseg_change (sec
, 0);
1706 if (fragP
->fr_subtype
== SUBYPTE_LOOP_16_22
)
1708 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
1709 fragP
->fr_offset
, 1,
1710 BFD_RELOC_UNUSED
+ opcode_converter
.fx_r_type
);
1713 else if (fragP
->fr_subtype
== SUBYPTE_LOOP_16_22
+ 1)
1715 unsigned char * buffer
=
1716 (unsigned char *) (fragP
->fr_fix
+ fragP
->fr_literal
);
1717 int loop_reg
= (buffer
[0] & 0x1f);
1720 md_number_to_chars ((char *) buffer
, 0x025f | (loop_reg
<< 11), 2);
1721 /* Now create the conditional branch + fixup to the final target. */
1722 /* 0x000107ea = bne LBL(disp17). */
1723 md_number_to_chars ((char *) buffer
+ 2, 0x000107ea, 4);
1724 fix_new (fragP
, fragP
->fr_fix
+2, 4, fragP
->fr_symbol
,
1725 fragP
->fr_offset
, 1,
1726 BFD_RELOC_V850_17_PCREL
);
1729 /* In range conditional or unconditional branch. */
1730 else if (fragP
->fr_subtype
== SUBYPTE_COND_9_22
1731 || fragP
->fr_subtype
== SUBYPTE_UNCOND_9_22
1732 || fragP
->fr_subtype
== SUBYPTE_COND_9_22_32
1733 || fragP
->fr_subtype
== SUBYPTE_UNCOND_9_22_32
1734 || fragP
->fr_subtype
== SUBYPTE_COND_9_17_22
1735 || fragP
->fr_subtype
== SUBYPTE_COND_9_17_22_32
1736 || fragP
->fr_subtype
== SUBYPTE_SA_9_22
1737 || fragP
->fr_subtype
== SUBYPTE_SA_9_22_32
1738 || fragP
->fr_subtype
== SUBYPTE_SA_9_17_22
1739 || fragP
->fr_subtype
== SUBYPTE_SA_9_17_22_32
)
1742 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
1743 fragP
->fr_offset
, 1,
1744 BFD_RELOC_UNUSED
+ opcode_converter
.fx_r_type
);
1747 /* V850e2r-v3 17bit conditional branch. */
1748 else if (fragP
->fr_subtype
== SUBYPTE_COND_9_17_22
+ 1
1749 || fragP
->fr_subtype
== SUBYPTE_COND_9_17_22_32
+ 1
1750 || fragP
->fr_subtype
== SUBYPTE_SA_9_17_22
+ 1
1751 || fragP
->fr_subtype
== SUBYPTE_SA_9_17_22_32
+ 1)
1753 unsigned char *buffer
=
1754 (unsigned char *) (fragP
->fr_fix
+ fragP
->fr_literal
);
1756 buffer
[0] &= 0x0f; /* Use condition. */
1760 /* Now create the unconditional branch + fixup to the final
1762 md_number_to_chars ((char *) buffer
+ 2, 0x0001, 2);
1763 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
1764 fragP
->fr_offset
, 1, BFD_RELOC_V850_17_PCREL
);
1767 /* Out of range conditional branch. Emit a branch around a 22bit jump. */
1768 else if (fragP
->fr_subtype
== SUBYPTE_COND_9_22
+ 1
1769 || fragP
->fr_subtype
== SUBYPTE_COND_9_22_32
+ 1
1770 || fragP
->fr_subtype
== SUBYPTE_COND_9_17_22
+ 2
1771 || fragP
->fr_subtype
== SUBYPTE_COND_9_17_22_32
+ 2)
1773 unsigned char *buffer
=
1774 (unsigned char *) (fragP
->fr_fix
+ fragP
->fr_literal
);
1776 /* Reverse the condition of the first branch. */
1778 /* Mask off all the displacement bits. */
1781 /* Now set the displacement bits so that we branch
1782 around the unconditional branch. */
1785 /* Now create the unconditional branch + fixup to the final
1787 md_number_to_chars ((char *) buffer
+ 2, 0x00000780, 4);
1788 fix_new (fragP
, fragP
->fr_fix
+ 2, 4, fragP
->fr_symbol
,
1789 fragP
->fr_offset
, 1, BFD_RELOC_V850_22_PCREL
);
1792 /* Out of range conditional branch. Emit a branch around a 32bit jump. */
1793 else if (fragP
->fr_subtype
== SUBYPTE_COND_9_22_32
+ 2
1794 || fragP
->fr_subtype
== SUBYPTE_COND_9_17_22_32
+ 3)
1796 unsigned char *buffer
=
1797 (unsigned char *) (fragP
->fr_fix
+ fragP
->fr_literal
);
1799 /* Reverse the condition of the first branch. */
1801 /* Mask off all the displacement bits. */
1804 /* Now set the displacement bits so that we branch
1805 around the unconditional branch. */
1808 /* Now create the unconditional branch + fixup to the final
1810 md_number_to_chars ((char *) buffer
+ 2, 0x02e0, 2);
1811 fix_new (fragP
, fragP
->fr_fix
+ 4, 4, fragP
->fr_symbol
,
1812 fragP
->fr_offset
+ 2, 1, BFD_RELOC_V850_32_PCREL
);
1815 /* Out of range unconditional branch. Emit a 22bit jump. */
1816 else if (fragP
->fr_subtype
== SUBYPTE_UNCOND_9_22
+ 1
1817 || fragP
->fr_subtype
== SUBYPTE_UNCOND_9_22_32
+ 1)
1819 md_number_to_chars (fragP
->fr_fix
+ fragP
->fr_literal
, 0x00000780, 4);
1820 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
1821 fragP
->fr_offset
, 1, BFD_RELOC_V850_22_PCREL
);
1824 /* Out of range unconditional branch. Emit a 32bit jump. */
1825 else if (fragP
->fr_subtype
== SUBYPTE_UNCOND_9_22_32
+ 2)
1827 md_number_to_chars (fragP
->fr_fix
+ fragP
->fr_literal
, 0x02e0, 2);
1828 fix_new (fragP
, fragP
->fr_fix
+ 4, 4, fragP
->fr_symbol
,
1829 fragP
->fr_offset
+ 2, 1, BFD_RELOC_V850_32_PCREL
);
1832 /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */
1833 else if (fragP
->fr_subtype
== SUBYPTE_SA_9_22
+ 1
1834 || fragP
->fr_subtype
== SUBYPTE_SA_9_22_32
+ 1
1835 || fragP
->fr_subtype
== SUBYPTE_SA_9_17_22
+ 2
1836 || fragP
->fr_subtype
== SUBYPTE_SA_9_17_22_32
+ 2)
1838 unsigned char *buffer
=
1839 (unsigned char *) (fragP
->fr_fix
+ fragP
->fr_literal
);
1847 md_number_to_chars ((char *) buffer
+ 2, 0x05b5, 2);
1849 /* Now create the unconditional branch + fixup to the final
1852 md_number_to_chars ((char *) buffer
+ 4, 0x00000780, 4);
1853 fix_new (fragP
, fragP
->fr_fix
+ 4, 4, fragP
->fr_symbol
,
1854 fragP
->fr_offset
, 1,
1855 BFD_RELOC_V850_22_PCREL
);
1858 /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */
1859 else if (fragP
->fr_subtype
== SUBYPTE_SA_9_22_32
+ 2
1860 || fragP
->fr_subtype
== SUBYPTE_SA_9_17_22_32
+ 3)
1862 unsigned char *buffer
=
1863 (unsigned char *) (fragP
->fr_fix
+ fragP
->fr_literal
);
1871 md_number_to_chars ((char *) buffer
+ 2, 0x05c5, 2);
1873 /* Now create the unconditional branch + fixup to the final
1876 md_number_to_chars ((char *) buffer
+ 4, 0x02e0, 2);
1877 fix_new (fragP
, fragP
->fr_fix
+ 6, 4, fragP
->fr_symbol
,
1878 fragP
->fr_offset
+ 2, 1, BFD_RELOC_V850_32_PCREL
);
1880 fragP
->fr_fix
+= 10;
1887 md_section_align (asection
*seg
, valueT addr
)
1889 int align
= bfd_get_section_alignment (stdoutput
, seg
);
1890 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
1896 char *prev_name
= "";
1897 const struct v850_opcode
*op
;
1899 if (strncmp (TARGET_CPU
, "v850e3v5", 8) == 0)
1902 machine
= bfd_mach_v850e3v5
;
1904 if (!processor_mask
)
1905 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E3V5
);
1907 else if (strncmp (TARGET_CPU
, "v850e2v4", 8) == 0)
1910 machine
= bfd_mach_v850e3v5
;
1912 if (!processor_mask
)
1913 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E3V5
);
1915 else if (strncmp (TARGET_CPU
, "v850e2v3", 8) == 0)
1918 machine
= bfd_mach_v850e2v3
;
1920 if (!processor_mask
)
1921 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E2V3
);
1923 else if (strncmp (TARGET_CPU
, "v850e2", 6) == 0)
1926 machine
= bfd_mach_v850e2
;
1928 if (!processor_mask
)
1929 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E2
);
1931 else if (strncmp (TARGET_CPU
, "v850e1", 6) == 0)
1934 machine
= bfd_mach_v850e1
;
1936 if (!processor_mask
)
1937 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E1
);
1939 else if (strncmp (TARGET_CPU
, "v850e", 5) == 0)
1942 machine
= bfd_mach_v850e
;
1944 if (!processor_mask
)
1945 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850E
);
1947 else if (strncmp (TARGET_CPU
, "v850", 4) == 0)
1952 if (!processor_mask
)
1953 SET_PROCESSOR_MASK (processor_mask
, PROCESSOR_V850
);
1956 /* xgettext:c-format */
1957 as_bad (_("Unable to determine default target processor from string: %s"),
1960 if (soft_float
== -1)
1961 soft_float
= machine
< bfd_mach_v850e2v3
;
1963 v850_hash
= hash_new ();
1965 /* Insert unique names into hash table. The V850 instruction set
1966 has many identical opcode names that have different opcodes based
1967 on the operands. This hash table then provides a quick index to
1968 the first opcode with a particular name in the opcode table. */
1972 if (strcmp (prev_name
, op
->name
))
1974 prev_name
= (char *) op
->name
;
1975 hash_insert (v850_hash
, op
->name
, (char *) op
);
1980 v850_seg_table
[BSS_SECTION
].s
= bss_section
;
1981 bfd_set_arch_mach (stdoutput
, v850_target_arch
, machine
);
1982 bfd_set_private_flags (stdoutput
, v850_e_flags
);
1986 static bfd_reloc_code_real_type
1987 handle_hi016 (const struct v850_operand
*operand
, const char **errmsg
)
1989 if (operand
== NULL
)
1990 return BFD_RELOC_HI16
;
1992 if (operand
->default_reloc
== BFD_RELOC_HI16
)
1993 return BFD_RELOC_HI16
;
1995 if (operand
->default_reloc
== BFD_RELOC_HI16_S
)
1996 return BFD_RELOC_HI16
;
1998 if (operand
->default_reloc
== BFD_RELOC_16
)
1999 return BFD_RELOC_HI16
;
2001 *errmsg
= _("hi0() relocation used on an instruction which does "
2003 return BFD_RELOC_64
; /* Used to indicate an error condition. */
2006 static bfd_reloc_code_real_type
2007 handle_hi16 (const struct v850_operand
*operand
, const char **errmsg
)
2009 if (operand
== NULL
)
2010 return BFD_RELOC_HI16_S
;
2012 if (operand
->default_reloc
== BFD_RELOC_HI16_S
)
2013 return BFD_RELOC_HI16_S
;
2015 if (operand
->default_reloc
== BFD_RELOC_HI16
)
2016 return BFD_RELOC_HI16_S
;
2018 if (operand
->default_reloc
== BFD_RELOC_16
)
2019 return BFD_RELOC_HI16_S
;
2021 *errmsg
= _("hi() relocation used on an instruction which does "
2023 return BFD_RELOC_64
; /* Used to indicate an error condition. */
2026 static bfd_reloc_code_real_type
2027 handle_lo16 (const struct v850_operand
*operand
, const char **errmsg
)
2029 if (operand
== NULL
)
2030 return BFD_RELOC_LO16
;
2032 if (operand
->default_reloc
== BFD_RELOC_LO16
)
2033 return BFD_RELOC_LO16
;
2035 if (operand
->default_reloc
== BFD_RELOC_V850_16_SPLIT_OFFSET
)
2036 return BFD_RELOC_V850_LO16_SPLIT_OFFSET
;
2038 if (operand
->default_reloc
== BFD_RELOC_V850_16_S1
)
2039 return BFD_RELOC_V850_LO16_S1
;
2041 if (operand
->default_reloc
== BFD_RELOC_16
)
2042 return BFD_RELOC_LO16
;
2044 *errmsg
= _("lo() relocation used on an instruction which does "
2046 return BFD_RELOC_64
; /* Used to indicate an error condition. */
2049 static bfd_reloc_code_real_type
2050 handle_ctoff (const struct v850_operand
*operand
, const char **errmsg
)
2052 if (v850_target_arch
== bfd_arch_v850_rh850
)
2054 *errmsg
= _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead");
2055 return BFD_RELOC_64
; /* Used to indicate an error condition. */
2058 if (operand
== NULL
)
2059 return BFD_RELOC_V850_CALLT_16_16_OFFSET
;
2061 if (operand
->default_reloc
== BFD_RELOC_V850_CALLT_6_7_OFFSET
)
2062 return operand
->default_reloc
;
2064 if (operand
->default_reloc
== BFD_RELOC_V850_16_S1
)
2065 return BFD_RELOC_V850_CALLT_15_16_OFFSET
;
2067 if (operand
->default_reloc
== BFD_RELOC_16
)
2068 return BFD_RELOC_V850_CALLT_16_16_OFFSET
;
2070 *errmsg
= _("ctoff() relocation used on an instruction which does not support it");
2071 return BFD_RELOC_64
; /* Used to indicate an error condition. */
2074 static bfd_reloc_code_real_type
2075 handle_sdaoff (const struct v850_operand
*operand
, const char **errmsg
)
2077 if (operand
== NULL
)
2078 return BFD_RELOC_V850_SDA_16_16_OFFSET
;
2080 if (operand
->default_reloc
== BFD_RELOC_V850_16_SPLIT_OFFSET
)
2081 return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
;
2083 if (operand
->default_reloc
== BFD_RELOC_16
)
2084 return BFD_RELOC_V850_SDA_16_16_OFFSET
;
2086 if (operand
->default_reloc
== BFD_RELOC_V850_16_S1
)
2087 return BFD_RELOC_V850_SDA_15_16_OFFSET
;
2089 *errmsg
= _("sdaoff() relocation used on an instruction which does not support it");
2090 return BFD_RELOC_64
; /* Used to indicate an error condition. */
2093 static bfd_reloc_code_real_type
2094 handle_zdaoff (const struct v850_operand
*operand
, const char **errmsg
)
2096 if (operand
== NULL
)
2097 return BFD_RELOC_V850_ZDA_16_16_OFFSET
;
2099 if (operand
->default_reloc
== BFD_RELOC_V850_16_SPLIT_OFFSET
)
2100 return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
;
2102 if (operand
->default_reloc
== BFD_RELOC_16
)
2103 return BFD_RELOC_V850_ZDA_16_16_OFFSET
;
2105 if (operand
->default_reloc
== BFD_RELOC_V850_16_S1
)
2106 return BFD_RELOC_V850_ZDA_15_16_OFFSET
;
2108 *errmsg
= _("zdaoff() relocation used on an instruction which does not support it");
2109 return BFD_RELOC_64
; /* Used to indicate an error condition. */
2112 static bfd_reloc_code_real_type
2113 handle_tdaoff (const struct v850_operand
*operand
, const char **errmsg
)
2115 if (operand
== NULL
)
2116 /* Data item, not an instruction. */
2117 return BFD_RELOC_V850_TDA_16_16_OFFSET
;
2119 switch (operand
->default_reloc
)
2121 /* sld.hu, operand: D5-4. */
2122 case BFD_RELOC_V850_TDA_4_5_OFFSET
:
2123 /* sld.bu, operand: D4. */
2124 case BFD_RELOC_V850_TDA_4_4_OFFSET
:
2125 /* sld.w/sst.w, operand: D8_6. */
2126 case BFD_RELOC_V850_TDA_6_8_OFFSET
:
2127 /* sld.h/sst.h, operand: D8_7. */
2128 case BFD_RELOC_V850_TDA_7_8_OFFSET
:
2129 /* sld.b/sst.b, operand: D7. */
2130 case BFD_RELOC_V850_TDA_7_7_OFFSET
:
2131 return operand
->default_reloc
;
2136 if (operand
->default_reloc
== BFD_RELOC_16
&& operand
->shift
== 16)
2137 /* set1 & chums, operands: D16. */
2138 return BFD_RELOC_V850_TDA_16_16_OFFSET
;
2140 *errmsg
= _("tdaoff() relocation used on an instruction which does not support it");
2141 /* Used to indicate an error condition. */
2142 return BFD_RELOC_64
;
2145 /* Warning: The code in this function relies upon the definitions
2146 in the v850_operands[] array (defined in opcodes/v850-opc.c)
2147 matching the hard coded values contained herein. */
2149 static bfd_reloc_code_real_type
2150 v850_reloc_prefix (const struct v850_operand
*operand
, const char **errmsg
)
2152 bfd_boolean paren_skipped
= FALSE
;
2154 /* Skip leading opening parenthesis. */
2155 if (*input_line_pointer
== '(')
2157 ++input_line_pointer
;
2158 paren_skipped
= TRUE
;
2161 #define CHECK_(name, reloc) \
2162 if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \
2164 input_line_pointer += strlen (name); \
2168 CHECK_ ("hi0", handle_hi016(operand
, errmsg
) );
2169 CHECK_ ("hi", handle_hi16(operand
, errmsg
) );
2170 CHECK_ ("lo", handle_lo16 (operand
, errmsg
) );
2171 CHECK_ ("sdaoff", handle_sdaoff (operand
, errmsg
));
2172 CHECK_ ("zdaoff", handle_zdaoff (operand
, errmsg
));
2173 CHECK_ ("tdaoff", handle_tdaoff (operand
, errmsg
));
2174 CHECK_ ("hilo", BFD_RELOC_32
);
2175 CHECK_ ("lo23", BFD_RELOC_V850_23
);
2176 CHECK_ ("ctoff", handle_ctoff (operand
, errmsg
) );
2178 /* Restore skipped parenthesis. */
2180 --input_line_pointer
;
2182 return BFD_RELOC_NONE
;
2185 /* Insert an operand value into an instruction. */
2187 static unsigned long
2188 v850_insert_operand (unsigned long insn
,
2189 const struct v850_operand
*operand
,
2191 const char **errmsg
)
2193 if (operand
->insert
)
2195 const char *message
= NULL
;
2197 insn
= operand
->insert (insn
, val
, &message
);
2198 if (message
!= NULL
)
2200 if ((operand
->flags
& V850_OPERAND_SIGNED
)
2201 && ! warn_signed_overflows
2202 && v850_msg_is_out_of_range (message
))
2204 /* Skip warning... */
2206 else if ((operand
->flags
& V850_OPERAND_SIGNED
) == 0
2207 && ! warn_unsigned_overflows
2208 && v850_msg_is_out_of_range (message
))
2210 /* Skip warning... */
2219 else if (operand
->bits
== -1
2220 || operand
->flags
& V850E_IMMEDIATE16
2221 || operand
->flags
& V850E_IMMEDIATE23
2222 || operand
->flags
& V850E_IMMEDIATE32
)
2228 if (operand
->bits
< 32)
2232 if ((operand
->flags
& V850_OPERAND_SIGNED
) != 0)
2234 if (! warn_signed_overflows
)
2235 max
= (1 << operand
->bits
) - 1;
2237 max
= (1 << (operand
->bits
- 1)) - 1;
2239 min
= -(1 << (operand
->bits
- 1));
2243 max
= (1 << operand
->bits
) - 1;
2245 if (! warn_unsigned_overflows
)
2246 min
= -(1 << (operand
->bits
- 1));
2251 /* Some people write constants with the sign extension done by
2252 hand but only up to 32 bits. This shouldn't really be valid,
2253 but, to permit this code to assemble on a 64-bit host, we
2254 sign extend the 32-bit value to 64 bits if so doing makes the
2257 && (offsetT
) (val
- 0x80000000 - 0x80000000) >= min
2258 && (offsetT
) (val
- 0x80000000 - 0x80000000) <= max
)
2259 val
= val
- 0x80000000 - 0x80000000;
2261 /* Similarly, people write expressions like ~(1<<15), and expect
2262 this to be OK for a 32-bit unsigned value. */
2264 && (offsetT
) (val
+ 0x80000000 + 0x80000000) >= min
2265 && (offsetT
) (val
+ 0x80000000 + 0x80000000) <= max
)
2266 val
= val
+ 0x80000000 + 0x80000000;
2268 else if (val
< (offsetT
) min
|| val
> (offsetT
) max
)
2270 static char buf
[128];
2272 /* Restore min and mix to expected values for decimal ranges. */
2273 if ((operand
->flags
& V850_OPERAND_SIGNED
)
2274 && ! warn_signed_overflows
)
2275 max
= (1 << (operand
->bits
- 1)) - 1;
2277 if (! (operand
->flags
& V850_OPERAND_SIGNED
)
2278 && ! warn_unsigned_overflows
)
2281 sprintf (buf
, _("operand out of range (%d is not between %d and %d)"),
2282 (int) val
, (int) min
, (int) max
);
2286 insn
|= (((long) val
& ((1 << operand
->bits
) - 1)) << operand
->shift
);
2290 insn
|= (((long) val
) << operand
->shift
);
2297 static char copy_of_instruction
[128];
2300 md_assemble (char *str
)
2303 char *start_of_operands
;
2304 struct v850_opcode
*opcode
;
2305 struct v850_opcode
*next_opcode
;
2306 const unsigned char *opindex_ptr
;
2310 unsigned long insn_size
;
2314 bfd_boolean extra_data_after_insn
= FALSE
;
2315 unsigned extra_data_len
= 0;
2316 unsigned long extra_data
= 0;
2317 char *saved_input_line_pointer
;
2318 char most_match_errmsg
[1024];
2319 int most_match_count
= -1;
2321 strncpy (copy_of_instruction
, str
, sizeof (copy_of_instruction
) - 1);
2322 most_match_errmsg
[0] = 0;
2324 /* Get the opcode. */
2325 for (s
= str
; *s
!= '\0' && ! ISSPACE (*s
); s
++)
2331 /* Find the first opcode with the proper name. */
2332 opcode
= (struct v850_opcode
*) hash_find (v850_hash
, str
);
2335 /* xgettext:c-format */
2336 as_bad (_("Unrecognized opcode: `%s'"), str
);
2337 ignore_rest_of_line ();
2342 while (ISSPACE (*str
))
2345 start_of_operands
= str
;
2347 saved_input_line_pointer
= input_line_pointer
;
2351 const char *errmsg
= NULL
;
2352 const char *warningmsg
= NULL
;
2355 opindex_ptr
= opcode
->operands
;
2359 if ((strncmp (opcode
->name
, "st.", 3) == 0
2360 && v850_operands
[opcode
->operands
[1]].bits
== 23)
2361 || (strncmp (opcode
->name
, "ld.", 3) == 0
2362 && v850_operands
[opcode
->operands
[0]].bits
== 23))
2364 errmsg
= _("st/ld offset 23 instruction was disabled .");
2369 if ((opcode
->processors
& processor_mask
& PROCESSOR_MASK
) == 0
2370 || (((opcode
->processors
& ~PROCESSOR_MASK
) != 0)
2371 && ((opcode
->processors
& processor_mask
& ~PROCESSOR_MASK
) == 0)))
2373 errmsg
= _("Target processor does not support this instruction.");
2380 insn
= opcode
->opcode
;
2382 extra_data_after_insn
= FALSE
;
2384 input_line_pointer
= str
= start_of_operands
;
2386 for (opindex_ptr
= opcode
->operands
; *opindex_ptr
!= 0; opindex_ptr
++)
2388 const struct v850_operand
*operand
;
2391 bfd_reloc_code_real_type reloc
;
2393 if (next_opindex
== 0)
2394 operand
= &v850_operands
[*opindex_ptr
];
2397 operand
= &v850_operands
[next_opindex
];
2406 if (operand
->flags
& V850_OPERAND_BANG
2409 else if (operand
->flags
& V850_OPERAND_PERCENT
2413 if (*str
== ',' || *str
== '[' || *str
== ']')
2419 if ( (strcmp (opcode
->name
, "pushsp") == 0
2420 || strcmp (opcode
->name
, "popsp") == 0
2421 || strcmp (opcode
->name
, "dbpush") == 0)
2425 if (operand
->flags
& V850_OPERAND_RELAX
)
2428 /* Gather the operand. */
2429 hold
= input_line_pointer
;
2430 input_line_pointer
= str
;
2432 /* lo(), hi(), hi0(), etc... */
2433 if ((reloc
= v850_reloc_prefix (operand
, &errmsg
)) != BFD_RELOC_NONE
)
2435 /* This is a fake reloc, used to indicate an error condition. */
2436 if (reloc
== BFD_RELOC_64
)
2444 if (ex
.X_op
== O_constant
)
2448 case BFD_RELOC_V850_ZDA_16_16_OFFSET
:
2449 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
:
2450 case BFD_RELOC_V850_ZDA_15_16_OFFSET
:
2451 /* To cope with "not1 7, zdaoff(0xfffff006)[r0]"
2455 case BFD_RELOC_LO16
:
2456 case BFD_RELOC_V850_LO16_S1
:
2457 case BFD_RELOC_V850_LO16_SPLIT_OFFSET
:
2459 /* Truncate, then sign extend the value. */
2460 ex
.X_add_number
= SEXT16 (ex
.X_add_number
);
2464 case BFD_RELOC_HI16
:
2466 /* Truncate, then sign extend the value. */
2467 ex
.X_add_number
= SEXT16 (ex
.X_add_number
>> 16);
2471 case BFD_RELOC_HI16_S
:
2473 /* Truncate, then sign extend the value. */
2474 int temp
= (ex
.X_add_number
>> 16) & 0xffff;
2476 temp
+= (ex
.X_add_number
>> 15) & 1;
2478 ex
.X_add_number
= SEXT16 (temp
);
2482 case BFD_RELOC_V850_23
:
2483 if ((operand
->flags
& V850E_IMMEDIATE23
) == 0)
2485 errmsg
= _("immediate operand is too large");
2491 case BFD_RELOC_V850_32_ABS
:
2492 case BFD_RELOC_V850_32_PCREL
:
2493 if ((operand
->flags
& V850E_IMMEDIATE32
) == 0)
2495 errmsg
= _("immediate operand is too large");
2502 as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc
);
2506 if (operand
->flags
& V850E_IMMEDIATE32
)
2508 extra_data_after_insn
= TRUE
;
2512 else if (operand
->flags
& V850E_IMMEDIATE23
)
2514 if (reloc
!= BFD_RELOC_V850_23
)
2516 errmsg
= _("immediate operand is too large");
2519 extra_data_after_insn
= TRUE
;
2523 else if ((operand
->flags
& V850E_IMMEDIATE16
)
2524 || (operand
->flags
& V850E_IMMEDIATE16HI
))
2526 if (operand
->flags
& V850E_IMMEDIATE16HI
2527 && reloc
!= BFD_RELOC_HI16
2528 && reloc
!= BFD_RELOC_HI16_S
)
2530 errmsg
= _("immediate operand is too large");
2533 else if (operand
->flags
& V850E_IMMEDIATE16
2534 && reloc
!= BFD_RELOC_LO16
)
2536 errmsg
= _("immediate operand is too large");
2540 extra_data_after_insn
= TRUE
;
2545 if (fc
> MAX_INSN_FIXUPS
)
2546 as_fatal (_("too many fixups"));
2548 fixups
[fc
].exp
= ex
;
2549 fixups
[fc
].opindex
= *opindex_ptr
;
2550 fixups
[fc
].reloc
= reloc
;
2553 else /* ex.X_op != O_constant. */
2555 if ((reloc
== BFD_RELOC_32
2556 || reloc
== BFD_RELOC_V850_32_ABS
2557 || reloc
== BFD_RELOC_V850_32_PCREL
)
2558 && operand
->bits
< 32)
2560 errmsg
= _("immediate operand is too large");
2563 else if (reloc
== BFD_RELOC_V850_23
2564 && (operand
->flags
& V850E_IMMEDIATE23
) == 0)
2566 errmsg
= _("immediate operand is too large");
2569 else if ((reloc
== BFD_RELOC_HI16
2570 || reloc
== BFD_RELOC_HI16_S
)
2571 && operand
->bits
< 16)
2573 errmsg
= _("immediate operand is too large");
2577 if (operand
->flags
& V850E_IMMEDIATE32
)
2579 extra_data_after_insn
= TRUE
;
2583 else if (operand
->flags
& V850E_IMMEDIATE23
)
2585 if (reloc
!= BFD_RELOC_V850_23
)
2587 errmsg
= _("immediate operand is too large");
2590 extra_data_after_insn
= TRUE
;
2594 else if ((operand
->flags
& V850E_IMMEDIATE16
)
2595 || (operand
->flags
& V850E_IMMEDIATE16HI
))
2597 if (operand
->flags
& V850E_IMMEDIATE16HI
2598 && reloc
!= BFD_RELOC_HI16
2599 && reloc
!= BFD_RELOC_HI16_S
)
2601 errmsg
= _("immediate operand is too large");
2604 else if (operand
->flags
& V850E_IMMEDIATE16
2605 && reloc
!= BFD_RELOC_LO16
)
2607 errmsg
= _("immediate operand is too large");
2611 extra_data_after_insn
= TRUE
;
2616 if (fc
> MAX_INSN_FIXUPS
)
2617 as_fatal (_("too many fixups"));
2619 fixups
[fc
].exp
= ex
;
2620 fixups
[fc
].opindex
= *opindex_ptr
;
2621 fixups
[fc
].reloc
= reloc
;
2625 else if (operand
->flags
& V850E_IMMEDIATE16
2626 || operand
->flags
& V850E_IMMEDIATE16HI
)
2633 if (operand
->flags
& V850E_IMMEDIATE16HI
)
2635 if (ex
.X_add_number
& 0xffff)
2637 errmsg
= _("constant too big to fit into instruction");
2641 ex
.X_add_number
>>= 16;
2643 if (operand
->flags
& V850E_IMMEDIATE16
)
2645 if ((ex
.X_add_number
& 0xffff8000)
2646 && ((ex
.X_add_number
& 0xffff8000) != 0xffff8000))
2648 errmsg
= _("constant too big to fit into instruction");
2655 errmsg
= _("illegal operand");
2659 errmsg
= _("missing operand");
2663 if (fc
>= MAX_INSN_FIXUPS
)
2664 as_fatal (_("too many fixups"));
2666 fixups
[fc
].exp
= ex
;
2667 fixups
[fc
].opindex
= *opindex_ptr
;
2668 fixups
[fc
].reloc
= operand
->default_reloc
;
2671 ex
.X_add_number
= 0;
2675 extra_data_after_insn
= TRUE
;
2677 extra_data
= ex
.X_add_number
;
2679 else if (operand
->flags
& V850E_IMMEDIATE23
)
2689 errmsg
= _("illegal operand");
2693 errmsg
= _("missing operand");
2700 if (fc
>= MAX_INSN_FIXUPS
)
2701 as_fatal (_("too many fixups"));
2703 fixups
[fc
].exp
= ex
;
2704 fixups
[fc
].opindex
= *opindex_ptr
;
2705 fixups
[fc
].reloc
= operand
->default_reloc
;
2708 extra_data_after_insn
= TRUE
;
2712 else if (operand
->flags
& V850E_IMMEDIATE32
)
2719 if ((operand
->default_reloc
== BFD_RELOC_V850_32_ABS
2720 || operand
->default_reloc
== BFD_RELOC_V850_32_PCREL
)
2721 && (ex
.X_add_number
& 1))
2723 errmsg
= _("odd number cannot be used here");
2729 errmsg
= _("illegal operand");
2733 errmsg
= _("missing operand");
2737 if (fc
>= MAX_INSN_FIXUPS
)
2738 as_fatal (_("too many fixups"));
2740 fixups
[fc
].exp
= ex
;
2741 fixups
[fc
].opindex
= *opindex_ptr
;
2742 fixups
[fc
].reloc
= operand
->default_reloc
;
2745 ex
.X_add_number
= 0;
2749 extra_data_after_insn
= TRUE
;
2751 extra_data
= ex
.X_add_number
;
2753 else if (operand
->flags
& V850E_OPERAND_REG_LIST
)
2755 errmsg
= parse_register_list (&insn
, operand
);
2764 if ((operand
->flags
& V850_OPERAND_REG
) != 0)
2766 if (!register_name (&ex
))
2768 errmsg
= _("invalid register name");
2771 if ((operand
->flags
& V850_NOT_R0
)
2772 && ex
.X_add_number
== 0)
2774 errmsg
= _("register r0 cannot be used here");
2777 if (operand
->flags
& V850_REG_EVEN
)
2779 if (ex
.X_add_number
% 2)
2780 errmsg
= _("odd register cannot be used here");
2781 ex
.X_add_number
= ex
.X_add_number
/ 2;
2785 else if ((operand
->flags
& V850_OPERAND_SRG
) != 0)
2787 if (!system_register_name (&ex
, TRUE
))
2789 errmsg
= _("invalid system register name");
2792 else if ((operand
->flags
& V850_OPERAND_EP
) != 0)
2794 char *start
= input_line_pointer
;
2795 char c
= get_symbol_end ();
2797 if (strcmp (start
, "ep") != 0 && strcmp (start
, "r30") != 0)
2799 /* Put things back the way we found them. */
2800 *input_line_pointer
= c
;
2801 input_line_pointer
= start
;
2802 errmsg
= _("expected EP register");
2806 *input_line_pointer
= c
;
2807 str
= input_line_pointer
;
2808 input_line_pointer
= hold
;
2810 while (*str
== ' ' || *str
== ','
2811 || *str
== '[' || *str
== ']')
2815 else if ((operand
->flags
& V850_OPERAND_CC
) != 0)
2817 if (!cc_name (&ex
, TRUE
))
2819 errmsg
= _("invalid condition code name");
2822 if ((operand
->flags
& V850_NOT_SA
)
2823 && ex
.X_add_number
== COND_SA_NUM
)
2825 errmsg
= _("condition sa cannot be used here");
2828 else if ((operand
->flags
& V850_OPERAND_FLOAT_CC
) != 0)
2830 if (!float_cc_name (&ex
, TRUE
))
2832 errmsg
= _("invalid condition code name");
2835 else if ((operand
->flags
& V850_OPERAND_CACHEOP
) != 0)
2837 if (!cacheop_name (&ex
, TRUE
))
2838 errmsg
= _("invalid cache oparation name");
2840 else if ((operand
->flags
& V850_OPERAND_PREFOP
) != 0)
2842 if (!prefop_name (&ex
, TRUE
))
2843 errmsg
= _("invalid pref oparation name");
2845 else if ((operand
->flags
& V850_OPERAND_VREG
) != 0)
2847 if (!vector_register_name (&ex
))
2848 errmsg
= _("invalid vector register name");
2850 else if ((register_name (&ex
)
2851 && (operand
->flags
& V850_OPERAND_REG
) == 0))
2856 /* It is possible that an alias has been defined that
2857 matches a register name. For example the code may
2858 include a ".set ZERO, 0" directive, which matches
2859 the register name "zero". Attempt to reparse the
2860 field as an expression, and only complain if we
2861 cannot generate a constant. */
2863 input_line_pointer
= str
;
2865 c
= get_symbol_end ();
2867 if (symbol_find (str
) != NULL
)
2870 *input_line_pointer
= c
;
2871 input_line_pointer
= str
;
2875 if (ex
.X_op
!= O_constant
)
2877 /* If this register is actually occurring too early on
2878 the parsing of the instruction, (because another
2879 field is missing) then report this. */
2880 if (opindex_ptr
[1] != 0
2881 && ((v850_operands
[opindex_ptr
[1]].flags
2883 ||(v850_operands
[opindex_ptr
[1]].flags
2884 & V850_OPERAND_VREG
)))
2885 errmsg
= _("syntax error: value is missing before the register name");
2887 errmsg
= _("syntax error: register not expected");
2889 /* If we created a symbol in the process of this
2890 test then delete it now, so that it will not
2891 be output with the real symbols... */
2893 && ex
.X_op
== O_symbol
)
2894 symbol_remove (ex
.X_add_symbol
,
2895 &symbol_rootP
, &symbol_lastP
);
2898 else if (system_register_name (&ex
, FALSE
)
2899 && (operand
->flags
& V850_OPERAND_SRG
) == 0)
2901 errmsg
= _("syntax error: system register not expected");
2903 else if (cc_name (&ex
, FALSE
)
2904 && (operand
->flags
& V850_OPERAND_CC
) == 0)
2906 errmsg
= _("syntax error: condition code not expected");
2908 else if (float_cc_name (&ex
, FALSE
)
2909 && (operand
->flags
& V850_OPERAND_FLOAT_CC
) == 0)
2911 errmsg
= _("syntax error: condition code not expected");
2913 else if (vector_register_name (&ex
)
2914 && (operand
->flags
& V850_OPERAND_VREG
) == 0)
2916 errmsg
= _("syntax error: vector register not expected");
2922 if ((operand
->flags
& V850_NOT_IMM0
)
2923 && ex
.X_op
== O_constant
2924 && ex
.X_add_number
== 0)
2926 errmsg
= _("immediate 0 cannot be used here");
2930 If we are assembling a MOV/JARL/JR instruction and the immediate
2931 value does not fit into the bits available then create a
2932 fake error so that the next MOV/JARL/JR instruction will be
2933 selected. This one has a 32 bit immediate field. */
2935 if ((strcmp (opcode
->name
, "mov") == 0
2936 || strcmp (opcode
->name
, "jarl") == 0
2937 || strcmp (opcode
->name
, "jr") == 0)
2938 && ex
.X_op
== O_constant
2939 && (ex
.X_add_number
< (-(1 << (operand
->bits
- 1)))
2940 || ex
.X_add_number
> ((1 << (operand
->bits
- 1)) - 1)))
2942 errmsg
= _("immediate operand is too large");
2945 if ((strcmp (opcode
->name
, "jarl") == 0
2946 || strcmp (opcode
->name
, "jr") == 0)
2947 && ex
.X_op
!= O_constant
2948 && operand
->bits
!= default_disp_size
)
2950 errmsg
= _("immediate operand is not match");
2954 If we are assembling a ld/st instruction and the immediate
2955 value does not fit into the bits available then create a
2956 fake error so that the next ld/st instruction will be
2958 if ( ( (strncmp (opcode
->name
, "st.", 3) == 0)
2959 || (strncmp (opcode
->name
, "ld.", 3) == 0))
2960 && ex
.X_op
== O_constant
2961 && (ex
.X_add_number
< (-(1 << (operand
->bits
- 1)))
2962 || ex
.X_add_number
> ((1 << (operand
->bits
- 1)) - 1)))
2963 errmsg
= _("displacement is too large");
2972 errmsg
= _("illegal operand");
2975 errmsg
= _("missing operand");
2979 & (V850_OPERAND_REG
| V850_OPERAND_SRG
| V850_OPERAND_VREG
)) == 0)
2981 errmsg
= _("invalid operand");
2985 insn
= v850_insert_operand (insn
, operand
,
2992 insn
= v850_insert_operand (insn
, operand
, ex
.X_add_number
,
2997 /* We need to generate a fixup for this expression. */
2998 if (fc
>= MAX_INSN_FIXUPS
)
2999 as_fatal (_("too many fixups"));
3001 fixups
[fc
].exp
= ex
;
3002 fixups
[fc
].opindex
= *opindex_ptr
;
3003 fixups
[fc
].reloc
= BFD_RELOC_NONE
;
3009 str
= input_line_pointer
;
3010 input_line_pointer
= hold
;
3012 while (*str
== ' ' || *str
== ',' || *str
== '[' || *str
== ']'
3017 while (ISSPACE (*str
))
3026 if ((opindex_ptr
- opcode
->operands
) >= most_match_count
)
3028 most_match_count
= opindex_ptr
- opcode
->operands
;
3030 strncpy (most_match_errmsg
, errmsg
, sizeof (most_match_errmsg
)-1);
3033 next_opcode
= opcode
+ 1;
3034 if (next_opcode
->name
!= NULL
3035 && strcmp (next_opcode
->name
, opcode
->name
) == 0)
3037 opcode
= next_opcode
;
3039 /* Skip versions that are not supported by the target
3041 if ((opcode
->processors
& processor_mask
) == 0)
3047 if (most_match_errmsg
[0] == 0)
3048 /* xgettext:c-format. */
3049 as_bad (_("junk at end of line: `%s'"), str
);
3051 as_bad ("%s: %s", copy_of_instruction
, most_match_errmsg
);
3053 if (*input_line_pointer
== ']')
3054 ++input_line_pointer
;
3056 ignore_rest_of_line ();
3057 input_line_pointer
= saved_input_line_pointer
;
3061 if (warningmsg
!= NULL
)
3062 as_warn ("%s", warningmsg
);
3066 input_line_pointer
= str
;
3068 /* Tie dwarf2 debug info to the address at the start of the insn.
3069 We can't do this after the insn has been output as the current
3070 frag may have been closed off. eg. by frag_var. */
3071 dwarf2_emit_insn (0);
3073 /* Write out the instruction. */
3075 if (relaxable
&& fc
> 0)
3080 if (strcmp (opcode
->name
, "loop") == 0)
3082 if (((processor_mask
& PROCESSOR_V850E3V5_UP
) == 0) || default_disp_size
== 22)
3085 f
= frag_var (rs_machine_dependent
, 6, 2, SUBYPTE_LOOP_16_22
,
3086 fixups
[0].exp
.X_add_symbol
,
3087 fixups
[0].exp
.X_add_number
,
3088 (char *)(size_t) fixups
[0].opindex
);
3089 md_number_to_chars (f
, insn
, insn_size
);
3090 md_number_to_chars (f
+4, 0, 4);
3094 as_bad (_("loop: 32-bit displacement not supported"));
3097 else if (strcmp (opcode
->name
, "br") == 0
3098 || strcmp (opcode
->name
, "jbr") == 0)
3100 if ((processor_mask
& PROCESSOR_V850E2_UP
) == 0 || default_disp_size
== 22)
3102 f
= frag_var (rs_machine_dependent
, 4, 2, SUBYPTE_UNCOND_9_22
,
3103 fixups
[0].exp
.X_add_symbol
,
3104 fixups
[0].exp
.X_add_number
,
3105 (char *)(size_t) fixups
[0].opindex
);
3106 md_number_to_chars (f
, insn
, insn_size
);
3107 md_number_to_chars (f
+ 2, 0, 2);
3111 f
= frag_var (rs_machine_dependent
, 6, 4, SUBYPTE_UNCOND_9_22_32
,
3112 fixups
[0].exp
.X_add_symbol
,
3113 fixups
[0].exp
.X_add_number
,
3114 (char *)(size_t) fixups
[0].opindex
);
3115 md_number_to_chars (f
, insn
, insn_size
);
3116 md_number_to_chars (f
+ 2, 0, 4);
3119 else /* b<cond>, j<cond>. */
3121 if (default_disp_size
== 22
3122 || (processor_mask
& PROCESSOR_V850E2_UP
) == 0)
3124 if (processor_mask
& PROCESSOR_V850E2V3_UP
&& !no_bcond17
)
3126 if (strcmp (opcode
->name
, "bsa") == 0)
3128 f
= frag_var (rs_machine_dependent
, 8, 6, SUBYPTE_SA_9_17_22
,
3129 fixups
[0].exp
.X_add_symbol
,
3130 fixups
[0].exp
.X_add_number
,
3131 (char *)(size_t) fixups
[0].opindex
);
3132 md_number_to_chars (f
, insn
, insn_size
);
3133 md_number_to_chars (f
+ 2, 0, 6);
3137 f
= frag_var (rs_machine_dependent
, 6, 4, SUBYPTE_COND_9_17_22
,
3138 fixups
[0].exp
.X_add_symbol
,
3139 fixups
[0].exp
.X_add_number
,
3140 (char *)(size_t) fixups
[0].opindex
);
3141 md_number_to_chars (f
, insn
, insn_size
);
3142 md_number_to_chars (f
+ 2, 0, 4);
3147 if (strcmp (opcode
->name
, "bsa") == 0)
3149 f
= frag_var (rs_machine_dependent
, 8, 6, SUBYPTE_SA_9_22
,
3150 fixups
[0].exp
.X_add_symbol
,
3151 fixups
[0].exp
.X_add_number
,
3152 (char *)(size_t) fixups
[0].opindex
);
3153 md_number_to_chars (f
, insn
, insn_size
);
3154 md_number_to_chars (f
+ 2, 0, 6);
3158 f
= frag_var (rs_machine_dependent
, 6, 4, SUBYPTE_COND_9_22
,
3159 fixups
[0].exp
.X_add_symbol
,
3160 fixups
[0].exp
.X_add_number
,
3161 (char *)(size_t) fixups
[0].opindex
);
3162 md_number_to_chars (f
, insn
, insn_size
);
3163 md_number_to_chars (f
+ 2, 0, 4);
3169 if (processor_mask
& PROCESSOR_V850E2V3_UP
&& !no_bcond17
)
3171 if (strcmp (opcode
->name
, "bsa") == 0)
3173 f
= frag_var (rs_machine_dependent
, 10, 8, SUBYPTE_SA_9_17_22_32
,
3174 fixups
[0].exp
.X_add_symbol
,
3175 fixups
[0].exp
.X_add_number
,
3176 (char *)(size_t) fixups
[0].opindex
);
3177 md_number_to_chars (f
, insn
, insn_size
);
3178 md_number_to_chars (f
+ 2, 0, 8);
3182 f
= frag_var (rs_machine_dependent
, 8, 6, SUBYPTE_COND_9_17_22_32
,
3183 fixups
[0].exp
.X_add_symbol
,
3184 fixups
[0].exp
.X_add_number
,
3185 (char *)(size_t) fixups
[0].opindex
);
3186 md_number_to_chars (f
, insn
, insn_size
);
3187 md_number_to_chars (f
+ 2, 0, 6);
3192 if (strcmp (opcode
->name
, "bsa") == 0)
3194 f
= frag_var (rs_machine_dependent
, 10, 8, SUBYPTE_SA_9_22_32
,
3195 fixups
[0].exp
.X_add_symbol
,
3196 fixups
[0].exp
.X_add_number
,
3197 (char *)(size_t) fixups
[0].opindex
);
3198 md_number_to_chars (f
, insn
, insn_size
);
3199 md_number_to_chars (f
+ 2, 0, 8);
3203 f
= frag_var (rs_machine_dependent
, 8, 6, SUBYPTE_COND_9_22_32
,
3204 fixups
[0].exp
.X_add_symbol
,
3205 fixups
[0].exp
.X_add_number
,
3206 (char *)(size_t) fixups
[0].opindex
);
3207 md_number_to_chars (f
, insn
, insn_size
);
3208 md_number_to_chars (f
+ 2, 0, 6);
3216 /* Four byte insns have an opcode with the two high bits on. */
3217 if ((insn
& 0x0600) == 0x0600)
3222 /* Special case: 32 bit MOV. */
3223 if ((insn
& 0xffe0) == 0x0620)
3226 /* Special case: 32 bit JARL,JMP,JR. */
3227 if ((insn
& 0x1ffe0) == 0x2e0 /* JARL. */
3228 || (insn
& 0x1ffe0) == 0x6e0 /* JMP. */
3229 || (insn
& 0x1ffff) == 0x2e0) /* JR. */
3232 if (obstack_room (& frchain_now
->frch_obstack
) < (insn_size
+ extra_data_len
))
3234 frag_wane (frag_now
);
3238 f
= frag_more (insn_size
);
3239 md_number_to_chars (f
, insn
, insn_size
);
3241 if (extra_data_after_insn
)
3243 f
= frag_more (extra_data_len
);
3244 md_number_to_chars (f
, extra_data
, extra_data_len
);
3246 extra_data_after_insn
= FALSE
;
3250 /* Create any fixups. At this point we do not use a
3251 bfd_reloc_code_real_type, but instead just use the
3252 BFD_RELOC_UNUSED plus the operand index. This lets us easily
3253 handle fixups for any operand type, although that is admittedly
3254 not a very exciting feature. We pick a BFD reloc type in
3256 for (i
= 0; i
< fc
; i
++)
3258 const struct v850_operand
*operand
;
3259 bfd_reloc_code_real_type reloc
;
3261 operand
= &v850_operands
[fixups
[i
].opindex
];
3263 reloc
= fixups
[i
].reloc
;
3265 if (reloc
!= BFD_RELOC_NONE
)
3267 reloc_howto_type
*reloc_howto
=
3268 bfd_reloc_type_lookup (stdoutput
, reloc
);
3276 size
= bfd_get_reloc_size (reloc_howto
);
3278 /* XXX This will abort on an R_V850_8 reloc -
3279 is this reloc actually used? */
3280 if (size
!= 2 && size
!= 4)
3283 if (extra_data_len
== 0)
3285 address
= (f
- frag_now
->fr_literal
) + insn_size
- size
;
3289 address
= (f
- frag_now
->fr_literal
) + extra_data_len
- size
;
3292 if ((operand
->flags
& V850E_IMMEDIATE32
) && (operand
->flags
& V850_PCREL
))
3294 fixups
[i
].exp
.X_add_number
+= 2;
3296 else if (operand
->default_reloc
== BFD_RELOC_V850_16_PCREL
)
3298 fixups
[i
].exp
.X_add_number
+= 2;
3302 /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */
3303 fixP
= fix_new_exp (frag_now
, address
, size
,
3305 reloc_howto
->pc_relative
,
3308 fixP
->tc_fix_data
= (void *) operand
;
3312 case BFD_RELOC_LO16
:
3313 case BFD_RELOC_V850_LO16_S1
:
3314 case BFD_RELOC_V850_LO16_SPLIT_OFFSET
:
3315 case BFD_RELOC_HI16
:
3316 case BFD_RELOC_HI16_S
:
3317 fixP
->fx_no_overflow
= 1;
3325 gas_assert (f
!= NULL
);
3326 fix_new_exp (frag_now
,
3327 f
- frag_now
->fr_literal
, 4,
3329 (operand
->flags
& V850_PCREL
) != 0,
3330 (bfd_reloc_code_real_type
) (fixups
[i
].opindex
3331 + (int) BFD_RELOC_UNUSED
));
3335 input_line_pointer
= saved_input_line_pointer
;
3338 /* If while processing a fixup, a reloc really needs to be created
3339 then it is done here. */
3342 tc_gen_reloc (asection
*seg ATTRIBUTE_UNUSED
, fixS
*fixp
)
3346 reloc
= xmalloc (sizeof (arelent
));
3347 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
3348 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3349 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3351 if ( fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
3352 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3353 || fixp
->fx_r_type
== BFD_RELOC_V850_LONGCALL
3354 || fixp
->fx_r_type
== BFD_RELOC_V850_LONGJUMP
3355 || fixp
->fx_r_type
== BFD_RELOC_V850_ALIGN
)
3356 reloc
->addend
= fixp
->fx_offset
;
3360 if (fixp
->fx_r_type
== BFD_RELOC_32
3362 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
3365 reloc
->addend
= fixp
->fx_addnumber
;
3368 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3370 if (reloc
->howto
== NULL
)
3372 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3373 /* xgettext:c-format */
3374 _("reloc %d not supported by object file format"),
3375 (int) fixp
->fx_r_type
);
3386 v850_handle_align (fragS
* frag
)
3389 && frag
->fr_type
== rs_align
3390 && frag
->fr_address
+ frag
->fr_fix
> 0
3391 && frag
->fr_offset
> 1
3392 && now_seg
!= bss_section
3393 && now_seg
!= v850_seg_table
[SBSS_SECTION
].s
3394 && now_seg
!= v850_seg_table
[TBSS_SECTION
].s
3395 && now_seg
!= v850_seg_table
[ZBSS_SECTION
].s
)
3396 fix_new (frag
, frag
->fr_fix
, 2, & abs_symbol
, frag
->fr_offset
, 0,
3397 BFD_RELOC_V850_ALIGN
);
3400 /* Return current size of variable part of frag. */
3403 md_estimate_size_before_relax (fragS
*fragp
, asection
*seg ATTRIBUTE_UNUSED
)
3405 if (fragp
->fr_subtype
>= sizeof (md_relax_table
) / sizeof (md_relax_table
[0]))
3408 return md_relax_table
[fragp
->fr_subtype
].rlx_length
;
3412 v850_pcrel_from_section (fixS
*fixp
, segT section
)
3414 /* If the symbol is undefined, or in a section other than our own,
3415 or it is weak (in which case it may well be in another section,
3416 then let the linker figure it out. */
3417 if (fixp
->fx_addsy
!= (symbolS
*) NULL
3418 && (! S_IS_DEFINED (fixp
->fx_addsy
)
3419 || S_IS_WEAK (fixp
->fx_addsy
)
3420 || (S_GET_SEGMENT (fixp
->fx_addsy
) != section
)))
3423 return fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3427 md_apply_fix (fixS
*fixP
, valueT
*valueP
, segT seg ATTRIBUTE_UNUSED
)
3429 valueT value
= * valueP
;
3432 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3433 || fixP
->fx_r_type
== BFD_RELOC_V850_LONGCALL
3434 || fixP
->fx_r_type
== BFD_RELOC_V850_LONGJUMP
3435 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3441 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
3442 fixP
->fx_addnumber
= value
,
3445 else if (fixP
->fx_pcrel
)
3446 fixP
->fx_addnumber
= fixP
->fx_offset
;
3450 value
= fixP
->fx_offset
;
3451 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
3453 if (S_GET_SEGMENT (fixP
->fx_subsy
) == absolute_section
)
3454 value
-= S_GET_VALUE (fixP
->fx_subsy
);
3456 /* We don't actually support subtracting a symbol. */
3457 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3458 _("expression too complex"));
3460 fixP
->fx_addnumber
= value
;
3463 if ((int) fixP
->fx_r_type
>= (int) BFD_RELOC_UNUSED
)
3466 const struct v850_operand
*operand
;
3468 const char *errmsg
= NULL
;
3470 opindex
= (int) fixP
->fx_r_type
- (int) BFD_RELOC_UNUSED
;
3471 operand
= &v850_operands
[opindex
];
3473 /* Fetch the instruction, insert the fully resolved operand
3474 value, and stuff the instruction back again.
3476 Note the instruction has been stored in little endian
3478 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
3480 if (fixP
->fx_size
> 2)
3481 insn
= bfd_getl32 ((unsigned char *) where
);
3483 insn
= bfd_getl16 ((unsigned char *) where
);
3485 /* When inserting loop offets a backwards displacement
3486 is encoded as a positive value. */
3487 if (operand
->flags
& V850_INVERSE_PCREL
)
3490 insn
= v850_insert_operand (insn
, operand
, (offsetT
) value
,
3493 as_warn_where (fixP
->fx_file
, fixP
->fx_line
, "%s", errmsg
);
3495 if (fixP
->fx_size
> 2)
3496 bfd_putl32 ((bfd_vma
) insn
, (unsigned char *) where
);
3498 bfd_putl16 ((bfd_vma
) insn
, (unsigned char *) where
);
3501 /* Nothing else to do here. */
3504 /* Determine a BFD reloc value based on the operand information.
3505 We are only prepared to turn a few of the operands into relocs. */
3507 if (operand
->default_reloc
== BFD_RELOC_NONE
)
3509 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
3510 _("unresolved expression that must be resolved"));
3516 fixP
->fx_r_type
= operand
->default_reloc
;
3517 if (operand
->default_reloc
== BFD_RELOC_V850_16_PCREL
)
3519 fixP
->fx_where
+= 2;
3521 fixP
->fx_addnumber
+= 2;
3525 else if (fixP
->fx_done
)
3527 /* We still have to insert the value into memory! */
3528 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
3530 if (fixP
->tc_fix_data
!= NULL
3531 && ((struct v850_operand
*) fixP
->tc_fix_data
)->insert
!= NULL
)
3533 const char * message
= NULL
;
3534 struct v850_operand
* operand
= (struct v850_operand
*) fixP
->tc_fix_data
;
3537 /* The variable "where" currently points at the exact point inside
3538 the insn where we need to insert the value. But we need to
3539 extract the entire insn so we probably need to move "where"
3540 back a few bytes. */
3542 if (fixP
->fx_size
== 2)
3544 else if (fixP
->fx_size
== 1)
3547 insn
= bfd_getl32 ((unsigned char *) where
);
3549 /* Use the operand's insertion procedure, if present, in order to
3550 make sure that the value is correctly stored in the insn. */
3551 insn
= operand
->insert (insn
, (offsetT
) value
, & message
);
3552 /* Ignore message even if it is set. */
3554 bfd_putl32 ((bfd_vma
) insn
, (unsigned char *) where
);
3558 switch (fixP
->fx_r_type
)
3560 case BFD_RELOC_V850_32_ABS
:
3561 case BFD_RELOC_V850_32_PCREL
:
3562 bfd_putl32 (value
& 0xfffffffe, (unsigned char *) where
);
3566 bfd_putl32 (value
, (unsigned char *) where
);
3569 case BFD_RELOC_V850_23
:
3570 bfd_putl32 (((value
& 0x7f) << 4) | ((value
& 0x7fff80) << (16-7))
3571 | (bfd_getl32 (where
) & ~((0x7f << 4) | (0xffff << 16))),
3572 (unsigned char *) where
);
3576 case BFD_RELOC_HI16
:
3577 case BFD_RELOC_HI16_S
:
3578 case BFD_RELOC_LO16
:
3579 case BFD_RELOC_V850_ZDA_16_16_OFFSET
:
3580 case BFD_RELOC_V850_SDA_16_16_OFFSET
:
3581 case BFD_RELOC_V850_TDA_16_16_OFFSET
:
3582 case BFD_RELOC_V850_CALLT_16_16_OFFSET
:
3583 bfd_putl16 (value
& 0xffff, (unsigned char *) where
);
3587 *where
= value
& 0xff;
3590 case BFD_RELOC_V850_9_PCREL
:
3591 bfd_putl16 (((value
& 0x1f0) << 7) | ((value
& 0x0e) << 3)
3592 | (bfd_getl16 (where
) & ~((0x1f0 << 7) | (0x0e << 3))), where
);
3595 case BFD_RELOC_V850_17_PCREL
:
3596 bfd_putl32 (((value
& 0x10000) >> (16 - 4)) | ((value
& 0xfffe) << 16)
3597 | (bfd_getl32 (where
) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where
);
3600 case BFD_RELOC_V850_16_PCREL
:
3601 bfd_putl16 ((-value
& 0xfffe) | (bfd_getl16 (where
+ 2) & 0x0001),
3602 (unsigned char *) (where
+ 2));
3605 case BFD_RELOC_V850_22_PCREL
:
3606 bfd_putl32 (((value
& 0xfffe) << 16) | ((value
& 0x3f0000) >> 16)
3607 | (bfd_getl32 (where
) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where
);
3610 case BFD_RELOC_V850_16_S1
:
3611 case BFD_RELOC_V850_LO16_S1
:
3612 case BFD_RELOC_V850_ZDA_15_16_OFFSET
:
3613 case BFD_RELOC_V850_SDA_15_16_OFFSET
:
3614 bfd_putl16 (value
& 0xfffe, (unsigned char *) where
);
3617 case BFD_RELOC_V850_16_SPLIT_OFFSET
:
3618 case BFD_RELOC_V850_LO16_SPLIT_OFFSET
:
3619 case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
:
3620 case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
:
3621 bfd_putl32 (((value
<< 16) & 0xfffe0000)
3622 | ((value
<< 5) & 0x20)
3623 | (bfd_getl32 (where
) & ~0xfffe0020), where
);
3626 case BFD_RELOC_V850_TDA_6_8_OFFSET
:
3627 *where
= (*where
& ~0x7e) | ((value
>> 1) & 0x7e);
3630 case BFD_RELOC_V850_TDA_7_8_OFFSET
:
3631 *where
= (*where
& ~0x7f) | ((value
>> 1) & 0x7f);
3634 case BFD_RELOC_V850_TDA_7_7_OFFSET
:
3635 *where
= (*where
& ~0x7f) | (value
& 0x7f);
3638 case BFD_RELOC_V850_TDA_4_5_OFFSET
:
3639 *where
= (*where
& ~0xf) | ((value
>> 1) & 0xf);
3642 case BFD_RELOC_V850_TDA_4_4_OFFSET
:
3643 *where
= (*where
& ~0xf) | (value
& 0xf);
3646 case BFD_RELOC_V850_CALLT_6_7_OFFSET
:
3647 *where
= (*where
& ~0x3f) | (value
& 0x3f);
3657 /* Parse a cons expression. We have to handle hi(), lo(), etc
3660 bfd_reloc_code_real_type
3661 parse_cons_expression_v850 (expressionS
*exp
)
3664 bfd_reloc_code_real_type r
;
3666 /* See if there's a reloc prefix like hi() we have to handle. */
3667 r
= v850_reloc_prefix (NULL
, &errmsg
);
3669 /* Do normal expression parsing. */
3674 /* Create a fixup for a cons expression. If parse_cons_expression_v850
3675 found a reloc prefix, then we use that reloc, else we choose an
3676 appropriate one based on the size of the expression. */
3679 cons_fix_new_v850 (fragS
*frag
,
3683 bfd_reloc_code_real_type r
)
3685 if (r
== BFD_RELOC_NONE
)
3696 fix_new_exp (frag
, where
, size
, exp
, 0, r
);
3698 fix_new (frag
, where
, size
, NULL
, 0, 0, r
);
3702 v850_fix_adjustable (fixS
*fixP
)
3704 if (fixP
->fx_addsy
== NULL
)
3707 /* Don't adjust function names. */
3708 if (S_IS_FUNCTION (fixP
->fx_addsy
))
3711 /* We need the symbol name for the VTABLE entries. */
3712 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3713 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3720 v850_force_relocation (struct fix
*fixP
)
3722 if (fixP
->fx_r_type
== BFD_RELOC_V850_LONGCALL
3723 || fixP
->fx_r_type
== BFD_RELOC_V850_LONGJUMP
)
3728 || fixP
->fx_r_type
== BFD_RELOC_V850_ALIGN
3729 || fixP
->fx_r_type
== BFD_RELOC_V850_9_PCREL
3730 || fixP
->fx_r_type
== BFD_RELOC_V850_16_PCREL
3731 || fixP
->fx_r_type
== BFD_RELOC_V850_17_PCREL
3732 || fixP
->fx_r_type
== BFD_RELOC_V850_22_PCREL
3733 || fixP
->fx_r_type
== BFD_RELOC_V850_32_PCREL
3734 || fixP
->fx_r_type
>= BFD_RELOC_UNUSED
))
3737 return generic_force_reloc (fixP
);
3740 /* Create a v850 note section. */
3745 segT orig_seg
= now_seg
;
3746 subsegT orig_subseg
= now_subseg
;
3749 note_sec
= subseg_new (V850_NOTE_SECNAME
, 0);
3750 bfd_set_section_flags (stdoutput
, note_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_MERGE
);
3751 bfd_set_section_alignment (stdoutput
, note_sec
, 2);
3753 /* Provide default values for all of the notes. */
3754 for (id
= V850_NOTE_ALIGNMENT
; id
<= NUM_V850_NOTES
; id
++)
3759 /* Follow the standard note section layout:
3760 First write the length of the name string. */
3762 md_number_to_chars (p
, 4, 4);
3764 /* Next comes the length of the "descriptor", i.e., the actual data. */
3766 md_number_to_chars (p
, 4, 4);
3768 /* Write the note type. */
3770 md_number_to_chars (p
, (valueT
) id
, 4);
3772 /* Write the name field. */
3774 memcpy (p
, V850_NOTE_NAME
, 4);
3776 /* Finally, write the descriptor. */
3780 case V850_NOTE_ALIGNMENT
:
3781 val
= v850_data_8
? EF_RH850_DATA_ALIGN8
: EF_RH850_DATA_ALIGN4
;
3784 case V850_NOTE_DATA_SIZE
:
3785 /* GCC does not currently support an option
3786 for 32-bit doubles with the V850 backend. */
3787 val
= EF_RH850_DOUBLE64
;
3790 case V850_NOTE_FPU_INFO
:
3794 case bfd_mach_v850e3v5
: val
= EF_RH850_FPU30
; break;
3795 case bfd_mach_v850e2v3
: val
= EF_RH850_FPU20
; break;
3803 md_number_to_chars (p
, val
, 4);
3806 /* Paranoia - we probably do not need this. */
3807 subseg_set (orig_seg
, orig_subseg
);