1 /* This is the machine dependent code of the Visium Assembler.
3 Copyright (C) 2005-2019 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include "safe-ctype.h"
27 #include "opcode/visium.h"
28 #include "elf/visium.h"
29 #include "dwarf2dbg.h"
30 #include "dw2gencfi.h"
32 /* Relocations and fixups:
34 There are two different cases where an instruction or data
35 directive operand requires relocation, or fixup.
37 1. Relative branch instructions, take an 16-bit signed word
38 offset. The formula for computing the offset is this:
40 offset = (destination - pc) / 4
42 Branch instructions never branch to a label not declared
43 locally, so the actual offset can always be computed by the assembler.
44 However, we provide a relocation type to support this.
46 2. Load literal instructions, such as MOVIU, which take a 16-bit
47 literal operand. The literal may be the top or bottom half of
48 a 32-bit value computed by the assembler, or by the linker. We provide
49 two relocation types here.
51 3. Data items (long, word and byte) preset with a value computed by
55 /* This string holds the chars that always start a comment. If the
56 pre-processor is disabled, these aren't very useful. The macro
57 tc_comment_chars points to this. */
58 const char *visium_comment_chars
= "!;";
60 /* This array holds the chars that only start a comment at the beginning
61 of a line. If the line seems to have the form '# 123 filename' .line
62 and .file directives will appear in the pre-processed output. Note that
63 input_file.c hand checks for '#' at the beginning of the first line of
64 the input file. This is because the compiler outputs #NO_APP at the
65 beginning of its output. Also note that comments like this one will
67 const char line_comment_chars
[] = "#!;";
68 const char line_separator_chars
[] = "";
70 /* Chars that can be used to separate mantissa from exponent in floating point
72 const char EXP_CHARS
[] = "eE";
74 /* Chars that mean this number is a floating point constant, as in
75 "0f12.456" or "0d1.2345e12".
77 ...Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
78 changed in read.c. Ideally it shouldn't have to know about it at all,
79 but nothing is ideal around here. */
80 const char FLT_CHARS
[] = "rRsSfFdDxXeE";
82 /* The size of a relocation record. */
83 const int md_reloc_size
= 8;
85 /* The architecture for which we are assembling. */
94 static enum visium_arch_val visium_arch
= VISIUM_ARCH_DEF
;
96 /* The opcode architecture for which we are assembling. In contrast to the
97 previous one, this only determines which instructions are supported. */
98 static enum visium_opcode_arch_val visium_opcode_arch
= VISIUM_OPCODE_ARCH_DEF
;
100 /* Flags to set in the ELF header e_flags field. */
101 static flagword visium_flags
= 0;
103 /* More than this number of nops in an alignment op gets a branch instead. */
104 static unsigned int nop_limit
= 5;
107 /* Translate internal representation of relocation info to BFD target
110 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
113 bfd_reloc_code_real_type code
;
115 reloc
= XNEW (arelent
);
117 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
118 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
119 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
121 switch (fixp
->fx_r_type
)
126 case BFD_RELOC_8_PCREL
:
127 case BFD_RELOC_16_PCREL
:
128 case BFD_RELOC_32_PCREL
:
129 case BFD_RELOC_VISIUM_HI16
:
130 case BFD_RELOC_VISIUM_LO16
:
131 case BFD_RELOC_VISIUM_IM16
:
132 case BFD_RELOC_VISIUM_REL16
:
133 case BFD_RELOC_VISIUM_HI16_PCREL
:
134 case BFD_RELOC_VISIUM_LO16_PCREL
:
135 case BFD_RELOC_VISIUM_IM16_PCREL
:
136 case BFD_RELOC_VTABLE_INHERIT
:
137 case BFD_RELOC_VTABLE_ENTRY
:
138 code
= fixp
->fx_r_type
;
141 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
142 "internal error: unknown relocation type %d (`%s')",
144 bfd_get_reloc_code_name (fixp
->fx_r_type
));
148 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
149 if (reloc
->howto
== 0)
151 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
152 "internal error: can't export reloc type %d (`%s')",
153 fixp
->fx_r_type
, bfd_get_reloc_code_name (code
));
157 /* Write the addend. */
158 if (reloc
->howto
->pc_relative
== 0)
159 reloc
->addend
= fixp
->fx_addnumber
;
161 reloc
->addend
= fixp
->fx_offset
;
166 extern char *input_line_pointer
;
169 static void s_bss (int);
170 static void visium_rdata (int);
172 static void visium_update_parity_bit (char *);
173 static char *parse_exp (char *, expressionS
*);
175 /* These are the back-ends for the various machine dependent pseudo-ops. */
176 void demand_empty_rest_of_line (void);
180 s_bss (int ignore ATTRIBUTE_UNUSED
)
182 /* We don't support putting frags in the BSS segment, we fake it
183 by marking in_bss, then looking at s_skip for clues. */
185 subseg_set (bss_section
, 0);
186 demand_empty_rest_of_line ();
190 /* This table describes all the machine specific pseudo-ops the assembler
191 has to support. The fields are:
193 1: Pseudo-op name without dot.
194 2: Function to call to execute this pseudo-op.
195 3: Integer arg to pass to the function. */
196 const pseudo_typeS md_pseudo_table
[] =
199 {"skip", s_space
, 0},
200 {"align", s_align_bytes
, 0},
201 {"noopt", s_ignore
, 0},
202 {"optim", s_ignore
, 0},
203 {"rdata", visium_rdata
, 0},
204 {"rodata", visium_rdata
, 0},
210 visium_rdata (int xxx
)
212 char *save_line
= input_line_pointer
;
213 static char section
[] = ".rodata\n";
215 /* Just pretend this is .section .rodata */
216 input_line_pointer
= section
;
217 obj_elf_section (xxx
);
218 input_line_pointer
= save_line
;
221 /* Align a section. */
223 md_section_align (asection
*seg
, valueT addr
)
225 int align
= bfd_get_section_alignment (stdoutput
, seg
);
227 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
231 md_number_to_chars (char *buf
, valueT val
, int n
)
233 number_to_chars_bigendian (buf
, val
, n
);
237 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
242 /* The parse options. */
243 const char *md_shortopts
= "m:";
245 struct option md_longopts
[] =
247 {NULL
, no_argument
, NULL
, 0}
250 size_t md_longopts_size
= sizeof (md_longopts
);
252 struct visium_option_table
254 char *option
; /* Option name to match. */
255 char *help
; /* Help information. */
256 int *var
; /* Variable to change. */
257 int value
; /* To what to change it. */
258 char *deprecated
; /* If non-null, print this message. */
261 static struct visium_option_table visium_opts
[] =
263 {NULL
, NULL
, NULL
, 0, NULL
}
266 struct visium_arch_option_table
269 enum visium_arch_val value
;
272 static struct visium_arch_option_table visium_archs
[] =
274 {"mcm24", VISIUM_ARCH_MCM24
},
275 {"mcm", VISIUM_ARCH_MCM
},
276 {"gr5", VISIUM_ARCH_MCM
},
277 {"gr6", VISIUM_ARCH_GR6
},
280 struct visium_long_option_table
282 const char *option
; /* Substring to match. */
283 const char *help
; /* Help information. */
284 int (*func
) (const char *subopt
); /* Function to decode sub-option. */
285 const char *deprecated
; /* If non-null, print this message. */
289 visium_parse_arch (const char *str
)
293 if (strlen (str
) == 0)
295 as_bad ("missing architecture name `%s'", str
);
299 for (i
= 0; i
< ARRAY_SIZE (visium_archs
); i
++)
300 if (strcmp (visium_archs
[i
].name
, str
) == 0)
302 visium_arch
= visium_archs
[i
].value
;
306 as_bad ("unknown architecture `%s'\n", str
);
310 static struct visium_long_option_table visium_long_opts
[] =
312 {"mtune=", "<arch_name>\t assemble for architecture <arch name>",
313 visium_parse_arch
, NULL
},
314 {NULL
, NULL
, NULL
, NULL
}
318 md_parse_option (int c
, const char *arg
)
320 struct visium_option_table
*opt
;
321 struct visium_long_option_table
*lopt
;
326 /* Listing option. Just ignore these, we don't support additional
331 for (opt
= visium_opts
; opt
->option
!= NULL
; opt
++)
333 if (c
== opt
->option
[0]
334 && ((arg
== NULL
&& opt
->option
[1] == 0)
335 || strcmp (arg
, opt
->option
+ 1) == 0))
337 /* If the option is deprecated, tell the user. */
338 if (opt
->deprecated
!= NULL
)
339 as_tsktsk ("option `-%c%s' is deprecated: %s", c
,
340 arg
? arg
: "", opt
->deprecated
);
342 if (opt
->var
!= NULL
)
343 *opt
->var
= opt
->value
;
349 for (lopt
= visium_long_opts
; lopt
->option
!= NULL
; lopt
++)
351 /* These options are expected to have an argument. */
352 if (c
== lopt
->option
[0]
354 && strncmp (arg
, lopt
->option
+ 1,
355 strlen (lopt
->option
+ 1)) == 0)
357 /* If the option is deprecated, tell the user. */
358 if (lopt
->deprecated
!= NULL
)
359 as_tsktsk ("option `-%c%s' is deprecated: %s", c
, arg
,
362 /* Call the sup-option parser. */
363 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
374 md_show_usage (FILE * fp
)
376 struct visium_option_table
*opt
;
377 struct visium_long_option_table
*lopt
;
379 fprintf (fp
, " Visium-specific assembler options:\n");
381 for (opt
= visium_opts
; opt
->option
!= NULL
; opt
++)
382 if (opt
->help
!= NULL
)
383 fprintf (fp
, " -%-23s%s\n", opt
->option
, opt
->help
);
385 for (lopt
= visium_long_opts
; lopt
->option
!= NULL
; lopt
++)
386 if (lopt
->help
!= NULL
)
387 fprintf (fp
, " -%s%s\n", lopt
->option
, lopt
->help
);
391 /* Interface to relax_segment. */
393 /* Return the estimate of the size of a machine dependent frag
394 before any relaxing is done. It may also create any necessary
397 md_estimate_size_before_relax (fragS
* fragP
,
398 segT segment ATTRIBUTE_UNUSED
)
404 /* Get the address of a symbol during relaxation. From tc-arm.c. */
406 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
412 sym
= fragp
->fr_symbol
;
413 sym_frag
= symbol_get_frag (sym
);
414 know (S_GET_SEGMENT (sym
) != absolute_section
415 || sym_frag
== &zero_address_frag
);
416 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
418 /* If frag has yet to be reached on this pass, assume it will
419 move by STRETCH just as we did. If this is not so, it will
420 be because some frag between grows, and that will force
423 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
427 /* Adjust stretch for any alignment frag. Note that if have
428 been expanding the earlier code, the symbol may be
429 defined in what appears to be an earlier frag. FIXME:
430 This doesn't handle the fr_subtype field, which specifies
431 a maximum number of bytes to skip when doing an
433 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
435 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
438 stretch
= - ((- stretch
)
439 & ~ ((1 << (int) f
->fr_offset
) - 1));
441 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
453 /* Relax a machine dependent frag. This returns the amount by which
454 the current size of the frag should change. */
456 visium_relax_frag (asection
*sec
, fragS
*fragP
, long stretch
)
458 int old_size
, new_size
;
461 /* We only handle relaxation for the BRR instruction. */
462 gas_assert (fragP
->fr_subtype
== mode_ci
);
464 if (!S_IS_DEFINED (fragP
->fr_symbol
)
465 || sec
!= S_GET_SEGMENT (fragP
->fr_symbol
)
466 || S_IS_WEAK (fragP
->fr_symbol
))
469 old_size
= fragP
->fr_var
;
470 addr
= relaxed_symbol_addr (fragP
, stretch
);
472 /* If the target is the address of the instruction, we'll insert a NOP. */
473 if (addr
== fragP
->fr_address
+ fragP
->fr_fix
)
478 fragP
->fr_var
= new_size
;
479 return new_size
- old_size
;
482 /* Convert a machine dependent frag. */
484 md_convert_frag (bfd
* abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
487 char *buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
491 /* We only handle relaxation for the BRR instruction. */
492 gas_assert (fragP
->fr_subtype
== mode_ci
);
494 /* Insert the NOP if requested. */
495 if (fragP
->fr_var
== 8)
497 memcpy (buf
+ 4, buf
, 4);
503 exp
.X_add_symbol
= fragP
->fr_symbol
;
504 exp
.X_add_number
= fragP
->fr_offset
;
506 /* Now we can create the relocation at the correct offset. */
507 fixP
= fix_new_exp (fragP
, fragP
->fr_fix
, 4, &exp
, 1, BFD_RELOC_VISIUM_REL16
);
508 fixP
->fx_file
= fragP
->fr_file
;
509 fixP
->fx_line
= fragP
->fr_line
;
514 /* The location from which a PC relative jump should be calculated,
515 given a PC relative jump reloc. */
517 visium_pcrel_from_section (fixS
*fixP
, segT sec
)
519 if (fixP
->fx_addsy
!= (symbolS
*) NULL
520 && (!S_IS_DEFINED (fixP
->fx_addsy
)
521 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
523 /* The symbol is undefined (or is defined but not in this section).
524 Let the linker figure it out. */
528 /* Return the address of the instruction. */
529 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
532 /* Indicate whether a fixup against a locally defined
533 symbol should be adjusted to be against the section
536 visium_fix_adjustable (fixS
*fix
)
538 /* We need the symbol name for the VTABLE entries. */
539 return (fix
->fx_r_type
!= BFD_RELOC_VTABLE_INHERIT
540 && fix
->fx_r_type
!= BFD_RELOC_VTABLE_ENTRY
);
543 /* Update the parity bit of the 4-byte instruction in BUF. */
545 visium_update_parity_bit (char *buf
)
547 int p1
= (buf
[0] & 0x7f) ^ buf
[1] ^ buf
[2] ^ buf
[3];
551 for (i
= 1; i
<= 8; i
++)
557 buf
[0] = (buf
[0] & 0x7f) | ((p2
<< 7) & 0x80);
560 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
561 of an rs_align_code fragment. */
563 visium_handle_align (fragS
*fragP
)
566 = fragP
->fr_next
->fr_address
- (fragP
->fr_address
+ fragP
->fr_fix
);
567 valueT fix
= count
& 3;
568 char *p
= fragP
->fr_literal
+ fragP
->fr_fix
;
575 fragP
->fr_fix
+= fix
;
583 if (count
> 4 * nop_limit
&& count
<= 131068)
587 /* Make a branch, then follow with nops. Insert another
588 frag to handle the nops. */
589 md_number_to_chars (p
, 0x78000000 + (count
>> 2), 4);
590 visium_update_parity_bit (p
);
592 rest
= xmalloc (SIZEOF_STRUCT_FRAG
+ 4);
593 memcpy (rest
, fragP
, SIZEOF_STRUCT_FRAG
);
594 fragP
->fr_next
= rest
;
595 rest
->fr_address
+= rest
->fr_fix
+ 4;
597 /* If we leave the next frag as rs_align_code we'll come here
598 again, resulting in a bunch of branches rather than a
599 branch followed by nops. */
600 rest
->fr_type
= rs_align
;
601 p
= rest
->fr_literal
;
607 /* Apply a fixS to the frags, now that we know the value it ought to
610 md_apply_fix (fixS
* fixP
, valueT
* value
, segT segment
)
612 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
618 gas_assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
620 /* Remember value for tc_gen_reloc. */
621 fixP
->fx_addnumber
= val
;
623 /* Since DIFF_EXPR_OK is defined, .-foo gets turned into PC
624 relative relocs. If this has happened, a non-PC relative
625 reloc must be reinstalled with its PC relative version here. */
628 switch (fixP
->fx_r_type
)
631 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
634 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
637 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
639 case BFD_RELOC_VISIUM_HI16
:
640 fixP
->fx_r_type
= BFD_RELOC_VISIUM_HI16_PCREL
;
642 case BFD_RELOC_VISIUM_LO16
:
643 fixP
->fx_r_type
= BFD_RELOC_VISIUM_LO16_PCREL
;
645 case BFD_RELOC_VISIUM_IM16
:
646 fixP
->fx_r_type
= BFD_RELOC_VISIUM_IM16_PCREL
;
653 /* If this is a data relocation, just output VAL. */
654 switch (fixP
->fx_r_type
)
657 case BFD_RELOC_8_PCREL
:
658 md_number_to_chars (buf
, val
, 1);
661 case BFD_RELOC_16_PCREL
:
662 md_number_to_chars (buf
, val
, 2);
665 case BFD_RELOC_32_PCREL
:
666 md_number_to_chars (buf
, val
, 4);
668 case BFD_RELOC_VTABLE_INHERIT
:
669 case BFD_RELOC_VTABLE_ENTRY
:
673 /* It's a relocation against an instruction. */
674 insn
= bfd_getb32 ((unsigned char *) buf
);
676 switch (fixP
->fx_r_type
)
678 case BFD_RELOC_VISIUM_REL16
:
679 if (fixP
->fx_addsy
== NULL
680 || (S_IS_DEFINED (fixP
->fx_addsy
)
681 && S_GET_SEGMENT (fixP
->fx_addsy
) == segment
))
683 if (val
> 0x1fffc || val
< -0x20000)
685 (fixP
->fx_file
, fixP
->fx_line
,
686 "16-bit word displacement out of range: value = %d",
690 insn
= (insn
& 0xffff0000) | (val
& 0x0000ffff);
694 case BFD_RELOC_VISIUM_HI16
:
695 case BFD_RELOC_VISIUM_HI16_PCREL
:
696 if (fixP
->fx_addsy
== NULL
)
697 insn
= (insn
& 0xffff0000) | ((val
>> 16) & 0x0000ffff);
700 case BFD_RELOC_VISIUM_LO16
:
701 case BFD_RELOC_VISIUM_LO16_PCREL
:
702 if (fixP
->fx_addsy
== NULL
)
703 insn
= (insn
& 0xffff0000) | (val
& 0x0000ffff);
706 case BFD_RELOC_VISIUM_IM16
:
707 case BFD_RELOC_VISIUM_IM16_PCREL
:
708 if (fixP
->fx_addsy
== NULL
)
710 if ((val
& 0xffff0000) != 0)
711 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
712 "16-bit immediate out of range: value = %d",
715 insn
= (insn
& 0xffff0000) | val
;
721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
722 "bad or unhandled relocation type: 0x%02x",
727 bfd_putb32 (insn
, (unsigned char *) buf
);
728 visium_update_parity_bit (buf
);
732 /* Are we finished with this relocation now? */
733 if (fixP
->fx_addsy
== NULL
)
738 parse_exp (char *s
, expressionS
* op
)
740 char *save
= input_line_pointer
;
748 input_line_pointer
= s
;
750 new = input_line_pointer
;
751 input_line_pointer
= save
;
755 /* If the given string is a Visium opcode mnemonic return the code
756 otherwise return -1. Use binary chop to find matching entry. */
758 get_opcode (int *code
, enum addressing_mode
*mode
, char *flags
, char *mnem
)
761 int r
= sizeof (opcode_table
) / sizeof (struct opcode_entry
) - 1;
765 int mid
= (l
+ r
) / 2;
766 int ans
= strcmp (mnem
, opcode_table
[mid
].mnem
);
774 *code
= opcode_table
[mid
].code
;
775 *mode
= opcode_table
[mid
].mode
;
776 *flags
= opcode_table
[mid
].flags
;
786 /* This function is called when the assembler starts up. It is called
787 after the options have been parsed and the output file has been
794 case VISIUM_ARCH_DEF
:
796 case VISIUM_ARCH_MCM24
:
797 visium_opcode_arch
= VISIUM_OPCODE_ARCH_GR5
;
798 visium_flags
|= EF_VISIUM_ARCH_MCM24
;
800 case VISIUM_ARCH_MCM
:
801 visium_opcode_arch
= VISIUM_OPCODE_ARCH_GR5
;
802 visium_flags
|= EF_VISIUM_ARCH_MCM
;
804 case VISIUM_ARCH_GR6
:
805 visium_opcode_arch
= VISIUM_OPCODE_ARCH_GR6
;
806 visium_flags
|= EF_VISIUM_ARCH_MCM
| EF_VISIUM_ARCH_GR6
;
813 bfd_set_private_flags (stdoutput
, visium_flags
);
816 /* This is identical to the md_atof in m68k.c. I think this is right,
819 Turn a string in input_line_pointer into a floating point constant of type
820 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
821 emitted is stored in *sizeP . An error message is returned,
824 /* Equal to MAX_PRECISION in atof-ieee.c. */
825 #define MAX_LITTLENUMS 6
828 md_atof (int type
, char *litP
, int *sizeP
)
831 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
862 return _("Bad call to MD_ATOF()");
865 t
= atof_ieee (input_line_pointer
, type
, words
);
867 input_line_pointer
= t
;
868 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
870 if (target_big_endian
)
872 for (i
= 0; i
< prec
; i
++)
874 md_number_to_chars (litP
, (valueT
) words
[i
],
875 sizeof (LITTLENUM_TYPE
));
876 litP
+= sizeof (LITTLENUM_TYPE
);
881 for (i
= prec
- 1; i
>= 0; i
--)
883 md_number_to_chars (litP
, (valueT
) words
[i
],
884 sizeof (LITTLENUM_TYPE
));
885 litP
+= sizeof (LITTLENUM_TYPE
);
895 while (*s
== ' ' || *s
== '\t')
902 parse_gen_reg (char **sptr
, int *rptr
)
904 char *s
= skip_space (*sptr
);
910 memset (buf
, '\0', 10);
911 while ((ISALNUM (*s
)) && cnt
< 10)
912 buf
[cnt
++] = TOLOWER (*s
++);
915 r
= sizeof (gen_reg_table
) / sizeof (struct reg_entry
) - 1;
919 int mid
= (l
+ r
) / 2;
920 int ans
= strcmp (buf
, gen_reg_table
[mid
].name
);
928 *rptr
= gen_reg_table
[mid
].code
;
939 parse_fp_reg (char **sptr
, int *rptr
)
941 char *s
= skip_space (*sptr
);
947 memset (buf
, '\0', 10);
948 while ((ISALNUM (*s
)) && cnt
< 10)
949 buf
[cnt
++] = TOLOWER (*s
++);
952 r
= sizeof (fp_reg_table
) / sizeof (struct reg_entry
) - 1;
956 int mid
= (l
+ r
) / 2;
957 int ans
= strcmp (buf
, fp_reg_table
[mid
].name
);
965 *rptr
= fp_reg_table
[mid
].code
;
976 parse_cc (char **sptr
, int *rptr
)
978 char *s
= skip_space (*sptr
);
984 memset (buf
, '\0', 10);
985 while ((ISALNUM (*s
)) && cnt
< 10)
986 buf
[cnt
++] = TOLOWER (*s
++);
989 r
= sizeof (cc_table
) / sizeof (struct cc_entry
) - 1;
993 int mid
= (l
+ r
) / 2;
994 int ans
= strcmp (buf
, cc_table
[mid
].name
);
1002 *rptr
= cc_table
[mid
].code
;
1012 /* Previous dest is the destination register number of the instruction
1013 before the current one. */
1014 static int previous_dest
= 0;
1015 static int previous_mode
= 0;
1016 static int condition_code
= 0;
1017 static int this_dest
= 0;
1018 static int this_mode
= 0;
1021 /* This is the main function in this file. It takes a line of assembly language
1022 source code and assembles it. Note, labels and pseudo ops have already
1023 been removed, so too has leading white space. */
1025 md_assemble (char *str0
)
1031 enum addressing_mode amode
;
1037 relax_substateT relax
= 0;
1043 /* Initialize the expression. */
1046 /* Initialize destination register.
1047 If the instruction we just looked at is in the delay slot of an
1048 unconditional branch, then there is no index hazard. */
1049 if ((previous_mode
== mode_cad
|| previous_mode
== mode_ci
)
1050 && condition_code
== 15)
1053 previous_dest
= this_dest
;
1054 previous_mode
= this_mode
;
1057 /* Drop leading whitespace (probably not required). */
1061 /* Get opcode mnemonic and make sure it's in lower case. */
1063 memset (mnem
, '\0', 10);
1064 while ((ISALNUM (*str
) || *str
== '.' || *str
== '_') && cnt
< 10)
1065 mnem
[cnt
++] = TOLOWER (*str
++);
1067 /* Look up mnemonic in opcode table, and get the code,
1068 the instruction format, and the flags that indicate
1069 which family members support this mnemonic. */
1070 if (get_opcode (&opcode
, &amode
, &arch_flags
, mnem
) < 0)
1072 as_bad ("Unknown instruction mnemonic `%s'", mnem
);
1076 if ((VISIUM_OPCODE_ARCH_MASK (visium_opcode_arch
) & arch_flags
) == 0)
1078 as_bad ("Architecture mismatch on `%s'", mnem
);
1090 ans
= parse_gen_reg (&str
, &r1
);
1093 as_bad ("Dest register required");
1096 opcode
|= (r1
<< 10);
1103 ans
= parse_gen_reg (&str
, &r1
);
1106 as_bad ("SourceA register required");
1109 opcode
|= (r1
<< 16);
1113 /* register * register
1116 ans
= parse_gen_reg (&str
, &r1
);
1119 as_bad ("SourceA register required");
1122 str
= skip_space (str
);
1126 ans
= parse_gen_reg (&str
, &r2
);
1129 as_bad ("SourceB register required");
1132 opcode
|= (r1
<< 16) | (r2
<< 4);
1136 as_bad ("SourceB register required");
1142 /* register := register
1145 ans
= parse_gen_reg (&str
, &r1
);
1148 as_bad ("Dest register required");
1151 str
= skip_space (str
);
1155 ans
= parse_gen_reg (&str
, &r2
);
1158 as_bad ("SourceA register required");
1161 opcode
|= (r1
<< 10) | (r2
<< 16);
1165 as_bad ("SourceB register required");
1172 /* register := register * register
1175 ans
= parse_gen_reg (&str
, &r1
);
1178 as_bad ("Dest register required");
1181 str
= skip_space (str
);
1185 ans
= parse_gen_reg (&str
, &r2
);
1188 as_bad ("SourceA register required");
1191 str
= skip_space (str
);
1195 ans
= parse_gen_reg (&str
, &r3
);
1198 as_bad ("SourceB register required");
1202 /* Got three regs, assemble instruction. */
1203 opcode
|= (r1
<< 10) | (r2
<< 16) | (r3
<< 4);
1207 as_bad ("SourceA register required");
1213 as_bad ("Dest register required");
1220 /* 5-bit immediate * register * register
1223 str
= parse_exp (str
, &e1
);
1224 str
= skip_space (str
);
1225 if (e1
.X_op
!= O_absent
&& *str
== ',')
1227 int eam_op
= e1
.X_add_number
;
1229 str
= skip_space (str
+ 1);
1230 ans
= parse_gen_reg (&str
, &r2
);
1233 as_bad ("SourceA register required");
1236 str
= skip_space (str
);
1240 ans
= parse_gen_reg (&str
, &r3
);
1243 as_bad ("SourceB register required");
1247 /* Got three operands, assemble instruction. */
1248 if (eam_op
< 0 || eam_op
> 31)
1250 as_bad ("eam_op out of range");
1252 opcode
|= ((eam_op
& 0x1f) << 10) | (r2
<< 16) | (r3
<< 4);
1257 as_bad ("EAM_OP required");
1263 /* zero * register * register
1266 ans
= parse_gen_reg (&str
, &r1
);
1269 as_bad ("SourceA register required");
1272 str
= skip_space (str
);
1276 ans
= parse_gen_reg (&str
, &r2
);
1279 as_bad ("SourceB register required");
1282 opcode
|= (r1
<< 16) | (r2
<< 4);
1286 as_bad ("SourceB register required");
1292 /* register * register * zero
1295 ans
= parse_gen_reg (&str
, &r1
);
1298 as_bad ("Dest register required");
1301 str
= skip_space (str
);
1305 ans
= parse_gen_reg (&str
, &r2
);
1308 as_bad ("SourceA register required");
1311 opcode
|= (r1
<< 10) | (r2
<< 16);
1315 as_bad ("SourceA register required");
1322 /* condition * register * register
1325 ans
= parse_cc (&str
, &cc
);
1328 as_bad ("condition code required");
1332 str
= skip_space (str
);
1335 str
= skip_space (str
+ 1);
1336 ans
= parse_gen_reg (&str
, &r2
);
1339 as_bad ("SourceA register required");
1342 str
= skip_space (str
);
1346 ans
= parse_gen_reg (&str
, &r3
);
1349 as_bad ("Dest register required");
1353 /* Got three operands, assemble instruction. */
1354 opcode
|= (cc
<< 27) | (r2
<< 16) | (r3
<< 10);
1358 as_bad ("Dest register required");
1364 as_bad ("SourceA register required");
1368 if (previous_mode
== mode_cad
|| previous_mode
== mode_ci
)
1369 as_bad ("branch instruction in delay slot");
1371 /* For the GR6, BRA insns must be aligned on 64-bit boundaries. */
1372 if (visium_arch
== VISIUM_ARCH_GR6
)
1373 do_align (3, NULL
, 0, 0);
1376 condition_code
= cc
;
1380 /* register := register * 5-bit immediate/register shift count
1383 ans
= parse_gen_reg (&str
, &r1
);
1386 as_bad ("Dest register required");
1389 str
= skip_space (str
);
1393 ans
= parse_gen_reg (&str
, &r2
);
1396 as_bad ("SourceA register required");
1399 str
= skip_space (str
);
1403 ans
= parse_gen_reg (&str
, &r3
);
1406 opcode
|= (r1
<< 10) | (r2
<< 16) | (r3
<< 4);
1410 str
= parse_exp (str
, &e1
);
1411 if (e1
.X_op
== O_constant
)
1413 int imm
= e1
.X_add_number
;
1415 if (imm
< 0 || imm
> 31)
1416 as_bad ("immediate value out of range");
1419 (r1
<< 10) | (r2
<< 16) | (1 << 9) | ((imm
& 0x1f) <<
1424 as_bad ("immediate operand required");
1432 as_bad ("SourceA register required");
1439 /* register := 5-bit immediate
1442 ans
= parse_gen_reg (&str
, &r1
);
1445 as_bad ("Dest register required");
1448 str
= skip_space (str
);
1452 str
= parse_exp (str
, &e1
);
1453 if (e1
.X_op
== O_constant
)
1455 int opnd2
= e1
.X_add_number
;
1457 if (opnd2
< 0 || opnd2
> 31)
1459 as_bad ("immediate operand out of range");
1462 opcode
|= (r1
<< 10) | ((opnd2
& 0x1f) << 4);
1466 as_bad ("immediate operand required");
1472 as_bad ("immediate operand required");
1479 /* 5-bit immediate * register, e.g. trace 1,r1 */
1480 str
= parse_exp (str
, &e1
);
1481 str
= skip_space (str
);
1482 if (e1
.X_op
== O_constant
&& *str
== ',')
1484 int opnd1
= e1
.X_add_number
;
1486 str
= skip_space (str
+ 1);
1487 ans
= parse_gen_reg (&str
, &r2
);
1490 as_bad ("SourceA register required");
1494 /* Got two operands, assemble instruction. */
1495 if (opnd1
< 0 || opnd1
> 31)
1497 as_bad ("1st operand out of range");
1499 opcode
|= ((opnd1
& 0x1f) << 10) | (r2
<< 16);
1503 as_bad ("Immediate operand required");
1509 /* register *= 16-bit unsigned immediate
1512 ans
= parse_gen_reg (&str
, &r1
);
1515 as_bad ("Dest register required");
1518 opcode
|= (r1
<< 16);
1520 str
= skip_space (str
);
1523 as_bad ("immediate value missing");
1530 /* MOVIL/WRTL traditionally get an implicit "%l" applied
1531 to their immediate value. For other opcodes, unless
1532 the immediate value is decorated with "%u" or "%l"
1533 it must be in the range 0 .. 65535. */
1534 if ((opcode
& 0x7fe00000) == 0x04800000
1535 || (opcode
& 0x7fe00000) == 0x05000000)
1536 reloc
= BFD_RELOC_VISIUM_LO16
;
1538 reloc
= BFD_RELOC_VISIUM_IM16
;
1540 str
= skip_space (str
+ 1);
1545 reloc
= BFD_RELOC_VISIUM_HI16
;
1546 else if (str
[1] == 'l')
1547 reloc
= BFD_RELOC_VISIUM_LO16
;
1550 as_bad ("bad char after %%");
1556 str
= parse_exp (str
, &e1
);
1557 if (e1
.X_op
!= O_absent
)
1559 if (e1
.X_op
== O_constant
)
1561 int imm
= e1
.X_add_number
;
1563 if (reloc
== BFD_RELOC_VISIUM_HI16
)
1564 opcode
|= ((imm
>> 16) & 0xffff);
1565 else if (reloc
== BFD_RELOC_VISIUM_LO16
)
1566 opcode
|= (imm
& 0xffff);
1569 if (imm
< 0 || imm
> 0xffff)
1570 as_bad ("immediate value out of range");
1572 opcode
|= (imm
& 0xffff);
1574 /* No relocation is needed. */
1580 as_bad ("immediate value missing");
1586 /* register * register * 5-bit immediate,
1587 SourceB * SourceA * Index
1591 str
= skip_space (str
);
1596 str
= parse_exp (str
, &e1
);
1597 if (e1
.X_op
== O_constant
)
1599 indx
= e1
.X_add_number
;
1601 if (indx
< 0 || indx
> 31)
1603 as_bad ("Index out of range");
1609 as_bad ("Index(SourceA) required");
1614 str
= skip_space (str
);
1618 as_bad ("Index(SourceA) required");
1622 str
= skip_space (str
+ 1);
1624 ans
= parse_gen_reg (&str
, &r1
);
1627 as_bad ("SourceA register required");
1630 str
= skip_space (str
);
1633 as_bad ("(SourceA) required");
1636 str
= skip_space (str
+ 1);
1640 str
= skip_space (str
+ 1);
1641 ans
= parse_gen_reg (&str
, &r2
);
1644 as_bad ("SourceB register required");
1650 as_bad ("SourceB register required");
1654 opcode
|= (r1
<< 16) | (r2
<< 4) | ((indx
& 0x1f) << 10);
1656 if (indx
!= 0 && previous_mode
== mode_cad
)
1658 /* We're in a delay slot.
1659 If the base reg is the destination of the branch, then issue
1661 Otherwise it is safe to use the base and index. */
1662 if (previous_dest
!= 0 && r1
== previous_dest
)
1664 as_bad ("base register not ready");
1668 else if (previous_dest
!= 0
1669 && r1
== previous_dest
1670 && (visium_arch
== VISIUM_ARCH_MCM
1671 || visium_arch
== VISIUM_ARCH_MCM24
1672 || (visium_arch
== VISIUM_ARCH_DEF
&& indx
!= 0)))
1674 as_warn ("base register not ready, NOP inserted.");
1675 /* Insert a NOP before the write instruction. */
1676 output
= frag_more (4);
1677 memset (output
, 0, 4);
1682 /* register := register * 5-bit immediate
1686 ans
= parse_gen_reg (&str
, &r1
);
1689 as_bad ("Dest register required");
1692 str
= skip_space (str
);
1695 as_bad ("SourceA required");
1698 str
= skip_space (str
+ 1);
1703 str
= parse_exp (str
, &e1
);
1704 if (e1
.X_op
== O_constant
)
1706 indx
= e1
.X_add_number
;
1708 if (indx
< 0 || indx
> 31)
1710 as_bad ("Index out of range");
1716 as_bad ("Immediate 0 to 31 required");
1722 as_bad ("(SourceA) required");
1726 ans
= parse_gen_reg (&str
, &r2
);
1729 as_bad ("SourceA register required");
1732 str
= skip_space (str
);
1735 as_bad ("(SourceA) required");
1739 opcode
|= (r1
<< 10) | (r2
<< 16) | ((indx
& 0x1f) << 4);
1742 if (indx
!= 0 && previous_mode
== mode_cad
)
1744 /* We're in a delay slot.
1745 If the base reg is the destination of the branch, then issue
1747 Otherwise it is safe to use the base and index. */
1748 if (previous_dest
!= 0 && r2
== previous_dest
)
1750 as_bad ("base register not ready");
1754 else if (previous_dest
!= 0
1755 && r2
== previous_dest
1756 && (visium_arch
== VISIUM_ARCH_MCM
1757 || visium_arch
== VISIUM_ARCH_MCM24
1758 || (visium_arch
== VISIUM_ARCH_DEF
&& indx
!= 0)))
1760 as_warn ("base register not ready, NOP inserted.");
1761 /* Insert a NOP before the read instruction. */
1762 output
= frag_more (4);
1763 memset (output
, 0, 4);
1771 str
= skip_space (str
);
1775 /* condition * 16-bit signed word displacement
1778 ans
= parse_cc (&str
, &cc
);
1781 as_bad ("condition code required");
1784 opcode
|= (cc
<< 27);
1786 str
= skip_space (str
);
1789 str
= skip_space (str
+ 1);
1790 str
= parse_exp (str
, &e1
);
1791 if (e1
.X_op
!= O_absent
)
1793 if (e1
.X_op
== O_constant
)
1795 int imm
= e1
.X_add_number
;
1797 if (imm
< -32768 || imm
> 32767)
1798 as_bad ("immediate value out of range");
1800 /* The GR6 doesn't correctly handle a 0 displacement
1801 so we insert a NOP and change it to -1. */
1802 if (imm
== 0 && cc
!= 0 && visium_arch
== VISIUM_ARCH_GR6
)
1804 output
= frag_more (4);
1805 memset (output
, 0, 4);
1809 opcode
|= (imm
& 0xffff);
1811 else if (e1
.X_op
== O_symbol
)
1813 /* The GR6 doesn't correctly handle a 0 displacement
1814 so the instruction requires relaxation. */
1815 if (cc
!= 0 && visium_arch
== VISIUM_ARCH_GR6
)
1818 reloc
= BFD_RELOC_VISIUM_REL16
;
1822 as_bad ("immediate value missing");
1828 as_bad ("immediate value missing");
1834 as_bad ("immediate value missing");
1838 if (previous_mode
== mode_cad
|| previous_mode
== mode_ci
)
1839 as_bad ("branch instruction in delay slot");
1841 condition_code
= cc
;
1845 /* float := float * float
1848 ans
= parse_fp_reg (&str
, &r1
);
1851 as_bad ("floating point destination register required");
1854 str
= skip_space (str
);
1858 ans
= parse_fp_reg (&str
, &r2
);
1861 as_bad ("floating point SourceA register required");
1864 str
= skip_space (str
);
1868 ans
= parse_fp_reg (&str
, &r3
);
1871 as_bad ("floating point SourceB register required");
1875 /* Got 3 floating regs, assemble instruction. */
1876 opcode
|= (r1
<< 10) | (r2
<< 16) | (r3
<< 4);
1880 as_bad ("floating point SourceB register required");
1886 as_bad ("floating point SourceA register required");
1892 /* 4-bit immediate * float * float * float
1894 fpinst 10,f1,f2,f3 */
1895 str
= parse_exp (str
, &e1
);
1896 str
= skip_space (str
);
1897 if (e1
.X_op
!= O_absent
&& *str
== ',')
1899 int finst
= e1
.X_add_number
;
1901 str
= skip_space (str
+ 1);
1902 ans
= parse_fp_reg (&str
, &r1
);
1905 as_bad ("floating point destination register required");
1908 str
= skip_space (str
);
1912 ans
= parse_fp_reg (&str
, &r2
);
1915 as_bad ("floating point SourceA register required");
1918 str
= skip_space (str
);
1922 ans
= parse_fp_reg (&str
, &r3
);
1925 as_bad ("floating point SourceB register required");
1929 /* Got immediate and 3 floating regs,
1930 assemble instruction. */
1931 if (finst
< 0 || finst
> 15)
1932 as_bad ("finst out of range");
1935 ((finst
& 0xf) << 27) | (r1
<< 10) | (r2
<< 16) | (r3
<<
1940 as_bad ("floating point SourceB register required");
1946 as_bad ("floating point SourceA register required");
1952 as_bad ("finst missing");
1958 /* 4-bit immediate * register * float * float
1960 fpuread 4,r25,f2,f3 */
1961 str
= parse_exp (str
, &e1
);
1962 str
= skip_space (str
);
1963 if (e1
.X_op
!= O_absent
&& *str
== ',')
1965 int finst
= e1
.X_add_number
;
1967 str
= skip_space (str
+ 1);
1968 ans
= parse_gen_reg (&str
, &r1
);
1971 as_bad ("destination general register required");
1974 str
= skip_space (str
);
1978 ans
= parse_fp_reg (&str
, &r2
);
1981 as_bad ("floating point SourceA register required");
1984 str
= skip_space (str
);
1988 ans
= parse_fp_reg (&str
, &r3
);
1991 as_bad ("floating point SourceB register required");
1995 /* Got immediate and 3 floating regs,
1996 assemble instruction. */
1997 if (finst
< 0 || finst
> 15)
1998 as_bad ("finst out of range");
2001 ((finst
& 0xf) << 27) | (r1
<< 10) | (r2
<< 16) | (r3
<<
2006 as_bad ("floating point SourceB register required");
2012 as_bad ("floating point SourceA register required");
2018 as_bad ("finst missing");
2027 ans
= parse_fp_reg (&str
, &r1
);
2030 as_bad ("floating point destination register required");
2033 str
= skip_space (str
);
2037 ans
= parse_fp_reg (&str
, &r2
);
2040 as_bad ("floating point source register required");
2044 /* Got 2 floating regs, assemble instruction. */
2045 opcode
|= (r1
<< 10) | (r2
<< 16);
2049 as_bad ("floating point source register required");
2055 /* float := register
2058 ans
= parse_fp_reg (&str
, &r1
);
2061 as_bad ("floating point destination register required");
2064 str
= skip_space (str
);
2068 ans
= parse_gen_reg (&str
, &r2
);
2071 as_bad ("SourceA general register required");
2075 /* Got 2 regs, assemble instruction. */
2076 opcode
|= (r1
<< 10) | (r2
<< 16);
2080 as_bad ("SourceA general register required");
2086 /* register := float * float
2089 For the GR6, register must be r0 and can be omitted. */
2090 ans
= parse_gen_reg (&str
, &r1
);
2093 if (visium_opcode_arch
== VISIUM_OPCODE_ARCH_GR5
)
2095 as_bad ("Dest general register required");
2102 if (r1
!= 0 && visium_opcode_arch
!= VISIUM_OPCODE_ARCH_GR5
)
2104 as_bad ("FCMP/FCMPE can only use r0 as Dest register");
2108 str
= skip_space (str
);
2113 as_bad ("floating point SourceA register required");
2118 ans
= parse_fp_reg (&str
, &r2
);
2121 as_bad ("floating point SourceA register required");
2124 str
= skip_space (str
);
2128 ans
= parse_fp_reg (&str
, &r3
);
2131 as_bad ("floating point SourceB register required");
2135 /* Got 3 regs, assemble instruction. */
2136 opcode
|= (r1
<< 10) | (r2
<< 16) | (r3
<< 4);
2143 /* register := float
2146 ans
= parse_gen_reg (&str
, &r1
);
2149 as_bad ("Dest general register required");
2152 str
= skip_space (str
);
2156 ans
= parse_fp_reg (&str
, &r2
);
2159 as_bad ("floating point source register required");
2163 /* Got 2 regs, assemble instruction. */
2164 opcode
|= (r1
<< 10) | (r2
<< 16);
2168 as_bad ("floating point source register required");
2176 /* register register register, all sources and destinations
2180 ans
= parse_gen_reg (&str
, &r1
);
2183 as_bad ("destination address register required");
2186 str
= skip_space (str
);
2190 ans
= parse_gen_reg (&str
, &r2
);
2193 as_bad ("source address register required");
2196 str
= skip_space (str
);
2200 ans
= parse_gen_reg (&str
, &r3
);
2203 as_bad ("count register required");
2207 /* We insist on three registers but the opcode can only use
2209 if (r1
!= 1 || r2
!= 2 || r3
!= 3)
2211 as_bad ("BMI/BMD can only use format op r1,r2,r3");
2215 /* Opcode is unmodified by what comes out of the table. */
2219 as_bad ("register required");
2225 as_bad ("register required");
2237 output
= frag_var (rs_machine_dependent
, 8, 4, relax
, e1
.X_add_symbol
,
2238 e1
.X_add_number
, NULL
);
2240 output
= frag_more (4);
2242 /* Build the 32-bit instruction in a host-endian-neutral fashion. */
2243 output
[0] = (opcode
>> 24) & 0xff;
2244 output
[1] = (opcode
>> 16) & 0xff;
2245 output
[2] = (opcode
>> 8) & 0xff;
2246 output
[3] = (opcode
>> 0) & 0xff;
2249 /* The size of the instruction is unknown, so tie the debug info to the
2250 start of the instruction. */
2251 dwarf2_emit_insn (0);
2255 fix_new_exp (frag_now
, output
- frag_now
->fr_literal
, 4, &e1
,
2256 reloc
== BFD_RELOC_VISIUM_REL16
, reloc
);
2258 visium_update_parity_bit (output
);
2260 dwarf2_emit_insn (4);
2264 as_bad ("junk after instruction");
2268 visium_cfi_frame_initial_instructions (void)
2270 /* The CFA is in SP on function entry. */
2271 cfi_add_CFA_def_cfa (23, 0);
2275 visium_regname_to_dw2regnum (char *regname
)
2280 if (regname
[0] == 'f' && regname
[1] == 'p' && !regname
[2])
2283 if (regname
[0] == 's' && regname
[1] == 'p' && !regname
[2])
2286 if (regname
[0] == 'm' && regname
[1] == 'd' && !regname
[3])
2289 case 'b': return 32;
2290 case 'a': return 33;
2291 case 'c': return 34;
2292 default : return -1;
2295 if (regname
[0] == 'f' || regname
[0] == 'r')
2298 unsigned int regnum
= strtoul (regname
+ 1, &p
, 10);
2301 if (regnum
>= (regname
[0] == 'f' ? 16 : 32))
2303 if (regname
[0] == 'f')