1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 size_t xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT
get_expanded_loop_offset (xtensa_opcode
);
440 static fragS
*get_literal_pool_location (segT
);
441 static void set_literal_pool_location (segT
, fragS
*);
442 static void xtensa_set_frag_assembly_state (fragS
*);
443 static void finish_vinsn (vliw_insn
*);
444 static bfd_boolean
emit_single_op (TInsn
*);
445 static int total_frag_text_expansion (fragS
*);
447 /* Alignment Functions. */
449 static size_t get_text_align_power (int);
450 static addressT
get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
452 /* Helpers for xtensa_relax_frag(). */
454 static long relax_frag_add_nop (fragS
*);
456 /* Accessors for additional per-subsegment information. */
458 static unsigned get_last_insn_flags (segT
, subsegT
);
459 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
460 static float get_subseg_total_freq (segT
, subsegT
);
461 static float get_subseg_target_freq (segT
, subsegT
);
462 static void set_subseg_freq (segT
, subsegT
, float, float);
464 /* Segment list functions. */
466 static void xtensa_move_literals (void);
467 static void xtensa_reorder_segments (void);
468 static void xtensa_switch_to_literal_fragment (emit_state
*);
469 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
470 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
471 static void xtensa_restore_emit_state (emit_state
*);
472 static void cache_literal_section
473 (seg_list
*, const char *, segT
*, bfd_boolean
);
475 /* Import from elf32-xtensa.c in BFD library. */
477 extern char *xtensa_get_property_section_name (asection
*, const char *);
479 /* op_placement_info functions. */
481 static void init_op_placement_info_table (void);
482 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
483 static int xg_get_single_size (xtensa_opcode
);
484 static xtensa_format
xg_get_single_format (xtensa_opcode
);
486 /* TInsn and IStack functions. */
488 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
489 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
490 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
491 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
492 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
493 static void tinsn_from_chars (TInsn
*, char *, int);
494 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
495 static int get_num_stack_text_bytes (IStack
*);
496 static int get_num_stack_literal_bytes (IStack
*);
498 /* vliw_insn functions. */
500 static void xg_init_vinsn (vliw_insn
*);
501 static void xg_clear_vinsn (vliw_insn
*);
502 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
503 static void xg_free_vinsn (vliw_insn
*);
504 static bfd_boolean vinsn_to_insnbuf
505 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
506 static void vinsn_from_chars (vliw_insn
*, char *);
508 /* Expression Utilities. */
510 bfd_boolean
expr_is_const (const expressionS
*);
511 offsetT
get_expr_const (const expressionS
*);
512 void set_expr_const (expressionS
*, offsetT
);
513 bfd_boolean
expr_is_register (const expressionS
*);
514 offsetT
get_expr_register (const expressionS
*);
515 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
516 static void set_expr_symbol_offset_diff
517 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
518 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
519 static void copy_expr (expressionS
*, const expressionS
*);
521 /* Section renaming. */
523 static void build_section_rename (const char *);
526 /* ISA imported from bfd. */
527 extern xtensa_isa xtensa_default_isa
;
529 extern int target_big_endian
;
531 static xtensa_opcode xtensa_addi_opcode
;
532 static xtensa_opcode xtensa_addmi_opcode
;
533 static xtensa_opcode xtensa_call0_opcode
;
534 static xtensa_opcode xtensa_call4_opcode
;
535 static xtensa_opcode xtensa_call8_opcode
;
536 static xtensa_opcode xtensa_call12_opcode
;
537 static xtensa_opcode xtensa_callx0_opcode
;
538 static xtensa_opcode xtensa_callx4_opcode
;
539 static xtensa_opcode xtensa_callx8_opcode
;
540 static xtensa_opcode xtensa_callx12_opcode
;
541 static xtensa_opcode xtensa_const16_opcode
;
542 static xtensa_opcode xtensa_entry_opcode
;
543 static xtensa_opcode xtensa_movi_opcode
;
544 static xtensa_opcode xtensa_movi_n_opcode
;
545 static xtensa_opcode xtensa_isync_opcode
;
546 static xtensa_opcode xtensa_jx_opcode
;
547 static xtensa_opcode xtensa_l32r_opcode
;
548 static xtensa_opcode xtensa_loop_opcode
;
549 static xtensa_opcode xtensa_loopnez_opcode
;
550 static xtensa_opcode xtensa_loopgtz_opcode
;
551 static xtensa_opcode xtensa_nop_opcode
;
552 static xtensa_opcode xtensa_nop_n_opcode
;
553 static xtensa_opcode xtensa_or_opcode
;
554 static xtensa_opcode xtensa_ret_opcode
;
555 static xtensa_opcode xtensa_ret_n_opcode
;
556 static xtensa_opcode xtensa_retw_opcode
;
557 static xtensa_opcode xtensa_retw_n_opcode
;
558 static xtensa_opcode xtensa_rsr_lcount_opcode
;
559 static xtensa_opcode xtensa_waiti_opcode
;
562 /* Command-line Options. */
564 bfd_boolean use_literal_section
= TRUE
;
565 static bfd_boolean align_targets
= TRUE
;
566 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
567 static bfd_boolean has_a0_b_retw
= FALSE
;
568 static bfd_boolean workaround_a0_b_retw
= FALSE
;
569 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
570 static bfd_boolean workaround_short_loop
= FALSE
;
571 static bfd_boolean maybe_has_short_loop
= FALSE
;
572 static bfd_boolean workaround_close_loop_end
= FALSE
;
573 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
575 /* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
581 static bfd_boolean workaround_all_short_loops
= FALSE
;
585 xtensa_setup_hw_workarounds (int earliest
, int latest
)
587 if (earliest
> latest
)
588 as_fatal (_("illegal range of target hardware versions"));
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest
< 105000 || latest
< 105000)
593 workaround_a0_b_retw
|= TRUE
;
594 workaround_b_j_loop_end
|= TRUE
;
595 workaround_short_loop
|= TRUE
;
596 workaround_close_loop_end
|= TRUE
;
597 workaround_all_short_loops
|= TRUE
;
604 option_density
= OPTION_MD_BASE
,
611 option_no_link_relax
,
619 option_text_section_literals
,
620 option_no_text_section_literals
,
622 option_absolute_literals
,
623 option_no_absolute_literals
,
625 option_align_targets
,
626 option_no_align_targets
,
628 option_warn_unaligned_targets
,
633 option_workaround_a0_b_retw
,
634 option_no_workaround_a0_b_retw
,
636 option_workaround_b_j_loop_end
,
637 option_no_workaround_b_j_loop_end
,
639 option_workaround_short_loop
,
640 option_no_workaround_short_loop
,
642 option_workaround_all_short_loops
,
643 option_no_workaround_all_short_loops
,
645 option_workaround_close_loop_end
,
646 option_no_workaround_close_loop_end
,
648 option_no_workarounds
,
650 option_rename_section_name
,
653 option_prefer_const16
,
655 option_target_hardware
658 const char *md_shortopts
= "";
660 struct option md_longopts
[] =
662 { "density", no_argument
, NULL
, option_density
},
663 { "no-density", no_argument
, NULL
, option_no_density
},
665 /* Both "relax" and "generics" are deprecated and treated as equivalent
666 to the "transform" option. */
667 { "relax", no_argument
, NULL
, option_relax
},
668 { "no-relax", no_argument
, NULL
, option_no_relax
},
669 { "generics", no_argument
, NULL
, option_generics
},
670 { "no-generics", no_argument
, NULL
, option_no_generics
},
672 { "transform", no_argument
, NULL
, option_transform
},
673 { "no-transform", no_argument
, NULL
, option_no_transform
},
674 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
675 { "no-text-section-literals", no_argument
, NULL
,
676 option_no_text_section_literals
},
677 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
678 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
679 /* This option was changed from -align-target to -target-align
680 because it conflicted with the "-al" option. */
681 { "target-align", no_argument
, NULL
, option_align_targets
},
682 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
683 { "warn-unaligned-targets", no_argument
, NULL
,
684 option_warn_unaligned_targets
},
685 { "longcalls", no_argument
, NULL
, option_longcalls
},
686 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
688 { "no-workaround-a0-b-retw", no_argument
, NULL
,
689 option_no_workaround_a0_b_retw
},
690 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
692 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
693 option_no_workaround_b_j_loop_end
},
694 { "workaround-b-j-loop-end", no_argument
, NULL
,
695 option_workaround_b_j_loop_end
},
697 { "no-workaround-short-loops", no_argument
, NULL
,
698 option_no_workaround_short_loop
},
699 { "workaround-short-loops", no_argument
, NULL
,
700 option_workaround_short_loop
},
702 { "no-workaround-all-short-loops", no_argument
, NULL
,
703 option_no_workaround_all_short_loops
},
704 { "workaround-all-short-loop", no_argument
, NULL
,
705 option_workaround_all_short_loops
},
707 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
708 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
710 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
712 { "no-workaround-close-loop-end", no_argument
, NULL
,
713 option_no_workaround_close_loop_end
},
714 { "workaround-close-loop-end", no_argument
, NULL
,
715 option_workaround_close_loop_end
},
717 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
719 { "link-relax", no_argument
, NULL
, option_link_relax
},
720 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
722 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
724 { NULL
, no_argument
, NULL
, 0 }
727 size_t md_longopts_size
= sizeof md_longopts
;
731 md_parse_option (int c
, char *arg
)
736 as_warn (_("--density option is ignored"));
738 case option_no_density
:
739 as_warn (_("--no-density option is ignored"));
741 case option_link_relax
:
744 case option_no_link_relax
:
747 case option_generics
:
748 as_warn (_("--generics is deprecated; use --transform instead"));
749 return md_parse_option (option_transform
, arg
);
750 case option_no_generics
:
751 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform
, arg
);
754 as_warn (_("--relax is deprecated; use --transform instead"));
755 return md_parse_option (option_transform
, arg
);
756 case option_no_relax
:
757 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
758 return md_parse_option (option_no_transform
, arg
);
759 case option_longcalls
:
760 directive_state
[directive_longcalls
] = TRUE
;
762 case option_no_longcalls
:
763 directive_state
[directive_longcalls
] = FALSE
;
765 case option_text_section_literals
:
766 use_literal_section
= FALSE
;
768 case option_no_text_section_literals
:
769 use_literal_section
= TRUE
;
771 case option_absolute_literals
:
772 if (!absolute_literals_supported
)
774 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
777 directive_state
[directive_absolute_literals
] = TRUE
;
779 case option_no_absolute_literals
:
780 directive_state
[directive_absolute_literals
] = FALSE
;
783 case option_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= TRUE
;
786 case option_no_workaround_a0_b_retw
:
787 workaround_a0_b_retw
= FALSE
;
789 case option_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= TRUE
;
792 case option_no_workaround_b_j_loop_end
:
793 workaround_b_j_loop_end
= FALSE
;
796 case option_workaround_short_loop
:
797 workaround_short_loop
= TRUE
;
799 case option_no_workaround_short_loop
:
800 workaround_short_loop
= FALSE
;
803 case option_workaround_all_short_loops
:
804 workaround_all_short_loops
= TRUE
;
806 case option_no_workaround_all_short_loops
:
807 workaround_all_short_loops
= FALSE
;
810 case option_workaround_close_loop_end
:
811 workaround_close_loop_end
= TRUE
;
813 case option_no_workaround_close_loop_end
:
814 workaround_close_loop_end
= FALSE
;
817 case option_no_workarounds
:
818 workaround_a0_b_retw
= FALSE
;
819 workaround_b_j_loop_end
= FALSE
;
820 workaround_short_loop
= FALSE
;
821 workaround_all_short_loops
= FALSE
;
822 workaround_close_loop_end
= FALSE
;
825 case option_align_targets
:
826 align_targets
= TRUE
;
828 case option_no_align_targets
:
829 align_targets
= FALSE
;
832 case option_warn_unaligned_targets
:
833 warn_unaligned_branch_targets
= TRUE
;
836 case option_rename_section_name
:
837 build_section_rename (arg
);
841 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
842 should be emitted or not. FIXME: Not implemented. */
845 case option_prefer_l32r
:
847 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
851 case option_prefer_const16
:
853 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
857 case option_target_hardware
:
859 int earliest
, latest
= 0;
860 if (*arg
== 0 || *arg
== '-')
861 as_fatal (_("invalid target hardware version"));
863 earliest
= strtol (arg
, &arg
, 0);
867 else if (*arg
== '-')
870 as_fatal (_("invalid target hardware version"));
871 latest
= strtol (arg
, &arg
, 0);
874 as_fatal (_("invalid target hardware version"));
876 xtensa_setup_hw_workarounds (earliest
, latest
);
880 case option_transform
:
881 /* This option has no affect other than to use the defaults,
882 which are already set. */
885 case option_no_transform
:
886 /* This option turns off all transformations of any kind.
887 However, because we want to preserve the state of other
888 directives, we only change its own field. Thus, before
889 you perform any transformation, always check if transform
890 is available. If you use the functions we provide for this
891 purpose, you will be ok. */
892 directive_state
[directive_transform
] = FALSE
;
902 md_show_usage (FILE *stream
)
906 --[no-]text-section-literals\n\
907 [Do not] put literals in the text section\n\
908 --[no-]absolute-literals\n\
909 [Do not] default to use non-PC-relative literals\n\
910 --[no-]target-align [Do not] try to align branch targets\n\
911 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
912 --[no-]transform [Do not] transform instructions\n\
913 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
917 /* Functions related to the list of current label symbols. */
920 xtensa_add_insn_label (symbolS
*sym
)
924 if (!free_insn_labels
)
925 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
928 l
= free_insn_labels
;
929 free_insn_labels
= l
->next
;
933 l
->next
= insn_labels
;
939 xtensa_clear_insn_labels (void)
943 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
950 /* The "loops_ok" argument is provided to allow ignoring labels that
951 define loop ends. This fixes a bug where the NOPs to align a
952 loop opcode were included in a previous zero-cost loop:
971 This argument is used to prevent moving the NOP to before the
972 loop-end label, which is what you want in this special case. */
975 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
979 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
981 symbolS
*lit_sym
= lit
->sym
;
982 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
984 S_SET_VALUE (lit_sym
, new_offset
);
985 symbol_set_frag (lit_sym
, new_frag
);
991 /* Directive data and functions. */
993 typedef struct state_stackS_struct
995 directiveE directive
;
997 bfd_boolean old_state
;
1001 struct state_stackS_struct
*prev
;
1004 state_stackS
*directive_state_stack
;
1006 const pseudo_typeS md_pseudo_table
[] =
1008 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1009 { "literal_position", xtensa_literal_position
, 0 },
1010 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1011 { "long", xtensa_elf_cons
, 4 },
1012 { "word", xtensa_elf_cons
, 4 },
1013 { "short", xtensa_elf_cons
, 2 },
1014 { "begin", xtensa_begin_directive
, 0 },
1015 { "end", xtensa_end_directive
, 0 },
1016 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1017 { "literal", xtensa_literal_pseudo
, 0 },
1018 { "frequency", xtensa_frequency_pseudo
, 0 },
1024 use_transform (void)
1026 /* After md_end, you should be checking frag by frag, rather
1027 than state directives. */
1028 assert (!past_xtensa_end
);
1029 return directive_state
[directive_transform
];
1034 do_align_targets (void)
1036 /* After md_end, you should be checking frag by frag, rather
1037 than state directives. */
1038 assert (!past_xtensa_end
);
1039 return align_targets
&& use_transform ();
1044 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1048 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1050 as_where (&file
, &line
);
1052 stack
->directive
= directive
;
1053 stack
->negated
= negated
;
1054 stack
->old_state
= directive_state
[directive
];
1057 stack
->datum
= datum
;
1058 stack
->prev
= directive_state_stack
;
1059 directive_state_stack
= stack
;
1061 directive_state
[directive
] = !negated
;
1066 directive_pop (directiveE
*directive
,
1067 bfd_boolean
*negated
,
1072 state_stackS
*top
= directive_state_stack
;
1074 if (!directive_state_stack
)
1076 as_bad (_("unmatched end directive"));
1077 *directive
= directive_none
;
1081 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1082 *directive
= top
->directive
;
1083 *negated
= top
->negated
;
1086 *datum
= top
->datum
;
1087 directive_state_stack
= top
->prev
;
1093 directive_balance (void)
1095 while (directive_state_stack
)
1097 directiveE directive
;
1098 bfd_boolean negated
;
1103 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1104 as_warn_where ((char *) file
, line
,
1105 _(".begin directive with no matching .end directive"));
1111 inside_directive (directiveE dir
)
1113 state_stackS
*top
= directive_state_stack
;
1115 while (top
&& top
->directive
!= dir
)
1118 return (top
!= NULL
);
1123 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1127 char *directive_string
;
1129 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1134 input_line_pointer
+= 3;
1137 len
= strspn (input_line_pointer
,
1138 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1140 /* This code is a hack to make .begin [no-][generics|relax] exactly
1141 equivalent to .begin [no-]transform. We should remove it when
1142 we stop accepting those options. */
1144 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1146 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1147 directive_string
= "transform";
1149 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1151 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1152 directive_string
= "transform";
1155 directive_string
= input_line_pointer
;
1157 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1159 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1161 input_line_pointer
+= len
;
1162 *directive
= (directiveE
) i
;
1163 if (*negated
&& !directive_info
[i
].can_be_negated
)
1164 as_bad (_("directive %s cannot be negated"),
1165 directive_info
[i
].name
);
1170 as_bad (_("unknown directive"));
1171 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1176 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1178 directiveE directive
;
1179 bfd_boolean negated
;
1184 get_directive (&directive
, &negated
);
1185 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1187 discard_rest_of_line ();
1191 if (cur_vinsn
.inside_bundle
)
1192 as_bad (_("directives are not valid inside bundles"));
1196 case directive_literal
:
1197 if (!inside_directive (directive_literal
))
1199 /* Previous labels go with whatever follows this directive, not with
1200 the literal, so save them now. */
1201 saved_insn_labels
= insn_labels
;
1204 as_warn (_(".begin literal is deprecated; use .literal instead"));
1205 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1206 xtensa_switch_to_literal_fragment (state
);
1207 directive_push (directive_literal
, negated
, state
);
1210 case directive_literal_prefix
:
1211 /* Have to flush pending output because a movi relaxed to an l32r
1212 might produce a literal. */
1213 md_flush_pending_output ();
1214 /* Check to see if the current fragment is a literal
1215 fragment. If it is, then this operation is not allowed. */
1216 if (generating_literals
)
1218 as_bad (_("cannot set literal_prefix inside literal fragment"));
1222 /* Allocate the literal state for this section and push
1223 onto the directive stack. */
1224 ls
= xmalloc (sizeof (lit_state
));
1227 *ls
= default_lit_sections
;
1229 directive_push (directive_literal_prefix
, negated
, ls
);
1231 /* Parse the new prefix from the input_line_pointer. */
1233 len
= strspn (input_line_pointer
,
1234 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1235 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1237 /* Process the new prefix. */
1238 xtensa_literal_prefix (input_line_pointer
, len
);
1240 /* Skip the name in the input line. */
1241 input_line_pointer
+= len
;
1244 case directive_freeregs
:
1245 /* This information is currently unused, but we'll accept the statement
1246 and just discard the rest of the line. This won't check the syntax,
1247 but it will accept every correct freeregs directive. */
1248 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1249 directive_push (directive_freeregs
, negated
, 0);
1252 case directive_schedule
:
1253 md_flush_pending_output ();
1254 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1255 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1256 directive_push (directive_schedule
, negated
, 0);
1257 xtensa_set_frag_assembly_state (frag_now
);
1260 case directive_density
:
1261 as_warn (_(".begin [no-]density is ignored"));
1264 case directive_absolute_literals
:
1265 md_flush_pending_output ();
1266 if (!absolute_literals_supported
&& !negated
)
1268 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1271 xtensa_set_frag_assembly_state (frag_now
);
1272 directive_push (directive
, negated
, 0);
1276 md_flush_pending_output ();
1277 xtensa_set_frag_assembly_state (frag_now
);
1278 directive_push (directive
, negated
, 0);
1282 demand_empty_rest_of_line ();
1287 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1289 directiveE begin_directive
, end_directive
;
1290 bfd_boolean begin_negated
, end_negated
;
1294 emit_state
**state_ptr
;
1297 if (cur_vinsn
.inside_bundle
)
1298 as_bad (_("directives are not valid inside bundles"));
1300 get_directive (&end_directive
, &end_negated
);
1302 md_flush_pending_output ();
1304 switch (end_directive
)
1306 case (directiveE
) XTENSA_UNDEFINED
:
1307 discard_rest_of_line ();
1310 case directive_density
:
1311 as_warn (_(".end [no-]density is ignored"));
1312 demand_empty_rest_of_line ();
1315 case directive_absolute_literals
:
1316 if (!absolute_literals_supported
&& !end_negated
)
1318 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1319 demand_empty_rest_of_line ();
1328 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1329 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1330 (const void **) state_ptr
);
1332 if (begin_directive
!= directive_none
)
1334 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1336 as_bad (_("does not match begin %s%s at %s:%d"),
1337 begin_negated
? "no-" : "",
1338 directive_info
[begin_directive
].name
, file
, line
);
1342 switch (end_directive
)
1344 case directive_literal
:
1345 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1346 xtensa_restore_emit_state (state
);
1347 xtensa_set_frag_assembly_state (frag_now
);
1349 if (!inside_directive (directive_literal
))
1351 /* Restore the list of current labels. */
1352 xtensa_clear_insn_labels ();
1353 insn_labels
= saved_insn_labels
;
1357 case directive_literal_prefix
:
1358 /* Restore the default collection sections from saved state. */
1359 s
= (lit_state
*) state
;
1362 if (use_literal_section
)
1363 default_lit_sections
= *s
;
1365 /* free the state storage */
1369 case directive_schedule
:
1370 case directive_freeregs
:
1374 xtensa_set_frag_assembly_state (frag_now
);
1380 demand_empty_rest_of_line ();
1384 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1386 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1389 xtensa_dwarf2_directive_loc (int x
)
1391 xtensa_loc_directive_seen
= TRUE
;
1392 dwarf2_directive_loc (x
);
1397 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1399 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1401 xtensa_loc_directive_seen
= FALSE
;
1402 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1406 /* Place an aligned literal fragment at the current location. */
1409 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1411 md_flush_pending_output ();
1413 if (inside_directive (directive_literal
))
1414 as_warn (_(".literal_position inside literal directive; ignoring"));
1415 xtensa_mark_literal_pool_location ();
1417 demand_empty_rest_of_line ();
1418 xtensa_clear_insn_labels ();
1422 /* Support .literal label, expr, ... */
1425 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1428 char *p
, *base_name
;
1432 if (inside_directive (directive_literal
))
1434 as_bad (_(".literal not allowed inside .begin literal region"));
1435 ignore_rest_of_line ();
1439 md_flush_pending_output ();
1441 /* Previous labels go with whatever follows this directive, not with
1442 the literal, so save them now. */
1443 saved_insn_labels
= insn_labels
;
1446 /* If we are using text-section literals, then this is the right value... */
1449 base_name
= input_line_pointer
;
1451 xtensa_switch_to_literal_fragment (&state
);
1453 /* ...but if we aren't using text-section-literals, then we
1454 need to put them in the section we just switched to. */
1455 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1458 /* All literals are aligned to four-byte boundaries. */
1459 frag_align (2, 0, 0);
1460 record_alignment (now_seg
, 2);
1462 c
= get_symbol_end ();
1463 /* Just after name is now '\0'. */
1464 p
= input_line_pointer
;
1468 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1470 as_bad (_("expected comma or colon after symbol name; "
1471 "rest of line ignored"));
1472 ignore_rest_of_line ();
1473 xtensa_restore_emit_state (&state
);
1481 input_line_pointer
++; /* skip ',' or ':' */
1483 xtensa_elf_cons (4);
1485 xtensa_restore_emit_state (&state
);
1487 /* Restore the list of current labels. */
1488 xtensa_clear_insn_labels ();
1489 insn_labels
= saved_insn_labels
;
1494 xtensa_literal_prefix (char const *start
, int len
)
1496 char *name
, *linkonce_suffix
;
1497 char *newname
, *newname4
;
1498 size_t linkonce_len
;
1500 /* Get a null-terminated copy of the name. */
1501 name
= xmalloc (len
+ 1);
1504 strncpy (name
, start
, len
);
1507 /* Allocate the sections (interesting note: the memory pointing to
1508 the name is actually used for the name by the new section). */
1510 newname
= xmalloc (len
+ strlen (".literal") + 1);
1511 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1513 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1514 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1515 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1517 strcpy (newname
, ".gnu.linkonce.literal");
1518 strcpy (newname4
, ".gnu.linkonce.lit4");
1520 strcat (newname
, linkonce_suffix
);
1521 strcat (newname4
, linkonce_suffix
);
1525 int suffix_pos
= len
;
1527 /* If the section name ends with ".text", then replace that suffix
1528 instead of appending an additional suffix. */
1529 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1532 strcpy (newname
, name
);
1533 strcpy (newname4
, name
);
1535 strcpy (newname
+ suffix_pos
, ".literal");
1536 strcpy (newname4
+ suffix_pos
, ".lit4");
1539 /* Note that cache_literal_section does not create a segment if
1540 it already exists. */
1541 default_lit_sections
.lit_seg
= NULL
;
1542 default_lit_sections
.lit4_seg
= NULL
;
1544 /* Canonicalizing section names allows renaming literal
1545 sections to occur correctly. */
1546 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1547 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1553 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1556 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1558 float fall_through_f
, target_f
;
1560 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1561 if (fall_through_f
< 0)
1563 as_bad (_("fall through frequency must be greater than 0"));
1564 ignore_rest_of_line ();
1568 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1571 as_bad (_("branch target frequency must be greater than 0"));
1572 ignore_rest_of_line ();
1576 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1578 demand_empty_rest_of_line ();
1582 /* Like normal .long/.short/.word, except support @plt, etc.
1583 Clobbers input_line_pointer, checks end-of-line. */
1586 xtensa_elf_cons (int nbytes
)
1589 bfd_reloc_code_real_type reloc
;
1591 md_flush_pending_output ();
1593 if (cur_vinsn
.inside_bundle
)
1594 as_bad (_("directives are not valid inside bundles"));
1596 if (is_it_end_of_statement ())
1598 demand_empty_rest_of_line ();
1605 if (exp
.X_op
== O_symbol
1606 && *input_line_pointer
== '@'
1607 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1610 reloc_howto_type
*reloc_howto
=
1611 bfd_reloc_type_lookup (stdoutput
, reloc
);
1613 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1614 as_bad (_("unsupported relocation"));
1615 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1616 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1617 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1618 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1619 as_bad (_("opcode-specific %s relocation used outside "
1620 "an instruction"), reloc_howto
->name
);
1621 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1622 as_bad (_("%s relocations do not fit in %d bytes"),
1623 reloc_howto
->name
, nbytes
);
1626 char *p
= frag_more ((int) nbytes
);
1627 xtensa_set_frag_assembly_state (frag_now
);
1628 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1629 nbytes
, &exp
, 0, reloc
);
1633 emit_expr (&exp
, (unsigned int) nbytes
);
1635 while (*input_line_pointer
++ == ',');
1637 input_line_pointer
--; /* Put terminator back into stream. */
1638 demand_empty_rest_of_line ();
1642 /* Parsing and Idiom Translation. */
1644 /* Parse @plt, etc. and return the desired relocation. */
1645 static bfd_reloc_code_real_type
1646 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1652 bfd_reloc_code_real_type reloc
;
1660 struct map_bfd
*ptr
;
1662 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1664 static struct map_bfd mapping
[] =
1666 MAP ("l", BFD_RELOC_LO16
),
1667 MAP ("h", BFD_RELOC_HI16
),
1668 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1669 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1673 return BFD_RELOC_NONE
;
1675 for (ch
= *str
, str2
= ident
;
1676 (str2
< ident
+ sizeof (ident
) - 1
1677 && (ISALNUM (ch
) || ch
== '@'));
1680 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1687 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1688 if (ch
== ptr
->string
[0]
1689 && len
== ptr
->length
1690 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1692 /* Now check for "identifier@suffix+constant". */
1693 if (*str
== '-' || *str
== '+')
1695 char *orig_line
= input_line_pointer
;
1696 expressionS new_exp
;
1698 input_line_pointer
= str
;
1699 expression (&new_exp
);
1700 if (new_exp
.X_op
== O_constant
)
1702 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1703 str
= input_line_pointer
;
1706 if (&input_line_pointer
!= str_p
)
1707 input_line_pointer
= orig_line
;
1714 return BFD_RELOC_UNUSED
;
1719 expression_end (const char *name
)
1742 #define ERROR_REG_NUM ((unsigned) -1)
1745 tc_get_register (const char *prefix
)
1748 const char *next_expr
;
1749 const char *old_line_pointer
;
1752 old_line_pointer
= input_line_pointer
;
1754 if (*input_line_pointer
== '$')
1755 ++input_line_pointer
;
1757 /* Accept "sp" as a synonym for "a1". */
1758 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1759 && expression_end (input_line_pointer
+ 2))
1761 input_line_pointer
+= 2;
1762 return 1; /* AR[1] */
1765 while (*input_line_pointer
++ == *prefix
++)
1767 --input_line_pointer
;
1772 as_bad (_("bad register name: %s"), old_line_pointer
);
1773 return ERROR_REG_NUM
;
1776 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1778 as_bad (_("bad register number: %s"), input_line_pointer
);
1779 return ERROR_REG_NUM
;
1784 while (ISDIGIT ((int) *input_line_pointer
))
1785 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1787 if (!(next_expr
= expression_end (input_line_pointer
)))
1789 as_bad (_("bad register name: %s"), old_line_pointer
);
1790 return ERROR_REG_NUM
;
1793 input_line_pointer
= (char *) next_expr
;
1800 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1802 xtensa_isa isa
= xtensa_default_isa
;
1804 /* Check if this is an immediate operand. */
1805 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1807 bfd_reloc_code_real_type reloc
;
1808 segT t
= expression (tok
);
1809 if (t
== absolute_section
1810 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1812 assert (tok
->X_op
== O_constant
);
1813 tok
->X_op
= O_symbol
;
1814 tok
->X_add_symbol
= &abs_symbol
;
1817 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1818 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1819 && (reloc
!= BFD_RELOC_NONE
))
1824 case BFD_RELOC_UNUSED
:
1825 as_bad (_("unsupported relocation"));
1828 case BFD_RELOC_XTENSA_PLT
:
1829 tok
->X_op
= O_pltrel
;
1832 case BFD_RELOC_LO16
:
1833 if (tok
->X_op
== O_constant
)
1834 tok
->X_add_number
&= 0xffff;
1839 case BFD_RELOC_HI16
:
1840 if (tok
->X_op
== O_constant
)
1841 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1850 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1851 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1853 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1856 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1857 as_bad (_("register number out of range"));
1860 tok
->X_op
= O_register
;
1861 tok
->X_add_symbol
= 0;
1862 tok
->X_add_number
= reg
;
1867 /* Split up the arguments for an opcode or pseudo-op. */
1870 tokenize_arguments (char **args
, char *str
)
1872 char *old_input_line_pointer
;
1873 bfd_boolean saw_comma
= FALSE
;
1874 bfd_boolean saw_arg
= FALSE
;
1875 bfd_boolean saw_colon
= FALSE
;
1877 char *arg_end
, *arg
;
1880 /* Save and restore input_line_pointer around this function. */
1881 old_input_line_pointer
= input_line_pointer
;
1882 input_line_pointer
= str
;
1884 while (*input_line_pointer
)
1887 switch (*input_line_pointer
)
1894 input_line_pointer
++;
1895 if (saw_comma
|| saw_colon
|| !saw_arg
)
1901 input_line_pointer
++;
1902 if (saw_comma
|| saw_colon
|| !saw_arg
)
1908 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1911 arg_end
= input_line_pointer
+ 1;
1912 while (!expression_end (arg_end
))
1915 arg_len
= arg_end
- input_line_pointer
;
1916 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1917 args
[num_args
] = arg
;
1921 strncpy (arg
, input_line_pointer
, arg_len
);
1922 arg
[arg_len
] = '\0';
1924 input_line_pointer
= arg_end
;
1934 if (saw_comma
|| saw_colon
)
1936 input_line_pointer
= old_input_line_pointer
;
1941 as_bad (_("extra comma"));
1943 as_bad (_("extra colon"));
1945 as_bad (_("missing argument"));
1947 as_bad (_("missing comma or colon"));
1948 input_line_pointer
= old_input_line_pointer
;
1953 /* Parse the arguments to an opcode. Return TRUE on error. */
1956 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1958 expressionS
*tok
, *last_tok
;
1959 xtensa_opcode opcode
= insn
->opcode
;
1960 bfd_boolean had_error
= TRUE
;
1961 xtensa_isa isa
= xtensa_default_isa
;
1962 int n
, num_regs
= 0;
1963 int opcode_operand_count
;
1964 int opnd_cnt
, last_opnd_cnt
;
1965 unsigned int next_reg
= 0;
1966 char *old_input_line_pointer
;
1968 if (insn
->insn_type
== ITYPE_LITERAL
)
1969 opcode_operand_count
= 1;
1971 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1974 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1976 /* Save and restore input_line_pointer around this function. */
1977 old_input_line_pointer
= input_line_pointer
;
1983 /* Skip invisible operands. */
1984 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1990 for (n
= 0; n
< num_args
; n
++)
1992 input_line_pointer
= arg_strings
[n
];
1993 if (*input_line_pointer
== ':')
1995 xtensa_regfile opnd_rf
;
1996 input_line_pointer
++;
1999 assert (opnd_cnt
> 0);
2001 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2003 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2004 as_warn (_("incorrect register number, ignoring"));
2009 if (opnd_cnt
>= opcode_operand_count
)
2011 as_warn (_("too many arguments"));
2014 assert (opnd_cnt
< MAX_INSN_ARGS
);
2016 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2017 next_reg
= tok
->X_add_number
+ 1;
2019 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2021 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2023 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2024 /* minus 1 because we are seeing one right now */
2030 last_opnd_cnt
= opnd_cnt
;
2037 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2041 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2044 insn
->ntok
= tok
- insn
->tok
;
2048 input_line_pointer
= old_input_line_pointer
;
2054 get_invisible_operands (TInsn
*insn
)
2056 xtensa_isa isa
= xtensa_default_isa
;
2057 static xtensa_insnbuf slotbuf
= NULL
;
2059 xtensa_opcode opc
= insn
->opcode
;
2060 int slot
, opnd
, fmt_found
;
2064 slotbuf
= xtensa_insnbuf_alloc (isa
);
2066 /* Find format/slot where this can be encoded. */
2069 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2071 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2073 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2079 if (fmt_found
) break;
2084 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2088 /* First encode all the visible operands
2089 (to deal with shared field operands). */
2090 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2092 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2093 && (insn
->tok
[opnd
].X_op
== O_register
2094 || insn
->tok
[opnd
].X_op
== O_constant
))
2096 val
= insn
->tok
[opnd
].X_add_number
;
2097 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2098 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2102 /* Then pull out the values for the invisible ones. */
2103 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2105 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2107 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2108 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2109 insn
->tok
[opnd
].X_add_number
= val
;
2110 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2111 insn
->tok
[opnd
].X_op
= O_register
;
2113 insn
->tok
[opnd
].X_op
= O_constant
;
2122 xg_reverse_shift_count (char **cnt_argp
)
2124 char *cnt_arg
, *new_arg
;
2125 cnt_arg
= *cnt_argp
;
2127 /* replace the argument with "31-(argument)" */
2128 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2129 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2132 *cnt_argp
= new_arg
;
2136 /* If "arg" is a constant expression, return non-zero with the value
2140 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2143 char *save_ptr
= input_line_pointer
;
2145 input_line_pointer
= arg
;
2147 input_line_pointer
= save_ptr
;
2149 if (exp
.X_op
== O_constant
)
2151 *valp
= exp
.X_add_number
;
2160 xg_replace_opname (char **popname
, char *newop
)
2163 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2164 strcpy (*popname
, newop
);
2169 xg_check_num_args (int *pnum_args
,
2174 int num_args
= *pnum_args
;
2176 if (num_args
< expected_num
)
2178 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2179 num_args
, opname
, expected_num
);
2183 if (num_args
> expected_num
)
2185 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2186 num_args
, opname
, expected_num
);
2187 while (num_args
-- > expected_num
)
2189 free (arg_strings
[num_args
]);
2190 arg_strings
[num_args
] = 0;
2192 *pnum_args
= expected_num
;
2200 /* If the register is not specified as part of the opcode,
2201 then get it from the operand and move it to the opcode. */
2204 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2206 xtensa_isa isa
= xtensa_default_isa
;
2208 char *opname
, *new_opname
;
2209 const char *sr_name
;
2210 int is_user
, is_write
;
2211 bfd_boolean has_underbar
= FALSE
;
2216 has_underbar
= TRUE
;
2219 is_user
= (opname
[1] == 'u');
2220 is_write
= (opname
[0] == 'w');
2222 /* Opname == [rw]ur or [rwx]sr... */
2224 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2227 /* Check if the argument is a symbolic register name. */
2228 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2229 /* Handle WSR to "INTSET" as a special case. */
2230 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2231 && !strcasecmp (arg_strings
[1], "intset"))
2232 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2233 if (sr
== XTENSA_UNDEFINED
2234 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2236 /* Maybe it's a register number.... */
2238 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2240 as_bad (_("invalid register '%s' for '%s' instruction"),
2241 arg_strings
[1], opname
);
2244 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2245 if (sr
== XTENSA_UNDEFINED
)
2247 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2253 /* Remove the last argument, which is now part of the opcode. */
2254 free (arg_strings
[1]);
2258 /* Translate the opcode. */
2259 sr_name
= xtensa_sysreg_name (isa
, sr
);
2260 /* Another special case for "WSR.INTSET".... */
2261 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2263 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2264 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2267 *popname
= new_opname
;
2274 xtensa_translate_old_userreg_ops (char **popname
)
2276 xtensa_isa isa
= xtensa_default_isa
;
2278 char *opname
, *new_opname
;
2279 const char *sr_name
;
2280 bfd_boolean has_underbar
= FALSE
;
2283 if (opname
[0] == '_')
2285 has_underbar
= TRUE
;
2289 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2290 if (sr
!= XTENSA_UNDEFINED
)
2292 /* The new default name ("nnn") is different from the old default
2293 name ("URnnn"). The old default is handled below, and we don't
2294 want to recognize [RW]nnn, so do nothing if the name is the (new)
2296 static char namebuf
[10];
2297 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2298 if (strcmp (namebuf
, opname
+ 1) == 0)
2306 /* Only continue if the reg name is "URnnn". */
2307 if (opname
[1] != 'u' || opname
[2] != 'r')
2309 val
= strtoul (opname
+ 3, &end
, 10);
2313 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2314 if (sr
== XTENSA_UNDEFINED
)
2316 as_bad (_("invalid register number (%ld) for '%s'"),
2322 /* Translate the opcode. */
2323 sr_name
= xtensa_sysreg_name (isa
, sr
);
2324 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2325 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2326 opname
[0], sr_name
);
2328 *popname
= new_opname
;
2335 xtensa_translate_zero_immed (char *old_op
,
2345 assert (opname
[0] != '_');
2347 if (strcmp (opname
, old_op
) != 0)
2350 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2352 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2354 xg_replace_opname (popname
, new_op
);
2355 free (arg_strings
[1]);
2356 arg_strings
[1] = arg_strings
[2];
2365 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2366 Returns non-zero if an error was found. */
2369 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2371 char *opname
= *popname
;
2372 bfd_boolean has_underbar
= FALSE
;
2374 if (cur_vinsn
.inside_bundle
)
2379 has_underbar
= TRUE
;
2383 if (strcmp (opname
, "mov") == 0)
2385 if (use_transform () && !has_underbar
&& density_supported
)
2386 xg_replace_opname (popname
, "mov.n");
2389 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2391 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2392 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2393 strcpy (arg_strings
[2], arg_strings
[1]);
2399 if (strcmp (opname
, "bbsi.l") == 0)
2401 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2403 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2404 if (target_big_endian
)
2405 xg_reverse_shift_count (&arg_strings
[1]);
2409 if (strcmp (opname
, "bbci.l") == 0)
2411 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2413 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2414 if (target_big_endian
)
2415 xg_reverse_shift_count (&arg_strings
[1]);
2419 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2420 && strcmp (opname
, "nop") == 0)
2422 if (use_transform () && !has_underbar
&& density_supported
)
2423 xg_replace_opname (popname
, "nop.n");
2426 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2428 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2429 arg_strings
[0] = (char *) xmalloc (3);
2430 arg_strings
[1] = (char *) xmalloc (3);
2431 arg_strings
[2] = (char *) xmalloc (3);
2432 strcpy (arg_strings
[0], "a1");
2433 strcpy (arg_strings
[1], "a1");
2434 strcpy (arg_strings
[2], "a1");
2440 /* Recognize [RW]UR and [RWX]SR. */
2441 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2442 && (opname
[1] == 'u' || opname
[1] == 's'))
2443 || (opname
[0] == 'x' && opname
[1] == 's'))
2445 && opname
[3] == '\0')
2446 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2448 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2449 [RW]<name> if <name> is the non-default name of a user register. */
2450 if ((opname
[0] == 'r' || opname
[0] == 'w')
2451 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2452 return xtensa_translate_old_userreg_ops (popname
);
2454 /* Relax branches that don't allow comparisons against an immediate value
2455 of zero to the corresponding branches with implicit zero immediates. */
2456 if (!has_underbar
&& use_transform ())
2458 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2459 pnum_args
, arg_strings
))
2462 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2463 pnum_args
, arg_strings
))
2466 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2467 pnum_args
, arg_strings
))
2470 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2471 pnum_args
, arg_strings
))
2479 /* Functions for dealing with the Xtensa ISA. */
2481 /* Currently the assembler only allows us to use a single target per
2482 fragment. Because of this, only one operand for a given
2483 instruction may be symbolic. If there is a PC-relative operand,
2484 the last one is chosen. Otherwise, the result is the number of the
2485 last immediate operand, and if there are none of those, we fail and
2489 get_relaxable_immed (xtensa_opcode opcode
)
2491 int last_immed
= -1;
2494 if (opcode
== XTENSA_UNDEFINED
)
2497 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2498 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2500 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2502 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2504 if (last_immed
== -1
2505 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2512 static xtensa_opcode
2513 get_opcode_from_buf (const char *buf
, int slot
)
2515 static xtensa_insnbuf insnbuf
= NULL
;
2516 static xtensa_insnbuf slotbuf
= NULL
;
2517 xtensa_isa isa
= xtensa_default_isa
;
2522 insnbuf
= xtensa_insnbuf_alloc (isa
);
2523 slotbuf
= xtensa_insnbuf_alloc (isa
);
2526 xtensa_insnbuf_from_chars (isa
, insnbuf
, buf
, 0);
2527 fmt
= xtensa_format_decode (isa
, insnbuf
);
2528 if (fmt
== XTENSA_UNDEFINED
)
2529 return XTENSA_UNDEFINED
;
2531 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2532 return XTENSA_UNDEFINED
;
2534 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2535 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2539 #ifdef TENSILICA_DEBUG
2541 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2544 xtensa_print_insn_table (void)
2546 int num_opcodes
, num_operands
;
2547 xtensa_opcode opcode
;
2548 xtensa_isa isa
= xtensa_default_isa
;
2550 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2551 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2554 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2555 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2556 for (opn
= 0; opn
< num_operands
; opn
++)
2558 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2560 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2562 xtensa_regfile opnd_rf
=
2563 xtensa_operand_regfile (isa
, opcode
, opn
);
2564 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2566 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2567 fputs ("[lLr] ", stderr
);
2569 fputs ("i ", stderr
);
2571 fprintf (stderr
, "\n");
2577 print_vliw_insn (xtensa_insnbuf vbuf
)
2579 xtensa_isa isa
= xtensa_default_isa
;
2580 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2581 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2584 fprintf (stderr
, "format = %d\n", f
);
2586 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2588 xtensa_opcode opcode
;
2592 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2593 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2594 opname
= xtensa_opcode_name (isa
, opcode
);
2596 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2597 fprintf (stderr
, " operands = ");
2599 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2603 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2605 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2606 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2607 fprintf (stderr
, "%d ", val
);
2609 fprintf (stderr
, "\n");
2611 xtensa_insnbuf_free (isa
, sbuf
);
2614 #endif /* TENSILICA_DEBUG */
2618 is_direct_call_opcode (xtensa_opcode opcode
)
2620 xtensa_isa isa
= xtensa_default_isa
;
2621 int n
, num_operands
;
2623 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2626 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2627 for (n
= 0; n
< num_operands
; n
++)
2629 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2630 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2637 /* Convert from BFD relocation type code to slot and operand number.
2638 Returns non-zero on failure. */
2641 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2643 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2644 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2646 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2649 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2650 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2652 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2662 /* Convert from slot number to BFD relocation type code for the
2663 standard PC-relative relocations. Return BFD_RELOC_NONE on
2666 static bfd_reloc_code_real_type
2667 encode_reloc (int slot
)
2669 if (slot
< 0 || slot
> 14)
2670 return BFD_RELOC_NONE
;
2672 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2676 /* Convert from slot numbers to BFD relocation type code for the
2677 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2679 static bfd_reloc_code_real_type
2680 encode_alt_reloc (int slot
)
2682 if (slot
< 0 || slot
> 14)
2683 return BFD_RELOC_NONE
;
2685 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2690 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2693 xtensa_opcode opcode
,
2699 uint32 valbuf
= value
;
2701 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2703 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2705 as_bad_where ((char *) file
, line
,
2706 _("operand %u is out of range for '%s'"), value
,
2707 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2709 as_bad_where ((char *) file
, line
,
2710 _("operand %u is invalid for '%s'"), value
,
2711 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2715 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2721 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2724 xtensa_opcode opcode
,
2728 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2729 fmt
, slot
, slotbuf
, &val
);
2730 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2735 /* Checks for rules from xtensa-relax tables. */
2737 /* The routine xg_instruction_matches_option_term must return TRUE
2738 when a given option term is true. The meaning of all of the option
2739 terms is given interpretation by this function. This is needed when
2740 an option depends on the state of a directive, but there are no such
2741 options in use right now. */
2744 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2745 const ReqOrOption
*option
)
2747 if (strcmp (option
->option_name
, "realnop") == 0
2748 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2750 /* These conditions were evaluated statically when building the
2751 relaxation table. There's no need to reevaluate them now. */
2756 as_fatal (_("internal error: unknown option name '%s'"),
2757 option
->option_name
);
2763 xg_instruction_matches_or_options (TInsn
*insn
,
2764 const ReqOrOptionList
*or_option
)
2766 const ReqOrOption
*option
;
2767 /* Must match each of the AND terms. */
2768 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2770 if (xg_instruction_matches_option_term (insn
, option
))
2778 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2780 const ReqOption
*req_options
;
2781 /* Must match each of the AND terms. */
2782 for (req_options
= options
;
2783 req_options
!= NULL
;
2784 req_options
= req_options
->next
)
2786 /* Must match one of the OR clauses. */
2787 if (!xg_instruction_matches_or_options (insn
,
2788 req_options
->or_option_terms
))
2795 /* Return the transition rule that matches or NULL if none matches. */
2798 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2800 PreconditionList
*condition_l
;
2802 if (rule
->opcode
!= insn
->opcode
)
2805 for (condition_l
= rule
->conditions
;
2806 condition_l
!= NULL
;
2807 condition_l
= condition_l
->next
)
2811 Precondition
*cond
= condition_l
->precond
;
2816 /* The expression must be the constant. */
2817 assert (cond
->op_num
< insn
->ntok
);
2818 exp1
= &insn
->tok
[cond
->op_num
];
2819 if (expr_is_const (exp1
))
2824 if (get_expr_const (exp1
) != cond
->op_data
)
2828 if (get_expr_const (exp1
) == cond
->op_data
)
2835 else if (expr_is_register (exp1
))
2840 if (get_expr_register (exp1
) != cond
->op_data
)
2844 if (get_expr_register (exp1
) == cond
->op_data
)
2856 assert (cond
->op_num
< insn
->ntok
);
2857 assert (cond
->op_data
< insn
->ntok
);
2858 exp1
= &insn
->tok
[cond
->op_num
];
2859 exp2
= &insn
->tok
[cond
->op_data
];
2864 if (!expr_is_equal (exp1
, exp2
))
2868 if (expr_is_equal (exp1
, exp2
))
2880 if (!xg_instruction_matches_options (insn
, rule
->options
))
2888 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2890 bfd_boolean a_greater
= FALSE
;
2891 bfd_boolean b_greater
= FALSE
;
2893 ReqOptionList
*l_a
= a
->options
;
2894 ReqOptionList
*l_b
= b
->options
;
2896 /* We only care if they both are the same except for
2897 a const16 vs. an l32r. */
2899 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2901 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2902 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2903 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2905 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2907 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2909 /* This is the case we care about. */
2910 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2911 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2918 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2919 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2929 l_or_a
= l_or_a
->next
;
2930 l_or_b
= l_or_b
->next
;
2932 if (l_or_a
|| l_or_b
)
2941 /* Incomparable if the substitution was used differently in two cases. */
2942 if (a_greater
&& b_greater
)
2954 static TransitionRule
*
2955 xg_instruction_match (TInsn
*insn
)
2957 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2959 assert (insn
->opcode
< table
->num_opcodes
);
2961 /* Walk through all of the possible transitions. */
2962 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2964 TransitionRule
*rule
= l
->rule
;
2965 if (xg_instruction_matches_rule (insn
, rule
))
2972 /* Various Other Internal Functions. */
2975 is_unique_insn_expansion (TransitionRule
*r
)
2977 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2979 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2986 xg_get_build_instr_size (BuildInstr
*insn
)
2988 assert (insn
->typ
== INSTR_INSTR
);
2989 return xg_get_single_size (insn
->opcode
);
2994 xg_is_narrow_insn (TInsn
*insn
)
2996 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2999 assert (insn
->insn_type
== ITYPE_INSN
);
3000 assert (insn
->opcode
< table
->num_opcodes
);
3002 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3004 TransitionRule
*rule
= l
->rule
;
3006 if (xg_instruction_matches_rule (insn
, rule
)
3007 && is_unique_insn_expansion (rule
))
3009 /* It only generates one instruction... */
3010 assert (insn
->insn_type
== ITYPE_INSN
);
3011 /* ...and it is a larger instruction. */
3012 if (xg_get_single_size (insn
->opcode
)
3013 < xg_get_build_instr_size (rule
->to_instr
))
3021 return (num_match
== 1);
3026 xg_is_single_relaxable_insn (TInsn
*insn
)
3028 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3031 assert (insn
->insn_type
== ITYPE_INSN
);
3032 assert (insn
->opcode
< table
->num_opcodes
);
3034 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3036 TransitionRule
*rule
= l
->rule
;
3038 if (xg_instruction_matches_rule (insn
, rule
)
3039 && is_unique_insn_expansion (rule
))
3041 /* It only generates one instruction... */
3042 assert (insn
->insn_type
== ITYPE_INSN
);
3043 /* ... and it is a larger instruction. */
3044 if (xg_get_single_size (insn
->opcode
)
3045 <= xg_get_build_instr_size (rule
->to_instr
))
3053 return (num_match
== 1);
3057 /* Return the maximum number of bytes this opcode can expand to. */
3060 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3062 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3064 int max_size
= xg_get_single_size (opcode
);
3066 assert (opcode
< table
->num_opcodes
);
3068 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3070 TransitionRule
*rule
= l
->rule
;
3071 BuildInstr
*build_list
;
3076 build_list
= rule
->to_instr
;
3077 if (is_unique_insn_expansion (rule
))
3079 assert (build_list
->typ
== INSTR_INSTR
);
3080 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3083 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3085 switch (build_list
->typ
)
3088 this_size
+= xg_get_single_size (build_list
->opcode
);
3090 case INSTR_LITERAL_DEF
:
3091 case INSTR_LABEL_DEF
:
3096 if (this_size
> max_size
)
3097 max_size
= this_size
;
3103 /* Return the maximum number of literal bytes this opcode can generate. */
3106 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3108 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3112 assert (opcode
< table
->num_opcodes
);
3114 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3116 TransitionRule
*rule
= l
->rule
;
3117 BuildInstr
*build_list
;
3122 build_list
= rule
->to_instr
;
3123 if (is_unique_insn_expansion (rule
))
3125 assert (build_list
->typ
== INSTR_INSTR
);
3126 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3129 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3131 switch (build_list
->typ
)
3133 case INSTR_LITERAL_DEF
:
3134 /* Hard-coded 4-byte literal. */
3138 case INSTR_LABEL_DEF
:
3143 if (this_size
> max_size
)
3144 max_size
= this_size
;
3151 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3153 int steps_taken
= 0;
3154 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3157 assert (insn
->insn_type
== ITYPE_INSN
);
3158 assert (insn
->opcode
< table
->num_opcodes
);
3160 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3162 TransitionRule
*rule
= l
->rule
;
3164 if (xg_instruction_matches_rule (insn
, rule
))
3166 if (steps_taken
== lateral_steps
)
3176 get_special_literal_symbol (void)
3178 static symbolS
*sym
= NULL
;
3181 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3187 get_special_label_symbol (void)
3189 static symbolS
*sym
= NULL
;
3192 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3198 xg_valid_literal_expression (const expressionS
*exp
)
3215 /* This will check to see if the value can be converted into the
3216 operand type. It will return TRUE if it does not fit. */
3219 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3221 uint32 valbuf
= value
;
3222 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3228 /* Assumes: All immeds are constants. Check that all constants fit
3229 into their immeds; return FALSE if not. */
3232 xg_immeds_fit (const TInsn
*insn
)
3234 xtensa_isa isa
= xtensa_default_isa
;
3238 assert (insn
->insn_type
== ITYPE_INSN
);
3239 for (i
= 0; i
< n
; ++i
)
3241 const expressionS
*expr
= &insn
->tok
[i
];
3242 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3249 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3254 /* The symbol should have a fixup associated with it. */
3263 /* This should only be called after we have an initial
3264 estimate of the addresses. */
3267 xg_symbolic_immeds_fit (const TInsn
*insn
,
3273 xtensa_isa isa
= xtensa_default_isa
;
3281 assert (insn
->insn_type
== ITYPE_INSN
);
3283 for (i
= 0; i
< n
; ++i
)
3285 const expressionS
*expr
= &insn
->tok
[i
];
3286 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3293 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3299 /* Check for the worst case. */
3300 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3305 /* We only allow symbols for PC-relative references.
3306 If pc_frag == 0, then we don't have frag locations yet. */
3308 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3311 /* If it is a weak symbol, then assume it won't reach. */
3312 if (S_IS_WEAK (expr
->X_add_symbol
))
3315 if (is_direct_call_opcode (insn
->opcode
)
3316 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3318 /* If callee is undefined or in a different segment, be
3319 optimistic and assume it will be in range. */
3320 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3324 /* Only references within a segment can be known to fit in the
3325 operands at assembly time. */
3326 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3329 symbolP
= expr
->X_add_symbol
;
3330 sym_frag
= symbol_get_frag (symbolP
);
3331 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3332 pc
= pc_frag
->fr_address
+ pc_offset
;
3334 /* If frag has yet to be reached on this pass, assume it
3335 will move by STRETCH just as we did. If this is not so,
3336 it will be because some frag between grows, and that will
3337 force another pass. Beware zero-length frags. There
3338 should be a faster way to do this. */
3341 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3342 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3347 new_offset
= target
;
3348 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3349 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3354 /* The symbol should have a fixup associated with it. */
3363 /* Return TRUE on success. */
3366 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3371 memset (targ
, 0, sizeof (TInsn
));
3372 targ
->loc
= insn
->loc
;
3377 targ
->opcode
= bi
->opcode
;
3378 targ
->insn_type
= ITYPE_INSN
;
3379 targ
->is_specific_opcode
= FALSE
;
3381 for (; op
!= NULL
; op
= op
->next
)
3383 int op_num
= op
->op_num
;
3384 int op_data
= op
->op_data
;
3386 assert (op
->op_num
< MAX_INSN_ARGS
);
3388 if (targ
->ntok
<= op_num
)
3389 targ
->ntok
= op_num
+ 1;
3394 set_expr_const (&targ
->tok
[op_num
], op_data
);
3397 assert (op_data
< insn
->ntok
);
3398 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3401 sym
= get_special_literal_symbol ();
3402 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3405 sym
= get_special_label_symbol ();
3406 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3408 case OP_OPERAND_HI16U
:
3409 case OP_OPERAND_LOW16U
:
3410 assert (op_data
< insn
->ntok
);
3411 if (expr_is_const (&insn
->tok
[op_data
]))
3414 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3415 val
= xg_apply_userdef_op_fn (op
->typ
,
3418 targ
->tok
[op_num
].X_add_number
= val
;
3422 /* For const16 we can create relocations for these. */
3423 if (targ
->opcode
== XTENSA_UNDEFINED
3424 || (targ
->opcode
!= xtensa_const16_opcode
))
3426 assert (op_data
< insn
->ntok
);
3427 /* Need to build a O_lo16 or O_hi16. */
3428 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3429 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3431 if (op
->typ
== OP_OPERAND_HI16U
)
3432 targ
->tok
[op_num
].X_op
= O_hi16
;
3433 else if (op
->typ
== OP_OPERAND_LOW16U
)
3434 targ
->tok
[op_num
].X_op
= O_lo16
;
3441 /* currently handles:
3444 OP_OPERAND_F32MINUS */
3445 if (xg_has_userdef_op_fn (op
->typ
))
3447 assert (op_data
< insn
->ntok
);
3448 if (expr_is_const (&insn
->tok
[op_data
]))
3451 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3452 val
= xg_apply_userdef_op_fn (op
->typ
,
3455 targ
->tok
[op_num
].X_add_number
= val
;
3458 return FALSE
; /* We cannot use a relocation for this. */
3467 case INSTR_LITERAL_DEF
:
3469 targ
->opcode
= XTENSA_UNDEFINED
;
3470 targ
->insn_type
= ITYPE_LITERAL
;
3471 targ
->is_specific_opcode
= FALSE
;
3472 for (; op
!= NULL
; op
= op
->next
)
3474 int op_num
= op
->op_num
;
3475 int op_data
= op
->op_data
;
3476 assert (op
->op_num
< MAX_INSN_ARGS
);
3478 if (targ
->ntok
<= op_num
)
3479 targ
->ntok
= op_num
+ 1;
3484 assert (op_data
< insn
->ntok
);
3485 /* We can only pass resolvable literals through. */
3486 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3488 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3500 case INSTR_LABEL_DEF
:
3502 targ
->opcode
= XTENSA_UNDEFINED
;
3503 targ
->insn_type
= ITYPE_LABEL
;
3504 targ
->is_specific_opcode
= FALSE
;
3505 /* Literal with no ops is a label? */
3506 assert (op
== NULL
);
3517 /* Return TRUE on success. */
3520 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3522 for (; bi
!= NULL
; bi
= bi
->next
)
3524 TInsn
*next_insn
= istack_push_space (istack
);
3526 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3533 /* Return TRUE on valid expansion. */
3536 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3538 int stack_size
= istack
->ninsn
;
3539 int steps_taken
= 0;
3540 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3543 assert (insn
->insn_type
== ITYPE_INSN
);
3544 assert (insn
->opcode
< table
->num_opcodes
);
3546 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3548 TransitionRule
*rule
= l
->rule
;
3550 if (xg_instruction_matches_rule (insn
, rule
))
3552 if (lateral_steps
== steps_taken
)
3556 /* This is it. Expand the rule to the stack. */
3557 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3560 /* Check to see if it fits. */
3561 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3563 TInsn
*insn
= &istack
->insn
[i
];
3565 if (insn
->insn_type
== ITYPE_INSN
3566 && !tinsn_has_symbolic_operands (insn
)
3567 && !xg_immeds_fit (insn
))
3569 istack
->ninsn
= stack_size
;
3583 xg_expand_narrow (TInsn
*targ
, TInsn
*insn
)
3585 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3588 assert (insn
->insn_type
== ITYPE_INSN
);
3589 assert (insn
->opcode
< table
->num_opcodes
);
3591 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3593 TransitionRule
*rule
= l
->rule
;
3594 if (xg_instruction_matches_rule (insn
, rule
)
3595 && is_unique_insn_expansion (rule
))
3597 /* Is it a larger instruction? */
3598 if (xg_get_single_size (insn
->opcode
)
3599 <= xg_get_build_instr_size (rule
->to_instr
))
3601 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3610 /* Relax the assembly instruction at least "min_steps".
3611 Return the number of steps taken. */
3614 xg_assembly_relax (IStack
*istack
,
3617 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3618 offsetT pc_offset
, /* offset in fragment */
3619 int min_steps
, /* minimum conversion steps */
3620 long stretch
) /* number of bytes stretched so far */
3622 int steps_taken
= 0;
3624 /* assert (has no symbolic operands)
3625 Some of its immeds don't fit.
3626 Try to build a relaxed version.
3627 This may go through a couple of stages
3628 of single instruction transformations before
3631 TInsn single_target
;
3633 int lateral_steps
= 0;
3634 int istack_size
= istack
->ninsn
;
3636 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3637 && steps_taken
>= min_steps
)
3639 istack_push (istack
, insn
);
3642 current_insn
= *insn
;
3644 /* Walk through all of the single instruction expansions. */
3645 while (xg_is_single_relaxable_insn (¤t_insn
))
3647 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3649 assert (!error_val
);
3651 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3655 if (steps_taken
>= min_steps
)
3657 istack_push (istack
, &single_target
);
3661 current_insn
= single_target
;
3664 /* Now check for a multi-instruction expansion. */
3665 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3667 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3670 if (steps_taken
>= min_steps
)
3672 istack_push (istack
, ¤t_insn
);
3677 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3679 if (steps_taken
>= min_steps
)
3683 istack
->ninsn
= istack_size
;
3686 /* It's not going to work -- use the original. */
3687 istack_push (istack
, insn
);
3693 xg_force_frag_space (int size
)
3695 /* This may have the side effect of creating a new fragment for the
3696 space to go into. I just do not like the name of the "frag"
3703 xg_finish_frag (char *last_insn
,
3704 enum xtensa_relax_statesE frag_state
,
3705 enum xtensa_relax_statesE slot0_state
,
3707 bfd_boolean is_insn
)
3709 /* Finish off this fragment so that it has at LEAST the desired
3710 max_growth. If it doesn't fit in this fragment, close this one
3711 and start a new one. In either case, return a pointer to the
3712 beginning of the growth area. */
3716 xg_force_frag_space (max_growth
);
3718 old_frag
= frag_now
;
3720 frag_now
->fr_opcode
= last_insn
;
3722 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3724 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3725 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3727 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3728 xtensa_set_frag_assembly_state (frag_now
);
3730 /* Just to make sure that we did not split it up. */
3731 assert (old_frag
->fr_next
== frag_now
);
3735 /* Return TRUE if the target frag is one of the next non-empty frags. */
3738 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3743 for (; fragP
; fragP
= fragP
->fr_next
)
3745 if (fragP
== target
)
3747 if (fragP
->fr_fix
!= 0)
3749 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3751 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3752 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3754 if (fragP
->fr_type
== rs_space
)
3762 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3764 xtensa_isa isa
= xtensa_default_isa
;
3766 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3771 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3772 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3775 for (i
= 0; i
< num_ops
; i
++)
3777 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3783 if (target_op
== -1)
3786 if (insn
->ntok
<= target_op
)
3789 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3792 sym
= insn
->tok
[target_op
].X_add_symbol
;
3796 if (insn
->tok
[target_op
].X_add_number
!= 0)
3799 target_frag
= symbol_get_frag (sym
);
3800 if (target_frag
== NULL
)
3803 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3804 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3812 xg_add_branch_and_loop_targets (TInsn
*insn
)
3814 xtensa_isa isa
= xtensa_default_isa
;
3815 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3817 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3820 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3821 && insn
->tok
[i
].X_op
== O_symbol
)
3822 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3826 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3827 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3831 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3833 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3834 && insn
->tok
[i
].X_op
== O_symbol
)
3836 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3837 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3838 if (S_IS_DEFINED (sym
))
3839 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3846 /* Return FALSE if no error. */
3849 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3854 switch (instr_spec
->typ
)
3857 new_insn
->insn_type
= ITYPE_INSN
;
3858 new_insn
->opcode
= instr_spec
->opcode
;
3859 new_insn
->is_specific_opcode
= FALSE
;
3860 new_insn
->loc
= old_insn
->loc
;
3862 case INSTR_LITERAL_DEF
:
3863 new_insn
->insn_type
= ITYPE_LITERAL
;
3864 new_insn
->opcode
= XTENSA_UNDEFINED
;
3865 new_insn
->is_specific_opcode
= FALSE
;
3866 new_insn
->loc
= old_insn
->loc
;
3868 case INSTR_LABEL_DEF
:
3869 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3873 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3876 const expressionS
*src_exp
;
3882 /* The expression must be the constant. */
3883 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3884 exp
= &new_insn
->tok
[b_op
->op_num
];
3885 set_expr_const (exp
, b_op
->op_data
);
3889 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3890 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3891 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3892 exp
= &new_insn
->tok
[b_op
->op_num
];
3893 copy_expr (exp
, src_exp
);
3898 as_bad (_("can't handle generation of literal/labels yet"));
3902 as_bad (_("can't handle undefined OP TYPE"));
3907 new_insn
->ntok
= num_ops
;
3912 /* Return TRUE if it was simplified. */
3915 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3917 TransitionRule
*rule
;
3918 BuildInstr
*insn_spec
;
3920 if (old_insn
->is_specific_opcode
|| !density_supported
)
3923 rule
= xg_instruction_match (old_insn
);
3927 insn_spec
= rule
->to_instr
;
3928 /* There should only be one. */
3929 assert (insn_spec
!= NULL
);
3930 assert (insn_spec
->next
== NULL
);
3931 if (insn_spec
->next
!= NULL
)
3934 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3940 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3941 l32i.n. (2) Check the number of operands. (3) Place the instruction
3942 tokens into the stack or relax it and place multiple
3943 instructions/literals onto the stack. Return FALSE if no error. */
3946 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3950 bfd_boolean do_expand
;
3952 memset (&new_insn
, 0, sizeof (TInsn
));
3954 /* Narrow it if we can. xg_simplify_insn now does all the
3955 appropriate checking (e.g., for the density option). */
3956 if (xg_simplify_insn (orig_insn
, &new_insn
))
3957 orig_insn
= &new_insn
;
3959 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3961 if (orig_insn
->ntok
< noperands
)
3963 as_bad (_("found %d operands for '%s': Expected %d"),
3965 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3969 if (orig_insn
->ntok
> noperands
)
3970 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3972 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3975 /* If there are not enough operands, we will assert above. If there
3976 are too many, just cut out the extras here. */
3977 orig_insn
->ntok
= noperands
;
3979 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3982 /* If the instruction will definitely need to be relaxed, it is better
3983 to expand it now for better scheduling. Decide whether to expand
3985 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3987 /* Calls should be expanded to longcalls only in the backend relaxation
3988 so that the assembly scheduler will keep the L32R/CALLX instructions
3990 if (is_direct_call_opcode (orig_insn
->opcode
))
3993 if (tinsn_has_symbolic_operands (orig_insn
))
3995 /* The values of symbolic operands are not known yet, so only expand
3996 now if an operand is "complex" (e.g., difference of symbols) and
3997 will have to be stored as a literal regardless of the value. */
3998 if (!tinsn_has_complex_operands (orig_insn
))
4001 else if (xg_immeds_fit (orig_insn
))
4005 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4007 istack_push (istack
, orig_insn
);
4013 /* Return TRUE if the section flags are marked linkonce
4014 or the name is .gnu.linkonce*. */
4017 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4019 flagword flags
, link_once_flags
;
4021 flags
= bfd_get_section_flags (abfd
, sec
);
4022 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4024 /* Flags might not be set yet. */
4025 if (!link_once_flags
)
4027 static size_t len
= sizeof ".gnu.linkonce.t.";
4029 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4030 link_once_flags
= SEC_LINK_ONCE
;
4032 return (link_once_flags
!= 0);
4037 xtensa_add_literal_sym (symbolS
*sym
)
4041 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4043 l
->next
= literal_syms
;
4049 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4051 static int lit_num
= 0;
4052 static char name
[256];
4055 sprintf (name
, ".L_lit_sym%d", lit_num
);
4057 /* Create a local symbol. If it is in a linkonce section, we have to
4058 be careful to make sure that if it is used in a relocation that the
4059 symbol will be in the output file. */
4060 if (get_is_linkonce_section (stdoutput
, sec
))
4062 symbolP
= symbol_new (name
, sec
, 0, frag
);
4063 S_CLEAR_EXTERNAL (symbolP
);
4064 /* symbolP->local = 1; */
4067 symbolP
= symbol_new (name
, sec
, 0, frag
);
4069 xtensa_add_literal_sym (symbolP
);
4071 frag
->tc_frag_data
.is_literal
= TRUE
;
4077 /* Currently all literals that are generated here are 32-bit L32R targets. */
4080 xg_assemble_literal (/* const */ TInsn
*insn
)
4083 symbolS
*lit_sym
= NULL
;
4085 /* size = 4 for L32R. It could easily be larger when we move to
4086 larger constants. Add a parameter later. */
4087 offsetT litsize
= 4;
4088 offsetT litalign
= 2; /* 2^2 = 4 */
4089 expressionS saved_loc
;
4090 expressionS
* emit_val
;
4092 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4094 assert (insn
->insn_type
== ITYPE_LITERAL
);
4095 assert (insn
->ntok
== 1); /* must be only one token here */
4097 xtensa_switch_to_literal_fragment (&state
);
4099 emit_val
= &insn
->tok
[0];
4100 if (emit_val
->X_op
== O_big
)
4102 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4105 /* This happens when someone writes a "movi a2, big_number". */
4106 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4107 _("invalid immediate"));
4108 xtensa_restore_emit_state (&state
);
4113 /* Force a 4-byte align here. Note that this opens a new frag, so all
4114 literals done with this function have a frag to themselves. That's
4115 important for the way text section literals work. */
4116 frag_align (litalign
, 0, 0);
4117 record_alignment (now_seg
, litalign
);
4119 if (emit_val
->X_op
== O_pltrel
)
4121 char *p
= frag_more (litsize
);
4122 xtensa_set_frag_assembly_state (frag_now
);
4123 if (emit_val
->X_add_symbol
)
4124 emit_val
->X_op
= O_symbol
;
4126 emit_val
->X_op
= O_constant
;
4127 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4128 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4131 emit_expr (emit_val
, litsize
);
4133 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4134 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4135 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4136 lit_sym
= frag_now
->fr_symbol
;
4137 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4140 xtensa_restore_emit_state (&state
);
4146 xg_assemble_literal_space (/* const */ int size
, int slot
)
4149 /* We might have to do something about this alignment. It only
4150 takes effect if something is placed here. */
4151 offsetT litalign
= 2; /* 2^2 = 4 */
4152 fragS
*lit_saved_frag
;
4154 assert (size
% 4 == 0);
4156 xtensa_switch_to_literal_fragment (&state
);
4158 /* Force a 4-byte align here. */
4159 frag_align (litalign
, 0, 0);
4160 record_alignment (now_seg
, litalign
);
4162 xg_force_frag_space (size
);
4164 lit_saved_frag
= frag_now
;
4165 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4166 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4167 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4168 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4171 xtensa_restore_emit_state (&state
);
4172 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4176 /* Put in a fixup record based on the opcode.
4177 Return TRUE on success. */
4180 xg_add_opcode_fix (TInsn
*tinsn
,
4188 xtensa_opcode opcode
= tinsn
->opcode
;
4189 bfd_reloc_code_real_type reloc
;
4190 reloc_howto_type
*howto
;
4194 reloc
= BFD_RELOC_NONE
;
4196 /* First try the special cases for "alternate" relocs. */
4197 if (opcode
== xtensa_l32r_opcode
)
4199 if (fragP
->tc_frag_data
.use_absolute_literals
)
4200 reloc
= encode_alt_reloc (slot
);
4202 else if (opcode
== xtensa_const16_opcode
)
4204 if (expr
->X_op
== O_lo16
)
4206 reloc
= encode_reloc (slot
);
4207 expr
->X_op
= O_symbol
;
4209 else if (expr
->X_op
== O_hi16
)
4211 reloc
= encode_alt_reloc (slot
);
4212 expr
->X_op
= O_symbol
;
4216 if (opnum
!= get_relaxable_immed (opcode
))
4218 as_bad (_("invalid relocation for operand %i of '%s'"),
4219 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4223 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4224 into the symbol table where the generic portions of the assembler
4225 won't know what to do with them. */
4226 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4228 as_bad (_("invalid expression for operand %i of '%s'"),
4229 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4233 /* Next try the generic relocs. */
4234 if (reloc
== BFD_RELOC_NONE
)
4235 reloc
= encode_reloc (slot
);
4236 if (reloc
== BFD_RELOC_NONE
)
4238 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4242 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4245 as_bad (_("undefined symbol for opcode \"%s\""),
4246 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4250 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4251 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4252 howto
->pc_relative
, reloc
);
4253 the_fix
->fx_no_overflow
= 1;
4255 if (expr
->X_add_symbol
4256 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4257 || S_IS_WEAK (expr
->X_add_symbol
)))
4258 the_fix
->fx_plt
= TRUE
;
4260 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4261 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4262 the_fix
->tc_fix_data
.slot
= slot
;
4269 xg_emit_insn_to_buf (TInsn
*tinsn
,
4274 bfd_boolean build_fix
)
4276 static xtensa_insnbuf insnbuf
= NULL
;
4277 bfd_boolean has_symbolic_immed
= FALSE
;
4278 bfd_boolean ok
= TRUE
;
4280 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4282 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4283 if (has_symbolic_immed
&& build_fix
)
4286 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4287 expressionS
*exp
= &tinsn
->tok
[opnum
];
4289 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4292 fragP
->tc_frag_data
.is_insn
= TRUE
;
4293 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4299 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4301 symbolS
*sym
= get_special_literal_symbol ();
4305 assert (insn
->insn_type
== ITYPE_INSN
);
4306 for (i
= 0; i
< insn
->ntok
; i
++)
4307 if (insn
->tok
[i
].X_add_symbol
== sym
)
4308 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4314 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4316 symbolS
*sym
= get_special_label_symbol ();
4318 /* assert (!insn->is_literal); */
4319 for (i
= 0; i
< insn
->ntok
; i
++)
4320 if (insn
->tok
[i
].X_add_symbol
== sym
)
4321 insn
->tok
[i
].X_add_symbol
= label_sym
;
4326 /* Return TRUE if the instruction can write to the specified
4327 integer register. */
4330 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4334 xtensa_isa isa
= xtensa_default_isa
;
4336 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4338 for (i
= 0; i
< num_ops
; i
++)
4341 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4342 if ((inout
== 'o' || inout
== 'm')
4343 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4345 xtensa_regfile opnd_rf
=
4346 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4347 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4349 if ((insn
->tok
[i
].X_op
== O_register
)
4350 && (insn
->tok
[i
].X_add_number
== regnum
))
4360 is_bad_loopend_opcode (const TInsn
*tinsn
)
4362 xtensa_opcode opcode
= tinsn
->opcode
;
4364 if (opcode
== XTENSA_UNDEFINED
)
4367 if (opcode
== xtensa_call0_opcode
4368 || opcode
== xtensa_callx0_opcode
4369 || opcode
== xtensa_call4_opcode
4370 || opcode
== xtensa_callx4_opcode
4371 || opcode
== xtensa_call8_opcode
4372 || opcode
== xtensa_callx8_opcode
4373 || opcode
== xtensa_call12_opcode
4374 || opcode
== xtensa_callx12_opcode
4375 || opcode
== xtensa_isync_opcode
4376 || opcode
== xtensa_ret_opcode
4377 || opcode
== xtensa_ret_n_opcode
4378 || opcode
== xtensa_retw_opcode
4379 || opcode
== xtensa_retw_n_opcode
4380 || opcode
== xtensa_waiti_opcode
4381 || opcode
== xtensa_rsr_lcount_opcode
)
4388 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4389 This allows the debugger to add unaligned labels.
4390 Also, the assembler generates stabs labels that need
4391 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4394 is_unaligned_label (symbolS
*sym
)
4396 const char *name
= S_GET_NAME (sym
);
4397 static size_t fake_size
= 0;
4401 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4404 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4406 fake_size
= strlen (FAKE_LABEL_NAME
);
4409 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4410 && (name
[fake_size
] == 'F'
4411 || name
[fake_size
] == 'L'
4412 || (name
[fake_size
] == 'e'
4413 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4421 next_non_empty_frag (const fragS
*fragP
)
4423 fragS
*next_fragP
= fragP
->fr_next
;
4425 /* Sometimes an empty will end up here due storage allocation issues.
4426 So we have to skip until we find something legit. */
4427 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4428 next_fragP
= next_fragP
->fr_next
;
4430 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4438 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4440 xtensa_opcode out_opcode
;
4441 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4443 if (next_fragP
== NULL
)
4446 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4447 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4449 *opcode
= out_opcode
;
4457 frag_format_size (const fragS
*fragP
)
4459 static xtensa_insnbuf insnbuf
= NULL
;
4460 xtensa_isa isa
= xtensa_default_isa
;
4465 insnbuf
= xtensa_insnbuf_alloc (isa
);
4468 return XTENSA_UNDEFINED
;
4470 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
, 0);
4472 fmt
= xtensa_format_decode (isa
, insnbuf
);
4473 if (fmt
== XTENSA_UNDEFINED
)
4474 return XTENSA_UNDEFINED
;
4475 fmt_size
= xtensa_format_length (isa
, fmt
);
4477 /* If the next format won't be changing due to relaxation, just
4478 return the length of the first format. */
4479 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4482 /* If during relaxation we have to pull an instruction out of a
4483 multi-slot instruction, we will return the more conservative
4484 number. This works because alignment on bigger instructions
4485 is more restrictive than alignment on smaller instructions.
4486 This is more conservative than we would like, but it happens
4489 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4492 /* If we aren't doing one of our own relaxations or it isn't
4493 slot-based, then the insn size won't change. */
4494 if (fragP
->fr_type
!= rs_machine_dependent
)
4496 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4499 /* If an instruction is about to grow, return the longer size. */
4500 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4501 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4504 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4505 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4512 next_frag_format_size (const fragS
*fragP
)
4514 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4515 return frag_format_size (next_fragP
);
4519 /* If the next legit fragment is an end-of-loop marker,
4520 switch its state so it will instantiate a NOP. */
4523 update_next_frag_state (fragS
*fragP
)
4525 fragS
*next_fragP
= fragP
->fr_next
;
4526 fragS
*new_target
= NULL
;
4530 /* We are guaranteed there will be one of these... */
4531 while (!(next_fragP
->fr_type
== rs_machine_dependent
4532 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4533 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4534 next_fragP
= next_fragP
->fr_next
;
4536 assert (next_fragP
->fr_type
== rs_machine_dependent
4537 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4538 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4540 /* ...and one of these. */
4541 new_target
= next_fragP
->fr_next
;
4542 while (!(new_target
->fr_type
== rs_machine_dependent
4543 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4544 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4545 new_target
= new_target
->fr_next
;
4547 assert (new_target
->fr_type
== rs_machine_dependent
4548 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4549 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4552 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4554 if (next_fragP
->fr_type
== rs_machine_dependent
4555 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4557 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4561 next_fragP
= next_fragP
->fr_next
;
4567 next_frag_is_branch_target (const fragS
*fragP
)
4569 /* Sometimes an empty will end up here due to storage allocation issues,
4570 so we have to skip until we find something legit. */
4571 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4573 if (fragP
->tc_frag_data
.is_branch_target
)
4575 if (fragP
->fr_fix
!= 0)
4583 next_frag_is_loop_target (const fragS
*fragP
)
4585 /* Sometimes an empty will end up here due storage allocation issues.
4586 So we have to skip until we find something legit. */
4587 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4589 if (fragP
->tc_frag_data
.is_loop_target
)
4591 if (fragP
->fr_fix
!= 0)
4599 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4601 const fragS
*next_fragp
= fragp
->fr_next
;
4602 xtensa_opcode next_opcode
;
4604 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4607 /* Sometimes an empty will end up here due to storage allocation issues,
4608 so we have to skip until we find something legit. */
4609 while (next_fragp
->fr_fix
== 0)
4610 next_fragp
= next_fragp
->fr_next
;
4612 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4615 /* There is some implicit knowledge encoded in here.
4616 The LOOP instructions that are NOT RELAX_IMMED have
4617 been relaxed. Note that we can assume that the LOOP
4618 instruction is in slot 0 because loops aren't bundleable. */
4619 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4620 return get_expanded_loop_offset (next_opcode
);
4626 /* Mark a location where we can later insert literal frags. Update
4627 the section's literal_pool_loc, so subsequent literals can be
4628 placed nearest to their use. */
4631 xtensa_mark_literal_pool_location (void)
4633 /* Any labels pointing to the current location need
4634 to be adjusted to after the literal pool. */
4636 fragS
*pool_location
;
4638 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4641 frag_align (2, 0, 0);
4642 record_alignment (now_seg
, 2);
4644 /* We stash info in the fr_var of these frags
4645 so we can later move the literal's fixes into this
4646 frchain's fix list. We can use fr_var because fr_var's
4647 interpretation depends solely on the fr_type and subtype. */
4648 pool_location
= frag_now
;
4649 frag_variant (rs_machine_dependent
, 0, (int) frchain_now
,
4650 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4651 xtensa_set_frag_assembly_state (frag_now
);
4652 frag_variant (rs_machine_dependent
, 0, (int) now_seg
,
4653 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4654 xtensa_set_frag_assembly_state (frag_now
);
4656 /* Now put a frag into the literal pool that points to this location. */
4657 set_literal_pool_location (now_seg
, pool_location
);
4658 xtensa_switch_to_non_abs_literal_fragment (&s
);
4659 frag_align (2, 0, 0);
4660 record_alignment (now_seg
, 2);
4662 /* Close whatever frag is there. */
4663 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4664 xtensa_set_frag_assembly_state (frag_now
);
4665 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4666 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4667 xtensa_restore_emit_state (&s
);
4668 xtensa_set_frag_assembly_state (frag_now
);
4672 /* Build a nop of the correct size into tinsn. */
4675 build_nop (TInsn
*tinsn
, int size
)
4681 tinsn
->opcode
= xtensa_nop_n_opcode
;
4683 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4684 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4688 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4690 tinsn
->opcode
= xtensa_or_opcode
;
4691 set_expr_const (&tinsn
->tok
[0], 1);
4692 set_expr_const (&tinsn
->tok
[1], 1);
4693 set_expr_const (&tinsn
->tok
[2], 1);
4697 tinsn
->opcode
= xtensa_nop_opcode
;
4699 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4704 /* Assemble a NOP of the requested size in the buffer. User must have
4705 allocated "buf" with at least "size" bytes. */
4708 assemble_nop (size_t size
, char *buf
)
4710 static xtensa_insnbuf insnbuf
= NULL
;
4713 build_nop (&tinsn
, size
);
4716 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4718 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4719 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4723 /* Return the number of bytes for the offset of the expanded loop
4724 instruction. This should be incorporated into the relaxation
4725 specification but is hard-coded here. This is used to auto-align
4726 the loop instruction. It is invalid to call this function if the
4727 configuration does not have loops or if the opcode is not a loop
4731 get_expanded_loop_offset (xtensa_opcode opcode
)
4733 /* This is the OFFSET of the loop instruction in the expanded loop.
4734 This MUST correspond directly to the specification of the loop
4735 expansion. It will be validated on fragment conversion. */
4736 assert (opcode
!= XTENSA_UNDEFINED
);
4737 if (opcode
== xtensa_loop_opcode
)
4739 if (opcode
== xtensa_loopnez_opcode
)
4741 if (opcode
== xtensa_loopgtz_opcode
)
4743 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4749 get_literal_pool_location (segT seg
)
4751 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4756 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4758 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4762 /* Set frag assembly state should be called when a new frag is
4763 opened and after a frag has been closed. */
4766 xtensa_set_frag_assembly_state (fragS
*fragP
)
4768 if (!density_supported
)
4769 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4771 /* This function is called from subsegs_finish, which is called
4772 after xtensa_end, so we can't use "use_transform" or
4773 "use_schedule" here. */
4774 if (!directive_state
[directive_transform
])
4775 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4776 if (directive_state
[directive_longcalls
])
4777 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4778 fragP
->tc_frag_data
.use_absolute_literals
=
4779 directive_state
[directive_absolute_literals
];
4780 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4785 relaxable_section (asection
*sec
)
4787 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4792 xtensa_find_unmarked_state_frags (void)
4796 /* Walk over each fragment of all of the current segments. For each
4797 unmarked fragment, mark it with the same info as the previous
4799 for (seclist
= &stdoutput
->sections
;
4800 seclist
&& *seclist
;
4801 seclist
= &(*seclist
)->next
)
4803 segT sec
= *seclist
;
4804 segment_info_type
*seginfo
;
4807 flags
= bfd_get_section_flags (stdoutput
, sec
);
4808 if (flags
& SEC_DEBUGGING
)
4810 if (!(flags
& SEC_ALLOC
))
4813 seginfo
= seg_info (sec
);
4814 if (seginfo
&& seginfo
->frchainP
)
4816 fragS
*last_fragP
= 0;
4817 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4818 fragP
= fragP
->fr_next
)
4820 if (fragP
->fr_fix
!= 0
4821 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4823 if (last_fragP
== 0)
4825 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4826 _("assembly state not set for first frag in section %s"),
4831 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4832 fragP
->tc_frag_data
.is_no_density
=
4833 last_fragP
->tc_frag_data
.is_no_density
;
4834 fragP
->tc_frag_data
.is_no_transform
=
4835 last_fragP
->tc_frag_data
.is_no_transform
;
4836 fragP
->tc_frag_data
.use_longcalls
=
4837 last_fragP
->tc_frag_data
.use_longcalls
;
4838 fragP
->tc_frag_data
.use_absolute_literals
=
4839 last_fragP
->tc_frag_data
.use_absolute_literals
;
4842 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4851 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4853 void *unused ATTRIBUTE_UNUSED
)
4855 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4856 segment_info_type
*seginfo
= seg_info (sec
);
4857 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4859 if (flags
& SEC_CODE
)
4861 xtensa_isa isa
= xtensa_default_isa
;
4862 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4863 while (frag
!= NULL
)
4865 if (frag
->tc_frag_data
.is_branch_target
)
4871 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4872 fmt
= xtensa_format_decode (isa
, insnbuf
);
4873 op_size
= xtensa_format_length (isa
, fmt
);
4874 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4875 if (frag_addr
+ op_size
> (int) xtensa_fetch_width
)
4876 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4877 _("unaligned branch target: %d bytes at 0x%lx"),
4878 op_size
, frag
->fr_address
);
4880 frag
= frag
->fr_next
;
4882 xtensa_insnbuf_free (isa
, insnbuf
);
4888 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4890 void *unused ATTRIBUTE_UNUSED
)
4892 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4893 segment_info_type
*seginfo
= seg_info (sec
);
4894 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4895 xtensa_isa isa
= xtensa_default_isa
;
4897 if (flags
& SEC_CODE
)
4899 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4900 while (frag
!= NULL
)
4902 if (frag
->tc_frag_data
.is_first_loop_insn
)
4908 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4909 fmt
= xtensa_format_decode (isa
, insnbuf
);
4910 op_size
= xtensa_format_length (isa
, fmt
);
4911 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4913 if (frag_addr
+ op_size
> (signed) xtensa_fetch_width
)
4914 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4915 _("unaligned loop: %d bytes at 0x%lx"),
4916 op_size
, frag
->fr_address
);
4918 frag
= frag
->fr_next
;
4920 xtensa_insnbuf_free (isa
, insnbuf
);
4926 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4928 xtensa_isa isa
= xtensa_default_isa
;
4929 static xtensa_insnbuf insnbuf
= NULL
;
4930 static xtensa_insnbuf slotbuf
= NULL
;
4933 bfd_boolean alt_reloc
;
4934 xtensa_opcode opcode
;
4935 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4937 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4939 as_fatal (_("unexpected fix"));
4943 insnbuf
= xtensa_insnbuf_alloc (isa
);
4944 slotbuf
= xtensa_insnbuf_alloc (isa
);
4947 xtensa_insnbuf_from_chars (isa
, insnbuf
, fixpos
, 0);
4948 fmt
= xtensa_format_decode (isa
, insnbuf
);
4949 if (fmt
== XTENSA_UNDEFINED
)
4950 as_fatal (_("undecodable fix"));
4951 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4952 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4953 if (opcode
== XTENSA_UNDEFINED
)
4954 as_fatal (_("undecodable fix"));
4956 /* CONST16 immediates are not PC-relative, despite the fact that we
4957 reuse the normal PC-relative operand relocations for the low part
4958 of a CONST16 operand. */
4959 if (opcode
== xtensa_const16_opcode
)
4962 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4963 get_relaxable_immed (opcode
), val
,
4964 fixP
->fx_file
, fixP
->fx_line
);
4966 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4967 xtensa_insnbuf_to_chars (isa
, insnbuf
, fixpos
, 0);
4973 /* External Functions and Other GAS Hooks. */
4976 xtensa_target_format (void)
4978 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4983 xtensa_file_arch_init (bfd
*abfd
)
4985 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4990 md_number_to_chars (char *buf
, valueT val
, int n
)
4992 if (target_big_endian
)
4993 number_to_chars_bigendian (buf
, val
, n
);
4995 number_to_chars_littleendian (buf
, val
, n
);
4999 /* This function is called once, at assembler startup time. It should
5000 set up all the tables, etc. that the MD part of the assembler will
5006 segT current_section
= now_seg
;
5007 int current_subsec
= now_subseg
;
5010 xtensa_default_isa
= xtensa_isa_init (0, 0);
5011 isa
= xtensa_default_isa
;
5015 /* Set up the .literal, .fini.literal and .init.literal sections. */
5016 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5017 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5018 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5019 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5020 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5022 subseg_set (current_section
, current_subsec
);
5024 xg_init_vinsn (&cur_vinsn
);
5026 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5027 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5028 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5029 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5030 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5031 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5032 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5033 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5034 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5035 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5036 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5037 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5038 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5039 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5040 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5041 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5042 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5043 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5044 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5045 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5046 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5047 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5048 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5049 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5050 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5051 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5052 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5053 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5054 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5056 init_op_placement_info_table ();
5058 /* Set up the assembly state. */
5059 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5060 xtensa_set_frag_assembly_state (frag_now
);
5064 /* TC_INIT_FIX_DATA hook */
5067 xtensa_init_fix_data (fixS
*x
)
5069 x
->tc_fix_data
.slot
= 0;
5070 x
->tc_fix_data
.X_add_symbol
= NULL
;
5071 x
->tc_fix_data
.X_add_number
= 0;
5075 /* tc_frob_label hook */
5078 xtensa_frob_label (symbolS
*sym
)
5080 /* Since the label was already attached to a frag associated with the
5081 previous basic block, it now needs to be reset to the current frag. */
5082 symbol_set_frag (sym
, frag_now
);
5083 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5085 if (generating_literals
)
5086 xtensa_add_literal_sym (sym
);
5088 xtensa_add_insn_label (sym
);
5090 if (symbol_get_tc (sym
)->is_loop_target
5091 && (get_last_insn_flags (now_seg
, now_subseg
)
5092 & FLAG_IS_BAD_LOOPEND
) != 0)
5093 as_bad (_("invalid last instruction for a zero-overhead loop"));
5095 /* No target aligning in the absolute section. */
5096 if (now_seg
!= absolute_section
5097 && do_align_targets ()
5098 && !is_unaligned_label (sym
)
5099 && !generating_literals
)
5101 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5102 xtensa_set_frag_assembly_state (frag_now
);
5104 /* The only time this type of frag grows is when there is a
5105 negatable branch that needs to be relaxed as the last
5106 instruction in a zero-overhead loop. Because alignment frags
5107 are so common, marking them all as possibly growing four
5108 bytes makes any worst-case analysis appear much worse than it
5109 is. So, we make fr_var not actually reflect the amount of
5110 memory allocated at the end of this frag, but rather the
5111 amount of memory this frag might grow. The "4, 0" below
5112 allocates four bytes at the end of the frag for room to grow
5113 if we need to relax a loop end with a NOP. Frags prior to
5114 this one might grow to align this one, but the frag itself
5115 won't grow unless it meets the condition above. */
5117 #define RELAX_LOOP_END_BYTES 4
5119 frag_var (rs_machine_dependent
,
5120 RELAX_LOOP_END_BYTES
, (int) freq
,
5121 RELAX_DESIRE_ALIGN_IF_TARGET
,
5122 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5123 xtensa_set_frag_assembly_state (frag_now
);
5124 xtensa_move_labels (frag_now
, 0, TRUE
);
5127 /* We need to mark the following properties even if we aren't aligning. */
5129 /* If the label is already known to be a branch target, i.e., a
5130 forward branch, mark the frag accordingly. Backward branches
5131 are handled by xg_add_branch_and_loop_targets. */
5132 if (symbol_get_tc (sym
)->is_branch_target
)
5133 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5135 /* Loops only go forward, so they can be identified here. */
5136 if (symbol_get_tc (sym
)->is_loop_target
)
5137 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5141 /* tc_unrecognized_line hook */
5144 xtensa_unrecognized_line (int ch
)
5149 if (cur_vinsn
.inside_bundle
== 0)
5151 /* PR8110: Cannot emit line number info inside a FLIX bundle
5152 when using --gstabs. Temporarily disable debug info. */
5153 generate_lineno_debug ();
5154 if (debug_type
== DEBUG_STABS
)
5156 xt_saved_debug_type
= debug_type
;
5157 debug_type
= DEBUG_NONE
;
5160 cur_vinsn
.inside_bundle
= 1;
5164 as_bad (_("extra opening brace"));
5170 if (cur_vinsn
.inside_bundle
)
5171 finish_vinsn (&cur_vinsn
);
5174 as_bad (_("extra closing brace"));
5179 as_bad (_("syntax error"));
5186 /* md_flush_pending_output hook */
5189 xtensa_flush_pending_output (void)
5191 if (cur_vinsn
.inside_bundle
)
5192 as_bad (_("missing closing brace"));
5194 /* If there is a non-zero instruction fragment, close it. */
5195 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5197 frag_wane (frag_now
);
5199 xtensa_set_frag_assembly_state (frag_now
);
5201 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5203 xtensa_clear_insn_labels ();
5207 /* We had an error while parsing an instruction. The string might look
5208 like this: "insn arg1, arg2 }". If so, we need to see the closing
5209 brace and reset some fields. Otherwise, the vinsn never gets closed
5210 and the num_slots field will grow past the end of the array of slots,
5211 and bad things happen. */
5214 error_reset_cur_vinsn (void)
5216 if (cur_vinsn
.inside_bundle
)
5218 if (*input_line_pointer
== '}'
5219 || *(input_line_pointer
- 1) == '}'
5220 || *(input_line_pointer
- 2) == '}')
5221 xg_clear_vinsn (&cur_vinsn
);
5227 md_assemble (char *str
)
5229 xtensa_isa isa
= xtensa_default_isa
;
5232 bfd_boolean has_underbar
= FALSE
;
5233 char *arg_strings
[MAX_INSN_ARGS
];
5235 TInsn orig_insn
; /* Original instruction from the input. */
5237 tinsn_init (&orig_insn
);
5239 /* Split off the opcode. */
5240 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5241 opname
= xmalloc (opnamelen
+ 1);
5242 memcpy (opname
, str
, opnamelen
);
5243 opname
[opnamelen
] = '\0';
5245 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5248 as_bad (_("syntax error"));
5252 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5255 /* Check for an underbar prefix. */
5258 has_underbar
= TRUE
;
5262 orig_insn
.insn_type
= ITYPE_INSN
;
5264 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5266 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5267 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5269 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5270 if (fmt
== XTENSA_UNDEFINED
)
5272 as_bad (_("unknown opcode or format name '%s'"), opname
);
5273 error_reset_cur_vinsn ();
5276 if (!cur_vinsn
.inside_bundle
)
5278 as_bad (_("format names only valid inside bundles"));
5279 error_reset_cur_vinsn ();
5282 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5283 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5285 cur_vinsn
.format
= fmt
;
5286 free (has_underbar
? opname
- 1 : opname
);
5287 error_reset_cur_vinsn ();
5291 /* Parse the arguments. */
5292 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5294 as_bad (_("syntax error"));
5295 error_reset_cur_vinsn ();
5299 /* Free the opcode and argument strings, now that they've been parsed. */
5300 free (has_underbar
? opname
- 1 : opname
);
5302 while (num_args
-- > 0)
5303 free (arg_strings
[num_args
]);
5305 /* Get expressions for invisible operands. */
5306 if (get_invisible_operands (&orig_insn
))
5308 error_reset_cur_vinsn ();
5312 /* Check for the right number and type of arguments. */
5313 if (tinsn_check_arguments (&orig_insn
))
5315 error_reset_cur_vinsn ();
5319 dwarf2_where (&orig_insn
.loc
);
5321 xg_add_branch_and_loop_targets (&orig_insn
);
5323 /* Special-case for "entry" instruction. */
5324 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5326 /* Check that the third opcode (#2) is >= 16. */
5327 if (orig_insn
.ntok
>= 3)
5329 expressionS
*exp
= &orig_insn
.tok
[2];
5333 if (exp
->X_add_number
< 16)
5334 as_warn (_("entry instruction with stack decrement < 16"));
5338 as_warn (_("entry instruction with non-constant decrement"));
5344 assemble_tokens (opcode, tok, ntok);
5345 expand the tokens from the orig_insn into the
5346 stack of instructions that will not expand
5347 unless required at relaxation time. */
5349 if (!cur_vinsn
.inside_bundle
)
5350 emit_single_op (&orig_insn
);
5351 else /* We are inside a bundle. */
5353 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5354 cur_vinsn
.num_slots
++;
5355 if (*input_line_pointer
== '}'
5356 || *(input_line_pointer
- 1) == '}'
5357 || *(input_line_pointer
- 2) == '}')
5358 finish_vinsn (&cur_vinsn
);
5361 /* We've just emitted a new instruction so clear the list of labels. */
5362 xtensa_clear_insn_labels ();
5366 /* HANDLE_ALIGN hook */
5368 /* For a .align directive, we mark the previous block with the alignment
5369 information. This will be placed in the object file in the
5370 property section corresponding to this section. */
5373 xtensa_handle_align (fragS
*fragP
)
5376 && ! fragP
->tc_frag_data
.is_literal
5377 && (fragP
->fr_type
== rs_align
5378 || fragP
->fr_type
== rs_align_code
)
5379 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5380 && fragP
->fr_offset
> 0
5381 && now_seg
!= bss_section
)
5383 fragP
->tc_frag_data
.is_align
= TRUE
;
5384 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5387 if (fragP
->fr_type
== rs_align_test
)
5390 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5392 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5393 _("unaligned entry instruction"));
5398 /* TC_FRAG_INIT hook */
5401 xtensa_frag_init (fragS
*frag
)
5403 xtensa_set_frag_assembly_state (frag
);
5408 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5414 /* Round up a section size to the appropriate boundary. */
5417 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5419 return size
; /* Byte alignment is fine. */
5424 md_pcrel_from (fixS
*fixP
)
5427 static xtensa_insnbuf insnbuf
= NULL
;
5428 static xtensa_insnbuf slotbuf
= NULL
;
5431 xtensa_opcode opcode
;
5434 xtensa_isa isa
= xtensa_default_isa
;
5435 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5436 bfd_boolean alt_reloc
;
5438 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5443 insnbuf
= xtensa_insnbuf_alloc (isa
);
5444 slotbuf
= xtensa_insnbuf_alloc (isa
);
5447 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5448 xtensa_insnbuf_from_chars (isa
, insnbuf
, insn_p
, 0);
5449 fmt
= xtensa_format_decode (isa
, insnbuf
);
5451 if (fmt
== XTENSA_UNDEFINED
)
5452 as_fatal (_("bad instruction format"));
5454 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5455 as_fatal (_("invalid relocation"));
5457 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5458 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5460 /* Check for "alternate" relocations (operand not specified). None
5461 of the current uses for these are really PC-relative. */
5462 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5464 if (opcode
!= xtensa_l32r_opcode
5465 && opcode
!= xtensa_const16_opcode
)
5466 as_fatal (_("invalid relocation for '%s' instruction"),
5467 xtensa_opcode_name (isa
, opcode
));
5471 opnum
= get_relaxable_immed (opcode
);
5473 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5474 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5476 as_bad_where (fixP
->fx_file
,
5478 _("invalid relocation for operand %d of '%s'"),
5479 opnum
, xtensa_opcode_name (isa
, opcode
));
5482 return 0 - opnd_value
;
5486 /* TC_FORCE_RELOCATION hook */
5489 xtensa_force_relocation (fixS
*fix
)
5491 switch (fix
->fx_r_type
)
5493 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5494 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5495 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5496 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5497 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5501 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5502 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5503 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5504 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5505 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5506 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5507 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5508 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5514 if (linkrelax
&& fix
->fx_addsy
5515 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5518 return generic_force_reloc (fix
);
5522 /* TC_VALIDATE_FIX_SUB hook */
5525 xtensa_validate_fix_sub (fixS
*fix
)
5527 segT add_symbol_segment
, sub_symbol_segment
;
5529 /* The difference of two symbols should be resolved by the assembler when
5530 linkrelax is not set. If the linker may relax the section containing
5531 the symbols, then an Xtensa DIFF relocation must be generated so that
5532 the linker knows to adjust the difference value. */
5533 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5536 /* Make sure both symbols are in the same segment, and that segment is
5537 "normal" and relaxable. If the segment is not "normal", then the
5538 fix is not valid. If the segment is not "relaxable", then the fix
5539 should have been handled earlier. */
5540 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5541 if (! SEG_NORMAL (add_symbol_segment
) ||
5542 ! relaxable_section (add_symbol_segment
))
5544 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5545 return (sub_symbol_segment
== add_symbol_segment
);
5549 /* NO_PSEUDO_DOT hook */
5551 /* This function has nothing to do with pseudo dots, but this is the
5552 nearest macro to where the check needs to take place. FIXME: This
5556 xtensa_check_inside_bundle (void)
5558 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5559 as_bad (_("directives are not valid inside bundles"));
5561 /* This function must always return FALSE because it is called via a
5562 macro that has nothing to do with bundling. */
5567 /* md_elf_section_change_hook */
5570 xtensa_elf_section_change_hook (void)
5572 /* Set up the assembly state. */
5573 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5574 xtensa_set_frag_assembly_state (frag_now
);
5578 /* tc_fix_adjustable hook */
5581 xtensa_fix_adjustable (fixS
*fixP
)
5583 /* An offset is not allowed in combination with the difference of two
5584 symbols, but that cannot be easily detected after a local symbol
5585 has been adjusted to a (section+offset) form. Return 0 so that such
5586 an fix will not be adjusted. */
5587 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5588 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5591 /* We need the symbol name for the VTABLE entries. */
5592 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5593 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5601 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg
)
5603 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5606 switch (fixP
->fx_r_type
)
5611 if (linkrelax
&& fixP
->fx_subsy
)
5613 switch (fixP
->fx_r_type
)
5616 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5619 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5622 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5628 /* An offset is only allowed when it results from adjusting a
5629 local symbol into a section-relative offset. If the offset
5630 came from the original expression, tc_fix_adjustable will have
5631 prevented the fix from being converted to a section-relative
5632 form so that we can flag the error here. */
5633 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5635 _("cannot represent subtraction with an offset"));
5637 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5638 - S_GET_VALUE (fixP
->fx_subsy
));
5640 /* The difference value gets written out, and the DIFF reloc
5641 identifies the address of the subtracted symbol (i.e., the one
5642 with the lowest address). */
5644 fixP
->fx_offset
-= val
;
5645 fixP
->fx_subsy
= NULL
;
5647 else if (! fixP
->fx_addsy
)
5654 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5655 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5658 case BFD_RELOC_XTENSA_SLOT0_OP
:
5659 case BFD_RELOC_XTENSA_SLOT1_OP
:
5660 case BFD_RELOC_XTENSA_SLOT2_OP
:
5661 case BFD_RELOC_XTENSA_SLOT3_OP
:
5662 case BFD_RELOC_XTENSA_SLOT4_OP
:
5663 case BFD_RELOC_XTENSA_SLOT5_OP
:
5664 case BFD_RELOC_XTENSA_SLOT6_OP
:
5665 case BFD_RELOC_XTENSA_SLOT7_OP
:
5666 case BFD_RELOC_XTENSA_SLOT8_OP
:
5667 case BFD_RELOC_XTENSA_SLOT9_OP
:
5668 case BFD_RELOC_XTENSA_SLOT10_OP
:
5669 case BFD_RELOC_XTENSA_SLOT11_OP
:
5670 case BFD_RELOC_XTENSA_SLOT12_OP
:
5671 case BFD_RELOC_XTENSA_SLOT13_OP
:
5672 case BFD_RELOC_XTENSA_SLOT14_OP
:
5675 /* Write the tentative value of a PC-relative relocation to a
5676 local symbol into the instruction. The value will be ignored
5677 by the linker, and it makes the object file disassembly
5678 readable when all branch targets are encoded in relocations. */
5680 assert (fixP
->fx_addsy
);
5681 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5682 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5684 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5685 - md_pcrel_from (fixP
));
5686 (void) xg_apply_fix_value (fixP
, val
);
5689 else if (! fixP
->fx_addsy
)
5692 if (xg_apply_fix_value (fixP
, val
))
5697 case BFD_RELOC_XTENSA_PLT
:
5698 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5699 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5700 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5701 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5702 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5704 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5705 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5706 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5707 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5708 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5710 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5711 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5712 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5713 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5714 /* These all need to be resolved at link-time. Do nothing now. */
5717 case BFD_RELOC_VTABLE_INHERIT
:
5718 case BFD_RELOC_VTABLE_ENTRY
:
5723 as_bad (_("unhandled local relocation fix %s"),
5724 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5730 md_atof (int type
, char *litP
, int *sizeP
)
5733 LITTLENUM_TYPE words
[4];
5749 return "bad call to md_atof";
5752 t
= atof_ieee (input_line_pointer
, type
, words
);
5754 input_line_pointer
= t
;
5758 for (i
= prec
- 1; i
>= 0; i
--)
5761 if (target_big_endian
)
5762 idx
= (prec
- 1 - i
);
5764 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5773 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5775 return total_frag_text_expansion (fragP
);
5779 /* Translate internal representation of relocation info to BFD target
5783 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5787 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5788 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5789 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5790 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5792 /* Make sure none of our internal relocations make it this far.
5793 They'd better have been fully resolved by this point. */
5794 assert ((int) fixp
->fx_r_type
> 0);
5796 reloc
->addend
= fixp
->fx_offset
;
5798 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5799 if (reloc
->howto
== NULL
)
5801 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5802 _("cannot represent `%s' relocation in object file"),
5803 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5804 free (reloc
->sym_ptr_ptr
);
5809 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5810 as_fatal (_("internal error? cannot generate `%s' relocation"),
5811 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5817 /* Checks for resource conflicts between instructions. */
5819 /* The func unit stuff could be implemented as bit-vectors rather
5820 than the iterative approach here. If it ends up being too
5821 slow, we will switch it. */
5824 new_resource_table (void *data
,
5827 unit_num_copies_func uncf
,
5828 opcode_num_units_func onuf
,
5829 opcode_funcUnit_use_unit_func ouuf
,
5830 opcode_funcUnit_use_stage_func ousf
)
5833 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5835 rt
->cycles
= cycles
;
5836 rt
->allocated_cycles
= cycles
;
5838 rt
->unit_num_copies
= uncf
;
5839 rt
->opcode_num_units
= onuf
;
5840 rt
->opcode_unit_use
= ouuf
;
5841 rt
->opcode_unit_stage
= ousf
;
5843 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
5844 for (i
= 0; i
< cycles
; i
++)
5845 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
5852 clear_resource_table (resource_table
*rt
)
5855 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5856 for (j
= 0; j
< rt
->num_units
; j
++)
5857 rt
->units
[i
][j
] = 0;
5861 /* We never shrink it, just fake it into thinking so. */
5864 resize_resource_table (resource_table
*rt
, int cycles
)
5868 rt
->cycles
= cycles
;
5869 if (cycles
<= rt
->allocated_cycles
)
5872 old_cycles
= rt
->allocated_cycles
;
5873 rt
->allocated_cycles
= cycles
;
5875 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
5876 for (i
= 0; i
< old_cycles
; i
++)
5877 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
5878 for (i
= old_cycles
; i
< cycles
; i
++)
5879 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
5884 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5887 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5889 for (i
= 0; i
< uses
; i
++)
5891 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5892 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5893 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5894 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5895 if (copies_in_use
>= copies
)
5903 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5906 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5908 for (i
= 0; i
< uses
; i
++)
5910 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5911 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5912 /* Note that this allows resources to be oversubscribed. That's
5913 essential to the way the optional scheduler works.
5914 resources_available reports when a resource is over-subscribed,
5915 so it's easy to tell. */
5916 rt
->units
[stage
+ cycle
][unit
]++;
5922 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5925 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5927 for (i
= 0; i
< uses
; i
++)
5929 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5930 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5931 rt
->units
[stage
+ cycle
][unit
]--;
5932 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
5937 /* Wrapper functions make parameterized resource reservation
5941 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5943 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5949 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5951 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5956 /* Note that this function does not check issue constraints, but
5957 solely whether the hardware is available to execute the given
5958 instructions together. It also doesn't check if the tinsns
5959 write the same state, or access the same tieports. That is
5960 checked by check_t1_t2_reads_and_writes. */
5963 resources_conflict (vliw_insn
*vinsn
)
5966 static resource_table
*rt
= NULL
;
5968 /* This is the most common case by far. Optimize it. */
5969 if (vinsn
->num_slots
== 1)
5974 xtensa_isa isa
= xtensa_default_isa
;
5975 rt
= new_resource_table
5976 (isa
, xtensa_isa_num_pipe_stages (isa
),
5977 xtensa_isa_num_funcUnits (isa
),
5978 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5979 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5980 opcode_funcUnit_use_unit
,
5981 opcode_funcUnit_use_stage
);
5984 clear_resource_table (rt
);
5986 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5988 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5990 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5997 /* finish_vinsn, emit_single_op and helper functions. */
5999 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6000 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6001 static void bundle_single_op (TInsn
*);
6002 static void xg_assemble_vliw_tokens (vliw_insn
*);
6005 /* We have reached the end of a bundle; emit into the frag. */
6008 finish_vinsn (vliw_insn
*vinsn
)
6015 if (find_vinsn_conflicts (vinsn
))
6017 xg_clear_vinsn (vinsn
);
6021 /* First, find a format that works. */
6022 if (vinsn
->format
== XTENSA_UNDEFINED
)
6023 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6025 if (vinsn
->format
== XTENSA_UNDEFINED
)
6027 as_where (&file_name
, &line
);
6028 as_bad_where (file_name
, line
,
6029 _("couldn't find a valid instruction format"));
6030 fprintf (stderr
, _(" ops were: "));
6031 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6032 fprintf (stderr
, _(" %s;"),
6033 xtensa_opcode_name (xtensa_default_isa
,
6034 vinsn
->slots
[i
].opcode
));
6035 fprintf (stderr
, _("\n"));
6036 xg_clear_vinsn (vinsn
);
6040 if (vinsn
->num_slots
6041 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6043 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6044 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6045 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6047 xg_clear_vinsn (vinsn
);
6051 if (resources_conflict (vinsn
))
6053 as_where (&file_name
, &line
);
6054 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6055 fprintf (stderr
, " ops were: ");
6056 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6057 fprintf (stderr
, " %s;",
6058 xtensa_opcode_name (xtensa_default_isa
,
6059 vinsn
->slots
[i
].opcode
));
6060 fprintf (stderr
, "\n");
6061 xg_clear_vinsn (vinsn
);
6065 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6067 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6069 symbolS
*lit_sym
= NULL
;
6071 bfd_boolean e
= FALSE
;
6072 bfd_boolean saved_density
= density_supported
;
6074 /* We don't want to narrow ops inside multi-slot bundles. */
6075 if (vinsn
->num_slots
> 1)
6076 density_supported
= FALSE
;
6078 istack_init (&slotstack
);
6079 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6081 vinsn
->slots
[i
].opcode
=
6082 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6084 vinsn
->slots
[i
].ntok
= 0;
6087 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6093 density_supported
= saved_density
;
6097 xg_clear_vinsn (vinsn
);
6101 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6103 TInsn
*insn
= &slotstack
.insn
[j
];
6104 if (insn
->insn_type
== ITYPE_LITERAL
)
6106 assert (lit_sym
== NULL
);
6107 lit_sym
= xg_assemble_literal (insn
);
6111 assert (insn
->insn_type
== ITYPE_INSN
);
6113 xg_resolve_literals (insn
, lit_sym
);
6114 if (j
!= slotstack
.ninsn
- 1)
6115 emit_single_op (insn
);
6119 if (vinsn
->num_slots
> 1)
6121 if (opcode_fits_format_slot
6122 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6125 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6129 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6130 if (vinsn
->format
== XTENSA_UNDEFINED
)
6131 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6133 vinsn
->slots
[i
].opcode
6134 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6137 vinsn
->slots
[i
].ntok
= 0;
6142 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6143 vinsn
->format
= XTENSA_UNDEFINED
;
6148 /* Now check resource conflicts on the modified bundle. */
6149 if (resources_conflict (vinsn
))
6151 as_where (&file_name
, &line
);
6152 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6153 fprintf (stderr
, " ops were: ");
6154 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6155 fprintf (stderr
, " %s;",
6156 xtensa_opcode_name (xtensa_default_isa
,
6157 vinsn
->slots
[i
].opcode
));
6158 fprintf (stderr
, "\n");
6159 xg_clear_vinsn (vinsn
);
6163 /* First, find a format that works. */
6164 if (vinsn
->format
== XTENSA_UNDEFINED
)
6165 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6167 xg_assemble_vliw_tokens (vinsn
);
6169 xg_clear_vinsn (vinsn
);
6173 /* Given an vliw instruction, what conflicts are there in register
6174 usage and in writes to states and queues?
6176 This function does two things:
6177 1. Reports an error when a vinsn contains illegal combinations
6178 of writes to registers states or queues.
6179 2. Marks individual tinsns as not relaxable if the combination
6180 contains antidependencies.
6182 Job 2 handles things like swap semantics in instructions that need
6183 to be relaxed. For example,
6187 normally would be relaxed to
6192 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6194 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6196 then we can't relax it into
6199 { add a0, a1, a0 ; add a2, a0, a4 ; }
6201 because the value of a0 is trashed before the second add can read it. */
6203 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6206 find_vinsn_conflicts (vliw_insn
*vinsn
)
6210 xtensa_isa isa
= xtensa_default_isa
;
6212 assert (!past_xtensa_end
);
6214 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6216 TInsn
*op1
= &vinsn
->slots
[i
];
6217 if (op1
->is_specific_opcode
)
6218 op1
->keep_wide
= TRUE
;
6220 op1
->keep_wide
= FALSE
;
6223 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6225 TInsn
*op1
= &vinsn
->slots
[i
];
6227 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6230 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6234 TInsn
*op2
= &vinsn
->slots
[j
];
6235 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6236 switch (conflict_type
)
6239 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6240 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6241 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6244 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6245 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6246 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6249 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6250 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6251 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6254 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6255 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6256 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6259 /* Everything is OK. */
6262 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6263 || conflict_type
== 'a');
6270 as_bad (_("multiple branches or jumps in the same bundle"));
6278 /* Check how the state used by t1 and t2 relate.
6281 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6282 case B: no relationship between what is read and written (both could
6283 read the same reg though)
6284 case C: t1 writes a register t2 writes (a register conflict within a
6286 case D: t1 writes a state that t2 also writes
6287 case E: t1 writes a tie queue that t2 also writes
6288 case F: two volatile queue accesses
6292 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6294 xtensa_isa isa
= xtensa_default_isa
;
6295 xtensa_regfile t1_regfile
, t2_regfile
;
6297 int t1_base_reg
, t1_last_reg
;
6298 int t2_base_reg
, t2_last_reg
;
6299 char t1_inout
, t2_inout
;
6301 char conflict
= 'b';
6306 bfd_boolean t1_volatile
= FALSE
;
6307 bfd_boolean t2_volatile
= FALSE
;
6309 /* Check registers. */
6310 for (j
= 0; j
< t2
->ntok
; j
++)
6312 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6315 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6316 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6317 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6319 for (i
= 0; i
< t1
->ntok
; i
++)
6321 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6324 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6326 if (t1_regfile
!= t2_regfile
)
6329 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6330 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6332 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6333 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6335 if (t1_inout
== 'm' || t1_inout
== 'o'
6336 || t2_inout
== 'm' || t2_inout
== 'o')
6343 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6344 t1_last_reg
= (t1_base_reg
6345 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6347 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6349 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6351 if (t1_reg
!= t2_reg
)
6354 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6360 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6366 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6374 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6375 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6376 for (j
= 0; j
< t2_states
; j
++)
6378 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6379 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6380 for (i
= 0; i
< t1_states
; i
++)
6382 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6383 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6387 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6393 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6399 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6404 /* Check tieports. */
6405 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6406 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6407 for (j
= 0; j
< t2_interfaces
; j
++)
6409 xtensa_interface t2_int
6410 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6411 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6413 t2_inout
= xtensa_interface_inout (isa
, j
);
6414 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6417 for (i
= 0; i
< t1_interfaces
; i
++)
6419 xtensa_interface t1_int
6420 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6421 int t1_class
= xtensa_interface_class_id (isa
, t2_int
);
6423 t1_inout
= xtensa_interface_inout (isa
, i
);
6424 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6427 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6430 if (t1_int
!= t2_int
)
6433 if (t2_inout
== 'i' && t1_inout
== 'o')
6439 if (t1_inout
== 'i' && t2_inout
== 'o')
6445 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6454 static xtensa_format
6455 xg_find_narrowest_format (vliw_insn
*vinsn
)
6457 /* Right now we assume that the ops within the vinsn are properly
6458 ordered for the slots that the programmer wanted them in. In
6459 other words, we don't rearrange the ops in hopes of finding a
6460 better format. The scheduler handles that. */
6462 xtensa_isa isa
= xtensa_default_isa
;
6463 xtensa_format format
;
6464 vliw_insn v_copy
= *vinsn
;
6465 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6467 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6470 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6474 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6476 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6478 v_copy
.slots
[slot
].opcode
=
6479 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6480 v_copy
.slots
[slot
].ntok
= 0;
6483 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6486 else if (v_copy
.num_slots
> 1)
6489 /* Try the widened version. */
6490 if (!v_copy
.slots
[slot
].keep_wide
6491 && !v_copy
.slots
[slot
].is_specific_opcode
6492 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
6493 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
6494 && opcode_fits_format_slot (widened
.opcode
,
6497 /* The xg_is_narrow clause requires some explanation:
6499 addi can be "widened" to an addmi, which is then
6500 expanded to an addmi/addi pair if the immediate
6501 requires it, but here we must have a single widen
6504 xg_is_narrow tells us that addi isn't really
6505 narrow. The widen_spec_list says that there are
6508 v_copy
.slots
[slot
] = widened
;
6513 if (fit
== v_copy
.num_slots
)
6516 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6517 vinsn
->format
= format
;
6523 if (format
== xtensa_isa_num_formats (isa
))
6524 return XTENSA_UNDEFINED
;
6530 /* Return the additional space needed in a frag
6531 for possible relaxations of any ops in a VLIW insn.
6532 Also fill out the relaxations that might be required of
6533 each tinsn in the vinsn. */
6536 relaxation_requirements (vliw_insn
*vinsn
)
6538 int extra_space
= 0;
6541 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6543 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6544 if (!tinsn_has_symbolic_operands (tinsn
))
6546 /* A narrow instruction could be widened later to help
6547 alignment issues. */
6548 if (xg_is_narrow_insn (tinsn
)
6549 && !tinsn
->is_specific_opcode
6550 && vinsn
->num_slots
== 1)
6552 /* Difference in bytes between narrow and wide insns... */
6554 tinsn
->subtype
= RELAX_NARROW
;
6555 tinsn
->record_fix
= TRUE
;
6560 tinsn
->record_fix
= FALSE
;
6561 /* No extra_space needed. */
6566 if (workaround_b_j_loop_end
6567 && tinsn
->opcode
== xtensa_jx_opcode
6568 && use_transform ())
6570 /* Add 2 of these. */
6571 extra_space
+= 3; /* for the nop size */
6572 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6575 /* Need to assemble it with space for the relocation. */
6576 if (xg_is_relaxable_insn (tinsn
, 0)
6577 && !tinsn
->is_specific_opcode
)
6579 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6580 int max_literal_size
=
6581 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6583 tinsn
->literal_space
= max_literal_size
;
6585 tinsn
->subtype
= RELAX_IMMED
;
6586 tinsn
->record_fix
= FALSE
;
6587 extra_space
+= max_size
;
6591 tinsn
->record_fix
= TRUE
;
6592 /* No extra space needed. */
6601 bundle_single_op (TInsn
*orig_insn
)
6603 xtensa_isa isa
= xtensa_default_isa
;
6608 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6609 assert (v
.format
!= XTENSA_UNDEFINED
);
6610 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6613 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6616 v
.slots
[slot
].opcode
=
6617 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6618 v
.slots
[slot
].ntok
= 0;
6619 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6622 v
.slots
[slot
] = *orig_insn
;
6625 for ( ; slot
< v
.num_slots
; slot
++)
6627 v
.slots
[slot
].opcode
=
6628 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6629 v
.slots
[slot
].ntok
= 0;
6630 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6639 emit_single_op (TInsn
*orig_insn
)
6642 IStack istack
; /* put instructions into here */
6643 symbolS
*lit_sym
= NULL
;
6644 symbolS
*label_sym
= NULL
;
6646 istack_init (&istack
);
6648 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6649 Because the scheduling and bundling characteristics of movi and
6650 l32r or const16 are so different, we can do much better if we relax
6651 it prior to scheduling and bundling, rather than after. */
6652 if ((orig_insn
->opcode
== xtensa_movi_opcode
6653 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6654 && !cur_vinsn
.inside_bundle
6655 && (orig_insn
->tok
[1].X_op
== O_symbol
6656 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6657 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6659 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6662 for (i
= 0; i
< istack
.ninsn
; i
++)
6664 TInsn
*insn
= &istack
.insn
[i
];
6665 switch (insn
->insn_type
)
6668 assert (lit_sym
== NULL
);
6669 lit_sym
= xg_assemble_literal (insn
);
6673 static int relaxed_sym_idx
= 0;
6674 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6675 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6677 assert (label_sym
== NULL
);
6678 label_sym
= symbol_find_or_make (label
);
6685 xg_resolve_literals (insn
, lit_sym
);
6687 xg_resolve_labels (insn
, label_sym
);
6688 bundle_single_op (insn
);
6700 total_frag_text_expansion (fragS
*fragP
)
6703 int total_expansion
= 0;
6705 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6706 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6708 return total_expansion
;
6712 /* Emit a vliw instruction to the current fragment. */
6715 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6717 bfd_boolean finish_frag
= FALSE
;
6718 bfd_boolean is_jump
= FALSE
;
6719 bfd_boolean is_branch
= FALSE
;
6720 xtensa_isa isa
= xtensa_default_isa
;
6726 struct dwarf2_line_info best_loc
;
6728 best_loc
.line
= INT_MAX
;
6730 if (generating_literals
)
6732 static int reported
= 0;
6734 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6735 _("cannot assemble into a literal fragment"));
6742 if (frag_now_fix () != 0
6743 && (! frag_now
->tc_frag_data
.is_insn
6744 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6745 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6746 || (directive_state
[directive_longcalls
]
6747 != frag_now
->tc_frag_data
.use_longcalls
)
6748 || (directive_state
[directive_absolute_literals
]
6749 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6751 frag_wane (frag_now
);
6753 xtensa_set_frag_assembly_state (frag_now
);
6756 if (workaround_a0_b_retw
6757 && vinsn
->num_slots
== 1
6758 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6759 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6760 && use_transform ())
6762 has_a0_b_retw
= TRUE
;
6764 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6765 After the first assembly pass we will check all of them and
6766 add a nop if needed. */
6767 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6768 frag_var (rs_machine_dependent
, 4, 4,
6769 RELAX_ADD_NOP_IF_A0_B_RETW
,
6770 frag_now
->fr_symbol
,
6771 frag_now
->fr_offset
,
6773 xtensa_set_frag_assembly_state (frag_now
);
6774 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6775 frag_var (rs_machine_dependent
, 4, 4,
6776 RELAX_ADD_NOP_IF_A0_B_RETW
,
6777 frag_now
->fr_symbol
,
6778 frag_now
->fr_offset
,
6780 xtensa_set_frag_assembly_state (frag_now
);
6783 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6785 /* See if the instruction implies an aligned section. */
6786 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6787 record_alignment (now_seg
, 2);
6789 /* Also determine the best line number for debug info. */
6790 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6791 ? vinsn
->slots
[i
].loc
: best_loc
;
6794 /* Special cases for instructions that force an alignment... */
6795 /* None of these opcodes are bundle-able. */
6796 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6800 xtensa_set_frag_assembly_state (frag_now
);
6801 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6803 max_fill
= get_text_align_max_fill_size
6804 (get_text_align_power (xtensa_fetch_width
),
6805 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6807 if (use_transform ())
6808 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6809 RELAX_ALIGN_NEXT_OPCODE
,
6810 frag_now
->fr_symbol
,
6811 frag_now
->fr_offset
,
6814 frag_var (rs_machine_dependent
, 0, 0,
6815 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6816 xtensa_set_frag_assembly_state (frag_now
);
6818 xtensa_move_labels (frag_now
, 0, FALSE
);
6821 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6822 && !vinsn
->slots
[0].is_specific_opcode
)
6824 xtensa_mark_literal_pool_location ();
6825 xtensa_move_labels (frag_now
, 0, TRUE
);
6826 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6829 if (vinsn
->num_slots
== 1)
6831 if (workaround_a0_b_retw
&& use_transform ())
6832 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6833 is_register_writer (&vinsn
->slots
[0], "a", 0));
6835 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6836 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6839 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6841 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6843 extra_space
= relaxation_requirements (vinsn
);
6845 /* vinsn_to_insnbuf will produce the error. */
6846 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6848 f
= (char *) frag_more (insn_size
+ extra_space
);
6849 xtensa_set_frag_assembly_state (frag_now
);
6850 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6853 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6854 if (vinsn
->format
== XTENSA_UNDEFINED
)
6857 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, f
, 0);
6859 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
6861 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6863 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6864 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6865 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6866 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6867 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6868 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6869 if (tinsn
->literal_space
!= 0)
6870 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6872 if (tinsn
->subtype
== RELAX_NARROW
)
6873 assert (vinsn
->num_slots
== 1);
6874 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6876 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6879 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6880 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6884 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6885 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6889 frag_variant (rs_machine_dependent
,
6890 extra_space
, extra_space
, RELAX_SLOTS
,
6891 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6892 xtensa_set_frag_assembly_state (frag_now
);
6895 /* Special cases for loops:
6896 close_loop_end should be inserted AFTER short_loop.
6897 Make sure that CLOSE loops are processed BEFORE short_loops
6898 when converting them. */
6900 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6901 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6902 && !vinsn
->slots
[0].is_specific_opcode
)
6904 if (workaround_short_loop
&& use_transform ())
6906 maybe_has_short_loop
= TRUE
;
6907 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6908 frag_var (rs_machine_dependent
, 4, 4,
6909 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6910 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6911 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6912 frag_var (rs_machine_dependent
, 4, 4,
6913 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6914 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6917 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6918 loop at least 12 bytes away from another loop's end. */
6919 if (workaround_close_loop_end
&& use_transform ())
6921 maybe_has_close_loop_end
= TRUE
;
6922 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6923 frag_var (rs_machine_dependent
, 12, 12,
6924 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6925 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6929 if (use_transform ())
6933 assert (finish_frag
);
6934 frag_var (rs_machine_dependent
,
6935 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6937 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6938 xtensa_set_frag_assembly_state (frag_now
);
6940 else if (is_branch
&& align_targets
)
6942 assert (finish_frag
);
6943 frag_var (rs_machine_dependent
,
6944 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6945 RELAX_MAYBE_UNREACHABLE
,
6946 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6947 xtensa_set_frag_assembly_state (frag_now
);
6948 frag_var (rs_machine_dependent
,
6950 RELAX_MAYBE_DESIRE_ALIGN
,
6951 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6952 xtensa_set_frag_assembly_state (frag_now
);
6956 /* Now, if the original opcode was a call... */
6957 if (do_align_targets ()
6958 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6960 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6961 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6962 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6963 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6964 xtensa_set_frag_assembly_state (frag_now
);
6967 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6969 frag_wane (frag_now
);
6971 xtensa_set_frag_assembly_state (frag_now
);
6976 /* xtensa_end and helper functions. */
6978 static void xtensa_cleanup_align_frags (void);
6979 static void xtensa_fix_target_frags (void);
6980 static void xtensa_mark_narrow_branches (void);
6981 static void xtensa_mark_zcl_first_insns (void);
6982 static void xtensa_fix_a0_b_retw_frags (void);
6983 static void xtensa_fix_b_j_loop_end_frags (void);
6984 static void xtensa_fix_close_loop_end_frags (void);
6985 static void xtensa_fix_short_loop_frags (void);
6986 static void xtensa_sanity_check (void);
6991 directive_balance ();
6992 xtensa_flush_pending_output ();
6994 past_xtensa_end
= TRUE
;
6996 xtensa_move_literals ();
6998 xtensa_reorder_segments ();
6999 xtensa_cleanup_align_frags ();
7000 xtensa_fix_target_frags ();
7001 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7002 xtensa_fix_a0_b_retw_frags ();
7003 if (workaround_b_j_loop_end
)
7004 xtensa_fix_b_j_loop_end_frags ();
7006 /* "close_loop_end" should be processed BEFORE "short_loop". */
7007 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7008 xtensa_fix_close_loop_end_frags ();
7010 if (workaround_short_loop
&& maybe_has_short_loop
)
7011 xtensa_fix_short_loop_frags ();
7012 xtensa_mark_narrow_branches ();
7013 xtensa_mark_zcl_first_insns ();
7015 xtensa_sanity_check ();
7020 xtensa_cleanup_align_frags (void)
7024 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7027 /* Walk over all of the fragments in a subsection. */
7028 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7030 if ((fragP
->fr_type
== rs_align
7031 || fragP
->fr_type
== rs_align_code
7032 || (fragP
->fr_type
== rs_machine_dependent
7033 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7034 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7035 && fragP
->fr_fix
== 0)
7037 fragS
*next
= fragP
->fr_next
;
7040 && next
->fr_fix
== 0
7041 && next
->fr_type
== rs_machine_dependent
7042 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7045 next
= next
->fr_next
;
7048 /* If we don't widen branch targets, then they
7049 will be easier to align. */
7050 if (fragP
->tc_frag_data
.is_branch_target
7051 && fragP
->fr_opcode
== fragP
->fr_literal
7052 && fragP
->fr_type
== rs_machine_dependent
7053 && fragP
->fr_subtype
== RELAX_SLOTS
7054 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7056 if (fragP
->fr_type
== rs_machine_dependent
7057 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7058 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7064 /* Re-process all of the fragments looking to convert all of the
7065 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7066 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7067 If the next fragment starts with a loop target, AND the previous
7068 fragment can be expanded to negate the branch, convert this to a
7069 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7071 static bfd_boolean
frag_can_negate_branch (fragS
*);
7074 xtensa_fix_target_frags (void)
7078 /* When this routine is called, all of the subsections are still intact
7079 so we walk over subsections instead of sections. */
7080 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7082 bfd_boolean prev_frag_can_negate_branch
= FALSE
;
7085 /* Walk over all of the fragments in a subsection. */
7086 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7088 if (fragP
->fr_type
== rs_machine_dependent
7089 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7091 if (next_frag_is_loop_target (fragP
))
7093 if (prev_frag_can_negate_branch
)
7095 fragP
->fr_subtype
= RELAX_LOOP_END
;
7096 /* See the comment near the frag_var with a
7097 RELAX_DESIRE_ALIGN to see why we do this. */
7098 fragP
->fr_var
= RELAX_LOOP_END_BYTES
;
7102 if (next_frag_is_branch_target (fragP
))
7103 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7108 else if (next_frag_is_branch_target (fragP
))
7109 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7113 if (fragP
->fr_fix
!= 0)
7114 prev_frag_can_negate_branch
= FALSE
;
7115 if (frag_can_negate_branch (fragP
))
7116 prev_frag_can_negate_branch
= TRUE
;
7123 frag_can_negate_branch (fragS
*fragP
)
7125 xtensa_isa isa
= xtensa_default_isa
;
7129 if (fragP
->fr_type
!= rs_machine_dependent
7130 || fragP
->fr_subtype
!= RELAX_SLOTS
)
7133 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7135 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, vinsn
.format
); slot
++)
7137 if ((fragP
->tc_frag_data
.slot_subtypes
[slot
] == RELAX_IMMED
)
7138 && xtensa_opcode_is_branch (isa
, vinsn
.slots
[slot
].opcode
) == 1)
7146 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7149 xtensa_mark_narrow_branches (void)
7153 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7156 /* Walk over all of the fragments in a subsection. */
7157 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7159 if (fragP
->fr_type
== rs_machine_dependent
7160 && fragP
->fr_subtype
== RELAX_SLOTS
7161 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7164 const expressionS
*expr
;
7167 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7168 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7170 expr
= &vinsn
.slots
[0].tok
[1];
7171 symbolP
= expr
->X_add_symbol
;
7173 if (vinsn
.num_slots
== 1
7174 && xtensa_opcode_is_branch (xtensa_default_isa
,
7175 vinsn
.slots
[0].opcode
)
7176 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7177 && is_narrow_branch_guaranteed_in_range (fragP
,
7180 fragP
->fr_subtype
= RELAX_SLOTS
;
7181 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7189 /* A branch is typically widened only when its target is out of
7190 range. However, we would like to widen them to align a subsequent
7191 branch target when possible.
7193 Because the branch relaxation code is so convoluted, the optimal solution
7194 (combining the two cases) is difficult to get right in all circumstances.
7195 We therefore go with an "almost as good" solution, where we only
7196 use for alignment narrow branches that definitely will not expand to a
7197 jump and a branch. These functions find and mark these cases. */
7199 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7200 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7201 We start counting beginning with the frag after the 2-byte branch, so the
7202 maximum offset is (4 - 2) + 63 = 65. */
7203 #define MAX_IMMED6 65
7205 static size_t unrelaxed_frag_max_size (fragS
*);
7208 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7210 const expressionS
*expr
= &tinsn
->tok
[1];
7211 symbolS
*symbolP
= expr
->X_add_symbol
;
7212 fragS
*target_frag
= symbol_get_frag (symbolP
);
7213 size_t max_distance
= expr
->X_add_number
;
7214 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7215 if (is_branch_jmp_to_next (tinsn
, fragP
))
7218 /* The branch doesn't branch over it's own frag,
7219 but over the subsequent ones. */
7220 fragP
= fragP
->fr_next
;
7221 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7223 max_distance
+= unrelaxed_frag_max_size (fragP
);
7224 fragP
= fragP
->fr_next
;
7226 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7233 xtensa_mark_zcl_first_insns (void)
7237 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7240 /* Walk over all of the fragments in a subsection. */
7241 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7243 if (fragP
->fr_type
== rs_machine_dependent
7244 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7245 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7247 /* Find the loop frag. */
7248 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7249 /* Find the first insn frag. */
7250 targ_frag
= next_non_empty_frag (targ_frag
);
7252 /* Of course, sometimes (mostly for toy test cases) a
7253 zero-cost loop instruction is the last in a section. */
7256 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7257 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7266 /* Re-process all of the fragments looking to convert all of the
7267 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7268 conditional branch or a retw/retw.n, convert this frag to one that
7269 will generate a NOP. In any case close it off with a .fill 0. */
7271 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7274 xtensa_fix_a0_b_retw_frags (void)
7278 /* When this routine is called, all of the subsections are still intact
7279 so we walk over subsections instead of sections. */
7280 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7284 /* Walk over all of the fragments in a subsection. */
7285 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7287 if (fragP
->fr_type
== rs_machine_dependent
7288 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7290 if (next_instrs_are_b_retw (fragP
))
7292 if (fragP
->tc_frag_data
.is_no_transform
)
7293 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7295 relax_frag_add_nop (fragP
);
7305 next_instrs_are_b_retw (fragS
*fragP
)
7307 xtensa_opcode opcode
;
7309 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7310 static xtensa_insnbuf insnbuf
= NULL
;
7311 static xtensa_insnbuf slotbuf
= NULL
;
7312 xtensa_isa isa
= xtensa_default_isa
;
7315 bfd_boolean branch_seen
= FALSE
;
7319 insnbuf
= xtensa_insnbuf_alloc (isa
);
7320 slotbuf
= xtensa_insnbuf_alloc (isa
);
7323 if (next_fragP
== NULL
)
7326 /* Check for the conditional branch. */
7327 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7328 fmt
= xtensa_format_decode (isa
, insnbuf
);
7329 if (fmt
== XTENSA_UNDEFINED
)
7332 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7334 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7335 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7337 branch_seen
= (branch_seen
7338 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7344 offset
+= xtensa_format_length (isa
, fmt
);
7345 if (offset
== next_fragP
->fr_fix
)
7347 next_fragP
= next_non_empty_frag (next_fragP
);
7351 if (next_fragP
== NULL
)
7354 /* Check for the retw/retw.n. */
7355 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7356 fmt
= xtensa_format_decode (isa
, insnbuf
);
7358 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7359 have no problems. */
7360 if (fmt
== XTENSA_UNDEFINED
7361 || xtensa_format_num_slots (isa
, fmt
) != 1)
7364 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7365 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7367 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7374 /* Re-process all of the fragments looking to convert all of the
7375 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7376 loop end label, convert this frag to one that will generate a NOP.
7377 In any case close it off with a .fill 0. */
7379 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7382 xtensa_fix_b_j_loop_end_frags (void)
7386 /* When this routine is called, all of the subsections are still intact
7387 so we walk over subsections instead of sections. */
7388 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7392 /* Walk over all of the fragments in a subsection. */
7393 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7395 if (fragP
->fr_type
== rs_machine_dependent
7396 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7398 if (next_instr_is_loop_end (fragP
))
7400 if (fragP
->tc_frag_data
.is_no_transform
)
7401 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7403 relax_frag_add_nop (fragP
);
7413 next_instr_is_loop_end (fragS
*fragP
)
7415 const fragS
*next_fragP
;
7417 if (next_frag_is_loop_target (fragP
))
7420 next_fragP
= next_non_empty_frag (fragP
);
7421 if (next_fragP
== NULL
)
7424 if (!next_frag_is_loop_target (next_fragP
))
7427 /* If the size is >= 3 then there is more than one instruction here.
7428 The hardware bug will not fire. */
7429 if (next_fragP
->fr_fix
> 3)
7436 /* Re-process all of the fragments looking to convert all of the
7437 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7438 not MY loop's loop end within 12 bytes, add enough nops here to
7439 make it at least 12 bytes away. In any case close it off with a
7442 static size_t min_bytes_to_other_loop_end (fragS
*, fragS
*, offsetT
, size_t);
7445 xtensa_fix_close_loop_end_frags (void)
7449 /* When this routine is called, all of the subsections are still intact
7450 so we walk over subsections instead of sections. */
7451 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7455 fragS
*current_target
= NULL
;
7456 offsetT current_offset
= 0;
7458 /* Walk over all of the fragments in a subsection. */
7459 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7461 if (fragP
->fr_type
== rs_machine_dependent
7462 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7463 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7464 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7467 /* Read it. If the instruction is a loop, get the target. */
7469 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7470 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7471 t_insn
.opcode
) == 1)
7473 /* Get the current fragment target. */
7474 if (fragP
->tc_frag_data
.slot_symbols
[0])
7476 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7477 current_target
= symbol_get_frag (sym
);
7478 current_offset
= fragP
->fr_offset
;
7484 && fragP
->fr_type
== rs_machine_dependent
7485 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7488 size_t bytes_added
= 0;
7490 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7491 /* Max out at 12. */
7492 min_bytes
= min_bytes_to_other_loop_end
7493 (fragP
->fr_next
, current_target
, current_offset
,
7494 REQUIRED_LOOP_DIVIDING_BYTES
);
7496 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7498 if (fragP
->tc_frag_data
.is_no_transform
)
7499 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7502 while (min_bytes
+ bytes_added
7503 < REQUIRED_LOOP_DIVIDING_BYTES
)
7507 if (fragP
->fr_var
< length
)
7508 as_fatal (_("fr_var %lu < length %d"),
7509 fragP
->fr_var
, length
);
7512 assemble_nop (length
,
7513 fragP
->fr_literal
+ fragP
->fr_fix
);
7514 fragP
->fr_fix
+= length
;
7515 fragP
->fr_var
-= length
;
7517 bytes_added
+= length
;
7523 assert (fragP
->fr_type
!= rs_machine_dependent
7524 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7530 static size_t unrelaxed_frag_min_size (fragS
*);
7533 min_bytes_to_other_loop_end (fragS
*fragP
,
7534 fragS
*current_target
,
7535 offsetT current_offset
,
7539 fragS
*current_fragP
;
7541 for (current_fragP
= fragP
;
7543 current_fragP
= current_fragP
->fr_next
)
7545 if (current_fragP
->tc_frag_data
.is_loop_target
7546 && current_fragP
!= current_target
)
7547 return offset
+ current_offset
;
7549 offset
+= unrelaxed_frag_min_size (current_fragP
);
7551 if (offset
+ current_offset
>= max_size
)
7559 unrelaxed_frag_min_size (fragS
*fragP
)
7561 size_t size
= fragP
->fr_fix
;
7564 if (fragP
->fr_type
== rs_fill
)
7565 size
+= fragP
->fr_offset
;
7572 unrelaxed_frag_max_size (fragS
*fragP
)
7574 size_t size
= fragP
->fr_fix
;
7575 switch (fragP
->fr_type
)
7578 /* Empty frags created by the obstack allocation scheme
7579 end up with type 0. */
7584 size
+= fragP
->fr_offset
;
7592 /* No further adjustments needed. */
7594 case rs_machine_dependent
:
7595 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7596 size
+= fragP
->fr_var
;
7599 /* We had darn well better know how big it is. */
7608 /* Re-process all of the fragments looking to convert all
7609 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7612 1) the instruction size count to the loop end label
7613 is too short (<= 2 instructions),
7614 2) loop has a jump or branch in it
7617 1) workaround_all_short_loops is TRUE
7618 2) The generating loop was a 'loopgtz' or 'loopnez'
7619 3) the instruction size count to the loop end label is too short
7621 then convert this frag (and maybe the next one) to generate a NOP.
7622 In any case close it off with a .fill 0. */
7624 static size_t count_insns_to_loop_end (fragS
*, bfd_boolean
, size_t);
7625 static bfd_boolean
branch_before_loop_end (fragS
*);
7628 xtensa_fix_short_loop_frags (void)
7632 /* When this routine is called, all of the subsections are still intact
7633 so we walk over subsections instead of sections. */
7634 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7637 fragS
*current_target
= NULL
;
7638 offsetT current_offset
= 0;
7639 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7641 /* Walk over all of the fragments in a subsection. */
7642 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7644 /* Check on the current loop. */
7645 if (fragP
->fr_type
== rs_machine_dependent
7646 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7647 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7648 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7653 /* Read it. If the instruction is a loop, get the target. */
7654 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7655 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7656 t_insn
.opcode
) == 1)
7658 /* Get the current fragment target. */
7659 if (fragP
->tc_frag_data
.slot_symbols
[0])
7661 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7662 current_target
= symbol_get_frag (sym
);
7663 current_offset
= fragP
->fr_offset
;
7664 current_opcode
= t_insn
.opcode
;
7669 if (fragP
->fr_type
== rs_machine_dependent
7670 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7673 count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3);
7675 && (branch_before_loop_end (fragP
->fr_next
)
7676 || (workaround_all_short_loops
7677 && current_opcode
!= XTENSA_UNDEFINED
7678 && current_opcode
!= xtensa_loop_opcode
)))
7680 if (fragP
->tc_frag_data
.is_no_transform
)
7681 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7683 relax_frag_add_nop (fragP
);
7692 static size_t unrelaxed_frag_min_insn_count (fragS
*);
7695 count_insns_to_loop_end (fragS
*base_fragP
,
7696 bfd_boolean count_relax_add
,
7699 fragS
*fragP
= NULL
;
7700 size_t insn_count
= 0;
7704 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7706 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7707 if (insn_count
>= max_count
)
7710 if (count_relax_add
)
7712 if (fragP
->fr_type
== rs_machine_dependent
7713 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7715 /* In order to add the appropriate number of
7716 NOPs, we count an instruction for downstream
7719 if (insn_count
>= max_count
)
7729 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7731 xtensa_isa isa
= xtensa_default_isa
;
7732 static xtensa_insnbuf insnbuf
= NULL
;
7733 size_t insn_count
= 0;
7736 if (!fragP
->tc_frag_data
.is_insn
)
7740 insnbuf
= xtensa_insnbuf_alloc (isa
);
7742 /* Decode the fixed instructions. */
7743 while (offset
< fragP
->fr_fix
)
7747 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7748 fmt
= xtensa_format_decode (isa
, insnbuf
);
7750 if (fmt
== XTENSA_UNDEFINED
)
7752 as_fatal (_("undecodable instruction in instruction frag"));
7755 offset
+= xtensa_format_length (isa
, fmt
);
7763 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7766 branch_before_loop_end (fragS
*base_fragP
)
7770 for (fragP
= base_fragP
;
7771 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7772 fragP
= fragP
->fr_next
)
7774 if (unrelaxed_frag_has_b_j (fragP
))
7782 unrelaxed_frag_has_b_j (fragS
*fragP
)
7784 static xtensa_insnbuf insnbuf
= NULL
;
7785 xtensa_isa isa
= xtensa_default_isa
;
7788 if (!fragP
->tc_frag_data
.is_insn
)
7792 insnbuf
= xtensa_insnbuf_alloc (isa
);
7794 /* Decode the fixed instructions. */
7795 while (offset
< fragP
->fr_fix
)
7800 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7801 fmt
= xtensa_format_decode (isa
, insnbuf
);
7802 if (fmt
== XTENSA_UNDEFINED
)
7805 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7807 xtensa_opcode opcode
=
7808 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7809 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7810 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7813 offset
+= xtensa_format_length (isa
, fmt
);
7819 /* Checks to be made after initial assembly but before relaxation. */
7821 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7822 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7825 xtensa_sanity_check (void)
7832 as_where (&file_name
, &line
);
7833 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7837 /* Walk over all of the fragments in a subsection. */
7838 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7840 /* Currently we only check for empty loops here. */
7841 if (fragP
->fr_type
== rs_machine_dependent
7842 && fragP
->fr_subtype
== RELAX_IMMED
)
7844 static xtensa_insnbuf insnbuf
= NULL
;
7847 if (fragP
->fr_opcode
!= NULL
)
7850 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7851 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7852 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7854 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7855 t_insn
.opcode
) == 1)
7857 if (is_empty_loop (&t_insn
, fragP
))
7859 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7860 as_bad (_("invalid empty loop"));
7862 if (!is_local_forward_loop (&t_insn
, fragP
))
7864 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7865 as_bad (_("loop target does not follow "
7866 "loop instruction in section"));
7873 new_logical_line (file_name
, line
);
7877 #define LOOP_IMMED_OPN 1
7879 /* Return TRUE if the loop target is the next non-zero fragment. */
7882 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7884 const expressionS
*expr
;
7888 if (insn
->insn_type
!= ITYPE_INSN
)
7891 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7894 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7897 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7899 if (expr
->X_op
!= O_symbol
)
7902 symbolP
= expr
->X_add_symbol
;
7906 if (symbol_get_frag (symbolP
) == NULL
)
7909 if (S_GET_VALUE (symbolP
) != 0)
7912 /* Walk through the zero-size fragments from this one. If we find
7913 the target fragment, then this is a zero-size loop. */
7915 for (next_fragP
= fragP
->fr_next
;
7917 next_fragP
= next_fragP
->fr_next
)
7919 if (next_fragP
== symbol_get_frag (symbolP
))
7921 if (next_fragP
->fr_fix
!= 0)
7929 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7931 const expressionS
*expr
;
7935 if (insn
->insn_type
!= ITYPE_INSN
)
7938 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7941 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7944 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7946 if (expr
->X_op
!= O_symbol
)
7949 symbolP
= expr
->X_add_symbol
;
7953 if (symbol_get_frag (symbolP
) == NULL
)
7956 /* Walk through fragments until we find the target.
7957 If we do not find the target, then this is an invalid loop. */
7959 for (next_fragP
= fragP
->fr_next
;
7961 next_fragP
= next_fragP
->fr_next
)
7963 if (next_fragP
== symbol_get_frag (symbolP
))
7971 /* Alignment Functions. */
7974 get_text_align_power (int target_size
)
7977 for (i
= 0; i
< sizeof (size_t); i
++)
7979 if (target_size
<= (1 << i
))
7988 get_text_align_max_fill_size (int align_pow
,
7989 bfd_boolean use_nops
,
7990 bfd_boolean use_no_density
)
7993 return (1 << align_pow
);
7995 return 3 * (1 << align_pow
);
7997 return 1 + (1 << align_pow
);
8001 /* get_text_align_fill_size ()
8005 target_size = size of next instruction
8006 align_pow = get_text_align_power (target_size).
8010 address = current address + loop instruction size;
8011 target_size = 3 (for 2 or 3 byte target)
8012 = 4 (for 4 byte target)
8013 = 8 (for 8 byte target)
8014 align_pow = get_text_align_power (target_size);
8016 use_no_density = set appropriately
8018 address = current address + loop instruction size;
8020 align_pow = get_text_align_power (target_size);
8022 use_no_density = 0. */
8025 get_text_align_fill_size (addressT address
,
8028 bfd_boolean use_nops
,
8029 bfd_boolean use_no_density
)
8033 align_pow: log2 (required alignment).
8035 target_size: alignment must allow the new_address and
8036 new_address+target_size-1.
8038 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
8040 use_no_density: if use_nops and use_no_density, we can only use
8043 Usually the align_pow is the power of 2 that is greater than
8044 or equal to the target_size. This handles the 2-byte, 3-byte
8045 and 8-byte instructions.
8049 (1) aligning an instruction properly, but without using NOPs.
8050 E.G.: a 3-byte instruction can go on any address where address mod 4
8051 is zero or one. The aligner uses this case to find the optimal
8052 number of fill bytes for relax_frag_for_align.
8054 (2) aligning an instruction properly, but where we might need to use
8055 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8056 or similar to get the optimal location. */
8058 size_t alignment
= (1 << align_pow
);
8060 assert (target_size
!= 0);
8064 unsigned fill_bytes
;
8065 for (fill_bytes
= 0; fill_bytes
< alignment
; fill_bytes
++)
8067 addressT end_address
= address
+ target_size
- 1 + fill_bytes
;
8068 addressT start_address
= address
+ fill_bytes
;
8069 if ((end_address
>> align_pow
) == (start_address
>> align_pow
))
8075 /* This is the slightly harder case. */
8076 assert ((int) alignment
>= target_size
);
8077 assert (target_size
> 0);
8078 if (!use_no_density
)
8081 for (i
= 0; i
< alignment
* 2; i
++)
8085 if ((address
+ i
) >> align_pow
8086 == (address
+ i
+ target_size
- 1) >> align_pow
)
8094 /* Can only fill multiples of 3. */
8095 for (i
= 0; i
<= alignment
* 3; i
+= 3)
8097 if ((address
+ i
) >> align_pow
8098 == (address
+ i
+ target_size
- 1) >> align_pow
)
8107 /* This will assert if it is not possible. */
8110 get_text_align_nop_count (size_t fill_size
, bfd_boolean use_no_density
)
8115 assert (fill_size
% 3 == 0);
8116 return (fill_size
/ 3);
8119 assert (fill_size
!= 1); /* Bad argument. */
8121 while (fill_size
> 1)
8123 size_t insn_size
= 3;
8124 if (fill_size
== 2 || fill_size
== 4)
8126 fill_size
-= insn_size
;
8129 assert (fill_size
!= 1); /* Bad algorithm. */
8135 get_text_align_nth_nop_size (size_t fill_size
,
8137 bfd_boolean use_no_density
)
8141 assert (get_text_align_nop_count (fill_size
, use_no_density
) > n
);
8146 while (fill_size
> 1)
8148 size_t insn_size
= 3;
8149 if (fill_size
== 2 || fill_size
== 4)
8151 fill_size
-= insn_size
;
8161 /* For the given fragment, find the appropriate address
8162 for it to begin at if we are using NOPs to align it. */
8165 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8167 /* The rule is: get next fragment's FIRST instruction. Find
8168 the smallest number of bytes that need to be added to
8169 ensure that the next fragment's FIRST instruction will fit
8172 E.G., 2 bytes : 0, 1, 2 mod 4
8175 If the FIRST instruction MIGHT be relaxed,
8176 assume that it will become a 3-byte instruction.
8178 Note again here that LOOP instructions are not bundleable,
8179 and this relaxation only applies to LOOP opcodes. */
8181 size_t fill_size
= 0;
8182 int first_insn_size
;
8184 addressT pre_opcode_bytes
;
8187 xtensa_opcode opcode
;
8188 bfd_boolean is_loop
;
8190 assert (fragP
->fr_type
== rs_machine_dependent
);
8191 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8193 /* Find the loop frag. */
8194 first_insn
= next_non_empty_frag (fragP
);
8195 /* Now find the first insn frag. */
8196 first_insn
= next_non_empty_frag (first_insn
);
8198 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8200 loop_insn_size
= xg_get_single_size (opcode
);
8202 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8203 pre_opcode_bytes
+= loop_insn_size
;
8205 /* For loops, the alignment depends on the size of the
8206 instruction following the loop, not the LOOP instruction. */
8208 if (first_insn
== NULL
)
8211 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8213 first_insn_size
= frag_format_size (first_insn
);
8215 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8216 first_insn_size
= 3; /* ISA specifies this */
8218 /* If it was 8, then we'll need a larger alignment for the section. */
8219 alignment
= get_text_align_power (first_insn_size
);
8221 /* Is now_seg valid? */
8222 record_alignment (now_seg
, alignment
);
8224 fill_size
= get_text_align_fill_size
8225 (address
+ pre_opcode_bytes
,
8226 get_text_align_power (first_insn_size
),
8227 first_insn_size
, TRUE
, fragP
->tc_frag_data
.is_no_density
);
8229 return address
+ fill_size
;
8233 /* 3 mechanisms for relaxing an alignment:
8235 Align to a power of 2.
8236 Align so the next fragment's instruction does not cross a word boundary.
8237 Align the current instruction so that if the next instruction
8238 were 3 bytes, it would not cross a word boundary.
8242 zeros - This is easy; always insert zeros.
8243 nops - 3-byte and 2-byte instructions
8247 >=5 : 3-byte instruction + fn (n-3)
8248 widening - widen previous instructions. */
8251 get_aligned_diff (fragS
*fragP
, addressT address
, addressT
*max_diff
)
8253 addressT target_address
, loop_insn_offset
;
8255 xtensa_opcode loop_opcode
;
8256 bfd_boolean is_loop
;
8257 int text_align_power
;
8260 assert (fragP
->fr_type
== rs_machine_dependent
);
8261 switch (fragP
->fr_subtype
)
8263 case RELAX_DESIRE_ALIGN
:
8264 target_size
= next_frag_format_size (fragP
);
8265 if (target_size
== XTENSA_UNDEFINED
)
8267 text_align_power
= get_text_align_power (xtensa_fetch_width
);
8268 opt_diff
= get_text_align_fill_size (address
, text_align_power
,
8269 target_size
, FALSE
, FALSE
);
8271 *max_diff
= opt_diff
+ xtensa_fetch_width
8272 - (target_size
+ ((address
+ opt_diff
) % xtensa_fetch_width
));
8273 assert (*max_diff
>= opt_diff
);
8276 case RELAX_ALIGN_NEXT_OPCODE
:
8277 target_size
= next_frag_format_size (fragP
);
8278 loop_insn_offset
= 0;
8279 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8282 /* If the loop has been expanded then the LOOP instruction
8283 could be at an offset from this fragment. */
8284 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8286 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8288 if (target_size
== 2)
8289 target_size
= 3; /* ISA specifies this */
8291 /* In an ideal world, which is what we are shooting for here,
8292 we wouldn't need to use any NOPs immediately prior to the
8293 LOOP instruction. If this approach fails, relax_frag_loop_align
8294 will call get_noop_aligned_address. */
8296 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8297 text_align_power
= get_text_align_power (target_size
),
8298 opt_diff
= get_text_align_fill_size (target_address
, text_align_power
,
8299 target_size
, FALSE
, FALSE
);
8301 *max_diff
= xtensa_fetch_width
8302 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8303 - target_size
+ opt_diff
;
8304 assert (*max_diff
>= opt_diff
);
8315 /* md_relax_frag Hook and Helper Functions. */
8317 static long relax_frag_loop_align (fragS
*, long);
8318 static long relax_frag_for_align (fragS
*, long);
8319 static long relax_frag_immed
8320 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8323 /* Return the number of bytes added to this fragment, given that the
8324 input has been stretched already by "stretch". */
8327 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8329 xtensa_isa isa
= xtensa_default_isa
;
8330 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8331 long new_stretch
= 0;
8334 static xtensa_insnbuf vbuf
= NULL
;
8335 int slot
, num_slots
;
8338 as_where (&file_name
, &line
);
8339 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8341 fragP
->tc_frag_data
.unreported_expansion
= 0;
8343 switch (fragP
->fr_subtype
)
8345 case RELAX_ALIGN_NEXT_OPCODE
:
8346 /* Always convert. */
8347 if (fragP
->tc_frag_data
.relax_seen
)
8348 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8351 case RELAX_LOOP_END
:
8355 case RELAX_LOOP_END_ADD_NOP
:
8356 /* Add a NOP and switch to .fill 0. */
8357 new_stretch
= relax_frag_add_nop (fragP
);
8361 case RELAX_DESIRE_ALIGN
:
8362 /* Do nothing. The narrowing before this frag will either align
8367 case RELAX_LITERAL_FINAL
:
8370 case RELAX_LITERAL_NR
:
8372 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8373 assert (unreported
== lit_size
);
8374 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8375 fragP
->fr_var
-= lit_size
;
8376 fragP
->fr_fix
+= lit_size
;
8382 vbuf
= xtensa_insnbuf_alloc (isa
);
8384 xtensa_insnbuf_from_chars (isa
, vbuf
, fragP
->fr_opcode
, 0);
8385 fmt
= xtensa_format_decode (isa
, vbuf
);
8386 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8388 for (slot
= 0; slot
< num_slots
; slot
++)
8390 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8393 if (fragP
->tc_frag_data
.relax_seen
)
8394 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8398 case RELAX_IMMED_STEP1
:
8399 case RELAX_IMMED_STEP2
:
8400 /* Place the immediate. */
8401 new_stretch
+= relax_frag_immed
8402 (now_seg
, fragP
, stretch
,
8403 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8404 fmt
, slot
, stretched_p
, FALSE
);
8408 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8414 case RELAX_LITERAL_POOL_BEGIN
:
8415 case RELAX_LITERAL_POOL_END
:
8416 case RELAX_MAYBE_UNREACHABLE
:
8417 case RELAX_MAYBE_DESIRE_ALIGN
:
8418 /* No relaxation required. */
8421 case RELAX_FILL_NOP
:
8422 case RELAX_UNREACHABLE
:
8423 if (fragP
->tc_frag_data
.relax_seen
)
8424 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8428 as_bad (_("bad relaxation state"));
8431 /* Tell gas we need another relaxation pass. */
8432 if (! fragP
->tc_frag_data
.relax_seen
)
8434 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8438 new_logical_line (file_name
, line
);
8444 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8446 addressT old_address
, old_next_address
, old_size
;
8447 addressT new_address
, new_next_address
, new_size
;
8450 /* All the frags with relax_frag_for_alignment prior to this one in the
8451 section have been done, hopefully eliminating the need for a NOP here.
8452 But, this will put it in if necessary. */
8454 /* Calculate the old address of this fragment and the next fragment. */
8455 old_address
= fragP
->fr_address
- stretch
;
8456 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8457 fragP
->tc_frag_data
.text_expansion
[0]);
8458 old_size
= old_next_address
- old_address
;
8460 /* Calculate the new address of this fragment and the next fragment. */
8461 new_address
= fragP
->fr_address
;
8463 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8464 new_size
= new_next_address
- new_address
;
8466 growth
= new_size
- old_size
;
8468 /* Fix up the text_expansion field and return the new growth. */
8469 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8474 /* Add a NOP instruction. */
8477 relax_frag_add_nop (fragS
*fragP
)
8479 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8480 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8481 assemble_nop (length
, nop_buf
);
8482 fragP
->tc_frag_data
.is_insn
= TRUE
;
8484 if (fragP
->fr_var
< length
)
8486 as_fatal (_("fr_var (%ld) < length (%d)"), fragP
->fr_var
, length
);
8490 fragP
->fr_fix
+= length
;
8491 fragP
->fr_var
-= length
;
8496 static long future_alignment_required (fragS
*, long);
8499 relax_frag_for_align (fragS
*fragP
, long stretch
)
8501 /* Overview of the relaxation procedure for alignment:
8502 We can widen with NOPs or by widening instructions or by filling
8503 bytes after jump instructions. Find the opportune places and widen
8504 them if necessary. */
8509 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8510 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8511 || (fragP
->fr_subtype
== RELAX_SLOTS
8512 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8514 stretch_me
= future_alignment_required (fragP
, stretch
);
8515 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8521 /* We expanded on a previous pass. Can we shrink now? */
8522 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8523 if (shrink
<= stretch
&& stretch
> 0)
8525 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8531 /* Below here, diff > 0. */
8532 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8538 /* Return the address of the next frag that should be aligned.
8540 By "address" we mean the address it _would_ be at if there
8541 is no action taken to align it between here and the target frag.
8542 In other words, if no narrows and no fill nops are used between
8543 here and the frag to align, _even_if_ some of the frags we use
8544 to align targets have already expanded on a previous relaxation
8547 Also, count each frag that may be used to help align the target.
8549 Return 0 if there are no frags left in the chain that need to be
8553 find_address_of_next_align_frag (fragS
**fragPP
,
8557 bfd_boolean
*paddable
)
8559 fragS
*fragP
= *fragPP
;
8560 addressT address
= fragP
->fr_address
;
8562 /* Do not reset the counts to 0. */
8566 /* Limit this to a small search. */
8572 address
+= fragP
->fr_fix
;
8574 if (fragP
->fr_type
== rs_fill
)
8575 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8576 else if (fragP
->fr_type
== rs_machine_dependent
)
8578 switch (fragP
->fr_subtype
)
8580 case RELAX_UNREACHABLE
:
8584 case RELAX_FILL_NOP
:
8586 if (!fragP
->tc_frag_data
.is_no_density
)
8591 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8596 address
+= total_frag_text_expansion (fragP
);;
8600 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8603 case RELAX_ALIGN_NEXT_OPCODE
:
8604 case RELAX_DESIRE_ALIGN
:
8608 case RELAX_MAYBE_UNREACHABLE
:
8609 case RELAX_MAYBE_DESIRE_ALIGN
:
8614 /* Just punt if we don't know the type. */
8621 /* Just punt if we don't know the type. */
8625 fragP
= fragP
->fr_next
;
8633 static long bytes_to_stretch (fragS
*, int, int, int, int);
8635 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8636 I'll leave this in until I am more confident this works. */
8638 #define LOOKAHEAD_ALIGNER 1
8641 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8643 fragS
*this_frag
= fragP
;
8647 int narrow_nops
= 0;
8648 bfd_boolean paddable
= FALSE
;
8649 offsetT local_opt_diff
;
8652 int stretch_amount
= 0;
8653 int local_stretch_amount
;
8654 int global_stretch_amount
;
8656 address
= find_address_of_next_align_frag
8657 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8661 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8662 opt_diff
= local_opt_diff
;
8663 assert (opt_diff
>= 0);
8664 assert (max_diff
>= opt_diff
);
8667 #ifdef LOOKAHEAD_ALIGNER
8669 fragP
= fragP
->fr_next
;
8671 while (fragP
&& opt_diff
< max_diff
&& address
)
8673 /* We only use these to determine if we can exit early
8674 because there will be plenty of ways to align future
8676 unsigned int glob_widens
= 0;
8679 bfd_boolean glob_pad
= 0;
8680 address
= find_address_of_next_align_frag
8681 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8682 /* If there is a padable portion, then skip. */
8683 if (glob_pad
|| (glob_widens
>= xtensa_fetch_width
))
8688 offsetT next_m_diff
;
8689 offsetT next_o_diff
;
8691 /* Downrange frags haven't had stretch added to them yet. */
8694 /* The address also includes any text expansion from this
8695 frag in a previous pass, but we don't want that. */
8696 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8698 /* Assume we are going to move at least opt_diff. In
8699 reality, we might not be able to, but assuming that
8700 we will helps catch cases where moving opt_diff pushes
8701 the next target from aligned to unaligned. */
8702 address
+= opt_diff
;
8704 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8706 /* Now cleanup for the adjustments to address. */
8707 next_o_diff
+= opt_diff
;
8708 next_m_diff
+= opt_diff
;
8709 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8710 opt_diff
= next_o_diff
;
8711 if (next_m_diff
< max_diff
)
8712 max_diff
= next_m_diff
;
8713 fragP
= fragP
->fr_next
;
8716 #endif /* LOOKAHEAD_ALIGNER */
8717 /* If there are enough wideners in between, do it. */
8720 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8722 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8727 local_stretch_amount
8728 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8729 num_widens
, local_opt_diff
);
8730 #ifdef LOOKAHEAD_ALIGNER
8731 global_stretch_amount
8732 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8733 num_widens
, opt_diff
);
8734 /* If the condition below is true, then the frag couldn't
8735 stretch the correct amount for the global case, so we just
8736 optimize locally. We'll rely on the subsequent frags to get
8737 the correct alignment in the global case. */
8738 if (global_stretch_amount
< local_stretch_amount
)
8739 stretch_amount
= local_stretch_amount
;
8741 stretch_amount
= global_stretch_amount
;
8742 #else /* ! LOOKAHEAD_ALIGNER */
8743 stretch_amount
= local_stretch_amount
;
8744 #endif /* ! LOOKAHEAD_ALIGNER */
8745 if (this_frag
->fr_subtype
== RELAX_SLOTS
8746 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8747 assert (stretch_amount
<= 1);
8748 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8750 if (this_frag
->tc_frag_data
.is_no_density
)
8751 assert (stretch_amount
== 3 || stretch_amount
== 0);
8753 assert (stretch_amount
<= 3);
8756 return stretch_amount
;
8760 /* The idea: widen everything you can to get a target or loop aligned,
8761 then start using NOPs.
8763 When we must have a NOP, here is a table of how we decide
8764 (so you don't have to fight through the control flow below):
8766 wide_nops = the number of wide NOPs available for aligning
8767 narrow_nops = the number of narrow NOPs available for aligning
8768 (a subset of wide_nops)
8769 widens = the number of narrow instructions that should be widened
8776 b 0 1 1 (case 3a makes this case unnecessary)
8779 c 0 1 2 (case 4a makes this case unnecessary)
8782 c 0 2 1 (case 5b makes this case unnecessary)
8785 c 0 1 4 (case 6b makes this case unneccesary)
8786 d 1 1 1 (case 6a makes this case unnecessary)
8787 e 0 2 2 (case 6a makes this case unnecessary)
8788 f 0 3 0 (case 6a makes this case unnecessary)
8791 c 1 1 2 (case 7b makes this case unnecessary)
8792 d 0 1 5 (case 7a makes this case unnecessary)
8793 e 0 2 3 (case 7b makes this case unnecessary)
8794 f 0 3 1 (case 7b makes this case unnecessary)
8795 g 1 2 1 (case 7b makes this case unnecessary)
8799 bytes_to_stretch (fragS
*this_frag
,
8805 int bytes_short
= desired_diff
- num_widens
;
8807 assert (desired_diff
>= 0 && desired_diff
< 8);
8808 if (desired_diff
== 0)
8811 assert (wide_nops
> 0 || num_widens
> 0);
8813 /* Always prefer widening to NOP-filling. */
8814 if (bytes_short
< 0)
8816 /* There are enough RELAX_NARROW frags after this one
8817 to align the target without widening this frag in any way. */
8821 if (bytes_short
== 0)
8823 /* Widen every narrow between here and the align target
8824 and the align target will be properly aligned. */
8825 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8831 /* From here we will need at least one NOP to get an alignment.
8832 However, we may not be able to align at all, in which case,
8834 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8836 switch (desired_diff
)
8841 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8842 return 2; /* case 2 */
8848 return 3; /* case 3a */
8850 if (num_widens
>= 1 && wide_nops
== 1)
8851 return 3; /* case 4a */
8852 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8853 return 2; /* case 4b */
8856 if (num_widens
>= 2 && wide_nops
== 1)
8857 return 3; /* case 5a */
8858 /* We will need two nops. Are there enough nops
8859 between here and the align target? */
8860 if (wide_nops
< 2 || narrow_nops
== 0)
8862 /* Are there other nops closer that can serve instead? */
8863 if (wide_nops
> 2 && narrow_nops
> 1)
8865 /* Take the density one first, because there might not be
8866 another density one available. */
8867 if (!this_frag
->tc_frag_data
.is_no_density
)
8868 return 2; /* case 5b narrow */
8870 return 3; /* case 5b wide */
8874 return 3; /* case 6a */
8875 else if (num_widens
>= 3 && wide_nops
== 1)
8876 return 3; /* case 6b */
8879 if (wide_nops
== 1 && num_widens
>= 4)
8880 return 3; /* case 7a */
8881 else if (wide_nops
== 2 && num_widens
>= 1)
8882 return 3; /* case 7b */
8890 /* We will need a NOP no matter what, but should we widen
8891 this instruction to help?
8893 This is a RELAX_FRAG_NARROW frag. */
8894 switch (desired_diff
)
8903 if (wide_nops
>= 1 && num_widens
== 1)
8904 return 1; /* case 4a */
8907 if (wide_nops
>= 1 && num_widens
== 2)
8908 return 1; /* case 5a */
8912 return 0; /* case 6a */
8913 else if (wide_nops
>= 1 && num_widens
== 3)
8914 return 1; /* case 6b */
8917 if (wide_nops
>= 1 && num_widens
== 4)
8918 return 1; /* case 7a */
8919 else if (wide_nops
>= 2 && num_widens
== 1)
8920 return 1; /* case 7b */
8933 relax_frag_immed (segT segP
,
8940 bfd_boolean estimate_only
)
8943 vliw_insn orig_vinsn
;
8945 bfd_boolean negatable_branch
= FALSE
;
8946 bfd_boolean branch_jmp_to_next
= FALSE
;
8947 bfd_boolean wide_insn
= FALSE
;
8948 xtensa_isa isa
= xtensa_default_isa
;
8950 offsetT frag_offset
;
8953 int num_text_bytes
, num_literal_bytes
;
8954 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8956 assert (fragP
->fr_opcode
!= NULL
);
8958 xg_init_vinsn (&orig_vinsn
);
8959 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
8960 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8963 tinsn
= orig_vinsn
.slots
[slot
];
8964 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8966 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8969 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8970 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8972 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8974 old_size
= xtensa_format_length (isa
, fmt
);
8976 /* Special case: replace a branch to the next instruction with a NOP.
8977 This is required to work around a hardware bug in T1040.0 and also
8978 serves as an optimization. */
8980 if (branch_jmp_to_next
8981 && ((old_size
== 2) || (old_size
== 3))
8982 && !next_frag_is_loop_target (fragP
))
8985 /* Here is the fun stuff: Get the immediate field from this
8986 instruction. If it fits, we are done. If not, find the next
8987 instruction sequence that fits. */
8989 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8990 istack_init (&istack
);
8991 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8992 min_steps
, stretch
);
8993 if (num_steps
< min_steps
)
8995 as_fatal (_("internal error: relaxation failed"));
8999 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9001 as_fatal (_("internal error: relaxation requires too many steps"));
9005 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9007 /* Figure out the number of bytes needed. */
9009 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9011 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9013 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9015 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9018 num_text_bytes
+= old_size
;
9019 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9020 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9022 total_text_diff
= num_text_bytes
- old_size
;
9023 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9025 /* It MUST get larger. If not, we could get an infinite loop. */
9026 assert (num_text_bytes
>= 0);
9027 assert (literal_diff
>= 0);
9028 assert (total_text_diff
>= 0);
9030 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9031 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9032 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9033 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9035 /* Find the associated expandable literal for this. */
9036 if (literal_diff
!= 0)
9038 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9041 assert (literal_diff
== 4);
9042 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9044 /* We expect that the literal section state has NOT been
9046 assert (lit_fragP
->fr_type
== rs_machine_dependent
9047 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9048 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9050 /* We need to mark this section for another iteration
9056 if (negatable_branch
&& istack
.ninsn
> 1)
9057 update_next_frag_state (fragP
);
9059 return this_text_diff
;
9063 /* md_convert_frag Hook and Helper Functions. */
9065 static void convert_frag_align_next_opcode (fragS
*);
9066 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9067 static void convert_frag_fill_nop (fragS
*);
9068 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9071 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9073 static xtensa_insnbuf vbuf
= NULL
;
9074 xtensa_isa isa
= xtensa_default_isa
;
9081 as_where (&file_name
, &line
);
9082 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9084 switch (fragp
->fr_subtype
)
9086 case RELAX_ALIGN_NEXT_OPCODE
:
9087 /* Always convert. */
9088 convert_frag_align_next_opcode (fragp
);
9091 case RELAX_DESIRE_ALIGN
:
9092 /* Do nothing. If not aligned already, too bad. */
9096 case RELAX_LITERAL_FINAL
:
9101 vbuf
= xtensa_insnbuf_alloc (isa
);
9103 xtensa_insnbuf_from_chars (isa
, vbuf
, fragp
->fr_opcode
, 0);
9104 fmt
= xtensa_format_decode (isa
, vbuf
);
9105 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9107 for (slot
= 0; slot
< num_slots
; slot
++)
9109 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9112 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9116 case RELAX_IMMED_STEP1
:
9117 case RELAX_IMMED_STEP2
:
9118 /* Place the immediate. */
9121 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9126 /* This is OK because some slots could have
9127 relaxations and others have none. */
9133 case RELAX_UNREACHABLE
:
9134 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9135 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9136 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9140 case RELAX_MAYBE_UNREACHABLE
:
9141 case RELAX_MAYBE_DESIRE_ALIGN
:
9145 case RELAX_FILL_NOP
:
9146 convert_frag_fill_nop (fragp
);
9149 case RELAX_LITERAL_NR
:
9150 if (use_literal_section
)
9152 /* This should have been handled during relaxation. When
9153 relaxing a code segment, literals sometimes need to be
9154 added to the corresponding literal segment. If that
9155 literal segment has already been relaxed, then we end up
9156 in this situation. Marking the literal segments as data
9157 would make this happen less often (since GAS always relaxes
9158 code before data), but we could still get into trouble if
9159 there are instructions in a segment that is not marked as
9160 containing code. Until we can implement a better solution,
9161 cheat and adjust the addresses of all the following frags.
9162 This could break subsequent alignments, but the linker's
9163 literal coalescing will do that anyway. */
9166 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9167 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9168 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9171 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9175 as_bad (_("invalid relaxation fragment result"));
9180 new_logical_line (file_name
, line
);
9185 convert_frag_align_next_opcode (fragS
*fragp
)
9187 char *nop_buf
; /* Location for Writing. */
9190 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9191 addressT aligned_address
;
9192 size_t fill_size
, nop_count
;
9194 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9196 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9197 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9198 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9200 for (i
= 0; i
< nop_count
; i
++)
9203 nop_size
= get_text_align_nth_nop_size (fill_size
, i
, use_no_density
);
9205 assemble_nop (nop_size
, nop_buf
);
9206 nop_buf
+= nop_size
;
9209 fragp
->fr_fix
+= fill_size
;
9210 fragp
->fr_var
-= fill_size
;
9215 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9217 TInsn tinsn
, single_target
;
9218 xtensa_format single_fmt
;
9219 int size
, old_size
, diff
, error_val
;
9220 offsetT frag_offset
;
9223 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9225 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9227 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9228 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9229 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9234 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9236 /* No conversion. */
9241 assert (fragP
->fr_opcode
!= NULL
);
9243 /* Frags in this relaxation state should only contain
9244 single instruction bundles. */
9245 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9247 /* Just convert it to a wide form.... */
9249 old_size
= xg_get_single_size (tinsn
.opcode
);
9251 tinsn_init (&single_target
);
9252 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9254 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
9257 as_bad (_("unable to widen instruction"));
9261 size
= xg_get_single_size (single_target
.opcode
);
9262 single_fmt
= xg_get_single_format (single_target
.opcode
);
9264 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9265 fragP
, frag_offset
, TRUE
);
9267 diff
= size
- old_size
;
9269 assert (diff
<= fragP
->fr_var
);
9270 fragP
->fr_var
-= diff
;
9271 fragP
->fr_fix
+= diff
;
9279 convert_frag_fill_nop (fragS
*fragP
)
9281 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9282 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9283 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9284 - fragP
->fr_address
- fragP
->fr_fix
));
9287 /* No conversion. */
9291 assemble_nop (size
, loc
);
9292 fragP
->tc_frag_data
.is_insn
= TRUE
;
9293 fragP
->fr_var
-= size
;
9294 fragP
->fr_fix
+= size
;
9299 static fixS
*fix_new_exp_in_seg
9300 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9301 bfd_reloc_code_real_type
);
9302 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9305 convert_frag_immed (segT segP
,
9311 char *immed_instr
= fragP
->fr_opcode
;
9313 bfd_boolean expanded
= FALSE
;
9314 bfd_boolean branch_jmp_to_next
= FALSE
;
9315 char *fr_opcode
= fragP
->fr_opcode
;
9316 vliw_insn orig_vinsn
;
9317 xtensa_isa isa
= xtensa_default_isa
;
9318 bfd_boolean wide_insn
= FALSE
;
9320 bfd_boolean is_loop
;
9322 assert (fr_opcode
!= NULL
);
9324 xg_init_vinsn (&orig_vinsn
);
9326 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9327 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9330 orig_tinsn
= orig_vinsn
.slots
[slot
];
9331 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9333 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9335 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9336 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9338 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9340 /* Conversion just inserts a NOP and marks the fix as completed. */
9341 bytes
= xtensa_format_length (isa
, fmt
);
9344 orig_vinsn
.slots
[slot
].opcode
=
9345 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9346 orig_vinsn
.slots
[slot
].ntok
= 0;
9350 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9351 assert (bytes
== 2 || bytes
== 3);
9352 build_nop (&orig_vinsn
.slots
[0], bytes
);
9353 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9355 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9356 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
, fr_opcode
, 0);
9361 /* Here is the fun stuff: Get the immediate field from this
9362 instruction. If it fits, we're done. If not, find the next
9363 instruction sequence that fits. */
9367 symbolS
*lit_sym
= NULL
;
9369 int target_offset
= 0;
9372 symbolS
*gen_label
= NULL
;
9373 offsetT frag_offset
;
9374 bfd_boolean first
= TRUE
;
9375 bfd_boolean last_is_jump
;
9377 /* It does not fit. Find something that does and
9378 convert immediately. */
9379 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9380 istack_init (&istack
);
9381 xg_assembly_relax (&istack
, &orig_tinsn
,
9382 segP
, fragP
, frag_offset
, min_steps
, 0);
9384 old_size
= xtensa_format_length (isa
, fmt
);
9386 /* Assemble this right inline. */
9388 /* First, create the mapping from a label name to the REAL label. */
9390 for (i
= 0; i
< istack
.ninsn
; i
++)
9392 TInsn
*tinsn
= &istack
.insn
[i
];
9395 switch (tinsn
->insn_type
)
9398 if (lit_sym
!= NULL
)
9399 as_bad (_("multiple literals in expansion"));
9400 /* First find the appropriate space in the literal pool. */
9401 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9402 if (lit_frag
== NULL
)
9403 as_bad (_("no registered fragment for literal"));
9404 if (tinsn
->ntok
!= 1)
9405 as_bad (_("number of literal tokens != 1"));
9407 /* Set the literal symbol and add a fixup. */
9408 lit_sym
= lit_frag
->fr_symbol
;
9412 if (align_targets
&& !is_loop
)
9414 fragS
*unreach
= fragP
->fr_next
;
9415 while (!(unreach
->fr_type
== rs_machine_dependent
9416 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9417 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9419 unreach
= unreach
->fr_next
;
9422 assert (unreach
->fr_type
== rs_machine_dependent
9423 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9424 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9426 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9428 assert (gen_label
== NULL
);
9429 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9430 fr_opcode
- fragP
->fr_literal
9431 + target_offset
, fragP
);
9435 if (first
&& wide_insn
)
9437 target_offset
+= xtensa_format_length (isa
, fmt
);
9439 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9440 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9443 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9450 last_is_jump
= FALSE
;
9451 for (i
= 0; i
< istack
.ninsn
; i
++)
9453 TInsn
*tinsn
= &istack
.insn
[i
];
9457 bfd_reloc_code_real_type reloc_type
;
9459 switch (tinsn
->insn_type
)
9462 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9463 /* Already checked. */
9464 assert (lit_frag
!= NULL
);
9465 assert (lit_sym
!= NULL
);
9466 assert (tinsn
->ntok
== 1);
9468 target_seg
= S_GET_SEGMENT (lit_sym
);
9469 assert (target_seg
);
9470 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9471 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9473 reloc_type
= BFD_RELOC_32
;
9474 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9475 &tinsn
->tok
[0], FALSE
, reloc_type
);
9482 xg_resolve_labels (tinsn
, gen_label
);
9483 xg_resolve_literals (tinsn
, lit_sym
);
9484 if (wide_insn
&& first
)
9487 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9489 tinsn
->record_fix
= TRUE
;
9490 orig_vinsn
.slots
[slot
] = *tinsn
;
9494 orig_vinsn
.slots
[slot
].opcode
=
9495 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9496 orig_vinsn
.slots
[slot
].ntok
= 0;
9497 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9499 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9500 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9502 fragP
->tc_frag_data
.is_insn
= TRUE
;
9503 size
= xtensa_format_length (isa
, fmt
);
9504 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9506 xtensa_format single_fmt
=
9507 xg_get_single_format (tinsn
->opcode
);
9510 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9511 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9512 size
+= xg_get_single_size (tinsn
->opcode
);
9517 xtensa_format single_format
;
9518 size
= xg_get_single_size (tinsn
->opcode
);
9519 single_format
= xg_get_single_format (tinsn
->opcode
);
9520 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9522 immed_instr
- fragP
->fr_literal
, TRUE
);
9524 immed_instr
+= size
;
9530 diff
= total_size
- old_size
;
9534 assert (diff
<= fragP
->fr_var
);
9535 fragP
->fr_var
-= diff
;
9536 fragP
->fr_fix
+= diff
;
9540 xg_free_vinsn (&orig_vinsn
);
9542 /* Check for undefined immediates in LOOP instructions. */
9546 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9547 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9549 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9552 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9553 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9555 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9560 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9561 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9563 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9565 /* Add an expansion note on the expanded instruction. */
9566 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9567 &orig_tinsn
.tok
[0], TRUE
,
9568 BFD_RELOC_XTENSA_ASM_EXPAND
);
9573 /* Add a new fix expression into the desired segment. We have to
9574 switch to that segment to do this. */
9577 fix_new_exp_in_seg (segT new_seg
,
9584 bfd_reloc_code_real_type r_type
)
9588 subsegT subseg
= now_subseg
;
9590 assert (new_seg
!= 0);
9591 subseg_set (new_seg
, new_subseg
);
9593 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9594 subseg_set (seg
, subseg
);
9599 /* Relax a loop instruction so that it can span loop >256 bytes.
9605 addi as, as, lo8 (label-.L1)
9606 addmi as, as, mid8 (label-.L1)
9617 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9622 unsigned long target
;
9623 static xtensa_insnbuf insnbuf
= NULL
;
9624 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9625 xtensa_isa isa
= xtensa_default_isa
;
9626 addressT loop_offset
;
9627 addressT addi_offset
= 9;
9628 addressT addmi_offset
= 12;
9630 size_t target_count
;
9633 insnbuf
= xtensa_insnbuf_alloc (isa
);
9635 /* Get the loop offset. */
9636 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9638 /* Validate that there really is a LOOP at the loop_offset. Because
9639 loops are not bundleable, we can assume that the instruction will be
9641 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9642 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9644 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9645 addi_offset
+= loop_offset
;
9646 addmi_offset
+= loop_offset
;
9648 assert (tinsn
->ntok
== 2);
9649 if (tinsn
->tok
[1].X_op
== O_constant
)
9650 target
= tinsn
->tok
[1].X_add_number
;
9651 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9653 /* Find the fragment. */
9654 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9655 assert (S_GET_SEGMENT (sym
) == segP
9656 || S_GET_SEGMENT (sym
) == absolute_section
);
9657 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9661 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9666 know (symbolP
->sy_frag
);
9667 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9668 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9670 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9671 loop_length_hi
= loop_length
& ~0x0ff;
9672 loop_length_lo
= loop_length
& 0x0ff;
9673 if (loop_length_lo
>= 128)
9675 loop_length_lo
-= 256;
9676 loop_length_hi
+= 256;
9679 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9680 32512. If the loop is larger than that, then we just fail. */
9681 if (loop_length_hi
> 32512)
9682 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9683 _("loop too long for LOOP instruction"));
9685 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9686 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9688 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9689 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9691 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9692 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9694 fragP
->tc_frag_data
.is_insn
= TRUE
;
9695 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addi_offset
, 0);
9697 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9698 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9699 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addmi_offset
, 0);
9701 /* Walk through all of the frags from here to the loop end
9702 and mark them as no_transform to keep them from being modified
9703 by the linker. If we ever have a relocation for the
9704 addi/addmi of the difference of two symbols we can remove this. */
9707 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9708 next_fragP
= next_fragP
->fr_next
)
9710 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9711 if (next_fragP
->tc_frag_data
.is_loop_target
)
9713 if (target_count
== 2)
9719 /* A map that keeps information on a per-subsegment basis. This is
9720 maintained during initial assembly, but is invalid once the
9721 subsegments are smashed together. I.E., it cannot be used during
9724 typedef struct subseg_map_struct
9732 float total_freq
; /* fall-through + branch target frequency */
9733 float target_freq
; /* branch target frequency alone */
9735 struct subseg_map_struct
*next
;
9739 static subseg_map
*sseg_map
= NULL
;
9742 get_subseg_info (segT seg
, subsegT subseg
)
9744 subseg_map
*subseg_e
;
9746 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9748 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9756 add_subseg_info (segT seg
, subsegT subseg
)
9758 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9759 memset (subseg_e
, 0, sizeof (subseg_map
));
9760 subseg_e
->seg
= seg
;
9761 subseg_e
->subseg
= subseg
;
9762 subseg_e
->flags
= 0;
9763 /* Start off considering every branch target very important. */
9764 subseg_e
->target_freq
= 1.0;
9765 subseg_e
->total_freq
= 1.0;
9766 subseg_e
->next
= sseg_map
;
9767 sseg_map
= subseg_e
;
9773 get_last_insn_flags (segT seg
, subsegT subseg
)
9775 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9777 return subseg_e
->flags
;
9783 set_last_insn_flags (segT seg
,
9788 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9790 subseg_e
= add_subseg_info (seg
, subseg
);
9792 subseg_e
->flags
|= fl
;
9794 subseg_e
->flags
&= ~fl
;
9799 get_subseg_total_freq (segT seg
, subsegT subseg
)
9801 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9803 return subseg_e
->total_freq
;
9809 get_subseg_target_freq (segT seg
, subsegT subseg
)
9811 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9813 return subseg_e
->target_freq
;
9819 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9821 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9823 subseg_e
= add_subseg_info (seg
, subseg
);
9824 subseg_e
->total_freq
= total_f
;
9825 subseg_e
->target_freq
= target_f
;
9829 /* Segment Lists and emit_state Stuff. */
9831 /* Remove the segment from the global sections list. */
9834 xtensa_remove_section (segT sec
)
9836 /* Handle brain-dead bfd_section_list_remove macro, which
9837 expect the address of the prior section's "next" field, not
9838 just the address of the section to remove. */
9840 segT
*ps_next_ptr
= &stdoutput
->sections
;
9841 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
9842 ps_next_ptr
= &(*ps_next_ptr
)->next
;
9844 assert (*ps_next_ptr
!= NULL
);
9846 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
9851 xtensa_insert_section (segT after_sec
, segT sec
)
9853 segT
*after_sec_next
;
9854 if (after_sec
== NULL
)
9855 after_sec_next
= &stdoutput
->sections
;
9857 after_sec_next
= &after_sec
->next
;
9859 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
9864 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9869 segT literal_section
= head
->seg
;
9871 /* Move the literal section to the front of the section list. */
9872 assert (literal_section
);
9873 xtensa_remove_section (literal_section
);
9874 xtensa_insert_section (NULL
, literal_section
);
9881 static void mark_literal_frags (seg_list
*);
9884 xtensa_move_literals (void)
9887 frchainS
*frchain_from
, *frchain_to
;
9888 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9889 fragS
**frag_splice
;
9892 fixS
*fix
, *next_fix
, **fix_splice
;
9895 mark_literal_frags (literal_head
->next
);
9896 mark_literal_frags (init_literal_head
->next
);
9897 mark_literal_frags (fini_literal_head
->next
);
9899 if (use_literal_section
)
9902 segment
= literal_head
->next
;
9905 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9906 search_frag
= frchain_from
->frch_root
;
9907 literal_pool
= NULL
;
9909 frag_splice
= &(frchain_from
->frch_root
);
9911 while (!search_frag
->tc_frag_data
.literal_frag
)
9913 assert (search_frag
->fr_fix
== 0
9914 || search_frag
->fr_type
== rs_align
);
9915 search_frag
= search_frag
->fr_next
;
9918 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9919 == RELAX_LITERAL_POOL_BEGIN
);
9920 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9922 /* Make sure that all the frags in this series are closed, and
9923 that there is at least one left over of zero-size. This
9924 prevents us from making a segment with an frchain without any
9926 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9927 xtensa_set_frag_assembly_state (frag_now
);
9928 last_frag
= frag_now
;
9929 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9930 xtensa_set_frag_assembly_state (frag_now
);
9932 while (search_frag
!= frag_now
)
9934 next_frag
= search_frag
->fr_next
;
9936 /* First, move the frag out of the literal section and
9937 to the appropriate place. */
9938 if (search_frag
->tc_frag_data
.literal_frag
)
9940 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9941 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9942 /* Note that we set this fr_var to be a fix
9943 chain when we created the literal pool location
9944 as RELAX_LITERAL_POOL_BEGIN. */
9945 frchain_to
= (frchainS
*) literal_pool
->fr_var
;
9947 insert_after
= literal_pool
;
9949 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9950 insert_after
= insert_after
->fr_next
;
9952 dest_seg
= (segT
) insert_after
->fr_next
->fr_var
;
9954 *frag_splice
= next_frag
;
9955 search_frag
->fr_next
= insert_after
->fr_next
;
9956 insert_after
->fr_next
= search_frag
;
9957 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9959 /* Now move any fixups associated with this frag to the
9961 fix
= frchain_from
->fix_root
;
9962 fix_splice
= &(frchain_from
->fix_root
);
9965 next_fix
= fix
->fx_next
;
9966 if (fix
->fx_frag
== search_frag
)
9968 *fix_splice
= next_fix
;
9969 fix
->fx_next
= frchain_to
->fix_root
;
9970 frchain_to
->fix_root
= fix
;
9971 if (frchain_to
->fix_tail
== NULL
)
9972 frchain_to
->fix_tail
= fix
;
9975 fix_splice
= &(fix
->fx_next
);
9978 search_frag
= next_frag
;
9981 if (frchain_from
->fix_root
!= NULL
)
9983 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9984 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9986 assert (frchain_from
->fix_root
== NULL
);
9988 frchain_from
->fix_tail
= NULL
;
9989 xtensa_restore_emit_state (&state
);
9990 segment
= segment
->next
;
9993 /* Now fix up the SEGMENT value for all the literal symbols. */
9994 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9996 symbolS
*lit_sym
= lit
->sym
;
9997 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9999 S_SET_SEGMENT (lit_sym
, dest_seg
);
10004 /* Walk over all the frags for segments in a list and mark them as
10005 containing literals. As clunky as this is, we can't rely on frag_var
10006 and frag_variant to get called in all situations. */
10009 mark_literal_frags (seg_list
*segment
)
10011 frchainS
*frchain_from
;
10012 fragS
*search_frag
;
10016 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10017 search_frag
= frchain_from
->frch_root
;
10018 while (search_frag
)
10020 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10021 search_frag
= search_frag
->fr_next
;
10023 segment
= segment
->next
;
10029 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10031 /* Move all of the sections in the section list to come
10032 after "after" in the gnu segment list. */
10037 segT literal_section
= head
->seg
;
10039 /* Move the literal section after "after". */
10040 assert (literal_section
);
10041 if (literal_section
!= after
)
10043 xtensa_remove_section (literal_section
);
10044 xtensa_insert_section (after
, literal_section
);
10052 /* Push all the literal segments to the end of the gnu list. */
10055 xtensa_reorder_segments (void)
10062 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10068 /* Now that we have the last section, push all the literal
10069 sections to the end. */
10070 xtensa_reorder_seg_list (literal_head
, last_sec
);
10071 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
10072 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
10074 /* Now perform the final error check. */
10075 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10077 assert (new_count
== old_count
);
10081 /* Change the emit state (seg, subseg, and frag related stuff) to the
10082 correct location. Return a emit_state which can be passed to
10083 xtensa_restore_emit_state to return to current fragment. */
10086 xtensa_switch_to_literal_fragment (emit_state
*result
)
10088 if (directive_state
[directive_absolute_literals
])
10090 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
10091 &default_lit_sections
.lit4_seg
, FALSE
);
10092 xtensa_switch_section_emit_state (result
,
10093 default_lit_sections
.lit4_seg
, 0);
10096 xtensa_switch_to_non_abs_literal_fragment (result
);
10098 /* Do a 4-byte align here. */
10099 frag_align (2, 0, 0);
10100 record_alignment (now_seg
, 2);
10105 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10107 /* When we mark a literal pool location, we want to put a frag in
10108 the literal pool that points to it. But to do that, we want to
10109 switch_to_literal_fragment. But literal sections don't have
10110 literal pools, so their location is always null, so we would
10111 recurse forever. This is kind of hacky, but it works. */
10113 static bfd_boolean recursive
= FALSE
;
10114 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10115 bfd_boolean is_init
=
10116 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10118 bfd_boolean is_fini
=
10119 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10121 if (pool_location
== NULL
10122 && !use_literal_section
10124 && !is_init
&& ! is_fini
)
10126 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10128 xtensa_mark_literal_pool_location ();
10132 /* Special case: If we are in the ".fini" or ".init" section, then
10133 we will ALWAYS be generating to the ".fini.literal" and
10134 ".init.literal" sections. */
10138 cache_literal_section (init_literal_head
,
10139 default_lit_sections
.init_lit_seg_name
,
10140 &default_lit_sections
.init_lit_seg
, TRUE
);
10141 xtensa_switch_section_emit_state (result
,
10142 default_lit_sections
.init_lit_seg
, 0);
10146 cache_literal_section (fini_literal_head
,
10147 default_lit_sections
.fini_lit_seg_name
,
10148 &default_lit_sections
.fini_lit_seg
, TRUE
);
10149 xtensa_switch_section_emit_state (result
,
10150 default_lit_sections
.fini_lit_seg
, 0);
10154 cache_literal_section (literal_head
,
10155 default_lit_sections
.lit_seg_name
,
10156 &default_lit_sections
.lit_seg
, TRUE
);
10157 xtensa_switch_section_emit_state (result
,
10158 default_lit_sections
.lit_seg
, 0);
10161 if (!use_literal_section
10162 && !is_init
&& !is_fini
10163 && get_literal_pool_location (now_seg
) != pool_location
)
10165 /* Close whatever frag is there. */
10166 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10167 xtensa_set_frag_assembly_state (frag_now
);
10168 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10169 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10170 xtensa_set_frag_assembly_state (frag_now
);
10175 /* Call this function before emitting data into the literal section.
10176 This is a helper function for xtensa_switch_to_literal_fragment.
10177 This is similar to a .section new_now_seg subseg. */
10180 xtensa_switch_section_emit_state (emit_state
*state
,
10182 subsegT new_now_subseg
)
10184 state
->name
= now_seg
->name
;
10185 state
->now_seg
= now_seg
;
10186 state
->now_subseg
= now_subseg
;
10187 state
->generating_literals
= generating_literals
;
10188 generating_literals
++;
10189 subseg_set (new_now_seg
, new_now_subseg
);
10193 /* Use to restore the emitting into the normal place. */
10196 xtensa_restore_emit_state (emit_state
*state
)
10198 generating_literals
= state
->generating_literals
;
10199 subseg_set (state
->now_seg
, state
->now_subseg
);
10203 /* Get a segment of a given name. If the segment is already
10204 present, return it; otherwise, create a new one. */
10207 cache_literal_section (seg_list
*head
,
10210 bfd_boolean is_code
)
10212 segT current_section
= now_seg
;
10213 int current_subsec
= now_subseg
;
10219 /* Check if the named section exists. */
10220 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10222 if (!strcmp (segment_name (seg
), name
))
10228 /* Create a new literal section. */
10229 seg
= subseg_new (name
, (subsegT
) 0);
10232 /* Add the newly created literal segment to the specified list. */
10233 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10235 n
->next
= head
->next
;
10238 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10239 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10240 | (is_code
? SEC_CODE
: SEC_DATA
));
10241 bfd_set_section_alignment (stdoutput
, seg
, 2);
10245 subseg_set (current_section
, current_subsec
);
10249 /* Property Tables Stuff. */
10251 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10252 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10253 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10255 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10256 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10258 static bfd_boolean
get_frag_is_literal (const fragS
*);
10259 static void xtensa_create_property_segments
10260 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10261 static void xtensa_create_xproperty_segments
10262 (frag_flags_fn
, const char *, xt_section_type
);
10263 static segment_info_type
*retrieve_segment_info (segT
);
10264 static segT
retrieve_xtensa_section (char *);
10265 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10266 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10267 static void add_xt_block_frags
10268 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10269 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10270 static void xtensa_frag_flags_init (frag_flags
*);
10271 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10272 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10273 static void add_xt_prop_frags
10274 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10276 /* Set up property tables after relaxation. */
10279 xtensa_post_relax_hook (void)
10281 xtensa_move_seg_list_to_beginning (literal_head
);
10282 xtensa_move_seg_list_to_beginning (init_literal_head
);
10283 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10285 xtensa_find_unmarked_state_frags ();
10287 if (use_literal_section
)
10288 xtensa_create_property_segments (get_frag_is_literal
,
10290 XTENSA_LIT_SEC_NAME
,
10292 xtensa_create_xproperty_segments (get_frag_property_flags
,
10293 XTENSA_PROP_SEC_NAME
,
10296 if (warn_unaligned_branch_targets
)
10297 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10298 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10302 /* This function is only meaningful after xtensa_move_literals. */
10305 get_frag_is_literal (const fragS
*fragP
)
10307 assert (fragP
!= NULL
);
10308 return fragP
->tc_frag_data
.is_literal
;
10313 xtensa_create_property_segments (frag_predicate property_function
,
10314 frag_predicate end_property_function
,
10315 const char *section_name_base
,
10316 xt_section_type sec_type
)
10320 /* Walk over all of the current segments.
10321 Walk over each fragment
10322 For each non-empty fragment,
10323 Build a property record (append where possible). */
10325 for (seclist
= &stdoutput
->sections
;
10326 seclist
&& *seclist
;
10327 seclist
= &(*seclist
)->next
)
10329 segT sec
= *seclist
;
10332 flags
= bfd_get_section_flags (stdoutput
, sec
);
10333 if (flags
& SEC_DEBUGGING
)
10335 if (!(flags
& SEC_ALLOC
))
10338 if (section_has_property (sec
, property_function
))
10340 char *property_section_name
=
10341 xtensa_get_property_section_name (sec
, section_name_base
);
10342 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10343 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10344 xtensa_block_info
**xt_blocks
=
10345 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10346 /* Walk over all of the frchains here and add new sections. */
10347 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10348 end_property_function
);
10352 /* Now we fill them out.... */
10354 for (seclist
= &stdoutput
->sections
;
10355 seclist
&& *seclist
;
10356 seclist
= &(*seclist
)->next
)
10358 segment_info_type
*seginfo
;
10359 xtensa_block_info
*block
;
10360 segT sec
= *seclist
;
10362 seginfo
= seg_info (sec
);
10363 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10367 xtensa_block_info
*cur_block
;
10368 /* This is a section with some data. */
10372 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10375 rec_size
= num_recs
* 8;
10376 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10378 /* In order to make this work with the assembler, we have to
10379 build some frags and then build the "fixups" for it. It
10380 would be easier to just set the contents then set the
10385 /* Allocate a fragment and leak it. */
10389 frchainS
*frchainP
;
10393 frag_size
= sizeof (fragS
) + rec_size
;
10394 fragP
= (fragS
*) xmalloc (frag_size
);
10396 memset (fragP
, 0, frag_size
);
10397 fragP
->fr_address
= 0;
10398 fragP
->fr_next
= NULL
;
10399 fragP
->fr_fix
= rec_size
;
10401 fragP
->fr_type
= rs_fill
;
10402 /* The rest are zeros. */
10404 frchainP
= seginfo
->frchainP
;
10405 frchainP
->frch_root
= fragP
;
10406 frchainP
->frch_last
= fragP
;
10408 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10409 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10411 seginfo
->fix_root
= fixes
;
10412 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10414 frag_data
= &fragP
->fr_literal
[0];
10415 for (i
= 0; i
< num_recs
; i
++)
10417 fixS
*fix
= &fixes
[i
];
10418 assert (cur_block
);
10420 /* Write the fixup. */
10421 if (i
!= num_recs
- 1)
10422 fix
->fx_next
= &fixes
[i
+ 1];
10424 fix
->fx_next
= NULL
;
10427 fix
->fx_frag
= fragP
;
10428 fix
->fx_where
= i
* 8;
10429 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10430 fix
->fx_offset
= cur_block
->offset
;
10431 fix
->fx_r_type
= BFD_RELOC_32
;
10432 fix
->fx_file
= "Internal Assembly";
10435 /* Write the length. */
10436 md_number_to_chars (&frag_data
[4 + 8 * i
],
10437 cur_block
->size
, 4);
10438 cur_block
= cur_block
->next
;
10447 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10448 const char *section_name_base
,
10449 xt_section_type sec_type
)
10453 /* Walk over all of the current segments.
10454 Walk over each fragment.
10455 For each fragment that has instructions,
10456 build an instruction record (append where possible). */
10458 for (seclist
= &stdoutput
->sections
;
10459 seclist
&& *seclist
;
10460 seclist
= &(*seclist
)->next
)
10462 segT sec
= *seclist
;
10465 flags
= bfd_get_section_flags (stdoutput
, sec
);
10466 if (flags
& SEC_DEBUGGING
)
10468 if (!(flags
& SEC_ALLOC
))
10471 if (section_has_xproperty (sec
, flag_fn
))
10473 char *property_section_name
=
10474 xtensa_get_property_section_name (sec
, section_name_base
);
10475 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10476 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10477 xtensa_block_info
**xt_blocks
=
10478 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10479 /* Walk over all of the frchains here and add new sections. */
10480 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10484 /* Now we fill them out.... */
10486 for (seclist
= &stdoutput
->sections
;
10487 seclist
&& *seclist
;
10488 seclist
= &(*seclist
)->next
)
10490 segment_info_type
*seginfo
;
10491 xtensa_block_info
*block
;
10492 segT sec
= *seclist
;
10494 seginfo
= seg_info (sec
);
10495 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10499 xtensa_block_info
*cur_block
;
10500 /* This is a section with some data. */
10504 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10507 rec_size
= num_recs
* (8 + 4);
10508 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10510 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10512 /* In order to make this work with the assembler, we have to build
10513 some frags then build the "fixups" for it. It would be easier to
10514 just set the contents then set the arlents. */
10518 /* Allocate a fragment and (unfortunately) leak it. */
10522 frchainS
*frchainP
;
10526 frag_size
= sizeof (fragS
) + rec_size
;
10527 fragP
= (fragS
*) xmalloc (frag_size
);
10529 memset (fragP
, 0, frag_size
);
10530 fragP
->fr_address
= 0;
10531 fragP
->fr_next
= NULL
;
10532 fragP
->fr_fix
= rec_size
;
10534 fragP
->fr_type
= rs_fill
;
10535 /* The rest are zeros. */
10537 frchainP
= seginfo
->frchainP
;
10538 frchainP
->frch_root
= fragP
;
10539 frchainP
->frch_last
= fragP
;
10541 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10542 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10544 seginfo
->fix_root
= fixes
;
10545 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10547 frag_data
= &fragP
->fr_literal
[0];
10548 for (i
= 0; i
< num_recs
; i
++)
10550 fixS
*fix
= &fixes
[i
];
10551 assert (cur_block
);
10553 /* Write the fixup. */
10554 if (i
!= num_recs
- 1)
10555 fix
->fx_next
= &fixes
[i
+ 1];
10557 fix
->fx_next
= NULL
;
10560 fix
->fx_frag
= fragP
;
10561 fix
->fx_where
= i
* (8 + 4);
10562 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10563 fix
->fx_offset
= cur_block
->offset
;
10564 fix
->fx_r_type
= BFD_RELOC_32
;
10565 fix
->fx_file
= "Internal Assembly";
10568 /* Write the length. */
10569 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10570 cur_block
->size
, 4);
10571 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10572 frag_flags_to_number (&cur_block
->flags
),
10574 cur_block
= cur_block
->next
;
10582 static segment_info_type
*
10583 retrieve_segment_info (segT seg
)
10585 segment_info_type
*seginfo
;
10586 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10589 frchainS
*frchainP
;
10591 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10592 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10593 seginfo
->fix_root
= NULL
;
10594 seginfo
->fix_tail
= NULL
;
10595 seginfo
->bfd_section
= seg
;
10597 /* We will not be dealing with these, only our special ones. */
10598 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10600 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10601 frchainP
->frch_root
= NULL
;
10602 frchainP
->frch_last
= NULL
;
10603 frchainP
->frch_next
= NULL
;
10604 frchainP
->frch_seg
= seg
;
10605 frchainP
->frch_subseg
= 0;
10606 frchainP
->fix_root
= NULL
;
10607 frchainP
->fix_tail
= NULL
;
10608 /* Do not init the objstack. */
10609 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10610 /* frchainP->frch_frag_now = fragP; */
10611 frchainP
->frch_frag_now
= NULL
;
10613 seginfo
->frchainP
= frchainP
;
10621 retrieve_xtensa_section (char *sec_name
)
10623 bfd
*abfd
= stdoutput
;
10624 flagword flags
, out_flags
, link_once_flags
;
10627 flags
= bfd_get_section_flags (abfd
, now_seg
);
10628 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10629 if (link_once_flags
)
10630 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10631 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10633 s
= bfd_make_section_old_way (abfd
, sec_name
);
10635 as_bad (_("could not create section %s"), sec_name
);
10636 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10637 as_bad (_("invalid flag combination on section %s"), sec_name
);
10644 section_has_property (segT sec
, frag_predicate property_function
)
10646 segment_info_type
*seginfo
= seg_info (sec
);
10649 if (seginfo
&& seginfo
->frchainP
)
10651 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10653 if (property_function (fragP
)
10654 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10663 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10665 segment_info_type
*seginfo
= seg_info (sec
);
10668 if (seginfo
&& seginfo
->frchainP
)
10670 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10672 frag_flags prop_flags
;
10673 property_function (fragP
, &prop_flags
);
10674 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10682 /* Two types of block sections exist right now: literal and insns. */
10685 add_xt_block_frags (segT sec
,
10687 xtensa_block_info
**xt_block
,
10688 frag_predicate property_function
,
10689 frag_predicate end_property_function
)
10691 segment_info_type
*seg_info
;
10692 segment_info_type
*xt_seg_info
;
10693 bfd_vma seg_offset
;
10696 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10697 seg_info
= retrieve_segment_info (sec
);
10699 /* Build it if needed. */
10700 while (*xt_block
!= NULL
)
10701 xt_block
= &(*xt_block
)->next
;
10702 /* We are either at NULL at the beginning or at the end. */
10704 /* Walk through the frags. */
10707 if (seg_info
->frchainP
)
10709 for (fragP
= seg_info
->frchainP
->frch_root
;
10711 fragP
= fragP
->fr_next
)
10713 if (property_function (fragP
)
10714 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10716 if (*xt_block
!= NULL
)
10718 if ((*xt_block
)->offset
+ (*xt_block
)->size
10719 == fragP
->fr_address
)
10720 (*xt_block
)->size
+= fragP
->fr_fix
;
10722 xt_block
= &((*xt_block
)->next
);
10724 if (*xt_block
== NULL
)
10726 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10727 xmalloc (sizeof (xtensa_block_info
));
10728 new_block
->sec
= sec
;
10729 new_block
->offset
= fragP
->fr_address
;
10730 new_block
->size
= fragP
->fr_fix
;
10731 new_block
->next
= NULL
;
10732 xtensa_frag_flags_init (&new_block
->flags
);
10733 *xt_block
= new_block
;
10735 if (end_property_function
10736 && end_property_function (fragP
))
10738 xt_block
= &((*xt_block
)->next
);
10746 /* Break the encapsulation of add_xt_prop_frags here. */
10749 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10751 if (prop_flags
->is_literal
10752 || prop_flags
->is_insn
10753 || prop_flags
->is_data
10754 || prop_flags
->is_unreachable
)
10761 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10763 memset (prop_flags
, 0, sizeof (frag_flags
));
10768 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10770 xtensa_frag_flags_init (prop_flags
);
10771 if (fragP
->tc_frag_data
.is_literal
)
10772 prop_flags
->is_literal
= TRUE
;
10773 if (fragP
->tc_frag_data
.is_unreachable
)
10774 prop_flags
->is_unreachable
= TRUE
;
10775 else if (fragP
->tc_frag_data
.is_insn
)
10777 prop_flags
->is_insn
= TRUE
;
10778 if (fragP
->tc_frag_data
.is_loop_target
)
10779 prop_flags
->insn
.is_loop_target
= TRUE
;
10780 if (fragP
->tc_frag_data
.is_branch_target
)
10781 prop_flags
->insn
.is_branch_target
= TRUE
;
10782 if (fragP
->tc_frag_data
.is_specific_opcode
10783 || fragP
->tc_frag_data
.is_no_transform
)
10784 prop_flags
->insn
.is_no_transform
= TRUE
;
10785 if (fragP
->tc_frag_data
.is_no_density
)
10786 prop_flags
->insn
.is_no_density
= TRUE
;
10787 if (fragP
->tc_frag_data
.use_absolute_literals
)
10788 prop_flags
->insn
.is_abslit
= TRUE
;
10790 if (fragP
->tc_frag_data
.is_align
)
10792 prop_flags
->is_align
= TRUE
;
10793 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10794 if (xtensa_frag_flags_is_empty (prop_flags
))
10795 prop_flags
->is_data
= TRUE
;
10801 frag_flags_to_number (const frag_flags
*prop_flags
)
10804 if (prop_flags
->is_literal
)
10805 num
|= XTENSA_PROP_LITERAL
;
10806 if (prop_flags
->is_insn
)
10807 num
|= XTENSA_PROP_INSN
;
10808 if (prop_flags
->is_data
)
10809 num
|= XTENSA_PROP_DATA
;
10810 if (prop_flags
->is_unreachable
)
10811 num
|= XTENSA_PROP_UNREACHABLE
;
10812 if (prop_flags
->insn
.is_loop_target
)
10813 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10814 if (prop_flags
->insn
.is_branch_target
)
10816 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10817 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10820 if (prop_flags
->insn
.is_no_density
)
10821 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10822 if (prop_flags
->insn
.is_no_transform
)
10823 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10824 if (prop_flags
->insn
.is_no_reorder
)
10825 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10826 if (prop_flags
->insn
.is_abslit
)
10827 num
|= XTENSA_PROP_INSN_ABSLIT
;
10829 if (prop_flags
->is_align
)
10831 num
|= XTENSA_PROP_ALIGN
;
10832 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10840 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10841 const frag_flags
*prop_flags_2
)
10843 /* Cannot combine with an end marker. */
10845 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10847 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10849 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10852 if (prop_flags_1
->is_insn
)
10854 /* Properties of the beginning of the frag. */
10855 if (prop_flags_2
->insn
.is_loop_target
)
10857 if (prop_flags_2
->insn
.is_branch_target
)
10859 if (prop_flags_1
->insn
.is_no_density
!=
10860 prop_flags_2
->insn
.is_no_density
)
10862 if (prop_flags_1
->insn
.is_no_transform
!=
10863 prop_flags_2
->insn
.is_no_transform
)
10865 if (prop_flags_1
->insn
.is_no_reorder
!=
10866 prop_flags_2
->insn
.is_no_reorder
)
10868 if (prop_flags_1
->insn
.is_abslit
!=
10869 prop_flags_2
->insn
.is_abslit
)
10873 if (prop_flags_1
->is_align
)
10881 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10886 if (!xt_block
->flags
.is_align
)
10887 return xt_block
->size
;
10889 end_addr
= xt_block
->offset
+ xt_block
->size
;
10890 align_bits
= xt_block
->flags
.alignment
;
10891 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10892 return end_addr
- xt_block
->offset
;
10897 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10898 const xtensa_block_info
*xt_block_2
)
10900 if (xt_block
->sec
!= xt_block_2
->sec
)
10902 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10903 != xt_block_2
->offset
)
10906 if (xt_block_2
->size
== 0
10907 && (!xt_block_2
->flags
.is_unreachable
10908 || xt_block
->flags
.is_unreachable
))
10910 if (xt_block_2
->flags
.is_align
10911 && xt_block
->flags
.is_align
)
10913 /* Nothing needed. */
10914 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10919 if (xt_block_2
->flags
.is_align
)
10921 /* Push alignment to previous entry. */
10922 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10923 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10928 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10929 &xt_block_2
->flags
))
10932 xt_block
->size
+= xt_block_2
->size
;
10934 if (xt_block_2
->flags
.is_align
)
10936 xt_block
->flags
.is_align
= TRUE
;
10937 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10945 add_xt_prop_frags (segT sec
,
10947 xtensa_block_info
**xt_block
,
10948 frag_flags_fn property_function
)
10950 segment_info_type
*seg_info
;
10951 segment_info_type
*xt_seg_info
;
10952 bfd_vma seg_offset
;
10955 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10956 seg_info
= retrieve_segment_info (sec
);
10957 /* Build it if needed. */
10958 while (*xt_block
!= NULL
)
10960 xt_block
= &(*xt_block
)->next
;
10962 /* We are either at NULL at the beginning or at the end. */
10964 /* Walk through the frags. */
10967 if (seg_info
->frchainP
)
10969 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10970 fragP
= fragP
->fr_next
)
10972 xtensa_block_info tmp_block
;
10973 tmp_block
.sec
= sec
;
10974 tmp_block
.offset
= fragP
->fr_address
;
10975 tmp_block
.size
= fragP
->fr_fix
;
10976 tmp_block
.next
= NULL
;
10977 property_function (fragP
, &tmp_block
.flags
);
10979 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10980 /* && fragP->fr_fix != 0) */
10982 if ((*xt_block
) == NULL
10983 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10985 xtensa_block_info
*new_block
;
10986 if ((*xt_block
) != NULL
)
10987 xt_block
= &(*xt_block
)->next
;
10988 new_block
= (xtensa_block_info
*)
10989 xmalloc (sizeof (xtensa_block_info
));
10990 *new_block
= tmp_block
;
10991 *xt_block
= new_block
;
10999 /* op_placement_info_table */
11001 /* op_placement_info makes it easier to determine which
11002 ops can go in which slots. */
11005 init_op_placement_info_table (void)
11007 xtensa_isa isa
= xtensa_default_isa
;
11008 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11009 xtensa_opcode opcode
;
11012 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11014 op_placement_table
= (op_placement_info_table
)
11015 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11016 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11018 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11020 op_placement_info
*opi
= &op_placement_table
[opcode
];
11021 /* FIXME: Make tinsn allocation dynamic. */
11022 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
11023 as_fatal (_("too many operands in instruction"));
11024 opi
->single
= XTENSA_UNDEFINED
;
11025 opi
->single_size
= 0;
11026 opi
->widest
= XTENSA_UNDEFINED
;
11027 opi
->widest_size
= 0;
11028 opi
->narrowest
= XTENSA_UNDEFINED
;
11029 opi
->narrowest_size
= 0x7F;
11031 opi
->num_formats
= 0;
11033 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11035 opi
->slots
[fmt
] = 0;
11036 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11038 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11040 int fmt_length
= xtensa_format_length (isa
, fmt
);
11042 set_bit (fmt
, opi
->formats
);
11043 set_bit (slot
, opi
->slots
[fmt
]);
11044 /* opi->slot_count[fmt]++; */
11045 if (fmt_length
< opi
->narrowest_size
)
11047 opi
->narrowest
= fmt
;
11048 opi
->narrowest_size
= fmt_length
;
11050 if (fmt_length
> opi
->widest_size
)
11053 opi
->widest_size
= fmt_length
;
11055 if (xtensa_format_num_slots (isa
, fmt
) == 1)
11057 if (opi
->single_size
== 0
11058 || fmt_length
< opi
->single_size
)
11061 opi
->single_size
= fmt_length
;
11067 opi
->num_formats
++;
11070 xtensa_insnbuf_free (isa
, ibuf
);
11075 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11077 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11081 /* If the opcode is available in a single slot format, return its size. */
11084 xg_get_single_size (xtensa_opcode opcode
)
11086 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
11087 return op_placement_table
[opcode
].single_size
;
11091 static xtensa_format
11092 xg_get_single_format (xtensa_opcode opcode
)
11094 return op_placement_table
[opcode
].single
;
11098 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11101 istack_init (IStack
*stack
)
11103 memset (stack
, 0, sizeof (IStack
));
11109 istack_empty (IStack
*stack
)
11111 return (stack
->ninsn
== 0);
11116 istack_full (IStack
*stack
)
11118 return (stack
->ninsn
== MAX_ISTACK
);
11122 /* Return a pointer to the top IStack entry.
11123 It is an error to call this if istack_empty () is TRUE. */
11126 istack_top (IStack
*stack
)
11128 int rec
= stack
->ninsn
- 1;
11129 assert (!istack_empty (stack
));
11130 return &stack
->insn
[rec
];
11134 /* Add a new TInsn to an IStack.
11135 It is an error to call this if istack_full () is TRUE. */
11138 istack_push (IStack
*stack
, TInsn
*insn
)
11140 int rec
= stack
->ninsn
;
11141 assert (!istack_full (stack
));
11142 stack
->insn
[rec
] = *insn
;
11147 /* Clear space for the next TInsn on the IStack and return a pointer
11148 to it. It is an error to call this if istack_full () is TRUE. */
11151 istack_push_space (IStack
*stack
)
11153 int rec
= stack
->ninsn
;
11155 assert (!istack_full (stack
));
11156 insn
= &stack
->insn
[rec
];
11157 memset (insn
, 0, sizeof (TInsn
));
11163 /* Remove the last pushed instruction. It is an error to call this if
11164 istack_empty () returns TRUE. */
11167 istack_pop (IStack
*stack
)
11169 int rec
= stack
->ninsn
- 1;
11170 assert (!istack_empty (stack
));
11172 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11176 /* TInsn functions. */
11179 tinsn_init (TInsn
*dst
)
11181 memset (dst
, 0, sizeof (TInsn
));
11185 /* Get the ``num''th token of the TInsn.
11186 It is illegal to call this if num > insn->ntoks. */
11189 tinsn_get_tok (TInsn
*insn
, int num
)
11191 assert (num
< insn
->ntok
);
11192 return &insn
->tok
[num
];
11196 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11199 tinsn_has_symbolic_operands (const TInsn
*insn
)
11202 int n
= insn
->ntok
;
11204 assert (insn
->insn_type
== ITYPE_INSN
);
11206 for (i
= 0; i
< n
; ++i
)
11208 switch (insn
->tok
[i
].X_op
)
11222 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11224 xtensa_isa isa
= xtensa_default_isa
;
11226 int n
= insn
->ntok
;
11228 assert (insn
->insn_type
== ITYPE_INSN
);
11230 for (i
= 0; i
< n
; ++i
)
11232 switch (insn
->tok
[i
].X_op
)
11240 /* Errors for these types are caught later. */
11245 /* Symbolic immediates are only allowed on the last immediate
11246 operand. At this time, CONST16 is the only opcode where we
11247 support non-PC-relative relocations. (It isn't necessary
11248 to complain about non-PC-relative relocations here, but
11249 otherwise, no error is reported until the relocations are
11250 generated, and the assembler won't get that far if there
11251 are any other errors. It's nice to see all the problems
11253 if (i
!= get_relaxable_immed (insn
->opcode
)
11254 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11255 && insn
->opcode
!= xtensa_const16_opcode
))
11257 as_bad (_("invalid symbolic operand %d on '%s'"),
11258 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11267 /* For assembly code with complex expressions (e.g. subtraction),
11268 we have to build them in the literal pool so that
11269 their results are calculated correctly after relaxation.
11270 The relaxation only handles expressions that
11271 boil down to SYMBOL + OFFSET. */
11274 tinsn_has_complex_operands (const TInsn
*insn
)
11277 int n
= insn
->ntok
;
11278 assert (insn
->insn_type
== ITYPE_INSN
);
11279 for (i
= 0; i
< n
; ++i
)
11281 switch (insn
->tok
[i
].X_op
)
11297 /* Convert the constant operands in the tinsn to insnbuf.
11298 Return TRUE if there is a symbol in the immediate field.
11300 Before this is called,
11301 1) the number of operands are correct
11302 2) the tinsn is a ITYPE_INSN
11303 3) ONLY the relaxable_ is built
11304 4) All operands are O_constant, O_symbol. All constants fit
11305 The return value tells whether there are any remaining O_symbols. */
11308 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11310 static xtensa_insnbuf slotbuf
= 0;
11311 xtensa_isa isa
= xtensa_default_isa
;
11312 xtensa_opcode opcode
= tinsn
->opcode
;
11313 xtensa_format fmt
= xg_get_single_format (opcode
);
11314 bfd_boolean has_fixup
= FALSE
;
11315 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11322 slotbuf
= xtensa_insnbuf_alloc (isa
);
11324 assert (tinsn
->insn_type
== ITYPE_INSN
);
11325 if (noperands
!= tinsn
->ntok
)
11326 as_fatal (_("operand number mismatch"));
11328 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11329 as_fatal (_("cannot encode opcode"));
11331 for (i
= 0; i
< noperands
; ++i
)
11333 expressionS
*expr
= &tinsn
->tok
[i
];
11334 switch (expr
->X_op
)
11337 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11339 /* The register number has already been checked in
11340 expression_maybe_register, so we don't need to check here. */
11341 opnd_value
= expr
->X_add_number
;
11342 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11343 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11344 slotbuf
, opnd_value
);
11348 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11350 as_where (&file_name
, &line
);
11351 /* It is a constant and we called this function,
11352 then we have to try to fit it. */
11353 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11354 expr
->X_add_number
, file_name
, line
);
11363 xtensa_format_encode (isa
, fmt
, insnbuf
);
11364 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11370 /* Convert the constant operands in the tinsn to slotbuf.
11371 Return TRUE if there is a symbol in the immediate field.
11372 (Eventually this should replace tinsn_to_insnbuf.) */
11374 /* Before this is called,
11375 1) the number of operands are correct
11376 2) the tinsn is a ITYPE_INSN
11377 3) ONLY the relaxable_ is built
11378 4) All operands are
11379 O_constant, O_symbol
11382 The return value tells whether there are any remaining O_symbols. */
11385 tinsn_to_slotbuf (xtensa_format fmt
,
11388 xtensa_insnbuf slotbuf
)
11390 xtensa_isa isa
= xtensa_default_isa
;
11391 xtensa_opcode opcode
= tinsn
->opcode
;
11392 bfd_boolean has_fixup
= FALSE
;
11393 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11396 *((int *) &slotbuf
[0]) = 0;
11397 *((int *) &slotbuf
[1]) = 0;
11398 assert (tinsn
->insn_type
== ITYPE_INSN
);
11399 if (noperands
!= tinsn
->ntok
)
11400 as_fatal (_("operand number mismatch"));
11402 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11404 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11405 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11409 for (i
= 0; i
< noperands
; i
++)
11411 expressionS
*expr
= &tinsn
->tok
[i
];
11416 switch (expr
->X_op
)
11419 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11421 /* The register number has already been checked in
11422 expression_maybe_register, so we don't need to check here. */
11423 opnd_value
= expr
->X_add_number
;
11424 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11425 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11428 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11432 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11434 as_where (&file_name
, &line
);
11435 /* It is a constant and we called this function
11436 then we have to try to fit it. */
11437 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11438 expr
->X_add_number
, file_name
, line
);
11451 /* Check the instruction arguments. Return TRUE on failure. */
11454 tinsn_check_arguments (const TInsn
*insn
)
11456 xtensa_isa isa
= xtensa_default_isa
;
11457 xtensa_opcode opcode
= insn
->opcode
;
11459 if (opcode
== XTENSA_UNDEFINED
)
11461 as_bad (_("invalid opcode"));
11465 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11467 as_bad (_("too few operands"));
11471 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11473 as_bad (_("too many operands"));
11480 /* Load an instruction from its encoded form. */
11483 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11487 xg_init_vinsn (&vinsn
);
11488 vinsn_from_chars (&vinsn
, f
);
11490 *tinsn
= vinsn
.slots
[slot
];
11491 xg_free_vinsn (&vinsn
);
11496 tinsn_from_insnbuf (TInsn
*tinsn
,
11497 xtensa_insnbuf slotbuf
,
11502 xtensa_isa isa
= xtensa_default_isa
;
11504 /* Find the immed. */
11505 tinsn_init (tinsn
);
11506 tinsn
->insn_type
= ITYPE_INSN
;
11507 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11508 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11509 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11510 for (i
= 0; i
< tinsn
->ntok
; i
++)
11512 set_expr_const (&tinsn
->tok
[i
],
11513 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11514 tinsn
->opcode
, i
));
11519 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11522 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11524 xtensa_opcode opcode
= tinsn
->opcode
;
11527 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11529 opnum
= get_relaxable_immed (opcode
);
11530 assert (opnum
>= 0);
11531 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11533 set_expr_symbol_offset_diff
11534 (&tinsn
->tok
[opnum
],
11535 fragP
->tc_frag_data
.slot_symbols
[slot
],
11536 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11537 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11541 set_expr_symbol_offset
11542 (&tinsn
->tok
[opnum
],
11543 fragP
->tc_frag_data
.slot_symbols
[slot
],
11544 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11551 get_num_stack_text_bytes (IStack
*istack
)
11554 int text_bytes
= 0;
11556 for (i
= 0; i
< istack
->ninsn
; i
++)
11558 TInsn
*tinsn
= &istack
->insn
[i
];
11559 if (tinsn
->insn_type
== ITYPE_INSN
)
11560 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11567 get_num_stack_literal_bytes (IStack
*istack
)
11572 for (i
= 0; i
< istack
->ninsn
; i
++)
11574 TInsn
*tinsn
= &istack
->insn
[i
];
11575 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11582 /* vliw_insn functions. */
11585 xg_init_vinsn (vliw_insn
*v
)
11588 xtensa_isa isa
= xtensa_default_isa
;
11590 xg_clear_vinsn (v
);
11592 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11593 if (v
->insnbuf
== NULL
)
11594 as_fatal (_("out of memory"));
11596 for (i
= 0; i
< MAX_SLOTS
; i
++)
11598 tinsn_init (&v
->slots
[i
]);
11599 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11600 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11601 if (v
->slotbuf
[i
] == NULL
)
11602 as_fatal (_("out of memory"));
11608 xg_clear_vinsn (vliw_insn
*v
)
11611 v
->format
= XTENSA_UNDEFINED
;
11613 v
->inside_bundle
= FALSE
;
11615 if (xt_saved_debug_type
!= DEBUG_NONE
)
11616 debug_type
= xt_saved_debug_type
;
11618 for (i
= 0; i
< MAX_SLOTS
; i
++)
11620 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11621 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11627 vinsn_has_specific_opcodes (vliw_insn
*v
)
11631 for (i
= 0; i
< v
->num_slots
; i
++)
11633 if (v
->slots
[i
].is_specific_opcode
)
11641 xg_free_vinsn (vliw_insn
*v
)
11644 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11645 for (i
= 0; i
< MAX_SLOTS
; i
++)
11646 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11650 /* Before this is called, we should have
11651 filled out the following fields:
11653 1) the number of operands for each opcode are correct
11654 2) the tinsn in the slots are ITYPE_INSN
11655 3) ONLY the relaxable_ is built
11656 4) All operands are
11657 O_constant, O_symbol
11660 The return value tells whether there are any remaining O_symbols. */
11663 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11666 bfd_boolean record_fixup
)
11668 xtensa_isa isa
= xtensa_default_isa
;
11669 xtensa_format fmt
= vinsn
->format
;
11670 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11672 bfd_boolean has_fixup
= FALSE
;
11674 xtensa_format_encode (isa
, fmt
, insnbuf
);
11676 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11678 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11679 bfd_boolean tinsn_has_fixup
=
11680 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11681 vinsn
->slotbuf
[slot
]);
11683 xtensa_format_set_slot (isa
, fmt
, slot
,
11684 insnbuf
, vinsn
->slotbuf
[slot
]);
11685 /* tinsn_has_fixup tracks if there is a fixup at all.
11686 record_fixup controls globally. I.E., we use this
11687 function from several places, some of which are after
11688 fixups have already been recorded. Finally,
11689 tinsn->record_fixup controls based on the individual ops,
11690 which may or may not need it based on the relaxation
11692 if (tinsn_has_fixup
&& record_fixup
)
11695 xtensa_opcode opcode
= tinsn
->opcode
;
11696 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11699 for (i
= 0; i
< noperands
; i
++)
11701 expressionS
* expr
= &tinsn
->tok
[i
];
11702 switch (expr
->X_op
)
11707 if (get_relaxable_immed (opcode
) == i
)
11709 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11711 if (!xg_add_opcode_fix
11712 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11713 frag_offset
- fragP
->fr_literal
))
11714 as_bad (_("instruction with constant operands does not fit"));
11718 tinsn
->symbol
= expr
->X_add_symbol
;
11719 tinsn
->offset
= expr
->X_add_number
;
11723 as_bad (_("invalid operand %d on '%s'"),
11724 i
, xtensa_opcode_name (isa
, opcode
));
11732 if (get_relaxable_immed (opcode
) == i
)
11734 if (tinsn
->record_fix
)
11735 as_bad (_("invalid subtract operand"));
11738 tinsn
->symbol
= expr
->X_add_symbol
;
11739 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11740 tinsn
->offset
= expr
->X_add_number
;
11744 as_bad (_("invalid operand %d on '%s'"),
11745 i
, xtensa_opcode_name (isa
, opcode
));
11749 as_bad (_("invalid expression for operand %d on '%s'"),
11750 i
, xtensa_opcode_name (isa
, opcode
));
11762 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11764 static xtensa_insnbuf insnbuf
= NULL
;
11765 static xtensa_insnbuf slotbuf
= NULL
;
11768 xtensa_isa isa
= xtensa_default_isa
;
11772 insnbuf
= xtensa_insnbuf_alloc (isa
);
11773 slotbuf
= xtensa_insnbuf_alloc (isa
);
11776 xtensa_insnbuf_from_chars (isa
, insnbuf
, f
, 0);
11777 fmt
= xtensa_format_decode (isa
, insnbuf
);
11778 if (fmt
== XTENSA_UNDEFINED
)
11779 as_fatal (_("cannot decode instruction format"));
11780 vinsn
->format
= fmt
;
11781 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11783 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11785 TInsn
*tinsn
= &vinsn
->slots
[i
];
11786 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11787 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11792 /* Expression utilities. */
11794 /* Return TRUE if the expression is an integer constant. */
11797 expr_is_const (const expressionS
*s
)
11799 return (s
->X_op
== O_constant
);
11803 /* Get the expression constant.
11804 Calling this is illegal if expr_is_const () returns TRUE. */
11807 get_expr_const (const expressionS
*s
)
11809 assert (expr_is_const (s
));
11810 return s
->X_add_number
;
11814 /* Set the expression to a constant value. */
11817 set_expr_const (expressionS
*s
, offsetT val
)
11819 s
->X_op
= O_constant
;
11820 s
->X_add_number
= val
;
11821 s
->X_add_symbol
= NULL
;
11822 s
->X_op_symbol
= NULL
;
11827 expr_is_register (const expressionS
*s
)
11829 return (s
->X_op
== O_register
);
11833 /* Get the expression constant.
11834 Calling this is illegal if expr_is_const () returns TRUE. */
11837 get_expr_register (const expressionS
*s
)
11839 assert (expr_is_register (s
));
11840 return s
->X_add_number
;
11844 /* Set the expression to a symbol + constant offset. */
11847 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11849 s
->X_op
= O_symbol
;
11850 s
->X_add_symbol
= sym
;
11851 s
->X_op_symbol
= NULL
; /* unused */
11852 s
->X_add_number
= offset
;
11856 /* Set the expression to symbol - minus_sym + offset. */
11859 set_expr_symbol_offset_diff (expressionS
*s
,
11861 symbolS
*minus_sym
,
11864 s
->X_op
= O_subtract
;
11865 s
->X_add_symbol
= sym
;
11866 s
->X_op_symbol
= minus_sym
; /* unused */
11867 s
->X_add_number
= offset
;
11871 /* Return TRUE if the two expressions are equal. */
11874 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11876 if (s1
->X_op
!= s2
->X_op
)
11878 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11880 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11882 if (s1
->X_add_number
!= s2
->X_add_number
)
11889 copy_expr (expressionS
*dst
, const expressionS
*src
)
11891 memcpy (dst
, src
, sizeof (expressionS
));
11895 /* Support for the "--rename-section" option. */
11897 struct rename_section_struct
11901 struct rename_section_struct
*next
;
11904 static struct rename_section_struct
*section_rename
;
11907 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11908 entries to the section_rename list. Note: Specifying multiple
11909 renamings separated by colons is not documented and is retained only
11910 for backward compatibility. */
11913 build_section_rename (const char *arg
)
11915 struct rename_section_struct
*r
;
11916 char *this_arg
= NULL
;
11917 char *next_arg
= NULL
;
11919 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11921 char *old_name
, *new_name
;
11925 next_arg
= strchr (this_arg
, ':');
11933 old_name
= this_arg
;
11934 new_name
= strchr (this_arg
, '=');
11936 if (*old_name
== '\0')
11938 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11941 if (!new_name
|| new_name
[1] == '\0')
11943 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11950 /* Check for invalid section renaming. */
11951 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11953 if (strcmp (r
->old_name
, old_name
) == 0)
11954 as_bad (_("section %s renamed multiple times"), old_name
);
11955 if (strcmp (r
->new_name
, new_name
) == 0)
11956 as_bad (_("multiple sections remapped to output section %s"),
11961 r
= (struct rename_section_struct
*)
11962 xmalloc (sizeof (struct rename_section_struct
));
11963 r
->old_name
= xstrdup (old_name
);
11964 r
->new_name
= xstrdup (new_name
);
11965 r
->next
= section_rename
;
11966 section_rename
= r
;
11972 xtensa_section_rename (char *name
)
11974 struct rename_section_struct
*r
= section_rename
;
11976 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11978 if (strcmp (r
->old_name
, name
) == 0)
11979 return r
->new_name
;