1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 size_t xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT
get_expanded_loop_offset (xtensa_opcode
);
440 static fragS
*get_literal_pool_location (segT
);
441 static void set_literal_pool_location (segT
, fragS
*);
442 static void xtensa_set_frag_assembly_state (fragS
*);
443 static void finish_vinsn (vliw_insn
*);
444 static bfd_boolean
emit_single_op (TInsn
*);
445 static int total_frag_text_expansion (fragS
*);
447 /* Alignment Functions. */
449 static size_t get_text_align_power (int);
450 static addressT
get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
452 /* Helpers for xtensa_relax_frag(). */
454 static long relax_frag_add_nop (fragS
*);
456 /* Accessors for additional per-subsegment information. */
458 static unsigned get_last_insn_flags (segT
, subsegT
);
459 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
460 static float get_subseg_total_freq (segT
, subsegT
);
461 static float get_subseg_target_freq (segT
, subsegT
);
462 static void set_subseg_freq (segT
, subsegT
, float, float);
464 /* Segment list functions. */
466 static void xtensa_move_literals (void);
467 static void xtensa_reorder_segments (void);
468 static void xtensa_switch_to_literal_fragment (emit_state
*);
469 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
470 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
471 static void xtensa_restore_emit_state (emit_state
*);
472 static void cache_literal_section
473 (seg_list
*, const char *, segT
*, bfd_boolean
);
475 /* Import from elf32-xtensa.c in BFD library. */
477 extern char *xtensa_get_property_section_name (asection
*, const char *);
479 /* op_placement_info functions. */
481 static void init_op_placement_info_table (void);
482 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
483 static int xg_get_single_size (xtensa_opcode
);
484 static xtensa_format
xg_get_single_format (xtensa_opcode
);
486 /* TInsn and IStack functions. */
488 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
489 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
490 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
491 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
492 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
493 static void tinsn_from_chars (TInsn
*, char *, int);
494 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
495 static int get_num_stack_text_bytes (IStack
*);
496 static int get_num_stack_literal_bytes (IStack
*);
498 /* vliw_insn functions. */
500 static void xg_init_vinsn (vliw_insn
*);
501 static void xg_clear_vinsn (vliw_insn
*);
502 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
503 static void xg_free_vinsn (vliw_insn
*);
504 static bfd_boolean vinsn_to_insnbuf
505 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
506 static void vinsn_from_chars (vliw_insn
*, char *);
508 /* Expression Utilities. */
510 bfd_boolean
expr_is_const (const expressionS
*);
511 offsetT
get_expr_const (const expressionS
*);
512 void set_expr_const (expressionS
*, offsetT
);
513 bfd_boolean
expr_is_register (const expressionS
*);
514 offsetT
get_expr_register (const expressionS
*);
515 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
516 static void set_expr_symbol_offset_diff
517 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
518 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
519 static void copy_expr (expressionS
*, const expressionS
*);
521 /* Section renaming. */
523 static void build_section_rename (const char *);
526 /* ISA imported from bfd. */
527 extern xtensa_isa xtensa_default_isa
;
529 extern int target_big_endian
;
531 static xtensa_opcode xtensa_addi_opcode
;
532 static xtensa_opcode xtensa_addmi_opcode
;
533 static xtensa_opcode xtensa_call0_opcode
;
534 static xtensa_opcode xtensa_call4_opcode
;
535 static xtensa_opcode xtensa_call8_opcode
;
536 static xtensa_opcode xtensa_call12_opcode
;
537 static xtensa_opcode xtensa_callx0_opcode
;
538 static xtensa_opcode xtensa_callx4_opcode
;
539 static xtensa_opcode xtensa_callx8_opcode
;
540 static xtensa_opcode xtensa_callx12_opcode
;
541 static xtensa_opcode xtensa_const16_opcode
;
542 static xtensa_opcode xtensa_entry_opcode
;
543 static xtensa_opcode xtensa_movi_opcode
;
544 static xtensa_opcode xtensa_movi_n_opcode
;
545 static xtensa_opcode xtensa_isync_opcode
;
546 static xtensa_opcode xtensa_jx_opcode
;
547 static xtensa_opcode xtensa_l32r_opcode
;
548 static xtensa_opcode xtensa_loop_opcode
;
549 static xtensa_opcode xtensa_loopnez_opcode
;
550 static xtensa_opcode xtensa_loopgtz_opcode
;
551 static xtensa_opcode xtensa_nop_opcode
;
552 static xtensa_opcode xtensa_nop_n_opcode
;
553 static xtensa_opcode xtensa_or_opcode
;
554 static xtensa_opcode xtensa_ret_opcode
;
555 static xtensa_opcode xtensa_ret_n_opcode
;
556 static xtensa_opcode xtensa_retw_opcode
;
557 static xtensa_opcode xtensa_retw_n_opcode
;
558 static xtensa_opcode xtensa_rsr_lcount_opcode
;
559 static xtensa_opcode xtensa_waiti_opcode
;
562 /* Command-line Options. */
564 bfd_boolean use_literal_section
= TRUE
;
565 static bfd_boolean align_targets
= TRUE
;
566 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
567 static bfd_boolean has_a0_b_retw
= FALSE
;
568 static bfd_boolean workaround_a0_b_retw
= FALSE
;
569 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
570 static bfd_boolean workaround_short_loop
= FALSE
;
571 static bfd_boolean maybe_has_short_loop
= FALSE
;
572 static bfd_boolean workaround_close_loop_end
= FALSE
;
573 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
575 /* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
581 static bfd_boolean workaround_all_short_loops
= FALSE
;
585 xtensa_setup_hw_workarounds (int earliest
, int latest
)
587 if (earliest
> latest
)
588 as_fatal (_("illegal range of target hardware versions"));
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest
< 105000 || latest
< 105000)
593 workaround_a0_b_retw
|= TRUE
;
594 workaround_b_j_loop_end
|= TRUE
;
595 workaround_short_loop
|= TRUE
;
596 workaround_close_loop_end
|= TRUE
;
597 workaround_all_short_loops
|= TRUE
;
604 option_density
= OPTION_MD_BASE
,
611 option_no_link_relax
,
619 option_text_section_literals
,
620 option_no_text_section_literals
,
622 option_absolute_literals
,
623 option_no_absolute_literals
,
625 option_align_targets
,
626 option_no_align_targets
,
628 option_warn_unaligned_targets
,
633 option_workaround_a0_b_retw
,
634 option_no_workaround_a0_b_retw
,
636 option_workaround_b_j_loop_end
,
637 option_no_workaround_b_j_loop_end
,
639 option_workaround_short_loop
,
640 option_no_workaround_short_loop
,
642 option_workaround_all_short_loops
,
643 option_no_workaround_all_short_loops
,
645 option_workaround_close_loop_end
,
646 option_no_workaround_close_loop_end
,
648 option_no_workarounds
,
650 option_rename_section_name
,
653 option_prefer_const16
,
655 option_target_hardware
658 const char *md_shortopts
= "";
660 struct option md_longopts
[] =
662 { "density", no_argument
, NULL
, option_density
},
663 { "no-density", no_argument
, NULL
, option_no_density
},
665 /* Both "relax" and "generics" are deprecated and treated as equivalent
666 to the "transform" option. */
667 { "relax", no_argument
, NULL
, option_relax
},
668 { "no-relax", no_argument
, NULL
, option_no_relax
},
669 { "generics", no_argument
, NULL
, option_generics
},
670 { "no-generics", no_argument
, NULL
, option_no_generics
},
672 { "transform", no_argument
, NULL
, option_transform
},
673 { "no-transform", no_argument
, NULL
, option_no_transform
},
674 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
675 { "no-text-section-literals", no_argument
, NULL
,
676 option_no_text_section_literals
},
677 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
678 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
679 /* This option was changed from -align-target to -target-align
680 because it conflicted with the "-al" option. */
681 { "target-align", no_argument
, NULL
, option_align_targets
},
682 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
683 { "warn-unaligned-targets", no_argument
, NULL
,
684 option_warn_unaligned_targets
},
685 { "longcalls", no_argument
, NULL
, option_longcalls
},
686 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
688 { "no-workaround-a0-b-retw", no_argument
, NULL
,
689 option_no_workaround_a0_b_retw
},
690 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
692 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
693 option_no_workaround_b_j_loop_end
},
694 { "workaround-b-j-loop-end", no_argument
, NULL
,
695 option_workaround_b_j_loop_end
},
697 { "no-workaround-short-loops", no_argument
, NULL
,
698 option_no_workaround_short_loop
},
699 { "workaround-short-loops", no_argument
, NULL
,
700 option_workaround_short_loop
},
702 { "no-workaround-all-short-loops", no_argument
, NULL
,
703 option_no_workaround_all_short_loops
},
704 { "workaround-all-short-loop", no_argument
, NULL
,
705 option_workaround_all_short_loops
},
707 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
708 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
710 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
712 { "no-workaround-close-loop-end", no_argument
, NULL
,
713 option_no_workaround_close_loop_end
},
714 { "workaround-close-loop-end", no_argument
, NULL
,
715 option_workaround_close_loop_end
},
717 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
719 { "link-relax", no_argument
, NULL
, option_link_relax
},
720 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
722 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
724 { NULL
, no_argument
, NULL
, 0 }
727 size_t md_longopts_size
= sizeof md_longopts
;
731 md_parse_option (int c
, char *arg
)
736 as_warn (_("--density option is ignored"));
738 case option_no_density
:
739 as_warn (_("--no-density option is ignored"));
741 case option_link_relax
:
744 case option_no_link_relax
:
747 case option_generics
:
748 as_warn (_("--generics is deprecated; use --transform instead"));
749 return md_parse_option (option_transform
, arg
);
750 case option_no_generics
:
751 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform
, arg
);
754 as_warn (_("--relax is deprecated; use --transform instead"));
755 return md_parse_option (option_transform
, arg
);
756 case option_no_relax
:
757 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
758 return md_parse_option (option_no_transform
, arg
);
759 case option_longcalls
:
760 directive_state
[directive_longcalls
] = TRUE
;
762 case option_no_longcalls
:
763 directive_state
[directive_longcalls
] = FALSE
;
765 case option_text_section_literals
:
766 use_literal_section
= FALSE
;
768 case option_no_text_section_literals
:
769 use_literal_section
= TRUE
;
771 case option_absolute_literals
:
772 if (!absolute_literals_supported
)
774 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
777 directive_state
[directive_absolute_literals
] = TRUE
;
779 case option_no_absolute_literals
:
780 directive_state
[directive_absolute_literals
] = FALSE
;
783 case option_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= TRUE
;
786 case option_no_workaround_a0_b_retw
:
787 workaround_a0_b_retw
= FALSE
;
789 case option_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= TRUE
;
792 case option_no_workaround_b_j_loop_end
:
793 workaround_b_j_loop_end
= FALSE
;
796 case option_workaround_short_loop
:
797 workaround_short_loop
= TRUE
;
799 case option_no_workaround_short_loop
:
800 workaround_short_loop
= FALSE
;
803 case option_workaround_all_short_loops
:
804 workaround_all_short_loops
= TRUE
;
806 case option_no_workaround_all_short_loops
:
807 workaround_all_short_loops
= FALSE
;
810 case option_workaround_close_loop_end
:
811 workaround_close_loop_end
= TRUE
;
813 case option_no_workaround_close_loop_end
:
814 workaround_close_loop_end
= FALSE
;
817 case option_no_workarounds
:
818 workaround_a0_b_retw
= FALSE
;
819 workaround_b_j_loop_end
= FALSE
;
820 workaround_short_loop
= FALSE
;
821 workaround_all_short_loops
= FALSE
;
822 workaround_close_loop_end
= FALSE
;
825 case option_align_targets
:
826 align_targets
= TRUE
;
828 case option_no_align_targets
:
829 align_targets
= FALSE
;
832 case option_warn_unaligned_targets
:
833 warn_unaligned_branch_targets
= TRUE
;
836 case option_rename_section_name
:
837 build_section_rename (arg
);
841 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
842 should be emitted or not. FIXME: Not implemented. */
845 case option_prefer_l32r
:
847 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
851 case option_prefer_const16
:
853 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
857 case option_target_hardware
:
859 int earliest
, latest
= 0;
860 if (*arg
== 0 || *arg
== '-')
861 as_fatal (_("invalid target hardware version"));
863 earliest
= strtol (arg
, &arg
, 0);
867 else if (*arg
== '-')
870 as_fatal (_("invalid target hardware version"));
871 latest
= strtol (arg
, &arg
, 0);
874 as_fatal (_("invalid target hardware version"));
876 xtensa_setup_hw_workarounds (earliest
, latest
);
880 case option_transform
:
881 /* This option has no affect other than to use the defaults,
882 which are already set. */
885 case option_no_transform
:
886 /* This option turns off all transformations of any kind.
887 However, because we want to preserve the state of other
888 directives, we only change its own field. Thus, before
889 you perform any transformation, always check if transform
890 is available. If you use the functions we provide for this
891 purpose, you will be ok. */
892 directive_state
[directive_transform
] = FALSE
;
902 md_show_usage (FILE *stream
)
906 --[no-]text-section-literals\n\
907 [Do not] put literals in the text section\n\
908 --[no-]absolute-literals\n\
909 [Do not] default to use non-PC-relative literals\n\
910 --[no-]target-align [Do not] try to align branch targets\n\
911 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
912 --[no-]transform [Do not] transform instructions\n\
913 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
917 /* Functions related to the list of current label symbols. */
920 xtensa_add_insn_label (symbolS
*sym
)
924 if (!free_insn_labels
)
925 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
928 l
= free_insn_labels
;
929 free_insn_labels
= l
->next
;
933 l
->next
= insn_labels
;
939 xtensa_clear_insn_labels (void)
943 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
950 /* The "loops_ok" argument is provided to allow ignoring labels that
951 define loop ends. This fixes a bug where the NOPs to align a
952 loop opcode were included in a previous zero-cost loop:
971 This argument is used to prevent moving the NOP to before the
972 loop-end label, which is what you want in this special case. */
975 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
979 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
981 symbolS
*lit_sym
= lit
->sym
;
982 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
984 S_SET_VALUE (lit_sym
, new_offset
);
985 symbol_set_frag (lit_sym
, new_frag
);
991 /* Directive data and functions. */
993 typedef struct state_stackS_struct
995 directiveE directive
;
997 bfd_boolean old_state
;
1001 struct state_stackS_struct
*prev
;
1004 state_stackS
*directive_state_stack
;
1006 const pseudo_typeS md_pseudo_table
[] =
1008 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1009 { "literal_position", xtensa_literal_position
, 0 },
1010 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1011 { "long", xtensa_elf_cons
, 4 },
1012 { "word", xtensa_elf_cons
, 4 },
1013 { "short", xtensa_elf_cons
, 2 },
1014 { "begin", xtensa_begin_directive
, 0 },
1015 { "end", xtensa_end_directive
, 0 },
1016 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1017 { "literal", xtensa_literal_pseudo
, 0 },
1018 { "frequency", xtensa_frequency_pseudo
, 0 },
1024 use_transform (void)
1026 /* After md_end, you should be checking frag by frag, rather
1027 than state directives. */
1028 assert (!past_xtensa_end
);
1029 return directive_state
[directive_transform
];
1034 use_longcalls (void)
1036 /* After md_end, you should be checking frag by frag, rather
1037 than state directives. */
1038 assert (!past_xtensa_end
);
1039 return directive_state
[directive_longcalls
] && use_transform ();
1044 do_align_targets (void)
1046 /* After md_end, you should be checking frag by frag, rather
1047 than state directives. */
1048 assert (!past_xtensa_end
);
1049 return align_targets
&& use_transform ();
1054 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1058 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1060 as_where (&file
, &line
);
1062 stack
->directive
= directive
;
1063 stack
->negated
= negated
;
1064 stack
->old_state
= directive_state
[directive
];
1067 stack
->datum
= datum
;
1068 stack
->prev
= directive_state_stack
;
1069 directive_state_stack
= stack
;
1071 directive_state
[directive
] = !negated
;
1076 directive_pop (directiveE
*directive
,
1077 bfd_boolean
*negated
,
1082 state_stackS
*top
= directive_state_stack
;
1084 if (!directive_state_stack
)
1086 as_bad (_("unmatched end directive"));
1087 *directive
= directive_none
;
1091 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1092 *directive
= top
->directive
;
1093 *negated
= top
->negated
;
1096 *datum
= top
->datum
;
1097 directive_state_stack
= top
->prev
;
1103 directive_balance (void)
1105 while (directive_state_stack
)
1107 directiveE directive
;
1108 bfd_boolean negated
;
1113 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1114 as_warn_where ((char *) file
, line
,
1115 _(".begin directive with no matching .end directive"));
1121 inside_directive (directiveE dir
)
1123 state_stackS
*top
= directive_state_stack
;
1125 while (top
&& top
->directive
!= dir
)
1128 return (top
!= NULL
);
1133 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1137 char *directive_string
;
1139 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1144 input_line_pointer
+= 3;
1147 len
= strspn (input_line_pointer
,
1148 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1150 /* This code is a hack to make .begin [no-][generics|relax] exactly
1151 equivalent to .begin [no-]transform. We should remove it when
1152 we stop accepting those options. */
1154 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1156 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1157 directive_string
= "transform";
1159 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1161 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1162 directive_string
= "transform";
1165 directive_string
= input_line_pointer
;
1167 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1169 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1171 input_line_pointer
+= len
;
1172 *directive
= (directiveE
) i
;
1173 if (*negated
&& !directive_info
[i
].can_be_negated
)
1174 as_bad (_("directive %s cannot be negated"),
1175 directive_info
[i
].name
);
1180 as_bad (_("unknown directive"));
1181 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1186 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1188 directiveE directive
;
1189 bfd_boolean negated
;
1194 get_directive (&directive
, &negated
);
1195 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1197 discard_rest_of_line ();
1201 if (cur_vinsn
.inside_bundle
)
1202 as_bad (_("directives are not valid inside bundles"));
1206 case directive_literal
:
1207 if (!inside_directive (directive_literal
))
1209 /* Previous labels go with whatever follows this directive, not with
1210 the literal, so save them now. */
1211 saved_insn_labels
= insn_labels
;
1214 as_warn (_(".begin literal is deprecated; use .literal instead"));
1215 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1216 xtensa_switch_to_literal_fragment (state
);
1217 directive_push (directive_literal
, negated
, state
);
1220 case directive_literal_prefix
:
1221 /* Have to flush pending output because a movi relaxed to an l32r
1222 might produce a literal. */
1223 md_flush_pending_output ();
1224 /* Check to see if the current fragment is a literal
1225 fragment. If it is, then this operation is not allowed. */
1226 if (generating_literals
)
1228 as_bad (_("cannot set literal_prefix inside literal fragment"));
1232 /* Allocate the literal state for this section and push
1233 onto the directive stack. */
1234 ls
= xmalloc (sizeof (lit_state
));
1237 *ls
= default_lit_sections
;
1239 directive_push (directive_literal_prefix
, negated
, ls
);
1241 /* Parse the new prefix from the input_line_pointer. */
1243 len
= strspn (input_line_pointer
,
1244 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1245 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1247 /* Process the new prefix. */
1248 xtensa_literal_prefix (input_line_pointer
, len
);
1250 /* Skip the name in the input line. */
1251 input_line_pointer
+= len
;
1254 case directive_freeregs
:
1255 /* This information is currently unused, but we'll accept the statement
1256 and just discard the rest of the line. This won't check the syntax,
1257 but it will accept every correct freeregs directive. */
1258 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1259 directive_push (directive_freeregs
, negated
, 0);
1262 case directive_schedule
:
1263 md_flush_pending_output ();
1264 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1265 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1266 directive_push (directive_schedule
, negated
, 0);
1267 xtensa_set_frag_assembly_state (frag_now
);
1270 case directive_density
:
1271 as_warn (_(".begin [no-]density is ignored"));
1274 case directive_absolute_literals
:
1275 md_flush_pending_output ();
1276 if (!absolute_literals_supported
&& !negated
)
1278 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1281 xtensa_set_frag_assembly_state (frag_now
);
1282 directive_push (directive
, negated
, 0);
1286 md_flush_pending_output ();
1287 xtensa_set_frag_assembly_state (frag_now
);
1288 directive_push (directive
, negated
, 0);
1292 demand_empty_rest_of_line ();
1297 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1299 directiveE begin_directive
, end_directive
;
1300 bfd_boolean begin_negated
, end_negated
;
1304 emit_state
**state_ptr
;
1307 if (cur_vinsn
.inside_bundle
)
1308 as_bad (_("directives are not valid inside bundles"));
1310 get_directive (&end_directive
, &end_negated
);
1312 md_flush_pending_output ();
1314 switch (end_directive
)
1316 case (directiveE
) XTENSA_UNDEFINED
:
1317 discard_rest_of_line ();
1320 case directive_density
:
1321 as_warn (_(".end [no-]density is ignored"));
1322 demand_empty_rest_of_line ();
1325 case directive_absolute_literals
:
1326 if (!absolute_literals_supported
&& !end_negated
)
1328 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1329 demand_empty_rest_of_line ();
1338 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1339 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1340 (const void **) state_ptr
);
1342 if (begin_directive
!= directive_none
)
1344 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1346 as_bad (_("does not match begin %s%s at %s:%d"),
1347 begin_negated
? "no-" : "",
1348 directive_info
[begin_directive
].name
, file
, line
);
1352 switch (end_directive
)
1354 case directive_literal
:
1355 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1356 xtensa_restore_emit_state (state
);
1357 xtensa_set_frag_assembly_state (frag_now
);
1359 if (!inside_directive (directive_literal
))
1361 /* Restore the list of current labels. */
1362 xtensa_clear_insn_labels ();
1363 insn_labels
= saved_insn_labels
;
1367 case directive_literal_prefix
:
1368 /* Restore the default collection sections from saved state. */
1369 s
= (lit_state
*) state
;
1372 if (use_literal_section
)
1373 default_lit_sections
= *s
;
1375 /* free the state storage */
1379 case directive_schedule
:
1380 case directive_freeregs
:
1384 xtensa_set_frag_assembly_state (frag_now
);
1390 demand_empty_rest_of_line ();
1394 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1396 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1399 xtensa_dwarf2_directive_loc (int x
)
1401 xtensa_loc_directive_seen
= TRUE
;
1402 dwarf2_directive_loc (x
);
1407 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1409 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1411 xtensa_loc_directive_seen
= FALSE
;
1412 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1416 /* Place an aligned literal fragment at the current location. */
1419 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1421 md_flush_pending_output ();
1423 if (inside_directive (directive_literal
))
1424 as_warn (_(".literal_position inside literal directive; ignoring"));
1425 xtensa_mark_literal_pool_location ();
1427 demand_empty_rest_of_line ();
1428 xtensa_clear_insn_labels ();
1432 /* Support .literal label, expr, ... */
1435 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1438 char *p
, *base_name
;
1442 if (inside_directive (directive_literal
))
1444 as_bad (_(".literal not allowed inside .begin literal region"));
1445 ignore_rest_of_line ();
1449 md_flush_pending_output ();
1451 /* Previous labels go with whatever follows this directive, not with
1452 the literal, so save them now. */
1453 saved_insn_labels
= insn_labels
;
1456 /* If we are using text-section literals, then this is the right value... */
1459 base_name
= input_line_pointer
;
1461 xtensa_switch_to_literal_fragment (&state
);
1463 /* ...but if we aren't using text-section-literals, then we
1464 need to put them in the section we just switched to. */
1465 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1468 /* All literals are aligned to four-byte boundaries. */
1469 frag_align (2, 0, 0);
1470 record_alignment (now_seg
, 2);
1472 c
= get_symbol_end ();
1473 /* Just after name is now '\0'. */
1474 p
= input_line_pointer
;
1478 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1480 as_bad (_("expected comma or colon after symbol name; "
1481 "rest of line ignored"));
1482 ignore_rest_of_line ();
1483 xtensa_restore_emit_state (&state
);
1491 input_line_pointer
++; /* skip ',' or ':' */
1493 xtensa_elf_cons (4);
1495 xtensa_restore_emit_state (&state
);
1497 /* Restore the list of current labels. */
1498 xtensa_clear_insn_labels ();
1499 insn_labels
= saved_insn_labels
;
1504 xtensa_literal_prefix (char const *start
, int len
)
1506 char *name
, *linkonce_suffix
;
1507 char *newname
, *newname4
;
1508 size_t linkonce_len
;
1510 /* Get a null-terminated copy of the name. */
1511 name
= xmalloc (len
+ 1);
1514 strncpy (name
, start
, len
);
1517 /* Allocate the sections (interesting note: the memory pointing to
1518 the name is actually used for the name by the new section). */
1520 newname
= xmalloc (len
+ strlen (".literal") + 1);
1521 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1523 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1524 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1525 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1527 strcpy (newname
, ".gnu.linkonce.literal");
1528 strcpy (newname4
, ".gnu.linkonce.lit4");
1530 strcat (newname
, linkonce_suffix
);
1531 strcat (newname4
, linkonce_suffix
);
1535 int suffix_pos
= len
;
1537 /* If the section name ends with ".text", then replace that suffix
1538 instead of appending an additional suffix. */
1539 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1542 strcpy (newname
, name
);
1543 strcpy (newname4
, name
);
1545 strcpy (newname
+ suffix_pos
, ".literal");
1546 strcpy (newname4
+ suffix_pos
, ".lit4");
1549 /* Note that cache_literal_section does not create a segment if
1550 it already exists. */
1551 default_lit_sections
.lit_seg
= NULL
;
1552 default_lit_sections
.lit4_seg
= NULL
;
1554 /* Canonicalizing section names allows renaming literal
1555 sections to occur correctly. */
1556 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1557 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1563 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1566 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1568 float fall_through_f
, target_f
;
1570 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1571 if (fall_through_f
< 0)
1573 as_bad (_("fall through frequency must be greater than 0"));
1574 ignore_rest_of_line ();
1578 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1581 as_bad (_("branch target frequency must be greater than 0"));
1582 ignore_rest_of_line ();
1586 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1588 demand_empty_rest_of_line ();
1592 /* Like normal .long/.short/.word, except support @plt, etc.
1593 Clobbers input_line_pointer, checks end-of-line. */
1596 xtensa_elf_cons (int nbytes
)
1599 bfd_reloc_code_real_type reloc
;
1601 md_flush_pending_output ();
1603 if (cur_vinsn
.inside_bundle
)
1604 as_bad (_("directives are not valid inside bundles"));
1606 if (is_it_end_of_statement ())
1608 demand_empty_rest_of_line ();
1615 if (exp
.X_op
== O_symbol
1616 && *input_line_pointer
== '@'
1617 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1620 reloc_howto_type
*reloc_howto
=
1621 bfd_reloc_type_lookup (stdoutput
, reloc
);
1623 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1624 as_bad (_("unsupported relocation"));
1625 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1626 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1627 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1628 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1629 as_bad (_("opcode-specific %s relocation used outside "
1630 "an instruction"), reloc_howto
->name
);
1631 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1632 as_bad (_("%s relocations do not fit in %d bytes"),
1633 reloc_howto
->name
, nbytes
);
1636 char *p
= frag_more ((int) nbytes
);
1637 xtensa_set_frag_assembly_state (frag_now
);
1638 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1639 nbytes
, &exp
, 0, reloc
);
1643 emit_expr (&exp
, (unsigned int) nbytes
);
1645 while (*input_line_pointer
++ == ',');
1647 input_line_pointer
--; /* Put terminator back into stream. */
1648 demand_empty_rest_of_line ();
1652 /* Parsing and Idiom Translation. */
1654 /* Parse @plt, etc. and return the desired relocation. */
1655 static bfd_reloc_code_real_type
1656 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1662 bfd_reloc_code_real_type reloc
;
1670 struct map_bfd
*ptr
;
1672 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1674 static struct map_bfd mapping
[] =
1676 MAP ("l", BFD_RELOC_LO16
),
1677 MAP ("h", BFD_RELOC_HI16
),
1678 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1679 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1683 return BFD_RELOC_NONE
;
1685 for (ch
= *str
, str2
= ident
;
1686 (str2
< ident
+ sizeof (ident
) - 1
1687 && (ISALNUM (ch
) || ch
== '@'));
1690 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1697 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1698 if (ch
== ptr
->string
[0]
1699 && len
== ptr
->length
1700 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1702 /* Now check for "identifier@suffix+constant". */
1703 if (*str
== '-' || *str
== '+')
1705 char *orig_line
= input_line_pointer
;
1706 expressionS new_exp
;
1708 input_line_pointer
= str
;
1709 expression (&new_exp
);
1710 if (new_exp
.X_op
== O_constant
)
1712 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1713 str
= input_line_pointer
;
1716 if (&input_line_pointer
!= str_p
)
1717 input_line_pointer
= orig_line
;
1724 return BFD_RELOC_UNUSED
;
1729 expression_end (const char *name
)
1752 #define ERROR_REG_NUM ((unsigned) -1)
1755 tc_get_register (const char *prefix
)
1758 const char *next_expr
;
1759 const char *old_line_pointer
;
1762 old_line_pointer
= input_line_pointer
;
1764 if (*input_line_pointer
== '$')
1765 ++input_line_pointer
;
1767 /* Accept "sp" as a synonym for "a1". */
1768 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1769 && expression_end (input_line_pointer
+ 2))
1771 input_line_pointer
+= 2;
1772 return 1; /* AR[1] */
1775 while (*input_line_pointer
++ == *prefix
++)
1777 --input_line_pointer
;
1782 as_bad (_("bad register name: %s"), old_line_pointer
);
1783 return ERROR_REG_NUM
;
1786 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1788 as_bad (_("bad register number: %s"), input_line_pointer
);
1789 return ERROR_REG_NUM
;
1794 while (ISDIGIT ((int) *input_line_pointer
))
1795 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1797 if (!(next_expr
= expression_end (input_line_pointer
)))
1799 as_bad (_("bad register name: %s"), old_line_pointer
);
1800 return ERROR_REG_NUM
;
1803 input_line_pointer
= (char *) next_expr
;
1810 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1812 xtensa_isa isa
= xtensa_default_isa
;
1814 /* Check if this is an immediate operand. */
1815 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1817 bfd_reloc_code_real_type reloc
;
1818 segT t
= expression (tok
);
1819 if (t
== absolute_section
1820 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1822 assert (tok
->X_op
== O_constant
);
1823 tok
->X_op
= O_symbol
;
1824 tok
->X_add_symbol
= &abs_symbol
;
1827 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1828 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1829 && (reloc
!= BFD_RELOC_NONE
))
1834 case BFD_RELOC_UNUSED
:
1835 as_bad (_("unsupported relocation"));
1838 case BFD_RELOC_XTENSA_PLT
:
1839 tok
->X_op
= O_pltrel
;
1842 case BFD_RELOC_LO16
:
1843 if (tok
->X_op
== O_constant
)
1844 tok
->X_add_number
&= 0xffff;
1849 case BFD_RELOC_HI16
:
1850 if (tok
->X_op
== O_constant
)
1851 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1860 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1861 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1863 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1866 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1867 as_bad (_("register number out of range"));
1870 tok
->X_op
= O_register
;
1871 tok
->X_add_symbol
= 0;
1872 tok
->X_add_number
= reg
;
1877 /* Split up the arguments for an opcode or pseudo-op. */
1880 tokenize_arguments (char **args
, char *str
)
1882 char *old_input_line_pointer
;
1883 bfd_boolean saw_comma
= FALSE
;
1884 bfd_boolean saw_arg
= FALSE
;
1885 bfd_boolean saw_colon
= FALSE
;
1887 char *arg_end
, *arg
;
1890 /* Save and restore input_line_pointer around this function. */
1891 old_input_line_pointer
= input_line_pointer
;
1892 input_line_pointer
= str
;
1894 while (*input_line_pointer
)
1897 switch (*input_line_pointer
)
1904 input_line_pointer
++;
1905 if (saw_comma
|| saw_colon
|| !saw_arg
)
1911 input_line_pointer
++;
1912 if (saw_comma
|| saw_colon
|| !saw_arg
)
1918 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1921 arg_end
= input_line_pointer
+ 1;
1922 while (!expression_end (arg_end
))
1925 arg_len
= arg_end
- input_line_pointer
;
1926 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1927 args
[num_args
] = arg
;
1931 strncpy (arg
, input_line_pointer
, arg_len
);
1932 arg
[arg_len
] = '\0';
1934 input_line_pointer
= arg_end
;
1944 if (saw_comma
|| saw_colon
)
1946 input_line_pointer
= old_input_line_pointer
;
1951 as_bad (_("extra comma"));
1953 as_bad (_("extra colon"));
1955 as_bad (_("missing argument"));
1957 as_bad (_("missing comma or colon"));
1958 input_line_pointer
= old_input_line_pointer
;
1963 /* Parse the arguments to an opcode. Return TRUE on error. */
1966 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1968 expressionS
*tok
, *last_tok
;
1969 xtensa_opcode opcode
= insn
->opcode
;
1970 bfd_boolean had_error
= TRUE
;
1971 xtensa_isa isa
= xtensa_default_isa
;
1972 int n
, num_regs
= 0;
1973 int opcode_operand_count
;
1974 int opnd_cnt
, last_opnd_cnt
;
1975 unsigned int next_reg
= 0;
1976 char *old_input_line_pointer
;
1978 if (insn
->insn_type
== ITYPE_LITERAL
)
1979 opcode_operand_count
= 1;
1981 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1984 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1986 /* Save and restore input_line_pointer around this function. */
1987 old_input_line_pointer
= input_line_pointer
;
1993 /* Skip invisible operands. */
1994 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2000 for (n
= 0; n
< num_args
; n
++)
2002 input_line_pointer
= arg_strings
[n
];
2003 if (*input_line_pointer
== ':')
2005 xtensa_regfile opnd_rf
;
2006 input_line_pointer
++;
2009 assert (opnd_cnt
> 0);
2011 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2013 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2014 as_warn (_("incorrect register number, ignoring"));
2019 if (opnd_cnt
>= opcode_operand_count
)
2021 as_warn (_("too many arguments"));
2024 assert (opnd_cnt
< MAX_INSN_ARGS
);
2026 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2027 next_reg
= tok
->X_add_number
+ 1;
2029 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2031 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2033 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2034 /* minus 1 because we are seeing one right now */
2040 last_opnd_cnt
= opnd_cnt
;
2047 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2051 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2054 insn
->ntok
= tok
- insn
->tok
;
2058 input_line_pointer
= old_input_line_pointer
;
2064 get_invisible_operands (TInsn
*insn
)
2066 xtensa_isa isa
= xtensa_default_isa
;
2067 static xtensa_insnbuf slotbuf
= NULL
;
2069 xtensa_opcode opc
= insn
->opcode
;
2070 int slot
, opnd
, fmt_found
;
2074 slotbuf
= xtensa_insnbuf_alloc (isa
);
2076 /* Find format/slot where this can be encoded. */
2079 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2081 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2083 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2089 if (fmt_found
) break;
2094 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2098 /* First encode all the visible operands
2099 (to deal with shared field operands). */
2100 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2102 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2103 && (insn
->tok
[opnd
].X_op
== O_register
2104 || insn
->tok
[opnd
].X_op
== O_constant
))
2106 val
= insn
->tok
[opnd
].X_add_number
;
2107 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2108 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2112 /* Then pull out the values for the invisible ones. */
2113 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2115 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2117 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2118 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2119 insn
->tok
[opnd
].X_add_number
= val
;
2120 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2121 insn
->tok
[opnd
].X_op
= O_register
;
2123 insn
->tok
[opnd
].X_op
= O_constant
;
2132 xg_reverse_shift_count (char **cnt_argp
)
2134 char *cnt_arg
, *new_arg
;
2135 cnt_arg
= *cnt_argp
;
2137 /* replace the argument with "31-(argument)" */
2138 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2139 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2142 *cnt_argp
= new_arg
;
2146 /* If "arg" is a constant expression, return non-zero with the value
2150 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2153 char *save_ptr
= input_line_pointer
;
2155 input_line_pointer
= arg
;
2157 input_line_pointer
= save_ptr
;
2159 if (exp
.X_op
== O_constant
)
2161 *valp
= exp
.X_add_number
;
2170 xg_replace_opname (char **popname
, char *newop
)
2173 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2174 strcpy (*popname
, newop
);
2179 xg_check_num_args (int *pnum_args
,
2184 int num_args
= *pnum_args
;
2186 if (num_args
< expected_num
)
2188 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2189 num_args
, opname
, expected_num
);
2193 if (num_args
> expected_num
)
2195 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2196 num_args
, opname
, expected_num
);
2197 while (num_args
-- > expected_num
)
2199 free (arg_strings
[num_args
]);
2200 arg_strings
[num_args
] = 0;
2202 *pnum_args
= expected_num
;
2210 /* If the register is not specified as part of the opcode,
2211 then get it from the operand and move it to the opcode. */
2214 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2216 xtensa_isa isa
= xtensa_default_isa
;
2218 char *opname
, *new_opname
;
2219 const char *sr_name
;
2220 int is_user
, is_write
;
2221 bfd_boolean has_underbar
= FALSE
;
2226 has_underbar
= TRUE
;
2229 is_user
= (opname
[1] == 'u');
2230 is_write
= (opname
[0] == 'w');
2232 /* Opname == [rw]ur or [rwx]sr... */
2234 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2237 /* Check if the argument is a symbolic register name. */
2238 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2239 /* Handle WSR to "INTSET" as a special case. */
2240 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2241 && !strcasecmp (arg_strings
[1], "intset"))
2242 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2243 if (sr
== XTENSA_UNDEFINED
2244 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2246 /* Maybe it's a register number.... */
2248 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2250 as_bad (_("invalid register '%s' for '%s' instruction"),
2251 arg_strings
[1], opname
);
2254 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2255 if (sr
== XTENSA_UNDEFINED
)
2257 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2263 /* Remove the last argument, which is now part of the opcode. */
2264 free (arg_strings
[1]);
2268 /* Translate the opcode. */
2269 sr_name
= xtensa_sysreg_name (isa
, sr
);
2270 /* Another special case for "WSR.INTSET".... */
2271 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2273 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2274 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2277 *popname
= new_opname
;
2284 xtensa_translate_old_userreg_ops (char **popname
)
2286 xtensa_isa isa
= xtensa_default_isa
;
2288 char *opname
, *new_opname
;
2289 const char *sr_name
;
2290 bfd_boolean has_underbar
= FALSE
;
2293 if (opname
[0] == '_')
2295 has_underbar
= TRUE
;
2299 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2300 if (sr
!= XTENSA_UNDEFINED
)
2302 /* The new default name ("nnn") is different from the old default
2303 name ("URnnn"). The old default is handled below, and we don't
2304 want to recognize [RW]nnn, so do nothing if the name is the (new)
2306 static char namebuf
[10];
2307 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2308 if (strcmp (namebuf
, opname
+ 1) == 0)
2316 /* Only continue if the reg name is "URnnn". */
2317 if (opname
[1] != 'u' || opname
[2] != 'r')
2319 val
= strtoul (opname
+ 3, &end
, 10);
2323 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2324 if (sr
== XTENSA_UNDEFINED
)
2326 as_bad (_("invalid register number (%ld) for '%s'"),
2332 /* Translate the opcode. */
2333 sr_name
= xtensa_sysreg_name (isa
, sr
);
2334 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2335 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2336 opname
[0], sr_name
);
2338 *popname
= new_opname
;
2345 xtensa_translate_zero_immed (char *old_op
,
2355 assert (opname
[0] != '_');
2357 if (strcmp (opname
, old_op
) != 0)
2360 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2362 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2364 xg_replace_opname (popname
, new_op
);
2365 free (arg_strings
[1]);
2366 arg_strings
[1] = arg_strings
[2];
2375 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2376 Returns non-zero if an error was found. */
2379 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2381 char *opname
= *popname
;
2382 bfd_boolean has_underbar
= FALSE
;
2384 if (cur_vinsn
.inside_bundle
)
2389 has_underbar
= TRUE
;
2393 if (strcmp (opname
, "mov") == 0)
2395 if (use_transform () && !has_underbar
&& density_supported
)
2396 xg_replace_opname (popname
, "mov.n");
2399 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2401 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2402 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2403 strcpy (arg_strings
[2], arg_strings
[1]);
2409 if (strcmp (opname
, "bbsi.l") == 0)
2411 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2413 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2414 if (target_big_endian
)
2415 xg_reverse_shift_count (&arg_strings
[1]);
2419 if (strcmp (opname
, "bbci.l") == 0)
2421 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2423 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2424 if (target_big_endian
)
2425 xg_reverse_shift_count (&arg_strings
[1]);
2429 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2430 && strcmp (opname
, "nop") == 0)
2432 if (use_transform () && !has_underbar
&& density_supported
)
2433 xg_replace_opname (popname
, "nop.n");
2436 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2438 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2439 arg_strings
[0] = (char *) xmalloc (3);
2440 arg_strings
[1] = (char *) xmalloc (3);
2441 arg_strings
[2] = (char *) xmalloc (3);
2442 strcpy (arg_strings
[0], "a1");
2443 strcpy (arg_strings
[1], "a1");
2444 strcpy (arg_strings
[2], "a1");
2450 /* Recognize [RW]UR and [RWX]SR. */
2451 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2452 && (opname
[1] == 'u' || opname
[1] == 's'))
2453 || (opname
[0] == 'x' && opname
[1] == 's'))
2455 && opname
[3] == '\0')
2456 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2458 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2459 [RW]<name> if <name> is the non-default name of a user register. */
2460 if ((opname
[0] == 'r' || opname
[0] == 'w')
2461 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2462 return xtensa_translate_old_userreg_ops (popname
);
2464 /* Relax branches that don't allow comparisons against an immediate value
2465 of zero to the corresponding branches with implicit zero immediates. */
2466 if (!has_underbar
&& use_transform ())
2468 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2469 pnum_args
, arg_strings
))
2472 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2473 pnum_args
, arg_strings
))
2476 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2477 pnum_args
, arg_strings
))
2480 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2481 pnum_args
, arg_strings
))
2489 /* Functions for dealing with the Xtensa ISA. */
2491 /* Currently the assembler only allows us to use a single target per
2492 fragment. Because of this, only one operand for a given
2493 instruction may be symbolic. If there is a PC-relative operand,
2494 the last one is chosen. Otherwise, the result is the number of the
2495 last immediate operand, and if there are none of those, we fail and
2499 get_relaxable_immed (xtensa_opcode opcode
)
2501 int last_immed
= -1;
2504 if (opcode
== XTENSA_UNDEFINED
)
2507 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2508 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2510 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2512 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2514 if (last_immed
== -1
2515 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2522 static xtensa_opcode
2523 get_opcode_from_buf (const char *buf
, int slot
)
2525 static xtensa_insnbuf insnbuf
= NULL
;
2526 static xtensa_insnbuf slotbuf
= NULL
;
2527 xtensa_isa isa
= xtensa_default_isa
;
2532 insnbuf
= xtensa_insnbuf_alloc (isa
);
2533 slotbuf
= xtensa_insnbuf_alloc (isa
);
2536 xtensa_insnbuf_from_chars (isa
, insnbuf
, buf
, 0);
2537 fmt
= xtensa_format_decode (isa
, insnbuf
);
2538 if (fmt
== XTENSA_UNDEFINED
)
2539 return XTENSA_UNDEFINED
;
2541 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2542 return XTENSA_UNDEFINED
;
2544 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2545 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2549 #ifdef TENSILICA_DEBUG
2551 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2554 xtensa_print_insn_table (void)
2556 int num_opcodes
, num_operands
;
2557 xtensa_opcode opcode
;
2558 xtensa_isa isa
= xtensa_default_isa
;
2560 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2561 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2564 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2565 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2566 for (opn
= 0; opn
< num_operands
; opn
++)
2568 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2570 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2572 xtensa_regfile opnd_rf
=
2573 xtensa_operand_regfile (isa
, opcode
, opn
);
2574 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2576 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2577 fputs ("[lLr] ", stderr
);
2579 fputs ("i ", stderr
);
2581 fprintf (stderr
, "\n");
2587 print_vliw_insn (xtensa_insnbuf vbuf
)
2589 xtensa_isa isa
= xtensa_default_isa
;
2590 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2591 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2594 fprintf (stderr
, "format = %d\n", f
);
2596 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2598 xtensa_opcode opcode
;
2602 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2603 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2604 opname
= xtensa_opcode_name (isa
, opcode
);
2606 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2607 fprintf (stderr
, " operands = ");
2609 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2613 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2615 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2616 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2617 fprintf (stderr
, "%d ", val
);
2619 fprintf (stderr
, "\n");
2621 xtensa_insnbuf_free (isa
, sbuf
);
2624 #endif /* TENSILICA_DEBUG */
2628 is_direct_call_opcode (xtensa_opcode opcode
)
2630 xtensa_isa isa
= xtensa_default_isa
;
2631 int n
, num_operands
;
2633 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2636 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2637 for (n
= 0; n
< num_operands
; n
++)
2639 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2640 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2647 /* Convert from BFD relocation type code to slot and operand number.
2648 Returns non-zero on failure. */
2651 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2653 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2654 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2656 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2659 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2660 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2662 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2672 /* Convert from slot number to BFD relocation type code for the
2673 standard PC-relative relocations. Return BFD_RELOC_NONE on
2676 static bfd_reloc_code_real_type
2677 encode_reloc (int slot
)
2679 if (slot
< 0 || slot
> 14)
2680 return BFD_RELOC_NONE
;
2682 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2686 /* Convert from slot numbers to BFD relocation type code for the
2687 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2689 static bfd_reloc_code_real_type
2690 encode_alt_reloc (int slot
)
2692 if (slot
< 0 || slot
> 14)
2693 return BFD_RELOC_NONE
;
2695 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2700 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2703 xtensa_opcode opcode
,
2709 uint32 valbuf
= value
;
2711 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2713 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2715 as_bad_where ((char *) file
, line
,
2716 _("operand %u is out of range for '%s'"), value
,
2717 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2719 as_bad_where ((char *) file
, line
,
2720 _("operand %u is invalid for '%s'"), value
,
2721 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2725 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2731 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2734 xtensa_opcode opcode
,
2738 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2739 fmt
, slot
, slotbuf
, &val
);
2740 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2745 /* Checks for rules from xtensa-relax tables. */
2747 /* The routine xg_instruction_matches_option_term must return TRUE
2748 when a given option term is true. The meaning of all of the option
2749 terms is given interpretation by this function. This is needed when
2750 an option depends on the state of a directive, but there are no such
2751 options in use right now. */
2754 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2755 const ReqOrOption
*option
)
2757 if (strcmp (option
->option_name
, "realnop") == 0
2758 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2760 /* These conditions were evaluated statically when building the
2761 relaxation table. There's no need to reevaluate them now. */
2766 as_fatal (_("internal error: unknown option name '%s'"),
2767 option
->option_name
);
2773 xg_instruction_matches_or_options (TInsn
*insn
,
2774 const ReqOrOptionList
*or_option
)
2776 const ReqOrOption
*option
;
2777 /* Must match each of the AND terms. */
2778 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2780 if (xg_instruction_matches_option_term (insn
, option
))
2788 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2790 const ReqOption
*req_options
;
2791 /* Must match each of the AND terms. */
2792 for (req_options
= options
;
2793 req_options
!= NULL
;
2794 req_options
= req_options
->next
)
2796 /* Must match one of the OR clauses. */
2797 if (!xg_instruction_matches_or_options (insn
,
2798 req_options
->or_option_terms
))
2805 /* Return the transition rule that matches or NULL if none matches. */
2808 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2810 PreconditionList
*condition_l
;
2812 if (rule
->opcode
!= insn
->opcode
)
2815 for (condition_l
= rule
->conditions
;
2816 condition_l
!= NULL
;
2817 condition_l
= condition_l
->next
)
2821 Precondition
*cond
= condition_l
->precond
;
2826 /* The expression must be the constant. */
2827 assert (cond
->op_num
< insn
->ntok
);
2828 exp1
= &insn
->tok
[cond
->op_num
];
2829 if (expr_is_const (exp1
))
2834 if (get_expr_const (exp1
) != cond
->op_data
)
2838 if (get_expr_const (exp1
) == cond
->op_data
)
2845 else if (expr_is_register (exp1
))
2850 if (get_expr_register (exp1
) != cond
->op_data
)
2854 if (get_expr_register (exp1
) == cond
->op_data
)
2866 assert (cond
->op_num
< insn
->ntok
);
2867 assert (cond
->op_data
< insn
->ntok
);
2868 exp1
= &insn
->tok
[cond
->op_num
];
2869 exp2
= &insn
->tok
[cond
->op_data
];
2874 if (!expr_is_equal (exp1
, exp2
))
2878 if (expr_is_equal (exp1
, exp2
))
2890 if (!xg_instruction_matches_options (insn
, rule
->options
))
2898 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2900 bfd_boolean a_greater
= FALSE
;
2901 bfd_boolean b_greater
= FALSE
;
2903 ReqOptionList
*l_a
= a
->options
;
2904 ReqOptionList
*l_b
= b
->options
;
2906 /* We only care if they both are the same except for
2907 a const16 vs. an l32r. */
2909 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2911 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2912 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2913 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2915 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2917 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2919 /* This is the case we care about. */
2920 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2921 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2928 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2929 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2939 l_or_a
= l_or_a
->next
;
2940 l_or_b
= l_or_b
->next
;
2942 if (l_or_a
|| l_or_b
)
2951 /* Incomparable if the substitution was used differently in two cases. */
2952 if (a_greater
&& b_greater
)
2964 static TransitionRule
*
2965 xg_instruction_match (TInsn
*insn
)
2967 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2969 assert (insn
->opcode
< table
->num_opcodes
);
2971 /* Walk through all of the possible transitions. */
2972 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2974 TransitionRule
*rule
= l
->rule
;
2975 if (xg_instruction_matches_rule (insn
, rule
))
2982 /* Various Other Internal Functions. */
2985 is_unique_insn_expansion (TransitionRule
*r
)
2987 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2989 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2996 xg_get_build_instr_size (BuildInstr
*insn
)
2998 assert (insn
->typ
== INSTR_INSTR
);
2999 return xg_get_single_size (insn
->opcode
);
3004 xg_is_narrow_insn (TInsn
*insn
)
3006 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3009 assert (insn
->insn_type
== ITYPE_INSN
);
3010 assert (insn
->opcode
< table
->num_opcodes
);
3012 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3014 TransitionRule
*rule
= l
->rule
;
3016 if (xg_instruction_matches_rule (insn
, rule
)
3017 && is_unique_insn_expansion (rule
))
3019 /* It only generates one instruction... */
3020 assert (insn
->insn_type
== ITYPE_INSN
);
3021 /* ...and it is a larger instruction. */
3022 if (xg_get_single_size (insn
->opcode
)
3023 < xg_get_build_instr_size (rule
->to_instr
))
3031 return (num_match
== 1);
3036 xg_is_single_relaxable_insn (TInsn
*insn
)
3038 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3041 assert (insn
->insn_type
== ITYPE_INSN
);
3042 assert (insn
->opcode
< table
->num_opcodes
);
3044 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3046 TransitionRule
*rule
= l
->rule
;
3048 if (xg_instruction_matches_rule (insn
, rule
)
3049 && is_unique_insn_expansion (rule
))
3051 /* It only generates one instruction... */
3052 assert (insn
->insn_type
== ITYPE_INSN
);
3053 /* ... and it is a larger instruction. */
3054 if (xg_get_single_size (insn
->opcode
)
3055 <= xg_get_build_instr_size (rule
->to_instr
))
3063 return (num_match
== 1);
3067 /* Return the maximum number of bytes this opcode can expand to. */
3070 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3072 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3074 int max_size
= xg_get_single_size (opcode
);
3076 assert (opcode
< table
->num_opcodes
);
3078 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3080 TransitionRule
*rule
= l
->rule
;
3081 BuildInstr
*build_list
;
3086 build_list
= rule
->to_instr
;
3087 if (is_unique_insn_expansion (rule
))
3089 assert (build_list
->typ
== INSTR_INSTR
);
3090 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3093 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3095 switch (build_list
->typ
)
3098 this_size
+= xg_get_single_size (build_list
->opcode
);
3100 case INSTR_LITERAL_DEF
:
3101 case INSTR_LABEL_DEF
:
3106 if (this_size
> max_size
)
3107 max_size
= this_size
;
3113 /* Return the maximum number of literal bytes this opcode can generate. */
3116 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3118 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3122 assert (opcode
< table
->num_opcodes
);
3124 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3126 TransitionRule
*rule
= l
->rule
;
3127 BuildInstr
*build_list
;
3132 build_list
= rule
->to_instr
;
3133 if (is_unique_insn_expansion (rule
))
3135 assert (build_list
->typ
== INSTR_INSTR
);
3136 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3139 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3141 switch (build_list
->typ
)
3143 case INSTR_LITERAL_DEF
:
3144 /* Hard-coded 4-byte literal. */
3148 case INSTR_LABEL_DEF
:
3153 if (this_size
> max_size
)
3154 max_size
= this_size
;
3161 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3163 int steps_taken
= 0;
3164 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3167 assert (insn
->insn_type
== ITYPE_INSN
);
3168 assert (insn
->opcode
< table
->num_opcodes
);
3170 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3172 TransitionRule
*rule
= l
->rule
;
3174 if (xg_instruction_matches_rule (insn
, rule
))
3176 if (steps_taken
== lateral_steps
)
3186 get_special_literal_symbol (void)
3188 static symbolS
*sym
= NULL
;
3191 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3197 get_special_label_symbol (void)
3199 static symbolS
*sym
= NULL
;
3202 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3208 xg_valid_literal_expression (const expressionS
*exp
)
3225 /* This will check to see if the value can be converted into the
3226 operand type. It will return TRUE if it does not fit. */
3229 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3231 uint32 valbuf
= value
;
3232 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3238 /* Assumes: All immeds are constants. Check that all constants fit
3239 into their immeds; return FALSE if not. */
3242 xg_immeds_fit (const TInsn
*insn
)
3244 xtensa_isa isa
= xtensa_default_isa
;
3248 assert (insn
->insn_type
== ITYPE_INSN
);
3249 for (i
= 0; i
< n
; ++i
)
3251 const expressionS
*expr
= &insn
->tok
[i
];
3252 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3259 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3264 /* The symbol should have a fixup associated with it. */
3273 /* This should only be called after we have an initial
3274 estimate of the addresses. */
3277 xg_symbolic_immeds_fit (const TInsn
*insn
,
3283 xtensa_isa isa
= xtensa_default_isa
;
3291 assert (insn
->insn_type
== ITYPE_INSN
);
3293 for (i
= 0; i
< n
; ++i
)
3295 const expressionS
*expr
= &insn
->tok
[i
];
3296 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3303 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3309 /* Check for the worst case. */
3310 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3315 /* We only allow symbols for pc-relative stuff.
3316 If pc_frag == 0, then we don't have frag locations yet. */
3320 /* If it is PC-relative and the symbol is not in the same
3321 segment as the PC.... */
3322 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0
3323 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3326 /* If it is a weak symbol, then assume it won't reach. This will
3327 only affect calls when longcalls are enabled, because if
3328 longcalls are disabled, then the call is marked as a specific
3330 if (S_IS_WEAK (expr
->X_add_symbol
))
3333 symbolP
= expr
->X_add_symbol
;
3334 sym_frag
= symbol_get_frag (symbolP
);
3335 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3336 pc
= pc_frag
->fr_address
+ pc_offset
;
3338 /* If frag has yet to be reached on this pass, assume it
3339 will move by STRETCH just as we did. If this is not so,
3340 it will be because some frag between grows, and that will
3341 force another pass. Beware zero-length frags. There
3342 should be a faster way to do this. */
3345 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3346 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3351 new_offset
= target
;
3352 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3353 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3358 /* The symbol should have a fixup associated with it. */
3367 /* Return TRUE on success. */
3370 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3375 memset (targ
, 0, sizeof (TInsn
));
3376 targ
->loc
= insn
->loc
;
3381 targ
->opcode
= bi
->opcode
;
3382 targ
->insn_type
= ITYPE_INSN
;
3383 targ
->is_specific_opcode
= FALSE
;
3385 for (; op
!= NULL
; op
= op
->next
)
3387 int op_num
= op
->op_num
;
3388 int op_data
= op
->op_data
;
3390 assert (op
->op_num
< MAX_INSN_ARGS
);
3392 if (targ
->ntok
<= op_num
)
3393 targ
->ntok
= op_num
+ 1;
3398 set_expr_const (&targ
->tok
[op_num
], op_data
);
3401 assert (op_data
< insn
->ntok
);
3402 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3405 sym
= get_special_literal_symbol ();
3406 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3409 sym
= get_special_label_symbol ();
3410 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3412 case OP_OPERAND_HI16U
:
3413 case OP_OPERAND_LOW16U
:
3414 assert (op_data
< insn
->ntok
);
3415 if (expr_is_const (&insn
->tok
[op_data
]))
3418 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3419 val
= xg_apply_userdef_op_fn (op
->typ
,
3422 targ
->tok
[op_num
].X_add_number
= val
;
3426 /* For const16 we can create relocations for these. */
3427 if (targ
->opcode
== XTENSA_UNDEFINED
3428 || (targ
->opcode
!= xtensa_const16_opcode
))
3430 assert (op_data
< insn
->ntok
);
3431 /* Need to build a O_lo16 or O_hi16. */
3432 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3433 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3435 if (op
->typ
== OP_OPERAND_HI16U
)
3436 targ
->tok
[op_num
].X_op
= O_hi16
;
3437 else if (op
->typ
== OP_OPERAND_LOW16U
)
3438 targ
->tok
[op_num
].X_op
= O_lo16
;
3445 /* currently handles:
3448 OP_OPERAND_F32MINUS */
3449 if (xg_has_userdef_op_fn (op
->typ
))
3451 assert (op_data
< insn
->ntok
);
3452 if (expr_is_const (&insn
->tok
[op_data
]))
3455 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3456 val
= xg_apply_userdef_op_fn (op
->typ
,
3459 targ
->tok
[op_num
].X_add_number
= val
;
3462 return FALSE
; /* We cannot use a relocation for this. */
3471 case INSTR_LITERAL_DEF
:
3473 targ
->opcode
= XTENSA_UNDEFINED
;
3474 targ
->insn_type
= ITYPE_LITERAL
;
3475 targ
->is_specific_opcode
= FALSE
;
3476 for (; op
!= NULL
; op
= op
->next
)
3478 int op_num
= op
->op_num
;
3479 int op_data
= op
->op_data
;
3480 assert (op
->op_num
< MAX_INSN_ARGS
);
3482 if (targ
->ntok
<= op_num
)
3483 targ
->ntok
= op_num
+ 1;
3488 assert (op_data
< insn
->ntok
);
3489 /* We can only pass resolvable literals through. */
3490 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3492 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3504 case INSTR_LABEL_DEF
:
3506 targ
->opcode
= XTENSA_UNDEFINED
;
3507 targ
->insn_type
= ITYPE_LABEL
;
3508 targ
->is_specific_opcode
= FALSE
;
3509 /* Literal with no ops is a label? */
3510 assert (op
== NULL
);
3521 /* Return TRUE on success. */
3524 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3526 for (; bi
!= NULL
; bi
= bi
->next
)
3528 TInsn
*next_insn
= istack_push_space (istack
);
3530 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3537 /* Return TRUE on valid expansion. */
3540 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3542 int stack_size
= istack
->ninsn
;
3543 int steps_taken
= 0;
3544 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3547 assert (insn
->insn_type
== ITYPE_INSN
);
3548 assert (insn
->opcode
< table
->num_opcodes
);
3550 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3552 TransitionRule
*rule
= l
->rule
;
3554 if (xg_instruction_matches_rule (insn
, rule
))
3556 if (lateral_steps
== steps_taken
)
3560 /* This is it. Expand the rule to the stack. */
3561 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3564 /* Check to see if it fits. */
3565 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3567 TInsn
*insn
= &istack
->insn
[i
];
3569 if (insn
->insn_type
== ITYPE_INSN
3570 && !tinsn_has_symbolic_operands (insn
)
3571 && !xg_immeds_fit (insn
))
3573 istack
->ninsn
= stack_size
;
3587 xg_expand_narrow (TInsn
*targ
, TInsn
*insn
)
3589 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3592 assert (insn
->insn_type
== ITYPE_INSN
);
3593 assert (insn
->opcode
< table
->num_opcodes
);
3595 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3597 TransitionRule
*rule
= l
->rule
;
3598 if (xg_instruction_matches_rule (insn
, rule
)
3599 && is_unique_insn_expansion (rule
))
3601 /* Is it a larger instruction? */
3602 if (xg_get_single_size (insn
->opcode
)
3603 <= xg_get_build_instr_size (rule
->to_instr
))
3605 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3614 /* Relax the assembly instruction at least "min_steps".
3615 Return the number of steps taken. */
3618 xg_assembly_relax (IStack
*istack
,
3621 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3622 offsetT pc_offset
, /* offset in fragment */
3623 int min_steps
, /* minimum conversion steps */
3624 long stretch
) /* number of bytes stretched so far */
3626 int steps_taken
= 0;
3628 /* assert (has no symbolic operands)
3629 Some of its immeds don't fit.
3630 Try to build a relaxed version.
3631 This may go through a couple of stages
3632 of single instruction transformations before
3635 TInsn single_target
;
3637 int lateral_steps
= 0;
3638 int istack_size
= istack
->ninsn
;
3640 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3641 && steps_taken
>= min_steps
)
3643 istack_push (istack
, insn
);
3646 current_insn
= *insn
;
3648 /* Walk through all of the single instruction expansions. */
3649 while (xg_is_single_relaxable_insn (¤t_insn
))
3651 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3653 assert (!error_val
);
3655 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3659 if (steps_taken
>= min_steps
)
3661 istack_push (istack
, &single_target
);
3665 current_insn
= single_target
;
3668 /* Now check for a multi-instruction expansion. */
3669 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3671 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3674 if (steps_taken
>= min_steps
)
3676 istack_push (istack
, ¤t_insn
);
3681 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3683 if (steps_taken
>= min_steps
)
3687 istack
->ninsn
= istack_size
;
3690 /* It's not going to work -- use the original. */
3691 istack_push (istack
, insn
);
3697 xg_force_frag_space (int size
)
3699 /* This may have the side effect of creating a new fragment for the
3700 space to go into. I just do not like the name of the "frag"
3707 xg_finish_frag (char *last_insn
,
3708 enum xtensa_relax_statesE frag_state
,
3709 enum xtensa_relax_statesE slot0_state
,
3711 bfd_boolean is_insn
)
3713 /* Finish off this fragment so that it has at LEAST the desired
3714 max_growth. If it doesn't fit in this fragment, close this one
3715 and start a new one. In either case, return a pointer to the
3716 beginning of the growth area. */
3720 xg_force_frag_space (max_growth
);
3722 old_frag
= frag_now
;
3724 frag_now
->fr_opcode
= last_insn
;
3726 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3728 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3729 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3731 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3732 xtensa_set_frag_assembly_state (frag_now
);
3734 /* Just to make sure that we did not split it up. */
3735 assert (old_frag
->fr_next
== frag_now
);
3739 /* Return TRUE if the target frag is one of the next non-empty frags. */
3742 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3747 for (; fragP
; fragP
= fragP
->fr_next
)
3749 if (fragP
== target
)
3751 if (fragP
->fr_fix
!= 0)
3753 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3755 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3756 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3758 if (fragP
->fr_type
== rs_space
)
3766 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3768 xtensa_isa isa
= xtensa_default_isa
;
3770 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3775 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3776 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3779 for (i
= 0; i
< num_ops
; i
++)
3781 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3787 if (target_op
== -1)
3790 if (insn
->ntok
<= target_op
)
3793 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3796 sym
= insn
->tok
[target_op
].X_add_symbol
;
3800 if (insn
->tok
[target_op
].X_add_number
!= 0)
3803 target_frag
= symbol_get_frag (sym
);
3804 if (target_frag
== NULL
)
3807 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3808 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3816 xg_add_branch_and_loop_targets (TInsn
*insn
)
3818 xtensa_isa isa
= xtensa_default_isa
;
3819 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3821 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3824 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3825 && insn
->tok
[i
].X_op
== O_symbol
)
3826 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3830 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3831 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3835 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3837 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3838 && insn
->tok
[i
].X_op
== O_symbol
)
3840 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3841 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3842 if (S_IS_DEFINED (sym
))
3843 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3850 /* Return FALSE if no error. */
3853 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3858 switch (instr_spec
->typ
)
3861 new_insn
->insn_type
= ITYPE_INSN
;
3862 new_insn
->opcode
= instr_spec
->opcode
;
3863 new_insn
->is_specific_opcode
= FALSE
;
3864 new_insn
->loc
= old_insn
->loc
;
3866 case INSTR_LITERAL_DEF
:
3867 new_insn
->insn_type
= ITYPE_LITERAL
;
3868 new_insn
->opcode
= XTENSA_UNDEFINED
;
3869 new_insn
->is_specific_opcode
= FALSE
;
3870 new_insn
->loc
= old_insn
->loc
;
3872 case INSTR_LABEL_DEF
:
3873 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3877 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3880 const expressionS
*src_exp
;
3886 /* The expression must be the constant. */
3887 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3888 exp
= &new_insn
->tok
[b_op
->op_num
];
3889 set_expr_const (exp
, b_op
->op_data
);
3893 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3894 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3895 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3896 exp
= &new_insn
->tok
[b_op
->op_num
];
3897 copy_expr (exp
, src_exp
);
3902 as_bad (_("can't handle generation of literal/labels yet"));
3906 as_bad (_("can't handle undefined OP TYPE"));
3911 new_insn
->ntok
= num_ops
;
3916 /* Return TRUE if it was simplified. */
3919 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3921 TransitionRule
*rule
;
3922 BuildInstr
*insn_spec
;
3924 if (old_insn
->is_specific_opcode
|| !density_supported
)
3927 rule
= xg_instruction_match (old_insn
);
3931 insn_spec
= rule
->to_instr
;
3932 /* There should only be one. */
3933 assert (insn_spec
!= NULL
);
3934 assert (insn_spec
->next
== NULL
);
3935 if (insn_spec
->next
!= NULL
)
3938 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3944 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3945 l32i.n. (2) Check the number of operands. (3) Place the instruction
3946 tokens into the stack or if we can relax it at assembly time, place
3947 multiple instructions/literals onto the stack. Return FALSE if no
3951 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3955 memset (&new_insn
, 0, sizeof (TInsn
));
3957 /* Narrow it if we can. xg_simplify_insn now does all the
3958 appropriate checking (e.g., for the density option). */
3959 if (xg_simplify_insn (orig_insn
, &new_insn
))
3960 orig_insn
= &new_insn
;
3962 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3964 if (orig_insn
->ntok
< noperands
)
3966 as_bad (_("found %d operands for '%s': Expected %d"),
3968 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3972 if (orig_insn
->ntok
> noperands
)
3973 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3975 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3978 /* If there are not enough operands, we will assert above. If there
3979 are too many, just cut out the extras here. */
3981 orig_insn
->ntok
= noperands
;
3985 Instructions with all constant immeds:
3986 Assemble them and relax the instruction if possible.
3987 Give error if not possible; no fixup needed.
3989 Instructions with symbolic immeds:
3990 Assemble them with a Fix up (that may cause instruction expansion).
3991 Also close out the fragment if the fixup may cause instruction expansion.
3993 There are some other special cases where we need alignment.
3994 1) before certain instructions with required alignment (OPCODE_ALIGN)
3995 2) before labels that have jumps (LABEL_ALIGN)
3996 3) after call instructions (RETURN_ALIGN)
3997 Multiple of these may be possible on the same fragment.
3998 If so, make sure to satisfy the required alignment.
3999 Then try to get the desired alignment. */
4001 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4004 if (orig_insn
->is_specific_opcode
|| !use_transform ())
4006 istack_push (istack
, orig_insn
);
4010 if (tinsn_has_symbolic_operands (orig_insn
))
4012 if (tinsn_has_complex_operands (orig_insn
))
4013 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4015 istack_push (istack
, orig_insn
);
4019 if (xg_immeds_fit (orig_insn
))
4020 istack_push (istack
, orig_insn
);
4022 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4029 /* Return TRUE if the section flags are marked linkonce
4030 or the name is .gnu.linkonce*. */
4033 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4035 flagword flags
, link_once_flags
;
4037 flags
= bfd_get_section_flags (abfd
, sec
);
4038 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4040 /* Flags might not be set yet. */
4041 if (!link_once_flags
)
4043 static size_t len
= sizeof ".gnu.linkonce.t.";
4045 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4046 link_once_flags
= SEC_LINK_ONCE
;
4048 return (link_once_flags
!= 0);
4053 xtensa_add_literal_sym (symbolS
*sym
)
4057 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4059 l
->next
= literal_syms
;
4065 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4067 static int lit_num
= 0;
4068 static char name
[256];
4071 sprintf (name
, ".L_lit_sym%d", lit_num
);
4073 /* Create a local symbol. If it is in a linkonce section, we have to
4074 be careful to make sure that if it is used in a relocation that the
4075 symbol will be in the output file. */
4076 if (get_is_linkonce_section (stdoutput
, sec
))
4078 symbolP
= symbol_new (name
, sec
, 0, frag
);
4079 S_CLEAR_EXTERNAL (symbolP
);
4080 /* symbolP->local = 1; */
4083 symbolP
= symbol_new (name
, sec
, 0, frag
);
4085 xtensa_add_literal_sym (symbolP
);
4087 frag
->tc_frag_data
.is_literal
= TRUE
;
4093 /* Currently all literals that are generated here are 32-bit L32R targets. */
4096 xg_assemble_literal (/* const */ TInsn
*insn
)
4099 symbolS
*lit_sym
= NULL
;
4101 /* size = 4 for L32R. It could easily be larger when we move to
4102 larger constants. Add a parameter later. */
4103 offsetT litsize
= 4;
4104 offsetT litalign
= 2; /* 2^2 = 4 */
4105 expressionS saved_loc
;
4106 expressionS
* emit_val
;
4108 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4110 assert (insn
->insn_type
== ITYPE_LITERAL
);
4111 assert (insn
->ntok
== 1); /* must be only one token here */
4113 xtensa_switch_to_literal_fragment (&state
);
4115 emit_val
= &insn
->tok
[0];
4116 if (emit_val
->X_op
== O_big
)
4118 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4121 /* This happens when someone writes a "movi a2, big_number". */
4122 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4123 _("invalid immediate"));
4124 xtensa_restore_emit_state (&state
);
4129 /* Force a 4-byte align here. Note that this opens a new frag, so all
4130 literals done with this function have a frag to themselves. That's
4131 important for the way text section literals work. */
4132 frag_align (litalign
, 0, 0);
4133 record_alignment (now_seg
, litalign
);
4135 if (emit_val
->X_op
== O_pltrel
)
4137 char *p
= frag_more (litsize
);
4138 xtensa_set_frag_assembly_state (frag_now
);
4139 if (emit_val
->X_add_symbol
)
4140 emit_val
->X_op
= O_symbol
;
4142 emit_val
->X_op
= O_constant
;
4143 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4144 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4147 emit_expr (emit_val
, litsize
);
4149 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4150 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4151 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4152 lit_sym
= frag_now
->fr_symbol
;
4153 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4156 xtensa_restore_emit_state (&state
);
4162 xg_assemble_literal_space (/* const */ int size
, int slot
)
4165 /* We might have to do something about this alignment. It only
4166 takes effect if something is placed here. */
4167 offsetT litalign
= 2; /* 2^2 = 4 */
4168 fragS
*lit_saved_frag
;
4170 assert (size
% 4 == 0);
4172 xtensa_switch_to_literal_fragment (&state
);
4174 /* Force a 4-byte align here. */
4175 frag_align (litalign
, 0, 0);
4176 record_alignment (now_seg
, litalign
);
4178 xg_force_frag_space (size
);
4180 lit_saved_frag
= frag_now
;
4181 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4182 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4183 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4184 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4187 xtensa_restore_emit_state (&state
);
4188 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4192 /* Put in a fixup record based on the opcode.
4193 Return TRUE on success. */
4196 xg_add_opcode_fix (TInsn
*tinsn
,
4204 xtensa_opcode opcode
= tinsn
->opcode
;
4205 bfd_reloc_code_real_type reloc
;
4206 reloc_howto_type
*howto
;
4210 reloc
= BFD_RELOC_NONE
;
4212 /* First try the special cases for "alternate" relocs. */
4213 if (opcode
== xtensa_l32r_opcode
)
4215 if (fragP
->tc_frag_data
.use_absolute_literals
)
4216 reloc
= encode_alt_reloc (slot
);
4218 else if (opcode
== xtensa_const16_opcode
)
4220 if (expr
->X_op
== O_lo16
)
4222 reloc
= encode_reloc (slot
);
4223 expr
->X_op
= O_symbol
;
4225 else if (expr
->X_op
== O_hi16
)
4227 reloc
= encode_alt_reloc (slot
);
4228 expr
->X_op
= O_symbol
;
4232 if (opnum
!= get_relaxable_immed (opcode
))
4234 as_bad (_("invalid relocation for operand %i of '%s'"),
4235 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4239 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4240 into the symbol table where the generic portions of the assembler
4241 won't know what to do with them. */
4242 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4244 as_bad (_("invalid expression for operand %i of '%s'"),
4245 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4249 /* Next try the generic relocs. */
4250 if (reloc
== BFD_RELOC_NONE
)
4251 reloc
= encode_reloc (slot
);
4252 if (reloc
== BFD_RELOC_NONE
)
4254 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4258 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4261 as_bad (_("undefined symbol for opcode \"%s\""),
4262 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4266 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4267 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4268 howto
->pc_relative
, reloc
);
4269 the_fix
->fx_no_overflow
= 1;
4271 if (expr
->X_add_symbol
4272 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4273 || S_IS_WEAK (expr
->X_add_symbol
)))
4274 the_fix
->fx_plt
= TRUE
;
4276 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4277 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4278 the_fix
->tc_fix_data
.slot
= slot
;
4285 xg_emit_insn_to_buf (TInsn
*tinsn
,
4290 bfd_boolean build_fix
)
4292 static xtensa_insnbuf insnbuf
= NULL
;
4293 bfd_boolean has_symbolic_immed
= FALSE
;
4294 bfd_boolean ok
= TRUE
;
4296 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4298 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4299 if (has_symbolic_immed
&& build_fix
)
4302 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4303 expressionS
*exp
= &tinsn
->tok
[opnum
];
4305 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4308 fragP
->tc_frag_data
.is_insn
= TRUE
;
4309 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4315 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4317 symbolS
*sym
= get_special_literal_symbol ();
4321 assert (insn
->insn_type
== ITYPE_INSN
);
4322 for (i
= 0; i
< insn
->ntok
; i
++)
4323 if (insn
->tok
[i
].X_add_symbol
== sym
)
4324 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4330 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4332 symbolS
*sym
= get_special_label_symbol ();
4334 /* assert (!insn->is_literal); */
4335 for (i
= 0; i
< insn
->ntok
; i
++)
4336 if (insn
->tok
[i
].X_add_symbol
== sym
)
4337 insn
->tok
[i
].X_add_symbol
= label_sym
;
4342 /* Return TRUE if the instruction can write to the specified
4343 integer register. */
4346 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4350 xtensa_isa isa
= xtensa_default_isa
;
4352 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4354 for (i
= 0; i
< num_ops
; i
++)
4357 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4358 if ((inout
== 'o' || inout
== 'm')
4359 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4361 xtensa_regfile opnd_rf
=
4362 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4363 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4365 if ((insn
->tok
[i
].X_op
== O_register
)
4366 && (insn
->tok
[i
].X_add_number
== regnum
))
4376 is_bad_loopend_opcode (const TInsn
*tinsn
)
4378 xtensa_opcode opcode
= tinsn
->opcode
;
4380 if (opcode
== XTENSA_UNDEFINED
)
4383 if (opcode
== xtensa_call0_opcode
4384 || opcode
== xtensa_callx0_opcode
4385 || opcode
== xtensa_call4_opcode
4386 || opcode
== xtensa_callx4_opcode
4387 || opcode
== xtensa_call8_opcode
4388 || opcode
== xtensa_callx8_opcode
4389 || opcode
== xtensa_call12_opcode
4390 || opcode
== xtensa_callx12_opcode
4391 || opcode
== xtensa_isync_opcode
4392 || opcode
== xtensa_ret_opcode
4393 || opcode
== xtensa_ret_n_opcode
4394 || opcode
== xtensa_retw_opcode
4395 || opcode
== xtensa_retw_n_opcode
4396 || opcode
== xtensa_waiti_opcode
4397 || opcode
== xtensa_rsr_lcount_opcode
)
4404 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4405 This allows the debugger to add unaligned labels.
4406 Also, the assembler generates stabs labels that need
4407 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4410 is_unaligned_label (symbolS
*sym
)
4412 const char *name
= S_GET_NAME (sym
);
4413 static size_t fake_size
= 0;
4417 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4420 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4422 fake_size
= strlen (FAKE_LABEL_NAME
);
4425 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4426 && (name
[fake_size
] == 'F'
4427 || name
[fake_size
] == 'L'
4428 || (name
[fake_size
] == 'e'
4429 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4437 next_non_empty_frag (const fragS
*fragP
)
4439 fragS
*next_fragP
= fragP
->fr_next
;
4441 /* Sometimes an empty will end up here due storage allocation issues.
4442 So we have to skip until we find something legit. */
4443 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4444 next_fragP
= next_fragP
->fr_next
;
4446 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4454 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4456 xtensa_opcode out_opcode
;
4457 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4459 if (next_fragP
== NULL
)
4462 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4463 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4465 *opcode
= out_opcode
;
4473 frag_format_size (const fragS
*fragP
)
4475 static xtensa_insnbuf insnbuf
= NULL
;
4476 xtensa_isa isa
= xtensa_default_isa
;
4481 insnbuf
= xtensa_insnbuf_alloc (isa
);
4484 return XTENSA_UNDEFINED
;
4486 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
, 0);
4488 fmt
= xtensa_format_decode (isa
, insnbuf
);
4489 if (fmt
== XTENSA_UNDEFINED
)
4490 return XTENSA_UNDEFINED
;
4491 fmt_size
= xtensa_format_length (isa
, fmt
);
4493 /* If the next format won't be changing due to relaxation, just
4494 return the length of the first format. */
4495 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4498 /* If during relaxation we have to pull an instruction out of a
4499 multi-slot instruction, we will return the more conservative
4500 number. This works because alignment on bigger instructions
4501 is more restrictive than alignment on smaller instructions.
4502 This is more conservative than we would like, but it happens
4505 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4508 /* If we aren't doing one of our own relaxations or it isn't
4509 slot-based, then the insn size won't change. */
4510 if (fragP
->fr_type
!= rs_machine_dependent
)
4512 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4515 /* If an instruction is about to grow, return the longer size. */
4516 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4517 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4520 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4521 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4528 next_frag_format_size (const fragS
*fragP
)
4530 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4531 return frag_format_size (next_fragP
);
4535 /* If the next legit fragment is an end-of-loop marker,
4536 switch its state so it will instantiate a NOP. */
4539 update_next_frag_state (fragS
*fragP
)
4541 fragS
*next_fragP
= fragP
->fr_next
;
4542 fragS
*new_target
= NULL
;
4546 /* We are guaranteed there will be one of these... */
4547 while (!(next_fragP
->fr_type
== rs_machine_dependent
4548 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4549 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4550 next_fragP
= next_fragP
->fr_next
;
4552 assert (next_fragP
->fr_type
== rs_machine_dependent
4553 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4554 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4556 /* ...and one of these. */
4557 new_target
= next_fragP
->fr_next
;
4558 while (!(new_target
->fr_type
== rs_machine_dependent
4559 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4560 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4561 new_target
= new_target
->fr_next
;
4563 assert (new_target
->fr_type
== rs_machine_dependent
4564 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4565 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4568 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4570 if (next_fragP
->fr_type
== rs_machine_dependent
4571 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4573 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4577 next_fragP
= next_fragP
->fr_next
;
4583 next_frag_is_branch_target (const fragS
*fragP
)
4585 /* Sometimes an empty will end up here due to storage allocation issues,
4586 so we have to skip until we find something legit. */
4587 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4589 if (fragP
->tc_frag_data
.is_branch_target
)
4591 if (fragP
->fr_fix
!= 0)
4599 next_frag_is_loop_target (const fragS
*fragP
)
4601 /* Sometimes an empty will end up here due storage allocation issues.
4602 So we have to skip until we find something legit. */
4603 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4605 if (fragP
->tc_frag_data
.is_loop_target
)
4607 if (fragP
->fr_fix
!= 0)
4615 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4617 const fragS
*next_fragp
= fragp
->fr_next
;
4618 xtensa_opcode next_opcode
;
4620 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4623 /* Sometimes an empty will end up here due to storage allocation issues,
4624 so we have to skip until we find something legit. */
4625 while (next_fragp
->fr_fix
== 0)
4626 next_fragp
= next_fragp
->fr_next
;
4628 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4631 /* There is some implicit knowledge encoded in here.
4632 The LOOP instructions that are NOT RELAX_IMMED have
4633 been relaxed. Note that we can assume that the LOOP
4634 instruction is in slot 0 because loops aren't bundleable. */
4635 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4636 return get_expanded_loop_offset (next_opcode
);
4642 /* Mark a location where we can later insert literal frags. Update
4643 the section's literal_pool_loc, so subsequent literals can be
4644 placed nearest to their use. */
4647 xtensa_mark_literal_pool_location (void)
4649 /* Any labels pointing to the current location need
4650 to be adjusted to after the literal pool. */
4652 fragS
*pool_location
;
4654 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4657 frag_align (2, 0, 0);
4658 record_alignment (now_seg
, 2);
4660 /* We stash info in the fr_var of these frags
4661 so we can later move the literal's fixes into this
4662 frchain's fix list. We can use fr_var because fr_var's
4663 interpretation depends solely on the fr_type and subtype. */
4664 pool_location
= frag_now
;
4665 frag_variant (rs_machine_dependent
, 0, (int) frchain_now
,
4666 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4667 xtensa_set_frag_assembly_state (frag_now
);
4668 frag_variant (rs_machine_dependent
, 0, (int) now_seg
,
4669 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4670 xtensa_set_frag_assembly_state (frag_now
);
4672 /* Now put a frag into the literal pool that points to this location. */
4673 set_literal_pool_location (now_seg
, pool_location
);
4674 xtensa_switch_to_non_abs_literal_fragment (&s
);
4675 frag_align (2, 0, 0);
4676 record_alignment (now_seg
, 2);
4678 /* Close whatever frag is there. */
4679 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4680 xtensa_set_frag_assembly_state (frag_now
);
4681 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4682 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4683 xtensa_restore_emit_state (&s
);
4684 xtensa_set_frag_assembly_state (frag_now
);
4688 /* Build a nop of the correct size into tinsn. */
4691 build_nop (TInsn
*tinsn
, int size
)
4697 tinsn
->opcode
= xtensa_nop_n_opcode
;
4699 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4700 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4704 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4706 tinsn
->opcode
= xtensa_or_opcode
;
4707 set_expr_const (&tinsn
->tok
[0], 1);
4708 set_expr_const (&tinsn
->tok
[1], 1);
4709 set_expr_const (&tinsn
->tok
[2], 1);
4713 tinsn
->opcode
= xtensa_nop_opcode
;
4715 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4720 /* Assemble a NOP of the requested size in the buffer. User must have
4721 allocated "buf" with at least "size" bytes. */
4724 assemble_nop (size_t size
, char *buf
)
4726 static xtensa_insnbuf insnbuf
= NULL
;
4729 build_nop (&tinsn
, size
);
4732 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4734 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4735 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4739 /* Return the number of bytes for the offset of the expanded loop
4740 instruction. This should be incorporated into the relaxation
4741 specification but is hard-coded here. This is used to auto-align
4742 the loop instruction. It is invalid to call this function if the
4743 configuration does not have loops or if the opcode is not a loop
4747 get_expanded_loop_offset (xtensa_opcode opcode
)
4749 /* This is the OFFSET of the loop instruction in the expanded loop.
4750 This MUST correspond directly to the specification of the loop
4751 expansion. It will be validated on fragment conversion. */
4752 assert (opcode
!= XTENSA_UNDEFINED
);
4753 if (opcode
== xtensa_loop_opcode
)
4755 if (opcode
== xtensa_loopnez_opcode
)
4757 if (opcode
== xtensa_loopgtz_opcode
)
4759 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4765 get_literal_pool_location (segT seg
)
4767 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4772 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4774 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4778 /* Set frag assembly state should be called when a new frag is
4779 opened and after a frag has been closed. */
4782 xtensa_set_frag_assembly_state (fragS
*fragP
)
4784 if (!density_supported
)
4785 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4787 /* This function is called from subsegs_finish, which is called
4788 after xtensa_end, so we can't use "use_transform" or
4789 "use_schedule" here. */
4790 if (!directive_state
[directive_transform
])
4791 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4792 fragP
->tc_frag_data
.use_absolute_literals
=
4793 directive_state
[directive_absolute_literals
];
4794 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4799 relaxable_section (asection
*sec
)
4801 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4806 xtensa_find_unmarked_state_frags (void)
4810 /* Walk over each fragment of all of the current segments. For each
4811 unmarked fragment, mark it with the same info as the previous
4813 for (seclist
= &stdoutput
->sections
;
4814 seclist
&& *seclist
;
4815 seclist
= &(*seclist
)->next
)
4817 segT sec
= *seclist
;
4818 segment_info_type
*seginfo
;
4821 flags
= bfd_get_section_flags (stdoutput
, sec
);
4822 if (flags
& SEC_DEBUGGING
)
4824 if (!(flags
& SEC_ALLOC
))
4827 seginfo
= seg_info (sec
);
4828 if (seginfo
&& seginfo
->frchainP
)
4830 fragS
*last_fragP
= 0;
4831 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4832 fragP
= fragP
->fr_next
)
4834 if (fragP
->fr_fix
!= 0
4835 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4837 if (last_fragP
== 0)
4839 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4840 _("assembly state not set for first frag in section %s"),
4845 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4846 fragP
->tc_frag_data
.is_no_density
=
4847 last_fragP
->tc_frag_data
.is_no_density
;
4848 fragP
->tc_frag_data
.is_no_transform
=
4849 last_fragP
->tc_frag_data
.is_no_transform
;
4850 fragP
->tc_frag_data
.use_absolute_literals
=
4851 last_fragP
->tc_frag_data
.use_absolute_literals
;
4854 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4863 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4865 void *unused ATTRIBUTE_UNUSED
)
4867 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4868 segment_info_type
*seginfo
= seg_info (sec
);
4869 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4871 if (flags
& SEC_CODE
)
4873 xtensa_isa isa
= xtensa_default_isa
;
4874 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4875 while (frag
!= NULL
)
4877 if (frag
->tc_frag_data
.is_branch_target
)
4883 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4884 fmt
= xtensa_format_decode (isa
, insnbuf
);
4885 op_size
= xtensa_format_length (isa
, fmt
);
4886 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4887 if (frag_addr
+ op_size
> (int) xtensa_fetch_width
)
4888 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4889 _("unaligned branch target: %d bytes at 0x%lx"),
4890 op_size
, frag
->fr_address
);
4892 frag
= frag
->fr_next
;
4894 xtensa_insnbuf_free (isa
, insnbuf
);
4900 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4902 void *unused ATTRIBUTE_UNUSED
)
4904 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4905 segment_info_type
*seginfo
= seg_info (sec
);
4906 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4907 xtensa_isa isa
= xtensa_default_isa
;
4909 if (flags
& SEC_CODE
)
4911 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4912 while (frag
!= NULL
)
4914 if (frag
->tc_frag_data
.is_first_loop_insn
)
4920 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4921 fmt
= xtensa_format_decode (isa
, insnbuf
);
4922 op_size
= xtensa_format_length (isa
, fmt
);
4923 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4925 if (frag_addr
+ op_size
> (signed) xtensa_fetch_width
)
4926 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4927 _("unaligned loop: %d bytes at 0x%lx"),
4928 op_size
, frag
->fr_address
);
4930 frag
= frag
->fr_next
;
4932 xtensa_insnbuf_free (isa
, insnbuf
);
4938 xg_apply_tentative_value (fixS
*fixP
, valueT val
)
4940 xtensa_isa isa
= xtensa_default_isa
;
4941 static xtensa_insnbuf insnbuf
= NULL
;
4942 static xtensa_insnbuf slotbuf
= NULL
;
4945 bfd_boolean alt_reloc
;
4946 xtensa_opcode opcode
;
4947 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4949 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4951 as_fatal (_("unexpected fix"));
4955 insnbuf
= xtensa_insnbuf_alloc (isa
);
4956 slotbuf
= xtensa_insnbuf_alloc (isa
);
4959 xtensa_insnbuf_from_chars (isa
, insnbuf
, fixpos
, 0);
4960 fmt
= xtensa_format_decode (isa
, insnbuf
);
4961 if (fmt
== XTENSA_UNDEFINED
)
4962 as_fatal (_("undecodable fix"));
4963 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4964 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4965 if (opcode
== XTENSA_UNDEFINED
)
4966 as_fatal (_("undecodable fix"));
4968 /* CONST16 immediates are not PC-relative, despite the fact that we
4969 reuse the normal PC-relative operand relocations for the low part
4970 of a CONST16 operand. The code in tc_gen_reloc does not decode
4971 the opcodes so it is more convenient to detect this special case
4973 if (opcode
== xtensa_const16_opcode
)
4976 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4977 get_relaxable_immed (opcode
), val
,
4978 fixP
->fx_file
, fixP
->fx_line
);
4980 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4981 xtensa_insnbuf_to_chars (isa
, insnbuf
, fixpos
, 0);
4985 /* External Functions and Other GAS Hooks. */
4988 xtensa_target_format (void)
4990 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4995 xtensa_file_arch_init (bfd
*abfd
)
4997 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5002 md_number_to_chars (char *buf
, valueT val
, int n
)
5004 if (target_big_endian
)
5005 number_to_chars_bigendian (buf
, val
, n
);
5007 number_to_chars_littleendian (buf
, val
, n
);
5011 /* This function is called once, at assembler startup time. It should
5012 set up all the tables, etc. that the MD part of the assembler will
5018 segT current_section
= now_seg
;
5019 int current_subsec
= now_subseg
;
5022 xtensa_default_isa
= xtensa_isa_init (0, 0);
5023 isa
= xtensa_default_isa
;
5027 /* Set up the .literal, .fini.literal and .init.literal sections. */
5028 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5029 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5030 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5031 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5032 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5034 subseg_set (current_section
, current_subsec
);
5036 xg_init_vinsn (&cur_vinsn
);
5038 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5039 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5040 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5041 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5042 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5043 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5044 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5045 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5046 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5047 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5048 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5049 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5050 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5051 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5052 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5053 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5054 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5055 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5056 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5057 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5058 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5059 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5060 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5061 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5062 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5063 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5064 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5065 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5066 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5068 init_op_placement_info_table ();
5070 /* Set up the assembly state. */
5071 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5072 xtensa_set_frag_assembly_state (frag_now
);
5076 /* TC_INIT_FIX_DATA hook */
5079 xtensa_init_fix_data (fixS
*x
)
5081 x
->tc_fix_data
.slot
= 0;
5082 x
->tc_fix_data
.X_add_symbol
= NULL
;
5083 x
->tc_fix_data
.X_add_number
= 0;
5087 /* tc_frob_label hook */
5090 xtensa_frob_label (symbolS
*sym
)
5092 /* Since the label was already attached to a frag associated with the
5093 previous basic block, it now needs to be reset to the current frag. */
5094 symbol_set_frag (sym
, frag_now
);
5095 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5097 if (generating_literals
)
5098 xtensa_add_literal_sym (sym
);
5100 xtensa_add_insn_label (sym
);
5102 if (symbol_get_tc (sym
)->is_loop_target
5103 && (get_last_insn_flags (now_seg
, now_subseg
)
5104 & FLAG_IS_BAD_LOOPEND
) != 0)
5105 as_bad (_("invalid last instruction for a zero-overhead loop"));
5107 /* No target aligning in the absolute section. */
5108 if (now_seg
!= absolute_section
5109 && do_align_targets ()
5110 && !is_unaligned_label (sym
)
5111 && !generating_literals
)
5113 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5114 xtensa_set_frag_assembly_state (frag_now
);
5116 /* The only time this type of frag grows is when there is a
5117 negatable branch that needs to be relaxed as the last
5118 instruction in a zero-overhead loop. Because alignment frags
5119 are so common, marking them all as possibly growing four
5120 bytes makes any worst-case analysis appear much worse than it
5121 is. So, we make fr_var not actually reflect the amount of
5122 memory allocated at the end of this frag, but rather the
5123 amount of memory this frag might grow. The "4, 0" below
5124 allocates four bytes at the end of the frag for room to grow
5125 if we need to relax a loop end with a NOP. Frags prior to
5126 this one might grow to align this one, but the frag itself
5127 won't grow unless it meets the condition above. */
5129 #define RELAX_LOOP_END_BYTES 4
5131 frag_var (rs_machine_dependent
,
5132 RELAX_LOOP_END_BYTES
, (int) freq
,
5133 RELAX_DESIRE_ALIGN_IF_TARGET
,
5134 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5135 xtensa_set_frag_assembly_state (frag_now
);
5136 xtensa_move_labels (frag_now
, 0, TRUE
);
5139 /* We need to mark the following properties even if we aren't aligning. */
5141 /* If the label is already known to be a branch target, i.e., a
5142 forward branch, mark the frag accordingly. Backward branches
5143 are handled by xg_add_branch_and_loop_targets. */
5144 if (symbol_get_tc (sym
)->is_branch_target
)
5145 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5147 /* Loops only go forward, so they can be identified here. */
5148 if (symbol_get_tc (sym
)->is_loop_target
)
5149 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5153 /* tc_unrecognized_line hook */
5156 xtensa_unrecognized_line (int ch
)
5161 if (cur_vinsn
.inside_bundle
== 0)
5163 /* PR8110: Cannot emit line number info inside a FLIX bundle
5164 when using --gstabs. Temporarily disable debug info. */
5165 generate_lineno_debug ();
5166 if (debug_type
== DEBUG_STABS
)
5168 xt_saved_debug_type
= debug_type
;
5169 debug_type
= DEBUG_NONE
;
5172 cur_vinsn
.inside_bundle
= 1;
5176 as_bad (_("extra opening brace"));
5182 if (cur_vinsn
.inside_bundle
)
5183 finish_vinsn (&cur_vinsn
);
5186 as_bad (_("extra closing brace"));
5191 as_bad (_("syntax error"));
5198 /* md_flush_pending_output hook */
5201 xtensa_flush_pending_output (void)
5203 if (cur_vinsn
.inside_bundle
)
5204 as_bad (_("missing closing brace"));
5206 /* If there is a non-zero instruction fragment, close it. */
5207 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5209 frag_wane (frag_now
);
5211 xtensa_set_frag_assembly_state (frag_now
);
5213 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5215 xtensa_clear_insn_labels ();
5219 /* We had an error while parsing an instruction. The string might look
5220 like this: "insn arg1, arg2 }". If so, we need to see the closing
5221 brace and reset some fields. Otherwise, the vinsn never gets closed
5222 and the num_slots field will grow past the end of the array of slots,
5223 and bad things happen. */
5226 error_reset_cur_vinsn (void)
5228 if (cur_vinsn
.inside_bundle
)
5230 if (*input_line_pointer
== '}'
5231 || *(input_line_pointer
- 1) == '}'
5232 || *(input_line_pointer
- 2) == '}')
5233 xg_clear_vinsn (&cur_vinsn
);
5239 md_assemble (char *str
)
5241 xtensa_isa isa
= xtensa_default_isa
;
5244 bfd_boolean has_underbar
= FALSE
;
5245 char *arg_strings
[MAX_INSN_ARGS
];
5247 TInsn orig_insn
; /* Original instruction from the input. */
5249 tinsn_init (&orig_insn
);
5251 /* Split off the opcode. */
5252 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5253 opname
= xmalloc (opnamelen
+ 1);
5254 memcpy (opname
, str
, opnamelen
);
5255 opname
[opnamelen
] = '\0';
5257 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5260 as_bad (_("syntax error"));
5264 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5267 /* Check for an underbar prefix. */
5270 has_underbar
= TRUE
;
5274 orig_insn
.insn_type
= ITYPE_INSN
;
5276 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5278 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5279 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5281 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5282 if (fmt
== XTENSA_UNDEFINED
)
5284 as_bad (_("unknown opcode or format name '%s'"), opname
);
5285 error_reset_cur_vinsn ();
5288 if (!cur_vinsn
.inside_bundle
)
5290 as_bad (_("format names only valid inside bundles"));
5291 error_reset_cur_vinsn ();
5294 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5295 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5297 cur_vinsn
.format
= fmt
;
5298 free (has_underbar
? opname
- 1 : opname
);
5299 error_reset_cur_vinsn ();
5303 /* Special case: The call instructions should be marked "specific opcode"
5304 to keep them from expanding. */
5305 if (!use_longcalls () && is_direct_call_opcode (orig_insn
.opcode
))
5306 orig_insn
.is_specific_opcode
= TRUE
;
5308 /* Parse the arguments. */
5309 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5311 as_bad (_("syntax error"));
5312 error_reset_cur_vinsn ();
5316 /* Free the opcode and argument strings, now that they've been parsed. */
5317 free (has_underbar
? opname
- 1 : opname
);
5319 while (num_args
-- > 0)
5320 free (arg_strings
[num_args
]);
5322 /* Get expressions for invisible operands. */
5323 if (get_invisible_operands (&orig_insn
))
5325 error_reset_cur_vinsn ();
5329 /* Check for the right number and type of arguments. */
5330 if (tinsn_check_arguments (&orig_insn
))
5332 error_reset_cur_vinsn ();
5336 dwarf2_where (&orig_insn
.loc
);
5338 xg_add_branch_and_loop_targets (&orig_insn
);
5340 /* Special-case for "entry" instruction. */
5341 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5343 /* Check that the third opcode (#2) is >= 16. */
5344 if (orig_insn
.ntok
>= 3)
5346 expressionS
*exp
= &orig_insn
.tok
[2];
5350 if (exp
->X_add_number
< 16)
5351 as_warn (_("entry instruction with stack decrement < 16"));
5355 as_warn (_("entry instruction with non-constant decrement"));
5361 assemble_tokens (opcode, tok, ntok);
5362 expand the tokens from the orig_insn into the
5363 stack of instructions that will not expand
5364 unless required at relaxation time. */
5366 if (!cur_vinsn
.inside_bundle
)
5367 emit_single_op (&orig_insn
);
5368 else /* We are inside a bundle. */
5370 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5371 cur_vinsn
.num_slots
++;
5372 if (*input_line_pointer
== '}'
5373 || *(input_line_pointer
- 1) == '}'
5374 || *(input_line_pointer
- 2) == '}')
5375 finish_vinsn (&cur_vinsn
);
5378 /* We've just emitted a new instruction so clear the list of labels. */
5379 xtensa_clear_insn_labels ();
5383 /* HANDLE_ALIGN hook */
5385 /* For a .align directive, we mark the previous block with the alignment
5386 information. This will be placed in the object file in the
5387 property section corresponding to this section. */
5390 xtensa_handle_align (fragS
*fragP
)
5393 && ! fragP
->tc_frag_data
.is_literal
5394 && (fragP
->fr_type
== rs_align
5395 || fragP
->fr_type
== rs_align_code
)
5396 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5397 && fragP
->fr_offset
> 0
5398 && now_seg
!= bss_section
)
5400 fragP
->tc_frag_data
.is_align
= TRUE
;
5401 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5404 if (fragP
->fr_type
== rs_align_test
)
5407 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5409 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5410 _("unaligned entry instruction"));
5415 /* TC_FRAG_INIT hook */
5418 xtensa_frag_init (fragS
*frag
)
5420 xtensa_set_frag_assembly_state (frag
);
5425 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5431 /* Round up a section size to the appropriate boundary. */
5434 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5436 return size
; /* Byte alignment is fine. */
5441 md_pcrel_from (fixS
*fixP
)
5444 static xtensa_insnbuf insnbuf
= NULL
;
5445 static xtensa_insnbuf slotbuf
= NULL
;
5448 xtensa_opcode opcode
;
5451 xtensa_isa isa
= xtensa_default_isa
;
5452 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5453 bfd_boolean alt_reloc
;
5458 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5463 insnbuf
= xtensa_insnbuf_alloc (isa
);
5464 slotbuf
= xtensa_insnbuf_alloc (isa
);
5467 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5468 xtensa_insnbuf_from_chars (isa
, insnbuf
, insn_p
, 0);
5469 fmt
= xtensa_format_decode (isa
, insnbuf
);
5471 if (fmt
== XTENSA_UNDEFINED
)
5472 as_fatal (_("bad instruction format"));
5474 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5475 as_fatal (_("invalid relocation"));
5477 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5478 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5480 /* Check for "alternate" relocation (operand not specified). */
5481 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5483 if (opcode
!= xtensa_l32r_opcode
5484 && opcode
!= xtensa_const16_opcode
)
5485 as_fatal (_("invalid relocation for '%s' instruction"),
5486 xtensa_opcode_name (isa
, opcode
));
5490 opnum
= get_relaxable_immed (opcode
);
5492 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5493 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5495 as_bad_where (fixP
->fx_file
,
5497 _("invalid relocation for operand %d of '%s'"),
5498 opnum
, xtensa_opcode_name (isa
, opcode
));
5501 return 0 - opnd_value
;
5505 /* TC_FORCE_RELOCATION hook */
5508 xtensa_force_relocation (fixS
*fix
)
5510 switch (fix
->fx_r_type
)
5512 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5513 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5514 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5515 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5516 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5517 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5518 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5519 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5520 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5521 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5522 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5523 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5524 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5525 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5526 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5527 case BFD_RELOC_VTABLE_INHERIT
:
5528 case BFD_RELOC_VTABLE_ENTRY
:
5534 if (linkrelax
&& fix
->fx_addsy
5535 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5538 return generic_force_reloc (fix
);
5542 /* NO_PSEUDO_DOT hook */
5544 /* This function has nothing to do with pseudo dots, but this is the
5545 nearest macro to where the check needs to take place. FIXME: This
5549 xtensa_check_inside_bundle (void)
5551 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5552 as_bad (_("directives are not valid inside bundles"));
5554 /* This function must always return FALSE because it is called via a
5555 macro that has nothing to do with bundling. */
5560 /* md_elf_section_change_hook */
5563 xtensa_elf_section_change_hook (void)
5565 /* Set up the assembly state. */
5566 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5567 xtensa_set_frag_assembly_state (frag_now
);
5571 /* tc_fix_adjustable hook */
5574 xtensa_fix_adjustable (fixS
*fixP
)
5576 /* An offset is not allowed in combination with the difference of two
5577 symbols, but that cannot be easily detected after a local symbol
5578 has been adjusted to a (section+offset) form. Return 0 so that such
5579 an fix will not be adjusted. */
5580 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5581 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5584 /* We need the symbol name for the VTABLE entries. */
5585 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5586 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5590 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || S_IS_WEAK (fixP
->fx_addsy
)))
5594 /* We may someday want to enable this code to preserve relocations for
5595 non-PC-relative fixes, possibly under control of a PIC flag. */
5596 return (fixP
->fx_pcrel
5597 || (fixP
->fx_subsy
!= NULL
5598 && (S_GET_SEGMENT (fixP
->fx_subsy
)
5599 == S_GET_SEGMENT (fixP
->fx_addsy
)))
5600 || S_IS_LOCAL (fixP
->fx_addsy
));
5608 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
5610 if (fixP
->fx_pcrel
== 0 && fixP
->fx_addsy
== 0)
5612 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5614 switch (fixP
->fx_r_type
)
5616 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5620 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
5621 as_bad (_("unhandled local relocation fix %s"),
5622 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5628 /* The only one we support that isn't an instruction field. */
5629 md_number_to_chars (fixpos
, *valP
, fixP
->fx_size
);
5633 case BFD_RELOC_VTABLE_INHERIT
:
5634 case BFD_RELOC_VTABLE_ENTRY
:
5639 as_bad (_("unhandled local relocation fix %s"),
5640 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5647 md_atof (int type
, char *litP
, int *sizeP
)
5650 LITTLENUM_TYPE words
[4];
5666 return "bad call to md_atof";
5669 t
= atof_ieee (input_line_pointer
, type
, words
);
5671 input_line_pointer
= t
;
5675 for (i
= prec
- 1; i
>= 0; i
--)
5678 if (target_big_endian
)
5679 idx
= (prec
- 1 - i
);
5681 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5690 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5692 return total_frag_text_expansion (fragP
);
5696 /* Translate internal representation of relocation info to BFD target
5700 tc_gen_reloc (asection
*section
, fixS
*fixp
)
5703 bfd_boolean apply_tentative_value
= FALSE
;
5705 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5706 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5707 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5708 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5710 /* Make sure none of our internal relocations make it this far.
5711 They'd better have been fully resolved by this point. */
5712 assert ((int) fixp
->fx_r_type
> 0);
5714 if (linkrelax
&& fixp
->fx_subsy
5715 && (fixp
->fx_r_type
== BFD_RELOC_8
5716 || fixp
->fx_r_type
== BFD_RELOC_16
5717 || fixp
->fx_r_type
== BFD_RELOC_32
))
5720 bfd_vma diff_value
, diff_mask
= 0;
5722 switch (fixp
->fx_r_type
)
5725 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5730 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5735 fixp
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5737 diff_mask
= 0xffffffff;
5743 /* An offset is only allowed when it results from adjusting a local
5744 symbol into a section-relative offset. If the offset came from the
5745 original expression, tc_fix_adjustable will have prevented the fix
5746 from being converted to a section-relative form so that we can flag
5748 if (fixp
->fx_offset
!= 0 && !symbol_section_p (fixp
->fx_addsy
))
5750 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5751 _("cannot represent subtraction with an offset"));
5752 free (reloc
->sym_ptr_ptr
);
5757 assert (S_GET_SEGMENT (fixp
->fx_addsy
)
5758 == S_GET_SEGMENT (fixp
->fx_subsy
));
5760 diff_value
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
5761 - S_GET_VALUE (fixp
->fx_subsy
));
5763 /* Check for overflow. */
5764 if ((diff_value
& ~diff_mask
) != 0)
5766 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5767 _("value of %ld too large"), diff_value
);
5768 free (reloc
->sym_ptr_ptr
);
5773 md_number_to_chars (fixp
->fx_frag
->fr_literal
+ fixp
->fx_where
,
5774 diff_value
, diff_size
);
5775 reloc
->addend
= fixp
->fx_offset
- diff_value
;
5779 reloc
->addend
= fixp
->fx_offset
;
5781 switch (fixp
->fx_r_type
)
5783 case BFD_RELOC_XTENSA_SLOT0_OP
:
5784 case BFD_RELOC_XTENSA_SLOT1_OP
:
5785 case BFD_RELOC_XTENSA_SLOT2_OP
:
5786 case BFD_RELOC_XTENSA_SLOT3_OP
:
5787 case BFD_RELOC_XTENSA_SLOT4_OP
:
5788 case BFD_RELOC_XTENSA_SLOT5_OP
:
5789 case BFD_RELOC_XTENSA_SLOT6_OP
:
5790 case BFD_RELOC_XTENSA_SLOT7_OP
:
5791 case BFD_RELOC_XTENSA_SLOT8_OP
:
5792 case BFD_RELOC_XTENSA_SLOT9_OP
:
5793 case BFD_RELOC_XTENSA_SLOT10_OP
:
5794 case BFD_RELOC_XTENSA_SLOT11_OP
:
5795 case BFD_RELOC_XTENSA_SLOT12_OP
:
5796 case BFD_RELOC_XTENSA_SLOT13_OP
:
5797 case BFD_RELOC_XTENSA_SLOT14_OP
:
5798 /* As a special case, the immediate value for a CONST16 opcode
5799 should not be applied, since this kind of relocation is
5800 handled specially for CONST16 and is not really PC-relative.
5801 Rather than decode the opcode here, just wait and handle it
5802 in xg_apply_tentative_value. */
5803 apply_tentative_value
= TRUE
;
5806 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5807 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5808 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5809 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5810 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5811 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5812 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5813 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5814 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5815 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5816 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5817 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5818 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5819 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5820 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5821 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5823 case BFD_RELOC_XTENSA_PLT
:
5824 case BFD_RELOC_VTABLE_INHERIT
:
5825 case BFD_RELOC_VTABLE_ENTRY
:
5828 case BFD_RELOC_XTENSA_ASM_SIMPLIFY
:
5829 as_warn (_("emitting simplification relocation"));
5833 as_warn (_("emitting unknown relocation"));
5837 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5838 if (reloc
->howto
== NULL
)
5840 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5841 _("cannot represent `%s' relocation in object file"),
5842 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5843 free (reloc
->sym_ptr_ptr
);
5848 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5849 as_fatal (_("internal error? cannot generate `%s' relocation"),
5850 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5852 /* Write the tentative value of a PC-relative relocation to a local symbol
5853 into the instruction. The value will be ignored by the linker, and it
5854 makes the object file disassembly readable when the linkrelax flag is
5855 set and all branch targets are encoded in relocations. */
5857 if (linkrelax
&& apply_tentative_value
&& fixp
->fx_pcrel
)
5860 assert (fixp
->fx_addsy
);
5861 if (S_GET_SEGMENT (fixp
->fx_addsy
) == section
&& !fixp
->fx_plt
5862 && !S_FORCE_RELOC (fixp
->fx_addsy
, 1))
5864 val
= (S_GET_VALUE (fixp
->fx_addsy
) + fixp
->fx_offset
5865 - md_pcrel_from (fixp
));
5866 xg_apply_tentative_value (fixp
, val
);
5874 /* Checks for resource conflicts between instructions. */
5876 /* The func unit stuff could be implemented as bit-vectors rather
5877 than the iterative approach here. If it ends up being too
5878 slow, we will switch it. */
5881 new_resource_table (void *data
,
5884 unit_num_copies_func uncf
,
5885 opcode_num_units_func onuf
,
5886 opcode_funcUnit_use_unit_func ouuf
,
5887 opcode_funcUnit_use_stage_func ousf
)
5890 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5892 rt
->cycles
= cycles
;
5893 rt
->allocated_cycles
= cycles
;
5895 rt
->unit_num_copies
= uncf
;
5896 rt
->opcode_num_units
= onuf
;
5897 rt
->opcode_unit_use
= ouuf
;
5898 rt
->opcode_unit_stage
= ousf
;
5900 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
5901 for (i
= 0; i
< cycles
; i
++)
5902 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
5909 clear_resource_table (resource_table
*rt
)
5912 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5913 for (j
= 0; j
< rt
->num_units
; j
++)
5914 rt
->units
[i
][j
] = 0;
5918 /* We never shrink it, just fake it into thinking so. */
5921 resize_resource_table (resource_table
*rt
, int cycles
)
5925 rt
->cycles
= cycles
;
5926 if (cycles
<= rt
->allocated_cycles
)
5929 old_cycles
= rt
->allocated_cycles
;
5930 rt
->allocated_cycles
= cycles
;
5932 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
5933 for (i
= 0; i
< old_cycles
; i
++)
5934 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
5935 for (i
= old_cycles
; i
< cycles
; i
++)
5936 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
5941 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5944 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5946 for (i
= 0; i
< uses
; i
++)
5948 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5949 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5950 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5951 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5952 if (copies_in_use
>= copies
)
5960 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5963 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5965 for (i
= 0; i
< uses
; i
++)
5967 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5968 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5969 /* Note that this allows resources to be oversubscribed. That's
5970 essential to the way the optional scheduler works.
5971 resources_available reports when a resource is over-subscribed,
5972 so it's easy to tell. */
5973 rt
->units
[stage
+ cycle
][unit
]++;
5979 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5982 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5984 for (i
= 0; i
< uses
; i
++)
5986 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5987 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5988 rt
->units
[stage
+ cycle
][unit
]--;
5989 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
5994 /* Wrapper functions make parameterized resource reservation
5998 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6000 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6006 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6008 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6013 /* Note that this function does not check issue constraints, but
6014 solely whether the hardware is available to execute the given
6015 instructions together. It also doesn't check if the tinsns
6016 write the same state, or access the same tieports. That is
6017 checked by check_t1_t2_reads_and_writes. */
6020 resources_conflict (vliw_insn
*vinsn
)
6023 static resource_table
*rt
= NULL
;
6025 /* This is the most common case by far. Optimize it. */
6026 if (vinsn
->num_slots
== 1)
6031 xtensa_isa isa
= xtensa_default_isa
;
6032 rt
= new_resource_table
6033 (isa
, xtensa_isa_num_pipe_stages (isa
),
6034 xtensa_isa_num_funcUnits (isa
),
6035 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6036 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6037 opcode_funcUnit_use_unit
,
6038 opcode_funcUnit_use_stage
);
6041 clear_resource_table (rt
);
6043 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6045 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6047 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6054 /* finish_vinsn, emit_single_op and helper functions. */
6056 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6057 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6058 static void bundle_single_op (TInsn
*);
6059 static void xg_assemble_vliw_tokens (vliw_insn
*);
6062 /* We have reached the end of a bundle; emit into the frag. */
6065 finish_vinsn (vliw_insn
*vinsn
)
6072 if (find_vinsn_conflicts (vinsn
))
6074 xg_clear_vinsn (vinsn
);
6078 /* First, find a format that works. */
6079 if (vinsn
->format
== XTENSA_UNDEFINED
)
6080 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6082 if (vinsn
->format
== XTENSA_UNDEFINED
)
6084 as_where (&file_name
, &line
);
6085 as_bad_where (file_name
, line
,
6086 _("couldn't find a valid instruction format"));
6087 fprintf (stderr
, _(" ops were: "));
6088 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6089 fprintf (stderr
, _(" %s;"),
6090 xtensa_opcode_name (xtensa_default_isa
,
6091 vinsn
->slots
[i
].opcode
));
6092 fprintf (stderr
, _("\n"));
6093 xg_clear_vinsn (vinsn
);
6097 if (vinsn
->num_slots
6098 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6100 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6101 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6102 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6104 xg_clear_vinsn (vinsn
);
6108 if (resources_conflict (vinsn
))
6110 as_where (&file_name
, &line
);
6111 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6112 fprintf (stderr
, " ops were: ");
6113 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6114 fprintf (stderr
, " %s;",
6115 xtensa_opcode_name (xtensa_default_isa
,
6116 vinsn
->slots
[i
].opcode
));
6117 fprintf (stderr
, "\n");
6118 xg_clear_vinsn (vinsn
);
6122 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6124 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6126 symbolS
*lit_sym
= NULL
;
6128 bfd_boolean e
= FALSE
;
6129 bfd_boolean saved_density
= density_supported
;
6131 /* We don't want to narrow ops inside multi-slot bundles. */
6132 if (vinsn
->num_slots
> 1)
6133 density_supported
= FALSE
;
6135 istack_init (&slotstack
);
6136 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6138 vinsn
->slots
[i
].opcode
=
6139 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6141 vinsn
->slots
[i
].ntok
= 0;
6144 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6150 density_supported
= saved_density
;
6154 xg_clear_vinsn (vinsn
);
6158 for (j
= 0; j
< slotstack
.ninsn
- 1; j
++)
6160 TInsn
*insn
= &slotstack
.insn
[j
];
6161 if (insn
->insn_type
== ITYPE_LITERAL
)
6163 assert (lit_sym
== NULL
);
6164 lit_sym
= xg_assemble_literal (insn
);
6169 xg_resolve_literals (insn
, lit_sym
);
6170 emit_single_op (insn
);
6174 if (vinsn
->num_slots
> 1)
6176 if (opcode_fits_format_slot
6177 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6180 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6184 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6185 if (vinsn
->format
== XTENSA_UNDEFINED
)
6186 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6188 vinsn
->slots
[i
].opcode
6189 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6192 vinsn
->slots
[i
].ntok
= 0;
6197 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6198 vinsn
->format
= XTENSA_UNDEFINED
;
6203 /* Now check resource conflicts on the modified bundle. */
6204 if (resources_conflict (vinsn
))
6206 as_where (&file_name
, &line
);
6207 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6208 fprintf (stderr
, " ops were: ");
6209 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6210 fprintf (stderr
, " %s;",
6211 xtensa_opcode_name (xtensa_default_isa
,
6212 vinsn
->slots
[i
].opcode
));
6213 fprintf (stderr
, "\n");
6214 xg_clear_vinsn (vinsn
);
6218 /* First, find a format that works. */
6219 if (vinsn
->format
== XTENSA_UNDEFINED
)
6220 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6222 xg_assemble_vliw_tokens (vinsn
);
6224 xg_clear_vinsn (vinsn
);
6228 /* Given an vliw instruction, what conflicts are there in register
6229 usage and in writes to states and queues?
6231 This function does two things:
6232 1. Reports an error when a vinsn contains illegal combinations
6233 of writes to registers states or queues.
6234 2. Marks individual tinsns as not relaxable if the combination
6235 contains antidependencies.
6237 Job 2 handles things like swap semantics in instructions that need
6238 to be relaxed. For example,
6242 normally would be relaxed to
6247 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6249 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6251 then we can't relax it into
6254 { add a0, a1, a0 ; add a2, a0, a4 ; }
6256 because the value of a0 is trashed before the second add can read it. */
6258 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6261 find_vinsn_conflicts (vliw_insn
*vinsn
)
6265 xtensa_isa isa
= xtensa_default_isa
;
6267 assert (!past_xtensa_end
);
6269 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6271 TInsn
*op1
= &vinsn
->slots
[i
];
6272 if (op1
->is_specific_opcode
)
6273 op1
->keep_wide
= TRUE
;
6275 op1
->keep_wide
= FALSE
;
6278 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6280 TInsn
*op1
= &vinsn
->slots
[i
];
6282 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6285 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6289 TInsn
*op2
= &vinsn
->slots
[j
];
6290 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6291 switch (conflict_type
)
6294 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6295 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6296 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6299 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6300 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6301 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6304 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6305 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6306 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6309 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6310 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6311 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6314 /* Everything is OK. */
6317 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6318 || conflict_type
== 'a');
6325 as_bad (_("multiple branches or jumps in the same bundle"));
6333 /* Check how the state used by t1 and t2 relate.
6336 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6337 case B: no relationship between what is read and written (both could
6338 read the same reg though)
6339 case C: t1 writes a register t2 writes (a register conflict within a
6341 case D: t1 writes a state that t2 also writes
6342 case E: t1 writes a tie queue that t2 also writes
6343 case F: two volatile queue accesses
6347 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6349 xtensa_isa isa
= xtensa_default_isa
;
6350 xtensa_regfile t1_regfile
, t2_regfile
;
6352 int t1_base_reg
, t1_last_reg
;
6353 int t2_base_reg
, t2_last_reg
;
6354 char t1_inout
, t2_inout
;
6356 char conflict
= 'b';
6361 bfd_boolean t1_volatile
= FALSE
;
6362 bfd_boolean t2_volatile
= FALSE
;
6364 /* Check registers. */
6365 for (j
= 0; j
< t2
->ntok
; j
++)
6367 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6370 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6371 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6372 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6374 for (i
= 0; i
< t1
->ntok
; i
++)
6376 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6379 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6381 if (t1_regfile
!= t2_regfile
)
6384 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6385 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6387 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6388 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6390 if (t1_inout
== 'm' || t1_inout
== 'o'
6391 || t2_inout
== 'm' || t2_inout
== 'o')
6398 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6399 t1_last_reg
= (t1_base_reg
6400 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6402 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6404 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6406 if (t1_reg
!= t2_reg
)
6409 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6415 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6421 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6429 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6430 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6431 for (j
= 0; j
< t2_states
; j
++)
6433 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6434 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6435 for (i
= 0; i
< t1_states
; i
++)
6437 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6438 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6442 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6448 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6454 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6459 /* Check tieports. */
6460 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6461 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6462 for (j
= 0; j
< t2_interfaces
; j
++)
6464 xtensa_interface t2_int
6465 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6466 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6468 t2_inout
= xtensa_interface_inout (isa
, j
);
6469 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6472 for (i
= 0; i
< t1_interfaces
; i
++)
6474 xtensa_interface t1_int
6475 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6476 int t1_class
= xtensa_interface_class_id (isa
, t2_int
);
6478 t1_inout
= xtensa_interface_inout (isa
, i
);
6479 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6482 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6485 if (t1_int
!= t2_int
)
6488 if (t2_inout
== 'i' && t1_inout
== 'o')
6494 if (t1_inout
== 'i' && t2_inout
== 'o')
6500 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6509 static xtensa_format
6510 xg_find_narrowest_format (vliw_insn
*vinsn
)
6512 /* Right now we assume that the ops within the vinsn are properly
6513 ordered for the slots that the programmer wanted them in. In
6514 other words, we don't rearrange the ops in hopes of finding a
6515 better format. The scheduler handles that. */
6517 xtensa_isa isa
= xtensa_default_isa
;
6518 xtensa_format format
;
6519 vliw_insn v_copy
= *vinsn
;
6520 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6522 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6525 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6529 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6531 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6533 v_copy
.slots
[slot
].opcode
=
6534 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6535 v_copy
.slots
[slot
].ntok
= 0;
6538 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6541 else if (v_copy
.num_slots
> 1)
6544 /* Try the widened version. */
6545 if (!v_copy
.slots
[slot
].keep_wide
6546 && !v_copy
.slots
[slot
].is_specific_opcode
6547 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
6548 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
6549 && opcode_fits_format_slot (widened
.opcode
,
6552 /* The xg_is_narrow clause requires some explanation:
6554 addi can be "widened" to an addmi, which is then
6555 expanded to an addmi/addi pair if the immediate
6556 requires it, but here we must have a single widen
6559 xg_is_narrow tells us that addi isn't really
6560 narrow. The widen_spec_list says that there are
6563 v_copy
.slots
[slot
] = widened
;
6568 if (fit
== v_copy
.num_slots
)
6571 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6572 vinsn
->format
= format
;
6578 if (format
== xtensa_isa_num_formats (isa
))
6579 return XTENSA_UNDEFINED
;
6585 /* Return the additional space needed in a frag
6586 for possible relaxations of any ops in a VLIW insn.
6587 Also fill out the relaxations that might be required of
6588 each tinsn in the vinsn. */
6591 relaxation_requirements (vliw_insn
*vinsn
)
6593 int extra_space
= 0;
6596 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6598 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6599 if (!tinsn_has_symbolic_operands (tinsn
))
6601 /* A narrow instruction could be widened later to help
6602 alignment issues. */
6603 if (xg_is_narrow_insn (tinsn
)
6604 && !tinsn
->is_specific_opcode
6605 && vinsn
->num_slots
== 1)
6607 /* Difference in bytes between narrow and wide insns... */
6609 tinsn
->subtype
= RELAX_NARROW
;
6610 tinsn
->record_fix
= TRUE
;
6615 tinsn
->record_fix
= FALSE
;
6616 /* No extra_space needed. */
6621 if (workaround_b_j_loop_end
6622 && tinsn
->opcode
== xtensa_jx_opcode
6623 && use_transform ())
6625 /* Add 2 of these. */
6626 extra_space
+= 3; /* for the nop size */
6627 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6630 /* Need to assemble it with space for the relocation. */
6631 if (xg_is_relaxable_insn (tinsn
, 0)
6632 && !tinsn
->is_specific_opcode
)
6634 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6635 int max_literal_size
=
6636 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6638 tinsn
->literal_space
= max_literal_size
;
6640 tinsn
->subtype
= RELAX_IMMED
;
6641 tinsn
->record_fix
= FALSE
;
6642 extra_space
+= max_size
;
6646 tinsn
->record_fix
= TRUE
;
6647 /* No extra space needed. */
6656 bundle_single_op (TInsn
*orig_insn
)
6658 xtensa_isa isa
= xtensa_default_isa
;
6663 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6664 assert (v
.format
!= XTENSA_UNDEFINED
);
6665 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6668 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6671 v
.slots
[slot
].opcode
=
6672 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6673 v
.slots
[slot
].ntok
= 0;
6674 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6677 v
.slots
[slot
] = *orig_insn
;
6680 for ( ; slot
< v
.num_slots
; slot
++)
6682 v
.slots
[slot
].opcode
=
6683 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6684 v
.slots
[slot
].ntok
= 0;
6685 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6694 emit_single_op (TInsn
*orig_insn
)
6697 IStack istack
; /* put instructions into here */
6698 symbolS
*lit_sym
= NULL
;
6699 symbolS
*label_sym
= NULL
;
6701 istack_init (&istack
);
6703 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6704 Because the scheduling and bundling characteristics of movi and
6705 l32r or const16 are so different, we can do much better if we relax
6706 it prior to scheduling and bundling, rather than after. */
6707 if ((orig_insn
->opcode
== xtensa_movi_opcode
6708 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6709 && !cur_vinsn
.inside_bundle
6710 && (orig_insn
->tok
[1].X_op
== O_symbol
6711 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6712 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6714 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6717 for (i
= 0; i
< istack
.ninsn
; i
++)
6719 TInsn
*insn
= &istack
.insn
[i
];
6720 switch (insn
->insn_type
)
6723 assert (lit_sym
== NULL
);
6724 lit_sym
= xg_assemble_literal (insn
);
6728 static int relaxed_sym_idx
= 0;
6729 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6730 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6732 assert (label_sym
== NULL
);
6733 label_sym
= symbol_find_or_make (label
);
6740 xg_resolve_literals (insn
, lit_sym
);
6742 xg_resolve_labels (insn
, label_sym
);
6743 bundle_single_op (insn
);
6755 total_frag_text_expansion (fragS
*fragP
)
6758 int total_expansion
= 0;
6760 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6761 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6763 return total_expansion
;
6767 /* Emit a vliw instruction to the current fragment. */
6770 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6772 bfd_boolean finish_frag
= FALSE
;
6773 bfd_boolean is_jump
= FALSE
;
6774 bfd_boolean is_branch
= FALSE
;
6775 xtensa_isa isa
= xtensa_default_isa
;
6781 struct dwarf2_line_info best_loc
;
6783 best_loc
.line
= INT_MAX
;
6785 if (generating_literals
)
6787 static int reported
= 0;
6789 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6790 _("cannot assemble into a literal fragment"));
6797 if (frag_now_fix () != 0
6798 && (! frag_now
->tc_frag_data
.is_insn
6799 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6800 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6801 || (directive_state
[directive_absolute_literals
]
6802 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6804 frag_wane (frag_now
);
6806 xtensa_set_frag_assembly_state (frag_now
);
6809 if (workaround_a0_b_retw
6810 && vinsn
->num_slots
== 1
6811 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6812 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6813 && use_transform ())
6815 has_a0_b_retw
= TRUE
;
6817 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6818 After the first assembly pass we will check all of them and
6819 add a nop if needed. */
6820 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6821 frag_var (rs_machine_dependent
, 4, 4,
6822 RELAX_ADD_NOP_IF_A0_B_RETW
,
6823 frag_now
->fr_symbol
,
6824 frag_now
->fr_offset
,
6826 xtensa_set_frag_assembly_state (frag_now
);
6827 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6828 frag_var (rs_machine_dependent
, 4, 4,
6829 RELAX_ADD_NOP_IF_A0_B_RETW
,
6830 frag_now
->fr_symbol
,
6831 frag_now
->fr_offset
,
6833 xtensa_set_frag_assembly_state (frag_now
);
6836 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6838 /* See if the instruction implies an aligned section. */
6839 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6840 record_alignment (now_seg
, 2);
6842 /* Also determine the best line number for debug info. */
6843 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6844 ? vinsn
->slots
[i
].loc
: best_loc
;
6847 /* Special cases for instructions that force an alignment... */
6848 /* None of these opcodes are bundle-able. */
6849 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6853 xtensa_set_frag_assembly_state (frag_now
);
6854 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6856 max_fill
= get_text_align_max_fill_size
6857 (get_text_align_power (xtensa_fetch_width
),
6858 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6860 if (use_transform ())
6861 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6862 RELAX_ALIGN_NEXT_OPCODE
,
6863 frag_now
->fr_symbol
,
6864 frag_now
->fr_offset
,
6867 frag_var (rs_machine_dependent
, 0, 0,
6868 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6869 xtensa_set_frag_assembly_state (frag_now
);
6871 xtensa_move_labels (frag_now
, 0, FALSE
);
6874 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6875 && !vinsn
->slots
[0].is_specific_opcode
)
6877 xtensa_mark_literal_pool_location ();
6878 xtensa_move_labels (frag_now
, 0, TRUE
);
6879 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6882 if (vinsn
->num_slots
== 1)
6884 if (workaround_a0_b_retw
&& use_transform ())
6885 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6886 is_register_writer (&vinsn
->slots
[0], "a", 0));
6888 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6889 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6892 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6894 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6896 extra_space
= relaxation_requirements (vinsn
);
6898 /* vinsn_to_insnbuf will produce the error. */
6899 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6901 f
= (char *) frag_more (insn_size
+ extra_space
);
6902 xtensa_set_frag_assembly_state (frag_now
);
6903 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6906 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6907 if (vinsn
->format
== XTENSA_UNDEFINED
)
6910 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, f
, 0);
6912 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
6914 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6916 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6917 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6918 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6919 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6920 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6921 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6922 if (tinsn
->literal_space
!= 0)
6923 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6925 if (tinsn
->subtype
== RELAX_NARROW
)
6926 assert (vinsn
->num_slots
== 1);
6927 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6929 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6932 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6933 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6937 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6938 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6942 frag_variant (rs_machine_dependent
,
6943 extra_space
, extra_space
, RELAX_SLOTS
,
6944 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6945 xtensa_set_frag_assembly_state (frag_now
);
6948 /* Special cases for loops:
6949 close_loop_end should be inserted AFTER short_loop.
6950 Make sure that CLOSE loops are processed BEFORE short_loops
6951 when converting them. */
6953 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6954 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6955 && !vinsn
->slots
[0].is_specific_opcode
)
6957 if (workaround_short_loop
&& use_transform ())
6959 maybe_has_short_loop
= TRUE
;
6960 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6961 frag_var (rs_machine_dependent
, 4, 4,
6962 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6963 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6964 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6965 frag_var (rs_machine_dependent
, 4, 4,
6966 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6967 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6970 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6971 loop at least 12 bytes away from another loop's end. */
6972 if (workaround_close_loop_end
&& use_transform ())
6974 maybe_has_close_loop_end
= TRUE
;
6975 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6976 frag_var (rs_machine_dependent
, 12, 12,
6977 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6978 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6982 if (use_transform ())
6986 assert (finish_frag
);
6987 frag_var (rs_machine_dependent
,
6988 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6990 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6991 xtensa_set_frag_assembly_state (frag_now
);
6993 else if (is_branch
&& align_targets
)
6995 assert (finish_frag
);
6996 frag_var (rs_machine_dependent
,
6997 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6998 RELAX_MAYBE_UNREACHABLE
,
6999 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7000 xtensa_set_frag_assembly_state (frag_now
);
7001 frag_var (rs_machine_dependent
,
7003 RELAX_MAYBE_DESIRE_ALIGN
,
7004 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7005 xtensa_set_frag_assembly_state (frag_now
);
7009 /* Now, if the original opcode was a call... */
7010 if (do_align_targets ()
7011 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7013 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7014 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7015 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7016 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7017 xtensa_set_frag_assembly_state (frag_now
);
7020 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7022 frag_wane (frag_now
);
7024 xtensa_set_frag_assembly_state (frag_now
);
7029 /* xtensa_end and helper functions. */
7031 static void xtensa_cleanup_align_frags (void);
7032 static void xtensa_fix_target_frags (void);
7033 static void xtensa_mark_narrow_branches (void);
7034 static void xtensa_mark_zcl_first_insns (void);
7035 static void xtensa_fix_a0_b_retw_frags (void);
7036 static void xtensa_fix_b_j_loop_end_frags (void);
7037 static void xtensa_fix_close_loop_end_frags (void);
7038 static void xtensa_fix_short_loop_frags (void);
7039 static void xtensa_sanity_check (void);
7044 directive_balance ();
7045 xtensa_flush_pending_output ();
7047 past_xtensa_end
= TRUE
;
7049 xtensa_move_literals ();
7051 xtensa_reorder_segments ();
7052 xtensa_cleanup_align_frags ();
7053 xtensa_fix_target_frags ();
7054 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7055 xtensa_fix_a0_b_retw_frags ();
7056 if (workaround_b_j_loop_end
)
7057 xtensa_fix_b_j_loop_end_frags ();
7059 /* "close_loop_end" should be processed BEFORE "short_loop". */
7060 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7061 xtensa_fix_close_loop_end_frags ();
7063 if (workaround_short_loop
&& maybe_has_short_loop
)
7064 xtensa_fix_short_loop_frags ();
7065 xtensa_mark_narrow_branches ();
7066 xtensa_mark_zcl_first_insns ();
7068 xtensa_sanity_check ();
7073 xtensa_cleanup_align_frags (void)
7077 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7080 /* Walk over all of the fragments in a subsection. */
7081 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7083 if ((fragP
->fr_type
== rs_align
7084 || fragP
->fr_type
== rs_align_code
7085 || (fragP
->fr_type
== rs_machine_dependent
7086 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7087 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7088 && fragP
->fr_fix
== 0)
7090 fragS
*next
= fragP
->fr_next
;
7093 && next
->fr_fix
== 0
7094 && next
->fr_type
== rs_machine_dependent
7095 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7098 next
= next
->fr_next
;
7101 /* If we don't widen branch targets, then they
7102 will be easier to align. */
7103 if (fragP
->tc_frag_data
.is_branch_target
7104 && fragP
->fr_opcode
== fragP
->fr_literal
7105 && fragP
->fr_type
== rs_machine_dependent
7106 && fragP
->fr_subtype
== RELAX_SLOTS
7107 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7109 if (fragP
->fr_type
== rs_machine_dependent
7110 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7111 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7117 /* Re-process all of the fragments looking to convert all of the
7118 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7119 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7120 If the next fragment starts with a loop target, AND the previous
7121 fragment can be expanded to negate the branch, convert this to a
7122 RELAX_LOOP_END. Otherwise, convert to a .fill 0. */
7124 static bfd_boolean
frag_can_negate_branch (fragS
*);
7127 xtensa_fix_target_frags (void)
7131 /* When this routine is called, all of the subsections are still intact
7132 so we walk over subsections instead of sections. */
7133 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7135 bfd_boolean prev_frag_can_negate_branch
= FALSE
;
7138 /* Walk over all of the fragments in a subsection. */
7139 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7141 if (fragP
->fr_type
== rs_machine_dependent
7142 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7144 if (next_frag_is_loop_target (fragP
))
7146 if (prev_frag_can_negate_branch
)
7148 fragP
->fr_subtype
= RELAX_LOOP_END
;
7149 /* See the comment near the frag_var with a
7150 RELAX_DESIRE_ALIGN to see why we do this. */
7151 fragP
->fr_var
= RELAX_LOOP_END_BYTES
;
7155 if (next_frag_is_branch_target (fragP
))
7156 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7161 else if (next_frag_is_branch_target (fragP
))
7162 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7166 if (fragP
->fr_fix
!= 0)
7167 prev_frag_can_negate_branch
= FALSE
;
7168 if (frag_can_negate_branch (fragP
))
7169 prev_frag_can_negate_branch
= TRUE
;
7176 frag_can_negate_branch (fragS
*fragP
)
7178 xtensa_isa isa
= xtensa_default_isa
;
7182 if (fragP
->fr_type
!= rs_machine_dependent
7183 || fragP
->fr_subtype
!= RELAX_SLOTS
)
7186 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7188 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, vinsn
.format
); slot
++)
7190 if ((fragP
->tc_frag_data
.slot_subtypes
[slot
] == RELAX_IMMED
)
7191 && xtensa_opcode_is_branch (isa
, vinsn
.slots
[slot
].opcode
) == 1)
7199 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7202 xtensa_mark_narrow_branches (void)
7206 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7209 /* Walk over all of the fragments in a subsection. */
7210 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7212 if (fragP
->fr_type
== rs_machine_dependent
7213 && fragP
->fr_subtype
== RELAX_SLOTS
7214 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7217 const expressionS
*expr
;
7220 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7221 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7223 expr
= &vinsn
.slots
[0].tok
[1];
7224 symbolP
= expr
->X_add_symbol
;
7226 if (vinsn
.num_slots
== 1
7227 && xtensa_opcode_is_branch (xtensa_default_isa
,
7228 vinsn
.slots
[0].opcode
)
7229 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7230 && is_narrow_branch_guaranteed_in_range (fragP
,
7233 fragP
->fr_subtype
= RELAX_SLOTS
;
7234 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7242 /* A branch is typically widened only when its target is out of
7243 range. However, we would like to widen them to align a subsequent
7244 branch target when possible.
7246 Because the branch relaxation code is so convoluted, the optimal solution
7247 (combining the two cases) is difficult to get right in all circumstances.
7248 We therefore go with an "almost as good" solution, where we only
7249 use for alignment narrow branches that definitely will not expand to a
7250 jump and a branch. These functions find and mark these cases. */
7252 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7253 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7254 We start counting beginning with the frag after the 2-byte branch, so the
7255 maximum offset is (4 - 2) + 63 = 65. */
7256 #define MAX_IMMED6 65
7258 static size_t unrelaxed_frag_max_size (fragS
*);
7261 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7263 const expressionS
*expr
= &tinsn
->tok
[1];
7264 symbolS
*symbolP
= expr
->X_add_symbol
;
7265 fragS
*target_frag
= symbol_get_frag (symbolP
);
7266 size_t max_distance
= expr
->X_add_number
;
7267 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7268 if (is_branch_jmp_to_next (tinsn
, fragP
))
7271 /* The branch doesn't branch over it's own frag,
7272 but over the subsequent ones. */
7273 fragP
= fragP
->fr_next
;
7274 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7276 max_distance
+= unrelaxed_frag_max_size (fragP
);
7277 fragP
= fragP
->fr_next
;
7279 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7286 xtensa_mark_zcl_first_insns (void)
7290 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7293 /* Walk over all of the fragments in a subsection. */
7294 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7296 if (fragP
->fr_type
== rs_machine_dependent
7297 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7298 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7300 /* Find the loop frag. */
7301 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7302 /* Find the first insn frag. */
7303 targ_frag
= next_non_empty_frag (targ_frag
);
7305 /* Of course, sometimes (mostly for toy test cases) a
7306 zero-cost loop instruction is the last in a section. */
7309 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7310 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7319 /* Re-process all of the fragments looking to convert all of the
7320 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7321 conditional branch or a retw/retw.n, convert this frag to one that
7322 will generate a NOP. In any case close it off with a .fill 0. */
7324 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7327 xtensa_fix_a0_b_retw_frags (void)
7331 /* When this routine is called, all of the subsections are still intact
7332 so we walk over subsections instead of sections. */
7333 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7337 /* Walk over all of the fragments in a subsection. */
7338 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7340 if (fragP
->fr_type
== rs_machine_dependent
7341 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7343 if (next_instrs_are_b_retw (fragP
))
7345 if (fragP
->tc_frag_data
.is_no_transform
)
7346 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7348 relax_frag_add_nop (fragP
);
7358 next_instrs_are_b_retw (fragS
*fragP
)
7360 xtensa_opcode opcode
;
7362 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7363 static xtensa_insnbuf insnbuf
= NULL
;
7364 static xtensa_insnbuf slotbuf
= NULL
;
7365 xtensa_isa isa
= xtensa_default_isa
;
7368 bfd_boolean branch_seen
= FALSE
;
7372 insnbuf
= xtensa_insnbuf_alloc (isa
);
7373 slotbuf
= xtensa_insnbuf_alloc (isa
);
7376 if (next_fragP
== NULL
)
7379 /* Check for the conditional branch. */
7380 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7381 fmt
= xtensa_format_decode (isa
, insnbuf
);
7382 if (fmt
== XTENSA_UNDEFINED
)
7385 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7387 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7388 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7390 branch_seen
= (branch_seen
7391 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7397 offset
+= xtensa_format_length (isa
, fmt
);
7398 if (offset
== next_fragP
->fr_fix
)
7400 next_fragP
= next_non_empty_frag (next_fragP
);
7404 if (next_fragP
== NULL
)
7407 /* Check for the retw/retw.n. */
7408 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7409 fmt
= xtensa_format_decode (isa
, insnbuf
);
7411 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7412 have no problems. */
7413 if (fmt
== XTENSA_UNDEFINED
7414 || xtensa_format_num_slots (isa
, fmt
) != 1)
7417 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7418 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7420 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7427 /* Re-process all of the fragments looking to convert all of the
7428 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7429 loop end label, convert this frag to one that will generate a NOP.
7430 In any case close it off with a .fill 0. */
7432 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7435 xtensa_fix_b_j_loop_end_frags (void)
7439 /* When this routine is called, all of the subsections are still intact
7440 so we walk over subsections instead of sections. */
7441 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7445 /* Walk over all of the fragments in a subsection. */
7446 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7448 if (fragP
->fr_type
== rs_machine_dependent
7449 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7451 if (next_instr_is_loop_end (fragP
))
7453 if (fragP
->tc_frag_data
.is_no_transform
)
7454 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7456 relax_frag_add_nop (fragP
);
7466 next_instr_is_loop_end (fragS
*fragP
)
7468 const fragS
*next_fragP
;
7470 if (next_frag_is_loop_target (fragP
))
7473 next_fragP
= next_non_empty_frag (fragP
);
7474 if (next_fragP
== NULL
)
7477 if (!next_frag_is_loop_target (next_fragP
))
7480 /* If the size is >= 3 then there is more than one instruction here.
7481 The hardware bug will not fire. */
7482 if (next_fragP
->fr_fix
> 3)
7489 /* Re-process all of the fragments looking to convert all of the
7490 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7491 not MY loop's loop end within 12 bytes, add enough nops here to
7492 make it at least 12 bytes away. In any case close it off with a
7495 static size_t min_bytes_to_other_loop_end (fragS
*, fragS
*, offsetT
, size_t);
7498 xtensa_fix_close_loop_end_frags (void)
7502 /* When this routine is called, all of the subsections are still intact
7503 so we walk over subsections instead of sections. */
7504 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7508 fragS
*current_target
= NULL
;
7509 offsetT current_offset
= 0;
7511 /* Walk over all of the fragments in a subsection. */
7512 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7514 if (fragP
->fr_type
== rs_machine_dependent
7515 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7516 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7517 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7520 /* Read it. If the instruction is a loop, get the target. */
7522 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7523 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7524 t_insn
.opcode
) == 1)
7526 /* Get the current fragment target. */
7527 if (fragP
->tc_frag_data
.slot_symbols
[0])
7529 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7530 current_target
= symbol_get_frag (sym
);
7531 current_offset
= fragP
->fr_offset
;
7537 && fragP
->fr_type
== rs_machine_dependent
7538 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7541 size_t bytes_added
= 0;
7543 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7544 /* Max out at 12. */
7545 min_bytes
= min_bytes_to_other_loop_end
7546 (fragP
->fr_next
, current_target
, current_offset
,
7547 REQUIRED_LOOP_DIVIDING_BYTES
);
7549 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7551 if (fragP
->tc_frag_data
.is_no_transform
)
7552 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7555 while (min_bytes
+ bytes_added
7556 < REQUIRED_LOOP_DIVIDING_BYTES
)
7560 if (fragP
->fr_var
< length
)
7561 as_fatal (_("fr_var %lu < length %d"),
7562 fragP
->fr_var
, length
);
7565 assemble_nop (length
,
7566 fragP
->fr_literal
+ fragP
->fr_fix
);
7567 fragP
->fr_fix
+= length
;
7568 fragP
->fr_var
-= length
;
7570 bytes_added
+= length
;
7576 assert (fragP
->fr_type
!= rs_machine_dependent
7577 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7583 static size_t unrelaxed_frag_min_size (fragS
*);
7586 min_bytes_to_other_loop_end (fragS
*fragP
,
7587 fragS
*current_target
,
7588 offsetT current_offset
,
7592 fragS
*current_fragP
;
7594 for (current_fragP
= fragP
;
7596 current_fragP
= current_fragP
->fr_next
)
7598 if (current_fragP
->tc_frag_data
.is_loop_target
7599 && current_fragP
!= current_target
)
7600 return offset
+ current_offset
;
7602 offset
+= unrelaxed_frag_min_size (current_fragP
);
7604 if (offset
+ current_offset
>= max_size
)
7612 unrelaxed_frag_min_size (fragS
*fragP
)
7614 size_t size
= fragP
->fr_fix
;
7617 if (fragP
->fr_type
== rs_fill
)
7618 size
+= fragP
->fr_offset
;
7625 unrelaxed_frag_max_size (fragS
*fragP
)
7627 size_t size
= fragP
->fr_fix
;
7628 switch (fragP
->fr_type
)
7631 /* Empty frags created by the obstack allocation scheme
7632 end up with type 0. */
7637 size
+= fragP
->fr_offset
;
7645 /* No further adjustments needed. */
7647 case rs_machine_dependent
:
7648 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7649 size
+= fragP
->fr_var
;
7652 /* We had darn well better know how big it is. */
7661 /* Re-process all of the fragments looking to convert all
7662 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7665 1) the instruction size count to the loop end label
7666 is too short (<= 2 instructions),
7667 2) loop has a jump or branch in it
7670 1) workaround_all_short_loops is TRUE
7671 2) The generating loop was a 'loopgtz' or 'loopnez'
7672 3) the instruction size count to the loop end label is too short
7674 then convert this frag (and maybe the next one) to generate a NOP.
7675 In any case close it off with a .fill 0. */
7677 static size_t count_insns_to_loop_end (fragS
*, bfd_boolean
, size_t);
7678 static bfd_boolean
branch_before_loop_end (fragS
*);
7681 xtensa_fix_short_loop_frags (void)
7685 /* When this routine is called, all of the subsections are still intact
7686 so we walk over subsections instead of sections. */
7687 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7690 fragS
*current_target
= NULL
;
7691 offsetT current_offset
= 0;
7692 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7694 /* Walk over all of the fragments in a subsection. */
7695 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7697 /* Check on the current loop. */
7698 if (fragP
->fr_type
== rs_machine_dependent
7699 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7700 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7701 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7706 /* Read it. If the instruction is a loop, get the target. */
7707 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7708 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7709 t_insn
.opcode
) == 1)
7711 /* Get the current fragment target. */
7712 if (fragP
->tc_frag_data
.slot_symbols
[0])
7714 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7715 current_target
= symbol_get_frag (sym
);
7716 current_offset
= fragP
->fr_offset
;
7717 current_opcode
= t_insn
.opcode
;
7722 if (fragP
->fr_type
== rs_machine_dependent
7723 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7726 count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3);
7728 && (branch_before_loop_end (fragP
->fr_next
)
7729 || (workaround_all_short_loops
7730 && current_opcode
!= XTENSA_UNDEFINED
7731 && current_opcode
!= xtensa_loop_opcode
)))
7733 if (fragP
->tc_frag_data
.is_no_transform
)
7734 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7736 relax_frag_add_nop (fragP
);
7745 static size_t unrelaxed_frag_min_insn_count (fragS
*);
7748 count_insns_to_loop_end (fragS
*base_fragP
,
7749 bfd_boolean count_relax_add
,
7752 fragS
*fragP
= NULL
;
7753 size_t insn_count
= 0;
7757 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7759 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7760 if (insn_count
>= max_count
)
7763 if (count_relax_add
)
7765 if (fragP
->fr_type
== rs_machine_dependent
7766 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7768 /* In order to add the appropriate number of
7769 NOPs, we count an instruction for downstream
7772 if (insn_count
>= max_count
)
7782 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7784 xtensa_isa isa
= xtensa_default_isa
;
7785 static xtensa_insnbuf insnbuf
= NULL
;
7786 size_t insn_count
= 0;
7789 if (!fragP
->tc_frag_data
.is_insn
)
7793 insnbuf
= xtensa_insnbuf_alloc (isa
);
7795 /* Decode the fixed instructions. */
7796 while (offset
< fragP
->fr_fix
)
7800 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7801 fmt
= xtensa_format_decode (isa
, insnbuf
);
7803 if (fmt
== XTENSA_UNDEFINED
)
7805 as_fatal (_("undecodable instruction in instruction frag"));
7808 offset
+= xtensa_format_length (isa
, fmt
);
7816 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7819 branch_before_loop_end (fragS
*base_fragP
)
7823 for (fragP
= base_fragP
;
7824 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7825 fragP
= fragP
->fr_next
)
7827 if (unrelaxed_frag_has_b_j (fragP
))
7835 unrelaxed_frag_has_b_j (fragS
*fragP
)
7837 static xtensa_insnbuf insnbuf
= NULL
;
7838 xtensa_isa isa
= xtensa_default_isa
;
7841 if (!fragP
->tc_frag_data
.is_insn
)
7845 insnbuf
= xtensa_insnbuf_alloc (isa
);
7847 /* Decode the fixed instructions. */
7848 while (offset
< fragP
->fr_fix
)
7853 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7854 fmt
= xtensa_format_decode (isa
, insnbuf
);
7855 if (fmt
== XTENSA_UNDEFINED
)
7858 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7860 xtensa_opcode opcode
=
7861 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7862 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7863 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7866 offset
+= xtensa_format_length (isa
, fmt
);
7872 /* Checks to be made after initial assembly but before relaxation. */
7874 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7875 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7878 xtensa_sanity_check (void)
7885 as_where (&file_name
, &line
);
7886 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7890 /* Walk over all of the fragments in a subsection. */
7891 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7893 /* Currently we only check for empty loops here. */
7894 if (fragP
->fr_type
== rs_machine_dependent
7895 && fragP
->fr_subtype
== RELAX_IMMED
)
7897 static xtensa_insnbuf insnbuf
= NULL
;
7900 if (fragP
->fr_opcode
!= NULL
)
7903 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7904 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7905 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7907 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7908 t_insn
.opcode
) == 1)
7910 if (is_empty_loop (&t_insn
, fragP
))
7912 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7913 as_bad (_("invalid empty loop"));
7915 if (!is_local_forward_loop (&t_insn
, fragP
))
7917 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7918 as_bad (_("loop target does not follow "
7919 "loop instruction in section"));
7926 new_logical_line (file_name
, line
);
7930 #define LOOP_IMMED_OPN 1
7932 /* Return TRUE if the loop target is the next non-zero fragment. */
7935 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7937 const expressionS
*expr
;
7941 if (insn
->insn_type
!= ITYPE_INSN
)
7944 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7947 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7950 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7952 if (expr
->X_op
!= O_symbol
)
7955 symbolP
= expr
->X_add_symbol
;
7959 if (symbol_get_frag (symbolP
) == NULL
)
7962 if (S_GET_VALUE (symbolP
) != 0)
7965 /* Walk through the zero-size fragments from this one. If we find
7966 the target fragment, then this is a zero-size loop. */
7968 for (next_fragP
= fragP
->fr_next
;
7970 next_fragP
= next_fragP
->fr_next
)
7972 if (next_fragP
== symbol_get_frag (symbolP
))
7974 if (next_fragP
->fr_fix
!= 0)
7982 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7984 const expressionS
*expr
;
7988 if (insn
->insn_type
!= ITYPE_INSN
)
7991 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7994 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7997 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7999 if (expr
->X_op
!= O_symbol
)
8002 symbolP
= expr
->X_add_symbol
;
8006 if (symbol_get_frag (symbolP
) == NULL
)
8009 /* Walk through fragments until we find the target.
8010 If we do not find the target, then this is an invalid loop. */
8012 for (next_fragP
= fragP
->fr_next
;
8014 next_fragP
= next_fragP
->fr_next
)
8016 if (next_fragP
== symbol_get_frag (symbolP
))
8024 /* Alignment Functions. */
8027 get_text_align_power (int target_size
)
8030 for (i
= 0; i
< sizeof (size_t); i
++)
8032 if (target_size
<= (1 << i
))
8041 get_text_align_max_fill_size (int align_pow
,
8042 bfd_boolean use_nops
,
8043 bfd_boolean use_no_density
)
8046 return (1 << align_pow
);
8048 return 3 * (1 << align_pow
);
8050 return 1 + (1 << align_pow
);
8054 /* get_text_align_fill_size ()
8058 target_size = size of next instruction
8059 align_pow = get_text_align_power (target_size).
8063 address = current address + loop instruction size;
8064 target_size = 3 (for 2 or 3 byte target)
8065 = 4 (for 4 byte target)
8066 = 8 (for 8 byte target)
8067 align_pow = get_text_align_power (target_size);
8069 use_no_density = set appropriately
8071 address = current address + loop instruction size;
8073 align_pow = get_text_align_power (target_size);
8075 use_no_density = 0. */
8078 get_text_align_fill_size (addressT address
,
8081 bfd_boolean use_nops
,
8082 bfd_boolean use_no_density
)
8086 align_pow: log2 (required alignment).
8088 target_size: alignment must allow the new_address and
8089 new_address+target_size-1.
8091 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
8093 use_no_density: if use_nops and use_no_density, we can only use
8096 Usually the align_pow is the power of 2 that is greater than
8097 or equal to the target_size. This handles the 2-byte, 3-byte
8098 and 8-byte instructions.
8102 (1) aligning an instruction properly, but without using NOPs.
8103 E.G.: a 3-byte instruction can go on any address where address mod 4
8104 is zero or one. The aligner uses this case to find the optimal
8105 number of fill bytes for relax_frag_for_align.
8107 (2) aligning an instruction properly, but where we might need to use
8108 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8109 or similar to get the optimal location. */
8111 size_t alignment
= (1 << align_pow
);
8113 assert (target_size
!= 0);
8117 unsigned fill_bytes
;
8118 for (fill_bytes
= 0; fill_bytes
< alignment
; fill_bytes
++)
8120 addressT end_address
= address
+ target_size
- 1 + fill_bytes
;
8121 addressT start_address
= address
+ fill_bytes
;
8122 if ((end_address
>> align_pow
) == (start_address
>> align_pow
))
8128 /* This is the slightly harder case. */
8129 assert ((int) alignment
>= target_size
);
8130 assert (target_size
> 0);
8131 if (!use_no_density
)
8134 for (i
= 0; i
< alignment
* 2; i
++)
8138 if ((address
+ i
) >> align_pow
8139 == (address
+ i
+ target_size
- 1) >> align_pow
)
8147 /* Can only fill multiples of 3. */
8148 for (i
= 0; i
<= alignment
* 3; i
+= 3)
8150 if ((address
+ i
) >> align_pow
8151 == (address
+ i
+ target_size
- 1) >> align_pow
)
8160 /* This will assert if it is not possible. */
8163 get_text_align_nop_count (size_t fill_size
, bfd_boolean use_no_density
)
8168 assert (fill_size
% 3 == 0);
8169 return (fill_size
/ 3);
8172 assert (fill_size
!= 1); /* Bad argument. */
8174 while (fill_size
> 1)
8176 size_t insn_size
= 3;
8177 if (fill_size
== 2 || fill_size
== 4)
8179 fill_size
-= insn_size
;
8182 assert (fill_size
!= 1); /* Bad algorithm. */
8188 get_text_align_nth_nop_size (size_t fill_size
,
8190 bfd_boolean use_no_density
)
8194 assert (get_text_align_nop_count (fill_size
, use_no_density
) > n
);
8199 while (fill_size
> 1)
8201 size_t insn_size
= 3;
8202 if (fill_size
== 2 || fill_size
== 4)
8204 fill_size
-= insn_size
;
8214 /* For the given fragment, find the appropriate address
8215 for it to begin at if we are using NOPs to align it. */
8218 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8220 /* The rule is: get next fragment's FIRST instruction. Find
8221 the smallest number of bytes that need to be added to
8222 ensure that the next fragment's FIRST instruction will fit
8225 E.G., 2 bytes : 0, 1, 2 mod 4
8228 If the FIRST instruction MIGHT be relaxed,
8229 assume that it will become a 3-byte instruction.
8231 Note again here that LOOP instructions are not bundleable,
8232 and this relaxation only applies to LOOP opcodes. */
8234 size_t fill_size
= 0;
8235 int first_insn_size
;
8237 addressT pre_opcode_bytes
;
8240 xtensa_opcode opcode
;
8241 bfd_boolean is_loop
;
8243 assert (fragP
->fr_type
== rs_machine_dependent
);
8244 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8246 /* Find the loop frag. */
8247 first_insn
= next_non_empty_frag (fragP
);
8248 /* Now find the first insn frag. */
8249 first_insn
= next_non_empty_frag (first_insn
);
8251 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8253 loop_insn_size
= xg_get_single_size (opcode
);
8255 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8256 pre_opcode_bytes
+= loop_insn_size
;
8258 /* For loops, the alignment depends on the size of the
8259 instruction following the loop, not the LOOP instruction. */
8261 if (first_insn
== NULL
)
8264 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8266 first_insn_size
= frag_format_size (first_insn
);
8268 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8269 first_insn_size
= 3; /* ISA specifies this */
8271 /* If it was 8, then we'll need a larger alignment for the section. */
8272 alignment
= get_text_align_power (first_insn_size
);
8274 /* Is now_seg valid? */
8275 record_alignment (now_seg
, alignment
);
8277 fill_size
= get_text_align_fill_size
8278 (address
+ pre_opcode_bytes
,
8279 get_text_align_power (first_insn_size
),
8280 first_insn_size
, TRUE
, fragP
->tc_frag_data
.is_no_density
);
8282 return address
+ fill_size
;
8286 /* 3 mechanisms for relaxing an alignment:
8288 Align to a power of 2.
8289 Align so the next fragment's instruction does not cross a word boundary.
8290 Align the current instruction so that if the next instruction
8291 were 3 bytes, it would not cross a word boundary.
8295 zeros - This is easy; always insert zeros.
8296 nops - 3-byte and 2-byte instructions
8300 >=5 : 3-byte instruction + fn (n-3)
8301 widening - widen previous instructions. */
8304 get_aligned_diff (fragS
*fragP
, addressT address
, addressT
*max_diff
)
8306 addressT target_address
, loop_insn_offset
;
8308 xtensa_opcode loop_opcode
;
8309 bfd_boolean is_loop
;
8310 int text_align_power
;
8313 assert (fragP
->fr_type
== rs_machine_dependent
);
8314 switch (fragP
->fr_subtype
)
8316 case RELAX_DESIRE_ALIGN
:
8317 target_size
= next_frag_format_size (fragP
);
8318 if (target_size
== XTENSA_UNDEFINED
)
8320 text_align_power
= get_text_align_power (xtensa_fetch_width
);
8321 opt_diff
= get_text_align_fill_size (address
, text_align_power
,
8322 target_size
, FALSE
, FALSE
);
8324 *max_diff
= opt_diff
+ xtensa_fetch_width
8325 - (target_size
+ ((address
+ opt_diff
) % xtensa_fetch_width
));
8326 assert (*max_diff
>= opt_diff
);
8329 case RELAX_ALIGN_NEXT_OPCODE
:
8330 target_size
= next_frag_format_size (fragP
);
8331 loop_insn_offset
= 0;
8332 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8335 /* If the loop has been expanded then the LOOP instruction
8336 could be at an offset from this fragment. */
8337 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8339 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8341 if (target_size
== 2)
8342 target_size
= 3; /* ISA specifies this */
8344 /* In an ideal world, which is what we are shooting for here,
8345 we wouldn't need to use any NOPs immediately prior to the
8346 LOOP instruction. If this approach fails, relax_frag_loop_align
8347 will call get_noop_aligned_address. */
8349 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8350 text_align_power
= get_text_align_power (target_size
),
8351 opt_diff
= get_text_align_fill_size (target_address
, text_align_power
,
8352 target_size
, FALSE
, FALSE
);
8354 *max_diff
= xtensa_fetch_width
8355 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8356 - target_size
+ opt_diff
;
8357 assert (*max_diff
>= opt_diff
);
8368 /* md_relax_frag Hook and Helper Functions. */
8370 static long relax_frag_loop_align (fragS
*, long);
8371 static long relax_frag_for_align (fragS
*, long);
8372 static long relax_frag_immed
8373 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8376 /* Return the number of bytes added to this fragment, given that the
8377 input has been stretched already by "stretch". */
8380 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8382 xtensa_isa isa
= xtensa_default_isa
;
8383 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8384 long new_stretch
= 0;
8387 static xtensa_insnbuf vbuf
= NULL
;
8388 int slot
, num_slots
;
8391 as_where (&file_name
, &line
);
8392 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8394 fragP
->tc_frag_data
.unreported_expansion
= 0;
8396 switch (fragP
->fr_subtype
)
8398 case RELAX_ALIGN_NEXT_OPCODE
:
8399 /* Always convert. */
8400 if (fragP
->tc_frag_data
.relax_seen
)
8401 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8404 case RELAX_LOOP_END
:
8408 case RELAX_LOOP_END_ADD_NOP
:
8409 /* Add a NOP and switch to .fill 0. */
8410 new_stretch
= relax_frag_add_nop (fragP
);
8414 case RELAX_DESIRE_ALIGN
:
8415 /* Do nothing. The narrowing before this frag will either align
8420 case RELAX_LITERAL_FINAL
:
8423 case RELAX_LITERAL_NR
:
8425 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8426 assert (unreported
== lit_size
);
8427 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8428 fragP
->fr_var
-= lit_size
;
8429 fragP
->fr_fix
+= lit_size
;
8435 vbuf
= xtensa_insnbuf_alloc (isa
);
8437 xtensa_insnbuf_from_chars (isa
, vbuf
, fragP
->fr_opcode
, 0);
8438 fmt
= xtensa_format_decode (isa
, vbuf
);
8439 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8441 for (slot
= 0; slot
< num_slots
; slot
++)
8443 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8446 if (fragP
->tc_frag_data
.relax_seen
)
8447 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8451 case RELAX_IMMED_STEP1
:
8452 case RELAX_IMMED_STEP2
:
8453 /* Place the immediate. */
8454 new_stretch
+= relax_frag_immed
8455 (now_seg
, fragP
, stretch
,
8456 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8457 fmt
, slot
, stretched_p
, FALSE
);
8461 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8467 case RELAX_LITERAL_POOL_BEGIN
:
8468 case RELAX_LITERAL_POOL_END
:
8469 case RELAX_MAYBE_UNREACHABLE
:
8470 case RELAX_MAYBE_DESIRE_ALIGN
:
8471 /* No relaxation required. */
8474 case RELAX_FILL_NOP
:
8475 case RELAX_UNREACHABLE
:
8476 if (fragP
->tc_frag_data
.relax_seen
)
8477 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8481 as_bad (_("bad relaxation state"));
8484 /* Tell gas we need another relaxation pass. */
8485 if (! fragP
->tc_frag_data
.relax_seen
)
8487 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8491 new_logical_line (file_name
, line
);
8497 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8499 addressT old_address
, old_next_address
, old_size
;
8500 addressT new_address
, new_next_address
, new_size
;
8503 /* All the frags with relax_frag_for_alignment prior to this one in the
8504 section have been done, hopefully eliminating the need for a NOP here.
8505 But, this will put it in if necessary. */
8507 /* Calculate the old address of this fragment and the next fragment. */
8508 old_address
= fragP
->fr_address
- stretch
;
8509 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8510 fragP
->tc_frag_data
.text_expansion
[0]);
8511 old_size
= old_next_address
- old_address
;
8513 /* Calculate the new address of this fragment and the next fragment. */
8514 new_address
= fragP
->fr_address
;
8516 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8517 new_size
= new_next_address
- new_address
;
8519 growth
= new_size
- old_size
;
8521 /* Fix up the text_expansion field and return the new growth. */
8522 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8527 /* Add a NOP instruction. */
8530 relax_frag_add_nop (fragS
*fragP
)
8532 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8533 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8534 assemble_nop (length
, nop_buf
);
8535 fragP
->tc_frag_data
.is_insn
= TRUE
;
8537 if (fragP
->fr_var
< length
)
8539 as_fatal (_("fr_var (%ld) < length (%d)"), fragP
->fr_var
, length
);
8543 fragP
->fr_fix
+= length
;
8544 fragP
->fr_var
-= length
;
8549 static long future_alignment_required (fragS
*, long);
8552 relax_frag_for_align (fragS
*fragP
, long stretch
)
8554 /* Overview of the relaxation procedure for alignment:
8555 We can widen with NOPs or by widening instructions or by filling
8556 bytes after jump instructions. Find the opportune places and widen
8557 them if necessary. */
8562 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8563 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8564 || (fragP
->fr_subtype
== RELAX_SLOTS
8565 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8567 stretch_me
= future_alignment_required (fragP
, stretch
);
8568 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8574 /* We expanded on a previous pass. Can we shrink now? */
8575 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8576 if (shrink
<= stretch
&& stretch
> 0)
8578 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8584 /* Below here, diff > 0. */
8585 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8591 /* Return the address of the next frag that should be aligned.
8593 By "address" we mean the address it _would_ be at if there
8594 is no action taken to align it between here and the target frag.
8595 In other words, if no narrows and no fill nops are used between
8596 here and the frag to align, _even_if_ some of the frags we use
8597 to align targets have already expanded on a previous relaxation
8600 Also, count each frag that may be used to help align the target.
8602 Return 0 if there are no frags left in the chain that need to be
8606 find_address_of_next_align_frag (fragS
**fragPP
,
8610 bfd_boolean
*paddable
)
8612 fragS
*fragP
= *fragPP
;
8613 addressT address
= fragP
->fr_address
;
8615 /* Do not reset the counts to 0. */
8619 /* Limit this to a small search. */
8625 address
+= fragP
->fr_fix
;
8627 if (fragP
->fr_type
== rs_fill
)
8628 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8629 else if (fragP
->fr_type
== rs_machine_dependent
)
8631 switch (fragP
->fr_subtype
)
8633 case RELAX_UNREACHABLE
:
8637 case RELAX_FILL_NOP
:
8639 if (!fragP
->tc_frag_data
.is_no_density
)
8644 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8649 address
+= total_frag_text_expansion (fragP
);;
8653 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8656 case RELAX_ALIGN_NEXT_OPCODE
:
8657 case RELAX_DESIRE_ALIGN
:
8661 case RELAX_MAYBE_UNREACHABLE
:
8662 case RELAX_MAYBE_DESIRE_ALIGN
:
8667 /* Just punt if we don't know the type. */
8674 /* Just punt if we don't know the type. */
8678 fragP
= fragP
->fr_next
;
8686 static long bytes_to_stretch (fragS
*, int, int, int, int);
8688 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8689 I'll leave this in until I am more confident this works. */
8691 #define LOOKAHEAD_ALIGNER 1
8694 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8696 fragS
*this_frag
= fragP
;
8700 int narrow_nops
= 0;
8701 bfd_boolean paddable
= FALSE
;
8702 offsetT local_opt_diff
;
8705 int stretch_amount
= 0;
8706 int local_stretch_amount
;
8707 int global_stretch_amount
;
8709 address
= find_address_of_next_align_frag
8710 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8714 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8715 opt_diff
= local_opt_diff
;
8716 assert (opt_diff
>= 0);
8717 assert (max_diff
>= opt_diff
);
8720 #ifdef LOOKAHEAD_ALIGNER
8722 fragP
= fragP
->fr_next
;
8724 while (fragP
&& opt_diff
< max_diff
&& address
)
8726 /* We only use these to determine if we can exit early
8727 because there will be plenty of ways to align future
8729 unsigned int glob_widens
= 0;
8732 bfd_boolean glob_pad
= 0;
8733 address
= find_address_of_next_align_frag
8734 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8735 /* If there is a padable portion, then skip. */
8736 if (glob_pad
|| (glob_widens
>= xtensa_fetch_width
))
8741 offsetT next_m_diff
;
8742 offsetT next_o_diff
;
8744 /* Downrange frags haven't had stretch added to them yet. */
8747 /* The address also includes any text expansion from this
8748 frag in a previous pass, but we don't want that. */
8749 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8751 /* Assume we are going to move at least opt_diff. In
8752 reality, we might not be able to, but assuming that
8753 we will helps catch cases where moving opt_diff pushes
8754 the next target from aligned to unaligned. */
8755 address
+= opt_diff
;
8757 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8759 /* Now cleanup for the adjustments to address. */
8760 next_o_diff
+= opt_diff
;
8761 next_m_diff
+= opt_diff
;
8762 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8763 opt_diff
= next_o_diff
;
8764 if (next_m_diff
< max_diff
)
8765 max_diff
= next_m_diff
;
8766 fragP
= fragP
->fr_next
;
8769 #endif /* LOOKAHEAD_ALIGNER */
8770 /* If there are enough wideners in between, do it. */
8773 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8775 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8780 local_stretch_amount
8781 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8782 num_widens
, local_opt_diff
);
8783 #ifdef LOOKAHEAD_ALIGNER
8784 global_stretch_amount
8785 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8786 num_widens
, opt_diff
);
8787 /* If the condition below is true, then the frag couldn't
8788 stretch the correct amount for the global case, so we just
8789 optimize locally. We'll rely on the subsequent frags to get
8790 the correct alignment in the global case. */
8791 if (global_stretch_amount
< local_stretch_amount
)
8792 stretch_amount
= local_stretch_amount
;
8794 stretch_amount
= global_stretch_amount
;
8795 #else /* ! LOOKAHEAD_ALIGNER */
8796 stretch_amount
= local_stretch_amount
;
8797 #endif /* ! LOOKAHEAD_ALIGNER */
8798 if (this_frag
->fr_subtype
== RELAX_SLOTS
8799 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8800 assert (stretch_amount
<= 1);
8801 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8803 if (this_frag
->tc_frag_data
.is_no_density
)
8804 assert (stretch_amount
== 3 || stretch_amount
== 0);
8806 assert (stretch_amount
<= 3);
8809 return stretch_amount
;
8813 /* The idea: widen everything you can to get a target or loop aligned,
8814 then start using NOPs.
8816 When we must have a NOP, here is a table of how we decide
8817 (so you don't have to fight through the control flow below):
8819 wide_nops = the number of wide NOPs available for aligning
8820 narrow_nops = the number of narrow NOPs available for aligning
8821 (a subset of wide_nops)
8822 widens = the number of narrow instructions that should be widened
8829 b 0 1 1 (case 3a makes this case unnecessary)
8832 c 0 1 2 (case 4a makes this case unnecessary)
8835 c 0 2 1 (case 5b makes this case unnecessary)
8838 c 0 1 4 (case 6b makes this case unneccesary)
8839 d 1 1 1 (case 6a makes this case unnecessary)
8840 e 0 2 2 (case 6a makes this case unnecessary)
8841 f 0 3 0 (case 6a makes this case unnecessary)
8844 c 1 1 2 (case 7b makes this case unnecessary)
8845 d 0 1 5 (case 7a makes this case unnecessary)
8846 e 0 2 3 (case 7b makes this case unnecessary)
8847 f 0 3 1 (case 7b makes this case unnecessary)
8848 g 1 2 1 (case 7b makes this case unnecessary)
8852 bytes_to_stretch (fragS
*this_frag
,
8858 int bytes_short
= desired_diff
- num_widens
;
8860 assert (desired_diff
>= 0 && desired_diff
< 8);
8861 if (desired_diff
== 0)
8864 assert (wide_nops
> 0 || num_widens
> 0);
8866 /* Always prefer widening to NOP-filling. */
8867 if (bytes_short
< 0)
8869 /* There are enough RELAX_NARROW frags after this one
8870 to align the target without widening this frag in any way. */
8874 if (bytes_short
== 0)
8876 /* Widen every narrow between here and the align target
8877 and the align target will be properly aligned. */
8878 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8884 /* From here we will need at least one NOP to get an alignment.
8885 However, we may not be able to align at all, in which case,
8887 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8889 switch (desired_diff
)
8894 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8895 return 2; /* case 2 */
8901 return 3; /* case 3a */
8903 if (num_widens
>= 1 && wide_nops
== 1)
8904 return 3; /* case 4a */
8905 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8906 return 2; /* case 4b */
8909 if (num_widens
>= 2 && wide_nops
== 1)
8910 return 3; /* case 5a */
8911 /* We will need two nops. Are there enough nops
8912 between here and the align target? */
8913 if (wide_nops
< 2 || narrow_nops
== 0)
8915 /* Are there other nops closer that can serve instead? */
8916 if (wide_nops
> 2 && narrow_nops
> 1)
8918 /* Take the density one first, because there might not be
8919 another density one available. */
8920 if (!this_frag
->tc_frag_data
.is_no_density
)
8921 return 2; /* case 5b narrow */
8923 return 3; /* case 5b wide */
8927 return 3; /* case 6a */
8928 else if (num_widens
>= 3 && wide_nops
== 1)
8929 return 3; /* case 6b */
8932 if (wide_nops
== 1 && num_widens
>= 4)
8933 return 3; /* case 7a */
8934 else if (wide_nops
== 2 && num_widens
>= 1)
8935 return 3; /* case 7b */
8943 /* We will need a NOP no matter what, but should we widen
8944 this instruction to help?
8946 This is a RELAX_FRAG_NARROW frag. */
8947 switch (desired_diff
)
8956 if (wide_nops
>= 1 && num_widens
== 1)
8957 return 1; /* case 4a */
8960 if (wide_nops
>= 1 && num_widens
== 2)
8961 return 1; /* case 5a */
8965 return 0; /* case 6a */
8966 else if (wide_nops
>= 1 && num_widens
== 3)
8967 return 1; /* case 6b */
8970 if (wide_nops
>= 1 && num_widens
== 4)
8971 return 1; /* case 7a */
8972 else if (wide_nops
>= 2 && num_widens
== 1)
8973 return 1; /* case 7b */
8986 relax_frag_immed (segT segP
,
8993 bfd_boolean estimate_only
)
8996 vliw_insn orig_vinsn
;
8998 bfd_boolean negatable_branch
= FALSE
;
8999 bfd_boolean branch_jmp_to_next
= FALSE
;
9000 bfd_boolean wide_insn
= FALSE
;
9001 xtensa_isa isa
= xtensa_default_isa
;
9003 offsetT frag_offset
;
9006 int num_text_bytes
, num_literal_bytes
;
9007 int literal_diff
, total_text_diff
, this_text_diff
, first
;
9009 assert (fragP
->fr_opcode
!= NULL
);
9011 xg_init_vinsn (&orig_vinsn
);
9012 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
9013 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9016 tinsn
= orig_vinsn
.slots
[slot
];
9017 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9019 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
9022 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9023 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9025 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9027 old_size
= xtensa_format_length (isa
, fmt
);
9029 /* Special case: replace a branch to the next instruction with a NOP.
9030 This is required to work around a hardware bug in T1040.0 and also
9031 serves as an optimization. */
9033 if (branch_jmp_to_next
9034 && ((old_size
== 2) || (old_size
== 3))
9035 && !next_frag_is_loop_target (fragP
))
9038 /* Here is the fun stuff: Get the immediate field from this
9039 instruction. If it fits, we are done. If not, find the next
9040 instruction sequence that fits. */
9042 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9043 istack_init (&istack
);
9044 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9045 min_steps
, stretch
);
9046 if (num_steps
< min_steps
)
9048 as_fatal (_("internal error: relaxation failed"));
9052 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
9054 as_fatal (_("internal error: relaxation requires too many steps"));
9058 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9060 /* Figure out the number of bytes needed. */
9062 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9064 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9066 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9068 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9071 num_text_bytes
+= old_size
;
9072 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9073 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9075 total_text_diff
= num_text_bytes
- old_size
;
9076 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9078 /* It MUST get larger. If not, we could get an infinite loop. */
9079 assert (num_text_bytes
>= 0);
9080 assert (literal_diff
>= 0);
9081 assert (total_text_diff
>= 0);
9083 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9084 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9085 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9086 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9088 /* Find the associated expandable literal for this. */
9089 if (literal_diff
!= 0)
9091 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9094 assert (literal_diff
== 4);
9095 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9097 /* We expect that the literal section state has NOT been
9099 assert (lit_fragP
->fr_type
== rs_machine_dependent
9100 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9101 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9103 /* We need to mark this section for another iteration
9109 if (negatable_branch
&& istack
.ninsn
> 1)
9110 update_next_frag_state (fragP
);
9112 return this_text_diff
;
9116 /* md_convert_frag Hook and Helper Functions. */
9118 static void convert_frag_align_next_opcode (fragS
*);
9119 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9120 static void convert_frag_fill_nop (fragS
*);
9121 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9124 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9126 static xtensa_insnbuf vbuf
= NULL
;
9127 xtensa_isa isa
= xtensa_default_isa
;
9134 as_where (&file_name
, &line
);
9135 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9137 switch (fragp
->fr_subtype
)
9139 case RELAX_ALIGN_NEXT_OPCODE
:
9140 /* Always convert. */
9141 convert_frag_align_next_opcode (fragp
);
9144 case RELAX_DESIRE_ALIGN
:
9145 /* Do nothing. If not aligned already, too bad. */
9149 case RELAX_LITERAL_FINAL
:
9154 vbuf
= xtensa_insnbuf_alloc (isa
);
9156 xtensa_insnbuf_from_chars (isa
, vbuf
, fragp
->fr_opcode
, 0);
9157 fmt
= xtensa_format_decode (isa
, vbuf
);
9158 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9160 for (slot
= 0; slot
< num_slots
; slot
++)
9162 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9165 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9169 case RELAX_IMMED_STEP1
:
9170 case RELAX_IMMED_STEP2
:
9171 /* Place the immediate. */
9174 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9179 /* This is OK because some slots could have
9180 relaxations and others have none. */
9186 case RELAX_UNREACHABLE
:
9187 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9188 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9189 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9193 case RELAX_MAYBE_UNREACHABLE
:
9194 case RELAX_MAYBE_DESIRE_ALIGN
:
9198 case RELAX_FILL_NOP
:
9199 convert_frag_fill_nop (fragp
);
9202 case RELAX_LITERAL_NR
:
9203 if (use_literal_section
)
9205 /* This should have been handled during relaxation. When
9206 relaxing a code segment, literals sometimes need to be
9207 added to the corresponding literal segment. If that
9208 literal segment has already been relaxed, then we end up
9209 in this situation. Marking the literal segments as data
9210 would make this happen less often (since GAS always relaxes
9211 code before data), but we could still get into trouble if
9212 there are instructions in a segment that is not marked as
9213 containing code. Until we can implement a better solution,
9214 cheat and adjust the addresses of all the following frags.
9215 This could break subsequent alignments, but the linker's
9216 literal coalescing will do that anyway. */
9219 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9220 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9221 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9224 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9228 as_bad (_("invalid relaxation fragment result"));
9233 new_logical_line (file_name
, line
);
9238 convert_frag_align_next_opcode (fragS
*fragp
)
9240 char *nop_buf
; /* Location for Writing. */
9243 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9244 addressT aligned_address
;
9245 size_t fill_size
, nop_count
;
9247 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9249 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9250 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9251 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9253 for (i
= 0; i
< nop_count
; i
++)
9256 nop_size
= get_text_align_nth_nop_size (fill_size
, i
, use_no_density
);
9258 assemble_nop (nop_size
, nop_buf
);
9259 nop_buf
+= nop_size
;
9262 fragp
->fr_fix
+= fill_size
;
9263 fragp
->fr_var
-= fill_size
;
9268 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9270 TInsn tinsn
, single_target
;
9271 xtensa_format single_fmt
;
9272 int size
, old_size
, diff
, error_val
;
9273 offsetT frag_offset
;
9276 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9278 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9280 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9281 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9282 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9287 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9289 /* No conversion. */
9294 assert (fragP
->fr_opcode
!= NULL
);
9296 /* Frags in this relaxation state should only contain
9297 single instruction bundles. */
9298 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9300 /* Just convert it to a wide form.... */
9302 old_size
= xg_get_single_size (tinsn
.opcode
);
9304 tinsn_init (&single_target
);
9305 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9307 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
9310 as_bad (_("unable to widen instruction"));
9314 size
= xg_get_single_size (single_target
.opcode
);
9315 single_fmt
= xg_get_single_format (single_target
.opcode
);
9317 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9318 fragP
, frag_offset
, TRUE
);
9320 diff
= size
- old_size
;
9322 assert (diff
<= fragP
->fr_var
);
9323 fragP
->fr_var
-= diff
;
9324 fragP
->fr_fix
+= diff
;
9332 convert_frag_fill_nop (fragS
*fragP
)
9334 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9335 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9336 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9337 - fragP
->fr_address
- fragP
->fr_fix
));
9340 /* No conversion. */
9344 assemble_nop (size
, loc
);
9345 fragP
->tc_frag_data
.is_insn
= TRUE
;
9346 fragP
->fr_var
-= size
;
9347 fragP
->fr_fix
+= size
;
9352 static fixS
*fix_new_exp_in_seg
9353 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9354 bfd_reloc_code_real_type
);
9355 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9358 convert_frag_immed (segT segP
,
9364 char *immed_instr
= fragP
->fr_opcode
;
9366 bfd_boolean expanded
= FALSE
;
9367 bfd_boolean branch_jmp_to_next
= FALSE
;
9368 char *fr_opcode
= fragP
->fr_opcode
;
9369 vliw_insn orig_vinsn
;
9370 xtensa_isa isa
= xtensa_default_isa
;
9371 bfd_boolean wide_insn
= FALSE
;
9373 bfd_boolean is_loop
;
9375 assert (fr_opcode
!= NULL
);
9377 xg_init_vinsn (&orig_vinsn
);
9379 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9380 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9383 orig_tinsn
= orig_vinsn
.slots
[slot
];
9384 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9386 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9388 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9389 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9391 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9393 /* Conversion just inserts a NOP and marks the fix as completed. */
9394 bytes
= xtensa_format_length (isa
, fmt
);
9397 orig_vinsn
.slots
[slot
].opcode
=
9398 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9399 orig_vinsn
.slots
[slot
].ntok
= 0;
9403 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9404 assert (bytes
== 2 || bytes
== 3);
9405 build_nop (&orig_vinsn
.slots
[0], bytes
);
9406 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9408 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9409 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
, fr_opcode
, 0);
9412 else if (!orig_tinsn
.is_specific_opcode
)
9414 /* Here is the fun stuff: Get the immediate field from this
9415 instruction. If it fits, we're done. If not, find the next
9416 instruction sequence that fits. */
9420 symbolS
*lit_sym
= NULL
;
9422 int target_offset
= 0;
9425 symbolS
*gen_label
= NULL
;
9426 offsetT frag_offset
;
9427 bfd_boolean first
= TRUE
;
9428 bfd_boolean last_is_jump
;
9430 /* It does not fit. Find something that does and
9431 convert immediately. */
9432 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9433 istack_init (&istack
);
9434 xg_assembly_relax (&istack
, &orig_tinsn
,
9435 segP
, fragP
, frag_offset
, min_steps
, 0);
9437 old_size
= xtensa_format_length (isa
, fmt
);
9439 /* Assemble this right inline. */
9441 /* First, create the mapping from a label name to the REAL label. */
9443 for (i
= 0; i
< istack
.ninsn
; i
++)
9445 TInsn
*tinsn
= &istack
.insn
[i
];
9448 switch (tinsn
->insn_type
)
9451 if (lit_sym
!= NULL
)
9452 as_bad (_("multiple literals in expansion"));
9453 /* First find the appropriate space in the literal pool. */
9454 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9455 if (lit_frag
== NULL
)
9456 as_bad (_("no registered fragment for literal"));
9457 if (tinsn
->ntok
!= 1)
9458 as_bad (_("number of literal tokens != 1"));
9460 /* Set the literal symbol and add a fixup. */
9461 lit_sym
= lit_frag
->fr_symbol
;
9465 if (align_targets
&& !is_loop
)
9467 fragS
*unreach
= fragP
->fr_next
;
9468 while (!(unreach
->fr_type
== rs_machine_dependent
9469 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9470 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9472 unreach
= unreach
->fr_next
;
9475 assert (unreach
->fr_type
== rs_machine_dependent
9476 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9477 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9479 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9481 assert (gen_label
== NULL
);
9482 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9483 fr_opcode
- fragP
->fr_literal
9484 + target_offset
, fragP
);
9488 if (first
&& wide_insn
)
9490 target_offset
+= xtensa_format_length (isa
, fmt
);
9492 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9493 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9496 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9503 last_is_jump
= FALSE
;
9504 for (i
= 0; i
< istack
.ninsn
; i
++)
9506 TInsn
*tinsn
= &istack
.insn
[i
];
9510 bfd_reloc_code_real_type reloc_type
;
9512 switch (tinsn
->insn_type
)
9515 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9516 /* Already checked. */
9517 assert (lit_frag
!= NULL
);
9518 assert (lit_sym
!= NULL
);
9519 assert (tinsn
->ntok
== 1);
9521 target_seg
= S_GET_SEGMENT (lit_sym
);
9522 assert (target_seg
);
9523 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9524 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9526 reloc_type
= BFD_RELOC_32
;
9527 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9528 &tinsn
->tok
[0], FALSE
, reloc_type
);
9535 xg_resolve_labels (tinsn
, gen_label
);
9536 xg_resolve_literals (tinsn
, lit_sym
);
9537 if (wide_insn
&& first
)
9540 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9542 tinsn
->record_fix
= TRUE
;
9543 orig_vinsn
.slots
[slot
] = *tinsn
;
9547 orig_vinsn
.slots
[slot
].opcode
=
9548 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9549 orig_vinsn
.slots
[slot
].ntok
= 0;
9550 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9552 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9553 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9555 fragP
->tc_frag_data
.is_insn
= TRUE
;
9556 size
= xtensa_format_length (isa
, fmt
);
9557 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9559 xtensa_format single_fmt
=
9560 xg_get_single_format (tinsn
->opcode
);
9563 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9564 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9565 size
+= xg_get_single_size (tinsn
->opcode
);
9570 xtensa_format single_format
;
9571 size
= xg_get_single_size (tinsn
->opcode
);
9572 single_format
= xg_get_single_format (tinsn
->opcode
);
9573 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9575 immed_instr
- fragP
->fr_literal
, TRUE
);
9577 /* Code to recognize branch-around expansion
9578 so the fragment is properly marked as ending in a
9580 if ((((i
== istack
.ninsn
- 2)
9581 && (istack
.insn
[istack
.ninsn
-1].insn_type
9583 || i
== istack
.ninsn
-1)
9584 && xtensa_opcode_is_jump (xtensa_default_isa
,
9586 && fragP
->fr_next
!= NULL
9587 && ! fragP
->fr_next
->tc_frag_data
.is_unreachable
)
9589 /* Create a new unreachable frag of zero size. */
9590 size_t frag_size
= sizeof (fragS
);
9591 fragS
*new_fragP
= (fragS
*) xmalloc (frag_size
);
9592 memset (new_fragP
, 0, frag_size
);
9593 new_fragP
->fr_address
= fragP
->fr_next
->fr_address
;
9594 new_fragP
->fr_next
= fragP
->fr_next
;
9595 new_fragP
->fr_fix
= 0;
9596 new_fragP
->fr_var
= 0;
9597 new_fragP
->fr_type
= rs_fill
;
9598 new_fragP
->tc_frag_data
.is_unreachable
= TRUE
;
9599 /* The rest are zeros.... */
9600 /* Link it in to the chain. */
9601 fragP
->fr_next
= new_fragP
;
9605 immed_instr
+= size
;
9611 diff
= total_size
- old_size
;
9615 assert (diff
<= fragP
->fr_var
);
9616 fragP
->fr_var
-= diff
;
9617 fragP
->fr_fix
+= diff
;
9621 xg_free_vinsn (&orig_vinsn
);
9623 /* Check for undefined immediates in LOOP instructions. */
9627 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9628 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9630 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9633 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9634 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9636 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9641 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9642 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9644 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9646 /* Add an expansion note on the expanded instruction. */
9647 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9648 &orig_tinsn
.tok
[0], TRUE
,
9649 BFD_RELOC_XTENSA_ASM_EXPAND
);
9654 /* Add a new fix expression into the desired segment. We have to
9655 switch to that segment to do this. */
9658 fix_new_exp_in_seg (segT new_seg
,
9665 bfd_reloc_code_real_type r_type
)
9669 subsegT subseg
= now_subseg
;
9671 assert (new_seg
!= 0);
9672 subseg_set (new_seg
, new_subseg
);
9674 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9675 subseg_set (seg
, subseg
);
9680 /* Relax a loop instruction so that it can span loop >256 bytes.
9686 addi as, as, lo8 (label-.L1)
9687 addmi as, as, mid8 (label-.L1)
9698 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9703 unsigned long target
;
9704 static xtensa_insnbuf insnbuf
= NULL
;
9705 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9706 xtensa_isa isa
= xtensa_default_isa
;
9707 addressT loop_offset
;
9708 addressT addi_offset
= 9;
9709 addressT addmi_offset
= 12;
9711 size_t target_count
;
9714 insnbuf
= xtensa_insnbuf_alloc (isa
);
9716 /* Get the loop offset. */
9717 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9719 /* Validate that there really is a LOOP at the loop_offset. Because
9720 loops are not bundleable, we can assume that the instruction will be
9722 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9723 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9725 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9726 addi_offset
+= loop_offset
;
9727 addmi_offset
+= loop_offset
;
9729 assert (tinsn
->ntok
== 2);
9730 if (tinsn
->tok
[1].X_op
== O_constant
)
9731 target
= tinsn
->tok
[1].X_add_number
;
9732 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9734 /* Find the fragment. */
9735 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9736 assert (S_GET_SEGMENT (sym
) == segP
9737 || S_GET_SEGMENT (sym
) == absolute_section
);
9738 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9742 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9747 know (symbolP
->sy_frag
);
9748 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9749 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9751 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9752 loop_length_hi
= loop_length
& ~0x0ff;
9753 loop_length_lo
= loop_length
& 0x0ff;
9754 if (loop_length_lo
>= 128)
9756 loop_length_lo
-= 256;
9757 loop_length_hi
+= 256;
9760 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9761 32512. If the loop is larger than that, then we just fail. */
9762 if (loop_length_hi
> 32512)
9763 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9764 _("loop too long for LOOP instruction"));
9766 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9767 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9769 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9770 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9772 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9773 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9775 fragP
->tc_frag_data
.is_insn
= TRUE
;
9776 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addi_offset
, 0);
9778 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9779 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9780 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addmi_offset
, 0);
9782 /* Walk through all of the frags from here to the loop end
9783 and mark them as no_transform to keep them from being modified
9784 by the linker. If we ever have a relocation for the
9785 addi/addmi of the difference of two symbols we can remove this. */
9788 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9789 next_fragP
= next_fragP
->fr_next
)
9791 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9792 if (next_fragP
->tc_frag_data
.is_loop_target
)
9794 if (target_count
== 2)
9800 /* A map that keeps information on a per-subsegment basis. This is
9801 maintained during initial assembly, but is invalid once the
9802 subsegments are smashed together. I.E., it cannot be used during
9805 typedef struct subseg_map_struct
9813 float total_freq
; /* fall-through + branch target frequency */
9814 float target_freq
; /* branch target frequency alone */
9816 struct subseg_map_struct
*next
;
9820 static subseg_map
*sseg_map
= NULL
;
9823 get_subseg_info (segT seg
, subsegT subseg
)
9825 subseg_map
*subseg_e
;
9827 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9829 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9837 add_subseg_info (segT seg
, subsegT subseg
)
9839 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9840 memset (subseg_e
, 0, sizeof (subseg_map
));
9841 subseg_e
->seg
= seg
;
9842 subseg_e
->subseg
= subseg
;
9843 subseg_e
->flags
= 0;
9844 /* Start off considering every branch target very important. */
9845 subseg_e
->target_freq
= 1.0;
9846 subseg_e
->total_freq
= 1.0;
9847 subseg_e
->next
= sseg_map
;
9848 sseg_map
= subseg_e
;
9854 get_last_insn_flags (segT seg
, subsegT subseg
)
9856 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9858 return subseg_e
->flags
;
9864 set_last_insn_flags (segT seg
,
9869 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9871 subseg_e
= add_subseg_info (seg
, subseg
);
9873 subseg_e
->flags
|= fl
;
9875 subseg_e
->flags
&= ~fl
;
9880 get_subseg_total_freq (segT seg
, subsegT subseg
)
9882 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9884 return subseg_e
->total_freq
;
9890 get_subseg_target_freq (segT seg
, subsegT subseg
)
9892 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9894 return subseg_e
->target_freq
;
9900 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9902 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9904 subseg_e
= add_subseg_info (seg
, subseg
);
9905 subseg_e
->total_freq
= total_f
;
9906 subseg_e
->target_freq
= target_f
;
9910 /* Segment Lists and emit_state Stuff. */
9912 /* Remove the segment from the global sections list. */
9915 xtensa_remove_section (segT sec
)
9917 /* Handle brain-dead bfd_section_list_remove macro, which
9918 expect the address of the prior section's "next" field, not
9919 just the address of the section to remove. */
9921 segT
*ps_next_ptr
= &stdoutput
->sections
;
9922 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
9923 ps_next_ptr
= &(*ps_next_ptr
)->next
;
9925 assert (*ps_next_ptr
!= NULL
);
9927 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
9932 xtensa_insert_section (segT after_sec
, segT sec
)
9934 segT
*after_sec_next
;
9935 if (after_sec
== NULL
)
9936 after_sec_next
= &stdoutput
->sections
;
9938 after_sec_next
= &after_sec
->next
;
9940 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
9945 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9950 segT literal_section
= head
->seg
;
9952 /* Move the literal section to the front of the section list. */
9953 assert (literal_section
);
9954 xtensa_remove_section (literal_section
);
9955 xtensa_insert_section (NULL
, literal_section
);
9962 static void mark_literal_frags (seg_list
*);
9965 xtensa_move_literals (void)
9968 frchainS
*frchain_from
, *frchain_to
;
9969 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9970 fragS
**frag_splice
;
9973 fixS
*fix
, *next_fix
, **fix_splice
;
9976 mark_literal_frags (literal_head
->next
);
9977 mark_literal_frags (init_literal_head
->next
);
9978 mark_literal_frags (fini_literal_head
->next
);
9980 if (use_literal_section
)
9983 segment
= literal_head
->next
;
9986 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9987 search_frag
= frchain_from
->frch_root
;
9988 literal_pool
= NULL
;
9990 frag_splice
= &(frchain_from
->frch_root
);
9992 while (!search_frag
->tc_frag_data
.literal_frag
)
9994 assert (search_frag
->fr_fix
== 0
9995 || search_frag
->fr_type
== rs_align
);
9996 search_frag
= search_frag
->fr_next
;
9999 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10000 == RELAX_LITERAL_POOL_BEGIN
);
10001 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10003 /* Make sure that all the frags in this series are closed, and
10004 that there is at least one left over of zero-size. This
10005 prevents us from making a segment with an frchain without any
10007 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10008 xtensa_set_frag_assembly_state (frag_now
);
10009 last_frag
= frag_now
;
10010 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10011 xtensa_set_frag_assembly_state (frag_now
);
10013 while (search_frag
!= frag_now
)
10015 next_frag
= search_frag
->fr_next
;
10017 /* First, move the frag out of the literal section and
10018 to the appropriate place. */
10019 if (search_frag
->tc_frag_data
.literal_frag
)
10021 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10022 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10023 /* Note that we set this fr_var to be a fix
10024 chain when we created the literal pool location
10025 as RELAX_LITERAL_POOL_BEGIN. */
10026 frchain_to
= (frchainS
*) literal_pool
->fr_var
;
10028 insert_after
= literal_pool
;
10030 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
10031 insert_after
= insert_after
->fr_next
;
10033 dest_seg
= (segT
) insert_after
->fr_next
->fr_var
;
10035 *frag_splice
= next_frag
;
10036 search_frag
->fr_next
= insert_after
->fr_next
;
10037 insert_after
->fr_next
= search_frag
;
10038 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10040 /* Now move any fixups associated with this frag to the
10042 fix
= frchain_from
->fix_root
;
10043 fix_splice
= &(frchain_from
->fix_root
);
10046 next_fix
= fix
->fx_next
;
10047 if (fix
->fx_frag
== search_frag
)
10049 *fix_splice
= next_fix
;
10050 fix
->fx_next
= frchain_to
->fix_root
;
10051 frchain_to
->fix_root
= fix
;
10052 if (frchain_to
->fix_tail
== NULL
)
10053 frchain_to
->fix_tail
= fix
;
10056 fix_splice
= &(fix
->fx_next
);
10059 search_frag
= next_frag
;
10062 if (frchain_from
->fix_root
!= NULL
)
10064 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10065 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10067 assert (frchain_from
->fix_root
== NULL
);
10069 frchain_from
->fix_tail
= NULL
;
10070 xtensa_restore_emit_state (&state
);
10071 segment
= segment
->next
;
10074 /* Now fix up the SEGMENT value for all the literal symbols. */
10075 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10077 symbolS
*lit_sym
= lit
->sym
;
10078 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10080 S_SET_SEGMENT (lit_sym
, dest_seg
);
10085 /* Walk over all the frags for segments in a list and mark them as
10086 containing literals. As clunky as this is, we can't rely on frag_var
10087 and frag_variant to get called in all situations. */
10090 mark_literal_frags (seg_list
*segment
)
10092 frchainS
*frchain_from
;
10093 fragS
*search_frag
;
10097 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10098 search_frag
= frchain_from
->frch_root
;
10099 while (search_frag
)
10101 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10102 search_frag
= search_frag
->fr_next
;
10104 segment
= segment
->next
;
10110 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10112 /* Move all of the sections in the section list to come
10113 after "after" in the gnu segment list. */
10118 segT literal_section
= head
->seg
;
10120 /* Move the literal section after "after". */
10121 assert (literal_section
);
10122 if (literal_section
!= after
)
10124 xtensa_remove_section (literal_section
);
10125 xtensa_insert_section (after
, literal_section
);
10133 /* Push all the literal segments to the end of the gnu list. */
10136 xtensa_reorder_segments (void)
10143 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10149 /* Now that we have the last section, push all the literal
10150 sections to the end. */
10151 xtensa_reorder_seg_list (literal_head
, last_sec
);
10152 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
10153 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
10155 /* Now perform the final error check. */
10156 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10158 assert (new_count
== old_count
);
10162 /* Change the emit state (seg, subseg, and frag related stuff) to the
10163 correct location. Return a emit_state which can be passed to
10164 xtensa_restore_emit_state to return to current fragment. */
10167 xtensa_switch_to_literal_fragment (emit_state
*result
)
10169 if (directive_state
[directive_absolute_literals
])
10171 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
10172 &default_lit_sections
.lit4_seg
, FALSE
);
10173 xtensa_switch_section_emit_state (result
,
10174 default_lit_sections
.lit4_seg
, 0);
10177 xtensa_switch_to_non_abs_literal_fragment (result
);
10179 /* Do a 4-byte align here. */
10180 frag_align (2, 0, 0);
10181 record_alignment (now_seg
, 2);
10186 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10188 /* When we mark a literal pool location, we want to put a frag in
10189 the literal pool that points to it. But to do that, we want to
10190 switch_to_literal_fragment. But literal sections don't have
10191 literal pools, so their location is always null, so we would
10192 recurse forever. This is kind of hacky, but it works. */
10194 static bfd_boolean recursive
= FALSE
;
10195 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10196 bfd_boolean is_init
=
10197 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10199 bfd_boolean is_fini
=
10200 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10202 if (pool_location
== NULL
10203 && !use_literal_section
10205 && !is_init
&& ! is_fini
)
10207 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10209 xtensa_mark_literal_pool_location ();
10213 /* Special case: If we are in the ".fini" or ".init" section, then
10214 we will ALWAYS be generating to the ".fini.literal" and
10215 ".init.literal" sections. */
10219 cache_literal_section (init_literal_head
,
10220 default_lit_sections
.init_lit_seg_name
,
10221 &default_lit_sections
.init_lit_seg
, TRUE
);
10222 xtensa_switch_section_emit_state (result
,
10223 default_lit_sections
.init_lit_seg
, 0);
10227 cache_literal_section (fini_literal_head
,
10228 default_lit_sections
.fini_lit_seg_name
,
10229 &default_lit_sections
.fini_lit_seg
, TRUE
);
10230 xtensa_switch_section_emit_state (result
,
10231 default_lit_sections
.fini_lit_seg
, 0);
10235 cache_literal_section (literal_head
,
10236 default_lit_sections
.lit_seg_name
,
10237 &default_lit_sections
.lit_seg
, TRUE
);
10238 xtensa_switch_section_emit_state (result
,
10239 default_lit_sections
.lit_seg
, 0);
10242 if (!use_literal_section
10243 && !is_init
&& !is_fini
10244 && get_literal_pool_location (now_seg
) != pool_location
)
10246 /* Close whatever frag is there. */
10247 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10248 xtensa_set_frag_assembly_state (frag_now
);
10249 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10250 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10251 xtensa_set_frag_assembly_state (frag_now
);
10256 /* Call this function before emitting data into the literal section.
10257 This is a helper function for xtensa_switch_to_literal_fragment.
10258 This is similar to a .section new_now_seg subseg. */
10261 xtensa_switch_section_emit_state (emit_state
*state
,
10263 subsegT new_now_subseg
)
10265 state
->name
= now_seg
->name
;
10266 state
->now_seg
= now_seg
;
10267 state
->now_subseg
= now_subseg
;
10268 state
->generating_literals
= generating_literals
;
10269 generating_literals
++;
10270 subseg_set (new_now_seg
, new_now_subseg
);
10274 /* Use to restore the emitting into the normal place. */
10277 xtensa_restore_emit_state (emit_state
*state
)
10279 generating_literals
= state
->generating_literals
;
10280 subseg_set (state
->now_seg
, state
->now_subseg
);
10284 /* Get a segment of a given name. If the segment is already
10285 present, return it; otherwise, create a new one. */
10288 cache_literal_section (seg_list
*head
,
10291 bfd_boolean is_code
)
10293 segT current_section
= now_seg
;
10294 int current_subsec
= now_subseg
;
10300 /* Check if the named section exists. */
10301 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10303 if (!strcmp (segment_name (seg
), name
))
10309 /* Create a new literal section. */
10310 seg
= subseg_new (name
, (subsegT
) 0);
10313 /* Add the newly created literal segment to the specified list. */
10314 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10316 n
->next
= head
->next
;
10319 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10320 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10321 | (is_code
? SEC_CODE
: SEC_DATA
));
10322 bfd_set_section_alignment (stdoutput
, seg
, 2);
10326 subseg_set (current_section
, current_subsec
);
10330 /* Property Tables Stuff. */
10332 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10333 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10334 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10336 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10337 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10339 static bfd_boolean
get_frag_is_literal (const fragS
*);
10340 static void xtensa_create_property_segments
10341 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10342 static void xtensa_create_xproperty_segments
10343 (frag_flags_fn
, const char *, xt_section_type
);
10344 static segment_info_type
*retrieve_segment_info (segT
);
10345 static segT
retrieve_xtensa_section (char *);
10346 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10347 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10348 static void add_xt_block_frags
10349 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10350 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10351 static void xtensa_frag_flags_init (frag_flags
*);
10352 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10353 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10354 static void add_xt_prop_frags
10355 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10357 /* Set up property tables after relaxation. */
10360 xtensa_post_relax_hook (void)
10362 xtensa_move_seg_list_to_beginning (literal_head
);
10363 xtensa_move_seg_list_to_beginning (init_literal_head
);
10364 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10366 xtensa_find_unmarked_state_frags ();
10368 if (use_literal_section
)
10369 xtensa_create_property_segments (get_frag_is_literal
,
10371 XTENSA_LIT_SEC_NAME
,
10373 xtensa_create_xproperty_segments (get_frag_property_flags
,
10374 XTENSA_PROP_SEC_NAME
,
10377 if (warn_unaligned_branch_targets
)
10378 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10379 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10383 /* This function is only meaningful after xtensa_move_literals. */
10386 get_frag_is_literal (const fragS
*fragP
)
10388 assert (fragP
!= NULL
);
10389 return fragP
->tc_frag_data
.is_literal
;
10394 xtensa_create_property_segments (frag_predicate property_function
,
10395 frag_predicate end_property_function
,
10396 const char *section_name_base
,
10397 xt_section_type sec_type
)
10401 /* Walk over all of the current segments.
10402 Walk over each fragment
10403 For each non-empty fragment,
10404 Build a property record (append where possible). */
10406 for (seclist
= &stdoutput
->sections
;
10407 seclist
&& *seclist
;
10408 seclist
= &(*seclist
)->next
)
10410 segT sec
= *seclist
;
10413 flags
= bfd_get_section_flags (stdoutput
, sec
);
10414 if (flags
& SEC_DEBUGGING
)
10416 if (!(flags
& SEC_ALLOC
))
10419 if (section_has_property (sec
, property_function
))
10421 char *property_section_name
=
10422 xtensa_get_property_section_name (sec
, section_name_base
);
10423 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10424 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10425 xtensa_block_info
**xt_blocks
=
10426 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10427 /* Walk over all of the frchains here and add new sections. */
10428 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10429 end_property_function
);
10433 /* Now we fill them out.... */
10435 for (seclist
= &stdoutput
->sections
;
10436 seclist
&& *seclist
;
10437 seclist
= &(*seclist
)->next
)
10439 segment_info_type
*seginfo
;
10440 xtensa_block_info
*block
;
10441 segT sec
= *seclist
;
10443 seginfo
= seg_info (sec
);
10444 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10448 xtensa_block_info
*cur_block
;
10449 /* This is a section with some data. */
10453 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10456 rec_size
= num_recs
* 8;
10457 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10459 /* In order to make this work with the assembler, we have to
10460 build some frags and then build the "fixups" for it. It
10461 would be easier to just set the contents then set the
10466 /* Allocate a fragment and leak it. */
10470 frchainS
*frchainP
;
10474 frag_size
= sizeof (fragS
) + rec_size
;
10475 fragP
= (fragS
*) xmalloc (frag_size
);
10477 memset (fragP
, 0, frag_size
);
10478 fragP
->fr_address
= 0;
10479 fragP
->fr_next
= NULL
;
10480 fragP
->fr_fix
= rec_size
;
10482 fragP
->fr_type
= rs_fill
;
10483 /* The rest are zeros. */
10485 frchainP
= seginfo
->frchainP
;
10486 frchainP
->frch_root
= fragP
;
10487 frchainP
->frch_last
= fragP
;
10489 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10490 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10492 seginfo
->fix_root
= fixes
;
10493 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10495 frag_data
= &fragP
->fr_literal
[0];
10496 for (i
= 0; i
< num_recs
; i
++)
10498 fixS
*fix
= &fixes
[i
];
10499 assert (cur_block
);
10501 /* Write the fixup. */
10502 if (i
!= num_recs
- 1)
10503 fix
->fx_next
= &fixes
[i
+ 1];
10505 fix
->fx_next
= NULL
;
10508 fix
->fx_frag
= fragP
;
10509 fix
->fx_where
= i
* 8;
10510 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10511 fix
->fx_offset
= cur_block
->offset
;
10512 fix
->fx_r_type
= BFD_RELOC_32
;
10513 fix
->fx_file
= "Internal Assembly";
10516 /* Write the length. */
10517 md_number_to_chars (&frag_data
[4 + 8 * i
],
10518 cur_block
->size
, 4);
10519 cur_block
= cur_block
->next
;
10528 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10529 const char *section_name_base
,
10530 xt_section_type sec_type
)
10534 /* Walk over all of the current segments.
10535 Walk over each fragment.
10536 For each fragment that has instructions,
10537 build an instruction record (append where possible). */
10539 for (seclist
= &stdoutput
->sections
;
10540 seclist
&& *seclist
;
10541 seclist
= &(*seclist
)->next
)
10543 segT sec
= *seclist
;
10546 flags
= bfd_get_section_flags (stdoutput
, sec
);
10547 if (flags
& SEC_DEBUGGING
)
10549 if (!(flags
& SEC_ALLOC
))
10552 if (section_has_xproperty (sec
, flag_fn
))
10554 char *property_section_name
=
10555 xtensa_get_property_section_name (sec
, section_name_base
);
10556 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10557 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10558 xtensa_block_info
**xt_blocks
=
10559 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10560 /* Walk over all of the frchains here and add new sections. */
10561 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10565 /* Now we fill them out.... */
10567 for (seclist
= &stdoutput
->sections
;
10568 seclist
&& *seclist
;
10569 seclist
= &(*seclist
)->next
)
10571 segment_info_type
*seginfo
;
10572 xtensa_block_info
*block
;
10573 segT sec
= *seclist
;
10575 seginfo
= seg_info (sec
);
10576 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10580 xtensa_block_info
*cur_block
;
10581 /* This is a section with some data. */
10585 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10588 rec_size
= num_recs
* (8 + 4);
10589 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10591 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10593 /* In order to make this work with the assembler, we have to build
10594 some frags then build the "fixups" for it. It would be easier to
10595 just set the contents then set the arlents. */
10599 /* Allocate a fragment and (unfortunately) leak it. */
10603 frchainS
*frchainP
;
10607 frag_size
= sizeof (fragS
) + rec_size
;
10608 fragP
= (fragS
*) xmalloc (frag_size
);
10610 memset (fragP
, 0, frag_size
);
10611 fragP
->fr_address
= 0;
10612 fragP
->fr_next
= NULL
;
10613 fragP
->fr_fix
= rec_size
;
10615 fragP
->fr_type
= rs_fill
;
10616 /* The rest are zeros. */
10618 frchainP
= seginfo
->frchainP
;
10619 frchainP
->frch_root
= fragP
;
10620 frchainP
->frch_last
= fragP
;
10622 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10623 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10625 seginfo
->fix_root
= fixes
;
10626 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10628 frag_data
= &fragP
->fr_literal
[0];
10629 for (i
= 0; i
< num_recs
; i
++)
10631 fixS
*fix
= &fixes
[i
];
10632 assert (cur_block
);
10634 /* Write the fixup. */
10635 if (i
!= num_recs
- 1)
10636 fix
->fx_next
= &fixes
[i
+ 1];
10638 fix
->fx_next
= NULL
;
10641 fix
->fx_frag
= fragP
;
10642 fix
->fx_where
= i
* (8 + 4);
10643 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10644 fix
->fx_offset
= cur_block
->offset
;
10645 fix
->fx_r_type
= BFD_RELOC_32
;
10646 fix
->fx_file
= "Internal Assembly";
10649 /* Write the length. */
10650 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10651 cur_block
->size
, 4);
10652 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10653 frag_flags_to_number (&cur_block
->flags
),
10655 cur_block
= cur_block
->next
;
10663 static segment_info_type
*
10664 retrieve_segment_info (segT seg
)
10666 segment_info_type
*seginfo
;
10667 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10670 frchainS
*frchainP
;
10672 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10673 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10674 seginfo
->fix_root
= NULL
;
10675 seginfo
->fix_tail
= NULL
;
10676 seginfo
->bfd_section
= seg
;
10678 /* We will not be dealing with these, only our special ones. */
10680 if (seg
== bfd_abs_section_ptr
)
10681 abs_seg_info
= seginfo
;
10682 else if (seg
== bfd_und_section_ptr
)
10683 und_seg_info
= seginfo
;
10686 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10688 seg_fix_rootP
= &segment_info
[seg
].fix_root
;
10689 seg_fix_tailP
= &segment_info
[seg
].fix_tail
;
10692 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10693 frchainP
->frch_root
= NULL
;
10694 frchainP
->frch_last
= NULL
;
10695 frchainP
->frch_next
= NULL
;
10696 frchainP
->frch_seg
= seg
;
10697 frchainP
->frch_subseg
= 0;
10698 frchainP
->fix_root
= NULL
;
10699 frchainP
->fix_tail
= NULL
;
10700 /* Do not init the objstack. */
10701 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10702 /* frchainP->frch_frag_now = fragP; */
10703 frchainP
->frch_frag_now
= NULL
;
10705 seginfo
->frchainP
= frchainP
;
10713 retrieve_xtensa_section (char *sec_name
)
10715 bfd
*abfd
= stdoutput
;
10716 flagword flags
, out_flags
, link_once_flags
;
10719 flags
= bfd_get_section_flags (abfd
, now_seg
);
10720 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10721 if (link_once_flags
)
10722 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10723 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10725 s
= bfd_make_section_old_way (abfd
, sec_name
);
10727 as_bad (_("could not create section %s"), sec_name
);
10728 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10729 as_bad (_("invalid flag combination on section %s"), sec_name
);
10736 section_has_property (segT sec
, frag_predicate property_function
)
10738 segment_info_type
*seginfo
= seg_info (sec
);
10741 if (seginfo
&& seginfo
->frchainP
)
10743 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10745 if (property_function (fragP
)
10746 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10755 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10757 segment_info_type
*seginfo
= seg_info (sec
);
10760 if (seginfo
&& seginfo
->frchainP
)
10762 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10764 frag_flags prop_flags
;
10765 property_function (fragP
, &prop_flags
);
10766 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10774 /* Two types of block sections exist right now: literal and insns. */
10777 add_xt_block_frags (segT sec
,
10779 xtensa_block_info
**xt_block
,
10780 frag_predicate property_function
,
10781 frag_predicate end_property_function
)
10783 segment_info_type
*seg_info
;
10784 segment_info_type
*xt_seg_info
;
10785 bfd_vma seg_offset
;
10788 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10789 seg_info
= retrieve_segment_info (sec
);
10791 /* Build it if needed. */
10792 while (*xt_block
!= NULL
)
10793 xt_block
= &(*xt_block
)->next
;
10794 /* We are either at NULL at the beginning or at the end. */
10796 /* Walk through the frags. */
10799 if (seg_info
->frchainP
)
10801 for (fragP
= seg_info
->frchainP
->frch_root
;
10803 fragP
= fragP
->fr_next
)
10805 if (property_function (fragP
)
10806 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10808 if (*xt_block
!= NULL
)
10810 if ((*xt_block
)->offset
+ (*xt_block
)->size
10811 == fragP
->fr_address
)
10812 (*xt_block
)->size
+= fragP
->fr_fix
;
10814 xt_block
= &((*xt_block
)->next
);
10816 if (*xt_block
== NULL
)
10818 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10819 xmalloc (sizeof (xtensa_block_info
));
10820 new_block
->sec
= sec
;
10821 new_block
->offset
= fragP
->fr_address
;
10822 new_block
->size
= fragP
->fr_fix
;
10823 new_block
->next
= NULL
;
10824 xtensa_frag_flags_init (&new_block
->flags
);
10825 *xt_block
= new_block
;
10827 if (end_property_function
10828 && end_property_function (fragP
))
10830 xt_block
= &((*xt_block
)->next
);
10838 /* Break the encapsulation of add_xt_prop_frags here. */
10841 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10843 if (prop_flags
->is_literal
10844 || prop_flags
->is_insn
10845 || prop_flags
->is_data
10846 || prop_flags
->is_unreachable
)
10853 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10855 memset (prop_flags
, 0, sizeof (frag_flags
));
10860 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10862 xtensa_frag_flags_init (prop_flags
);
10863 if (fragP
->tc_frag_data
.is_literal
)
10864 prop_flags
->is_literal
= TRUE
;
10865 if (fragP
->tc_frag_data
.is_unreachable
)
10866 prop_flags
->is_unreachable
= TRUE
;
10867 else if (fragP
->tc_frag_data
.is_insn
)
10869 prop_flags
->is_insn
= TRUE
;
10870 if (fragP
->tc_frag_data
.is_loop_target
)
10871 prop_flags
->insn
.is_loop_target
= TRUE
;
10872 if (fragP
->tc_frag_data
.is_branch_target
)
10873 prop_flags
->insn
.is_branch_target
= TRUE
;
10874 if (fragP
->tc_frag_data
.is_specific_opcode
10875 || fragP
->tc_frag_data
.is_no_transform
)
10876 prop_flags
->insn
.is_no_transform
= TRUE
;
10877 if (fragP
->tc_frag_data
.is_no_density
)
10878 prop_flags
->insn
.is_no_density
= TRUE
;
10879 if (fragP
->tc_frag_data
.use_absolute_literals
)
10880 prop_flags
->insn
.is_abslit
= TRUE
;
10882 if (fragP
->tc_frag_data
.is_align
)
10884 prop_flags
->is_align
= TRUE
;
10885 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10886 if (xtensa_frag_flags_is_empty (prop_flags
))
10887 prop_flags
->is_data
= TRUE
;
10893 frag_flags_to_number (const frag_flags
*prop_flags
)
10896 if (prop_flags
->is_literal
)
10897 num
|= XTENSA_PROP_LITERAL
;
10898 if (prop_flags
->is_insn
)
10899 num
|= XTENSA_PROP_INSN
;
10900 if (prop_flags
->is_data
)
10901 num
|= XTENSA_PROP_DATA
;
10902 if (prop_flags
->is_unreachable
)
10903 num
|= XTENSA_PROP_UNREACHABLE
;
10904 if (prop_flags
->insn
.is_loop_target
)
10905 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10906 if (prop_flags
->insn
.is_branch_target
)
10908 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10909 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10912 if (prop_flags
->insn
.is_no_density
)
10913 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10914 if (prop_flags
->insn
.is_no_transform
)
10915 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10916 if (prop_flags
->insn
.is_no_reorder
)
10917 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10918 if (prop_flags
->insn
.is_abslit
)
10919 num
|= XTENSA_PROP_INSN_ABSLIT
;
10921 if (prop_flags
->is_align
)
10923 num
|= XTENSA_PROP_ALIGN
;
10924 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10932 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10933 const frag_flags
*prop_flags_2
)
10935 /* Cannot combine with an end marker. */
10937 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10939 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10941 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10944 if (prop_flags_1
->is_insn
)
10946 /* Properties of the beginning of the frag. */
10947 if (prop_flags_2
->insn
.is_loop_target
)
10949 if (prop_flags_2
->insn
.is_branch_target
)
10951 if (prop_flags_1
->insn
.is_no_density
!=
10952 prop_flags_2
->insn
.is_no_density
)
10954 if (prop_flags_1
->insn
.is_no_transform
!=
10955 prop_flags_2
->insn
.is_no_transform
)
10957 if (prop_flags_1
->insn
.is_no_reorder
!=
10958 prop_flags_2
->insn
.is_no_reorder
)
10960 if (prop_flags_1
->insn
.is_abslit
!=
10961 prop_flags_2
->insn
.is_abslit
)
10965 if (prop_flags_1
->is_align
)
10973 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10978 if (!xt_block
->flags
.is_align
)
10979 return xt_block
->size
;
10981 end_addr
= xt_block
->offset
+ xt_block
->size
;
10982 align_bits
= xt_block
->flags
.alignment
;
10983 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10984 return end_addr
- xt_block
->offset
;
10989 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10990 const xtensa_block_info
*xt_block_2
)
10992 if (xt_block
->sec
!= xt_block_2
->sec
)
10994 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10995 != xt_block_2
->offset
)
10998 if (xt_block_2
->size
== 0
10999 && (!xt_block_2
->flags
.is_unreachable
11000 || xt_block
->flags
.is_unreachable
))
11002 if (xt_block_2
->flags
.is_align
11003 && xt_block
->flags
.is_align
)
11005 /* Nothing needed. */
11006 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11011 if (xt_block_2
->flags
.is_align
)
11013 /* Push alignment to previous entry. */
11014 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11015 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11020 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11021 &xt_block_2
->flags
))
11024 xt_block
->size
+= xt_block_2
->size
;
11026 if (xt_block_2
->flags
.is_align
)
11028 xt_block
->flags
.is_align
= TRUE
;
11029 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11037 add_xt_prop_frags (segT sec
,
11039 xtensa_block_info
**xt_block
,
11040 frag_flags_fn property_function
)
11042 segment_info_type
*seg_info
;
11043 segment_info_type
*xt_seg_info
;
11044 bfd_vma seg_offset
;
11047 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
11048 seg_info
= retrieve_segment_info (sec
);
11049 /* Build it if needed. */
11050 while (*xt_block
!= NULL
)
11052 xt_block
= &(*xt_block
)->next
;
11054 /* We are either at NULL at the beginning or at the end. */
11056 /* Walk through the frags. */
11059 if (seg_info
->frchainP
)
11061 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
11062 fragP
= fragP
->fr_next
)
11064 xtensa_block_info tmp_block
;
11065 tmp_block
.sec
= sec
;
11066 tmp_block
.offset
= fragP
->fr_address
;
11067 tmp_block
.size
= fragP
->fr_fix
;
11068 tmp_block
.next
= NULL
;
11069 property_function (fragP
, &tmp_block
.flags
);
11071 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11072 /* && fragP->fr_fix != 0) */
11074 if ((*xt_block
) == NULL
11075 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11077 xtensa_block_info
*new_block
;
11078 if ((*xt_block
) != NULL
)
11079 xt_block
= &(*xt_block
)->next
;
11080 new_block
= (xtensa_block_info
*)
11081 xmalloc (sizeof (xtensa_block_info
));
11082 *new_block
= tmp_block
;
11083 *xt_block
= new_block
;
11091 /* op_placement_info_table */
11093 /* op_placement_info makes it easier to determine which
11094 ops can go in which slots. */
11097 init_op_placement_info_table (void)
11099 xtensa_isa isa
= xtensa_default_isa
;
11100 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11101 xtensa_opcode opcode
;
11104 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11106 op_placement_table
= (op_placement_info_table
)
11107 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11108 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11110 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11112 op_placement_info
*opi
= &op_placement_table
[opcode
];
11113 /* FIXME: Make tinsn allocation dynamic. */
11114 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
11115 as_fatal (_("too many operands in instruction"));
11116 opi
->single
= XTENSA_UNDEFINED
;
11117 opi
->single_size
= 0;
11118 opi
->widest
= XTENSA_UNDEFINED
;
11119 opi
->widest_size
= 0;
11120 opi
->narrowest
= XTENSA_UNDEFINED
;
11121 opi
->narrowest_size
= 0x7F;
11123 opi
->num_formats
= 0;
11125 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11127 opi
->slots
[fmt
] = 0;
11128 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11130 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11132 int fmt_length
= xtensa_format_length (isa
, fmt
);
11134 set_bit (fmt
, opi
->formats
);
11135 set_bit (slot
, opi
->slots
[fmt
]);
11136 /* opi->slot_count[fmt]++; */
11137 if (fmt_length
< opi
->narrowest_size
)
11139 opi
->narrowest
= fmt
;
11140 opi
->narrowest_size
= fmt_length
;
11142 if (fmt_length
> opi
->widest_size
)
11145 opi
->widest_size
= fmt_length
;
11147 if (xtensa_format_num_slots (isa
, fmt
) == 1)
11149 if (opi
->single_size
== 0
11150 || fmt_length
< opi
->single_size
)
11153 opi
->single_size
= fmt_length
;
11159 opi
->num_formats
++;
11162 xtensa_insnbuf_free (isa
, ibuf
);
11167 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11169 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11173 /* If the opcode is available in a single slot format, return its size. */
11176 xg_get_single_size (xtensa_opcode opcode
)
11178 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
11179 return op_placement_table
[opcode
].single_size
;
11183 static xtensa_format
11184 xg_get_single_format (xtensa_opcode opcode
)
11186 return op_placement_table
[opcode
].single
;
11190 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11193 istack_init (IStack
*stack
)
11195 memset (stack
, 0, sizeof (IStack
));
11201 istack_empty (IStack
*stack
)
11203 return (stack
->ninsn
== 0);
11208 istack_full (IStack
*stack
)
11210 return (stack
->ninsn
== MAX_ISTACK
);
11214 /* Return a pointer to the top IStack entry.
11215 It is an error to call this if istack_empty () is TRUE. */
11218 istack_top (IStack
*stack
)
11220 int rec
= stack
->ninsn
- 1;
11221 assert (!istack_empty (stack
));
11222 return &stack
->insn
[rec
];
11226 /* Add a new TInsn to an IStack.
11227 It is an error to call this if istack_full () is TRUE. */
11230 istack_push (IStack
*stack
, TInsn
*insn
)
11232 int rec
= stack
->ninsn
;
11233 assert (!istack_full (stack
));
11234 stack
->insn
[rec
] = *insn
;
11239 /* Clear space for the next TInsn on the IStack and return a pointer
11240 to it. It is an error to call this if istack_full () is TRUE. */
11243 istack_push_space (IStack
*stack
)
11245 int rec
= stack
->ninsn
;
11247 assert (!istack_full (stack
));
11248 insn
= &stack
->insn
[rec
];
11249 memset (insn
, 0, sizeof (TInsn
));
11255 /* Remove the last pushed instruction. It is an error to call this if
11256 istack_empty () returns TRUE. */
11259 istack_pop (IStack
*stack
)
11261 int rec
= stack
->ninsn
- 1;
11262 assert (!istack_empty (stack
));
11264 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11268 /* TInsn functions. */
11271 tinsn_init (TInsn
*dst
)
11273 memset (dst
, 0, sizeof (TInsn
));
11277 /* Get the ``num''th token of the TInsn.
11278 It is illegal to call this if num > insn->ntoks. */
11281 tinsn_get_tok (TInsn
*insn
, int num
)
11283 assert (num
< insn
->ntok
);
11284 return &insn
->tok
[num
];
11288 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11291 tinsn_has_symbolic_operands (const TInsn
*insn
)
11294 int n
= insn
->ntok
;
11296 assert (insn
->insn_type
== ITYPE_INSN
);
11298 for (i
= 0; i
< n
; ++i
)
11300 switch (insn
->tok
[i
].X_op
)
11314 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11316 xtensa_isa isa
= xtensa_default_isa
;
11318 int n
= insn
->ntok
;
11320 assert (insn
->insn_type
== ITYPE_INSN
);
11322 for (i
= 0; i
< n
; ++i
)
11324 switch (insn
->tok
[i
].X_op
)
11332 /* Errors for these types are caught later. */
11337 /* Symbolic immediates are only allowed on the last immediate
11338 operand. At this time, CONST16 is the only opcode where we
11339 support non-PC-relative relocations. (It isn't necessary
11340 to complain about non-PC-relative relocations here, but
11341 otherwise, no error is reported until the relocations are
11342 generated, and the assembler won't get that far if there
11343 are any other errors. It's nice to see all the problems
11345 if (i
!= get_relaxable_immed (insn
->opcode
)
11346 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11347 && insn
->opcode
!= xtensa_const16_opcode
))
11349 as_bad (_("invalid symbolic operand %d on '%s'"),
11350 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11359 /* For assembly code with complex expressions (e.g. subtraction),
11360 we have to build them in the literal pool so that
11361 their results are calculated correctly after relaxation.
11362 The relaxation only handles expressions that
11363 boil down to SYMBOL + OFFSET. */
11366 tinsn_has_complex_operands (const TInsn
*insn
)
11369 int n
= insn
->ntok
;
11370 assert (insn
->insn_type
== ITYPE_INSN
);
11371 for (i
= 0; i
< n
; ++i
)
11373 switch (insn
->tok
[i
].X_op
)
11389 /* Convert the constant operands in the tinsn to insnbuf.
11390 Return TRUE if there is a symbol in the immediate field.
11392 Before this is called,
11393 1) the number of operands are correct
11394 2) the tinsn is a ITYPE_INSN
11395 3) ONLY the relaxable_ is built
11396 4) All operands are O_constant, O_symbol. All constants fit
11397 The return value tells whether there are any remaining O_symbols. */
11400 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11402 static xtensa_insnbuf slotbuf
= 0;
11403 xtensa_isa isa
= xtensa_default_isa
;
11404 xtensa_opcode opcode
= tinsn
->opcode
;
11405 xtensa_format fmt
= xg_get_single_format (opcode
);
11406 bfd_boolean has_fixup
= FALSE
;
11407 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11414 slotbuf
= xtensa_insnbuf_alloc (isa
);
11416 assert (tinsn
->insn_type
== ITYPE_INSN
);
11417 if (noperands
!= tinsn
->ntok
)
11418 as_fatal (_("operand number mismatch"));
11420 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11421 as_fatal (_("cannot encode opcode"));
11423 for (i
= 0; i
< noperands
; ++i
)
11425 expressionS
*expr
= &tinsn
->tok
[i
];
11426 switch (expr
->X_op
)
11429 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11431 /* The register number has already been checked in
11432 expression_maybe_register, so we don't need to check here. */
11433 opnd_value
= expr
->X_add_number
;
11434 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11435 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11436 slotbuf
, opnd_value
);
11440 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11442 as_where (&file_name
, &line
);
11443 /* It is a constant and we called this function,
11444 then we have to try to fit it. */
11445 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11446 expr
->X_add_number
, file_name
, line
);
11455 xtensa_format_encode (isa
, fmt
, insnbuf
);
11456 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11462 /* Convert the constant operands in the tinsn to slotbuf.
11463 Return TRUE if there is a symbol in the immediate field.
11464 (Eventually this should replace tinsn_to_insnbuf.) */
11466 /* Before this is called,
11467 1) the number of operands are correct
11468 2) the tinsn is a ITYPE_INSN
11469 3) ONLY the relaxable_ is built
11470 4) All operands are
11471 O_constant, O_symbol
11474 The return value tells whether there are any remaining O_symbols. */
11477 tinsn_to_slotbuf (xtensa_format fmt
,
11480 xtensa_insnbuf slotbuf
)
11482 xtensa_isa isa
= xtensa_default_isa
;
11483 xtensa_opcode opcode
= tinsn
->opcode
;
11484 bfd_boolean has_fixup
= FALSE
;
11485 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11488 *((int *) &slotbuf
[0]) = 0;
11489 *((int *) &slotbuf
[1]) = 0;
11490 assert (tinsn
->insn_type
== ITYPE_INSN
);
11491 if (noperands
!= tinsn
->ntok
)
11492 as_fatal (_("operand number mismatch"));
11494 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11496 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11497 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11501 for (i
= 0; i
< noperands
; i
++)
11503 expressionS
*expr
= &tinsn
->tok
[i
];
11508 switch (expr
->X_op
)
11511 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11513 /* The register number has already been checked in
11514 expression_maybe_register, so we don't need to check here. */
11515 opnd_value
= expr
->X_add_number
;
11516 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11517 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11520 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11524 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11526 as_where (&file_name
, &line
);
11527 /* It is a constant and we called this function
11528 then we have to try to fit it. */
11529 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11530 expr
->X_add_number
, file_name
, line
);
11543 /* Check the instruction arguments. Return TRUE on failure. */
11546 tinsn_check_arguments (const TInsn
*insn
)
11548 xtensa_isa isa
= xtensa_default_isa
;
11549 xtensa_opcode opcode
= insn
->opcode
;
11551 if (opcode
== XTENSA_UNDEFINED
)
11553 as_bad (_("invalid opcode"));
11557 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11559 as_bad (_("too few operands"));
11563 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11565 as_bad (_("too many operands"));
11572 /* Load an instruction from its encoded form. */
11575 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11579 xg_init_vinsn (&vinsn
);
11580 vinsn_from_chars (&vinsn
, f
);
11582 *tinsn
= vinsn
.slots
[slot
];
11583 xg_free_vinsn (&vinsn
);
11588 tinsn_from_insnbuf (TInsn
*tinsn
,
11589 xtensa_insnbuf slotbuf
,
11594 xtensa_isa isa
= xtensa_default_isa
;
11596 /* Find the immed. */
11597 tinsn_init (tinsn
);
11598 tinsn
->insn_type
= ITYPE_INSN
;
11599 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11600 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11601 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11602 for (i
= 0; i
< tinsn
->ntok
; i
++)
11604 set_expr_const (&tinsn
->tok
[i
],
11605 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11606 tinsn
->opcode
, i
));
11611 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11614 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11616 xtensa_opcode opcode
= tinsn
->opcode
;
11619 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11621 opnum
= get_relaxable_immed (opcode
);
11622 assert (opnum
>= 0);
11623 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11625 set_expr_symbol_offset_diff
11626 (&tinsn
->tok
[opnum
],
11627 fragP
->tc_frag_data
.slot_symbols
[slot
],
11628 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11629 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11633 set_expr_symbol_offset
11634 (&tinsn
->tok
[opnum
],
11635 fragP
->tc_frag_data
.slot_symbols
[slot
],
11636 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11643 get_num_stack_text_bytes (IStack
*istack
)
11646 int text_bytes
= 0;
11648 for (i
= 0; i
< istack
->ninsn
; i
++)
11650 TInsn
*tinsn
= &istack
->insn
[i
];
11651 if (tinsn
->insn_type
== ITYPE_INSN
)
11652 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11659 get_num_stack_literal_bytes (IStack
*istack
)
11664 for (i
= 0; i
< istack
->ninsn
; i
++)
11666 TInsn
*tinsn
= &istack
->insn
[i
];
11667 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11674 /* vliw_insn functions. */
11677 xg_init_vinsn (vliw_insn
*v
)
11680 xtensa_isa isa
= xtensa_default_isa
;
11682 xg_clear_vinsn (v
);
11684 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11685 if (v
->insnbuf
== NULL
)
11686 as_fatal (_("out of memory"));
11688 for (i
= 0; i
< MAX_SLOTS
; i
++)
11690 tinsn_init (&v
->slots
[i
]);
11691 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11692 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11693 if (v
->slotbuf
[i
] == NULL
)
11694 as_fatal (_("out of memory"));
11700 xg_clear_vinsn (vliw_insn
*v
)
11703 v
->format
= XTENSA_UNDEFINED
;
11705 v
->inside_bundle
= FALSE
;
11707 if (xt_saved_debug_type
!= DEBUG_NONE
)
11708 debug_type
= xt_saved_debug_type
;
11710 for (i
= 0; i
< MAX_SLOTS
; i
++)
11712 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11713 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11719 vinsn_has_specific_opcodes (vliw_insn
*v
)
11723 for (i
= 0; i
< v
->num_slots
; i
++)
11725 if (v
->slots
[i
].is_specific_opcode
)
11733 xg_free_vinsn (vliw_insn
*v
)
11736 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11737 for (i
= 0; i
< MAX_SLOTS
; i
++)
11738 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11742 /* Before this is called, we should have
11743 filled out the following fields:
11745 1) the number of operands for each opcode are correct
11746 2) the tinsn in the slots are ITYPE_INSN
11747 3) ONLY the relaxable_ is built
11748 4) All operands are
11749 O_constant, O_symbol
11752 The return value tells whether there are any remaining O_symbols. */
11755 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11758 bfd_boolean record_fixup
)
11760 xtensa_isa isa
= xtensa_default_isa
;
11761 xtensa_format fmt
= vinsn
->format
;
11762 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11764 bfd_boolean has_fixup
= FALSE
;
11766 xtensa_format_encode (isa
, fmt
, insnbuf
);
11768 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11770 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11771 bfd_boolean tinsn_has_fixup
=
11772 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11773 vinsn
->slotbuf
[slot
]);
11775 xtensa_format_set_slot (isa
, fmt
, slot
,
11776 insnbuf
, vinsn
->slotbuf
[slot
]);
11777 /* tinsn_has_fixup tracks if there is a fixup at all.
11778 record_fixup controls globally. I.E., we use this
11779 function from several places, some of which are after
11780 fixups have already been recorded. Finally,
11781 tinsn->record_fixup controls based on the individual ops,
11782 which may or may not need it based on the relaxation
11784 if (tinsn_has_fixup
&& record_fixup
)
11787 xtensa_opcode opcode
= tinsn
->opcode
;
11788 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11791 for (i
= 0; i
< noperands
; i
++)
11793 expressionS
* expr
= &tinsn
->tok
[i
];
11794 switch (expr
->X_op
)
11799 if (get_relaxable_immed (opcode
) == i
)
11801 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11803 if (!xg_add_opcode_fix
11804 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11805 frag_offset
- fragP
->fr_literal
))
11806 as_bad (_("instruction with constant operands does not fit"));
11810 tinsn
->symbol
= expr
->X_add_symbol
;
11811 tinsn
->offset
= expr
->X_add_number
;
11815 as_bad (_("invalid operand %d on '%s'"),
11816 i
, xtensa_opcode_name (isa
, opcode
));
11824 if (get_relaxable_immed (opcode
) == i
)
11826 if (tinsn
->record_fix
)
11827 as_bad (_("invalid subtract operand"));
11830 tinsn
->symbol
= expr
->X_add_symbol
;
11831 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11832 tinsn
->offset
= expr
->X_add_number
;
11836 as_bad (_("invalid operand %d on '%s'"),
11837 i
, xtensa_opcode_name (isa
, opcode
));
11841 as_bad (_("invalid expression for operand %d on '%s'"),
11842 i
, xtensa_opcode_name (isa
, opcode
));
11854 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11856 static xtensa_insnbuf insnbuf
= NULL
;
11857 static xtensa_insnbuf slotbuf
= NULL
;
11860 xtensa_isa isa
= xtensa_default_isa
;
11864 insnbuf
= xtensa_insnbuf_alloc (isa
);
11865 slotbuf
= xtensa_insnbuf_alloc (isa
);
11868 xtensa_insnbuf_from_chars (isa
, insnbuf
, f
, 0);
11869 fmt
= xtensa_format_decode (isa
, insnbuf
);
11870 if (fmt
== XTENSA_UNDEFINED
)
11871 as_fatal (_("cannot decode instruction format"));
11872 vinsn
->format
= fmt
;
11873 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11875 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11877 TInsn
*tinsn
= &vinsn
->slots
[i
];
11878 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11879 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11884 /* Expression utilities. */
11886 /* Return TRUE if the expression is an integer constant. */
11889 expr_is_const (const expressionS
*s
)
11891 return (s
->X_op
== O_constant
);
11895 /* Get the expression constant.
11896 Calling this is illegal if expr_is_const () returns TRUE. */
11899 get_expr_const (const expressionS
*s
)
11901 assert (expr_is_const (s
));
11902 return s
->X_add_number
;
11906 /* Set the expression to a constant value. */
11909 set_expr_const (expressionS
*s
, offsetT val
)
11911 s
->X_op
= O_constant
;
11912 s
->X_add_number
= val
;
11913 s
->X_add_symbol
= NULL
;
11914 s
->X_op_symbol
= NULL
;
11919 expr_is_register (const expressionS
*s
)
11921 return (s
->X_op
== O_register
);
11925 /* Get the expression constant.
11926 Calling this is illegal if expr_is_const () returns TRUE. */
11929 get_expr_register (const expressionS
*s
)
11931 assert (expr_is_register (s
));
11932 return s
->X_add_number
;
11936 /* Set the expression to a symbol + constant offset. */
11939 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11941 s
->X_op
= O_symbol
;
11942 s
->X_add_symbol
= sym
;
11943 s
->X_op_symbol
= NULL
; /* unused */
11944 s
->X_add_number
= offset
;
11948 /* Set the expression to symbol - minus_sym + offset. */
11951 set_expr_symbol_offset_diff (expressionS
*s
,
11953 symbolS
*minus_sym
,
11956 s
->X_op
= O_subtract
;
11957 s
->X_add_symbol
= sym
;
11958 s
->X_op_symbol
= minus_sym
; /* unused */
11959 s
->X_add_number
= offset
;
11963 /* Return TRUE if the two expressions are equal. */
11966 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11968 if (s1
->X_op
!= s2
->X_op
)
11970 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11972 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11974 if (s1
->X_add_number
!= s2
->X_add_number
)
11981 copy_expr (expressionS
*dst
, const expressionS
*src
)
11983 memcpy (dst
, src
, sizeof (expressionS
));
11987 /* Support for the "--rename-section" option. */
11989 struct rename_section_struct
11993 struct rename_section_struct
*next
;
11996 static struct rename_section_struct
*section_rename
;
11999 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
12000 entries to the section_rename list. Note: Specifying multiple
12001 renamings separated by colons is not documented and is retained only
12002 for backward compatibility. */
12005 build_section_rename (const char *arg
)
12007 struct rename_section_struct
*r
;
12008 char *this_arg
= NULL
;
12009 char *next_arg
= NULL
;
12011 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
12013 char *old_name
, *new_name
;
12017 next_arg
= strchr (this_arg
, ':');
12025 old_name
= this_arg
;
12026 new_name
= strchr (this_arg
, '=');
12028 if (*old_name
== '\0')
12030 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12033 if (!new_name
|| new_name
[1] == '\0')
12035 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12042 /* Check for invalid section renaming. */
12043 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12045 if (strcmp (r
->old_name
, old_name
) == 0)
12046 as_bad (_("section %s renamed multiple times"), old_name
);
12047 if (strcmp (r
->new_name
, new_name
) == 0)
12048 as_bad (_("multiple sections remapped to output section %s"),
12053 r
= (struct rename_section_struct
*)
12054 xmalloc (sizeof (struct rename_section_struct
));
12055 r
->old_name
= xstrdup (old_name
);
12056 r
->new_name
= xstrdup (new_name
);
12057 r
->next
= section_rename
;
12058 section_rename
= r
;
12064 xtensa_section_rename (char *name
)
12066 struct rename_section_struct
*r
= section_rename
;
12068 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12070 if (strcmp (r
->old_name
, name
) == 0)
12071 return r
->new_name
;