1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_num_pipe_stages
;
80 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg
;
121 static lit_state default_lit_sections
;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct
*next
;
150 static sym_list
*insn_labels
= NULL
;
151 static sym_list
*free_insn_labels
= NULL
;
152 static sym_list
*saved_insn_labels
= NULL
;
154 static sym_list
*literal_syms
;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16
= 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals
= 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
266 /* is_specific_opcode implies no_transform. */
267 unsigned is_no_transform
: 1;
271 unsigned is_loop_target
: 1;
272 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority
: 2;
275 unsigned is_no_density
: 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
278 unsigned is_no_reorder
: 1;
280 /* Uses absolute literal addressing for l32r. */
281 unsigned is_abslit
: 1;
283 unsigned is_align
: 1;
284 unsigned alignment
: 5;
288 /* Structure for saving information about a block of property data
289 for frags that have the same flags. */
290 struct xtensa_block_info_struct
296 struct xtensa_block_info_struct
*next
;
300 /* Structure for saving the current state before emitting literals. */
301 typedef struct emit_state_struct
306 int generating_literals
;
310 /* Opcode placement information */
312 typedef unsigned long long bitfield
;
313 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
314 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
315 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317 #define MAX_FORMATS 32
319 typedef struct op_placement_info_struct
322 /* A number describing how restrictive the issue is for this
323 opcode. For example, an opcode that fits lots of different
324 formats has a high freedom, as does an opcode that fits
325 only one format but many slots in that format. The most
326 restrictive is the opcode that fits only one slot in one
329 xtensa_format narrowest
;
333 /* formats is a bitfield with the Nth bit set
334 if the opcode fits in the Nth xtensa_format. */
337 /* slots[N]'s Mth bit is set if the op fits in the
338 Mth slot of the Nth xtensa_format. */
339 bitfield slots
[MAX_FORMATS
];
341 /* A count of the number of slots in a given format
342 an op can fit (i.e., the bitcount of the slot field above). */
343 char slots_in_format
[MAX_FORMATS
];
345 } op_placement_info
, *op_placement_info_table
;
347 op_placement_info_table op_placement_table
;
350 /* Extra expression types. */
352 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
353 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
354 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 #define O_pcrel O_md4 /* value is a PC-relative offset */
356 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
357 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
358 #define O_tlscall O_md7 /* TLS_CALL relocation */
359 #define O_tpoff O_md8 /* TPOFF relocation */
360 #define O_dtpoff O_md9 /* DTPOFF relocation */
362 struct suffix_reloc_map
366 bfd_reloc_code_real_type reloc
;
370 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
372 static struct suffix_reloc_map suffix_relocs
[] =
374 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
375 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
376 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
377 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
378 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
379 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
380 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
381 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
382 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
383 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
397 directive_literal_prefix
,
399 directive_absolute_literals
,
400 directive_last_directive
406 bfd_boolean can_be_negated
;
409 const directive_infoS directive_info
[] =
412 { "literal", FALSE
},
414 { "transform", TRUE
},
415 { "freeregs", FALSE
},
416 { "longcalls", TRUE
},
417 { "literal_prefix", FALSE
},
418 { "schedule", TRUE
},
419 { "absolute-literals", TRUE
}
422 bfd_boolean directive_state
[] =
426 #if !XCHAL_HAVE_DENSITY
431 TRUE
, /* transform */
432 FALSE
, /* freeregs */
433 FALSE
, /* longcalls */
434 FALSE
, /* literal_prefix */
435 FALSE
, /* schedule */
436 #if XSHAL_USE_ABSOLUTE_LITERALS
437 TRUE
/* absolute_literals */
439 FALSE
/* absolute_literals */
443 /* A circular list of all potential and actual literal pool locations
447 struct litpool_frag
*next
;
448 struct litpool_frag
*prev
;
451 short priority
; /* 1, 2, or 3 -- 1 is highest */
452 short original_priority
;
455 /* Map a segment to its litpool_frag list. */
458 struct litpool_seg
*next
;
460 struct litpool_frag frag_list
;
461 int frag_count
; /* since last litpool location */
464 static struct litpool_seg litpool_seg_list
;
467 /* Directive functions. */
469 static void xtensa_begin_directive (int);
470 static void xtensa_end_directive (int);
471 static void xtensa_literal_prefix (void);
472 static void xtensa_literal_position (int);
473 static void xtensa_literal_pseudo (int);
474 static void xtensa_frequency_pseudo (int);
475 static void xtensa_elf_cons (int);
476 static void xtensa_leb128 (int);
478 /* Parsing and Idiom Translation. */
480 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
482 /* Various Other Internal Functions. */
484 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
485 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
486 static void xtensa_mark_literal_pool_location (void);
487 static addressT
get_expanded_loop_offset (xtensa_opcode
);
488 static fragS
*get_literal_pool_location (segT
);
489 static void set_literal_pool_location (segT
, fragS
*);
490 static void xtensa_set_frag_assembly_state (fragS
*);
491 static void finish_vinsn (vliw_insn
*);
492 static bfd_boolean
emit_single_op (TInsn
*);
493 static int total_frag_text_expansion (fragS
*);
494 static bfd_boolean use_trampolines
= TRUE
;
495 static void xtensa_check_frag_count (void);
496 static void xtensa_create_trampoline_frag (bfd_boolean
);
497 static void xtensa_maybe_create_trampoline_frag (void);
498 struct trampoline_frag
;
499 static int init_trampoline_frag (struct trampoline_frag
*);
500 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
501 static bfd_boolean auto_litpools
= FALSE
;
502 static int auto_litpool_limit
= 10000;
504 /* Alignment Functions. */
506 static int get_text_align_power (unsigned);
507 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
508 static int branch_align_power (segT
);
510 /* Helpers for xtensa_relax_frag(). */
512 static long relax_frag_add_nop (fragS
*);
514 /* Accessors for additional per-subsegment information. */
516 static unsigned get_last_insn_flags (segT
, subsegT
);
517 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
518 static float get_subseg_total_freq (segT
, subsegT
);
519 static float get_subseg_target_freq (segT
, subsegT
);
520 static void set_subseg_freq (segT
, subsegT
, float, float);
522 /* Segment list functions. */
524 static void xtensa_move_literals (void);
525 static void xtensa_reorder_segments (void);
526 static void xtensa_switch_to_literal_fragment (emit_state
*);
527 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
528 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
529 static void xtensa_restore_emit_state (emit_state
*);
530 static segT
cache_literal_section (bfd_boolean
);
532 /* Import from elf32-xtensa.c in BFD library. */
534 extern asection
*xtensa_make_property_section (asection
*, const char *);
536 /* op_placement_info functions. */
538 static void init_op_placement_info_table (void);
539 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
540 static int xg_get_single_size (xtensa_opcode
);
541 static xtensa_format
xg_get_single_format (xtensa_opcode
);
542 static int xg_get_single_slot (xtensa_opcode
);
544 /* TInsn and IStack functions. */
546 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
547 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
548 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
549 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
550 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
551 static void tinsn_from_chars (TInsn
*, char *, int);
552 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
553 static int get_num_stack_text_bytes (IStack
*);
554 static int get_num_stack_literal_bytes (IStack
*);
555 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
557 /* vliw_insn functions. */
559 static void xg_init_vinsn (vliw_insn
*);
560 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
561 static void xg_clear_vinsn (vliw_insn
*);
562 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
563 static void xg_free_vinsn (vliw_insn
*);
564 static bfd_boolean vinsn_to_insnbuf
565 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
566 static void vinsn_from_chars (vliw_insn
*, char *);
568 /* Expression Utilities. */
570 bfd_boolean
expr_is_const (const expressionS
*);
571 offsetT
get_expr_const (const expressionS
*);
572 void set_expr_const (expressionS
*, offsetT
);
573 bfd_boolean
expr_is_register (const expressionS
*);
574 offsetT
get_expr_register (const expressionS
*);
575 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
576 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
577 static void copy_expr (expressionS
*, const expressionS
*);
579 /* Section renaming. */
581 static void build_section_rename (const char *);
584 /* ISA imported from bfd. */
585 extern xtensa_isa xtensa_default_isa
;
587 extern int target_big_endian
;
589 static xtensa_opcode xtensa_addi_opcode
;
590 static xtensa_opcode xtensa_addmi_opcode
;
591 static xtensa_opcode xtensa_call0_opcode
;
592 static xtensa_opcode xtensa_call4_opcode
;
593 static xtensa_opcode xtensa_call8_opcode
;
594 static xtensa_opcode xtensa_call12_opcode
;
595 static xtensa_opcode xtensa_callx0_opcode
;
596 static xtensa_opcode xtensa_callx4_opcode
;
597 static xtensa_opcode xtensa_callx8_opcode
;
598 static xtensa_opcode xtensa_callx12_opcode
;
599 static xtensa_opcode xtensa_const16_opcode
;
600 static xtensa_opcode xtensa_entry_opcode
;
601 static xtensa_opcode xtensa_extui_opcode
;
602 static xtensa_opcode xtensa_movi_opcode
;
603 static xtensa_opcode xtensa_movi_n_opcode
;
604 static xtensa_opcode xtensa_isync_opcode
;
605 static xtensa_opcode xtensa_j_opcode
;
606 static xtensa_opcode xtensa_jx_opcode
;
607 static xtensa_opcode xtensa_l32r_opcode
;
608 static xtensa_opcode xtensa_loop_opcode
;
609 static xtensa_opcode xtensa_loopnez_opcode
;
610 static xtensa_opcode xtensa_loopgtz_opcode
;
611 static xtensa_opcode xtensa_nop_opcode
;
612 static xtensa_opcode xtensa_nop_n_opcode
;
613 static xtensa_opcode xtensa_or_opcode
;
614 static xtensa_opcode xtensa_ret_opcode
;
615 static xtensa_opcode xtensa_ret_n_opcode
;
616 static xtensa_opcode xtensa_retw_opcode
;
617 static xtensa_opcode xtensa_retw_n_opcode
;
618 static xtensa_opcode xtensa_rsr_lcount_opcode
;
619 static xtensa_opcode xtensa_waiti_opcode
;
620 static int config_max_slots
= 0;
623 /* Command-line Options. */
625 bfd_boolean use_literal_section
= TRUE
;
626 enum flix_level produce_flix
= FLIX_ALL
;
627 static bfd_boolean align_targets
= TRUE
;
628 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
629 static bfd_boolean has_a0_b_retw
= FALSE
;
630 static bfd_boolean workaround_a0_b_retw
= FALSE
;
631 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
632 static bfd_boolean workaround_short_loop
= FALSE
;
633 static bfd_boolean maybe_has_short_loop
= FALSE
;
634 static bfd_boolean workaround_close_loop_end
= FALSE
;
635 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
636 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
638 /* When workaround_short_loops is TRUE, all loops with early exits must
639 have at least 3 instructions. workaround_all_short_loops is a modifier
640 to the workaround_short_loop flag. In addition to the
641 workaround_short_loop actions, all straightline loopgtz and loopnez
642 must have at least 3 instructions. */
644 static bfd_boolean workaround_all_short_loops
= FALSE
;
648 xtensa_setup_hw_workarounds (int earliest
, int latest
)
650 if (earliest
> latest
)
651 as_fatal (_("illegal range of target hardware versions"));
653 /* Enable all workarounds for pre-T1050.0 hardware. */
654 if (earliest
< 105000 || latest
< 105000)
656 workaround_a0_b_retw
|= TRUE
;
657 workaround_b_j_loop_end
|= TRUE
;
658 workaround_short_loop
|= TRUE
;
659 workaround_close_loop_end
|= TRUE
;
660 workaround_all_short_loops
|= TRUE
;
661 enforce_three_byte_loop_align
= TRUE
;
668 option_density
= OPTION_MD_BASE
,
672 option_no_generate_flix
,
679 option_no_link_relax
,
687 option_text_section_literals
,
688 option_no_text_section_literals
,
690 option_absolute_literals
,
691 option_no_absolute_literals
,
693 option_align_targets
,
694 option_no_align_targets
,
696 option_warn_unaligned_targets
,
701 option_workaround_a0_b_retw
,
702 option_no_workaround_a0_b_retw
,
704 option_workaround_b_j_loop_end
,
705 option_no_workaround_b_j_loop_end
,
707 option_workaround_short_loop
,
708 option_no_workaround_short_loop
,
710 option_workaround_all_short_loops
,
711 option_no_workaround_all_short_loops
,
713 option_workaround_close_loop_end
,
714 option_no_workaround_close_loop_end
,
716 option_no_workarounds
,
718 option_rename_section_name
,
721 option_prefer_const16
,
723 option_target_hardware
,
726 option_no_trampolines
,
728 option_auto_litpools
,
729 option_no_auto_litpools
,
730 option_auto_litpool_limit
,
733 const char *md_shortopts
= "";
735 struct option md_longopts
[] =
737 { "density", no_argument
, NULL
, option_density
},
738 { "no-density", no_argument
, NULL
, option_no_density
},
740 { "flix", no_argument
, NULL
, option_flix
},
741 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
742 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
744 /* Both "relax" and "generics" are deprecated and treated as equivalent
745 to the "transform" option. */
746 { "relax", no_argument
, NULL
, option_relax
},
747 { "no-relax", no_argument
, NULL
, option_no_relax
},
748 { "generics", no_argument
, NULL
, option_generics
},
749 { "no-generics", no_argument
, NULL
, option_no_generics
},
751 { "transform", no_argument
, NULL
, option_transform
},
752 { "no-transform", no_argument
, NULL
, option_no_transform
},
753 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
754 { "no-text-section-literals", no_argument
, NULL
,
755 option_no_text_section_literals
},
756 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
757 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
758 /* This option was changed from -align-target to -target-align
759 because it conflicted with the "-al" option. */
760 { "target-align", no_argument
, NULL
, option_align_targets
},
761 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
762 { "warn-unaligned-targets", no_argument
, NULL
,
763 option_warn_unaligned_targets
},
764 { "longcalls", no_argument
, NULL
, option_longcalls
},
765 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
767 { "no-workaround-a0-b-retw", no_argument
, NULL
,
768 option_no_workaround_a0_b_retw
},
769 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
771 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
772 option_no_workaround_b_j_loop_end
},
773 { "workaround-b-j-loop-end", no_argument
, NULL
,
774 option_workaround_b_j_loop_end
},
776 { "no-workaround-short-loops", no_argument
, NULL
,
777 option_no_workaround_short_loop
},
778 { "workaround-short-loops", no_argument
, NULL
,
779 option_workaround_short_loop
},
781 { "no-workaround-all-short-loops", no_argument
, NULL
,
782 option_no_workaround_all_short_loops
},
783 { "workaround-all-short-loop", no_argument
, NULL
,
784 option_workaround_all_short_loops
},
786 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
787 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
789 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
791 { "no-workaround-close-loop-end", no_argument
, NULL
,
792 option_no_workaround_close_loop_end
},
793 { "workaround-close-loop-end", no_argument
, NULL
,
794 option_workaround_close_loop_end
},
796 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
798 { "link-relax", no_argument
, NULL
, option_link_relax
},
799 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
801 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
803 { "trampolines", no_argument
, NULL
, option_trampolines
},
804 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
806 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
807 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
808 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
810 { NULL
, no_argument
, NULL
, 0 }
813 size_t md_longopts_size
= sizeof md_longopts
;
817 md_parse_option (int c
, const char *arg
)
822 as_warn (_("--density option is ignored"));
824 case option_no_density
:
825 as_warn (_("--no-density option is ignored"));
827 case option_link_relax
:
830 case option_no_link_relax
:
834 produce_flix
= FLIX_ALL
;
836 case option_no_generate_flix
:
837 produce_flix
= FLIX_NO_GENERATE
;
840 produce_flix
= FLIX_NONE
;
842 case option_generics
:
843 as_warn (_("--generics is deprecated; use --transform instead"));
844 return md_parse_option (option_transform
, arg
);
845 case option_no_generics
:
846 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
847 return md_parse_option (option_no_transform
, arg
);
849 as_warn (_("--relax is deprecated; use --transform instead"));
850 return md_parse_option (option_transform
, arg
);
851 case option_no_relax
:
852 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
853 return md_parse_option (option_no_transform
, arg
);
854 case option_longcalls
:
855 directive_state
[directive_longcalls
] = TRUE
;
857 case option_no_longcalls
:
858 directive_state
[directive_longcalls
] = FALSE
;
860 case option_text_section_literals
:
861 use_literal_section
= FALSE
;
863 case option_no_text_section_literals
:
864 use_literal_section
= TRUE
;
866 case option_absolute_literals
:
867 if (!absolute_literals_supported
)
869 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
872 directive_state
[directive_absolute_literals
] = TRUE
;
874 case option_no_absolute_literals
:
875 directive_state
[directive_absolute_literals
] = FALSE
;
878 case option_workaround_a0_b_retw
:
879 workaround_a0_b_retw
= TRUE
;
881 case option_no_workaround_a0_b_retw
:
882 workaround_a0_b_retw
= FALSE
;
884 case option_workaround_b_j_loop_end
:
885 workaround_b_j_loop_end
= TRUE
;
887 case option_no_workaround_b_j_loop_end
:
888 workaround_b_j_loop_end
= FALSE
;
891 case option_workaround_short_loop
:
892 workaround_short_loop
= TRUE
;
894 case option_no_workaround_short_loop
:
895 workaround_short_loop
= FALSE
;
898 case option_workaround_all_short_loops
:
899 workaround_all_short_loops
= TRUE
;
901 case option_no_workaround_all_short_loops
:
902 workaround_all_short_loops
= FALSE
;
905 case option_workaround_close_loop_end
:
906 workaround_close_loop_end
= TRUE
;
908 case option_no_workaround_close_loop_end
:
909 workaround_close_loop_end
= FALSE
;
912 case option_no_workarounds
:
913 workaround_a0_b_retw
= FALSE
;
914 workaround_b_j_loop_end
= FALSE
;
915 workaround_short_loop
= FALSE
;
916 workaround_all_short_loops
= FALSE
;
917 workaround_close_loop_end
= FALSE
;
920 case option_align_targets
:
921 align_targets
= TRUE
;
923 case option_no_align_targets
:
924 align_targets
= FALSE
;
927 case option_warn_unaligned_targets
:
928 warn_unaligned_branch_targets
= TRUE
;
931 case option_rename_section_name
:
932 build_section_rename (arg
);
936 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
937 should be emitted or not. FIXME: Not implemented. */
940 case option_prefer_l32r
:
942 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
946 case option_prefer_const16
:
948 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
952 case option_target_hardware
:
954 int earliest
, latest
= 0;
956 if (*arg
== 0 || *arg
== '-')
957 as_fatal (_("invalid target hardware version"));
959 earliest
= strtol (arg
, &end
, 0);
963 else if (*end
== '-')
966 as_fatal (_("invalid target hardware version"));
967 latest
= strtol (end
, &end
, 0);
970 as_fatal (_("invalid target hardware version"));
972 xtensa_setup_hw_workarounds (earliest
, latest
);
976 case option_transform
:
977 /* This option has no affect other than to use the defaults,
978 which are already set. */
981 case option_no_transform
:
982 /* This option turns off all transformations of any kind.
983 However, because we want to preserve the state of other
984 directives, we only change its own field. Thus, before
985 you perform any transformation, always check if transform
986 is available. If you use the functions we provide for this
987 purpose, you will be ok. */
988 directive_state
[directive_transform
] = FALSE
;
991 case option_trampolines
:
992 use_trampolines
= TRUE
;
995 case option_no_trampolines
:
996 use_trampolines
= FALSE
;
999 case option_auto_litpools
:
1000 auto_litpools
= TRUE
;
1001 use_literal_section
= FALSE
;
1004 case option_no_auto_litpools
:
1005 auto_litpools
= FALSE
;
1006 auto_litpool_limit
= -1;
1009 case option_auto_litpool_limit
:
1013 if (auto_litpool_limit
< 0)
1014 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1015 if (*arg
== 0 || *arg
== '-')
1016 as_fatal (_("invalid auto-litpool-limit argument"));
1017 value
= strtol (arg
, &end
, 10);
1019 as_fatal (_("invalid auto-litpool-limit argument"));
1020 if (value
< 100 || value
> 10000)
1021 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1022 auto_litpool_limit
= value
;
1023 auto_litpools
= TRUE
;
1024 use_literal_section
= FALSE
;
1035 md_show_usage (FILE *stream
)
1039 --[no-]text-section-literals\n\
1040 [Do not] put literals in the text section\n\
1041 --[no-]absolute-literals\n\
1042 [Do not] default to use non-PC-relative literals\n\
1043 --[no-]target-align [Do not] try to align branch targets\n\
1044 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1045 --[no-]transform [Do not] transform instructions\n\
1046 --flix both allow hand-written and generate flix bundles\n\
1047 --no-generate-flix allow hand-written but do not generate\n\
1049 --no-allow-flix neither allow hand-written nor generate\n\
1051 --rename-section old=new Rename section 'old' to 'new'\n\
1052 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1053 when jumps do not reach their targets\n\
1054 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1055 --auto-litpool-limit=<value>\n\
1056 (range 100-10000) Maximum number of blocks of\n\
1057 instructions to emit between literal pool\n\
1058 locations; implies --auto-litpools flag\n", stream
);
1062 /* Functions related to the list of current label symbols. */
1065 xtensa_add_insn_label (symbolS
*sym
)
1069 if (!free_insn_labels
)
1070 l
= XNEW (sym_list
);
1073 l
= free_insn_labels
;
1074 free_insn_labels
= l
->next
;
1078 l
->next
= insn_labels
;
1084 xtensa_clear_insn_labels (void)
1088 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1096 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1100 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1102 symbolS
*lit_sym
= lit
->sym
;
1103 S_SET_VALUE (lit_sym
, new_offset
);
1104 symbol_set_frag (lit_sym
, new_frag
);
1109 /* Directive data and functions. */
1111 typedef struct state_stackS_struct
1113 directiveE directive
;
1114 bfd_boolean negated
;
1115 bfd_boolean old_state
;
1119 struct state_stackS_struct
*prev
;
1122 state_stackS
*directive_state_stack
;
1124 const pseudo_typeS md_pseudo_table
[] =
1126 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1127 { "literal_position", xtensa_literal_position
, 0 },
1128 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1129 { "long", xtensa_elf_cons
, 4 },
1130 { "word", xtensa_elf_cons
, 4 },
1131 { "4byte", xtensa_elf_cons
, 4 },
1132 { "short", xtensa_elf_cons
, 2 },
1133 { "2byte", xtensa_elf_cons
, 2 },
1134 { "sleb128", xtensa_leb128
, 1},
1135 { "uleb128", xtensa_leb128
, 0},
1136 { "begin", xtensa_begin_directive
, 0 },
1137 { "end", xtensa_end_directive
, 0 },
1138 { "literal", xtensa_literal_pseudo
, 0 },
1139 { "frequency", xtensa_frequency_pseudo
, 0 },
1145 use_transform (void)
1147 /* After md_end, you should be checking frag by frag, rather
1148 than state directives. */
1149 gas_assert (!past_xtensa_end
);
1150 return directive_state
[directive_transform
];
1155 do_align_targets (void)
1157 /* Do not use this function after md_end; just look at align_targets
1158 instead. There is no target-align directive, so alignment is either
1159 enabled for all frags or not done at all. */
1160 gas_assert (!past_xtensa_end
);
1161 return align_targets
&& use_transform ();
1166 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1170 state_stackS
*stack
= XNEW (state_stackS
);
1172 file
= as_where (&line
);
1174 stack
->directive
= directive
;
1175 stack
->negated
= negated
;
1176 stack
->old_state
= directive_state
[directive
];
1179 stack
->datum
= datum
;
1180 stack
->prev
= directive_state_stack
;
1181 directive_state_stack
= stack
;
1183 directive_state
[directive
] = !negated
;
1188 directive_pop (directiveE
*directive
,
1189 bfd_boolean
*negated
,
1194 state_stackS
*top
= directive_state_stack
;
1196 if (!directive_state_stack
)
1198 as_bad (_("unmatched end directive"));
1199 *directive
= directive_none
;
1203 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1204 *directive
= top
->directive
;
1205 *negated
= top
->negated
;
1208 *datum
= top
->datum
;
1209 directive_state_stack
= top
->prev
;
1215 directive_balance (void)
1217 while (directive_state_stack
)
1219 directiveE directive
;
1220 bfd_boolean negated
;
1225 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1226 as_warn_where ((char *) file
, line
,
1227 _(".begin directive with no matching .end directive"));
1233 inside_directive (directiveE dir
)
1235 state_stackS
*top
= directive_state_stack
;
1237 while (top
&& top
->directive
!= dir
)
1240 return (top
!= NULL
);
1245 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1249 const char *directive_string
;
1251 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1256 input_line_pointer
+= 3;
1259 len
= strspn (input_line_pointer
,
1260 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1262 /* This code is a hack to make .begin [no-][generics|relax] exactly
1263 equivalent to .begin [no-]transform. We should remove it when
1264 we stop accepting those options. */
1266 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1268 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1269 directive_string
= "transform";
1271 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1273 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1274 directive_string
= "transform";
1277 directive_string
= input_line_pointer
;
1279 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1281 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1283 input_line_pointer
+= len
;
1284 *directive
= (directiveE
) i
;
1285 if (*negated
&& !directive_info
[i
].can_be_negated
)
1286 as_bad (_("directive %s cannot be negated"),
1287 directive_info
[i
].name
);
1292 as_bad (_("unknown directive"));
1293 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1298 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1300 directiveE directive
;
1301 bfd_boolean negated
;
1305 get_directive (&directive
, &negated
);
1306 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1308 discard_rest_of_line ();
1312 if (cur_vinsn
.inside_bundle
)
1313 as_bad (_("directives are not valid inside bundles"));
1317 case directive_literal
:
1318 if (!inside_directive (directive_literal
))
1320 /* Previous labels go with whatever follows this directive, not with
1321 the literal, so save them now. */
1322 saved_insn_labels
= insn_labels
;
1325 as_warn (_(".begin literal is deprecated; use .literal instead"));
1326 state
= XNEW (emit_state
);
1327 xtensa_switch_to_literal_fragment (state
);
1328 directive_push (directive_literal
, negated
, state
);
1331 case directive_literal_prefix
:
1332 /* Have to flush pending output because a movi relaxed to an l32r
1333 might produce a literal. */
1334 md_flush_pending_output ();
1335 /* Check to see if the current fragment is a literal
1336 fragment. If it is, then this operation is not allowed. */
1337 if (generating_literals
)
1339 as_bad (_("cannot set literal_prefix inside literal fragment"));
1343 /* Allocate the literal state for this section and push
1344 onto the directive stack. */
1345 ls
= XNEW (lit_state
);
1348 *ls
= default_lit_sections
;
1349 directive_push (directive_literal_prefix
, negated
, ls
);
1351 /* Process the new prefix. */
1352 xtensa_literal_prefix ();
1355 case directive_freeregs
:
1356 /* This information is currently unused, but we'll accept the statement
1357 and just discard the rest of the line. This won't check the syntax,
1358 but it will accept every correct freeregs directive. */
1359 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1360 directive_push (directive_freeregs
, negated
, 0);
1363 case directive_schedule
:
1364 md_flush_pending_output ();
1365 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1366 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1367 directive_push (directive_schedule
, negated
, 0);
1368 xtensa_set_frag_assembly_state (frag_now
);
1371 case directive_density
:
1372 as_warn (_(".begin [no-]density is ignored"));
1375 case directive_absolute_literals
:
1376 md_flush_pending_output ();
1377 if (!absolute_literals_supported
&& !negated
)
1379 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1382 xtensa_set_frag_assembly_state (frag_now
);
1383 directive_push (directive
, negated
, 0);
1387 md_flush_pending_output ();
1388 xtensa_set_frag_assembly_state (frag_now
);
1389 directive_push (directive
, negated
, 0);
1393 demand_empty_rest_of_line ();
1398 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1400 directiveE begin_directive
, end_directive
;
1401 bfd_boolean begin_negated
, end_negated
;
1405 emit_state
**state_ptr
;
1408 if (cur_vinsn
.inside_bundle
)
1409 as_bad (_("directives are not valid inside bundles"));
1411 get_directive (&end_directive
, &end_negated
);
1413 md_flush_pending_output ();
1415 switch ((int) end_directive
)
1417 case XTENSA_UNDEFINED
:
1418 discard_rest_of_line ();
1421 case (int) directive_density
:
1422 as_warn (_(".end [no-]density is ignored"));
1423 demand_empty_rest_of_line ();
1426 case (int) directive_absolute_literals
:
1427 if (!absolute_literals_supported
&& !end_negated
)
1429 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1430 demand_empty_rest_of_line ();
1439 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1440 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1441 (const void **) state_ptr
);
1443 if (begin_directive
!= directive_none
)
1445 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1447 as_bad (_("does not match begin %s%s at %s:%d"),
1448 begin_negated
? "no-" : "",
1449 directive_info
[begin_directive
].name
, file
, line
);
1453 switch (end_directive
)
1455 case directive_literal
:
1456 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1457 xtensa_restore_emit_state (state
);
1458 xtensa_set_frag_assembly_state (frag_now
);
1460 if (!inside_directive (directive_literal
))
1462 /* Restore the list of current labels. */
1463 xtensa_clear_insn_labels ();
1464 insn_labels
= saved_insn_labels
;
1468 case directive_literal_prefix
:
1469 /* Restore the default collection sections from saved state. */
1470 s
= (lit_state
*) state
;
1472 default_lit_sections
= *s
;
1474 /* Free the state storage. */
1475 free (s
->lit_prefix
);
1479 case directive_schedule
:
1480 case directive_freeregs
:
1484 xtensa_set_frag_assembly_state (frag_now
);
1490 demand_empty_rest_of_line ();
1494 /* Place an aligned literal fragment at the current location. */
1497 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1499 md_flush_pending_output ();
1501 if (inside_directive (directive_literal
))
1502 as_warn (_(".literal_position inside literal directive; ignoring"));
1503 xtensa_mark_literal_pool_location ();
1505 demand_empty_rest_of_line ();
1506 xtensa_clear_insn_labels ();
1510 /* Support .literal label, expr, ... */
1513 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1516 char *p
, *base_name
;
1520 if (inside_directive (directive_literal
))
1522 as_bad (_(".literal not allowed inside .begin literal region"));
1523 ignore_rest_of_line ();
1527 md_flush_pending_output ();
1529 /* Previous labels go with whatever follows this directive, not with
1530 the literal, so save them now. */
1531 saved_insn_labels
= insn_labels
;
1534 /* If we are using text-section literals, then this is the right value... */
1537 base_name
= input_line_pointer
;
1539 xtensa_switch_to_literal_fragment (&state
);
1541 /* ...but if we aren't using text-section-literals, then we
1542 need to put them in the section we just switched to. */
1543 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1546 /* FIXME, despite the previous comments, dest_seg is unused... */
1549 /* All literals are aligned to four-byte boundaries. */
1550 frag_align (2, 0, 0);
1551 record_alignment (now_seg
, 2);
1553 c
= get_symbol_name (&base_name
);
1554 /* Just after name is now '\0'. */
1555 p
= input_line_pointer
;
1557 SKIP_WHITESPACE_AFTER_NAME ();
1559 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1561 as_bad (_("expected comma or colon after symbol name; "
1562 "rest of line ignored"));
1563 ignore_rest_of_line ();
1564 xtensa_restore_emit_state (&state
);
1572 input_line_pointer
++; /* skip ',' or ':' */
1574 xtensa_elf_cons (4);
1576 xtensa_restore_emit_state (&state
);
1578 /* Restore the list of current labels. */
1579 xtensa_clear_insn_labels ();
1580 insn_labels
= saved_insn_labels
;
1585 xtensa_literal_prefix (void)
1590 /* Parse the new prefix from the input_line_pointer. */
1592 len
= strspn (input_line_pointer
,
1593 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1594 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1596 /* Get a null-terminated copy of the name. */
1597 name
= xmemdup0 (input_line_pointer
, len
);
1599 /* Skip the name in the input line. */
1600 input_line_pointer
+= len
;
1602 default_lit_sections
.lit_prefix
= name
;
1604 /* Clear cached literal sections, since the prefix has changed. */
1605 default_lit_sections
.lit_seg
= NULL
;
1606 default_lit_sections
.lit4_seg
= NULL
;
1610 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1613 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1615 float fall_through_f
, target_f
;
1617 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1618 if (fall_through_f
< 0)
1620 as_bad (_("fall through frequency must be greater than 0"));
1621 ignore_rest_of_line ();
1625 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1628 as_bad (_("branch target frequency must be greater than 0"));
1629 ignore_rest_of_line ();
1633 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1635 demand_empty_rest_of_line ();
1639 /* Like normal .long/.short/.word, except support @plt, etc.
1640 Clobbers input_line_pointer, checks end-of-line. */
1643 xtensa_elf_cons (int nbytes
)
1646 bfd_reloc_code_real_type reloc
;
1648 md_flush_pending_output ();
1650 if (cur_vinsn
.inside_bundle
)
1651 as_bad (_("directives are not valid inside bundles"));
1653 if (is_it_end_of_statement ())
1655 demand_empty_rest_of_line ();
1662 if (exp
.X_op
== O_symbol
1663 && *input_line_pointer
== '@'
1664 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1667 reloc_howto_type
*reloc_howto
=
1668 bfd_reloc_type_lookup (stdoutput
, reloc
);
1670 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1671 as_bad (_("unsupported relocation"));
1672 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1673 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1674 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1675 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1676 as_bad (_("opcode-specific %s relocation used outside "
1677 "an instruction"), reloc_howto
->name
);
1678 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1679 as_bad (_("%s relocations do not fit in %d bytes"),
1680 reloc_howto
->name
, nbytes
);
1681 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1682 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1683 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1684 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1687 char *p
= frag_more ((int) nbytes
);
1688 xtensa_set_frag_assembly_state (frag_now
);
1689 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1690 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1695 xtensa_set_frag_assembly_state (frag_now
);
1696 emit_expr (&exp
, (unsigned int) nbytes
);
1699 while (*input_line_pointer
++ == ',');
1701 input_line_pointer
--; /* Put terminator back into stream. */
1702 demand_empty_rest_of_line ();
1705 static bfd_boolean is_leb128_expr
;
1708 xtensa_leb128 (int sign
)
1710 is_leb128_expr
= TRUE
;
1712 is_leb128_expr
= FALSE
;
1716 /* Parsing and Idiom Translation. */
1718 /* Parse @plt, etc. and return the desired relocation. */
1719 static bfd_reloc_code_real_type
1720 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1727 struct suffix_reloc_map
*ptr
;
1730 return BFD_RELOC_NONE
;
1732 for (ch
= *str
, str2
= ident
;
1733 (str2
< ident
+ sizeof (ident
) - 1
1734 && (ISALNUM (ch
) || ch
== '@'));
1737 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1744 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1745 if (ch
== ptr
->suffix
[0]
1746 && len
== ptr
->length
1747 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1749 /* Now check for "identifier@suffix+constant". */
1750 if (*str
== '-' || *str
== '+')
1752 char *orig_line
= input_line_pointer
;
1753 expressionS new_exp
;
1755 input_line_pointer
= str
;
1756 expression (&new_exp
);
1757 if (new_exp
.X_op
== O_constant
)
1759 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1760 str
= input_line_pointer
;
1763 if (&input_line_pointer
!= str_p
)
1764 input_line_pointer
= orig_line
;
1771 return BFD_RELOC_UNUSED
;
1775 /* Find the matching operator type. */
1777 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1779 struct suffix_reloc_map
*sfx
;
1780 operatorT
operator = O_illegal
;
1782 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1784 if (sfx
->reloc
== reloc
)
1786 operator = sfx
->operator;
1790 gas_assert (operator != O_illegal
);
1795 /* Find the matching reloc type. */
1796 static bfd_reloc_code_real_type
1797 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1799 struct suffix_reloc_map
*sfx
;
1800 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1802 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1804 if (sfx
->operator == operator)
1813 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1814 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1815 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1816 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1819 if (reloc
== BFD_RELOC_UNUSED
)
1820 return BFD_RELOC_32
;
1827 expression_end (const char *name
)
1850 #define ERROR_REG_NUM ((unsigned) -1)
1853 tc_get_register (const char *prefix
)
1856 const char *next_expr
;
1857 const char *old_line_pointer
;
1860 old_line_pointer
= input_line_pointer
;
1862 if (*input_line_pointer
== '$')
1863 ++input_line_pointer
;
1865 /* Accept "sp" as a synonym for "a1". */
1866 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1867 && expression_end (input_line_pointer
+ 2))
1869 input_line_pointer
+= 2;
1870 return 1; /* AR[1] */
1873 while (*input_line_pointer
++ == *prefix
++)
1875 --input_line_pointer
;
1880 as_bad (_("bad register name: %s"), old_line_pointer
);
1881 return ERROR_REG_NUM
;
1884 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1886 as_bad (_("bad register number: %s"), input_line_pointer
);
1887 return ERROR_REG_NUM
;
1892 while (ISDIGIT ((int) *input_line_pointer
))
1893 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1895 if (!(next_expr
= expression_end (input_line_pointer
)))
1897 as_bad (_("bad register name: %s"), old_line_pointer
);
1898 return ERROR_REG_NUM
;
1901 input_line_pointer
= (char *) next_expr
;
1908 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1910 xtensa_isa isa
= xtensa_default_isa
;
1912 /* Check if this is an immediate operand. */
1913 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1915 bfd_reloc_code_real_type reloc
;
1916 segT t
= expression (tok
);
1918 if (t
== absolute_section
1919 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1921 gas_assert (tok
->X_op
== O_constant
);
1922 tok
->X_op
= O_symbol
;
1923 tok
->X_add_symbol
= &abs_symbol
;
1926 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1927 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1932 case BFD_RELOC_LO16
:
1933 if (tok
->X_op
== O_constant
)
1935 tok
->X_add_number
&= 0xffff;
1939 case BFD_RELOC_HI16
:
1940 if (tok
->X_op
== O_constant
)
1942 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1946 case BFD_RELOC_UNUSED
:
1947 as_bad (_("unsupported relocation"));
1949 case BFD_RELOC_32_PCREL
:
1950 as_bad (_("pcrel relocation not allowed in an instruction"));
1955 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1960 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1961 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1963 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1966 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1967 as_bad (_("register number out of range"));
1970 tok
->X_op
= O_register
;
1971 tok
->X_add_symbol
= 0;
1972 tok
->X_add_number
= reg
;
1977 /* Split up the arguments for an opcode or pseudo-op. */
1980 tokenize_arguments (char **args
, char *str
)
1982 char *old_input_line_pointer
;
1983 bfd_boolean saw_comma
= FALSE
;
1984 bfd_boolean saw_arg
= FALSE
;
1985 bfd_boolean saw_colon
= FALSE
;
1987 char *arg_end
, *arg
;
1990 /* Save and restore input_line_pointer around this function. */
1991 old_input_line_pointer
= input_line_pointer
;
1992 input_line_pointer
= str
;
1994 while (*input_line_pointer
)
1997 switch (*input_line_pointer
)
2004 input_line_pointer
++;
2005 if (saw_comma
|| saw_colon
|| !saw_arg
)
2011 input_line_pointer
++;
2012 if (saw_comma
|| saw_colon
|| !saw_arg
)
2018 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2021 arg_end
= input_line_pointer
+ 1;
2022 while (!expression_end (arg_end
))
2025 arg_len
= arg_end
- input_line_pointer
;
2026 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2027 args
[num_args
] = arg
;
2031 strncpy (arg
, input_line_pointer
, arg_len
);
2032 arg
[arg_len
] = '\0';
2034 input_line_pointer
= arg_end
;
2044 if (saw_comma
|| saw_colon
)
2046 input_line_pointer
= old_input_line_pointer
;
2051 as_bad (_("extra comma"));
2053 as_bad (_("extra colon"));
2055 as_bad (_("missing argument"));
2057 as_bad (_("missing comma or colon"));
2058 input_line_pointer
= old_input_line_pointer
;
2063 /* Parse the arguments to an opcode. Return TRUE on error. */
2066 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2068 expressionS
*tok
, *last_tok
;
2069 xtensa_opcode opcode
= insn
->opcode
;
2070 bfd_boolean had_error
= TRUE
;
2071 xtensa_isa isa
= xtensa_default_isa
;
2072 int n
, num_regs
= 0;
2073 int opcode_operand_count
;
2074 int opnd_cnt
, last_opnd_cnt
;
2075 unsigned int next_reg
= 0;
2076 char *old_input_line_pointer
;
2078 if (insn
->insn_type
== ITYPE_LITERAL
)
2079 opcode_operand_count
= 1;
2081 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2084 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2086 /* Save and restore input_line_pointer around this function. */
2087 old_input_line_pointer
= input_line_pointer
;
2093 /* Skip invisible operands. */
2094 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2100 for (n
= 0; n
< num_args
; n
++)
2102 input_line_pointer
= arg_strings
[n
];
2103 if (*input_line_pointer
== ':')
2105 xtensa_regfile opnd_rf
;
2106 input_line_pointer
++;
2109 gas_assert (opnd_cnt
> 0);
2111 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2113 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2114 as_warn (_("incorrect register number, ignoring"));
2119 if (opnd_cnt
>= opcode_operand_count
)
2121 as_warn (_("too many arguments"));
2124 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2126 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2127 next_reg
= tok
->X_add_number
+ 1;
2129 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2131 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2133 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2134 /* minus 1 because we are seeing one right now */
2140 last_opnd_cnt
= opnd_cnt
;
2141 demand_empty_rest_of_line ();
2148 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2152 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2155 insn
->ntok
= tok
- insn
->tok
;
2159 input_line_pointer
= old_input_line_pointer
;
2165 get_invisible_operands (TInsn
*insn
)
2167 xtensa_isa isa
= xtensa_default_isa
;
2168 static xtensa_insnbuf slotbuf
= NULL
;
2170 xtensa_opcode opc
= insn
->opcode
;
2171 int slot
, opnd
, fmt_found
;
2175 slotbuf
= xtensa_insnbuf_alloc (isa
);
2177 /* Find format/slot where this can be encoded. */
2180 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2182 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2184 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2190 if (fmt_found
) break;
2195 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2199 /* First encode all the visible operands
2200 (to deal with shared field operands). */
2201 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2203 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2204 && (insn
->tok
[opnd
].X_op
== O_register
2205 || insn
->tok
[opnd
].X_op
== O_constant
))
2207 val
= insn
->tok
[opnd
].X_add_number
;
2208 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2209 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2213 /* Then pull out the values for the invisible ones. */
2214 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2216 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2218 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2219 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2220 insn
->tok
[opnd
].X_add_number
= val
;
2221 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2222 insn
->tok
[opnd
].X_op
= O_register
;
2224 insn
->tok
[opnd
].X_op
= O_constant
;
2233 xg_reverse_shift_count (char **cnt_argp
)
2235 char *cnt_arg
, *new_arg
;
2236 cnt_arg
= *cnt_argp
;
2238 /* replace the argument with "31-(argument)" */
2239 new_arg
= concat ("31-(", cnt_argp
, ")", (char *) NULL
);
2242 *cnt_argp
= new_arg
;
2246 /* If "arg" is a constant expression, return non-zero with the value
2250 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2253 char *save_ptr
= input_line_pointer
;
2255 input_line_pointer
= arg
;
2257 input_line_pointer
= save_ptr
;
2259 if (exp
.X_op
== O_constant
)
2261 *valp
= exp
.X_add_number
;
2270 xg_replace_opname (char **popname
, const char *newop
)
2273 *popname
= xstrdup (newop
);
2278 xg_check_num_args (int *pnum_args
,
2283 int num_args
= *pnum_args
;
2285 if (num_args
< expected_num
)
2287 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2288 num_args
, opname
, expected_num
);
2292 if (num_args
> expected_num
)
2294 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2295 num_args
, opname
, expected_num
);
2296 while (num_args
-- > expected_num
)
2298 free (arg_strings
[num_args
]);
2299 arg_strings
[num_args
] = 0;
2301 *pnum_args
= expected_num
;
2309 /* If the register is not specified as part of the opcode,
2310 then get it from the operand and move it to the opcode. */
2313 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2315 xtensa_isa isa
= xtensa_default_isa
;
2317 char *opname
, *new_opname
;
2318 const char *sr_name
;
2319 int is_user
, is_write
;
2324 is_user
= (opname
[1] == 'u');
2325 is_write
= (opname
[0] == 'w');
2327 /* Opname == [rw]ur or [rwx]sr... */
2329 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2332 /* Check if the argument is a symbolic register name. */
2333 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2334 /* Handle WSR to "INTSET" as a special case. */
2335 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2336 && !strcasecmp (arg_strings
[1], "intset"))
2337 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2338 if (sr
== XTENSA_UNDEFINED
2339 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2341 /* Maybe it's a register number.... */
2343 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2345 as_bad (_("invalid register '%s' for '%s' instruction"),
2346 arg_strings
[1], opname
);
2349 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2350 if (sr
== XTENSA_UNDEFINED
)
2352 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2353 (long) val
, opname
);
2358 /* Remove the last argument, which is now part of the opcode. */
2359 free (arg_strings
[1]);
2363 /* Translate the opcode. */
2364 sr_name
= xtensa_sysreg_name (isa
, sr
);
2365 /* Another special case for "WSR.INTSET".... */
2366 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2368 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2370 *popname
= new_opname
;
2377 xtensa_translate_old_userreg_ops (char **popname
)
2379 xtensa_isa isa
= xtensa_default_isa
;
2381 char *opname
, *new_opname
;
2382 const char *sr_name
;
2383 bfd_boolean has_underbar
= FALSE
;
2386 if (opname
[0] == '_')
2388 has_underbar
= TRUE
;
2392 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2393 if (sr
!= XTENSA_UNDEFINED
)
2395 /* The new default name ("nnn") is different from the old default
2396 name ("URnnn"). The old default is handled below, and we don't
2397 want to recognize [RW]nnn, so do nothing if the name is the (new)
2399 static char namebuf
[10];
2400 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2401 if (strcmp (namebuf
, opname
+ 1) == 0)
2409 /* Only continue if the reg name is "URnnn". */
2410 if (opname
[1] != 'u' || opname
[2] != 'r')
2412 val
= strtoul (opname
+ 3, &end
, 10);
2416 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2417 if (sr
== XTENSA_UNDEFINED
)
2419 as_bad (_("invalid register number (%ld) for '%s'"),
2420 (long) val
, opname
);
2425 /* Translate the opcode. */
2426 sr_name
= xtensa_sysreg_name (isa
, sr
);
2427 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2428 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2429 opname
[0], sr_name
);
2431 *popname
= new_opname
;
2438 xtensa_translate_zero_immed (const char *old_op
,
2448 gas_assert (opname
[0] != '_');
2450 if (strcmp (opname
, old_op
) != 0)
2453 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2455 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2457 xg_replace_opname (popname
, new_op
);
2458 free (arg_strings
[1]);
2459 arg_strings
[1] = arg_strings
[2];
2468 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2469 Returns non-zero if an error was found. */
2472 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2474 char *opname
= *popname
;
2475 bfd_boolean has_underbar
= FALSE
;
2479 has_underbar
= TRUE
;
2483 if (strcmp (opname
, "mov") == 0)
2485 if (use_transform () && !has_underbar
&& density_supported
)
2486 xg_replace_opname (popname
, "mov.n");
2489 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2491 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2492 arg_strings
[2] = xstrdup (arg_strings
[1]);
2498 if (strcmp (opname
, "bbsi.l") == 0)
2500 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2502 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2503 if (target_big_endian
)
2504 xg_reverse_shift_count (&arg_strings
[1]);
2508 if (strcmp (opname
, "bbci.l") == 0)
2510 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2512 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2513 if (target_big_endian
)
2514 xg_reverse_shift_count (&arg_strings
[1]);
2518 /* Don't do anything special with NOPs inside FLIX instructions. They
2519 are handled elsewhere. Real NOP instructions are always available
2520 in configurations with FLIX, so this should never be an issue but
2521 check for it anyway. */
2522 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2523 && strcmp (opname
, "nop") == 0)
2525 if (use_transform () && !has_underbar
&& density_supported
)
2526 xg_replace_opname (popname
, "nop.n");
2529 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2531 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2532 arg_strings
[0] = xstrdup ("a1");
2533 arg_strings
[1] = xstrdup ("a1");
2534 arg_strings
[2] = xstrdup ("a1");
2540 /* Recognize [RW]UR and [RWX]SR. */
2541 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2542 && (opname
[1] == 'u' || opname
[1] == 's'))
2543 || (opname
[0] == 'x' && opname
[1] == 's'))
2545 && opname
[3] == '\0')
2546 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2548 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2549 [RW]<name> if <name> is the non-default name of a user register. */
2550 if ((opname
[0] == 'r' || opname
[0] == 'w')
2551 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2552 return xtensa_translate_old_userreg_ops (popname
);
2554 /* Relax branches that don't allow comparisons against an immediate value
2555 of zero to the corresponding branches with implicit zero immediates. */
2556 if (!has_underbar
&& use_transform ())
2558 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2559 pnum_args
, arg_strings
))
2562 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2563 pnum_args
, arg_strings
))
2566 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2567 pnum_args
, arg_strings
))
2570 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2571 pnum_args
, arg_strings
))
2579 /* Functions for dealing with the Xtensa ISA. */
2581 /* Currently the assembler only allows us to use a single target per
2582 fragment. Because of this, only one operand for a given
2583 instruction may be symbolic. If there is a PC-relative operand,
2584 the last one is chosen. Otherwise, the result is the number of the
2585 last immediate operand, and if there are none of those, we fail and
2589 get_relaxable_immed (xtensa_opcode opcode
)
2591 int last_immed
= -1;
2594 if (opcode
== XTENSA_UNDEFINED
)
2597 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2598 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2600 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2602 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2604 if (last_immed
== -1
2605 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2612 static xtensa_opcode
2613 get_opcode_from_buf (const char *buf
, int slot
)
2615 static xtensa_insnbuf insnbuf
= NULL
;
2616 static xtensa_insnbuf slotbuf
= NULL
;
2617 xtensa_isa isa
= xtensa_default_isa
;
2622 insnbuf
= xtensa_insnbuf_alloc (isa
);
2623 slotbuf
= xtensa_insnbuf_alloc (isa
);
2626 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2627 fmt
= xtensa_format_decode (isa
, insnbuf
);
2628 if (fmt
== XTENSA_UNDEFINED
)
2629 return XTENSA_UNDEFINED
;
2631 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2632 return XTENSA_UNDEFINED
;
2634 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2635 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2639 #ifdef TENSILICA_DEBUG
2641 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2644 xtensa_print_insn_table (void)
2646 int num_opcodes
, num_operands
;
2647 xtensa_opcode opcode
;
2648 xtensa_isa isa
= xtensa_default_isa
;
2650 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2651 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2654 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2655 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2656 for (opn
= 0; opn
< num_operands
; opn
++)
2658 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2660 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2662 xtensa_regfile opnd_rf
=
2663 xtensa_operand_regfile (isa
, opcode
, opn
);
2664 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2666 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2667 fputs ("[lLr] ", stderr
);
2669 fputs ("i ", stderr
);
2671 fprintf (stderr
, "\n");
2677 print_vliw_insn (xtensa_insnbuf vbuf
)
2679 xtensa_isa isa
= xtensa_default_isa
;
2680 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2681 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2684 fprintf (stderr
, "format = %d\n", f
);
2686 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2688 xtensa_opcode opcode
;
2692 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2693 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2694 opname
= xtensa_opcode_name (isa
, opcode
);
2696 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2697 fprintf (stderr
, " operands = ");
2699 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2703 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2705 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2706 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2707 fprintf (stderr
, "%d ", val
);
2709 fprintf (stderr
, "\n");
2711 xtensa_insnbuf_free (isa
, sbuf
);
2714 #endif /* TENSILICA_DEBUG */
2718 is_direct_call_opcode (xtensa_opcode opcode
)
2720 xtensa_isa isa
= xtensa_default_isa
;
2721 int n
, num_operands
;
2723 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2726 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2727 for (n
= 0; n
< num_operands
; n
++)
2729 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2730 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2737 /* Convert from BFD relocation type code to slot and operand number.
2738 Returns non-zero on failure. */
2741 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2743 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2744 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2746 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2749 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2750 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2752 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2762 /* Convert from slot number to BFD relocation type code for the
2763 standard PC-relative relocations. Return BFD_RELOC_NONE on
2766 static bfd_reloc_code_real_type
2767 encode_reloc (int slot
)
2769 if (slot
< 0 || slot
> 14)
2770 return BFD_RELOC_NONE
;
2772 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2776 /* Convert from slot numbers to BFD relocation type code for the
2777 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2779 static bfd_reloc_code_real_type
2780 encode_alt_reloc (int slot
)
2782 if (slot
< 0 || slot
> 14)
2783 return BFD_RELOC_NONE
;
2785 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2790 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2793 xtensa_opcode opcode
,
2799 uint32 valbuf
= value
;
2801 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2803 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2805 as_bad_where ((char *) file
, line
,
2806 _("operand %d of '%s' has out of range value '%u'"),
2808 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2811 as_bad_where ((char *) file
, line
,
2812 _("operand %d of '%s' has invalid value '%u'"),
2814 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2819 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2825 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2828 xtensa_opcode opcode
,
2832 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2833 fmt
, slot
, slotbuf
, &val
);
2834 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2839 /* Checks for rules from xtensa-relax tables. */
2841 /* The routine xg_instruction_matches_option_term must return TRUE
2842 when a given option term is true. The meaning of all of the option
2843 terms is given interpretation by this function. */
2846 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2848 if (strcmp (option
->option_name
, "realnop") == 0
2849 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2851 /* These conditions were evaluated statically when building the
2852 relaxation table. There's no need to reevaluate them now. */
2855 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2856 return insn
->extra_arg
.X_op
== O_register
;
2859 as_fatal (_("internal error: unknown option name '%s'"),
2860 option
->option_name
);
2866 xg_instruction_matches_or_options (TInsn
*insn
,
2867 const ReqOrOptionList
*or_option
)
2869 const ReqOrOption
*option
;
2870 /* Must match each of the AND terms. */
2871 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2873 if (xg_instruction_matches_option_term (insn
, option
))
2881 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2883 const ReqOption
*req_options
;
2884 /* Must match each of the AND terms. */
2885 for (req_options
= options
;
2886 req_options
!= NULL
;
2887 req_options
= req_options
->next
)
2889 /* Must match one of the OR clauses. */
2890 if (!xg_instruction_matches_or_options (insn
,
2891 req_options
->or_option_terms
))
2898 /* Return the transition rule that matches or NULL if none matches. */
2901 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2903 PreconditionList
*condition_l
;
2905 if (rule
->opcode
!= insn
->opcode
)
2908 for (condition_l
= rule
->conditions
;
2909 condition_l
!= NULL
;
2910 condition_l
= condition_l
->next
)
2914 Precondition
*cond
= condition_l
->precond
;
2919 /* The expression must be the constant. */
2920 gas_assert (cond
->op_num
< insn
->ntok
);
2921 exp1
= &insn
->tok
[cond
->op_num
];
2922 if (expr_is_const (exp1
))
2927 if (get_expr_const (exp1
) != cond
->op_data
)
2931 if (get_expr_const (exp1
) == cond
->op_data
)
2938 else if (expr_is_register (exp1
))
2943 if (get_expr_register (exp1
) != cond
->op_data
)
2947 if (get_expr_register (exp1
) == cond
->op_data
)
2959 gas_assert (cond
->op_num
< insn
->ntok
);
2960 gas_assert (cond
->op_data
< insn
->ntok
);
2961 exp1
= &insn
->tok
[cond
->op_num
];
2962 exp2
= &insn
->tok
[cond
->op_data
];
2967 if (!expr_is_equal (exp1
, exp2
))
2971 if (expr_is_equal (exp1
, exp2
))
2983 if (!xg_instruction_matches_options (insn
, rule
->options
))
2991 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2993 bfd_boolean a_greater
= FALSE
;
2994 bfd_boolean b_greater
= FALSE
;
2996 ReqOptionList
*l_a
= a
->options
;
2997 ReqOptionList
*l_b
= b
->options
;
2999 /* We only care if they both are the same except for
3000 a const16 vs. an l32r. */
3002 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3004 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
3005 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
3006 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3008 if (l_or_a
->is_true
!= l_or_b
->is_true
)
3010 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
3012 /* This is the case we care about. */
3013 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3014 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3021 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3022 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3032 l_or_a
= l_or_a
->next
;
3033 l_or_b
= l_or_b
->next
;
3035 if (l_or_a
|| l_or_b
)
3044 /* Incomparable if the substitution was used differently in two cases. */
3045 if (a_greater
&& b_greater
)
3057 static TransitionRule
*
3058 xg_instruction_match (TInsn
*insn
)
3060 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3062 gas_assert (insn
->opcode
< table
->num_opcodes
);
3064 /* Walk through all of the possible transitions. */
3065 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3067 TransitionRule
*rule
= l
->rule
;
3068 if (xg_instruction_matches_rule (insn
, rule
))
3075 /* Various Other Internal Functions. */
3078 is_unique_insn_expansion (TransitionRule
*r
)
3080 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3082 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3088 /* Check if there is exactly one relaxation for INSN that converts it to
3089 another instruction of equal or larger size. If so, and if TARG is
3090 non-null, go ahead and generate the relaxed instruction into TARG. If
3091 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3092 instruction, i.e., ignore relaxations that convert to an instruction of
3093 equal size. In some contexts where this function is used, only
3094 a single widening is allowed and the NARROW_ONLY argument is used to
3095 exclude cases like ADDI being "widened" to an ADDMI, which may
3096 later be relaxed to an ADDMI/ADDI pair. */
3099 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3101 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3103 TransitionRule
*match
= 0;
3105 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3106 gas_assert (insn
->opcode
< table
->num_opcodes
);
3108 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3110 TransitionRule
*rule
= l
->rule
;
3112 if (xg_instruction_matches_rule (insn
, rule
)
3113 && is_unique_insn_expansion (rule
)
3114 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3115 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3126 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3131 /* Return the maximum number of bytes this opcode can expand to. */
3134 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3136 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3138 int max_size
= xg_get_single_size (opcode
);
3140 gas_assert (opcode
< table
->num_opcodes
);
3142 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3144 TransitionRule
*rule
= l
->rule
;
3145 BuildInstr
*build_list
;
3150 build_list
= rule
->to_instr
;
3151 if (is_unique_insn_expansion (rule
))
3153 gas_assert (build_list
->typ
== INSTR_INSTR
);
3154 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3157 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3159 switch (build_list
->typ
)
3162 this_size
+= xg_get_single_size (build_list
->opcode
);
3164 case INSTR_LITERAL_DEF
:
3165 case INSTR_LABEL_DEF
:
3170 if (this_size
> max_size
)
3171 max_size
= this_size
;
3177 /* Return the maximum number of literal bytes this opcode can generate. */
3180 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3182 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3186 gas_assert (opcode
< table
->num_opcodes
);
3188 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3190 TransitionRule
*rule
= l
->rule
;
3191 BuildInstr
*build_list
;
3196 build_list
= rule
->to_instr
;
3197 if (is_unique_insn_expansion (rule
))
3199 gas_assert (build_list
->typ
== INSTR_INSTR
);
3200 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3203 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3205 switch (build_list
->typ
)
3207 case INSTR_LITERAL_DEF
:
3208 /* Hard-coded 4-byte literal. */
3212 case INSTR_LABEL_DEF
:
3217 if (this_size
> max_size
)
3218 max_size
= this_size
;
3225 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3227 int steps_taken
= 0;
3228 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3231 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3232 gas_assert (insn
->opcode
< table
->num_opcodes
);
3234 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3236 TransitionRule
*rule
= l
->rule
;
3238 if (xg_instruction_matches_rule (insn
, rule
))
3240 if (steps_taken
== lateral_steps
)
3250 get_special_literal_symbol (void)
3252 static symbolS
*sym
= NULL
;
3255 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3261 get_special_label_symbol (void)
3263 static symbolS
*sym
= NULL
;
3266 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3272 xg_valid_literal_expression (const expressionS
*exp
)
3294 /* This will check to see if the value can be converted into the
3295 operand type. It will return TRUE if it does not fit. */
3298 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3300 uint32 valbuf
= value
;
3301 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3307 /* Assumes: All immeds are constants. Check that all constants fit
3308 into their immeds; return FALSE if not. */
3311 xg_immeds_fit (const TInsn
*insn
)
3313 xtensa_isa isa
= xtensa_default_isa
;
3317 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3318 for (i
= 0; i
< n
; ++i
)
3320 const expressionS
*exp
= &insn
->tok
[i
];
3322 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3329 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3334 /* The symbol should have a fixup associated with it. */
3343 /* This should only be called after we have an initial
3344 estimate of the addresses. */
3347 xg_symbolic_immeds_fit (const TInsn
*insn
,
3353 xtensa_isa isa
= xtensa_default_isa
;
3361 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3363 for (i
= 0; i
< n
; ++i
)
3365 const expressionS
*exp
= &insn
->tok
[i
];
3367 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3374 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3380 /* Check for the worst case. */
3381 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3386 /* We only allow symbols for PC-relative references.
3387 If pc_frag == 0, then we don't have frag locations yet. */
3389 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3392 /* If it is a weak symbol or a symbol in a different section,
3393 it cannot be known to fit at assembly time. */
3394 if (S_IS_WEAK (exp
->X_add_symbol
)
3395 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3397 /* For a direct call with --no-longcalls, be optimistic and
3398 assume it will be in range. If the symbol is weak and
3399 undefined, it may remain undefined at link-time, in which
3400 case it will have a zero value and almost certainly be out
3401 of range for a direct call; thus, relax for undefined weak
3402 symbols even if longcalls is not enabled. */
3403 if (is_direct_call_opcode (insn
->opcode
)
3404 && ! pc_frag
->tc_frag_data
.use_longcalls
3405 && (! S_IS_WEAK (exp
->X_add_symbol
)
3406 || S_IS_DEFINED (exp
->X_add_symbol
)))
3412 symbolP
= exp
->X_add_symbol
;
3413 sym_frag
= symbol_get_frag (symbolP
);
3414 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3415 pc
= pc_frag
->fr_address
+ pc_offset
;
3417 /* If frag has yet to be reached on this pass, assume it
3418 will move by STRETCH just as we did. If this is not so,
3419 it will be because some frag between grows, and that will
3420 force another pass. Beware zero-length frags. There
3421 should be a faster way to do this. */
3424 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3425 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3430 new_offset
= target
;
3431 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3432 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3437 /* The symbol should have a fixup associated with it. */
3446 /* Return TRUE on success. */
3449 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3455 targ
->debug_line
= insn
->debug_line
;
3456 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3461 targ
->opcode
= bi
->opcode
;
3462 targ
->insn_type
= ITYPE_INSN
;
3463 targ
->is_specific_opcode
= FALSE
;
3465 for (; op
!= NULL
; op
= op
->next
)
3467 int op_num
= op
->op_num
;
3468 int op_data
= op
->op_data
;
3470 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3472 if (targ
->ntok
<= op_num
)
3473 targ
->ntok
= op_num
+ 1;
3478 set_expr_const (&targ
->tok
[op_num
], op_data
);
3481 gas_assert (op_data
< insn
->ntok
);
3482 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3485 if (insn
->extra_arg
.X_op
!= O_register
)
3487 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3490 sym
= get_special_literal_symbol ();
3491 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3492 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3493 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3494 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3497 sym
= get_special_label_symbol ();
3498 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3500 case OP_OPERAND_HI16U
:
3501 case OP_OPERAND_LOW16U
:
3502 gas_assert (op_data
< insn
->ntok
);
3503 if (expr_is_const (&insn
->tok
[op_data
]))
3506 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3507 val
= xg_apply_userdef_op_fn (op
->typ
,
3510 targ
->tok
[op_num
].X_add_number
= val
;
3514 /* For const16 we can create relocations for these. */
3515 if (targ
->opcode
== XTENSA_UNDEFINED
3516 || (targ
->opcode
!= xtensa_const16_opcode
))
3518 gas_assert (op_data
< insn
->ntok
);
3519 /* Need to build a O_lo16 or O_hi16. */
3520 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3521 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3523 if (op
->typ
== OP_OPERAND_HI16U
)
3524 targ
->tok
[op_num
].X_op
= O_hi16
;
3525 else if (op
->typ
== OP_OPERAND_LOW16U
)
3526 targ
->tok
[op_num
].X_op
= O_lo16
;
3533 /* currently handles:
3536 OP_OPERAND_F32MINUS */
3537 if (xg_has_userdef_op_fn (op
->typ
))
3539 gas_assert (op_data
< insn
->ntok
);
3540 if (expr_is_const (&insn
->tok
[op_data
]))
3543 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3544 val
= xg_apply_userdef_op_fn (op
->typ
,
3547 targ
->tok
[op_num
].X_add_number
= val
;
3550 return FALSE
; /* We cannot use a relocation for this. */
3559 case INSTR_LITERAL_DEF
:
3561 targ
->opcode
= XTENSA_UNDEFINED
;
3562 targ
->insn_type
= ITYPE_LITERAL
;
3563 targ
->is_specific_opcode
= FALSE
;
3564 for (; op
!= NULL
; op
= op
->next
)
3566 int op_num
= op
->op_num
;
3567 int op_data
= op
->op_data
;
3568 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3570 if (targ
->ntok
<= op_num
)
3571 targ
->ntok
= op_num
+ 1;
3576 gas_assert (op_data
< insn
->ntok
);
3577 /* We can only pass resolvable literals through. */
3578 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3580 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3592 case INSTR_LABEL_DEF
:
3594 targ
->opcode
= XTENSA_UNDEFINED
;
3595 targ
->insn_type
= ITYPE_LABEL
;
3596 targ
->is_specific_opcode
= FALSE
;
3597 /* Literal with no ops is a label? */
3598 gas_assert (op
== NULL
);
3609 /* Return TRUE on success. */
3612 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3614 for (; bi
!= NULL
; bi
= bi
->next
)
3616 TInsn
*next_insn
= istack_push_space (istack
);
3618 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3625 /* Return TRUE on valid expansion. */
3628 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3630 int stack_size
= istack
->ninsn
;
3631 int steps_taken
= 0;
3632 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3635 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3636 gas_assert (insn
->opcode
< table
->num_opcodes
);
3638 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3640 TransitionRule
*rule
= l
->rule
;
3642 if (xg_instruction_matches_rule (insn
, rule
))
3644 if (lateral_steps
== steps_taken
)
3648 /* This is it. Expand the rule to the stack. */
3649 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3652 /* Check to see if it fits. */
3653 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3655 TInsn
*tinsn
= &istack
->insn
[i
];
3657 if (tinsn
->insn_type
== ITYPE_INSN
3658 && !tinsn_has_symbolic_operands (tinsn
)
3659 && !xg_immeds_fit (tinsn
))
3661 istack
->ninsn
= stack_size
;
3674 /* Relax the assembly instruction at least "min_steps".
3675 Return the number of steps taken.
3677 For relaxation to correctly terminate, every relaxation chain must
3678 terminate in one of two ways:
3680 1. If the chain from one instruction to the next consists entirely of
3681 single instructions, then the chain *must* handle all possible
3682 immediates without failing. It must not ever fail because an
3683 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3684 chain is one example. L32R loads 32 bits, and there cannot be an
3685 immediate larger than 32 bits, so it satisfies this condition.
3686 Single instruction relaxation chains are as defined by
3687 xg_is_single_relaxable_instruction.
3689 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3690 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3692 Strictly speaking, in most cases you can violate condition 1 and be OK
3693 -- in particular when the last two instructions have the same single
3694 size. But nevertheless, you should guarantee the above two conditions.
3696 We could fix this so that single-instruction expansions correctly
3697 terminate when they can't handle the range, but the error messages are
3698 worse, and it actually turns out that in every case but one (18-bit wide
3699 branches), you need a multi-instruction expansion to get the full range
3700 anyway. And because 18-bit branches are handled identically to 15-bit
3701 branches, there isn't any point in changing it. */
3704 xg_assembly_relax (IStack
*istack
,
3707 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3708 offsetT pc_offset
, /* offset in fragment */
3709 int min_steps
, /* minimum conversion steps */
3710 long stretch
) /* number of bytes stretched so far */
3712 int steps_taken
= 0;
3714 /* Some of its immeds don't fit. Try to build a relaxed version.
3715 This may go through a couple of stages of single instruction
3716 transformations before we get there. */
3718 TInsn single_target
;
3720 int lateral_steps
= 0;
3721 int istack_size
= istack
->ninsn
;
3723 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3724 && steps_taken
>= min_steps
)
3726 istack_push (istack
, insn
);
3729 current_insn
= *insn
;
3731 /* Walk through all of the single instruction expansions. */
3732 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3735 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3738 if (steps_taken
>= min_steps
)
3740 istack_push (istack
, &single_target
);
3744 current_insn
= single_target
;
3747 /* Now check for a multi-instruction expansion. */
3748 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3750 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3753 if (steps_taken
>= min_steps
)
3755 istack_push (istack
, ¤t_insn
);
3760 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3762 if (steps_taken
>= min_steps
)
3766 istack
->ninsn
= istack_size
;
3769 /* It's not going to work -- use the original. */
3770 istack_push (istack
, insn
);
3776 xg_finish_frag (char *last_insn
,
3777 enum xtensa_relax_statesE frag_state
,
3778 enum xtensa_relax_statesE slot0_state
,
3780 bfd_boolean is_insn
)
3782 /* Finish off this fragment so that it has at LEAST the desired
3783 max_growth. If it doesn't fit in this fragment, close this one
3784 and start a new one. In either case, return a pointer to the
3785 beginning of the growth area. */
3789 frag_grow (max_growth
);
3790 old_frag
= frag_now
;
3792 frag_now
->fr_opcode
= last_insn
;
3794 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3796 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3797 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3799 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3800 xtensa_set_frag_assembly_state (frag_now
);
3802 /* Just to make sure that we did not split it up. */
3803 gas_assert (old_frag
->fr_next
== frag_now
);
3807 /* Return TRUE if the target frag is one of the next non-empty frags. */
3810 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3815 for (; fragP
; fragP
= fragP
->fr_next
)
3817 if (fragP
== target
)
3819 if (fragP
->fr_fix
!= 0)
3821 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3823 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3824 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3826 if (fragP
->fr_type
== rs_space
)
3834 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3836 xtensa_isa isa
= xtensa_default_isa
;
3838 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3843 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3844 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3847 for (i
= 0; i
< num_ops
; i
++)
3849 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3855 if (target_op
== -1)
3858 if (insn
->ntok
<= target_op
)
3861 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3864 sym
= insn
->tok
[target_op
].X_add_symbol
;
3868 if (insn
->tok
[target_op
].X_add_number
!= 0)
3871 target_frag
= symbol_get_frag (sym
);
3872 if (target_frag
== NULL
)
3875 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3876 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3884 xg_add_branch_and_loop_targets (TInsn
*insn
)
3886 xtensa_isa isa
= xtensa_default_isa
;
3887 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3889 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3892 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3893 && insn
->tok
[i
].X_op
== O_symbol
)
3894 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3898 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3899 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3903 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3905 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3906 && insn
->tok
[i
].X_op
== O_symbol
)
3908 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3909 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3910 if (S_IS_DEFINED (sym
))
3911 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3918 /* Return FALSE if no error. */
3921 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3926 switch (instr_spec
->typ
)
3929 new_insn
->insn_type
= ITYPE_INSN
;
3930 new_insn
->opcode
= instr_spec
->opcode
;
3932 case INSTR_LITERAL_DEF
:
3933 new_insn
->insn_type
= ITYPE_LITERAL
;
3934 new_insn
->opcode
= XTENSA_UNDEFINED
;
3936 case INSTR_LABEL_DEF
:
3939 new_insn
->is_specific_opcode
= FALSE
;
3940 new_insn
->debug_line
= old_insn
->debug_line
;
3941 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3943 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3946 const expressionS
*src_exp
;
3952 /* The expression must be the constant. */
3953 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3954 exp
= &new_insn
->tok
[b_op
->op_num
];
3955 set_expr_const (exp
, b_op
->op_data
);
3959 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3960 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3961 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3962 exp
= &new_insn
->tok
[b_op
->op_num
];
3963 copy_expr (exp
, src_exp
);
3968 as_bad (_("can't handle generation of literal/labels yet"));
3972 as_bad (_("can't handle undefined OP TYPE"));
3977 new_insn
->ntok
= num_ops
;
3982 /* Return TRUE if it was simplified. */
3985 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3987 TransitionRule
*rule
;
3988 BuildInstr
*insn_spec
;
3990 if (old_insn
->is_specific_opcode
|| !density_supported
)
3993 rule
= xg_instruction_match (old_insn
);
3997 insn_spec
= rule
->to_instr
;
3998 /* There should only be one. */
3999 gas_assert (insn_spec
!= NULL
);
4000 gas_assert (insn_spec
->next
== NULL
);
4001 if (insn_spec
->next
!= NULL
)
4004 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
4010 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4011 l32i.n. (2) Check the number of operands. (3) Place the instruction
4012 tokens into the stack or relax it and place multiple
4013 instructions/literals onto the stack. Return FALSE if no error. */
4016 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4020 bfd_boolean do_expand
;
4022 tinsn_init (&new_insn
);
4024 /* Narrow it if we can. xg_simplify_insn now does all the
4025 appropriate checking (e.g., for the density option). */
4026 if (xg_simplify_insn (orig_insn
, &new_insn
))
4027 orig_insn
= &new_insn
;
4029 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4031 if (orig_insn
->ntok
< noperands
)
4033 as_bad (_("found %d operands for '%s': Expected %d"),
4035 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4039 if (orig_insn
->ntok
> noperands
)
4040 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
4042 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4045 /* If there are not enough operands, we will assert above. If there
4046 are too many, just cut out the extras here. */
4047 orig_insn
->ntok
= noperands
;
4049 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4052 /* Special case for extui opcode which has constraints not handled
4053 by the ordinary operand encoding checks. The number of operands
4054 and related syntax issues have already been checked. */
4055 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4057 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4058 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4059 if (shiftimm
+ maskimm
> 32)
4061 as_bad (_("immediate operands sum to greater than 32"));
4066 /* If the instruction will definitely need to be relaxed, it is better
4067 to expand it now for better scheduling. Decide whether to expand
4069 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4071 /* Calls should be expanded to longcalls only in the backend relaxation
4072 so that the assembly scheduler will keep the L32R/CALLX instructions
4074 if (is_direct_call_opcode (orig_insn
->opcode
))
4077 if (tinsn_has_symbolic_operands (orig_insn
))
4079 /* The values of symbolic operands are not known yet, so only expand
4080 now if an operand is "complex" (e.g., difference of symbols) and
4081 will have to be stored as a literal regardless of the value. */
4082 if (!tinsn_has_complex_operands (orig_insn
))
4085 else if (xg_immeds_fit (orig_insn
))
4089 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4091 istack_push (istack
, orig_insn
);
4097 /* Return TRUE if the section flags are marked linkonce
4098 or the name is .gnu.linkonce.*. */
4100 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4103 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4105 flagword flags
, link_once_flags
;
4107 flags
= bfd_get_section_flags (abfd
, sec
);
4108 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4110 /* Flags might not be set yet. */
4111 if (!link_once_flags
4112 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4113 link_once_flags
= SEC_LINK_ONCE
;
4115 return (link_once_flags
!= 0);
4120 xtensa_add_literal_sym (symbolS
*sym
)
4124 l
= XNEW (sym_list
);
4126 l
->next
= literal_syms
;
4132 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4134 static int lit_num
= 0;
4135 static char name
[256];
4138 sprintf (name
, ".L_lit_sym%d", lit_num
);
4140 /* Create a local symbol. If it is in a linkonce section, we have to
4141 be careful to make sure that if it is used in a relocation that the
4142 symbol will be in the output file. */
4143 if (get_is_linkonce_section (stdoutput
, sec
))
4145 symbolP
= symbol_new (name
, sec
, 0, frag
);
4146 S_CLEAR_EXTERNAL (symbolP
);
4147 /* symbolP->local = 1; */
4150 symbolP
= symbol_new (name
, sec
, 0, frag
);
4152 xtensa_add_literal_sym (symbolP
);
4159 /* Currently all literals that are generated here are 32-bit L32R targets. */
4162 xg_assemble_literal (/* const */ TInsn
*insn
)
4165 symbolS
*lit_sym
= NULL
;
4166 bfd_reloc_code_real_type reloc
;
4167 bfd_boolean pcrel
= FALSE
;
4170 /* size = 4 for L32R. It could easily be larger when we move to
4171 larger constants. Add a parameter later. */
4172 offsetT litsize
= 4;
4173 offsetT litalign
= 2; /* 2^2 = 4 */
4174 expressionS saved_loc
;
4175 expressionS
* emit_val
;
4177 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4179 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4180 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4182 xtensa_switch_to_literal_fragment (&state
);
4184 emit_val
= &insn
->tok
[0];
4185 if (emit_val
->X_op
== O_big
)
4187 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4190 /* This happens when someone writes a "movi a2, big_number". */
4191 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4192 _("invalid immediate"));
4193 xtensa_restore_emit_state (&state
);
4198 /* Force a 4-byte align here. Note that this opens a new frag, so all
4199 literals done with this function have a frag to themselves. That's
4200 important for the way text section literals work. */
4201 frag_align (litalign
, 0, 0);
4202 record_alignment (now_seg
, litalign
);
4204 switch (emit_val
->X_op
)
4214 p
= frag_more (litsize
);
4215 xtensa_set_frag_assembly_state (frag_now
);
4216 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4217 if (emit_val
->X_add_symbol
)
4218 emit_val
->X_op
= O_symbol
;
4220 emit_val
->X_op
= O_constant
;
4221 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4222 litsize
, emit_val
, pcrel
, reloc
);
4226 emit_expr (emit_val
, litsize
);
4230 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4231 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4232 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4233 lit_sym
= frag_now
->fr_symbol
;
4236 xtensa_restore_emit_state (&state
);
4242 xg_assemble_literal_space (/* const */ int size
, int slot
)
4245 /* We might have to do something about this alignment. It only
4246 takes effect if something is placed here. */
4247 offsetT litalign
= 2; /* 2^2 = 4 */
4248 fragS
*lit_saved_frag
;
4250 gas_assert (size
% 4 == 0);
4252 xtensa_switch_to_literal_fragment (&state
);
4254 /* Force a 4-byte align here. */
4255 frag_align (litalign
, 0, 0);
4256 record_alignment (now_seg
, litalign
);
4260 lit_saved_frag
= frag_now
;
4261 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4262 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4263 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4266 xtensa_restore_emit_state (&state
);
4267 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4271 /* Put in a fixup record based on the opcode.
4272 Return TRUE on success. */
4275 xg_add_opcode_fix (TInsn
*tinsn
,
4283 xtensa_opcode opcode
= tinsn
->opcode
;
4284 bfd_reloc_code_real_type reloc
;
4285 reloc_howto_type
*howto
;
4289 reloc
= BFD_RELOC_NONE
;
4291 /* First try the special cases for "alternate" relocs. */
4292 if (opcode
== xtensa_l32r_opcode
)
4294 if (fragP
->tc_frag_data
.use_absolute_literals
)
4295 reloc
= encode_alt_reloc (slot
);
4297 else if (opcode
== xtensa_const16_opcode
)
4299 if (exp
->X_op
== O_lo16
)
4301 reloc
= encode_reloc (slot
);
4302 exp
->X_op
= O_symbol
;
4304 else if (exp
->X_op
== O_hi16
)
4306 reloc
= encode_alt_reloc (slot
);
4307 exp
->X_op
= O_symbol
;
4311 if (opnum
!= get_relaxable_immed (opcode
))
4313 as_bad (_("invalid relocation for operand %i of '%s'"),
4314 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4318 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4319 into the symbol table where the generic portions of the assembler
4320 won't know what to do with them. */
4321 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4323 as_bad (_("invalid expression for operand %i of '%s'"),
4324 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4328 /* Next try the generic relocs. */
4329 if (reloc
== BFD_RELOC_NONE
)
4330 reloc
= encode_reloc (slot
);
4331 if (reloc
== BFD_RELOC_NONE
)
4333 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4337 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4340 as_bad (_("undefined symbol for opcode \"%s\""),
4341 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4345 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4346 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4347 howto
->pc_relative
, reloc
);
4348 the_fix
->fx_no_overflow
= 1;
4349 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4350 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4351 the_fix
->tc_fix_data
.slot
= slot
;
4358 xg_emit_insn_to_buf (TInsn
*tinsn
,
4362 bfd_boolean build_fix
)
4364 static xtensa_insnbuf insnbuf
= NULL
;
4365 bfd_boolean has_symbolic_immed
= FALSE
;
4366 bfd_boolean ok
= TRUE
;
4369 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4371 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4372 if (has_symbolic_immed
&& build_fix
)
4375 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4376 int slot
= xg_get_single_slot (tinsn
->opcode
);
4377 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4378 expressionS
*exp
= &tinsn
->tok
[opnum
];
4380 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4383 fragP
->tc_frag_data
.is_insn
= TRUE
;
4384 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4385 (unsigned char *) buf
, 0);
4391 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4393 symbolS
*sym
= get_special_literal_symbol ();
4397 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4398 for (i
= 0; i
< insn
->ntok
; i
++)
4399 if (insn
->tok
[i
].X_add_symbol
== sym
)
4400 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4406 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4408 symbolS
*sym
= get_special_label_symbol ();
4410 for (i
= 0; i
< insn
->ntok
; i
++)
4411 if (insn
->tok
[i
].X_add_symbol
== sym
)
4412 insn
->tok
[i
].X_add_symbol
= label_sym
;
4417 /* Return TRUE if the instruction can write to the specified
4418 integer register. */
4421 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4425 xtensa_isa isa
= xtensa_default_isa
;
4427 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4429 for (i
= 0; i
< num_ops
; i
++)
4432 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4433 if ((inout
== 'o' || inout
== 'm')
4434 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4436 xtensa_regfile opnd_rf
=
4437 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4438 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4440 if ((insn
->tok
[i
].X_op
== O_register
)
4441 && (insn
->tok
[i
].X_add_number
== regnum
))
4451 is_bad_loopend_opcode (const TInsn
*tinsn
)
4453 xtensa_opcode opcode
= tinsn
->opcode
;
4455 if (opcode
== XTENSA_UNDEFINED
)
4458 if (opcode
== xtensa_call0_opcode
4459 || opcode
== xtensa_callx0_opcode
4460 || opcode
== xtensa_call4_opcode
4461 || opcode
== xtensa_callx4_opcode
4462 || opcode
== xtensa_call8_opcode
4463 || opcode
== xtensa_callx8_opcode
4464 || opcode
== xtensa_call12_opcode
4465 || opcode
== xtensa_callx12_opcode
4466 || opcode
== xtensa_isync_opcode
4467 || opcode
== xtensa_ret_opcode
4468 || opcode
== xtensa_ret_n_opcode
4469 || opcode
== xtensa_retw_opcode
4470 || opcode
== xtensa_retw_n_opcode
4471 || opcode
== xtensa_waiti_opcode
4472 || opcode
== xtensa_rsr_lcount_opcode
)
4479 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4480 This allows the debugger to add unaligned labels.
4481 Also, the assembler generates stabs labels that need
4482 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4485 is_unaligned_label (symbolS
*sym
)
4487 const char *name
= S_GET_NAME (sym
);
4488 static size_t fake_size
= 0;
4492 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4495 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4497 fake_size
= strlen (FAKE_LABEL_NAME
);
4500 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4501 && (name
[fake_size
] == 'F'
4502 || name
[fake_size
] == 'L'
4503 || (name
[fake_size
] == 'e'
4504 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4512 next_non_empty_frag (const fragS
*fragP
)
4514 fragS
*next_fragP
= fragP
->fr_next
;
4516 /* Sometimes an empty will end up here due storage allocation issues.
4517 So we have to skip until we find something legit. */
4518 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4519 next_fragP
= next_fragP
->fr_next
;
4521 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4529 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4531 xtensa_opcode out_opcode
;
4532 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4534 if (next_fragP
== NULL
)
4537 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4538 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4540 *opcode
= out_opcode
;
4548 frag_format_size (const fragS
*fragP
)
4550 static xtensa_insnbuf insnbuf
= NULL
;
4551 xtensa_isa isa
= xtensa_default_isa
;
4556 insnbuf
= xtensa_insnbuf_alloc (isa
);
4559 return XTENSA_UNDEFINED
;
4561 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4562 (unsigned char *) fragP
->fr_literal
, 0);
4564 fmt
= xtensa_format_decode (isa
, insnbuf
);
4565 if (fmt
== XTENSA_UNDEFINED
)
4566 return XTENSA_UNDEFINED
;
4567 fmt_size
= xtensa_format_length (isa
, fmt
);
4569 /* If the next format won't be changing due to relaxation, just
4570 return the length of the first format. */
4571 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4574 /* If during relaxation we have to pull an instruction out of a
4575 multi-slot instruction, we will return the more conservative
4576 number. This works because alignment on bigger instructions
4577 is more restrictive than alignment on smaller instructions.
4578 This is more conservative than we would like, but it happens
4581 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4584 /* If we aren't doing one of our own relaxations or it isn't
4585 slot-based, then the insn size won't change. */
4586 if (fragP
->fr_type
!= rs_machine_dependent
)
4588 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4591 /* If an instruction is about to grow, return the longer size. */
4592 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4593 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4594 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4596 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4597 instruction in the relaxed version is of length 3. (The case
4598 where we have to pull the instruction out of a FLIX bundle
4599 is handled conservatively above.) However, frags with opcodes
4600 that are expanding to wide branches end up having formats that
4601 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4602 we can't tell directly what format the relaxer picked. This
4603 is a wart in the design of the relaxer that should someday be
4604 fixed, but would require major changes, or at least should
4605 be accompanied by major changes to make use of that data.
4607 In any event, we can tell that we are expanding from a single-slot
4608 format to a wider one with the logic below. */
4611 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4613 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4615 if (relaxed_size
== xtensa_format_length (isa
, i
))
4616 return relaxed_size
;
4622 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4623 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4630 next_frag_format_size (const fragS
*fragP
)
4632 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4633 return frag_format_size (next_fragP
);
4637 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4638 required two-byte instructions to be treated as three-byte instructions
4639 for loop instruction alignment. This restriction was removed beginning
4640 with Xtensa LX. Now the only requirement on loop instruction alignment
4641 is that the first instruction of the loop must appear at an address that
4642 does not cross a fetch boundary. */
4645 get_loop_align_size (int insn_size
)
4647 if (insn_size
== XTENSA_UNDEFINED
)
4648 return xtensa_fetch_width
;
4650 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4657 /* If the next legit fragment is an end-of-loop marker,
4658 switch its state so it will instantiate a NOP. */
4661 update_next_frag_state (fragS
*fragP
)
4663 fragS
*next_fragP
= fragP
->fr_next
;
4664 fragS
*new_target
= NULL
;
4668 /* We are guaranteed there will be one of these... */
4669 while (!(next_fragP
->fr_type
== rs_machine_dependent
4670 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4671 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4672 next_fragP
= next_fragP
->fr_next
;
4674 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4675 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4676 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4678 /* ...and one of these. */
4679 new_target
= next_fragP
->fr_next
;
4680 while (!(new_target
->fr_type
== rs_machine_dependent
4681 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4682 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4683 new_target
= new_target
->fr_next
;
4685 gas_assert (new_target
->fr_type
== rs_machine_dependent
4686 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4687 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4690 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4692 if (next_fragP
->fr_type
== rs_machine_dependent
4693 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4695 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4699 next_fragP
= next_fragP
->fr_next
;
4705 next_frag_is_branch_target (const fragS
*fragP
)
4707 /* Sometimes an empty will end up here due to storage allocation issues,
4708 so we have to skip until we find something legit. */
4709 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4711 if (fragP
->tc_frag_data
.is_branch_target
)
4713 if (fragP
->fr_fix
!= 0)
4721 next_frag_is_loop_target (const fragS
*fragP
)
4723 /* Sometimes an empty will end up here due storage allocation issues.
4724 So we have to skip until we find something legit. */
4725 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4727 if (fragP
->tc_frag_data
.is_loop_target
)
4729 if (fragP
->fr_fix
!= 0)
4736 /* As specified in the relaxation table, when a loop instruction is
4737 relaxed, there are 24 bytes between the loop instruction itself and
4738 the first instruction in the loop. */
4740 #define RELAXED_LOOP_INSN_BYTES 24
4743 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4745 const fragS
*next_fragp
= fragp
->fr_next
;
4746 xtensa_opcode next_opcode
;
4748 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4751 /* Sometimes an empty will end up here due to storage allocation issues,
4752 so we have to skip until we find something legit. */
4753 while (next_fragp
->fr_fix
== 0)
4754 next_fragp
= next_fragp
->fr_next
;
4756 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4759 /* There is some implicit knowledge encoded in here.
4760 The LOOP instructions that are NOT RELAX_IMMED have
4761 been relaxed. Note that we can assume that the LOOP
4762 instruction is in slot 0 because loops aren't bundleable. */
4763 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4764 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4770 /* Mark a location where we can later insert literal frags. Update
4771 the section's literal_pool_loc, so subsequent literals can be
4772 placed nearest to their use. */
4775 xtensa_mark_literal_pool_location (void)
4777 /* Any labels pointing to the current location need
4778 to be adjusted to after the literal pool. */
4780 fragS
*pool_location
;
4782 if (use_literal_section
)
4785 /* We stash info in these frags so we can later move the literal's
4786 fixes into this frchain's fix list. */
4787 pool_location
= frag_now
;
4788 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4789 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4790 /* Just record this frag. */
4791 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4792 frag_variant (rs_machine_dependent
, 0, 0,
4793 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4794 xtensa_set_frag_assembly_state (frag_now
);
4795 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4796 frag_variant (rs_machine_dependent
, 0, 0,
4797 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4798 xtensa_set_frag_assembly_state (frag_now
);
4800 /* Now put a frag into the literal pool that points to this location. */
4801 set_literal_pool_location (now_seg
, pool_location
);
4802 xtensa_switch_to_non_abs_literal_fragment (&s
);
4803 frag_align (2, 0, 0);
4804 record_alignment (now_seg
, 2);
4806 /* Close whatever frag is there. */
4807 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4808 xtensa_set_frag_assembly_state (frag_now
);
4809 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4810 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4811 xtensa_restore_emit_state (&s
);
4812 xtensa_set_frag_assembly_state (frag_now
);
4816 /* Build a nop of the correct size into tinsn. */
4819 build_nop (TInsn
*tinsn
, int size
)
4825 tinsn
->opcode
= xtensa_nop_n_opcode
;
4827 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4828 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4832 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4834 tinsn
->opcode
= xtensa_or_opcode
;
4835 set_expr_const (&tinsn
->tok
[0], 1);
4836 set_expr_const (&tinsn
->tok
[1], 1);
4837 set_expr_const (&tinsn
->tok
[2], 1);
4841 tinsn
->opcode
= xtensa_nop_opcode
;
4843 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4848 /* Assemble a NOP of the requested size in the buffer. User must have
4849 allocated "buf" with at least "size" bytes. */
4852 assemble_nop (int size
, char *buf
)
4854 static xtensa_insnbuf insnbuf
= NULL
;
4857 build_nop (&tinsn
, size
);
4860 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4862 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4863 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4864 (unsigned char *) buf
, 0);
4868 /* Return the number of bytes for the offset of the expanded loop
4869 instruction. This should be incorporated into the relaxation
4870 specification but is hard-coded here. This is used to auto-align
4871 the loop instruction. It is invalid to call this function if the
4872 configuration does not have loops or if the opcode is not a loop
4876 get_expanded_loop_offset (xtensa_opcode opcode
)
4878 /* This is the OFFSET of the loop instruction in the expanded loop.
4879 This MUST correspond directly to the specification of the loop
4880 expansion. It will be validated on fragment conversion. */
4881 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4882 if (opcode
== xtensa_loop_opcode
)
4884 if (opcode
== xtensa_loopnez_opcode
)
4886 if (opcode
== xtensa_loopgtz_opcode
)
4888 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4894 get_literal_pool_location (segT seg
)
4896 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4897 struct litpool_frag
*lpf
;
4898 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4902 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4903 { /* Skip "candidates" for now. */
4904 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4908 /* Must convert a lower-priority pool. */
4909 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4911 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4914 /* Still no match -- try for a low priority pool. */
4915 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4917 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4921 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4926 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4928 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4932 /* Set frag assembly state should be called when a new frag is
4933 opened and after a frag has been closed. */
4936 xtensa_set_frag_assembly_state (fragS
*fragP
)
4938 if (!density_supported
)
4939 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4941 /* This function is called from subsegs_finish, which is called
4942 after xtensa_end, so we can't use "use_transform" or
4943 "use_schedule" here. */
4944 if (!directive_state
[directive_transform
])
4945 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4946 if (directive_state
[directive_longcalls
])
4947 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4948 fragP
->tc_frag_data
.use_absolute_literals
=
4949 directive_state
[directive_absolute_literals
];
4950 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4955 relaxable_section (asection
*sec
)
4957 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4958 && strcmp (sec
->name
, ".eh_frame") != 0);
4963 xtensa_mark_frags_for_org (void)
4967 /* Walk over each fragment of all of the current segments. If we find
4968 a .org frag in any of the segments, mark all frags prior to it as
4969 "no transform", which will prevent linker optimizations from messing
4970 up the .org distance. This should be done after
4971 xtensa_find_unmarked_state_frags, because we don't want to worry here
4972 about that function trashing the data we save here. */
4974 for (seclist
= &stdoutput
->sections
;
4975 seclist
&& *seclist
;
4976 seclist
= &(*seclist
)->next
)
4978 segT sec
= *seclist
;
4979 segment_info_type
*seginfo
;
4982 flags
= bfd_get_section_flags (stdoutput
, sec
);
4983 if (flags
& SEC_DEBUGGING
)
4985 if (!(flags
& SEC_ALLOC
))
4988 seginfo
= seg_info (sec
);
4989 if (seginfo
&& seginfo
->frchainP
)
4991 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4992 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4993 fragP
= fragP
->fr_next
)
4995 /* cvt_frag_to_fill has changed the fr_type of org frags to
4996 rs_fill, so use the value as cached in rs_subtype here. */
4997 if (fragP
->fr_subtype
== RELAX_ORG
)
4999 while (last_fragP
!= fragP
->fr_next
)
5001 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
5002 last_fragP
= last_fragP
->fr_next
;
5012 xtensa_find_unmarked_state_frags (void)
5016 /* Walk over each fragment of all of the current segments. For each
5017 unmarked fragment, mark it with the same info as the previous
5019 for (seclist
= &stdoutput
->sections
;
5020 seclist
&& *seclist
;
5021 seclist
= &(*seclist
)->next
)
5023 segT sec
= *seclist
;
5024 segment_info_type
*seginfo
;
5027 flags
= bfd_get_section_flags (stdoutput
, sec
);
5028 if (flags
& SEC_DEBUGGING
)
5030 if (!(flags
& SEC_ALLOC
))
5033 seginfo
= seg_info (sec
);
5034 if (seginfo
&& seginfo
->frchainP
)
5036 fragS
*last_fragP
= 0;
5037 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5038 fragP
= fragP
->fr_next
)
5040 if (fragP
->fr_fix
!= 0
5041 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5043 if (last_fragP
== 0)
5045 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5046 _("assembly state not set for first frag in section %s"),
5051 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5052 fragP
->tc_frag_data
.is_no_density
=
5053 last_fragP
->tc_frag_data
.is_no_density
;
5054 fragP
->tc_frag_data
.is_no_transform
=
5055 last_fragP
->tc_frag_data
.is_no_transform
;
5056 fragP
->tc_frag_data
.use_longcalls
=
5057 last_fragP
->tc_frag_data
.use_longcalls
;
5058 fragP
->tc_frag_data
.use_absolute_literals
=
5059 last_fragP
->tc_frag_data
.use_absolute_literals
;
5062 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5071 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5073 void *unused ATTRIBUTE_UNUSED
)
5075 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5076 segment_info_type
*seginfo
= seg_info (sec
);
5077 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5079 if (flags
& SEC_CODE
)
5081 xtensa_isa isa
= xtensa_default_isa
;
5082 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5083 while (frag
!= NULL
)
5085 if (frag
->tc_frag_data
.is_branch_target
)
5088 addressT branch_align
, frag_addr
;
5091 xtensa_insnbuf_from_chars
5092 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5093 fmt
= xtensa_format_decode (isa
, insnbuf
);
5094 op_size
= xtensa_format_length (isa
, fmt
);
5095 branch_align
= 1 << branch_align_power (sec
);
5096 frag_addr
= frag
->fr_address
% branch_align
;
5097 if (frag_addr
+ op_size
> branch_align
)
5098 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5099 _("unaligned branch target: %d bytes at 0x%lx"),
5100 op_size
, (long) frag
->fr_address
);
5102 frag
= frag
->fr_next
;
5104 xtensa_insnbuf_free (isa
, insnbuf
);
5110 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5112 void *unused ATTRIBUTE_UNUSED
)
5114 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5115 segment_info_type
*seginfo
= seg_info (sec
);
5116 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5117 xtensa_isa isa
= xtensa_default_isa
;
5119 if (flags
& SEC_CODE
)
5121 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5122 while (frag
!= NULL
)
5124 if (frag
->tc_frag_data
.is_first_loop_insn
)
5130 if (frag
->fr_fix
== 0)
5131 frag
= next_non_empty_frag (frag
);
5135 xtensa_insnbuf_from_chars
5136 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5137 fmt
= xtensa_format_decode (isa
, insnbuf
);
5138 op_size
= xtensa_format_length (isa
, fmt
);
5139 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5141 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5142 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5143 _("unaligned loop: %d bytes at 0x%lx"),
5144 op_size
, (long) frag
->fr_address
);
5147 frag
= frag
->fr_next
;
5149 xtensa_insnbuf_free (isa
, insnbuf
);
5155 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5157 xtensa_isa isa
= xtensa_default_isa
;
5158 static xtensa_insnbuf insnbuf
= NULL
;
5159 static xtensa_insnbuf slotbuf
= NULL
;
5162 bfd_boolean alt_reloc
;
5163 xtensa_opcode opcode
;
5164 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5166 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5168 as_fatal (_("unexpected fix"));
5172 insnbuf
= xtensa_insnbuf_alloc (isa
);
5173 slotbuf
= xtensa_insnbuf_alloc (isa
);
5176 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5177 fmt
= xtensa_format_decode (isa
, insnbuf
);
5178 if (fmt
== XTENSA_UNDEFINED
)
5179 as_fatal (_("undecodable fix"));
5180 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5181 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5182 if (opcode
== XTENSA_UNDEFINED
)
5183 as_fatal (_("undecodable fix"));
5185 /* CONST16 immediates are not PC-relative, despite the fact that we
5186 reuse the normal PC-relative operand relocations for the low part
5187 of a CONST16 operand. */
5188 if (opcode
== xtensa_const16_opcode
)
5191 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5192 get_relaxable_immed (opcode
), val
,
5193 fixP
->fx_file
, fixP
->fx_line
);
5195 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5196 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5202 /* External Functions and Other GAS Hooks. */
5205 xtensa_target_format (void)
5207 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5212 xtensa_file_arch_init (bfd
*abfd
)
5214 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5219 md_number_to_chars (char *buf
, valueT val
, int n
)
5221 if (target_big_endian
)
5222 number_to_chars_bigendian (buf
, val
, n
);
5224 number_to_chars_littleendian (buf
, val
, n
);
5228 /* This function is called once, at assembler startup time. It should
5229 set up all the tables, etc. that the MD part of the assembler will
5235 segT current_section
= now_seg
;
5236 int current_subsec
= now_subseg
;
5240 xtensa_default_isa
= xtensa_isa_init (0, 0);
5241 isa
= xtensa_default_isa
;
5245 /* Set up the literal sections. */
5246 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5248 subseg_set (current_section
, current_subsec
);
5250 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5251 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5252 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5253 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5254 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5255 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5256 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5257 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5258 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5259 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5260 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5261 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5262 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5263 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5264 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5265 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5266 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5267 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5268 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5269 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5270 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5271 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5272 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5273 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5274 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5275 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5276 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5277 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5278 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5279 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5280 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5282 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5284 int format_slots
= xtensa_format_num_slots (isa
, i
);
5285 if (format_slots
> config_max_slots
)
5286 config_max_slots
= format_slots
;
5289 xg_init_vinsn (&cur_vinsn
);
5291 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5293 init_op_placement_info_table ();
5295 /* Set up the assembly state. */
5296 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5297 xtensa_set_frag_assembly_state (frag_now
);
5301 /* TC_INIT_FIX_DATA hook */
5304 xtensa_init_fix_data (fixS
*x
)
5306 x
->tc_fix_data
.slot
= 0;
5307 x
->tc_fix_data
.X_add_symbol
= NULL
;
5308 x
->tc_fix_data
.X_add_number
= 0;
5312 /* tc_frob_label hook */
5315 xtensa_frob_label (symbolS
*sym
)
5319 if (cur_vinsn
.inside_bundle
)
5321 as_bad (_("labels are not valid inside bundles"));
5325 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5327 /* Since the label was already attached to a frag associated with the
5328 previous basic block, it now needs to be reset to the current frag. */
5329 symbol_set_frag (sym
, frag_now
);
5330 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5332 if (generating_literals
)
5333 xtensa_add_literal_sym (sym
);
5335 xtensa_add_insn_label (sym
);
5337 if (symbol_get_tc (sym
)->is_loop_target
)
5339 if ((get_last_insn_flags (now_seg
, now_subseg
)
5340 & FLAG_IS_BAD_LOOPEND
) != 0)
5341 as_bad (_("invalid last instruction for a zero-overhead loop"));
5343 xtensa_set_frag_assembly_state (frag_now
);
5344 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5345 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5347 xtensa_set_frag_assembly_state (frag_now
);
5348 xtensa_move_labels (frag_now
, 0);
5351 /* No target aligning in the absolute section. */
5352 if (now_seg
!= absolute_section
5353 && !is_unaligned_label (sym
)
5354 && !generating_literals
)
5356 xtensa_set_frag_assembly_state (frag_now
);
5358 if (do_align_targets ())
5359 frag_var (rs_machine_dependent
, 0, (int) freq
,
5360 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5361 frag_now
->fr_offset
, NULL
);
5363 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5364 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5365 xtensa_set_frag_assembly_state (frag_now
);
5366 xtensa_move_labels (frag_now
, 0);
5369 /* We need to mark the following properties even if we aren't aligning. */
5371 /* If the label is already known to be a branch target, i.e., a
5372 forward branch, mark the frag accordingly. Backward branches
5373 are handled by xg_add_branch_and_loop_targets. */
5374 if (symbol_get_tc (sym
)->is_branch_target
)
5375 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5377 /* Loops only go forward, so they can be identified here. */
5378 if (symbol_get_tc (sym
)->is_loop_target
)
5379 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5381 dwarf2_emit_label (sym
);
5385 /* tc_unrecognized_line hook */
5388 xtensa_unrecognized_line (int ch
)
5393 if (cur_vinsn
.inside_bundle
== 0)
5395 /* PR8110: Cannot emit line number info inside a FLIX bundle
5396 when using --gstabs. Temporarily disable debug info. */
5397 generate_lineno_debug ();
5398 if (debug_type
== DEBUG_STABS
)
5400 xt_saved_debug_type
= debug_type
;
5401 debug_type
= DEBUG_NONE
;
5404 cur_vinsn
.inside_bundle
= 1;
5408 as_bad (_("extra opening brace"));
5414 if (cur_vinsn
.inside_bundle
)
5415 finish_vinsn (&cur_vinsn
);
5418 as_bad (_("extra closing brace"));
5423 as_bad (_("syntax error"));
5430 /* md_flush_pending_output hook */
5433 xtensa_flush_pending_output (void)
5435 /* This line fixes a bug where automatically generated gstabs info
5436 separates a function label from its entry instruction, ending up
5437 with the literal position between the function label and the entry
5438 instruction and crashing code. It only happens with --gstabs and
5439 --text-section-literals, and when several other obscure relaxation
5440 conditions are met. */
5441 if (outputting_stabs_line_debug
)
5444 if (cur_vinsn
.inside_bundle
)
5445 as_bad (_("missing closing brace"));
5447 /* If there is a non-zero instruction fragment, close it. */
5448 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5450 frag_wane (frag_now
);
5452 xtensa_set_frag_assembly_state (frag_now
);
5454 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5456 xtensa_clear_insn_labels ();
5460 /* We had an error while parsing an instruction. The string might look
5461 like this: "insn arg1, arg2 }". If so, we need to see the closing
5462 brace and reset some fields. Otherwise, the vinsn never gets closed
5463 and the num_slots field will grow past the end of the array of slots,
5464 and bad things happen. */
5467 error_reset_cur_vinsn (void)
5469 if (cur_vinsn
.inside_bundle
)
5471 if (*input_line_pointer
== '}'
5472 || *(input_line_pointer
- 1) == '}'
5473 || *(input_line_pointer
- 2) == '}')
5474 xg_clear_vinsn (&cur_vinsn
);
5480 md_assemble (char *str
)
5482 xtensa_isa isa
= xtensa_default_isa
;
5485 bfd_boolean has_underbar
= FALSE
;
5486 char *arg_strings
[MAX_INSN_ARGS
];
5488 TInsn orig_insn
; /* Original instruction from the input. */
5490 tinsn_init (&orig_insn
);
5492 /* Split off the opcode. */
5493 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5494 opname
= xstrndup (str
, opnamelen
);
5496 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5499 as_bad (_("syntax error"));
5503 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5506 /* Check for an underbar prefix. */
5509 has_underbar
= TRUE
;
5513 orig_insn
.insn_type
= ITYPE_INSN
;
5515 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5516 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5518 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5519 extra argument and set the opcode to "CALLXn". */
5520 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5521 && strncasecmp (opname
, "callx", 5) == 0)
5523 unsigned long window_size
;
5526 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5527 if (suffix
!= opname
+ 5
5528 && (window_size
== 0
5531 || window_size
== 12)
5532 && strcasecmp (suffix
, ".tls") == 0)
5534 switch (window_size
)
5536 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5537 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5538 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5539 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5543 as_bad (_("wrong number of operands for '%s'"), opname
);
5546 bfd_reloc_code_real_type reloc
;
5547 char *old_input_line_pointer
;
5548 expressionS
*tok
= &orig_insn
.extra_arg
;
5550 old_input_line_pointer
= input_line_pointer
;
5551 input_line_pointer
= arg_strings
[num_args
- 1];
5554 if (tok
->X_op
== O_symbol
5555 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5556 == BFD_RELOC_XTENSA_TLS_CALL
))
5557 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5559 as_bad (_("bad relocation expression for '%s'"), opname
);
5561 input_line_pointer
= old_input_line_pointer
;
5567 /* Special case: Check for "j.l" psuedo op. */
5568 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5569 && strncasecmp (opname
, "j.l", 3) == 0)
5572 as_bad (_("wrong number of operands for '%s'"), opname
);
5575 char *old_input_line_pointer
;
5576 expressionS
*tok
= &orig_insn
.extra_arg
;
5578 old_input_line_pointer
= input_line_pointer
;
5579 input_line_pointer
= arg_strings
[num_args
- 1];
5581 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5582 input_line_pointer
= old_input_line_pointer
;
5585 orig_insn
.opcode
= xtensa_j_opcode
;
5589 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5591 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5592 if (fmt
== XTENSA_UNDEFINED
)
5594 as_bad (_("unknown opcode or format name '%s'"), opname
);
5595 error_reset_cur_vinsn ();
5598 if (!cur_vinsn
.inside_bundle
)
5600 as_bad (_("format names only valid inside bundles"));
5601 error_reset_cur_vinsn ();
5604 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5605 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5607 cur_vinsn
.format
= fmt
;
5608 free (has_underbar
? opname
- 1 : opname
);
5609 error_reset_cur_vinsn ();
5613 /* Parse the arguments. */
5614 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5616 as_bad (_("syntax error"));
5617 error_reset_cur_vinsn ();
5621 /* Free the opcode and argument strings, now that they've been parsed. */
5622 free (has_underbar
? opname
- 1 : opname
);
5624 while (num_args
-- > 0)
5625 free (arg_strings
[num_args
]);
5627 /* Get expressions for invisible operands. */
5628 if (get_invisible_operands (&orig_insn
))
5630 error_reset_cur_vinsn ();
5634 /* Check for the right number and type of arguments. */
5635 if (tinsn_check_arguments (&orig_insn
))
5637 error_reset_cur_vinsn ();
5641 /* Record the line number for each TInsn, because a FLIX bundle may be
5642 spread across multiple input lines and individual instructions may be
5643 moved around in some cases. */
5644 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5645 dwarf2_where (&orig_insn
.debug_line
);
5646 dwarf2_consume_line_info ();
5648 xg_add_branch_and_loop_targets (&orig_insn
);
5650 /* Check that immediate value for ENTRY is >= 16. */
5651 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5653 expressionS
*exp
= &orig_insn
.tok
[2];
5654 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5655 as_warn (_("entry instruction with stack decrement < 16"));
5659 assemble_tokens (opcode, tok, ntok);
5660 expand the tokens from the orig_insn into the
5661 stack of instructions that will not expand
5662 unless required at relaxation time. */
5664 if (!cur_vinsn
.inside_bundle
)
5665 emit_single_op (&orig_insn
);
5666 else /* We are inside a bundle. */
5668 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5669 cur_vinsn
.num_slots
++;
5670 if (*input_line_pointer
== '}'
5671 || *(input_line_pointer
- 1) == '}'
5672 || *(input_line_pointer
- 2) == '}')
5673 finish_vinsn (&cur_vinsn
);
5676 /* We've just emitted a new instruction so clear the list of labels. */
5677 xtensa_clear_insn_labels ();
5679 xtensa_check_frag_count ();
5683 /* HANDLE_ALIGN hook */
5685 /* For a .align directive, we mark the previous block with the alignment
5686 information. This will be placed in the object file in the
5687 property section corresponding to this section. */
5690 xtensa_handle_align (fragS
*fragP
)
5693 && ! fragP
->tc_frag_data
.is_literal
5694 && (fragP
->fr_type
== rs_align
5695 || fragP
->fr_type
== rs_align_code
)
5696 && fragP
->fr_offset
> 0
5697 && now_seg
!= bss_section
)
5699 fragP
->tc_frag_data
.is_align
= TRUE
;
5700 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5703 if (fragP
->fr_type
== rs_align_test
)
5706 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5708 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5709 _("unaligned entry instruction"));
5712 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5713 fragP
->fr_subtype
= RELAX_ORG
;
5717 /* TC_FRAG_INIT hook */
5720 xtensa_frag_init (fragS
*frag
)
5722 xtensa_set_frag_assembly_state (frag
);
5727 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5733 /* Round up a section size to the appropriate boundary. */
5736 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5738 return size
; /* Byte alignment is fine. */
5743 md_pcrel_from (fixS
*fixP
)
5746 static xtensa_insnbuf insnbuf
= NULL
;
5747 static xtensa_insnbuf slotbuf
= NULL
;
5750 xtensa_opcode opcode
;
5753 xtensa_isa isa
= xtensa_default_isa
;
5754 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5755 bfd_boolean alt_reloc
;
5757 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5760 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5765 insnbuf
= xtensa_insnbuf_alloc (isa
);
5766 slotbuf
= xtensa_insnbuf_alloc (isa
);
5769 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5770 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5771 fmt
= xtensa_format_decode (isa
, insnbuf
);
5773 if (fmt
== XTENSA_UNDEFINED
)
5774 as_fatal (_("bad instruction format"));
5776 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5777 as_fatal (_("invalid relocation"));
5779 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5780 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5782 /* Check for "alternate" relocations (operand not specified). None
5783 of the current uses for these are really PC-relative. */
5784 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5786 if (opcode
!= xtensa_l32r_opcode
5787 && opcode
!= xtensa_const16_opcode
)
5788 as_fatal (_("invalid relocation for '%s' instruction"),
5789 xtensa_opcode_name (isa
, opcode
));
5793 opnum
= get_relaxable_immed (opcode
);
5795 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5796 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5798 as_bad_where (fixP
->fx_file
,
5800 _("invalid relocation for operand %d of '%s'"),
5801 opnum
, xtensa_opcode_name (isa
, opcode
));
5804 return 0 - opnd_value
;
5808 /* TC_FORCE_RELOCATION hook */
5811 xtensa_force_relocation (fixS
*fix
)
5813 switch (fix
->fx_r_type
)
5815 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5816 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5817 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5818 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5819 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5820 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5821 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5822 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5823 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5824 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5825 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5826 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5827 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5828 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5829 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5830 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5836 if (linkrelax
&& fix
->fx_addsy
5837 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5840 return generic_force_reloc (fix
);
5844 /* TC_VALIDATE_FIX_SUB hook */
5847 xtensa_validate_fix_sub (fixS
*fix
)
5849 segT add_symbol_segment
, sub_symbol_segment
;
5851 /* The difference of two symbols should be resolved by the assembler when
5852 linkrelax is not set. If the linker may relax the section containing
5853 the symbols, then an Xtensa DIFF relocation must be generated so that
5854 the linker knows to adjust the difference value. */
5855 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5858 /* Make sure both symbols are in the same segment, and that segment is
5859 "normal" and relaxable. If the segment is not "normal", then the
5860 fix is not valid. If the segment is not "relaxable", then the fix
5861 should have been handled earlier. */
5862 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5863 if (! SEG_NORMAL (add_symbol_segment
) ||
5864 ! relaxable_section (add_symbol_segment
))
5866 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5867 return (sub_symbol_segment
== add_symbol_segment
);
5871 /* NO_PSEUDO_DOT hook */
5873 /* This function has nothing to do with pseudo dots, but this is the
5874 nearest macro to where the check needs to take place. FIXME: This
5878 xtensa_check_inside_bundle (void)
5880 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5881 as_bad (_("directives are not valid inside bundles"));
5883 /* This function must always return FALSE because it is called via a
5884 macro that has nothing to do with bundling. */
5889 /* md_elf_section_change_hook */
5892 xtensa_elf_section_change_hook (void)
5894 /* Set up the assembly state. */
5895 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5896 xtensa_set_frag_assembly_state (frag_now
);
5900 /* tc_fix_adjustable hook */
5903 xtensa_fix_adjustable (fixS
*fixP
)
5905 /* We need the symbol name for the VTABLE entries. */
5906 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5907 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5914 /* tc_symbol_new_hook */
5916 symbolS
*expr_symbols
= NULL
;
5919 xtensa_symbol_new_hook (symbolS
*sym
)
5921 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5923 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5930 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5932 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5935 /* Subtracted symbols are only allowed for a few relocation types, and
5936 unless linkrelax is enabled, they should not make it to this point. */
5937 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5938 || fixP
->fx_r_type
== BFD_RELOC_16
5939 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5942 switch (fixP
->fx_r_type
)
5944 case BFD_RELOC_32_PCREL
:
5950 switch (fixP
->fx_r_type
)
5953 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5954 fixP
->fx_signed
= 0;
5957 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5958 fixP
->fx_signed
= 0;
5961 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5962 fixP
->fx_signed
= 0;
5968 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5969 - S_GET_VALUE (fixP
->fx_subsy
));
5971 /* The difference value gets written out, and the DIFF reloc
5972 identifies the address of the subtracted symbol (i.e., the one
5973 with the lowest address). */
5975 fixP
->fx_offset
-= val
;
5976 fixP
->fx_subsy
= NULL
;
5978 else if (! fixP
->fx_addsy
)
5985 case BFD_RELOC_XTENSA_PLT
:
5986 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5987 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5990 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5991 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5992 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5993 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5994 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5995 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5996 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5999 case BFD_RELOC_XTENSA_SLOT0_OP
:
6000 case BFD_RELOC_XTENSA_SLOT1_OP
:
6001 case BFD_RELOC_XTENSA_SLOT2_OP
:
6002 case BFD_RELOC_XTENSA_SLOT3_OP
:
6003 case BFD_RELOC_XTENSA_SLOT4_OP
:
6004 case BFD_RELOC_XTENSA_SLOT5_OP
:
6005 case BFD_RELOC_XTENSA_SLOT6_OP
:
6006 case BFD_RELOC_XTENSA_SLOT7_OP
:
6007 case BFD_RELOC_XTENSA_SLOT8_OP
:
6008 case BFD_RELOC_XTENSA_SLOT9_OP
:
6009 case BFD_RELOC_XTENSA_SLOT10_OP
:
6010 case BFD_RELOC_XTENSA_SLOT11_OP
:
6011 case BFD_RELOC_XTENSA_SLOT12_OP
:
6012 case BFD_RELOC_XTENSA_SLOT13_OP
:
6013 case BFD_RELOC_XTENSA_SLOT14_OP
:
6016 /* Write the tentative value of a PC-relative relocation to a
6017 local symbol into the instruction. The value will be ignored
6018 by the linker, and it makes the object file disassembly
6019 readable when all branch targets are encoded in relocations. */
6021 gas_assert (fixP
->fx_addsy
);
6022 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6023 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6025 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6026 - md_pcrel_from (fixP
));
6027 (void) xg_apply_fix_value (fixP
, val
);
6030 else if (! fixP
->fx_addsy
)
6033 if (xg_apply_fix_value (fixP
, val
))
6038 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6039 case BFD_RELOC_XTENSA_TLS_FUNC
:
6040 case BFD_RELOC_XTENSA_TLS_ARG
:
6041 case BFD_RELOC_XTENSA_TLS_CALL
:
6042 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6043 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6044 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6045 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6046 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6047 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6048 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6049 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6050 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6051 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6052 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6053 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6054 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6055 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6056 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6057 /* These all need to be resolved at link-time. Do nothing now. */
6060 case BFD_RELOC_VTABLE_INHERIT
:
6061 case BFD_RELOC_VTABLE_ENTRY
:
6066 as_bad (_("unhandled local relocation fix %s"),
6067 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6073 md_atof (int type
, char *litP
, int *sizeP
)
6075 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6080 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6082 return total_frag_text_expansion (fragP
);
6086 /* Translate internal representation of relocation info to BFD target
6090 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6094 reloc
= XNEW (arelent
);
6095 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6096 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6097 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6099 /* Make sure none of our internal relocations make it this far.
6100 They'd better have been fully resolved by this point. */
6101 gas_assert ((int) fixp
->fx_r_type
> 0);
6103 reloc
->addend
= fixp
->fx_offset
;
6105 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6106 if (reloc
->howto
== NULL
)
6108 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6109 _("cannot represent `%s' relocation in object file"),
6110 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6111 free (reloc
->sym_ptr_ptr
);
6116 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6117 as_fatal (_("internal error; cannot generate `%s' relocation"),
6118 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6124 /* Checks for resource conflicts between instructions. */
6126 /* The func unit stuff could be implemented as bit-vectors rather
6127 than the iterative approach here. If it ends up being too
6128 slow, we will switch it. */
6131 new_resource_table (void *data
,
6134 unit_num_copies_func uncf
,
6135 opcode_num_units_func onuf
,
6136 opcode_funcUnit_use_unit_func ouuf
,
6137 opcode_funcUnit_use_stage_func ousf
)
6140 resource_table
*rt
= XNEW (resource_table
);
6142 rt
->cycles
= cycles
;
6143 rt
->allocated_cycles
= cycles
;
6145 rt
->unit_num_copies
= uncf
;
6146 rt
->opcode_num_units
= onuf
;
6147 rt
->opcode_unit_use
= ouuf
;
6148 rt
->opcode_unit_stage
= ousf
;
6150 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6151 for (i
= 0; i
< cycles
; i
++)
6152 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6159 clear_resource_table (resource_table
*rt
)
6162 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6163 for (j
= 0; j
< rt
->num_units
; j
++)
6164 rt
->units
[i
][j
] = 0;
6168 /* We never shrink it, just fake it into thinking so. */
6171 resize_resource_table (resource_table
*rt
, int cycles
)
6175 rt
->cycles
= cycles
;
6176 if (cycles
<= rt
->allocated_cycles
)
6179 old_cycles
= rt
->allocated_cycles
;
6180 rt
->allocated_cycles
= cycles
;
6182 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6183 for (i
= 0; i
< old_cycles
; i
++)
6184 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6185 for (i
= old_cycles
; i
< cycles
; i
++)
6186 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6191 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6194 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6196 for (i
= 0; i
< uses
; i
++)
6198 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6199 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6200 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6201 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6202 if (copies_in_use
>= copies
)
6210 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6213 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6215 for (i
= 0; i
< uses
; i
++)
6217 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6218 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6219 /* Note that this allows resources to be oversubscribed. That's
6220 essential to the way the optional scheduler works.
6221 resources_available reports when a resource is over-subscribed,
6222 so it's easy to tell. */
6223 rt
->units
[stage
+ cycle
][unit
]++;
6229 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6232 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6234 for (i
= 0; i
< uses
; i
++)
6236 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6237 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6238 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6239 rt
->units
[stage
+ cycle
][unit
]--;
6244 /* Wrapper functions make parameterized resource reservation
6248 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6250 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6256 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6258 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6263 /* Note that this function does not check issue constraints, but
6264 solely whether the hardware is available to execute the given
6265 instructions together. It also doesn't check if the tinsns
6266 write the same state, or access the same tieports. That is
6267 checked by check_t1_t2_reads_and_writes. */
6270 resources_conflict (vliw_insn
*vinsn
)
6273 static resource_table
*rt
= NULL
;
6275 /* This is the most common case by far. Optimize it. */
6276 if (vinsn
->num_slots
== 1)
6281 xtensa_isa isa
= xtensa_default_isa
;
6282 rt
= new_resource_table
6283 (isa
, xtensa_num_pipe_stages
,
6284 xtensa_isa_num_funcUnits (isa
),
6285 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6286 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6287 opcode_funcUnit_use_unit
,
6288 opcode_funcUnit_use_stage
);
6291 clear_resource_table (rt
);
6293 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6295 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6297 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6304 /* finish_vinsn, emit_single_op and helper functions. */
6306 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6307 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6308 static void xg_assemble_vliw_tokens (vliw_insn
*);
6311 /* We have reached the end of a bundle; emit into the frag. */
6314 finish_vinsn (vliw_insn
*vinsn
)
6319 if (find_vinsn_conflicts (vinsn
))
6321 xg_clear_vinsn (vinsn
);
6325 /* First, find a format that works. */
6326 if (vinsn
->format
== XTENSA_UNDEFINED
)
6327 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6329 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6330 && produce_flix
== FLIX_NONE
)
6332 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6333 xg_clear_vinsn (vinsn
);
6337 if (vinsn
->format
== XTENSA_UNDEFINED
)
6339 as_bad (_("couldn't find a valid instruction format"));
6340 fprintf (stderr
, _(" ops were: "));
6341 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6342 fprintf (stderr
, _(" %s;"),
6343 xtensa_opcode_name (xtensa_default_isa
,
6344 vinsn
->slots
[i
].opcode
));
6345 fprintf (stderr
, _("\n"));
6346 xg_clear_vinsn (vinsn
);
6350 if (vinsn
->num_slots
6351 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6353 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6354 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6355 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6357 xg_clear_vinsn (vinsn
);
6361 if (resources_conflict (vinsn
))
6363 as_bad (_("illegal resource usage in bundle"));
6364 fprintf (stderr
, " ops were: ");
6365 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6366 fprintf (stderr
, " %s;",
6367 xtensa_opcode_name (xtensa_default_isa
,
6368 vinsn
->slots
[i
].opcode
));
6369 fprintf (stderr
, "\n");
6370 xg_clear_vinsn (vinsn
);
6374 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6376 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6378 symbolS
*lit_sym
= NULL
;
6380 bfd_boolean e
= FALSE
;
6381 bfd_boolean saved_density
= density_supported
;
6383 /* We don't want to narrow ops inside multi-slot bundles. */
6384 if (vinsn
->num_slots
> 1)
6385 density_supported
= FALSE
;
6387 istack_init (&slotstack
);
6388 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6390 vinsn
->slots
[i
].opcode
=
6391 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6393 vinsn
->slots
[i
].ntok
= 0;
6396 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6402 density_supported
= saved_density
;
6406 xg_clear_vinsn (vinsn
);
6410 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6412 TInsn
*insn
= &slotstack
.insn
[j
];
6413 if (insn
->insn_type
== ITYPE_LITERAL
)
6415 gas_assert (lit_sym
== NULL
);
6416 lit_sym
= xg_assemble_literal (insn
);
6420 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6422 xg_resolve_literals (insn
, lit_sym
);
6423 if (j
!= slotstack
.ninsn
- 1)
6424 emit_single_op (insn
);
6428 if (vinsn
->num_slots
> 1)
6430 if (opcode_fits_format_slot
6431 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6434 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6438 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6439 if (vinsn
->format
== XTENSA_UNDEFINED
)
6440 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6442 vinsn
->slots
[i
].opcode
6443 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6446 vinsn
->slots
[i
].ntok
= 0;
6451 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6452 vinsn
->format
= XTENSA_UNDEFINED
;
6457 /* Now check resource conflicts on the modified bundle. */
6458 if (resources_conflict (vinsn
))
6460 as_bad (_("illegal resource usage in bundle"));
6461 fprintf (stderr
, " ops were: ");
6462 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6463 fprintf (stderr
, " %s;",
6464 xtensa_opcode_name (xtensa_default_isa
,
6465 vinsn
->slots
[i
].opcode
));
6466 fprintf (stderr
, "\n");
6467 xg_clear_vinsn (vinsn
);
6471 /* First, find a format that works. */
6472 if (vinsn
->format
== XTENSA_UNDEFINED
)
6473 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6475 xg_assemble_vliw_tokens (vinsn
);
6477 xg_clear_vinsn (vinsn
);
6479 xtensa_check_frag_count ();
6483 /* Given an vliw instruction, what conflicts are there in register
6484 usage and in writes to states and queues?
6486 This function does two things:
6487 1. Reports an error when a vinsn contains illegal combinations
6488 of writes to registers states or queues.
6489 2. Marks individual tinsns as not relaxable if the combination
6490 contains antidependencies.
6492 Job 2 handles things like swap semantics in instructions that need
6493 to be relaxed. For example,
6497 normally would be relaxed to
6502 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6504 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6506 then we can't relax it into
6509 { add a0, a1, a0 ; add a2, a0, a4 ; }
6511 because the value of a0 is trashed before the second add can read it. */
6513 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6516 find_vinsn_conflicts (vliw_insn
*vinsn
)
6520 xtensa_isa isa
= xtensa_default_isa
;
6522 gas_assert (!past_xtensa_end
);
6524 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6526 TInsn
*op1
= &vinsn
->slots
[i
];
6527 if (op1
->is_specific_opcode
)
6528 op1
->keep_wide
= TRUE
;
6530 op1
->keep_wide
= FALSE
;
6533 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6535 TInsn
*op1
= &vinsn
->slots
[i
];
6537 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6540 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6544 TInsn
*op2
= &vinsn
->slots
[j
];
6545 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6546 switch (conflict_type
)
6549 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6550 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6551 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6554 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6555 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6556 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6559 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6560 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6561 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6564 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6565 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6566 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6569 /* Everything is OK. */
6572 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6573 || conflict_type
== 'a');
6580 as_bad (_("multiple branches or jumps in the same bundle"));
6588 /* Check how the state used by t1 and t2 relate.
6591 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6592 case B: no relationship between what is read and written (both could
6593 read the same reg though)
6594 case C: t1 writes a register t2 writes (a register conflict within a
6596 case D: t1 writes a state that t2 also writes
6597 case E: t1 writes a tie queue that t2 also writes
6598 case F: two volatile queue accesses
6602 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6604 xtensa_isa isa
= xtensa_default_isa
;
6605 xtensa_regfile t1_regfile
, t2_regfile
;
6607 int t1_base_reg
, t1_last_reg
;
6608 int t2_base_reg
, t2_last_reg
;
6609 char t1_inout
, t2_inout
;
6611 char conflict
= 'b';
6616 bfd_boolean t1_volatile
= FALSE
;
6617 bfd_boolean t2_volatile
= FALSE
;
6619 /* Check registers. */
6620 for (j
= 0; j
< t2
->ntok
; j
++)
6622 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6625 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6626 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6627 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6629 for (i
= 0; i
< t1
->ntok
; i
++)
6631 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6634 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6636 if (t1_regfile
!= t2_regfile
)
6639 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6640 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6642 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6643 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6645 if (t1_inout
== 'm' || t1_inout
== 'o'
6646 || t2_inout
== 'm' || t2_inout
== 'o')
6653 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6654 t1_last_reg
= (t1_base_reg
6655 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6657 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6659 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6661 if (t1_reg
!= t2_reg
)
6664 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6670 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6676 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6684 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6685 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6686 for (j
= 0; j
< t2_states
; j
++)
6688 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6689 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6690 for (i
= 0; i
< t1_states
; i
++)
6692 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6693 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6694 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6697 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6703 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6709 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6714 /* Check tieports. */
6715 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6716 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6717 for (j
= 0; j
< t2_interfaces
; j
++)
6719 xtensa_interface t2_int
6720 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6721 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6723 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6724 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6727 for (i
= 0; i
< t1_interfaces
; i
++)
6729 xtensa_interface t1_int
6730 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6731 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6733 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6734 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6737 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6740 if (t1_int
!= t2_int
)
6743 if (t2_inout
== 'i' && t1_inout
== 'o')
6749 if (t1_inout
== 'i' && t2_inout
== 'o')
6755 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6764 static xtensa_format
6765 xg_find_narrowest_format (vliw_insn
*vinsn
)
6767 /* Right now we assume that the ops within the vinsn are properly
6768 ordered for the slots that the programmer wanted them in. In
6769 other words, we don't rearrange the ops in hopes of finding a
6770 better format. The scheduler handles that. */
6772 xtensa_isa isa
= xtensa_default_isa
;
6773 xtensa_format format
;
6774 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6776 if (vinsn
->num_slots
== 1)
6777 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6779 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6782 xg_copy_vinsn (&v_copy
, vinsn
);
6783 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6787 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6789 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6791 v_copy
.slots
[slot
].opcode
=
6792 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6793 v_copy
.slots
[slot
].ntok
= 0;
6796 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6799 else if (v_copy
.num_slots
> 1)
6802 /* Try the widened version. */
6803 if (!v_copy
.slots
[slot
].keep_wide
6804 && !v_copy
.slots
[slot
].is_specific_opcode
6805 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6807 && opcode_fits_format_slot (widened
.opcode
,
6810 v_copy
.slots
[slot
] = widened
;
6815 if (fit
== v_copy
.num_slots
)
6817 xg_copy_vinsn (vinsn
, &v_copy
);
6818 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6819 vinsn
->format
= format
;
6825 if (format
== xtensa_isa_num_formats (isa
))
6826 return XTENSA_UNDEFINED
;
6832 /* Return the additional space needed in a frag
6833 for possible relaxations of any ops in a VLIW insn.
6834 Also fill out the relaxations that might be required of
6835 each tinsn in the vinsn. */
6838 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6840 bfd_boolean finish_frag
= FALSE
;
6841 int extra_space
= 0;
6844 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6846 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6847 if (!tinsn_has_symbolic_operands (tinsn
))
6849 /* A narrow instruction could be widened later to help
6850 alignment issues. */
6851 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6852 && !tinsn
->is_specific_opcode
6853 && vinsn
->num_slots
== 1)
6855 /* Difference in bytes between narrow and wide insns... */
6857 tinsn
->subtype
= RELAX_NARROW
;
6862 if (workaround_b_j_loop_end
6863 && tinsn
->opcode
== xtensa_jx_opcode
6864 && use_transform ())
6866 /* Add 2 of these. */
6867 extra_space
+= 3; /* for the nop size */
6868 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6871 /* Need to assemble it with space for the relocation. */
6872 if (xg_is_relaxable_insn (tinsn
, 0)
6873 && !tinsn
->is_specific_opcode
)
6875 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6876 int max_literal_size
=
6877 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6879 tinsn
->literal_space
= max_literal_size
;
6881 tinsn
->subtype
= RELAX_IMMED
;
6882 extra_space
+= max_size
;
6886 /* A fix record will be added for this instruction prior
6887 to relaxation, so make it end the frag. */
6892 *pfinish_frag
= finish_frag
;
6898 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6900 xtensa_isa isa
= xtensa_default_isa
;
6901 int slot
, chosen_slot
;
6903 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6904 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6905 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6907 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6908 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6910 if (slot
== chosen_slot
)
6911 vinsn
->slots
[slot
] = *tinsn
;
6914 vinsn
->slots
[slot
].opcode
=
6915 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6916 vinsn
->slots
[slot
].ntok
= 0;
6917 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6924 emit_single_op (TInsn
*orig_insn
)
6927 IStack istack
; /* put instructions into here */
6928 symbolS
*lit_sym
= NULL
;
6929 symbolS
*label_sym
= NULL
;
6931 istack_init (&istack
);
6933 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6934 Because the scheduling and bundling characteristics of movi and
6935 l32r or const16 are so different, we can do much better if we relax
6936 it prior to scheduling and bundling, rather than after. */
6937 if ((orig_insn
->opcode
== xtensa_movi_opcode
6938 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6939 && !cur_vinsn
.inside_bundle
6940 && (orig_insn
->tok
[1].X_op
== O_symbol
6941 || orig_insn
->tok
[1].X_op
== O_pltrel
6942 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6943 || orig_insn
->tok
[1].X_op
== O_tlsarg
6944 || orig_insn
->tok
[1].X_op
== O_tpoff
6945 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6946 && !orig_insn
->is_specific_opcode
&& use_transform ())
6947 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6949 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6952 for (i
= 0; i
< istack
.ninsn
; i
++)
6954 TInsn
*insn
= &istack
.insn
[i
];
6955 switch (insn
->insn_type
)
6958 gas_assert (lit_sym
== NULL
);
6959 lit_sym
= xg_assemble_literal (insn
);
6963 static int relaxed_sym_idx
= 0;
6964 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
6965 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6967 gas_assert (label_sym
== NULL
);
6968 label_sym
= symbol_find_or_make (label
);
6969 gas_assert (label_sym
);
6977 xg_resolve_literals (insn
, lit_sym
);
6979 xg_resolve_labels (insn
, label_sym
);
6981 bundle_tinsn (insn
, &v
);
6996 total_frag_text_expansion (fragS
*fragP
)
6999 int total_expansion
= 0;
7001 for (slot
= 0; slot
< config_max_slots
; slot
++)
7002 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7004 return total_expansion
;
7008 /* Emit a vliw instruction to the current fragment. */
7011 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7013 bfd_boolean finish_frag
;
7014 bfd_boolean is_jump
= FALSE
;
7015 bfd_boolean is_branch
= FALSE
;
7016 xtensa_isa isa
= xtensa_default_isa
;
7021 struct dwarf2_line_info debug_line
;
7022 bfd_boolean loc_directive_seen
= FALSE
;
7025 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7027 if (generating_literals
)
7029 static int reported
= 0;
7031 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7032 _("cannot assemble into a literal fragment"));
7039 if (frag_now_fix () != 0
7040 && (! frag_now
->tc_frag_data
.is_insn
7041 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7042 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7043 || (directive_state
[directive_longcalls
]
7044 != frag_now
->tc_frag_data
.use_longcalls
)
7045 || (directive_state
[directive_absolute_literals
]
7046 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7048 frag_wane (frag_now
);
7050 xtensa_set_frag_assembly_state (frag_now
);
7053 if (workaround_a0_b_retw
7054 && vinsn
->num_slots
== 1
7055 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7056 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7057 && use_transform ())
7059 has_a0_b_retw
= TRUE
;
7061 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7062 After the first assembly pass we will check all of them and
7063 add a nop if needed. */
7064 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7065 frag_var (rs_machine_dependent
, 4, 4,
7066 RELAX_ADD_NOP_IF_A0_B_RETW
,
7067 frag_now
->fr_symbol
,
7068 frag_now
->fr_offset
,
7070 xtensa_set_frag_assembly_state (frag_now
);
7071 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7072 frag_var (rs_machine_dependent
, 4, 4,
7073 RELAX_ADD_NOP_IF_A0_B_RETW
,
7074 frag_now
->fr_symbol
,
7075 frag_now
->fr_offset
,
7077 xtensa_set_frag_assembly_state (frag_now
);
7080 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7082 tinsn
= &vinsn
->slots
[slot
];
7084 /* See if the instruction implies an aligned section. */
7085 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7086 record_alignment (now_seg
, 2);
7088 /* Determine the best line number for debug info. */
7089 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7090 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7091 || tinsn
->debug_line
.line
< debug_line
.line
7092 || tinsn
->debug_line
.column
< debug_line
.column
))
7093 debug_line
= tinsn
->debug_line
;
7094 if (tinsn
->loc_directive_seen
)
7095 loc_directive_seen
= TRUE
;
7098 /* Special cases for instructions that force an alignment... */
7099 /* None of these opcodes are bundle-able. */
7100 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7104 /* Remember the symbol that marks the end of the loop in the frag
7105 that marks the start of the loop. This way we can easily find
7106 the end of the loop at the beginning, without adding special code
7107 to mark the loop instructions themselves. */
7108 symbolS
*target_sym
= NULL
;
7109 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7110 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7112 xtensa_set_frag_assembly_state (frag_now
);
7113 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7115 max_fill
= get_text_align_max_fill_size
7116 (get_text_align_power (xtensa_fetch_width
),
7117 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7119 if (use_transform ())
7120 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7121 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7123 frag_var (rs_machine_dependent
, 0, 0,
7124 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7125 xtensa_set_frag_assembly_state (frag_now
);
7128 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7129 && !vinsn
->slots
[0].is_specific_opcode
)
7131 xtensa_mark_literal_pool_location ();
7132 xtensa_move_labels (frag_now
, 0);
7133 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7136 if (vinsn
->num_slots
== 1)
7138 if (workaround_a0_b_retw
&& use_transform ())
7139 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7140 is_register_writer (&vinsn
->slots
[0], "a", 0));
7142 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7143 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7146 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7148 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7150 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7152 /* vinsn_to_insnbuf will produce the error. */
7153 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7155 f
= frag_more (insn_size
+ extra_space
);
7156 xtensa_set_frag_assembly_state (frag_now
);
7157 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7160 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7161 if (vinsn
->format
== XTENSA_UNDEFINED
)
7164 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7166 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7167 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7170 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7172 tinsn
= &vinsn
->slots
[slot
];
7173 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7174 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7175 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7176 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7177 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7179 frag_now
->tc_frag_data
.literal_frags
[slot
] =
7180 tinsn
->tok
[1].X_add_symbol
->sy_frag
;
7182 if (tinsn
->literal_space
!= 0)
7183 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7184 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7186 if (tinsn
->subtype
== RELAX_NARROW
)
7187 gas_assert (vinsn
->num_slots
== 1);
7188 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7190 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7193 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7194 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7198 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7199 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7203 frag_variant (rs_machine_dependent
,
7204 extra_space
, extra_space
, RELAX_SLOTS
,
7205 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7206 xtensa_set_frag_assembly_state (frag_now
);
7209 /* Special cases for loops:
7210 close_loop_end should be inserted AFTER short_loop.
7211 Make sure that CLOSE loops are processed BEFORE short_loops
7212 when converting them. */
7214 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7215 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7216 && !vinsn
->slots
[0].is_specific_opcode
)
7218 if (workaround_short_loop
&& use_transform ())
7220 maybe_has_short_loop
= TRUE
;
7221 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7222 frag_var (rs_machine_dependent
, 4, 4,
7223 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7224 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7225 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7226 frag_var (rs_machine_dependent
, 4, 4,
7227 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7228 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7231 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7232 loop at least 12 bytes away from another loop's end. */
7233 if (workaround_close_loop_end
&& use_transform ())
7235 maybe_has_close_loop_end
= TRUE
;
7236 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7237 frag_var (rs_machine_dependent
, 12, 12,
7238 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7239 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7243 if (use_transform ())
7247 gas_assert (finish_frag
);
7248 frag_var (rs_machine_dependent
,
7249 xtensa_fetch_width
, xtensa_fetch_width
,
7251 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7252 xtensa_set_frag_assembly_state (frag_now
);
7253 xtensa_maybe_create_trampoline_frag ();
7254 /* Always create one here. */
7255 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7257 else if (is_branch
&& do_align_targets ())
7259 gas_assert (finish_frag
);
7260 frag_var (rs_machine_dependent
,
7261 xtensa_fetch_width
, xtensa_fetch_width
,
7262 RELAX_MAYBE_UNREACHABLE
,
7263 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7264 xtensa_set_frag_assembly_state (frag_now
);
7265 frag_var (rs_machine_dependent
,
7267 RELAX_MAYBE_DESIRE_ALIGN
,
7268 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7269 xtensa_set_frag_assembly_state (frag_now
);
7273 /* Now, if the original opcode was a call... */
7274 if (do_align_targets ()
7275 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7277 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7278 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7279 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7280 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7281 xtensa_set_frag_assembly_state (frag_now
);
7284 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7286 frag_wane (frag_now
);
7288 xtensa_set_frag_assembly_state (frag_now
);
7293 /* xtensa_end and helper functions. */
7295 static void xtensa_cleanup_align_frags (void);
7296 static void xtensa_fix_target_frags (void);
7297 static void xtensa_mark_narrow_branches (void);
7298 static void xtensa_mark_zcl_first_insns (void);
7299 static void xtensa_mark_difference_of_two_symbols (void);
7300 static void xtensa_fix_a0_b_retw_frags (void);
7301 static void xtensa_fix_b_j_loop_end_frags (void);
7302 static void xtensa_fix_close_loop_end_frags (void);
7303 static void xtensa_fix_short_loop_frags (void);
7304 static void xtensa_sanity_check (void);
7305 static void xtensa_add_config_info (void);
7310 directive_balance ();
7311 xtensa_flush_pending_output ();
7313 past_xtensa_end
= TRUE
;
7315 xtensa_move_literals ();
7317 xtensa_reorder_segments ();
7318 xtensa_cleanup_align_frags ();
7319 xtensa_fix_target_frags ();
7320 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7321 xtensa_fix_a0_b_retw_frags ();
7322 if (workaround_b_j_loop_end
)
7323 xtensa_fix_b_j_loop_end_frags ();
7325 /* "close_loop_end" should be processed BEFORE "short_loop". */
7326 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7327 xtensa_fix_close_loop_end_frags ();
7329 if (workaround_short_loop
&& maybe_has_short_loop
)
7330 xtensa_fix_short_loop_frags ();
7332 xtensa_mark_narrow_branches ();
7333 xtensa_mark_zcl_first_insns ();
7335 xtensa_sanity_check ();
7337 xtensa_add_config_info ();
7339 xtensa_check_frag_count ();
7343 struct trampoline_frag
7345 struct trampoline_frag
*next
;
7346 bfd_boolean needs_jump_around
;
7351 struct trampoline_seg
7353 struct trampoline_seg
*next
;
7355 struct trampoline_frag trampoline_list
;
7358 static struct trampoline_seg trampoline_seg_list
;
7359 #define J_RANGE (128 * 1024)
7361 static int unreachable_count
= 0;
7365 xtensa_maybe_create_trampoline_frag (void)
7367 if (!use_trampolines
)
7370 /* We create an area for possible trampolines every 10 unreachable frags.
7371 These are preferred over the ones not preceded by an unreachable frag,
7372 because we don't have to jump around them. This function is called after
7373 each RELAX_UNREACHABLE frag is created. */
7375 if (++unreachable_count
> 10)
7377 xtensa_create_trampoline_frag (FALSE
);
7378 clear_frag_count ();
7379 unreachable_count
= 0;
7384 xtensa_check_frag_count (void)
7386 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7389 /* We create an area for possible trampolines every 8000 frags or so. This
7390 is an estimate based on the max range of a "j" insn (+/-128K) divided
7391 by a typical frag byte count (16), minus a few for safety. This function
7392 is called after each source line is processed. */
7394 if (get_frag_count () > 8000)
7396 xtensa_create_trampoline_frag (TRUE
);
7397 clear_frag_count ();
7398 unreachable_count
= 0;
7401 /* We create an area for a possible literal pool every N (default 5000)
7403 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7406 static xtensa_insnbuf trampoline_buf
= NULL
;
7407 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7409 static xtensa_insnbuf litpool_buf
= NULL
;
7410 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7412 #define TRAMPOLINE_FRAG_SIZE 3000
7415 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7417 /* Emit a frag where we can place intermediate jump instructions,
7418 in case we need to jump farther than 128K bytes.
7419 Each jump instruction takes three bytes.
7420 We allocate enough for 1000 trampolines in each frag.
7421 If that's not enough, oh well. */
7423 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7424 struct trampoline_frag
*tf
;
7427 int size
= TRAMPOLINE_FRAG_SIZE
;
7429 for ( ; ts
; ts
= ts
->next
)
7431 if (ts
->seg
== now_seg
)
7437 ts
= XCNEW(struct trampoline_seg
);
7438 ts
->next
= trampoline_seg_list
.next
;
7439 trampoline_seg_list
.next
= ts
;
7443 frag_wane (frag_now
);
7445 xtensa_set_frag_assembly_state (frag_now
);
7446 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7447 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7448 if (trampoline_buf
== NULL
)
7450 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7451 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7453 tf
= XNEW (struct trampoline_frag
);
7454 tf
->next
= ts
->trampoline_list
.next
;
7455 ts
->trampoline_list
.next
= tf
;
7456 tf
->needs_jump_around
= needs_jump_around
;
7462 static struct trampoline_seg
*
7463 find_trampoline_seg (asection
*seg
)
7465 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7467 for ( ; ts
; ts
= ts
->next
)
7477 void dump_trampolines (void);
7480 dump_trampolines (void)
7482 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7484 for ( ; ts
; ts
= ts
->next
)
7486 asection
*seg
= ts
->seg
;
7490 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7491 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7492 for ( ; tf
; tf
= tf
->next
)
7494 if (tf
->fragP
== NULL
)
7496 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7497 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7498 tf
->needs_jump_around
? "T" : "F");
7503 static void dump_litpools (void) __attribute__ ((unused
));
7506 dump_litpools (void)
7508 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7509 struct litpool_frag
*lpf
;
7511 for ( ; lps
; lps
= lps
->next
)
7513 printf("litpool seg %s\n", lps
->seg
->name
);
7514 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7516 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7518 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7520 if (litfrag
->fr_fix
== 4)
7522 litfrag
= litfrag
->fr_next
;
7524 printf(" %ld <%d:%d> (%d) [%d]: ",
7525 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7526 lpf
->fragP
->fr_line
, count
);
7527 //dump_frag(lpf->fragP);
7533 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7534 bfd_boolean only_if_needed
)
7536 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7538 struct litpool_frag
*lpf
;
7539 bfd_boolean needed
= FALSE
;
7541 if (use_literal_section
|| !auto_litpools
)
7544 for ( ; lps
; lps
= lps
->next
)
7546 if (lps
->seg
== now_seg
)
7552 lps
= XCNEW (struct litpool_seg
);
7553 lps
->next
= litpool_seg_list
.next
;
7554 litpool_seg_list
.next
= lps
;
7556 lps
->frag_list
.next
= &lps
->frag_list
;
7557 lps
->frag_list
.prev
= &lps
->frag_list
;
7566 if (past_xtensa_end
|| !use_transform() ||
7567 frag_now
->tc_frag_data
.is_no_transform
)
7571 if (auto_litpool_limit
<= 0)
7573 /* Don't create a litpool based only on frag count. */
7576 else if (lps
->frag_count
> auto_litpool_limit
)
7593 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7594 /* Create a potential site for a literal pool. */
7595 frag_wane (frag_now
);
7597 xtensa_set_frag_assembly_state (frag_now
);
7599 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7600 fragP
->tc_frag_data
.literal_frag
= fragP
;
7601 frag_var (rs_machine_dependent
, size
, size
,
7603 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7604 RELAX_LITERAL_POOL_BEGIN
,
7606 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7607 frag_variant (rs_machine_dependent
, 0, 0,
7608 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7609 xtensa_set_frag_assembly_state (frag_now
);
7613 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7614 just record it here. */
7618 lpf
= XNEW (struct litpool_frag
);
7619 /* Insert at tail of circular list. */
7621 lps
->frag_list
.prev
->next
= lpf
;
7622 lpf
->next
= &lps
->frag_list
;
7623 lpf
->prev
= lps
->frag_list
.prev
;
7624 lps
->frag_list
.prev
= lpf
;
7626 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7627 lpf
->original_priority
= lpf
->priority
;
7629 lps
->frag_count
= 0;
7633 xtensa_cleanup_align_frags (void)
7638 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7639 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7642 /* Walk over all of the fragments in a subsection. */
7643 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7645 if ((fragP
->fr_type
== rs_align
7646 || fragP
->fr_type
== rs_align_code
7647 || (fragP
->fr_type
== rs_machine_dependent
7648 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7649 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7650 && fragP
->fr_fix
== 0)
7652 fragS
*next
= fragP
->fr_next
;
7655 && next
->fr_fix
== 0
7656 && next
->fr_type
== rs_machine_dependent
7657 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7660 next
= next
->fr_next
;
7663 /* If we don't widen branch targets, then they
7664 will be easier to align. */
7665 if (fragP
->tc_frag_data
.is_branch_target
7666 && fragP
->fr_opcode
== fragP
->fr_literal
7667 && fragP
->fr_type
== rs_machine_dependent
7668 && fragP
->fr_subtype
== RELAX_SLOTS
7669 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7671 if (fragP
->fr_type
== rs_machine_dependent
7672 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7673 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7679 /* Re-process all of the fragments looking to convert all of the
7680 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7681 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7682 Otherwise, convert to a .fill 0. */
7685 xtensa_fix_target_frags (void)
7690 /* When this routine is called, all of the subsections are still intact
7691 so we walk over subsections instead of sections. */
7692 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7693 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7697 /* Walk over all of the fragments in a subsection. */
7698 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7700 if (fragP
->fr_type
== rs_machine_dependent
7701 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7703 if (next_frag_is_branch_target (fragP
))
7704 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7713 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7716 xtensa_mark_narrow_branches (void)
7721 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7722 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7725 /* Walk over all of the fragments in a subsection. */
7726 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7728 if (fragP
->fr_type
== rs_machine_dependent
7729 && fragP
->fr_subtype
== RELAX_SLOTS
7730 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7734 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7735 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7737 if (vinsn
.num_slots
== 1
7738 && xtensa_opcode_is_branch (xtensa_default_isa
,
7739 vinsn
.slots
[0].opcode
) == 1
7740 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7741 && is_narrow_branch_guaranteed_in_range (fragP
,
7744 fragP
->fr_subtype
= RELAX_SLOTS
;
7745 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7746 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7754 /* A branch is typically widened only when its target is out of
7755 range. However, we would like to widen them to align a subsequent
7756 branch target when possible.
7758 Because the branch relaxation code is so convoluted, the optimal solution
7759 (combining the two cases) is difficult to get right in all circumstances.
7760 We therefore go with an "almost as good" solution, where we only
7761 use for alignment narrow branches that definitely will not expand to a
7762 jump and a branch. These functions find and mark these cases. */
7764 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7765 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7766 We start counting beginning with the frag after the 2-byte branch, so the
7767 maximum offset is (4 - 2) + 63 = 65. */
7768 #define MAX_IMMED6 65
7770 static offsetT
unrelaxed_frag_max_size (fragS
*);
7773 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7775 const expressionS
*exp
= &tinsn
->tok
[1];
7776 symbolS
*symbolP
= exp
->X_add_symbol
;
7777 offsetT max_distance
= exp
->X_add_number
;
7780 if (exp
->X_op
!= O_symbol
)
7783 target_frag
= symbol_get_frag (symbolP
);
7785 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7786 if (is_branch_jmp_to_next (tinsn
, fragP
))
7789 /* The branch doesn't branch over it's own frag,
7790 but over the subsequent ones. */
7791 fragP
= fragP
->fr_next
;
7792 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7794 max_distance
+= unrelaxed_frag_max_size (fragP
);
7795 fragP
= fragP
->fr_next
;
7797 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7804 xtensa_mark_zcl_first_insns (void)
7809 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7810 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7813 /* Walk over all of the fragments in a subsection. */
7814 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7816 if (fragP
->fr_type
== rs_machine_dependent
7817 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7818 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7820 /* Find the loop frag. */
7821 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7822 /* Find the first insn frag. */
7823 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7825 /* Handle a corner case that comes up in hardware
7826 diagnostics. The original assembly looks like this:
7829 <empty_frag>--not found by next_non_empty_frag
7832 Depending on the start address, the assembler may or
7833 may not change it to look something like this:
7836 nop--frag isn't empty anymore
7839 So set up to check the alignment of the nop if it
7841 while (loop_frag
!= targ_frag
)
7843 if (loop_frag
->fr_type
== rs_machine_dependent
7844 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7845 || loop_frag
->fr_subtype
7846 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7847 targ_frag
= loop_frag
;
7849 loop_frag
= loop_frag
->fr_next
;
7852 /* Of course, sometimes (mostly for toy test cases) a
7853 zero-cost loop instruction is the last in a section. */
7856 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7857 /* Do not widen a frag that is the first instruction of a
7858 zero-cost loop. It makes that loop harder to align. */
7859 if (targ_frag
->fr_type
== rs_machine_dependent
7860 && targ_frag
->fr_subtype
== RELAX_SLOTS
7861 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7864 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7865 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7868 frag_wane (targ_frag
);
7869 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7873 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7881 /* When a difference-of-symbols expression is encoded as a uleb128 or
7882 sleb128 value, the linker is unable to adjust that value to account for
7883 link-time relaxation. Mark all the code between such symbols so that
7884 its size cannot be changed by linker relaxation. */
7887 xtensa_mark_difference_of_two_symbols (void)
7891 for (expr_sym
= expr_symbols
; expr_sym
;
7892 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7894 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7896 if (exp
->X_op
== O_subtract
)
7898 symbolS
*left
= exp
->X_add_symbol
;
7899 symbolS
*right
= exp
->X_op_symbol
;
7901 /* Difference of two symbols not in the same section
7902 are handled with relocations in the linker. */
7903 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7909 if (symbol_get_frag (left
)->fr_address
7910 <= symbol_get_frag (right
)->fr_address
)
7912 start
= symbol_get_frag (left
);
7913 end
= symbol_get_frag (right
);
7917 start
= symbol_get_frag (right
);
7918 end
= symbol_get_frag (left
);
7921 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7922 walk
= start
->tc_frag_data
.no_transform_end
;
7927 walk
->tc_frag_data
.is_no_transform
= 1;
7928 walk
= walk
->fr_next
;
7930 while (walk
&& walk
->fr_address
< end
->fr_address
);
7932 start
->tc_frag_data
.no_transform_end
= walk
;
7939 /* Re-process all of the fragments looking to convert all of the
7940 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7941 conditional branch or a retw/retw.n, convert this frag to one that
7942 will generate a NOP. In any case close it off with a .fill 0. */
7944 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7947 xtensa_fix_a0_b_retw_frags (void)
7952 /* When this routine is called, all of the subsections are still intact
7953 so we walk over subsections instead of sections. */
7954 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7955 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7959 /* Walk over all of the fragments in a subsection. */
7960 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7962 if (fragP
->fr_type
== rs_machine_dependent
7963 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7965 if (next_instrs_are_b_retw (fragP
))
7967 if (fragP
->tc_frag_data
.is_no_transform
)
7968 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7970 relax_frag_add_nop (fragP
);
7980 next_instrs_are_b_retw (fragS
*fragP
)
7982 xtensa_opcode opcode
;
7984 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7985 static xtensa_insnbuf insnbuf
= NULL
;
7986 static xtensa_insnbuf slotbuf
= NULL
;
7987 xtensa_isa isa
= xtensa_default_isa
;
7990 bfd_boolean branch_seen
= FALSE
;
7994 insnbuf
= xtensa_insnbuf_alloc (isa
);
7995 slotbuf
= xtensa_insnbuf_alloc (isa
);
7998 if (next_fragP
== NULL
)
8001 /* Check for the conditional branch. */
8002 xtensa_insnbuf_from_chars
8003 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8004 fmt
= xtensa_format_decode (isa
, insnbuf
);
8005 if (fmt
== XTENSA_UNDEFINED
)
8008 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8010 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8011 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8013 branch_seen
= (branch_seen
8014 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8020 offset
+= xtensa_format_length (isa
, fmt
);
8021 if (offset
== next_fragP
->fr_fix
)
8023 next_fragP
= next_non_empty_frag (next_fragP
);
8027 if (next_fragP
== NULL
)
8030 /* Check for the retw/retw.n. */
8031 xtensa_insnbuf_from_chars
8032 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8033 fmt
= xtensa_format_decode (isa
, insnbuf
);
8035 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8036 have no problems. */
8037 if (fmt
== XTENSA_UNDEFINED
8038 || xtensa_format_num_slots (isa
, fmt
) != 1)
8041 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8042 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8044 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8051 /* Re-process all of the fragments looking to convert all of the
8052 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8053 loop end label, convert this frag to one that will generate a NOP.
8054 In any case close it off with a .fill 0. */
8056 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8059 xtensa_fix_b_j_loop_end_frags (void)
8064 /* When this routine is called, all of the subsections are still intact
8065 so we walk over subsections instead of sections. */
8066 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8067 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8071 /* Walk over all of the fragments in a subsection. */
8072 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8074 if (fragP
->fr_type
== rs_machine_dependent
8075 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8077 if (next_instr_is_loop_end (fragP
))
8079 if (fragP
->tc_frag_data
.is_no_transform
)
8080 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8082 relax_frag_add_nop (fragP
);
8092 next_instr_is_loop_end (fragS
*fragP
)
8094 const fragS
*next_fragP
;
8096 if (next_frag_is_loop_target (fragP
))
8099 next_fragP
= next_non_empty_frag (fragP
);
8100 if (next_fragP
== NULL
)
8103 if (!next_frag_is_loop_target (next_fragP
))
8106 /* If the size is >= 3 then there is more than one instruction here.
8107 The hardware bug will not fire. */
8108 if (next_fragP
->fr_fix
> 3)
8115 /* Re-process all of the fragments looking to convert all of the
8116 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8117 not MY loop's loop end within 12 bytes, add enough nops here to
8118 make it at least 12 bytes away. In any case close it off with a
8121 static offsetT min_bytes_to_other_loop_end
8122 (fragS
*, fragS
*, offsetT
);
8125 xtensa_fix_close_loop_end_frags (void)
8130 /* When this routine is called, all of the subsections are still intact
8131 so we walk over subsections instead of sections. */
8132 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8133 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8137 fragS
*current_target
= NULL
;
8139 /* Walk over all of the fragments in a subsection. */
8140 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8142 if (fragP
->fr_type
== rs_machine_dependent
8143 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8144 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8145 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8148 && fragP
->fr_type
== rs_machine_dependent
8149 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8152 int bytes_added
= 0;
8154 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8155 /* Max out at 12. */
8156 min_bytes
= min_bytes_to_other_loop_end
8157 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8159 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8161 if (fragP
->tc_frag_data
.is_no_transform
)
8162 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8165 while (min_bytes
+ bytes_added
8166 < REQUIRED_LOOP_DIVIDING_BYTES
)
8170 if (fragP
->fr_var
< length
)
8171 as_fatal (_("fr_var %lu < length %d"),
8172 (long) fragP
->fr_var
, length
);
8175 assemble_nop (length
,
8176 fragP
->fr_literal
+ fragP
->fr_fix
);
8177 fragP
->fr_fix
+= length
;
8178 fragP
->fr_var
-= length
;
8180 bytes_added
+= length
;
8186 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8187 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8193 static offsetT
unrelaxed_frag_min_size (fragS
*);
8196 min_bytes_to_other_loop_end (fragS
*fragP
,
8197 fragS
*current_target
,
8201 fragS
*current_fragP
;
8203 for (current_fragP
= fragP
;
8205 current_fragP
= current_fragP
->fr_next
)
8207 if (current_fragP
->tc_frag_data
.is_loop_target
8208 && current_fragP
!= current_target
)
8211 offset
+= unrelaxed_frag_min_size (current_fragP
);
8213 if (offset
>= max_size
)
8221 unrelaxed_frag_min_size (fragS
*fragP
)
8223 offsetT size
= fragP
->fr_fix
;
8225 /* Add fill size. */
8226 if (fragP
->fr_type
== rs_fill
)
8227 size
+= fragP
->fr_offset
;
8234 unrelaxed_frag_max_size (fragS
*fragP
)
8236 offsetT size
= fragP
->fr_fix
;
8237 switch (fragP
->fr_type
)
8240 /* Empty frags created by the obstack allocation scheme
8241 end up with type 0. */
8246 size
+= fragP
->fr_offset
;
8254 /* No further adjustments needed. */
8256 case rs_machine_dependent
:
8257 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8258 size
+= fragP
->fr_var
;
8261 /* We had darn well better know how big it is. */
8270 /* Re-process all of the fragments looking to convert all
8271 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8274 1) the instruction size count to the loop end label
8275 is too short (<= 2 instructions),
8276 2) loop has a jump or branch in it
8279 1) workaround_all_short_loops is TRUE
8280 2) The generating loop was a 'loopgtz' or 'loopnez'
8281 3) the instruction size count to the loop end label is too short
8283 then convert this frag (and maybe the next one) to generate a NOP.
8284 In any case close it off with a .fill 0. */
8286 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8287 static bfd_boolean
branch_before_loop_end (fragS
*);
8290 xtensa_fix_short_loop_frags (void)
8295 /* When this routine is called, all of the subsections are still intact
8296 so we walk over subsections instead of sections. */
8297 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8298 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8301 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8303 /* Walk over all of the fragments in a subsection. */
8304 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8306 if (fragP
->fr_type
== rs_machine_dependent
8307 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8308 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8311 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8312 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8313 current_opcode
= t_insn
.opcode
;
8314 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8315 current_opcode
) == 1);
8318 if (fragP
->fr_type
== rs_machine_dependent
8319 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8321 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8322 && (branch_before_loop_end (fragP
->fr_next
)
8323 || (workaround_all_short_loops
8324 && current_opcode
!= XTENSA_UNDEFINED
8325 && current_opcode
!= xtensa_loop_opcode
)))
8327 if (fragP
->tc_frag_data
.is_no_transform
)
8328 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8330 relax_frag_add_nop (fragP
);
8339 static int unrelaxed_frag_min_insn_count (fragS
*);
8342 count_insns_to_loop_end (fragS
*base_fragP
,
8343 bfd_boolean count_relax_add
,
8346 fragS
*fragP
= NULL
;
8351 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8353 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8354 if (insn_count
>= max_count
)
8357 if (count_relax_add
)
8359 if (fragP
->fr_type
== rs_machine_dependent
8360 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8362 /* In order to add the appropriate number of
8363 NOPs, we count an instruction for downstream
8366 if (insn_count
>= max_count
)
8376 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8378 xtensa_isa isa
= xtensa_default_isa
;
8379 static xtensa_insnbuf insnbuf
= NULL
;
8383 if (!fragP
->tc_frag_data
.is_insn
)
8387 insnbuf
= xtensa_insnbuf_alloc (isa
);
8389 /* Decode the fixed instructions. */
8390 while (offset
< fragP
->fr_fix
)
8394 xtensa_insnbuf_from_chars
8395 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8396 fmt
= xtensa_format_decode (isa
, insnbuf
);
8398 if (fmt
== XTENSA_UNDEFINED
)
8400 as_fatal (_("undecodable instruction in instruction frag"));
8403 offset
+= xtensa_format_length (isa
, fmt
);
8411 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8414 branch_before_loop_end (fragS
*base_fragP
)
8418 for (fragP
= base_fragP
;
8419 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8420 fragP
= fragP
->fr_next
)
8422 if (unrelaxed_frag_has_b_j (fragP
))
8430 unrelaxed_frag_has_b_j (fragS
*fragP
)
8432 static xtensa_insnbuf insnbuf
= NULL
;
8433 xtensa_isa isa
= xtensa_default_isa
;
8436 if (!fragP
->tc_frag_data
.is_insn
)
8440 insnbuf
= xtensa_insnbuf_alloc (isa
);
8442 /* Decode the fixed instructions. */
8443 while (offset
< fragP
->fr_fix
)
8448 xtensa_insnbuf_from_chars
8449 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8450 fmt
= xtensa_format_decode (isa
, insnbuf
);
8451 if (fmt
== XTENSA_UNDEFINED
)
8454 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8456 xtensa_opcode opcode
=
8457 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8458 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8459 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8462 offset
+= xtensa_format_length (isa
, fmt
);
8468 /* Checks to be made after initial assembly but before relaxation. */
8470 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8471 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8474 xtensa_sanity_check (void)
8476 const char *file_name
;
8481 file_name
= as_where (&line
);
8482 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8483 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8487 /* Walk over all of the fragments in a subsection. */
8488 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8490 if (fragP
->fr_type
== rs_machine_dependent
8491 && fragP
->fr_subtype
== RELAX_SLOTS
8492 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8494 static xtensa_insnbuf insnbuf
= NULL
;
8497 if (fragP
->fr_opcode
!= NULL
)
8500 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8501 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8502 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8504 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8505 t_insn
.opcode
) == 1)
8507 if (is_empty_loop (&t_insn
, fragP
))
8509 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8510 as_bad (_("invalid empty loop"));
8512 if (!is_local_forward_loop (&t_insn
, fragP
))
8514 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8515 as_bad (_("loop target does not follow "
8516 "loop instruction in section"));
8523 new_logical_line (file_name
, line
);
8527 #define LOOP_IMMED_OPN 1
8529 /* Return TRUE if the loop target is the next non-zero fragment. */
8532 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8534 const expressionS
*exp
;
8538 if (insn
->insn_type
!= ITYPE_INSN
)
8541 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8544 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8547 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8549 if (exp
->X_op
!= O_symbol
)
8552 symbolP
= exp
->X_add_symbol
;
8556 if (symbol_get_frag (symbolP
) == NULL
)
8559 if (S_GET_VALUE (symbolP
) != 0)
8562 /* Walk through the zero-size fragments from this one. If we find
8563 the target fragment, then this is a zero-size loop. */
8565 for (next_fragP
= fragP
->fr_next
;
8567 next_fragP
= next_fragP
->fr_next
)
8569 if (next_fragP
== symbol_get_frag (symbolP
))
8571 if (next_fragP
->fr_fix
!= 0)
8579 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8581 const expressionS
*exp
;
8585 if (insn
->insn_type
!= ITYPE_INSN
)
8588 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8591 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8594 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8596 if (exp
->X_op
!= O_symbol
)
8599 symbolP
= exp
->X_add_symbol
;
8603 if (symbol_get_frag (symbolP
) == NULL
)
8606 /* Walk through fragments until we find the target.
8607 If we do not find the target, then this is an invalid loop. */
8609 for (next_fragP
= fragP
->fr_next
;
8611 next_fragP
= next_fragP
->fr_next
)
8613 if (next_fragP
== symbol_get_frag (symbolP
))
8621 #define XTINFO_NAME "Xtensa_Info"
8622 #define XTINFO_NAMESZ 12
8623 #define XTINFO_TYPE 1
8626 xtensa_add_config_info (void)
8632 info_sec
= subseg_new (".xtensa.info", 0);
8633 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8635 data
= XNEWVEC (char, 100);
8636 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8637 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8638 sz
= strlen (data
) + 1;
8640 /* Add enough null terminators to pad to a word boundary. */
8643 while ((sz
& 3) != 0);
8645 /* Follow the standard note section layout:
8646 First write the length of the name string. */
8648 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8650 /* Next comes the length of the "descriptor", i.e., the actual data. */
8652 md_number_to_chars (p
, (valueT
) sz
, 4);
8654 /* Write the note type. */
8656 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8658 /* Write the name field. */
8659 p
= frag_more (XTINFO_NAMESZ
);
8660 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8662 /* Finally, write the descriptor. */
8664 memcpy (p
, data
, sz
);
8670 /* Alignment Functions. */
8673 get_text_align_power (unsigned target_size
)
8675 if (target_size
<= 4)
8678 if (target_size
<= 8)
8681 if (target_size
<= 16)
8684 if (target_size
<= 32)
8687 if (target_size
<= 64)
8690 if (target_size
<= 128)
8693 if (target_size
<= 256)
8696 if (target_size
<= 512)
8699 if (target_size
<= 1024)
8708 get_text_align_max_fill_size (int align_pow
,
8709 bfd_boolean use_nops
,
8710 bfd_boolean use_no_density
)
8713 return (1 << align_pow
);
8715 return 3 * (1 << align_pow
);
8717 return 1 + (1 << align_pow
);
8721 /* Calculate the minimum bytes of fill needed at "address" to align a
8722 target instruction of size "target_size" so that it does not cross a
8723 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8724 the fill can be an arbitrary number of bytes. Otherwise, the space must
8725 be filled by NOP instructions. */
8728 get_text_align_fill_size (addressT address
,
8731 bfd_boolean use_nops
,
8732 bfd_boolean use_no_density
)
8734 addressT alignment
, fill
, fill_limit
, fill_step
;
8735 bfd_boolean skip_one
= FALSE
;
8737 alignment
= (1 << align_pow
);
8738 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8742 fill_limit
= alignment
;
8745 else if (!use_no_density
)
8747 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8748 fill_limit
= alignment
* 2;
8754 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8755 fill_limit
= alignment
* 3;
8759 /* Try all fill sizes until finding one that works. */
8760 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8762 if (skip_one
&& fill
== 1)
8764 if ((address
+ fill
) >> align_pow
8765 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8774 branch_align_power (segT sec
)
8776 /* If the Xtensa processor has a fetch width of X, and
8777 the section is aligned to at least that boundary, then a branch
8778 target need only fit within that aligned block of memory to avoid
8779 a stall. Otherwise, try to fit branch targets within 4-byte
8780 aligned blocks (which may be insufficient, e.g., if the section
8781 has no alignment, but it's good enough). */
8782 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8783 int sec_align
= get_recorded_alignment (sec
);
8785 if (sec_align
>= fetch_align
)
8792 /* This will assert if it is not possible. */
8795 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8801 gas_assert (fill_size
% 3 == 0);
8802 return (fill_size
/ 3);
8805 gas_assert (fill_size
!= 1); /* Bad argument. */
8807 while (fill_size
> 1)
8810 if (fill_size
== 2 || fill_size
== 4)
8812 fill_size
-= insn_size
;
8815 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8821 get_text_align_nth_nop_size (offsetT fill_size
,
8823 bfd_boolean use_no_density
)
8830 gas_assert (fill_size
!= 1); /* Bad argument. */
8832 while (fill_size
> 1)
8835 if (fill_size
== 2 || fill_size
== 4)
8837 fill_size
-= insn_size
;
8847 /* For the given fragment, find the appropriate address
8848 for it to begin at if we are using NOPs to align it. */
8851 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8853 /* The rule is: get next fragment's FIRST instruction. Find
8854 the smallest number of bytes that need to be added to
8855 ensure that the next fragment's FIRST instruction will fit
8858 E.G., 2 bytes : 0, 1, 2 mod 4
8861 If the FIRST instruction MIGHT be relaxed,
8862 assume that it will become a 3-byte instruction.
8864 Note again here that LOOP instructions are not bundleable,
8865 and this relaxation only applies to LOOP opcodes. */
8868 int first_insn_size
;
8870 addressT pre_opcode_bytes
;
8873 xtensa_opcode opcode
;
8874 bfd_boolean is_loop
;
8876 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8877 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8879 /* Find the loop frag. */
8880 first_insn
= next_non_empty_frag (fragP
);
8881 /* Now find the first insn frag. */
8882 first_insn
= next_non_empty_frag (first_insn
);
8884 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8885 gas_assert (is_loop
);
8886 loop_insn_size
= xg_get_single_size (opcode
);
8888 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8889 pre_opcode_bytes
+= loop_insn_size
;
8891 /* For loops, the alignment depends on the size of the
8892 instruction following the loop, not the LOOP instruction. */
8894 if (first_insn
== NULL
)
8895 first_insn_size
= xtensa_fetch_width
;
8897 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8899 /* If it was 8, then we'll need a larger alignment for the section. */
8900 align_power
= get_text_align_power (first_insn_size
);
8901 record_alignment (now_seg
, align_power
);
8903 fill_size
= get_text_align_fill_size
8904 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8905 fragP
->tc_frag_data
.is_no_density
);
8907 return address
+ fill_size
;
8911 /* 3 mechanisms for relaxing an alignment:
8913 Align to a power of 2.
8914 Align so the next fragment's instruction does not cross a word boundary.
8915 Align the current instruction so that if the next instruction
8916 were 3 bytes, it would not cross a word boundary.
8920 zeros - This is easy; always insert zeros.
8921 nops - 3-byte and 2-byte instructions
8925 >=5 : 3-byte instruction + fn (n-3)
8926 widening - widen previous instructions. */
8929 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8931 addressT target_address
, loop_insn_offset
;
8933 xtensa_opcode loop_opcode
;
8934 bfd_boolean is_loop
;
8937 offsetT branch_align
;
8940 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8941 switch (fragP
->fr_subtype
)
8943 case RELAX_DESIRE_ALIGN
:
8944 target_size
= next_frag_format_size (fragP
);
8945 if (target_size
== XTENSA_UNDEFINED
)
8947 align_power
= branch_align_power (now_seg
);
8948 branch_align
= 1 << align_power
;
8949 /* Don't count on the section alignment being as large as the target. */
8950 if (target_size
> branch_align
)
8951 target_size
= branch_align
;
8952 opt_diff
= get_text_align_fill_size (address
, align_power
,
8953 target_size
, FALSE
, FALSE
);
8955 *max_diff
= (opt_diff
+ branch_align
8956 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8957 gas_assert (*max_diff
>= opt_diff
);
8960 case RELAX_ALIGN_NEXT_OPCODE
:
8961 /* The next non-empty frag after this one holds the LOOP instruction
8962 that needs to be aligned. The required alignment depends on the
8963 size of the next non-empty frag after the loop frag, i.e., the
8964 first instruction in the loop. */
8965 loop_frag
= next_non_empty_frag (fragP
);
8966 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8967 loop_insn_offset
= 0;
8968 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8969 gas_assert (is_loop
);
8971 /* If the loop has been expanded then the LOOP instruction
8972 could be at an offset from this fragment. */
8973 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8974 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8976 /* In an ideal world, which is what we are shooting for here,
8977 we wouldn't need to use any NOPs immediately prior to the
8978 LOOP instruction. If this approach fails, relax_frag_loop_align
8979 will call get_noop_aligned_address. */
8981 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8982 align_power
= get_text_align_power (target_size
);
8983 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8984 target_size
, FALSE
, FALSE
);
8986 *max_diff
= xtensa_fetch_width
8987 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8988 - target_size
+ opt_diff
;
8989 gas_assert (*max_diff
>= opt_diff
);
9000 /* md_relax_frag Hook and Helper Functions. */
9002 static long relax_frag_loop_align (fragS
*, long);
9003 static long relax_frag_for_align (fragS
*, long);
9004 static long relax_frag_immed
9005 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9007 typedef struct cached_fixup cached_fixupS
;
9016 typedef struct fixup_cache fixup_cacheS
;
9019 cached_fixupS
*fixups
;
9027 static int fixup_order (const void *a
, const void *b
)
9029 const cached_fixupS
*pa
= a
;
9030 const cached_fixupS
*pb
= b
;
9032 if (pa
->addr
== pb
->addr
)
9034 if (pa
->target
== pb
->target
)
9036 if (pa
->fixP
->fx_r_type
== pb
->fixP
->fx_r_type
)
9038 return pa
->fixP
->fx_r_type
< pb
->fixP
->fx_r_type
? -1 : 1;
9040 return pa
->target
- pb
->target
;
9042 return pa
->addr
- pb
->addr
;
9045 static bfd_boolean
xtensa_make_cached_fixup (cached_fixupS
*o
, fixS
*fixP
)
9047 xtensa_isa isa
= xtensa_default_isa
;
9048 int addr
= fixP
->fx_frag
->fr_address
;
9051 symbolS
*s
= fixP
->fx_addsy
;
9054 xtensa_opcode opcode
;
9056 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9057 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9059 target
= S_GET_VALUE (s
);
9060 delta
= target
- addr
;
9062 if (abs(delta
) < J_RANGE
/ 2)
9065 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9066 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9068 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9069 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9070 slot
= fixP
->tc_fix_data
.slot
;
9071 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9072 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9073 if (opcode
!= xtensa_j_opcode
)
9084 static void xtensa_realloc_fixup_cache (fixup_cacheS
*cache
, unsigned add
)
9086 if (cache
->n_fixups
+ add
> cache
->n_max
)
9088 cache
->n_max
= (cache
->n_fixups
+ add
) * 2;
9089 cache
->fixups
= XRESIZEVEC (cached_fixupS
, cache
->fixups
, cache
->n_max
);
9093 static void xtensa_cache_relaxable_fixups (fixup_cacheS
*cache
,
9094 segment_info_type
*seginfo
)
9098 cache
->n_fixups
= 0;
9100 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
9102 xtensa_realloc_fixup_cache (cache
, 1);
9104 if (xtensa_make_cached_fixup (cache
->fixups
+ cache
->n_fixups
, fixP
))
9107 qsort (cache
->fixups
, cache
->n_fixups
, sizeof (*cache
->fixups
), fixup_order
);
9110 static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS
*cache
,
9114 unsigned b
= cache
->n_fixups
;
9118 unsigned c
= (a
+ b
) / 2;
9120 if (cache
->fixups
[c
].addr
< addr
)
9128 static void xtensa_delete_cached_fixup (fixup_cacheS
*cache
, unsigned i
)
9130 memmove (cache
->fixups
+ i
, cache
->fixups
+ i
+ 1,
9131 (cache
->n_fixups
- i
- 1) * sizeof (*cache
->fixups
));
9135 static bfd_boolean
xtensa_add_cached_fixup (fixup_cacheS
*cache
, fixS
*fixP
)
9140 if (!xtensa_make_cached_fixup (&o
, fixP
))
9142 xtensa_realloc_fixup_cache (cache
, 1);
9143 i
= xtensa_find_first_cached_fixup (cache
, o
.addr
);
9144 if (i
< cache
->n_fixups
)
9147 memmove (cache
->fixups
+ i
+ 1, cache
->fixups
+ i
,
9148 (cache
->n_fixups
- i
) * sizeof (*cache
->fixups
));
9150 cache
->fixups
[i
] = o
;
9155 /* Return the number of bytes added to this fragment, given that the
9156 input has been stretched already by "stretch". */
9159 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9161 xtensa_isa isa
= xtensa_default_isa
;
9162 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9163 long new_stretch
= 0;
9164 const char *file_name
;
9167 static xtensa_insnbuf vbuf
= NULL
;
9168 int slot
, num_slots
;
9171 file_name
= as_where (&line
);
9172 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9174 fragP
->tc_frag_data
.unreported_expansion
= 0;
9176 switch (fragP
->fr_subtype
)
9178 case RELAX_ALIGN_NEXT_OPCODE
:
9179 /* Always convert. */
9180 if (fragP
->tc_frag_data
.relax_seen
)
9181 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9184 case RELAX_LOOP_END
:
9188 case RELAX_LOOP_END_ADD_NOP
:
9189 /* Add a NOP and switch to .fill 0. */
9190 new_stretch
= relax_frag_add_nop (fragP
);
9194 case RELAX_DESIRE_ALIGN
:
9195 /* Do nothing. The narrowing before this frag will either align
9200 case RELAX_LITERAL_FINAL
:
9203 case RELAX_LITERAL_NR
:
9205 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9206 gas_assert (unreported
== lit_size
);
9207 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9208 fragP
->fr_var
-= lit_size
;
9209 fragP
->fr_fix
+= lit_size
;
9215 vbuf
= xtensa_insnbuf_alloc (isa
);
9217 xtensa_insnbuf_from_chars
9218 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9219 fmt
= xtensa_format_decode (isa
, vbuf
);
9220 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9222 for (slot
= 0; slot
< num_slots
; slot
++)
9224 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9227 if (fragP
->tc_frag_data
.relax_seen
)
9228 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9232 case RELAX_IMMED_STEP1
:
9233 case RELAX_IMMED_STEP2
:
9234 case RELAX_IMMED_STEP3
:
9235 /* Place the immediate. */
9236 new_stretch
+= relax_frag_immed
9237 (now_seg
, fragP
, stretch
,
9238 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9239 fmt
, slot
, stretched_p
, FALSE
);
9243 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9249 case RELAX_LITERAL_POOL_BEGIN
:
9250 if (fragP
->fr_var
!= 0)
9252 /* We have a converted "candidate" literal pool;
9253 assemble a jump around it. */
9255 if (!litpool_slotbuf
)
9257 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9258 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9261 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9262 fragP
->tc_frag_data
.is_insn
= TRUE
;
9264 insn
.insn_type
= ITYPE_INSN
;
9265 insn
.opcode
= xtensa_j_opcode
;
9267 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9269 fmt
= xg_get_single_format (xtensa_j_opcode
);
9270 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9271 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9272 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9273 (unsigned char *)fragP
->fr_literal
+
9278 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9279 BFD_RELOC_XTENSA_SLOT0_OP
);
9283 case RELAX_LITERAL_POOL_END
:
9284 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9285 case RELAX_MAYBE_UNREACHABLE
:
9286 case RELAX_MAYBE_DESIRE_ALIGN
:
9287 /* No relaxation required. */
9290 case RELAX_FILL_NOP
:
9291 case RELAX_UNREACHABLE
:
9292 if (fragP
->tc_frag_data
.relax_seen
)
9293 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9296 case RELAX_TRAMPOLINE
:
9297 if (fragP
->tc_frag_data
.relax_seen
)
9299 static fixup_cacheS fixup_cache
;
9300 segment_info_type
*seginfo
= seg_info (now_seg
);
9301 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9302 int searchaddr
= trampaddr
< J_RANGE
? 0 : trampaddr
- J_RANGE
;
9305 if (now_seg
!= fixup_cache
.seg
||
9306 fragP
== fixup_cache
.first_frag
||
9307 fixup_cache
.first_frag
== NULL
)
9309 xtensa_cache_relaxable_fixups (&fixup_cache
, seginfo
);
9310 fixup_cache
.seg
= now_seg
;
9311 fixup_cache
.first_frag
= fragP
;
9314 /* Scan for jumps that will not reach. */
9315 for (i
= xtensa_find_first_cached_fixup (&fixup_cache
, searchaddr
);
9316 i
< fixup_cache
.n_fixups
; ++i
)
9319 fixS
*fixP
= fixup_cache
.fixups
[i
].fixP
;
9320 int target
= fixup_cache
.fixups
[i
].target
;
9321 int addr
= fixup_cache
.fixups
[i
].addr
;
9322 int delta
= fixup_cache
.fixups
[i
].delta
+ stretch
;
9324 trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9326 if (addr
+ J_RANGE
< trampaddr
)
9328 if (addr
> trampaddr
+ J_RANGE
)
9330 if (abs (delta
) < J_RANGE
)
9333 slot
= fixP
->tc_fix_data
.slot
;
9335 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
9336 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
9337 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9338 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9339 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9340 int lower
= (target
< addr
) ? target
: addr
;
9341 int upper
= (target
> addr
) ? target
: addr
;
9342 int midpoint
= lower
+ (upper
- lower
) / 2;
9344 if ((upper
- lower
) > 2 * J_RANGE
)
9346 /* One trampoline won't suffice; we need multiple jumps.
9347 Jump to the trampoline that's farthest, but still in
9348 range relative to the original "j" instruction. */
9349 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9351 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9352 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
9357 if (this_addr
- addr
< J_RANGE
)
9362 /* Backward jump. */
9363 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9370 struct trampoline_frag
*best_tf
= NULL
;
9373 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9375 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9376 int this_delta
= abs (this_addr
- midpoint
);
9378 if (!best_tf
|| this_delta
< best_delta
)
9381 best_delta
= this_delta
;
9386 if (tf
->fragP
== fragP
)
9388 if (abs (addr
- trampaddr
) < J_RANGE
)
9389 { /* The trampoline is in range of original; fix it! */
9394 fragS
*fP
; /* The out-of-range jump. */
9396 new_stretch
+= init_trampoline_frag (tf
);
9397 offset
= fragP
->fr_fix
; /* Where to assemble the j insn. */
9398 lsym
= fragP
->fr_symbol
;
9400 /* Assemble a jump to the target label here. */
9402 insn
.insn_type
= ITYPE_INSN
;
9403 insn
.opcode
= xtensa_j_opcode
;
9405 set_expr_symbol_offset (&insn
.tok
[0], lsym
, offset
);
9406 fmt
= xg_get_single_format (xtensa_j_opcode
);
9407 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9408 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9409 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fragP
->fr_literal
+ offset
, 3);
9412 /* Add a fix-up for the original j insn. */
9413 newfixP
= fix_new (fP
, fixP
->fx_where
, fixP
->fx_size
, lsym
, fragP
->fr_fix
- 3, TRUE
, fixP
->fx_r_type
);
9414 newfixP
->fx_no_overflow
= 1;
9415 newfixP
->tc_fix_data
.X_add_symbol
= lsym
;
9416 newfixP
->tc_fix_data
.X_add_number
= offset
;
9417 newfixP
->tc_fix_data
.slot
= slot
;
9419 xtensa_delete_cached_fixup (&fixup_cache
, i
);
9420 xtensa_add_cached_fixup (&fixup_cache
, newfixP
);
9422 /* Move the fix-up from the original j insn to this one. */
9423 fixP
->fx_frag
= fragP
;
9424 fixP
->fx_where
= fragP
->fr_fix
- 3;
9425 fixP
->tc_fix_data
.slot
= 0;
9427 xtensa_add_cached_fixup (&fixup_cache
, fixP
);
9429 /* re-do current fixup */
9432 /* Adjust the jump around this trampoline (if present). */
9433 if (tf
->fixP
!= NULL
)
9435 tf
->fixP
->fx_offset
+= 3;
9438 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9439 /* Do we have room for more? */
9440 if (fragP
->fr_var
< 3)
9441 { /* No, convert to fill. */
9443 fragP
->fr_subtype
= 0;
9444 /* Remove from the trampoline_list. */
9445 prev
->next
= tf
->next
;
9446 if (fragP
== fixup_cache
.first_frag
)
9447 fixup_cache
.first_frag
= NULL
;
9458 as_bad (_("bad relaxation state"));
9461 /* Tell gas we need another relaxation pass. */
9462 if (! fragP
->tc_frag_data
.relax_seen
)
9464 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9468 new_logical_line (file_name
, line
);
9474 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9476 addressT old_address
, old_next_address
, old_size
;
9477 addressT new_address
, new_next_address
, new_size
;
9480 /* All the frags with relax_frag_for_alignment prior to this one in the
9481 section have been done, hopefully eliminating the need for a NOP here.
9482 But, this will put it in if necessary. */
9484 /* Calculate the old address of this fragment and the next fragment. */
9485 old_address
= fragP
->fr_address
- stretch
;
9486 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9487 fragP
->tc_frag_data
.text_expansion
[0]);
9488 old_size
= old_next_address
- old_address
;
9490 /* Calculate the new address of this fragment and the next fragment. */
9491 new_address
= fragP
->fr_address
;
9493 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9494 new_size
= new_next_address
- new_address
;
9496 growth
= new_size
- old_size
;
9498 /* Fix up the text_expansion field and return the new growth. */
9499 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9504 /* Add a NOP instruction. */
9507 relax_frag_add_nop (fragS
*fragP
)
9509 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9510 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9511 assemble_nop (length
, nop_buf
);
9512 fragP
->tc_frag_data
.is_insn
= TRUE
;
9514 if (fragP
->fr_var
< length
)
9516 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9520 fragP
->fr_fix
+= length
;
9521 fragP
->fr_var
-= length
;
9526 static long future_alignment_required (fragS
*, long);
9529 relax_frag_for_align (fragS
*fragP
, long stretch
)
9531 /* Overview of the relaxation procedure for alignment:
9532 We can widen with NOPs or by widening instructions or by filling
9533 bytes after jump instructions. Find the opportune places and widen
9534 them if necessary. */
9539 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9540 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9541 || (fragP
->fr_subtype
== RELAX_SLOTS
9542 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9544 stretch_me
= future_alignment_required (fragP
, stretch
);
9545 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9551 /* We expanded on a previous pass. Can we shrink now? */
9552 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9553 if (shrink
<= stretch
&& stretch
> 0)
9555 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9561 /* Below here, diff > 0. */
9562 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9568 /* Return the address of the next frag that should be aligned.
9570 By "address" we mean the address it _would_ be at if there
9571 is no action taken to align it between here and the target frag.
9572 In other words, if no narrows and no fill nops are used between
9573 here and the frag to align, _even_if_ some of the frags we use
9574 to align targets have already expanded on a previous relaxation
9577 Also, count each frag that may be used to help align the target.
9579 Return 0 if there are no frags left in the chain that need to be
9583 find_address_of_next_align_frag (fragS
**fragPP
,
9587 bfd_boolean
*paddable
)
9589 fragS
*fragP
= *fragPP
;
9590 addressT address
= fragP
->fr_address
;
9592 /* Do not reset the counts to 0. */
9596 /* Limit this to a small search. */
9597 if (*widens
>= (int) xtensa_fetch_width
)
9602 address
+= fragP
->fr_fix
;
9604 if (fragP
->fr_type
== rs_fill
)
9605 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9606 else if (fragP
->fr_type
== rs_machine_dependent
)
9608 switch (fragP
->fr_subtype
)
9610 case RELAX_UNREACHABLE
:
9614 case RELAX_FILL_NOP
:
9616 if (!fragP
->tc_frag_data
.is_no_density
)
9621 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9626 address
+= total_frag_text_expansion (fragP
);
9630 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9633 case RELAX_ALIGN_NEXT_OPCODE
:
9634 case RELAX_DESIRE_ALIGN
:
9638 case RELAX_MAYBE_UNREACHABLE
:
9639 case RELAX_MAYBE_DESIRE_ALIGN
:
9644 /* Just punt if we don't know the type. */
9651 /* Just punt if we don't know the type. */
9655 fragP
= fragP
->fr_next
;
9663 static long bytes_to_stretch (fragS
*, int, int, int, int);
9666 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9668 fragS
*this_frag
= fragP
;
9672 int narrow_nops
= 0;
9673 bfd_boolean paddable
= FALSE
;
9674 offsetT local_opt_diff
;
9677 int stretch_amount
= 0;
9678 int local_stretch_amount
;
9679 int global_stretch_amount
;
9681 address
= find_address_of_next_align_frag
9682 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9686 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9687 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9689 frag_wane (this_frag
);
9693 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9694 opt_diff
= local_opt_diff
;
9695 gas_assert (opt_diff
>= 0);
9696 gas_assert (max_diff
>= opt_diff
);
9701 fragP
= fragP
->fr_next
;
9703 while (fragP
&& opt_diff
< max_diff
&& address
)
9705 /* We only use these to determine if we can exit early
9706 because there will be plenty of ways to align future
9708 int glob_widens
= 0;
9711 bfd_boolean glob_pad
= 0;
9712 address
= find_address_of_next_align_frag
9713 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9714 /* If there is a padable portion, then skip. */
9715 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9720 offsetT next_m_diff
;
9721 offsetT next_o_diff
;
9723 /* Downrange frags haven't had stretch added to them yet. */
9726 /* The address also includes any text expansion from this
9727 frag in a previous pass, but we don't want that. */
9728 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9730 /* Assume we are going to move at least opt_diff. In
9731 reality, we might not be able to, but assuming that
9732 we will helps catch cases where moving opt_diff pushes
9733 the next target from aligned to unaligned. */
9734 address
+= opt_diff
;
9736 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9738 /* Now cleanup for the adjustments to address. */
9739 next_o_diff
+= opt_diff
;
9740 next_m_diff
+= opt_diff
;
9741 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9742 opt_diff
= next_o_diff
;
9743 if (next_m_diff
< max_diff
)
9744 max_diff
= next_m_diff
;
9745 fragP
= fragP
->fr_next
;
9749 /* If there are enough wideners in between, do it. */
9752 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9754 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9759 local_stretch_amount
9760 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9761 num_widens
, local_opt_diff
);
9762 global_stretch_amount
9763 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9764 num_widens
, opt_diff
);
9765 /* If the condition below is true, then the frag couldn't
9766 stretch the correct amount for the global case, so we just
9767 optimize locally. We'll rely on the subsequent frags to get
9768 the correct alignment in the global case. */
9769 if (global_stretch_amount
< local_stretch_amount
)
9770 stretch_amount
= local_stretch_amount
;
9772 stretch_amount
= global_stretch_amount
;
9774 if (this_frag
->fr_subtype
== RELAX_SLOTS
9775 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9776 gas_assert (stretch_amount
<= 1);
9777 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9779 if (this_frag
->tc_frag_data
.is_no_density
)
9780 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9782 gas_assert (stretch_amount
<= 3);
9785 return stretch_amount
;
9789 /* The idea: widen everything you can to get a target or loop aligned,
9790 then start using NOPs.
9792 wide_nops = the number of wide NOPs available for aligning
9793 narrow_nops = the number of narrow NOPs available for aligning
9794 (a subset of wide_nops)
9795 widens = the number of narrow instructions that should be widened
9800 bytes_to_stretch (fragS
*this_frag
,
9809 int bytes_short
= desired_diff
- num_widens
;
9811 gas_assert (desired_diff
>= 0
9812 && desired_diff
< (signed) xtensa_fetch_width
);
9813 if (desired_diff
== 0)
9816 gas_assert (wide_nops
> 0 || num_widens
> 0);
9818 /* Always prefer widening to NOP-filling. */
9819 if (bytes_short
< 0)
9821 /* There are enough RELAX_NARROW frags after this one
9822 to align the target without widening this frag in any way. */
9826 if (bytes_short
== 0)
9828 /* Widen every narrow between here and the align target
9829 and the align target will be properly aligned. */
9830 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9836 /* From here we will need at least one NOP to get an alignment.
9837 However, we may not be able to align at all, in which case,
9839 nops_needed
= desired_diff
/ 3;
9841 /* If there aren't enough nops, don't widen. */
9842 if (nops_needed
> wide_nops
)
9845 /* First try it with all wide nops. */
9846 nop_bytes
= nops_needed
* 3;
9847 extra_bytes
= desired_diff
- nop_bytes
;
9849 if (nop_bytes
+ num_widens
>= desired_diff
)
9851 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9853 else if (num_widens
== extra_bytes
)
9858 /* Add a narrow nop. */
9862 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9865 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9867 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9868 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9869 else if (num_widens
== extra_bytes
)
9874 /* Replace a wide nop with a narrow nop--we can get here if
9875 extra_bytes was negative in the previous conditional. */
9876 if (narrow_nops
== 1)
9880 if (nop_bytes
+ num_widens
>= desired_diff
)
9882 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9883 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9884 else if (num_widens
== extra_bytes
)
9889 /* If we can't satisfy any of the above cases, then we can't align
9890 using padding or fill nops. */
9895 static struct trampoline_frag
*
9896 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9898 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9899 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9900 struct trampoline_frag
*best_tf
= NULL
;
9903 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9904 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9905 offsetT addr
= fragP
->fr_address
;
9906 offsetT lower
= (addr
< target
) ? addr
: target
;
9907 offsetT upper
= (addr
> target
) ? addr
: target
;
9908 int delta
= upper
- lower
;
9909 offsetT midpoint
= lower
+ delta
/ 2;
9910 int this_delta
= -1;
9913 if (delta
> 2 * J_RANGE
)
9915 /* One trampoline won't do; we need multiple.
9916 Choose the farthest trampoline that's still in range of the original
9917 and let a later pass finish the job. */
9918 for ( ; tf
; tf
= tf
->next
)
9920 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9922 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9926 if (this_addr
- addr
< J_RANGE
)
9931 /* Backward jump. */
9932 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9936 if (abs (addr
- this_addr
) < J_RANGE
)
9941 for ( ; tf
; tf
= tf
->next
)
9943 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9944 this_delta
= abs (this_addr
- midpoint
);
9945 if (unreachable_only
&& tf
->needs_jump_around
)
9947 if (!best_tf
|| this_delta
< best_delta
)
9950 best_delta
= this_delta
;
9951 best_addr
= this_addr
;
9956 best_delta
< J_RANGE
&&
9957 abs(best_addr
- lower
) < J_RANGE
&&
9958 abs(best_addr
- upper
) < J_RANGE
)
9961 return NULL
; /* No suitable trampoline found. */
9965 static struct trampoline_frag
*
9966 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9968 struct trampoline_frag
*tf
= NULL
;
9970 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9973 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
9980 check_and_update_trampolines (void)
9982 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9983 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9984 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9986 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9988 if (tf
->fragP
->fr_var
< 3)
9990 frag_wane (tf
->fragP
);
9991 prev
->next
= tf
->next
;
9999 init_trampoline_frag (struct trampoline_frag
*trampP
)
10001 fragS
*fp
= trampP
->fragP
;
10004 if (fp
->fr_fix
== 0)
10007 char label
[10 + 2 * sizeof(fp
)];
10008 sprintf (label
, ".L0_TR_%p", fp
);
10010 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10011 fp
->fr_symbol
= lsym
;
10012 if (trampP
->needs_jump_around
)
10014 /* Add a jump around this block of jumps, in case
10015 control flows into this block. */
10019 xtensa_isa isa
= xtensa_default_isa
;
10021 fp
->tc_frag_data
.is_insn
= 1;
10022 /* Assemble a jump insn. */
10023 tinsn_init (&insn
);
10024 insn
.insn_type
= ITYPE_INSN
;
10025 insn
.opcode
= xtensa_j_opcode
;
10027 set_expr_symbol_offset (&insn
.tok
[0], lsym
, 3);
10028 fmt
= xg_get_single_format (xtensa_j_opcode
);
10029 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10030 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10031 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fp
->fr_literal
, 3);
10035 fixP
= fix_new (fp
, 0, 3, lsym
, 3, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10036 trampP
->fixP
= fixP
;
10044 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
10046 fragS
*tramp
= trampP
->fragP
;
10048 int offset
= tramp
->fr_fix
; /* Where to assemble the j insn. */
10054 xtensa_isa isa
= xtensa_default_isa
;
10057 lsym
= tramp
->fr_symbol
;
10058 /* Assemble a jump to the target label in the trampoline frag. */
10059 tsym
= origfrag
->tc_frag_data
.slot_symbols
[0];
10060 toffset
= origfrag
-> tc_frag_data
.slot_offsets
[0];
10061 tinsn_init (&insn
);
10062 insn
.insn_type
= ITYPE_INSN
;
10063 insn
.opcode
= xtensa_j_opcode
;
10065 set_expr_symbol_offset (&insn
.tok
[0], tsym
, toffset
);
10066 fmt
= xg_get_single_format (xtensa_j_opcode
);
10067 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10068 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10069 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)tramp
->fr_literal
+ offset
, 3);
10070 tramp
->fr_fix
+= 3;
10071 tramp
->fr_var
-= 3;
10073 /* add a fix-up for the trampoline jump. */
10074 fixP
= fix_new (tramp
, tramp
->fr_fix
- 3, 3, tsym
, toffset
, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10075 /* Modify the jump at the start of this trampoline to point past the newly-added jump. */
10076 fixP
= trampP
->fixP
;
10078 fixP
->fx_offset
+= 3;
10079 /* Modify the original j to point here. */
10080 origfrag
->tc_frag_data
.slot_symbols
[0] = lsym
;
10081 origfrag
->tc_frag_data
.slot_offsets
[0] = tramp
->fr_fix
- 3;
10082 /* If trampoline is full, remove it from the list. */
10083 check_and_update_trampolines ();
10090 relax_frag_immed (segT segP
,
10097 bfd_boolean estimate_only
)
10101 bfd_boolean negatable_branch
= FALSE
;
10102 bfd_boolean branch_jmp_to_next
= FALSE
;
10103 bfd_boolean from_wide_insn
= FALSE
;
10104 xtensa_isa isa
= xtensa_default_isa
;
10106 offsetT frag_offset
;
10108 int num_text_bytes
, num_literal_bytes
;
10109 int literal_diff
, total_text_diff
, this_text_diff
;
10111 gas_assert (fragP
->fr_opcode
!= NULL
);
10113 xg_clear_vinsn (&cur_vinsn
);
10114 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10115 if (cur_vinsn
.num_slots
> 1)
10116 from_wide_insn
= TRUE
;
10118 tinsn
= cur_vinsn
.slots
[slot
];
10119 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10121 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10124 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10125 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10127 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10129 old_size
= xtensa_format_length (isa
, fmt
);
10131 /* Special case: replace a branch to the next instruction with a NOP.
10132 This is required to work around a hardware bug in T1040.0 and also
10133 serves as an optimization. */
10135 if (branch_jmp_to_next
10136 && ((old_size
== 2) || (old_size
== 3))
10137 && !next_frag_is_loop_target (fragP
))
10140 /* Here is the fun stuff: Get the immediate field from this
10141 instruction. If it fits, we are done. If not, find the next
10142 instruction sequence that fits. */
10144 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10145 istack_init (&istack
);
10146 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10147 min_steps
, stretch
);
10148 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10150 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10152 /* Figure out the number of bytes needed. */
10153 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10155 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10156 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10158 if (from_wide_insn
)
10161 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10164 num_text_bytes
+= old_size
;
10165 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10166 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10169 /* The first instruction in the relaxed sequence will go after
10170 the current wide instruction, and thus its symbolic immediates
10173 istack_init (&istack
);
10174 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10175 frag_offset
+ old_size
,
10176 min_steps
, stretch
+ old_size
);
10177 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10179 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10180 = (int) RELAX_IMMED
+ num_steps
;
10182 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10184 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10186 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10190 total_text_diff
= num_text_bytes
- old_size
;
10191 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10193 /* It MUST get larger. If not, we could get an infinite loop. */
10194 gas_assert (num_text_bytes
>= 0);
10195 gas_assert (literal_diff
>= 0);
10196 gas_assert (total_text_diff
>= 0);
10198 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10199 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10200 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10201 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10203 /* Find the associated expandable literal for this. */
10204 if (literal_diff
!= 0)
10206 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10209 gas_assert (literal_diff
== 4);
10210 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10212 /* We expect that the literal section state has NOT been
10214 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10215 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10216 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10218 /* We need to mark this section for another iteration
10224 if (negatable_branch
&& istack
.ninsn
> 1)
10225 update_next_frag_state (fragP
);
10227 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10228 if (istack
.ninsn
> 2 &&
10229 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10230 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10231 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10233 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10235 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
10237 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
10241 this_text_diff
+= init_trampoline_frag (tf
);
10242 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
10246 /* If target symbol is undefined, assume it will reach once linked. */
10247 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10249 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10251 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10252 _("jump target out of range; no usable trampoline found"));
10258 return this_text_diff
;
10262 /* md_convert_frag Hook and Helper Functions. */
10264 static void convert_frag_align_next_opcode (fragS
*);
10265 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10266 static void convert_frag_fill_nop (fragS
*);
10267 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10270 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10272 static xtensa_insnbuf vbuf
= NULL
;
10273 xtensa_isa isa
= xtensa_default_isa
;
10277 const char *file_name
;
10280 file_name
= as_where (&line
);
10281 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10283 switch (fragp
->fr_subtype
)
10285 case RELAX_ALIGN_NEXT_OPCODE
:
10286 /* Always convert. */
10287 convert_frag_align_next_opcode (fragp
);
10290 case RELAX_DESIRE_ALIGN
:
10291 /* Do nothing. If not aligned already, too bad. */
10294 case RELAX_LITERAL
:
10295 case RELAX_LITERAL_FINAL
:
10300 vbuf
= xtensa_insnbuf_alloc (isa
);
10302 xtensa_insnbuf_from_chars
10303 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10304 fmt
= xtensa_format_decode (isa
, vbuf
);
10305 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10307 for (slot
= 0; slot
< num_slots
; slot
++)
10309 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10312 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10316 case RELAX_IMMED_STEP1
:
10317 case RELAX_IMMED_STEP2
:
10318 case RELAX_IMMED_STEP3
:
10319 /* Place the immediate. */
10322 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10327 /* This is OK because some slots could have
10328 relaxations and others have none. */
10334 case RELAX_UNREACHABLE
:
10335 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10336 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10337 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10341 case RELAX_MAYBE_UNREACHABLE
:
10342 case RELAX_MAYBE_DESIRE_ALIGN
:
10346 case RELAX_FILL_NOP
:
10347 convert_frag_fill_nop (fragp
);
10350 case RELAX_LITERAL_NR
:
10351 if (use_literal_section
)
10353 /* This should have been handled during relaxation. When
10354 relaxing a code segment, literals sometimes need to be
10355 added to the corresponding literal segment. If that
10356 literal segment has already been relaxed, then we end up
10357 in this situation. Marking the literal segments as data
10358 would make this happen less often (since GAS always relaxes
10359 code before data), but we could still get into trouble if
10360 there are instructions in a segment that is not marked as
10361 containing code. Until we can implement a better solution,
10362 cheat and adjust the addresses of all the following frags.
10363 This could break subsequent alignments, but the linker's
10364 literal coalescing will do that anyway. */
10367 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10368 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10369 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10370 fragp
->fr_var
-= 4;
10371 fragp
->fr_fix
+= 4;
10372 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10373 f
->fr_address
+= 4;
10376 as_bad (_("invalid relaxation fragment result"));
10379 case RELAX_TRAMPOLINE
:
10384 new_logical_line (file_name
, line
);
10389 convert_frag_align_next_opcode (fragS
*fragp
)
10391 char *nop_buf
; /* Location for Writing. */
10392 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10393 addressT aligned_address
;
10395 int nop
, nop_count
;
10397 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10399 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10400 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10401 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10403 for (nop
= 0; nop
< nop_count
; nop
++)
10406 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10408 assemble_nop (nop_size
, nop_buf
);
10409 nop_buf
+= nop_size
;
10412 fragp
->fr_fix
+= fill_size
;
10413 fragp
->fr_var
-= fill_size
;
10418 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10420 TInsn tinsn
, single_target
;
10421 int size
, old_size
, diff
;
10422 offsetT frag_offset
;
10424 gas_assert (slot
== 0);
10425 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10427 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10429 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10430 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10431 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10436 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10438 /* No conversion. */
10443 gas_assert (fragP
->fr_opcode
!= NULL
);
10445 /* Frags in this relaxation state should only contain
10446 single instruction bundles. */
10447 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10449 /* Just convert it to a wide form.... */
10451 old_size
= xg_get_single_size (tinsn
.opcode
);
10453 tinsn_init (&single_target
);
10454 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10456 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10458 as_bad (_("unable to widen instruction"));
10462 size
= xg_get_single_size (single_target
.opcode
);
10463 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10464 frag_offset
, TRUE
);
10466 diff
= size
- old_size
;
10467 gas_assert (diff
>= 0);
10468 gas_assert (diff
<= fragP
->fr_var
);
10469 fragP
->fr_var
-= diff
;
10470 fragP
->fr_fix
+= diff
;
10478 convert_frag_fill_nop (fragS
*fragP
)
10480 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10481 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10482 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10483 - fragP
->fr_address
- fragP
->fr_fix
));
10486 /* No conversion. */
10490 assemble_nop (size
, loc
);
10491 fragP
->tc_frag_data
.is_insn
= TRUE
;
10492 fragP
->fr_var
-= size
;
10493 fragP
->fr_fix
+= size
;
10498 static fixS
*fix_new_exp_in_seg
10499 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10500 bfd_reloc_code_real_type
);
10501 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10504 convert_frag_immed (segT segP
,
10510 char *immed_instr
= fragP
->fr_opcode
;
10512 bfd_boolean expanded
= FALSE
;
10513 bfd_boolean branch_jmp_to_next
= FALSE
;
10514 char *fr_opcode
= fragP
->fr_opcode
;
10515 xtensa_isa isa
= xtensa_default_isa
;
10516 bfd_boolean from_wide_insn
= FALSE
;
10518 bfd_boolean is_loop
;
10520 gas_assert (fr_opcode
!= NULL
);
10522 xg_clear_vinsn (&cur_vinsn
);
10524 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10525 if (cur_vinsn
.num_slots
> 1)
10526 from_wide_insn
= TRUE
;
10528 orig_tinsn
= cur_vinsn
.slots
[slot
];
10529 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10531 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10533 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10534 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10536 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10538 /* Conversion just inserts a NOP and marks the fix as completed. */
10539 bytes
= xtensa_format_length (isa
, fmt
);
10542 cur_vinsn
.slots
[slot
].opcode
=
10543 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10544 cur_vinsn
.slots
[slot
].ntok
= 0;
10548 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10549 gas_assert (bytes
== 2 || bytes
== 3);
10550 build_nop (&cur_vinsn
.slots
[0], bytes
);
10551 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10553 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10554 xtensa_insnbuf_to_chars
10555 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10560 /* Here is the fun stuff: Get the immediate field from this
10561 instruction. If it fits, we're done. If not, find the next
10562 instruction sequence that fits. */
10566 symbolS
*lit_sym
= NULL
;
10567 int total_size
= 0;
10568 int target_offset
= 0;
10571 symbolS
*gen_label
= NULL
;
10572 offsetT frag_offset
;
10573 bfd_boolean first
= TRUE
;
10575 /* It does not fit. Find something that does and
10576 convert immediately. */
10577 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10578 istack_init (&istack
);
10579 xg_assembly_relax (&istack
, &orig_tinsn
,
10580 segP
, fragP
, frag_offset
, min_steps
, 0);
10582 old_size
= xtensa_format_length (isa
, fmt
);
10584 /* Assemble this right inline. */
10586 /* First, create the mapping from a label name to the REAL label. */
10588 for (i
= 0; i
< istack
.ninsn
; i
++)
10590 TInsn
*tinsn
= &istack
.insn
[i
];
10593 switch (tinsn
->insn_type
)
10595 case ITYPE_LITERAL
:
10596 if (lit_sym
!= NULL
)
10597 as_bad (_("multiple literals in expansion"));
10598 /* First find the appropriate space in the literal pool. */
10599 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10600 if (lit_frag
== NULL
)
10601 as_bad (_("no registered fragment for literal"));
10602 if (tinsn
->ntok
!= 1)
10603 as_bad (_("number of literal tokens != 1"));
10605 /* Set the literal symbol and add a fixup. */
10606 lit_sym
= lit_frag
->fr_symbol
;
10610 if (align_targets
&& !is_loop
)
10612 fragS
*unreach
= fragP
->fr_next
;
10613 while (!(unreach
->fr_type
== rs_machine_dependent
10614 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10615 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10617 unreach
= unreach
->fr_next
;
10620 gas_assert (unreach
->fr_type
== rs_machine_dependent
10621 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10622 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10624 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10626 gas_assert (gen_label
== NULL
);
10627 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10628 fr_opcode
- fragP
->fr_literal
10629 + target_offset
, fragP
);
10633 if (first
&& from_wide_insn
)
10635 target_offset
+= xtensa_format_length (isa
, fmt
);
10637 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10638 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10641 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10648 for (i
= 0; i
< istack
.ninsn
; i
++)
10650 TInsn
*tinsn
= &istack
.insn
[i
];
10654 bfd_reloc_code_real_type reloc_type
;
10656 switch (tinsn
->insn_type
)
10658 case ITYPE_LITERAL
:
10659 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10660 /* Already checked. */
10661 gas_assert (lit_frag
!= NULL
);
10662 gas_assert (lit_sym
!= NULL
);
10663 gas_assert (tinsn
->ntok
== 1);
10665 target_seg
= S_GET_SEGMENT (lit_sym
);
10666 gas_assert (target_seg
);
10667 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10668 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10669 &tinsn
->tok
[0], FALSE
, reloc_type
);
10676 xg_resolve_labels (tinsn
, gen_label
);
10677 xg_resolve_literals (tinsn
, lit_sym
);
10678 if (from_wide_insn
&& first
)
10681 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10683 cur_vinsn
.slots
[slot
] = *tinsn
;
10687 cur_vinsn
.slots
[slot
].opcode
=
10688 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10689 cur_vinsn
.slots
[slot
].ntok
= 0;
10691 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10692 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10693 (unsigned char *) immed_instr
, 0);
10694 fragP
->tc_frag_data
.is_insn
= TRUE
;
10695 size
= xtensa_format_length (isa
, fmt
);
10696 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10698 xg_emit_insn_to_buf
10699 (tinsn
, immed_instr
+ size
, fragP
,
10700 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10701 size
+= xg_get_single_size (tinsn
->opcode
);
10706 size
= xg_get_single_size (tinsn
->opcode
);
10707 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10708 immed_instr
- fragP
->fr_literal
, TRUE
);
10710 immed_instr
+= size
;
10711 total_size
+= size
;
10716 diff
= total_size
- old_size
;
10717 gas_assert (diff
>= 0);
10720 gas_assert (diff
<= fragP
->fr_var
);
10721 fragP
->fr_var
-= diff
;
10722 fragP
->fr_fix
+= diff
;
10725 /* Check for undefined immediates in LOOP instructions. */
10729 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10730 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10732 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10735 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10736 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10738 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10743 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10744 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10746 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10748 /* Add an expansion note on the expanded instruction. */
10749 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10750 &orig_tinsn
.tok
[0], TRUE
,
10751 BFD_RELOC_XTENSA_ASM_EXPAND
);
10756 /* Add a new fix expression into the desired segment. We have to
10757 switch to that segment to do this. */
10760 fix_new_exp_in_seg (segT new_seg
,
10761 subsegT new_subseg
,
10767 bfd_reloc_code_real_type r_type
)
10770 segT seg
= now_seg
;
10771 subsegT subseg
= now_subseg
;
10773 gas_assert (new_seg
!= 0);
10774 subseg_set (new_seg
, new_subseg
);
10776 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10777 subseg_set (seg
, subseg
);
10782 /* Relax a loop instruction so that it can span loop >256 bytes.
10788 addi as, as, lo8 (label-.L1)
10789 addmi as, as, mid8 (label-.L1)
10800 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10805 unsigned long target
;
10806 static xtensa_insnbuf insnbuf
= NULL
;
10807 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10808 xtensa_isa isa
= xtensa_default_isa
;
10809 addressT loop_offset
;
10810 addressT addi_offset
= 9;
10811 addressT addmi_offset
= 12;
10816 insnbuf
= xtensa_insnbuf_alloc (isa
);
10818 /* Get the loop offset. */
10819 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10821 /* Validate that there really is a LOOP at the loop_offset. Because
10822 loops are not bundleable, we can assume that the instruction will be
10824 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10825 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10827 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10828 addi_offset
+= loop_offset
;
10829 addmi_offset
+= loop_offset
;
10831 gas_assert (tinsn
->ntok
== 2);
10832 if (tinsn
->tok
[1].X_op
== O_constant
)
10833 target
= tinsn
->tok
[1].X_add_number
;
10834 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10836 /* Find the fragment. */
10837 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10838 gas_assert (S_GET_SEGMENT (sym
) == segP
10839 || S_GET_SEGMENT (sym
) == absolute_section
);
10840 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10844 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10848 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10849 loop_length_hi
= loop_length
& ~0x0ff;
10850 loop_length_lo
= loop_length
& 0x0ff;
10851 if (loop_length_lo
>= 128)
10853 loop_length_lo
-= 256;
10854 loop_length_hi
+= 256;
10857 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10858 32512. If the loop is larger than that, then we just fail. */
10859 if (loop_length_hi
> 32512)
10860 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10861 _("loop too long for LOOP instruction"));
10863 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10864 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10866 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10867 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10869 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10870 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10872 fragP
->tc_frag_data
.is_insn
= TRUE
;
10873 xtensa_insnbuf_to_chars
10874 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10876 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10877 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10878 xtensa_insnbuf_to_chars
10879 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10881 /* Walk through all of the frags from here to the loop end
10882 and mark them as no_transform to keep them from being modified
10883 by the linker. If we ever have a relocation for the
10884 addi/addmi of the difference of two symbols we can remove this. */
10887 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10888 next_fragP
= next_fragP
->fr_next
)
10890 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10891 if (next_fragP
->tc_frag_data
.is_loop_target
)
10893 if (target_count
== 2)
10899 /* A map that keeps information on a per-subsegment basis. This is
10900 maintained during initial assembly, but is invalid once the
10901 subsegments are smashed together. I.E., it cannot be used during
10904 typedef struct subseg_map_struct
10912 float total_freq
; /* fall-through + branch target frequency */
10913 float target_freq
; /* branch target frequency alone */
10915 struct subseg_map_struct
*next
;
10919 static subseg_map
*sseg_map
= NULL
;
10921 static subseg_map
*
10922 get_subseg_info (segT seg
, subsegT subseg
)
10924 subseg_map
*subseg_e
;
10926 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10928 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10935 static subseg_map
*
10936 add_subseg_info (segT seg
, subsegT subseg
)
10938 subseg_map
*subseg_e
= XNEW (subseg_map
);
10939 memset (subseg_e
, 0, sizeof (subseg_map
));
10940 subseg_e
->seg
= seg
;
10941 subseg_e
->subseg
= subseg
;
10942 subseg_e
->flags
= 0;
10943 /* Start off considering every branch target very important. */
10944 subseg_e
->target_freq
= 1.0;
10945 subseg_e
->total_freq
= 1.0;
10946 subseg_e
->next
= sseg_map
;
10947 sseg_map
= subseg_e
;
10953 get_last_insn_flags (segT seg
, subsegT subseg
)
10955 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10957 return subseg_e
->flags
;
10963 set_last_insn_flags (segT seg
,
10968 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10970 subseg_e
= add_subseg_info (seg
, subseg
);
10972 subseg_e
->flags
|= fl
;
10974 subseg_e
->flags
&= ~fl
;
10979 get_subseg_total_freq (segT seg
, subsegT subseg
)
10981 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10983 return subseg_e
->total_freq
;
10989 get_subseg_target_freq (segT seg
, subsegT subseg
)
10991 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10993 return subseg_e
->target_freq
;
10999 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11001 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11003 subseg_e
= add_subseg_info (seg
, subseg
);
11004 subseg_e
->total_freq
= total_f
;
11005 subseg_e
->target_freq
= target_f
;
11009 /* Segment Lists and emit_state Stuff. */
11012 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11017 segT literal_section
= head
->seg
;
11019 /* Move the literal section to the front of the section list. */
11020 gas_assert (literal_section
);
11021 if (literal_section
!= stdoutput
->sections
)
11023 bfd_section_list_remove (stdoutput
, literal_section
);
11024 bfd_section_list_prepend (stdoutput
, literal_section
);
11031 static void mark_literal_frags (seg_list
*);
11034 xtensa_move_literals (void)
11037 frchainS
*frchain_from
, *frchain_to
;
11038 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11039 fragS
**frag_splice
;
11042 fixS
*fix
, *next_fix
, **fix_splice
;
11044 struct litpool_seg
*lps
;
11045 const char *init_name
= INIT_SECTION_NAME
;
11046 const char *fini_name
= FINI_SECTION_NAME
;
11047 int init_name_len
= strlen(init_name
);
11048 int fini_name_len
= strlen(fini_name
);
11050 mark_literal_frags (literal_head
->next
);
11052 if (use_literal_section
)
11055 /* Assign addresses (rough estimates) to the potential literal pool locations
11056 and create new ones if the gaps are too large. */
11058 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11060 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11061 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11064 for ( ; frchP
; frchP
= frchP
->frch_next
)
11067 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11069 if (lpf
&& fragP
== lpf
->fragP
)
11071 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11072 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11073 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11074 /* Found a litpool location. */
11078 if (fragP
->fr_type
== rs_machine_dependent
&&
11079 fragP
->fr_subtype
== RELAX_SLOTS
)
11082 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11084 if (fragP
->tc_frag_data
.literal_frags
[slot
])
11086 /* L32R; point its literal to the nearest litpool
11087 preferring non-"candidate" positions to avoid
11088 the jump-around. */
11089 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11090 struct litpool_frag
*lp
= lpf
->prev
;
11095 while (lp
->fragP
->fr_subtype
==
11096 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11099 if (lp
->fragP
== NULL
)
11101 /* End of list; have to bite the bullet.
11102 Take the nearest. */
11106 /* Does it (conservatively) reach? */
11107 if (addr
- lp
->addr
<= 128 * 1024)
11109 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
11111 /* Found a good one. */
11114 else if (lp
->prev
->fragP
&&
11115 addr
- lp
->prev
->addr
> 128 * 1024)
11117 /* This is still a "candidate" but the next one
11118 will be too far away, so revert to the nearest
11119 one, convert it and add the jump around. */
11123 char label
[10 + 2 * sizeof (fragS
*)];
11125 poolbeg
= lp
->fragP
;
11127 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11128 poolend
= poolbeg
->fr_next
;
11129 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11130 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11131 /* Create a local symbol pointing to the
11132 end of the pool. */
11133 sprintf (label
, ".L0_LT_%p", poolbeg
);
11134 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11136 poolbeg
->fr_symbol
= lsym
;
11137 /* Rest is done in xtensa_relax_frag. */
11141 if (! litfrag
->tc_frag_data
.literal_frag
)
11143 /* Take earliest use of this literal to avoid
11145 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11150 addr
+= fragP
->fr_fix
;
11151 if (fragP
->fr_type
== rs_fill
)
11152 addr
+= fragP
->fr_offset
;
11157 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11159 const char *seg_name
= segment_name (segment
->seg
);
11161 /* Keep the literals for .init and .fini in separate sections. */
11162 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11163 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11164 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11165 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11168 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11169 search_frag
= frchain_from
->frch_root
;
11170 literal_pool
= NULL
;
11172 frag_splice
= &(frchain_from
->frch_root
);
11174 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11176 gas_assert (search_frag
->fr_fix
== 0
11177 || search_frag
->fr_type
== rs_align
);
11178 search_frag
= search_frag
->fr_next
;
11183 search_frag
= frchain_from
->frch_root
;
11184 as_bad_where (search_frag
->fr_file
, search_frag
->fr_line
,
11185 _("literal pool location required for text-section-literals; specify with .literal_position"));
11189 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11190 == RELAX_LITERAL_POOL_BEGIN
);
11191 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11193 /* Make sure that all the frags in this series are closed, and
11194 that there is at least one left over of zero-size. This
11195 prevents us from making a segment with an frchain without any
11197 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11198 xtensa_set_frag_assembly_state (frag_now
);
11199 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11200 xtensa_set_frag_assembly_state (frag_now
);
11202 while (search_frag
!= frag_now
)
11204 next_frag
= search_frag
->fr_next
;
11205 if (search_frag
->tc_frag_data
.literal_frag
)
11207 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11208 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11209 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11210 gas_assert (frchain_to
);
11213 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11215 /* Skip empty fill frags. */
11216 *frag_splice
= next_frag
;
11217 search_frag
= next_frag
;
11221 if (search_frag
->fr_type
== rs_align
)
11223 /* Skip alignment frags, because the pool as a whole will be
11224 aligned if used, and we don't want to force alignment if the
11226 *frag_splice
= next_frag
;
11227 search_frag
= next_frag
;
11231 /* First, move the frag out of the literal section and
11232 to the appropriate place. */
11234 /* Insert an aligmnent frag at start of pool. */
11235 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11236 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11238 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11239 emit_state prev_state
;
11242 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11243 prev_frag
= frag_now
;
11244 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11245 align_frag
= frag_now
;
11246 frag_align (2, 0, 0);
11247 /* Splice it into the right place. */
11248 prev_frag
->fr_next
= align_frag
->fr_next
;
11249 align_frag
->fr_next
= literal_pool
->fr_next
;
11250 literal_pool
->fr_next
= align_frag
;
11251 /* Insert after this one. */
11252 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11253 xtensa_restore_emit_state (&prev_state
);
11255 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11256 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11257 /* Skip align frag. */
11258 if (insert_after
->fr_next
->fr_type
== rs_align
)
11260 insert_after
= insert_after
->fr_next
;
11263 *frag_splice
= next_frag
;
11264 search_frag
->fr_next
= insert_after
->fr_next
;
11265 insert_after
->fr_next
= search_frag
;
11266 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11267 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11269 /* Now move any fixups associated with this frag to the
11271 fix
= frchain_from
->fix_root
;
11272 fix_splice
= &(frchain_from
->fix_root
);
11275 next_fix
= fix
->fx_next
;
11276 if (fix
->fx_frag
== search_frag
)
11278 *fix_splice
= next_fix
;
11279 fix
->fx_next
= frchain_to
->fix_root
;
11280 frchain_to
->fix_root
= fix
;
11281 if (frchain_to
->fix_tail
== NULL
)
11282 frchain_to
->fix_tail
= fix
;
11285 fix_splice
= &(fix
->fx_next
);
11288 search_frag
= next_frag
;
11291 if (frchain_from
->fix_root
!= NULL
)
11293 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11294 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11296 gas_assert (frchain_from
->fix_root
== NULL
);
11298 frchain_from
->fix_tail
= NULL
;
11299 xtensa_restore_emit_state (&state
);
11302 /* Now fix up the SEGMENT value for all the literal symbols. */
11303 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11305 symbolS
*lit_sym
= lit
->sym
;
11306 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11308 S_SET_SEGMENT (lit_sym
, dseg
);
11313 /* Walk over all the frags for segments in a list and mark them as
11314 containing literals. As clunky as this is, we can't rely on frag_var
11315 and frag_variant to get called in all situations. */
11318 mark_literal_frags (seg_list
*segment
)
11320 frchainS
*frchain_from
;
11321 fragS
*search_frag
;
11325 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11326 search_frag
= frchain_from
->frch_root
;
11327 while (search_frag
)
11329 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11330 search_frag
= search_frag
->fr_next
;
11332 segment
= segment
->next
;
11338 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11340 /* Move all of the sections in the section list to come
11341 after "after" in the gnu segment list. */
11346 segT literal_section
= head
->seg
;
11348 /* Move the literal section after "after". */
11349 gas_assert (literal_section
);
11350 if (literal_section
!= after
)
11352 bfd_section_list_remove (stdoutput
, literal_section
);
11353 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11361 /* Push all the literal segments to the end of the gnu list. */
11364 xtensa_reorder_segments (void)
11371 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11377 /* Now that we have the last section, push all the literal
11378 sections to the end. */
11379 xtensa_reorder_seg_list (literal_head
, last_sec
);
11381 /* Now perform the final error check. */
11382 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11384 gas_assert (new_count
== old_count
);
11388 /* Change the emit state (seg, subseg, and frag related stuff) to the
11389 correct location. Return a emit_state which can be passed to
11390 xtensa_restore_emit_state to return to current fragment. */
11393 xtensa_switch_to_literal_fragment (emit_state
*result
)
11395 if (directive_state
[directive_absolute_literals
])
11397 segT lit4_seg
= cache_literal_section (TRUE
);
11398 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11401 xtensa_switch_to_non_abs_literal_fragment (result
);
11403 /* Do a 4-byte align here. */
11404 frag_align (2, 0, 0);
11405 record_alignment (now_seg
, 2);
11410 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11412 static bfd_boolean recursive
= FALSE
;
11413 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11415 bfd_boolean is_init
=
11416 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
11417 bfd_boolean is_fini
=
11418 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
11420 if (pool_location
== NULL
11421 && !use_literal_section
11423 && !is_init
&& ! is_fini
)
11425 if (!auto_litpools
)
11427 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11430 /* When we mark a literal pool location, we want to put a frag in
11431 the literal pool that points to it. But to do that, we want to
11432 switch_to_literal_fragment. But literal sections don't have
11433 literal pools, so their location is always null, so we would
11434 recurse forever. This is kind of hacky, but it works. */
11437 xtensa_mark_literal_pool_location ();
11441 lit_seg
= cache_literal_section (FALSE
);
11442 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11444 if (!use_literal_section
11445 && !is_init
&& !is_fini
11446 && get_literal_pool_location (now_seg
) != pool_location
)
11448 /* Close whatever frag is there. */
11449 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11450 xtensa_set_frag_assembly_state (frag_now
);
11451 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11452 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11453 xtensa_set_frag_assembly_state (frag_now
);
11458 /* Call this function before emitting data into the literal section.
11459 This is a helper function for xtensa_switch_to_literal_fragment.
11460 This is similar to a .section new_now_seg subseg. */
11463 xtensa_switch_section_emit_state (emit_state
*state
,
11465 subsegT new_now_subseg
)
11467 state
->name
= now_seg
->name
;
11468 state
->now_seg
= now_seg
;
11469 state
->now_subseg
= now_subseg
;
11470 state
->generating_literals
= generating_literals
;
11471 generating_literals
++;
11472 subseg_set (new_now_seg
, new_now_subseg
);
11476 /* Use to restore the emitting into the normal place. */
11479 xtensa_restore_emit_state (emit_state
*state
)
11481 generating_literals
= state
->generating_literals
;
11482 subseg_set (state
->now_seg
, state
->now_subseg
);
11486 /* Predicate function used to look up a section in a particular group. */
11489 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11491 const char *gname
= inf
;
11492 const char *group_name
= elf_group_name (sec
);
11494 return (group_name
== gname
11495 || (group_name
!= NULL
11497 && strcmp (group_name
, gname
) == 0));
11501 /* Get the literal section to be used for the current text section.
11502 The result may be cached in the default_lit_sections structure. */
11505 cache_literal_section (bfd_boolean use_abs_literals
)
11507 const char *text_name
, *group_name
= 0;
11508 const char *base_name
, *suffix
;
11511 segT seg
, current_section
;
11512 int current_subsec
;
11513 bfd_boolean linkonce
= FALSE
;
11515 /* Save the current section/subsection. */
11516 current_section
= now_seg
;
11517 current_subsec
= now_subseg
;
11519 /* Clear the cached values if they are no longer valid. */
11520 if (now_seg
!= default_lit_sections
.current_text_seg
)
11522 default_lit_sections
.current_text_seg
= now_seg
;
11523 default_lit_sections
.lit_seg
= NULL
;
11524 default_lit_sections
.lit4_seg
= NULL
;
11527 /* Check if the literal section is already cached. */
11528 if (use_abs_literals
)
11529 pcached
= &default_lit_sections
.lit4_seg
;
11531 pcached
= &default_lit_sections
.lit_seg
;
11536 text_name
= default_lit_sections
.lit_prefix
;
11537 if (! text_name
|| ! *text_name
)
11539 text_name
= segment_name (current_section
);
11540 group_name
= elf_group_name (current_section
);
11541 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11544 base_name
= use_abs_literals
? ".lit4" : ".literal";
11547 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11549 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11551 suffix
= strchr (text_name
+ linkonce_len
, '.');
11553 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11559 /* If the section name begins or ends with ".text", then replace
11560 that portion instead of appending an additional suffix. */
11561 size_t len
= strlen (text_name
);
11563 && (strcmp (text_name
+ len
- 5, ".text") == 0
11564 || strncmp (text_name
, ".text", 5) == 0))
11567 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11568 if (strncmp (text_name
, ".text", 5) == 0)
11570 strcpy (name
, base_name
);
11571 strcat (name
, text_name
+ 5);
11575 strcpy (name
, text_name
);
11576 strcpy (name
+ len
, base_name
);
11580 /* Canonicalize section names to allow renaming literal sections.
11581 The group name, if any, came from the current text section and
11582 has already been canonicalized. */
11583 name
= tc_canonicalize_symbol_name (name
);
11585 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11586 (void *) group_name
);
11591 seg
= subseg_force_new (name
, 0);
11593 if (! use_abs_literals
)
11595 /* Add the newly created literal segment to the list. */
11596 seg_list
*n
= XNEW (seg_list
);
11598 n
->next
= literal_head
->next
;
11599 literal_head
->next
= n
;
11602 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11603 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11604 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11606 elf_group_name (seg
) = group_name
;
11608 bfd_set_section_flags (stdoutput
, seg
, flags
);
11609 bfd_set_section_alignment (stdoutput
, seg
, 2);
11613 subseg_set (current_section
, current_subsec
);
11618 /* Property Tables Stuff. */
11620 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11621 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11622 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11624 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11625 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11627 static bfd_boolean
get_frag_is_literal (const fragS
*);
11628 static void xtensa_create_property_segments
11629 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11630 static void xtensa_create_xproperty_segments
11631 (frag_flags_fn
, const char *, xt_section_type
);
11632 static bfd_boolean
exclude_section_from_property_tables (segT
);
11633 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11634 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11635 static void add_xt_block_frags
11636 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11637 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11638 static void xtensa_frag_flags_init (frag_flags
*);
11639 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11640 static flagword
frag_flags_to_number (const frag_flags
*);
11641 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11643 /* Set up property tables after relaxation. */
11646 xtensa_post_relax_hook (void)
11648 xtensa_move_seg_list_to_beginning (literal_head
);
11650 xtensa_find_unmarked_state_frags ();
11651 xtensa_mark_frags_for_org ();
11652 xtensa_mark_difference_of_two_symbols ();
11654 xtensa_create_property_segments (get_frag_is_literal
,
11656 XTENSA_LIT_SEC_NAME
,
11658 xtensa_create_xproperty_segments (get_frag_property_flags
,
11659 XTENSA_PROP_SEC_NAME
,
11662 if (warn_unaligned_branch_targets
)
11663 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11664 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11668 /* This function is only meaningful after xtensa_move_literals. */
11671 get_frag_is_literal (const fragS
*fragP
)
11673 gas_assert (fragP
!= NULL
);
11674 return fragP
->tc_frag_data
.is_literal
;
11679 xtensa_create_property_segments (frag_predicate property_function
,
11680 frag_predicate end_property_function
,
11681 const char *section_name_base
,
11682 xt_section_type sec_type
)
11686 /* Walk over all of the current segments.
11687 Walk over each fragment
11688 For each non-empty fragment,
11689 Build a property record (append where possible). */
11691 for (seclist
= &stdoutput
->sections
;
11692 seclist
&& *seclist
;
11693 seclist
= &(*seclist
)->next
)
11695 segT sec
= *seclist
;
11697 if (exclude_section_from_property_tables (sec
))
11700 if (section_has_property (sec
, property_function
))
11702 segment_info_type
*xt_seg_info
;
11703 xtensa_block_info
**xt_blocks
;
11704 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11706 prop_sec
->output_section
= prop_sec
;
11707 subseg_set (prop_sec
, 0);
11708 xt_seg_info
= seg_info (prop_sec
);
11709 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11711 /* Walk over all of the frchains here and add new sections. */
11712 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11713 end_property_function
);
11717 /* Now we fill them out.... */
11719 for (seclist
= &stdoutput
->sections
;
11720 seclist
&& *seclist
;
11721 seclist
= &(*seclist
)->next
)
11723 segment_info_type
*seginfo
;
11724 xtensa_block_info
*block
;
11725 segT sec
= *seclist
;
11727 seginfo
= seg_info (sec
);
11728 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11732 xtensa_block_info
*cur_block
;
11734 bfd_size_type rec_size
;
11736 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11739 rec_size
= num_recs
* 8;
11740 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11747 subseg_set (sec
, 0);
11748 frag_data
= frag_more (rec_size
);
11750 for (i
= 0; i
< num_recs
; i
++)
11754 /* Write the fixup. */
11755 gas_assert (cur_block
);
11756 fix
= fix_new (frag_now
, i
* 8, 4,
11757 section_symbol (cur_block
->sec
),
11759 FALSE
, BFD_RELOC_32
);
11760 fix
->fx_file
= "<internal>";
11763 /* Write the length. */
11764 md_number_to_chars (&frag_data
[4 + i
* 8],
11765 cur_block
->size
, 4);
11766 cur_block
= cur_block
->next
;
11768 frag_wane (frag_now
);
11770 frag_wane (frag_now
);
11778 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11779 const char *section_name_base
,
11780 xt_section_type sec_type
)
11784 /* Walk over all of the current segments.
11785 Walk over each fragment.
11786 For each fragment that has instructions,
11787 build an instruction record (append where possible). */
11789 for (seclist
= &stdoutput
->sections
;
11790 seclist
&& *seclist
;
11791 seclist
= &(*seclist
)->next
)
11793 segT sec
= *seclist
;
11795 if (exclude_section_from_property_tables (sec
))
11798 if (section_has_xproperty (sec
, flag_fn
))
11800 segment_info_type
*xt_seg_info
;
11801 xtensa_block_info
**xt_blocks
;
11802 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11804 prop_sec
->output_section
= prop_sec
;
11805 subseg_set (prop_sec
, 0);
11806 xt_seg_info
= seg_info (prop_sec
);
11807 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11809 /* Walk over all of the frchains here and add new sections. */
11810 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11814 /* Now we fill them out.... */
11816 for (seclist
= &stdoutput
->sections
;
11817 seclist
&& *seclist
;
11818 seclist
= &(*seclist
)->next
)
11820 segment_info_type
*seginfo
;
11821 xtensa_block_info
*block
;
11822 segT sec
= *seclist
;
11824 seginfo
= seg_info (sec
);
11825 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11829 xtensa_block_info
*cur_block
;
11831 bfd_size_type rec_size
;
11833 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11836 rec_size
= num_recs
* (8 + 4);
11837 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11838 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11845 subseg_set (sec
, 0);
11846 frag_data
= frag_more (rec_size
);
11848 for (i
= 0; i
< num_recs
; i
++)
11852 /* Write the fixup. */
11853 gas_assert (cur_block
);
11854 fix
= fix_new (frag_now
, i
* 12, 4,
11855 section_symbol (cur_block
->sec
),
11857 FALSE
, BFD_RELOC_32
);
11858 fix
->fx_file
= "<internal>";
11861 /* Write the length. */
11862 md_number_to_chars (&frag_data
[4 + i
* 12],
11863 cur_block
->size
, 4);
11864 md_number_to_chars (&frag_data
[8 + i
* 12],
11865 frag_flags_to_number (&cur_block
->flags
),
11866 sizeof (flagword
));
11867 cur_block
= cur_block
->next
;
11869 frag_wane (frag_now
);
11871 frag_wane (frag_now
);
11879 exclude_section_from_property_tables (segT sec
)
11881 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11883 /* Sections that don't contribute to the memory footprint are excluded. */
11884 if ((flags
& SEC_DEBUGGING
)
11885 || !(flags
& SEC_ALLOC
)
11886 || (flags
& SEC_MERGE
))
11889 /* Linker cie and fde optimizations mess up property entries for
11890 eh_frame sections, but there is nothing inside them relevant to
11891 property tables anyway. */
11892 if (strcmp (sec
->name
, ".eh_frame") == 0)
11900 section_has_property (segT sec
, frag_predicate property_function
)
11902 segment_info_type
*seginfo
= seg_info (sec
);
11905 if (seginfo
&& seginfo
->frchainP
)
11907 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11909 if (property_function (fragP
)
11910 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11919 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11921 segment_info_type
*seginfo
= seg_info (sec
);
11924 if (seginfo
&& seginfo
->frchainP
)
11926 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11928 frag_flags prop_flags
;
11929 property_function (fragP
, &prop_flags
);
11930 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11938 /* Two types of block sections exist right now: literal and insns. */
11941 add_xt_block_frags (segT sec
,
11942 xtensa_block_info
**xt_block
,
11943 frag_predicate property_function
,
11944 frag_predicate end_property_function
)
11948 /* Build it if needed. */
11949 while (*xt_block
!= NULL
)
11950 xt_block
= &(*xt_block
)->next
;
11951 /* We are either at NULL at the beginning or at the end. */
11953 /* Walk through the frags. */
11954 if (seg_info (sec
)->frchainP
)
11956 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11958 fragP
= fragP
->fr_next
)
11960 if (property_function (fragP
)
11961 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11963 if (*xt_block
!= NULL
)
11965 if ((*xt_block
)->offset
+ (*xt_block
)->size
11966 == fragP
->fr_address
)
11967 (*xt_block
)->size
+= fragP
->fr_fix
;
11969 xt_block
= &((*xt_block
)->next
);
11971 if (*xt_block
== NULL
)
11973 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
11974 new_block
->sec
= sec
;
11975 new_block
->offset
= fragP
->fr_address
;
11976 new_block
->size
= fragP
->fr_fix
;
11977 new_block
->next
= NULL
;
11978 xtensa_frag_flags_init (&new_block
->flags
);
11979 *xt_block
= new_block
;
11981 if (end_property_function
11982 && end_property_function (fragP
))
11984 xt_block
= &((*xt_block
)->next
);
11992 /* Break the encapsulation of add_xt_prop_frags here. */
11995 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
11997 if (prop_flags
->is_literal
11998 || prop_flags
->is_insn
11999 || prop_flags
->is_data
12000 || prop_flags
->is_unreachable
)
12007 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12009 memset (prop_flags
, 0, sizeof (frag_flags
));
12014 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12016 xtensa_frag_flags_init (prop_flags
);
12017 if (fragP
->tc_frag_data
.is_literal
)
12018 prop_flags
->is_literal
= TRUE
;
12019 if (fragP
->tc_frag_data
.is_specific_opcode
12020 || fragP
->tc_frag_data
.is_no_transform
)
12022 prop_flags
->is_no_transform
= TRUE
;
12023 if (xtensa_frag_flags_is_empty (prop_flags
))
12024 prop_flags
->is_data
= TRUE
;
12026 if (fragP
->tc_frag_data
.is_unreachable
)
12027 prop_flags
->is_unreachable
= TRUE
;
12028 else if (fragP
->tc_frag_data
.is_insn
)
12030 prop_flags
->is_insn
= TRUE
;
12031 if (fragP
->tc_frag_data
.is_loop_target
)
12032 prop_flags
->insn
.is_loop_target
= TRUE
;
12033 if (fragP
->tc_frag_data
.is_branch_target
)
12034 prop_flags
->insn
.is_branch_target
= TRUE
;
12035 if (fragP
->tc_frag_data
.is_no_density
)
12036 prop_flags
->insn
.is_no_density
= TRUE
;
12037 if (fragP
->tc_frag_data
.use_absolute_literals
)
12038 prop_flags
->insn
.is_abslit
= TRUE
;
12040 if (fragP
->tc_frag_data
.is_align
)
12042 prop_flags
->is_align
= TRUE
;
12043 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12044 if (xtensa_frag_flags_is_empty (prop_flags
))
12045 prop_flags
->is_data
= TRUE
;
12051 frag_flags_to_number (const frag_flags
*prop_flags
)
12054 if (prop_flags
->is_literal
)
12055 num
|= XTENSA_PROP_LITERAL
;
12056 if (prop_flags
->is_insn
)
12057 num
|= XTENSA_PROP_INSN
;
12058 if (prop_flags
->is_data
)
12059 num
|= XTENSA_PROP_DATA
;
12060 if (prop_flags
->is_unreachable
)
12061 num
|= XTENSA_PROP_UNREACHABLE
;
12062 if (prop_flags
->insn
.is_loop_target
)
12063 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12064 if (prop_flags
->insn
.is_branch_target
)
12066 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12067 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12070 if (prop_flags
->insn
.is_no_density
)
12071 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12072 if (prop_flags
->is_no_transform
)
12073 num
|= XTENSA_PROP_NO_TRANSFORM
;
12074 if (prop_flags
->insn
.is_no_reorder
)
12075 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12076 if (prop_flags
->insn
.is_abslit
)
12077 num
|= XTENSA_PROP_INSN_ABSLIT
;
12079 if (prop_flags
->is_align
)
12081 num
|= XTENSA_PROP_ALIGN
;
12082 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12090 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12091 const frag_flags
*prop_flags_2
)
12093 /* Cannot combine with an end marker. */
12095 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12097 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12099 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12102 if (prop_flags_1
->is_insn
)
12104 /* Properties of the beginning of the frag. */
12105 if (prop_flags_2
->insn
.is_loop_target
)
12107 if (prop_flags_2
->insn
.is_branch_target
)
12109 if (prop_flags_1
->insn
.is_no_density
!=
12110 prop_flags_2
->insn
.is_no_density
)
12112 if (prop_flags_1
->is_no_transform
!=
12113 prop_flags_2
->is_no_transform
)
12115 if (prop_flags_1
->insn
.is_no_reorder
!=
12116 prop_flags_2
->insn
.is_no_reorder
)
12118 if (prop_flags_1
->insn
.is_abslit
!=
12119 prop_flags_2
->insn
.is_abslit
)
12123 if (prop_flags_1
->is_align
)
12131 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12134 unsigned align_bits
;
12136 if (!xt_block
->flags
.is_align
)
12137 return xt_block
->size
;
12139 end_addr
= xt_block
->offset
+ xt_block
->size
;
12140 align_bits
= xt_block
->flags
.alignment
;
12141 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12142 return end_addr
- xt_block
->offset
;
12147 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12148 const xtensa_block_info
*xt_block_2
)
12150 if (xt_block
->sec
!= xt_block_2
->sec
)
12152 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12153 != xt_block_2
->offset
)
12156 if (xt_block_2
->size
== 0
12157 && (!xt_block_2
->flags
.is_unreachable
12158 || xt_block
->flags
.is_unreachable
))
12160 if (xt_block_2
->flags
.is_align
12161 && xt_block
->flags
.is_align
)
12163 /* Nothing needed. */
12164 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12169 if (xt_block_2
->flags
.is_align
)
12171 /* Push alignment to previous entry. */
12172 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12173 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12178 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12179 &xt_block_2
->flags
))
12182 xt_block
->size
+= xt_block_2
->size
;
12184 if (xt_block_2
->flags
.is_align
)
12186 xt_block
->flags
.is_align
= TRUE
;
12187 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12195 add_xt_prop_frags (segT sec
,
12196 xtensa_block_info
**xt_block
,
12197 frag_flags_fn property_function
)
12201 /* Build it if needed. */
12202 while (*xt_block
!= NULL
)
12204 xt_block
= &(*xt_block
)->next
;
12206 /* We are either at NULL at the beginning or at the end. */
12208 /* Walk through the frags. */
12209 if (seg_info (sec
)->frchainP
)
12211 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12212 fragP
= fragP
->fr_next
)
12214 xtensa_block_info tmp_block
;
12215 tmp_block
.sec
= sec
;
12216 tmp_block
.offset
= fragP
->fr_address
;
12217 tmp_block
.size
= fragP
->fr_fix
;
12218 tmp_block
.next
= NULL
;
12219 property_function (fragP
, &tmp_block
.flags
);
12221 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12222 /* && fragP->fr_fix != 0) */
12224 if ((*xt_block
) == NULL
12225 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12227 xtensa_block_info
*new_block
;
12228 if ((*xt_block
) != NULL
)
12229 xt_block
= &(*xt_block
)->next
;
12230 new_block
= XNEW (xtensa_block_info
);
12231 *new_block
= tmp_block
;
12232 *xt_block
= new_block
;
12240 /* op_placement_info_table */
12242 /* op_placement_info makes it easier to determine which
12243 ops can go in which slots. */
12246 init_op_placement_info_table (void)
12248 xtensa_isa isa
= xtensa_default_isa
;
12249 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12250 xtensa_opcode opcode
;
12253 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12255 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12256 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12258 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12260 op_placement_info
*opi
= &op_placement_table
[opcode
];
12261 /* FIXME: Make tinsn allocation dynamic. */
12262 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12263 as_fatal (_("too many operands in instruction"));
12264 opi
->narrowest
= XTENSA_UNDEFINED
;
12265 opi
->narrowest_size
= 0x7F;
12266 opi
->narrowest_slot
= 0;
12268 opi
->num_formats
= 0;
12270 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12272 opi
->slots
[fmt
] = 0;
12273 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12275 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12277 int fmt_length
= xtensa_format_length (isa
, fmt
);
12279 set_bit (fmt
, opi
->formats
);
12280 set_bit (slot
, opi
->slots
[fmt
]);
12281 if (fmt_length
< opi
->narrowest_size
12282 || (fmt_length
== opi
->narrowest_size
12283 && (xtensa_format_num_slots (isa
, fmt
)
12284 < xtensa_format_num_slots (isa
,
12287 opi
->narrowest
= fmt
;
12288 opi
->narrowest_size
= fmt_length
;
12289 opi
->narrowest_slot
= slot
;
12294 opi
->num_formats
++;
12297 xtensa_insnbuf_free (isa
, ibuf
);
12302 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12304 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12308 /* If the opcode is available in a single slot format, return its size. */
12311 xg_get_single_size (xtensa_opcode opcode
)
12313 return op_placement_table
[opcode
].narrowest_size
;
12317 static xtensa_format
12318 xg_get_single_format (xtensa_opcode opcode
)
12320 return op_placement_table
[opcode
].narrowest
;
12325 xg_get_single_slot (xtensa_opcode opcode
)
12327 return op_placement_table
[opcode
].narrowest_slot
;
12331 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12334 istack_init (IStack
*stack
)
12341 istack_empty (IStack
*stack
)
12343 return (stack
->ninsn
== 0);
12348 istack_full (IStack
*stack
)
12350 return (stack
->ninsn
== MAX_ISTACK
);
12354 /* Return a pointer to the top IStack entry.
12355 It is an error to call this if istack_empty () is TRUE. */
12358 istack_top (IStack
*stack
)
12360 int rec
= stack
->ninsn
- 1;
12361 gas_assert (!istack_empty (stack
));
12362 return &stack
->insn
[rec
];
12366 /* Add a new TInsn to an IStack.
12367 It is an error to call this if istack_full () is TRUE. */
12370 istack_push (IStack
*stack
, TInsn
*insn
)
12372 int rec
= stack
->ninsn
;
12373 gas_assert (!istack_full (stack
));
12374 stack
->insn
[rec
] = *insn
;
12379 /* Clear space for the next TInsn on the IStack and return a pointer
12380 to it. It is an error to call this if istack_full () is TRUE. */
12383 istack_push_space (IStack
*stack
)
12385 int rec
= stack
->ninsn
;
12387 gas_assert (!istack_full (stack
));
12388 insn
= &stack
->insn
[rec
];
12395 /* Remove the last pushed instruction. It is an error to call this if
12396 istack_empty () returns TRUE. */
12399 istack_pop (IStack
*stack
)
12401 int rec
= stack
->ninsn
- 1;
12402 gas_assert (!istack_empty (stack
));
12404 tinsn_init (&stack
->insn
[rec
]);
12408 /* TInsn functions. */
12411 tinsn_init (TInsn
*dst
)
12413 memset (dst
, 0, sizeof (TInsn
));
12417 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12420 tinsn_has_symbolic_operands (const TInsn
*insn
)
12423 int n
= insn
->ntok
;
12425 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12427 for (i
= 0; i
< n
; ++i
)
12429 switch (insn
->tok
[i
].X_op
)
12443 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12445 xtensa_isa isa
= xtensa_default_isa
;
12447 int n
= insn
->ntok
;
12449 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12451 for (i
= 0; i
< n
; ++i
)
12453 switch (insn
->tok
[i
].X_op
)
12461 /* Errors for these types are caught later. */
12466 /* Symbolic immediates are only allowed on the last immediate
12467 operand. At this time, CONST16 is the only opcode where we
12468 support non-PC-relative relocations. */
12469 if (i
!= get_relaxable_immed (insn
->opcode
)
12470 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12471 && insn
->opcode
!= xtensa_const16_opcode
))
12473 as_bad (_("invalid symbolic operand"));
12482 /* For assembly code with complex expressions (e.g. subtraction),
12483 we have to build them in the literal pool so that
12484 their results are calculated correctly after relaxation.
12485 The relaxation only handles expressions that
12486 boil down to SYMBOL + OFFSET. */
12489 tinsn_has_complex_operands (const TInsn
*insn
)
12492 int n
= insn
->ntok
;
12493 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12494 for (i
= 0; i
< n
; ++i
)
12496 switch (insn
->tok
[i
].X_op
)
12512 /* Encode a TInsn opcode and its constant operands into slotbuf.
12513 Return TRUE if there is a symbol in the immediate field. This
12514 function assumes that:
12515 1) The number of operands are correct.
12516 2) The insn_type is ITYPE_INSN.
12517 3) The opcode can be encoded in the specified format and slot.
12518 4) Operands are either O_constant or O_symbol, and all constants fit. */
12521 tinsn_to_slotbuf (xtensa_format fmt
,
12524 xtensa_insnbuf slotbuf
)
12526 xtensa_isa isa
= xtensa_default_isa
;
12527 xtensa_opcode opcode
= tinsn
->opcode
;
12528 bfd_boolean has_fixup
= FALSE
;
12529 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12532 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12533 if (noperands
!= tinsn
->ntok
)
12534 as_fatal (_("operand number mismatch"));
12536 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12538 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12539 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12543 for (i
= 0; i
< noperands
; i
++)
12545 expressionS
*exp
= &tinsn
->tok
[i
];
12548 const char *file_name
;
12554 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12556 /* The register number has already been checked in
12557 expression_maybe_register, so we don't need to check here. */
12558 opnd_value
= exp
->X_add_number
;
12559 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12560 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12563 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12567 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12569 file_name
= as_where (&line
);
12570 /* It is a constant and we called this function
12571 then we have to try to fit it. */
12572 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12573 exp
->X_add_number
, file_name
, line
);
12586 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12587 into a multi-slot instruction, fill the other slots with NOPs.
12588 Return TRUE if there is a symbol in the immediate field. See also the
12589 assumptions listed for tinsn_to_slotbuf. */
12592 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12594 static xtensa_insnbuf slotbuf
= 0;
12595 static vliw_insn vinsn
;
12596 xtensa_isa isa
= xtensa_default_isa
;
12597 bfd_boolean has_fixup
= FALSE
;
12602 slotbuf
= xtensa_insnbuf_alloc (isa
);
12603 xg_init_vinsn (&vinsn
);
12606 xg_clear_vinsn (&vinsn
);
12608 bundle_tinsn (tinsn
, &vinsn
);
12610 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12612 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12614 /* Only one slot may have a fix-up because the rest contains NOPs. */
12616 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12617 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12624 /* Check the instruction arguments. Return TRUE on failure. */
12627 tinsn_check_arguments (const TInsn
*insn
)
12629 xtensa_isa isa
= xtensa_default_isa
;
12630 xtensa_opcode opcode
= insn
->opcode
;
12631 xtensa_regfile t1_regfile
, t2_regfile
;
12632 int t1_reg
, t2_reg
;
12633 int t1_base_reg
, t1_last_reg
;
12634 int t2_base_reg
, t2_last_reg
;
12635 char t1_inout
, t2_inout
;
12638 if (opcode
== XTENSA_UNDEFINED
)
12640 as_bad (_("invalid opcode"));
12644 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12646 as_bad (_("too few operands"));
12650 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12652 as_bad (_("too many operands"));
12656 /* Check registers. */
12657 for (j
= 0; j
< insn
->ntok
; j
++)
12659 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12662 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12663 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12665 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12667 for (i
= 0; i
< insn
->ntok
; i
++)
12672 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12675 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12677 if (t1_regfile
!= t2_regfile
)
12680 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12681 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12683 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12684 t1_last_reg
= (t1_base_reg
12685 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12687 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12689 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12691 if (t1_reg
!= t2_reg
)
12694 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12696 as_bad (_("multiple writes to the same register"));
12707 /* Load an instruction from its encoded form. */
12710 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12714 xg_init_vinsn (&vinsn
);
12715 vinsn_from_chars (&vinsn
, f
);
12717 *tinsn
= vinsn
.slots
[slot
];
12718 xg_free_vinsn (&vinsn
);
12723 tinsn_from_insnbuf (TInsn
*tinsn
,
12724 xtensa_insnbuf slotbuf
,
12729 xtensa_isa isa
= xtensa_default_isa
;
12731 /* Find the immed. */
12732 tinsn_init (tinsn
);
12733 tinsn
->insn_type
= ITYPE_INSN
;
12734 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12735 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12736 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12737 for (i
= 0; i
< tinsn
->ntok
; i
++)
12739 set_expr_const (&tinsn
->tok
[i
],
12740 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12741 tinsn
->opcode
, i
));
12746 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12749 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12751 xtensa_opcode opcode
= tinsn
->opcode
;
12754 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12756 opnum
= get_relaxable_immed (opcode
);
12757 gas_assert (opnum
>= 0);
12758 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12759 fragP
->tc_frag_data
.slot_symbols
[slot
],
12760 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12762 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12767 get_num_stack_text_bytes (IStack
*istack
)
12770 int text_bytes
= 0;
12772 for (i
= 0; i
< istack
->ninsn
; i
++)
12774 TInsn
*tinsn
= &istack
->insn
[i
];
12775 if (tinsn
->insn_type
== ITYPE_INSN
)
12776 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12783 get_num_stack_literal_bytes (IStack
*istack
)
12788 for (i
= 0; i
< istack
->ninsn
; i
++)
12790 TInsn
*tinsn
= &istack
->insn
[i
];
12791 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12798 /* vliw_insn functions. */
12801 xg_init_vinsn (vliw_insn
*v
)
12804 xtensa_isa isa
= xtensa_default_isa
;
12806 xg_clear_vinsn (v
);
12808 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12809 if (v
->insnbuf
== NULL
)
12810 as_fatal (_("out of memory"));
12812 for (i
= 0; i
< config_max_slots
; i
++)
12814 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12815 if (v
->slotbuf
[i
] == NULL
)
12816 as_fatal (_("out of memory"));
12822 xg_clear_vinsn (vliw_insn
*v
)
12826 memset (v
, 0, offsetof (vliw_insn
, slots
)
12827 + sizeof(TInsn
) * config_max_slots
);
12829 v
->format
= XTENSA_UNDEFINED
;
12831 v
->inside_bundle
= FALSE
;
12833 if (xt_saved_debug_type
!= DEBUG_NONE
)
12834 debug_type
= xt_saved_debug_type
;
12836 for (i
= 0; i
< config_max_slots
; i
++)
12837 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12842 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12845 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12846 dst
->insnbuf
= src
->insnbuf
;
12847 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12852 vinsn_has_specific_opcodes (vliw_insn
*v
)
12856 for (i
= 0; i
< v
->num_slots
; i
++)
12858 if (v
->slots
[i
].is_specific_opcode
)
12866 xg_free_vinsn (vliw_insn
*v
)
12869 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12870 for (i
= 0; i
< config_max_slots
; i
++)
12871 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12875 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12876 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12879 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12882 bfd_boolean record_fixup
)
12884 xtensa_isa isa
= xtensa_default_isa
;
12885 xtensa_format fmt
= vinsn
->format
;
12886 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12888 bfd_boolean has_fixup
= FALSE
;
12890 xtensa_format_encode (isa
, fmt
, insnbuf
);
12892 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12894 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12895 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12896 bfd_boolean tinsn_has_fixup
=
12897 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12898 vinsn
->slotbuf
[slot
]);
12900 xtensa_format_set_slot (isa
, fmt
, slot
,
12901 insnbuf
, vinsn
->slotbuf
[slot
]);
12902 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12904 if (vinsn
->num_slots
!= 1)
12905 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12906 else if (record_fixup
)
12907 /* Instructions that generate TLS relocations should always be
12908 relaxed in the front-end. If "record_fixup" is set, then this
12909 function is being called during back-end relaxation, so flag
12910 the unexpected behavior as an error. */
12911 as_bad (_("unexpected TLS relocation"));
12913 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12914 xtensa_format_length (isa
, fmt
),
12915 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12916 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12918 if (tinsn_has_fixup
)
12921 xtensa_opcode opcode
= tinsn
->opcode
;
12922 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12925 for (i
= 0; i
< noperands
; i
++)
12927 expressionS
* exp
= &tinsn
->tok
[i
];
12933 if (get_relaxable_immed (opcode
) == i
)
12935 /* Add a fix record for the instruction, except if this
12936 function is being called prior to relaxation, i.e.,
12937 if record_fixup is false, and the instruction might
12938 be relaxed later. */
12940 || tinsn
->is_specific_opcode
12941 || !xg_is_relaxable_insn (tinsn
, 0))
12943 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12944 frag_offset
- fragP
->fr_literal
);
12948 if (exp
->X_op
!= O_symbol
)
12949 as_bad (_("invalid operand"));
12950 tinsn
->symbol
= exp
->X_add_symbol
;
12951 tinsn
->offset
= exp
->X_add_number
;
12955 as_bad (_("symbolic operand not allowed"));
12963 as_bad (_("expression too complex"));
12975 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
12977 static xtensa_insnbuf insnbuf
= NULL
;
12978 static xtensa_insnbuf slotbuf
= NULL
;
12981 xtensa_isa isa
= xtensa_default_isa
;
12985 insnbuf
= xtensa_insnbuf_alloc (isa
);
12986 slotbuf
= xtensa_insnbuf_alloc (isa
);
12989 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
12990 fmt
= xtensa_format_decode (isa
, insnbuf
);
12991 if (fmt
== XTENSA_UNDEFINED
)
12992 as_fatal (_("cannot decode instruction format"));
12993 vinsn
->format
= fmt
;
12994 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
12996 for (i
= 0; i
< vinsn
->num_slots
; i
++)
12998 TInsn
*tinsn
= &vinsn
->slots
[i
];
12999 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13000 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13005 /* Expression utilities. */
13007 /* Return TRUE if the expression is an integer constant. */
13010 expr_is_const (const expressionS
*s
)
13012 return (s
->X_op
== O_constant
);
13016 /* Get the expression constant.
13017 Calling this is illegal if expr_is_const () returns TRUE. */
13020 get_expr_const (const expressionS
*s
)
13022 gas_assert (expr_is_const (s
));
13023 return s
->X_add_number
;
13027 /* Set the expression to a constant value. */
13030 set_expr_const (expressionS
*s
, offsetT val
)
13032 s
->X_op
= O_constant
;
13033 s
->X_add_number
= val
;
13034 s
->X_add_symbol
= NULL
;
13035 s
->X_op_symbol
= NULL
;
13040 expr_is_register (const expressionS
*s
)
13042 return (s
->X_op
== O_register
);
13046 /* Get the expression constant.
13047 Calling this is illegal if expr_is_const () returns TRUE. */
13050 get_expr_register (const expressionS
*s
)
13052 gas_assert (expr_is_register (s
));
13053 return s
->X_add_number
;
13057 /* Set the expression to a symbol + constant offset. */
13060 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13062 s
->X_op
= O_symbol
;
13063 s
->X_add_symbol
= sym
;
13064 s
->X_op_symbol
= NULL
; /* unused */
13065 s
->X_add_number
= offset
;
13069 /* Return TRUE if the two expressions are equal. */
13072 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13074 if (s1
->X_op
!= s2
->X_op
)
13076 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13078 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13080 if (s1
->X_add_number
!= s2
->X_add_number
)
13087 copy_expr (expressionS
*dst
, const expressionS
*src
)
13089 memcpy (dst
, src
, sizeof (expressionS
));
13093 /* Support for the "--rename-section" option. */
13095 struct rename_section_struct
13097 const char *old_name
;
13099 struct rename_section_struct
*next
;
13102 static struct rename_section_struct
*section_rename
;
13105 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13106 entries to the section_rename list. Note: Specifying multiple
13107 renamings separated by colons is not documented and is retained only
13108 for backward compatibility. */
13111 build_section_rename (const char *arg
)
13113 struct rename_section_struct
*r
;
13114 char *this_arg
= NULL
;
13115 char *next_arg
= NULL
;
13117 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13119 char *old_name
, *new_name
;
13123 next_arg
= strchr (this_arg
, ':');
13131 old_name
= this_arg
;
13132 new_name
= strchr (this_arg
, '=');
13134 if (*old_name
== '\0')
13136 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13139 if (!new_name
|| new_name
[1] == '\0')
13141 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13148 /* Check for invalid section renaming. */
13149 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13151 if (strcmp (r
->old_name
, old_name
) == 0)
13152 as_bad (_("section %s renamed multiple times"), old_name
);
13153 if (strcmp (r
->new_name
, new_name
) == 0)
13154 as_bad (_("multiple sections remapped to output section %s"),
13159 r
= XNEW (struct rename_section_struct
);
13160 r
->old_name
= xstrdup (old_name
);
13161 r
->new_name
= xstrdup (new_name
);
13162 r
->next
= section_rename
;
13163 section_rename
= r
;
13169 xtensa_section_rename (const char *name
)
13171 struct rename_section_struct
*r
= section_rename
;
13173 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13175 if (strcmp (r
->old_name
, name
) == 0)
13176 return r
->new_name
;
13179 return (char *) name
;