1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
32 #include "elf/xtensa.h"
34 /* Provide default values for new configuration settings. */
40 #define uint32 unsigned int
43 #define int32 signed int
48 Naming conventions (used somewhat inconsistently):
49 The xtensa_ functions are exported
50 The xg_ functions are internal
52 We also have a couple of different extensibility mechanisms.
53 1) The idiom replacement:
54 This is used when a line is first parsed to
55 replace an instruction pattern with another instruction
56 It is currently limited to replacements of instructions
57 with constant operands.
58 2) The xtensa-relax.c mechanism that has stronger instruction
59 replacement patterns. When an instruction's immediate field
60 does not fit the next instruction sequence is attempted.
61 In addition, "narrow" opcodes are supported this way. */
64 /* Define characters with special meanings to GAS. */
65 const char comment_chars
[] = "#";
66 const char line_comment_chars
[] = "#";
67 const char line_separator_chars
[] = ";";
68 const char EXP_CHARS
[] = "eE";
69 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
72 /* Flags to indicate whether the hardware supports the density and
73 absolute literals options. */
75 bfd_boolean density_supported
;
76 bfd_boolean absolute_literals_supported
;
78 static vliw_insn cur_vinsn
;
80 unsigned xtensa_num_pipe_stages
;
81 unsigned xtensa_fetch_width
;
83 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
85 /* Some functions are only valid in the front end. This variable
86 allows us to assert that we haven't crossed over into the
88 static bfd_boolean past_xtensa_end
= FALSE
;
90 /* Flags for properties of the last instruction in a segment. */
91 #define FLAG_IS_A0_WRITER 0x1
92 #define FLAG_IS_BAD_LOOPEND 0x2
95 /* We define a special segment names ".literal" to place literals
96 into. The .fini and .init sections are special because they
97 contain code that is moved together by the linker. We give them
98 their own special .fini.literal and .init.literal sections. */
100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. If lit_prefix is set, it is
108 used to determine the literal section names; otherwise, the literal
109 sections are determined based on the current text section. The
110 lit_seg and lit4_seg fields cache these literal sections, with the
111 current_text_seg field used a tag to indicate whether the cached
114 typedef struct lit_state_struct
117 segT current_text_seg
;
122 static lit_state default_lit_sections
;
125 /* We keep a list of literal segments. The seg_list type is the node
126 for this list. The literal_head pointer is the head of the list,
127 with the literal_head_h dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
139 /* Lists of symbols. We keep a list of symbols that label the current
140 instruction, so that we can adjust the symbols when inserting alignment
141 for various instructions. We also keep a list of all the symbols on
142 literals, so that we can fix up those symbols when the literals are
143 later moved into the text sections. */
145 typedef struct sym_list_struct
147 struct sym_list_struct
*next
;
151 static sym_list
*insn_labels
= NULL
;
152 static sym_list
*free_insn_labels
= NULL
;
153 static sym_list
*saved_insn_labels
= NULL
;
155 static sym_list
*literal_syms
;
158 /* Flags to determine whether to prefer const16 or l32r
159 if both options are available. */
160 int prefer_const16
= 0;
163 /* Global flag to indicate when we are emitting literals. */
164 int generating_literals
= 0;
166 /* The following PROPERTY table definitions are copied from
167 <elf/xtensa.h> and must be kept in sync with the code there. */
169 /* Flags in the property tables to specify whether blocks of memory
170 are literals, instructions, data, or unreachable. For
171 instructions, blocks that begin loop targets and branch targets are
172 designated. Blocks that do not allow density, instruction
173 reordering or transformation are also specified. Finally, for
174 branch targets, branch target alignment priority is included.
175 Alignment of the next block is specified in the current block
176 and the size of the current block does not include any fill required
177 to align to the next block. */
179 #define XTENSA_PROP_LITERAL 0x00000001
180 #define XTENSA_PROP_INSN 0x00000002
181 #define XTENSA_PROP_DATA 0x00000004
182 #define XTENSA_PROP_UNREACHABLE 0x00000008
183 /* Instruction only properties at beginning of code. */
184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
186 /* Instruction only properties about code. */
187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190 but it should apply to literals under certain circumstances. */
191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
193 /* Branch target alignment information. This transmits information
194 to the linker optimization about the priority of aligning a
195 particular block for branch target alignment: None, low priority,
196 high priority, or required. These only need to be checked in
197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201 case XTENSA_PROP_BT_ALIGN_NONE:
202 case XTENSA_PROP_BT_ALIGN_LOW:
203 case XTENSA_PROP_BT_ALIGN_HIGH:
204 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208 /* No branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
210 /* Low priority branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
212 /* High priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
214 /* Required branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
218 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
219 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
222 /* Alignment is specified in the block BEFORE the one that needs
223 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
224 get the required alignment specified as a power of 2. Use
225 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
226 alignment. Be careful of side effects since the SET will evaluate
227 flags twice. Also, note that the SIZE of a block in the property
228 table does not include the alignment size, so the alignment fill
229 must be calculated to determine if two blocks are contiguous.
230 TEXT_ALIGN is not currently implemented but is a placeholder for a
231 possible future implementation. */
233 #define XTENSA_PROP_ALIGN 0x00000800
235 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
237 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
238 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
239 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
241 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
244 /* Structure for saving instruction and alignment per-fragment data
245 that will be written to the object file. This structure is
246 equivalent to the actual data that will be written out to the file
247 but is easier to use. We provide a conversion to file flags
248 in frag_flags_to_number. */
250 typedef struct frag_flags_struct frag_flags
;
252 struct frag_flags_struct
254 /* is_literal should only be used after xtensa_move_literals.
255 If you need to check if you are generating a literal fragment,
256 then use the generating_literals global. */
258 unsigned is_literal
: 1;
259 unsigned is_insn
: 1;
260 unsigned is_data
: 1;
261 unsigned is_unreachable
: 1;
263 /* is_specific_opcode implies no_transform. */
264 unsigned is_no_transform
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
275 unsigned is_no_reorder
: 1;
277 /* Uses absolute literal addressing for l32r. */
278 unsigned is_abslit
: 1;
280 unsigned is_align
: 1;
281 unsigned alignment
: 5;
285 /* Structure for saving information about a block of property data
286 for frags that have the same flags. */
287 struct xtensa_block_info_struct
293 struct xtensa_block_info_struct
*next
;
297 /* Structure for saving the current state before emitting literals. */
298 typedef struct emit_state_struct
303 int generating_literals
;
307 /* Opcode placement information */
309 typedef unsigned long long bitfield
;
310 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
311 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
312 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
314 #define MAX_FORMATS 32
316 typedef struct op_placement_info_struct
319 /* A number describing how restrictive the issue is for this
320 opcode. For example, an opcode that fits lots of different
321 formats has a high freedom, as does an opcode that fits
322 only one format but many slots in that format. The most
323 restrictive is the opcode that fits only one slot in one
326 xtensa_format narrowest
;
330 /* formats is a bitfield with the Nth bit set
331 if the opcode fits in the Nth xtensa_format. */
334 /* slots[N]'s Mth bit is set if the op fits in the
335 Mth slot of the Nth xtensa_format. */
336 bitfield slots
[MAX_FORMATS
];
338 /* A count of the number of slots in a given format
339 an op can fit (i.e., the bitcount of the slot field above). */
340 char slots_in_format
[MAX_FORMATS
];
342 } op_placement_info
, *op_placement_info_table
;
344 op_placement_info_table op_placement_table
;
347 /* Extra expression types. */
349 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
350 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
351 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
352 #define O_pcrel O_md4 /* value is a PC-relative offset */
353 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
354 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
355 #define O_tlscall O_md7 /* TLS_CALL relocation */
356 #define O_tpoff O_md8 /* TPOFF relocation */
357 #define O_dtpoff O_md9 /* DTPOFF relocation */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
376 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
377 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
378 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
379 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
393 directive_literal_prefix
,
395 directive_absolute_literals
,
396 directive_last_directive
402 bfd_boolean can_be_negated
;
405 const directive_infoS directive_info
[] =
408 { "literal", FALSE
},
410 { "transform", TRUE
},
411 { "freeregs", FALSE
},
412 { "longcalls", TRUE
},
413 { "literal_prefix", FALSE
},
414 { "schedule", TRUE
},
415 { "absolute-literals", TRUE
}
418 bfd_boolean directive_state
[] =
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 FALSE
/* absolute_literals */
431 /* A circular list of all potential and actual literal pool locations
435 struct litpool_frag
*next
;
436 struct litpool_frag
*prev
;
439 short priority
; /* 1, 2, or 3 -- 1 is highest */
440 short original_priority
;
444 /* Map a segment to its litpool_frag list. */
447 struct litpool_seg
*next
;
449 struct litpool_frag frag_list
;
450 int frag_count
; /* since last litpool location */
453 static struct litpool_seg litpool_seg_list
;
455 /* Limit maximal size of auto litpool by half of the j range. */
456 #define MAX_AUTO_POOL_LITERALS 16384
458 /* Limit maximal size of explicit literal pool by l32r range. */
459 #define MAX_EXPLICIT_POOL_LITERALS 65536
461 #define MAX_POOL_LITERALS \
462 (auto_litpools ? MAX_AUTO_POOL_LITERALS : MAX_EXPLICIT_POOL_LITERALS)
464 /* Directive functions. */
466 static void xtensa_begin_directive (int);
467 static void xtensa_end_directive (int);
468 static void xtensa_literal_prefix (void);
469 static void xtensa_literal_position (int);
470 static void xtensa_literal_pseudo (int);
471 static void xtensa_frequency_pseudo (int);
472 static void xtensa_elf_cons (int);
473 static void xtensa_leb128 (int);
475 /* Parsing and Idiom Translation. */
477 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
479 /* Various Other Internal Functions. */
481 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
482 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
483 static void xtensa_mark_literal_pool_location (void);
484 static addressT
get_expanded_loop_offset (xtensa_opcode
);
485 static fragS
*get_literal_pool_location (segT
);
486 static void set_literal_pool_location (segT
, fragS
*);
487 static void xtensa_set_frag_assembly_state (fragS
*);
488 static void finish_vinsn (vliw_insn
*);
489 static bfd_boolean
emit_single_op (TInsn
*);
490 static int total_frag_text_expansion (fragS
*);
491 static bfd_boolean use_trampolines
= TRUE
;
492 static void xtensa_check_frag_count (void);
493 static void xtensa_create_trampoline_frag (bfd_boolean
);
494 static void xtensa_maybe_create_trampoline_frag (void);
495 struct trampoline_frag
;
496 static int init_trampoline_frag (fragS
*);
497 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
);
498 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
499 static bfd_boolean auto_litpools
= FALSE
;
500 static int auto_litpool_limit
= 0;
502 /* Alignment Functions. */
504 static int get_text_align_power (unsigned);
505 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
506 static int branch_align_power (segT
);
508 /* Helpers for xtensa_relax_frag(). */
510 static long relax_frag_add_nop (fragS
*);
512 /* Accessors for additional per-subsegment information. */
514 static unsigned get_last_insn_flags (segT
, subsegT
);
515 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
516 static float get_subseg_total_freq (segT
, subsegT
);
517 static float get_subseg_target_freq (segT
, subsegT
);
518 static void set_subseg_freq (segT
, subsegT
, float, float);
520 /* Segment list functions. */
522 static void xtensa_move_literals (void);
523 static void xtensa_reorder_segments (void);
524 static void xtensa_switch_to_literal_fragment (emit_state
*);
525 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
526 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
527 static void xtensa_restore_emit_state (emit_state
*);
528 static segT
cache_literal_section (bfd_boolean
);
530 /* op_placement_info functions. */
532 static void init_op_placement_info_table (void);
533 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
534 static int xg_get_single_size (xtensa_opcode
);
535 static xtensa_format
xg_get_single_format (xtensa_opcode
);
536 static int xg_get_single_slot (xtensa_opcode
);
538 /* TInsn and IStack functions. */
540 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
541 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
542 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
543 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
544 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
545 static void tinsn_from_chars (TInsn
*, char *, int);
546 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
547 static int get_num_stack_text_bytes (IStack
*);
548 static int get_num_stack_literal_bytes (IStack
*);
549 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
551 /* vliw_insn functions. */
553 static void xg_init_vinsn (vliw_insn
*);
554 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
555 static void xg_clear_vinsn (vliw_insn
*);
556 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
557 static void xg_free_vinsn (vliw_insn
*);
558 static bfd_boolean vinsn_to_insnbuf
559 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
560 static void vinsn_from_chars (vliw_insn
*, char *);
562 /* Expression Utilities. */
564 bfd_boolean
expr_is_const (const expressionS
*);
565 offsetT
get_expr_const (const expressionS
*);
566 void set_expr_const (expressionS
*, offsetT
);
567 bfd_boolean
expr_is_register (const expressionS
*);
568 offsetT
get_expr_register (const expressionS
*);
569 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
570 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
571 static void copy_expr (expressionS
*, const expressionS
*);
573 /* Section renaming. */
575 static void build_section_rename (const char *);
578 /* ISA imported from bfd. */
579 extern xtensa_isa xtensa_default_isa
;
581 extern int target_big_endian
;
583 static xtensa_opcode xtensa_addi_opcode
;
584 static xtensa_opcode xtensa_addmi_opcode
;
585 static xtensa_opcode xtensa_call0_opcode
;
586 static xtensa_opcode xtensa_call4_opcode
;
587 static xtensa_opcode xtensa_call8_opcode
;
588 static xtensa_opcode xtensa_call12_opcode
;
589 static xtensa_opcode xtensa_callx0_opcode
;
590 static xtensa_opcode xtensa_callx4_opcode
;
591 static xtensa_opcode xtensa_callx8_opcode
;
592 static xtensa_opcode xtensa_callx12_opcode
;
593 static xtensa_opcode xtensa_const16_opcode
;
594 static xtensa_opcode xtensa_entry_opcode
;
595 static xtensa_opcode xtensa_extui_opcode
;
596 static xtensa_opcode xtensa_movi_opcode
;
597 static xtensa_opcode xtensa_movi_n_opcode
;
598 static xtensa_opcode xtensa_isync_opcode
;
599 static xtensa_opcode xtensa_j_opcode
;
600 static xtensa_opcode xtensa_jx_opcode
;
601 static xtensa_opcode xtensa_l32r_opcode
;
602 static xtensa_opcode xtensa_loop_opcode
;
603 static xtensa_opcode xtensa_loopnez_opcode
;
604 static xtensa_opcode xtensa_loopgtz_opcode
;
605 static xtensa_opcode xtensa_nop_opcode
;
606 static xtensa_opcode xtensa_nop_n_opcode
;
607 static xtensa_opcode xtensa_or_opcode
;
608 static xtensa_opcode xtensa_ret_opcode
;
609 static xtensa_opcode xtensa_ret_n_opcode
;
610 static xtensa_opcode xtensa_retw_opcode
;
611 static xtensa_opcode xtensa_retw_n_opcode
;
612 static xtensa_opcode xtensa_rsr_lcount_opcode
;
613 static xtensa_opcode xtensa_waiti_opcode
;
614 static int config_max_slots
= 0;
617 /* Command-line Options. */
619 bfd_boolean use_literal_section
= TRUE
;
620 enum flix_level produce_flix
= FLIX_ALL
;
621 static bfd_boolean align_targets
= TRUE
;
622 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
623 static bfd_boolean has_a0_b_retw
= FALSE
;
624 static bfd_boolean workaround_a0_b_retw
= FALSE
;
625 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
626 static bfd_boolean workaround_short_loop
= FALSE
;
627 static bfd_boolean maybe_has_short_loop
= FALSE
;
628 static bfd_boolean workaround_close_loop_end
= FALSE
;
629 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
630 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
632 /* When workaround_short_loops is TRUE, all loops with early exits must
633 have at least 3 instructions. workaround_all_short_loops is a modifier
634 to the workaround_short_loop flag. In addition to the
635 workaround_short_loop actions, all straightline loopgtz and loopnez
636 must have at least 3 instructions. */
638 static bfd_boolean workaround_all_short_loops
= FALSE
;
642 xtensa_setup_hw_workarounds (int earliest
, int latest
)
644 if (earliest
> latest
)
645 as_fatal (_("illegal range of target hardware versions"));
647 /* Enable all workarounds for pre-T1050.0 hardware. */
648 if (earliest
< 105000 || latest
< 105000)
650 workaround_a0_b_retw
|= TRUE
;
651 workaround_b_j_loop_end
|= TRUE
;
652 workaround_short_loop
|= TRUE
;
653 workaround_close_loop_end
|= TRUE
;
654 workaround_all_short_loops
|= TRUE
;
655 enforce_three_byte_loop_align
= TRUE
;
662 option_density
= OPTION_MD_BASE
,
666 option_no_generate_flix
,
673 option_no_link_relax
,
681 option_text_section_literals
,
682 option_no_text_section_literals
,
684 option_absolute_literals
,
685 option_no_absolute_literals
,
687 option_align_targets
,
688 option_no_align_targets
,
690 option_warn_unaligned_targets
,
695 option_workaround_a0_b_retw
,
696 option_no_workaround_a0_b_retw
,
698 option_workaround_b_j_loop_end
,
699 option_no_workaround_b_j_loop_end
,
701 option_workaround_short_loop
,
702 option_no_workaround_short_loop
,
704 option_workaround_all_short_loops
,
705 option_no_workaround_all_short_loops
,
707 option_workaround_close_loop_end
,
708 option_no_workaround_close_loop_end
,
710 option_no_workarounds
,
712 option_rename_section_name
,
715 option_prefer_const16
,
717 option_target_hardware
,
720 option_no_trampolines
,
722 option_auto_litpools
,
723 option_no_auto_litpools
,
724 option_auto_litpool_limit
,
727 const char *md_shortopts
= "";
729 struct option md_longopts
[] =
731 { "density", no_argument
, NULL
, option_density
},
732 { "no-density", no_argument
, NULL
, option_no_density
},
734 { "flix", no_argument
, NULL
, option_flix
},
735 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
736 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
738 /* Both "relax" and "generics" are deprecated and treated as equivalent
739 to the "transform" option. */
740 { "relax", no_argument
, NULL
, option_relax
},
741 { "no-relax", no_argument
, NULL
, option_no_relax
},
742 { "generics", no_argument
, NULL
, option_generics
},
743 { "no-generics", no_argument
, NULL
, option_no_generics
},
745 { "transform", no_argument
, NULL
, option_transform
},
746 { "no-transform", no_argument
, NULL
, option_no_transform
},
747 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
748 { "no-text-section-literals", no_argument
, NULL
,
749 option_no_text_section_literals
},
750 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
751 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
752 /* This option was changed from -align-target to -target-align
753 because it conflicted with the "-al" option. */
754 { "target-align", no_argument
, NULL
, option_align_targets
},
755 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
756 { "warn-unaligned-targets", no_argument
, NULL
,
757 option_warn_unaligned_targets
},
758 { "longcalls", no_argument
, NULL
, option_longcalls
},
759 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
761 { "no-workaround-a0-b-retw", no_argument
, NULL
,
762 option_no_workaround_a0_b_retw
},
763 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
765 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
766 option_no_workaround_b_j_loop_end
},
767 { "workaround-b-j-loop-end", no_argument
, NULL
,
768 option_workaround_b_j_loop_end
},
770 { "no-workaround-short-loops", no_argument
, NULL
,
771 option_no_workaround_short_loop
},
772 { "workaround-short-loops", no_argument
, NULL
,
773 option_workaround_short_loop
},
775 { "no-workaround-all-short-loops", no_argument
, NULL
,
776 option_no_workaround_all_short_loops
},
777 { "workaround-all-short-loop", no_argument
, NULL
,
778 option_workaround_all_short_loops
},
780 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
781 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
783 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
785 { "no-workaround-close-loop-end", no_argument
, NULL
,
786 option_no_workaround_close_loop_end
},
787 { "workaround-close-loop-end", no_argument
, NULL
,
788 option_workaround_close_loop_end
},
790 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
792 { "link-relax", no_argument
, NULL
, option_link_relax
},
793 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
795 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
797 { "trampolines", no_argument
, NULL
, option_trampolines
},
798 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
800 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
801 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
802 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
804 { NULL
, no_argument
, NULL
, 0 }
807 size_t md_longopts_size
= sizeof md_longopts
;
811 md_parse_option (int c
, const char *arg
)
816 as_warn (_("--density option is ignored"));
818 case option_no_density
:
819 as_warn (_("--no-density option is ignored"));
821 case option_link_relax
:
824 case option_no_link_relax
:
828 produce_flix
= FLIX_ALL
;
830 case option_no_generate_flix
:
831 produce_flix
= FLIX_NO_GENERATE
;
834 produce_flix
= FLIX_NONE
;
836 case option_generics
:
837 as_warn (_("--generics is deprecated; use --transform instead"));
838 return md_parse_option (option_transform
, arg
);
839 case option_no_generics
:
840 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
841 return md_parse_option (option_no_transform
, arg
);
843 as_warn (_("--relax is deprecated; use --transform instead"));
844 return md_parse_option (option_transform
, arg
);
845 case option_no_relax
:
846 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
847 return md_parse_option (option_no_transform
, arg
);
848 case option_longcalls
:
849 directive_state
[directive_longcalls
] = TRUE
;
851 case option_no_longcalls
:
852 directive_state
[directive_longcalls
] = FALSE
;
854 case option_text_section_literals
:
855 use_literal_section
= FALSE
;
857 case option_no_text_section_literals
:
858 use_literal_section
= TRUE
;
860 case option_absolute_literals
:
861 if (!absolute_literals_supported
)
863 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
866 directive_state
[directive_absolute_literals
] = TRUE
;
868 case option_no_absolute_literals
:
869 directive_state
[directive_absolute_literals
] = FALSE
;
872 case option_workaround_a0_b_retw
:
873 workaround_a0_b_retw
= TRUE
;
875 case option_no_workaround_a0_b_retw
:
876 workaround_a0_b_retw
= FALSE
;
878 case option_workaround_b_j_loop_end
:
879 workaround_b_j_loop_end
= TRUE
;
881 case option_no_workaround_b_j_loop_end
:
882 workaround_b_j_loop_end
= FALSE
;
885 case option_workaround_short_loop
:
886 workaround_short_loop
= TRUE
;
888 case option_no_workaround_short_loop
:
889 workaround_short_loop
= FALSE
;
892 case option_workaround_all_short_loops
:
893 workaround_all_short_loops
= TRUE
;
895 case option_no_workaround_all_short_loops
:
896 workaround_all_short_loops
= FALSE
;
899 case option_workaround_close_loop_end
:
900 workaround_close_loop_end
= TRUE
;
902 case option_no_workaround_close_loop_end
:
903 workaround_close_loop_end
= FALSE
;
906 case option_no_workarounds
:
907 workaround_a0_b_retw
= FALSE
;
908 workaround_b_j_loop_end
= FALSE
;
909 workaround_short_loop
= FALSE
;
910 workaround_all_short_loops
= FALSE
;
911 workaround_close_loop_end
= FALSE
;
914 case option_align_targets
:
915 align_targets
= TRUE
;
917 case option_no_align_targets
:
918 align_targets
= FALSE
;
921 case option_warn_unaligned_targets
:
922 warn_unaligned_branch_targets
= TRUE
;
925 case option_rename_section_name
:
926 build_section_rename (arg
);
930 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
931 should be emitted or not. FIXME: Not implemented. */
934 case option_prefer_l32r
:
936 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
940 case option_prefer_const16
:
942 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
946 case option_target_hardware
:
948 int earliest
, latest
= 0;
950 if (*arg
== 0 || *arg
== '-')
951 as_fatal (_("invalid target hardware version"));
953 earliest
= strtol (arg
, &end
, 0);
957 else if (*end
== '-')
960 as_fatal (_("invalid target hardware version"));
961 latest
= strtol (end
, &end
, 0);
964 as_fatal (_("invalid target hardware version"));
966 xtensa_setup_hw_workarounds (earliest
, latest
);
970 case option_transform
:
971 /* This option has no affect other than to use the defaults,
972 which are already set. */
975 case option_no_transform
:
976 /* This option turns off all transformations of any kind.
977 However, because we want to preserve the state of other
978 directives, we only change its own field. Thus, before
979 you perform any transformation, always check if transform
980 is available. If you use the functions we provide for this
981 purpose, you will be ok. */
982 directive_state
[directive_transform
] = FALSE
;
985 case option_trampolines
:
986 use_trampolines
= TRUE
;
989 case option_no_trampolines
:
990 use_trampolines
= FALSE
;
993 case option_auto_litpools
:
994 auto_litpools
= TRUE
;
995 use_literal_section
= FALSE
;
996 if (auto_litpool_limit
<= 0)
997 auto_litpool_limit
= MAX_AUTO_POOL_LITERALS
/ 2;
1000 case option_no_auto_litpools
:
1001 auto_litpools
= FALSE
;
1002 auto_litpool_limit
= -1;
1005 case option_auto_litpool_limit
:
1009 if (auto_litpool_limit
< 0)
1010 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1011 if (*arg
== 0 || *arg
== '-')
1012 as_fatal (_("invalid auto-litpool-limit argument"));
1013 value
= strtol (arg
, &end
, 10);
1015 as_fatal (_("invalid auto-litpool-limit argument"));
1016 if (value
< 100 || value
> 10000)
1017 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1018 auto_litpool_limit
= value
;
1019 auto_litpools
= TRUE
;
1020 use_literal_section
= FALSE
;
1031 md_show_usage (FILE *stream
)
1035 --[no-]text-section-literals\n\
1036 [Do not] put literals in the text section\n\
1037 --[no-]absolute-literals\n\
1038 [Do not] default to use non-PC-relative literals\n\
1039 --[no-]target-align [Do not] try to align branch targets\n\
1040 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1041 --[no-]transform [Do not] transform instructions\n\
1042 --flix both allow hand-written and generate flix bundles\n\
1043 --no-generate-flix allow hand-written but do not generate\n\
1045 --no-allow-flix neither allow hand-written nor generate\n\
1047 --rename-section old=new Rename section 'old' to 'new'\n\
1048 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1049 when jumps do not reach their targets\n\
1050 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1051 --auto-litpool-limit=<value>\n\
1052 (range 100-10000) Maximum number of blocks of\n\
1053 instructions to emit between literal pool\n\
1054 locations; implies --auto-litpools flag\n", stream
);
1058 /* Functions related to the list of current label symbols. */
1061 xtensa_add_insn_label (symbolS
*sym
)
1065 if (!free_insn_labels
)
1066 l
= XNEW (sym_list
);
1069 l
= free_insn_labels
;
1070 free_insn_labels
= l
->next
;
1074 l
->next
= insn_labels
;
1080 xtensa_clear_insn_labels (void)
1084 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1092 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1096 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1098 symbolS
*lit_sym
= lit
->sym
;
1099 S_SET_VALUE (lit_sym
, new_offset
);
1100 symbol_set_frag (lit_sym
, new_frag
);
1105 /* Directive data and functions. */
1107 typedef struct state_stackS_struct
1109 directiveE directive
;
1110 bfd_boolean negated
;
1111 bfd_boolean old_state
;
1115 struct state_stackS_struct
*prev
;
1118 state_stackS
*directive_state_stack
;
1120 const pseudo_typeS md_pseudo_table
[] =
1122 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1123 { "literal_position", xtensa_literal_position
, 0 },
1124 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1125 { "long", xtensa_elf_cons
, 4 },
1126 { "word", xtensa_elf_cons
, 4 },
1127 { "4byte", xtensa_elf_cons
, 4 },
1128 { "short", xtensa_elf_cons
, 2 },
1129 { "2byte", xtensa_elf_cons
, 2 },
1130 { "sleb128", xtensa_leb128
, 1},
1131 { "uleb128", xtensa_leb128
, 0},
1132 { "begin", xtensa_begin_directive
, 0 },
1133 { "end", xtensa_end_directive
, 0 },
1134 { "literal", xtensa_literal_pseudo
, 0 },
1135 { "frequency", xtensa_frequency_pseudo
, 0 },
1141 use_transform (void)
1143 /* After md_end, you should be checking frag by frag, rather
1144 than state directives. */
1145 gas_assert (!past_xtensa_end
);
1146 return directive_state
[directive_transform
];
1151 do_align_targets (void)
1153 /* Do not use this function after md_end; just look at align_targets
1154 instead. There is no target-align directive, so alignment is either
1155 enabled for all frags or not done at all. */
1156 gas_assert (!past_xtensa_end
);
1157 return align_targets
&& use_transform ();
1162 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1166 state_stackS
*stack
= XNEW (state_stackS
);
1168 file
= as_where (&line
);
1170 stack
->directive
= directive
;
1171 stack
->negated
= negated
;
1172 stack
->old_state
= directive_state
[directive
];
1175 stack
->datum
= datum
;
1176 stack
->prev
= directive_state_stack
;
1177 directive_state_stack
= stack
;
1179 directive_state
[directive
] = !negated
;
1184 directive_pop (directiveE
*directive
,
1185 bfd_boolean
*negated
,
1190 state_stackS
*top
= directive_state_stack
;
1192 if (!directive_state_stack
)
1194 as_bad (_("unmatched .end directive"));
1195 *directive
= directive_none
;
1199 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1200 *directive
= top
->directive
;
1201 *negated
= top
->negated
;
1204 *datum
= top
->datum
;
1205 directive_state_stack
= top
->prev
;
1211 directive_balance (void)
1213 while (directive_state_stack
)
1215 directiveE directive
;
1216 bfd_boolean negated
;
1221 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1222 as_warn_where ((char *) file
, line
,
1223 _(".begin directive with no matching .end directive"));
1229 inside_directive (directiveE dir
)
1231 state_stackS
*top
= directive_state_stack
;
1233 while (top
&& top
->directive
!= dir
)
1236 return (top
!= NULL
);
1241 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1245 const char *directive_string
;
1247 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1252 input_line_pointer
+= 3;
1255 len
= strspn (input_line_pointer
,
1256 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1258 /* This code is a hack to make .begin [no-][generics|relax] exactly
1259 equivalent to .begin [no-]transform. We should remove it when
1260 we stop accepting those options. */
1262 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1264 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1265 directive_string
= "transform";
1267 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1269 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1270 directive_string
= "transform";
1273 directive_string
= input_line_pointer
;
1275 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1277 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1279 input_line_pointer
+= len
;
1280 *directive
= (directiveE
) i
;
1281 if (*negated
&& !directive_info
[i
].can_be_negated
)
1282 as_bad (_("directive %s cannot be negated"),
1283 directive_info
[i
].name
);
1288 as_bad (_("unknown directive"));
1289 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1294 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1296 directiveE directive
;
1297 bfd_boolean negated
;
1301 get_directive (&directive
, &negated
);
1302 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1304 discard_rest_of_line ();
1308 if (cur_vinsn
.inside_bundle
)
1309 as_bad (_("directives are not valid inside bundles"));
1313 case directive_literal
:
1314 if (!inside_directive (directive_literal
))
1316 /* Previous labels go with whatever follows this directive, not with
1317 the literal, so save them now. */
1318 saved_insn_labels
= insn_labels
;
1321 as_warn (_(".begin literal is deprecated; use .literal instead"));
1322 state
= XNEW (emit_state
);
1323 xtensa_switch_to_literal_fragment (state
);
1324 directive_push (directive_literal
, negated
, state
);
1327 case directive_literal_prefix
:
1328 /* Have to flush pending output because a movi relaxed to an l32r
1329 might produce a literal. */
1330 md_flush_pending_output ();
1331 /* Check to see if the current fragment is a literal
1332 fragment. If it is, then this operation is not allowed. */
1333 if (generating_literals
)
1335 as_bad (_("cannot set literal_prefix inside literal fragment"));
1339 /* Allocate the literal state for this section and push
1340 onto the directive stack. */
1341 ls
= XNEW (lit_state
);
1344 *ls
= default_lit_sections
;
1345 directive_push (directive_literal_prefix
, negated
, ls
);
1347 /* Process the new prefix. */
1348 xtensa_literal_prefix ();
1351 case directive_freeregs
:
1352 /* This information is currently unused, but we'll accept the statement
1353 and just discard the rest of the line. This won't check the syntax,
1354 but it will accept every correct freeregs directive. */
1355 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1356 directive_push (directive_freeregs
, negated
, 0);
1359 case directive_schedule
:
1360 md_flush_pending_output ();
1361 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1362 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1363 directive_push (directive_schedule
, negated
, 0);
1364 xtensa_set_frag_assembly_state (frag_now
);
1367 case directive_density
:
1368 as_warn (_(".begin [no-]density is ignored"));
1371 case directive_absolute_literals
:
1372 md_flush_pending_output ();
1373 if (!absolute_literals_supported
&& !negated
)
1375 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1378 xtensa_set_frag_assembly_state (frag_now
);
1379 directive_push (directive
, negated
, 0);
1383 md_flush_pending_output ();
1384 xtensa_set_frag_assembly_state (frag_now
);
1385 directive_push (directive
, negated
, 0);
1389 demand_empty_rest_of_line ();
1394 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1396 directiveE begin_directive
, end_directive
;
1397 bfd_boolean begin_negated
, end_negated
;
1401 emit_state
**state_ptr
;
1404 if (cur_vinsn
.inside_bundle
)
1405 as_bad (_("directives are not valid inside bundles"));
1407 get_directive (&end_directive
, &end_negated
);
1409 md_flush_pending_output ();
1411 switch ((int) end_directive
)
1413 case XTENSA_UNDEFINED
:
1414 discard_rest_of_line ();
1417 case (int) directive_density
:
1418 as_warn (_(".end [no-]density is ignored"));
1419 demand_empty_rest_of_line ();
1422 case (int) directive_absolute_literals
:
1423 if (!absolute_literals_supported
&& !end_negated
)
1425 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1426 demand_empty_rest_of_line ();
1435 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1436 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1437 (const void **) state_ptr
);
1439 if (begin_directive
!= directive_none
)
1441 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1443 as_bad (_("does not match begin %s%s at %s:%d"),
1444 begin_negated
? "no-" : "",
1445 directive_info
[begin_directive
].name
, file
, line
);
1449 switch (end_directive
)
1451 case directive_literal
:
1452 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1453 xtensa_restore_emit_state (state
);
1454 xtensa_set_frag_assembly_state (frag_now
);
1456 if (!inside_directive (directive_literal
))
1458 /* Restore the list of current labels. */
1459 xtensa_clear_insn_labels ();
1460 insn_labels
= saved_insn_labels
;
1464 case directive_literal_prefix
:
1465 /* Restore the default collection sections from saved state. */
1466 s
= (lit_state
*) state
;
1468 default_lit_sections
= *s
;
1470 /* Free the state storage. */
1471 free (s
->lit_prefix
);
1475 case directive_schedule
:
1476 case directive_freeregs
:
1480 xtensa_set_frag_assembly_state (frag_now
);
1486 demand_empty_rest_of_line ();
1490 /* Place an aligned literal fragment at the current location. */
1493 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1495 md_flush_pending_output ();
1497 if (inside_directive (directive_literal
))
1498 as_warn (_(".literal_position inside literal directive; ignoring"));
1499 xtensa_mark_literal_pool_location ();
1501 demand_empty_rest_of_line ();
1502 xtensa_clear_insn_labels ();
1506 /* Support .literal label, expr, ... */
1509 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1512 char *p
, *base_name
;
1516 if (inside_directive (directive_literal
))
1518 as_bad (_(".literal not allowed inside .begin literal region"));
1519 ignore_rest_of_line ();
1523 md_flush_pending_output ();
1525 /* Previous labels go with whatever follows this directive, not with
1526 the literal, so save them now. */
1527 saved_insn_labels
= insn_labels
;
1530 /* If we are using text-section literals, then this is the right value... */
1533 base_name
= input_line_pointer
;
1535 xtensa_switch_to_literal_fragment (&state
);
1537 /* ...but if we aren't using text-section-literals, then we
1538 need to put them in the section we just switched to. */
1539 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1542 /* FIXME, despite the previous comments, dest_seg is unused... */
1545 /* All literals are aligned to four-byte boundaries. */
1546 frag_align (2, 0, 0);
1547 record_alignment (now_seg
, 2);
1549 c
= get_symbol_name (&base_name
);
1550 /* Just after name is now '\0'. */
1551 p
= input_line_pointer
;
1553 SKIP_WHITESPACE_AFTER_NAME ();
1555 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1557 as_bad (_("expected comma or colon after symbol name; "
1558 "rest of line ignored"));
1559 ignore_rest_of_line ();
1560 xtensa_restore_emit_state (&state
);
1568 input_line_pointer
++; /* skip ',' or ':' */
1570 xtensa_elf_cons (4);
1572 xtensa_restore_emit_state (&state
);
1574 /* Restore the list of current labels. */
1575 xtensa_clear_insn_labels ();
1576 insn_labels
= saved_insn_labels
;
1581 xtensa_literal_prefix (void)
1586 /* Parse the new prefix from the input_line_pointer. */
1588 len
= strspn (input_line_pointer
,
1589 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1590 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1592 /* Get a null-terminated copy of the name. */
1593 name
= xmemdup0 (input_line_pointer
, len
);
1595 /* Skip the name in the input line. */
1596 input_line_pointer
+= len
;
1598 default_lit_sections
.lit_prefix
= name
;
1600 /* Clear cached literal sections, since the prefix has changed. */
1601 default_lit_sections
.lit_seg
= NULL
;
1602 default_lit_sections
.lit4_seg
= NULL
;
1606 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1609 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1611 float fall_through_f
, target_f
;
1613 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1614 if (fall_through_f
< 0)
1616 as_bad (_("fall through frequency must be greater than 0"));
1617 ignore_rest_of_line ();
1621 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1624 as_bad (_("branch target frequency must be greater than 0"));
1625 ignore_rest_of_line ();
1629 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1631 demand_empty_rest_of_line ();
1635 /* Like normal .long/.short/.word, except support @plt, etc.
1636 Clobbers input_line_pointer, checks end-of-line. */
1639 xtensa_elf_cons (int nbytes
)
1642 bfd_reloc_code_real_type reloc
;
1644 md_flush_pending_output ();
1646 if (cur_vinsn
.inside_bundle
)
1647 as_bad (_("directives are not valid inside bundles"));
1649 if (is_it_end_of_statement ())
1651 demand_empty_rest_of_line ();
1658 if (exp
.X_op
== O_symbol
1659 && *input_line_pointer
== '@'
1660 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1663 reloc_howto_type
*reloc_howto
=
1664 bfd_reloc_type_lookup (stdoutput
, reloc
);
1666 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1667 as_bad (_("unsupported relocation"));
1668 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1669 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1670 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1671 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1672 as_bad (_("opcode-specific %s relocation used outside "
1673 "an instruction"), reloc_howto
->name
);
1674 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1675 as_bad (ngettext ("%s relocations do not fit in %d byte",
1676 "%s relocations do not fit in %d bytes",
1678 reloc_howto
->name
, nbytes
);
1679 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1680 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1681 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1682 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1685 char *p
= frag_more ((int) nbytes
);
1686 xtensa_set_frag_assembly_state (frag_now
);
1687 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1688 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1693 xtensa_set_frag_assembly_state (frag_now
);
1694 emit_expr (&exp
, (unsigned int) nbytes
);
1697 while (*input_line_pointer
++ == ',');
1699 input_line_pointer
--; /* Put terminator back into stream. */
1700 demand_empty_rest_of_line ();
1703 static bfd_boolean is_leb128_expr
;
1706 xtensa_leb128 (int sign
)
1708 is_leb128_expr
= TRUE
;
1710 is_leb128_expr
= FALSE
;
1714 /* Parsing and Idiom Translation. */
1716 /* Parse @plt, etc. and return the desired relocation. */
1717 static bfd_reloc_code_real_type
1718 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1728 return BFD_RELOC_NONE
;
1730 for (ch
= *str
, str2
= ident
;
1731 (str2
< ident
+ sizeof (ident
) - 1
1732 && (ISALNUM (ch
) || ch
== '@'));
1735 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1742 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1743 if (ch
== suffix_relocs
[i
].suffix
[0]
1744 && len
== suffix_relocs
[i
].length
1745 && memcmp (ident
, suffix_relocs
[i
].suffix
, suffix_relocs
[i
].length
) == 0)
1747 /* Now check for "identifier@suffix+constant". */
1748 if (*str
== '-' || *str
== '+')
1750 char *orig_line
= input_line_pointer
;
1751 expressionS new_exp
;
1753 input_line_pointer
= str
;
1754 expression (&new_exp
);
1755 if (new_exp
.X_op
== O_constant
)
1757 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1758 str
= input_line_pointer
;
1761 if (&input_line_pointer
!= str_p
)
1762 input_line_pointer
= orig_line
;
1766 return suffix_relocs
[i
].reloc
;
1769 return BFD_RELOC_UNUSED
;
1773 /* Find the matching operator type. */
1775 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1777 operatorT
operator = O_illegal
;
1780 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1782 if (suffix_relocs
[i
].reloc
== reloc
)
1784 operator = suffix_relocs
[i
].operator;
1788 gas_assert (operator != O_illegal
);
1793 /* Find the matching reloc type. */
1794 static bfd_reloc_code_real_type
1795 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1798 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1800 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1802 if (suffix_relocs
[i
].operator == operator)
1804 reloc
= suffix_relocs
[i
].reloc
;
1811 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1812 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1813 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1814 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1817 if (reloc
== BFD_RELOC_UNUSED
)
1818 return BFD_RELOC_32
;
1825 expression_end (const char *name
)
1848 #define ERROR_REG_NUM ((unsigned) -1)
1851 tc_get_register (const char *prefix
)
1854 const char *next_expr
;
1855 const char *old_line_pointer
;
1858 old_line_pointer
= input_line_pointer
;
1860 if (*input_line_pointer
== '$')
1861 ++input_line_pointer
;
1863 /* Accept "sp" as a synonym for "a1". */
1864 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1865 && expression_end (input_line_pointer
+ 2))
1867 input_line_pointer
+= 2;
1868 return 1; /* AR[1] */
1871 while (*input_line_pointer
++ == *prefix
++)
1873 --input_line_pointer
;
1878 as_bad (_("bad register name: %s"), old_line_pointer
);
1879 return ERROR_REG_NUM
;
1882 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1884 as_bad (_("bad register number: %s"), input_line_pointer
);
1885 return ERROR_REG_NUM
;
1890 while (ISDIGIT ((int) *input_line_pointer
))
1891 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1893 if (!(next_expr
= expression_end (input_line_pointer
)))
1895 as_bad (_("bad register name: %s"), old_line_pointer
);
1896 return ERROR_REG_NUM
;
1899 input_line_pointer
= (char *) next_expr
;
1906 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1908 xtensa_isa isa
= xtensa_default_isa
;
1910 /* Check if this is an immediate operand. */
1911 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1913 bfd_reloc_code_real_type reloc
;
1914 segT t
= expression (tok
);
1916 if (t
== absolute_section
1917 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1919 gas_assert (tok
->X_op
== O_constant
);
1920 tok
->X_op
= O_symbol
;
1921 tok
->X_add_symbol
= &abs_symbol
;
1924 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1925 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1930 case BFD_RELOC_LO16
:
1931 if (tok
->X_op
== O_constant
)
1933 tok
->X_add_number
&= 0xffff;
1937 case BFD_RELOC_HI16
:
1938 if (tok
->X_op
== O_constant
)
1940 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1944 case BFD_RELOC_UNUSED
:
1945 as_bad (_("unsupported relocation"));
1947 case BFD_RELOC_32_PCREL
:
1948 as_bad (_("pcrel relocation not allowed in an instruction"));
1953 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1958 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1959 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1961 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1964 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1965 as_bad (_("register number out of range"));
1968 tok
->X_op
= O_register
;
1969 tok
->X_add_symbol
= 0;
1970 tok
->X_add_number
= reg
;
1975 /* Split up the arguments for an opcode or pseudo-op. */
1978 tokenize_arguments (char **args
, char *str
)
1980 char *old_input_line_pointer
;
1981 bfd_boolean saw_comma
= FALSE
;
1982 bfd_boolean saw_arg
= FALSE
;
1983 bfd_boolean saw_colon
= FALSE
;
1985 char *arg_end
, *arg
;
1988 /* Save and restore input_line_pointer around this function. */
1989 old_input_line_pointer
= input_line_pointer
;
1990 input_line_pointer
= str
;
1992 while (*input_line_pointer
)
1995 switch (*input_line_pointer
)
2002 input_line_pointer
++;
2003 if (saw_comma
|| saw_colon
|| !saw_arg
)
2009 input_line_pointer
++;
2010 if (saw_comma
|| saw_colon
|| !saw_arg
)
2016 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2019 arg_end
= input_line_pointer
+ 1;
2020 while (!expression_end (arg_end
))
2023 arg_len
= arg_end
- input_line_pointer
;
2024 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2025 args
[num_args
] = arg
;
2029 strncpy (arg
, input_line_pointer
, arg_len
);
2030 arg
[arg_len
] = '\0';
2032 input_line_pointer
= arg_end
;
2042 if (saw_comma
|| saw_colon
)
2044 input_line_pointer
= old_input_line_pointer
;
2049 as_bad (_("extra comma"));
2051 as_bad (_("extra colon"));
2053 as_bad (_("missing argument"));
2055 as_bad (_("missing comma or colon"));
2056 input_line_pointer
= old_input_line_pointer
;
2061 /* Parse the arguments to an opcode. Return TRUE on error. */
2064 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2066 expressionS
*tok
, *last_tok
;
2067 xtensa_opcode opcode
= insn
->opcode
;
2068 bfd_boolean had_error
= TRUE
;
2069 xtensa_isa isa
= xtensa_default_isa
;
2070 int n
, num_regs
= 0;
2071 int opcode_operand_count
;
2072 int opnd_cnt
, last_opnd_cnt
;
2073 unsigned int next_reg
= 0;
2074 char *old_input_line_pointer
;
2076 if (insn
->insn_type
== ITYPE_LITERAL
)
2077 opcode_operand_count
= 1;
2079 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2082 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2084 /* Save and restore input_line_pointer around this function. */
2085 old_input_line_pointer
= input_line_pointer
;
2091 /* Skip invisible operands. */
2092 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2098 for (n
= 0; n
< num_args
; n
++)
2100 input_line_pointer
= arg_strings
[n
];
2101 if (*input_line_pointer
== ':')
2103 xtensa_regfile opnd_rf
;
2104 input_line_pointer
++;
2107 gas_assert (opnd_cnt
> 0);
2109 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2111 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2112 as_warn (_("incorrect register number, ignoring"));
2117 if (opnd_cnt
>= opcode_operand_count
)
2119 as_warn (_("too many arguments"));
2122 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2124 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2125 next_reg
= tok
->X_add_number
+ 1;
2127 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2129 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2131 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2132 /* minus 1 because we are seeing one right now */
2138 last_opnd_cnt
= opnd_cnt
;
2139 demand_empty_rest_of_line ();
2146 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2150 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2153 insn
->ntok
= tok
- insn
->tok
;
2157 input_line_pointer
= old_input_line_pointer
;
2163 get_invisible_operands (TInsn
*insn
)
2165 xtensa_isa isa
= xtensa_default_isa
;
2166 static xtensa_insnbuf slotbuf
= NULL
;
2168 xtensa_opcode opc
= insn
->opcode
;
2169 int slot
, opnd
, fmt_found
;
2173 slotbuf
= xtensa_insnbuf_alloc (isa
);
2175 /* Find format/slot where this can be encoded. */
2178 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2180 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2182 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2188 if (fmt_found
) break;
2193 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2197 /* First encode all the visible operands
2198 (to deal with shared field operands). */
2199 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2201 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2202 && (insn
->tok
[opnd
].X_op
== O_register
2203 || insn
->tok
[opnd
].X_op
== O_constant
))
2205 val
= insn
->tok
[opnd
].X_add_number
;
2206 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2207 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2211 /* Then pull out the values for the invisible ones. */
2212 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2214 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2216 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2217 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2218 insn
->tok
[opnd
].X_add_number
= val
;
2219 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2220 insn
->tok
[opnd
].X_op
= O_register
;
2222 insn
->tok
[opnd
].X_op
= O_constant
;
2231 xg_reverse_shift_count (char **cnt_argp
)
2233 char *cnt_arg
, *new_arg
;
2234 cnt_arg
= *cnt_argp
;
2236 /* replace the argument with "31-(argument)" */
2237 new_arg
= concat ("31-(", cnt_arg
, ")", (char *) NULL
);
2240 *cnt_argp
= new_arg
;
2244 /* If "arg" is a constant expression, return non-zero with the value
2248 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2251 char *save_ptr
= input_line_pointer
;
2253 input_line_pointer
= arg
;
2255 input_line_pointer
= save_ptr
;
2257 if (exp
.X_op
== O_constant
)
2259 *valp
= exp
.X_add_number
;
2268 xg_replace_opname (char **popname
, const char *newop
)
2271 *popname
= xstrdup (newop
);
2276 xg_check_num_args (int *pnum_args
,
2281 int num_args
= *pnum_args
;
2283 if (num_args
< expected_num
)
2285 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2286 num_args
, opname
, expected_num
);
2290 if (num_args
> expected_num
)
2292 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2293 num_args
, opname
, expected_num
);
2294 while (num_args
-- > expected_num
)
2296 free (arg_strings
[num_args
]);
2297 arg_strings
[num_args
] = 0;
2299 *pnum_args
= expected_num
;
2307 /* If the register is not specified as part of the opcode,
2308 then get it from the operand and move it to the opcode. */
2311 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2313 xtensa_isa isa
= xtensa_default_isa
;
2315 char *opname
, *new_opname
;
2316 const char *sr_name
;
2317 int is_user
, is_write
;
2322 is_user
= (opname
[1] == 'u');
2323 is_write
= (opname
[0] == 'w');
2325 /* Opname == [rw]ur or [rwx]sr... */
2327 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2330 /* Check if the argument is a symbolic register name. */
2331 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2332 /* Handle WSR to "INTSET" as a special case. */
2333 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2334 && !strcasecmp (arg_strings
[1], "intset"))
2335 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2336 if (sr
== XTENSA_UNDEFINED
2337 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2339 /* Maybe it's a register number.... */
2341 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2343 as_bad (_("invalid register '%s' for '%s' instruction"),
2344 arg_strings
[1], opname
);
2347 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2348 if (sr
== XTENSA_UNDEFINED
)
2350 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2351 (long) val
, opname
);
2356 /* Remove the last argument, which is now part of the opcode. */
2357 free (arg_strings
[1]);
2361 /* Translate the opcode. */
2362 sr_name
= xtensa_sysreg_name (isa
, sr
);
2363 /* Another special case for "WSR.INTSET".... */
2364 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2366 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2368 *popname
= new_opname
;
2375 xtensa_translate_old_userreg_ops (char **popname
)
2377 xtensa_isa isa
= xtensa_default_isa
;
2379 char *opname
, *new_opname
;
2380 const char *sr_name
;
2381 bfd_boolean has_underbar
= FALSE
;
2384 if (opname
[0] == '_')
2386 has_underbar
= TRUE
;
2390 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2391 if (sr
!= XTENSA_UNDEFINED
)
2393 /* The new default name ("nnn") is different from the old default
2394 name ("URnnn"). The old default is handled below, and we don't
2395 want to recognize [RW]nnn, so do nothing if the name is the (new)
2397 static char namebuf
[10];
2398 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2399 if (strcmp (namebuf
, opname
+ 1) == 0)
2407 /* Only continue if the reg name is "URnnn". */
2408 if (opname
[1] != 'u' || opname
[2] != 'r')
2410 val
= strtoul (opname
+ 3, &end
, 10);
2414 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2415 if (sr
== XTENSA_UNDEFINED
)
2417 as_bad (_("invalid register number (%ld) for '%s'"),
2418 (long) val
, opname
);
2423 /* Translate the opcode. */
2424 sr_name
= xtensa_sysreg_name (isa
, sr
);
2425 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2426 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2427 opname
[0], sr_name
);
2429 *popname
= new_opname
;
2436 xtensa_translate_zero_immed (const char *old_op
,
2446 gas_assert (opname
[0] != '_');
2448 if (strcmp (opname
, old_op
) != 0)
2451 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2453 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2455 xg_replace_opname (popname
, new_op
);
2456 free (arg_strings
[1]);
2457 arg_strings
[1] = arg_strings
[2];
2466 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2467 Returns non-zero if an error was found. */
2470 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2472 char *opname
= *popname
;
2473 bfd_boolean has_underbar
= FALSE
;
2477 has_underbar
= TRUE
;
2481 if (strcmp (opname
, "mov") == 0)
2483 if (use_transform () && !has_underbar
&& density_supported
)
2484 xg_replace_opname (popname
, "mov.n");
2487 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2489 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2490 arg_strings
[2] = xstrdup (arg_strings
[1]);
2496 if (strcmp (opname
, "bbsi.l") == 0)
2498 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2500 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2501 if (target_big_endian
)
2502 xg_reverse_shift_count (&arg_strings
[1]);
2506 if (strcmp (opname
, "bbci.l") == 0)
2508 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2510 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2511 if (target_big_endian
)
2512 xg_reverse_shift_count (&arg_strings
[1]);
2516 /* Don't do anything special with NOPs inside FLIX instructions. They
2517 are handled elsewhere. Real NOP instructions are always available
2518 in configurations with FLIX, so this should never be an issue but
2519 check for it anyway. */
2520 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2521 && strcmp (opname
, "nop") == 0)
2523 if (use_transform () && !has_underbar
&& density_supported
)
2524 xg_replace_opname (popname
, "nop.n");
2527 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2529 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2530 arg_strings
[0] = xstrdup ("a1");
2531 arg_strings
[1] = xstrdup ("a1");
2532 arg_strings
[2] = xstrdup ("a1");
2538 /* Recognize [RW]UR and [RWX]SR. */
2539 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2540 && (opname
[1] == 'u' || opname
[1] == 's'))
2541 || (opname
[0] == 'x' && opname
[1] == 's'))
2543 && opname
[3] == '\0')
2544 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2546 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2547 [RW]<name> if <name> is the non-default name of a user register. */
2548 if ((opname
[0] == 'r' || opname
[0] == 'w')
2549 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2550 return xtensa_translate_old_userreg_ops (popname
);
2552 /* Relax branches that don't allow comparisons against an immediate value
2553 of zero to the corresponding branches with implicit zero immediates. */
2554 if (!has_underbar
&& use_transform ())
2556 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2557 pnum_args
, arg_strings
))
2560 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2561 pnum_args
, arg_strings
))
2564 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2565 pnum_args
, arg_strings
))
2568 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2569 pnum_args
, arg_strings
))
2577 /* Functions for dealing with the Xtensa ISA. */
2579 /* Currently the assembler only allows us to use a single target per
2580 fragment. Because of this, only one operand for a given
2581 instruction may be symbolic. If there is a PC-relative operand,
2582 the last one is chosen. Otherwise, the result is the number of the
2583 last immediate operand, and if there are none of those, we fail and
2587 get_relaxable_immed (xtensa_opcode opcode
)
2589 int last_immed
= -1;
2592 if (opcode
== XTENSA_UNDEFINED
)
2595 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2596 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2598 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2600 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2602 if (last_immed
== -1
2603 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2610 static xtensa_opcode
2611 get_opcode_from_buf (const char *buf
, int slot
)
2613 static xtensa_insnbuf insnbuf
= NULL
;
2614 static xtensa_insnbuf slotbuf
= NULL
;
2615 xtensa_isa isa
= xtensa_default_isa
;
2620 insnbuf
= xtensa_insnbuf_alloc (isa
);
2621 slotbuf
= xtensa_insnbuf_alloc (isa
);
2624 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2625 fmt
= xtensa_format_decode (isa
, insnbuf
);
2626 if (fmt
== XTENSA_UNDEFINED
)
2627 return XTENSA_UNDEFINED
;
2629 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2630 return XTENSA_UNDEFINED
;
2632 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2633 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2637 #ifdef TENSILICA_DEBUG
2639 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2642 xtensa_print_insn_table (void)
2644 int num_opcodes
, num_operands
;
2645 xtensa_opcode opcode
;
2646 xtensa_isa isa
= xtensa_default_isa
;
2648 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2649 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2652 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2653 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2654 for (opn
= 0; opn
< num_operands
; opn
++)
2656 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2658 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2660 xtensa_regfile opnd_rf
=
2661 xtensa_operand_regfile (isa
, opcode
, opn
);
2662 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2664 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2665 fputs ("[lLr] ", stderr
);
2667 fputs ("i ", stderr
);
2669 fprintf (stderr
, "\n");
2675 print_vliw_insn (xtensa_insnbuf vbuf
)
2677 xtensa_isa isa
= xtensa_default_isa
;
2678 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2679 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2682 fprintf (stderr
, "format = %d\n", f
);
2684 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2686 xtensa_opcode opcode
;
2690 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2691 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2692 opname
= xtensa_opcode_name (isa
, opcode
);
2694 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2695 fprintf (stderr
, " operands = ");
2697 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2701 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2703 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2704 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2705 fprintf (stderr
, "%d ", val
);
2707 fprintf (stderr
, "\n");
2709 xtensa_insnbuf_free (isa
, sbuf
);
2712 #endif /* TENSILICA_DEBUG */
2716 is_direct_call_opcode (xtensa_opcode opcode
)
2718 xtensa_isa isa
= xtensa_default_isa
;
2719 int n
, num_operands
;
2721 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2724 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2725 for (n
= 0; n
< num_operands
; n
++)
2727 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2728 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2735 /* Convert from BFD relocation type code to slot and operand number.
2736 Returns non-zero on failure. */
2739 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2741 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2742 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2744 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2747 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2748 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2750 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2760 /* Convert from slot number to BFD relocation type code for the
2761 standard PC-relative relocations. Return BFD_RELOC_NONE on
2764 static bfd_reloc_code_real_type
2765 encode_reloc (int slot
)
2767 if (slot
< 0 || slot
> 14)
2768 return BFD_RELOC_NONE
;
2770 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2774 /* Convert from slot numbers to BFD relocation type code for the
2775 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2777 static bfd_reloc_code_real_type
2778 encode_alt_reloc (int slot
)
2780 if (slot
< 0 || slot
> 14)
2781 return BFD_RELOC_NONE
;
2783 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2788 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2791 xtensa_opcode opcode
,
2797 uint32 valbuf
= value
;
2799 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2801 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2803 as_bad_where ((char *) file
, line
,
2804 _("operand %d of '%s' has out of range value '%u'"),
2806 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2809 as_bad_where ((char *) file
, line
,
2810 _("operand %d of '%s' has invalid value '%u'"),
2812 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2817 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2823 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2826 xtensa_opcode opcode
,
2830 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2831 fmt
, slot
, slotbuf
, &val
);
2832 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2837 /* Checks for rules from xtensa-relax tables. */
2839 /* The routine xg_instruction_matches_option_term must return TRUE
2840 when a given option term is true. The meaning of all of the option
2841 terms is given interpretation by this function. */
2844 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2846 if (strcmp (option
->option_name
, "realnop") == 0
2847 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2849 /* These conditions were evaluated statically when building the
2850 relaxation table. There's no need to reevaluate them now. */
2853 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2854 return insn
->extra_arg
.X_op
== O_register
;
2857 as_fatal (_("internal error: unknown option name '%s'"),
2858 option
->option_name
);
2864 xg_instruction_matches_or_options (TInsn
*insn
,
2865 const ReqOrOptionList
*or_option
)
2867 const ReqOrOption
*option
;
2868 /* Must match each of the AND terms. */
2869 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2871 if (xg_instruction_matches_option_term (insn
, option
))
2879 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2881 const ReqOption
*req_options
;
2882 /* Must match each of the AND terms. */
2883 for (req_options
= options
;
2884 req_options
!= NULL
;
2885 req_options
= req_options
->next
)
2887 /* Must match one of the OR clauses. */
2888 if (!xg_instruction_matches_or_options (insn
,
2889 req_options
->or_option_terms
))
2896 /* Return the transition rule that matches or NULL if none matches. */
2899 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2901 PreconditionList
*condition_l
;
2903 if (rule
->opcode
!= insn
->opcode
)
2906 for (condition_l
= rule
->conditions
;
2907 condition_l
!= NULL
;
2908 condition_l
= condition_l
->next
)
2912 Precondition
*cond
= condition_l
->precond
;
2917 /* The expression must be the constant. */
2918 gas_assert (cond
->op_num
< insn
->ntok
);
2919 exp1
= &insn
->tok
[cond
->op_num
];
2920 if (expr_is_const (exp1
))
2925 if (get_expr_const (exp1
) != cond
->op_data
)
2929 if (get_expr_const (exp1
) == cond
->op_data
)
2936 else if (expr_is_register (exp1
))
2941 if (get_expr_register (exp1
) != cond
->op_data
)
2945 if (get_expr_register (exp1
) == cond
->op_data
)
2957 gas_assert (cond
->op_num
< insn
->ntok
);
2958 gas_assert (cond
->op_data
< insn
->ntok
);
2959 exp1
= &insn
->tok
[cond
->op_num
];
2960 exp2
= &insn
->tok
[cond
->op_data
];
2965 if (!expr_is_equal (exp1
, exp2
))
2969 if (expr_is_equal (exp1
, exp2
))
2981 if (!xg_instruction_matches_options (insn
, rule
->options
))
2989 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2991 bfd_boolean a_greater
= FALSE
;
2992 bfd_boolean b_greater
= FALSE
;
2994 ReqOptionList
*l_a
= a
->options
;
2995 ReqOptionList
*l_b
= b
->options
;
2997 /* We only care if they both are the same except for
2998 a const16 vs. an l32r. */
3000 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3002 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
3003 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
3004 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3006 if (l_or_a
->is_true
!= l_or_b
->is_true
)
3008 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
3010 /* This is the case we care about. */
3011 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3012 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3019 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3020 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3030 l_or_a
= l_or_a
->next
;
3031 l_or_b
= l_or_b
->next
;
3033 if (l_or_a
|| l_or_b
)
3042 /* Incomparable if the substitution was used differently in two cases. */
3043 if (a_greater
&& b_greater
)
3055 static TransitionRule
*
3056 xg_instruction_match (TInsn
*insn
)
3058 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3060 gas_assert (insn
->opcode
< table
->num_opcodes
);
3062 /* Walk through all of the possible transitions. */
3063 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3065 TransitionRule
*rule
= l
->rule
;
3066 if (xg_instruction_matches_rule (insn
, rule
))
3073 /* Various Other Internal Functions. */
3076 is_unique_insn_expansion (TransitionRule
*r
)
3078 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3080 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3086 /* Check if there is exactly one relaxation for INSN that converts it to
3087 another instruction of equal or larger size. If so, and if TARG is
3088 non-null, go ahead and generate the relaxed instruction into TARG. If
3089 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3090 instruction, i.e., ignore relaxations that convert to an instruction of
3091 equal size. In some contexts where this function is used, only
3092 a single widening is allowed and the NARROW_ONLY argument is used to
3093 exclude cases like ADDI being "widened" to an ADDMI, which may
3094 later be relaxed to an ADDMI/ADDI pair. */
3097 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3099 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3101 TransitionRule
*match
= 0;
3103 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3104 gas_assert (insn
->opcode
< table
->num_opcodes
);
3106 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3108 TransitionRule
*rule
= l
->rule
;
3110 if (xg_instruction_matches_rule (insn
, rule
)
3111 && is_unique_insn_expansion (rule
)
3112 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3113 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3124 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3129 /* Return the maximum number of bytes this opcode can expand to. */
3132 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3134 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3136 int max_size
= xg_get_single_size (opcode
);
3138 gas_assert (opcode
< table
->num_opcodes
);
3140 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3142 TransitionRule
*rule
= l
->rule
;
3143 BuildInstr
*build_list
;
3148 build_list
= rule
->to_instr
;
3149 if (is_unique_insn_expansion (rule
))
3151 gas_assert (build_list
->typ
== INSTR_INSTR
);
3152 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3155 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3157 switch (build_list
->typ
)
3160 this_size
+= xg_get_single_size (build_list
->opcode
);
3162 case INSTR_LITERAL_DEF
:
3163 case INSTR_LABEL_DEF
:
3168 if (this_size
> max_size
)
3169 max_size
= this_size
;
3175 /* Return the maximum number of literal bytes this opcode can generate. */
3178 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3180 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3184 gas_assert (opcode
< table
->num_opcodes
);
3186 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3188 TransitionRule
*rule
= l
->rule
;
3189 BuildInstr
*build_list
;
3194 build_list
= rule
->to_instr
;
3195 if (is_unique_insn_expansion (rule
))
3197 gas_assert (build_list
->typ
== INSTR_INSTR
);
3198 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3201 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3203 switch (build_list
->typ
)
3205 case INSTR_LITERAL_DEF
:
3206 /* Hard-coded 4-byte literal. */
3210 case INSTR_LABEL_DEF
:
3215 if (this_size
> max_size
)
3216 max_size
= this_size
;
3223 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3225 int steps_taken
= 0;
3226 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3229 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3230 gas_assert (insn
->opcode
< table
->num_opcodes
);
3232 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3234 TransitionRule
*rule
= l
->rule
;
3236 if (xg_instruction_matches_rule (insn
, rule
))
3238 if (steps_taken
== lateral_steps
)
3248 get_special_literal_symbol (void)
3250 static symbolS
*sym
= NULL
;
3253 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3259 get_special_label_symbol (void)
3261 static symbolS
*sym
= NULL
;
3264 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3270 xg_valid_literal_expression (const expressionS
*exp
)
3292 /* This will check to see if the value can be converted into the
3293 operand type. It will return TRUE if it does not fit. */
3296 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3298 uint32 valbuf
= value
;
3299 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3305 /* Assumes: All immeds are constants. Check that all constants fit
3306 into their immeds; return FALSE if not. */
3309 xg_immeds_fit (const TInsn
*insn
)
3311 xtensa_isa isa
= xtensa_default_isa
;
3315 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3316 for (i
= 0; i
< n
; ++i
)
3318 const expressionS
*exp
= &insn
->tok
[i
];
3320 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3327 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3332 /* The symbol should have a fixup associated with it. */
3341 /* This should only be called after we have an initial
3342 estimate of the addresses. */
3345 xg_symbolic_immeds_fit (const TInsn
*insn
,
3351 xtensa_isa isa
= xtensa_default_isa
;
3359 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3361 for (i
= 0; i
< n
; ++i
)
3363 const expressionS
*exp
= &insn
->tok
[i
];
3365 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3372 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3378 /* Check for the worst case. */
3379 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3384 /* We only allow symbols for PC-relative references.
3385 If pc_frag == 0, then we don't have frag locations yet. */
3387 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3390 /* If it is a weak symbol or a symbol in a different section,
3391 it cannot be known to fit at assembly time. */
3392 if (S_IS_WEAK (exp
->X_add_symbol
)
3393 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3395 /* For a direct call with --no-longcalls, be optimistic and
3396 assume it will be in range. If the symbol is weak and
3397 undefined, it may remain undefined at link-time, in which
3398 case it will have a zero value and almost certainly be out
3399 of range for a direct call; thus, relax for undefined weak
3400 symbols even if longcalls is not enabled. */
3401 if (is_direct_call_opcode (insn
->opcode
)
3402 && ! pc_frag
->tc_frag_data
.use_longcalls
3403 && (! S_IS_WEAK (exp
->X_add_symbol
)
3404 || S_IS_DEFINED (exp
->X_add_symbol
)))
3410 symbolP
= exp
->X_add_symbol
;
3411 sym_frag
= symbol_get_frag (symbolP
);
3412 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3413 pc
= pc_frag
->fr_address
+ pc_offset
;
3415 /* If frag has yet to be reached on this pass, assume it
3416 will move by STRETCH just as we did. If this is not so,
3417 it will be because some frag between grows, and that will
3418 force another pass. Beware zero-length frags. There
3419 should be a faster way to do this. */
3422 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3423 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3428 new_offset
= target
;
3429 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3430 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3435 /* The symbol should have a fixup associated with it. */
3444 /* Return TRUE on success. */
3447 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3453 targ
->debug_line
= insn
->debug_line
;
3454 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3459 targ
->opcode
= bi
->opcode
;
3460 targ
->insn_type
= ITYPE_INSN
;
3461 targ
->is_specific_opcode
= FALSE
;
3463 for (; op
!= NULL
; op
= op
->next
)
3465 int op_num
= op
->op_num
;
3466 int op_data
= op
->op_data
;
3468 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3470 if (targ
->ntok
<= op_num
)
3471 targ
->ntok
= op_num
+ 1;
3476 set_expr_const (&targ
->tok
[op_num
], op_data
);
3479 gas_assert (op_data
< insn
->ntok
);
3480 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3483 if (insn
->extra_arg
.X_op
!= O_register
)
3485 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3488 sym
= get_special_literal_symbol ();
3489 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3490 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3491 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3492 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3495 sym
= get_special_label_symbol ();
3496 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3498 case OP_OPERAND_HI16U
:
3499 case OP_OPERAND_LOW16U
:
3500 gas_assert (op_data
< insn
->ntok
);
3501 if (expr_is_const (&insn
->tok
[op_data
]))
3504 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3505 val
= xg_apply_userdef_op_fn (op
->typ
,
3508 targ
->tok
[op_num
].X_add_number
= val
;
3512 /* For const16 we can create relocations for these. */
3513 if (targ
->opcode
== XTENSA_UNDEFINED
3514 || (targ
->opcode
!= xtensa_const16_opcode
))
3516 gas_assert (op_data
< insn
->ntok
);
3517 /* Need to build a O_lo16 or O_hi16. */
3518 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3519 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3521 if (op
->typ
== OP_OPERAND_HI16U
)
3522 targ
->tok
[op_num
].X_op
= O_hi16
;
3523 else if (op
->typ
== OP_OPERAND_LOW16U
)
3524 targ
->tok
[op_num
].X_op
= O_lo16
;
3531 /* currently handles:
3534 OP_OPERAND_F32MINUS */
3535 if (xg_has_userdef_op_fn (op
->typ
))
3537 gas_assert (op_data
< insn
->ntok
);
3538 if (expr_is_const (&insn
->tok
[op_data
]))
3541 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3542 val
= xg_apply_userdef_op_fn (op
->typ
,
3545 targ
->tok
[op_num
].X_add_number
= val
;
3548 return FALSE
; /* We cannot use a relocation for this. */
3557 case INSTR_LITERAL_DEF
:
3559 targ
->opcode
= XTENSA_UNDEFINED
;
3560 targ
->insn_type
= ITYPE_LITERAL
;
3561 targ
->is_specific_opcode
= FALSE
;
3562 for (; op
!= NULL
; op
= op
->next
)
3564 int op_num
= op
->op_num
;
3565 int op_data
= op
->op_data
;
3566 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3568 if (targ
->ntok
<= op_num
)
3569 targ
->ntok
= op_num
+ 1;
3574 gas_assert (op_data
< insn
->ntok
);
3575 /* We can only pass resolvable literals through. */
3576 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3578 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3590 case INSTR_LABEL_DEF
:
3592 targ
->opcode
= XTENSA_UNDEFINED
;
3593 targ
->insn_type
= ITYPE_LABEL
;
3594 targ
->is_specific_opcode
= FALSE
;
3595 /* Literal with no ops is a label? */
3596 gas_assert (op
== NULL
);
3607 /* Return TRUE on success. */
3610 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3612 for (; bi
!= NULL
; bi
= bi
->next
)
3614 TInsn
*next_insn
= istack_push_space (istack
);
3616 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3623 /* Return TRUE on valid expansion. */
3626 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3628 int stack_size
= istack
->ninsn
;
3629 int steps_taken
= 0;
3630 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3633 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3634 gas_assert (insn
->opcode
< table
->num_opcodes
);
3636 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3638 TransitionRule
*rule
= l
->rule
;
3640 if (xg_instruction_matches_rule (insn
, rule
))
3642 if (lateral_steps
== steps_taken
)
3646 /* This is it. Expand the rule to the stack. */
3647 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3650 /* Check to see if it fits. */
3651 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3653 TInsn
*tinsn
= &istack
->insn
[i
];
3655 if (tinsn
->insn_type
== ITYPE_INSN
3656 && !tinsn_has_symbolic_operands (tinsn
)
3657 && !xg_immeds_fit (tinsn
))
3659 istack
->ninsn
= stack_size
;
3672 /* Relax the assembly instruction at least "min_steps".
3673 Return the number of steps taken.
3675 For relaxation to correctly terminate, every relaxation chain must
3676 terminate in one of two ways:
3678 1. If the chain from one instruction to the next consists entirely of
3679 single instructions, then the chain *must* handle all possible
3680 immediates without failing. It must not ever fail because an
3681 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3682 chain is one example. L32R loads 32 bits, and there cannot be an
3683 immediate larger than 32 bits, so it satisfies this condition.
3684 Single instruction relaxation chains are as defined by
3685 xg_is_single_relaxable_instruction.
3687 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3688 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3690 Strictly speaking, in most cases you can violate condition 1 and be OK
3691 -- in particular when the last two instructions have the same single
3692 size. But nevertheless, you should guarantee the above two conditions.
3694 We could fix this so that single-instruction expansions correctly
3695 terminate when they can't handle the range, but the error messages are
3696 worse, and it actually turns out that in every case but one (18-bit wide
3697 branches), you need a multi-instruction expansion to get the full range
3698 anyway. And because 18-bit branches are handled identically to 15-bit
3699 branches, there isn't any point in changing it. */
3702 xg_assembly_relax (IStack
*istack
,
3705 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3706 offsetT pc_offset
, /* offset in fragment */
3707 int min_steps
, /* minimum conversion steps */
3708 long stretch
) /* number of bytes stretched so far */
3710 int steps_taken
= 0;
3712 /* Some of its immeds don't fit. Try to build a relaxed version.
3713 This may go through a couple of stages of single instruction
3714 transformations before we get there. */
3716 TInsn single_target
;
3718 int lateral_steps
= 0;
3719 int istack_size
= istack
->ninsn
;
3721 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3722 && steps_taken
>= min_steps
)
3724 istack_push (istack
, insn
);
3727 current_insn
= *insn
;
3729 /* Walk through all of the single instruction expansions. */
3730 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3733 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3736 if (steps_taken
>= min_steps
)
3738 istack_push (istack
, &single_target
);
3742 current_insn
= single_target
;
3745 /* Now check for a multi-instruction expansion. */
3746 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3748 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3751 if (steps_taken
>= min_steps
)
3753 istack_push (istack
, ¤t_insn
);
3758 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3760 if (steps_taken
>= min_steps
)
3764 istack
->ninsn
= istack_size
;
3767 /* It's not going to work -- use the original. */
3768 istack_push (istack
, insn
);
3774 xg_finish_frag (char *last_insn
,
3775 enum xtensa_relax_statesE frag_state
,
3776 enum xtensa_relax_statesE slot0_state
,
3778 bfd_boolean is_insn
)
3780 /* Finish off this fragment so that it has at LEAST the desired
3781 max_growth. If it doesn't fit in this fragment, close this one
3782 and start a new one. In either case, return a pointer to the
3783 beginning of the growth area. */
3787 frag_grow (max_growth
);
3788 old_frag
= frag_now
;
3790 frag_now
->fr_opcode
= last_insn
;
3792 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3794 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3795 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3797 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3798 xtensa_set_frag_assembly_state (frag_now
);
3800 /* Just to make sure that we did not split it up. */
3801 gas_assert (old_frag
->fr_next
== frag_now
);
3805 /* Return TRUE if the target frag is one of the next non-empty frags. */
3808 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3813 for (; fragP
; fragP
= fragP
->fr_next
)
3815 if (fragP
== target
)
3817 if (fragP
->fr_fix
!= 0)
3819 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3821 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3822 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3824 if (fragP
->fr_type
== rs_space
)
3832 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3834 xtensa_isa isa
= xtensa_default_isa
;
3836 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3841 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3842 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3845 for (i
= 0; i
< num_ops
; i
++)
3847 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3853 if (target_op
== -1)
3856 if (insn
->ntok
<= target_op
)
3859 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3862 sym
= insn
->tok
[target_op
].X_add_symbol
;
3866 if (insn
->tok
[target_op
].X_add_number
!= 0)
3869 target_frag
= symbol_get_frag (sym
);
3870 if (target_frag
== NULL
)
3873 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3874 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3882 xg_add_branch_and_loop_targets (TInsn
*insn
)
3884 xtensa_isa isa
= xtensa_default_isa
;
3885 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3887 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3890 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3891 && insn
->tok
[i
].X_op
== O_symbol
)
3892 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3896 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3897 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3901 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3903 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3904 && insn
->tok
[i
].X_op
== O_symbol
)
3906 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3907 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3908 if (S_IS_DEFINED (sym
))
3909 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3916 /* Return FALSE if no error. */
3919 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3924 switch (instr_spec
->typ
)
3927 new_insn
->insn_type
= ITYPE_INSN
;
3928 new_insn
->opcode
= instr_spec
->opcode
;
3930 case INSTR_LITERAL_DEF
:
3931 new_insn
->insn_type
= ITYPE_LITERAL
;
3932 new_insn
->opcode
= XTENSA_UNDEFINED
;
3934 case INSTR_LABEL_DEF
:
3937 new_insn
->is_specific_opcode
= FALSE
;
3938 new_insn
->debug_line
= old_insn
->debug_line
;
3939 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3941 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3944 const expressionS
*src_exp
;
3950 /* The expression must be the constant. */
3951 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3952 exp
= &new_insn
->tok
[b_op
->op_num
];
3953 set_expr_const (exp
, b_op
->op_data
);
3957 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3958 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3959 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3960 exp
= &new_insn
->tok
[b_op
->op_num
];
3961 copy_expr (exp
, src_exp
);
3966 as_bad (_("can't handle generation of literal/labels yet"));
3970 as_bad (_("can't handle undefined OP TYPE"));
3975 new_insn
->ntok
= num_ops
;
3980 /* Return TRUE if it was simplified. */
3983 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3985 TransitionRule
*rule
;
3986 BuildInstr
*insn_spec
;
3988 if (old_insn
->is_specific_opcode
|| !density_supported
)
3991 rule
= xg_instruction_match (old_insn
);
3995 insn_spec
= rule
->to_instr
;
3996 /* There should only be one. */
3997 gas_assert (insn_spec
!= NULL
);
3998 gas_assert (insn_spec
->next
== NULL
);
3999 if (insn_spec
->next
!= NULL
)
4002 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
4008 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4009 l32i.n. (2) Check the number of operands. (3) Place the instruction
4010 tokens into the stack or relax it and place multiple
4011 instructions/literals onto the stack. Return FALSE if no error. */
4014 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4018 bfd_boolean do_expand
;
4020 tinsn_init (&new_insn
);
4022 /* Narrow it if we can. xg_simplify_insn now does all the
4023 appropriate checking (e.g., for the density option). */
4024 if (xg_simplify_insn (orig_insn
, &new_insn
))
4025 orig_insn
= &new_insn
;
4027 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4029 if (orig_insn
->ntok
< noperands
)
4031 as_bad (ngettext ("found %d operand for '%s': Expected %d",
4032 "found %d operands for '%s': Expected %d",
4035 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4039 if (orig_insn
->ntok
> noperands
)
4040 as_warn (ngettext ("found %d operand for '%s': Expected %d",
4041 "found %d operands for '%s': Expected %d",
4044 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4047 /* If there are not enough operands, we will assert above. If there
4048 are too many, just cut out the extras here. */
4049 orig_insn
->ntok
= noperands
;
4051 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4054 /* Special case for extui opcode which has constraints not handled
4055 by the ordinary operand encoding checks. The number of operands
4056 and related syntax issues have already been checked. */
4057 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4059 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4060 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4061 if (shiftimm
+ maskimm
> 32)
4063 as_bad (_("immediate operands sum to greater than 32"));
4068 /* If the instruction will definitely need to be relaxed, it is better
4069 to expand it now for better scheduling. Decide whether to expand
4071 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4073 /* Calls should be expanded to longcalls only in the backend relaxation
4074 so that the assembly scheduler will keep the L32R/CALLX instructions
4076 if (is_direct_call_opcode (orig_insn
->opcode
))
4079 if (tinsn_has_symbolic_operands (orig_insn
))
4081 /* The values of symbolic operands are not known yet, so only expand
4082 now if an operand is "complex" (e.g., difference of symbols) and
4083 will have to be stored as a literal regardless of the value. */
4084 if (!tinsn_has_complex_operands (orig_insn
))
4087 else if (xg_immeds_fit (orig_insn
))
4091 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4093 istack_push (istack
, orig_insn
);
4099 /* Return TRUE if the section flags are marked linkonce
4100 or the name is .gnu.linkonce.*. */
4102 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4105 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4107 flagword flags
, link_once_flags
;
4109 flags
= bfd_get_section_flags (abfd
, sec
);
4110 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4112 /* Flags might not be set yet. */
4113 if (!link_once_flags
4114 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4115 link_once_flags
= SEC_LINK_ONCE
;
4117 return (link_once_flags
!= 0);
4122 xtensa_add_literal_sym (symbolS
*sym
)
4126 l
= XNEW (sym_list
);
4128 l
->next
= literal_syms
;
4134 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4136 static int lit_num
= 0;
4137 static char name
[256];
4140 sprintf (name
, ".L_lit_sym%d", lit_num
);
4142 /* Create a local symbol. If it is in a linkonce section, we have to
4143 be careful to make sure that if it is used in a relocation that the
4144 symbol will be in the output file. */
4145 if (get_is_linkonce_section (stdoutput
, sec
))
4147 symbolP
= symbol_new (name
, sec
, 0, frag
);
4148 S_CLEAR_EXTERNAL (symbolP
);
4149 /* symbolP->local = 1; */
4152 symbolP
= symbol_new (name
, sec
, 0, frag
);
4154 xtensa_add_literal_sym (symbolP
);
4161 /* Currently all literals that are generated here are 32-bit L32R targets. */
4164 xg_assemble_literal (/* const */ TInsn
*insn
)
4167 symbolS
*lit_sym
= NULL
;
4168 bfd_reloc_code_real_type reloc
;
4169 bfd_boolean pcrel
= FALSE
;
4172 /* size = 4 for L32R. It could easily be larger when we move to
4173 larger constants. Add a parameter later. */
4174 offsetT litsize
= 4;
4175 offsetT litalign
= 2; /* 2^2 = 4 */
4176 expressionS saved_loc
;
4177 expressionS
* emit_val
;
4179 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4181 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4182 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4184 xtensa_switch_to_literal_fragment (&state
);
4186 emit_val
= &insn
->tok
[0];
4187 if (emit_val
->X_op
== O_big
)
4189 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4192 /* This happens when someone writes a "movi a2, big_number". */
4193 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4194 _("invalid immediate"));
4195 xtensa_restore_emit_state (&state
);
4200 /* Force a 4-byte align here. Note that this opens a new frag, so all
4201 literals done with this function have a frag to themselves. That's
4202 important for the way text section literals work. */
4203 frag_align (litalign
, 0, 0);
4204 record_alignment (now_seg
, litalign
);
4206 switch (emit_val
->X_op
)
4216 p
= frag_more (litsize
);
4217 xtensa_set_frag_assembly_state (frag_now
);
4218 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4219 if (emit_val
->X_add_symbol
)
4220 emit_val
->X_op
= O_symbol
;
4222 emit_val
->X_op
= O_constant
;
4223 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4224 litsize
, emit_val
, pcrel
, reloc
);
4228 emit_expr (emit_val
, litsize
);
4232 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4233 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4234 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4235 lit_sym
= frag_now
->fr_symbol
;
4238 xtensa_restore_emit_state (&state
);
4244 xg_assemble_literal_space (/* const */ int size
, int slot
)
4247 /* We might have to do something about this alignment. It only
4248 takes effect if something is placed here. */
4249 offsetT litalign
= 2; /* 2^2 = 4 */
4250 fragS
*lit_saved_frag
;
4252 gas_assert (size
% 4 == 0);
4254 xtensa_switch_to_literal_fragment (&state
);
4256 /* Force a 4-byte align here. */
4257 frag_align (litalign
, 0, 0);
4258 record_alignment (now_seg
, litalign
);
4262 lit_saved_frag
= frag_now
;
4263 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4264 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4265 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4268 xtensa_restore_emit_state (&state
);
4269 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4273 /* Put in a fixup record based on the opcode.
4274 Return TRUE on success. */
4277 xg_add_opcode_fix (TInsn
*tinsn
,
4285 xtensa_opcode opcode
= tinsn
->opcode
;
4286 bfd_reloc_code_real_type reloc
;
4287 reloc_howto_type
*howto
;
4291 reloc
= BFD_RELOC_NONE
;
4293 /* First try the special cases for "alternate" relocs. */
4294 if (opcode
== xtensa_l32r_opcode
)
4296 if (fragP
->tc_frag_data
.use_absolute_literals
)
4297 reloc
= encode_alt_reloc (slot
);
4299 else if (opcode
== xtensa_const16_opcode
)
4301 if (exp
->X_op
== O_lo16
)
4303 reloc
= encode_reloc (slot
);
4304 exp
->X_op
= O_symbol
;
4306 else if (exp
->X_op
== O_hi16
)
4308 reloc
= encode_alt_reloc (slot
);
4309 exp
->X_op
= O_symbol
;
4313 if (opnum
!= get_relaxable_immed (opcode
))
4315 as_bad (_("invalid relocation for operand %i of '%s'"),
4316 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4320 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4321 into the symbol table where the generic portions of the assembler
4322 won't know what to do with them. */
4323 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4325 as_bad (_("invalid expression for operand %i of '%s'"),
4326 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4330 /* Next try the generic relocs. */
4331 if (reloc
== BFD_RELOC_NONE
)
4332 reloc
= encode_reloc (slot
);
4333 if (reloc
== BFD_RELOC_NONE
)
4335 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4339 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4342 as_bad (_("undefined symbol for opcode \"%s\""),
4343 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4347 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4348 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4349 howto
->pc_relative
, reloc
);
4350 the_fix
->fx_no_overflow
= 1;
4351 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4352 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4353 the_fix
->tc_fix_data
.slot
= slot
;
4360 xg_emit_insn_to_buf (TInsn
*tinsn
,
4364 bfd_boolean build_fix
)
4366 static xtensa_insnbuf insnbuf
= NULL
;
4367 bfd_boolean has_symbolic_immed
= FALSE
;
4368 bfd_boolean ok
= TRUE
;
4371 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4373 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4374 if (has_symbolic_immed
&& build_fix
)
4377 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4378 int slot
= xg_get_single_slot (tinsn
->opcode
);
4379 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4380 expressionS
*exp
= &tinsn
->tok
[opnum
];
4382 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4385 fragP
->tc_frag_data
.is_insn
= TRUE
;
4386 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4387 (unsigned char *) buf
, 0);
4393 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4395 symbolS
*sym
= get_special_literal_symbol ();
4399 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4400 for (i
= 0; i
< insn
->ntok
; i
++)
4401 if (insn
->tok
[i
].X_add_symbol
== sym
)
4402 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4408 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4410 symbolS
*sym
= get_special_label_symbol ();
4412 for (i
= 0; i
< insn
->ntok
; i
++)
4413 if (insn
->tok
[i
].X_add_symbol
== sym
)
4414 insn
->tok
[i
].X_add_symbol
= label_sym
;
4419 /* Return TRUE if the instruction can write to the specified
4420 integer register. */
4423 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4427 xtensa_isa isa
= xtensa_default_isa
;
4429 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4431 for (i
= 0; i
< num_ops
; i
++)
4434 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4435 if ((inout
== 'o' || inout
== 'm')
4436 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4438 xtensa_regfile opnd_rf
=
4439 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4440 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4442 if ((insn
->tok
[i
].X_op
== O_register
)
4443 && (insn
->tok
[i
].X_add_number
== regnum
))
4453 is_bad_loopend_opcode (const TInsn
*tinsn
)
4455 xtensa_opcode opcode
= tinsn
->opcode
;
4457 if (opcode
== XTENSA_UNDEFINED
)
4460 if (opcode
== xtensa_call0_opcode
4461 || opcode
== xtensa_callx0_opcode
4462 || opcode
== xtensa_call4_opcode
4463 || opcode
== xtensa_callx4_opcode
4464 || opcode
== xtensa_call8_opcode
4465 || opcode
== xtensa_callx8_opcode
4466 || opcode
== xtensa_call12_opcode
4467 || opcode
== xtensa_callx12_opcode
4468 || opcode
== xtensa_isync_opcode
4469 || opcode
== xtensa_ret_opcode
4470 || opcode
== xtensa_ret_n_opcode
4471 || opcode
== xtensa_retw_opcode
4472 || opcode
== xtensa_retw_n_opcode
4473 || opcode
== xtensa_waiti_opcode
4474 || opcode
== xtensa_rsr_lcount_opcode
)
4481 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4482 This allows the debugger to add unaligned labels.
4483 Also, the assembler generates stabs labels that need
4484 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4487 is_unaligned_label (symbolS
*sym
)
4489 const char *name
= S_GET_NAME (sym
);
4490 static size_t fake_size
= 0;
4494 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4497 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4499 fake_size
= strlen (FAKE_LABEL_NAME
);
4502 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4503 && (name
[fake_size
] == 'F'
4504 || name
[fake_size
] == 'L'
4505 || (name
[fake_size
] == 'e'
4506 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4514 next_non_empty_frag (const fragS
*fragP
)
4516 fragS
*next_fragP
= fragP
->fr_next
;
4518 /* Sometimes an empty will end up here due storage allocation issues.
4519 So we have to skip until we find something legit. */
4520 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4521 next_fragP
= next_fragP
->fr_next
;
4523 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4531 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4533 xtensa_opcode out_opcode
;
4534 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4536 if (next_fragP
== NULL
)
4539 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4540 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4542 *opcode
= out_opcode
;
4550 frag_format_size (const fragS
*fragP
)
4552 static xtensa_insnbuf insnbuf
= NULL
;
4553 xtensa_isa isa
= xtensa_default_isa
;
4558 insnbuf
= xtensa_insnbuf_alloc (isa
);
4561 return XTENSA_UNDEFINED
;
4563 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4564 (unsigned char *) fragP
->fr_literal
, 0);
4566 fmt
= xtensa_format_decode (isa
, insnbuf
);
4567 if (fmt
== XTENSA_UNDEFINED
)
4568 return XTENSA_UNDEFINED
;
4569 fmt_size
= xtensa_format_length (isa
, fmt
);
4571 /* If the next format won't be changing due to relaxation, just
4572 return the length of the first format. */
4573 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4576 /* If during relaxation we have to pull an instruction out of a
4577 multi-slot instruction, we will return the more conservative
4578 number. This works because alignment on bigger instructions
4579 is more restrictive than alignment on smaller instructions.
4580 This is more conservative than we would like, but it happens
4583 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4586 /* If we aren't doing one of our own relaxations or it isn't
4587 slot-based, then the insn size won't change. */
4588 if (fragP
->fr_type
!= rs_machine_dependent
)
4590 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4593 /* If an instruction is about to grow, return the longer size. */
4594 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4595 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4596 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4598 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4599 instruction in the relaxed version is of length 3. (The case
4600 where we have to pull the instruction out of a FLIX bundle
4601 is handled conservatively above.) However, frags with opcodes
4602 that are expanding to wide branches end up having formats that
4603 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4604 we can't tell directly what format the relaxer picked. This
4605 is a wart in the design of the relaxer that should someday be
4606 fixed, but would require major changes, or at least should
4607 be accompanied by major changes to make use of that data.
4609 In any event, we can tell that we are expanding from a single-slot
4610 format to a wider one with the logic below. */
4613 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4615 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4617 if (relaxed_size
== xtensa_format_length (isa
, i
))
4618 return relaxed_size
;
4624 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4625 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4632 next_frag_format_size (const fragS
*fragP
)
4634 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4635 return frag_format_size (next_fragP
);
4639 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4640 required two-byte instructions to be treated as three-byte instructions
4641 for loop instruction alignment. This restriction was removed beginning
4642 with Xtensa LX. Now the only requirement on loop instruction alignment
4643 is that the first instruction of the loop must appear at an address that
4644 does not cross a fetch boundary. */
4647 get_loop_align_size (int insn_size
)
4649 if (insn_size
== XTENSA_UNDEFINED
)
4650 return xtensa_fetch_width
;
4652 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4659 /* If the next legit fragment is an end-of-loop marker,
4660 switch its state so it will instantiate a NOP. */
4663 update_next_frag_state (fragS
*fragP
)
4665 fragS
*next_fragP
= fragP
->fr_next
;
4666 fragS
*new_target
= NULL
;
4670 /* We are guaranteed there will be one of these... */
4671 while (!(next_fragP
->fr_type
== rs_machine_dependent
4672 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4673 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4674 next_fragP
= next_fragP
->fr_next
;
4676 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4677 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4678 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4680 /* ...and one of these. */
4681 new_target
= next_fragP
->fr_next
;
4682 while (!(new_target
->fr_type
== rs_machine_dependent
4683 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4684 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4685 new_target
= new_target
->fr_next
;
4687 gas_assert (new_target
->fr_type
== rs_machine_dependent
4688 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4689 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4692 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4694 if (next_fragP
->fr_type
== rs_machine_dependent
4695 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4697 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4701 next_fragP
= next_fragP
->fr_next
;
4707 next_frag_is_branch_target (const fragS
*fragP
)
4709 /* Sometimes an empty will end up here due to storage allocation issues,
4710 so we have to skip until we find something legit. */
4711 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4713 if (fragP
->tc_frag_data
.is_branch_target
)
4715 if (fragP
->fr_fix
!= 0)
4723 next_frag_is_loop_target (const fragS
*fragP
)
4725 /* Sometimes an empty will end up here due storage allocation issues.
4726 So we have to skip until we find something legit. */
4727 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4729 if (fragP
->tc_frag_data
.is_loop_target
)
4731 if (fragP
->fr_fix
!= 0)
4738 /* As specified in the relaxation table, when a loop instruction is
4739 relaxed, there are 24 bytes between the loop instruction itself and
4740 the first instruction in the loop. */
4742 #define RELAXED_LOOP_INSN_BYTES 24
4745 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4747 const fragS
*next_fragp
= fragp
->fr_next
;
4748 xtensa_opcode next_opcode
;
4750 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4753 /* Sometimes an empty will end up here due to storage allocation issues,
4754 so we have to skip until we find something legit. */
4755 while (next_fragp
->fr_fix
== 0)
4756 next_fragp
= next_fragp
->fr_next
;
4758 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4761 /* There is some implicit knowledge encoded in here.
4762 The LOOP instructions that are NOT RELAX_IMMED have
4763 been relaxed. Note that we can assume that the LOOP
4764 instruction is in slot 0 because loops aren't bundleable. */
4765 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4766 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4772 /* Mark a location where we can later insert literal frags. Update
4773 the section's literal_pool_loc, so subsequent literals can be
4774 placed nearest to their use. */
4777 xtensa_mark_literal_pool_location (void)
4779 /* Any labels pointing to the current location need
4780 to be adjusted to after the literal pool. */
4782 fragS
*pool_location
;
4784 if (use_literal_section
)
4787 /* We stash info in these frags so we can later move the literal's
4788 fixes into this frchain's fix list. */
4789 pool_location
= frag_now
;
4790 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4791 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4792 /* Just record this frag. */
4793 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4794 frag_variant (rs_machine_dependent
, 0, 0,
4795 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4796 xtensa_set_frag_assembly_state (frag_now
);
4797 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4798 frag_variant (rs_machine_dependent
, 0, 0,
4799 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4800 xtensa_set_frag_assembly_state (frag_now
);
4802 /* Now put a frag into the literal pool that points to this location. */
4803 set_literal_pool_location (now_seg
, pool_location
);
4804 xtensa_switch_to_non_abs_literal_fragment (&s
);
4805 frag_align (2, 0, 0);
4806 record_alignment (now_seg
, 2);
4808 /* Close whatever frag is there. */
4809 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4810 xtensa_set_frag_assembly_state (frag_now
);
4811 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4812 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4813 xtensa_restore_emit_state (&s
);
4814 xtensa_set_frag_assembly_state (frag_now
);
4818 /* Build a nop of the correct size into tinsn. */
4821 build_nop (TInsn
*tinsn
, int size
)
4827 tinsn
->opcode
= xtensa_nop_n_opcode
;
4829 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4830 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4834 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4836 tinsn
->opcode
= xtensa_or_opcode
;
4837 set_expr_const (&tinsn
->tok
[0], 1);
4838 set_expr_const (&tinsn
->tok
[1], 1);
4839 set_expr_const (&tinsn
->tok
[2], 1);
4843 tinsn
->opcode
= xtensa_nop_opcode
;
4845 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4850 /* Assemble a NOP of the requested size in the buffer. User must have
4851 allocated "buf" with at least "size" bytes. */
4854 assemble_nop (int size
, char *buf
)
4856 static xtensa_insnbuf insnbuf
= NULL
;
4859 build_nop (&tinsn
, size
);
4862 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4864 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4865 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4866 (unsigned char *) buf
, 0);
4870 /* Return the number of bytes for the offset of the expanded loop
4871 instruction. This should be incorporated into the relaxation
4872 specification but is hard-coded here. This is used to auto-align
4873 the loop instruction. It is invalid to call this function if the
4874 configuration does not have loops or if the opcode is not a loop
4878 get_expanded_loop_offset (xtensa_opcode opcode
)
4880 /* This is the OFFSET of the loop instruction in the expanded loop.
4881 This MUST correspond directly to the specification of the loop
4882 expansion. It will be validated on fragment conversion. */
4883 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4884 if (opcode
== xtensa_loop_opcode
)
4886 if (opcode
== xtensa_loopnez_opcode
)
4888 if (opcode
== xtensa_loopgtz_opcode
)
4890 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4896 get_literal_pool_location (segT seg
)
4898 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4899 struct litpool_frag
*lpf
;
4900 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4904 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4905 { /* Skip "candidates" for now. */
4906 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4910 /* Must convert a lower-priority pool. */
4911 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4913 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4916 /* Still no match -- try for a low priority pool. */
4917 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4919 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4923 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4928 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4930 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4934 /* Set frag assembly state should be called when a new frag is
4935 opened and after a frag has been closed. */
4938 xtensa_set_frag_assembly_state (fragS
*fragP
)
4940 if (!density_supported
)
4941 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4943 /* This function is called from subsegs_finish, which is called
4944 after xtensa_end, so we can't use "use_transform" or
4945 "use_schedule" here. */
4946 if (!directive_state
[directive_transform
])
4947 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4948 if (directive_state
[directive_longcalls
])
4949 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4950 fragP
->tc_frag_data
.use_absolute_literals
=
4951 directive_state
[directive_absolute_literals
];
4952 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4957 relaxable_section (asection
*sec
)
4959 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4960 && strcmp (sec
->name
, ".eh_frame") != 0);
4965 xtensa_mark_frags_for_org (void)
4969 /* Walk over each fragment of all of the current segments. If we find
4970 a .org frag in any of the segments, mark all frags prior to it as
4971 "no transform", which will prevent linker optimizations from messing
4972 up the .org distance. This should be done after
4973 xtensa_find_unmarked_state_frags, because we don't want to worry here
4974 about that function trashing the data we save here. */
4976 for (seclist
= &stdoutput
->sections
;
4977 seclist
&& *seclist
;
4978 seclist
= &(*seclist
)->next
)
4980 segT sec
= *seclist
;
4981 segment_info_type
*seginfo
;
4984 flags
= bfd_get_section_flags (stdoutput
, sec
);
4985 if (flags
& SEC_DEBUGGING
)
4987 if (!(flags
& SEC_ALLOC
))
4990 seginfo
= seg_info (sec
);
4991 if (seginfo
&& seginfo
->frchainP
)
4993 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4994 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4995 fragP
= fragP
->fr_next
)
4997 /* cvt_frag_to_fill has changed the fr_type of org frags to
4998 rs_fill, so use the value as cached in rs_subtype here. */
4999 if (fragP
->fr_subtype
== RELAX_ORG
)
5001 while (last_fragP
!= fragP
->fr_next
)
5003 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
5004 last_fragP
= last_fragP
->fr_next
;
5014 xtensa_find_unmarked_state_frags (void)
5018 /* Walk over each fragment of all of the current segments. For each
5019 unmarked fragment, mark it with the same info as the previous
5021 for (seclist
= &stdoutput
->sections
;
5022 seclist
&& *seclist
;
5023 seclist
= &(*seclist
)->next
)
5025 segT sec
= *seclist
;
5026 segment_info_type
*seginfo
;
5029 flags
= bfd_get_section_flags (stdoutput
, sec
);
5030 if (flags
& SEC_DEBUGGING
)
5032 if (!(flags
& SEC_ALLOC
))
5035 seginfo
= seg_info (sec
);
5036 if (seginfo
&& seginfo
->frchainP
)
5038 fragS
*last_fragP
= 0;
5039 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5040 fragP
= fragP
->fr_next
)
5042 if (fragP
->fr_fix
!= 0
5043 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5045 if (last_fragP
== 0)
5047 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5048 _("assembly state not set for first frag in section %s"),
5053 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5054 fragP
->tc_frag_data
.is_no_density
=
5055 last_fragP
->tc_frag_data
.is_no_density
;
5056 fragP
->tc_frag_data
.is_no_transform
=
5057 last_fragP
->tc_frag_data
.is_no_transform
;
5058 fragP
->tc_frag_data
.use_longcalls
=
5059 last_fragP
->tc_frag_data
.use_longcalls
;
5060 fragP
->tc_frag_data
.use_absolute_literals
=
5061 last_fragP
->tc_frag_data
.use_absolute_literals
;
5064 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5073 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5075 void *unused ATTRIBUTE_UNUSED
)
5077 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5078 segment_info_type
*seginfo
= seg_info (sec
);
5079 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5081 if (flags
& SEC_CODE
)
5083 xtensa_isa isa
= xtensa_default_isa
;
5084 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5085 while (frag
!= NULL
)
5087 if (frag
->tc_frag_data
.is_branch_target
)
5090 addressT branch_align
, frag_addr
;
5093 xtensa_insnbuf_from_chars
5094 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5095 fmt
= xtensa_format_decode (isa
, insnbuf
);
5096 op_size
= xtensa_format_length (isa
, fmt
);
5097 branch_align
= 1 << branch_align_power (sec
);
5098 frag_addr
= frag
->fr_address
% branch_align
;
5099 if (frag_addr
+ op_size
> branch_align
)
5100 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5101 _("unaligned branch target: %d bytes at 0x%lx"),
5102 op_size
, (long) frag
->fr_address
);
5104 frag
= frag
->fr_next
;
5106 xtensa_insnbuf_free (isa
, insnbuf
);
5112 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5114 void *unused ATTRIBUTE_UNUSED
)
5116 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5117 segment_info_type
*seginfo
= seg_info (sec
);
5118 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5119 xtensa_isa isa
= xtensa_default_isa
;
5121 if (flags
& SEC_CODE
)
5123 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5124 while (frag
!= NULL
)
5126 if (frag
->tc_frag_data
.is_first_loop_insn
)
5132 if (frag
->fr_fix
== 0)
5133 frag
= next_non_empty_frag (frag
);
5137 xtensa_insnbuf_from_chars
5138 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5139 fmt
= xtensa_format_decode (isa
, insnbuf
);
5140 op_size
= xtensa_format_length (isa
, fmt
);
5141 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5143 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5144 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5145 _("unaligned loop: %d bytes at 0x%lx"),
5146 op_size
, (long) frag
->fr_address
);
5149 frag
= frag
->fr_next
;
5151 xtensa_insnbuf_free (isa
, insnbuf
);
5157 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5159 xtensa_isa isa
= xtensa_default_isa
;
5160 static xtensa_insnbuf insnbuf
= NULL
;
5161 static xtensa_insnbuf slotbuf
= NULL
;
5164 bfd_boolean alt_reloc
;
5165 xtensa_opcode opcode
;
5166 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5168 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5170 as_fatal (_("unexpected fix"));
5174 insnbuf
= xtensa_insnbuf_alloc (isa
);
5175 slotbuf
= xtensa_insnbuf_alloc (isa
);
5178 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5179 fmt
= xtensa_format_decode (isa
, insnbuf
);
5180 if (fmt
== XTENSA_UNDEFINED
)
5181 as_fatal (_("undecodable fix"));
5182 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5183 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5184 if (opcode
== XTENSA_UNDEFINED
)
5185 as_fatal (_("undecodable fix"));
5187 /* CONST16 immediates are not PC-relative, despite the fact that we
5188 reuse the normal PC-relative operand relocations for the low part
5189 of a CONST16 operand. */
5190 if (opcode
== xtensa_const16_opcode
)
5193 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5194 get_relaxable_immed (opcode
), val
,
5195 fixP
->fx_file
, fixP
->fx_line
);
5197 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5198 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5204 /* External Functions and Other GAS Hooks. */
5207 xtensa_target_format (void)
5209 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5214 xtensa_file_arch_init (bfd
*abfd
)
5216 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5221 md_number_to_chars (char *buf
, valueT val
, int n
)
5223 if (target_big_endian
)
5224 number_to_chars_bigendian (buf
, val
, n
);
5226 number_to_chars_littleendian (buf
, val
, n
);
5230 xg_init_global_config (void)
5232 target_big_endian
= XCHAL_HAVE_BE
;
5234 density_supported
= XCHAL_HAVE_DENSITY
;
5235 absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
5236 xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
5238 directive_state
[directive_density
] = XCHAL_HAVE_DENSITY
;
5239 directive_state
[directive_absolute_literals
] = XSHAL_USE_ABSOLUTE_LITERALS
;
5243 xtensa_init (int argc ATTRIBUTE_UNUSED
, char **argv ATTRIBUTE_UNUSED
)
5245 xg_init_global_config ();
5248 /* This function is called once, at assembler startup time. It should
5249 set up all the tables, etc. that the MD part of the assembler will
5255 segT current_section
= now_seg
;
5256 int current_subsec
= now_subseg
;
5260 xtensa_default_isa
= xtensa_isa_init (0, 0);
5261 isa
= xtensa_default_isa
;
5265 /* Set up the literal sections. */
5266 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5268 subseg_set (current_section
, current_subsec
);
5270 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5271 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5272 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5273 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5274 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5275 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5276 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5277 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5278 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5279 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5280 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5281 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5282 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5283 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5284 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5285 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5286 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5287 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5288 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5289 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5290 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5291 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5292 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5293 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5294 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5295 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5296 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5297 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5298 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5299 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5300 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5302 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5304 int format_slots
= xtensa_format_num_slots (isa
, i
);
5305 if (format_slots
> config_max_slots
)
5306 config_max_slots
= format_slots
;
5309 xg_init_vinsn (&cur_vinsn
);
5311 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5313 init_op_placement_info_table ();
5315 /* Set up the assembly state. */
5316 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5317 xtensa_set_frag_assembly_state (frag_now
);
5321 /* TC_INIT_FIX_DATA hook */
5324 xtensa_init_fix_data (fixS
*x
)
5326 x
->tc_fix_data
.slot
= 0;
5327 x
->tc_fix_data
.X_add_symbol
= NULL
;
5328 x
->tc_fix_data
.X_add_number
= 0;
5332 /* tc_frob_label hook */
5335 xtensa_frob_label (symbolS
*sym
)
5339 if (cur_vinsn
.inside_bundle
)
5341 as_bad (_("labels are not valid inside bundles"));
5345 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5347 /* Since the label was already attached to a frag associated with the
5348 previous basic block, it now needs to be reset to the current frag. */
5349 symbol_set_frag (sym
, frag_now
);
5350 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5352 if (generating_literals
)
5353 xtensa_add_literal_sym (sym
);
5355 xtensa_add_insn_label (sym
);
5357 if (symbol_get_tc (sym
)->is_loop_target
)
5359 if ((get_last_insn_flags (now_seg
, now_subseg
)
5360 & FLAG_IS_BAD_LOOPEND
) != 0)
5361 as_bad (_("invalid last instruction for a zero-overhead loop"));
5363 xtensa_set_frag_assembly_state (frag_now
);
5364 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5365 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5367 xtensa_set_frag_assembly_state (frag_now
);
5368 xtensa_move_labels (frag_now
, 0);
5371 /* No target aligning in the absolute section. */
5372 if (now_seg
!= absolute_section
5373 && !is_unaligned_label (sym
)
5374 && !generating_literals
)
5376 xtensa_set_frag_assembly_state (frag_now
);
5378 if (do_align_targets ())
5379 frag_var (rs_machine_dependent
, 0, (int) freq
,
5380 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5381 frag_now
->fr_offset
, NULL
);
5383 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5384 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5385 xtensa_set_frag_assembly_state (frag_now
);
5386 xtensa_move_labels (frag_now
, 0);
5389 /* We need to mark the following properties even if we aren't aligning. */
5391 /* If the label is already known to be a branch target, i.e., a
5392 forward branch, mark the frag accordingly. Backward branches
5393 are handled by xg_add_branch_and_loop_targets. */
5394 if (symbol_get_tc (sym
)->is_branch_target
)
5395 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5397 /* Loops only go forward, so they can be identified here. */
5398 if (symbol_get_tc (sym
)->is_loop_target
)
5399 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5401 dwarf2_emit_label (sym
);
5405 /* tc_unrecognized_line hook */
5408 xtensa_unrecognized_line (int ch
)
5413 if (cur_vinsn
.inside_bundle
== 0)
5415 /* PR8110: Cannot emit line number info inside a FLIX bundle
5416 when using --gstabs. Temporarily disable debug info. */
5417 generate_lineno_debug ();
5418 if (debug_type
== DEBUG_STABS
)
5420 xt_saved_debug_type
= debug_type
;
5421 debug_type
= DEBUG_NONE
;
5424 cur_vinsn
.inside_bundle
= 1;
5428 as_bad (_("extra opening brace"));
5434 if (cur_vinsn
.inside_bundle
)
5435 finish_vinsn (&cur_vinsn
);
5438 as_bad (_("extra closing brace"));
5443 as_bad (_("syntax error"));
5450 /* md_flush_pending_output hook */
5453 xtensa_flush_pending_output (void)
5455 /* This line fixes a bug where automatically generated gstabs info
5456 separates a function label from its entry instruction, ending up
5457 with the literal position between the function label and the entry
5458 instruction and crashing code. It only happens with --gstabs and
5459 --text-section-literals, and when several other obscure relaxation
5460 conditions are met. */
5461 if (outputting_stabs_line_debug
)
5464 if (cur_vinsn
.inside_bundle
)
5465 as_bad (_("missing closing brace"));
5467 /* If there is a non-zero instruction fragment, close it. */
5468 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5470 frag_wane (frag_now
);
5472 xtensa_set_frag_assembly_state (frag_now
);
5474 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5476 xtensa_clear_insn_labels ();
5480 /* We had an error while parsing an instruction. The string might look
5481 like this: "insn arg1, arg2 }". If so, we need to see the closing
5482 brace and reset some fields. Otherwise, the vinsn never gets closed
5483 and the num_slots field will grow past the end of the array of slots,
5484 and bad things happen. */
5487 error_reset_cur_vinsn (void)
5489 if (cur_vinsn
.inside_bundle
)
5491 if (*input_line_pointer
== '}'
5492 || *(input_line_pointer
- 1) == '}'
5493 || *(input_line_pointer
- 2) == '}')
5494 xg_clear_vinsn (&cur_vinsn
);
5500 md_assemble (char *str
)
5502 xtensa_isa isa
= xtensa_default_isa
;
5505 bfd_boolean has_underbar
= FALSE
;
5506 char *arg_strings
[MAX_INSN_ARGS
];
5508 TInsn orig_insn
; /* Original instruction from the input. */
5510 tinsn_init (&orig_insn
);
5512 /* Split off the opcode. */
5513 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5514 opname
= xstrndup (str
, opnamelen
);
5516 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5519 as_bad (_("syntax error"));
5523 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5526 /* Check for an underbar prefix. */
5529 has_underbar
= TRUE
;
5533 orig_insn
.insn_type
= ITYPE_INSN
;
5535 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5536 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5538 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5539 extra argument and set the opcode to "CALLXn". */
5540 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5541 && strncasecmp (opname
, "callx", 5) == 0)
5543 unsigned long window_size
;
5546 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5547 if (suffix
!= opname
+ 5
5548 && (window_size
== 0
5551 || window_size
== 12)
5552 && strcasecmp (suffix
, ".tls") == 0)
5554 switch (window_size
)
5556 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5557 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5558 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5559 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5563 as_bad (_("wrong number of operands for '%s'"), opname
);
5566 bfd_reloc_code_real_type reloc
;
5567 char *old_input_line_pointer
;
5568 expressionS
*tok
= &orig_insn
.extra_arg
;
5570 old_input_line_pointer
= input_line_pointer
;
5571 input_line_pointer
= arg_strings
[num_args
- 1];
5574 if (tok
->X_op
== O_symbol
5575 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5576 == BFD_RELOC_XTENSA_TLS_CALL
))
5577 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5579 as_bad (_("bad relocation expression for '%s'"), opname
);
5581 input_line_pointer
= old_input_line_pointer
;
5587 /* Special case: Check for "j.l" pseudo op. */
5588 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5589 && strncasecmp (opname
, "j.l", 3) == 0)
5592 as_bad (_("wrong number of operands for '%s'"), opname
);
5595 char *old_input_line_pointer
;
5596 expressionS
*tok
= &orig_insn
.extra_arg
;
5598 old_input_line_pointer
= input_line_pointer
;
5599 input_line_pointer
= arg_strings
[num_args
- 1];
5601 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5602 input_line_pointer
= old_input_line_pointer
;
5605 orig_insn
.opcode
= xtensa_j_opcode
;
5609 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5611 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5612 if (fmt
== XTENSA_UNDEFINED
)
5614 as_bad (_("unknown opcode or format name '%s'"), opname
);
5615 error_reset_cur_vinsn ();
5618 if (!cur_vinsn
.inside_bundle
)
5620 as_bad (_("format names only valid inside bundles"));
5621 error_reset_cur_vinsn ();
5624 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5625 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5627 cur_vinsn
.format
= fmt
;
5628 free (has_underbar
? opname
- 1 : opname
);
5629 error_reset_cur_vinsn ();
5633 /* Parse the arguments. */
5634 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5636 as_bad (_("syntax error"));
5637 error_reset_cur_vinsn ();
5641 /* Free the opcode and argument strings, now that they've been parsed. */
5642 free (has_underbar
? opname
- 1 : opname
);
5644 while (num_args
-- > 0)
5645 free (arg_strings
[num_args
]);
5647 /* Get expressions for invisible operands. */
5648 if (get_invisible_operands (&orig_insn
))
5650 error_reset_cur_vinsn ();
5654 /* Check for the right number and type of arguments. */
5655 if (tinsn_check_arguments (&orig_insn
))
5657 error_reset_cur_vinsn ();
5661 /* Record the line number for each TInsn, because a FLIX bundle may be
5662 spread across multiple input lines and individual instructions may be
5663 moved around in some cases. */
5664 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5665 dwarf2_where (&orig_insn
.debug_line
);
5666 dwarf2_consume_line_info ();
5668 xg_add_branch_and_loop_targets (&orig_insn
);
5670 /* Check that immediate value for ENTRY is >= 16. */
5671 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5673 expressionS
*exp
= &orig_insn
.tok
[2];
5674 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5675 as_warn (_("entry instruction with stack decrement < 16"));
5679 assemble_tokens (opcode, tok, ntok);
5680 expand the tokens from the orig_insn into the
5681 stack of instructions that will not expand
5682 unless required at relaxation time. */
5684 if (!cur_vinsn
.inside_bundle
)
5685 emit_single_op (&orig_insn
);
5686 else /* We are inside a bundle. */
5688 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5689 cur_vinsn
.num_slots
++;
5690 if (*input_line_pointer
== '}'
5691 || *(input_line_pointer
- 1) == '}'
5692 || *(input_line_pointer
- 2) == '}')
5693 finish_vinsn (&cur_vinsn
);
5696 /* We've just emitted a new instruction so clear the list of labels. */
5697 xtensa_clear_insn_labels ();
5699 xtensa_check_frag_count ();
5703 /* HANDLE_ALIGN hook */
5705 /* For a .align directive, we mark the previous block with the alignment
5706 information. This will be placed in the object file in the
5707 property section corresponding to this section. */
5710 xtensa_handle_align (fragS
*fragP
)
5713 && ! fragP
->tc_frag_data
.is_literal
5714 && (fragP
->fr_type
== rs_align
5715 || fragP
->fr_type
== rs_align_code
)
5716 && fragP
->fr_offset
> 0
5717 && now_seg
!= bss_section
)
5719 fragP
->tc_frag_data
.is_align
= TRUE
;
5720 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5723 if (fragP
->fr_type
== rs_align_test
)
5726 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5728 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5729 _("unaligned entry instruction"));
5732 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5733 fragP
->fr_subtype
= RELAX_ORG
;
5737 /* TC_FRAG_INIT hook */
5740 xtensa_frag_init (fragS
*frag
)
5742 xtensa_set_frag_assembly_state (frag
);
5747 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5753 /* Round up a section size to the appropriate boundary. */
5756 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5758 return size
; /* Byte alignment is fine. */
5763 md_pcrel_from (fixS
*fixP
)
5766 static xtensa_insnbuf insnbuf
= NULL
;
5767 static xtensa_insnbuf slotbuf
= NULL
;
5770 xtensa_opcode opcode
;
5773 xtensa_isa isa
= xtensa_default_isa
;
5774 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5775 bfd_boolean alt_reloc
;
5777 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5780 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5785 insnbuf
= xtensa_insnbuf_alloc (isa
);
5786 slotbuf
= xtensa_insnbuf_alloc (isa
);
5789 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5790 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5791 fmt
= xtensa_format_decode (isa
, insnbuf
);
5793 if (fmt
== XTENSA_UNDEFINED
)
5794 as_fatal (_("bad instruction format"));
5796 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5797 as_fatal (_("invalid relocation"));
5799 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5800 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5802 /* Check for "alternate" relocations (operand not specified). None
5803 of the current uses for these are really PC-relative. */
5804 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5806 if (opcode
!= xtensa_l32r_opcode
5807 && opcode
!= xtensa_const16_opcode
)
5808 as_fatal (_("invalid relocation for '%s' instruction"),
5809 xtensa_opcode_name (isa
, opcode
));
5813 opnum
= get_relaxable_immed (opcode
);
5815 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5816 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5818 as_bad_where (fixP
->fx_file
,
5820 _("invalid relocation for operand %d of '%s'"),
5821 opnum
, xtensa_opcode_name (isa
, opcode
));
5824 return 0 - opnd_value
;
5828 /* TC_FORCE_RELOCATION hook */
5831 xtensa_force_relocation (fixS
*fix
)
5833 switch (fix
->fx_r_type
)
5835 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5836 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5837 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5838 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5839 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5840 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5841 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5842 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5843 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5844 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5845 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5846 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5847 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5848 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5849 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5850 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5856 if (linkrelax
&& fix
->fx_addsy
5857 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5860 return generic_force_reloc (fix
);
5864 /* TC_VALIDATE_FIX_SUB hook */
5867 xtensa_validate_fix_sub (fixS
*fix
)
5869 segT add_symbol_segment
, sub_symbol_segment
;
5871 /* The difference of two symbols should be resolved by the assembler when
5872 linkrelax is not set. If the linker may relax the section containing
5873 the symbols, then an Xtensa DIFF relocation must be generated so that
5874 the linker knows to adjust the difference value. */
5875 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5878 /* Make sure both symbols are in the same segment, and that segment is
5879 "normal" and relaxable. If the segment is not "normal", then the
5880 fix is not valid. If the segment is not "relaxable", then the fix
5881 should have been handled earlier. */
5882 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5883 if (! SEG_NORMAL (add_symbol_segment
) ||
5884 ! relaxable_section (add_symbol_segment
))
5886 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5887 return (sub_symbol_segment
== add_symbol_segment
);
5891 /* NO_PSEUDO_DOT hook */
5893 /* This function has nothing to do with pseudo dots, but this is the
5894 nearest macro to where the check needs to take place. FIXME: This
5898 xtensa_check_inside_bundle (void)
5900 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5901 as_bad (_("directives are not valid inside bundles"));
5903 /* This function must always return FALSE because it is called via a
5904 macro that has nothing to do with bundling. */
5909 /* md_elf_section_change_hook */
5912 xtensa_elf_section_change_hook (void)
5914 /* Set up the assembly state. */
5915 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5916 xtensa_set_frag_assembly_state (frag_now
);
5920 /* tc_fix_adjustable hook */
5923 xtensa_fix_adjustable (fixS
*fixP
)
5925 /* We need the symbol name for the VTABLE entries. */
5926 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5927 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5934 /* tc_symbol_new_hook */
5936 symbolS
*expr_symbols
= NULL
;
5939 xtensa_symbol_new_hook (symbolS
*sym
)
5941 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5943 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5950 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5952 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5955 /* Subtracted symbols are only allowed for a few relocation types, and
5956 unless linkrelax is enabled, they should not make it to this point. */
5957 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5958 || fixP
->fx_r_type
== BFD_RELOC_16
5959 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5962 switch (fixP
->fx_r_type
)
5964 case BFD_RELOC_32_PCREL
:
5970 switch (fixP
->fx_r_type
)
5973 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5974 fixP
->fx_signed
= 0;
5977 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5978 fixP
->fx_signed
= 0;
5981 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5982 fixP
->fx_signed
= 0;
5988 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5989 - S_GET_VALUE (fixP
->fx_subsy
));
5991 /* The difference value gets written out, and the DIFF reloc
5992 identifies the address of the subtracted symbol (i.e., the one
5993 with the lowest address). */
5995 fixP
->fx_offset
-= val
;
5996 fixP
->fx_subsy
= NULL
;
5998 else if (! fixP
->fx_addsy
)
6005 case BFD_RELOC_XTENSA_PLT
:
6006 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
6007 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6010 case BFD_RELOC_XTENSA_TLSDESC_FN
:
6011 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
6012 case BFD_RELOC_XTENSA_TLS_TPOFF
:
6013 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
6014 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
6015 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
6016 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6019 case BFD_RELOC_XTENSA_SLOT0_OP
:
6020 case BFD_RELOC_XTENSA_SLOT1_OP
:
6021 case BFD_RELOC_XTENSA_SLOT2_OP
:
6022 case BFD_RELOC_XTENSA_SLOT3_OP
:
6023 case BFD_RELOC_XTENSA_SLOT4_OP
:
6024 case BFD_RELOC_XTENSA_SLOT5_OP
:
6025 case BFD_RELOC_XTENSA_SLOT6_OP
:
6026 case BFD_RELOC_XTENSA_SLOT7_OP
:
6027 case BFD_RELOC_XTENSA_SLOT8_OP
:
6028 case BFD_RELOC_XTENSA_SLOT9_OP
:
6029 case BFD_RELOC_XTENSA_SLOT10_OP
:
6030 case BFD_RELOC_XTENSA_SLOT11_OP
:
6031 case BFD_RELOC_XTENSA_SLOT12_OP
:
6032 case BFD_RELOC_XTENSA_SLOT13_OP
:
6033 case BFD_RELOC_XTENSA_SLOT14_OP
:
6036 /* Write the tentative value of a PC-relative relocation to a
6037 local symbol into the instruction. The value will be ignored
6038 by the linker, and it makes the object file disassembly
6039 readable when all branch targets are encoded in relocations. */
6041 gas_assert (fixP
->fx_addsy
);
6042 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6043 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6045 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6046 - md_pcrel_from (fixP
));
6047 (void) xg_apply_fix_value (fixP
, val
);
6050 else if (! fixP
->fx_addsy
)
6053 if (xg_apply_fix_value (fixP
, val
))
6058 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6059 case BFD_RELOC_XTENSA_TLS_FUNC
:
6060 case BFD_RELOC_XTENSA_TLS_ARG
:
6061 case BFD_RELOC_XTENSA_TLS_CALL
:
6062 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6063 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6064 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6065 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6066 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6067 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6068 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6069 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6070 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6071 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6072 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6073 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6074 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6075 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6076 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6077 /* These all need to be resolved at link-time. Do nothing now. */
6080 case BFD_RELOC_VTABLE_INHERIT
:
6081 case BFD_RELOC_VTABLE_ENTRY
:
6086 as_bad (_("unhandled local relocation fix %s"),
6087 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6093 md_atof (int type
, char *litP
, int *sizeP
)
6095 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6100 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6102 return total_frag_text_expansion (fragP
);
6106 /* Translate internal representation of relocation info to BFD target
6110 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6114 reloc
= XNEW (arelent
);
6115 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6116 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6117 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6119 /* Make sure none of our internal relocations make it this far.
6120 They'd better have been fully resolved by this point. */
6121 gas_assert ((int) fixp
->fx_r_type
> 0);
6123 reloc
->addend
= fixp
->fx_offset
;
6125 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6126 if (reloc
->howto
== NULL
)
6128 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6129 _("cannot represent `%s' relocation in object file"),
6130 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6131 free (reloc
->sym_ptr_ptr
);
6136 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6137 as_fatal (_("internal error; cannot generate `%s' relocation"),
6138 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6144 /* Checks for resource conflicts between instructions. */
6146 /* The func unit stuff could be implemented as bit-vectors rather
6147 than the iterative approach here. If it ends up being too
6148 slow, we will switch it. */
6151 new_resource_table (void *data
,
6154 unit_num_copies_func uncf
,
6155 opcode_num_units_func onuf
,
6156 opcode_funcUnit_use_unit_func ouuf
,
6157 opcode_funcUnit_use_stage_func ousf
)
6160 resource_table
*rt
= XNEW (resource_table
);
6162 rt
->cycles
= cycles
;
6163 rt
->allocated_cycles
= cycles
;
6165 rt
->unit_num_copies
= uncf
;
6166 rt
->opcode_num_units
= onuf
;
6167 rt
->opcode_unit_use
= ouuf
;
6168 rt
->opcode_unit_stage
= ousf
;
6170 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6171 for (i
= 0; i
< cycles
; i
++)
6172 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6179 clear_resource_table (resource_table
*rt
)
6182 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6183 for (j
= 0; j
< rt
->num_units
; j
++)
6184 rt
->units
[i
][j
] = 0;
6188 /* We never shrink it, just fake it into thinking so. */
6191 resize_resource_table (resource_table
*rt
, int cycles
)
6195 rt
->cycles
= cycles
;
6196 if (cycles
<= rt
->allocated_cycles
)
6199 old_cycles
= rt
->allocated_cycles
;
6200 rt
->allocated_cycles
= cycles
;
6202 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6203 for (i
= 0; i
< old_cycles
; i
++)
6204 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6205 for (i
= old_cycles
; i
< cycles
; i
++)
6206 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6211 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6214 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6216 for (i
= 0; i
< uses
; i
++)
6218 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6219 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6220 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6221 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6222 if (copies_in_use
>= copies
)
6230 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6233 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6235 for (i
= 0; i
< uses
; i
++)
6237 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6238 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6239 /* Note that this allows resources to be oversubscribed. That's
6240 essential to the way the optional scheduler works.
6241 resources_available reports when a resource is over-subscribed,
6242 so it's easy to tell. */
6243 rt
->units
[stage
+ cycle
][unit
]++;
6249 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6252 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6254 for (i
= 0; i
< uses
; i
++)
6256 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6257 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6258 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6259 rt
->units
[stage
+ cycle
][unit
]--;
6264 /* Wrapper functions make parameterized resource reservation
6268 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6270 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6276 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6278 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6283 /* Note that this function does not check issue constraints, but
6284 solely whether the hardware is available to execute the given
6285 instructions together. It also doesn't check if the tinsns
6286 write the same state, or access the same tieports. That is
6287 checked by check_t1_t2_reads_and_writes. */
6290 resources_conflict (vliw_insn
*vinsn
)
6293 static resource_table
*rt
= NULL
;
6295 /* This is the most common case by far. Optimize it. */
6296 if (vinsn
->num_slots
== 1)
6301 xtensa_isa isa
= xtensa_default_isa
;
6302 rt
= new_resource_table
6303 (isa
, xtensa_num_pipe_stages
,
6304 xtensa_isa_num_funcUnits (isa
),
6305 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6306 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6307 opcode_funcUnit_use_unit
,
6308 opcode_funcUnit_use_stage
);
6311 clear_resource_table (rt
);
6313 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6315 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6317 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6324 /* finish_vinsn, emit_single_op and helper functions. */
6326 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6327 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6328 static void xg_assemble_vliw_tokens (vliw_insn
*);
6331 /* We have reached the end of a bundle; emit into the frag. */
6334 finish_vinsn (vliw_insn
*vinsn
)
6340 if (find_vinsn_conflicts (vinsn
))
6342 xg_clear_vinsn (vinsn
);
6346 /* First, find a format that works. */
6347 if (vinsn
->format
== XTENSA_UNDEFINED
)
6348 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6350 slots
= xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
);
6352 && produce_flix
== FLIX_NONE
)
6354 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6355 xg_clear_vinsn (vinsn
);
6359 if (vinsn
->format
== XTENSA_UNDEFINED
)
6361 as_bad (_("couldn't find a valid instruction format"));
6362 fprintf (stderr
, _(" ops were: "));
6363 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6364 fprintf (stderr
, _(" %s;"),
6365 xtensa_opcode_name (xtensa_default_isa
,
6366 vinsn
->slots
[i
].opcode
));
6367 fprintf (stderr
, _("\n"));
6368 xg_clear_vinsn (vinsn
);
6372 if (vinsn
->num_slots
!= slots
)
6374 as_bad (_("mismatch for format '%s': #slots = %d, #opcodes = %d"),
6375 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6376 slots
, vinsn
->num_slots
);
6377 xg_clear_vinsn (vinsn
);
6381 if (resources_conflict (vinsn
))
6383 as_bad (_("illegal resource usage in bundle"));
6384 fprintf (stderr
, " ops were: ");
6385 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6386 fprintf (stderr
, " %s;",
6387 xtensa_opcode_name (xtensa_default_isa
,
6388 vinsn
->slots
[i
].opcode
));
6389 fprintf (stderr
, "\n");
6390 xg_clear_vinsn (vinsn
);
6394 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6396 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6398 symbolS
*lit_sym
= NULL
;
6400 bfd_boolean e
= FALSE
;
6401 bfd_boolean saved_density
= density_supported
;
6403 /* We don't want to narrow ops inside multi-slot bundles. */
6404 if (vinsn
->num_slots
> 1)
6405 density_supported
= FALSE
;
6407 istack_init (&slotstack
);
6408 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6410 vinsn
->slots
[i
].opcode
=
6411 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6413 vinsn
->slots
[i
].ntok
= 0;
6416 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6422 density_supported
= saved_density
;
6426 xg_clear_vinsn (vinsn
);
6430 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6432 TInsn
*insn
= &slotstack
.insn
[j
];
6433 if (insn
->insn_type
== ITYPE_LITERAL
)
6435 gas_assert (lit_sym
== NULL
);
6436 lit_sym
= xg_assemble_literal (insn
);
6440 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6442 xg_resolve_literals (insn
, lit_sym
);
6443 if (j
!= slotstack
.ninsn
- 1)
6444 emit_single_op (insn
);
6448 if (vinsn
->num_slots
> 1)
6450 if (opcode_fits_format_slot
6451 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6454 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6458 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6459 if (vinsn
->format
== XTENSA_UNDEFINED
)
6460 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6462 vinsn
->slots
[i
].opcode
6463 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6466 vinsn
->slots
[i
].ntok
= 0;
6471 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6472 vinsn
->format
= XTENSA_UNDEFINED
;
6477 /* Now check resource conflicts on the modified bundle. */
6478 if (resources_conflict (vinsn
))
6480 as_bad (_("illegal resource usage in bundle"));
6481 fprintf (stderr
, " ops were: ");
6482 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6483 fprintf (stderr
, " %s;",
6484 xtensa_opcode_name (xtensa_default_isa
,
6485 vinsn
->slots
[i
].opcode
));
6486 fprintf (stderr
, "\n");
6487 xg_clear_vinsn (vinsn
);
6491 /* First, find a format that works. */
6492 if (vinsn
->format
== XTENSA_UNDEFINED
)
6493 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6495 xg_assemble_vliw_tokens (vinsn
);
6497 xg_clear_vinsn (vinsn
);
6499 xtensa_check_frag_count ();
6503 /* Given an vliw instruction, what conflicts are there in register
6504 usage and in writes to states and queues?
6506 This function does two things:
6507 1. Reports an error when a vinsn contains illegal combinations
6508 of writes to registers states or queues.
6509 2. Marks individual tinsns as not relaxable if the combination
6510 contains antidependencies.
6512 Job 2 handles things like swap semantics in instructions that need
6513 to be relaxed. For example,
6517 normally would be relaxed to
6522 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6524 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6526 then we can't relax it into
6529 { add a0, a1, a0 ; add a2, a0, a4 ; }
6531 because the value of a0 is trashed before the second add can read it. */
6533 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6536 find_vinsn_conflicts (vliw_insn
*vinsn
)
6540 xtensa_isa isa
= xtensa_default_isa
;
6542 gas_assert (!past_xtensa_end
);
6544 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6546 TInsn
*op1
= &vinsn
->slots
[i
];
6547 if (op1
->is_specific_opcode
)
6548 op1
->keep_wide
= TRUE
;
6550 op1
->keep_wide
= FALSE
;
6553 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6555 TInsn
*op1
= &vinsn
->slots
[i
];
6557 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6560 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6564 TInsn
*op2
= &vinsn
->slots
[j
];
6565 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6566 switch (conflict_type
)
6569 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6570 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6571 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6574 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6575 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6576 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6579 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6580 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6581 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6584 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6585 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6586 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6589 /* Everything is OK. */
6592 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6593 || conflict_type
== 'a');
6600 as_bad (_("multiple branches or jumps in the same bundle"));
6608 /* Check how the state used by t1 and t2 relate.
6611 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6612 case B: no relationship between what is read and written (both could
6613 read the same reg though)
6614 case C: t1 writes a register t2 writes (a register conflict within a
6616 case D: t1 writes a state that t2 also writes
6617 case E: t1 writes a tie queue that t2 also writes
6618 case F: two volatile queue accesses
6622 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6624 xtensa_isa isa
= xtensa_default_isa
;
6625 xtensa_regfile t1_regfile
, t2_regfile
;
6627 int t1_base_reg
, t1_last_reg
;
6628 int t2_base_reg
, t2_last_reg
;
6629 char t1_inout
, t2_inout
;
6631 char conflict
= 'b';
6636 bfd_boolean t1_volatile
= FALSE
;
6637 bfd_boolean t2_volatile
= FALSE
;
6639 /* Check registers. */
6640 for (j
= 0; j
< t2
->ntok
; j
++)
6642 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6645 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6646 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6647 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6649 for (i
= 0; i
< t1
->ntok
; i
++)
6651 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6654 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6656 if (t1_regfile
!= t2_regfile
)
6659 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6660 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6662 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6663 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6665 if (t1_inout
== 'm' || t1_inout
== 'o'
6666 || t2_inout
== 'm' || t2_inout
== 'o')
6673 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6674 t1_last_reg
= (t1_base_reg
6675 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6677 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6679 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6681 if (t1_reg
!= t2_reg
)
6684 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6690 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6696 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6704 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6705 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6706 for (j
= 0; j
< t2_states
; j
++)
6708 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6709 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6710 for (i
= 0; i
< t1_states
; i
++)
6712 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6713 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6714 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6717 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6723 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6729 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6734 /* Check tieports. */
6735 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6736 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6737 for (j
= 0; j
< t2_interfaces
; j
++)
6739 xtensa_interface t2_int
6740 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6741 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6743 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6744 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6747 for (i
= 0; i
< t1_interfaces
; i
++)
6749 xtensa_interface t1_int
6750 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6751 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6753 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6754 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6757 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6760 if (t1_int
!= t2_int
)
6763 if (t2_inout
== 'i' && t1_inout
== 'o')
6769 if (t1_inout
== 'i' && t2_inout
== 'o')
6775 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6784 static xtensa_format
6785 xg_find_narrowest_format (vliw_insn
*vinsn
)
6787 /* Right now we assume that the ops within the vinsn are properly
6788 ordered for the slots that the programmer wanted them in. In
6789 other words, we don't rearrange the ops in hopes of finding a
6790 better format. The scheduler handles that. */
6792 xtensa_isa isa
= xtensa_default_isa
;
6793 xtensa_format format
;
6794 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6796 if (vinsn
->num_slots
== 1)
6797 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6799 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6802 xg_copy_vinsn (&v_copy
, vinsn
);
6803 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6807 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6809 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6811 v_copy
.slots
[slot
].opcode
=
6812 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6813 v_copy
.slots
[slot
].ntok
= 0;
6816 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6819 else if (v_copy
.num_slots
> 1)
6822 /* Try the widened version. */
6823 if (!v_copy
.slots
[slot
].keep_wide
6824 && !v_copy
.slots
[slot
].is_specific_opcode
6825 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6827 && opcode_fits_format_slot (widened
.opcode
,
6830 v_copy
.slots
[slot
] = widened
;
6835 if (fit
== v_copy
.num_slots
)
6837 xg_copy_vinsn (vinsn
, &v_copy
);
6838 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6839 vinsn
->format
= format
;
6845 if (format
== xtensa_isa_num_formats (isa
))
6846 return XTENSA_UNDEFINED
;
6852 /* Return the additional space needed in a frag
6853 for possible relaxations of any ops in a VLIW insn.
6854 Also fill out the relaxations that might be required of
6855 each tinsn in the vinsn. */
6858 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6860 bfd_boolean finish_frag
= FALSE
;
6861 int extra_space
= 0;
6864 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6866 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6867 if (!tinsn_has_symbolic_operands (tinsn
))
6869 /* A narrow instruction could be widened later to help
6870 alignment issues. */
6871 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6872 && !tinsn
->is_specific_opcode
6873 && vinsn
->num_slots
== 1)
6875 /* Difference in bytes between narrow and wide insns... */
6877 tinsn
->subtype
= RELAX_NARROW
;
6882 if (workaround_b_j_loop_end
6883 && tinsn
->opcode
== xtensa_jx_opcode
6884 && use_transform ())
6886 /* Add 2 of these. */
6887 extra_space
+= 3; /* for the nop size */
6888 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6891 /* Need to assemble it with space for the relocation. */
6892 if (xg_is_relaxable_insn (tinsn
, 0)
6893 && !tinsn
->is_specific_opcode
)
6895 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6896 int max_literal_size
=
6897 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6899 tinsn
->literal_space
= max_literal_size
;
6901 tinsn
->subtype
= RELAX_IMMED
;
6902 extra_space
+= max_size
;
6906 /* A fix record will be added for this instruction prior
6907 to relaxation, so make it end the frag. */
6912 *pfinish_frag
= finish_frag
;
6918 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6920 xtensa_isa isa
= xtensa_default_isa
;
6921 int slot
, chosen_slot
;
6923 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6924 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6925 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6927 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6928 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6930 if (slot
== chosen_slot
)
6931 vinsn
->slots
[slot
] = *tinsn
;
6934 vinsn
->slots
[slot
].opcode
=
6935 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6936 vinsn
->slots
[slot
].ntok
= 0;
6937 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6944 emit_single_op (TInsn
*orig_insn
)
6947 IStack istack
; /* put instructions into here */
6948 symbolS
*lit_sym
= NULL
;
6949 symbolS
*label_sym
= NULL
;
6951 istack_init (&istack
);
6953 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6954 Because the scheduling and bundling characteristics of movi and
6955 l32r or const16 are so different, we can do much better if we relax
6956 it prior to scheduling and bundling, rather than after. */
6957 if ((orig_insn
->opcode
== xtensa_movi_opcode
6958 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6959 && !cur_vinsn
.inside_bundle
6960 && (orig_insn
->tok
[1].X_op
== O_symbol
6961 || orig_insn
->tok
[1].X_op
== O_pltrel
6962 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6963 || orig_insn
->tok
[1].X_op
== O_tlsarg
6964 || orig_insn
->tok
[1].X_op
== O_tpoff
6965 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6966 && !orig_insn
->is_specific_opcode
&& use_transform ())
6967 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6969 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6972 for (i
= 0; i
< istack
.ninsn
; i
++)
6974 TInsn
*insn
= &istack
.insn
[i
];
6975 switch (insn
->insn_type
)
6978 gas_assert (lit_sym
== NULL
);
6979 lit_sym
= xg_assemble_literal (insn
);
6983 static int relaxed_sym_idx
= 0;
6984 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
6985 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6987 gas_assert (label_sym
== NULL
);
6988 label_sym
= symbol_find_or_make (label
);
6989 gas_assert (label_sym
);
6997 xg_resolve_literals (insn
, lit_sym
);
6999 xg_resolve_labels (insn
, label_sym
);
7001 bundle_tinsn (insn
, &v
);
7016 total_frag_text_expansion (fragS
*fragP
)
7019 int total_expansion
= 0;
7021 for (slot
= 0; slot
< config_max_slots
; slot
++)
7022 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7024 return total_expansion
;
7028 /* Emit a vliw instruction to the current fragment. */
7031 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7033 bfd_boolean finish_frag
;
7034 bfd_boolean is_jump
= FALSE
;
7035 bfd_boolean is_branch
= FALSE
;
7036 xtensa_isa isa
= xtensa_default_isa
;
7041 struct dwarf2_line_info debug_line
;
7042 bfd_boolean loc_directive_seen
= FALSE
;
7045 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7047 if (generating_literals
)
7049 static int reported
= 0;
7051 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7052 _("cannot assemble into a literal fragment"));
7059 if (frag_now_fix () != 0
7060 && (! frag_now
->tc_frag_data
.is_insn
7061 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7062 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7063 || (directive_state
[directive_longcalls
]
7064 != frag_now
->tc_frag_data
.use_longcalls
)
7065 || (directive_state
[directive_absolute_literals
]
7066 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7068 frag_wane (frag_now
);
7070 xtensa_set_frag_assembly_state (frag_now
);
7073 if (workaround_a0_b_retw
7074 && vinsn
->num_slots
== 1
7075 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7076 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7077 && use_transform ())
7079 has_a0_b_retw
= TRUE
;
7081 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7082 After the first assembly pass we will check all of them and
7083 add a nop if needed. */
7084 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7085 frag_var (rs_machine_dependent
, 4, 4,
7086 RELAX_ADD_NOP_IF_A0_B_RETW
,
7087 frag_now
->fr_symbol
,
7088 frag_now
->fr_offset
,
7090 xtensa_set_frag_assembly_state (frag_now
);
7091 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7092 frag_var (rs_machine_dependent
, 4, 4,
7093 RELAX_ADD_NOP_IF_A0_B_RETW
,
7094 frag_now
->fr_symbol
,
7095 frag_now
->fr_offset
,
7097 xtensa_set_frag_assembly_state (frag_now
);
7100 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7102 tinsn
= &vinsn
->slots
[slot
];
7104 /* See if the instruction implies an aligned section. */
7105 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7106 record_alignment (now_seg
, 2);
7108 /* Determine the best line number for debug info. */
7109 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7110 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7111 || tinsn
->debug_line
.line
< debug_line
.line
7112 || tinsn
->debug_line
.column
< debug_line
.column
))
7113 debug_line
= tinsn
->debug_line
;
7114 if (tinsn
->loc_directive_seen
)
7115 loc_directive_seen
= TRUE
;
7118 /* Special cases for instructions that force an alignment... */
7119 /* None of these opcodes are bundle-able. */
7120 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7124 /* Remember the symbol that marks the end of the loop in the frag
7125 that marks the start of the loop. This way we can easily find
7126 the end of the loop at the beginning, without adding special code
7127 to mark the loop instructions themselves. */
7128 symbolS
*target_sym
= NULL
;
7129 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7130 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7132 xtensa_set_frag_assembly_state (frag_now
);
7133 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7135 max_fill
= get_text_align_max_fill_size
7136 (get_text_align_power (xtensa_fetch_width
),
7137 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7139 if (use_transform ())
7140 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7141 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7143 frag_var (rs_machine_dependent
, 0, 0,
7144 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7145 xtensa_set_frag_assembly_state (frag_now
);
7148 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7149 && !vinsn
->slots
[0].is_specific_opcode
)
7151 xtensa_mark_literal_pool_location ();
7152 xtensa_move_labels (frag_now
, 0);
7153 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7156 if (vinsn
->num_slots
== 1)
7158 if (workaround_a0_b_retw
&& use_transform ())
7159 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7160 is_register_writer (&vinsn
->slots
[0], "a", 0));
7162 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7163 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7166 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7168 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7170 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7172 /* vinsn_to_insnbuf will produce the error. */
7173 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7175 f
= frag_more (insn_size
+ extra_space
);
7176 xtensa_set_frag_assembly_state (frag_now
);
7177 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7180 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7181 if (vinsn
->format
== XTENSA_UNDEFINED
)
7184 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7186 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7187 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7190 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7192 tinsn
= &vinsn
->slots
[slot
];
7193 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7194 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7195 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7196 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7197 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7199 frag_now
->tc_frag_data
.literal_frags
[slot
] =
7200 tinsn
->tok
[1].X_add_symbol
->sy_frag
;
7202 if (tinsn
->literal_space
!= 0)
7203 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7204 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7206 if (tinsn
->subtype
== RELAX_NARROW
)
7207 gas_assert (vinsn
->num_slots
== 1);
7208 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7210 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7213 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7214 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7218 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7219 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7223 frag_variant (rs_machine_dependent
,
7224 extra_space
, extra_space
, RELAX_SLOTS
,
7225 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7226 xtensa_set_frag_assembly_state (frag_now
);
7229 /* Special cases for loops:
7230 close_loop_end should be inserted AFTER short_loop.
7231 Make sure that CLOSE loops are processed BEFORE short_loops
7232 when converting them. */
7234 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7235 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7236 && !vinsn
->slots
[0].is_specific_opcode
)
7238 if (workaround_short_loop
&& use_transform ())
7240 maybe_has_short_loop
= TRUE
;
7241 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7242 frag_var (rs_machine_dependent
, 4, 4,
7243 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7244 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7245 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7246 frag_var (rs_machine_dependent
, 4, 4,
7247 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7248 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7251 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7252 loop at least 12 bytes away from another loop's end. */
7253 if (workaround_close_loop_end
&& use_transform ())
7255 maybe_has_close_loop_end
= TRUE
;
7256 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7257 frag_var (rs_machine_dependent
, 12, 12,
7258 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7259 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7263 if (use_transform ())
7267 gas_assert (finish_frag
);
7268 frag_var (rs_machine_dependent
,
7269 xtensa_fetch_width
, xtensa_fetch_width
,
7271 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7272 xtensa_set_frag_assembly_state (frag_now
);
7273 xtensa_maybe_create_trampoline_frag ();
7274 /* Always create one here. */
7275 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7277 else if (is_branch
&& do_align_targets ())
7279 gas_assert (finish_frag
);
7280 frag_var (rs_machine_dependent
,
7281 xtensa_fetch_width
, xtensa_fetch_width
,
7282 RELAX_MAYBE_UNREACHABLE
,
7283 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7284 xtensa_set_frag_assembly_state (frag_now
);
7285 frag_var (rs_machine_dependent
,
7287 RELAX_MAYBE_DESIRE_ALIGN
,
7288 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7289 xtensa_set_frag_assembly_state (frag_now
);
7293 /* Now, if the original opcode was a call... */
7294 if (do_align_targets ()
7295 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7297 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7298 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7299 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7300 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7301 xtensa_set_frag_assembly_state (frag_now
);
7304 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7306 frag_wane (frag_now
);
7308 xtensa_set_frag_assembly_state (frag_now
);
7313 /* xtensa_end and helper functions. */
7315 static void xtensa_cleanup_align_frags (void);
7316 static void xtensa_fix_target_frags (void);
7317 static void xtensa_mark_narrow_branches (void);
7318 static void xtensa_mark_zcl_first_insns (void);
7319 static void xtensa_mark_difference_of_two_symbols (void);
7320 static void xtensa_fix_a0_b_retw_frags (void);
7321 static void xtensa_fix_b_j_loop_end_frags (void);
7322 static void xtensa_fix_close_loop_end_frags (void);
7323 static void xtensa_fix_short_loop_frags (void);
7324 static void xtensa_sanity_check (void);
7325 static void xtensa_add_config_info (void);
7330 directive_balance ();
7331 xtensa_flush_pending_output ();
7333 past_xtensa_end
= TRUE
;
7335 xtensa_move_literals ();
7337 xtensa_reorder_segments ();
7338 xtensa_cleanup_align_frags ();
7339 xtensa_fix_target_frags ();
7340 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7341 xtensa_fix_a0_b_retw_frags ();
7342 if (workaround_b_j_loop_end
)
7343 xtensa_fix_b_j_loop_end_frags ();
7345 /* "close_loop_end" should be processed BEFORE "short_loop". */
7346 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7347 xtensa_fix_close_loop_end_frags ();
7349 if (workaround_short_loop
&& maybe_has_short_loop
)
7350 xtensa_fix_short_loop_frags ();
7352 xtensa_mark_narrow_branches ();
7353 xtensa_mark_zcl_first_insns ();
7355 xtensa_sanity_check ();
7357 xtensa_add_config_info ();
7359 xtensa_check_frag_count ();
7362 struct trampoline_chain_entry
7368 /* Trampoline chain for a given (sym, offset) pair is a sorted array
7369 of locations of trampoline jumps leading there. Jumps are represented
7370 as pairs (sym, offset): trampoline frag symbol and offset of the jump
7372 struct trampoline_chain
7374 struct trampoline_chain_entry target
;
7375 struct trampoline_chain_entry
*entry
;
7378 bfd_boolean needs_sorting
;
7381 struct trampoline_chain_index
7383 struct trampoline_chain
*entry
;
7386 bfd_boolean needs_sorting
;
7389 struct trampoline_index
7396 struct trampoline_seg
7398 struct trampoline_seg
*next
;
7400 /* Trampolines ordered by their frag fr_address */
7401 struct trampoline_index index
;
7402 /* Known trampoline chains ordered by (sym, offset) pair */
7403 struct trampoline_chain_index chain_index
;
7406 static struct trampoline_seg trampoline_seg_list
;
7407 #define J_RANGE (128 * 1024)
7408 #define J_MARGIN 4096
7410 static int unreachable_count
= 0;
7414 xtensa_maybe_create_trampoline_frag (void)
7416 if (!use_trampolines
)
7419 /* We create an area for possible trampolines every 10 unreachable frags.
7420 These are preferred over the ones not preceded by an unreachable frag,
7421 because we don't have to jump around them. This function is called after
7422 each RELAX_UNREACHABLE frag is created. */
7424 if (++unreachable_count
> 10)
7426 xtensa_create_trampoline_frag (FALSE
);
7427 clear_frag_count ();
7428 unreachable_count
= 0;
7433 xtensa_check_frag_count (void)
7435 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7438 /* We create an area for possible trampolines every 8000 frags or so. This
7439 is an estimate based on the max range of a "j" insn (+/-128K) divided
7440 by a typical frag byte count (16), minus a few for safety. This function
7441 is called after each source line is processed. */
7443 if (get_frag_count () > 8000)
7445 xtensa_create_trampoline_frag (TRUE
);
7446 clear_frag_count ();
7447 unreachable_count
= 0;
7450 /* We create an area for a possible literal pool every N (default 5000)
7452 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7455 static xtensa_insnbuf trampoline_buf
= NULL
;
7456 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7458 static xtensa_insnbuf litpool_buf
= NULL
;
7459 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7461 #define TRAMPOLINE_FRAG_SIZE 3000
7463 static struct trampoline_seg
*
7464 find_trampoline_seg (asection
*seg
)
7466 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7467 static struct trampoline_seg
*mr
;
7469 if (mr
&& mr
->seg
== seg
)
7472 for ( ; ts
; ts
= ts
->next
)
7484 static size_t xg_find_trampoline (const struct trampoline_index
*idx
,
7488 size_t b
= idx
->n_entries
;
7492 size_t c
= (a
+ b
) / 2;
7494 if (idx
->entry
[c
]->fr_address
<= addr
)
7502 static void xg_add_trampoline_to_index (struct trampoline_index
*idx
,
7505 if (idx
->n_entries
== idx
->n_max
)
7507 idx
->n_max
= (idx
->n_entries
+ 1) * 2;
7508 idx
->entry
= xrealloc (idx
->entry
,
7509 sizeof (*idx
->entry
) * idx
->n_max
);
7511 idx
->entry
[idx
->n_entries
] = fragP
;
7515 static void xg_remove_trampoline_from_index (struct trampoline_index
*idx
,
7518 gas_assert (i
< idx
->n_entries
);
7519 memmove (idx
->entry
+ i
, idx
->entry
+ i
+ 1,
7520 (idx
->n_entries
- i
- 1) * sizeof (*idx
->entry
));
7524 static void xg_add_trampoline_to_seg (struct trampoline_seg
*ts
,
7527 xg_add_trampoline_to_index (&ts
->index
, fragP
);
7531 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7533 /* Emit a frag where we can place intermediate jump instructions,
7534 in case we need to jump farther than 128K bytes.
7535 Each jump instruction takes three bytes.
7536 We allocate enough for 1000 trampolines in each frag.
7537 If that's not enough, oh well. */
7539 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
7542 int size
= TRAMPOLINE_FRAG_SIZE
;
7546 ts
= XCNEW(struct trampoline_seg
);
7547 ts
->next
= trampoline_seg_list
.next
;
7548 trampoline_seg_list
.next
= ts
;
7552 frag_wane (frag_now
);
7554 xtensa_set_frag_assembly_state (frag_now
);
7555 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7556 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7557 if (trampoline_buf
== NULL
)
7559 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7560 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7562 fragP
->tc_frag_data
.needs_jump_around
= needs_jump_around
;
7563 xg_add_trampoline_to_seg (ts
, fragP
);
7566 static bfd_boolean
xg_is_trampoline_frag_full (const fragS
*fragP
)
7568 return fragP
->fr_var
< 3;
7571 static int xg_order_trampoline_chain_entry (const void *a
, const void *b
)
7573 const struct trampoline_chain_entry
*pa
= a
;
7574 const struct trampoline_chain_entry
*pb
= b
;
7576 if (pa
->sym
== pb
->sym
||
7577 S_GET_VALUE (pa
->sym
) == S_GET_VALUE (pb
->sym
))
7578 if (pa
->offset
== pb
->offset
)
7581 return pa
->offset
< pb
->offset
? -1 : 1;
7583 return S_GET_VALUE (pa
->sym
) < S_GET_VALUE (pb
->sym
) ? -1 : 1;
7586 static void xg_sort_trampoline_chain (struct trampoline_chain
*tc
)
7588 qsort (tc
->entry
, tc
->n_entries
, sizeof (*tc
->entry
),
7589 xg_order_trampoline_chain_entry
);
7590 tc
->needs_sorting
= FALSE
;
7593 /* Find entry index in the given chain with maximal address <= source. */
7594 static size_t xg_find_chain_entry (struct trampoline_chain
*tc
,
7598 size_t b
= tc
->n_entries
;
7600 if (tc
->needs_sorting
)
7601 xg_sort_trampoline_chain (tc
);
7605 size_t c
= (a
+ b
) / 2;
7606 struct trampoline_chain_entry
*e
= tc
->entry
+ c
;
7608 if (S_GET_VALUE(e
->sym
) + e
->offset
<= source
)
7616 /* Find the best jump target for the source in the given trampoline chain.
7617 The best jump target is the one that results in the shortest path to the
7618 final target, it's the location of the jump closest to the final target,
7619 but within the J_RANGE - J_MARGIN from the source. */
7620 static struct trampoline_chain_entry
*
7621 xg_get_best_chain_entry (struct trampoline_chain
*tc
, addressT source
)
7623 addressT target
= S_GET_VALUE(tc
->target
.sym
) + tc
->target
.offset
;
7624 size_t i
= xg_find_chain_entry (tc
, source
);
7625 struct trampoline_chain_entry
*e
= tc
->entry
+ i
;
7626 int step
= target
< source
? -1 : 1;
7627 addressT chained_target
;
7630 if (target
> source
&&
7631 S_GET_VALUE(e
->sym
) + e
->offset
<= source
&&
7632 i
+ 1 < tc
->n_entries
)
7635 while (i
+ step
< tc
->n_entries
)
7637 struct trampoline_chain_entry
*next
= tc
->entry
+ i
+ step
;
7639 chained_target
= S_GET_VALUE(next
->sym
) + next
->offset
;
7640 off
= source
- chained_target
;
7642 if (labs (off
) >= J_RANGE
- J_MARGIN
)
7649 chained_target
= S_GET_VALUE(e
->sym
) + e
->offset
;
7650 off
= source
- chained_target
;
7652 if (labs (off
) < J_MARGIN
||
7653 labs (off
) >= J_RANGE
- J_MARGIN
)
7655 return tc
->entry
+ i
;
7658 static int xg_order_trampoline_chain (const void *a
, const void *b
)
7660 const struct trampoline_chain
*_pa
= a
;
7661 const struct trampoline_chain
*_pb
= b
;
7662 const struct trampoline_chain_entry
*pa
= &_pa
->target
;
7663 const struct trampoline_chain_entry
*pb
= &_pb
->target
;
7664 symbolS
*s1
= pa
->sym
;
7665 symbolS
*s2
= pb
->sym
;
7667 if (s1
->sy_flags
.sy_local_symbol
7668 && local_symbol_converted_p ((struct local_symbol
*) s1
))
7669 s1
= local_symbol_get_real_symbol ((struct local_symbol
*) s1
);
7671 if (s2
->sy_flags
.sy_local_symbol
7672 && local_symbol_converted_p ((struct local_symbol
*) s2
))
7673 s2
= local_symbol_get_real_symbol ((struct local_symbol
*) s2
);
7676 if (pa
->offset
== pb
->offset
)
7679 return pa
->offset
< pb
->offset
? -1 : 1;
7681 return s1
< s2
? -1 : 1;
7684 static struct trampoline_chain
*
7685 xg_get_trampoline_chain (struct trampoline_seg
*ts
,
7689 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7690 struct trampoline_chain c
;
7692 if (idx
->needs_sorting
)
7694 qsort (idx
->entry
, idx
->n_entries
, sizeof (*idx
->entry
),
7695 xg_order_trampoline_chain
);
7696 idx
->needs_sorting
= FALSE
;
7699 c
.target
.offset
= offset
;
7700 return bsearch (&c
, idx
->entry
, idx
->n_entries
,
7701 sizeof (struct trampoline_chain
),
7702 xg_order_trampoline_chain
);
7705 /* Find trampoline chain in the given trampoline segment that is going
7706 to the *sym + *offset. If found, replace *sym and *offset with the
7707 best jump target in that chain. */
7708 static struct trampoline_chain
*
7709 xg_find_best_eq_target (struct trampoline_seg
*ts
,
7710 addressT source
, symbolS
**sym
,
7713 struct trampoline_chain
*tc
= xg_get_trampoline_chain (ts
, *sym
, *offset
);
7717 struct trampoline_chain_entry
*e
= xg_get_best_chain_entry (tc
, source
);
7720 *offset
= e
->offset
;
7725 static void xg_add_location_to_chain (struct trampoline_chain
*tc
,
7726 symbolS
*sym
, addressT offset
)
7728 struct trampoline_chain_entry
*e
;
7730 if (tc
->n_entries
== tc
->n_max
)
7732 tc
->n_max
= (tc
->n_max
+ 1) * 2;
7733 tc
->entry
= xrealloc (tc
->entry
, sizeof (*tc
->entry
) * tc
->n_max
);
7735 e
= tc
->entry
+ tc
->n_entries
;
7739 tc
->needs_sorting
= TRUE
;
7742 static struct trampoline_chain
*
7743 xg_create_trampoline_chain (struct trampoline_seg
*ts
,
7744 symbolS
*sym
, addressT offset
)
7746 struct trampoline_chain_index
*idx
= &ts
->chain_index
;
7747 struct trampoline_chain
*tc
;
7749 if (idx
->n_entries
== idx
->n_max
)
7751 idx
->n_max
= (idx
->n_max
+ 1) * 2;
7752 idx
->entry
= xrealloc (idx
->entry
,
7753 sizeof (*idx
->entry
) * idx
->n_max
);
7756 tc
= idx
->entry
+ idx
->n_entries
;
7757 tc
->target
.sym
= sym
;
7758 tc
->target
.offset
= offset
;
7762 xg_add_location_to_chain (tc
, sym
, offset
);
7765 idx
->needs_sorting
= TRUE
;
7770 void dump_trampolines (void);
7773 dump_trampolines (void)
7775 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7777 for ( ; ts
; ts
= ts
->next
)
7780 asection
*seg
= ts
->seg
;
7784 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7786 for (i
= 0; i
< ts
->index
.n_entries
; ++i
)
7788 fragS
*tf
= ts
->index
.entry
[i
];
7790 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7791 (int)tf
->fr_address
, (int)tf
->fr_fix
,
7792 tf
->tc_frag_data
.needs_jump_around
? "T" : "F");
7797 static void dump_litpools (void) __attribute__ ((unused
));
7800 dump_litpools (void)
7802 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7803 struct litpool_frag
*lpf
;
7805 for ( ; lps
; lps
= lps
->next
)
7807 printf("litpool seg %s\n", lps
->seg
->name
);
7808 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7810 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7812 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7814 if (litfrag
->fr_fix
== 4)
7816 litfrag
= litfrag
->fr_next
;
7818 printf(" %ld <%d:%d> (%d) [%d]: ",
7819 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7820 lpf
->fragP
->fr_line
, count
);
7821 //dump_frag(lpf->fragP);
7827 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7828 bfd_boolean only_if_needed
)
7830 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7832 struct litpool_frag
*lpf
;
7833 bfd_boolean needed
= FALSE
;
7835 if (use_literal_section
|| !auto_litpools
)
7838 for ( ; lps
; lps
= lps
->next
)
7840 if (lps
->seg
== now_seg
)
7846 lps
= XCNEW (struct litpool_seg
);
7847 lps
->next
= litpool_seg_list
.next
;
7848 litpool_seg_list
.next
= lps
;
7850 lps
->frag_list
.next
= &lps
->frag_list
;
7851 lps
->frag_list
.prev
= &lps
->frag_list
;
7852 /* Put candidate literal pool at the beginning of every section,
7853 so that even when section starts with literal load there's a
7854 literal pool available. */
7855 lps
->frag_count
= auto_litpool_limit
;
7864 if (past_xtensa_end
|| !use_transform() ||
7865 frag_now
->tc_frag_data
.is_no_transform
)
7869 if (auto_litpool_limit
<= 0)
7871 /* Don't create a litpool based only on frag count. */
7874 else if (lps
->frag_count
> auto_litpool_limit
)
7891 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7892 /* Create a potential site for a literal pool. */
7893 frag_wane (frag_now
);
7895 xtensa_set_frag_assembly_state (frag_now
);
7897 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7898 fragP
->tc_frag_data
.literal_frag
= fragP
;
7899 frag_var (rs_machine_dependent
, size
, size
,
7901 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7902 RELAX_LITERAL_POOL_BEGIN
,
7904 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7905 frag_variant (rs_machine_dependent
, 0, 0,
7906 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7907 xtensa_set_frag_assembly_state (frag_now
);
7911 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7912 just record it here. */
7916 lpf
= XNEW (struct litpool_frag
);
7917 /* Insert at tail of circular list. */
7919 lps
->frag_list
.prev
->next
= lpf
;
7920 lpf
->next
= &lps
->frag_list
;
7921 lpf
->prev
= lps
->frag_list
.prev
;
7922 lps
->frag_list
.prev
= lpf
;
7924 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7925 lpf
->original_priority
= lpf
->priority
;
7926 lpf
->literal_count
= 0;
7928 lps
->frag_count
= 0;
7932 xtensa_cleanup_align_frags (void)
7937 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7938 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7941 /* Walk over all of the fragments in a subsection. */
7942 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7944 if ((fragP
->fr_type
== rs_align
7945 || fragP
->fr_type
== rs_align_code
7946 || (fragP
->fr_type
== rs_machine_dependent
7947 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7948 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7949 && fragP
->fr_fix
== 0)
7951 fragS
*next
= fragP
->fr_next
;
7954 && next
->fr_fix
== 0
7955 && next
->fr_type
== rs_machine_dependent
7956 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7959 next
= next
->fr_next
;
7962 /* If we don't widen branch targets, then they
7963 will be easier to align. */
7964 if (fragP
->tc_frag_data
.is_branch_target
7965 && fragP
->fr_opcode
== fragP
->fr_literal
7966 && fragP
->fr_type
== rs_machine_dependent
7967 && fragP
->fr_subtype
== RELAX_SLOTS
7968 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7970 if (fragP
->fr_type
== rs_machine_dependent
7971 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7972 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7978 /* Re-process all of the fragments looking to convert all of the
7979 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7980 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7981 Otherwise, convert to a .fill 0. */
7984 xtensa_fix_target_frags (void)
7989 /* When this routine is called, all of the subsections are still intact
7990 so we walk over subsections instead of sections. */
7991 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7992 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7996 /* Walk over all of the fragments in a subsection. */
7997 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7999 if (fragP
->fr_type
== rs_machine_dependent
8000 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
8002 if (next_frag_is_branch_target (fragP
))
8003 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
8012 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
8015 xtensa_mark_narrow_branches (void)
8020 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8021 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8024 /* Walk over all of the fragments in a subsection. */
8025 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8027 if (fragP
->fr_type
== rs_machine_dependent
8028 && fragP
->fr_subtype
== RELAX_SLOTS
8029 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8033 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
8034 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
8036 if (vinsn
.num_slots
== 1
8037 && xtensa_opcode_is_branch (xtensa_default_isa
,
8038 vinsn
.slots
[0].opcode
) == 1
8039 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
8040 && is_narrow_branch_guaranteed_in_range (fragP
,
8043 fragP
->fr_subtype
= RELAX_SLOTS
;
8044 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
8045 fragP
->tc_frag_data
.is_aligning_branch
= 1;
8053 /* A branch is typically widened only when its target is out of
8054 range. However, we would like to widen them to align a subsequent
8055 branch target when possible.
8057 Because the branch relaxation code is so convoluted, the optimal solution
8058 (combining the two cases) is difficult to get right in all circumstances.
8059 We therefore go with an "almost as good" solution, where we only
8060 use for alignment narrow branches that definitely will not expand to a
8061 jump and a branch. These functions find and mark these cases. */
8063 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
8064 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
8065 We start counting beginning with the frag after the 2-byte branch, so the
8066 maximum offset is (4 - 2) + 63 = 65. */
8067 #define MAX_IMMED6 65
8069 static offsetT
unrelaxed_frag_max_size (fragS
*);
8072 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
8074 const expressionS
*exp
= &tinsn
->tok
[1];
8075 symbolS
*symbolP
= exp
->X_add_symbol
;
8076 offsetT max_distance
= exp
->X_add_number
;
8079 if (exp
->X_op
!= O_symbol
)
8082 target_frag
= symbol_get_frag (symbolP
);
8084 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
8085 if (is_branch_jmp_to_next (tinsn
, fragP
))
8088 /* The branch doesn't branch over it's own frag,
8089 but over the subsequent ones. */
8090 fragP
= fragP
->fr_next
;
8091 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
8093 max_distance
+= unrelaxed_frag_max_size (fragP
);
8094 fragP
= fragP
->fr_next
;
8096 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
8103 xtensa_mark_zcl_first_insns (void)
8108 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8109 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8112 /* Walk over all of the fragments in a subsection. */
8113 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8115 if (fragP
->fr_type
== rs_machine_dependent
8116 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8117 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8119 /* Find the loop frag. */
8120 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8121 /* Find the first insn frag. */
8122 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
8124 /* Handle a corner case that comes up in hardware
8125 diagnostics. The original assembly looks like this:
8128 <empty_frag>--not found by next_non_empty_frag
8131 Depending on the start address, the assembler may or
8132 may not change it to look something like this:
8135 nop--frag isn't empty anymore
8138 So set up to check the alignment of the nop if it
8140 while (loop_frag
!= targ_frag
)
8142 if (loop_frag
->fr_type
== rs_machine_dependent
8143 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
8144 || loop_frag
->fr_subtype
8145 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
8146 targ_frag
= loop_frag
;
8148 loop_frag
= loop_frag
->fr_next
;
8151 /* Of course, sometimes (mostly for toy test cases) a
8152 zero-cost loop instruction is the last in a section. */
8155 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
8156 /* Do not widen a frag that is the first instruction of a
8157 zero-cost loop. It makes that loop harder to align. */
8158 if (targ_frag
->fr_type
== rs_machine_dependent
8159 && targ_frag
->fr_subtype
== RELAX_SLOTS
8160 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
8163 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
8164 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8167 frag_wane (targ_frag
);
8168 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
8172 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
8180 /* When a difference-of-symbols expression is encoded as a uleb128 or
8181 sleb128 value, the linker is unable to adjust that value to account for
8182 link-time relaxation. Mark all the code between such symbols so that
8183 its size cannot be changed by linker relaxation. */
8186 xtensa_mark_difference_of_two_symbols (void)
8190 for (expr_sym
= expr_symbols
; expr_sym
;
8191 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
8193 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
8195 if (exp
->X_op
== O_subtract
)
8197 symbolS
*left
= exp
->X_add_symbol
;
8198 symbolS
*right
= exp
->X_op_symbol
;
8200 /* Difference of two symbols not in the same section
8201 are handled with relocations in the linker. */
8202 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
8208 if (symbol_get_frag (left
)->fr_address
8209 <= symbol_get_frag (right
)->fr_address
)
8211 start
= symbol_get_frag (left
);
8212 end
= symbol_get_frag (right
);
8216 start
= symbol_get_frag (right
);
8217 end
= symbol_get_frag (left
);
8220 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
8221 walk
= start
->tc_frag_data
.no_transform_end
;
8226 walk
->tc_frag_data
.is_no_transform
= 1;
8227 walk
= walk
->fr_next
;
8229 while (walk
&& walk
->fr_address
< end
->fr_address
);
8231 start
->tc_frag_data
.no_transform_end
= walk
;
8238 /* Re-process all of the fragments looking to convert all of the
8239 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
8240 conditional branch or a retw/retw.n, convert this frag to one that
8241 will generate a NOP. In any case close it off with a .fill 0. */
8243 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
8246 xtensa_fix_a0_b_retw_frags (void)
8251 /* When this routine is called, all of the subsections are still intact
8252 so we walk over subsections instead of sections. */
8253 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8254 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8258 /* Walk over all of the fragments in a subsection. */
8259 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8261 if (fragP
->fr_type
== rs_machine_dependent
8262 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
8264 if (next_instrs_are_b_retw (fragP
))
8266 if (fragP
->tc_frag_data
.is_no_transform
)
8267 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
8269 relax_frag_add_nop (fragP
);
8279 next_instrs_are_b_retw (fragS
*fragP
)
8281 xtensa_opcode opcode
;
8283 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
8284 static xtensa_insnbuf insnbuf
= NULL
;
8285 static xtensa_insnbuf slotbuf
= NULL
;
8286 xtensa_isa isa
= xtensa_default_isa
;
8289 bfd_boolean branch_seen
= FALSE
;
8293 insnbuf
= xtensa_insnbuf_alloc (isa
);
8294 slotbuf
= xtensa_insnbuf_alloc (isa
);
8297 if (next_fragP
== NULL
)
8300 /* Check for the conditional branch. */
8301 xtensa_insnbuf_from_chars
8302 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8303 fmt
= xtensa_format_decode (isa
, insnbuf
);
8304 if (fmt
== XTENSA_UNDEFINED
)
8307 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8309 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8310 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8312 branch_seen
= (branch_seen
8313 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8319 offset
+= xtensa_format_length (isa
, fmt
);
8320 if (offset
== next_fragP
->fr_fix
)
8322 next_fragP
= next_non_empty_frag (next_fragP
);
8326 if (next_fragP
== NULL
)
8329 /* Check for the retw/retw.n. */
8330 xtensa_insnbuf_from_chars
8331 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8332 fmt
= xtensa_format_decode (isa
, insnbuf
);
8334 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8335 have no problems. */
8336 if (fmt
== XTENSA_UNDEFINED
8337 || xtensa_format_num_slots (isa
, fmt
) != 1)
8340 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8341 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8343 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8350 /* Re-process all of the fragments looking to convert all of the
8351 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8352 loop end label, convert this frag to one that will generate a NOP.
8353 In any case close it off with a .fill 0. */
8355 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8358 xtensa_fix_b_j_loop_end_frags (void)
8363 /* When this routine is called, all of the subsections are still intact
8364 so we walk over subsections instead of sections. */
8365 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8366 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8370 /* Walk over all of the fragments in a subsection. */
8371 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8373 if (fragP
->fr_type
== rs_machine_dependent
8374 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8376 if (next_instr_is_loop_end (fragP
))
8378 if (fragP
->tc_frag_data
.is_no_transform
)
8379 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8381 relax_frag_add_nop (fragP
);
8391 next_instr_is_loop_end (fragS
*fragP
)
8393 const fragS
*next_fragP
;
8395 if (next_frag_is_loop_target (fragP
))
8398 next_fragP
= next_non_empty_frag (fragP
);
8399 if (next_fragP
== NULL
)
8402 if (!next_frag_is_loop_target (next_fragP
))
8405 /* If the size is >= 3 then there is more than one instruction here.
8406 The hardware bug will not fire. */
8407 if (next_fragP
->fr_fix
> 3)
8414 /* Re-process all of the fragments looking to convert all of the
8415 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8416 not MY loop's loop end within 12 bytes, add enough nops here to
8417 make it at least 12 bytes away. In any case close it off with a
8420 static offsetT min_bytes_to_other_loop_end
8421 (fragS
*, fragS
*, offsetT
);
8424 xtensa_fix_close_loop_end_frags (void)
8429 /* When this routine is called, all of the subsections are still intact
8430 so we walk over subsections instead of sections. */
8431 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8432 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8436 fragS
*current_target
= NULL
;
8438 /* Walk over all of the fragments in a subsection. */
8439 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8441 if (fragP
->fr_type
== rs_machine_dependent
8442 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8443 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8444 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8447 && fragP
->fr_type
== rs_machine_dependent
8448 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8451 int bytes_added
= 0;
8453 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8454 /* Max out at 12. */
8455 min_bytes
= min_bytes_to_other_loop_end
8456 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8458 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8460 if (fragP
->tc_frag_data
.is_no_transform
)
8461 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8464 while (min_bytes
+ bytes_added
8465 < REQUIRED_LOOP_DIVIDING_BYTES
)
8469 if (fragP
->fr_var
< length
)
8470 as_fatal (_("fr_var %lu < length %d"),
8471 (long) fragP
->fr_var
, length
);
8474 assemble_nop (length
,
8475 fragP
->fr_literal
+ fragP
->fr_fix
);
8476 fragP
->fr_fix
+= length
;
8477 fragP
->fr_var
-= length
;
8479 bytes_added
+= length
;
8485 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8486 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8492 static offsetT
unrelaxed_frag_min_size (fragS
*);
8495 min_bytes_to_other_loop_end (fragS
*fragP
,
8496 fragS
*current_target
,
8500 fragS
*current_fragP
;
8502 for (current_fragP
= fragP
;
8504 current_fragP
= current_fragP
->fr_next
)
8506 if (current_fragP
->tc_frag_data
.is_loop_target
8507 && current_fragP
!= current_target
)
8510 offset
+= unrelaxed_frag_min_size (current_fragP
);
8512 if (offset
>= max_size
)
8520 unrelaxed_frag_min_size (fragS
*fragP
)
8522 offsetT size
= fragP
->fr_fix
;
8524 /* Add fill size. */
8525 if (fragP
->fr_type
== rs_fill
)
8526 size
+= fragP
->fr_offset
;
8533 unrelaxed_frag_max_size (fragS
*fragP
)
8535 offsetT size
= fragP
->fr_fix
;
8536 switch (fragP
->fr_type
)
8539 /* Empty frags created by the obstack allocation scheme
8540 end up with type 0. */
8545 size
+= fragP
->fr_offset
;
8553 /* No further adjustments needed. */
8555 case rs_machine_dependent
:
8556 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8557 size
+= fragP
->fr_var
;
8560 /* We had darn well better know how big it is. */
8569 /* Re-process all of the fragments looking to convert all
8570 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8573 1) the instruction size count to the loop end label
8574 is too short (<= 2 instructions),
8575 2) loop has a jump or branch in it
8578 1) workaround_all_short_loops is TRUE
8579 2) The generating loop was a 'loopgtz' or 'loopnez'
8580 3) the instruction size count to the loop end label is too short
8582 then convert this frag (and maybe the next one) to generate a NOP.
8583 In any case close it off with a .fill 0. */
8585 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8586 static bfd_boolean
branch_before_loop_end (fragS
*);
8589 xtensa_fix_short_loop_frags (void)
8594 /* When this routine is called, all of the subsections are still intact
8595 so we walk over subsections instead of sections. */
8596 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8597 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8600 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8602 /* Walk over all of the fragments in a subsection. */
8603 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8605 if (fragP
->fr_type
== rs_machine_dependent
8606 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8607 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8610 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8611 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8612 current_opcode
= t_insn
.opcode
;
8613 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8614 current_opcode
) == 1);
8617 if (fragP
->fr_type
== rs_machine_dependent
8618 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8620 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8621 && (branch_before_loop_end (fragP
->fr_next
)
8622 || (workaround_all_short_loops
8623 && current_opcode
!= XTENSA_UNDEFINED
8624 && current_opcode
!= xtensa_loop_opcode
)))
8626 if (fragP
->tc_frag_data
.is_no_transform
)
8627 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8629 relax_frag_add_nop (fragP
);
8638 static int unrelaxed_frag_min_insn_count (fragS
*);
8641 count_insns_to_loop_end (fragS
*base_fragP
,
8642 bfd_boolean count_relax_add
,
8645 fragS
*fragP
= NULL
;
8650 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8652 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8653 if (insn_count
>= max_count
)
8656 if (count_relax_add
)
8658 if (fragP
->fr_type
== rs_machine_dependent
8659 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8661 /* In order to add the appropriate number of
8662 NOPs, we count an instruction for downstream
8665 if (insn_count
>= max_count
)
8675 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8677 xtensa_isa isa
= xtensa_default_isa
;
8678 static xtensa_insnbuf insnbuf
= NULL
;
8682 if (!fragP
->tc_frag_data
.is_insn
)
8686 insnbuf
= xtensa_insnbuf_alloc (isa
);
8688 /* Decode the fixed instructions. */
8689 while (offset
< fragP
->fr_fix
)
8693 xtensa_insnbuf_from_chars
8694 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8695 fmt
= xtensa_format_decode (isa
, insnbuf
);
8697 if (fmt
== XTENSA_UNDEFINED
)
8699 as_fatal (_("undecodable instruction in instruction frag"));
8702 offset
+= xtensa_format_length (isa
, fmt
);
8710 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8713 branch_before_loop_end (fragS
*base_fragP
)
8717 for (fragP
= base_fragP
;
8718 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8719 fragP
= fragP
->fr_next
)
8721 if (unrelaxed_frag_has_b_j (fragP
))
8729 unrelaxed_frag_has_b_j (fragS
*fragP
)
8731 static xtensa_insnbuf insnbuf
= NULL
;
8732 xtensa_isa isa
= xtensa_default_isa
;
8735 if (!fragP
->tc_frag_data
.is_insn
)
8739 insnbuf
= xtensa_insnbuf_alloc (isa
);
8741 /* Decode the fixed instructions. */
8742 while (offset
< fragP
->fr_fix
)
8747 xtensa_insnbuf_from_chars
8748 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8749 fmt
= xtensa_format_decode (isa
, insnbuf
);
8750 if (fmt
== XTENSA_UNDEFINED
)
8753 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8755 xtensa_opcode opcode
=
8756 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8757 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8758 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8761 offset
+= xtensa_format_length (isa
, fmt
);
8767 /* Checks to be made after initial assembly but before relaxation. */
8769 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8770 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8773 xtensa_sanity_check (void)
8775 const char *file_name
;
8780 file_name
= as_where (&line
);
8781 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8782 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8786 /* Walk over all of the fragments in a subsection. */
8787 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8789 if (fragP
->fr_type
== rs_machine_dependent
8790 && fragP
->fr_subtype
== RELAX_SLOTS
8791 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8793 static xtensa_insnbuf insnbuf
= NULL
;
8796 if (fragP
->fr_opcode
!= NULL
)
8799 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8800 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8801 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8803 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8804 t_insn
.opcode
) == 1)
8806 if (is_empty_loop (&t_insn
, fragP
))
8808 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8809 as_bad (_("invalid empty loop"));
8811 if (!is_local_forward_loop (&t_insn
, fragP
))
8813 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8814 as_bad (_("loop target does not follow "
8815 "loop instruction in section"));
8822 new_logical_line (file_name
, line
);
8826 #define LOOP_IMMED_OPN 1
8828 /* Return TRUE if the loop target is the next non-zero fragment. */
8831 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8833 const expressionS
*exp
;
8837 if (insn
->insn_type
!= ITYPE_INSN
)
8840 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8843 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8846 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8848 if (exp
->X_op
!= O_symbol
)
8851 symbolP
= exp
->X_add_symbol
;
8855 if (symbol_get_frag (symbolP
) == NULL
)
8858 if (S_GET_VALUE (symbolP
) != 0)
8861 /* Walk through the zero-size fragments from this one. If we find
8862 the target fragment, then this is a zero-size loop. */
8864 for (next_fragP
= fragP
->fr_next
;
8866 next_fragP
= next_fragP
->fr_next
)
8868 if (next_fragP
== symbol_get_frag (symbolP
))
8870 if (next_fragP
->fr_fix
!= 0)
8878 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8880 const expressionS
*exp
;
8884 if (insn
->insn_type
!= ITYPE_INSN
)
8887 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8890 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8893 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8895 if (exp
->X_op
!= O_symbol
)
8898 symbolP
= exp
->X_add_symbol
;
8902 if (symbol_get_frag (symbolP
) == NULL
)
8905 /* Walk through fragments until we find the target.
8906 If we do not find the target, then this is an invalid loop. */
8908 for (next_fragP
= fragP
->fr_next
;
8910 next_fragP
= next_fragP
->fr_next
)
8912 if (next_fragP
== symbol_get_frag (symbolP
))
8920 #define XTINFO_NAME "Xtensa_Info"
8921 #define XTINFO_NAMESZ 12
8922 #define XTINFO_TYPE 1
8925 xtensa_add_config_info (void)
8931 info_sec
= subseg_new (".xtensa.info", 0);
8932 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8934 data
= XNEWVEC (char, 100);
8935 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8936 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8937 sz
= strlen (data
) + 1;
8939 /* Add enough null terminators to pad to a word boundary. */
8942 while ((sz
& 3) != 0);
8944 /* Follow the standard note section layout:
8945 First write the length of the name string. */
8947 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8949 /* Next comes the length of the "descriptor", i.e., the actual data. */
8951 md_number_to_chars (p
, (valueT
) sz
, 4);
8953 /* Write the note type. */
8955 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8957 /* Write the name field. */
8958 p
= frag_more (XTINFO_NAMESZ
);
8959 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8961 /* Finally, write the descriptor. */
8963 memcpy (p
, data
, sz
);
8969 /* Alignment Functions. */
8972 get_text_align_power (unsigned target_size
)
8974 if (target_size
<= 4)
8977 if (target_size
<= 8)
8980 if (target_size
<= 16)
8983 if (target_size
<= 32)
8986 if (target_size
<= 64)
8989 if (target_size
<= 128)
8992 if (target_size
<= 256)
8995 if (target_size
<= 512)
8998 if (target_size
<= 1024)
9007 get_text_align_max_fill_size (int align_pow
,
9008 bfd_boolean use_nops
,
9009 bfd_boolean use_no_density
)
9012 return (1 << align_pow
);
9014 return 3 * (1 << align_pow
);
9016 return 1 + (1 << align_pow
);
9020 /* Calculate the minimum bytes of fill needed at "address" to align a
9021 target instruction of size "target_size" so that it does not cross a
9022 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
9023 the fill can be an arbitrary number of bytes. Otherwise, the space must
9024 be filled by NOP instructions. */
9027 get_text_align_fill_size (addressT address
,
9030 bfd_boolean use_nops
,
9031 bfd_boolean use_no_density
)
9033 addressT alignment
, fill
, fill_limit
, fill_step
;
9034 bfd_boolean skip_one
= FALSE
;
9036 alignment
= (1 << align_pow
);
9037 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
9041 fill_limit
= alignment
;
9044 else if (!use_no_density
)
9046 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
9047 fill_limit
= alignment
* 2;
9053 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
9054 fill_limit
= alignment
* 3;
9058 /* Try all fill sizes until finding one that works. */
9059 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
9061 if (skip_one
&& fill
== 1)
9063 if ((address
+ fill
) >> align_pow
9064 == (address
+ fill
+ target_size
- 1) >> align_pow
)
9073 branch_align_power (segT sec
)
9075 /* If the Xtensa processor has a fetch width of X, and
9076 the section is aligned to at least that boundary, then a branch
9077 target need only fit within that aligned block of memory to avoid
9078 a stall. Otherwise, try to fit branch targets within 4-byte
9079 aligned blocks (which may be insufficient, e.g., if the section
9080 has no alignment, but it's good enough). */
9081 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
9082 int sec_align
= get_recorded_alignment (sec
);
9084 if (sec_align
>= fetch_align
)
9091 /* This will assert if it is not possible. */
9094 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
9100 gas_assert (fill_size
% 3 == 0);
9101 return (fill_size
/ 3);
9104 gas_assert (fill_size
!= 1); /* Bad argument. */
9106 while (fill_size
> 1)
9109 if (fill_size
== 2 || fill_size
== 4)
9111 fill_size
-= insn_size
;
9114 gas_assert (fill_size
!= 1); /* Bad algorithm. */
9120 get_text_align_nth_nop_size (offsetT fill_size
,
9122 bfd_boolean use_no_density
)
9129 gas_assert (fill_size
!= 1); /* Bad argument. */
9131 while (fill_size
> 1)
9134 if (fill_size
== 2 || fill_size
== 4)
9136 fill_size
-= insn_size
;
9146 /* For the given fragment, find the appropriate address
9147 for it to begin at if we are using NOPs to align it. */
9150 get_noop_aligned_address (fragS
*fragP
, addressT address
)
9152 /* The rule is: get next fragment's FIRST instruction. Find
9153 the smallest number of bytes that need to be added to
9154 ensure that the next fragment's FIRST instruction will fit
9157 E.G., 2 bytes : 0, 1, 2 mod 4
9160 If the FIRST instruction MIGHT be relaxed,
9161 assume that it will become a 3-byte instruction.
9163 Note again here that LOOP instructions are not bundleable,
9164 and this relaxation only applies to LOOP opcodes. */
9167 int first_insn_size
;
9169 addressT pre_opcode_bytes
;
9172 xtensa_opcode opcode
;
9173 bfd_boolean is_loop
;
9175 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9176 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
9178 /* Find the loop frag. */
9179 first_insn
= next_non_empty_frag (fragP
);
9180 /* Now find the first insn frag. */
9181 first_insn
= next_non_empty_frag (first_insn
);
9183 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
9184 gas_assert (is_loop
);
9185 loop_insn_size
= xg_get_single_size (opcode
);
9187 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
9188 pre_opcode_bytes
+= loop_insn_size
;
9190 /* For loops, the alignment depends on the size of the
9191 instruction following the loop, not the LOOP instruction. */
9193 if (first_insn
== NULL
)
9194 first_insn_size
= xtensa_fetch_width
;
9196 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
9198 /* If it was 8, then we'll need a larger alignment for the section. */
9199 align_power
= get_text_align_power (first_insn_size
);
9200 record_alignment (now_seg
, align_power
);
9202 fill_size
= get_text_align_fill_size
9203 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
9204 fragP
->tc_frag_data
.is_no_density
);
9206 return address
+ fill_size
;
9210 /* 3 mechanisms for relaxing an alignment:
9212 Align to a power of 2.
9213 Align so the next fragment's instruction does not cross a word boundary.
9214 Align the current instruction so that if the next instruction
9215 were 3 bytes, it would not cross a word boundary.
9219 zeros - This is easy; always insert zeros.
9220 nops - 3-byte and 2-byte instructions
9224 >=5 : 3-byte instruction + fn (n-3)
9225 widening - widen previous instructions. */
9228 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
9230 addressT target_address
, loop_insn_offset
;
9232 xtensa_opcode loop_opcode
;
9233 bfd_boolean is_loop
;
9236 offsetT branch_align
;
9239 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
9240 switch (fragP
->fr_subtype
)
9242 case RELAX_DESIRE_ALIGN
:
9243 target_size
= next_frag_format_size (fragP
);
9244 if (target_size
== XTENSA_UNDEFINED
)
9246 align_power
= branch_align_power (now_seg
);
9247 branch_align
= 1 << align_power
;
9248 /* Don't count on the section alignment being as large as the target. */
9249 if (target_size
> branch_align
)
9250 target_size
= branch_align
;
9251 opt_diff
= get_text_align_fill_size (address
, align_power
,
9252 target_size
, FALSE
, FALSE
);
9254 *max_diff
= (opt_diff
+ branch_align
9255 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
9256 gas_assert (*max_diff
>= opt_diff
);
9259 case RELAX_ALIGN_NEXT_OPCODE
:
9260 /* The next non-empty frag after this one holds the LOOP instruction
9261 that needs to be aligned. The required alignment depends on the
9262 size of the next non-empty frag after the loop frag, i.e., the
9263 first instruction in the loop. */
9264 loop_frag
= next_non_empty_frag (fragP
);
9265 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
9266 loop_insn_offset
= 0;
9267 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
9268 gas_assert (is_loop
);
9270 /* If the loop has been expanded then the LOOP instruction
9271 could be at an offset from this fragment. */
9272 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
9273 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
9275 /* In an ideal world, which is what we are shooting for here,
9276 we wouldn't need to use any NOPs immediately prior to the
9277 LOOP instruction. If this approach fails, relax_frag_loop_align
9278 will call get_noop_aligned_address. */
9280 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
9281 align_power
= get_text_align_power (target_size
);
9282 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
9283 target_size
, FALSE
, FALSE
);
9285 *max_diff
= xtensa_fetch_width
9286 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
9287 - target_size
+ opt_diff
;
9288 gas_assert (*max_diff
>= opt_diff
);
9299 /* md_relax_frag Hook and Helper Functions. */
9301 static long relax_frag_loop_align (fragS
*, long);
9302 static long relax_frag_for_align (fragS
*, long);
9303 static long relax_frag_immed
9304 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9306 /* Get projected address for the first fulcrum on a path from source to
9308 static addressT
xg_get_fulcrum (addressT source
, addressT target
)
9310 offsetT delta
= target
- source
;
9313 n
= (labs (delta
) + J_RANGE
- J_MARGIN
- 1) / (J_RANGE
- J_MARGIN
);
9314 return source
+ delta
/ n
;
9317 /* Given trampoline index, source and target of a jump find the best
9318 candidate trampoline for the first fulcrum. The best trampoline is
9319 the one in the reach of "j' instruction from the source, closest to
9320 the projected fulcrum address, and preferrably w/o a jump around or
9321 with already initialized jump around. */
9322 static size_t xg_find_best_trampoline (struct trampoline_index
*idx
,
9323 addressT source
, addressT target
)
9325 addressT fulcrum
= xg_get_fulcrum (source
, target
);
9328 size_t base_tr
= xg_find_trampoline (idx
, fulcrum
);
9331 /* Check trampoline frags around the base_tr to find the best. */
9332 for (dist
= 0; checked
; ++dist
)
9335 size_t tr
= base_tr
- dist
;
9339 /* Trampolines are checked in the following order:
9340 base_tr, base_tr + 1, base_tr - 1, base_tr + 2, base_tr - 2 */
9341 for (i
= 0; i
< 2; ++i
, tr
= base_tr
+ dist
+ 1)
9342 if (tr
< idx
->n_entries
)
9344 fragS
*trampoline_frag
= idx
->entry
[tr
];
9347 /* Don't check trampolines outside source - target interval. */
9348 if ((trampoline_frag
->fr_address
< source
&&
9349 trampoline_frag
->fr_address
< target
) ||
9350 (trampoline_frag
->fr_address
> source
&&
9351 trampoline_frag
->fr_address
> target
))
9354 /* Don't choose trampoline that contains the source. */
9355 if (source
>= trampoline_frag
->fr_address
9356 && source
<= trampoline_frag
->fr_address
+
9357 trampoline_frag
->fr_fix
)
9360 off
= trampoline_frag
->fr_address
- fulcrum
;
9361 /* Stop if some trampoline is found and the search is more than
9362 J_RANGE / 4 from the projected fulcrum. A trampoline w/o jump
9363 around is nice, but it shouldn't have much overhead. */
9364 if (best
< idx
->n_entries
&& labs (off
) > J_RANGE
/ 4)
9367 off
= trampoline_frag
->fr_address
- source
;
9368 if (labs (off
) < J_RANGE
- J_MARGIN
)
9371 /* Stop if a trampoline w/o jump around is found or initialized
9372 trampoline with jump around is found. */
9373 if (!trampoline_frag
->tc_frag_data
.needs_jump_around
||
9374 trampoline_frag
->fr_fix
)
9376 else if (best
>= idx
->n_entries
)
9382 if (best
< idx
->n_entries
)
9385 as_fatal (_("cannot find suitable trampoline"));
9388 static fixS
*xg_relax_fixup (struct trampoline_index
*idx
, fixS
*fixP
)
9390 symbolS
*s
= fixP
->fx_addsy
;
9391 addressT source
= fixP
->fx_frag
->fr_address
;
9392 addressT target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9393 size_t tr
= xg_find_best_trampoline (idx
, source
, target
);
9394 fragS
*trampoline_frag
= idx
->entry
[tr
];
9397 init_trampoline_frag (trampoline_frag
);
9398 newfixP
= xg_append_jump (trampoline_frag
,
9399 fixP
->fx_addsy
, fixP
->fx_offset
);
9401 /* Adjust the fixup for the original "j" instruction to
9402 point to the newly added jump. */
9403 fixP
->fx_addsy
= trampoline_frag
->fr_symbol
;
9404 fixP
->fx_offset
= trampoline_frag
->fr_fix
- 3;
9405 fixP
->tc_fix_data
.X_add_symbol
= trampoline_frag
->fr_symbol
;
9406 fixP
->tc_fix_data
.X_add_number
= trampoline_frag
->fr_fix
- 3;
9408 trampoline_frag
->tc_frag_data
.relax_seen
= FALSE
;
9410 if (xg_is_trampoline_frag_full (trampoline_frag
))
9411 xg_remove_trampoline_from_index (idx
, tr
);
9416 static bfd_boolean
xg_is_relaxable_fixup (fixS
*fixP
)
9418 xtensa_isa isa
= xtensa_default_isa
;
9419 addressT addr
= fixP
->fx_frag
->fr_address
;
9422 symbolS
*s
= fixP
->fx_addsy
;
9425 xtensa_opcode opcode
;
9427 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9428 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9431 target
= S_GET_VALUE (s
) + fixP
->fx_offset
;
9432 delta
= target
- addr
;
9434 if (labs (delta
) < J_RANGE
- J_MARGIN
)
9437 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9438 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9440 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9441 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9442 slot
= fixP
->tc_fix_data
.slot
;
9443 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9444 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9445 return opcode
== xtensa_j_opcode
;
9448 static void xg_relax_fixups (struct trampoline_seg
*ts
)
9450 struct trampoline_index
*idx
= &ts
->index
;
9451 segment_info_type
*seginfo
= seg_info (now_seg
);
9454 for (fx
= seginfo
->fix_root
; fx
; fx
= fx
->fx_next
)
9457 struct trampoline_chain
*tc
= NULL
;
9459 if (xg_is_relaxable_fixup (fixP
))
9461 tc
= xg_find_best_eq_target (ts
, fixP
->fx_frag
->fr_address
,
9462 &fixP
->fx_addsy
, &fixP
->fx_offset
);
9464 tc
= xg_create_trampoline_chain (ts
, fixP
->fx_addsy
,
9469 while (xg_is_relaxable_fixup (fixP
))
9471 fixP
= xg_relax_fixup (idx
, fixP
);
9472 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
9478 /* Given a trampoline frag relax all jumps that might want to use this
9479 trampoline. Only do real work once per relaxation cycle, when
9480 xg_relax_trampoline is called for the first trampoline in the now_seg.
9481 Don't use stretch, don't update new_stretch: place fulcrums with a
9482 slack to tolerate code movement. In the worst case if a jump between
9483 two trampolines wouldn't reach the next relaxation pass will fix it. */
9484 static void xg_relax_trampoline (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
,
9485 long *new_stretch ATTRIBUTE_UNUSED
)
9487 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9489 if (ts
->index
.n_entries
&& ts
->index
.entry
[0] == fragP
)
9490 xg_relax_fixups (ts
);
9493 /* Return the number of bytes added to this fragment, given that the
9494 input has been stretched already by "stretch". */
9497 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9499 xtensa_isa isa
= xtensa_default_isa
;
9500 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9501 long new_stretch
= 0;
9502 const char *file_name
;
9505 static xtensa_insnbuf vbuf
= NULL
;
9506 int slot
, num_slots
;
9509 file_name
= as_where (&line
);
9510 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9512 fragP
->tc_frag_data
.unreported_expansion
= 0;
9514 switch (fragP
->fr_subtype
)
9516 case RELAX_ALIGN_NEXT_OPCODE
:
9517 /* Always convert. */
9518 if (fragP
->tc_frag_data
.relax_seen
)
9519 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9522 case RELAX_LOOP_END
:
9526 case RELAX_LOOP_END_ADD_NOP
:
9527 /* Add a NOP and switch to .fill 0. */
9528 new_stretch
= relax_frag_add_nop (fragP
);
9532 case RELAX_DESIRE_ALIGN
:
9533 /* Do nothing. The narrowing before this frag will either align
9538 case RELAX_LITERAL_FINAL
:
9541 case RELAX_LITERAL_NR
:
9543 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9544 gas_assert (unreported
== lit_size
);
9545 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9546 fragP
->fr_var
-= lit_size
;
9547 fragP
->fr_fix
+= lit_size
;
9553 vbuf
= xtensa_insnbuf_alloc (isa
);
9555 xtensa_insnbuf_from_chars
9556 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9557 fmt
= xtensa_format_decode (isa
, vbuf
);
9558 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9560 for (slot
= 0; slot
< num_slots
; slot
++)
9562 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9565 if (fragP
->tc_frag_data
.relax_seen
)
9566 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9570 case RELAX_IMMED_STEP1
:
9571 case RELAX_IMMED_STEP2
:
9572 case RELAX_IMMED_STEP3
:
9573 /* Place the immediate. */
9574 new_stretch
+= relax_frag_immed
9575 (now_seg
, fragP
, stretch
,
9576 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9577 fmt
, slot
, stretched_p
, FALSE
);
9581 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9587 case RELAX_LITERAL_POOL_BEGIN
:
9588 if (fragP
->fr_var
!= 0)
9590 /* We have a converted "candidate" literal pool;
9591 assemble a jump around it. */
9593 if (!litpool_slotbuf
)
9595 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9596 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9599 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9600 fragP
->tc_frag_data
.is_insn
= TRUE
;
9602 insn
.insn_type
= ITYPE_INSN
;
9603 insn
.opcode
= xtensa_j_opcode
;
9605 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9607 fmt
= xg_get_single_format (xtensa_j_opcode
);
9608 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9609 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9610 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9611 (unsigned char *)fragP
->fr_literal
+
9616 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9617 BFD_RELOC_XTENSA_SLOT0_OP
);
9621 case RELAX_LITERAL_POOL_END
:
9622 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9623 case RELAX_MAYBE_UNREACHABLE
:
9624 case RELAX_MAYBE_DESIRE_ALIGN
:
9625 /* No relaxation required. */
9628 case RELAX_FILL_NOP
:
9629 case RELAX_UNREACHABLE
:
9630 if (fragP
->tc_frag_data
.relax_seen
)
9631 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9634 case RELAX_TRAMPOLINE
:
9635 if (fragP
->tc_frag_data
.relax_seen
)
9636 xg_relax_trampoline (fragP
, stretch
, &new_stretch
);
9640 as_bad (_("bad relaxation state"));
9643 /* Tell gas we need another relaxation pass. */
9644 if (! fragP
->tc_frag_data
.relax_seen
)
9646 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9650 new_logical_line (file_name
, line
);
9656 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9658 addressT old_address
, old_next_address
, old_size
;
9659 addressT new_address
, new_next_address
, new_size
;
9662 /* All the frags with relax_frag_for_alignment prior to this one in the
9663 section have been done, hopefully eliminating the need for a NOP here.
9664 But, this will put it in if necessary. */
9666 /* Calculate the old address of this fragment and the next fragment. */
9667 old_address
= fragP
->fr_address
- stretch
;
9668 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9669 fragP
->tc_frag_data
.text_expansion
[0]);
9670 old_size
= old_next_address
- old_address
;
9672 /* Calculate the new address of this fragment and the next fragment. */
9673 new_address
= fragP
->fr_address
;
9675 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9676 new_size
= new_next_address
- new_address
;
9678 growth
= new_size
- old_size
;
9680 /* Fix up the text_expansion field and return the new growth. */
9681 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9686 /* Add a NOP instruction. */
9689 relax_frag_add_nop (fragS
*fragP
)
9691 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9692 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9693 assemble_nop (length
, nop_buf
);
9694 fragP
->tc_frag_data
.is_insn
= TRUE
;
9696 if (fragP
->fr_var
< length
)
9698 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9702 fragP
->fr_fix
+= length
;
9703 fragP
->fr_var
-= length
;
9708 static long future_alignment_required (fragS
*, long);
9711 relax_frag_for_align (fragS
*fragP
, long stretch
)
9713 /* Overview of the relaxation procedure for alignment:
9714 We can widen with NOPs or by widening instructions or by filling
9715 bytes after jump instructions. Find the opportune places and widen
9716 them if necessary. */
9721 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9722 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9723 || (fragP
->fr_subtype
== RELAX_SLOTS
9724 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9726 stretch_me
= future_alignment_required (fragP
, stretch
);
9727 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9733 /* We expanded on a previous pass. Can we shrink now? */
9734 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9735 if (shrink
<= stretch
&& stretch
> 0)
9737 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9743 /* Below here, diff > 0. */
9744 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9750 /* Return the address of the next frag that should be aligned.
9752 By "address" we mean the address it _would_ be at if there
9753 is no action taken to align it between here and the target frag.
9754 In other words, if no narrows and no fill nops are used between
9755 here and the frag to align, _even_if_ some of the frags we use
9756 to align targets have already expanded on a previous relaxation
9759 Also, count each frag that may be used to help align the target.
9761 Return 0 if there are no frags left in the chain that need to be
9765 find_address_of_next_align_frag (fragS
**fragPP
,
9769 bfd_boolean
*paddable
)
9771 fragS
*fragP
= *fragPP
;
9772 addressT address
= fragP
->fr_address
;
9774 /* Do not reset the counts to 0. */
9778 /* Limit this to a small search. */
9779 if (*widens
>= (int) xtensa_fetch_width
)
9784 address
+= fragP
->fr_fix
;
9786 if (fragP
->fr_type
== rs_fill
)
9787 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9788 else if (fragP
->fr_type
== rs_machine_dependent
)
9790 switch (fragP
->fr_subtype
)
9792 case RELAX_UNREACHABLE
:
9796 case RELAX_FILL_NOP
:
9798 if (!fragP
->tc_frag_data
.is_no_density
)
9803 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9808 address
+= total_frag_text_expansion (fragP
);
9812 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9815 case RELAX_ALIGN_NEXT_OPCODE
:
9816 case RELAX_DESIRE_ALIGN
:
9820 case RELAX_MAYBE_UNREACHABLE
:
9821 case RELAX_MAYBE_DESIRE_ALIGN
:
9826 /* Just punt if we don't know the type. */
9833 /* Just punt if we don't know the type. */
9837 fragP
= fragP
->fr_next
;
9845 static long bytes_to_stretch (fragS
*, int, int, int, int);
9848 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9850 fragS
*this_frag
= fragP
;
9854 int narrow_nops
= 0;
9855 bfd_boolean paddable
= FALSE
;
9856 offsetT local_opt_diff
;
9859 int stretch_amount
= 0;
9860 int local_stretch_amount
;
9861 int global_stretch_amount
;
9863 address
= find_address_of_next_align_frag
9864 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9868 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9869 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9871 frag_wane (this_frag
);
9875 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9876 opt_diff
= local_opt_diff
;
9877 gas_assert (opt_diff
>= 0);
9878 gas_assert (max_diff
>= opt_diff
);
9883 fragP
= fragP
->fr_next
;
9885 while (fragP
&& opt_diff
< max_diff
&& address
)
9887 /* We only use these to determine if we can exit early
9888 because there will be plenty of ways to align future
9890 int glob_widens
= 0;
9893 bfd_boolean glob_pad
= 0;
9894 address
= find_address_of_next_align_frag
9895 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9896 /* If there is a padable portion, then skip. */
9897 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9902 offsetT next_m_diff
;
9903 offsetT next_o_diff
;
9905 /* Downrange frags haven't had stretch added to them yet. */
9908 /* The address also includes any text expansion from this
9909 frag in a previous pass, but we don't want that. */
9910 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9912 /* Assume we are going to move at least opt_diff. In
9913 reality, we might not be able to, but assuming that
9914 we will helps catch cases where moving opt_diff pushes
9915 the next target from aligned to unaligned. */
9916 address
+= opt_diff
;
9918 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9920 /* Now cleanup for the adjustments to address. */
9921 next_o_diff
+= opt_diff
;
9922 next_m_diff
+= opt_diff
;
9923 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9924 opt_diff
= next_o_diff
;
9925 if (next_m_diff
< max_diff
)
9926 max_diff
= next_m_diff
;
9927 fragP
= fragP
->fr_next
;
9931 /* If there are enough wideners in between, do it. */
9934 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9936 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9941 local_stretch_amount
9942 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9943 num_widens
, local_opt_diff
);
9944 global_stretch_amount
9945 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9946 num_widens
, opt_diff
);
9947 /* If the condition below is true, then the frag couldn't
9948 stretch the correct amount for the global case, so we just
9949 optimize locally. We'll rely on the subsequent frags to get
9950 the correct alignment in the global case. */
9951 if (global_stretch_amount
< local_stretch_amount
)
9952 stretch_amount
= local_stretch_amount
;
9954 stretch_amount
= global_stretch_amount
;
9956 if (this_frag
->fr_subtype
== RELAX_SLOTS
9957 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9958 gas_assert (stretch_amount
<= 1);
9959 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9961 if (this_frag
->tc_frag_data
.is_no_density
)
9962 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9964 gas_assert (stretch_amount
<= 3);
9967 return stretch_amount
;
9971 /* The idea: widen everything you can to get a target or loop aligned,
9972 then start using NOPs.
9974 wide_nops = the number of wide NOPs available for aligning
9975 narrow_nops = the number of narrow NOPs available for aligning
9976 (a subset of wide_nops)
9977 widens = the number of narrow instructions that should be widened
9982 bytes_to_stretch (fragS
*this_frag
,
9991 int bytes_short
= desired_diff
- num_widens
;
9993 gas_assert (desired_diff
>= 0
9994 && desired_diff
< (signed) xtensa_fetch_width
);
9995 if (desired_diff
== 0)
9998 gas_assert (wide_nops
> 0 || num_widens
> 0);
10000 /* Always prefer widening to NOP-filling. */
10001 if (bytes_short
< 0)
10003 /* There are enough RELAX_NARROW frags after this one
10004 to align the target without widening this frag in any way. */
10008 if (bytes_short
== 0)
10010 /* Widen every narrow between here and the align target
10011 and the align target will be properly aligned. */
10012 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10018 /* From here we will need at least one NOP to get an alignment.
10019 However, we may not be able to align at all, in which case,
10021 nops_needed
= desired_diff
/ 3;
10023 /* If there aren't enough nops, don't widen. */
10024 if (nops_needed
> wide_nops
)
10027 /* First try it with all wide nops. */
10028 nop_bytes
= nops_needed
* 3;
10029 extra_bytes
= desired_diff
- nop_bytes
;
10031 if (nop_bytes
+ num_widens
>= desired_diff
)
10033 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10035 else if (num_widens
== extra_bytes
)
10040 /* Add a narrow nop. */
10044 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
10047 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
10049 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10050 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10051 else if (num_widens
== extra_bytes
)
10056 /* Replace a wide nop with a narrow nop--we can get here if
10057 extra_bytes was negative in the previous conditional. */
10058 if (narrow_nops
== 1)
10062 if (nop_bytes
+ num_widens
>= desired_diff
)
10064 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
10065 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
10066 else if (num_widens
== extra_bytes
)
10071 /* If we can't satisfy any of the above cases, then we can't align
10072 using padding or fill nops. */
10078 xg_find_best_trampoline_for_tinsn (TInsn
*tinsn
, fragS
*fragP
)
10080 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
10081 addressT source
= fragP
->fr_address
;
10082 addressT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
10083 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10086 if (!ts
|| !ts
->index
.n_entries
)
10089 i
= xg_find_best_trampoline (&ts
->index
, source
, target
);
10091 return ts
->index
.entry
[i
];
10095 /* Append jump to sym + offset to the end of the trampoline frag fragP.
10096 Adjust fragP's jump around if it's present. Adjust fragP's fr_fix/fr_var
10097 and finish the frag if it's full (but don't remove it from the trampoline
10098 frag index). Return fixup for the newly created jump. */
10099 static fixS
*xg_append_jump (fragS
*fragP
, symbolS
*sym
, offsetT offset
)
10104 xtensa_isa isa
= xtensa_default_isa
;
10106 gas_assert (fragP
->fr_var
>= 3);
10107 tinsn_init (&insn
);
10108 insn
.insn_type
= ITYPE_INSN
;
10109 insn
.opcode
= xtensa_j_opcode
;
10111 set_expr_symbol_offset (&insn
.tok
[0], sym
, offset
);
10112 fmt
= xg_get_single_format (xtensa_j_opcode
);
10113 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10114 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10115 xtensa_insnbuf_to_chars (isa
, trampoline_buf
,
10116 (unsigned char *)fragP
->fr_literal
+ fragP
->fr_fix
, 3);
10117 fixP
= fix_new (fragP
, fragP
->fr_fix
, 3, sym
, offset
, TRUE
,
10118 BFD_RELOC_XTENSA_SLOT0_OP
);
10119 fixP
->tc_fix_data
.slot
= 0;
10121 fragP
->fr_fix
+= 3;
10122 fragP
->fr_var
-= 3;
10124 /* Adjust the jump around this trampoline (if present). */
10125 if (fragP
->tc_frag_data
.jump_around_fix
)
10126 fragP
->tc_frag_data
.jump_around_fix
->fx_offset
+= 3;
10128 /* Do we have room for more? */
10129 if (xg_is_trampoline_frag_full (fragP
))
10132 fragP
->fr_subtype
= 0;
10140 init_trampoline_frag (fragS
*fp
)
10144 if (fp
->fr_fix
== 0)
10147 char label
[10 + 2 * sizeof(fp
)];
10149 sprintf (label
, ".L0_TR_%p", fp
);
10150 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10151 fp
->fr_symbol
= lsym
;
10152 if (fp
->tc_frag_data
.needs_jump_around
)
10154 fp
->tc_frag_data
.jump_around_fix
= xg_append_jump (fp
, lsym
, 3);
10162 xg_get_single_symbol_slot (fragS
*fragP
)
10167 for (i
= 0; i
< MAX_SLOTS
; ++i
)
10168 if (fragP
->tc_frag_data
.slot_symbols
[i
])
10170 gas_assert (slot
== -1);
10174 gas_assert (slot
>= 0 && slot
< MAX_SLOTS
);
10180 add_jump_to_trampoline (fragS
*tramp
, fragS
*origfrag
)
10182 int slot
= xg_get_single_symbol_slot (origfrag
);
10185 /* Assemble a jump to the target label in the trampoline frag. */
10186 fixP
= xg_append_jump (tramp
,
10187 origfrag
->tc_frag_data
.slot_symbols
[slot
],
10188 origfrag
->tc_frag_data
.slot_offsets
[slot
]);
10190 /* Modify the original j to point here. */
10191 origfrag
->tc_frag_data
.slot_symbols
[slot
] = tramp
->fr_symbol
;
10192 origfrag
->tc_frag_data
.slot_offsets
[slot
] = tramp
->fr_fix
- 3;
10194 /* If trampoline is full, remove it from the list. */
10195 if (xg_is_trampoline_frag_full (tramp
))
10197 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
10198 size_t tr
= xg_find_trampoline (&ts
->index
, tramp
->fr_address
);
10200 gas_assert (ts
->index
.entry
[tr
] == tramp
);
10201 xg_remove_trampoline_from_index (&ts
->index
, tr
);
10209 relax_frag_immed (segT segP
,
10216 bfd_boolean estimate_only
)
10220 bfd_boolean negatable_branch
= FALSE
;
10221 bfd_boolean branch_jmp_to_next
= FALSE
;
10222 bfd_boolean from_wide_insn
= FALSE
;
10223 xtensa_isa isa
= xtensa_default_isa
;
10225 offsetT frag_offset
;
10227 int num_text_bytes
, num_literal_bytes
;
10228 int literal_diff
, total_text_diff
, this_text_diff
;
10230 gas_assert (fragP
->fr_opcode
!= NULL
);
10232 xg_clear_vinsn (&cur_vinsn
);
10233 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10234 if (cur_vinsn
.num_slots
> 1)
10235 from_wide_insn
= TRUE
;
10237 tinsn
= cur_vinsn
.slots
[slot
];
10238 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10240 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10243 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10244 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10246 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10248 old_size
= xtensa_format_length (isa
, fmt
);
10250 /* Special case: replace a branch to the next instruction with a NOP.
10251 This is required to work around a hardware bug in T1040.0 and also
10252 serves as an optimization. */
10254 if (branch_jmp_to_next
10255 && ((old_size
== 2) || (old_size
== 3))
10256 && !next_frag_is_loop_target (fragP
))
10259 /* Here is the fun stuff: Get the immediate field from this
10260 instruction. If it fits, we are done. If not, find the next
10261 instruction sequence that fits. */
10263 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10264 istack_init (&istack
);
10265 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10266 min_steps
, stretch
);
10267 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10269 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10271 /* Figure out the number of bytes needed. */
10272 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10274 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10275 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10277 if (from_wide_insn
)
10280 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10283 num_text_bytes
+= old_size
;
10284 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10285 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10288 /* The first instruction in the relaxed sequence will go after
10289 the current wide instruction, and thus its symbolic immediates
10292 istack_init (&istack
);
10293 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10294 frag_offset
+ old_size
,
10295 min_steps
, stretch
+ old_size
);
10296 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10298 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10299 = (int) RELAX_IMMED
+ num_steps
;
10301 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10303 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10305 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10309 total_text_diff
= num_text_bytes
- old_size
;
10310 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10312 /* It MUST get larger. If not, we could get an infinite loop. */
10313 gas_assert (num_text_bytes
>= 0);
10314 gas_assert (literal_diff
>= 0);
10315 gas_assert (total_text_diff
>= 0);
10317 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10318 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10319 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10320 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10322 /* Find the associated expandable literal for this. */
10323 if (literal_diff
!= 0)
10325 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10328 gas_assert (literal_diff
== 4);
10329 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10331 /* We expect that the literal section state has NOT been
10333 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10334 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10335 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10337 /* We need to mark this section for another iteration
10343 if (negatable_branch
&& istack
.ninsn
> 1)
10344 update_next_frag_state (fragP
);
10346 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10347 if (istack
.ninsn
> 2 &&
10348 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10349 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10350 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10352 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10353 struct trampoline_seg
*ts
= find_trampoline_seg (segP
);
10354 struct trampoline_chain
*tc
= NULL
;
10357 !xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10360 int s
= xg_get_single_symbol_slot (fragP
);
10361 addressT offset
= fragP
->tc_frag_data
.slot_offsets
[s
];
10363 tc
= xg_find_best_eq_target (ts
, fragP
->fr_address
,
10364 &fragP
->tc_frag_data
.slot_symbols
[s
],
10368 tc
= xg_create_trampoline_chain (ts
,
10369 fragP
->tc_frag_data
.slot_symbols
[s
],
10371 fragP
->tc_frag_data
.slot_offsets
[s
] = offset
;
10372 tinsn_immed_from_frag (jinsn
, fragP
, s
);
10375 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
,
10378 fragS
*tf
= xg_find_best_trampoline_for_tinsn (jinsn
, fragP
);
10384 this_text_diff
+= init_trampoline_frag (tf
) + 3;
10385 fixP
= add_jump_to_trampoline (tf
, fragP
);
10386 xg_add_location_to_chain (tc
, fixP
->fx_frag
->fr_symbol
,
10388 fragP
->tc_frag_data
.relax_seen
= FALSE
;
10392 /* If target symbol is undefined, assume it will reach once linked. */
10393 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10395 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10397 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10398 _("jump target out of range; no usable trampoline found"));
10404 return this_text_diff
;
10408 /* md_convert_frag Hook and Helper Functions. */
10410 static void convert_frag_align_next_opcode (fragS
*);
10411 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10412 static void convert_frag_fill_nop (fragS
*);
10413 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10416 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10418 static xtensa_insnbuf vbuf
= NULL
;
10419 xtensa_isa isa
= xtensa_default_isa
;
10423 const char *file_name
;
10426 file_name
= as_where (&line
);
10427 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10429 switch (fragp
->fr_subtype
)
10431 case RELAX_ALIGN_NEXT_OPCODE
:
10432 /* Always convert. */
10433 convert_frag_align_next_opcode (fragp
);
10436 case RELAX_DESIRE_ALIGN
:
10437 /* Do nothing. If not aligned already, too bad. */
10440 case RELAX_LITERAL
:
10441 case RELAX_LITERAL_FINAL
:
10446 vbuf
= xtensa_insnbuf_alloc (isa
);
10448 xtensa_insnbuf_from_chars
10449 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10450 fmt
= xtensa_format_decode (isa
, vbuf
);
10451 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10453 for (slot
= 0; slot
< num_slots
; slot
++)
10455 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10458 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10462 case RELAX_IMMED_STEP1
:
10463 case RELAX_IMMED_STEP2
:
10464 case RELAX_IMMED_STEP3
:
10465 /* Place the immediate. */
10468 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10473 /* This is OK because some slots could have
10474 relaxations and others have none. */
10480 case RELAX_UNREACHABLE
:
10481 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10482 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10483 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10487 case RELAX_MAYBE_UNREACHABLE
:
10488 case RELAX_MAYBE_DESIRE_ALIGN
:
10492 case RELAX_FILL_NOP
:
10493 convert_frag_fill_nop (fragp
);
10496 case RELAX_LITERAL_NR
:
10497 if (use_literal_section
)
10499 /* This should have been handled during relaxation. When
10500 relaxing a code segment, literals sometimes need to be
10501 added to the corresponding literal segment. If that
10502 literal segment has already been relaxed, then we end up
10503 in this situation. Marking the literal segments as data
10504 would make this happen less often (since GAS always relaxes
10505 code before data), but we could still get into trouble if
10506 there are instructions in a segment that is not marked as
10507 containing code. Until we can implement a better solution,
10508 cheat and adjust the addresses of all the following frags.
10509 This could break subsequent alignments, but the linker's
10510 literal coalescing will do that anyway. */
10513 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10514 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10515 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10516 fragp
->fr_var
-= 4;
10517 fragp
->fr_fix
+= 4;
10518 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10519 f
->fr_address
+= 4;
10522 as_bad (_("invalid relaxation fragment result"));
10525 case RELAX_TRAMPOLINE
:
10530 new_logical_line (file_name
, line
);
10535 convert_frag_align_next_opcode (fragS
*fragp
)
10537 char *nop_buf
; /* Location for Writing. */
10538 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10539 addressT aligned_address
;
10541 int nop
, nop_count
;
10543 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10545 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10546 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10547 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10549 for (nop
= 0; nop
< nop_count
; nop
++)
10552 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10554 assemble_nop (nop_size
, nop_buf
);
10555 nop_buf
+= nop_size
;
10558 fragp
->fr_fix
+= fill_size
;
10559 fragp
->fr_var
-= fill_size
;
10564 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10566 TInsn tinsn
, single_target
;
10567 int size
, old_size
, diff
;
10568 offsetT frag_offset
;
10570 gas_assert (slot
== 0);
10571 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10573 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10575 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10576 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10577 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10582 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10584 /* No conversion. */
10589 gas_assert (fragP
->fr_opcode
!= NULL
);
10591 /* Frags in this relaxation state should only contain
10592 single instruction bundles. */
10593 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10595 /* Just convert it to a wide form.... */
10597 old_size
= xg_get_single_size (tinsn
.opcode
);
10599 tinsn_init (&single_target
);
10600 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10602 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10604 as_bad (_("unable to widen instruction"));
10608 size
= xg_get_single_size (single_target
.opcode
);
10609 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10610 frag_offset
, TRUE
);
10612 diff
= size
- old_size
;
10613 gas_assert (diff
>= 0);
10614 gas_assert (diff
<= fragP
->fr_var
);
10615 fragP
->fr_var
-= diff
;
10616 fragP
->fr_fix
+= diff
;
10624 convert_frag_fill_nop (fragS
*fragP
)
10626 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10627 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10628 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10629 - fragP
->fr_address
- fragP
->fr_fix
));
10632 /* No conversion. */
10636 assemble_nop (size
, loc
);
10637 fragP
->tc_frag_data
.is_insn
= TRUE
;
10638 fragP
->fr_var
-= size
;
10639 fragP
->fr_fix
+= size
;
10644 static fixS
*fix_new_exp_in_seg
10645 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10646 bfd_reloc_code_real_type
);
10647 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10650 convert_frag_immed (segT segP
,
10656 char *immed_instr
= fragP
->fr_opcode
;
10658 bfd_boolean expanded
= FALSE
;
10659 bfd_boolean branch_jmp_to_next
= FALSE
;
10660 char *fr_opcode
= fragP
->fr_opcode
;
10661 xtensa_isa isa
= xtensa_default_isa
;
10662 bfd_boolean from_wide_insn
= FALSE
;
10664 bfd_boolean is_loop
;
10666 gas_assert (fr_opcode
!= NULL
);
10668 xg_clear_vinsn (&cur_vinsn
);
10670 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10671 if (cur_vinsn
.num_slots
> 1)
10672 from_wide_insn
= TRUE
;
10674 orig_tinsn
= cur_vinsn
.slots
[slot
];
10675 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10677 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10679 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10680 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10682 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10684 /* Conversion just inserts a NOP and marks the fix as completed. */
10685 bytes
= xtensa_format_length (isa
, fmt
);
10688 cur_vinsn
.slots
[slot
].opcode
=
10689 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10690 cur_vinsn
.slots
[slot
].ntok
= 0;
10694 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10695 gas_assert (bytes
== 2 || bytes
== 3);
10696 build_nop (&cur_vinsn
.slots
[0], bytes
);
10697 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10699 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10700 xtensa_insnbuf_to_chars
10701 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10706 /* Here is the fun stuff: Get the immediate field from this
10707 instruction. If it fits, we're done. If not, find the next
10708 instruction sequence that fits. */
10712 symbolS
*lit_sym
= NULL
;
10713 int total_size
= 0;
10714 int target_offset
= 0;
10717 symbolS
*gen_label
= NULL
;
10718 offsetT frag_offset
;
10719 bfd_boolean first
= TRUE
;
10721 /* It does not fit. Find something that does and
10722 convert immediately. */
10723 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10724 istack_init (&istack
);
10725 xg_assembly_relax (&istack
, &orig_tinsn
,
10726 segP
, fragP
, frag_offset
, min_steps
, 0);
10728 old_size
= xtensa_format_length (isa
, fmt
);
10730 /* Assemble this right inline. */
10732 /* First, create the mapping from a label name to the REAL label. */
10734 for (i
= 0; i
< istack
.ninsn
; i
++)
10736 TInsn
*tinsn
= &istack
.insn
[i
];
10739 switch (tinsn
->insn_type
)
10741 case ITYPE_LITERAL
:
10742 if (lit_sym
!= NULL
)
10743 as_bad (_("multiple literals in expansion"));
10744 /* First find the appropriate space in the literal pool. */
10745 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10746 if (lit_frag
== NULL
)
10747 as_bad (_("no registered fragment for literal"));
10748 if (tinsn
->ntok
!= 1)
10749 as_bad (_("number of literal tokens != 1"));
10751 /* Set the literal symbol and add a fixup. */
10752 lit_sym
= lit_frag
->fr_symbol
;
10756 if (align_targets
&& !is_loop
)
10758 fragS
*unreach
= fragP
->fr_next
;
10759 while (!(unreach
->fr_type
== rs_machine_dependent
10760 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10761 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10763 unreach
= unreach
->fr_next
;
10766 gas_assert (unreach
->fr_type
== rs_machine_dependent
10767 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10768 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10770 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10772 gas_assert (gen_label
== NULL
);
10773 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10774 fr_opcode
- fragP
->fr_literal
10775 + target_offset
, fragP
);
10779 if (first
&& from_wide_insn
)
10781 target_offset
+= xtensa_format_length (isa
, fmt
);
10783 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10784 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10787 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10794 for (i
= 0; i
< istack
.ninsn
; i
++)
10796 TInsn
*tinsn
= &istack
.insn
[i
];
10800 bfd_reloc_code_real_type reloc_type
;
10802 switch (tinsn
->insn_type
)
10804 case ITYPE_LITERAL
:
10805 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10806 /* Already checked. */
10807 gas_assert (lit_frag
!= NULL
);
10808 gas_assert (lit_sym
!= NULL
);
10809 gas_assert (tinsn
->ntok
== 1);
10811 target_seg
= S_GET_SEGMENT (lit_sym
);
10812 gas_assert (target_seg
);
10813 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10814 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10815 &tinsn
->tok
[0], FALSE
, reloc_type
);
10822 xg_resolve_labels (tinsn
, gen_label
);
10823 xg_resolve_literals (tinsn
, lit_sym
);
10824 if (from_wide_insn
&& first
)
10827 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10829 cur_vinsn
.slots
[slot
] = *tinsn
;
10833 cur_vinsn
.slots
[slot
].opcode
=
10834 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10835 cur_vinsn
.slots
[slot
].ntok
= 0;
10837 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10838 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10839 (unsigned char *) immed_instr
, 0);
10840 fragP
->tc_frag_data
.is_insn
= TRUE
;
10841 size
= xtensa_format_length (isa
, fmt
);
10842 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10844 xg_emit_insn_to_buf
10845 (tinsn
, immed_instr
+ size
, fragP
,
10846 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10847 size
+= xg_get_single_size (tinsn
->opcode
);
10852 size
= xg_get_single_size (tinsn
->opcode
);
10853 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10854 immed_instr
- fragP
->fr_literal
, TRUE
);
10856 immed_instr
+= size
;
10857 total_size
+= size
;
10862 diff
= total_size
- old_size
;
10863 gas_assert (diff
>= 0);
10866 gas_assert (diff
<= fragP
->fr_var
);
10867 fragP
->fr_var
-= diff
;
10868 fragP
->fr_fix
+= diff
;
10871 /* Check for undefined immediates in LOOP instructions. */
10875 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10876 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10878 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10881 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10882 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10884 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10889 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10890 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10892 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10894 /* Add an expansion note on the expanded instruction. */
10895 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10896 &orig_tinsn
.tok
[0], TRUE
,
10897 BFD_RELOC_XTENSA_ASM_EXPAND
);
10902 /* Add a new fix expression into the desired segment. We have to
10903 switch to that segment to do this. */
10906 fix_new_exp_in_seg (segT new_seg
,
10907 subsegT new_subseg
,
10913 bfd_reloc_code_real_type r_type
)
10916 segT seg
= now_seg
;
10917 subsegT subseg
= now_subseg
;
10919 gas_assert (new_seg
!= 0);
10920 subseg_set (new_seg
, new_subseg
);
10922 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10923 subseg_set (seg
, subseg
);
10928 /* Relax a loop instruction so that it can span loop >256 bytes.
10934 addi as, as, lo8 (label-.L1)
10935 addmi as, as, mid8 (label-.L1)
10946 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10951 unsigned long target
;
10952 static xtensa_insnbuf insnbuf
= NULL
;
10953 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10954 xtensa_isa isa
= xtensa_default_isa
;
10955 addressT loop_offset
;
10956 addressT addi_offset
= 9;
10957 addressT addmi_offset
= 12;
10962 insnbuf
= xtensa_insnbuf_alloc (isa
);
10964 /* Get the loop offset. */
10965 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10967 /* Validate that there really is a LOOP at the loop_offset. Because
10968 loops are not bundleable, we can assume that the instruction will be
10970 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10971 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10973 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10974 addi_offset
+= loop_offset
;
10975 addmi_offset
+= loop_offset
;
10977 gas_assert (tinsn
->ntok
== 2);
10978 if (tinsn
->tok
[1].X_op
== O_constant
)
10979 target
= tinsn
->tok
[1].X_add_number
;
10980 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10982 /* Find the fragment. */
10983 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10984 gas_assert (S_GET_SEGMENT (sym
) == segP
10985 || S_GET_SEGMENT (sym
) == absolute_section
);
10986 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10990 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10994 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10995 loop_length_hi
= loop_length
& ~0x0ff;
10996 loop_length_lo
= loop_length
& 0x0ff;
10997 if (loop_length_lo
>= 128)
10999 loop_length_lo
-= 256;
11000 loop_length_hi
+= 256;
11003 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
11004 32512. If the loop is larger than that, then we just fail. */
11005 if (loop_length_hi
> 32512)
11006 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
11007 _("loop too long for LOOP instruction"));
11009 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
11010 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
11012 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
11013 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
11015 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
11016 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
11018 fragP
->tc_frag_data
.is_insn
= TRUE
;
11019 xtensa_insnbuf_to_chars
11020 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
11022 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
11023 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
11024 xtensa_insnbuf_to_chars
11025 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
11027 /* Walk through all of the frags from here to the loop end
11028 and mark them as no_transform to keep them from being modified
11029 by the linker. If we ever have a relocation for the
11030 addi/addmi of the difference of two symbols we can remove this. */
11033 for (next_fragP
= fragP
; next_fragP
!= NULL
;
11034 next_fragP
= next_fragP
->fr_next
)
11036 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
11037 if (next_fragP
->tc_frag_data
.is_loop_target
)
11039 if (target_count
== 2)
11045 /* A map that keeps information on a per-subsegment basis. This is
11046 maintained during initial assembly, but is invalid once the
11047 subsegments are smashed together. I.E., it cannot be used during
11050 typedef struct subseg_map_struct
11058 float total_freq
; /* fall-through + branch target frequency */
11059 float target_freq
; /* branch target frequency alone */
11061 struct subseg_map_struct
*next
;
11065 static subseg_map
*sseg_map
= NULL
;
11067 static subseg_map
*
11068 get_subseg_info (segT seg
, subsegT subseg
)
11070 subseg_map
*subseg_e
;
11072 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
11074 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
11081 static subseg_map
*
11082 add_subseg_info (segT seg
, subsegT subseg
)
11084 subseg_map
*subseg_e
= XNEW (subseg_map
);
11085 memset (subseg_e
, 0, sizeof (subseg_map
));
11086 subseg_e
->seg
= seg
;
11087 subseg_e
->subseg
= subseg
;
11088 subseg_e
->flags
= 0;
11089 /* Start off considering every branch target very important. */
11090 subseg_e
->target_freq
= 1.0;
11091 subseg_e
->total_freq
= 1.0;
11092 subseg_e
->next
= sseg_map
;
11093 sseg_map
= subseg_e
;
11099 get_last_insn_flags (segT seg
, subsegT subseg
)
11101 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11103 return subseg_e
->flags
;
11109 set_last_insn_flags (segT seg
,
11114 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11116 subseg_e
= add_subseg_info (seg
, subseg
);
11118 subseg_e
->flags
|= fl
;
11120 subseg_e
->flags
&= ~fl
;
11125 get_subseg_total_freq (segT seg
, subsegT subseg
)
11127 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11129 return subseg_e
->total_freq
;
11135 get_subseg_target_freq (segT seg
, subsegT subseg
)
11137 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11139 return subseg_e
->target_freq
;
11145 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11147 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11149 subseg_e
= add_subseg_info (seg
, subseg
);
11150 subseg_e
->total_freq
= total_f
;
11151 subseg_e
->target_freq
= target_f
;
11155 /* Segment Lists and emit_state Stuff. */
11158 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11163 segT literal_section
= head
->seg
;
11165 /* Move the literal section to the front of the section list. */
11166 gas_assert (literal_section
);
11167 if (literal_section
!= stdoutput
->sections
)
11169 bfd_section_list_remove (stdoutput
, literal_section
);
11170 bfd_section_list_prepend (stdoutput
, literal_section
);
11177 static void mark_literal_frags (seg_list
*);
11180 xg_promote_candidate_litpool (struct litpool_seg
*lps
,
11181 struct litpool_frag
*lp
)
11186 char label
[10 + 2 * sizeof (fragS
*)];
11188 poolbeg
= lp
->fragP
;
11190 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11191 poolend
= poolbeg
->fr_next
;
11192 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11193 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11194 /* Create a local symbol pointing to the
11195 end of the pool. */
11196 sprintf (label
, ".L0_LT_%p", poolbeg
);
11197 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11199 poolbeg
->fr_symbol
= lsym
;
11200 /* Rest is done in xtensa_relax_frag. */
11203 static struct litpool_frag
*xg_find_litpool (struct litpool_seg
*lps
,
11204 struct litpool_frag
*lpf
,
11207 struct litpool_frag
*lp
= lpf
->prev
;
11209 gas_assert (lp
->fragP
);
11211 while (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11214 if (lp
->fragP
== NULL
)
11216 /* End of list; have to bite the bullet.
11217 Take the nearest. */
11221 /* Does it (conservatively) reach? */
11222 if (addr
- lp
->addr
<= 128 * 1024)
11224 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
11225 lp
->literal_count
< MAX_POOL_LITERALS
)
11227 /* Found a good one. */
11230 else if (lp
->prev
->fragP
&&
11231 addr
- lp
->prev
->addr
> 128 * 1024 &&
11232 lp
->prev
->literal_count
< MAX_POOL_LITERALS
)
11234 /* This is still a "candidate" but the next one
11235 will be too far away, so revert to the nearest
11236 one, convert it and add the jump around. */
11243 if (lp
->literal_count
>= MAX_POOL_LITERALS
)
11246 while (lp
&& lp
->fragP
&& lp
->literal_count
>= MAX_POOL_LITERALS
)
11253 gas_assert (lp
&& lp
->fragP
&& lp
->literal_count
< MAX_POOL_LITERALS
);
11254 ++lp
->literal_count
;
11256 /* Convert candidate and add the jump around. */
11257 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11258 xg_promote_candidate_litpool (lps
, lp
);
11264 xtensa_move_literals (void)
11267 frchainS
*frchain_from
, *frchain_to
;
11268 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11269 fragS
**frag_splice
;
11272 fixS
*fix
, *next_fix
, **fix_splice
;
11274 struct litpool_seg
*lps
;
11275 const char *init_name
= INIT_SECTION_NAME
;
11276 const char *fini_name
= FINI_SECTION_NAME
;
11277 int init_name_len
= strlen(init_name
);
11278 int fini_name_len
= strlen(fini_name
);
11280 mark_literal_frags (literal_head
->next
);
11282 if (use_literal_section
)
11285 /* Assign addresses (rough estimates) to the potential literal pool locations
11286 and create new ones if the gaps are too large. */
11288 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11290 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11291 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11294 for ( ; frchP
; frchP
= frchP
->frch_next
)
11297 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11299 if (lpf
&& fragP
== lpf
->fragP
)
11301 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11302 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11303 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11304 /* Found a litpool location. */
11308 if (fragP
->fr_type
== rs_machine_dependent
&&
11309 fragP
->fr_subtype
== RELAX_SLOTS
)
11312 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11314 if (fragP
->tc_frag_data
.literal_frags
[slot
])
11316 /* L32R; point its literal to the nearest litpool
11317 preferring non-"candidate" positions to avoid
11318 the jump-around. */
11319 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11321 if (!litfrag
->tc_frag_data
.literal_frag
)
11323 struct litpool_frag
*lp
;
11325 lp
= xg_find_litpool (lps
, lpf
, addr
);
11326 /* Take earliest use of this literal to avoid
11328 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11333 addr
+= fragP
->fr_fix
;
11334 if (fragP
->fr_type
== rs_fill
)
11335 addr
+= fragP
->fr_offset
;
11340 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11342 const char *seg_name
= segment_name (segment
->seg
);
11344 /* Keep the literals for .init and .fini in separate sections. */
11345 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11346 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11347 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11348 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11351 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11352 search_frag
= frchain_from
->frch_root
;
11353 literal_pool
= NULL
;
11355 frag_splice
= &(frchain_from
->frch_root
);
11357 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11359 gas_assert (search_frag
->fr_fix
== 0
11360 || search_frag
->fr_type
== rs_align
);
11361 search_frag
= search_frag
->fr_next
;
11366 search_frag
= frchain_from
->frch_root
;
11367 as_bad_where (search_frag
->fr_file
, search_frag
->fr_line
,
11368 _("literal pool location required for text-section-literals; specify with .literal_position"));
11372 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11373 == RELAX_LITERAL_POOL_BEGIN
);
11374 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11376 /* Make sure that all the frags in this series are closed, and
11377 that there is at least one left over of zero-size. This
11378 prevents us from making a segment with an frchain without any
11380 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11381 xtensa_set_frag_assembly_state (frag_now
);
11382 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11383 xtensa_set_frag_assembly_state (frag_now
);
11385 while (search_frag
!= frag_now
)
11387 next_frag
= search_frag
->fr_next
;
11388 if (search_frag
->tc_frag_data
.literal_frag
)
11390 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11391 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11392 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11393 gas_assert (frchain_to
);
11396 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11398 /* Skip empty fill frags. */
11399 *frag_splice
= next_frag
;
11400 search_frag
= next_frag
;
11404 if (search_frag
->fr_type
== rs_align
)
11406 /* Skip alignment frags, because the pool as a whole will be
11407 aligned if used, and we don't want to force alignment if the
11409 *frag_splice
= next_frag
;
11410 search_frag
= next_frag
;
11414 /* First, move the frag out of the literal section and
11415 to the appropriate place. */
11417 /* Insert an alignment frag at start of pool. */
11418 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11419 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11421 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11422 emit_state prev_state
;
11425 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11426 prev_frag
= frag_now
;
11427 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11428 align_frag
= frag_now
;
11429 frag_align (2, 0, 0);
11430 /* Splice it into the right place. */
11431 prev_frag
->fr_next
= align_frag
->fr_next
;
11432 align_frag
->fr_next
= literal_pool
->fr_next
;
11433 literal_pool
->fr_next
= align_frag
;
11434 /* Insert after this one. */
11435 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11436 xtensa_restore_emit_state (&prev_state
);
11438 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11439 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11440 /* Skip align frag. */
11441 if (insert_after
->fr_next
->fr_type
== rs_align
)
11443 insert_after
= insert_after
->fr_next
;
11446 *frag_splice
= next_frag
;
11447 search_frag
->fr_next
= insert_after
->fr_next
;
11448 insert_after
->fr_next
= search_frag
;
11449 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11450 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11452 /* Now move any fixups associated with this frag to the
11454 fix
= frchain_from
->fix_root
;
11455 fix_splice
= &(frchain_from
->fix_root
);
11458 next_fix
= fix
->fx_next
;
11459 if (fix
->fx_frag
== search_frag
)
11461 *fix_splice
= next_fix
;
11462 fix
->fx_next
= frchain_to
->fix_root
;
11463 frchain_to
->fix_root
= fix
;
11464 if (frchain_to
->fix_tail
== NULL
)
11465 frchain_to
->fix_tail
= fix
;
11468 fix_splice
= &(fix
->fx_next
);
11471 search_frag
= next_frag
;
11474 if (frchain_from
->fix_root
!= NULL
)
11476 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11477 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11479 gas_assert (frchain_from
->fix_root
== NULL
);
11481 frchain_from
->fix_tail
= NULL
;
11482 xtensa_restore_emit_state (&state
);
11485 /* Now fix up the SEGMENT value for all the literal symbols. */
11486 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11488 symbolS
*lit_sym
= lit
->sym
;
11489 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11491 S_SET_SEGMENT (lit_sym
, dseg
);
11496 /* Walk over all the frags for segments in a list and mark them as
11497 containing literals. As clunky as this is, we can't rely on frag_var
11498 and frag_variant to get called in all situations. */
11501 mark_literal_frags (seg_list
*segment
)
11503 frchainS
*frchain_from
;
11504 fragS
*search_frag
;
11508 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11509 search_frag
= frchain_from
->frch_root
;
11510 while (search_frag
)
11512 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11513 search_frag
= search_frag
->fr_next
;
11515 segment
= segment
->next
;
11521 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11523 /* Move all of the sections in the section list to come
11524 after "after" in the gnu segment list. */
11529 segT literal_section
= head
->seg
;
11531 /* Move the literal section after "after". */
11532 gas_assert (literal_section
);
11533 if (literal_section
!= after
)
11535 bfd_section_list_remove (stdoutput
, literal_section
);
11536 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11544 /* Push all the literal segments to the end of the gnu list. */
11547 xtensa_reorder_segments (void)
11554 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11560 /* Now that we have the last section, push all the literal
11561 sections to the end. */
11562 xtensa_reorder_seg_list (literal_head
, last_sec
);
11564 /* Now perform the final error check. */
11565 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11567 gas_assert (new_count
== old_count
);
11571 /* Change the emit state (seg, subseg, and frag related stuff) to the
11572 correct location. Return a emit_state which can be passed to
11573 xtensa_restore_emit_state to return to current fragment. */
11576 xtensa_switch_to_literal_fragment (emit_state
*result
)
11578 if (directive_state
[directive_absolute_literals
])
11580 segT lit4_seg
= cache_literal_section (TRUE
);
11581 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11584 xtensa_switch_to_non_abs_literal_fragment (result
);
11586 /* Do a 4-byte align here. */
11587 frag_align (2, 0, 0);
11588 record_alignment (now_seg
, 2);
11593 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11595 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11597 bfd_boolean is_init
=
11598 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
11599 bfd_boolean is_fini
=
11600 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
11602 if (pool_location
== NULL
11603 && !use_literal_section
11604 && !is_init
&& ! is_fini
)
11606 if (!auto_litpools
)
11608 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11610 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
11611 pool_location
= get_literal_pool_location (now_seg
);
11614 lit_seg
= cache_literal_section (FALSE
);
11615 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11617 if (!use_literal_section
11618 && !is_init
&& !is_fini
11619 && get_literal_pool_location (now_seg
) != pool_location
)
11621 /* Close whatever frag is there. */
11622 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11623 xtensa_set_frag_assembly_state (frag_now
);
11624 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11625 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11626 xtensa_set_frag_assembly_state (frag_now
);
11631 /* Call this function before emitting data into the literal section.
11632 This is a helper function for xtensa_switch_to_literal_fragment.
11633 This is similar to a .section new_now_seg subseg. */
11636 xtensa_switch_section_emit_state (emit_state
*state
,
11638 subsegT new_now_subseg
)
11640 state
->name
= now_seg
->name
;
11641 state
->now_seg
= now_seg
;
11642 state
->now_subseg
= now_subseg
;
11643 state
->generating_literals
= generating_literals
;
11644 generating_literals
++;
11645 subseg_set (new_now_seg
, new_now_subseg
);
11649 /* Use to restore the emitting into the normal place. */
11652 xtensa_restore_emit_state (emit_state
*state
)
11654 generating_literals
= state
->generating_literals
;
11655 subseg_set (state
->now_seg
, state
->now_subseg
);
11659 /* Predicate function used to look up a section in a particular group. */
11662 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11664 const char *gname
= inf
;
11665 const char *group_name
= elf_group_name (sec
);
11667 return (group_name
== gname
11668 || (group_name
!= NULL
11670 && strcmp (group_name
, gname
) == 0));
11674 /* Get the literal section to be used for the current text section.
11675 The result may be cached in the default_lit_sections structure. */
11678 cache_literal_section (bfd_boolean use_abs_literals
)
11680 const char *text_name
, *group_name
= 0;
11681 const char *base_name
, *suffix
;
11684 segT seg
, current_section
;
11685 int current_subsec
;
11686 bfd_boolean linkonce
= FALSE
;
11688 /* Save the current section/subsection. */
11689 current_section
= now_seg
;
11690 current_subsec
= now_subseg
;
11692 /* Clear the cached values if they are no longer valid. */
11693 if (now_seg
!= default_lit_sections
.current_text_seg
)
11695 default_lit_sections
.current_text_seg
= now_seg
;
11696 default_lit_sections
.lit_seg
= NULL
;
11697 default_lit_sections
.lit4_seg
= NULL
;
11700 /* Check if the literal section is already cached. */
11701 if (use_abs_literals
)
11702 pcached
= &default_lit_sections
.lit4_seg
;
11704 pcached
= &default_lit_sections
.lit_seg
;
11709 text_name
= default_lit_sections
.lit_prefix
;
11710 if (! text_name
|| ! *text_name
)
11712 text_name
= segment_name (current_section
);
11713 group_name
= elf_group_name (current_section
);
11714 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11717 base_name
= use_abs_literals
? ".lit4" : ".literal";
11720 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11722 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11724 suffix
= strchr (text_name
+ linkonce_len
, '.');
11726 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11732 /* If the section name begins or ends with ".text", then replace
11733 that portion instead of appending an additional suffix. */
11734 size_t len
= strlen (text_name
);
11736 && (strcmp (text_name
+ len
- 5, ".text") == 0
11737 || strncmp (text_name
, ".text", 5) == 0))
11740 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11741 if (strncmp (text_name
, ".text", 5) == 0)
11743 strcpy (name
, base_name
);
11744 strcat (name
, text_name
+ 5);
11748 strcpy (name
, text_name
);
11749 strcpy (name
+ len
, base_name
);
11753 /* Canonicalize section names to allow renaming literal sections.
11754 The group name, if any, came from the current text section and
11755 has already been canonicalized. */
11756 name
= tc_canonicalize_symbol_name (name
);
11758 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11759 (void *) group_name
);
11764 seg
= subseg_force_new (name
, 0);
11766 if (! use_abs_literals
)
11768 /* Add the newly created literal segment to the list. */
11769 seg_list
*n
= XNEW (seg_list
);
11771 n
->next
= literal_head
->next
;
11772 literal_head
->next
= n
;
11775 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11776 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11777 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11779 elf_group_name (seg
) = group_name
;
11781 bfd_set_section_flags (stdoutput
, seg
, flags
);
11782 bfd_set_section_alignment (stdoutput
, seg
, 2);
11786 subseg_set (current_section
, current_subsec
);
11791 /* Property Tables Stuff. */
11793 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11794 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11795 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11797 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11798 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11800 static bfd_boolean
get_frag_is_literal (const fragS
*);
11801 static void xtensa_create_property_segments
11802 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11803 static void xtensa_create_xproperty_segments
11804 (frag_flags_fn
, const char *, xt_section_type
);
11805 static bfd_boolean
exclude_section_from_property_tables (segT
);
11806 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11807 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11808 static void add_xt_block_frags
11809 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11810 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11811 static void xtensa_frag_flags_init (frag_flags
*);
11812 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11813 static flagword
frag_flags_to_number (const frag_flags
*);
11814 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11816 /* Set up property tables after relaxation. */
11819 xtensa_post_relax_hook (void)
11821 xtensa_move_seg_list_to_beginning (literal_head
);
11823 xtensa_find_unmarked_state_frags ();
11824 xtensa_mark_frags_for_org ();
11825 xtensa_mark_difference_of_two_symbols ();
11827 xtensa_create_property_segments (get_frag_is_literal
,
11829 XTENSA_LIT_SEC_NAME
,
11831 xtensa_create_xproperty_segments (get_frag_property_flags
,
11832 XTENSA_PROP_SEC_NAME
,
11835 if (warn_unaligned_branch_targets
)
11836 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11837 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11841 /* This function is only meaningful after xtensa_move_literals. */
11844 get_frag_is_literal (const fragS
*fragP
)
11846 gas_assert (fragP
!= NULL
);
11847 return fragP
->tc_frag_data
.is_literal
;
11852 xtensa_create_property_segments (frag_predicate property_function
,
11853 frag_predicate end_property_function
,
11854 const char *section_name_base
,
11855 xt_section_type sec_type
)
11859 /* Walk over all of the current segments.
11860 Walk over each fragment
11861 For each non-empty fragment,
11862 Build a property record (append where possible). */
11864 for (seclist
= &stdoutput
->sections
;
11865 seclist
&& *seclist
;
11866 seclist
= &(*seclist
)->next
)
11868 segT sec
= *seclist
;
11870 if (exclude_section_from_property_tables (sec
))
11873 if (section_has_property (sec
, property_function
))
11875 segment_info_type
*xt_seg_info
;
11876 xtensa_block_info
**xt_blocks
;
11877 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11879 prop_sec
->output_section
= prop_sec
;
11880 subseg_set (prop_sec
, 0);
11881 xt_seg_info
= seg_info (prop_sec
);
11882 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11884 /* Walk over all of the frchains here and add new sections. */
11885 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11886 end_property_function
);
11890 /* Now we fill them out.... */
11892 for (seclist
= &stdoutput
->sections
;
11893 seclist
&& *seclist
;
11894 seclist
= &(*seclist
)->next
)
11896 segment_info_type
*seginfo
;
11897 xtensa_block_info
*block
;
11898 segT sec
= *seclist
;
11900 seginfo
= seg_info (sec
);
11901 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11905 xtensa_block_info
*cur_block
;
11907 bfd_size_type rec_size
;
11909 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11912 rec_size
= num_recs
* 8;
11913 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11920 subseg_set (sec
, 0);
11921 frag_data
= frag_more (rec_size
);
11923 for (i
= 0; i
< num_recs
; i
++)
11927 /* Write the fixup. */
11928 gas_assert (cur_block
);
11929 fix
= fix_new (frag_now
, i
* 8, 4,
11930 section_symbol (cur_block
->sec
),
11932 FALSE
, BFD_RELOC_32
);
11933 fix
->fx_file
= "<internal>";
11936 /* Write the length. */
11937 md_number_to_chars (&frag_data
[4 + i
* 8],
11938 cur_block
->size
, 4);
11939 cur_block
= cur_block
->next
;
11941 frag_wane (frag_now
);
11943 frag_wane (frag_now
);
11951 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11952 const char *section_name_base
,
11953 xt_section_type sec_type
)
11957 /* Walk over all of the current segments.
11958 Walk over each fragment.
11959 For each fragment that has instructions,
11960 build an instruction record (append where possible). */
11962 for (seclist
= &stdoutput
->sections
;
11963 seclist
&& *seclist
;
11964 seclist
= &(*seclist
)->next
)
11966 segT sec
= *seclist
;
11968 if (exclude_section_from_property_tables (sec
))
11971 if (section_has_xproperty (sec
, flag_fn
))
11973 segment_info_type
*xt_seg_info
;
11974 xtensa_block_info
**xt_blocks
;
11975 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11977 prop_sec
->output_section
= prop_sec
;
11978 subseg_set (prop_sec
, 0);
11979 xt_seg_info
= seg_info (prop_sec
);
11980 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11982 /* Walk over all of the frchains here and add new sections. */
11983 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11987 /* Now we fill them out.... */
11989 for (seclist
= &stdoutput
->sections
;
11990 seclist
&& *seclist
;
11991 seclist
= &(*seclist
)->next
)
11993 segment_info_type
*seginfo
;
11994 xtensa_block_info
*block
;
11995 segT sec
= *seclist
;
11997 seginfo
= seg_info (sec
);
11998 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
12002 xtensa_block_info
*cur_block
;
12004 bfd_size_type rec_size
;
12006 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
12009 rec_size
= num_recs
* (8 + 4);
12010 bfd_set_section_size (stdoutput
, sec
, rec_size
);
12011 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
12018 subseg_set (sec
, 0);
12019 frag_data
= frag_more (rec_size
);
12021 for (i
= 0; i
< num_recs
; i
++)
12025 /* Write the fixup. */
12026 gas_assert (cur_block
);
12027 fix
= fix_new (frag_now
, i
* 12, 4,
12028 section_symbol (cur_block
->sec
),
12030 FALSE
, BFD_RELOC_32
);
12031 fix
->fx_file
= "<internal>";
12034 /* Write the length. */
12035 md_number_to_chars (&frag_data
[4 + i
* 12],
12036 cur_block
->size
, 4);
12037 md_number_to_chars (&frag_data
[8 + i
* 12],
12038 frag_flags_to_number (&cur_block
->flags
),
12039 sizeof (flagword
));
12040 cur_block
= cur_block
->next
;
12042 frag_wane (frag_now
);
12044 frag_wane (frag_now
);
12052 exclude_section_from_property_tables (segT sec
)
12054 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
12056 /* Sections that don't contribute to the memory footprint are excluded. */
12057 if ((flags
& SEC_DEBUGGING
)
12058 || !(flags
& SEC_ALLOC
)
12059 || (flags
& SEC_MERGE
))
12062 /* Linker cie and fde optimizations mess up property entries for
12063 eh_frame sections, but there is nothing inside them relevant to
12064 property tables anyway. */
12065 if (strcmp (sec
->name
, ".eh_frame") == 0)
12073 section_has_property (segT sec
, frag_predicate property_function
)
12075 segment_info_type
*seginfo
= seg_info (sec
);
12078 if (seginfo
&& seginfo
->frchainP
)
12080 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12082 if (property_function (fragP
)
12083 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12092 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
12094 segment_info_type
*seginfo
= seg_info (sec
);
12097 if (seginfo
&& seginfo
->frchainP
)
12099 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
12101 frag_flags prop_flags
;
12102 property_function (fragP
, &prop_flags
);
12103 if (!xtensa_frag_flags_is_empty (&prop_flags
))
12111 /* Two types of block sections exist right now: literal and insns. */
12114 add_xt_block_frags (segT sec
,
12115 xtensa_block_info
**xt_block
,
12116 frag_predicate property_function
,
12117 frag_predicate end_property_function
)
12121 /* Build it if needed. */
12122 while (*xt_block
!= NULL
)
12123 xt_block
= &(*xt_block
)->next
;
12124 /* We are either at NULL at the beginning or at the end. */
12126 /* Walk through the frags. */
12127 if (seg_info (sec
)->frchainP
)
12129 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
12131 fragP
= fragP
->fr_next
)
12133 if (property_function (fragP
)
12134 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
12136 if (*xt_block
!= NULL
)
12138 if ((*xt_block
)->offset
+ (*xt_block
)->size
12139 == fragP
->fr_address
)
12140 (*xt_block
)->size
+= fragP
->fr_fix
;
12142 xt_block
= &((*xt_block
)->next
);
12144 if (*xt_block
== NULL
)
12146 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
12147 new_block
->sec
= sec
;
12148 new_block
->offset
= fragP
->fr_address
;
12149 new_block
->size
= fragP
->fr_fix
;
12150 new_block
->next
= NULL
;
12151 xtensa_frag_flags_init (&new_block
->flags
);
12152 *xt_block
= new_block
;
12154 if (end_property_function
12155 && end_property_function (fragP
))
12157 xt_block
= &((*xt_block
)->next
);
12165 /* Break the encapsulation of add_xt_prop_frags here. */
12168 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
12170 if (prop_flags
->is_literal
12171 || prop_flags
->is_insn
12172 || prop_flags
->is_data
12173 || prop_flags
->is_unreachable
)
12180 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12182 memset (prop_flags
, 0, sizeof (frag_flags
));
12187 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12189 xtensa_frag_flags_init (prop_flags
);
12190 if (fragP
->tc_frag_data
.is_literal
)
12191 prop_flags
->is_literal
= TRUE
;
12192 if (fragP
->tc_frag_data
.is_specific_opcode
12193 || fragP
->tc_frag_data
.is_no_transform
)
12195 prop_flags
->is_no_transform
= TRUE
;
12196 if (xtensa_frag_flags_is_empty (prop_flags
))
12197 prop_flags
->is_data
= TRUE
;
12199 if (fragP
->tc_frag_data
.is_unreachable
)
12200 prop_flags
->is_unreachable
= TRUE
;
12201 else if (fragP
->tc_frag_data
.is_insn
)
12203 prop_flags
->is_insn
= TRUE
;
12204 if (fragP
->tc_frag_data
.is_loop_target
)
12205 prop_flags
->insn
.is_loop_target
= TRUE
;
12206 if (fragP
->tc_frag_data
.is_branch_target
)
12207 prop_flags
->insn
.is_branch_target
= TRUE
;
12208 if (fragP
->tc_frag_data
.is_no_density
)
12209 prop_flags
->insn
.is_no_density
= TRUE
;
12210 if (fragP
->tc_frag_data
.use_absolute_literals
)
12211 prop_flags
->insn
.is_abslit
= TRUE
;
12213 if (fragP
->tc_frag_data
.is_align
)
12215 prop_flags
->is_align
= TRUE
;
12216 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12217 if (xtensa_frag_flags_is_empty (prop_flags
))
12218 prop_flags
->is_data
= TRUE
;
12224 frag_flags_to_number (const frag_flags
*prop_flags
)
12227 if (prop_flags
->is_literal
)
12228 num
|= XTENSA_PROP_LITERAL
;
12229 if (prop_flags
->is_insn
)
12230 num
|= XTENSA_PROP_INSN
;
12231 if (prop_flags
->is_data
)
12232 num
|= XTENSA_PROP_DATA
;
12233 if (prop_flags
->is_unreachable
)
12234 num
|= XTENSA_PROP_UNREACHABLE
;
12235 if (prop_flags
->insn
.is_loop_target
)
12236 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12237 if (prop_flags
->insn
.is_branch_target
)
12239 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12240 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12243 if (prop_flags
->insn
.is_no_density
)
12244 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12245 if (prop_flags
->is_no_transform
)
12246 num
|= XTENSA_PROP_NO_TRANSFORM
;
12247 if (prop_flags
->insn
.is_no_reorder
)
12248 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12249 if (prop_flags
->insn
.is_abslit
)
12250 num
|= XTENSA_PROP_INSN_ABSLIT
;
12252 if (prop_flags
->is_align
)
12254 num
|= XTENSA_PROP_ALIGN
;
12255 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12263 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12264 const frag_flags
*prop_flags_2
)
12266 /* Cannot combine with an end marker. */
12268 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12270 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12272 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12275 if (prop_flags_1
->is_insn
)
12277 /* Properties of the beginning of the frag. */
12278 if (prop_flags_2
->insn
.is_loop_target
)
12280 if (prop_flags_2
->insn
.is_branch_target
)
12282 if (prop_flags_1
->insn
.is_no_density
!=
12283 prop_flags_2
->insn
.is_no_density
)
12285 if (prop_flags_1
->is_no_transform
!=
12286 prop_flags_2
->is_no_transform
)
12288 if (prop_flags_1
->insn
.is_no_reorder
!=
12289 prop_flags_2
->insn
.is_no_reorder
)
12291 if (prop_flags_1
->insn
.is_abslit
!=
12292 prop_flags_2
->insn
.is_abslit
)
12296 if (prop_flags_1
->is_align
)
12304 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12307 unsigned align_bits
;
12309 if (!xt_block
->flags
.is_align
)
12310 return xt_block
->size
;
12312 end_addr
= xt_block
->offset
+ xt_block
->size
;
12313 align_bits
= xt_block
->flags
.alignment
;
12314 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12315 return end_addr
- xt_block
->offset
;
12320 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12321 const xtensa_block_info
*xt_block_2
)
12323 if (xt_block
->sec
!= xt_block_2
->sec
)
12325 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12326 != xt_block_2
->offset
)
12329 if (xt_block_2
->size
== 0
12330 && (!xt_block_2
->flags
.is_unreachable
12331 || xt_block
->flags
.is_unreachable
))
12333 if (xt_block_2
->flags
.is_align
12334 && xt_block
->flags
.is_align
)
12336 /* Nothing needed. */
12337 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12342 if (xt_block_2
->flags
.is_align
)
12344 /* Push alignment to previous entry. */
12345 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12346 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12351 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12352 &xt_block_2
->flags
))
12355 xt_block
->size
+= xt_block_2
->size
;
12357 if (xt_block_2
->flags
.is_align
)
12359 xt_block
->flags
.is_align
= TRUE
;
12360 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12368 add_xt_prop_frags (segT sec
,
12369 xtensa_block_info
**xt_block
,
12370 frag_flags_fn property_function
)
12374 /* Build it if needed. */
12375 while (*xt_block
!= NULL
)
12377 xt_block
= &(*xt_block
)->next
;
12379 /* We are either at NULL at the beginning or at the end. */
12381 /* Walk through the frags. */
12382 if (seg_info (sec
)->frchainP
)
12384 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12385 fragP
= fragP
->fr_next
)
12387 xtensa_block_info tmp_block
;
12388 tmp_block
.sec
= sec
;
12389 tmp_block
.offset
= fragP
->fr_address
;
12390 tmp_block
.size
= fragP
->fr_fix
;
12391 tmp_block
.next
= NULL
;
12392 property_function (fragP
, &tmp_block
.flags
);
12394 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12395 /* && fragP->fr_fix != 0) */
12397 if ((*xt_block
) == NULL
12398 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12400 xtensa_block_info
*new_block
;
12401 if ((*xt_block
) != NULL
)
12402 xt_block
= &(*xt_block
)->next
;
12403 new_block
= XNEW (xtensa_block_info
);
12404 *new_block
= tmp_block
;
12405 *xt_block
= new_block
;
12413 /* op_placement_info_table */
12415 /* op_placement_info makes it easier to determine which
12416 ops can go in which slots. */
12419 init_op_placement_info_table (void)
12421 xtensa_isa isa
= xtensa_default_isa
;
12422 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12423 xtensa_opcode opcode
;
12426 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12428 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12429 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12431 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12433 op_placement_info
*opi
= &op_placement_table
[opcode
];
12434 /* FIXME: Make tinsn allocation dynamic. */
12435 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12436 as_fatal (_("too many operands in instruction"));
12437 opi
->narrowest
= XTENSA_UNDEFINED
;
12438 opi
->narrowest_size
= 0x7F;
12439 opi
->narrowest_slot
= 0;
12441 opi
->num_formats
= 0;
12443 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12445 opi
->slots
[fmt
] = 0;
12446 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12448 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12450 int fmt_length
= xtensa_format_length (isa
, fmt
);
12452 set_bit (fmt
, opi
->formats
);
12453 set_bit (slot
, opi
->slots
[fmt
]);
12454 if (fmt_length
< opi
->narrowest_size
12455 || (fmt_length
== opi
->narrowest_size
12456 && (xtensa_format_num_slots (isa
, fmt
)
12457 < xtensa_format_num_slots (isa
,
12460 opi
->narrowest
= fmt
;
12461 opi
->narrowest_size
= fmt_length
;
12462 opi
->narrowest_slot
= slot
;
12467 opi
->num_formats
++;
12470 xtensa_insnbuf_free (isa
, ibuf
);
12475 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12477 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12481 /* If the opcode is available in a single slot format, return its size. */
12484 xg_get_single_size (xtensa_opcode opcode
)
12486 return op_placement_table
[opcode
].narrowest_size
;
12490 static xtensa_format
12491 xg_get_single_format (xtensa_opcode opcode
)
12493 return op_placement_table
[opcode
].narrowest
;
12498 xg_get_single_slot (xtensa_opcode opcode
)
12500 return op_placement_table
[opcode
].narrowest_slot
;
12504 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12507 istack_init (IStack
*stack
)
12514 istack_empty (IStack
*stack
)
12516 return (stack
->ninsn
== 0);
12521 istack_full (IStack
*stack
)
12523 return (stack
->ninsn
== MAX_ISTACK
);
12527 /* Return a pointer to the top IStack entry.
12528 It is an error to call this if istack_empty () is TRUE. */
12531 istack_top (IStack
*stack
)
12533 int rec
= stack
->ninsn
- 1;
12534 gas_assert (!istack_empty (stack
));
12535 return &stack
->insn
[rec
];
12539 /* Add a new TInsn to an IStack.
12540 It is an error to call this if istack_full () is TRUE. */
12543 istack_push (IStack
*stack
, TInsn
*insn
)
12545 int rec
= stack
->ninsn
;
12546 gas_assert (!istack_full (stack
));
12547 stack
->insn
[rec
] = *insn
;
12552 /* Clear space for the next TInsn on the IStack and return a pointer
12553 to it. It is an error to call this if istack_full () is TRUE. */
12556 istack_push_space (IStack
*stack
)
12558 int rec
= stack
->ninsn
;
12560 gas_assert (!istack_full (stack
));
12561 insn
= &stack
->insn
[rec
];
12568 /* Remove the last pushed instruction. It is an error to call this if
12569 istack_empty () returns TRUE. */
12572 istack_pop (IStack
*stack
)
12574 int rec
= stack
->ninsn
- 1;
12575 gas_assert (!istack_empty (stack
));
12577 tinsn_init (&stack
->insn
[rec
]);
12581 /* TInsn functions. */
12584 tinsn_init (TInsn
*dst
)
12586 memset (dst
, 0, sizeof (TInsn
));
12590 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12593 tinsn_has_symbolic_operands (const TInsn
*insn
)
12596 int n
= insn
->ntok
;
12598 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12600 for (i
= 0; i
< n
; ++i
)
12602 switch (insn
->tok
[i
].X_op
)
12616 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12618 xtensa_isa isa
= xtensa_default_isa
;
12620 int n
= insn
->ntok
;
12622 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12624 for (i
= 0; i
< n
; ++i
)
12626 switch (insn
->tok
[i
].X_op
)
12634 /* Errors for these types are caught later. */
12639 /* Symbolic immediates are only allowed on the last immediate
12640 operand. At this time, CONST16 is the only opcode where we
12641 support non-PC-relative relocations. */
12642 if (i
!= get_relaxable_immed (insn
->opcode
)
12643 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12644 && insn
->opcode
!= xtensa_const16_opcode
))
12646 as_bad (_("invalid symbolic operand"));
12655 /* For assembly code with complex expressions (e.g. subtraction),
12656 we have to build them in the literal pool so that
12657 their results are calculated correctly after relaxation.
12658 The relaxation only handles expressions that
12659 boil down to SYMBOL + OFFSET. */
12662 tinsn_has_complex_operands (const TInsn
*insn
)
12665 int n
= insn
->ntok
;
12666 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12667 for (i
= 0; i
< n
; ++i
)
12669 switch (insn
->tok
[i
].X_op
)
12685 /* Encode a TInsn opcode and its constant operands into slotbuf.
12686 Return TRUE if there is a symbol in the immediate field. This
12687 function assumes that:
12688 1) The number of operands are correct.
12689 2) The insn_type is ITYPE_INSN.
12690 3) The opcode can be encoded in the specified format and slot.
12691 4) Operands are either O_constant or O_symbol, and all constants fit. */
12694 tinsn_to_slotbuf (xtensa_format fmt
,
12697 xtensa_insnbuf slotbuf
)
12699 xtensa_isa isa
= xtensa_default_isa
;
12700 xtensa_opcode opcode
= tinsn
->opcode
;
12701 bfd_boolean has_fixup
= FALSE
;
12702 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12705 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12706 if (noperands
!= tinsn
->ntok
)
12707 as_fatal (_("operand number mismatch"));
12709 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12711 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12712 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12716 for (i
= 0; i
< noperands
; i
++)
12718 expressionS
*exp
= &tinsn
->tok
[i
];
12721 const char *file_name
;
12727 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12729 /* The register number has already been checked in
12730 expression_maybe_register, so we don't need to check here. */
12731 opnd_value
= exp
->X_add_number
;
12732 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12733 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12736 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12740 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12742 file_name
= as_where (&line
);
12743 /* It is a constant and we called this function
12744 then we have to try to fit it. */
12745 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12746 exp
->X_add_number
, file_name
, line
);
12759 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12760 into a multi-slot instruction, fill the other slots with NOPs.
12761 Return TRUE if there is a symbol in the immediate field. See also the
12762 assumptions listed for tinsn_to_slotbuf. */
12765 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12767 static xtensa_insnbuf slotbuf
= 0;
12768 static vliw_insn vinsn
;
12769 xtensa_isa isa
= xtensa_default_isa
;
12770 bfd_boolean has_fixup
= FALSE
;
12775 slotbuf
= xtensa_insnbuf_alloc (isa
);
12776 xg_init_vinsn (&vinsn
);
12779 xg_clear_vinsn (&vinsn
);
12781 bundle_tinsn (tinsn
, &vinsn
);
12783 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12785 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12787 /* Only one slot may have a fix-up because the rest contains NOPs. */
12789 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12790 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12797 /* Check the instruction arguments. Return TRUE on failure. */
12800 tinsn_check_arguments (const TInsn
*insn
)
12802 xtensa_isa isa
= xtensa_default_isa
;
12803 xtensa_opcode opcode
= insn
->opcode
;
12804 xtensa_regfile t1_regfile
, t2_regfile
;
12805 int t1_reg
, t2_reg
;
12806 int t1_base_reg
, t1_last_reg
;
12807 int t2_base_reg
, t2_last_reg
;
12808 char t1_inout
, t2_inout
;
12811 if (opcode
== XTENSA_UNDEFINED
)
12813 as_bad (_("invalid opcode"));
12817 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12819 as_bad (_("too few operands"));
12823 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12825 as_bad (_("too many operands"));
12829 /* Check registers. */
12830 for (j
= 0; j
< insn
->ntok
; j
++)
12832 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12835 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12836 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12838 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12840 for (i
= 0; i
< insn
->ntok
; i
++)
12845 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12848 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12850 if (t1_regfile
!= t2_regfile
)
12853 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12854 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12856 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12857 t1_last_reg
= (t1_base_reg
12858 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12860 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12862 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12864 if (t1_reg
!= t2_reg
)
12867 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12869 as_bad (_("multiple writes to the same register"));
12880 /* Load an instruction from its encoded form. */
12883 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12887 xg_init_vinsn (&vinsn
);
12888 vinsn_from_chars (&vinsn
, f
);
12890 *tinsn
= vinsn
.slots
[slot
];
12891 xg_free_vinsn (&vinsn
);
12896 tinsn_from_insnbuf (TInsn
*tinsn
,
12897 xtensa_insnbuf slotbuf
,
12902 xtensa_isa isa
= xtensa_default_isa
;
12904 /* Find the immed. */
12905 tinsn_init (tinsn
);
12906 tinsn
->insn_type
= ITYPE_INSN
;
12907 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12908 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12909 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12910 for (i
= 0; i
< tinsn
->ntok
; i
++)
12912 set_expr_const (&tinsn
->tok
[i
],
12913 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12914 tinsn
->opcode
, i
));
12919 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12922 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12924 xtensa_opcode opcode
= tinsn
->opcode
;
12927 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12929 opnum
= get_relaxable_immed (opcode
);
12930 gas_assert (opnum
>= 0);
12931 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12932 fragP
->tc_frag_data
.slot_symbols
[slot
],
12933 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12935 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12940 get_num_stack_text_bytes (IStack
*istack
)
12943 int text_bytes
= 0;
12945 for (i
= 0; i
< istack
->ninsn
; i
++)
12947 TInsn
*tinsn
= &istack
->insn
[i
];
12948 if (tinsn
->insn_type
== ITYPE_INSN
)
12949 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12956 get_num_stack_literal_bytes (IStack
*istack
)
12961 for (i
= 0; i
< istack
->ninsn
; i
++)
12963 TInsn
*tinsn
= &istack
->insn
[i
];
12964 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12971 /* vliw_insn functions. */
12974 xg_init_vinsn (vliw_insn
*v
)
12977 xtensa_isa isa
= xtensa_default_isa
;
12979 xg_clear_vinsn (v
);
12981 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12982 if (v
->insnbuf
== NULL
)
12983 as_fatal (_("out of memory"));
12985 for (i
= 0; i
< config_max_slots
; i
++)
12987 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12988 if (v
->slotbuf
[i
] == NULL
)
12989 as_fatal (_("out of memory"));
12995 xg_clear_vinsn (vliw_insn
*v
)
12999 memset (v
, 0, offsetof (vliw_insn
, slots
)
13000 + sizeof(TInsn
) * config_max_slots
);
13002 v
->format
= XTENSA_UNDEFINED
;
13004 v
->inside_bundle
= FALSE
;
13006 if (xt_saved_debug_type
!= DEBUG_NONE
)
13007 debug_type
= xt_saved_debug_type
;
13009 for (i
= 0; i
< config_max_slots
; i
++)
13010 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
13015 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
13018 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
13019 dst
->insnbuf
= src
->insnbuf
;
13020 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
13025 vinsn_has_specific_opcodes (vliw_insn
*v
)
13029 for (i
= 0; i
< v
->num_slots
; i
++)
13031 if (v
->slots
[i
].is_specific_opcode
)
13039 xg_free_vinsn (vliw_insn
*v
)
13042 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
13043 for (i
= 0; i
< config_max_slots
; i
++)
13044 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
13048 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
13049 operands. See also the assumptions listed for tinsn_to_slotbuf. */
13052 vinsn_to_insnbuf (vliw_insn
*vinsn
,
13055 bfd_boolean record_fixup
)
13057 xtensa_isa isa
= xtensa_default_isa
;
13058 xtensa_format fmt
= vinsn
->format
;
13059 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
13061 bfd_boolean has_fixup
= FALSE
;
13063 xtensa_format_encode (isa
, fmt
, insnbuf
);
13065 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
13067 TInsn
*tinsn
= &vinsn
->slots
[slot
];
13068 expressionS
*extra_arg
= &tinsn
->extra_arg
;
13069 bfd_boolean tinsn_has_fixup
=
13070 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
13071 vinsn
->slotbuf
[slot
]);
13073 xtensa_format_set_slot (isa
, fmt
, slot
,
13074 insnbuf
, vinsn
->slotbuf
[slot
]);
13075 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
13077 if (vinsn
->num_slots
!= 1)
13078 as_bad (_("TLS relocation not allowed in FLIX bundle"));
13079 else if (record_fixup
)
13080 /* Instructions that generate TLS relocations should always be
13081 relaxed in the front-end. If "record_fixup" is set, then this
13082 function is being called during back-end relaxation, so flag
13083 the unexpected behavior as an error. */
13084 as_bad (_("unexpected TLS relocation"));
13086 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
13087 xtensa_format_length (isa
, fmt
),
13088 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
13089 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
13091 if (tinsn_has_fixup
)
13094 xtensa_opcode opcode
= tinsn
->opcode
;
13095 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
13098 for (i
= 0; i
< noperands
; i
++)
13100 expressionS
* exp
= &tinsn
->tok
[i
];
13106 if (get_relaxable_immed (opcode
) == i
)
13108 /* Add a fix record for the instruction, except if this
13109 function is being called prior to relaxation, i.e.,
13110 if record_fixup is false, and the instruction might
13111 be relaxed later. */
13113 || tinsn
->is_specific_opcode
13114 || !xg_is_relaxable_insn (tinsn
, 0))
13116 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
13117 frag_offset
- fragP
->fr_literal
);
13121 if (exp
->X_op
!= O_symbol
)
13122 as_bad (_("invalid operand"));
13123 tinsn
->symbol
= exp
->X_add_symbol
;
13124 tinsn
->offset
= exp
->X_add_number
;
13128 as_bad (_("symbolic operand not allowed"));
13136 as_bad (_("expression too complex"));
13148 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
13150 static xtensa_insnbuf insnbuf
= NULL
;
13151 static xtensa_insnbuf slotbuf
= NULL
;
13154 xtensa_isa isa
= xtensa_default_isa
;
13158 insnbuf
= xtensa_insnbuf_alloc (isa
);
13159 slotbuf
= xtensa_insnbuf_alloc (isa
);
13162 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
13163 fmt
= xtensa_format_decode (isa
, insnbuf
);
13164 if (fmt
== XTENSA_UNDEFINED
)
13165 as_fatal (_("cannot decode instruction format"));
13166 vinsn
->format
= fmt
;
13167 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
13169 for (i
= 0; i
< vinsn
->num_slots
; i
++)
13171 TInsn
*tinsn
= &vinsn
->slots
[i
];
13172 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13173 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13178 /* Expression utilities. */
13180 /* Return TRUE if the expression is an integer constant. */
13183 expr_is_const (const expressionS
*s
)
13185 return (s
->X_op
== O_constant
);
13189 /* Get the expression constant.
13190 Calling this is illegal if expr_is_const () returns TRUE. */
13193 get_expr_const (const expressionS
*s
)
13195 gas_assert (expr_is_const (s
));
13196 return s
->X_add_number
;
13200 /* Set the expression to a constant value. */
13203 set_expr_const (expressionS
*s
, offsetT val
)
13205 s
->X_op
= O_constant
;
13206 s
->X_add_number
= val
;
13207 s
->X_add_symbol
= NULL
;
13208 s
->X_op_symbol
= NULL
;
13213 expr_is_register (const expressionS
*s
)
13215 return (s
->X_op
== O_register
);
13219 /* Get the expression constant.
13220 Calling this is illegal if expr_is_const () returns TRUE. */
13223 get_expr_register (const expressionS
*s
)
13225 gas_assert (expr_is_register (s
));
13226 return s
->X_add_number
;
13230 /* Set the expression to a symbol + constant offset. */
13233 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13235 s
->X_op
= O_symbol
;
13236 s
->X_add_symbol
= sym
;
13237 s
->X_op_symbol
= NULL
; /* unused */
13238 s
->X_add_number
= offset
;
13242 /* Return TRUE if the two expressions are equal. */
13245 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13247 if (s1
->X_op
!= s2
->X_op
)
13249 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13251 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13253 if (s1
->X_add_number
!= s2
->X_add_number
)
13260 copy_expr (expressionS
*dst
, const expressionS
*src
)
13262 memcpy (dst
, src
, sizeof (expressionS
));
13266 /* Support for the "--rename-section" option. */
13268 struct rename_section_struct
13270 const char *old_name
;
13272 struct rename_section_struct
*next
;
13275 static struct rename_section_struct
*section_rename
;
13278 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13279 entries to the section_rename list. Note: Specifying multiple
13280 renamings separated by colons is not documented and is retained only
13281 for backward compatibility. */
13284 build_section_rename (const char *arg
)
13286 struct rename_section_struct
*r
;
13287 char *this_arg
= NULL
;
13288 char *next_arg
= NULL
;
13290 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13292 char *old_name
, *new_name
;
13296 next_arg
= strchr (this_arg
, ':');
13304 old_name
= this_arg
;
13305 new_name
= strchr (this_arg
, '=');
13307 if (*old_name
== '\0')
13309 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13312 if (!new_name
|| new_name
[1] == '\0')
13314 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13321 /* Check for invalid section renaming. */
13322 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13324 if (strcmp (r
->old_name
, old_name
) == 0)
13325 as_bad (_("section %s renamed multiple times"), old_name
);
13326 if (strcmp (r
->new_name
, new_name
) == 0)
13327 as_bad (_("multiple sections remapped to output section %s"),
13332 r
= XNEW (struct rename_section_struct
);
13333 r
->old_name
= xstrdup (old_name
);
13334 r
->new_name
= xstrdup (new_name
);
13335 r
->next
= section_rename
;
13336 section_rename
= r
;
13342 xtensa_section_rename (const char *name
)
13344 struct rename_section_struct
*r
= section_rename
;
13346 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13348 if (strcmp (r
->old_name
, name
) == 0)
13349 return r
->new_name
;
13352 return (char *) name
;