1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_num_pipe_stages
;
80 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg
;
121 static lit_state default_lit_sections
;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct
*next
;
150 static sym_list
*insn_labels
= NULL
;
151 static sym_list
*free_insn_labels
= NULL
;
152 static sym_list
*saved_insn_labels
= NULL
;
154 static sym_list
*literal_syms
;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16
= 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals
= 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
266 /* is_specific_opcode implies no_transform. */
267 unsigned is_no_transform
: 1;
271 unsigned is_loop_target
: 1;
272 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority
: 2;
275 unsigned is_no_density
: 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
278 unsigned is_no_reorder
: 1;
280 /* Uses absolute literal addressing for l32r. */
281 unsigned is_abslit
: 1;
283 unsigned is_align
: 1;
284 unsigned alignment
: 5;
288 /* Structure for saving information about a block of property data
289 for frags that have the same flags. */
290 struct xtensa_block_info_struct
296 struct xtensa_block_info_struct
*next
;
300 /* Structure for saving the current state before emitting literals. */
301 typedef struct emit_state_struct
306 int generating_literals
;
310 /* Opcode placement information */
312 typedef unsigned long long bitfield
;
313 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
314 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
315 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317 #define MAX_FORMATS 32
319 typedef struct op_placement_info_struct
322 /* A number describing how restrictive the issue is for this
323 opcode. For example, an opcode that fits lots of different
324 formats has a high freedom, as does an opcode that fits
325 only one format but many slots in that format. The most
326 restrictive is the opcode that fits only one slot in one
329 xtensa_format narrowest
;
333 /* formats is a bitfield with the Nth bit set
334 if the opcode fits in the Nth xtensa_format. */
337 /* slots[N]'s Mth bit is set if the op fits in the
338 Mth slot of the Nth xtensa_format. */
339 bitfield slots
[MAX_FORMATS
];
341 /* A count of the number of slots in a given format
342 an op can fit (i.e., the bitcount of the slot field above). */
343 char slots_in_format
[MAX_FORMATS
];
345 } op_placement_info
, *op_placement_info_table
;
347 op_placement_info_table op_placement_table
;
350 /* Extra expression types. */
352 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
353 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
354 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 #define O_pcrel O_md4 /* value is a PC-relative offset */
356 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
357 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
358 #define O_tlscall O_md7 /* TLS_CALL relocation */
359 #define O_tpoff O_md8 /* TPOFF relocation */
360 #define O_dtpoff O_md9 /* DTPOFF relocation */
362 struct suffix_reloc_map
366 bfd_reloc_code_real_type reloc
;
367 unsigned char operator;
370 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
372 static struct suffix_reloc_map suffix_relocs
[] =
374 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
375 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
376 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
377 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
378 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
379 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
380 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
381 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
382 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
383 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
397 directive_literal_prefix
,
399 directive_absolute_literals
,
400 directive_last_directive
406 bfd_boolean can_be_negated
;
409 const directive_infoS directive_info
[] =
412 { "literal", FALSE
},
414 { "transform", TRUE
},
415 { "freeregs", FALSE
},
416 { "longcalls", TRUE
},
417 { "literal_prefix", FALSE
},
418 { "schedule", TRUE
},
419 { "absolute-literals", TRUE
}
422 bfd_boolean directive_state
[] =
426 #if !XCHAL_HAVE_DENSITY
431 TRUE
, /* transform */
432 FALSE
, /* freeregs */
433 FALSE
, /* longcalls */
434 FALSE
, /* literal_prefix */
435 FALSE
, /* schedule */
436 #if XSHAL_USE_ABSOLUTE_LITERALS
437 TRUE
/* absolute_literals */
439 FALSE
/* absolute_literals */
444 /* Directive functions. */
446 static void xtensa_begin_directive (int);
447 static void xtensa_end_directive (int);
448 static void xtensa_literal_prefix (void);
449 static void xtensa_literal_position (int);
450 static void xtensa_literal_pseudo (int);
451 static void xtensa_frequency_pseudo (int);
452 static void xtensa_elf_cons (int);
453 static void xtensa_leb128 (int);
455 /* Parsing and Idiom Translation. */
457 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
459 /* Various Other Internal Functions. */
461 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
462 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
463 static void xtensa_mark_literal_pool_location (void);
464 static addressT
get_expanded_loop_offset (xtensa_opcode
);
465 static fragS
*get_literal_pool_location (segT
);
466 static void set_literal_pool_location (segT
, fragS
*);
467 static void xtensa_set_frag_assembly_state (fragS
*);
468 static void finish_vinsn (vliw_insn
*);
469 static bfd_boolean
emit_single_op (TInsn
*);
470 static int total_frag_text_expansion (fragS
*);
471 static bfd_boolean use_trampolines
= TRUE
;
472 static void xtensa_check_frag_count (void);
473 static void xtensa_create_trampoline_frag (bfd_boolean
);
474 static void xtensa_maybe_create_trampoline_frag (void);
475 struct trampoline_frag
;
476 static int init_trampoline_frag (struct trampoline_frag
*);
478 /* Alignment Functions. */
480 static int get_text_align_power (unsigned);
481 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
482 static int branch_align_power (segT
);
484 /* Helpers for xtensa_relax_frag(). */
486 static long relax_frag_add_nop (fragS
*);
488 /* Accessors for additional per-subsegment information. */
490 static unsigned get_last_insn_flags (segT
, subsegT
);
491 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
492 static float get_subseg_total_freq (segT
, subsegT
);
493 static float get_subseg_target_freq (segT
, subsegT
);
494 static void set_subseg_freq (segT
, subsegT
, float, float);
496 /* Segment list functions. */
498 static void xtensa_move_literals (void);
499 static void xtensa_reorder_segments (void);
500 static void xtensa_switch_to_literal_fragment (emit_state
*);
501 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
502 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
503 static void xtensa_restore_emit_state (emit_state
*);
504 static segT
cache_literal_section (bfd_boolean
);
506 /* Import from elf32-xtensa.c in BFD library. */
508 extern asection
*xtensa_make_property_section (asection
*, const char *);
510 /* op_placement_info functions. */
512 static void init_op_placement_info_table (void);
513 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
514 static int xg_get_single_size (xtensa_opcode
);
515 static xtensa_format
xg_get_single_format (xtensa_opcode
);
516 static int xg_get_single_slot (xtensa_opcode
);
518 /* TInsn and IStack functions. */
520 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
521 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
522 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
523 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
524 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
525 static void tinsn_from_chars (TInsn
*, char *, int);
526 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
527 static int get_num_stack_text_bytes (IStack
*);
528 static int get_num_stack_literal_bytes (IStack
*);
529 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
531 /* vliw_insn functions. */
533 static void xg_init_vinsn (vliw_insn
*);
534 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
535 static void xg_clear_vinsn (vliw_insn
*);
536 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
537 static void xg_free_vinsn (vliw_insn
*);
538 static bfd_boolean vinsn_to_insnbuf
539 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
540 static void vinsn_from_chars (vliw_insn
*, char *);
542 /* Expression Utilities. */
544 bfd_boolean
expr_is_const (const expressionS
*);
545 offsetT
get_expr_const (const expressionS
*);
546 void set_expr_const (expressionS
*, offsetT
);
547 bfd_boolean
expr_is_register (const expressionS
*);
548 offsetT
get_expr_register (const expressionS
*);
549 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
550 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
551 static void copy_expr (expressionS
*, const expressionS
*);
553 /* Section renaming. */
555 static void build_section_rename (const char *);
558 /* ISA imported from bfd. */
559 extern xtensa_isa xtensa_default_isa
;
561 extern int target_big_endian
;
563 static xtensa_opcode xtensa_addi_opcode
;
564 static xtensa_opcode xtensa_addmi_opcode
;
565 static xtensa_opcode xtensa_call0_opcode
;
566 static xtensa_opcode xtensa_call4_opcode
;
567 static xtensa_opcode xtensa_call8_opcode
;
568 static xtensa_opcode xtensa_call12_opcode
;
569 static xtensa_opcode xtensa_callx0_opcode
;
570 static xtensa_opcode xtensa_callx4_opcode
;
571 static xtensa_opcode xtensa_callx8_opcode
;
572 static xtensa_opcode xtensa_callx12_opcode
;
573 static xtensa_opcode xtensa_const16_opcode
;
574 static xtensa_opcode xtensa_entry_opcode
;
575 static xtensa_opcode xtensa_extui_opcode
;
576 static xtensa_opcode xtensa_movi_opcode
;
577 static xtensa_opcode xtensa_movi_n_opcode
;
578 static xtensa_opcode xtensa_isync_opcode
;
579 static xtensa_opcode xtensa_j_opcode
;
580 static xtensa_opcode xtensa_jx_opcode
;
581 static xtensa_opcode xtensa_l32r_opcode
;
582 static xtensa_opcode xtensa_loop_opcode
;
583 static xtensa_opcode xtensa_loopnez_opcode
;
584 static xtensa_opcode xtensa_loopgtz_opcode
;
585 static xtensa_opcode xtensa_nop_opcode
;
586 static xtensa_opcode xtensa_nop_n_opcode
;
587 static xtensa_opcode xtensa_or_opcode
;
588 static xtensa_opcode xtensa_ret_opcode
;
589 static xtensa_opcode xtensa_ret_n_opcode
;
590 static xtensa_opcode xtensa_retw_opcode
;
591 static xtensa_opcode xtensa_retw_n_opcode
;
592 static xtensa_opcode xtensa_rsr_lcount_opcode
;
593 static xtensa_opcode xtensa_waiti_opcode
;
594 static int config_max_slots
= 0;
597 /* Command-line Options. */
599 bfd_boolean use_literal_section
= TRUE
;
600 enum flix_level produce_flix
= FLIX_ALL
;
601 static bfd_boolean align_targets
= TRUE
;
602 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
603 static bfd_boolean has_a0_b_retw
= FALSE
;
604 static bfd_boolean workaround_a0_b_retw
= FALSE
;
605 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
606 static bfd_boolean workaround_short_loop
= FALSE
;
607 static bfd_boolean maybe_has_short_loop
= FALSE
;
608 static bfd_boolean workaround_close_loop_end
= FALSE
;
609 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
610 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
612 /* When workaround_short_loops is TRUE, all loops with early exits must
613 have at least 3 instructions. workaround_all_short_loops is a modifier
614 to the workaround_short_loop flag. In addition to the
615 workaround_short_loop actions, all straightline loopgtz and loopnez
616 must have at least 3 instructions. */
618 static bfd_boolean workaround_all_short_loops
= FALSE
;
622 xtensa_setup_hw_workarounds (int earliest
, int latest
)
624 if (earliest
> latest
)
625 as_fatal (_("illegal range of target hardware versions"));
627 /* Enable all workarounds for pre-T1050.0 hardware. */
628 if (earliest
< 105000 || latest
< 105000)
630 workaround_a0_b_retw
|= TRUE
;
631 workaround_b_j_loop_end
|= TRUE
;
632 workaround_short_loop
|= TRUE
;
633 workaround_close_loop_end
|= TRUE
;
634 workaround_all_short_loops
|= TRUE
;
635 enforce_three_byte_loop_align
= TRUE
;
642 option_density
= OPTION_MD_BASE
,
646 option_no_generate_flix
,
653 option_no_link_relax
,
661 option_text_section_literals
,
662 option_no_text_section_literals
,
664 option_absolute_literals
,
665 option_no_absolute_literals
,
667 option_align_targets
,
668 option_no_align_targets
,
670 option_warn_unaligned_targets
,
675 option_workaround_a0_b_retw
,
676 option_no_workaround_a0_b_retw
,
678 option_workaround_b_j_loop_end
,
679 option_no_workaround_b_j_loop_end
,
681 option_workaround_short_loop
,
682 option_no_workaround_short_loop
,
684 option_workaround_all_short_loops
,
685 option_no_workaround_all_short_loops
,
687 option_workaround_close_loop_end
,
688 option_no_workaround_close_loop_end
,
690 option_no_workarounds
,
692 option_rename_section_name
,
695 option_prefer_const16
,
697 option_target_hardware
,
700 option_no_trampolines
,
703 const char *md_shortopts
= "";
705 struct option md_longopts
[] =
707 { "density", no_argument
, NULL
, option_density
},
708 { "no-density", no_argument
, NULL
, option_no_density
},
710 { "flix", no_argument
, NULL
, option_flix
},
711 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
712 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
714 /* Both "relax" and "generics" are deprecated and treated as equivalent
715 to the "transform" option. */
716 { "relax", no_argument
, NULL
, option_relax
},
717 { "no-relax", no_argument
, NULL
, option_no_relax
},
718 { "generics", no_argument
, NULL
, option_generics
},
719 { "no-generics", no_argument
, NULL
, option_no_generics
},
721 { "transform", no_argument
, NULL
, option_transform
},
722 { "no-transform", no_argument
, NULL
, option_no_transform
},
723 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
724 { "no-text-section-literals", no_argument
, NULL
,
725 option_no_text_section_literals
},
726 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
727 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
728 /* This option was changed from -align-target to -target-align
729 because it conflicted with the "-al" option. */
730 { "target-align", no_argument
, NULL
, option_align_targets
},
731 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
732 { "warn-unaligned-targets", no_argument
, NULL
,
733 option_warn_unaligned_targets
},
734 { "longcalls", no_argument
, NULL
, option_longcalls
},
735 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
737 { "no-workaround-a0-b-retw", no_argument
, NULL
,
738 option_no_workaround_a0_b_retw
},
739 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
741 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
742 option_no_workaround_b_j_loop_end
},
743 { "workaround-b-j-loop-end", no_argument
, NULL
,
744 option_workaround_b_j_loop_end
},
746 { "no-workaround-short-loops", no_argument
, NULL
,
747 option_no_workaround_short_loop
},
748 { "workaround-short-loops", no_argument
, NULL
,
749 option_workaround_short_loop
},
751 { "no-workaround-all-short-loops", no_argument
, NULL
,
752 option_no_workaround_all_short_loops
},
753 { "workaround-all-short-loop", no_argument
, NULL
,
754 option_workaround_all_short_loops
},
756 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
757 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
759 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
761 { "no-workaround-close-loop-end", no_argument
, NULL
,
762 option_no_workaround_close_loop_end
},
763 { "workaround-close-loop-end", no_argument
, NULL
,
764 option_workaround_close_loop_end
},
766 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
768 { "link-relax", no_argument
, NULL
, option_link_relax
},
769 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
771 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
773 { "trampolines", no_argument
, NULL
, option_trampolines
},
774 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
776 { NULL
, no_argument
, NULL
, 0 }
779 size_t md_longopts_size
= sizeof md_longopts
;
783 md_parse_option (int c
, char *arg
)
788 as_warn (_("--density option is ignored"));
790 case option_no_density
:
791 as_warn (_("--no-density option is ignored"));
793 case option_link_relax
:
796 case option_no_link_relax
:
800 produce_flix
= FLIX_ALL
;
802 case option_no_generate_flix
:
803 produce_flix
= FLIX_NO_GENERATE
;
806 produce_flix
= FLIX_NONE
;
808 case option_generics
:
809 as_warn (_("--generics is deprecated; use --transform instead"));
810 return md_parse_option (option_transform
, arg
);
811 case option_no_generics
:
812 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
813 return md_parse_option (option_no_transform
, arg
);
815 as_warn (_("--relax is deprecated; use --transform instead"));
816 return md_parse_option (option_transform
, arg
);
817 case option_no_relax
:
818 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
819 return md_parse_option (option_no_transform
, arg
);
820 case option_longcalls
:
821 directive_state
[directive_longcalls
] = TRUE
;
823 case option_no_longcalls
:
824 directive_state
[directive_longcalls
] = FALSE
;
826 case option_text_section_literals
:
827 use_literal_section
= FALSE
;
829 case option_no_text_section_literals
:
830 use_literal_section
= TRUE
;
832 case option_absolute_literals
:
833 if (!absolute_literals_supported
)
835 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
838 directive_state
[directive_absolute_literals
] = TRUE
;
840 case option_no_absolute_literals
:
841 directive_state
[directive_absolute_literals
] = FALSE
;
844 case option_workaround_a0_b_retw
:
845 workaround_a0_b_retw
= TRUE
;
847 case option_no_workaround_a0_b_retw
:
848 workaround_a0_b_retw
= FALSE
;
850 case option_workaround_b_j_loop_end
:
851 workaround_b_j_loop_end
= TRUE
;
853 case option_no_workaround_b_j_loop_end
:
854 workaround_b_j_loop_end
= FALSE
;
857 case option_workaround_short_loop
:
858 workaround_short_loop
= TRUE
;
860 case option_no_workaround_short_loop
:
861 workaround_short_loop
= FALSE
;
864 case option_workaround_all_short_loops
:
865 workaround_all_short_loops
= TRUE
;
867 case option_no_workaround_all_short_loops
:
868 workaround_all_short_loops
= FALSE
;
871 case option_workaround_close_loop_end
:
872 workaround_close_loop_end
= TRUE
;
874 case option_no_workaround_close_loop_end
:
875 workaround_close_loop_end
= FALSE
;
878 case option_no_workarounds
:
879 workaround_a0_b_retw
= FALSE
;
880 workaround_b_j_loop_end
= FALSE
;
881 workaround_short_loop
= FALSE
;
882 workaround_all_short_loops
= FALSE
;
883 workaround_close_loop_end
= FALSE
;
886 case option_align_targets
:
887 align_targets
= TRUE
;
889 case option_no_align_targets
:
890 align_targets
= FALSE
;
893 case option_warn_unaligned_targets
:
894 warn_unaligned_branch_targets
= TRUE
;
897 case option_rename_section_name
:
898 build_section_rename (arg
);
902 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
903 should be emitted or not. FIXME: Not implemented. */
906 case option_prefer_l32r
:
908 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
912 case option_prefer_const16
:
914 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
918 case option_target_hardware
:
920 int earliest
, latest
= 0;
921 if (*arg
== 0 || *arg
== '-')
922 as_fatal (_("invalid target hardware version"));
924 earliest
= strtol (arg
, &arg
, 0);
928 else if (*arg
== '-')
931 as_fatal (_("invalid target hardware version"));
932 latest
= strtol (arg
, &arg
, 0);
935 as_fatal (_("invalid target hardware version"));
937 xtensa_setup_hw_workarounds (earliest
, latest
);
941 case option_transform
:
942 /* This option has no affect other than to use the defaults,
943 which are already set. */
946 case option_no_transform
:
947 /* This option turns off all transformations of any kind.
948 However, because we want to preserve the state of other
949 directives, we only change its own field. Thus, before
950 you perform any transformation, always check if transform
951 is available. If you use the functions we provide for this
952 purpose, you will be ok. */
953 directive_state
[directive_transform
] = FALSE
;
956 case option_trampolines
:
957 use_trampolines
= TRUE
;
960 case option_no_trampolines
:
961 use_trampolines
= FALSE
;
971 md_show_usage (FILE *stream
)
975 --[no-]text-section-literals\n\
976 [Do not] put literals in the text section\n\
977 --[no-]absolute-literals\n\
978 [Do not] default to use non-PC-relative literals\n\
979 --[no-]target-align [Do not] try to align branch targets\n\
980 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
981 --[no-]transform [Do not] transform instructions\n\
982 --flix both allow hand-written and generate flix bundles\n\
983 --no-generate-flix allow hand-written but do not generate\n\
985 --no-allow-flix neither allow hand-written nor generate\n\
987 --rename-section old=new Rename section 'old' to 'new'\n\
988 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
989 when jumps do not reach their targets\n", stream
);
993 /* Functions related to the list of current label symbols. */
996 xtensa_add_insn_label (symbolS
*sym
)
1000 if (!free_insn_labels
)
1001 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
1004 l
= free_insn_labels
;
1005 free_insn_labels
= l
->next
;
1009 l
->next
= insn_labels
;
1015 xtensa_clear_insn_labels (void)
1019 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1027 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1031 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1033 symbolS
*lit_sym
= lit
->sym
;
1034 S_SET_VALUE (lit_sym
, new_offset
);
1035 symbol_set_frag (lit_sym
, new_frag
);
1040 /* Directive data and functions. */
1042 typedef struct state_stackS_struct
1044 directiveE directive
;
1045 bfd_boolean negated
;
1046 bfd_boolean old_state
;
1050 struct state_stackS_struct
*prev
;
1053 state_stackS
*directive_state_stack
;
1055 const pseudo_typeS md_pseudo_table
[] =
1057 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1058 { "literal_position", xtensa_literal_position
, 0 },
1059 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1060 { "long", xtensa_elf_cons
, 4 },
1061 { "word", xtensa_elf_cons
, 4 },
1062 { "4byte", xtensa_elf_cons
, 4 },
1063 { "short", xtensa_elf_cons
, 2 },
1064 { "2byte", xtensa_elf_cons
, 2 },
1065 { "sleb128", xtensa_leb128
, 1},
1066 { "uleb128", xtensa_leb128
, 0},
1067 { "begin", xtensa_begin_directive
, 0 },
1068 { "end", xtensa_end_directive
, 0 },
1069 { "literal", xtensa_literal_pseudo
, 0 },
1070 { "frequency", xtensa_frequency_pseudo
, 0 },
1076 use_transform (void)
1078 /* After md_end, you should be checking frag by frag, rather
1079 than state directives. */
1080 gas_assert (!past_xtensa_end
);
1081 return directive_state
[directive_transform
];
1086 do_align_targets (void)
1088 /* Do not use this function after md_end; just look at align_targets
1089 instead. There is no target-align directive, so alignment is either
1090 enabled for all frags or not done at all. */
1091 gas_assert (!past_xtensa_end
);
1092 return align_targets
&& use_transform ();
1097 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1101 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1103 as_where (&file
, &line
);
1105 stack
->directive
= directive
;
1106 stack
->negated
= negated
;
1107 stack
->old_state
= directive_state
[directive
];
1110 stack
->datum
= datum
;
1111 stack
->prev
= directive_state_stack
;
1112 directive_state_stack
= stack
;
1114 directive_state
[directive
] = !negated
;
1119 directive_pop (directiveE
*directive
,
1120 bfd_boolean
*negated
,
1125 state_stackS
*top
= directive_state_stack
;
1127 if (!directive_state_stack
)
1129 as_bad (_("unmatched end directive"));
1130 *directive
= directive_none
;
1134 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1135 *directive
= top
->directive
;
1136 *negated
= top
->negated
;
1139 *datum
= top
->datum
;
1140 directive_state_stack
= top
->prev
;
1146 directive_balance (void)
1148 while (directive_state_stack
)
1150 directiveE directive
;
1151 bfd_boolean negated
;
1156 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1157 as_warn_where ((char *) file
, line
,
1158 _(".begin directive with no matching .end directive"));
1164 inside_directive (directiveE dir
)
1166 state_stackS
*top
= directive_state_stack
;
1168 while (top
&& top
->directive
!= dir
)
1171 return (top
!= NULL
);
1176 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1180 char *directive_string
;
1182 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1187 input_line_pointer
+= 3;
1190 len
= strspn (input_line_pointer
,
1191 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1193 /* This code is a hack to make .begin [no-][generics|relax] exactly
1194 equivalent to .begin [no-]transform. We should remove it when
1195 we stop accepting those options. */
1197 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1199 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1200 directive_string
= "transform";
1202 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1204 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1205 directive_string
= "transform";
1208 directive_string
= input_line_pointer
;
1210 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1212 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1214 input_line_pointer
+= len
;
1215 *directive
= (directiveE
) i
;
1216 if (*negated
&& !directive_info
[i
].can_be_negated
)
1217 as_bad (_("directive %s cannot be negated"),
1218 directive_info
[i
].name
);
1223 as_bad (_("unknown directive"));
1224 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1229 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1231 directiveE directive
;
1232 bfd_boolean negated
;
1236 get_directive (&directive
, &negated
);
1237 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1239 discard_rest_of_line ();
1243 if (cur_vinsn
.inside_bundle
)
1244 as_bad (_("directives are not valid inside bundles"));
1248 case directive_literal
:
1249 if (!inside_directive (directive_literal
))
1251 /* Previous labels go with whatever follows this directive, not with
1252 the literal, so save them now. */
1253 saved_insn_labels
= insn_labels
;
1256 as_warn (_(".begin literal is deprecated; use .literal instead"));
1257 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1258 xtensa_switch_to_literal_fragment (state
);
1259 directive_push (directive_literal
, negated
, state
);
1262 case directive_literal_prefix
:
1263 /* Have to flush pending output because a movi relaxed to an l32r
1264 might produce a literal. */
1265 md_flush_pending_output ();
1266 /* Check to see if the current fragment is a literal
1267 fragment. If it is, then this operation is not allowed. */
1268 if (generating_literals
)
1270 as_bad (_("cannot set literal_prefix inside literal fragment"));
1274 /* Allocate the literal state for this section and push
1275 onto the directive stack. */
1276 ls
= xmalloc (sizeof (lit_state
));
1279 *ls
= default_lit_sections
;
1280 directive_push (directive_literal_prefix
, negated
, ls
);
1282 /* Process the new prefix. */
1283 xtensa_literal_prefix ();
1286 case directive_freeregs
:
1287 /* This information is currently unused, but we'll accept the statement
1288 and just discard the rest of the line. This won't check the syntax,
1289 but it will accept every correct freeregs directive. */
1290 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1291 directive_push (directive_freeregs
, negated
, 0);
1294 case directive_schedule
:
1295 md_flush_pending_output ();
1296 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1297 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1298 directive_push (directive_schedule
, negated
, 0);
1299 xtensa_set_frag_assembly_state (frag_now
);
1302 case directive_density
:
1303 as_warn (_(".begin [no-]density is ignored"));
1306 case directive_absolute_literals
:
1307 md_flush_pending_output ();
1308 if (!absolute_literals_supported
&& !negated
)
1310 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1313 xtensa_set_frag_assembly_state (frag_now
);
1314 directive_push (directive
, negated
, 0);
1318 md_flush_pending_output ();
1319 xtensa_set_frag_assembly_state (frag_now
);
1320 directive_push (directive
, negated
, 0);
1324 demand_empty_rest_of_line ();
1329 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1331 directiveE begin_directive
, end_directive
;
1332 bfd_boolean begin_negated
, end_negated
;
1336 emit_state
**state_ptr
;
1339 if (cur_vinsn
.inside_bundle
)
1340 as_bad (_("directives are not valid inside bundles"));
1342 get_directive (&end_directive
, &end_negated
);
1344 md_flush_pending_output ();
1346 switch ((int) end_directive
)
1348 case XTENSA_UNDEFINED
:
1349 discard_rest_of_line ();
1352 case (int) directive_density
:
1353 as_warn (_(".end [no-]density is ignored"));
1354 demand_empty_rest_of_line ();
1357 case (int) directive_absolute_literals
:
1358 if (!absolute_literals_supported
&& !end_negated
)
1360 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1361 demand_empty_rest_of_line ();
1370 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1371 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1372 (const void **) state_ptr
);
1374 if (begin_directive
!= directive_none
)
1376 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1378 as_bad (_("does not match begin %s%s at %s:%d"),
1379 begin_negated
? "no-" : "",
1380 directive_info
[begin_directive
].name
, file
, line
);
1384 switch (end_directive
)
1386 case directive_literal
:
1387 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1388 xtensa_restore_emit_state (state
);
1389 xtensa_set_frag_assembly_state (frag_now
);
1391 if (!inside_directive (directive_literal
))
1393 /* Restore the list of current labels. */
1394 xtensa_clear_insn_labels ();
1395 insn_labels
= saved_insn_labels
;
1399 case directive_literal_prefix
:
1400 /* Restore the default collection sections from saved state. */
1401 s
= (lit_state
*) state
;
1403 default_lit_sections
= *s
;
1405 /* Free the state storage. */
1406 free (s
->lit_prefix
);
1410 case directive_schedule
:
1411 case directive_freeregs
:
1415 xtensa_set_frag_assembly_state (frag_now
);
1421 demand_empty_rest_of_line ();
1425 /* Place an aligned literal fragment at the current location. */
1428 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1430 md_flush_pending_output ();
1432 if (inside_directive (directive_literal
))
1433 as_warn (_(".literal_position inside literal directive; ignoring"));
1434 xtensa_mark_literal_pool_location ();
1436 demand_empty_rest_of_line ();
1437 xtensa_clear_insn_labels ();
1441 /* Support .literal label, expr, ... */
1444 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1447 char *p
, *base_name
;
1451 if (inside_directive (directive_literal
))
1453 as_bad (_(".literal not allowed inside .begin literal region"));
1454 ignore_rest_of_line ();
1458 md_flush_pending_output ();
1460 /* Previous labels go with whatever follows this directive, not with
1461 the literal, so save them now. */
1462 saved_insn_labels
= insn_labels
;
1465 /* If we are using text-section literals, then this is the right value... */
1468 base_name
= input_line_pointer
;
1470 xtensa_switch_to_literal_fragment (&state
);
1472 /* ...but if we aren't using text-section-literals, then we
1473 need to put them in the section we just switched to. */
1474 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1477 /* FIXME, despite the previous comments, dest_seg is unused... */
1480 /* All literals are aligned to four-byte boundaries. */
1481 frag_align (2, 0, 0);
1482 record_alignment (now_seg
, 2);
1484 c
= get_symbol_end ();
1485 /* Just after name is now '\0'. */
1486 p
= input_line_pointer
;
1490 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1492 as_bad (_("expected comma or colon after symbol name; "
1493 "rest of line ignored"));
1494 ignore_rest_of_line ();
1495 xtensa_restore_emit_state (&state
);
1503 input_line_pointer
++; /* skip ',' or ':' */
1505 xtensa_elf_cons (4);
1507 xtensa_restore_emit_state (&state
);
1509 /* Restore the list of current labels. */
1510 xtensa_clear_insn_labels ();
1511 insn_labels
= saved_insn_labels
;
1516 xtensa_literal_prefix (void)
1521 /* Parse the new prefix from the input_line_pointer. */
1523 len
= strspn (input_line_pointer
,
1524 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1525 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1527 /* Get a null-terminated copy of the name. */
1528 name
= xmalloc (len
+ 1);
1530 strncpy (name
, input_line_pointer
, len
);
1533 /* Skip the name in the input line. */
1534 input_line_pointer
+= len
;
1536 default_lit_sections
.lit_prefix
= name
;
1538 /* Clear cached literal sections, since the prefix has changed. */
1539 default_lit_sections
.lit_seg
= NULL
;
1540 default_lit_sections
.lit4_seg
= NULL
;
1544 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1547 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1549 float fall_through_f
, target_f
;
1551 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1552 if (fall_through_f
< 0)
1554 as_bad (_("fall through frequency must be greater than 0"));
1555 ignore_rest_of_line ();
1559 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1562 as_bad (_("branch target frequency must be greater than 0"));
1563 ignore_rest_of_line ();
1567 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1569 demand_empty_rest_of_line ();
1573 /* Like normal .long/.short/.word, except support @plt, etc.
1574 Clobbers input_line_pointer, checks end-of-line. */
1577 xtensa_elf_cons (int nbytes
)
1580 bfd_reloc_code_real_type reloc
;
1582 md_flush_pending_output ();
1584 if (cur_vinsn
.inside_bundle
)
1585 as_bad (_("directives are not valid inside bundles"));
1587 if (is_it_end_of_statement ())
1589 demand_empty_rest_of_line ();
1596 if (exp
.X_op
== O_symbol
1597 && *input_line_pointer
== '@'
1598 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1601 reloc_howto_type
*reloc_howto
=
1602 bfd_reloc_type_lookup (stdoutput
, reloc
);
1604 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1605 as_bad (_("unsupported relocation"));
1606 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1607 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1608 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1609 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1610 as_bad (_("opcode-specific %s relocation used outside "
1611 "an instruction"), reloc_howto
->name
);
1612 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1613 as_bad (_("%s relocations do not fit in %d bytes"),
1614 reloc_howto
->name
, nbytes
);
1615 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1616 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1617 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1618 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1621 char *p
= frag_more ((int) nbytes
);
1622 xtensa_set_frag_assembly_state (frag_now
);
1623 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1624 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1629 xtensa_set_frag_assembly_state (frag_now
);
1630 emit_expr (&exp
, (unsigned int) nbytes
);
1633 while (*input_line_pointer
++ == ',');
1635 input_line_pointer
--; /* Put terminator back into stream. */
1636 demand_empty_rest_of_line ();
1639 static bfd_boolean is_leb128_expr
;
1642 xtensa_leb128 (int sign
)
1644 is_leb128_expr
= TRUE
;
1646 is_leb128_expr
= FALSE
;
1650 /* Parsing and Idiom Translation. */
1652 /* Parse @plt, etc. and return the desired relocation. */
1653 static bfd_reloc_code_real_type
1654 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1661 struct suffix_reloc_map
*ptr
;
1664 return BFD_RELOC_NONE
;
1666 for (ch
= *str
, str2
= ident
;
1667 (str2
< ident
+ sizeof (ident
) - 1
1668 && (ISALNUM (ch
) || ch
== '@'));
1671 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1678 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1679 if (ch
== ptr
->suffix
[0]
1680 && len
== ptr
->length
1681 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1683 /* Now check for "identifier@suffix+constant". */
1684 if (*str
== '-' || *str
== '+')
1686 char *orig_line
= input_line_pointer
;
1687 expressionS new_exp
;
1689 input_line_pointer
= str
;
1690 expression (&new_exp
);
1691 if (new_exp
.X_op
== O_constant
)
1693 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1694 str
= input_line_pointer
;
1697 if (&input_line_pointer
!= str_p
)
1698 input_line_pointer
= orig_line
;
1705 return BFD_RELOC_UNUSED
;
1709 /* Find the matching operator type. */
1710 static unsigned char
1711 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1713 struct suffix_reloc_map
*sfx
;
1714 unsigned char operator = (unsigned char) -1;
1716 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1718 if (sfx
->reloc
== reloc
)
1720 operator = sfx
->operator;
1724 gas_assert (operator != (unsigned char) -1);
1729 /* Find the matching reloc type. */
1730 static bfd_reloc_code_real_type
1731 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1733 struct suffix_reloc_map
*sfx
;
1734 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1736 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1738 if (sfx
->operator == operator)
1747 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1748 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1749 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1750 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1753 if (reloc
== BFD_RELOC_UNUSED
)
1754 return BFD_RELOC_32
;
1761 expression_end (const char *name
)
1784 #define ERROR_REG_NUM ((unsigned) -1)
1787 tc_get_register (const char *prefix
)
1790 const char *next_expr
;
1791 const char *old_line_pointer
;
1794 old_line_pointer
= input_line_pointer
;
1796 if (*input_line_pointer
== '$')
1797 ++input_line_pointer
;
1799 /* Accept "sp" as a synonym for "a1". */
1800 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1801 && expression_end (input_line_pointer
+ 2))
1803 input_line_pointer
+= 2;
1804 return 1; /* AR[1] */
1807 while (*input_line_pointer
++ == *prefix
++)
1809 --input_line_pointer
;
1814 as_bad (_("bad register name: %s"), old_line_pointer
);
1815 return ERROR_REG_NUM
;
1818 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1820 as_bad (_("bad register number: %s"), input_line_pointer
);
1821 return ERROR_REG_NUM
;
1826 while (ISDIGIT ((int) *input_line_pointer
))
1827 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1829 if (!(next_expr
= expression_end (input_line_pointer
)))
1831 as_bad (_("bad register name: %s"), old_line_pointer
);
1832 return ERROR_REG_NUM
;
1835 input_line_pointer
= (char *) next_expr
;
1842 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1844 xtensa_isa isa
= xtensa_default_isa
;
1846 /* Check if this is an immediate operand. */
1847 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1849 bfd_reloc_code_real_type reloc
;
1850 segT t
= expression (tok
);
1852 if (t
== absolute_section
1853 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1855 gas_assert (tok
->X_op
== O_constant
);
1856 tok
->X_op
= O_symbol
;
1857 tok
->X_add_symbol
= &abs_symbol
;
1860 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1861 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1866 case BFD_RELOC_LO16
:
1867 if (tok
->X_op
== O_constant
)
1869 tok
->X_add_number
&= 0xffff;
1873 case BFD_RELOC_HI16
:
1874 if (tok
->X_op
== O_constant
)
1876 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1880 case BFD_RELOC_UNUSED
:
1881 as_bad (_("unsupported relocation"));
1883 case BFD_RELOC_32_PCREL
:
1884 as_bad (_("pcrel relocation not allowed in an instruction"));
1889 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1894 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1895 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1897 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1900 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1901 as_bad (_("register number out of range"));
1904 tok
->X_op
= O_register
;
1905 tok
->X_add_symbol
= 0;
1906 tok
->X_add_number
= reg
;
1911 /* Split up the arguments for an opcode or pseudo-op. */
1914 tokenize_arguments (char **args
, char *str
)
1916 char *old_input_line_pointer
;
1917 bfd_boolean saw_comma
= FALSE
;
1918 bfd_boolean saw_arg
= FALSE
;
1919 bfd_boolean saw_colon
= FALSE
;
1921 char *arg_end
, *arg
;
1924 /* Save and restore input_line_pointer around this function. */
1925 old_input_line_pointer
= input_line_pointer
;
1926 input_line_pointer
= str
;
1928 while (*input_line_pointer
)
1931 switch (*input_line_pointer
)
1938 input_line_pointer
++;
1939 if (saw_comma
|| saw_colon
|| !saw_arg
)
1945 input_line_pointer
++;
1946 if (saw_comma
|| saw_colon
|| !saw_arg
)
1952 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1955 arg_end
= input_line_pointer
+ 1;
1956 while (!expression_end (arg_end
))
1959 arg_len
= arg_end
- input_line_pointer
;
1960 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1961 args
[num_args
] = arg
;
1965 strncpy (arg
, input_line_pointer
, arg_len
);
1966 arg
[arg_len
] = '\0';
1968 input_line_pointer
= arg_end
;
1978 if (saw_comma
|| saw_colon
)
1980 input_line_pointer
= old_input_line_pointer
;
1985 as_bad (_("extra comma"));
1987 as_bad (_("extra colon"));
1989 as_bad (_("missing argument"));
1991 as_bad (_("missing comma or colon"));
1992 input_line_pointer
= old_input_line_pointer
;
1997 /* Parse the arguments to an opcode. Return TRUE on error. */
2000 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2002 expressionS
*tok
, *last_tok
;
2003 xtensa_opcode opcode
= insn
->opcode
;
2004 bfd_boolean had_error
= TRUE
;
2005 xtensa_isa isa
= xtensa_default_isa
;
2006 int n
, num_regs
= 0;
2007 int opcode_operand_count
;
2008 int opnd_cnt
, last_opnd_cnt
;
2009 unsigned int next_reg
= 0;
2010 char *old_input_line_pointer
;
2012 if (insn
->insn_type
== ITYPE_LITERAL
)
2013 opcode_operand_count
= 1;
2015 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2018 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2020 /* Save and restore input_line_pointer around this function. */
2021 old_input_line_pointer
= input_line_pointer
;
2027 /* Skip invisible operands. */
2028 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2034 for (n
= 0; n
< num_args
; n
++)
2036 input_line_pointer
= arg_strings
[n
];
2037 if (*input_line_pointer
== ':')
2039 xtensa_regfile opnd_rf
;
2040 input_line_pointer
++;
2043 gas_assert (opnd_cnt
> 0);
2045 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2047 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2048 as_warn (_("incorrect register number, ignoring"));
2053 if (opnd_cnt
>= opcode_operand_count
)
2055 as_warn (_("too many arguments"));
2058 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2060 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2061 next_reg
= tok
->X_add_number
+ 1;
2063 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2065 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2067 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2068 /* minus 1 because we are seeing one right now */
2074 last_opnd_cnt
= opnd_cnt
;
2075 demand_empty_rest_of_line ();
2082 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2086 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2089 insn
->ntok
= tok
- insn
->tok
;
2093 input_line_pointer
= old_input_line_pointer
;
2099 get_invisible_operands (TInsn
*insn
)
2101 xtensa_isa isa
= xtensa_default_isa
;
2102 static xtensa_insnbuf slotbuf
= NULL
;
2104 xtensa_opcode opc
= insn
->opcode
;
2105 int slot
, opnd
, fmt_found
;
2109 slotbuf
= xtensa_insnbuf_alloc (isa
);
2111 /* Find format/slot where this can be encoded. */
2114 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2116 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2118 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2124 if (fmt_found
) break;
2129 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2133 /* First encode all the visible operands
2134 (to deal with shared field operands). */
2135 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2137 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2138 && (insn
->tok
[opnd
].X_op
== O_register
2139 || insn
->tok
[opnd
].X_op
== O_constant
))
2141 val
= insn
->tok
[opnd
].X_add_number
;
2142 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2143 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2147 /* Then pull out the values for the invisible ones. */
2148 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2150 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2152 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2153 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2154 insn
->tok
[opnd
].X_add_number
= val
;
2155 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2156 insn
->tok
[opnd
].X_op
= O_register
;
2158 insn
->tok
[opnd
].X_op
= O_constant
;
2167 xg_reverse_shift_count (char **cnt_argp
)
2169 char *cnt_arg
, *new_arg
;
2170 cnt_arg
= *cnt_argp
;
2172 /* replace the argument with "31-(argument)" */
2173 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2174 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2177 *cnt_argp
= new_arg
;
2181 /* If "arg" is a constant expression, return non-zero with the value
2185 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2188 char *save_ptr
= input_line_pointer
;
2190 input_line_pointer
= arg
;
2192 input_line_pointer
= save_ptr
;
2194 if (exp
.X_op
== O_constant
)
2196 *valp
= exp
.X_add_number
;
2205 xg_replace_opname (char **popname
, char *newop
)
2208 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2209 strcpy (*popname
, newop
);
2214 xg_check_num_args (int *pnum_args
,
2219 int num_args
= *pnum_args
;
2221 if (num_args
< expected_num
)
2223 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2224 num_args
, opname
, expected_num
);
2228 if (num_args
> expected_num
)
2230 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2231 num_args
, opname
, expected_num
);
2232 while (num_args
-- > expected_num
)
2234 free (arg_strings
[num_args
]);
2235 arg_strings
[num_args
] = 0;
2237 *pnum_args
= expected_num
;
2245 /* If the register is not specified as part of the opcode,
2246 then get it from the operand and move it to the opcode. */
2249 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2251 xtensa_isa isa
= xtensa_default_isa
;
2253 char *opname
, *new_opname
;
2254 const char *sr_name
;
2255 int is_user
, is_write
;
2260 is_user
= (opname
[1] == 'u');
2261 is_write
= (opname
[0] == 'w');
2263 /* Opname == [rw]ur or [rwx]sr... */
2265 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2268 /* Check if the argument is a symbolic register name. */
2269 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2270 /* Handle WSR to "INTSET" as a special case. */
2271 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2272 && !strcasecmp (arg_strings
[1], "intset"))
2273 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2274 if (sr
== XTENSA_UNDEFINED
2275 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2277 /* Maybe it's a register number.... */
2279 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2281 as_bad (_("invalid register '%s' for '%s' instruction"),
2282 arg_strings
[1], opname
);
2285 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2286 if (sr
== XTENSA_UNDEFINED
)
2288 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2289 (long) val
, opname
);
2294 /* Remove the last argument, which is now part of the opcode. */
2295 free (arg_strings
[1]);
2299 /* Translate the opcode. */
2300 sr_name
= xtensa_sysreg_name (isa
, sr
);
2301 /* Another special case for "WSR.INTSET".... */
2302 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2304 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2305 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2307 *popname
= new_opname
;
2314 xtensa_translate_old_userreg_ops (char **popname
)
2316 xtensa_isa isa
= xtensa_default_isa
;
2318 char *opname
, *new_opname
;
2319 const char *sr_name
;
2320 bfd_boolean has_underbar
= FALSE
;
2323 if (opname
[0] == '_')
2325 has_underbar
= TRUE
;
2329 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2330 if (sr
!= XTENSA_UNDEFINED
)
2332 /* The new default name ("nnn") is different from the old default
2333 name ("URnnn"). The old default is handled below, and we don't
2334 want to recognize [RW]nnn, so do nothing if the name is the (new)
2336 static char namebuf
[10];
2337 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2338 if (strcmp (namebuf
, opname
+ 1) == 0)
2346 /* Only continue if the reg name is "URnnn". */
2347 if (opname
[1] != 'u' || opname
[2] != 'r')
2349 val
= strtoul (opname
+ 3, &end
, 10);
2353 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2354 if (sr
== XTENSA_UNDEFINED
)
2356 as_bad (_("invalid register number (%ld) for '%s'"),
2357 (long) val
, opname
);
2362 /* Translate the opcode. */
2363 sr_name
= xtensa_sysreg_name (isa
, sr
);
2364 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2365 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2366 opname
[0], sr_name
);
2368 *popname
= new_opname
;
2375 xtensa_translate_zero_immed (char *old_op
,
2385 gas_assert (opname
[0] != '_');
2387 if (strcmp (opname
, old_op
) != 0)
2390 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2392 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2394 xg_replace_opname (popname
, new_op
);
2395 free (arg_strings
[1]);
2396 arg_strings
[1] = arg_strings
[2];
2405 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2406 Returns non-zero if an error was found. */
2409 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2411 char *opname
= *popname
;
2412 bfd_boolean has_underbar
= FALSE
;
2416 has_underbar
= TRUE
;
2420 if (strcmp (opname
, "mov") == 0)
2422 if (use_transform () && !has_underbar
&& density_supported
)
2423 xg_replace_opname (popname
, "mov.n");
2426 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2428 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2429 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2430 strcpy (arg_strings
[2], arg_strings
[1]);
2436 if (strcmp (opname
, "bbsi.l") == 0)
2438 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2440 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2441 if (target_big_endian
)
2442 xg_reverse_shift_count (&arg_strings
[1]);
2446 if (strcmp (opname
, "bbci.l") == 0)
2448 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2450 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2451 if (target_big_endian
)
2452 xg_reverse_shift_count (&arg_strings
[1]);
2456 /* Don't do anything special with NOPs inside FLIX instructions. They
2457 are handled elsewhere. Real NOP instructions are always available
2458 in configurations with FLIX, so this should never be an issue but
2459 check for it anyway. */
2460 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2461 && strcmp (opname
, "nop") == 0)
2463 if (use_transform () && !has_underbar
&& density_supported
)
2464 xg_replace_opname (popname
, "nop.n");
2467 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2469 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2470 arg_strings
[0] = (char *) xmalloc (3);
2471 arg_strings
[1] = (char *) xmalloc (3);
2472 arg_strings
[2] = (char *) xmalloc (3);
2473 strcpy (arg_strings
[0], "a1");
2474 strcpy (arg_strings
[1], "a1");
2475 strcpy (arg_strings
[2], "a1");
2481 /* Recognize [RW]UR and [RWX]SR. */
2482 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2483 && (opname
[1] == 'u' || opname
[1] == 's'))
2484 || (opname
[0] == 'x' && opname
[1] == 's'))
2486 && opname
[3] == '\0')
2487 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2489 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2490 [RW]<name> if <name> is the non-default name of a user register. */
2491 if ((opname
[0] == 'r' || opname
[0] == 'w')
2492 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2493 return xtensa_translate_old_userreg_ops (popname
);
2495 /* Relax branches that don't allow comparisons against an immediate value
2496 of zero to the corresponding branches with implicit zero immediates. */
2497 if (!has_underbar
&& use_transform ())
2499 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2500 pnum_args
, arg_strings
))
2503 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2504 pnum_args
, arg_strings
))
2507 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2508 pnum_args
, arg_strings
))
2511 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2512 pnum_args
, arg_strings
))
2520 /* Functions for dealing with the Xtensa ISA. */
2522 /* Currently the assembler only allows us to use a single target per
2523 fragment. Because of this, only one operand for a given
2524 instruction may be symbolic. If there is a PC-relative operand,
2525 the last one is chosen. Otherwise, the result is the number of the
2526 last immediate operand, and if there are none of those, we fail and
2530 get_relaxable_immed (xtensa_opcode opcode
)
2532 int last_immed
= -1;
2535 if (opcode
== XTENSA_UNDEFINED
)
2538 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2539 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2541 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2543 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2545 if (last_immed
== -1
2546 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2553 static xtensa_opcode
2554 get_opcode_from_buf (const char *buf
, int slot
)
2556 static xtensa_insnbuf insnbuf
= NULL
;
2557 static xtensa_insnbuf slotbuf
= NULL
;
2558 xtensa_isa isa
= xtensa_default_isa
;
2563 insnbuf
= xtensa_insnbuf_alloc (isa
);
2564 slotbuf
= xtensa_insnbuf_alloc (isa
);
2567 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2568 fmt
= xtensa_format_decode (isa
, insnbuf
);
2569 if (fmt
== XTENSA_UNDEFINED
)
2570 return XTENSA_UNDEFINED
;
2572 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2573 return XTENSA_UNDEFINED
;
2575 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2576 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2580 #ifdef TENSILICA_DEBUG
2582 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2585 xtensa_print_insn_table (void)
2587 int num_opcodes
, num_operands
;
2588 xtensa_opcode opcode
;
2589 xtensa_isa isa
= xtensa_default_isa
;
2591 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2592 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2595 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2596 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2597 for (opn
= 0; opn
< num_operands
; opn
++)
2599 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2601 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2603 xtensa_regfile opnd_rf
=
2604 xtensa_operand_regfile (isa
, opcode
, opn
);
2605 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2607 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2608 fputs ("[lLr] ", stderr
);
2610 fputs ("i ", stderr
);
2612 fprintf (stderr
, "\n");
2618 print_vliw_insn (xtensa_insnbuf vbuf
)
2620 xtensa_isa isa
= xtensa_default_isa
;
2621 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2622 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2625 fprintf (stderr
, "format = %d\n", f
);
2627 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2629 xtensa_opcode opcode
;
2633 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2634 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2635 opname
= xtensa_opcode_name (isa
, opcode
);
2637 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2638 fprintf (stderr
, " operands = ");
2640 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2644 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2646 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2647 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2648 fprintf (stderr
, "%d ", val
);
2650 fprintf (stderr
, "\n");
2652 xtensa_insnbuf_free (isa
, sbuf
);
2655 #endif /* TENSILICA_DEBUG */
2659 is_direct_call_opcode (xtensa_opcode opcode
)
2661 xtensa_isa isa
= xtensa_default_isa
;
2662 int n
, num_operands
;
2664 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2667 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2668 for (n
= 0; n
< num_operands
; n
++)
2670 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2671 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2678 /* Convert from BFD relocation type code to slot and operand number.
2679 Returns non-zero on failure. */
2682 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2684 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2685 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2687 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2690 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2691 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2693 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2703 /* Convert from slot number to BFD relocation type code for the
2704 standard PC-relative relocations. Return BFD_RELOC_NONE on
2707 static bfd_reloc_code_real_type
2708 encode_reloc (int slot
)
2710 if (slot
< 0 || slot
> 14)
2711 return BFD_RELOC_NONE
;
2713 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2717 /* Convert from slot numbers to BFD relocation type code for the
2718 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2720 static bfd_reloc_code_real_type
2721 encode_alt_reloc (int slot
)
2723 if (slot
< 0 || slot
> 14)
2724 return BFD_RELOC_NONE
;
2726 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2731 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2734 xtensa_opcode opcode
,
2740 uint32 valbuf
= value
;
2742 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2744 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2746 as_bad_where ((char *) file
, line
,
2747 _("operand %d of '%s' has out of range value '%u'"),
2749 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2752 as_bad_where ((char *) file
, line
,
2753 _("operand %d of '%s' has invalid value '%u'"),
2755 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2760 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2766 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2769 xtensa_opcode opcode
,
2773 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2774 fmt
, slot
, slotbuf
, &val
);
2775 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2780 /* Checks for rules from xtensa-relax tables. */
2782 /* The routine xg_instruction_matches_option_term must return TRUE
2783 when a given option term is true. The meaning of all of the option
2784 terms is given interpretation by this function. */
2787 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2789 if (strcmp (option
->option_name
, "realnop") == 0
2790 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2792 /* These conditions were evaluated statically when building the
2793 relaxation table. There's no need to reevaluate them now. */
2796 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2797 return insn
->extra_arg
.X_op
== O_register
;
2800 as_fatal (_("internal error: unknown option name '%s'"),
2801 option
->option_name
);
2807 xg_instruction_matches_or_options (TInsn
*insn
,
2808 const ReqOrOptionList
*or_option
)
2810 const ReqOrOption
*option
;
2811 /* Must match each of the AND terms. */
2812 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2814 if (xg_instruction_matches_option_term (insn
, option
))
2822 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2824 const ReqOption
*req_options
;
2825 /* Must match each of the AND terms. */
2826 for (req_options
= options
;
2827 req_options
!= NULL
;
2828 req_options
= req_options
->next
)
2830 /* Must match one of the OR clauses. */
2831 if (!xg_instruction_matches_or_options (insn
,
2832 req_options
->or_option_terms
))
2839 /* Return the transition rule that matches or NULL if none matches. */
2842 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2844 PreconditionList
*condition_l
;
2846 if (rule
->opcode
!= insn
->opcode
)
2849 for (condition_l
= rule
->conditions
;
2850 condition_l
!= NULL
;
2851 condition_l
= condition_l
->next
)
2855 Precondition
*cond
= condition_l
->precond
;
2860 /* The expression must be the constant. */
2861 gas_assert (cond
->op_num
< insn
->ntok
);
2862 exp1
= &insn
->tok
[cond
->op_num
];
2863 if (expr_is_const (exp1
))
2868 if (get_expr_const (exp1
) != cond
->op_data
)
2872 if (get_expr_const (exp1
) == cond
->op_data
)
2879 else if (expr_is_register (exp1
))
2884 if (get_expr_register (exp1
) != cond
->op_data
)
2888 if (get_expr_register (exp1
) == cond
->op_data
)
2900 gas_assert (cond
->op_num
< insn
->ntok
);
2901 gas_assert (cond
->op_data
< insn
->ntok
);
2902 exp1
= &insn
->tok
[cond
->op_num
];
2903 exp2
= &insn
->tok
[cond
->op_data
];
2908 if (!expr_is_equal (exp1
, exp2
))
2912 if (expr_is_equal (exp1
, exp2
))
2924 if (!xg_instruction_matches_options (insn
, rule
->options
))
2932 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2934 bfd_boolean a_greater
= FALSE
;
2935 bfd_boolean b_greater
= FALSE
;
2937 ReqOptionList
*l_a
= a
->options
;
2938 ReqOptionList
*l_b
= b
->options
;
2940 /* We only care if they both are the same except for
2941 a const16 vs. an l32r. */
2943 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2945 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2946 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2947 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2949 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2951 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2953 /* This is the case we care about. */
2954 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2955 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2962 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2963 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2973 l_or_a
= l_or_a
->next
;
2974 l_or_b
= l_or_b
->next
;
2976 if (l_or_a
|| l_or_b
)
2985 /* Incomparable if the substitution was used differently in two cases. */
2986 if (a_greater
&& b_greater
)
2998 static TransitionRule
*
2999 xg_instruction_match (TInsn
*insn
)
3001 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3003 gas_assert (insn
->opcode
< table
->num_opcodes
);
3005 /* Walk through all of the possible transitions. */
3006 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3008 TransitionRule
*rule
= l
->rule
;
3009 if (xg_instruction_matches_rule (insn
, rule
))
3016 /* Various Other Internal Functions. */
3019 is_unique_insn_expansion (TransitionRule
*r
)
3021 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3023 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3029 /* Check if there is exactly one relaxation for INSN that converts it to
3030 another instruction of equal or larger size. If so, and if TARG is
3031 non-null, go ahead and generate the relaxed instruction into TARG. If
3032 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3033 instruction, i.e., ignore relaxations that convert to an instruction of
3034 equal size. In some contexts where this function is used, only
3035 a single widening is allowed and the NARROW_ONLY argument is used to
3036 exclude cases like ADDI being "widened" to an ADDMI, which may
3037 later be relaxed to an ADDMI/ADDI pair. */
3040 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3042 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3044 TransitionRule
*match
= 0;
3046 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3047 gas_assert (insn
->opcode
< table
->num_opcodes
);
3049 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3051 TransitionRule
*rule
= l
->rule
;
3053 if (xg_instruction_matches_rule (insn
, rule
)
3054 && is_unique_insn_expansion (rule
)
3055 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3056 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3067 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3072 /* Return the maximum number of bytes this opcode can expand to. */
3075 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3077 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3079 int max_size
= xg_get_single_size (opcode
);
3081 gas_assert (opcode
< table
->num_opcodes
);
3083 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3085 TransitionRule
*rule
= l
->rule
;
3086 BuildInstr
*build_list
;
3091 build_list
= rule
->to_instr
;
3092 if (is_unique_insn_expansion (rule
))
3094 gas_assert (build_list
->typ
== INSTR_INSTR
);
3095 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3098 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3100 switch (build_list
->typ
)
3103 this_size
+= xg_get_single_size (build_list
->opcode
);
3105 case INSTR_LITERAL_DEF
:
3106 case INSTR_LABEL_DEF
:
3111 if (this_size
> max_size
)
3112 max_size
= this_size
;
3118 /* Return the maximum number of literal bytes this opcode can generate. */
3121 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3123 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3127 gas_assert (opcode
< table
->num_opcodes
);
3129 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3131 TransitionRule
*rule
= l
->rule
;
3132 BuildInstr
*build_list
;
3137 build_list
= rule
->to_instr
;
3138 if (is_unique_insn_expansion (rule
))
3140 gas_assert (build_list
->typ
== INSTR_INSTR
);
3141 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3144 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3146 switch (build_list
->typ
)
3148 case INSTR_LITERAL_DEF
:
3149 /* Hard-coded 4-byte literal. */
3153 case INSTR_LABEL_DEF
:
3158 if (this_size
> max_size
)
3159 max_size
= this_size
;
3166 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3168 int steps_taken
= 0;
3169 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3172 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3173 gas_assert (insn
->opcode
< table
->num_opcodes
);
3175 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3177 TransitionRule
*rule
= l
->rule
;
3179 if (xg_instruction_matches_rule (insn
, rule
))
3181 if (steps_taken
== lateral_steps
)
3191 get_special_literal_symbol (void)
3193 static symbolS
*sym
= NULL
;
3196 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3202 get_special_label_symbol (void)
3204 static symbolS
*sym
= NULL
;
3207 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3213 xg_valid_literal_expression (const expressionS
*exp
)
3235 /* This will check to see if the value can be converted into the
3236 operand type. It will return TRUE if it does not fit. */
3239 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3241 uint32 valbuf
= value
;
3242 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3248 /* Assumes: All immeds are constants. Check that all constants fit
3249 into their immeds; return FALSE if not. */
3252 xg_immeds_fit (const TInsn
*insn
)
3254 xtensa_isa isa
= xtensa_default_isa
;
3258 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3259 for (i
= 0; i
< n
; ++i
)
3261 const expressionS
*exp
= &insn
->tok
[i
];
3263 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3270 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3275 /* The symbol should have a fixup associated with it. */
3284 /* This should only be called after we have an initial
3285 estimate of the addresses. */
3288 xg_symbolic_immeds_fit (const TInsn
*insn
,
3294 xtensa_isa isa
= xtensa_default_isa
;
3302 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3304 for (i
= 0; i
< n
; ++i
)
3306 const expressionS
*exp
= &insn
->tok
[i
];
3308 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3315 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3321 /* Check for the worst case. */
3322 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3327 /* We only allow symbols for PC-relative references.
3328 If pc_frag == 0, then we don't have frag locations yet. */
3330 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3333 /* If it is a weak symbol or a symbol in a different section,
3334 it cannot be known to fit at assembly time. */
3335 if (S_IS_WEAK (exp
->X_add_symbol
)
3336 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3338 /* For a direct call with --no-longcalls, be optimistic and
3339 assume it will be in range. If the symbol is weak and
3340 undefined, it may remain undefined at link-time, in which
3341 case it will have a zero value and almost certainly be out
3342 of range for a direct call; thus, relax for undefined weak
3343 symbols even if longcalls is not enabled. */
3344 if (is_direct_call_opcode (insn
->opcode
)
3345 && ! pc_frag
->tc_frag_data
.use_longcalls
3346 && (! S_IS_WEAK (exp
->X_add_symbol
)
3347 || S_IS_DEFINED (exp
->X_add_symbol
)))
3353 symbolP
= exp
->X_add_symbol
;
3354 sym_frag
= symbol_get_frag (symbolP
);
3355 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3356 pc
= pc_frag
->fr_address
+ pc_offset
;
3358 /* If frag has yet to be reached on this pass, assume it
3359 will move by STRETCH just as we did. If this is not so,
3360 it will be because some frag between grows, and that will
3361 force another pass. Beware zero-length frags. There
3362 should be a faster way to do this. */
3365 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3366 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3371 new_offset
= target
;
3372 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3373 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3378 /* The symbol should have a fixup associated with it. */
3387 /* Return TRUE on success. */
3390 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3396 targ
->debug_line
= insn
->debug_line
;
3397 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3402 targ
->opcode
= bi
->opcode
;
3403 targ
->insn_type
= ITYPE_INSN
;
3404 targ
->is_specific_opcode
= FALSE
;
3406 for (; op
!= NULL
; op
= op
->next
)
3408 int op_num
= op
->op_num
;
3409 int op_data
= op
->op_data
;
3411 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3413 if (targ
->ntok
<= op_num
)
3414 targ
->ntok
= op_num
+ 1;
3419 set_expr_const (&targ
->tok
[op_num
], op_data
);
3422 gas_assert (op_data
< insn
->ntok
);
3423 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3426 if (insn
->extra_arg
.X_op
!= O_register
)
3428 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3431 sym
= get_special_literal_symbol ();
3432 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3433 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3434 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3435 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3438 sym
= get_special_label_symbol ();
3439 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3441 case OP_OPERAND_HI16U
:
3442 case OP_OPERAND_LOW16U
:
3443 gas_assert (op_data
< insn
->ntok
);
3444 if (expr_is_const (&insn
->tok
[op_data
]))
3447 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3448 val
= xg_apply_userdef_op_fn (op
->typ
,
3451 targ
->tok
[op_num
].X_add_number
= val
;
3455 /* For const16 we can create relocations for these. */
3456 if (targ
->opcode
== XTENSA_UNDEFINED
3457 || (targ
->opcode
!= xtensa_const16_opcode
))
3459 gas_assert (op_data
< insn
->ntok
);
3460 /* Need to build a O_lo16 or O_hi16. */
3461 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3462 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3464 if (op
->typ
== OP_OPERAND_HI16U
)
3465 targ
->tok
[op_num
].X_op
= O_hi16
;
3466 else if (op
->typ
== OP_OPERAND_LOW16U
)
3467 targ
->tok
[op_num
].X_op
= O_lo16
;
3474 /* currently handles:
3477 OP_OPERAND_F32MINUS */
3478 if (xg_has_userdef_op_fn (op
->typ
))
3480 gas_assert (op_data
< insn
->ntok
);
3481 if (expr_is_const (&insn
->tok
[op_data
]))
3484 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3485 val
= xg_apply_userdef_op_fn (op
->typ
,
3488 targ
->tok
[op_num
].X_add_number
= val
;
3491 return FALSE
; /* We cannot use a relocation for this. */
3500 case INSTR_LITERAL_DEF
:
3502 targ
->opcode
= XTENSA_UNDEFINED
;
3503 targ
->insn_type
= ITYPE_LITERAL
;
3504 targ
->is_specific_opcode
= FALSE
;
3505 for (; op
!= NULL
; op
= op
->next
)
3507 int op_num
= op
->op_num
;
3508 int op_data
= op
->op_data
;
3509 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3511 if (targ
->ntok
<= op_num
)
3512 targ
->ntok
= op_num
+ 1;
3517 gas_assert (op_data
< insn
->ntok
);
3518 /* We can only pass resolvable literals through. */
3519 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3521 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3533 case INSTR_LABEL_DEF
:
3535 targ
->opcode
= XTENSA_UNDEFINED
;
3536 targ
->insn_type
= ITYPE_LABEL
;
3537 targ
->is_specific_opcode
= FALSE
;
3538 /* Literal with no ops is a label? */
3539 gas_assert (op
== NULL
);
3550 /* Return TRUE on success. */
3553 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3555 for (; bi
!= NULL
; bi
= bi
->next
)
3557 TInsn
*next_insn
= istack_push_space (istack
);
3559 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3566 /* Return TRUE on valid expansion. */
3569 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3571 int stack_size
= istack
->ninsn
;
3572 int steps_taken
= 0;
3573 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3576 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3577 gas_assert (insn
->opcode
< table
->num_opcodes
);
3579 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3581 TransitionRule
*rule
= l
->rule
;
3583 if (xg_instruction_matches_rule (insn
, rule
))
3585 if (lateral_steps
== steps_taken
)
3589 /* This is it. Expand the rule to the stack. */
3590 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3593 /* Check to see if it fits. */
3594 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3596 TInsn
*tinsn
= &istack
->insn
[i
];
3598 if (tinsn
->insn_type
== ITYPE_INSN
3599 && !tinsn_has_symbolic_operands (tinsn
)
3600 && !xg_immeds_fit (tinsn
))
3602 istack
->ninsn
= stack_size
;
3615 /* Relax the assembly instruction at least "min_steps".
3616 Return the number of steps taken.
3618 For relaxation to correctly terminate, every relaxation chain must
3619 terminate in one of two ways:
3621 1. If the chain from one instruction to the next consists entirely of
3622 single instructions, then the chain *must* handle all possible
3623 immediates without failing. It must not ever fail because an
3624 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3625 chain is one example. L32R loads 32 bits, and there cannot be an
3626 immediate larger than 32 bits, so it satisfies this condition.
3627 Single instruction relaxation chains are as defined by
3628 xg_is_single_relaxable_instruction.
3630 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3631 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3633 Strictly speaking, in most cases you can violate condition 1 and be OK
3634 -- in particular when the last two instructions have the same single
3635 size. But nevertheless, you should guarantee the above two conditions.
3637 We could fix this so that single-instruction expansions correctly
3638 terminate when they can't handle the range, but the error messages are
3639 worse, and it actually turns out that in every case but one (18-bit wide
3640 branches), you need a multi-instruction expansion to get the full range
3641 anyway. And because 18-bit branches are handled identically to 15-bit
3642 branches, there isn't any point in changing it. */
3645 xg_assembly_relax (IStack
*istack
,
3648 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3649 offsetT pc_offset
, /* offset in fragment */
3650 int min_steps
, /* minimum conversion steps */
3651 long stretch
) /* number of bytes stretched so far */
3653 int steps_taken
= 0;
3655 /* Some of its immeds don't fit. Try to build a relaxed version.
3656 This may go through a couple of stages of single instruction
3657 transformations before we get there. */
3659 TInsn single_target
;
3661 int lateral_steps
= 0;
3662 int istack_size
= istack
->ninsn
;
3664 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3665 && steps_taken
>= min_steps
)
3667 istack_push (istack
, insn
);
3670 current_insn
= *insn
;
3672 /* Walk through all of the single instruction expansions. */
3673 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3676 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3679 if (steps_taken
>= min_steps
)
3681 istack_push (istack
, &single_target
);
3685 current_insn
= single_target
;
3688 /* Now check for a multi-instruction expansion. */
3689 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3691 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3694 if (steps_taken
>= min_steps
)
3696 istack_push (istack
, ¤t_insn
);
3701 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3703 if (steps_taken
>= min_steps
)
3707 istack
->ninsn
= istack_size
;
3710 /* It's not going to work -- use the original. */
3711 istack_push (istack
, insn
);
3717 xg_finish_frag (char *last_insn
,
3718 enum xtensa_relax_statesE frag_state
,
3719 enum xtensa_relax_statesE slot0_state
,
3721 bfd_boolean is_insn
)
3723 /* Finish off this fragment so that it has at LEAST the desired
3724 max_growth. If it doesn't fit in this fragment, close this one
3725 and start a new one. In either case, return a pointer to the
3726 beginning of the growth area. */
3730 frag_grow (max_growth
);
3731 old_frag
= frag_now
;
3733 frag_now
->fr_opcode
= last_insn
;
3735 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3737 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3738 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3740 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3741 xtensa_set_frag_assembly_state (frag_now
);
3743 /* Just to make sure that we did not split it up. */
3744 gas_assert (old_frag
->fr_next
== frag_now
);
3748 /* Return TRUE if the target frag is one of the next non-empty frags. */
3751 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3756 for (; fragP
; fragP
= fragP
->fr_next
)
3758 if (fragP
== target
)
3760 if (fragP
->fr_fix
!= 0)
3762 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3764 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3765 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3767 if (fragP
->fr_type
== rs_space
)
3775 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3777 xtensa_isa isa
= xtensa_default_isa
;
3779 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3784 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3785 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3788 for (i
= 0; i
< num_ops
; i
++)
3790 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3796 if (target_op
== -1)
3799 if (insn
->ntok
<= target_op
)
3802 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3805 sym
= insn
->tok
[target_op
].X_add_symbol
;
3809 if (insn
->tok
[target_op
].X_add_number
!= 0)
3812 target_frag
= symbol_get_frag (sym
);
3813 if (target_frag
== NULL
)
3816 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3817 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3825 xg_add_branch_and_loop_targets (TInsn
*insn
)
3827 xtensa_isa isa
= xtensa_default_isa
;
3828 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3830 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3833 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3834 && insn
->tok
[i
].X_op
== O_symbol
)
3835 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3839 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3840 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3844 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3846 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3847 && insn
->tok
[i
].X_op
== O_symbol
)
3849 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3850 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3851 if (S_IS_DEFINED (sym
))
3852 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3859 /* Return FALSE if no error. */
3862 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3867 switch (instr_spec
->typ
)
3870 new_insn
->insn_type
= ITYPE_INSN
;
3871 new_insn
->opcode
= instr_spec
->opcode
;
3873 case INSTR_LITERAL_DEF
:
3874 new_insn
->insn_type
= ITYPE_LITERAL
;
3875 new_insn
->opcode
= XTENSA_UNDEFINED
;
3877 case INSTR_LABEL_DEF
:
3880 new_insn
->is_specific_opcode
= FALSE
;
3881 new_insn
->debug_line
= old_insn
->debug_line
;
3882 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3884 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3887 const expressionS
*src_exp
;
3893 /* The expression must be the constant. */
3894 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3895 exp
= &new_insn
->tok
[b_op
->op_num
];
3896 set_expr_const (exp
, b_op
->op_data
);
3900 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3901 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3902 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3903 exp
= &new_insn
->tok
[b_op
->op_num
];
3904 copy_expr (exp
, src_exp
);
3909 as_bad (_("can't handle generation of literal/labels yet"));
3913 as_bad (_("can't handle undefined OP TYPE"));
3918 new_insn
->ntok
= num_ops
;
3923 /* Return TRUE if it was simplified. */
3926 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3928 TransitionRule
*rule
;
3929 BuildInstr
*insn_spec
;
3931 if (old_insn
->is_specific_opcode
|| !density_supported
)
3934 rule
= xg_instruction_match (old_insn
);
3938 insn_spec
= rule
->to_instr
;
3939 /* There should only be one. */
3940 gas_assert (insn_spec
!= NULL
);
3941 gas_assert (insn_spec
->next
== NULL
);
3942 if (insn_spec
->next
!= NULL
)
3945 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3951 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3952 l32i.n. (2) Check the number of operands. (3) Place the instruction
3953 tokens into the stack or relax it and place multiple
3954 instructions/literals onto the stack. Return FALSE if no error. */
3957 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3961 bfd_boolean do_expand
;
3963 tinsn_init (&new_insn
);
3965 /* Narrow it if we can. xg_simplify_insn now does all the
3966 appropriate checking (e.g., for the density option). */
3967 if (xg_simplify_insn (orig_insn
, &new_insn
))
3968 orig_insn
= &new_insn
;
3970 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3972 if (orig_insn
->ntok
< noperands
)
3974 as_bad (_("found %d operands for '%s': Expected %d"),
3976 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3980 if (orig_insn
->ntok
> noperands
)
3981 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3983 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3986 /* If there are not enough operands, we will assert above. If there
3987 are too many, just cut out the extras here. */
3988 orig_insn
->ntok
= noperands
;
3990 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3993 /* Special case for extui opcode which has constraints not handled
3994 by the ordinary operand encoding checks. The number of operands
3995 and related syntax issues have already been checked. */
3996 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3998 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3999 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4000 if (shiftimm
+ maskimm
> 32)
4002 as_bad (_("immediate operands sum to greater than 32"));
4007 /* If the instruction will definitely need to be relaxed, it is better
4008 to expand it now for better scheduling. Decide whether to expand
4010 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4012 /* Calls should be expanded to longcalls only in the backend relaxation
4013 so that the assembly scheduler will keep the L32R/CALLX instructions
4015 if (is_direct_call_opcode (orig_insn
->opcode
))
4018 if (tinsn_has_symbolic_operands (orig_insn
))
4020 /* The values of symbolic operands are not known yet, so only expand
4021 now if an operand is "complex" (e.g., difference of symbols) and
4022 will have to be stored as a literal regardless of the value. */
4023 if (!tinsn_has_complex_operands (orig_insn
))
4026 else if (xg_immeds_fit (orig_insn
))
4030 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4032 istack_push (istack
, orig_insn
);
4038 /* Return TRUE if the section flags are marked linkonce
4039 or the name is .gnu.linkonce.*. */
4041 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4044 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4046 flagword flags
, link_once_flags
;
4048 flags
= bfd_get_section_flags (abfd
, sec
);
4049 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4051 /* Flags might not be set yet. */
4052 if (!link_once_flags
4053 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4054 link_once_flags
= SEC_LINK_ONCE
;
4056 return (link_once_flags
!= 0);
4061 xtensa_add_literal_sym (symbolS
*sym
)
4065 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4067 l
->next
= literal_syms
;
4073 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4075 static int lit_num
= 0;
4076 static char name
[256];
4079 sprintf (name
, ".L_lit_sym%d", lit_num
);
4081 /* Create a local symbol. If it is in a linkonce section, we have to
4082 be careful to make sure that if it is used in a relocation that the
4083 symbol will be in the output file. */
4084 if (get_is_linkonce_section (stdoutput
, sec
))
4086 symbolP
= symbol_new (name
, sec
, 0, frag
);
4087 S_CLEAR_EXTERNAL (symbolP
);
4088 /* symbolP->local = 1; */
4091 symbolP
= symbol_new (name
, sec
, 0, frag
);
4093 xtensa_add_literal_sym (symbolP
);
4100 /* Currently all literals that are generated here are 32-bit L32R targets. */
4103 xg_assemble_literal (/* const */ TInsn
*insn
)
4106 symbolS
*lit_sym
= NULL
;
4107 bfd_reloc_code_real_type reloc
;
4108 bfd_boolean pcrel
= FALSE
;
4111 /* size = 4 for L32R. It could easily be larger when we move to
4112 larger constants. Add a parameter later. */
4113 offsetT litsize
= 4;
4114 offsetT litalign
= 2; /* 2^2 = 4 */
4115 expressionS saved_loc
;
4116 expressionS
* emit_val
;
4118 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4120 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4121 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4123 xtensa_switch_to_literal_fragment (&state
);
4125 emit_val
= &insn
->tok
[0];
4126 if (emit_val
->X_op
== O_big
)
4128 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4131 /* This happens when someone writes a "movi a2, big_number". */
4132 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4133 _("invalid immediate"));
4134 xtensa_restore_emit_state (&state
);
4139 /* Force a 4-byte align here. Note that this opens a new frag, so all
4140 literals done with this function have a frag to themselves. That's
4141 important for the way text section literals work. */
4142 frag_align (litalign
, 0, 0);
4143 record_alignment (now_seg
, litalign
);
4145 switch (emit_val
->X_op
)
4155 p
= frag_more (litsize
);
4156 xtensa_set_frag_assembly_state (frag_now
);
4157 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4158 if (emit_val
->X_add_symbol
)
4159 emit_val
->X_op
= O_symbol
;
4161 emit_val
->X_op
= O_constant
;
4162 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4163 litsize
, emit_val
, pcrel
, reloc
);
4167 emit_expr (emit_val
, litsize
);
4171 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4172 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4173 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4174 lit_sym
= frag_now
->fr_symbol
;
4177 xtensa_restore_emit_state (&state
);
4183 xg_assemble_literal_space (/* const */ int size
, int slot
)
4186 /* We might have to do something about this alignment. It only
4187 takes effect if something is placed here. */
4188 offsetT litalign
= 2; /* 2^2 = 4 */
4189 fragS
*lit_saved_frag
;
4191 gas_assert (size
% 4 == 0);
4193 xtensa_switch_to_literal_fragment (&state
);
4195 /* Force a 4-byte align here. */
4196 frag_align (litalign
, 0, 0);
4197 record_alignment (now_seg
, litalign
);
4201 lit_saved_frag
= frag_now
;
4202 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4203 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4204 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4207 xtensa_restore_emit_state (&state
);
4208 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4212 /* Put in a fixup record based on the opcode.
4213 Return TRUE on success. */
4216 xg_add_opcode_fix (TInsn
*tinsn
,
4224 xtensa_opcode opcode
= tinsn
->opcode
;
4225 bfd_reloc_code_real_type reloc
;
4226 reloc_howto_type
*howto
;
4230 reloc
= BFD_RELOC_NONE
;
4232 /* First try the special cases for "alternate" relocs. */
4233 if (opcode
== xtensa_l32r_opcode
)
4235 if (fragP
->tc_frag_data
.use_absolute_literals
)
4236 reloc
= encode_alt_reloc (slot
);
4238 else if (opcode
== xtensa_const16_opcode
)
4240 if (exp
->X_op
== O_lo16
)
4242 reloc
= encode_reloc (slot
);
4243 exp
->X_op
= O_symbol
;
4245 else if (exp
->X_op
== O_hi16
)
4247 reloc
= encode_alt_reloc (slot
);
4248 exp
->X_op
= O_symbol
;
4252 if (opnum
!= get_relaxable_immed (opcode
))
4254 as_bad (_("invalid relocation for operand %i of '%s'"),
4255 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4259 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4260 into the symbol table where the generic portions of the assembler
4261 won't know what to do with them. */
4262 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4264 as_bad (_("invalid expression for operand %i of '%s'"),
4265 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4269 /* Next try the generic relocs. */
4270 if (reloc
== BFD_RELOC_NONE
)
4271 reloc
= encode_reloc (slot
);
4272 if (reloc
== BFD_RELOC_NONE
)
4274 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4278 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4281 as_bad (_("undefined symbol for opcode \"%s\""),
4282 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4286 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4287 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4288 howto
->pc_relative
, reloc
);
4289 the_fix
->fx_no_overflow
= 1;
4290 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4291 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4292 the_fix
->tc_fix_data
.slot
= slot
;
4299 xg_emit_insn_to_buf (TInsn
*tinsn
,
4303 bfd_boolean build_fix
)
4305 static xtensa_insnbuf insnbuf
= NULL
;
4306 bfd_boolean has_symbolic_immed
= FALSE
;
4307 bfd_boolean ok
= TRUE
;
4310 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4312 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4313 if (has_symbolic_immed
&& build_fix
)
4316 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4317 int slot
= xg_get_single_slot (tinsn
->opcode
);
4318 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4319 expressionS
*exp
= &tinsn
->tok
[opnum
];
4321 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4324 fragP
->tc_frag_data
.is_insn
= TRUE
;
4325 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4326 (unsigned char *) buf
, 0);
4332 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4334 symbolS
*sym
= get_special_literal_symbol ();
4338 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4339 for (i
= 0; i
< insn
->ntok
; i
++)
4340 if (insn
->tok
[i
].X_add_symbol
== sym
)
4341 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4347 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4349 symbolS
*sym
= get_special_label_symbol ();
4351 for (i
= 0; i
< insn
->ntok
; i
++)
4352 if (insn
->tok
[i
].X_add_symbol
== sym
)
4353 insn
->tok
[i
].X_add_symbol
= label_sym
;
4358 /* Return TRUE if the instruction can write to the specified
4359 integer register. */
4362 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4366 xtensa_isa isa
= xtensa_default_isa
;
4368 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4370 for (i
= 0; i
< num_ops
; i
++)
4373 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4374 if ((inout
== 'o' || inout
== 'm')
4375 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4377 xtensa_regfile opnd_rf
=
4378 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4379 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4381 if ((insn
->tok
[i
].X_op
== O_register
)
4382 && (insn
->tok
[i
].X_add_number
== regnum
))
4392 is_bad_loopend_opcode (const TInsn
*tinsn
)
4394 xtensa_opcode opcode
= tinsn
->opcode
;
4396 if (opcode
== XTENSA_UNDEFINED
)
4399 if (opcode
== xtensa_call0_opcode
4400 || opcode
== xtensa_callx0_opcode
4401 || opcode
== xtensa_call4_opcode
4402 || opcode
== xtensa_callx4_opcode
4403 || opcode
== xtensa_call8_opcode
4404 || opcode
== xtensa_callx8_opcode
4405 || opcode
== xtensa_call12_opcode
4406 || opcode
== xtensa_callx12_opcode
4407 || opcode
== xtensa_isync_opcode
4408 || opcode
== xtensa_ret_opcode
4409 || opcode
== xtensa_ret_n_opcode
4410 || opcode
== xtensa_retw_opcode
4411 || opcode
== xtensa_retw_n_opcode
4412 || opcode
== xtensa_waiti_opcode
4413 || opcode
== xtensa_rsr_lcount_opcode
)
4420 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4421 This allows the debugger to add unaligned labels.
4422 Also, the assembler generates stabs labels that need
4423 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4426 is_unaligned_label (symbolS
*sym
)
4428 const char *name
= S_GET_NAME (sym
);
4429 static size_t fake_size
= 0;
4433 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4436 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4438 fake_size
= strlen (FAKE_LABEL_NAME
);
4441 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4442 && (name
[fake_size
] == 'F'
4443 || name
[fake_size
] == 'L'
4444 || (name
[fake_size
] == 'e'
4445 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4453 next_non_empty_frag (const fragS
*fragP
)
4455 fragS
*next_fragP
= fragP
->fr_next
;
4457 /* Sometimes an empty will end up here due storage allocation issues.
4458 So we have to skip until we find something legit. */
4459 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4460 next_fragP
= next_fragP
->fr_next
;
4462 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4470 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4472 xtensa_opcode out_opcode
;
4473 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4475 if (next_fragP
== NULL
)
4478 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4479 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4481 *opcode
= out_opcode
;
4489 frag_format_size (const fragS
*fragP
)
4491 static xtensa_insnbuf insnbuf
= NULL
;
4492 xtensa_isa isa
= xtensa_default_isa
;
4497 insnbuf
= xtensa_insnbuf_alloc (isa
);
4500 return XTENSA_UNDEFINED
;
4502 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4503 (unsigned char *) fragP
->fr_literal
, 0);
4505 fmt
= xtensa_format_decode (isa
, insnbuf
);
4506 if (fmt
== XTENSA_UNDEFINED
)
4507 return XTENSA_UNDEFINED
;
4508 fmt_size
= xtensa_format_length (isa
, fmt
);
4510 /* If the next format won't be changing due to relaxation, just
4511 return the length of the first format. */
4512 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4515 /* If during relaxation we have to pull an instruction out of a
4516 multi-slot instruction, we will return the more conservative
4517 number. This works because alignment on bigger instructions
4518 is more restrictive than alignment on smaller instructions.
4519 This is more conservative than we would like, but it happens
4522 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4525 /* If we aren't doing one of our own relaxations or it isn't
4526 slot-based, then the insn size won't change. */
4527 if (fragP
->fr_type
!= rs_machine_dependent
)
4529 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4532 /* If an instruction is about to grow, return the longer size. */
4533 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4534 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4535 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4537 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4538 instruction in the relaxed version is of length 3. (The case
4539 where we have to pull the instruction out of a FLIX bundle
4540 is handled conservatively above.) However, frags with opcodes
4541 that are expanding to wide branches end up having formats that
4542 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4543 we can't tell directly what format the relaxer picked. This
4544 is a wart in the design of the relaxer that should someday be
4545 fixed, but would require major changes, or at least should
4546 be accompanied by major changes to make use of that data.
4548 In any event, we can tell that we are expanding from a single-slot
4549 format to a wider one with the logic below. */
4552 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4554 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4556 if (relaxed_size
== xtensa_format_length (isa
, i
))
4557 return relaxed_size
;
4563 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4564 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4571 next_frag_format_size (const fragS
*fragP
)
4573 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4574 return frag_format_size (next_fragP
);
4578 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4579 required two-byte instructions to be treated as three-byte instructions
4580 for loop instruction alignment. This restriction was removed beginning
4581 with Xtensa LX. Now the only requirement on loop instruction alignment
4582 is that the first instruction of the loop must appear at an address that
4583 does not cross a fetch boundary. */
4586 get_loop_align_size (int insn_size
)
4588 if (insn_size
== XTENSA_UNDEFINED
)
4589 return xtensa_fetch_width
;
4591 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4598 /* If the next legit fragment is an end-of-loop marker,
4599 switch its state so it will instantiate a NOP. */
4602 update_next_frag_state (fragS
*fragP
)
4604 fragS
*next_fragP
= fragP
->fr_next
;
4605 fragS
*new_target
= NULL
;
4609 /* We are guaranteed there will be one of these... */
4610 while (!(next_fragP
->fr_type
== rs_machine_dependent
4611 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4612 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4613 next_fragP
= next_fragP
->fr_next
;
4615 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4616 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4617 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4619 /* ...and one of these. */
4620 new_target
= next_fragP
->fr_next
;
4621 while (!(new_target
->fr_type
== rs_machine_dependent
4622 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4623 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4624 new_target
= new_target
->fr_next
;
4626 gas_assert (new_target
->fr_type
== rs_machine_dependent
4627 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4628 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4631 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4633 if (next_fragP
->fr_type
== rs_machine_dependent
4634 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4636 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4640 next_fragP
= next_fragP
->fr_next
;
4646 next_frag_is_branch_target (const fragS
*fragP
)
4648 /* Sometimes an empty will end up here due to storage allocation issues,
4649 so we have to skip until we find something legit. */
4650 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4652 if (fragP
->tc_frag_data
.is_branch_target
)
4654 if (fragP
->fr_fix
!= 0)
4662 next_frag_is_loop_target (const fragS
*fragP
)
4664 /* Sometimes an empty will end up here due storage allocation issues.
4665 So we have to skip until we find something legit. */
4666 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4668 if (fragP
->tc_frag_data
.is_loop_target
)
4670 if (fragP
->fr_fix
!= 0)
4677 /* As specified in the relaxation table, when a loop instruction is
4678 relaxed, there are 24 bytes between the loop instruction itself and
4679 the first instruction in the loop. */
4681 #define RELAXED_LOOP_INSN_BYTES 24
4684 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4686 const fragS
*next_fragp
= fragp
->fr_next
;
4687 xtensa_opcode next_opcode
;
4689 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4692 /* Sometimes an empty will end up here due to storage allocation issues,
4693 so we have to skip until we find something legit. */
4694 while (next_fragp
->fr_fix
== 0)
4695 next_fragp
= next_fragp
->fr_next
;
4697 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4700 /* There is some implicit knowledge encoded in here.
4701 The LOOP instructions that are NOT RELAX_IMMED have
4702 been relaxed. Note that we can assume that the LOOP
4703 instruction is in slot 0 because loops aren't bundleable. */
4704 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4705 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4711 /* Mark a location where we can later insert literal frags. Update
4712 the section's literal_pool_loc, so subsequent literals can be
4713 placed nearest to their use. */
4716 xtensa_mark_literal_pool_location (void)
4718 /* Any labels pointing to the current location need
4719 to be adjusted to after the literal pool. */
4721 fragS
*pool_location
;
4723 if (use_literal_section
)
4726 /* We stash info in these frags so we can later move the literal's
4727 fixes into this frchain's fix list. */
4728 pool_location
= frag_now
;
4729 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4730 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4731 frag_variant (rs_machine_dependent
, 0, 0,
4732 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4733 xtensa_set_frag_assembly_state (frag_now
);
4734 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4735 frag_variant (rs_machine_dependent
, 0, 0,
4736 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4737 xtensa_set_frag_assembly_state (frag_now
);
4739 /* Now put a frag into the literal pool that points to this location. */
4740 set_literal_pool_location (now_seg
, pool_location
);
4741 xtensa_switch_to_non_abs_literal_fragment (&s
);
4742 frag_align (2, 0, 0);
4743 record_alignment (now_seg
, 2);
4745 /* Close whatever frag is there. */
4746 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4747 xtensa_set_frag_assembly_state (frag_now
);
4748 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4749 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4750 xtensa_restore_emit_state (&s
);
4751 xtensa_set_frag_assembly_state (frag_now
);
4755 /* Build a nop of the correct size into tinsn. */
4758 build_nop (TInsn
*tinsn
, int size
)
4764 tinsn
->opcode
= xtensa_nop_n_opcode
;
4766 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4767 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4771 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4773 tinsn
->opcode
= xtensa_or_opcode
;
4774 set_expr_const (&tinsn
->tok
[0], 1);
4775 set_expr_const (&tinsn
->tok
[1], 1);
4776 set_expr_const (&tinsn
->tok
[2], 1);
4780 tinsn
->opcode
= xtensa_nop_opcode
;
4782 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4787 /* Assemble a NOP of the requested size in the buffer. User must have
4788 allocated "buf" with at least "size" bytes. */
4791 assemble_nop (int size
, char *buf
)
4793 static xtensa_insnbuf insnbuf
= NULL
;
4796 build_nop (&tinsn
, size
);
4799 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4801 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4802 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4803 (unsigned char *) buf
, 0);
4807 /* Return the number of bytes for the offset of the expanded loop
4808 instruction. This should be incorporated into the relaxation
4809 specification but is hard-coded here. This is used to auto-align
4810 the loop instruction. It is invalid to call this function if the
4811 configuration does not have loops or if the opcode is not a loop
4815 get_expanded_loop_offset (xtensa_opcode opcode
)
4817 /* This is the OFFSET of the loop instruction in the expanded loop.
4818 This MUST correspond directly to the specification of the loop
4819 expansion. It will be validated on fragment conversion. */
4820 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4821 if (opcode
== xtensa_loop_opcode
)
4823 if (opcode
== xtensa_loopnez_opcode
)
4825 if (opcode
== xtensa_loopgtz_opcode
)
4827 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4833 get_literal_pool_location (segT seg
)
4835 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4840 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4842 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4846 /* Set frag assembly state should be called when a new frag is
4847 opened and after a frag has been closed. */
4850 xtensa_set_frag_assembly_state (fragS
*fragP
)
4852 if (!density_supported
)
4853 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4855 /* This function is called from subsegs_finish, which is called
4856 after xtensa_end, so we can't use "use_transform" or
4857 "use_schedule" here. */
4858 if (!directive_state
[directive_transform
])
4859 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4860 if (directive_state
[directive_longcalls
])
4861 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4862 fragP
->tc_frag_data
.use_absolute_literals
=
4863 directive_state
[directive_absolute_literals
];
4864 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4869 relaxable_section (asection
*sec
)
4871 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4872 && strcmp (sec
->name
, ".eh_frame") != 0);
4877 xtensa_mark_frags_for_org (void)
4881 /* Walk over each fragment of all of the current segments. If we find
4882 a .org frag in any of the segments, mark all frags prior to it as
4883 "no transform", which will prevent linker optimizations from messing
4884 up the .org distance. This should be done after
4885 xtensa_find_unmarked_state_frags, because we don't want to worry here
4886 about that function trashing the data we save here. */
4888 for (seclist
= &stdoutput
->sections
;
4889 seclist
&& *seclist
;
4890 seclist
= &(*seclist
)->next
)
4892 segT sec
= *seclist
;
4893 segment_info_type
*seginfo
;
4896 flags
= bfd_get_section_flags (stdoutput
, sec
);
4897 if (flags
& SEC_DEBUGGING
)
4899 if (!(flags
& SEC_ALLOC
))
4902 seginfo
= seg_info (sec
);
4903 if (seginfo
&& seginfo
->frchainP
)
4905 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4906 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4907 fragP
= fragP
->fr_next
)
4909 /* cvt_frag_to_fill has changed the fr_type of org frags to
4910 rs_fill, so use the value as cached in rs_subtype here. */
4911 if (fragP
->fr_subtype
== RELAX_ORG
)
4913 while (last_fragP
!= fragP
->fr_next
)
4915 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4916 last_fragP
= last_fragP
->fr_next
;
4926 xtensa_find_unmarked_state_frags (void)
4930 /* Walk over each fragment of all of the current segments. For each
4931 unmarked fragment, mark it with the same info as the previous
4933 for (seclist
= &stdoutput
->sections
;
4934 seclist
&& *seclist
;
4935 seclist
= &(*seclist
)->next
)
4937 segT sec
= *seclist
;
4938 segment_info_type
*seginfo
;
4941 flags
= bfd_get_section_flags (stdoutput
, sec
);
4942 if (flags
& SEC_DEBUGGING
)
4944 if (!(flags
& SEC_ALLOC
))
4947 seginfo
= seg_info (sec
);
4948 if (seginfo
&& seginfo
->frchainP
)
4950 fragS
*last_fragP
= 0;
4951 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4952 fragP
= fragP
->fr_next
)
4954 if (fragP
->fr_fix
!= 0
4955 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4957 if (last_fragP
== 0)
4959 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4960 _("assembly state not set for first frag in section %s"),
4965 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4966 fragP
->tc_frag_data
.is_no_density
=
4967 last_fragP
->tc_frag_data
.is_no_density
;
4968 fragP
->tc_frag_data
.is_no_transform
=
4969 last_fragP
->tc_frag_data
.is_no_transform
;
4970 fragP
->tc_frag_data
.use_longcalls
=
4971 last_fragP
->tc_frag_data
.use_longcalls
;
4972 fragP
->tc_frag_data
.use_absolute_literals
=
4973 last_fragP
->tc_frag_data
.use_absolute_literals
;
4976 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4985 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4987 void *unused ATTRIBUTE_UNUSED
)
4989 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4990 segment_info_type
*seginfo
= seg_info (sec
);
4991 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4993 if (flags
& SEC_CODE
)
4995 xtensa_isa isa
= xtensa_default_isa
;
4996 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4997 while (frag
!= NULL
)
4999 if (frag
->tc_frag_data
.is_branch_target
)
5002 addressT branch_align
, frag_addr
;
5005 xtensa_insnbuf_from_chars
5006 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5007 fmt
= xtensa_format_decode (isa
, insnbuf
);
5008 op_size
= xtensa_format_length (isa
, fmt
);
5009 branch_align
= 1 << branch_align_power (sec
);
5010 frag_addr
= frag
->fr_address
% branch_align
;
5011 if (frag_addr
+ op_size
> branch_align
)
5012 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5013 _("unaligned branch target: %d bytes at 0x%lx"),
5014 op_size
, (long) frag
->fr_address
);
5016 frag
= frag
->fr_next
;
5018 xtensa_insnbuf_free (isa
, insnbuf
);
5024 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5026 void *unused ATTRIBUTE_UNUSED
)
5028 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5029 segment_info_type
*seginfo
= seg_info (sec
);
5030 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5031 xtensa_isa isa
= xtensa_default_isa
;
5033 if (flags
& SEC_CODE
)
5035 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5036 while (frag
!= NULL
)
5038 if (frag
->tc_frag_data
.is_first_loop_insn
)
5044 if (frag
->fr_fix
== 0)
5045 frag
= next_non_empty_frag (frag
);
5049 xtensa_insnbuf_from_chars
5050 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5051 fmt
= xtensa_format_decode (isa
, insnbuf
);
5052 op_size
= xtensa_format_length (isa
, fmt
);
5053 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5055 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5056 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5057 _("unaligned loop: %d bytes at 0x%lx"),
5058 op_size
, (long) frag
->fr_address
);
5061 frag
= frag
->fr_next
;
5063 xtensa_insnbuf_free (isa
, insnbuf
);
5069 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5071 xtensa_isa isa
= xtensa_default_isa
;
5072 static xtensa_insnbuf insnbuf
= NULL
;
5073 static xtensa_insnbuf slotbuf
= NULL
;
5076 bfd_boolean alt_reloc
;
5077 xtensa_opcode opcode
;
5078 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5080 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5082 as_fatal (_("unexpected fix"));
5086 insnbuf
= xtensa_insnbuf_alloc (isa
);
5087 slotbuf
= xtensa_insnbuf_alloc (isa
);
5090 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5091 fmt
= xtensa_format_decode (isa
, insnbuf
);
5092 if (fmt
== XTENSA_UNDEFINED
)
5093 as_fatal (_("undecodable fix"));
5094 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5095 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5096 if (opcode
== XTENSA_UNDEFINED
)
5097 as_fatal (_("undecodable fix"));
5099 /* CONST16 immediates are not PC-relative, despite the fact that we
5100 reuse the normal PC-relative operand relocations for the low part
5101 of a CONST16 operand. */
5102 if (opcode
== xtensa_const16_opcode
)
5105 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5106 get_relaxable_immed (opcode
), val
,
5107 fixP
->fx_file
, fixP
->fx_line
);
5109 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5110 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5116 /* External Functions and Other GAS Hooks. */
5119 xtensa_target_format (void)
5121 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5126 xtensa_file_arch_init (bfd
*abfd
)
5128 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5133 md_number_to_chars (char *buf
, valueT val
, int n
)
5135 if (target_big_endian
)
5136 number_to_chars_bigendian (buf
, val
, n
);
5138 number_to_chars_littleendian (buf
, val
, n
);
5142 /* This function is called once, at assembler startup time. It should
5143 set up all the tables, etc. that the MD part of the assembler will
5149 segT current_section
= now_seg
;
5150 int current_subsec
= now_subseg
;
5154 xtensa_default_isa
= xtensa_isa_init (0, 0);
5155 isa
= xtensa_default_isa
;
5159 /* Set up the literal sections. */
5160 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5162 subseg_set (current_section
, current_subsec
);
5164 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5165 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5166 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5167 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5168 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5169 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5170 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5171 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5172 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5173 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5174 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5175 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5176 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5177 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5178 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5179 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5180 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5181 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5182 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5183 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5184 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5185 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5186 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5187 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5188 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5189 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5190 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5191 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5192 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5193 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5194 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5196 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5198 int format_slots
= xtensa_format_num_slots (isa
, i
);
5199 if (format_slots
> config_max_slots
)
5200 config_max_slots
= format_slots
;
5203 xg_init_vinsn (&cur_vinsn
);
5205 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5207 init_op_placement_info_table ();
5209 /* Set up the assembly state. */
5210 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5211 xtensa_set_frag_assembly_state (frag_now
);
5215 /* TC_INIT_FIX_DATA hook */
5218 xtensa_init_fix_data (fixS
*x
)
5220 x
->tc_fix_data
.slot
= 0;
5221 x
->tc_fix_data
.X_add_symbol
= NULL
;
5222 x
->tc_fix_data
.X_add_number
= 0;
5226 /* tc_frob_label hook */
5229 xtensa_frob_label (symbolS
*sym
)
5233 if (cur_vinsn
.inside_bundle
)
5235 as_bad (_("labels are not valid inside bundles"));
5239 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5241 /* Since the label was already attached to a frag associated with the
5242 previous basic block, it now needs to be reset to the current frag. */
5243 symbol_set_frag (sym
, frag_now
);
5244 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5246 if (generating_literals
)
5247 xtensa_add_literal_sym (sym
);
5249 xtensa_add_insn_label (sym
);
5251 if (symbol_get_tc (sym
)->is_loop_target
)
5253 if ((get_last_insn_flags (now_seg
, now_subseg
)
5254 & FLAG_IS_BAD_LOOPEND
) != 0)
5255 as_bad (_("invalid last instruction for a zero-overhead loop"));
5257 xtensa_set_frag_assembly_state (frag_now
);
5258 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5259 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5261 xtensa_set_frag_assembly_state (frag_now
);
5262 xtensa_move_labels (frag_now
, 0);
5265 /* No target aligning in the absolute section. */
5266 if (now_seg
!= absolute_section
5267 && !is_unaligned_label (sym
)
5268 && !generating_literals
)
5270 xtensa_set_frag_assembly_state (frag_now
);
5272 if (do_align_targets ())
5273 frag_var (rs_machine_dependent
, 0, (int) freq
,
5274 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5275 frag_now
->fr_offset
, NULL
);
5277 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5278 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5279 xtensa_set_frag_assembly_state (frag_now
);
5280 xtensa_move_labels (frag_now
, 0);
5283 /* We need to mark the following properties even if we aren't aligning. */
5285 /* If the label is already known to be a branch target, i.e., a
5286 forward branch, mark the frag accordingly. Backward branches
5287 are handled by xg_add_branch_and_loop_targets. */
5288 if (symbol_get_tc (sym
)->is_branch_target
)
5289 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5291 /* Loops only go forward, so they can be identified here. */
5292 if (symbol_get_tc (sym
)->is_loop_target
)
5293 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5295 dwarf2_emit_label (sym
);
5299 /* tc_unrecognized_line hook */
5302 xtensa_unrecognized_line (int ch
)
5307 if (cur_vinsn
.inside_bundle
== 0)
5309 /* PR8110: Cannot emit line number info inside a FLIX bundle
5310 when using --gstabs. Temporarily disable debug info. */
5311 generate_lineno_debug ();
5312 if (debug_type
== DEBUG_STABS
)
5314 xt_saved_debug_type
= debug_type
;
5315 debug_type
= DEBUG_NONE
;
5318 cur_vinsn
.inside_bundle
= 1;
5322 as_bad (_("extra opening brace"));
5328 if (cur_vinsn
.inside_bundle
)
5329 finish_vinsn (&cur_vinsn
);
5332 as_bad (_("extra closing brace"));
5337 as_bad (_("syntax error"));
5344 /* md_flush_pending_output hook */
5347 xtensa_flush_pending_output (void)
5349 /* This line fixes a bug where automatically generated gstabs info
5350 separates a function label from its entry instruction, ending up
5351 with the literal position between the function label and the entry
5352 instruction and crashing code. It only happens with --gstabs and
5353 --text-section-literals, and when several other obscure relaxation
5354 conditions are met. */
5355 if (outputting_stabs_line_debug
)
5358 if (cur_vinsn
.inside_bundle
)
5359 as_bad (_("missing closing brace"));
5361 /* If there is a non-zero instruction fragment, close it. */
5362 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5364 frag_wane (frag_now
);
5366 xtensa_set_frag_assembly_state (frag_now
);
5368 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5370 xtensa_clear_insn_labels ();
5374 /* We had an error while parsing an instruction. The string might look
5375 like this: "insn arg1, arg2 }". If so, we need to see the closing
5376 brace and reset some fields. Otherwise, the vinsn never gets closed
5377 and the num_slots field will grow past the end of the array of slots,
5378 and bad things happen. */
5381 error_reset_cur_vinsn (void)
5383 if (cur_vinsn
.inside_bundle
)
5385 if (*input_line_pointer
== '}'
5386 || *(input_line_pointer
- 1) == '}'
5387 || *(input_line_pointer
- 2) == '}')
5388 xg_clear_vinsn (&cur_vinsn
);
5394 md_assemble (char *str
)
5396 xtensa_isa isa
= xtensa_default_isa
;
5399 bfd_boolean has_underbar
= FALSE
;
5400 char *arg_strings
[MAX_INSN_ARGS
];
5402 TInsn orig_insn
; /* Original instruction from the input. */
5404 tinsn_init (&orig_insn
);
5406 /* Split off the opcode. */
5407 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5408 opname
= xmalloc (opnamelen
+ 1);
5409 memcpy (opname
, str
, opnamelen
);
5410 opname
[opnamelen
] = '\0';
5412 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5415 as_bad (_("syntax error"));
5419 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5422 /* Check for an underbar prefix. */
5425 has_underbar
= TRUE
;
5429 orig_insn
.insn_type
= ITYPE_INSN
;
5431 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5432 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5434 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5435 extra argument and set the opcode to "CALLXn". */
5436 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5437 && strncasecmp (opname
, "callx", 5) == 0)
5439 unsigned long window_size
;
5442 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5443 if (suffix
!= opname
+ 5
5444 && (window_size
== 0
5447 || window_size
== 12)
5448 && strcasecmp (suffix
, ".tls") == 0)
5450 switch (window_size
)
5452 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5453 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5454 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5455 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5459 as_bad (_("wrong number of operands for '%s'"), opname
);
5462 bfd_reloc_code_real_type reloc
;
5463 char *old_input_line_pointer
;
5464 expressionS
*tok
= &orig_insn
.extra_arg
;
5466 old_input_line_pointer
= input_line_pointer
;
5467 input_line_pointer
= arg_strings
[num_args
- 1];
5470 if (tok
->X_op
== O_symbol
5471 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5472 == BFD_RELOC_XTENSA_TLS_CALL
))
5473 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5475 as_bad (_("bad relocation expression for '%s'"), opname
);
5477 input_line_pointer
= old_input_line_pointer
;
5483 /* Special case: Check for "j.l" psuedo op. */
5484 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5485 && strncasecmp (opname
, "j.l", 3) == 0)
5488 as_bad (_("wrong number of operands for '%s'"), opname
);
5491 char *old_input_line_pointer
;
5492 expressionS
*tok
= &orig_insn
.extra_arg
;
5494 old_input_line_pointer
= input_line_pointer
;
5495 input_line_pointer
= arg_strings
[num_args
- 1];
5497 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5498 input_line_pointer
= old_input_line_pointer
;
5501 orig_insn
.opcode
= xtensa_j_opcode
;
5505 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5507 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5508 if (fmt
== XTENSA_UNDEFINED
)
5510 as_bad (_("unknown opcode or format name '%s'"), opname
);
5511 error_reset_cur_vinsn ();
5514 if (!cur_vinsn
.inside_bundle
)
5516 as_bad (_("format names only valid inside bundles"));
5517 error_reset_cur_vinsn ();
5520 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5521 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5523 cur_vinsn
.format
= fmt
;
5524 free (has_underbar
? opname
- 1 : opname
);
5525 error_reset_cur_vinsn ();
5529 /* Parse the arguments. */
5530 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5532 as_bad (_("syntax error"));
5533 error_reset_cur_vinsn ();
5537 /* Free the opcode and argument strings, now that they've been parsed. */
5538 free (has_underbar
? opname
- 1 : opname
);
5540 while (num_args
-- > 0)
5541 free (arg_strings
[num_args
]);
5543 /* Get expressions for invisible operands. */
5544 if (get_invisible_operands (&orig_insn
))
5546 error_reset_cur_vinsn ();
5550 /* Check for the right number and type of arguments. */
5551 if (tinsn_check_arguments (&orig_insn
))
5553 error_reset_cur_vinsn ();
5557 /* Record the line number for each TInsn, because a FLIX bundle may be
5558 spread across multiple input lines and individual instructions may be
5559 moved around in some cases. */
5560 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5561 dwarf2_where (&orig_insn
.debug_line
);
5562 dwarf2_consume_line_info ();
5564 xg_add_branch_and_loop_targets (&orig_insn
);
5566 /* Check that immediate value for ENTRY is >= 16. */
5567 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5569 expressionS
*exp
= &orig_insn
.tok
[2];
5570 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5571 as_warn (_("entry instruction with stack decrement < 16"));
5575 assemble_tokens (opcode, tok, ntok);
5576 expand the tokens from the orig_insn into the
5577 stack of instructions that will not expand
5578 unless required at relaxation time. */
5580 if (!cur_vinsn
.inside_bundle
)
5581 emit_single_op (&orig_insn
);
5582 else /* We are inside a bundle. */
5584 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5585 cur_vinsn
.num_slots
++;
5586 if (*input_line_pointer
== '}'
5587 || *(input_line_pointer
- 1) == '}'
5588 || *(input_line_pointer
- 2) == '}')
5589 finish_vinsn (&cur_vinsn
);
5592 /* We've just emitted a new instruction so clear the list of labels. */
5593 xtensa_clear_insn_labels ();
5595 xtensa_check_frag_count ();
5599 /* HANDLE_ALIGN hook */
5601 /* For a .align directive, we mark the previous block with the alignment
5602 information. This will be placed in the object file in the
5603 property section corresponding to this section. */
5606 xtensa_handle_align (fragS
*fragP
)
5609 && ! fragP
->tc_frag_data
.is_literal
5610 && (fragP
->fr_type
== rs_align
5611 || fragP
->fr_type
== rs_align_code
)
5612 && fragP
->fr_offset
> 0
5613 && now_seg
!= bss_section
)
5615 fragP
->tc_frag_data
.is_align
= TRUE
;
5616 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5619 if (fragP
->fr_type
== rs_align_test
)
5622 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5624 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5625 _("unaligned entry instruction"));
5628 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5629 fragP
->fr_subtype
= RELAX_ORG
;
5633 /* TC_FRAG_INIT hook */
5636 xtensa_frag_init (fragS
*frag
)
5638 xtensa_set_frag_assembly_state (frag
);
5643 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5649 /* Round up a section size to the appropriate boundary. */
5652 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5654 return size
; /* Byte alignment is fine. */
5659 md_pcrel_from (fixS
*fixP
)
5662 static xtensa_insnbuf insnbuf
= NULL
;
5663 static xtensa_insnbuf slotbuf
= NULL
;
5666 xtensa_opcode opcode
;
5669 xtensa_isa isa
= xtensa_default_isa
;
5670 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5671 bfd_boolean alt_reloc
;
5673 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5676 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5681 insnbuf
= xtensa_insnbuf_alloc (isa
);
5682 slotbuf
= xtensa_insnbuf_alloc (isa
);
5685 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5686 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5687 fmt
= xtensa_format_decode (isa
, insnbuf
);
5689 if (fmt
== XTENSA_UNDEFINED
)
5690 as_fatal (_("bad instruction format"));
5692 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5693 as_fatal (_("invalid relocation"));
5695 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5696 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5698 /* Check for "alternate" relocations (operand not specified). None
5699 of the current uses for these are really PC-relative. */
5700 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5702 if (opcode
!= xtensa_l32r_opcode
5703 && opcode
!= xtensa_const16_opcode
)
5704 as_fatal (_("invalid relocation for '%s' instruction"),
5705 xtensa_opcode_name (isa
, opcode
));
5709 opnum
= get_relaxable_immed (opcode
);
5711 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5712 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5714 as_bad_where (fixP
->fx_file
,
5716 _("invalid relocation for operand %d of '%s'"),
5717 opnum
, xtensa_opcode_name (isa
, opcode
));
5720 return 0 - opnd_value
;
5724 /* TC_FORCE_RELOCATION hook */
5727 xtensa_force_relocation (fixS
*fix
)
5729 switch (fix
->fx_r_type
)
5731 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5732 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5733 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5734 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5735 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5736 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5737 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5738 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5739 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5740 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5741 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5742 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5743 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5744 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5745 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5746 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5752 if (linkrelax
&& fix
->fx_addsy
5753 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5756 return generic_force_reloc (fix
);
5760 /* TC_VALIDATE_FIX_SUB hook */
5763 xtensa_validate_fix_sub (fixS
*fix
)
5765 segT add_symbol_segment
, sub_symbol_segment
;
5767 /* The difference of two symbols should be resolved by the assembler when
5768 linkrelax is not set. If the linker may relax the section containing
5769 the symbols, then an Xtensa DIFF relocation must be generated so that
5770 the linker knows to adjust the difference value. */
5771 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5774 /* Make sure both symbols are in the same segment, and that segment is
5775 "normal" and relaxable. If the segment is not "normal", then the
5776 fix is not valid. If the segment is not "relaxable", then the fix
5777 should have been handled earlier. */
5778 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5779 if (! SEG_NORMAL (add_symbol_segment
) ||
5780 ! relaxable_section (add_symbol_segment
))
5782 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5783 return (sub_symbol_segment
== add_symbol_segment
);
5787 /* NO_PSEUDO_DOT hook */
5789 /* This function has nothing to do with pseudo dots, but this is the
5790 nearest macro to where the check needs to take place. FIXME: This
5794 xtensa_check_inside_bundle (void)
5796 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5797 as_bad (_("directives are not valid inside bundles"));
5799 /* This function must always return FALSE because it is called via a
5800 macro that has nothing to do with bundling. */
5805 /* md_elf_section_change_hook */
5808 xtensa_elf_section_change_hook (void)
5810 /* Set up the assembly state. */
5811 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5812 xtensa_set_frag_assembly_state (frag_now
);
5816 /* tc_fix_adjustable hook */
5819 xtensa_fix_adjustable (fixS
*fixP
)
5821 /* We need the symbol name for the VTABLE entries. */
5822 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5823 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5830 /* tc_symbol_new_hook */
5832 symbolS
*expr_symbols
= NULL
;
5835 xtensa_symbol_new_hook (symbolS
*sym
)
5837 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5839 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5846 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5848 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5851 /* Subtracted symbols are only allowed for a few relocation types, and
5852 unless linkrelax is enabled, they should not make it to this point. */
5853 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5854 || fixP
->fx_r_type
== BFD_RELOC_16
5855 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5858 switch (fixP
->fx_r_type
)
5860 case BFD_RELOC_32_PCREL
:
5866 switch (fixP
->fx_r_type
)
5869 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5872 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5875 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5881 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5882 - S_GET_VALUE (fixP
->fx_subsy
));
5884 /* The difference value gets written out, and the DIFF reloc
5885 identifies the address of the subtracted symbol (i.e., the one
5886 with the lowest address). */
5888 fixP
->fx_offset
-= val
;
5889 fixP
->fx_subsy
= NULL
;
5891 else if (! fixP
->fx_addsy
)
5898 case BFD_RELOC_XTENSA_PLT
:
5899 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5900 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5903 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5904 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5905 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5906 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5907 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5908 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5909 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5912 case BFD_RELOC_XTENSA_SLOT0_OP
:
5913 case BFD_RELOC_XTENSA_SLOT1_OP
:
5914 case BFD_RELOC_XTENSA_SLOT2_OP
:
5915 case BFD_RELOC_XTENSA_SLOT3_OP
:
5916 case BFD_RELOC_XTENSA_SLOT4_OP
:
5917 case BFD_RELOC_XTENSA_SLOT5_OP
:
5918 case BFD_RELOC_XTENSA_SLOT6_OP
:
5919 case BFD_RELOC_XTENSA_SLOT7_OP
:
5920 case BFD_RELOC_XTENSA_SLOT8_OP
:
5921 case BFD_RELOC_XTENSA_SLOT9_OP
:
5922 case BFD_RELOC_XTENSA_SLOT10_OP
:
5923 case BFD_RELOC_XTENSA_SLOT11_OP
:
5924 case BFD_RELOC_XTENSA_SLOT12_OP
:
5925 case BFD_RELOC_XTENSA_SLOT13_OP
:
5926 case BFD_RELOC_XTENSA_SLOT14_OP
:
5929 /* Write the tentative value of a PC-relative relocation to a
5930 local symbol into the instruction. The value will be ignored
5931 by the linker, and it makes the object file disassembly
5932 readable when all branch targets are encoded in relocations. */
5934 gas_assert (fixP
->fx_addsy
);
5935 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5936 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5938 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5939 - md_pcrel_from (fixP
));
5940 (void) xg_apply_fix_value (fixP
, val
);
5943 else if (! fixP
->fx_addsy
)
5946 if (xg_apply_fix_value (fixP
, val
))
5951 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5952 case BFD_RELOC_XTENSA_TLS_FUNC
:
5953 case BFD_RELOC_XTENSA_TLS_ARG
:
5954 case BFD_RELOC_XTENSA_TLS_CALL
:
5955 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5956 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5957 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5958 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5959 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5960 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5961 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5962 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5963 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5964 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5965 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5966 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5967 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5968 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5969 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5970 /* These all need to be resolved at link-time. Do nothing now. */
5973 case BFD_RELOC_VTABLE_INHERIT
:
5974 case BFD_RELOC_VTABLE_ENTRY
:
5979 as_bad (_("unhandled local relocation fix %s"),
5980 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5986 md_atof (int type
, char *litP
, int *sizeP
)
5988 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5993 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5995 return total_frag_text_expansion (fragP
);
5999 /* Translate internal representation of relocation info to BFD target
6003 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6007 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
6008 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6009 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6010 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6012 /* Make sure none of our internal relocations make it this far.
6013 They'd better have been fully resolved by this point. */
6014 gas_assert ((int) fixp
->fx_r_type
> 0);
6016 reloc
->addend
= fixp
->fx_offset
;
6018 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6019 if (reloc
->howto
== NULL
)
6021 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6022 _("cannot represent `%s' relocation in object file"),
6023 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6024 free (reloc
->sym_ptr_ptr
);
6029 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6030 as_fatal (_("internal error; cannot generate `%s' relocation"),
6031 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6037 /* Checks for resource conflicts between instructions. */
6039 /* The func unit stuff could be implemented as bit-vectors rather
6040 than the iterative approach here. If it ends up being too
6041 slow, we will switch it. */
6044 new_resource_table (void *data
,
6047 unit_num_copies_func uncf
,
6048 opcode_num_units_func onuf
,
6049 opcode_funcUnit_use_unit_func ouuf
,
6050 opcode_funcUnit_use_stage_func ousf
)
6053 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
6055 rt
->cycles
= cycles
;
6056 rt
->allocated_cycles
= cycles
;
6058 rt
->unit_num_copies
= uncf
;
6059 rt
->opcode_num_units
= onuf
;
6060 rt
->opcode_unit_use
= ouuf
;
6061 rt
->opcode_unit_stage
= ousf
;
6063 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6064 for (i
= 0; i
< cycles
; i
++)
6065 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6072 clear_resource_table (resource_table
*rt
)
6075 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6076 for (j
= 0; j
< rt
->num_units
; j
++)
6077 rt
->units
[i
][j
] = 0;
6081 /* We never shrink it, just fake it into thinking so. */
6084 resize_resource_table (resource_table
*rt
, int cycles
)
6088 rt
->cycles
= cycles
;
6089 if (cycles
<= rt
->allocated_cycles
)
6092 old_cycles
= rt
->allocated_cycles
;
6093 rt
->allocated_cycles
= cycles
;
6095 rt
->units
= xrealloc (rt
->units
,
6096 rt
->allocated_cycles
* sizeof (unsigned char *));
6097 for (i
= 0; i
< old_cycles
; i
++)
6098 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6099 rt
->num_units
* sizeof (unsigned char));
6100 for (i
= old_cycles
; i
< cycles
; i
++)
6101 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6106 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6109 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6111 for (i
= 0; i
< uses
; i
++)
6113 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6114 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6115 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6116 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6117 if (copies_in_use
>= copies
)
6125 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6128 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6130 for (i
= 0; i
< uses
; i
++)
6132 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6133 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6134 /* Note that this allows resources to be oversubscribed. That's
6135 essential to the way the optional scheduler works.
6136 resources_available reports when a resource is over-subscribed,
6137 so it's easy to tell. */
6138 rt
->units
[stage
+ cycle
][unit
]++;
6144 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6147 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6149 for (i
= 0; i
< uses
; i
++)
6151 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6152 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6153 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6154 rt
->units
[stage
+ cycle
][unit
]--;
6159 /* Wrapper functions make parameterized resource reservation
6163 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6165 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6171 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6173 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6178 /* Note that this function does not check issue constraints, but
6179 solely whether the hardware is available to execute the given
6180 instructions together. It also doesn't check if the tinsns
6181 write the same state, or access the same tieports. That is
6182 checked by check_t1_t2_reads_and_writes. */
6185 resources_conflict (vliw_insn
*vinsn
)
6188 static resource_table
*rt
= NULL
;
6190 /* This is the most common case by far. Optimize it. */
6191 if (vinsn
->num_slots
== 1)
6196 xtensa_isa isa
= xtensa_default_isa
;
6197 rt
= new_resource_table
6198 (isa
, xtensa_num_pipe_stages
,
6199 xtensa_isa_num_funcUnits (isa
),
6200 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6201 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6202 opcode_funcUnit_use_unit
,
6203 opcode_funcUnit_use_stage
);
6206 clear_resource_table (rt
);
6208 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6210 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6212 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6219 /* finish_vinsn, emit_single_op and helper functions. */
6221 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6222 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6223 static void xg_assemble_vliw_tokens (vliw_insn
*);
6226 /* We have reached the end of a bundle; emit into the frag. */
6229 finish_vinsn (vliw_insn
*vinsn
)
6236 if (find_vinsn_conflicts (vinsn
))
6238 xg_clear_vinsn (vinsn
);
6242 /* First, find a format that works. */
6243 if (vinsn
->format
== XTENSA_UNDEFINED
)
6244 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6246 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6247 && produce_flix
== FLIX_NONE
)
6249 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6250 xg_clear_vinsn (vinsn
);
6254 if (vinsn
->format
== XTENSA_UNDEFINED
)
6256 as_where (&file_name
, &line
);
6257 as_bad_where (file_name
, line
,
6258 _("couldn't find a valid instruction format"));
6259 fprintf (stderr
, _(" ops were: "));
6260 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6261 fprintf (stderr
, _(" %s;"),
6262 xtensa_opcode_name (xtensa_default_isa
,
6263 vinsn
->slots
[i
].opcode
));
6264 fprintf (stderr
, _("\n"));
6265 xg_clear_vinsn (vinsn
);
6269 if (vinsn
->num_slots
6270 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6272 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6273 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6274 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6276 xg_clear_vinsn (vinsn
);
6280 if (resources_conflict (vinsn
))
6282 as_where (&file_name
, &line
);
6283 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6284 fprintf (stderr
, " ops were: ");
6285 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6286 fprintf (stderr
, " %s;",
6287 xtensa_opcode_name (xtensa_default_isa
,
6288 vinsn
->slots
[i
].opcode
));
6289 fprintf (stderr
, "\n");
6290 xg_clear_vinsn (vinsn
);
6294 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6296 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6298 symbolS
*lit_sym
= NULL
;
6300 bfd_boolean e
= FALSE
;
6301 bfd_boolean saved_density
= density_supported
;
6303 /* We don't want to narrow ops inside multi-slot bundles. */
6304 if (vinsn
->num_slots
> 1)
6305 density_supported
= FALSE
;
6307 istack_init (&slotstack
);
6308 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6310 vinsn
->slots
[i
].opcode
=
6311 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6313 vinsn
->slots
[i
].ntok
= 0;
6316 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6322 density_supported
= saved_density
;
6326 xg_clear_vinsn (vinsn
);
6330 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6332 TInsn
*insn
= &slotstack
.insn
[j
];
6333 if (insn
->insn_type
== ITYPE_LITERAL
)
6335 gas_assert (lit_sym
== NULL
);
6336 lit_sym
= xg_assemble_literal (insn
);
6340 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6342 xg_resolve_literals (insn
, lit_sym
);
6343 if (j
!= slotstack
.ninsn
- 1)
6344 emit_single_op (insn
);
6348 if (vinsn
->num_slots
> 1)
6350 if (opcode_fits_format_slot
6351 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6354 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6358 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6359 if (vinsn
->format
== XTENSA_UNDEFINED
)
6360 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6362 vinsn
->slots
[i
].opcode
6363 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6366 vinsn
->slots
[i
].ntok
= 0;
6371 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6372 vinsn
->format
= XTENSA_UNDEFINED
;
6377 /* Now check resource conflicts on the modified bundle. */
6378 if (resources_conflict (vinsn
))
6380 as_where (&file_name
, &line
);
6381 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6382 fprintf (stderr
, " ops were: ");
6383 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6384 fprintf (stderr
, " %s;",
6385 xtensa_opcode_name (xtensa_default_isa
,
6386 vinsn
->slots
[i
].opcode
));
6387 fprintf (stderr
, "\n");
6388 xg_clear_vinsn (vinsn
);
6392 /* First, find a format that works. */
6393 if (vinsn
->format
== XTENSA_UNDEFINED
)
6394 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6396 xg_assemble_vliw_tokens (vinsn
);
6398 xg_clear_vinsn (vinsn
);
6400 xtensa_check_frag_count ();
6404 /* Given an vliw instruction, what conflicts are there in register
6405 usage and in writes to states and queues?
6407 This function does two things:
6408 1. Reports an error when a vinsn contains illegal combinations
6409 of writes to registers states or queues.
6410 2. Marks individual tinsns as not relaxable if the combination
6411 contains antidependencies.
6413 Job 2 handles things like swap semantics in instructions that need
6414 to be relaxed. For example,
6418 normally would be relaxed to
6423 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6425 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6427 then we can't relax it into
6430 { add a0, a1, a0 ; add a2, a0, a4 ; }
6432 because the value of a0 is trashed before the second add can read it. */
6434 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6437 find_vinsn_conflicts (vliw_insn
*vinsn
)
6441 xtensa_isa isa
= xtensa_default_isa
;
6443 gas_assert (!past_xtensa_end
);
6445 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6447 TInsn
*op1
= &vinsn
->slots
[i
];
6448 if (op1
->is_specific_opcode
)
6449 op1
->keep_wide
= TRUE
;
6451 op1
->keep_wide
= FALSE
;
6454 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6456 TInsn
*op1
= &vinsn
->slots
[i
];
6458 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6461 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6465 TInsn
*op2
= &vinsn
->slots
[j
];
6466 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6467 switch (conflict_type
)
6470 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6471 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6472 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6475 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6476 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6477 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6480 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6481 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6482 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6485 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6486 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6487 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6490 /* Everything is OK. */
6493 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6494 || conflict_type
== 'a');
6501 as_bad (_("multiple branches or jumps in the same bundle"));
6509 /* Check how the state used by t1 and t2 relate.
6512 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6513 case B: no relationship between what is read and written (both could
6514 read the same reg though)
6515 case C: t1 writes a register t2 writes (a register conflict within a
6517 case D: t1 writes a state that t2 also writes
6518 case E: t1 writes a tie queue that t2 also writes
6519 case F: two volatile queue accesses
6523 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6525 xtensa_isa isa
= xtensa_default_isa
;
6526 xtensa_regfile t1_regfile
, t2_regfile
;
6528 int t1_base_reg
, t1_last_reg
;
6529 int t2_base_reg
, t2_last_reg
;
6530 char t1_inout
, t2_inout
;
6532 char conflict
= 'b';
6537 bfd_boolean t1_volatile
= FALSE
;
6538 bfd_boolean t2_volatile
= FALSE
;
6540 /* Check registers. */
6541 for (j
= 0; j
< t2
->ntok
; j
++)
6543 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6546 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6547 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6548 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6550 for (i
= 0; i
< t1
->ntok
; i
++)
6552 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6555 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6557 if (t1_regfile
!= t2_regfile
)
6560 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6561 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6563 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6564 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6566 if (t1_inout
== 'm' || t1_inout
== 'o'
6567 || t2_inout
== 'm' || t2_inout
== 'o')
6574 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6575 t1_last_reg
= (t1_base_reg
6576 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6578 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6580 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6582 if (t1_reg
!= t2_reg
)
6585 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6591 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6597 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6605 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6606 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6607 for (j
= 0; j
< t2_states
; j
++)
6609 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6610 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6611 for (i
= 0; i
< t1_states
; i
++)
6613 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6614 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6615 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6618 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6624 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6630 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6635 /* Check tieports. */
6636 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6637 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6638 for (j
= 0; j
< t2_interfaces
; j
++)
6640 xtensa_interface t2_int
6641 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6642 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6644 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6645 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6648 for (i
= 0; i
< t1_interfaces
; i
++)
6650 xtensa_interface t1_int
6651 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6652 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6654 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6655 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6658 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6661 if (t1_int
!= t2_int
)
6664 if (t2_inout
== 'i' && t1_inout
== 'o')
6670 if (t1_inout
== 'i' && t2_inout
== 'o')
6676 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6685 static xtensa_format
6686 xg_find_narrowest_format (vliw_insn
*vinsn
)
6688 /* Right now we assume that the ops within the vinsn are properly
6689 ordered for the slots that the programmer wanted them in. In
6690 other words, we don't rearrange the ops in hopes of finding a
6691 better format. The scheduler handles that. */
6693 xtensa_isa isa
= xtensa_default_isa
;
6694 xtensa_format format
;
6695 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6697 if (vinsn
->num_slots
== 1)
6698 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6700 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6703 xg_copy_vinsn (&v_copy
, vinsn
);
6704 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6708 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6710 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6712 v_copy
.slots
[slot
].opcode
=
6713 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6714 v_copy
.slots
[slot
].ntok
= 0;
6717 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6720 else if (v_copy
.num_slots
> 1)
6723 /* Try the widened version. */
6724 if (!v_copy
.slots
[slot
].keep_wide
6725 && !v_copy
.slots
[slot
].is_specific_opcode
6726 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6728 && opcode_fits_format_slot (widened
.opcode
,
6731 v_copy
.slots
[slot
] = widened
;
6736 if (fit
== v_copy
.num_slots
)
6738 xg_copy_vinsn (vinsn
, &v_copy
);
6739 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6740 vinsn
->format
= format
;
6746 if (format
== xtensa_isa_num_formats (isa
))
6747 return XTENSA_UNDEFINED
;
6753 /* Return the additional space needed in a frag
6754 for possible relaxations of any ops in a VLIW insn.
6755 Also fill out the relaxations that might be required of
6756 each tinsn in the vinsn. */
6759 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6761 bfd_boolean finish_frag
= FALSE
;
6762 int extra_space
= 0;
6765 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6767 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6768 if (!tinsn_has_symbolic_operands (tinsn
))
6770 /* A narrow instruction could be widened later to help
6771 alignment issues. */
6772 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6773 && !tinsn
->is_specific_opcode
6774 && vinsn
->num_slots
== 1)
6776 /* Difference in bytes between narrow and wide insns... */
6778 tinsn
->subtype
= RELAX_NARROW
;
6783 if (workaround_b_j_loop_end
6784 && tinsn
->opcode
== xtensa_jx_opcode
6785 && use_transform ())
6787 /* Add 2 of these. */
6788 extra_space
+= 3; /* for the nop size */
6789 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6792 /* Need to assemble it with space for the relocation. */
6793 if (xg_is_relaxable_insn (tinsn
, 0)
6794 && !tinsn
->is_specific_opcode
)
6796 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6797 int max_literal_size
=
6798 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6800 tinsn
->literal_space
= max_literal_size
;
6802 tinsn
->subtype
= RELAX_IMMED
;
6803 extra_space
+= max_size
;
6807 /* A fix record will be added for this instruction prior
6808 to relaxation, so make it end the frag. */
6813 *pfinish_frag
= finish_frag
;
6819 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6821 xtensa_isa isa
= xtensa_default_isa
;
6822 int slot
, chosen_slot
;
6824 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6825 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6826 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6828 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6829 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6831 if (slot
== chosen_slot
)
6832 vinsn
->slots
[slot
] = *tinsn
;
6835 vinsn
->slots
[slot
].opcode
=
6836 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6837 vinsn
->slots
[slot
].ntok
= 0;
6838 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6845 emit_single_op (TInsn
*orig_insn
)
6848 IStack istack
; /* put instructions into here */
6849 symbolS
*lit_sym
= NULL
;
6850 symbolS
*label_sym
= NULL
;
6852 istack_init (&istack
);
6854 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6855 Because the scheduling and bundling characteristics of movi and
6856 l32r or const16 are so different, we can do much better if we relax
6857 it prior to scheduling and bundling, rather than after. */
6858 if ((orig_insn
->opcode
== xtensa_movi_opcode
6859 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6860 && !cur_vinsn
.inside_bundle
6861 && (orig_insn
->tok
[1].X_op
== O_symbol
6862 || orig_insn
->tok
[1].X_op
== O_pltrel
6863 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6864 || orig_insn
->tok
[1].X_op
== O_tlsarg
6865 || orig_insn
->tok
[1].X_op
== O_tpoff
6866 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6867 && !orig_insn
->is_specific_opcode
&& use_transform ())
6868 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6870 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6873 for (i
= 0; i
< istack
.ninsn
; i
++)
6875 TInsn
*insn
= &istack
.insn
[i
];
6876 switch (insn
->insn_type
)
6879 gas_assert (lit_sym
== NULL
);
6880 lit_sym
= xg_assemble_literal (insn
);
6884 static int relaxed_sym_idx
= 0;
6885 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6886 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6888 gas_assert (label_sym
== NULL
);
6889 label_sym
= symbol_find_or_make (label
);
6890 gas_assert (label_sym
);
6898 xg_resolve_literals (insn
, lit_sym
);
6900 xg_resolve_labels (insn
, label_sym
);
6902 bundle_tinsn (insn
, &v
);
6917 total_frag_text_expansion (fragS
*fragP
)
6920 int total_expansion
= 0;
6922 for (slot
= 0; slot
< config_max_slots
; slot
++)
6923 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6925 return total_expansion
;
6929 /* Emit a vliw instruction to the current fragment. */
6932 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6934 bfd_boolean finish_frag
;
6935 bfd_boolean is_jump
= FALSE
;
6936 bfd_boolean is_branch
= FALSE
;
6937 xtensa_isa isa
= xtensa_default_isa
;
6942 struct dwarf2_line_info debug_line
;
6943 bfd_boolean loc_directive_seen
= FALSE
;
6946 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6948 if (generating_literals
)
6950 static int reported
= 0;
6952 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6953 _("cannot assemble into a literal fragment"));
6960 if (frag_now_fix () != 0
6961 && (! frag_now
->tc_frag_data
.is_insn
6962 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6963 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6964 || (directive_state
[directive_longcalls
]
6965 != frag_now
->tc_frag_data
.use_longcalls
)
6966 || (directive_state
[directive_absolute_literals
]
6967 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6969 frag_wane (frag_now
);
6971 xtensa_set_frag_assembly_state (frag_now
);
6974 if (workaround_a0_b_retw
6975 && vinsn
->num_slots
== 1
6976 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6977 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6978 && use_transform ())
6980 has_a0_b_retw
= TRUE
;
6982 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6983 After the first assembly pass we will check all of them and
6984 add a nop if needed. */
6985 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6986 frag_var (rs_machine_dependent
, 4, 4,
6987 RELAX_ADD_NOP_IF_A0_B_RETW
,
6988 frag_now
->fr_symbol
,
6989 frag_now
->fr_offset
,
6991 xtensa_set_frag_assembly_state (frag_now
);
6992 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6993 frag_var (rs_machine_dependent
, 4, 4,
6994 RELAX_ADD_NOP_IF_A0_B_RETW
,
6995 frag_now
->fr_symbol
,
6996 frag_now
->fr_offset
,
6998 xtensa_set_frag_assembly_state (frag_now
);
7001 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7003 tinsn
= &vinsn
->slots
[slot
];
7005 /* See if the instruction implies an aligned section. */
7006 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7007 record_alignment (now_seg
, 2);
7009 /* Determine the best line number for debug info. */
7010 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7011 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7012 || tinsn
->debug_line
.line
< debug_line
.line
7013 || tinsn
->debug_line
.column
< debug_line
.column
))
7014 debug_line
= tinsn
->debug_line
;
7015 if (tinsn
->loc_directive_seen
)
7016 loc_directive_seen
= TRUE
;
7019 /* Special cases for instructions that force an alignment... */
7020 /* None of these opcodes are bundle-able. */
7021 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7025 /* Remember the symbol that marks the end of the loop in the frag
7026 that marks the start of the loop. This way we can easily find
7027 the end of the loop at the beginning, without adding special code
7028 to mark the loop instructions themselves. */
7029 symbolS
*target_sym
= NULL
;
7030 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7031 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7033 xtensa_set_frag_assembly_state (frag_now
);
7034 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7036 max_fill
= get_text_align_max_fill_size
7037 (get_text_align_power (xtensa_fetch_width
),
7038 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7040 if (use_transform ())
7041 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7042 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7044 frag_var (rs_machine_dependent
, 0, 0,
7045 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7046 xtensa_set_frag_assembly_state (frag_now
);
7049 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7050 && !vinsn
->slots
[0].is_specific_opcode
)
7052 xtensa_mark_literal_pool_location ();
7053 xtensa_move_labels (frag_now
, 0);
7054 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7057 if (vinsn
->num_slots
== 1)
7059 if (workaround_a0_b_retw
&& use_transform ())
7060 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7061 is_register_writer (&vinsn
->slots
[0], "a", 0));
7063 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7064 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7067 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7069 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7071 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7073 /* vinsn_to_insnbuf will produce the error. */
7074 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7076 f
= frag_more (insn_size
+ extra_space
);
7077 xtensa_set_frag_assembly_state (frag_now
);
7078 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7081 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7082 if (vinsn
->format
== XTENSA_UNDEFINED
)
7085 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7087 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7088 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7091 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7093 tinsn
= &vinsn
->slots
[slot
];
7094 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7095 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7096 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7097 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7098 if (tinsn
->literal_space
!= 0)
7099 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7100 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7102 if (tinsn
->subtype
== RELAX_NARROW
)
7103 gas_assert (vinsn
->num_slots
== 1);
7104 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7106 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7109 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7110 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7114 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7115 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7119 frag_variant (rs_machine_dependent
,
7120 extra_space
, extra_space
, RELAX_SLOTS
,
7121 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7122 xtensa_set_frag_assembly_state (frag_now
);
7125 /* Special cases for loops:
7126 close_loop_end should be inserted AFTER short_loop.
7127 Make sure that CLOSE loops are processed BEFORE short_loops
7128 when converting them. */
7130 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7131 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7132 && !vinsn
->slots
[0].is_specific_opcode
)
7134 if (workaround_short_loop
&& use_transform ())
7136 maybe_has_short_loop
= TRUE
;
7137 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7138 frag_var (rs_machine_dependent
, 4, 4,
7139 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7140 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7141 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7142 frag_var (rs_machine_dependent
, 4, 4,
7143 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7144 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7147 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7148 loop at least 12 bytes away from another loop's end. */
7149 if (workaround_close_loop_end
&& use_transform ())
7151 maybe_has_close_loop_end
= TRUE
;
7152 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7153 frag_var (rs_machine_dependent
, 12, 12,
7154 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7155 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7159 if (use_transform ())
7163 gas_assert (finish_frag
);
7164 frag_var (rs_machine_dependent
,
7165 xtensa_fetch_width
, xtensa_fetch_width
,
7167 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7168 xtensa_set_frag_assembly_state (frag_now
);
7169 xtensa_maybe_create_trampoline_frag ();
7171 else if (is_branch
&& do_align_targets ())
7173 gas_assert (finish_frag
);
7174 frag_var (rs_machine_dependent
,
7175 xtensa_fetch_width
, xtensa_fetch_width
,
7176 RELAX_MAYBE_UNREACHABLE
,
7177 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7178 xtensa_set_frag_assembly_state (frag_now
);
7179 frag_var (rs_machine_dependent
,
7181 RELAX_MAYBE_DESIRE_ALIGN
,
7182 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7183 xtensa_set_frag_assembly_state (frag_now
);
7187 /* Now, if the original opcode was a call... */
7188 if (do_align_targets ()
7189 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7191 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7192 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7193 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7194 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7195 xtensa_set_frag_assembly_state (frag_now
);
7198 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7200 frag_wane (frag_now
);
7202 xtensa_set_frag_assembly_state (frag_now
);
7207 /* xtensa_end and helper functions. */
7209 static void xtensa_cleanup_align_frags (void);
7210 static void xtensa_fix_target_frags (void);
7211 static void xtensa_mark_narrow_branches (void);
7212 static void xtensa_mark_zcl_first_insns (void);
7213 static void xtensa_mark_difference_of_two_symbols (void);
7214 static void xtensa_fix_a0_b_retw_frags (void);
7215 static void xtensa_fix_b_j_loop_end_frags (void);
7216 static void xtensa_fix_close_loop_end_frags (void);
7217 static void xtensa_fix_short_loop_frags (void);
7218 static void xtensa_sanity_check (void);
7219 static void xtensa_add_config_info (void);
7224 directive_balance ();
7225 xtensa_flush_pending_output ();
7227 past_xtensa_end
= TRUE
;
7229 xtensa_move_literals ();
7231 xtensa_reorder_segments ();
7232 xtensa_cleanup_align_frags ();
7233 xtensa_fix_target_frags ();
7234 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7235 xtensa_fix_a0_b_retw_frags ();
7236 if (workaround_b_j_loop_end
)
7237 xtensa_fix_b_j_loop_end_frags ();
7239 /* "close_loop_end" should be processed BEFORE "short_loop". */
7240 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7241 xtensa_fix_close_loop_end_frags ();
7243 if (workaround_short_loop
&& maybe_has_short_loop
)
7244 xtensa_fix_short_loop_frags ();
7246 xtensa_mark_narrow_branches ();
7247 xtensa_mark_zcl_first_insns ();
7249 xtensa_sanity_check ();
7251 xtensa_add_config_info ();
7253 xtensa_check_frag_count ();
7257 struct trampoline_frag
7259 struct trampoline_frag
*next
;
7260 bfd_boolean needs_jump_around
;
7265 struct trampoline_seg
7267 struct trampoline_seg
*next
;
7269 struct trampoline_frag trampoline_list
;
7272 static struct trampoline_seg trampoline_seg_list
;
7273 #define J_RANGE (128 * 1024)
7275 static int unreachable_count
= 0;
7279 xtensa_maybe_create_trampoline_frag (void)
7281 if (!use_trampolines
)
7284 /* We create an area for possible trampolines every 10 unreachable frags.
7285 These are preferred over the ones not preceded by an unreachable frag,
7286 because we don't have to jump around them. This function is called after
7287 each RELAX_UNREACHABLE frag is created. */
7289 if (++unreachable_count
> 10)
7291 xtensa_create_trampoline_frag (FALSE
);
7292 clear_frag_count ();
7293 unreachable_count
= 0;
7298 xtensa_check_frag_count (void)
7300 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7303 /* We create an area for possible trampolines every 8000 frags or so. This
7304 is an estimate based on the max range of a "j" insn (+/-128K) divided
7305 by a typical frag byte count (16), minus a few for safety. This function
7306 is called after each source line is processed. */
7308 if (get_frag_count () > 8000)
7310 xtensa_create_trampoline_frag (TRUE
);
7311 clear_frag_count ();
7312 unreachable_count
= 0;
7316 static xtensa_insnbuf trampoline_buf
= NULL
;
7317 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7319 #define TRAMPOLINE_FRAG_SIZE 3000
7322 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7324 /* Emit a frag where we can place intermediate jump instructions,
7325 in case we need to jump farther than 128K bytes.
7326 Each jump instruction takes three bytes.
7327 We allocate enough for 1000 trampolines in each frag.
7328 If that's not enough, oh well. */
7330 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7331 struct trampoline_frag
*tf
;
7334 int size
= TRAMPOLINE_FRAG_SIZE
;
7336 for ( ; ts
; ts
= ts
->next
)
7338 if (ts
->seg
== now_seg
)
7344 ts
= (struct trampoline_seg
*)xcalloc(sizeof (struct trampoline_seg
), 1);
7345 ts
->next
= trampoline_seg_list
.next
;
7346 trampoline_seg_list
.next
= ts
;
7350 frag_wane (frag_now
);
7352 xtensa_set_frag_assembly_state (frag_now
);
7353 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7354 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7355 if (trampoline_buf
== NULL
)
7357 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7358 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7360 tf
= (struct trampoline_frag
*)xmalloc(sizeof (struct trampoline_frag
));
7361 tf
->next
= ts
->trampoline_list
.next
;
7362 ts
->trampoline_list
.next
= tf
;
7363 tf
->needs_jump_around
= needs_jump_around
;
7369 static struct trampoline_seg
*
7370 find_trampoline_seg (asection
*seg
)
7372 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7374 for ( ; ts
; ts
= ts
->next
)
7384 void dump_trampolines (void);
7387 dump_trampolines (void)
7389 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7391 for ( ; ts
; ts
= ts
->next
)
7393 asection
*seg
= ts
->seg
;
7397 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7398 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7399 for ( ; tf
; tf
= tf
->next
)
7401 if (tf
->fragP
== NULL
)
7403 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7404 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7405 tf
->needs_jump_around
? "T" : "F");
7411 xtensa_cleanup_align_frags (void)
7416 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7417 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7420 /* Walk over all of the fragments in a subsection. */
7421 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7423 if ((fragP
->fr_type
== rs_align
7424 || fragP
->fr_type
== rs_align_code
7425 || (fragP
->fr_type
== rs_machine_dependent
7426 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7427 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7428 && fragP
->fr_fix
== 0)
7430 fragS
*next
= fragP
->fr_next
;
7433 && next
->fr_fix
== 0
7434 && next
->fr_type
== rs_machine_dependent
7435 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7438 next
= next
->fr_next
;
7441 /* If we don't widen branch targets, then they
7442 will be easier to align. */
7443 if (fragP
->tc_frag_data
.is_branch_target
7444 && fragP
->fr_opcode
== fragP
->fr_literal
7445 && fragP
->fr_type
== rs_machine_dependent
7446 && fragP
->fr_subtype
== RELAX_SLOTS
7447 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7449 if (fragP
->fr_type
== rs_machine_dependent
7450 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7451 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7457 /* Re-process all of the fragments looking to convert all of the
7458 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7459 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7460 Otherwise, convert to a .fill 0. */
7463 xtensa_fix_target_frags (void)
7468 /* When this routine is called, all of the subsections are still intact
7469 so we walk over subsections instead of sections. */
7470 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7471 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7475 /* Walk over all of the fragments in a subsection. */
7476 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7478 if (fragP
->fr_type
== rs_machine_dependent
7479 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7481 if (next_frag_is_branch_target (fragP
))
7482 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7491 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7494 xtensa_mark_narrow_branches (void)
7499 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7500 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7503 /* Walk over all of the fragments in a subsection. */
7504 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7506 if (fragP
->fr_type
== rs_machine_dependent
7507 && fragP
->fr_subtype
== RELAX_SLOTS
7508 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7512 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7513 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7515 if (vinsn
.num_slots
== 1
7516 && xtensa_opcode_is_branch (xtensa_default_isa
,
7517 vinsn
.slots
[0].opcode
) == 1
7518 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7519 && is_narrow_branch_guaranteed_in_range (fragP
,
7522 fragP
->fr_subtype
= RELAX_SLOTS
;
7523 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7524 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7532 /* A branch is typically widened only when its target is out of
7533 range. However, we would like to widen them to align a subsequent
7534 branch target when possible.
7536 Because the branch relaxation code is so convoluted, the optimal solution
7537 (combining the two cases) is difficult to get right in all circumstances.
7538 We therefore go with an "almost as good" solution, where we only
7539 use for alignment narrow branches that definitely will not expand to a
7540 jump and a branch. These functions find and mark these cases. */
7542 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7543 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7544 We start counting beginning with the frag after the 2-byte branch, so the
7545 maximum offset is (4 - 2) + 63 = 65. */
7546 #define MAX_IMMED6 65
7548 static offsetT
unrelaxed_frag_max_size (fragS
*);
7551 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7553 const expressionS
*exp
= &tinsn
->tok
[1];
7554 symbolS
*symbolP
= exp
->X_add_symbol
;
7555 offsetT max_distance
= exp
->X_add_number
;
7558 if (exp
->X_op
!= O_symbol
)
7561 target_frag
= symbol_get_frag (symbolP
);
7563 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7564 if (is_branch_jmp_to_next (tinsn
, fragP
))
7567 /* The branch doesn't branch over it's own frag,
7568 but over the subsequent ones. */
7569 fragP
= fragP
->fr_next
;
7570 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7572 max_distance
+= unrelaxed_frag_max_size (fragP
);
7573 fragP
= fragP
->fr_next
;
7575 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7582 xtensa_mark_zcl_first_insns (void)
7587 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7588 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7591 /* Walk over all of the fragments in a subsection. */
7592 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7594 if (fragP
->fr_type
== rs_machine_dependent
7595 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7596 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7598 /* Find the loop frag. */
7599 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7600 /* Find the first insn frag. */
7601 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7603 /* Handle a corner case that comes up in hardware
7604 diagnostics. The original assembly looks like this:
7607 <empty_frag>--not found by next_non_empty_frag
7610 Depending on the start address, the assembler may or
7611 may not change it to look something like this:
7614 nop--frag isn't empty anymore
7617 So set up to check the alignment of the nop if it
7619 while (loop_frag
!= targ_frag
)
7621 if (loop_frag
->fr_type
== rs_machine_dependent
7622 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7623 || loop_frag
->fr_subtype
7624 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7625 targ_frag
= loop_frag
;
7627 loop_frag
= loop_frag
->fr_next
;
7630 /* Of course, sometimes (mostly for toy test cases) a
7631 zero-cost loop instruction is the last in a section. */
7634 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7635 /* Do not widen a frag that is the first instruction of a
7636 zero-cost loop. It makes that loop harder to align. */
7637 if (targ_frag
->fr_type
== rs_machine_dependent
7638 && targ_frag
->fr_subtype
== RELAX_SLOTS
7639 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7642 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7643 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7646 frag_wane (targ_frag
);
7647 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7651 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7659 /* When a difference-of-symbols expression is encoded as a uleb128 or
7660 sleb128 value, the linker is unable to adjust that value to account for
7661 link-time relaxation. Mark all the code between such symbols so that
7662 its size cannot be changed by linker relaxation. */
7665 xtensa_mark_difference_of_two_symbols (void)
7669 for (expr_sym
= expr_symbols
; expr_sym
;
7670 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7672 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7674 if (exp
->X_op
== O_subtract
)
7676 symbolS
*left
= exp
->X_add_symbol
;
7677 symbolS
*right
= exp
->X_op_symbol
;
7679 /* Difference of two symbols not in the same section
7680 are handled with relocations in the linker. */
7681 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7687 if (symbol_get_frag (left
)->fr_address
7688 <= symbol_get_frag (right
)->fr_address
)
7690 start
= symbol_get_frag (left
);
7691 end
= symbol_get_frag (right
);
7695 start
= symbol_get_frag (right
);
7696 end
= symbol_get_frag (left
);
7699 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7700 walk
= start
->tc_frag_data
.no_transform_end
;
7705 walk
->tc_frag_data
.is_no_transform
= 1;
7706 walk
= walk
->fr_next
;
7708 while (walk
&& walk
->fr_address
< end
->fr_address
);
7710 start
->tc_frag_data
.no_transform_end
= walk
;
7717 /* Re-process all of the fragments looking to convert all of the
7718 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7719 conditional branch or a retw/retw.n, convert this frag to one that
7720 will generate a NOP. In any case close it off with a .fill 0. */
7722 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7725 xtensa_fix_a0_b_retw_frags (void)
7730 /* When this routine is called, all of the subsections are still intact
7731 so we walk over subsections instead of sections. */
7732 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7733 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7737 /* Walk over all of the fragments in a subsection. */
7738 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7740 if (fragP
->fr_type
== rs_machine_dependent
7741 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7743 if (next_instrs_are_b_retw (fragP
))
7745 if (fragP
->tc_frag_data
.is_no_transform
)
7746 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7748 relax_frag_add_nop (fragP
);
7758 next_instrs_are_b_retw (fragS
*fragP
)
7760 xtensa_opcode opcode
;
7762 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7763 static xtensa_insnbuf insnbuf
= NULL
;
7764 static xtensa_insnbuf slotbuf
= NULL
;
7765 xtensa_isa isa
= xtensa_default_isa
;
7768 bfd_boolean branch_seen
= FALSE
;
7772 insnbuf
= xtensa_insnbuf_alloc (isa
);
7773 slotbuf
= xtensa_insnbuf_alloc (isa
);
7776 if (next_fragP
== NULL
)
7779 /* Check for the conditional branch. */
7780 xtensa_insnbuf_from_chars
7781 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7782 fmt
= xtensa_format_decode (isa
, insnbuf
);
7783 if (fmt
== XTENSA_UNDEFINED
)
7786 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7788 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7789 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7791 branch_seen
= (branch_seen
7792 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7798 offset
+= xtensa_format_length (isa
, fmt
);
7799 if (offset
== next_fragP
->fr_fix
)
7801 next_fragP
= next_non_empty_frag (next_fragP
);
7805 if (next_fragP
== NULL
)
7808 /* Check for the retw/retw.n. */
7809 xtensa_insnbuf_from_chars
7810 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7811 fmt
= xtensa_format_decode (isa
, insnbuf
);
7813 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7814 have no problems. */
7815 if (fmt
== XTENSA_UNDEFINED
7816 || xtensa_format_num_slots (isa
, fmt
) != 1)
7819 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7820 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7822 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7829 /* Re-process all of the fragments looking to convert all of the
7830 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7831 loop end label, convert this frag to one that will generate a NOP.
7832 In any case close it off with a .fill 0. */
7834 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7837 xtensa_fix_b_j_loop_end_frags (void)
7842 /* When this routine is called, all of the subsections are still intact
7843 so we walk over subsections instead of sections. */
7844 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7845 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7849 /* Walk over all of the fragments in a subsection. */
7850 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7852 if (fragP
->fr_type
== rs_machine_dependent
7853 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7855 if (next_instr_is_loop_end (fragP
))
7857 if (fragP
->tc_frag_data
.is_no_transform
)
7858 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7860 relax_frag_add_nop (fragP
);
7870 next_instr_is_loop_end (fragS
*fragP
)
7872 const fragS
*next_fragP
;
7874 if (next_frag_is_loop_target (fragP
))
7877 next_fragP
= next_non_empty_frag (fragP
);
7878 if (next_fragP
== NULL
)
7881 if (!next_frag_is_loop_target (next_fragP
))
7884 /* If the size is >= 3 then there is more than one instruction here.
7885 The hardware bug will not fire. */
7886 if (next_fragP
->fr_fix
> 3)
7893 /* Re-process all of the fragments looking to convert all of the
7894 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7895 not MY loop's loop end within 12 bytes, add enough nops here to
7896 make it at least 12 bytes away. In any case close it off with a
7899 static offsetT min_bytes_to_other_loop_end
7900 (fragS
*, fragS
*, offsetT
);
7903 xtensa_fix_close_loop_end_frags (void)
7908 /* When this routine is called, all of the subsections are still intact
7909 so we walk over subsections instead of sections. */
7910 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7911 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7915 fragS
*current_target
= NULL
;
7917 /* Walk over all of the fragments in a subsection. */
7918 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7920 if (fragP
->fr_type
== rs_machine_dependent
7921 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7922 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7923 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7926 && fragP
->fr_type
== rs_machine_dependent
7927 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7930 int bytes_added
= 0;
7932 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7933 /* Max out at 12. */
7934 min_bytes
= min_bytes_to_other_loop_end
7935 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7937 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7939 if (fragP
->tc_frag_data
.is_no_transform
)
7940 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7943 while (min_bytes
+ bytes_added
7944 < REQUIRED_LOOP_DIVIDING_BYTES
)
7948 if (fragP
->fr_var
< length
)
7949 as_fatal (_("fr_var %lu < length %d"),
7950 (long) fragP
->fr_var
, length
);
7953 assemble_nop (length
,
7954 fragP
->fr_literal
+ fragP
->fr_fix
);
7955 fragP
->fr_fix
+= length
;
7956 fragP
->fr_var
-= length
;
7958 bytes_added
+= length
;
7964 gas_assert (fragP
->fr_type
!= rs_machine_dependent
7965 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7971 static offsetT
unrelaxed_frag_min_size (fragS
*);
7974 min_bytes_to_other_loop_end (fragS
*fragP
,
7975 fragS
*current_target
,
7979 fragS
*current_fragP
;
7981 for (current_fragP
= fragP
;
7983 current_fragP
= current_fragP
->fr_next
)
7985 if (current_fragP
->tc_frag_data
.is_loop_target
7986 && current_fragP
!= current_target
)
7989 offset
+= unrelaxed_frag_min_size (current_fragP
);
7991 if (offset
>= max_size
)
7999 unrelaxed_frag_min_size (fragS
*fragP
)
8001 offsetT size
= fragP
->fr_fix
;
8003 /* Add fill size. */
8004 if (fragP
->fr_type
== rs_fill
)
8005 size
+= fragP
->fr_offset
;
8012 unrelaxed_frag_max_size (fragS
*fragP
)
8014 offsetT size
= fragP
->fr_fix
;
8015 switch (fragP
->fr_type
)
8018 /* Empty frags created by the obstack allocation scheme
8019 end up with type 0. */
8024 size
+= fragP
->fr_offset
;
8032 /* No further adjustments needed. */
8034 case rs_machine_dependent
:
8035 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8036 size
+= fragP
->fr_var
;
8039 /* We had darn well better know how big it is. */
8048 /* Re-process all of the fragments looking to convert all
8049 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8052 1) the instruction size count to the loop end label
8053 is too short (<= 2 instructions),
8054 2) loop has a jump or branch in it
8057 1) workaround_all_short_loops is TRUE
8058 2) The generating loop was a 'loopgtz' or 'loopnez'
8059 3) the instruction size count to the loop end label is too short
8061 then convert this frag (and maybe the next one) to generate a NOP.
8062 In any case close it off with a .fill 0. */
8064 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8065 static bfd_boolean
branch_before_loop_end (fragS
*);
8068 xtensa_fix_short_loop_frags (void)
8073 /* When this routine is called, all of the subsections are still intact
8074 so we walk over subsections instead of sections. */
8075 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8076 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8079 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8081 /* Walk over all of the fragments in a subsection. */
8082 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8084 if (fragP
->fr_type
== rs_machine_dependent
8085 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8086 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8089 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8090 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8091 current_opcode
= t_insn
.opcode
;
8092 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8093 current_opcode
) == 1);
8096 if (fragP
->fr_type
== rs_machine_dependent
8097 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8099 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8100 && (branch_before_loop_end (fragP
->fr_next
)
8101 || (workaround_all_short_loops
8102 && current_opcode
!= XTENSA_UNDEFINED
8103 && current_opcode
!= xtensa_loop_opcode
)))
8105 if (fragP
->tc_frag_data
.is_no_transform
)
8106 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8108 relax_frag_add_nop (fragP
);
8117 static int unrelaxed_frag_min_insn_count (fragS
*);
8120 count_insns_to_loop_end (fragS
*base_fragP
,
8121 bfd_boolean count_relax_add
,
8124 fragS
*fragP
= NULL
;
8129 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8131 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8132 if (insn_count
>= max_count
)
8135 if (count_relax_add
)
8137 if (fragP
->fr_type
== rs_machine_dependent
8138 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8140 /* In order to add the appropriate number of
8141 NOPs, we count an instruction for downstream
8144 if (insn_count
>= max_count
)
8154 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8156 xtensa_isa isa
= xtensa_default_isa
;
8157 static xtensa_insnbuf insnbuf
= NULL
;
8161 if (!fragP
->tc_frag_data
.is_insn
)
8165 insnbuf
= xtensa_insnbuf_alloc (isa
);
8167 /* Decode the fixed instructions. */
8168 while (offset
< fragP
->fr_fix
)
8172 xtensa_insnbuf_from_chars
8173 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8174 fmt
= xtensa_format_decode (isa
, insnbuf
);
8176 if (fmt
== XTENSA_UNDEFINED
)
8178 as_fatal (_("undecodable instruction in instruction frag"));
8181 offset
+= xtensa_format_length (isa
, fmt
);
8189 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8192 branch_before_loop_end (fragS
*base_fragP
)
8196 for (fragP
= base_fragP
;
8197 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8198 fragP
= fragP
->fr_next
)
8200 if (unrelaxed_frag_has_b_j (fragP
))
8208 unrelaxed_frag_has_b_j (fragS
*fragP
)
8210 static xtensa_insnbuf insnbuf
= NULL
;
8211 xtensa_isa isa
= xtensa_default_isa
;
8214 if (!fragP
->tc_frag_data
.is_insn
)
8218 insnbuf
= xtensa_insnbuf_alloc (isa
);
8220 /* Decode the fixed instructions. */
8221 while (offset
< fragP
->fr_fix
)
8226 xtensa_insnbuf_from_chars
8227 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8228 fmt
= xtensa_format_decode (isa
, insnbuf
);
8229 if (fmt
== XTENSA_UNDEFINED
)
8232 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8234 xtensa_opcode opcode
=
8235 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8236 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8237 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8240 offset
+= xtensa_format_length (isa
, fmt
);
8246 /* Checks to be made after initial assembly but before relaxation. */
8248 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8249 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8252 xtensa_sanity_check (void)
8259 as_where (&file_name
, &line
);
8260 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8261 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8265 /* Walk over all of the fragments in a subsection. */
8266 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8268 if (fragP
->fr_type
== rs_machine_dependent
8269 && fragP
->fr_subtype
== RELAX_SLOTS
8270 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8272 static xtensa_insnbuf insnbuf
= NULL
;
8275 if (fragP
->fr_opcode
!= NULL
)
8278 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8279 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8280 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8282 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8283 t_insn
.opcode
) == 1)
8285 if (is_empty_loop (&t_insn
, fragP
))
8287 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8288 as_bad (_("invalid empty loop"));
8290 if (!is_local_forward_loop (&t_insn
, fragP
))
8292 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8293 as_bad (_("loop target does not follow "
8294 "loop instruction in section"));
8301 new_logical_line (file_name
, line
);
8305 #define LOOP_IMMED_OPN 1
8307 /* Return TRUE if the loop target is the next non-zero fragment. */
8310 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8312 const expressionS
*exp
;
8316 if (insn
->insn_type
!= ITYPE_INSN
)
8319 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8322 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8325 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8327 if (exp
->X_op
!= O_symbol
)
8330 symbolP
= exp
->X_add_symbol
;
8334 if (symbol_get_frag (symbolP
) == NULL
)
8337 if (S_GET_VALUE (symbolP
) != 0)
8340 /* Walk through the zero-size fragments from this one. If we find
8341 the target fragment, then this is a zero-size loop. */
8343 for (next_fragP
= fragP
->fr_next
;
8345 next_fragP
= next_fragP
->fr_next
)
8347 if (next_fragP
== symbol_get_frag (symbolP
))
8349 if (next_fragP
->fr_fix
!= 0)
8357 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8359 const expressionS
*exp
;
8363 if (insn
->insn_type
!= ITYPE_INSN
)
8366 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8369 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8372 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8374 if (exp
->X_op
!= O_symbol
)
8377 symbolP
= exp
->X_add_symbol
;
8381 if (symbol_get_frag (symbolP
) == NULL
)
8384 /* Walk through fragments until we find the target.
8385 If we do not find the target, then this is an invalid loop. */
8387 for (next_fragP
= fragP
->fr_next
;
8389 next_fragP
= next_fragP
->fr_next
)
8391 if (next_fragP
== symbol_get_frag (symbolP
))
8399 #define XTINFO_NAME "Xtensa_Info"
8400 #define XTINFO_NAMESZ 12
8401 #define XTINFO_TYPE 1
8404 xtensa_add_config_info (void)
8410 info_sec
= subseg_new (".xtensa.info", 0);
8411 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8413 data
= xmalloc (100);
8414 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8415 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8416 sz
= strlen (data
) + 1;
8418 /* Add enough null terminators to pad to a word boundary. */
8421 while ((sz
& 3) != 0);
8423 /* Follow the standard note section layout:
8424 First write the length of the name string. */
8426 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8428 /* Next comes the length of the "descriptor", i.e., the actual data. */
8430 md_number_to_chars (p
, (valueT
) sz
, 4);
8432 /* Write the note type. */
8434 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8436 /* Write the name field. */
8437 p
= frag_more (XTINFO_NAMESZ
);
8438 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8440 /* Finally, write the descriptor. */
8442 memcpy (p
, data
, sz
);
8448 /* Alignment Functions. */
8451 get_text_align_power (unsigned target_size
)
8453 if (target_size
<= 4)
8456 if (target_size
<= 8)
8459 if (target_size
<= 16)
8462 if (target_size
<= 32)
8465 if (target_size
<= 64)
8468 if (target_size
<= 128)
8471 if (target_size
<= 256)
8474 if (target_size
<= 512)
8477 if (target_size
<= 1024)
8486 get_text_align_max_fill_size (int align_pow
,
8487 bfd_boolean use_nops
,
8488 bfd_boolean use_no_density
)
8491 return (1 << align_pow
);
8493 return 3 * (1 << align_pow
);
8495 return 1 + (1 << align_pow
);
8499 /* Calculate the minimum bytes of fill needed at "address" to align a
8500 target instruction of size "target_size" so that it does not cross a
8501 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8502 the fill can be an arbitrary number of bytes. Otherwise, the space must
8503 be filled by NOP instructions. */
8506 get_text_align_fill_size (addressT address
,
8509 bfd_boolean use_nops
,
8510 bfd_boolean use_no_density
)
8512 addressT alignment
, fill
, fill_limit
, fill_step
;
8513 bfd_boolean skip_one
= FALSE
;
8515 alignment
= (1 << align_pow
);
8516 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8520 fill_limit
= alignment
;
8523 else if (!use_no_density
)
8525 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8526 fill_limit
= alignment
* 2;
8532 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8533 fill_limit
= alignment
* 3;
8537 /* Try all fill sizes until finding one that works. */
8538 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8540 if (skip_one
&& fill
== 1)
8542 if ((address
+ fill
) >> align_pow
8543 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8552 branch_align_power (segT sec
)
8554 /* If the Xtensa processor has a fetch width of X, and
8555 the section is aligned to at least that boundary, then a branch
8556 target need only fit within that aligned block of memory to avoid
8557 a stall. Otherwise, try to fit branch targets within 4-byte
8558 aligned blocks (which may be insufficient, e.g., if the section
8559 has no alignment, but it's good enough). */
8560 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8561 int sec_align
= get_recorded_alignment (sec
);
8563 if (sec_align
>= fetch_align
)
8570 /* This will assert if it is not possible. */
8573 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8579 gas_assert (fill_size
% 3 == 0);
8580 return (fill_size
/ 3);
8583 gas_assert (fill_size
!= 1); /* Bad argument. */
8585 while (fill_size
> 1)
8588 if (fill_size
== 2 || fill_size
== 4)
8590 fill_size
-= insn_size
;
8593 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8599 get_text_align_nth_nop_size (offsetT fill_size
,
8601 bfd_boolean use_no_density
)
8608 gas_assert (fill_size
!= 1); /* Bad argument. */
8610 while (fill_size
> 1)
8613 if (fill_size
== 2 || fill_size
== 4)
8615 fill_size
-= insn_size
;
8625 /* For the given fragment, find the appropriate address
8626 for it to begin at if we are using NOPs to align it. */
8629 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8631 /* The rule is: get next fragment's FIRST instruction. Find
8632 the smallest number of bytes that need to be added to
8633 ensure that the next fragment's FIRST instruction will fit
8636 E.G., 2 bytes : 0, 1, 2 mod 4
8639 If the FIRST instruction MIGHT be relaxed,
8640 assume that it will become a 3-byte instruction.
8642 Note again here that LOOP instructions are not bundleable,
8643 and this relaxation only applies to LOOP opcodes. */
8646 int first_insn_size
;
8648 addressT pre_opcode_bytes
;
8651 xtensa_opcode opcode
;
8652 bfd_boolean is_loop
;
8654 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8655 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8657 /* Find the loop frag. */
8658 first_insn
= next_non_empty_frag (fragP
);
8659 /* Now find the first insn frag. */
8660 first_insn
= next_non_empty_frag (first_insn
);
8662 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8663 gas_assert (is_loop
);
8664 loop_insn_size
= xg_get_single_size (opcode
);
8666 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8667 pre_opcode_bytes
+= loop_insn_size
;
8669 /* For loops, the alignment depends on the size of the
8670 instruction following the loop, not the LOOP instruction. */
8672 if (first_insn
== NULL
)
8673 first_insn_size
= xtensa_fetch_width
;
8675 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8677 /* If it was 8, then we'll need a larger alignment for the section. */
8678 align_power
= get_text_align_power (first_insn_size
);
8679 record_alignment (now_seg
, align_power
);
8681 fill_size
= get_text_align_fill_size
8682 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8683 fragP
->tc_frag_data
.is_no_density
);
8685 return address
+ fill_size
;
8689 /* 3 mechanisms for relaxing an alignment:
8691 Align to a power of 2.
8692 Align so the next fragment's instruction does not cross a word boundary.
8693 Align the current instruction so that if the next instruction
8694 were 3 bytes, it would not cross a word boundary.
8698 zeros - This is easy; always insert zeros.
8699 nops - 3-byte and 2-byte instructions
8703 >=5 : 3-byte instruction + fn (n-3)
8704 widening - widen previous instructions. */
8707 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8709 addressT target_address
, loop_insn_offset
;
8711 xtensa_opcode loop_opcode
;
8712 bfd_boolean is_loop
;
8715 offsetT branch_align
;
8718 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8719 switch (fragP
->fr_subtype
)
8721 case RELAX_DESIRE_ALIGN
:
8722 target_size
= next_frag_format_size (fragP
);
8723 if (target_size
== XTENSA_UNDEFINED
)
8725 align_power
= branch_align_power (now_seg
);
8726 branch_align
= 1 << align_power
;
8727 /* Don't count on the section alignment being as large as the target. */
8728 if (target_size
> branch_align
)
8729 target_size
= branch_align
;
8730 opt_diff
= get_text_align_fill_size (address
, align_power
,
8731 target_size
, FALSE
, FALSE
);
8733 *max_diff
= (opt_diff
+ branch_align
8734 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8735 gas_assert (*max_diff
>= opt_diff
);
8738 case RELAX_ALIGN_NEXT_OPCODE
:
8739 /* The next non-empty frag after this one holds the LOOP instruction
8740 that needs to be aligned. The required alignment depends on the
8741 size of the next non-empty frag after the loop frag, i.e., the
8742 first instruction in the loop. */
8743 loop_frag
= next_non_empty_frag (fragP
);
8744 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8745 loop_insn_offset
= 0;
8746 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8747 gas_assert (is_loop
);
8749 /* If the loop has been expanded then the LOOP instruction
8750 could be at an offset from this fragment. */
8751 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8752 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8754 /* In an ideal world, which is what we are shooting for here,
8755 we wouldn't need to use any NOPs immediately prior to the
8756 LOOP instruction. If this approach fails, relax_frag_loop_align
8757 will call get_noop_aligned_address. */
8759 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8760 align_power
= get_text_align_power (target_size
);
8761 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8762 target_size
, FALSE
, FALSE
);
8764 *max_diff
= xtensa_fetch_width
8765 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8766 - target_size
+ opt_diff
;
8767 gas_assert (*max_diff
>= opt_diff
);
8778 /* md_relax_frag Hook and Helper Functions. */
8780 static long relax_frag_loop_align (fragS
*, long);
8781 static long relax_frag_for_align (fragS
*, long);
8782 static long relax_frag_immed
8783 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8786 /* Return the number of bytes added to this fragment, given that the
8787 input has been stretched already by "stretch". */
8790 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8792 xtensa_isa isa
= xtensa_default_isa
;
8793 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8794 long new_stretch
= 0;
8798 static xtensa_insnbuf vbuf
= NULL
;
8799 int slot
, num_slots
;
8802 as_where (&file_name
, &line
);
8803 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8805 fragP
->tc_frag_data
.unreported_expansion
= 0;
8807 switch (fragP
->fr_subtype
)
8809 case RELAX_ALIGN_NEXT_OPCODE
:
8810 /* Always convert. */
8811 if (fragP
->tc_frag_data
.relax_seen
)
8812 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8815 case RELAX_LOOP_END
:
8819 case RELAX_LOOP_END_ADD_NOP
:
8820 /* Add a NOP and switch to .fill 0. */
8821 new_stretch
= relax_frag_add_nop (fragP
);
8825 case RELAX_DESIRE_ALIGN
:
8826 /* Do nothing. The narrowing before this frag will either align
8831 case RELAX_LITERAL_FINAL
:
8834 case RELAX_LITERAL_NR
:
8836 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8837 gas_assert (unreported
== lit_size
);
8838 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8839 fragP
->fr_var
-= lit_size
;
8840 fragP
->fr_fix
+= lit_size
;
8846 vbuf
= xtensa_insnbuf_alloc (isa
);
8848 xtensa_insnbuf_from_chars
8849 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8850 fmt
= xtensa_format_decode (isa
, vbuf
);
8851 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8853 for (slot
= 0; slot
< num_slots
; slot
++)
8855 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8858 if (fragP
->tc_frag_data
.relax_seen
)
8859 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8863 case RELAX_IMMED_STEP1
:
8864 case RELAX_IMMED_STEP2
:
8865 case RELAX_IMMED_STEP3
:
8866 /* Place the immediate. */
8867 new_stretch
+= relax_frag_immed
8868 (now_seg
, fragP
, stretch
,
8869 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8870 fmt
, slot
, stretched_p
, FALSE
);
8874 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8880 case RELAX_LITERAL_POOL_BEGIN
:
8881 case RELAX_LITERAL_POOL_END
:
8882 case RELAX_MAYBE_UNREACHABLE
:
8883 case RELAX_MAYBE_DESIRE_ALIGN
:
8884 /* No relaxation required. */
8887 case RELAX_FILL_NOP
:
8888 case RELAX_UNREACHABLE
:
8889 if (fragP
->tc_frag_data
.relax_seen
)
8890 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8893 case RELAX_TRAMPOLINE
:
8894 if (fragP
->tc_frag_data
.relax_seen
)
8896 segment_info_type
*seginfo
= seg_info (now_seg
);
8897 fragS
*fP
; /* The out-of-range jump. */
8900 /* Scan for jumps that will not reach. */
8901 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
8903 symbolS
*s
= fixP
->fx_addsy
;
8904 xtensa_opcode opcode
;
8909 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
8910 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
8912 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
8913 (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8915 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
8916 gas_assert (fmt
!= XTENSA_UNDEFINED
);
8917 slot
= fixP
->tc_fix_data
.slot
;
8918 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
8919 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
8920 if (opcode
!= xtensa_j_opcode
)
8922 target
= S_GET_VALUE (s
);
8923 addr
= fixP
->fx_frag
->fr_address
;
8924 delta
= target
- addr
+ stretch
;
8925 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
8926 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
8927 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
8928 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
8929 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
8930 int lower
= (target
< addr
) ? target
: addr
;
8931 int upper
= (target
> addr
) ? target
: addr
;
8932 int midpoint
= lower
+ (upper
- lower
) / 2;
8934 if ((upper
- lower
) > 2 * J_RANGE
)
8936 /* One trampoline won't suffice; we need multiple jumps.
8937 Jump to the trampoline that's farthest, but still in
8938 range relative to the original "j" instruction. */
8939 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
8941 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
8942 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
8947 if (this_addr
- addr
< J_RANGE
)
8952 /* Backward jump. */
8953 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
8960 struct trampoline_frag
*best_tf
= NULL
;
8963 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
8965 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
8966 int this_delta
= abs (this_addr
- midpoint
);
8968 if (!best_tf
|| this_delta
< best_delta
)
8971 best_delta
= this_delta
;
8976 if (tf
->fragP
== fragP
)
8978 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
8980 if (abs (addr
- trampaddr
) < J_RANGE
)
8981 { /* The trampoline is in range of original; fix it! */
8987 new_stretch
+= init_trampoline_frag (tf
);
8988 offset
= fragP
->fr_fix
; /* Where to assemble the j insn. */
8989 lsym
= fragP
->fr_symbol
;
8991 /* Assemble a jump to the target label here. */
8993 insn
.insn_type
= ITYPE_INSN
;
8994 insn
.opcode
= xtensa_j_opcode
;
8996 set_expr_symbol_offset (&insn
.tok
[0], lsym
, offset
);
8997 fmt
= xg_get_single_format (xtensa_j_opcode
);
8998 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
8999 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9000 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fragP
->fr_literal
+ offset
, 3);
9003 /* Add a fix-up for the original j insn. */
9004 newfixP
= fix_new (fP
, fixP
->fx_where
, fixP
->fx_size
, lsym
, fragP
->fr_fix
- 3, TRUE
, fixP
->fx_r_type
);
9005 newfixP
->fx_no_overflow
= 1;
9006 newfixP
->tc_fix_data
.X_add_symbol
= lsym
;
9007 newfixP
->tc_fix_data
.X_add_number
= offset
;
9008 newfixP
->tc_fix_data
.slot
= slot
;
9009 /* Move the fix-up from the original j insn to this one. */
9010 fixP
->fx_frag
= fragP
;
9011 fixP
->fx_where
= fragP
->fr_fix
- 3;
9012 fixP
->tc_fix_data
.slot
= 0;
9013 /* Adjust the jump around this trampoline (if present). */
9014 if (tf
->fixP
!= NULL
)
9016 tf
->fixP
->fx_offset
+= 3;
9019 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9020 /* Do we have room for more? */
9021 if (fragP
->fr_var
< 3)
9022 { /* No, convert to fill. */
9024 fragP
->fr_subtype
= 0;
9025 /* Remove from the trampoline_list. */
9026 prev
->next
= tf
->next
;
9037 as_bad (_("bad relaxation state"));
9040 /* Tell gas we need another relaxation pass. */
9041 if (! fragP
->tc_frag_data
.relax_seen
)
9043 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9047 new_logical_line (file_name
, line
);
9053 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9055 addressT old_address
, old_next_address
, old_size
;
9056 addressT new_address
, new_next_address
, new_size
;
9059 /* All the frags with relax_frag_for_alignment prior to this one in the
9060 section have been done, hopefully eliminating the need for a NOP here.
9061 But, this will put it in if necessary. */
9063 /* Calculate the old address of this fragment and the next fragment. */
9064 old_address
= fragP
->fr_address
- stretch
;
9065 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9066 fragP
->tc_frag_data
.text_expansion
[0]);
9067 old_size
= old_next_address
- old_address
;
9069 /* Calculate the new address of this fragment and the next fragment. */
9070 new_address
= fragP
->fr_address
;
9072 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9073 new_size
= new_next_address
- new_address
;
9075 growth
= new_size
- old_size
;
9077 /* Fix up the text_expansion field and return the new growth. */
9078 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9083 /* Add a NOP instruction. */
9086 relax_frag_add_nop (fragS
*fragP
)
9088 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9089 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9090 assemble_nop (length
, nop_buf
);
9091 fragP
->tc_frag_data
.is_insn
= TRUE
;
9093 if (fragP
->fr_var
< length
)
9095 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9099 fragP
->fr_fix
+= length
;
9100 fragP
->fr_var
-= length
;
9105 static long future_alignment_required (fragS
*, long);
9108 relax_frag_for_align (fragS
*fragP
, long stretch
)
9110 /* Overview of the relaxation procedure for alignment:
9111 We can widen with NOPs or by widening instructions or by filling
9112 bytes after jump instructions. Find the opportune places and widen
9113 them if necessary. */
9118 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9119 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9120 || (fragP
->fr_subtype
== RELAX_SLOTS
9121 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9123 stretch_me
= future_alignment_required (fragP
, stretch
);
9124 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9130 /* We expanded on a previous pass. Can we shrink now? */
9131 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9132 if (shrink
<= stretch
&& stretch
> 0)
9134 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9140 /* Below here, diff > 0. */
9141 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9147 /* Return the address of the next frag that should be aligned.
9149 By "address" we mean the address it _would_ be at if there
9150 is no action taken to align it between here and the target frag.
9151 In other words, if no narrows and no fill nops are used between
9152 here and the frag to align, _even_if_ some of the frags we use
9153 to align targets have already expanded on a previous relaxation
9156 Also, count each frag that may be used to help align the target.
9158 Return 0 if there are no frags left in the chain that need to be
9162 find_address_of_next_align_frag (fragS
**fragPP
,
9166 bfd_boolean
*paddable
)
9168 fragS
*fragP
= *fragPP
;
9169 addressT address
= fragP
->fr_address
;
9171 /* Do not reset the counts to 0. */
9175 /* Limit this to a small search. */
9176 if (*widens
>= (int) xtensa_fetch_width
)
9181 address
+= fragP
->fr_fix
;
9183 if (fragP
->fr_type
== rs_fill
)
9184 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9185 else if (fragP
->fr_type
== rs_machine_dependent
)
9187 switch (fragP
->fr_subtype
)
9189 case RELAX_UNREACHABLE
:
9193 case RELAX_FILL_NOP
:
9195 if (!fragP
->tc_frag_data
.is_no_density
)
9200 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9205 address
+= total_frag_text_expansion (fragP
);
9209 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9212 case RELAX_ALIGN_NEXT_OPCODE
:
9213 case RELAX_DESIRE_ALIGN
:
9217 case RELAX_MAYBE_UNREACHABLE
:
9218 case RELAX_MAYBE_DESIRE_ALIGN
:
9223 /* Just punt if we don't know the type. */
9230 /* Just punt if we don't know the type. */
9234 fragP
= fragP
->fr_next
;
9242 static long bytes_to_stretch (fragS
*, int, int, int, int);
9245 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9247 fragS
*this_frag
= fragP
;
9251 int narrow_nops
= 0;
9252 bfd_boolean paddable
= FALSE
;
9253 offsetT local_opt_diff
;
9256 int stretch_amount
= 0;
9257 int local_stretch_amount
;
9258 int global_stretch_amount
;
9260 address
= find_address_of_next_align_frag
9261 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9265 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9266 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9268 frag_wane (this_frag
);
9272 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9273 opt_diff
= local_opt_diff
;
9274 gas_assert (opt_diff
>= 0);
9275 gas_assert (max_diff
>= opt_diff
);
9280 fragP
= fragP
->fr_next
;
9282 while (fragP
&& opt_diff
< max_diff
&& address
)
9284 /* We only use these to determine if we can exit early
9285 because there will be plenty of ways to align future
9287 int glob_widens
= 0;
9290 bfd_boolean glob_pad
= 0;
9291 address
= find_address_of_next_align_frag
9292 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9293 /* If there is a padable portion, then skip. */
9294 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9299 offsetT next_m_diff
;
9300 offsetT next_o_diff
;
9302 /* Downrange frags haven't had stretch added to them yet. */
9305 /* The address also includes any text expansion from this
9306 frag in a previous pass, but we don't want that. */
9307 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9309 /* Assume we are going to move at least opt_diff. In
9310 reality, we might not be able to, but assuming that
9311 we will helps catch cases where moving opt_diff pushes
9312 the next target from aligned to unaligned. */
9313 address
+= opt_diff
;
9315 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9317 /* Now cleanup for the adjustments to address. */
9318 next_o_diff
+= opt_diff
;
9319 next_m_diff
+= opt_diff
;
9320 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9321 opt_diff
= next_o_diff
;
9322 if (next_m_diff
< max_diff
)
9323 max_diff
= next_m_diff
;
9324 fragP
= fragP
->fr_next
;
9328 /* If there are enough wideners in between, do it. */
9331 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9333 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9338 local_stretch_amount
9339 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9340 num_widens
, local_opt_diff
);
9341 global_stretch_amount
9342 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9343 num_widens
, opt_diff
);
9344 /* If the condition below is true, then the frag couldn't
9345 stretch the correct amount for the global case, so we just
9346 optimize locally. We'll rely on the subsequent frags to get
9347 the correct alignment in the global case. */
9348 if (global_stretch_amount
< local_stretch_amount
)
9349 stretch_amount
= local_stretch_amount
;
9351 stretch_amount
= global_stretch_amount
;
9353 if (this_frag
->fr_subtype
== RELAX_SLOTS
9354 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9355 gas_assert (stretch_amount
<= 1);
9356 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9358 if (this_frag
->tc_frag_data
.is_no_density
)
9359 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9361 gas_assert (stretch_amount
<= 3);
9364 return stretch_amount
;
9368 /* The idea: widen everything you can to get a target or loop aligned,
9369 then start using NOPs.
9371 wide_nops = the number of wide NOPs available for aligning
9372 narrow_nops = the number of narrow NOPs available for aligning
9373 (a subset of wide_nops)
9374 widens = the number of narrow instructions that should be widened
9379 bytes_to_stretch (fragS
*this_frag
,
9388 int bytes_short
= desired_diff
- num_widens
;
9390 gas_assert (desired_diff
>= 0
9391 && desired_diff
< (signed) xtensa_fetch_width
);
9392 if (desired_diff
== 0)
9395 gas_assert (wide_nops
> 0 || num_widens
> 0);
9397 /* Always prefer widening to NOP-filling. */
9398 if (bytes_short
< 0)
9400 /* There are enough RELAX_NARROW frags after this one
9401 to align the target without widening this frag in any way. */
9405 if (bytes_short
== 0)
9407 /* Widen every narrow between here and the align target
9408 and the align target will be properly aligned. */
9409 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9415 /* From here we will need at least one NOP to get an alignment.
9416 However, we may not be able to align at all, in which case,
9418 nops_needed
= desired_diff
/ 3;
9420 /* If there aren't enough nops, don't widen. */
9421 if (nops_needed
> wide_nops
)
9424 /* First try it with all wide nops. */
9425 nop_bytes
= nops_needed
* 3;
9426 extra_bytes
= desired_diff
- nop_bytes
;
9428 if (nop_bytes
+ num_widens
>= desired_diff
)
9430 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9432 else if (num_widens
== extra_bytes
)
9437 /* Add a narrow nop. */
9441 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9444 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9446 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9447 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9448 else if (num_widens
== extra_bytes
)
9453 /* Replace a wide nop with a narrow nop--we can get here if
9454 extra_bytes was negative in the previous conditional. */
9455 if (narrow_nops
== 1)
9459 if (nop_bytes
+ num_widens
>= desired_diff
)
9461 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9462 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9463 else if (num_widens
== extra_bytes
)
9468 /* If we can't satisfy any of the above cases, then we can't align
9469 using padding or fill nops. */
9474 static struct trampoline_frag
*
9475 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9477 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9478 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9479 struct trampoline_frag
*best_tf
= NULL
;
9482 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9483 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9484 offsetT addr
= fragP
->fr_address
;
9485 offsetT lower
= (addr
< target
) ? addr
: target
;
9486 offsetT upper
= (addr
> target
) ? addr
: target
;
9487 int delta
= upper
- lower
;
9488 offsetT midpoint
= lower
+ delta
/ 2;
9489 int this_delta
= -1;
9492 if (delta
> 2 * J_RANGE
)
9494 /* One trampoline won't do; we need multiple.
9495 Choose the farthest trampoline that's still in range of the original
9496 and let a later pass finish the job. */
9497 for ( ; tf
; tf
= tf
->next
)
9499 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9501 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9505 if (this_addr
- addr
< J_RANGE
)
9510 /* Backward jump. */
9511 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9514 if (abs (addr
- this_addr
) < J_RANGE
)
9520 for ( ; tf
; tf
= tf
->next
)
9522 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9523 this_delta
= abs (this_addr
- midpoint
);
9524 if (unreachable_only
&& tf
->needs_jump_around
)
9526 if (!best_tf
|| this_delta
< best_delta
)
9529 best_delta
= this_delta
;
9530 best_addr
= this_addr
;
9535 best_delta
< J_RANGE
&&
9536 abs(best_addr
- lower
) < J_RANGE
&&
9537 abs(best_addr
- upper
) < J_RANGE
)
9540 return NULL
; /* No suitable trampoline found. */
9544 static struct trampoline_frag
*
9545 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9547 struct trampoline_frag
*tf
= NULL
;
9549 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9552 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
9559 check_and_update_trampolines (void)
9561 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9562 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9563 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9565 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9567 if (tf
->fragP
->fr_var
< 3)
9569 frag_wane (tf
->fragP
);
9570 prev
->next
= tf
->next
;
9578 init_trampoline_frag (struct trampoline_frag
*trampP
)
9580 fragS
*fp
= trampP
->fragP
;
9583 if (fp
->fr_fix
== 0)
9586 char label
[10 + 2 * sizeof(fp
)];
9587 sprintf (label
, ".L0_TR_%p", fp
);
9589 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
9590 fp
->fr_symbol
= lsym
;
9591 if (trampP
->needs_jump_around
)
9593 /* Add a jump around this block of jumps, in case
9594 control flows into this block. */
9598 xtensa_isa isa
= xtensa_default_isa
;
9600 fp
->tc_frag_data
.is_insn
= 1;
9601 /* Assemble a jump insn. */
9603 insn
.insn_type
= ITYPE_INSN
;
9604 insn
.opcode
= xtensa_j_opcode
;
9606 set_expr_symbol_offset (&insn
.tok
[0], lsym
, 3);
9607 fmt
= xg_get_single_format (xtensa_j_opcode
);
9608 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9609 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9610 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fp
->fr_literal
, 3);
9614 fixP
= fix_new (fp
, 0, 3, lsym
, 3, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
9615 trampP
->fixP
= fixP
;
9623 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
9625 fragS
*tramp
= trampP
->fragP
;
9627 int offset
= tramp
->fr_fix
; /* Where to assemble the j insn. */
9633 xtensa_isa isa
= xtensa_default_isa
;
9636 lsym
= tramp
->fr_symbol
;
9637 /* Assemble a jump to the target label in the trampoline frag. */
9638 tsym
= origfrag
->tc_frag_data
.slot_symbols
[0];
9639 toffset
= origfrag
-> tc_frag_data
.slot_offsets
[0];
9641 insn
.insn_type
= ITYPE_INSN
;
9642 insn
.opcode
= xtensa_j_opcode
;
9644 set_expr_symbol_offset (&insn
.tok
[0], tsym
, toffset
);
9645 fmt
= xg_get_single_format (xtensa_j_opcode
);
9646 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9647 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9648 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)tramp
->fr_literal
+ offset
, 3);
9652 /* add a fix-up for the trampoline jump. */
9653 fixP
= fix_new (tramp
, tramp
->fr_fix
- 3, 3, tsym
, toffset
, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
9654 /* Modify the jump at the start of this trampoline to point past the newly-added jump. */
9655 fixP
= trampP
->fixP
;
9657 fixP
->fx_offset
+= 3;
9658 /* Modify the original j to point here. */
9659 origfrag
->tc_frag_data
.slot_symbols
[0] = lsym
;
9660 origfrag
->tc_frag_data
.slot_offsets
[0] = tramp
->fr_fix
- 3;
9661 /* If trampoline is full, remove it from the list. */
9662 check_and_update_trampolines ();
9669 relax_frag_immed (segT segP
,
9676 bfd_boolean estimate_only
)
9680 bfd_boolean negatable_branch
= FALSE
;
9681 bfd_boolean branch_jmp_to_next
= FALSE
;
9682 bfd_boolean from_wide_insn
= FALSE
;
9683 xtensa_isa isa
= xtensa_default_isa
;
9685 offsetT frag_offset
;
9687 int num_text_bytes
, num_literal_bytes
;
9688 int literal_diff
, total_text_diff
, this_text_diff
;
9690 gas_assert (fragP
->fr_opcode
!= NULL
);
9692 xg_clear_vinsn (&cur_vinsn
);
9693 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9694 if (cur_vinsn
.num_slots
> 1)
9695 from_wide_insn
= TRUE
;
9697 tinsn
= cur_vinsn
.slots
[slot
];
9698 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9700 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9703 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9704 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9706 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9708 old_size
= xtensa_format_length (isa
, fmt
);
9710 /* Special case: replace a branch to the next instruction with a NOP.
9711 This is required to work around a hardware bug in T1040.0 and also
9712 serves as an optimization. */
9714 if (branch_jmp_to_next
9715 && ((old_size
== 2) || (old_size
== 3))
9716 && !next_frag_is_loop_target (fragP
))
9719 /* Here is the fun stuff: Get the immediate field from this
9720 instruction. If it fits, we are done. If not, find the next
9721 instruction sequence that fits. */
9723 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9724 istack_init (&istack
);
9725 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9726 min_steps
, stretch
);
9727 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9729 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9731 /* Figure out the number of bytes needed. */
9732 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9734 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9735 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9740 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9743 num_text_bytes
+= old_size
;
9744 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9745 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9748 /* The first instruction in the relaxed sequence will go after
9749 the current wide instruction, and thus its symbolic immediates
9752 istack_init (&istack
);
9753 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9754 frag_offset
+ old_size
,
9755 min_steps
, stretch
+ old_size
);
9756 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9758 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9759 = (int) RELAX_IMMED
+ num_steps
;
9761 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9763 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9765 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9769 total_text_diff
= num_text_bytes
- old_size
;
9770 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9772 /* It MUST get larger. If not, we could get an infinite loop. */
9773 gas_assert (num_text_bytes
>= 0);
9774 gas_assert (literal_diff
>= 0);
9775 gas_assert (total_text_diff
>= 0);
9777 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9778 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9779 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9780 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9782 /* Find the associated expandable literal for this. */
9783 if (literal_diff
!= 0)
9785 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9788 gas_assert (literal_diff
== 4);
9789 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9791 /* We expect that the literal section state has NOT been
9793 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
9794 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9795 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9797 /* We need to mark this section for another iteration
9803 if (negatable_branch
&& istack
.ninsn
> 1)
9804 update_next_frag_state (fragP
);
9806 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
9807 if (istack
.ninsn
> 2 &&
9808 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
9809 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
9810 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
9812 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
9814 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
9816 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
9820 this_text_diff
+= init_trampoline_frag (tf
);
9821 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
9825 /* If target symbol is undefined, assume it will reach once linked. */
9826 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
9828 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
9830 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9831 _("jump target out of range; no usable trampoline found"));
9837 return this_text_diff
;
9841 /* md_convert_frag Hook and Helper Functions. */
9843 static void convert_frag_align_next_opcode (fragS
*);
9844 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9845 static void convert_frag_fill_nop (fragS
*);
9846 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9849 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9851 static xtensa_insnbuf vbuf
= NULL
;
9852 xtensa_isa isa
= xtensa_default_isa
;
9859 as_where (&file_name
, &line
);
9860 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9862 switch (fragp
->fr_subtype
)
9864 case RELAX_ALIGN_NEXT_OPCODE
:
9865 /* Always convert. */
9866 convert_frag_align_next_opcode (fragp
);
9869 case RELAX_DESIRE_ALIGN
:
9870 /* Do nothing. If not aligned already, too bad. */
9874 case RELAX_LITERAL_FINAL
:
9879 vbuf
= xtensa_insnbuf_alloc (isa
);
9881 xtensa_insnbuf_from_chars
9882 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9883 fmt
= xtensa_format_decode (isa
, vbuf
);
9884 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9886 for (slot
= 0; slot
< num_slots
; slot
++)
9888 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9891 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9895 case RELAX_IMMED_STEP1
:
9896 case RELAX_IMMED_STEP2
:
9897 case RELAX_IMMED_STEP3
:
9898 /* Place the immediate. */
9901 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9906 /* This is OK because some slots could have
9907 relaxations and others have none. */
9913 case RELAX_UNREACHABLE
:
9914 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9915 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9916 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9920 case RELAX_MAYBE_UNREACHABLE
:
9921 case RELAX_MAYBE_DESIRE_ALIGN
:
9925 case RELAX_FILL_NOP
:
9926 convert_frag_fill_nop (fragp
);
9929 case RELAX_LITERAL_NR
:
9930 if (use_literal_section
)
9932 /* This should have been handled during relaxation. When
9933 relaxing a code segment, literals sometimes need to be
9934 added to the corresponding literal segment. If that
9935 literal segment has already been relaxed, then we end up
9936 in this situation. Marking the literal segments as data
9937 would make this happen less often (since GAS always relaxes
9938 code before data), but we could still get into trouble if
9939 there are instructions in a segment that is not marked as
9940 containing code. Until we can implement a better solution,
9941 cheat and adjust the addresses of all the following frags.
9942 This could break subsequent alignments, but the linker's
9943 literal coalescing will do that anyway. */
9946 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9947 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9948 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9951 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9955 as_bad (_("invalid relaxation fragment result"));
9958 case RELAX_TRAMPOLINE
:
9963 new_logical_line (file_name
, line
);
9968 convert_frag_align_next_opcode (fragS
*fragp
)
9970 char *nop_buf
; /* Location for Writing. */
9971 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9972 addressT aligned_address
;
9976 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9978 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9979 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9980 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9982 for (nop
= 0; nop
< nop_count
; nop
++)
9985 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9987 assemble_nop (nop_size
, nop_buf
);
9988 nop_buf
+= nop_size
;
9991 fragp
->fr_fix
+= fill_size
;
9992 fragp
->fr_var
-= fill_size
;
9997 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9999 TInsn tinsn
, single_target
;
10000 int size
, old_size
, diff
;
10001 offsetT frag_offset
;
10003 gas_assert (slot
== 0);
10004 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10006 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10008 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10009 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10010 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10015 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10017 /* No conversion. */
10022 gas_assert (fragP
->fr_opcode
!= NULL
);
10024 /* Frags in this relaxation state should only contain
10025 single instruction bundles. */
10026 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10028 /* Just convert it to a wide form.... */
10030 old_size
= xg_get_single_size (tinsn
.opcode
);
10032 tinsn_init (&single_target
);
10033 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10035 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10037 as_bad (_("unable to widen instruction"));
10041 size
= xg_get_single_size (single_target
.opcode
);
10042 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10043 frag_offset
, TRUE
);
10045 diff
= size
- old_size
;
10046 gas_assert (diff
>= 0);
10047 gas_assert (diff
<= fragP
->fr_var
);
10048 fragP
->fr_var
-= diff
;
10049 fragP
->fr_fix
+= diff
;
10057 convert_frag_fill_nop (fragS
*fragP
)
10059 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10060 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10061 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10062 - fragP
->fr_address
- fragP
->fr_fix
));
10065 /* No conversion. */
10069 assemble_nop (size
, loc
);
10070 fragP
->tc_frag_data
.is_insn
= TRUE
;
10071 fragP
->fr_var
-= size
;
10072 fragP
->fr_fix
+= size
;
10077 static fixS
*fix_new_exp_in_seg
10078 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10079 bfd_reloc_code_real_type
);
10080 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10083 convert_frag_immed (segT segP
,
10089 char *immed_instr
= fragP
->fr_opcode
;
10091 bfd_boolean expanded
= FALSE
;
10092 bfd_boolean branch_jmp_to_next
= FALSE
;
10093 char *fr_opcode
= fragP
->fr_opcode
;
10094 xtensa_isa isa
= xtensa_default_isa
;
10095 bfd_boolean from_wide_insn
= FALSE
;
10097 bfd_boolean is_loop
;
10099 gas_assert (fr_opcode
!= NULL
);
10101 xg_clear_vinsn (&cur_vinsn
);
10103 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10104 if (cur_vinsn
.num_slots
> 1)
10105 from_wide_insn
= TRUE
;
10107 orig_tinsn
= cur_vinsn
.slots
[slot
];
10108 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10110 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10112 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10113 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10115 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10117 /* Conversion just inserts a NOP and marks the fix as completed. */
10118 bytes
= xtensa_format_length (isa
, fmt
);
10121 cur_vinsn
.slots
[slot
].opcode
=
10122 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10123 cur_vinsn
.slots
[slot
].ntok
= 0;
10127 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10128 gas_assert (bytes
== 2 || bytes
== 3);
10129 build_nop (&cur_vinsn
.slots
[0], bytes
);
10130 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10132 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10133 xtensa_insnbuf_to_chars
10134 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10139 /* Here is the fun stuff: Get the immediate field from this
10140 instruction. If it fits, we're done. If not, find the next
10141 instruction sequence that fits. */
10145 symbolS
*lit_sym
= NULL
;
10146 int total_size
= 0;
10147 int target_offset
= 0;
10150 symbolS
*gen_label
= NULL
;
10151 offsetT frag_offset
;
10152 bfd_boolean first
= TRUE
;
10154 /* It does not fit. Find something that does and
10155 convert immediately. */
10156 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10157 istack_init (&istack
);
10158 xg_assembly_relax (&istack
, &orig_tinsn
,
10159 segP
, fragP
, frag_offset
, min_steps
, 0);
10161 old_size
= xtensa_format_length (isa
, fmt
);
10163 /* Assemble this right inline. */
10165 /* First, create the mapping from a label name to the REAL label. */
10167 for (i
= 0; i
< istack
.ninsn
; i
++)
10169 TInsn
*tinsn
= &istack
.insn
[i
];
10172 switch (tinsn
->insn_type
)
10174 case ITYPE_LITERAL
:
10175 if (lit_sym
!= NULL
)
10176 as_bad (_("multiple literals in expansion"));
10177 /* First find the appropriate space in the literal pool. */
10178 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10179 if (lit_frag
== NULL
)
10180 as_bad (_("no registered fragment for literal"));
10181 if (tinsn
->ntok
!= 1)
10182 as_bad (_("number of literal tokens != 1"));
10184 /* Set the literal symbol and add a fixup. */
10185 lit_sym
= lit_frag
->fr_symbol
;
10189 if (align_targets
&& !is_loop
)
10191 fragS
*unreach
= fragP
->fr_next
;
10192 while (!(unreach
->fr_type
== rs_machine_dependent
10193 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10194 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10196 unreach
= unreach
->fr_next
;
10199 gas_assert (unreach
->fr_type
== rs_machine_dependent
10200 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10201 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10203 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10205 gas_assert (gen_label
== NULL
);
10206 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10207 fr_opcode
- fragP
->fr_literal
10208 + target_offset
, fragP
);
10212 if (first
&& from_wide_insn
)
10214 target_offset
+= xtensa_format_length (isa
, fmt
);
10216 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10217 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10220 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10227 for (i
= 0; i
< istack
.ninsn
; i
++)
10229 TInsn
*tinsn
= &istack
.insn
[i
];
10233 bfd_reloc_code_real_type reloc_type
;
10235 switch (tinsn
->insn_type
)
10237 case ITYPE_LITERAL
:
10238 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10239 /* Already checked. */
10240 gas_assert (lit_frag
!= NULL
);
10241 gas_assert (lit_sym
!= NULL
);
10242 gas_assert (tinsn
->ntok
== 1);
10244 target_seg
= S_GET_SEGMENT (lit_sym
);
10245 gas_assert (target_seg
);
10246 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10247 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10248 &tinsn
->tok
[0], FALSE
, reloc_type
);
10255 xg_resolve_labels (tinsn
, gen_label
);
10256 xg_resolve_literals (tinsn
, lit_sym
);
10257 if (from_wide_insn
&& first
)
10260 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10262 cur_vinsn
.slots
[slot
] = *tinsn
;
10266 cur_vinsn
.slots
[slot
].opcode
=
10267 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10268 cur_vinsn
.slots
[slot
].ntok
= 0;
10270 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10271 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10272 (unsigned char *) immed_instr
, 0);
10273 fragP
->tc_frag_data
.is_insn
= TRUE
;
10274 size
= xtensa_format_length (isa
, fmt
);
10275 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10277 xg_emit_insn_to_buf
10278 (tinsn
, immed_instr
+ size
, fragP
,
10279 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10280 size
+= xg_get_single_size (tinsn
->opcode
);
10285 size
= xg_get_single_size (tinsn
->opcode
);
10286 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10287 immed_instr
- fragP
->fr_literal
, TRUE
);
10289 immed_instr
+= size
;
10290 total_size
+= size
;
10295 diff
= total_size
- old_size
;
10296 gas_assert (diff
>= 0);
10299 gas_assert (diff
<= fragP
->fr_var
);
10300 fragP
->fr_var
-= diff
;
10301 fragP
->fr_fix
+= diff
;
10304 /* Check for undefined immediates in LOOP instructions. */
10308 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10309 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10311 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10314 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10315 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10317 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10322 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10323 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10325 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10327 /* Add an expansion note on the expanded instruction. */
10328 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10329 &orig_tinsn
.tok
[0], TRUE
,
10330 BFD_RELOC_XTENSA_ASM_EXPAND
);
10335 /* Add a new fix expression into the desired segment. We have to
10336 switch to that segment to do this. */
10339 fix_new_exp_in_seg (segT new_seg
,
10340 subsegT new_subseg
,
10346 bfd_reloc_code_real_type r_type
)
10349 segT seg
= now_seg
;
10350 subsegT subseg
= now_subseg
;
10352 gas_assert (new_seg
!= 0);
10353 subseg_set (new_seg
, new_subseg
);
10355 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10356 subseg_set (seg
, subseg
);
10361 /* Relax a loop instruction so that it can span loop >256 bytes.
10367 addi as, as, lo8 (label-.L1)
10368 addmi as, as, mid8 (label-.L1)
10379 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10384 unsigned long target
;
10385 static xtensa_insnbuf insnbuf
= NULL
;
10386 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10387 xtensa_isa isa
= xtensa_default_isa
;
10388 addressT loop_offset
;
10389 addressT addi_offset
= 9;
10390 addressT addmi_offset
= 12;
10395 insnbuf
= xtensa_insnbuf_alloc (isa
);
10397 /* Get the loop offset. */
10398 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10400 /* Validate that there really is a LOOP at the loop_offset. Because
10401 loops are not bundleable, we can assume that the instruction will be
10403 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10404 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10406 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10407 addi_offset
+= loop_offset
;
10408 addmi_offset
+= loop_offset
;
10410 gas_assert (tinsn
->ntok
== 2);
10411 if (tinsn
->tok
[1].X_op
== O_constant
)
10412 target
= tinsn
->tok
[1].X_add_number
;
10413 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10415 /* Find the fragment. */
10416 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10417 gas_assert (S_GET_SEGMENT (sym
) == segP
10418 || S_GET_SEGMENT (sym
) == absolute_section
);
10419 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10423 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10427 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10428 loop_length_hi
= loop_length
& ~0x0ff;
10429 loop_length_lo
= loop_length
& 0x0ff;
10430 if (loop_length_lo
>= 128)
10432 loop_length_lo
-= 256;
10433 loop_length_hi
+= 256;
10436 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10437 32512. If the loop is larger than that, then we just fail. */
10438 if (loop_length_hi
> 32512)
10439 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10440 _("loop too long for LOOP instruction"));
10442 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10443 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10445 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10446 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10448 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10449 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10451 fragP
->tc_frag_data
.is_insn
= TRUE
;
10452 xtensa_insnbuf_to_chars
10453 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10455 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10456 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10457 xtensa_insnbuf_to_chars
10458 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10460 /* Walk through all of the frags from here to the loop end
10461 and mark them as no_transform to keep them from being modified
10462 by the linker. If we ever have a relocation for the
10463 addi/addmi of the difference of two symbols we can remove this. */
10466 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10467 next_fragP
= next_fragP
->fr_next
)
10469 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10470 if (next_fragP
->tc_frag_data
.is_loop_target
)
10472 if (target_count
== 2)
10478 /* A map that keeps information on a per-subsegment basis. This is
10479 maintained during initial assembly, but is invalid once the
10480 subsegments are smashed together. I.E., it cannot be used during
10483 typedef struct subseg_map_struct
10491 float total_freq
; /* fall-through + branch target frequency */
10492 float target_freq
; /* branch target frequency alone */
10494 struct subseg_map_struct
*next
;
10498 static subseg_map
*sseg_map
= NULL
;
10500 static subseg_map
*
10501 get_subseg_info (segT seg
, subsegT subseg
)
10503 subseg_map
*subseg_e
;
10505 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10507 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10514 static subseg_map
*
10515 add_subseg_info (segT seg
, subsegT subseg
)
10517 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
10518 memset (subseg_e
, 0, sizeof (subseg_map
));
10519 subseg_e
->seg
= seg
;
10520 subseg_e
->subseg
= subseg
;
10521 subseg_e
->flags
= 0;
10522 /* Start off considering every branch target very important. */
10523 subseg_e
->target_freq
= 1.0;
10524 subseg_e
->total_freq
= 1.0;
10525 subseg_e
->next
= sseg_map
;
10526 sseg_map
= subseg_e
;
10532 get_last_insn_flags (segT seg
, subsegT subseg
)
10534 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10536 return subseg_e
->flags
;
10542 set_last_insn_flags (segT seg
,
10547 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10549 subseg_e
= add_subseg_info (seg
, subseg
);
10551 subseg_e
->flags
|= fl
;
10553 subseg_e
->flags
&= ~fl
;
10558 get_subseg_total_freq (segT seg
, subsegT subseg
)
10560 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10562 return subseg_e
->total_freq
;
10568 get_subseg_target_freq (segT seg
, subsegT subseg
)
10570 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10572 return subseg_e
->target_freq
;
10578 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
10580 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10582 subseg_e
= add_subseg_info (seg
, subseg
);
10583 subseg_e
->total_freq
= total_f
;
10584 subseg_e
->target_freq
= target_f
;
10588 /* Segment Lists and emit_state Stuff. */
10591 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10596 segT literal_section
= head
->seg
;
10598 /* Move the literal section to the front of the section list. */
10599 gas_assert (literal_section
);
10600 if (literal_section
!= stdoutput
->sections
)
10602 bfd_section_list_remove (stdoutput
, literal_section
);
10603 bfd_section_list_prepend (stdoutput
, literal_section
);
10610 static void mark_literal_frags (seg_list
*);
10613 xtensa_move_literals (void)
10616 frchainS
*frchain_from
, *frchain_to
;
10617 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
10618 fragS
**frag_splice
;
10621 fixS
*fix
, *next_fix
, **fix_splice
;
10624 mark_literal_frags (literal_head
->next
);
10626 if (use_literal_section
)
10629 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10631 /* Keep the literals for .init and .fini in separate sections. */
10632 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10633 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10636 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10637 search_frag
= frchain_from
->frch_root
;
10638 literal_pool
= NULL
;
10640 frag_splice
= &(frchain_from
->frch_root
);
10642 while (!search_frag
->tc_frag_data
.literal_frag
)
10644 gas_assert (search_frag
->fr_fix
== 0
10645 || search_frag
->fr_type
== rs_align
);
10646 search_frag
= search_frag
->fr_next
;
10649 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10650 == RELAX_LITERAL_POOL_BEGIN
);
10651 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10653 /* Make sure that all the frags in this series are closed, and
10654 that there is at least one left over of zero-size. This
10655 prevents us from making a segment with an frchain without any
10657 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10658 xtensa_set_frag_assembly_state (frag_now
);
10659 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10660 xtensa_set_frag_assembly_state (frag_now
);
10662 while (search_frag
!= frag_now
)
10664 next_frag
= search_frag
->fr_next
;
10666 /* First, move the frag out of the literal section and
10667 to the appropriate place. */
10668 if (search_frag
->tc_frag_data
.literal_frag
)
10670 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10671 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10672 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10673 gas_assert (frchain_to
);
10675 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10676 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10678 *frag_splice
= next_frag
;
10679 search_frag
->fr_next
= insert_after
->fr_next
;
10680 insert_after
->fr_next
= search_frag
;
10681 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10682 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10684 /* Now move any fixups associated with this frag to the
10686 fix
= frchain_from
->fix_root
;
10687 fix_splice
= &(frchain_from
->fix_root
);
10690 next_fix
= fix
->fx_next
;
10691 if (fix
->fx_frag
== search_frag
)
10693 *fix_splice
= next_fix
;
10694 fix
->fx_next
= frchain_to
->fix_root
;
10695 frchain_to
->fix_root
= fix
;
10696 if (frchain_to
->fix_tail
== NULL
)
10697 frchain_to
->fix_tail
= fix
;
10700 fix_splice
= &(fix
->fx_next
);
10703 search_frag
= next_frag
;
10706 if (frchain_from
->fix_root
!= NULL
)
10708 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10709 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10711 gas_assert (frchain_from
->fix_root
== NULL
);
10713 frchain_from
->fix_tail
= NULL
;
10714 xtensa_restore_emit_state (&state
);
10717 /* Now fix up the SEGMENT value for all the literal symbols. */
10718 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10720 symbolS
*lit_sym
= lit
->sym
;
10721 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10723 S_SET_SEGMENT (lit_sym
, dseg
);
10728 /* Walk over all the frags for segments in a list and mark them as
10729 containing literals. As clunky as this is, we can't rely on frag_var
10730 and frag_variant to get called in all situations. */
10733 mark_literal_frags (seg_list
*segment
)
10735 frchainS
*frchain_from
;
10736 fragS
*search_frag
;
10740 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10741 search_frag
= frchain_from
->frch_root
;
10742 while (search_frag
)
10744 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10745 search_frag
= search_frag
->fr_next
;
10747 segment
= segment
->next
;
10753 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10755 /* Move all of the sections in the section list to come
10756 after "after" in the gnu segment list. */
10761 segT literal_section
= head
->seg
;
10763 /* Move the literal section after "after". */
10764 gas_assert (literal_section
);
10765 if (literal_section
!= after
)
10767 bfd_section_list_remove (stdoutput
, literal_section
);
10768 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10776 /* Push all the literal segments to the end of the gnu list. */
10779 xtensa_reorder_segments (void)
10786 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10792 /* Now that we have the last section, push all the literal
10793 sections to the end. */
10794 xtensa_reorder_seg_list (literal_head
, last_sec
);
10796 /* Now perform the final error check. */
10797 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10799 gas_assert (new_count
== old_count
);
10803 /* Change the emit state (seg, subseg, and frag related stuff) to the
10804 correct location. Return a emit_state which can be passed to
10805 xtensa_restore_emit_state to return to current fragment. */
10808 xtensa_switch_to_literal_fragment (emit_state
*result
)
10810 if (directive_state
[directive_absolute_literals
])
10812 segT lit4_seg
= cache_literal_section (TRUE
);
10813 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10816 xtensa_switch_to_non_abs_literal_fragment (result
);
10818 /* Do a 4-byte align here. */
10819 frag_align (2, 0, 0);
10820 record_alignment (now_seg
, 2);
10825 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10827 static bfd_boolean recursive
= FALSE
;
10828 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10830 bfd_boolean is_init
=
10831 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10832 bfd_boolean is_fini
=
10833 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10835 if (pool_location
== NULL
10836 && !use_literal_section
10838 && !is_init
&& ! is_fini
)
10840 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10842 /* When we mark a literal pool location, we want to put a frag in
10843 the literal pool that points to it. But to do that, we want to
10844 switch_to_literal_fragment. But literal sections don't have
10845 literal pools, so their location is always null, so we would
10846 recurse forever. This is kind of hacky, but it works. */
10849 xtensa_mark_literal_pool_location ();
10853 lit_seg
= cache_literal_section (FALSE
);
10854 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10856 if (!use_literal_section
10857 && !is_init
&& !is_fini
10858 && get_literal_pool_location (now_seg
) != pool_location
)
10860 /* Close whatever frag is there. */
10861 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10862 xtensa_set_frag_assembly_state (frag_now
);
10863 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10864 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10865 xtensa_set_frag_assembly_state (frag_now
);
10870 /* Call this function before emitting data into the literal section.
10871 This is a helper function for xtensa_switch_to_literal_fragment.
10872 This is similar to a .section new_now_seg subseg. */
10875 xtensa_switch_section_emit_state (emit_state
*state
,
10877 subsegT new_now_subseg
)
10879 state
->name
= now_seg
->name
;
10880 state
->now_seg
= now_seg
;
10881 state
->now_subseg
= now_subseg
;
10882 state
->generating_literals
= generating_literals
;
10883 generating_literals
++;
10884 subseg_set (new_now_seg
, new_now_subseg
);
10888 /* Use to restore the emitting into the normal place. */
10891 xtensa_restore_emit_state (emit_state
*state
)
10893 generating_literals
= state
->generating_literals
;
10894 subseg_set (state
->now_seg
, state
->now_subseg
);
10898 /* Predicate function used to look up a section in a particular group. */
10901 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10903 const char *gname
= inf
;
10904 const char *group_name
= elf_group_name (sec
);
10906 return (group_name
== gname
10907 || (group_name
!= NULL
10909 && strcmp (group_name
, gname
) == 0));
10913 /* Get the literal section to be used for the current text section.
10914 The result may be cached in the default_lit_sections structure. */
10917 cache_literal_section (bfd_boolean use_abs_literals
)
10919 const char *text_name
, *group_name
= 0;
10920 char *base_name
, *name
, *suffix
;
10922 segT seg
, current_section
;
10923 int current_subsec
;
10924 bfd_boolean linkonce
= FALSE
;
10926 /* Save the current section/subsection. */
10927 current_section
= now_seg
;
10928 current_subsec
= now_subseg
;
10930 /* Clear the cached values if they are no longer valid. */
10931 if (now_seg
!= default_lit_sections
.current_text_seg
)
10933 default_lit_sections
.current_text_seg
= now_seg
;
10934 default_lit_sections
.lit_seg
= NULL
;
10935 default_lit_sections
.lit4_seg
= NULL
;
10938 /* Check if the literal section is already cached. */
10939 if (use_abs_literals
)
10940 pcached
= &default_lit_sections
.lit4_seg
;
10942 pcached
= &default_lit_sections
.lit_seg
;
10947 text_name
= default_lit_sections
.lit_prefix
;
10948 if (! text_name
|| ! *text_name
)
10950 text_name
= segment_name (current_section
);
10951 group_name
= elf_group_name (current_section
);
10952 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10955 base_name
= use_abs_literals
? ".lit4" : ".literal";
10958 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10959 sprintf (name
, "%s.%s", base_name
, group_name
);
10961 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10963 suffix
= strchr (text_name
+ linkonce_len
, '.');
10965 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10966 + (suffix
? strlen (suffix
) : 0));
10967 strcpy (name
, ".gnu.linkonce");
10968 strcat (name
, base_name
);
10970 strcat (name
, suffix
);
10975 /* If the section name begins or ends with ".text", then replace
10976 that portion instead of appending an additional suffix. */
10977 size_t len
= strlen (text_name
);
10979 && (strcmp (text_name
+ len
- 5, ".text") == 0
10980 || strncmp (text_name
, ".text", 5) == 0))
10983 name
= xmalloc (len
+ strlen (base_name
) + 1);
10984 if (strncmp (text_name
, ".text", 5) == 0)
10986 strcpy (name
, base_name
);
10987 strcat (name
, text_name
+ 5);
10991 strcpy (name
, text_name
);
10992 strcpy (name
+ len
, base_name
);
10996 /* Canonicalize section names to allow renaming literal sections.
10997 The group name, if any, came from the current text section and
10998 has already been canonicalized. */
10999 name
= tc_canonicalize_symbol_name (name
);
11001 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11002 (void *) group_name
);
11007 seg
= subseg_force_new (name
, 0);
11009 if (! use_abs_literals
)
11011 /* Add the newly created literal segment to the list. */
11012 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
11014 n
->next
= literal_head
->next
;
11015 literal_head
->next
= n
;
11018 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11019 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11020 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11022 elf_group_name (seg
) = group_name
;
11024 bfd_set_section_flags (stdoutput
, seg
, flags
);
11025 bfd_set_section_alignment (stdoutput
, seg
, 2);
11029 subseg_set (current_section
, current_subsec
);
11034 /* Property Tables Stuff. */
11036 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11037 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11038 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11040 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11041 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11043 static bfd_boolean
get_frag_is_literal (const fragS
*);
11044 static void xtensa_create_property_segments
11045 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11046 static void xtensa_create_xproperty_segments
11047 (frag_flags_fn
, const char *, xt_section_type
);
11048 static bfd_boolean
exclude_section_from_property_tables (segT
);
11049 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11050 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11051 static void add_xt_block_frags
11052 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11053 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11054 static void xtensa_frag_flags_init (frag_flags
*);
11055 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11056 static flagword
frag_flags_to_number (const frag_flags
*);
11057 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11059 /* Set up property tables after relaxation. */
11062 xtensa_post_relax_hook (void)
11064 xtensa_move_seg_list_to_beginning (literal_head
);
11066 xtensa_find_unmarked_state_frags ();
11067 xtensa_mark_frags_for_org ();
11068 xtensa_mark_difference_of_two_symbols ();
11070 xtensa_create_property_segments (get_frag_is_literal
,
11072 XTENSA_LIT_SEC_NAME
,
11074 xtensa_create_xproperty_segments (get_frag_property_flags
,
11075 XTENSA_PROP_SEC_NAME
,
11078 if (warn_unaligned_branch_targets
)
11079 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11080 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11084 /* This function is only meaningful after xtensa_move_literals. */
11087 get_frag_is_literal (const fragS
*fragP
)
11089 gas_assert (fragP
!= NULL
);
11090 return fragP
->tc_frag_data
.is_literal
;
11095 xtensa_create_property_segments (frag_predicate property_function
,
11096 frag_predicate end_property_function
,
11097 const char *section_name_base
,
11098 xt_section_type sec_type
)
11102 /* Walk over all of the current segments.
11103 Walk over each fragment
11104 For each non-empty fragment,
11105 Build a property record (append where possible). */
11107 for (seclist
= &stdoutput
->sections
;
11108 seclist
&& *seclist
;
11109 seclist
= &(*seclist
)->next
)
11111 segT sec
= *seclist
;
11113 if (exclude_section_from_property_tables (sec
))
11116 if (section_has_property (sec
, property_function
))
11118 segment_info_type
*xt_seg_info
;
11119 xtensa_block_info
**xt_blocks
;
11120 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11122 prop_sec
->output_section
= prop_sec
;
11123 subseg_set (prop_sec
, 0);
11124 xt_seg_info
= seg_info (prop_sec
);
11125 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11127 /* Walk over all of the frchains here and add new sections. */
11128 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11129 end_property_function
);
11133 /* Now we fill them out.... */
11135 for (seclist
= &stdoutput
->sections
;
11136 seclist
&& *seclist
;
11137 seclist
= &(*seclist
)->next
)
11139 segment_info_type
*seginfo
;
11140 xtensa_block_info
*block
;
11141 segT sec
= *seclist
;
11143 seginfo
= seg_info (sec
);
11144 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11148 xtensa_block_info
*cur_block
;
11150 bfd_size_type rec_size
;
11152 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11155 rec_size
= num_recs
* 8;
11156 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11163 subseg_set (sec
, 0);
11164 frag_data
= frag_more (rec_size
);
11166 for (i
= 0; i
< num_recs
; i
++)
11170 /* Write the fixup. */
11171 gas_assert (cur_block
);
11172 fix
= fix_new (frag_now
, i
* 8, 4,
11173 section_symbol (cur_block
->sec
),
11175 FALSE
, BFD_RELOC_32
);
11176 fix
->fx_file
= "<internal>";
11179 /* Write the length. */
11180 md_number_to_chars (&frag_data
[4 + i
* 8],
11181 cur_block
->size
, 4);
11182 cur_block
= cur_block
->next
;
11184 frag_wane (frag_now
);
11186 frag_wane (frag_now
);
11194 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11195 const char *section_name_base
,
11196 xt_section_type sec_type
)
11200 /* Walk over all of the current segments.
11201 Walk over each fragment.
11202 For each fragment that has instructions,
11203 build an instruction record (append where possible). */
11205 for (seclist
= &stdoutput
->sections
;
11206 seclist
&& *seclist
;
11207 seclist
= &(*seclist
)->next
)
11209 segT sec
= *seclist
;
11211 if (exclude_section_from_property_tables (sec
))
11214 if (section_has_xproperty (sec
, flag_fn
))
11216 segment_info_type
*xt_seg_info
;
11217 xtensa_block_info
**xt_blocks
;
11218 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11220 prop_sec
->output_section
= prop_sec
;
11221 subseg_set (prop_sec
, 0);
11222 xt_seg_info
= seg_info (prop_sec
);
11223 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11225 /* Walk over all of the frchains here and add new sections. */
11226 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11230 /* Now we fill them out.... */
11232 for (seclist
= &stdoutput
->sections
;
11233 seclist
&& *seclist
;
11234 seclist
= &(*seclist
)->next
)
11236 segment_info_type
*seginfo
;
11237 xtensa_block_info
*block
;
11238 segT sec
= *seclist
;
11240 seginfo
= seg_info (sec
);
11241 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11245 xtensa_block_info
*cur_block
;
11247 bfd_size_type rec_size
;
11249 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11252 rec_size
= num_recs
* (8 + 4);
11253 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11254 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11261 subseg_set (sec
, 0);
11262 frag_data
= frag_more (rec_size
);
11264 for (i
= 0; i
< num_recs
; i
++)
11268 /* Write the fixup. */
11269 gas_assert (cur_block
);
11270 fix
= fix_new (frag_now
, i
* 12, 4,
11271 section_symbol (cur_block
->sec
),
11273 FALSE
, BFD_RELOC_32
);
11274 fix
->fx_file
= "<internal>";
11277 /* Write the length. */
11278 md_number_to_chars (&frag_data
[4 + i
* 12],
11279 cur_block
->size
, 4);
11280 md_number_to_chars (&frag_data
[8 + i
* 12],
11281 frag_flags_to_number (&cur_block
->flags
),
11282 sizeof (flagword
));
11283 cur_block
= cur_block
->next
;
11285 frag_wane (frag_now
);
11287 frag_wane (frag_now
);
11295 exclude_section_from_property_tables (segT sec
)
11297 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11299 /* Sections that don't contribute to the memory footprint are excluded. */
11300 if ((flags
& SEC_DEBUGGING
)
11301 || !(flags
& SEC_ALLOC
)
11302 || (flags
& SEC_MERGE
))
11305 /* Linker cie and fde optimizations mess up property entries for
11306 eh_frame sections, but there is nothing inside them relevant to
11307 property tables anyway. */
11308 if (strcmp (sec
->name
, ".eh_frame") == 0)
11316 section_has_property (segT sec
, frag_predicate property_function
)
11318 segment_info_type
*seginfo
= seg_info (sec
);
11321 if (seginfo
&& seginfo
->frchainP
)
11323 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11325 if (property_function (fragP
)
11326 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11335 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11337 segment_info_type
*seginfo
= seg_info (sec
);
11340 if (seginfo
&& seginfo
->frchainP
)
11342 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11344 frag_flags prop_flags
;
11345 property_function (fragP
, &prop_flags
);
11346 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11354 /* Two types of block sections exist right now: literal and insns. */
11357 add_xt_block_frags (segT sec
,
11358 xtensa_block_info
**xt_block
,
11359 frag_predicate property_function
,
11360 frag_predicate end_property_function
)
11364 /* Build it if needed. */
11365 while (*xt_block
!= NULL
)
11366 xt_block
= &(*xt_block
)->next
;
11367 /* We are either at NULL at the beginning or at the end. */
11369 /* Walk through the frags. */
11370 if (seg_info (sec
)->frchainP
)
11372 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11374 fragP
= fragP
->fr_next
)
11376 if (property_function (fragP
)
11377 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11379 if (*xt_block
!= NULL
)
11381 if ((*xt_block
)->offset
+ (*xt_block
)->size
11382 == fragP
->fr_address
)
11383 (*xt_block
)->size
+= fragP
->fr_fix
;
11385 xt_block
= &((*xt_block
)->next
);
11387 if (*xt_block
== NULL
)
11389 xtensa_block_info
*new_block
= (xtensa_block_info
*)
11390 xmalloc (sizeof (xtensa_block_info
));
11391 new_block
->sec
= sec
;
11392 new_block
->offset
= fragP
->fr_address
;
11393 new_block
->size
= fragP
->fr_fix
;
11394 new_block
->next
= NULL
;
11395 xtensa_frag_flags_init (&new_block
->flags
);
11396 *xt_block
= new_block
;
11398 if (end_property_function
11399 && end_property_function (fragP
))
11401 xt_block
= &((*xt_block
)->next
);
11409 /* Break the encapsulation of add_xt_prop_frags here. */
11412 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
11414 if (prop_flags
->is_literal
11415 || prop_flags
->is_insn
11416 || prop_flags
->is_data
11417 || prop_flags
->is_unreachable
)
11424 xtensa_frag_flags_init (frag_flags
*prop_flags
)
11426 memset (prop_flags
, 0, sizeof (frag_flags
));
11431 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
11433 xtensa_frag_flags_init (prop_flags
);
11434 if (fragP
->tc_frag_data
.is_literal
)
11435 prop_flags
->is_literal
= TRUE
;
11436 if (fragP
->tc_frag_data
.is_specific_opcode
11437 || fragP
->tc_frag_data
.is_no_transform
)
11439 prop_flags
->is_no_transform
= TRUE
;
11440 if (xtensa_frag_flags_is_empty (prop_flags
))
11441 prop_flags
->is_data
= TRUE
;
11443 if (fragP
->tc_frag_data
.is_unreachable
)
11444 prop_flags
->is_unreachable
= TRUE
;
11445 else if (fragP
->tc_frag_data
.is_insn
)
11447 prop_flags
->is_insn
= TRUE
;
11448 if (fragP
->tc_frag_data
.is_loop_target
)
11449 prop_flags
->insn
.is_loop_target
= TRUE
;
11450 if (fragP
->tc_frag_data
.is_branch_target
)
11451 prop_flags
->insn
.is_branch_target
= TRUE
;
11452 if (fragP
->tc_frag_data
.is_no_density
)
11453 prop_flags
->insn
.is_no_density
= TRUE
;
11454 if (fragP
->tc_frag_data
.use_absolute_literals
)
11455 prop_flags
->insn
.is_abslit
= TRUE
;
11457 if (fragP
->tc_frag_data
.is_align
)
11459 prop_flags
->is_align
= TRUE
;
11460 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
11461 if (xtensa_frag_flags_is_empty (prop_flags
))
11462 prop_flags
->is_data
= TRUE
;
11468 frag_flags_to_number (const frag_flags
*prop_flags
)
11471 if (prop_flags
->is_literal
)
11472 num
|= XTENSA_PROP_LITERAL
;
11473 if (prop_flags
->is_insn
)
11474 num
|= XTENSA_PROP_INSN
;
11475 if (prop_flags
->is_data
)
11476 num
|= XTENSA_PROP_DATA
;
11477 if (prop_flags
->is_unreachable
)
11478 num
|= XTENSA_PROP_UNREACHABLE
;
11479 if (prop_flags
->insn
.is_loop_target
)
11480 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
11481 if (prop_flags
->insn
.is_branch_target
)
11483 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
11484 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
11487 if (prop_flags
->insn
.is_no_density
)
11488 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
11489 if (prop_flags
->is_no_transform
)
11490 num
|= XTENSA_PROP_NO_TRANSFORM
;
11491 if (prop_flags
->insn
.is_no_reorder
)
11492 num
|= XTENSA_PROP_INSN_NO_REORDER
;
11493 if (prop_flags
->insn
.is_abslit
)
11494 num
|= XTENSA_PROP_INSN_ABSLIT
;
11496 if (prop_flags
->is_align
)
11498 num
|= XTENSA_PROP_ALIGN
;
11499 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
11507 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
11508 const frag_flags
*prop_flags_2
)
11510 /* Cannot combine with an end marker. */
11512 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
11514 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
11516 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
11519 if (prop_flags_1
->is_insn
)
11521 /* Properties of the beginning of the frag. */
11522 if (prop_flags_2
->insn
.is_loop_target
)
11524 if (prop_flags_2
->insn
.is_branch_target
)
11526 if (prop_flags_1
->insn
.is_no_density
!=
11527 prop_flags_2
->insn
.is_no_density
)
11529 if (prop_flags_1
->is_no_transform
!=
11530 prop_flags_2
->is_no_transform
)
11532 if (prop_flags_1
->insn
.is_no_reorder
!=
11533 prop_flags_2
->insn
.is_no_reorder
)
11535 if (prop_flags_1
->insn
.is_abslit
!=
11536 prop_flags_2
->insn
.is_abslit
)
11540 if (prop_flags_1
->is_align
)
11548 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
11551 unsigned align_bits
;
11553 if (!xt_block
->flags
.is_align
)
11554 return xt_block
->size
;
11556 end_addr
= xt_block
->offset
+ xt_block
->size
;
11557 align_bits
= xt_block
->flags
.alignment
;
11558 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
11559 return end_addr
- xt_block
->offset
;
11564 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
11565 const xtensa_block_info
*xt_block_2
)
11567 if (xt_block
->sec
!= xt_block_2
->sec
)
11569 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
11570 != xt_block_2
->offset
)
11573 if (xt_block_2
->size
== 0
11574 && (!xt_block_2
->flags
.is_unreachable
11575 || xt_block
->flags
.is_unreachable
))
11577 if (xt_block_2
->flags
.is_align
11578 && xt_block
->flags
.is_align
)
11580 /* Nothing needed. */
11581 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
11586 if (xt_block_2
->flags
.is_align
)
11588 /* Push alignment to previous entry. */
11589 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
11590 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11595 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11596 &xt_block_2
->flags
))
11599 xt_block
->size
+= xt_block_2
->size
;
11601 if (xt_block_2
->flags
.is_align
)
11603 xt_block
->flags
.is_align
= TRUE
;
11604 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11612 add_xt_prop_frags (segT sec
,
11613 xtensa_block_info
**xt_block
,
11614 frag_flags_fn property_function
)
11618 /* Build it if needed. */
11619 while (*xt_block
!= NULL
)
11621 xt_block
= &(*xt_block
)->next
;
11623 /* We are either at NULL at the beginning or at the end. */
11625 /* Walk through the frags. */
11626 if (seg_info (sec
)->frchainP
)
11628 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11629 fragP
= fragP
->fr_next
)
11631 xtensa_block_info tmp_block
;
11632 tmp_block
.sec
= sec
;
11633 tmp_block
.offset
= fragP
->fr_address
;
11634 tmp_block
.size
= fragP
->fr_fix
;
11635 tmp_block
.next
= NULL
;
11636 property_function (fragP
, &tmp_block
.flags
);
11638 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11639 /* && fragP->fr_fix != 0) */
11641 if ((*xt_block
) == NULL
11642 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11644 xtensa_block_info
*new_block
;
11645 if ((*xt_block
) != NULL
)
11646 xt_block
= &(*xt_block
)->next
;
11647 new_block
= (xtensa_block_info
*)
11648 xmalloc (sizeof (xtensa_block_info
));
11649 *new_block
= tmp_block
;
11650 *xt_block
= new_block
;
11658 /* op_placement_info_table */
11660 /* op_placement_info makes it easier to determine which
11661 ops can go in which slots. */
11664 init_op_placement_info_table (void)
11666 xtensa_isa isa
= xtensa_default_isa
;
11667 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11668 xtensa_opcode opcode
;
11671 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11673 op_placement_table
= (op_placement_info_table
)
11674 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11675 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11677 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11679 op_placement_info
*opi
= &op_placement_table
[opcode
];
11680 /* FIXME: Make tinsn allocation dynamic. */
11681 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11682 as_fatal (_("too many operands in instruction"));
11683 opi
->narrowest
= XTENSA_UNDEFINED
;
11684 opi
->narrowest_size
= 0x7F;
11685 opi
->narrowest_slot
= 0;
11687 opi
->num_formats
= 0;
11689 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11691 opi
->slots
[fmt
] = 0;
11692 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11694 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11696 int fmt_length
= xtensa_format_length (isa
, fmt
);
11698 set_bit (fmt
, opi
->formats
);
11699 set_bit (slot
, opi
->slots
[fmt
]);
11700 if (fmt_length
< opi
->narrowest_size
11701 || (fmt_length
== opi
->narrowest_size
11702 && (xtensa_format_num_slots (isa
, fmt
)
11703 < xtensa_format_num_slots (isa
,
11706 opi
->narrowest
= fmt
;
11707 opi
->narrowest_size
= fmt_length
;
11708 opi
->narrowest_slot
= slot
;
11713 opi
->num_formats
++;
11716 xtensa_insnbuf_free (isa
, ibuf
);
11721 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11723 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11727 /* If the opcode is available in a single slot format, return its size. */
11730 xg_get_single_size (xtensa_opcode opcode
)
11732 return op_placement_table
[opcode
].narrowest_size
;
11736 static xtensa_format
11737 xg_get_single_format (xtensa_opcode opcode
)
11739 return op_placement_table
[opcode
].narrowest
;
11744 xg_get_single_slot (xtensa_opcode opcode
)
11746 return op_placement_table
[opcode
].narrowest_slot
;
11750 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11753 istack_init (IStack
*stack
)
11760 istack_empty (IStack
*stack
)
11762 return (stack
->ninsn
== 0);
11767 istack_full (IStack
*stack
)
11769 return (stack
->ninsn
== MAX_ISTACK
);
11773 /* Return a pointer to the top IStack entry.
11774 It is an error to call this if istack_empty () is TRUE. */
11777 istack_top (IStack
*stack
)
11779 int rec
= stack
->ninsn
- 1;
11780 gas_assert (!istack_empty (stack
));
11781 return &stack
->insn
[rec
];
11785 /* Add a new TInsn to an IStack.
11786 It is an error to call this if istack_full () is TRUE. */
11789 istack_push (IStack
*stack
, TInsn
*insn
)
11791 int rec
= stack
->ninsn
;
11792 gas_assert (!istack_full (stack
));
11793 stack
->insn
[rec
] = *insn
;
11798 /* Clear space for the next TInsn on the IStack and return a pointer
11799 to it. It is an error to call this if istack_full () is TRUE. */
11802 istack_push_space (IStack
*stack
)
11804 int rec
= stack
->ninsn
;
11806 gas_assert (!istack_full (stack
));
11807 insn
= &stack
->insn
[rec
];
11814 /* Remove the last pushed instruction. It is an error to call this if
11815 istack_empty () returns TRUE. */
11818 istack_pop (IStack
*stack
)
11820 int rec
= stack
->ninsn
- 1;
11821 gas_assert (!istack_empty (stack
));
11823 tinsn_init (&stack
->insn
[rec
]);
11827 /* TInsn functions. */
11830 tinsn_init (TInsn
*dst
)
11832 memset (dst
, 0, sizeof (TInsn
));
11836 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11839 tinsn_has_symbolic_operands (const TInsn
*insn
)
11842 int n
= insn
->ntok
;
11844 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11846 for (i
= 0; i
< n
; ++i
)
11848 switch (insn
->tok
[i
].X_op
)
11862 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11864 xtensa_isa isa
= xtensa_default_isa
;
11866 int n
= insn
->ntok
;
11868 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11870 for (i
= 0; i
< n
; ++i
)
11872 switch (insn
->tok
[i
].X_op
)
11880 /* Errors for these types are caught later. */
11885 /* Symbolic immediates are only allowed on the last immediate
11886 operand. At this time, CONST16 is the only opcode where we
11887 support non-PC-relative relocations. */
11888 if (i
!= get_relaxable_immed (insn
->opcode
)
11889 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11890 && insn
->opcode
!= xtensa_const16_opcode
))
11892 as_bad (_("invalid symbolic operand"));
11901 /* For assembly code with complex expressions (e.g. subtraction),
11902 we have to build them in the literal pool so that
11903 their results are calculated correctly after relaxation.
11904 The relaxation only handles expressions that
11905 boil down to SYMBOL + OFFSET. */
11908 tinsn_has_complex_operands (const TInsn
*insn
)
11911 int n
= insn
->ntok
;
11912 gas_assert (insn
->insn_type
== ITYPE_INSN
);
11913 for (i
= 0; i
< n
; ++i
)
11915 switch (insn
->tok
[i
].X_op
)
11931 /* Encode a TInsn opcode and its constant operands into slotbuf.
11932 Return TRUE if there is a symbol in the immediate field. This
11933 function assumes that:
11934 1) The number of operands are correct.
11935 2) The insn_type is ITYPE_INSN.
11936 3) The opcode can be encoded in the specified format and slot.
11937 4) Operands are either O_constant or O_symbol, and all constants fit. */
11940 tinsn_to_slotbuf (xtensa_format fmt
,
11943 xtensa_insnbuf slotbuf
)
11945 xtensa_isa isa
= xtensa_default_isa
;
11946 xtensa_opcode opcode
= tinsn
->opcode
;
11947 bfd_boolean has_fixup
= FALSE
;
11948 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11951 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
11952 if (noperands
!= tinsn
->ntok
)
11953 as_fatal (_("operand number mismatch"));
11955 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11957 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11958 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11962 for (i
= 0; i
< noperands
; i
++)
11964 expressionS
*exp
= &tinsn
->tok
[i
];
11973 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11975 /* The register number has already been checked in
11976 expression_maybe_register, so we don't need to check here. */
11977 opnd_value
= exp
->X_add_number
;
11978 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11979 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11982 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11986 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11988 as_where (&file_name
, &line
);
11989 /* It is a constant and we called this function
11990 then we have to try to fit it. */
11991 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11992 exp
->X_add_number
, file_name
, line
);
12005 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12006 into a multi-slot instruction, fill the other slots with NOPs.
12007 Return TRUE if there is a symbol in the immediate field. See also the
12008 assumptions listed for tinsn_to_slotbuf. */
12011 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12013 static xtensa_insnbuf slotbuf
= 0;
12014 static vliw_insn vinsn
;
12015 xtensa_isa isa
= xtensa_default_isa
;
12016 bfd_boolean has_fixup
= FALSE
;
12021 slotbuf
= xtensa_insnbuf_alloc (isa
);
12022 xg_init_vinsn (&vinsn
);
12025 xg_clear_vinsn (&vinsn
);
12027 bundle_tinsn (tinsn
, &vinsn
);
12029 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12031 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12033 /* Only one slot may have a fix-up because the rest contains NOPs. */
12035 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12036 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12043 /* Check the instruction arguments. Return TRUE on failure. */
12046 tinsn_check_arguments (const TInsn
*insn
)
12048 xtensa_isa isa
= xtensa_default_isa
;
12049 xtensa_opcode opcode
= insn
->opcode
;
12050 xtensa_regfile t1_regfile
, t2_regfile
;
12051 int t1_reg
, t2_reg
;
12052 int t1_base_reg
, t1_last_reg
;
12053 int t2_base_reg
, t2_last_reg
;
12054 char t1_inout
, t2_inout
;
12057 if (opcode
== XTENSA_UNDEFINED
)
12059 as_bad (_("invalid opcode"));
12063 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12065 as_bad (_("too few operands"));
12069 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12071 as_bad (_("too many operands"));
12075 /* Check registers. */
12076 for (j
= 0; j
< insn
->ntok
; j
++)
12078 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12081 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12082 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12084 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12086 for (i
= 0; i
< insn
->ntok
; i
++)
12091 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12094 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12096 if (t1_regfile
!= t2_regfile
)
12099 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12100 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12102 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12103 t1_last_reg
= (t1_base_reg
12104 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12106 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12108 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12110 if (t1_reg
!= t2_reg
)
12113 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12115 as_bad (_("multiple writes to the same register"));
12126 /* Load an instruction from its encoded form. */
12129 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12133 xg_init_vinsn (&vinsn
);
12134 vinsn_from_chars (&vinsn
, f
);
12136 *tinsn
= vinsn
.slots
[slot
];
12137 xg_free_vinsn (&vinsn
);
12142 tinsn_from_insnbuf (TInsn
*tinsn
,
12143 xtensa_insnbuf slotbuf
,
12148 xtensa_isa isa
= xtensa_default_isa
;
12150 /* Find the immed. */
12151 tinsn_init (tinsn
);
12152 tinsn
->insn_type
= ITYPE_INSN
;
12153 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12154 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12155 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12156 for (i
= 0; i
< tinsn
->ntok
; i
++)
12158 set_expr_const (&tinsn
->tok
[i
],
12159 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12160 tinsn
->opcode
, i
));
12165 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12168 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12170 xtensa_opcode opcode
= tinsn
->opcode
;
12173 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12175 opnum
= get_relaxable_immed (opcode
);
12176 gas_assert (opnum
>= 0);
12177 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12178 fragP
->tc_frag_data
.slot_symbols
[slot
],
12179 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12181 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12186 get_num_stack_text_bytes (IStack
*istack
)
12189 int text_bytes
= 0;
12191 for (i
= 0; i
< istack
->ninsn
; i
++)
12193 TInsn
*tinsn
= &istack
->insn
[i
];
12194 if (tinsn
->insn_type
== ITYPE_INSN
)
12195 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12202 get_num_stack_literal_bytes (IStack
*istack
)
12207 for (i
= 0; i
< istack
->ninsn
; i
++)
12209 TInsn
*tinsn
= &istack
->insn
[i
];
12210 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12217 /* vliw_insn functions. */
12220 xg_init_vinsn (vliw_insn
*v
)
12223 xtensa_isa isa
= xtensa_default_isa
;
12225 xg_clear_vinsn (v
);
12227 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12228 if (v
->insnbuf
== NULL
)
12229 as_fatal (_("out of memory"));
12231 for (i
= 0; i
< config_max_slots
; i
++)
12233 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12234 if (v
->slotbuf
[i
] == NULL
)
12235 as_fatal (_("out of memory"));
12241 xg_clear_vinsn (vliw_insn
*v
)
12245 memset (v
, 0, offsetof (vliw_insn
, slots
)
12246 + sizeof(TInsn
) * config_max_slots
);
12248 v
->format
= XTENSA_UNDEFINED
;
12250 v
->inside_bundle
= FALSE
;
12252 if (xt_saved_debug_type
!= DEBUG_NONE
)
12253 debug_type
= xt_saved_debug_type
;
12255 for (i
= 0; i
< config_max_slots
; i
++)
12256 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12261 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12264 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12265 dst
->insnbuf
= src
->insnbuf
;
12266 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12271 vinsn_has_specific_opcodes (vliw_insn
*v
)
12275 for (i
= 0; i
< v
->num_slots
; i
++)
12277 if (v
->slots
[i
].is_specific_opcode
)
12285 xg_free_vinsn (vliw_insn
*v
)
12288 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12289 for (i
= 0; i
< config_max_slots
; i
++)
12290 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12294 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12295 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12298 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12301 bfd_boolean record_fixup
)
12303 xtensa_isa isa
= xtensa_default_isa
;
12304 xtensa_format fmt
= vinsn
->format
;
12305 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12307 bfd_boolean has_fixup
= FALSE
;
12309 xtensa_format_encode (isa
, fmt
, insnbuf
);
12311 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12313 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12314 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12315 bfd_boolean tinsn_has_fixup
=
12316 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12317 vinsn
->slotbuf
[slot
]);
12319 xtensa_format_set_slot (isa
, fmt
, slot
,
12320 insnbuf
, vinsn
->slotbuf
[slot
]);
12321 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12323 if (vinsn
->num_slots
!= 1)
12324 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12325 else if (record_fixup
)
12326 /* Instructions that generate TLS relocations should always be
12327 relaxed in the front-end. If "record_fixup" is set, then this
12328 function is being called during back-end relaxation, so flag
12329 the unexpected behavior as an error. */
12330 as_bad (_("unexpected TLS relocation"));
12332 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12333 xtensa_format_length (isa
, fmt
),
12334 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12335 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12337 if (tinsn_has_fixup
)
12340 xtensa_opcode opcode
= tinsn
->opcode
;
12341 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12344 for (i
= 0; i
< noperands
; i
++)
12346 expressionS
* exp
= &tinsn
->tok
[i
];
12352 if (get_relaxable_immed (opcode
) == i
)
12354 /* Add a fix record for the instruction, except if this
12355 function is being called prior to relaxation, i.e.,
12356 if record_fixup is false, and the instruction might
12357 be relaxed later. */
12359 || tinsn
->is_specific_opcode
12360 || !xg_is_relaxable_insn (tinsn
, 0))
12362 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12363 frag_offset
- fragP
->fr_literal
);
12367 if (exp
->X_op
!= O_symbol
)
12368 as_bad (_("invalid operand"));
12369 tinsn
->symbol
= exp
->X_add_symbol
;
12370 tinsn
->offset
= exp
->X_add_number
;
12374 as_bad (_("symbolic operand not allowed"));
12382 as_bad (_("expression too complex"));
12394 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
12396 static xtensa_insnbuf insnbuf
= NULL
;
12397 static xtensa_insnbuf slotbuf
= NULL
;
12400 xtensa_isa isa
= xtensa_default_isa
;
12404 insnbuf
= xtensa_insnbuf_alloc (isa
);
12405 slotbuf
= xtensa_insnbuf_alloc (isa
);
12408 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
12409 fmt
= xtensa_format_decode (isa
, insnbuf
);
12410 if (fmt
== XTENSA_UNDEFINED
)
12411 as_fatal (_("cannot decode instruction format"));
12412 vinsn
->format
= fmt
;
12413 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
12415 for (i
= 0; i
< vinsn
->num_slots
; i
++)
12417 TInsn
*tinsn
= &vinsn
->slots
[i
];
12418 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
12419 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
12424 /* Expression utilities. */
12426 /* Return TRUE if the expression is an integer constant. */
12429 expr_is_const (const expressionS
*s
)
12431 return (s
->X_op
== O_constant
);
12435 /* Get the expression constant.
12436 Calling this is illegal if expr_is_const () returns TRUE. */
12439 get_expr_const (const expressionS
*s
)
12441 gas_assert (expr_is_const (s
));
12442 return s
->X_add_number
;
12446 /* Set the expression to a constant value. */
12449 set_expr_const (expressionS
*s
, offsetT val
)
12451 s
->X_op
= O_constant
;
12452 s
->X_add_number
= val
;
12453 s
->X_add_symbol
= NULL
;
12454 s
->X_op_symbol
= NULL
;
12459 expr_is_register (const expressionS
*s
)
12461 return (s
->X_op
== O_register
);
12465 /* Get the expression constant.
12466 Calling this is illegal if expr_is_const () returns TRUE. */
12469 get_expr_register (const expressionS
*s
)
12471 gas_assert (expr_is_register (s
));
12472 return s
->X_add_number
;
12476 /* Set the expression to a symbol + constant offset. */
12479 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
12481 s
->X_op
= O_symbol
;
12482 s
->X_add_symbol
= sym
;
12483 s
->X_op_symbol
= NULL
; /* unused */
12484 s
->X_add_number
= offset
;
12488 /* Return TRUE if the two expressions are equal. */
12491 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
12493 if (s1
->X_op
!= s2
->X_op
)
12495 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
12497 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
12499 if (s1
->X_add_number
!= s2
->X_add_number
)
12506 copy_expr (expressionS
*dst
, const expressionS
*src
)
12508 memcpy (dst
, src
, sizeof (expressionS
));
12512 /* Support for the "--rename-section" option. */
12514 struct rename_section_struct
12518 struct rename_section_struct
*next
;
12521 static struct rename_section_struct
*section_rename
;
12524 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
12525 entries to the section_rename list. Note: Specifying multiple
12526 renamings separated by colons is not documented and is retained only
12527 for backward compatibility. */
12530 build_section_rename (const char *arg
)
12532 struct rename_section_struct
*r
;
12533 char *this_arg
= NULL
;
12534 char *next_arg
= NULL
;
12536 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
12538 char *old_name
, *new_name
;
12542 next_arg
= strchr (this_arg
, ':');
12550 old_name
= this_arg
;
12551 new_name
= strchr (this_arg
, '=');
12553 if (*old_name
== '\0')
12555 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
12558 if (!new_name
|| new_name
[1] == '\0')
12560 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
12567 /* Check for invalid section renaming. */
12568 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12570 if (strcmp (r
->old_name
, old_name
) == 0)
12571 as_bad (_("section %s renamed multiple times"), old_name
);
12572 if (strcmp (r
->new_name
, new_name
) == 0)
12573 as_bad (_("multiple sections remapped to output section %s"),
12578 r
= (struct rename_section_struct
*)
12579 xmalloc (sizeof (struct rename_section_struct
));
12580 r
->old_name
= xstrdup (old_name
);
12581 r
->new_name
= xstrdup (new_name
);
12582 r
->next
= section_rename
;
12583 section_rename
= r
;
12589 xtensa_section_rename (char *name
)
12591 struct rename_section_struct
*r
= section_rename
;
12593 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
12595 if (strcmp (r
->old_name
, name
) == 0)
12596 return r
->new_name
;