1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "xtensa-istack.h"
29 #include "dwarf2dbg.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
84 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
86 /* Some functions are only valid in the front end. This variable
87 allows us to assert that we haven't crossed over into the
89 static bfd_boolean past_xtensa_end
= FALSE
;
91 /* Flags for properties of the last instruction in a segment. */
92 #define FLAG_IS_A0_WRITER 0x1
93 #define FLAG_IS_BAD_LOOPEND 0x2
96 /* We define a special segment names ".literal" to place literals
97 into. The .fini and .init sections are special because they
98 contain code that is moved together by the linker. We give them
99 their own special .fini.literal and .init.literal sections. */
101 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
102 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
103 #define INIT_SECTION_NAME xtensa_section_rename (".init")
104 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
107 /* This type is used for the directive_stack to keep track of the
108 state of the literal collection pools. If lit_prefix is set, it is
109 used to determine the literal section names; otherwise, the literal
110 sections are determined based on the current text section. The
111 lit_seg and lit4_seg fields cache these literal sections, with the
112 current_text_seg field used a tag to indicate whether the cached
115 typedef struct lit_state_struct
118 segT current_text_seg
;
123 static lit_state default_lit_sections
;
126 /* We keep a list of literal segments. The seg_list type is the node
127 for this list. The literal_head pointer is the head of the list,
128 with the literal_head_h dummy node at the start. */
130 typedef struct seg_list_struct
132 struct seg_list_struct
*next
;
136 static seg_list literal_head_h
;
137 static seg_list
*literal_head
= &literal_head_h
;
140 /* Lists of symbols. We keep a list of symbols that label the current
141 instruction, so that we can adjust the symbols when inserting alignment
142 for various instructions. We also keep a list of all the symbols on
143 literals, so that we can fix up those symbols when the literals are
144 later moved into the text sections. */
146 typedef struct sym_list_struct
148 struct sym_list_struct
*next
;
152 static sym_list
*insn_labels
= NULL
;
153 static sym_list
*free_insn_labels
= NULL
;
154 static sym_list
*saved_insn_labels
= NULL
;
156 static sym_list
*literal_syms
;
159 /* Flags to determine whether to prefer const16 or l32r
160 if both options are available. */
161 int prefer_const16
= 0;
164 /* Global flag to indicate when we are emitting literals. */
165 int generating_literals
= 0;
167 /* The following PROPERTY table definitions are copied from
168 <elf/xtensa.h> and must be kept in sync with the code there. */
170 /* Flags in the property tables to specify whether blocks of memory
171 are literals, instructions, data, or unreachable. For
172 instructions, blocks that begin loop targets and branch targets are
173 designated. Blocks that do not allow density, instruction
174 reordering or transformation are also specified. Finally, for
175 branch targets, branch target alignment priority is included.
176 Alignment of the next block is specified in the current block
177 and the size of the current block does not include any fill required
178 to align to the next block. */
180 #define XTENSA_PROP_LITERAL 0x00000001
181 #define XTENSA_PROP_INSN 0x00000002
182 #define XTENSA_PROP_DATA 0x00000004
183 #define XTENSA_PROP_UNREACHABLE 0x00000008
184 /* Instruction only properties at beginning of code. */
185 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
186 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
187 /* Instruction only properties about code. */
188 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
189 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
190 /* Historically, NO_TRANSFORM was a property of instructions,
191 but it should apply to literals under certain circumstances. */
192 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
268 /* is_specific_opcode implies no_transform. */
269 unsigned is_no_transform
: 1;
273 unsigned is_loop_target
: 1;
274 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
275 unsigned bt_align_priority
: 2;
277 unsigned is_no_density
: 1;
278 /* no_longcalls flag does not need to be placed in the object file. */
280 unsigned is_no_reorder
: 1;
282 /* Uses absolute literal addressing for l32r. */
283 unsigned is_abslit
: 1;
285 unsigned is_align
: 1;
286 unsigned alignment
: 5;
290 /* Structure for saving information about a block of property data
291 for frags that have the same flags. */
292 struct xtensa_block_info_struct
298 struct xtensa_block_info_struct
*next
;
302 /* Structure for saving the current state before emitting literals. */
303 typedef struct emit_state_struct
308 int generating_literals
;
312 /* Opcode placement information */
314 typedef unsigned long long bitfield
;
315 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
316 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
317 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
319 #define MAX_FORMATS 32
321 typedef struct op_placement_info_struct
324 /* A number describing how restrictive the issue is for this
325 opcode. For example, an opcode that fits lots of different
326 formats has a high freedom, as does an opcode that fits
327 only one format but many slots in that format. The most
328 restrictive is the opcode that fits only one slot in one
331 xtensa_format narrowest
;
335 /* formats is a bitfield with the Nth bit set
336 if the opcode fits in the Nth xtensa_format. */
339 /* slots[N]'s Mth bit is set if the op fits in the
340 Mth slot of the Nth xtensa_format. */
341 bitfield slots
[MAX_FORMATS
];
343 /* A count of the number of slots in a given format
344 an op can fit (i.e., the bitcount of the slot field above). */
345 char slots_in_format
[MAX_FORMATS
];
347 } op_placement_info
, *op_placement_info_table
;
349 op_placement_info_table op_placement_table
;
352 /* Extra expression types. */
354 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
355 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
356 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 struct suffix_reloc_map
362 bfd_reloc_code_real_type reloc
;
363 unsigned char operator;
366 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
368 static struct suffix_reloc_map suffix_relocs
[] =
370 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
371 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
372 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
373 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
387 directive_literal_prefix
,
389 directive_absolute_literals
,
390 directive_last_directive
396 bfd_boolean can_be_negated
;
399 const directive_infoS directive_info
[] =
402 { "literal", FALSE
},
404 { "transform", TRUE
},
405 { "freeregs", FALSE
},
406 { "longcalls", TRUE
},
407 { "literal_prefix", FALSE
},
408 { "schedule", TRUE
},
409 { "absolute-literals", TRUE
}
412 bfd_boolean directive_state
[] =
416 #if !XCHAL_HAVE_DENSITY
421 TRUE
, /* transform */
422 FALSE
, /* freeregs */
423 FALSE
, /* longcalls */
424 FALSE
, /* literal_prefix */
425 FALSE
, /* schedule */
426 #if XSHAL_USE_ABSOLUTE_LITERALS
427 TRUE
/* absolute_literals */
429 FALSE
/* absolute_literals */
434 /* Directive functions. */
436 static void xtensa_begin_directive (int);
437 static void xtensa_end_directive (int);
438 static void xtensa_literal_prefix (void);
439 static void xtensa_literal_position (int);
440 static void xtensa_literal_pseudo (int);
441 static void xtensa_frequency_pseudo (int);
442 static void xtensa_elf_cons (int);
444 /* Parsing and Idiom Translation. */
446 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
448 /* Various Other Internal Functions. */
450 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
451 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
452 static void xtensa_mark_literal_pool_location (void);
453 static addressT
get_expanded_loop_offset (xtensa_opcode
);
454 static fragS
*get_literal_pool_location (segT
);
455 static void set_literal_pool_location (segT
, fragS
*);
456 static void xtensa_set_frag_assembly_state (fragS
*);
457 static void finish_vinsn (vliw_insn
*);
458 static bfd_boolean
emit_single_op (TInsn
*);
459 static int total_frag_text_expansion (fragS
*);
461 /* Alignment Functions. */
463 static int get_text_align_power (unsigned);
464 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
465 static int branch_align_power (segT
);
467 /* Helpers for xtensa_relax_frag(). */
469 static long relax_frag_add_nop (fragS
*);
471 /* Accessors for additional per-subsegment information. */
473 static unsigned get_last_insn_flags (segT
, subsegT
);
474 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
475 static float get_subseg_total_freq (segT
, subsegT
);
476 static float get_subseg_target_freq (segT
, subsegT
);
477 static void set_subseg_freq (segT
, subsegT
, float, float);
479 /* Segment list functions. */
481 static void xtensa_move_literals (void);
482 static void xtensa_reorder_segments (void);
483 static void xtensa_switch_to_literal_fragment (emit_state
*);
484 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
485 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
486 static void xtensa_restore_emit_state (emit_state
*);
487 static segT
cache_literal_section (bfd_boolean
);
489 /* Import from elf32-xtensa.c in BFD library. */
491 extern asection
*xtensa_get_property_section (asection
*, const char *);
493 /* op_placement_info functions. */
495 static void init_op_placement_info_table (void);
496 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
497 static int xg_get_single_size (xtensa_opcode
);
498 static xtensa_format
xg_get_single_format (xtensa_opcode
);
499 static int xg_get_single_slot (xtensa_opcode
);
501 /* TInsn and IStack functions. */
503 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
504 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
505 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
506 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
507 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
508 static void tinsn_from_chars (TInsn
*, char *, int);
509 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
510 static int get_num_stack_text_bytes (IStack
*);
511 static int get_num_stack_literal_bytes (IStack
*);
513 /* vliw_insn functions. */
515 static void xg_init_vinsn (vliw_insn
*);
516 static void xg_clear_vinsn (vliw_insn
*);
517 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
518 static void xg_free_vinsn (vliw_insn
*);
519 static bfd_boolean vinsn_to_insnbuf
520 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
521 static void vinsn_from_chars (vliw_insn
*, char *);
523 /* Expression Utilities. */
525 bfd_boolean
expr_is_const (const expressionS
*);
526 offsetT
get_expr_const (const expressionS
*);
527 void set_expr_const (expressionS
*, offsetT
);
528 bfd_boolean
expr_is_register (const expressionS
*);
529 offsetT
get_expr_register (const expressionS
*);
530 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
531 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
532 static void copy_expr (expressionS
*, const expressionS
*);
534 /* Section renaming. */
536 static void build_section_rename (const char *);
539 /* ISA imported from bfd. */
540 extern xtensa_isa xtensa_default_isa
;
542 extern int target_big_endian
;
544 static xtensa_opcode xtensa_addi_opcode
;
545 static xtensa_opcode xtensa_addmi_opcode
;
546 static xtensa_opcode xtensa_call0_opcode
;
547 static xtensa_opcode xtensa_call4_opcode
;
548 static xtensa_opcode xtensa_call8_opcode
;
549 static xtensa_opcode xtensa_call12_opcode
;
550 static xtensa_opcode xtensa_callx0_opcode
;
551 static xtensa_opcode xtensa_callx4_opcode
;
552 static xtensa_opcode xtensa_callx8_opcode
;
553 static xtensa_opcode xtensa_callx12_opcode
;
554 static xtensa_opcode xtensa_const16_opcode
;
555 static xtensa_opcode xtensa_entry_opcode
;
556 static xtensa_opcode xtensa_movi_opcode
;
557 static xtensa_opcode xtensa_movi_n_opcode
;
558 static xtensa_opcode xtensa_isync_opcode
;
559 static xtensa_opcode xtensa_jx_opcode
;
560 static xtensa_opcode xtensa_l32r_opcode
;
561 static xtensa_opcode xtensa_loop_opcode
;
562 static xtensa_opcode xtensa_loopnez_opcode
;
563 static xtensa_opcode xtensa_loopgtz_opcode
;
564 static xtensa_opcode xtensa_nop_opcode
;
565 static xtensa_opcode xtensa_nop_n_opcode
;
566 static xtensa_opcode xtensa_or_opcode
;
567 static xtensa_opcode xtensa_ret_opcode
;
568 static xtensa_opcode xtensa_ret_n_opcode
;
569 static xtensa_opcode xtensa_retw_opcode
;
570 static xtensa_opcode xtensa_retw_n_opcode
;
571 static xtensa_opcode xtensa_rsr_lcount_opcode
;
572 static xtensa_opcode xtensa_waiti_opcode
;
575 /* Command-line Options. */
577 bfd_boolean use_literal_section
= TRUE
;
578 static bfd_boolean align_targets
= TRUE
;
579 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
580 static bfd_boolean has_a0_b_retw
= FALSE
;
581 static bfd_boolean workaround_a0_b_retw
= FALSE
;
582 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
583 static bfd_boolean workaround_short_loop
= FALSE
;
584 static bfd_boolean maybe_has_short_loop
= FALSE
;
585 static bfd_boolean workaround_close_loop_end
= FALSE
;
586 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
587 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
589 /* When workaround_short_loops is TRUE, all loops with early exits must
590 have at least 3 instructions. workaround_all_short_loops is a modifier
591 to the workaround_short_loop flag. In addition to the
592 workaround_short_loop actions, all straightline loopgtz and loopnez
593 must have at least 3 instructions. */
595 static bfd_boolean workaround_all_short_loops
= FALSE
;
599 xtensa_setup_hw_workarounds (int earliest
, int latest
)
601 if (earliest
> latest
)
602 as_fatal (_("illegal range of target hardware versions"));
604 /* Enable all workarounds for pre-T1050.0 hardware. */
605 if (earliest
< 105000 || latest
< 105000)
607 workaround_a0_b_retw
|= TRUE
;
608 workaround_b_j_loop_end
|= TRUE
;
609 workaround_short_loop
|= TRUE
;
610 workaround_close_loop_end
|= TRUE
;
611 workaround_all_short_loops
|= TRUE
;
612 enforce_three_byte_loop_align
= TRUE
;
619 option_density
= OPTION_MD_BASE
,
626 option_no_link_relax
,
634 option_text_section_literals
,
635 option_no_text_section_literals
,
637 option_absolute_literals
,
638 option_no_absolute_literals
,
640 option_align_targets
,
641 option_no_align_targets
,
643 option_warn_unaligned_targets
,
648 option_workaround_a0_b_retw
,
649 option_no_workaround_a0_b_retw
,
651 option_workaround_b_j_loop_end
,
652 option_no_workaround_b_j_loop_end
,
654 option_workaround_short_loop
,
655 option_no_workaround_short_loop
,
657 option_workaround_all_short_loops
,
658 option_no_workaround_all_short_loops
,
660 option_workaround_close_loop_end
,
661 option_no_workaround_close_loop_end
,
663 option_no_workarounds
,
665 option_rename_section_name
,
668 option_prefer_const16
,
670 option_target_hardware
673 const char *md_shortopts
= "";
675 struct option md_longopts
[] =
677 { "density", no_argument
, NULL
, option_density
},
678 { "no-density", no_argument
, NULL
, option_no_density
},
680 /* Both "relax" and "generics" are deprecated and treated as equivalent
681 to the "transform" option. */
682 { "relax", no_argument
, NULL
, option_relax
},
683 { "no-relax", no_argument
, NULL
, option_no_relax
},
684 { "generics", no_argument
, NULL
, option_generics
},
685 { "no-generics", no_argument
, NULL
, option_no_generics
},
687 { "transform", no_argument
, NULL
, option_transform
},
688 { "no-transform", no_argument
, NULL
, option_no_transform
},
689 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
690 { "no-text-section-literals", no_argument
, NULL
,
691 option_no_text_section_literals
},
692 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
693 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
694 /* This option was changed from -align-target to -target-align
695 because it conflicted with the "-al" option. */
696 { "target-align", no_argument
, NULL
, option_align_targets
},
697 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
698 { "warn-unaligned-targets", no_argument
, NULL
,
699 option_warn_unaligned_targets
},
700 { "longcalls", no_argument
, NULL
, option_longcalls
},
701 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
703 { "no-workaround-a0-b-retw", no_argument
, NULL
,
704 option_no_workaround_a0_b_retw
},
705 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
707 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
708 option_no_workaround_b_j_loop_end
},
709 { "workaround-b-j-loop-end", no_argument
, NULL
,
710 option_workaround_b_j_loop_end
},
712 { "no-workaround-short-loops", no_argument
, NULL
,
713 option_no_workaround_short_loop
},
714 { "workaround-short-loops", no_argument
, NULL
,
715 option_workaround_short_loop
},
717 { "no-workaround-all-short-loops", no_argument
, NULL
,
718 option_no_workaround_all_short_loops
},
719 { "workaround-all-short-loop", no_argument
, NULL
,
720 option_workaround_all_short_loops
},
722 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
723 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
725 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
727 { "no-workaround-close-loop-end", no_argument
, NULL
,
728 option_no_workaround_close_loop_end
},
729 { "workaround-close-loop-end", no_argument
, NULL
,
730 option_workaround_close_loop_end
},
732 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
734 { "link-relax", no_argument
, NULL
, option_link_relax
},
735 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
737 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
739 { NULL
, no_argument
, NULL
, 0 }
742 size_t md_longopts_size
= sizeof md_longopts
;
746 md_parse_option (int c
, char *arg
)
751 as_warn (_("--density option is ignored"));
753 case option_no_density
:
754 as_warn (_("--no-density option is ignored"));
756 case option_link_relax
:
759 case option_no_link_relax
:
762 case option_generics
:
763 as_warn (_("--generics is deprecated; use --transform instead"));
764 return md_parse_option (option_transform
, arg
);
765 case option_no_generics
:
766 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
767 return md_parse_option (option_no_transform
, arg
);
769 as_warn (_("--relax is deprecated; use --transform instead"));
770 return md_parse_option (option_transform
, arg
);
771 case option_no_relax
:
772 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
773 return md_parse_option (option_no_transform
, arg
);
774 case option_longcalls
:
775 directive_state
[directive_longcalls
] = TRUE
;
777 case option_no_longcalls
:
778 directive_state
[directive_longcalls
] = FALSE
;
780 case option_text_section_literals
:
781 use_literal_section
= FALSE
;
783 case option_no_text_section_literals
:
784 use_literal_section
= TRUE
;
786 case option_absolute_literals
:
787 if (!absolute_literals_supported
)
789 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
792 directive_state
[directive_absolute_literals
] = TRUE
;
794 case option_no_absolute_literals
:
795 directive_state
[directive_absolute_literals
] = FALSE
;
798 case option_workaround_a0_b_retw
:
799 workaround_a0_b_retw
= TRUE
;
801 case option_no_workaround_a0_b_retw
:
802 workaround_a0_b_retw
= FALSE
;
804 case option_workaround_b_j_loop_end
:
805 workaround_b_j_loop_end
= TRUE
;
807 case option_no_workaround_b_j_loop_end
:
808 workaround_b_j_loop_end
= FALSE
;
811 case option_workaround_short_loop
:
812 workaround_short_loop
= TRUE
;
814 case option_no_workaround_short_loop
:
815 workaround_short_loop
= FALSE
;
818 case option_workaround_all_short_loops
:
819 workaround_all_short_loops
= TRUE
;
821 case option_no_workaround_all_short_loops
:
822 workaround_all_short_loops
= FALSE
;
825 case option_workaround_close_loop_end
:
826 workaround_close_loop_end
= TRUE
;
828 case option_no_workaround_close_loop_end
:
829 workaround_close_loop_end
= FALSE
;
832 case option_no_workarounds
:
833 workaround_a0_b_retw
= FALSE
;
834 workaround_b_j_loop_end
= FALSE
;
835 workaround_short_loop
= FALSE
;
836 workaround_all_short_loops
= FALSE
;
837 workaround_close_loop_end
= FALSE
;
840 case option_align_targets
:
841 align_targets
= TRUE
;
843 case option_no_align_targets
:
844 align_targets
= FALSE
;
847 case option_warn_unaligned_targets
:
848 warn_unaligned_branch_targets
= TRUE
;
851 case option_rename_section_name
:
852 build_section_rename (arg
);
856 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
857 should be emitted or not. FIXME: Not implemented. */
860 case option_prefer_l32r
:
862 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
866 case option_prefer_const16
:
868 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
872 case option_target_hardware
:
874 int earliest
, latest
= 0;
875 if (*arg
== 0 || *arg
== '-')
876 as_fatal (_("invalid target hardware version"));
878 earliest
= strtol (arg
, &arg
, 0);
882 else if (*arg
== '-')
885 as_fatal (_("invalid target hardware version"));
886 latest
= strtol (arg
, &arg
, 0);
889 as_fatal (_("invalid target hardware version"));
891 xtensa_setup_hw_workarounds (earliest
, latest
);
895 case option_transform
:
896 /* This option has no affect other than to use the defaults,
897 which are already set. */
900 case option_no_transform
:
901 /* This option turns off all transformations of any kind.
902 However, because we want to preserve the state of other
903 directives, we only change its own field. Thus, before
904 you perform any transformation, always check if transform
905 is available. If you use the functions we provide for this
906 purpose, you will be ok. */
907 directive_state
[directive_transform
] = FALSE
;
917 md_show_usage (FILE *stream
)
921 --[no-]text-section-literals\n\
922 [Do not] put literals in the text section\n\
923 --[no-]absolute-literals\n\
924 [Do not] default to use non-PC-relative literals\n\
925 --[no-]target-align [Do not] try to align branch targets\n\
926 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
927 --[no-]transform [Do not] transform instructions\n\
928 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
932 /* Functions related to the list of current label symbols. */
935 xtensa_add_insn_label (symbolS
*sym
)
939 if (!free_insn_labels
)
940 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
943 l
= free_insn_labels
;
944 free_insn_labels
= l
->next
;
948 l
->next
= insn_labels
;
954 xtensa_clear_insn_labels (void)
958 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
966 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
970 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
972 symbolS
*lit_sym
= lit
->sym
;
973 S_SET_VALUE (lit_sym
, new_offset
);
974 symbol_set_frag (lit_sym
, new_frag
);
979 /* Directive data and functions. */
981 typedef struct state_stackS_struct
983 directiveE directive
;
985 bfd_boolean old_state
;
989 struct state_stackS_struct
*prev
;
992 state_stackS
*directive_state_stack
;
994 const pseudo_typeS md_pseudo_table
[] =
996 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
997 { "literal_position", xtensa_literal_position
, 0 },
998 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
999 { "long", xtensa_elf_cons
, 4 },
1000 { "word", xtensa_elf_cons
, 4 },
1001 { "short", xtensa_elf_cons
, 2 },
1002 { "begin", xtensa_begin_directive
, 0 },
1003 { "end", xtensa_end_directive
, 0 },
1004 { "literal", xtensa_literal_pseudo
, 0 },
1005 { "frequency", xtensa_frequency_pseudo
, 0 },
1011 use_transform (void)
1013 /* After md_end, you should be checking frag by frag, rather
1014 than state directives. */
1015 assert (!past_xtensa_end
);
1016 return directive_state
[directive_transform
];
1021 do_align_targets (void)
1023 /* Do not use this function after md_end; just look at align_targets
1024 instead. There is no target-align directive, so alignment is either
1025 enabled for all frags or not done at all. */
1026 assert (!past_xtensa_end
);
1027 return align_targets
&& use_transform ();
1032 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1036 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1038 as_where (&file
, &line
);
1040 stack
->directive
= directive
;
1041 stack
->negated
= negated
;
1042 stack
->old_state
= directive_state
[directive
];
1045 stack
->datum
= datum
;
1046 stack
->prev
= directive_state_stack
;
1047 directive_state_stack
= stack
;
1049 directive_state
[directive
] = !negated
;
1054 directive_pop (directiveE
*directive
,
1055 bfd_boolean
*negated
,
1060 state_stackS
*top
= directive_state_stack
;
1062 if (!directive_state_stack
)
1064 as_bad (_("unmatched end directive"));
1065 *directive
= directive_none
;
1069 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1070 *directive
= top
->directive
;
1071 *negated
= top
->negated
;
1074 *datum
= top
->datum
;
1075 directive_state_stack
= top
->prev
;
1081 directive_balance (void)
1083 while (directive_state_stack
)
1085 directiveE directive
;
1086 bfd_boolean negated
;
1091 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1092 as_warn_where ((char *) file
, line
,
1093 _(".begin directive with no matching .end directive"));
1099 inside_directive (directiveE dir
)
1101 state_stackS
*top
= directive_state_stack
;
1103 while (top
&& top
->directive
!= dir
)
1106 return (top
!= NULL
);
1111 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1115 char *directive_string
;
1117 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1122 input_line_pointer
+= 3;
1125 len
= strspn (input_line_pointer
,
1126 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1128 /* This code is a hack to make .begin [no-][generics|relax] exactly
1129 equivalent to .begin [no-]transform. We should remove it when
1130 we stop accepting those options. */
1132 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1134 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1135 directive_string
= "transform";
1137 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1139 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1140 directive_string
= "transform";
1143 directive_string
= input_line_pointer
;
1145 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1147 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1149 input_line_pointer
+= len
;
1150 *directive
= (directiveE
) i
;
1151 if (*negated
&& !directive_info
[i
].can_be_negated
)
1152 as_bad (_("directive %s cannot be negated"),
1153 directive_info
[i
].name
);
1158 as_bad (_("unknown directive"));
1159 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1164 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1166 directiveE directive
;
1167 bfd_boolean negated
;
1171 get_directive (&directive
, &negated
);
1172 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1174 discard_rest_of_line ();
1178 if (cur_vinsn
.inside_bundle
)
1179 as_bad (_("directives are not valid inside bundles"));
1183 case directive_literal
:
1184 if (!inside_directive (directive_literal
))
1186 /* Previous labels go with whatever follows this directive, not with
1187 the literal, so save them now. */
1188 saved_insn_labels
= insn_labels
;
1191 as_warn (_(".begin literal is deprecated; use .literal instead"));
1192 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1193 xtensa_switch_to_literal_fragment (state
);
1194 directive_push (directive_literal
, negated
, state
);
1197 case directive_literal_prefix
:
1198 /* Have to flush pending output because a movi relaxed to an l32r
1199 might produce a literal. */
1200 md_flush_pending_output ();
1201 /* Check to see if the current fragment is a literal
1202 fragment. If it is, then this operation is not allowed. */
1203 if (generating_literals
)
1205 as_bad (_("cannot set literal_prefix inside literal fragment"));
1209 /* Allocate the literal state for this section and push
1210 onto the directive stack. */
1211 ls
= xmalloc (sizeof (lit_state
));
1214 *ls
= default_lit_sections
;
1215 directive_push (directive_literal_prefix
, negated
, ls
);
1217 /* Process the new prefix. */
1218 xtensa_literal_prefix ();
1221 case directive_freeregs
:
1222 /* This information is currently unused, but we'll accept the statement
1223 and just discard the rest of the line. This won't check the syntax,
1224 but it will accept every correct freeregs directive. */
1225 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1226 directive_push (directive_freeregs
, negated
, 0);
1229 case directive_schedule
:
1230 md_flush_pending_output ();
1231 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1232 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1233 directive_push (directive_schedule
, negated
, 0);
1234 xtensa_set_frag_assembly_state (frag_now
);
1237 case directive_density
:
1238 as_warn (_(".begin [no-]density is ignored"));
1241 case directive_absolute_literals
:
1242 md_flush_pending_output ();
1243 if (!absolute_literals_supported
&& !negated
)
1245 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1248 xtensa_set_frag_assembly_state (frag_now
);
1249 directive_push (directive
, negated
, 0);
1253 md_flush_pending_output ();
1254 xtensa_set_frag_assembly_state (frag_now
);
1255 directive_push (directive
, negated
, 0);
1259 demand_empty_rest_of_line ();
1264 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1266 directiveE begin_directive
, end_directive
;
1267 bfd_boolean begin_negated
, end_negated
;
1271 emit_state
**state_ptr
;
1274 if (cur_vinsn
.inside_bundle
)
1275 as_bad (_("directives are not valid inside bundles"));
1277 get_directive (&end_directive
, &end_negated
);
1279 md_flush_pending_output ();
1281 switch (end_directive
)
1283 case (directiveE
) XTENSA_UNDEFINED
:
1284 discard_rest_of_line ();
1287 case directive_density
:
1288 as_warn (_(".end [no-]density is ignored"));
1289 demand_empty_rest_of_line ();
1292 case directive_absolute_literals
:
1293 if (!absolute_literals_supported
&& !end_negated
)
1295 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1296 demand_empty_rest_of_line ();
1305 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1306 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1307 (const void **) state_ptr
);
1309 if (begin_directive
!= directive_none
)
1311 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1313 as_bad (_("does not match begin %s%s at %s:%d"),
1314 begin_negated
? "no-" : "",
1315 directive_info
[begin_directive
].name
, file
, line
);
1319 switch (end_directive
)
1321 case directive_literal
:
1322 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1323 xtensa_restore_emit_state (state
);
1324 xtensa_set_frag_assembly_state (frag_now
);
1326 if (!inside_directive (directive_literal
))
1328 /* Restore the list of current labels. */
1329 xtensa_clear_insn_labels ();
1330 insn_labels
= saved_insn_labels
;
1334 case directive_literal_prefix
:
1335 /* Restore the default collection sections from saved state. */
1336 s
= (lit_state
*) state
;
1338 default_lit_sections
= *s
;
1340 /* Free the state storage. */
1341 free (s
->lit_prefix
);
1345 case directive_schedule
:
1346 case directive_freeregs
:
1350 xtensa_set_frag_assembly_state (frag_now
);
1356 demand_empty_rest_of_line ();
1360 /* Place an aligned literal fragment at the current location. */
1363 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1365 md_flush_pending_output ();
1367 if (inside_directive (directive_literal
))
1368 as_warn (_(".literal_position inside literal directive; ignoring"));
1369 xtensa_mark_literal_pool_location ();
1371 demand_empty_rest_of_line ();
1372 xtensa_clear_insn_labels ();
1376 /* Support .literal label, expr, ... */
1379 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1382 char *p
, *base_name
;
1386 if (inside_directive (directive_literal
))
1388 as_bad (_(".literal not allowed inside .begin literal region"));
1389 ignore_rest_of_line ();
1393 md_flush_pending_output ();
1395 /* Previous labels go with whatever follows this directive, not with
1396 the literal, so save them now. */
1397 saved_insn_labels
= insn_labels
;
1400 /* If we are using text-section literals, then this is the right value... */
1403 base_name
= input_line_pointer
;
1405 xtensa_switch_to_literal_fragment (&state
);
1407 /* ...but if we aren't using text-section-literals, then we
1408 need to put them in the section we just switched to. */
1409 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1412 /* All literals are aligned to four-byte boundaries. */
1413 frag_align (2, 0, 0);
1414 record_alignment (now_seg
, 2);
1416 c
= get_symbol_end ();
1417 /* Just after name is now '\0'. */
1418 p
= input_line_pointer
;
1422 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1424 as_bad (_("expected comma or colon after symbol name; "
1425 "rest of line ignored"));
1426 ignore_rest_of_line ();
1427 xtensa_restore_emit_state (&state
);
1435 input_line_pointer
++; /* skip ',' or ':' */
1437 xtensa_elf_cons (4);
1439 xtensa_restore_emit_state (&state
);
1441 /* Restore the list of current labels. */
1442 xtensa_clear_insn_labels ();
1443 insn_labels
= saved_insn_labels
;
1448 xtensa_literal_prefix (void)
1453 /* Parse the new prefix from the input_line_pointer. */
1455 len
= strspn (input_line_pointer
,
1456 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1457 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1459 /* Get a null-terminated copy of the name. */
1460 name
= xmalloc (len
+ 1);
1462 strncpy (name
, input_line_pointer
, len
);
1465 /* Skip the name in the input line. */
1466 input_line_pointer
+= len
;
1468 default_lit_sections
.lit_prefix
= name
;
1470 /* Clear cached literal sections, since the prefix has changed. */
1471 default_lit_sections
.lit_seg
= NULL
;
1472 default_lit_sections
.lit4_seg
= NULL
;
1476 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1479 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1481 float fall_through_f
, target_f
;
1483 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1484 if (fall_through_f
< 0)
1486 as_bad (_("fall through frequency must be greater than 0"));
1487 ignore_rest_of_line ();
1491 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1494 as_bad (_("branch target frequency must be greater than 0"));
1495 ignore_rest_of_line ();
1499 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1501 demand_empty_rest_of_line ();
1505 /* Like normal .long/.short/.word, except support @plt, etc.
1506 Clobbers input_line_pointer, checks end-of-line. */
1509 xtensa_elf_cons (int nbytes
)
1512 bfd_reloc_code_real_type reloc
;
1514 md_flush_pending_output ();
1516 if (cur_vinsn
.inside_bundle
)
1517 as_bad (_("directives are not valid inside bundles"));
1519 if (is_it_end_of_statement ())
1521 demand_empty_rest_of_line ();
1528 if (exp
.X_op
== O_symbol
1529 && *input_line_pointer
== '@'
1530 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1533 reloc_howto_type
*reloc_howto
=
1534 bfd_reloc_type_lookup (stdoutput
, reloc
);
1536 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1537 as_bad (_("unsupported relocation"));
1538 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1539 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1540 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1541 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1542 as_bad (_("opcode-specific %s relocation used outside "
1543 "an instruction"), reloc_howto
->name
);
1544 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1545 as_bad (_("%s relocations do not fit in %d bytes"),
1546 reloc_howto
->name
, nbytes
);
1549 char *p
= frag_more ((int) nbytes
);
1550 xtensa_set_frag_assembly_state (frag_now
);
1551 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1552 nbytes
, &exp
, 0, reloc
);
1556 emit_expr (&exp
, (unsigned int) nbytes
);
1558 while (*input_line_pointer
++ == ',');
1560 input_line_pointer
--; /* Put terminator back into stream. */
1561 demand_empty_rest_of_line ();
1565 /* Parsing and Idiom Translation. */
1567 /* Parse @plt, etc. and return the desired relocation. */
1568 static bfd_reloc_code_real_type
1569 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1576 struct suffix_reloc_map
*ptr
;
1579 return BFD_RELOC_NONE
;
1581 for (ch
= *str
, str2
= ident
;
1582 (str2
< ident
+ sizeof (ident
) - 1
1583 && (ISALNUM (ch
) || ch
== '@'));
1586 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1593 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1594 if (ch
== ptr
->suffix
[0]
1595 && len
== ptr
->length
1596 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1598 /* Now check for "identifier@suffix+constant". */
1599 if (*str
== '-' || *str
== '+')
1601 char *orig_line
= input_line_pointer
;
1602 expressionS new_exp
;
1604 input_line_pointer
= str
;
1605 expression (&new_exp
);
1606 if (new_exp
.X_op
== O_constant
)
1608 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1609 str
= input_line_pointer
;
1612 if (&input_line_pointer
!= str_p
)
1613 input_line_pointer
= orig_line
;
1620 return BFD_RELOC_UNUSED
;
1624 /* Find the matching operator type. */
1625 static unsigned char
1626 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1628 struct suffix_reloc_map
*sfx
;
1629 unsigned char operator = (unsigned char) -1;
1631 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1633 if (sfx
->reloc
== reloc
)
1635 operator = sfx
->operator;
1639 assert (operator != (unsigned char) -1);
1644 /* Find the matching reloc type. */
1645 static bfd_reloc_code_real_type
1646 map_operator_to_reloc (unsigned char operator)
1648 struct suffix_reloc_map
*sfx
;
1649 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1651 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1653 if (sfx
->operator == operator)
1660 if (reloc
== BFD_RELOC_UNUSED
)
1661 return BFD_RELOC_32
;
1668 expression_end (const char *name
)
1691 #define ERROR_REG_NUM ((unsigned) -1)
1694 tc_get_register (const char *prefix
)
1697 const char *next_expr
;
1698 const char *old_line_pointer
;
1701 old_line_pointer
= input_line_pointer
;
1703 if (*input_line_pointer
== '$')
1704 ++input_line_pointer
;
1706 /* Accept "sp" as a synonym for "a1". */
1707 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1708 && expression_end (input_line_pointer
+ 2))
1710 input_line_pointer
+= 2;
1711 return 1; /* AR[1] */
1714 while (*input_line_pointer
++ == *prefix
++)
1716 --input_line_pointer
;
1721 as_bad (_("bad register name: %s"), old_line_pointer
);
1722 return ERROR_REG_NUM
;
1725 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1727 as_bad (_("bad register number: %s"), input_line_pointer
);
1728 return ERROR_REG_NUM
;
1733 while (ISDIGIT ((int) *input_line_pointer
))
1734 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1736 if (!(next_expr
= expression_end (input_line_pointer
)))
1738 as_bad (_("bad register name: %s"), old_line_pointer
);
1739 return ERROR_REG_NUM
;
1742 input_line_pointer
= (char *) next_expr
;
1749 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1751 xtensa_isa isa
= xtensa_default_isa
;
1753 /* Check if this is an immediate operand. */
1754 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1756 bfd_reloc_code_real_type reloc
;
1757 segT t
= expression (tok
);
1758 if (t
== absolute_section
1759 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1761 assert (tok
->X_op
== O_constant
);
1762 tok
->X_op
= O_symbol
;
1763 tok
->X_add_symbol
= &abs_symbol
;
1766 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1767 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1770 if (reloc
== BFD_RELOC_UNUSED
)
1772 as_bad (_("unsupported relocation"));
1776 if (tok
->X_op
== O_constant
)
1780 case BFD_RELOC_LO16
:
1781 tok
->X_add_number
&= 0xffff;
1784 case BFD_RELOC_HI16
:
1785 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1792 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1797 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1798 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1800 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1803 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1804 as_bad (_("register number out of range"));
1807 tok
->X_op
= O_register
;
1808 tok
->X_add_symbol
= 0;
1809 tok
->X_add_number
= reg
;
1814 /* Split up the arguments for an opcode or pseudo-op. */
1817 tokenize_arguments (char **args
, char *str
)
1819 char *old_input_line_pointer
;
1820 bfd_boolean saw_comma
= FALSE
;
1821 bfd_boolean saw_arg
= FALSE
;
1822 bfd_boolean saw_colon
= FALSE
;
1824 char *arg_end
, *arg
;
1827 /* Save and restore input_line_pointer around this function. */
1828 old_input_line_pointer
= input_line_pointer
;
1829 input_line_pointer
= str
;
1831 while (*input_line_pointer
)
1834 switch (*input_line_pointer
)
1841 input_line_pointer
++;
1842 if (saw_comma
|| saw_colon
|| !saw_arg
)
1848 input_line_pointer
++;
1849 if (saw_comma
|| saw_colon
|| !saw_arg
)
1855 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1858 arg_end
= input_line_pointer
+ 1;
1859 while (!expression_end (arg_end
))
1862 arg_len
= arg_end
- input_line_pointer
;
1863 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1864 args
[num_args
] = arg
;
1868 strncpy (arg
, input_line_pointer
, arg_len
);
1869 arg
[arg_len
] = '\0';
1871 input_line_pointer
= arg_end
;
1881 if (saw_comma
|| saw_colon
)
1883 input_line_pointer
= old_input_line_pointer
;
1888 as_bad (_("extra comma"));
1890 as_bad (_("extra colon"));
1892 as_bad (_("missing argument"));
1894 as_bad (_("missing comma or colon"));
1895 input_line_pointer
= old_input_line_pointer
;
1900 /* Parse the arguments to an opcode. Return TRUE on error. */
1903 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1905 expressionS
*tok
, *last_tok
;
1906 xtensa_opcode opcode
= insn
->opcode
;
1907 bfd_boolean had_error
= TRUE
;
1908 xtensa_isa isa
= xtensa_default_isa
;
1909 int n
, num_regs
= 0;
1910 int opcode_operand_count
;
1911 int opnd_cnt
, last_opnd_cnt
;
1912 unsigned int next_reg
= 0;
1913 char *old_input_line_pointer
;
1915 if (insn
->insn_type
== ITYPE_LITERAL
)
1916 opcode_operand_count
= 1;
1918 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1921 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1923 /* Save and restore input_line_pointer around this function. */
1924 old_input_line_pointer
= input_line_pointer
;
1930 /* Skip invisible operands. */
1931 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1937 for (n
= 0; n
< num_args
; n
++)
1939 input_line_pointer
= arg_strings
[n
];
1940 if (*input_line_pointer
== ':')
1942 xtensa_regfile opnd_rf
;
1943 input_line_pointer
++;
1946 assert (opnd_cnt
> 0);
1948 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1950 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1951 as_warn (_("incorrect register number, ignoring"));
1956 if (opnd_cnt
>= opcode_operand_count
)
1958 as_warn (_("too many arguments"));
1961 assert (opnd_cnt
< MAX_INSN_ARGS
);
1963 expression_maybe_register (opcode
, opnd_cnt
, tok
);
1964 next_reg
= tok
->X_add_number
+ 1;
1966 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
1968 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
1970 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
1971 /* minus 1 because we are seeing one right now */
1977 last_opnd_cnt
= opnd_cnt
;
1984 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
1988 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
1991 insn
->ntok
= tok
- insn
->tok
;
1995 input_line_pointer
= old_input_line_pointer
;
2001 get_invisible_operands (TInsn
*insn
)
2003 xtensa_isa isa
= xtensa_default_isa
;
2004 static xtensa_insnbuf slotbuf
= NULL
;
2006 xtensa_opcode opc
= insn
->opcode
;
2007 int slot
, opnd
, fmt_found
;
2011 slotbuf
= xtensa_insnbuf_alloc (isa
);
2013 /* Find format/slot where this can be encoded. */
2016 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2018 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2020 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2026 if (fmt_found
) break;
2031 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2035 /* First encode all the visible operands
2036 (to deal with shared field operands). */
2037 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2039 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2040 && (insn
->tok
[opnd
].X_op
== O_register
2041 || insn
->tok
[opnd
].X_op
== O_constant
))
2043 val
= insn
->tok
[opnd
].X_add_number
;
2044 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2045 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2049 /* Then pull out the values for the invisible ones. */
2050 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2052 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2054 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2055 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2056 insn
->tok
[opnd
].X_add_number
= val
;
2057 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2058 insn
->tok
[opnd
].X_op
= O_register
;
2060 insn
->tok
[opnd
].X_op
= O_constant
;
2069 xg_reverse_shift_count (char **cnt_argp
)
2071 char *cnt_arg
, *new_arg
;
2072 cnt_arg
= *cnt_argp
;
2074 /* replace the argument with "31-(argument)" */
2075 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2076 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2079 *cnt_argp
= new_arg
;
2083 /* If "arg" is a constant expression, return non-zero with the value
2087 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2090 char *save_ptr
= input_line_pointer
;
2092 input_line_pointer
= arg
;
2094 input_line_pointer
= save_ptr
;
2096 if (exp
.X_op
== O_constant
)
2098 *valp
= exp
.X_add_number
;
2107 xg_replace_opname (char **popname
, char *newop
)
2110 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2111 strcpy (*popname
, newop
);
2116 xg_check_num_args (int *pnum_args
,
2121 int num_args
= *pnum_args
;
2123 if (num_args
< expected_num
)
2125 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2126 num_args
, opname
, expected_num
);
2130 if (num_args
> expected_num
)
2132 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2133 num_args
, opname
, expected_num
);
2134 while (num_args
-- > expected_num
)
2136 free (arg_strings
[num_args
]);
2137 arg_strings
[num_args
] = 0;
2139 *pnum_args
= expected_num
;
2147 /* If the register is not specified as part of the opcode,
2148 then get it from the operand and move it to the opcode. */
2151 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2153 xtensa_isa isa
= xtensa_default_isa
;
2155 char *opname
, *new_opname
;
2156 const char *sr_name
;
2157 int is_user
, is_write
;
2162 is_user
= (opname
[1] == 'u');
2163 is_write
= (opname
[0] == 'w');
2165 /* Opname == [rw]ur or [rwx]sr... */
2167 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2170 /* Check if the argument is a symbolic register name. */
2171 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2172 /* Handle WSR to "INTSET" as a special case. */
2173 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2174 && !strcasecmp (arg_strings
[1], "intset"))
2175 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2176 if (sr
== XTENSA_UNDEFINED
2177 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2179 /* Maybe it's a register number.... */
2181 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2183 as_bad (_("invalid register '%s' for '%s' instruction"),
2184 arg_strings
[1], opname
);
2187 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2188 if (sr
== XTENSA_UNDEFINED
)
2190 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2191 (long) val
, opname
);
2196 /* Remove the last argument, which is now part of the opcode. */
2197 free (arg_strings
[1]);
2201 /* Translate the opcode. */
2202 sr_name
= xtensa_sysreg_name (isa
, sr
);
2203 /* Another special case for "WSR.INTSET".... */
2204 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2206 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2207 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2209 *popname
= new_opname
;
2216 xtensa_translate_old_userreg_ops (char **popname
)
2218 xtensa_isa isa
= xtensa_default_isa
;
2220 char *opname
, *new_opname
;
2221 const char *sr_name
;
2222 bfd_boolean has_underbar
= FALSE
;
2225 if (opname
[0] == '_')
2227 has_underbar
= TRUE
;
2231 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2232 if (sr
!= XTENSA_UNDEFINED
)
2234 /* The new default name ("nnn") is different from the old default
2235 name ("URnnn"). The old default is handled below, and we don't
2236 want to recognize [RW]nnn, so do nothing if the name is the (new)
2238 static char namebuf
[10];
2239 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2240 if (strcmp (namebuf
, opname
+ 1) == 0)
2248 /* Only continue if the reg name is "URnnn". */
2249 if (opname
[1] != 'u' || opname
[2] != 'r')
2251 val
= strtoul (opname
+ 3, &end
, 10);
2255 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2256 if (sr
== XTENSA_UNDEFINED
)
2258 as_bad (_("invalid register number (%ld) for '%s'"),
2259 (long) val
, opname
);
2264 /* Translate the opcode. */
2265 sr_name
= xtensa_sysreg_name (isa
, sr
);
2266 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2267 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2268 opname
[0], sr_name
);
2270 *popname
= new_opname
;
2277 xtensa_translate_zero_immed (char *old_op
,
2287 assert (opname
[0] != '_');
2289 if (strcmp (opname
, old_op
) != 0)
2292 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2294 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2296 xg_replace_opname (popname
, new_op
);
2297 free (arg_strings
[1]);
2298 arg_strings
[1] = arg_strings
[2];
2307 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2308 Returns non-zero if an error was found. */
2311 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2313 char *opname
= *popname
;
2314 bfd_boolean has_underbar
= FALSE
;
2318 has_underbar
= TRUE
;
2322 if (strcmp (opname
, "mov") == 0)
2324 if (use_transform () && !has_underbar
&& density_supported
)
2325 xg_replace_opname (popname
, "mov.n");
2328 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2330 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2331 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2332 strcpy (arg_strings
[2], arg_strings
[1]);
2338 if (strcmp (opname
, "bbsi.l") == 0)
2340 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2342 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2343 if (target_big_endian
)
2344 xg_reverse_shift_count (&arg_strings
[1]);
2348 if (strcmp (opname
, "bbci.l") == 0)
2350 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2352 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2353 if (target_big_endian
)
2354 xg_reverse_shift_count (&arg_strings
[1]);
2358 /* Don't do anything special with NOPs inside FLIX instructions. They
2359 are handled elsewhere. Real NOP instructions are always available
2360 in configurations with FLIX, so this should never be an issue but
2361 check for it anyway. */
2362 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2363 && strcmp (opname
, "nop") == 0)
2365 if (use_transform () && !has_underbar
&& density_supported
)
2366 xg_replace_opname (popname
, "nop.n");
2369 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2371 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2372 arg_strings
[0] = (char *) xmalloc (3);
2373 arg_strings
[1] = (char *) xmalloc (3);
2374 arg_strings
[2] = (char *) xmalloc (3);
2375 strcpy (arg_strings
[0], "a1");
2376 strcpy (arg_strings
[1], "a1");
2377 strcpy (arg_strings
[2], "a1");
2383 /* Recognize [RW]UR and [RWX]SR. */
2384 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2385 && (opname
[1] == 'u' || opname
[1] == 's'))
2386 || (opname
[0] == 'x' && opname
[1] == 's'))
2388 && opname
[3] == '\0')
2389 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2391 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2392 [RW]<name> if <name> is the non-default name of a user register. */
2393 if ((opname
[0] == 'r' || opname
[0] == 'w')
2394 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2395 return xtensa_translate_old_userreg_ops (popname
);
2397 /* Relax branches that don't allow comparisons against an immediate value
2398 of zero to the corresponding branches with implicit zero immediates. */
2399 if (!has_underbar
&& use_transform ())
2401 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2402 pnum_args
, arg_strings
))
2405 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2406 pnum_args
, arg_strings
))
2409 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2410 pnum_args
, arg_strings
))
2413 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2414 pnum_args
, arg_strings
))
2422 /* Functions for dealing with the Xtensa ISA. */
2424 /* Currently the assembler only allows us to use a single target per
2425 fragment. Because of this, only one operand for a given
2426 instruction may be symbolic. If there is a PC-relative operand,
2427 the last one is chosen. Otherwise, the result is the number of the
2428 last immediate operand, and if there are none of those, we fail and
2432 get_relaxable_immed (xtensa_opcode opcode
)
2434 int last_immed
= -1;
2437 if (opcode
== XTENSA_UNDEFINED
)
2440 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2441 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2443 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2445 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2447 if (last_immed
== -1
2448 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2455 static xtensa_opcode
2456 get_opcode_from_buf (const char *buf
, int slot
)
2458 static xtensa_insnbuf insnbuf
= NULL
;
2459 static xtensa_insnbuf slotbuf
= NULL
;
2460 xtensa_isa isa
= xtensa_default_isa
;
2465 insnbuf
= xtensa_insnbuf_alloc (isa
);
2466 slotbuf
= xtensa_insnbuf_alloc (isa
);
2469 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2470 fmt
= xtensa_format_decode (isa
, insnbuf
);
2471 if (fmt
== XTENSA_UNDEFINED
)
2472 return XTENSA_UNDEFINED
;
2474 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2475 return XTENSA_UNDEFINED
;
2477 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2478 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2482 #ifdef TENSILICA_DEBUG
2484 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2487 xtensa_print_insn_table (void)
2489 int num_opcodes
, num_operands
;
2490 xtensa_opcode opcode
;
2491 xtensa_isa isa
= xtensa_default_isa
;
2493 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2494 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2497 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2498 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2499 for (opn
= 0; opn
< num_operands
; opn
++)
2501 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2503 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2505 xtensa_regfile opnd_rf
=
2506 xtensa_operand_regfile (isa
, opcode
, opn
);
2507 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2509 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2510 fputs ("[lLr] ", stderr
);
2512 fputs ("i ", stderr
);
2514 fprintf (stderr
, "\n");
2520 print_vliw_insn (xtensa_insnbuf vbuf
)
2522 xtensa_isa isa
= xtensa_default_isa
;
2523 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2524 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2527 fprintf (stderr
, "format = %d\n", f
);
2529 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2531 xtensa_opcode opcode
;
2535 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2536 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2537 opname
= xtensa_opcode_name (isa
, opcode
);
2539 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2540 fprintf (stderr
, " operands = ");
2542 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2546 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2548 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2549 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2550 fprintf (stderr
, "%d ", val
);
2552 fprintf (stderr
, "\n");
2554 xtensa_insnbuf_free (isa
, sbuf
);
2557 #endif /* TENSILICA_DEBUG */
2561 is_direct_call_opcode (xtensa_opcode opcode
)
2563 xtensa_isa isa
= xtensa_default_isa
;
2564 int n
, num_operands
;
2566 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2569 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2570 for (n
= 0; n
< num_operands
; n
++)
2572 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2573 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2580 /* Convert from BFD relocation type code to slot and operand number.
2581 Returns non-zero on failure. */
2584 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2586 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2587 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2589 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2592 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2593 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2595 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2605 /* Convert from slot number to BFD relocation type code for the
2606 standard PC-relative relocations. Return BFD_RELOC_NONE on
2609 static bfd_reloc_code_real_type
2610 encode_reloc (int slot
)
2612 if (slot
< 0 || slot
> 14)
2613 return BFD_RELOC_NONE
;
2615 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2619 /* Convert from slot numbers to BFD relocation type code for the
2620 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2622 static bfd_reloc_code_real_type
2623 encode_alt_reloc (int slot
)
2625 if (slot
< 0 || slot
> 14)
2626 return BFD_RELOC_NONE
;
2628 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2633 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2636 xtensa_opcode opcode
,
2642 uint32 valbuf
= value
;
2644 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2646 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2648 as_bad_where ((char *) file
, line
,
2649 _("operand %d of '%s' has out of range value '%u'"),
2651 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2654 as_bad_where ((char *) file
, line
,
2655 _("operand %d of '%s' has invalid value '%u'"),
2657 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2662 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2668 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2671 xtensa_opcode opcode
,
2675 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2676 fmt
, slot
, slotbuf
, &val
);
2677 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2682 /* Checks for rules from xtensa-relax tables. */
2684 /* The routine xg_instruction_matches_option_term must return TRUE
2685 when a given option term is true. The meaning of all of the option
2686 terms is given interpretation by this function. This is needed when
2687 an option depends on the state of a directive, but there are no such
2688 options in use right now. */
2691 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2692 const ReqOrOption
*option
)
2694 if (strcmp (option
->option_name
, "realnop") == 0
2695 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2697 /* These conditions were evaluated statically when building the
2698 relaxation table. There's no need to reevaluate them now. */
2703 as_fatal (_("internal error: unknown option name '%s'"),
2704 option
->option_name
);
2710 xg_instruction_matches_or_options (TInsn
*insn
,
2711 const ReqOrOptionList
*or_option
)
2713 const ReqOrOption
*option
;
2714 /* Must match each of the AND terms. */
2715 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2717 if (xg_instruction_matches_option_term (insn
, option
))
2725 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2727 const ReqOption
*req_options
;
2728 /* Must match each of the AND terms. */
2729 for (req_options
= options
;
2730 req_options
!= NULL
;
2731 req_options
= req_options
->next
)
2733 /* Must match one of the OR clauses. */
2734 if (!xg_instruction_matches_or_options (insn
,
2735 req_options
->or_option_terms
))
2742 /* Return the transition rule that matches or NULL if none matches. */
2745 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2747 PreconditionList
*condition_l
;
2749 if (rule
->opcode
!= insn
->opcode
)
2752 for (condition_l
= rule
->conditions
;
2753 condition_l
!= NULL
;
2754 condition_l
= condition_l
->next
)
2758 Precondition
*cond
= condition_l
->precond
;
2763 /* The expression must be the constant. */
2764 assert (cond
->op_num
< insn
->ntok
);
2765 exp1
= &insn
->tok
[cond
->op_num
];
2766 if (expr_is_const (exp1
))
2771 if (get_expr_const (exp1
) != cond
->op_data
)
2775 if (get_expr_const (exp1
) == cond
->op_data
)
2782 else if (expr_is_register (exp1
))
2787 if (get_expr_register (exp1
) != cond
->op_data
)
2791 if (get_expr_register (exp1
) == cond
->op_data
)
2803 assert (cond
->op_num
< insn
->ntok
);
2804 assert (cond
->op_data
< insn
->ntok
);
2805 exp1
= &insn
->tok
[cond
->op_num
];
2806 exp2
= &insn
->tok
[cond
->op_data
];
2811 if (!expr_is_equal (exp1
, exp2
))
2815 if (expr_is_equal (exp1
, exp2
))
2827 if (!xg_instruction_matches_options (insn
, rule
->options
))
2835 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2837 bfd_boolean a_greater
= FALSE
;
2838 bfd_boolean b_greater
= FALSE
;
2840 ReqOptionList
*l_a
= a
->options
;
2841 ReqOptionList
*l_b
= b
->options
;
2843 /* We only care if they both are the same except for
2844 a const16 vs. an l32r. */
2846 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2848 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2849 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2850 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2852 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2854 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2856 /* This is the case we care about. */
2857 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2858 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2865 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2866 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2876 l_or_a
= l_or_a
->next
;
2877 l_or_b
= l_or_b
->next
;
2879 if (l_or_a
|| l_or_b
)
2888 /* Incomparable if the substitution was used differently in two cases. */
2889 if (a_greater
&& b_greater
)
2901 static TransitionRule
*
2902 xg_instruction_match (TInsn
*insn
)
2904 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2906 assert (insn
->opcode
< table
->num_opcodes
);
2908 /* Walk through all of the possible transitions. */
2909 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2911 TransitionRule
*rule
= l
->rule
;
2912 if (xg_instruction_matches_rule (insn
, rule
))
2919 /* Various Other Internal Functions. */
2922 is_unique_insn_expansion (TransitionRule
*r
)
2924 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2926 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2932 /* Check if there is exactly one relaxation for INSN that converts it to
2933 another instruction of equal or larger size. If so, and if TARG is
2934 non-null, go ahead and generate the relaxed instruction into TARG. If
2935 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2936 instruction, i.e., ignore relaxations that convert to an instruction of
2937 equal size. In some contexts where this function is used, only
2938 a single widening is allowed and the NARROW_ONLY argument is used to
2939 exclude cases like ADDI being "widened" to an ADDMI, which may
2940 later be relaxed to an ADDMI/ADDI pair. */
2943 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2945 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2947 TransitionRule
*match
= 0;
2949 assert (insn
->insn_type
== ITYPE_INSN
);
2950 assert (insn
->opcode
< table
->num_opcodes
);
2952 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2954 TransitionRule
*rule
= l
->rule
;
2956 if (xg_instruction_matches_rule (insn
, rule
)
2957 && is_unique_insn_expansion (rule
)
2958 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
2959 <= xg_get_single_size (rule
->to_instr
->opcode
)))
2970 xg_build_to_insn (targ
, insn
, match
->to_instr
);
2975 /* Return the maximum number of bytes this opcode can expand to. */
2978 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
2980 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2982 int max_size
= xg_get_single_size (opcode
);
2984 assert (opcode
< table
->num_opcodes
);
2986 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
2988 TransitionRule
*rule
= l
->rule
;
2989 BuildInstr
*build_list
;
2994 build_list
= rule
->to_instr
;
2995 if (is_unique_insn_expansion (rule
))
2997 assert (build_list
->typ
== INSTR_INSTR
);
2998 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3001 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3003 switch (build_list
->typ
)
3006 this_size
+= xg_get_single_size (build_list
->opcode
);
3008 case INSTR_LITERAL_DEF
:
3009 case INSTR_LABEL_DEF
:
3014 if (this_size
> max_size
)
3015 max_size
= this_size
;
3021 /* Return the maximum number of literal bytes this opcode can generate. */
3024 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3026 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3030 assert (opcode
< table
->num_opcodes
);
3032 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3034 TransitionRule
*rule
= l
->rule
;
3035 BuildInstr
*build_list
;
3040 build_list
= rule
->to_instr
;
3041 if (is_unique_insn_expansion (rule
))
3043 assert (build_list
->typ
== INSTR_INSTR
);
3044 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3047 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3049 switch (build_list
->typ
)
3051 case INSTR_LITERAL_DEF
:
3052 /* Hard-coded 4-byte literal. */
3056 case INSTR_LABEL_DEF
:
3061 if (this_size
> max_size
)
3062 max_size
= this_size
;
3069 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3071 int steps_taken
= 0;
3072 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3075 assert (insn
->insn_type
== ITYPE_INSN
);
3076 assert (insn
->opcode
< table
->num_opcodes
);
3078 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3080 TransitionRule
*rule
= l
->rule
;
3082 if (xg_instruction_matches_rule (insn
, rule
))
3084 if (steps_taken
== lateral_steps
)
3094 get_special_literal_symbol (void)
3096 static symbolS
*sym
= NULL
;
3099 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3105 get_special_label_symbol (void)
3107 static symbolS
*sym
= NULL
;
3110 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3116 xg_valid_literal_expression (const expressionS
*exp
)
3133 /* This will check to see if the value can be converted into the
3134 operand type. It will return TRUE if it does not fit. */
3137 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3139 uint32 valbuf
= value
;
3140 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3146 /* Assumes: All immeds are constants. Check that all constants fit
3147 into their immeds; return FALSE if not. */
3150 xg_immeds_fit (const TInsn
*insn
)
3152 xtensa_isa isa
= xtensa_default_isa
;
3156 assert (insn
->insn_type
== ITYPE_INSN
);
3157 for (i
= 0; i
< n
; ++i
)
3159 const expressionS
*expr
= &insn
->tok
[i
];
3160 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3167 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3172 /* The symbol should have a fixup associated with it. */
3181 /* This should only be called after we have an initial
3182 estimate of the addresses. */
3185 xg_symbolic_immeds_fit (const TInsn
*insn
,
3191 xtensa_isa isa
= xtensa_default_isa
;
3199 assert (insn
->insn_type
== ITYPE_INSN
);
3201 for (i
= 0; i
< n
; ++i
)
3203 const expressionS
*expr
= &insn
->tok
[i
];
3204 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3211 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3217 /* Check for the worst case. */
3218 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3223 /* We only allow symbols for PC-relative references.
3224 If pc_frag == 0, then we don't have frag locations yet. */
3226 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3229 /* If it is a weak symbol, then assume it won't reach. */
3230 if (S_IS_WEAK (expr
->X_add_symbol
))
3233 if (is_direct_call_opcode (insn
->opcode
)
3234 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3236 /* If callee is undefined or in a different segment, be
3237 optimistic and assume it will be in range. */
3238 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3242 /* Only references within a segment can be known to fit in the
3243 operands at assembly time. */
3244 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3247 symbolP
= expr
->X_add_symbol
;
3248 sym_frag
= symbol_get_frag (symbolP
);
3249 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3250 pc
= pc_frag
->fr_address
+ pc_offset
;
3252 /* If frag has yet to be reached on this pass, assume it
3253 will move by STRETCH just as we did. If this is not so,
3254 it will be because some frag between grows, and that will
3255 force another pass. Beware zero-length frags. There
3256 should be a faster way to do this. */
3259 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3260 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3265 new_offset
= target
;
3266 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3267 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3272 /* The symbol should have a fixup associated with it. */
3281 /* Return TRUE on success. */
3284 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3290 targ
->linenum
= insn
->linenum
;
3295 targ
->opcode
= bi
->opcode
;
3296 targ
->insn_type
= ITYPE_INSN
;
3297 targ
->is_specific_opcode
= FALSE
;
3299 for (; op
!= NULL
; op
= op
->next
)
3301 int op_num
= op
->op_num
;
3302 int op_data
= op
->op_data
;
3304 assert (op
->op_num
< MAX_INSN_ARGS
);
3306 if (targ
->ntok
<= op_num
)
3307 targ
->ntok
= op_num
+ 1;
3312 set_expr_const (&targ
->tok
[op_num
], op_data
);
3315 assert (op_data
< insn
->ntok
);
3316 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3319 sym
= get_special_literal_symbol ();
3320 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3323 sym
= get_special_label_symbol ();
3324 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3326 case OP_OPERAND_HI16U
:
3327 case OP_OPERAND_LOW16U
:
3328 assert (op_data
< insn
->ntok
);
3329 if (expr_is_const (&insn
->tok
[op_data
]))
3332 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3333 val
= xg_apply_userdef_op_fn (op
->typ
,
3336 targ
->tok
[op_num
].X_add_number
= val
;
3340 /* For const16 we can create relocations for these. */
3341 if (targ
->opcode
== XTENSA_UNDEFINED
3342 || (targ
->opcode
!= xtensa_const16_opcode
))
3344 assert (op_data
< insn
->ntok
);
3345 /* Need to build a O_lo16 or O_hi16. */
3346 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3347 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3349 if (op
->typ
== OP_OPERAND_HI16U
)
3350 targ
->tok
[op_num
].X_op
= O_hi16
;
3351 else if (op
->typ
== OP_OPERAND_LOW16U
)
3352 targ
->tok
[op_num
].X_op
= O_lo16
;
3359 /* currently handles:
3362 OP_OPERAND_F32MINUS */
3363 if (xg_has_userdef_op_fn (op
->typ
))
3365 assert (op_data
< insn
->ntok
);
3366 if (expr_is_const (&insn
->tok
[op_data
]))
3369 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3370 val
= xg_apply_userdef_op_fn (op
->typ
,
3373 targ
->tok
[op_num
].X_add_number
= val
;
3376 return FALSE
; /* We cannot use a relocation for this. */
3385 case INSTR_LITERAL_DEF
:
3387 targ
->opcode
= XTENSA_UNDEFINED
;
3388 targ
->insn_type
= ITYPE_LITERAL
;
3389 targ
->is_specific_opcode
= FALSE
;
3390 for (; op
!= NULL
; op
= op
->next
)
3392 int op_num
= op
->op_num
;
3393 int op_data
= op
->op_data
;
3394 assert (op
->op_num
< MAX_INSN_ARGS
);
3396 if (targ
->ntok
<= op_num
)
3397 targ
->ntok
= op_num
+ 1;
3402 assert (op_data
< insn
->ntok
);
3403 /* We can only pass resolvable literals through. */
3404 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3406 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3418 case INSTR_LABEL_DEF
:
3420 targ
->opcode
= XTENSA_UNDEFINED
;
3421 targ
->insn_type
= ITYPE_LABEL
;
3422 targ
->is_specific_opcode
= FALSE
;
3423 /* Literal with no ops is a label? */
3424 assert (op
== NULL
);
3435 /* Return TRUE on success. */
3438 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3440 for (; bi
!= NULL
; bi
= bi
->next
)
3442 TInsn
*next_insn
= istack_push_space (istack
);
3444 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3451 /* Return TRUE on valid expansion. */
3454 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3456 int stack_size
= istack
->ninsn
;
3457 int steps_taken
= 0;
3458 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3461 assert (insn
->insn_type
== ITYPE_INSN
);
3462 assert (insn
->opcode
< table
->num_opcodes
);
3464 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3466 TransitionRule
*rule
= l
->rule
;
3468 if (xg_instruction_matches_rule (insn
, rule
))
3470 if (lateral_steps
== steps_taken
)
3474 /* This is it. Expand the rule to the stack. */
3475 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3478 /* Check to see if it fits. */
3479 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3481 TInsn
*insn
= &istack
->insn
[i
];
3483 if (insn
->insn_type
== ITYPE_INSN
3484 && !tinsn_has_symbolic_operands (insn
)
3485 && !xg_immeds_fit (insn
))
3487 istack
->ninsn
= stack_size
;
3500 /* Relax the assembly instruction at least "min_steps".
3501 Return the number of steps taken. */
3504 xg_assembly_relax (IStack
*istack
,
3507 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3508 offsetT pc_offset
, /* offset in fragment */
3509 int min_steps
, /* minimum conversion steps */
3510 long stretch
) /* number of bytes stretched so far */
3512 int steps_taken
= 0;
3514 /* assert (has no symbolic operands)
3515 Some of its immeds don't fit.
3516 Try to build a relaxed version.
3517 This may go through a couple of stages
3518 of single instruction transformations before
3521 TInsn single_target
;
3523 int lateral_steps
= 0;
3524 int istack_size
= istack
->ninsn
;
3526 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3527 && steps_taken
>= min_steps
)
3529 istack_push (istack
, insn
);
3532 current_insn
= *insn
;
3534 /* Walk through all of the single instruction expansions. */
3535 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3538 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3541 if (steps_taken
>= min_steps
)
3543 istack_push (istack
, &single_target
);
3547 current_insn
= single_target
;
3550 /* Now check for a multi-instruction expansion. */
3551 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3553 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3556 if (steps_taken
>= min_steps
)
3558 istack_push (istack
, ¤t_insn
);
3563 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3565 if (steps_taken
>= min_steps
)
3569 istack
->ninsn
= istack_size
;
3572 /* It's not going to work -- use the original. */
3573 istack_push (istack
, insn
);
3579 xg_force_frag_space (int size
)
3581 /* This may have the side effect of creating a new fragment for the
3582 space to go into. I just do not like the name of the "frag"
3589 xg_finish_frag (char *last_insn
,
3590 enum xtensa_relax_statesE frag_state
,
3591 enum xtensa_relax_statesE slot0_state
,
3593 bfd_boolean is_insn
)
3595 /* Finish off this fragment so that it has at LEAST the desired
3596 max_growth. If it doesn't fit in this fragment, close this one
3597 and start a new one. In either case, return a pointer to the
3598 beginning of the growth area. */
3602 xg_force_frag_space (max_growth
);
3604 old_frag
= frag_now
;
3606 frag_now
->fr_opcode
= last_insn
;
3608 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3610 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3611 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3613 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3614 xtensa_set_frag_assembly_state (frag_now
);
3616 /* Just to make sure that we did not split it up. */
3617 assert (old_frag
->fr_next
== frag_now
);
3621 /* Return TRUE if the target frag is one of the next non-empty frags. */
3624 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3629 for (; fragP
; fragP
= fragP
->fr_next
)
3631 if (fragP
== target
)
3633 if (fragP
->fr_fix
!= 0)
3635 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3637 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3638 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3640 if (fragP
->fr_type
== rs_space
)
3648 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3650 xtensa_isa isa
= xtensa_default_isa
;
3652 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3657 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3658 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3661 for (i
= 0; i
< num_ops
; i
++)
3663 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3669 if (target_op
== -1)
3672 if (insn
->ntok
<= target_op
)
3675 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3678 sym
= insn
->tok
[target_op
].X_add_symbol
;
3682 if (insn
->tok
[target_op
].X_add_number
!= 0)
3685 target_frag
= symbol_get_frag (sym
);
3686 if (target_frag
== NULL
)
3689 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3690 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3698 xg_add_branch_and_loop_targets (TInsn
*insn
)
3700 xtensa_isa isa
= xtensa_default_isa
;
3701 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3703 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3706 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3707 && insn
->tok
[i
].X_op
== O_symbol
)
3708 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3712 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3713 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3717 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3719 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3720 && insn
->tok
[i
].X_op
== O_symbol
)
3722 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3723 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3724 if (S_IS_DEFINED (sym
))
3725 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3732 /* Return FALSE if no error. */
3735 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3740 switch (instr_spec
->typ
)
3743 new_insn
->insn_type
= ITYPE_INSN
;
3744 new_insn
->opcode
= instr_spec
->opcode
;
3745 new_insn
->is_specific_opcode
= FALSE
;
3746 new_insn
->linenum
= old_insn
->linenum
;
3748 case INSTR_LITERAL_DEF
:
3749 new_insn
->insn_type
= ITYPE_LITERAL
;
3750 new_insn
->opcode
= XTENSA_UNDEFINED
;
3751 new_insn
->is_specific_opcode
= FALSE
;
3752 new_insn
->linenum
= old_insn
->linenum
;
3754 case INSTR_LABEL_DEF
:
3755 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3759 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3762 const expressionS
*src_exp
;
3768 /* The expression must be the constant. */
3769 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3770 exp
= &new_insn
->tok
[b_op
->op_num
];
3771 set_expr_const (exp
, b_op
->op_data
);
3775 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3776 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3777 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3778 exp
= &new_insn
->tok
[b_op
->op_num
];
3779 copy_expr (exp
, src_exp
);
3784 as_bad (_("can't handle generation of literal/labels yet"));
3788 as_bad (_("can't handle undefined OP TYPE"));
3793 new_insn
->ntok
= num_ops
;
3798 /* Return TRUE if it was simplified. */
3801 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3803 TransitionRule
*rule
;
3804 BuildInstr
*insn_spec
;
3806 if (old_insn
->is_specific_opcode
|| !density_supported
)
3809 rule
= xg_instruction_match (old_insn
);
3813 insn_spec
= rule
->to_instr
;
3814 /* There should only be one. */
3815 assert (insn_spec
!= NULL
);
3816 assert (insn_spec
->next
== NULL
);
3817 if (insn_spec
->next
!= NULL
)
3820 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3826 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3827 l32i.n. (2) Check the number of operands. (3) Place the instruction
3828 tokens into the stack or relax it and place multiple
3829 instructions/literals onto the stack. Return FALSE if no error. */
3832 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3836 bfd_boolean do_expand
;
3838 tinsn_init (&new_insn
);
3840 /* Narrow it if we can. xg_simplify_insn now does all the
3841 appropriate checking (e.g., for the density option). */
3842 if (xg_simplify_insn (orig_insn
, &new_insn
))
3843 orig_insn
= &new_insn
;
3845 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3847 if (orig_insn
->ntok
< noperands
)
3849 as_bad (_("found %d operands for '%s': Expected %d"),
3851 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3855 if (orig_insn
->ntok
> noperands
)
3856 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3858 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3861 /* If there are not enough operands, we will assert above. If there
3862 are too many, just cut out the extras here. */
3863 orig_insn
->ntok
= noperands
;
3865 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3868 /* If the instruction will definitely need to be relaxed, it is better
3869 to expand it now for better scheduling. Decide whether to expand
3871 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3873 /* Calls should be expanded to longcalls only in the backend relaxation
3874 so that the assembly scheduler will keep the L32R/CALLX instructions
3876 if (is_direct_call_opcode (orig_insn
->opcode
))
3879 if (tinsn_has_symbolic_operands (orig_insn
))
3881 /* The values of symbolic operands are not known yet, so only expand
3882 now if an operand is "complex" (e.g., difference of symbols) and
3883 will have to be stored as a literal regardless of the value. */
3884 if (!tinsn_has_complex_operands (orig_insn
))
3887 else if (xg_immeds_fit (orig_insn
))
3891 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3893 istack_push (istack
, orig_insn
);
3899 /* Return TRUE if the section flags are marked linkonce
3900 or the name is .gnu.linkonce.*. */
3902 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3905 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3907 flagword flags
, link_once_flags
;
3909 flags
= bfd_get_section_flags (abfd
, sec
);
3910 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3912 /* Flags might not be set yet. */
3913 if (!link_once_flags
3914 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
3915 link_once_flags
= SEC_LINK_ONCE
;
3917 return (link_once_flags
!= 0);
3922 xtensa_add_literal_sym (symbolS
*sym
)
3926 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
3928 l
->next
= literal_syms
;
3934 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
3936 static int lit_num
= 0;
3937 static char name
[256];
3940 sprintf (name
, ".L_lit_sym%d", lit_num
);
3942 /* Create a local symbol. If it is in a linkonce section, we have to
3943 be careful to make sure that if it is used in a relocation that the
3944 symbol will be in the output file. */
3945 if (get_is_linkonce_section (stdoutput
, sec
))
3947 symbolP
= symbol_new (name
, sec
, 0, frag
);
3948 S_CLEAR_EXTERNAL (symbolP
);
3949 /* symbolP->local = 1; */
3952 symbolP
= symbol_new (name
, sec
, 0, frag
);
3954 xtensa_add_literal_sym (symbolP
);
3961 /* Currently all literals that are generated here are 32-bit L32R targets. */
3964 xg_assemble_literal (/* const */ TInsn
*insn
)
3967 symbolS
*lit_sym
= NULL
;
3968 bfd_reloc_code_real_type reloc
;
3971 /* size = 4 for L32R. It could easily be larger when we move to
3972 larger constants. Add a parameter later. */
3973 offsetT litsize
= 4;
3974 offsetT litalign
= 2; /* 2^2 = 4 */
3975 expressionS saved_loc
;
3976 expressionS
* emit_val
;
3978 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
3980 assert (insn
->insn_type
== ITYPE_LITERAL
);
3981 assert (insn
->ntok
== 1); /* must be only one token here */
3983 xtensa_switch_to_literal_fragment (&state
);
3985 emit_val
= &insn
->tok
[0];
3986 if (emit_val
->X_op
== O_big
)
3988 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
3991 /* This happens when someone writes a "movi a2, big_number". */
3992 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
3993 _("invalid immediate"));
3994 xtensa_restore_emit_state (&state
);
3999 /* Force a 4-byte align here. Note that this opens a new frag, so all
4000 literals done with this function have a frag to themselves. That's
4001 important for the way text section literals work. */
4002 frag_align (litalign
, 0, 0);
4003 record_alignment (now_seg
, litalign
);
4005 switch (emit_val
->X_op
)
4008 p
= frag_more (litsize
);
4009 xtensa_set_frag_assembly_state (frag_now
);
4010 reloc
= map_operator_to_reloc (emit_val
->X_op
);
4011 if (emit_val
->X_add_symbol
)
4012 emit_val
->X_op
= O_symbol
;
4014 emit_val
->X_op
= O_constant
;
4015 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4016 litsize
, emit_val
, 0, reloc
);
4020 emit_expr (emit_val
, litsize
);
4024 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4025 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4026 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4027 lit_sym
= frag_now
->fr_symbol
;
4030 xtensa_restore_emit_state (&state
);
4036 xg_assemble_literal_space (/* const */ int size
, int slot
)
4039 /* We might have to do something about this alignment. It only
4040 takes effect if something is placed here. */
4041 offsetT litalign
= 2; /* 2^2 = 4 */
4042 fragS
*lit_saved_frag
;
4044 assert (size
% 4 == 0);
4046 xtensa_switch_to_literal_fragment (&state
);
4048 /* Force a 4-byte align here. */
4049 frag_align (litalign
, 0, 0);
4050 record_alignment (now_seg
, litalign
);
4052 xg_force_frag_space (size
);
4054 lit_saved_frag
= frag_now
;
4055 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4056 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4057 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4060 xtensa_restore_emit_state (&state
);
4061 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4065 /* Put in a fixup record based on the opcode.
4066 Return TRUE on success. */
4069 xg_add_opcode_fix (TInsn
*tinsn
,
4077 xtensa_opcode opcode
= tinsn
->opcode
;
4078 bfd_reloc_code_real_type reloc
;
4079 reloc_howto_type
*howto
;
4083 reloc
= BFD_RELOC_NONE
;
4085 /* First try the special cases for "alternate" relocs. */
4086 if (opcode
== xtensa_l32r_opcode
)
4088 if (fragP
->tc_frag_data
.use_absolute_literals
)
4089 reloc
= encode_alt_reloc (slot
);
4091 else if (opcode
== xtensa_const16_opcode
)
4093 if (expr
->X_op
== O_lo16
)
4095 reloc
= encode_reloc (slot
);
4096 expr
->X_op
= O_symbol
;
4098 else if (expr
->X_op
== O_hi16
)
4100 reloc
= encode_alt_reloc (slot
);
4101 expr
->X_op
= O_symbol
;
4105 if (opnum
!= get_relaxable_immed (opcode
))
4107 as_bad (_("invalid relocation for operand %i of '%s'"),
4108 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4112 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4113 into the symbol table where the generic portions of the assembler
4114 won't know what to do with them. */
4115 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4117 as_bad (_("invalid expression for operand %i of '%s'"),
4118 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4122 /* Next try the generic relocs. */
4123 if (reloc
== BFD_RELOC_NONE
)
4124 reloc
= encode_reloc (slot
);
4125 if (reloc
== BFD_RELOC_NONE
)
4127 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4131 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4134 as_bad (_("undefined symbol for opcode \"%s\""),
4135 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4139 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4140 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4141 howto
->pc_relative
, reloc
);
4142 the_fix
->fx_no_overflow
= 1;
4143 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4144 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4145 the_fix
->tc_fix_data
.slot
= slot
;
4152 xg_emit_insn_to_buf (TInsn
*tinsn
,
4156 bfd_boolean build_fix
)
4158 static xtensa_insnbuf insnbuf
= NULL
;
4159 bfd_boolean has_symbolic_immed
= FALSE
;
4160 bfd_boolean ok
= TRUE
;
4163 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4165 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4166 if (has_symbolic_immed
&& build_fix
)
4169 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4170 int slot
= xg_get_single_slot (tinsn
->opcode
);
4171 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4172 expressionS
*exp
= &tinsn
->tok
[opnum
];
4174 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4177 fragP
->tc_frag_data
.is_insn
= TRUE
;
4178 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4179 (unsigned char *) buf
, 0);
4185 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4187 symbolS
*sym
= get_special_literal_symbol ();
4191 assert (insn
->insn_type
== ITYPE_INSN
);
4192 for (i
= 0; i
< insn
->ntok
; i
++)
4193 if (insn
->tok
[i
].X_add_symbol
== sym
)
4194 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4200 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4202 symbolS
*sym
= get_special_label_symbol ();
4204 for (i
= 0; i
< insn
->ntok
; i
++)
4205 if (insn
->tok
[i
].X_add_symbol
== sym
)
4206 insn
->tok
[i
].X_add_symbol
= label_sym
;
4211 /* Return TRUE if the instruction can write to the specified
4212 integer register. */
4215 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4219 xtensa_isa isa
= xtensa_default_isa
;
4221 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4223 for (i
= 0; i
< num_ops
; i
++)
4226 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4227 if ((inout
== 'o' || inout
== 'm')
4228 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4230 xtensa_regfile opnd_rf
=
4231 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4232 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4234 if ((insn
->tok
[i
].X_op
== O_register
)
4235 && (insn
->tok
[i
].X_add_number
== regnum
))
4245 is_bad_loopend_opcode (const TInsn
*tinsn
)
4247 xtensa_opcode opcode
= tinsn
->opcode
;
4249 if (opcode
== XTENSA_UNDEFINED
)
4252 if (opcode
== xtensa_call0_opcode
4253 || opcode
== xtensa_callx0_opcode
4254 || opcode
== xtensa_call4_opcode
4255 || opcode
== xtensa_callx4_opcode
4256 || opcode
== xtensa_call8_opcode
4257 || opcode
== xtensa_callx8_opcode
4258 || opcode
== xtensa_call12_opcode
4259 || opcode
== xtensa_callx12_opcode
4260 || opcode
== xtensa_isync_opcode
4261 || opcode
== xtensa_ret_opcode
4262 || opcode
== xtensa_ret_n_opcode
4263 || opcode
== xtensa_retw_opcode
4264 || opcode
== xtensa_retw_n_opcode
4265 || opcode
== xtensa_waiti_opcode
4266 || opcode
== xtensa_rsr_lcount_opcode
)
4273 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4274 This allows the debugger to add unaligned labels.
4275 Also, the assembler generates stabs labels that need
4276 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4279 is_unaligned_label (symbolS
*sym
)
4281 const char *name
= S_GET_NAME (sym
);
4282 static size_t fake_size
= 0;
4286 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4289 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4291 fake_size
= strlen (FAKE_LABEL_NAME
);
4294 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4295 && (name
[fake_size
] == 'F'
4296 || name
[fake_size
] == 'L'
4297 || (name
[fake_size
] == 'e'
4298 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4306 next_non_empty_frag (const fragS
*fragP
)
4308 fragS
*next_fragP
= fragP
->fr_next
;
4310 /* Sometimes an empty will end up here due storage allocation issues.
4311 So we have to skip until we find something legit. */
4312 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4313 next_fragP
= next_fragP
->fr_next
;
4315 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4323 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4325 xtensa_opcode out_opcode
;
4326 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4328 if (next_fragP
== NULL
)
4331 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4332 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4334 *opcode
= out_opcode
;
4342 frag_format_size (const fragS
*fragP
)
4344 static xtensa_insnbuf insnbuf
= NULL
;
4345 xtensa_isa isa
= xtensa_default_isa
;
4350 insnbuf
= xtensa_insnbuf_alloc (isa
);
4353 return XTENSA_UNDEFINED
;
4355 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4356 (unsigned char *) fragP
->fr_literal
, 0);
4358 fmt
= xtensa_format_decode (isa
, insnbuf
);
4359 if (fmt
== XTENSA_UNDEFINED
)
4360 return XTENSA_UNDEFINED
;
4361 fmt_size
= xtensa_format_length (isa
, fmt
);
4363 /* If the next format won't be changing due to relaxation, just
4364 return the length of the first format. */
4365 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4368 /* If during relaxation we have to pull an instruction out of a
4369 multi-slot instruction, we will return the more conservative
4370 number. This works because alignment on bigger instructions
4371 is more restrictive than alignment on smaller instructions.
4372 This is more conservative than we would like, but it happens
4375 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4378 /* If we aren't doing one of our own relaxations or it isn't
4379 slot-based, then the insn size won't change. */
4380 if (fragP
->fr_type
!= rs_machine_dependent
)
4382 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4385 /* If an instruction is about to grow, return the longer size. */
4386 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4387 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4390 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4391 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4398 next_frag_format_size (const fragS
*fragP
)
4400 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4401 return frag_format_size (next_fragP
);
4405 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4406 required two-byte instructions to be treated as three-byte instructions
4407 for loop instruction alignment. This restriction was removed beginning
4408 with Xtensa LX. Now the only requirement on loop instruction alignment
4409 is that the first instruction of the loop must appear at an address that
4410 does not cross a fetch boundary. */
4413 get_loop_align_size (int insn_size
)
4415 if (insn_size
== XTENSA_UNDEFINED
)
4416 return xtensa_fetch_width
;
4418 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4425 /* If the next legit fragment is an end-of-loop marker,
4426 switch its state so it will instantiate a NOP. */
4429 update_next_frag_state (fragS
*fragP
)
4431 fragS
*next_fragP
= fragP
->fr_next
;
4432 fragS
*new_target
= NULL
;
4436 /* We are guaranteed there will be one of these... */
4437 while (!(next_fragP
->fr_type
== rs_machine_dependent
4438 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4439 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4440 next_fragP
= next_fragP
->fr_next
;
4442 assert (next_fragP
->fr_type
== rs_machine_dependent
4443 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4444 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4446 /* ...and one of these. */
4447 new_target
= next_fragP
->fr_next
;
4448 while (!(new_target
->fr_type
== rs_machine_dependent
4449 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4450 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4451 new_target
= new_target
->fr_next
;
4453 assert (new_target
->fr_type
== rs_machine_dependent
4454 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4455 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4458 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4460 if (next_fragP
->fr_type
== rs_machine_dependent
4461 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4463 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4467 next_fragP
= next_fragP
->fr_next
;
4473 next_frag_is_branch_target (const fragS
*fragP
)
4475 /* Sometimes an empty will end up here due to storage allocation issues,
4476 so we have to skip until we find something legit. */
4477 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4479 if (fragP
->tc_frag_data
.is_branch_target
)
4481 if (fragP
->fr_fix
!= 0)
4489 next_frag_is_loop_target (const fragS
*fragP
)
4491 /* Sometimes an empty will end up here due storage allocation issues.
4492 So we have to skip until we find something legit. */
4493 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4495 if (fragP
->tc_frag_data
.is_loop_target
)
4497 if (fragP
->fr_fix
!= 0)
4505 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4507 const fragS
*next_fragp
= fragp
->fr_next
;
4508 xtensa_opcode next_opcode
;
4510 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4513 /* Sometimes an empty will end up here due to storage allocation issues,
4514 so we have to skip until we find something legit. */
4515 while (next_fragp
->fr_fix
== 0)
4516 next_fragp
= next_fragp
->fr_next
;
4518 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4521 /* There is some implicit knowledge encoded in here.
4522 The LOOP instructions that are NOT RELAX_IMMED have
4523 been relaxed. Note that we can assume that the LOOP
4524 instruction is in slot 0 because loops aren't bundleable. */
4525 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4526 return get_expanded_loop_offset (next_opcode
);
4532 /* Mark a location where we can later insert literal frags. Update
4533 the section's literal_pool_loc, so subsequent literals can be
4534 placed nearest to their use. */
4537 xtensa_mark_literal_pool_location (void)
4539 /* Any labels pointing to the current location need
4540 to be adjusted to after the literal pool. */
4542 fragS
*pool_location
;
4544 if (use_literal_section
)
4547 /* We stash info in these frags so we can later move the literal's
4548 fixes into this frchain's fix list. */
4549 pool_location
= frag_now
;
4550 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4551 frag_variant (rs_machine_dependent
, 0, 0,
4552 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4553 xtensa_set_frag_assembly_state (frag_now
);
4554 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4555 frag_variant (rs_machine_dependent
, 0, 0,
4556 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4557 xtensa_set_frag_assembly_state (frag_now
);
4559 /* Now put a frag into the literal pool that points to this location. */
4560 set_literal_pool_location (now_seg
, pool_location
);
4561 xtensa_switch_to_non_abs_literal_fragment (&s
);
4562 frag_align (2, 0, 0);
4563 record_alignment (now_seg
, 2);
4565 /* Close whatever frag is there. */
4566 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4567 xtensa_set_frag_assembly_state (frag_now
);
4568 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4569 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4570 xtensa_restore_emit_state (&s
);
4571 xtensa_set_frag_assembly_state (frag_now
);
4575 /* Build a nop of the correct size into tinsn. */
4578 build_nop (TInsn
*tinsn
, int size
)
4584 tinsn
->opcode
= xtensa_nop_n_opcode
;
4586 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4587 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4591 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4593 tinsn
->opcode
= xtensa_or_opcode
;
4594 set_expr_const (&tinsn
->tok
[0], 1);
4595 set_expr_const (&tinsn
->tok
[1], 1);
4596 set_expr_const (&tinsn
->tok
[2], 1);
4600 tinsn
->opcode
= xtensa_nop_opcode
;
4602 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4607 /* Assemble a NOP of the requested size in the buffer. User must have
4608 allocated "buf" with at least "size" bytes. */
4611 assemble_nop (int size
, char *buf
)
4613 static xtensa_insnbuf insnbuf
= NULL
;
4616 build_nop (&tinsn
, size
);
4619 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4621 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4622 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4623 (unsigned char *) buf
, 0);
4627 /* Return the number of bytes for the offset of the expanded loop
4628 instruction. This should be incorporated into the relaxation
4629 specification but is hard-coded here. This is used to auto-align
4630 the loop instruction. It is invalid to call this function if the
4631 configuration does not have loops or if the opcode is not a loop
4635 get_expanded_loop_offset (xtensa_opcode opcode
)
4637 /* This is the OFFSET of the loop instruction in the expanded loop.
4638 This MUST correspond directly to the specification of the loop
4639 expansion. It will be validated on fragment conversion. */
4640 assert (opcode
!= XTENSA_UNDEFINED
);
4641 if (opcode
== xtensa_loop_opcode
)
4643 if (opcode
== xtensa_loopnez_opcode
)
4645 if (opcode
== xtensa_loopgtz_opcode
)
4647 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4653 get_literal_pool_location (segT seg
)
4655 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4660 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4662 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4666 /* Set frag assembly state should be called when a new frag is
4667 opened and after a frag has been closed. */
4670 xtensa_set_frag_assembly_state (fragS
*fragP
)
4672 if (!density_supported
)
4673 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4675 /* This function is called from subsegs_finish, which is called
4676 after xtensa_end, so we can't use "use_transform" or
4677 "use_schedule" here. */
4678 if (!directive_state
[directive_transform
])
4679 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4680 if (directive_state
[directive_longcalls
])
4681 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4682 fragP
->tc_frag_data
.use_absolute_literals
=
4683 directive_state
[directive_absolute_literals
];
4684 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4689 relaxable_section (asection
*sec
)
4691 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4696 xtensa_mark_frags_for_org (void)
4700 /* Walk over each fragment of all of the current segments. If we find
4701 a .org frag in any of the segments, mark all frags prior to it as
4702 "no transform", which will prevent linker optimizations from messing
4703 up the .org distance. This should be done after
4704 xtensa_find_unmarked_state_frags, because we don't want to worry here
4705 about that function trashing the data we save here. */
4707 for (seclist
= &stdoutput
->sections
;
4708 seclist
&& *seclist
;
4709 seclist
= &(*seclist
)->next
)
4711 segT sec
= *seclist
;
4712 segment_info_type
*seginfo
;
4715 flags
= bfd_get_section_flags (stdoutput
, sec
);
4716 if (flags
& SEC_DEBUGGING
)
4718 if (!(flags
& SEC_ALLOC
))
4721 seginfo
= seg_info (sec
);
4722 if (seginfo
&& seginfo
->frchainP
)
4724 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4725 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4726 fragP
= fragP
->fr_next
)
4728 /* cvt_frag_to_fill has changed the fr_type of org frags to
4729 rs_fill, so use the value as cached in rs_subtype here. */
4730 if (fragP
->fr_subtype
== RELAX_ORG
)
4732 while (last_fragP
!= fragP
->fr_next
)
4734 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4735 last_fragP
= last_fragP
->fr_next
;
4745 xtensa_find_unmarked_state_frags (void)
4749 /* Walk over each fragment of all of the current segments. For each
4750 unmarked fragment, mark it with the same info as the previous
4752 for (seclist
= &stdoutput
->sections
;
4753 seclist
&& *seclist
;
4754 seclist
= &(*seclist
)->next
)
4756 segT sec
= *seclist
;
4757 segment_info_type
*seginfo
;
4760 flags
= bfd_get_section_flags (stdoutput
, sec
);
4761 if (flags
& SEC_DEBUGGING
)
4763 if (!(flags
& SEC_ALLOC
))
4766 seginfo
= seg_info (sec
);
4767 if (seginfo
&& seginfo
->frchainP
)
4769 fragS
*last_fragP
= 0;
4770 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4771 fragP
= fragP
->fr_next
)
4773 if (fragP
->fr_fix
!= 0
4774 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4776 if (last_fragP
== 0)
4778 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4779 _("assembly state not set for first frag in section %s"),
4784 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4785 fragP
->tc_frag_data
.is_no_density
=
4786 last_fragP
->tc_frag_data
.is_no_density
;
4787 fragP
->tc_frag_data
.is_no_transform
=
4788 last_fragP
->tc_frag_data
.is_no_transform
;
4789 fragP
->tc_frag_data
.use_longcalls
=
4790 last_fragP
->tc_frag_data
.use_longcalls
;
4791 fragP
->tc_frag_data
.use_absolute_literals
=
4792 last_fragP
->tc_frag_data
.use_absolute_literals
;
4795 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4804 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4806 void *unused ATTRIBUTE_UNUSED
)
4808 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4809 segment_info_type
*seginfo
= seg_info (sec
);
4810 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4812 if (flags
& SEC_CODE
)
4814 xtensa_isa isa
= xtensa_default_isa
;
4815 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4816 while (frag
!= NULL
)
4818 if (frag
->tc_frag_data
.is_branch_target
)
4821 addressT branch_align
, frag_addr
;
4824 xtensa_insnbuf_from_chars
4825 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4826 fmt
= xtensa_format_decode (isa
, insnbuf
);
4827 op_size
= xtensa_format_length (isa
, fmt
);
4828 branch_align
= 1 << branch_align_power (sec
);
4829 frag_addr
= frag
->fr_address
% branch_align
;
4830 if (frag_addr
+ op_size
> branch_align
)
4831 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4832 _("unaligned branch target: %d bytes at 0x%lx"),
4833 op_size
, (long) frag
->fr_address
);
4835 frag
= frag
->fr_next
;
4837 xtensa_insnbuf_free (isa
, insnbuf
);
4843 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4845 void *unused ATTRIBUTE_UNUSED
)
4847 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4848 segment_info_type
*seginfo
= seg_info (sec
);
4849 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4850 xtensa_isa isa
= xtensa_default_isa
;
4852 if (flags
& SEC_CODE
)
4854 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4855 while (frag
!= NULL
)
4857 if (frag
->tc_frag_data
.is_first_loop_insn
)
4863 xtensa_insnbuf_from_chars
4864 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4865 fmt
= xtensa_format_decode (isa
, insnbuf
);
4866 op_size
= xtensa_format_length (isa
, fmt
);
4867 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4869 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4870 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4871 _("unaligned loop: %d bytes at 0x%lx"),
4872 op_size
, (long) frag
->fr_address
);
4874 frag
= frag
->fr_next
;
4876 xtensa_insnbuf_free (isa
, insnbuf
);
4882 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4884 xtensa_isa isa
= xtensa_default_isa
;
4885 static xtensa_insnbuf insnbuf
= NULL
;
4886 static xtensa_insnbuf slotbuf
= NULL
;
4889 bfd_boolean alt_reloc
;
4890 xtensa_opcode opcode
;
4891 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4893 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4895 as_fatal (_("unexpected fix"));
4899 insnbuf
= xtensa_insnbuf_alloc (isa
);
4900 slotbuf
= xtensa_insnbuf_alloc (isa
);
4903 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4904 fmt
= xtensa_format_decode (isa
, insnbuf
);
4905 if (fmt
== XTENSA_UNDEFINED
)
4906 as_fatal (_("undecodable fix"));
4907 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4908 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4909 if (opcode
== XTENSA_UNDEFINED
)
4910 as_fatal (_("undecodable fix"));
4912 /* CONST16 immediates are not PC-relative, despite the fact that we
4913 reuse the normal PC-relative operand relocations for the low part
4914 of a CONST16 operand. */
4915 if (opcode
== xtensa_const16_opcode
)
4918 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4919 get_relaxable_immed (opcode
), val
,
4920 fixP
->fx_file
, fixP
->fx_line
);
4922 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4923 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
4929 /* External Functions and Other GAS Hooks. */
4932 xtensa_target_format (void)
4934 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4939 xtensa_file_arch_init (bfd
*abfd
)
4941 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4946 md_number_to_chars (char *buf
, valueT val
, int n
)
4948 if (target_big_endian
)
4949 number_to_chars_bigendian (buf
, val
, n
);
4951 number_to_chars_littleendian (buf
, val
, n
);
4955 /* This function is called once, at assembler startup time. It should
4956 set up all the tables, etc. that the MD part of the assembler will
4962 segT current_section
= now_seg
;
4963 int current_subsec
= now_subseg
;
4966 xtensa_default_isa
= xtensa_isa_init (0, 0);
4967 isa
= xtensa_default_isa
;
4971 /* Set up the literal sections. */
4972 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
4974 subseg_set (current_section
, current_subsec
);
4976 xg_init_vinsn (&cur_vinsn
);
4978 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
4979 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
4980 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
4981 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
4982 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
4983 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
4984 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
4985 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
4986 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
4987 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
4988 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
4989 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
4990 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
4991 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
4992 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
4993 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
4994 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
4995 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
4996 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
4997 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
4998 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
4999 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5000 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5001 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5002 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5003 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5004 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5005 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5006 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5008 init_op_placement_info_table ();
5010 /* Set up the assembly state. */
5011 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5012 xtensa_set_frag_assembly_state (frag_now
);
5016 /* TC_INIT_FIX_DATA hook */
5019 xtensa_init_fix_data (fixS
*x
)
5021 x
->tc_fix_data
.slot
= 0;
5022 x
->tc_fix_data
.X_add_symbol
= NULL
;
5023 x
->tc_fix_data
.X_add_number
= 0;
5027 /* tc_frob_label hook */
5030 xtensa_frob_label (symbolS
*sym
)
5034 if (cur_vinsn
.inside_bundle
)
5036 as_bad (_("labels are not valid inside bundles"));
5040 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5042 /* Since the label was already attached to a frag associated with the
5043 previous basic block, it now needs to be reset to the current frag. */
5044 symbol_set_frag (sym
, frag_now
);
5045 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5047 if (generating_literals
)
5048 xtensa_add_literal_sym (sym
);
5050 xtensa_add_insn_label (sym
);
5052 if (symbol_get_tc (sym
)->is_loop_target
)
5054 if ((get_last_insn_flags (now_seg
, now_subseg
)
5055 & FLAG_IS_BAD_LOOPEND
) != 0)
5056 as_bad (_("invalid last instruction for a zero-overhead loop"));
5058 xtensa_set_frag_assembly_state (frag_now
);
5059 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5060 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5062 xtensa_set_frag_assembly_state (frag_now
);
5063 xtensa_move_labels (frag_now
, 0);
5066 /* No target aligning in the absolute section. */
5067 if (now_seg
!= absolute_section
5068 && do_align_targets ()
5069 && !is_unaligned_label (sym
)
5070 && !generating_literals
)
5072 xtensa_set_frag_assembly_state (frag_now
);
5074 frag_var (rs_machine_dependent
,
5076 RELAX_DESIRE_ALIGN_IF_TARGET
,
5077 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5078 xtensa_set_frag_assembly_state (frag_now
);
5079 xtensa_move_labels (frag_now
, 0);
5082 /* We need to mark the following properties even if we aren't aligning. */
5084 /* If the label is already known to be a branch target, i.e., a
5085 forward branch, mark the frag accordingly. Backward branches
5086 are handled by xg_add_branch_and_loop_targets. */
5087 if (symbol_get_tc (sym
)->is_branch_target
)
5088 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5090 /* Loops only go forward, so they can be identified here. */
5091 if (symbol_get_tc (sym
)->is_loop_target
)
5092 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5094 dwarf2_emit_label (sym
);
5098 /* tc_unrecognized_line hook */
5101 xtensa_unrecognized_line (int ch
)
5106 if (cur_vinsn
.inside_bundle
== 0)
5108 /* PR8110: Cannot emit line number info inside a FLIX bundle
5109 when using --gstabs. Temporarily disable debug info. */
5110 generate_lineno_debug ();
5111 if (debug_type
== DEBUG_STABS
)
5113 xt_saved_debug_type
= debug_type
;
5114 debug_type
= DEBUG_NONE
;
5117 cur_vinsn
.inside_bundle
= 1;
5121 as_bad (_("extra opening brace"));
5127 if (cur_vinsn
.inside_bundle
)
5128 finish_vinsn (&cur_vinsn
);
5131 as_bad (_("extra closing brace"));
5136 as_bad (_("syntax error"));
5143 /* md_flush_pending_output hook */
5146 xtensa_flush_pending_output (void)
5148 /* This line fixes a bug where automatically generated gstabs info
5149 separates a function label from its entry instruction, ending up
5150 with the literal position between the function label and the entry
5151 instruction and crashing code. It only happens with --gstabs and
5152 --text-section-literals, and when several other obscure relaxation
5153 conditions are met. */
5154 if (outputting_stabs_line_debug
)
5157 if (cur_vinsn
.inside_bundle
)
5158 as_bad (_("missing closing brace"));
5160 /* If there is a non-zero instruction fragment, close it. */
5161 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5163 frag_wane (frag_now
);
5165 xtensa_set_frag_assembly_state (frag_now
);
5167 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5169 xtensa_clear_insn_labels ();
5173 /* We had an error while parsing an instruction. The string might look
5174 like this: "insn arg1, arg2 }". If so, we need to see the closing
5175 brace and reset some fields. Otherwise, the vinsn never gets closed
5176 and the num_slots field will grow past the end of the array of slots,
5177 and bad things happen. */
5180 error_reset_cur_vinsn (void)
5182 if (cur_vinsn
.inside_bundle
)
5184 if (*input_line_pointer
== '}'
5185 || *(input_line_pointer
- 1) == '}'
5186 || *(input_line_pointer
- 2) == '}')
5187 xg_clear_vinsn (&cur_vinsn
);
5193 md_assemble (char *str
)
5195 xtensa_isa isa
= xtensa_default_isa
;
5196 char *opname
, *file_name
;
5198 bfd_boolean has_underbar
= FALSE
;
5199 char *arg_strings
[MAX_INSN_ARGS
];
5201 TInsn orig_insn
; /* Original instruction from the input. */
5203 tinsn_init (&orig_insn
);
5205 /* Split off the opcode. */
5206 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5207 opname
= xmalloc (opnamelen
+ 1);
5208 memcpy (opname
, str
, opnamelen
);
5209 opname
[opnamelen
] = '\0';
5211 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5214 as_bad (_("syntax error"));
5218 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5221 /* Check for an underbar prefix. */
5224 has_underbar
= TRUE
;
5228 orig_insn
.insn_type
= ITYPE_INSN
;
5230 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5232 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5233 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5235 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5236 if (fmt
== XTENSA_UNDEFINED
)
5238 as_bad (_("unknown opcode or format name '%s'"), opname
);
5239 error_reset_cur_vinsn ();
5242 if (!cur_vinsn
.inside_bundle
)
5244 as_bad (_("format names only valid inside bundles"));
5245 error_reset_cur_vinsn ();
5248 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5249 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5251 cur_vinsn
.format
= fmt
;
5252 free (has_underbar
? opname
- 1 : opname
);
5253 error_reset_cur_vinsn ();
5257 /* Parse the arguments. */
5258 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5260 as_bad (_("syntax error"));
5261 error_reset_cur_vinsn ();
5265 /* Free the opcode and argument strings, now that they've been parsed. */
5266 free (has_underbar
? opname
- 1 : opname
);
5268 while (num_args
-- > 0)
5269 free (arg_strings
[num_args
]);
5271 /* Get expressions for invisible operands. */
5272 if (get_invisible_operands (&orig_insn
))
5274 error_reset_cur_vinsn ();
5278 /* Check for the right number and type of arguments. */
5279 if (tinsn_check_arguments (&orig_insn
))
5281 error_reset_cur_vinsn ();
5285 /* A FLIX bundle may be spread across multiple input lines. We want to
5286 report the first such line in the debug information. Record the line
5287 number for each TInsn (assume the file name doesn't change), so the
5288 first line can be found later. */
5289 as_where (&file_name
, &orig_insn
.linenum
);
5291 xg_add_branch_and_loop_targets (&orig_insn
);
5293 /* Check that immediate value for ENTRY is >= 16. */
5294 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5296 expressionS
*exp
= &orig_insn
.tok
[2];
5297 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5298 as_warn (_("entry instruction with stack decrement < 16"));
5302 assemble_tokens (opcode, tok, ntok);
5303 expand the tokens from the orig_insn into the
5304 stack of instructions that will not expand
5305 unless required at relaxation time. */
5307 if (!cur_vinsn
.inside_bundle
)
5308 emit_single_op (&orig_insn
);
5309 else /* We are inside a bundle. */
5311 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5312 cur_vinsn
.num_slots
++;
5313 if (*input_line_pointer
== '}'
5314 || *(input_line_pointer
- 1) == '}'
5315 || *(input_line_pointer
- 2) == '}')
5316 finish_vinsn (&cur_vinsn
);
5319 /* We've just emitted a new instruction so clear the list of labels. */
5320 xtensa_clear_insn_labels ();
5324 /* HANDLE_ALIGN hook */
5326 /* For a .align directive, we mark the previous block with the alignment
5327 information. This will be placed in the object file in the
5328 property section corresponding to this section. */
5331 xtensa_handle_align (fragS
*fragP
)
5334 && ! fragP
->tc_frag_data
.is_literal
5335 && (fragP
->fr_type
== rs_align
5336 || fragP
->fr_type
== rs_align_code
)
5337 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5338 && fragP
->fr_offset
> 0
5339 && now_seg
!= bss_section
)
5341 fragP
->tc_frag_data
.is_align
= TRUE
;
5342 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5345 if (fragP
->fr_type
== rs_align_test
)
5348 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5350 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5351 _("unaligned entry instruction"));
5354 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5355 fragP
->fr_subtype
= RELAX_ORG
;
5359 /* TC_FRAG_INIT hook */
5362 xtensa_frag_init (fragS
*frag
)
5364 xtensa_set_frag_assembly_state (frag
);
5369 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5375 /* Round up a section size to the appropriate boundary. */
5378 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5380 return size
; /* Byte alignment is fine. */
5385 md_pcrel_from (fixS
*fixP
)
5388 static xtensa_insnbuf insnbuf
= NULL
;
5389 static xtensa_insnbuf slotbuf
= NULL
;
5392 xtensa_opcode opcode
;
5395 xtensa_isa isa
= xtensa_default_isa
;
5396 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5397 bfd_boolean alt_reloc
;
5399 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5404 insnbuf
= xtensa_insnbuf_alloc (isa
);
5405 slotbuf
= xtensa_insnbuf_alloc (isa
);
5408 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5409 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5410 fmt
= xtensa_format_decode (isa
, insnbuf
);
5412 if (fmt
== XTENSA_UNDEFINED
)
5413 as_fatal (_("bad instruction format"));
5415 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5416 as_fatal (_("invalid relocation"));
5418 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5419 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5421 /* Check for "alternate" relocations (operand not specified). None
5422 of the current uses for these are really PC-relative. */
5423 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5425 if (opcode
!= xtensa_l32r_opcode
5426 && opcode
!= xtensa_const16_opcode
)
5427 as_fatal (_("invalid relocation for '%s' instruction"),
5428 xtensa_opcode_name (isa
, opcode
));
5432 opnum
= get_relaxable_immed (opcode
);
5434 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5435 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5437 as_bad_where (fixP
->fx_file
,
5439 _("invalid relocation for operand %d of '%s'"),
5440 opnum
, xtensa_opcode_name (isa
, opcode
));
5443 return 0 - opnd_value
;
5447 /* TC_FORCE_RELOCATION hook */
5450 xtensa_force_relocation (fixS
*fix
)
5452 switch (fix
->fx_r_type
)
5454 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5455 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5456 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5457 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5458 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5459 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5460 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5461 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5462 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5463 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5464 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5465 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5466 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5467 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5468 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5469 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5475 if (linkrelax
&& fix
->fx_addsy
5476 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5479 return generic_force_reloc (fix
);
5483 /* TC_VALIDATE_FIX_SUB hook */
5486 xtensa_validate_fix_sub (fixS
*fix
)
5488 segT add_symbol_segment
, sub_symbol_segment
;
5490 /* The difference of two symbols should be resolved by the assembler when
5491 linkrelax is not set. If the linker may relax the section containing
5492 the symbols, then an Xtensa DIFF relocation must be generated so that
5493 the linker knows to adjust the difference value. */
5494 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5497 /* Make sure both symbols are in the same segment, and that segment is
5498 "normal" and relaxable. If the segment is not "normal", then the
5499 fix is not valid. If the segment is not "relaxable", then the fix
5500 should have been handled earlier. */
5501 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5502 if (! SEG_NORMAL (add_symbol_segment
) ||
5503 ! relaxable_section (add_symbol_segment
))
5505 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5506 return (sub_symbol_segment
== add_symbol_segment
);
5510 /* NO_PSEUDO_DOT hook */
5512 /* This function has nothing to do with pseudo dots, but this is the
5513 nearest macro to where the check needs to take place. FIXME: This
5517 xtensa_check_inside_bundle (void)
5519 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5520 as_bad (_("directives are not valid inside bundles"));
5522 /* This function must always return FALSE because it is called via a
5523 macro that has nothing to do with bundling. */
5528 /* md_elf_section_change_hook */
5531 xtensa_elf_section_change_hook (void)
5533 /* Set up the assembly state. */
5534 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5535 xtensa_set_frag_assembly_state (frag_now
);
5539 /* tc_fix_adjustable hook */
5542 xtensa_fix_adjustable (fixS
*fixP
)
5544 /* An offset is not allowed in combination with the difference of two
5545 symbols, but that cannot be easily detected after a local symbol
5546 has been adjusted to a (section+offset) form. Return 0 so that such
5547 an fix will not be adjusted. */
5548 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5549 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5552 /* We need the symbol name for the VTABLE entries. */
5553 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5554 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5562 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5564 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5567 /* Subtracted symbols are only allowed for a few relocation types, and
5568 unless linkrelax is enabled, they should not make it to this point. */
5569 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5570 || fixP
->fx_r_type
== BFD_RELOC_16
5571 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5574 switch (fixP
->fx_r_type
)
5581 switch (fixP
->fx_r_type
)
5584 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5587 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5590 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5596 /* An offset is only allowed when it results from adjusting a
5597 local symbol into a section-relative offset. If the offset
5598 came from the original expression, tc_fix_adjustable will have
5599 prevented the fix from being converted to a section-relative
5600 form so that we can flag the error here. */
5601 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5603 _("cannot represent subtraction with an offset"));
5605 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5606 - S_GET_VALUE (fixP
->fx_subsy
));
5608 /* The difference value gets written out, and the DIFF reloc
5609 identifies the address of the subtracted symbol (i.e., the one
5610 with the lowest address). */
5612 fixP
->fx_offset
-= val
;
5613 fixP
->fx_subsy
= NULL
;
5615 else if (! fixP
->fx_addsy
)
5622 case BFD_RELOC_XTENSA_PLT
:
5623 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5624 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5627 case BFD_RELOC_XTENSA_SLOT0_OP
:
5628 case BFD_RELOC_XTENSA_SLOT1_OP
:
5629 case BFD_RELOC_XTENSA_SLOT2_OP
:
5630 case BFD_RELOC_XTENSA_SLOT3_OP
:
5631 case BFD_RELOC_XTENSA_SLOT4_OP
:
5632 case BFD_RELOC_XTENSA_SLOT5_OP
:
5633 case BFD_RELOC_XTENSA_SLOT6_OP
:
5634 case BFD_RELOC_XTENSA_SLOT7_OP
:
5635 case BFD_RELOC_XTENSA_SLOT8_OP
:
5636 case BFD_RELOC_XTENSA_SLOT9_OP
:
5637 case BFD_RELOC_XTENSA_SLOT10_OP
:
5638 case BFD_RELOC_XTENSA_SLOT11_OP
:
5639 case BFD_RELOC_XTENSA_SLOT12_OP
:
5640 case BFD_RELOC_XTENSA_SLOT13_OP
:
5641 case BFD_RELOC_XTENSA_SLOT14_OP
:
5644 /* Write the tentative value of a PC-relative relocation to a
5645 local symbol into the instruction. The value will be ignored
5646 by the linker, and it makes the object file disassembly
5647 readable when all branch targets are encoded in relocations. */
5649 assert (fixP
->fx_addsy
);
5650 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5651 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5653 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5654 - md_pcrel_from (fixP
));
5655 (void) xg_apply_fix_value (fixP
, val
);
5658 else if (! fixP
->fx_addsy
)
5661 if (xg_apply_fix_value (fixP
, val
))
5666 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5667 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5668 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5669 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5670 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5671 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5672 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5673 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5674 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5675 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5676 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5677 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5678 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5679 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5680 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5681 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5682 /* These all need to be resolved at link-time. Do nothing now. */
5685 case BFD_RELOC_VTABLE_INHERIT
:
5686 case BFD_RELOC_VTABLE_ENTRY
:
5691 as_bad (_("unhandled local relocation fix %s"),
5692 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5698 md_atof (int type
, char *litP
, int *sizeP
)
5701 LITTLENUM_TYPE words
[4];
5717 return "bad call to md_atof";
5720 t
= atof_ieee (input_line_pointer
, type
, words
);
5722 input_line_pointer
= t
;
5726 for (i
= prec
- 1; i
>= 0; i
--)
5729 if (target_big_endian
)
5730 idx
= (prec
- 1 - i
);
5732 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5741 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5743 return total_frag_text_expansion (fragP
);
5747 /* Translate internal representation of relocation info to BFD target
5751 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5755 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5756 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5757 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5758 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5760 /* Make sure none of our internal relocations make it this far.
5761 They'd better have been fully resolved by this point. */
5762 assert ((int) fixp
->fx_r_type
> 0);
5764 reloc
->addend
= fixp
->fx_offset
;
5766 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5767 if (reloc
->howto
== NULL
)
5769 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5770 _("cannot represent `%s' relocation in object file"),
5771 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5772 free (reloc
->sym_ptr_ptr
);
5777 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5778 as_fatal (_("internal error? cannot generate `%s' relocation"),
5779 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5785 /* Checks for resource conflicts between instructions. */
5787 /* The func unit stuff could be implemented as bit-vectors rather
5788 than the iterative approach here. If it ends up being too
5789 slow, we will switch it. */
5792 new_resource_table (void *data
,
5795 unit_num_copies_func uncf
,
5796 opcode_num_units_func onuf
,
5797 opcode_funcUnit_use_unit_func ouuf
,
5798 opcode_funcUnit_use_stage_func ousf
)
5801 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5803 rt
->cycles
= cycles
;
5804 rt
->allocated_cycles
= cycles
;
5806 rt
->unit_num_copies
= uncf
;
5807 rt
->opcode_num_units
= onuf
;
5808 rt
->opcode_unit_use
= ouuf
;
5809 rt
->opcode_unit_stage
= ousf
;
5811 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
5812 for (i
= 0; i
< cycles
; i
++)
5813 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
5820 clear_resource_table (resource_table
*rt
)
5823 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5824 for (j
= 0; j
< rt
->num_units
; j
++)
5825 rt
->units
[i
][j
] = 0;
5829 /* We never shrink it, just fake it into thinking so. */
5832 resize_resource_table (resource_table
*rt
, int cycles
)
5836 rt
->cycles
= cycles
;
5837 if (cycles
<= rt
->allocated_cycles
)
5840 old_cycles
= rt
->allocated_cycles
;
5841 rt
->allocated_cycles
= cycles
;
5843 rt
->units
= xrealloc (rt
->units
,
5844 rt
->allocated_cycles
* sizeof (unsigned char *));
5845 for (i
= 0; i
< old_cycles
; i
++)
5846 rt
->units
[i
] = xrealloc (rt
->units
[i
],
5847 rt
->num_units
* sizeof (unsigned char));
5848 for (i
= old_cycles
; i
< cycles
; i
++)
5849 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
5854 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5857 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5859 for (i
= 0; i
< uses
; i
++)
5861 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5862 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5863 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5864 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5865 if (copies_in_use
>= copies
)
5873 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5876 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5878 for (i
= 0; i
< uses
; i
++)
5880 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5881 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5882 /* Note that this allows resources to be oversubscribed. That's
5883 essential to the way the optional scheduler works.
5884 resources_available reports when a resource is over-subscribed,
5885 so it's easy to tell. */
5886 rt
->units
[stage
+ cycle
][unit
]++;
5892 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5895 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5897 for (i
= 0; i
< uses
; i
++)
5899 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5900 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5901 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
5902 rt
->units
[stage
+ cycle
][unit
]--;
5907 /* Wrapper functions make parameterized resource reservation
5911 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5913 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5919 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5921 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5926 /* Note that this function does not check issue constraints, but
5927 solely whether the hardware is available to execute the given
5928 instructions together. It also doesn't check if the tinsns
5929 write the same state, or access the same tieports. That is
5930 checked by check_t1_t2_reads_and_writes. */
5933 resources_conflict (vliw_insn
*vinsn
)
5936 static resource_table
*rt
= NULL
;
5938 /* This is the most common case by far. Optimize it. */
5939 if (vinsn
->num_slots
== 1)
5944 xtensa_isa isa
= xtensa_default_isa
;
5945 rt
= new_resource_table
5946 (isa
, xtensa_isa_num_pipe_stages (isa
),
5947 xtensa_isa_num_funcUnits (isa
),
5948 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5949 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5950 opcode_funcUnit_use_unit
,
5951 opcode_funcUnit_use_stage
);
5954 clear_resource_table (rt
);
5956 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5958 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5960 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5967 /* finish_vinsn, emit_single_op and helper functions. */
5969 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5970 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5971 static void xg_assemble_vliw_tokens (vliw_insn
*);
5974 /* We have reached the end of a bundle; emit into the frag. */
5977 finish_vinsn (vliw_insn
*vinsn
)
5984 if (find_vinsn_conflicts (vinsn
))
5986 xg_clear_vinsn (vinsn
);
5990 /* First, find a format that works. */
5991 if (vinsn
->format
== XTENSA_UNDEFINED
)
5992 vinsn
->format
= xg_find_narrowest_format (vinsn
);
5994 if (vinsn
->format
== XTENSA_UNDEFINED
)
5996 as_where (&file_name
, &line
);
5997 as_bad_where (file_name
, line
,
5998 _("couldn't find a valid instruction format"));
5999 fprintf (stderr
, _(" ops were: "));
6000 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6001 fprintf (stderr
, _(" %s;"),
6002 xtensa_opcode_name (xtensa_default_isa
,
6003 vinsn
->slots
[i
].opcode
));
6004 fprintf (stderr
, _("\n"));
6005 xg_clear_vinsn (vinsn
);
6009 if (vinsn
->num_slots
6010 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6012 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6013 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6014 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6016 xg_clear_vinsn (vinsn
);
6020 if (resources_conflict (vinsn
))
6022 as_where (&file_name
, &line
);
6023 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6024 fprintf (stderr
, " ops were: ");
6025 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6026 fprintf (stderr
, " %s;",
6027 xtensa_opcode_name (xtensa_default_isa
,
6028 vinsn
->slots
[i
].opcode
));
6029 fprintf (stderr
, "\n");
6030 xg_clear_vinsn (vinsn
);
6034 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6036 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6038 symbolS
*lit_sym
= NULL
;
6040 bfd_boolean e
= FALSE
;
6041 bfd_boolean saved_density
= density_supported
;
6043 /* We don't want to narrow ops inside multi-slot bundles. */
6044 if (vinsn
->num_slots
> 1)
6045 density_supported
= FALSE
;
6047 istack_init (&slotstack
);
6048 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6050 vinsn
->slots
[i
].opcode
=
6051 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6053 vinsn
->slots
[i
].ntok
= 0;
6056 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6062 density_supported
= saved_density
;
6066 xg_clear_vinsn (vinsn
);
6070 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6072 TInsn
*insn
= &slotstack
.insn
[j
];
6073 if (insn
->insn_type
== ITYPE_LITERAL
)
6075 assert (lit_sym
== NULL
);
6076 lit_sym
= xg_assemble_literal (insn
);
6080 assert (insn
->insn_type
== ITYPE_INSN
);
6082 xg_resolve_literals (insn
, lit_sym
);
6083 if (j
!= slotstack
.ninsn
- 1)
6084 emit_single_op (insn
);
6088 if (vinsn
->num_slots
> 1)
6090 if (opcode_fits_format_slot
6091 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6094 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6098 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6099 if (vinsn
->format
== XTENSA_UNDEFINED
)
6100 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6102 vinsn
->slots
[i
].opcode
6103 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6106 vinsn
->slots
[i
].ntok
= 0;
6111 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6112 vinsn
->format
= XTENSA_UNDEFINED
;
6117 /* Now check resource conflicts on the modified bundle. */
6118 if (resources_conflict (vinsn
))
6120 as_where (&file_name
, &line
);
6121 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6122 fprintf (stderr
, " ops were: ");
6123 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6124 fprintf (stderr
, " %s;",
6125 xtensa_opcode_name (xtensa_default_isa
,
6126 vinsn
->slots
[i
].opcode
));
6127 fprintf (stderr
, "\n");
6128 xg_clear_vinsn (vinsn
);
6132 /* First, find a format that works. */
6133 if (vinsn
->format
== XTENSA_UNDEFINED
)
6134 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6136 xg_assemble_vliw_tokens (vinsn
);
6138 xg_clear_vinsn (vinsn
);
6142 /* Given an vliw instruction, what conflicts are there in register
6143 usage and in writes to states and queues?
6145 This function does two things:
6146 1. Reports an error when a vinsn contains illegal combinations
6147 of writes to registers states or queues.
6148 2. Marks individual tinsns as not relaxable if the combination
6149 contains antidependencies.
6151 Job 2 handles things like swap semantics in instructions that need
6152 to be relaxed. For example,
6156 normally would be relaxed to
6161 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6163 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6165 then we can't relax it into
6168 { add a0, a1, a0 ; add a2, a0, a4 ; }
6170 because the value of a0 is trashed before the second add can read it. */
6172 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6175 find_vinsn_conflicts (vliw_insn
*vinsn
)
6179 xtensa_isa isa
= xtensa_default_isa
;
6181 assert (!past_xtensa_end
);
6183 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6185 TInsn
*op1
= &vinsn
->slots
[i
];
6186 if (op1
->is_specific_opcode
)
6187 op1
->keep_wide
= TRUE
;
6189 op1
->keep_wide
= FALSE
;
6192 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6194 TInsn
*op1
= &vinsn
->slots
[i
];
6196 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6199 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6203 TInsn
*op2
= &vinsn
->slots
[j
];
6204 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6205 switch (conflict_type
)
6208 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6209 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6210 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6213 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6214 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6215 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6218 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6219 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6220 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6223 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6224 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6225 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6228 /* Everything is OK. */
6231 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6232 || conflict_type
== 'a');
6239 as_bad (_("multiple branches or jumps in the same bundle"));
6247 /* Check how the state used by t1 and t2 relate.
6250 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6251 case B: no relationship between what is read and written (both could
6252 read the same reg though)
6253 case C: t1 writes a register t2 writes (a register conflict within a
6255 case D: t1 writes a state that t2 also writes
6256 case E: t1 writes a tie queue that t2 also writes
6257 case F: two volatile queue accesses
6261 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6263 xtensa_isa isa
= xtensa_default_isa
;
6264 xtensa_regfile t1_regfile
, t2_regfile
;
6266 int t1_base_reg
, t1_last_reg
;
6267 int t2_base_reg
, t2_last_reg
;
6268 char t1_inout
, t2_inout
;
6270 char conflict
= 'b';
6275 bfd_boolean t1_volatile
= FALSE
;
6276 bfd_boolean t2_volatile
= FALSE
;
6278 /* Check registers. */
6279 for (j
= 0; j
< t2
->ntok
; j
++)
6281 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6284 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6285 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6286 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6288 for (i
= 0; i
< t1
->ntok
; i
++)
6290 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6293 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6295 if (t1_regfile
!= t2_regfile
)
6298 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6299 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6301 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6302 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6304 if (t1_inout
== 'm' || t1_inout
== 'o'
6305 || t2_inout
== 'm' || t2_inout
== 'o')
6312 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6313 t1_last_reg
= (t1_base_reg
6314 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6316 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6318 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6320 if (t1_reg
!= t2_reg
)
6323 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6329 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6335 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6343 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6344 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6345 for (j
= 0; j
< t2_states
; j
++)
6347 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6348 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6349 for (i
= 0; i
< t1_states
; i
++)
6351 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6352 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6356 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6362 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6368 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6373 /* Check tieports. */
6374 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6375 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6376 for (j
= 0; j
< t2_interfaces
; j
++)
6378 xtensa_interface t2_int
6379 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6380 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6382 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6383 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6386 for (i
= 0; i
< t1_interfaces
; i
++)
6388 xtensa_interface t1_int
6389 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6390 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6392 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6393 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6396 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6399 if (t1_int
!= t2_int
)
6402 if (t2_inout
== 'i' && t1_inout
== 'o')
6408 if (t1_inout
== 'i' && t2_inout
== 'o')
6414 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6423 static xtensa_format
6424 xg_find_narrowest_format (vliw_insn
*vinsn
)
6426 /* Right now we assume that the ops within the vinsn are properly
6427 ordered for the slots that the programmer wanted them in. In
6428 other words, we don't rearrange the ops in hopes of finding a
6429 better format. The scheduler handles that. */
6431 xtensa_isa isa
= xtensa_default_isa
;
6432 xtensa_format format
;
6433 vliw_insn v_copy
= *vinsn
;
6434 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6436 if (vinsn
->num_slots
== 1)
6437 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6439 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6442 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6446 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6448 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6450 v_copy
.slots
[slot
].opcode
=
6451 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6452 v_copy
.slots
[slot
].ntok
= 0;
6455 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6458 else if (v_copy
.num_slots
> 1)
6461 /* Try the widened version. */
6462 if (!v_copy
.slots
[slot
].keep_wide
6463 && !v_copy
.slots
[slot
].is_specific_opcode
6464 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6466 && opcode_fits_format_slot (widened
.opcode
,
6469 v_copy
.slots
[slot
] = widened
;
6474 if (fit
== v_copy
.num_slots
)
6477 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6478 vinsn
->format
= format
;
6484 if (format
== xtensa_isa_num_formats (isa
))
6485 return XTENSA_UNDEFINED
;
6491 /* Return the additional space needed in a frag
6492 for possible relaxations of any ops in a VLIW insn.
6493 Also fill out the relaxations that might be required of
6494 each tinsn in the vinsn. */
6497 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6499 bfd_boolean finish_frag
= FALSE
;
6500 int extra_space
= 0;
6503 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6505 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6506 if (!tinsn_has_symbolic_operands (tinsn
))
6508 /* A narrow instruction could be widened later to help
6509 alignment issues. */
6510 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6511 && !tinsn
->is_specific_opcode
6512 && vinsn
->num_slots
== 1)
6514 /* Difference in bytes between narrow and wide insns... */
6516 tinsn
->subtype
= RELAX_NARROW
;
6521 if (workaround_b_j_loop_end
6522 && tinsn
->opcode
== xtensa_jx_opcode
6523 && use_transform ())
6525 /* Add 2 of these. */
6526 extra_space
+= 3; /* for the nop size */
6527 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6530 /* Need to assemble it with space for the relocation. */
6531 if (xg_is_relaxable_insn (tinsn
, 0)
6532 && !tinsn
->is_specific_opcode
)
6534 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6535 int max_literal_size
=
6536 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6538 tinsn
->literal_space
= max_literal_size
;
6540 tinsn
->subtype
= RELAX_IMMED
;
6541 extra_space
+= max_size
;
6545 /* A fix record will be added for this instruction prior
6546 to relaxation, so make it end the frag. */
6551 *pfinish_frag
= finish_frag
;
6557 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6559 xtensa_isa isa
= xtensa_default_isa
;
6560 int slot
, chosen_slot
;
6562 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6563 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6564 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6566 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6567 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6569 if (slot
== chosen_slot
)
6570 vinsn
->slots
[slot
] = *tinsn
;
6573 vinsn
->slots
[slot
].opcode
=
6574 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6575 vinsn
->slots
[slot
].ntok
= 0;
6576 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6583 emit_single_op (TInsn
*orig_insn
)
6586 IStack istack
; /* put instructions into here */
6587 symbolS
*lit_sym
= NULL
;
6588 symbolS
*label_sym
= NULL
;
6590 istack_init (&istack
);
6592 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6593 Because the scheduling and bundling characteristics of movi and
6594 l32r or const16 are so different, we can do much better if we relax
6595 it prior to scheduling and bundling, rather than after. */
6596 if ((orig_insn
->opcode
== xtensa_movi_opcode
6597 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6598 && !cur_vinsn
.inside_bundle
6599 && (orig_insn
->tok
[1].X_op
== O_symbol
6600 || orig_insn
->tok
[1].X_op
== O_pltrel
)
6601 && !orig_insn
->is_specific_opcode
&& use_transform ())
6602 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6604 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6607 for (i
= 0; i
< istack
.ninsn
; i
++)
6609 TInsn
*insn
= &istack
.insn
[i
];
6610 switch (insn
->insn_type
)
6613 assert (lit_sym
== NULL
);
6614 lit_sym
= xg_assemble_literal (insn
);
6618 static int relaxed_sym_idx
= 0;
6619 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6620 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6622 assert (label_sym
== NULL
);
6623 label_sym
= symbol_find_or_make (label
);
6632 xg_resolve_literals (insn
, lit_sym
);
6634 xg_resolve_labels (insn
, label_sym
);
6636 bundle_tinsn (insn
, &v
);
6651 total_frag_text_expansion (fragS
*fragP
)
6654 int total_expansion
= 0;
6656 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6657 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6659 return total_expansion
;
6663 /* Emit a vliw instruction to the current fragment. */
6666 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6668 bfd_boolean finish_frag
;
6669 bfd_boolean is_jump
= FALSE
;
6670 bfd_boolean is_branch
= FALSE
;
6671 xtensa_isa isa
= xtensa_default_isa
;
6677 unsigned current_line
, best_linenum
;
6680 best_linenum
= UINT_MAX
;
6682 if (generating_literals
)
6684 static int reported
= 0;
6686 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6687 _("cannot assemble into a literal fragment"));
6694 if (frag_now_fix () != 0
6695 && (! frag_now
->tc_frag_data
.is_insn
6696 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6697 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6698 || (directive_state
[directive_longcalls
]
6699 != frag_now
->tc_frag_data
.use_longcalls
)
6700 || (directive_state
[directive_absolute_literals
]
6701 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6703 frag_wane (frag_now
);
6705 xtensa_set_frag_assembly_state (frag_now
);
6708 if (workaround_a0_b_retw
6709 && vinsn
->num_slots
== 1
6710 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6711 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6712 && use_transform ())
6714 has_a0_b_retw
= TRUE
;
6716 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6717 After the first assembly pass we will check all of them and
6718 add a nop if needed. */
6719 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6720 frag_var (rs_machine_dependent
, 4, 4,
6721 RELAX_ADD_NOP_IF_A0_B_RETW
,
6722 frag_now
->fr_symbol
,
6723 frag_now
->fr_offset
,
6725 xtensa_set_frag_assembly_state (frag_now
);
6726 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6727 frag_var (rs_machine_dependent
, 4, 4,
6728 RELAX_ADD_NOP_IF_A0_B_RETW
,
6729 frag_now
->fr_symbol
,
6730 frag_now
->fr_offset
,
6732 xtensa_set_frag_assembly_state (frag_now
);
6735 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6737 /* See if the instruction implies an aligned section. */
6738 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6739 record_alignment (now_seg
, 2);
6741 /* Also determine the best line number for debug info. */
6742 best_linenum
= vinsn
->slots
[i
].linenum
< best_linenum
6743 ? vinsn
->slots
[i
].linenum
: best_linenum
;
6746 /* Special cases for instructions that force an alignment... */
6747 /* None of these opcodes are bundle-able. */
6748 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6752 /* Remember the symbol that marks the end of the loop in the frag
6753 that marks the start of the loop. This way we can easily find
6754 the end of the loop at the beginning, without adding special code
6755 to mark the loop instructions themselves. */
6756 symbolS
*target_sym
= NULL
;
6757 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6758 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6760 xtensa_set_frag_assembly_state (frag_now
);
6761 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6763 max_fill
= get_text_align_max_fill_size
6764 (get_text_align_power (xtensa_fetch_width
),
6765 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6767 if (use_transform ())
6768 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6769 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6771 frag_var (rs_machine_dependent
, 0, 0,
6772 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6773 xtensa_set_frag_assembly_state (frag_now
);
6776 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6777 && !vinsn
->slots
[0].is_specific_opcode
)
6779 xtensa_mark_literal_pool_location ();
6780 xtensa_move_labels (frag_now
, 0);
6781 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6784 if (vinsn
->num_slots
== 1)
6786 if (workaround_a0_b_retw
&& use_transform ())
6787 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6788 is_register_writer (&vinsn
->slots
[0], "a", 0));
6790 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6791 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6794 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6796 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6798 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
6800 /* vinsn_to_insnbuf will produce the error. */
6801 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6803 f
= frag_more (insn_size
+ extra_space
);
6804 xtensa_set_frag_assembly_state (frag_now
);
6805 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6808 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
6809 if (vinsn
->format
== XTENSA_UNDEFINED
)
6812 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
6814 /* Temporarily set the logical line number to the one we want to appear
6815 in the debug information. */
6816 as_where (¤t_file
, ¤t_line
);
6817 new_logical_line (current_file
, best_linenum
);
6818 dwarf2_emit_insn (insn_size
+ extra_space
);
6819 new_logical_line (current_file
, current_line
);
6821 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6823 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6824 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6825 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6826 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6827 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6828 if (tinsn
->literal_space
!= 0)
6829 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6831 if (tinsn
->subtype
== RELAX_NARROW
)
6832 assert (vinsn
->num_slots
== 1);
6833 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6835 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6838 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
6839 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
6843 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6844 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6848 frag_variant (rs_machine_dependent
,
6849 extra_space
, extra_space
, RELAX_SLOTS
,
6850 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6851 xtensa_set_frag_assembly_state (frag_now
);
6854 /* Special cases for loops:
6855 close_loop_end should be inserted AFTER short_loop.
6856 Make sure that CLOSE loops are processed BEFORE short_loops
6857 when converting them. */
6859 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6860 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
6861 && !vinsn
->slots
[0].is_specific_opcode
)
6863 if (workaround_short_loop
&& use_transform ())
6865 maybe_has_short_loop
= TRUE
;
6866 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6867 frag_var (rs_machine_dependent
, 4, 4,
6868 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6869 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6870 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6871 frag_var (rs_machine_dependent
, 4, 4,
6872 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6873 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6876 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6877 loop at least 12 bytes away from another loop's end. */
6878 if (workaround_close_loop_end
&& use_transform ())
6880 maybe_has_close_loop_end
= TRUE
;
6881 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6882 frag_var (rs_machine_dependent
, 12, 12,
6883 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6884 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6888 if (use_transform ())
6892 assert (finish_frag
);
6893 frag_var (rs_machine_dependent
,
6894 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6896 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6897 xtensa_set_frag_assembly_state (frag_now
);
6899 else if (is_branch
&& do_align_targets ())
6901 assert (finish_frag
);
6902 frag_var (rs_machine_dependent
,
6903 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6904 RELAX_MAYBE_UNREACHABLE
,
6905 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6906 xtensa_set_frag_assembly_state (frag_now
);
6907 frag_var (rs_machine_dependent
,
6909 RELAX_MAYBE_DESIRE_ALIGN
,
6910 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6911 xtensa_set_frag_assembly_state (frag_now
);
6915 /* Now, if the original opcode was a call... */
6916 if (do_align_targets ()
6917 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6919 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6920 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6921 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6922 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6923 xtensa_set_frag_assembly_state (frag_now
);
6926 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6928 frag_wane (frag_now
);
6930 xtensa_set_frag_assembly_state (frag_now
);
6935 /* xtensa_end and helper functions. */
6937 static void xtensa_cleanup_align_frags (void);
6938 static void xtensa_fix_target_frags (void);
6939 static void xtensa_mark_narrow_branches (void);
6940 static void xtensa_mark_zcl_first_insns (void);
6941 static void xtensa_fix_a0_b_retw_frags (void);
6942 static void xtensa_fix_b_j_loop_end_frags (void);
6943 static void xtensa_fix_close_loop_end_frags (void);
6944 static void xtensa_fix_short_loop_frags (void);
6945 static void xtensa_sanity_check (void);
6946 static void xtensa_add_config_info (void);
6951 directive_balance ();
6952 xtensa_flush_pending_output ();
6954 past_xtensa_end
= TRUE
;
6956 xtensa_move_literals ();
6958 xtensa_reorder_segments ();
6959 xtensa_cleanup_align_frags ();
6960 xtensa_fix_target_frags ();
6961 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6962 xtensa_fix_a0_b_retw_frags ();
6963 if (workaround_b_j_loop_end
)
6964 xtensa_fix_b_j_loop_end_frags ();
6966 /* "close_loop_end" should be processed BEFORE "short_loop". */
6967 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
6968 xtensa_fix_close_loop_end_frags ();
6970 if (workaround_short_loop
&& maybe_has_short_loop
)
6971 xtensa_fix_short_loop_frags ();
6973 xtensa_mark_narrow_branches ();
6974 xtensa_mark_zcl_first_insns ();
6976 xtensa_sanity_check ();
6978 xtensa_add_config_info ();
6983 xtensa_cleanup_align_frags (void)
6988 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
6989 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
6992 /* Walk over all of the fragments in a subsection. */
6993 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
6995 if ((fragP
->fr_type
== rs_align
6996 || fragP
->fr_type
== rs_align_code
6997 || (fragP
->fr_type
== rs_machine_dependent
6998 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
6999 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7000 && fragP
->fr_fix
== 0)
7002 fragS
*next
= fragP
->fr_next
;
7005 && next
->fr_fix
== 0
7006 && next
->fr_type
== rs_machine_dependent
7007 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7010 next
= next
->fr_next
;
7013 /* If we don't widen branch targets, then they
7014 will be easier to align. */
7015 if (fragP
->tc_frag_data
.is_branch_target
7016 && fragP
->fr_opcode
== fragP
->fr_literal
7017 && fragP
->fr_type
== rs_machine_dependent
7018 && fragP
->fr_subtype
== RELAX_SLOTS
7019 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7021 if (fragP
->fr_type
== rs_machine_dependent
7022 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7023 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7029 /* Re-process all of the fragments looking to convert all of the
7030 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7031 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7032 Otherwise, convert to a .fill 0. */
7035 xtensa_fix_target_frags (void)
7040 /* When this routine is called, all of the subsections are still intact
7041 so we walk over subsections instead of sections. */
7042 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7043 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7047 /* Walk over all of the fragments in a subsection. */
7048 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7050 if (fragP
->fr_type
== rs_machine_dependent
7051 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7053 if (next_frag_is_branch_target (fragP
))
7054 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7063 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7066 xtensa_mark_narrow_branches (void)
7071 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7072 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7075 /* Walk over all of the fragments in a subsection. */
7076 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7078 if (fragP
->fr_type
== rs_machine_dependent
7079 && fragP
->fr_subtype
== RELAX_SLOTS
7080 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7084 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7085 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7087 if (vinsn
.num_slots
== 1
7088 && xtensa_opcode_is_branch (xtensa_default_isa
,
7089 vinsn
.slots
[0].opcode
) == 1
7090 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7091 && is_narrow_branch_guaranteed_in_range (fragP
,
7094 fragP
->fr_subtype
= RELAX_SLOTS
;
7095 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7096 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7104 /* A branch is typically widened only when its target is out of
7105 range. However, we would like to widen them to align a subsequent
7106 branch target when possible.
7108 Because the branch relaxation code is so convoluted, the optimal solution
7109 (combining the two cases) is difficult to get right in all circumstances.
7110 We therefore go with an "almost as good" solution, where we only
7111 use for alignment narrow branches that definitely will not expand to a
7112 jump and a branch. These functions find and mark these cases. */
7114 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7115 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7116 We start counting beginning with the frag after the 2-byte branch, so the
7117 maximum offset is (4 - 2) + 63 = 65. */
7118 #define MAX_IMMED6 65
7120 static offsetT
unrelaxed_frag_max_size (fragS
*);
7123 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7125 const expressionS
*expr
= &tinsn
->tok
[1];
7126 symbolS
*symbolP
= expr
->X_add_symbol
;
7127 offsetT max_distance
= expr
->X_add_number
;
7130 if (expr
->X_op
!= O_symbol
)
7133 target_frag
= symbol_get_frag (symbolP
);
7135 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7136 if (is_branch_jmp_to_next (tinsn
, fragP
))
7139 /* The branch doesn't branch over it's own frag,
7140 but over the subsequent ones. */
7141 fragP
= fragP
->fr_next
;
7142 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7144 max_distance
+= unrelaxed_frag_max_size (fragP
);
7145 fragP
= fragP
->fr_next
;
7147 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7154 xtensa_mark_zcl_first_insns (void)
7159 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7160 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7163 /* Walk over all of the fragments in a subsection. */
7164 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7166 if (fragP
->fr_type
== rs_machine_dependent
7167 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7168 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7170 /* Find the loop frag. */
7171 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7172 /* Find the first insn frag. */
7173 targ_frag
= next_non_empty_frag (targ_frag
);
7175 /* Of course, sometimes (mostly for toy test cases) a
7176 zero-cost loop instruction is the last in a section. */
7179 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7180 /* Do not widen a frag that is the first instruction of a
7181 zero-cost loop. It makes that loop harder to align. */
7182 if (targ_frag
->fr_type
== rs_machine_dependent
7183 && targ_frag
->fr_subtype
== RELAX_SLOTS
7184 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7187 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7188 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7191 frag_wane (targ_frag
);
7192 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7196 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7204 /* Re-process all of the fragments looking to convert all of the
7205 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7206 conditional branch or a retw/retw.n, convert this frag to one that
7207 will generate a NOP. In any case close it off with a .fill 0. */
7209 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7212 xtensa_fix_a0_b_retw_frags (void)
7217 /* When this routine is called, all of the subsections are still intact
7218 so we walk over subsections instead of sections. */
7219 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7220 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7224 /* Walk over all of the fragments in a subsection. */
7225 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7227 if (fragP
->fr_type
== rs_machine_dependent
7228 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7230 if (next_instrs_are_b_retw (fragP
))
7232 if (fragP
->tc_frag_data
.is_no_transform
)
7233 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7235 relax_frag_add_nop (fragP
);
7245 next_instrs_are_b_retw (fragS
*fragP
)
7247 xtensa_opcode opcode
;
7249 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7250 static xtensa_insnbuf insnbuf
= NULL
;
7251 static xtensa_insnbuf slotbuf
= NULL
;
7252 xtensa_isa isa
= xtensa_default_isa
;
7255 bfd_boolean branch_seen
= FALSE
;
7259 insnbuf
= xtensa_insnbuf_alloc (isa
);
7260 slotbuf
= xtensa_insnbuf_alloc (isa
);
7263 if (next_fragP
== NULL
)
7266 /* Check for the conditional branch. */
7267 xtensa_insnbuf_from_chars
7268 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7269 fmt
= xtensa_format_decode (isa
, insnbuf
);
7270 if (fmt
== XTENSA_UNDEFINED
)
7273 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7275 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7276 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7278 branch_seen
= (branch_seen
7279 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7285 offset
+= xtensa_format_length (isa
, fmt
);
7286 if (offset
== next_fragP
->fr_fix
)
7288 next_fragP
= next_non_empty_frag (next_fragP
);
7292 if (next_fragP
== NULL
)
7295 /* Check for the retw/retw.n. */
7296 xtensa_insnbuf_from_chars
7297 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7298 fmt
= xtensa_format_decode (isa
, insnbuf
);
7300 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7301 have no problems. */
7302 if (fmt
== XTENSA_UNDEFINED
7303 || xtensa_format_num_slots (isa
, fmt
) != 1)
7306 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7307 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7309 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7316 /* Re-process all of the fragments looking to convert all of the
7317 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7318 loop end label, convert this frag to one that will generate a NOP.
7319 In any case close it off with a .fill 0. */
7321 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7324 xtensa_fix_b_j_loop_end_frags (void)
7329 /* When this routine is called, all of the subsections are still intact
7330 so we walk over subsections instead of sections. */
7331 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7332 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7336 /* Walk over all of the fragments in a subsection. */
7337 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7339 if (fragP
->fr_type
== rs_machine_dependent
7340 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7342 if (next_instr_is_loop_end (fragP
))
7344 if (fragP
->tc_frag_data
.is_no_transform
)
7345 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7347 relax_frag_add_nop (fragP
);
7357 next_instr_is_loop_end (fragS
*fragP
)
7359 const fragS
*next_fragP
;
7361 if (next_frag_is_loop_target (fragP
))
7364 next_fragP
= next_non_empty_frag (fragP
);
7365 if (next_fragP
== NULL
)
7368 if (!next_frag_is_loop_target (next_fragP
))
7371 /* If the size is >= 3 then there is more than one instruction here.
7372 The hardware bug will not fire. */
7373 if (next_fragP
->fr_fix
> 3)
7380 /* Re-process all of the fragments looking to convert all of the
7381 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7382 not MY loop's loop end within 12 bytes, add enough nops here to
7383 make it at least 12 bytes away. In any case close it off with a
7386 static offsetT min_bytes_to_other_loop_end
7387 (fragS
*, fragS
*, offsetT
);
7390 xtensa_fix_close_loop_end_frags (void)
7395 /* When this routine is called, all of the subsections are still intact
7396 so we walk over subsections instead of sections. */
7397 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7398 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7402 fragS
*current_target
= NULL
;
7404 /* Walk over all of the fragments in a subsection. */
7405 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7407 if (fragP
->fr_type
== rs_machine_dependent
7408 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7409 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7410 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7413 && fragP
->fr_type
== rs_machine_dependent
7414 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7417 int bytes_added
= 0;
7419 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7420 /* Max out at 12. */
7421 min_bytes
= min_bytes_to_other_loop_end
7422 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7424 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7426 if (fragP
->tc_frag_data
.is_no_transform
)
7427 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7430 while (min_bytes
+ bytes_added
7431 < REQUIRED_LOOP_DIVIDING_BYTES
)
7435 if (fragP
->fr_var
< length
)
7436 as_fatal (_("fr_var %lu < length %d"),
7437 (long) fragP
->fr_var
, length
);
7440 assemble_nop (length
,
7441 fragP
->fr_literal
+ fragP
->fr_fix
);
7442 fragP
->fr_fix
+= length
;
7443 fragP
->fr_var
-= length
;
7445 bytes_added
+= length
;
7451 assert (fragP
->fr_type
!= rs_machine_dependent
7452 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7458 static offsetT
unrelaxed_frag_min_size (fragS
*);
7461 min_bytes_to_other_loop_end (fragS
*fragP
,
7462 fragS
*current_target
,
7466 fragS
*current_fragP
;
7468 for (current_fragP
= fragP
;
7470 current_fragP
= current_fragP
->fr_next
)
7472 if (current_fragP
->tc_frag_data
.is_loop_target
7473 && current_fragP
!= current_target
)
7476 offset
+= unrelaxed_frag_min_size (current_fragP
);
7478 if (offset
>= max_size
)
7486 unrelaxed_frag_min_size (fragS
*fragP
)
7488 offsetT size
= fragP
->fr_fix
;
7490 /* Add fill size. */
7491 if (fragP
->fr_type
== rs_fill
)
7492 size
+= fragP
->fr_offset
;
7499 unrelaxed_frag_max_size (fragS
*fragP
)
7501 offsetT size
= fragP
->fr_fix
;
7502 switch (fragP
->fr_type
)
7505 /* Empty frags created by the obstack allocation scheme
7506 end up with type 0. */
7511 size
+= fragP
->fr_offset
;
7519 /* No further adjustments needed. */
7521 case rs_machine_dependent
:
7522 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7523 size
+= fragP
->fr_var
;
7526 /* We had darn well better know how big it is. */
7535 /* Re-process all of the fragments looking to convert all
7536 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7539 1) the instruction size count to the loop end label
7540 is too short (<= 2 instructions),
7541 2) loop has a jump or branch in it
7544 1) workaround_all_short_loops is TRUE
7545 2) The generating loop was a 'loopgtz' or 'loopnez'
7546 3) the instruction size count to the loop end label is too short
7548 then convert this frag (and maybe the next one) to generate a NOP.
7549 In any case close it off with a .fill 0. */
7551 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7552 static bfd_boolean
branch_before_loop_end (fragS
*);
7555 xtensa_fix_short_loop_frags (void)
7560 /* When this routine is called, all of the subsections are still intact
7561 so we walk over subsections instead of sections. */
7562 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7563 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7566 fragS
*current_target
= NULL
;
7567 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7569 /* Walk over all of the fragments in a subsection. */
7570 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7572 if (fragP
->fr_type
== rs_machine_dependent
7573 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7574 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7577 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7578 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7579 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7580 current_opcode
= t_insn
.opcode
;
7581 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7582 current_opcode
) == 1);
7585 if (fragP
->fr_type
== rs_machine_dependent
7586 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7588 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7589 && (branch_before_loop_end (fragP
->fr_next
)
7590 || (workaround_all_short_loops
7591 && current_opcode
!= XTENSA_UNDEFINED
7592 && current_opcode
!= xtensa_loop_opcode
)))
7594 if (fragP
->tc_frag_data
.is_no_transform
)
7595 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7597 relax_frag_add_nop (fragP
);
7606 static int unrelaxed_frag_min_insn_count (fragS
*);
7609 count_insns_to_loop_end (fragS
*base_fragP
,
7610 bfd_boolean count_relax_add
,
7613 fragS
*fragP
= NULL
;
7618 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7620 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7621 if (insn_count
>= max_count
)
7624 if (count_relax_add
)
7626 if (fragP
->fr_type
== rs_machine_dependent
7627 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7629 /* In order to add the appropriate number of
7630 NOPs, we count an instruction for downstream
7633 if (insn_count
>= max_count
)
7643 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7645 xtensa_isa isa
= xtensa_default_isa
;
7646 static xtensa_insnbuf insnbuf
= NULL
;
7650 if (!fragP
->tc_frag_data
.is_insn
)
7654 insnbuf
= xtensa_insnbuf_alloc (isa
);
7656 /* Decode the fixed instructions. */
7657 while (offset
< fragP
->fr_fix
)
7661 xtensa_insnbuf_from_chars
7662 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7663 fmt
= xtensa_format_decode (isa
, insnbuf
);
7665 if (fmt
== XTENSA_UNDEFINED
)
7667 as_fatal (_("undecodable instruction in instruction frag"));
7670 offset
+= xtensa_format_length (isa
, fmt
);
7678 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7681 branch_before_loop_end (fragS
*base_fragP
)
7685 for (fragP
= base_fragP
;
7686 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7687 fragP
= fragP
->fr_next
)
7689 if (unrelaxed_frag_has_b_j (fragP
))
7697 unrelaxed_frag_has_b_j (fragS
*fragP
)
7699 static xtensa_insnbuf insnbuf
= NULL
;
7700 xtensa_isa isa
= xtensa_default_isa
;
7703 if (!fragP
->tc_frag_data
.is_insn
)
7707 insnbuf
= xtensa_insnbuf_alloc (isa
);
7709 /* Decode the fixed instructions. */
7710 while (offset
< fragP
->fr_fix
)
7715 xtensa_insnbuf_from_chars
7716 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7717 fmt
= xtensa_format_decode (isa
, insnbuf
);
7718 if (fmt
== XTENSA_UNDEFINED
)
7721 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7723 xtensa_opcode opcode
=
7724 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7725 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7726 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7729 offset
+= xtensa_format_length (isa
, fmt
);
7735 /* Checks to be made after initial assembly but before relaxation. */
7737 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7738 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7741 xtensa_sanity_check (void)
7748 as_where (&file_name
, &line
);
7749 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7750 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7754 /* Walk over all of the fragments in a subsection. */
7755 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7757 if (fragP
->fr_type
== rs_machine_dependent
7758 && fragP
->fr_subtype
== RELAX_SLOTS
7759 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7761 static xtensa_insnbuf insnbuf
= NULL
;
7764 if (fragP
->fr_opcode
!= NULL
)
7767 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7768 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7769 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7771 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7772 t_insn
.opcode
) == 1)
7774 if (is_empty_loop (&t_insn
, fragP
))
7776 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7777 as_bad (_("invalid empty loop"));
7779 if (!is_local_forward_loop (&t_insn
, fragP
))
7781 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7782 as_bad (_("loop target does not follow "
7783 "loop instruction in section"));
7790 new_logical_line (file_name
, line
);
7794 #define LOOP_IMMED_OPN 1
7796 /* Return TRUE if the loop target is the next non-zero fragment. */
7799 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7801 const expressionS
*expr
;
7805 if (insn
->insn_type
!= ITYPE_INSN
)
7808 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7811 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7814 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7816 if (expr
->X_op
!= O_symbol
)
7819 symbolP
= expr
->X_add_symbol
;
7823 if (symbol_get_frag (symbolP
) == NULL
)
7826 if (S_GET_VALUE (symbolP
) != 0)
7829 /* Walk through the zero-size fragments from this one. If we find
7830 the target fragment, then this is a zero-size loop. */
7832 for (next_fragP
= fragP
->fr_next
;
7834 next_fragP
= next_fragP
->fr_next
)
7836 if (next_fragP
== symbol_get_frag (symbolP
))
7838 if (next_fragP
->fr_fix
!= 0)
7846 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7848 const expressionS
*expr
;
7852 if (insn
->insn_type
!= ITYPE_INSN
)
7855 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7858 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7861 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7863 if (expr
->X_op
!= O_symbol
)
7866 symbolP
= expr
->X_add_symbol
;
7870 if (symbol_get_frag (symbolP
) == NULL
)
7873 /* Walk through fragments until we find the target.
7874 If we do not find the target, then this is an invalid loop. */
7876 for (next_fragP
= fragP
->fr_next
;
7878 next_fragP
= next_fragP
->fr_next
)
7880 if (next_fragP
== symbol_get_frag (symbolP
))
7888 #define XTINFO_NAME "Xtensa_Info"
7889 #define XTINFO_NAMESZ 12
7890 #define XTINFO_TYPE 1
7893 xtensa_add_config_info (void)
7899 info_sec
= subseg_new (".xtensa.info", 0);
7900 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
7902 data
= xmalloc (100);
7903 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
7904 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
7905 sz
= strlen (data
) + 1;
7907 /* Add enough null terminators to pad to a word boundary. */
7910 while ((sz
& 3) != 0);
7912 /* Follow the standard note section layout:
7913 First write the length of the name string. */
7915 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
7917 /* Next comes the length of the "descriptor", i.e., the actual data. */
7919 md_number_to_chars (p
, (valueT
) sz
, 4);
7921 /* Write the note type. */
7923 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
7925 /* Write the name field. */
7926 p
= frag_more (XTINFO_NAMESZ
);
7927 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
7929 /* Finally, write the descriptor. */
7931 memcpy (p
, data
, sz
);
7937 /* Alignment Functions. */
7940 get_text_align_power (unsigned target_size
)
7942 if (target_size
<= 4)
7944 assert (target_size
== 8);
7950 get_text_align_max_fill_size (int align_pow
,
7951 bfd_boolean use_nops
,
7952 bfd_boolean use_no_density
)
7955 return (1 << align_pow
);
7957 return 3 * (1 << align_pow
);
7959 return 1 + (1 << align_pow
);
7963 /* Calculate the minimum bytes of fill needed at "address" to align a
7964 target instruction of size "target_size" so that it does not cross a
7965 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
7966 the fill can be an arbitrary number of bytes. Otherwise, the space must
7967 be filled by NOP instructions. */
7970 get_text_align_fill_size (addressT address
,
7973 bfd_boolean use_nops
,
7974 bfd_boolean use_no_density
)
7976 addressT alignment
, fill
, fill_limit
, fill_step
;
7977 bfd_boolean skip_one
= FALSE
;
7979 alignment
= (1 << align_pow
);
7980 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
7984 fill_limit
= alignment
;
7987 else if (!use_no_density
)
7989 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
7990 fill_limit
= alignment
* 2;
7996 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
7997 fill_limit
= alignment
* 3;
8001 /* Try all fill sizes until finding one that works. */
8002 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8004 if (skip_one
&& fill
== 1)
8006 if ((address
+ fill
) >> align_pow
8007 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8016 branch_align_power (segT sec
)
8018 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8019 is aligned to at least an 8-byte boundary, then a branch target need
8020 only fit within an 8-byte aligned block of memory to avoid a stall.
8021 Otherwise, try to fit branch targets within 4-byte aligned blocks
8022 (which may be insufficient, e.g., if the section has no alignment, but
8023 it's good enough). */
8024 if (xtensa_fetch_width
== 8)
8026 if (get_recorded_alignment (sec
) >= 3)
8030 assert (xtensa_fetch_width
== 4);
8036 /* This will assert if it is not possible. */
8039 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8045 assert (fill_size
% 3 == 0);
8046 return (fill_size
/ 3);
8049 assert (fill_size
!= 1); /* Bad argument. */
8051 while (fill_size
> 1)
8054 if (fill_size
== 2 || fill_size
== 4)
8056 fill_size
-= insn_size
;
8059 assert (fill_size
!= 1); /* Bad algorithm. */
8065 get_text_align_nth_nop_size (offsetT fill_size
,
8067 bfd_boolean use_no_density
)
8074 assert (fill_size
!= 1); /* Bad argument. */
8076 while (fill_size
> 1)
8079 if (fill_size
== 2 || fill_size
== 4)
8081 fill_size
-= insn_size
;
8091 /* For the given fragment, find the appropriate address
8092 for it to begin at if we are using NOPs to align it. */
8095 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8097 /* The rule is: get next fragment's FIRST instruction. Find
8098 the smallest number of bytes that need to be added to
8099 ensure that the next fragment's FIRST instruction will fit
8102 E.G., 2 bytes : 0, 1, 2 mod 4
8105 If the FIRST instruction MIGHT be relaxed,
8106 assume that it will become a 3-byte instruction.
8108 Note again here that LOOP instructions are not bundleable,
8109 and this relaxation only applies to LOOP opcodes. */
8112 int first_insn_size
;
8114 addressT pre_opcode_bytes
;
8117 xtensa_opcode opcode
;
8118 bfd_boolean is_loop
;
8120 assert (fragP
->fr_type
== rs_machine_dependent
);
8121 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8123 /* Find the loop frag. */
8124 first_insn
= next_non_empty_frag (fragP
);
8125 /* Now find the first insn frag. */
8126 first_insn
= next_non_empty_frag (first_insn
);
8128 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8130 loop_insn_size
= xg_get_single_size (opcode
);
8132 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8133 pre_opcode_bytes
+= loop_insn_size
;
8135 /* For loops, the alignment depends on the size of the
8136 instruction following the loop, not the LOOP instruction. */
8138 if (first_insn
== NULL
)
8139 first_insn_size
= xtensa_fetch_width
;
8141 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8143 /* If it was 8, then we'll need a larger alignment for the section. */
8144 align_power
= get_text_align_power (first_insn_size
);
8145 record_alignment (now_seg
, align_power
);
8147 fill_size
= get_text_align_fill_size
8148 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8149 fragP
->tc_frag_data
.is_no_density
);
8151 return address
+ fill_size
;
8155 /* 3 mechanisms for relaxing an alignment:
8157 Align to a power of 2.
8158 Align so the next fragment's instruction does not cross a word boundary.
8159 Align the current instruction so that if the next instruction
8160 were 3 bytes, it would not cross a word boundary.
8164 zeros - This is easy; always insert zeros.
8165 nops - 3-byte and 2-byte instructions
8169 >=5 : 3-byte instruction + fn (n-3)
8170 widening - widen previous instructions. */
8173 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8175 addressT target_address
, loop_insn_offset
;
8177 xtensa_opcode loop_opcode
;
8178 bfd_boolean is_loop
;
8181 offsetT branch_align
;
8183 assert (fragP
->fr_type
== rs_machine_dependent
);
8184 switch (fragP
->fr_subtype
)
8186 case RELAX_DESIRE_ALIGN
:
8187 target_size
= next_frag_format_size (fragP
);
8188 if (target_size
== XTENSA_UNDEFINED
)
8190 align_power
= branch_align_power (now_seg
);
8191 branch_align
= 1 << align_power
;
8192 /* Don't count on the section alignment being as large as the target. */
8193 if (target_size
> branch_align
)
8194 target_size
= branch_align
;
8195 opt_diff
= get_text_align_fill_size (address
, align_power
,
8196 target_size
, FALSE
, FALSE
);
8198 *max_diff
= (opt_diff
+ branch_align
8199 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8200 assert (*max_diff
>= opt_diff
);
8203 case RELAX_ALIGN_NEXT_OPCODE
:
8204 target_size
= get_loop_align_size (next_frag_format_size (fragP
));
8205 loop_insn_offset
= 0;
8206 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8209 /* If the loop has been expanded then the LOOP instruction
8210 could be at an offset from this fragment. */
8211 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8213 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8215 /* In an ideal world, which is what we are shooting for here,
8216 we wouldn't need to use any NOPs immediately prior to the
8217 LOOP instruction. If this approach fails, relax_frag_loop_align
8218 will call get_noop_aligned_address. */
8220 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8221 align_power
= get_text_align_power (target_size
),
8222 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8223 target_size
, FALSE
, FALSE
);
8225 *max_diff
= xtensa_fetch_width
8226 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8227 - target_size
+ opt_diff
;
8228 assert (*max_diff
>= opt_diff
);
8239 /* md_relax_frag Hook and Helper Functions. */
8241 static long relax_frag_loop_align (fragS
*, long);
8242 static long relax_frag_for_align (fragS
*, long);
8243 static long relax_frag_immed
8244 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8247 /* Return the number of bytes added to this fragment, given that the
8248 input has been stretched already by "stretch". */
8251 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8253 xtensa_isa isa
= xtensa_default_isa
;
8254 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8255 long new_stretch
= 0;
8259 static xtensa_insnbuf vbuf
= NULL
;
8260 int slot
, num_slots
;
8263 as_where (&file_name
, &line
);
8264 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8266 fragP
->tc_frag_data
.unreported_expansion
= 0;
8268 switch (fragP
->fr_subtype
)
8270 case RELAX_ALIGN_NEXT_OPCODE
:
8271 /* Always convert. */
8272 if (fragP
->tc_frag_data
.relax_seen
)
8273 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8276 case RELAX_LOOP_END
:
8280 case RELAX_LOOP_END_ADD_NOP
:
8281 /* Add a NOP and switch to .fill 0. */
8282 new_stretch
= relax_frag_add_nop (fragP
);
8286 case RELAX_DESIRE_ALIGN
:
8287 /* Do nothing. The narrowing before this frag will either align
8292 case RELAX_LITERAL_FINAL
:
8295 case RELAX_LITERAL_NR
:
8297 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8298 assert (unreported
== lit_size
);
8299 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8300 fragP
->fr_var
-= lit_size
;
8301 fragP
->fr_fix
+= lit_size
;
8307 vbuf
= xtensa_insnbuf_alloc (isa
);
8309 xtensa_insnbuf_from_chars
8310 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8311 fmt
= xtensa_format_decode (isa
, vbuf
);
8312 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8314 for (slot
= 0; slot
< num_slots
; slot
++)
8316 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8319 if (fragP
->tc_frag_data
.relax_seen
)
8320 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8324 case RELAX_IMMED_STEP1
:
8325 case RELAX_IMMED_STEP2
:
8326 /* Place the immediate. */
8327 new_stretch
+= relax_frag_immed
8328 (now_seg
, fragP
, stretch
,
8329 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8330 fmt
, slot
, stretched_p
, FALSE
);
8334 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8340 case RELAX_LITERAL_POOL_BEGIN
:
8341 case RELAX_LITERAL_POOL_END
:
8342 case RELAX_MAYBE_UNREACHABLE
:
8343 case RELAX_MAYBE_DESIRE_ALIGN
:
8344 /* No relaxation required. */
8347 case RELAX_FILL_NOP
:
8348 case RELAX_UNREACHABLE
:
8349 if (fragP
->tc_frag_data
.relax_seen
)
8350 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8354 as_bad (_("bad relaxation state"));
8357 /* Tell gas we need another relaxation pass. */
8358 if (! fragP
->tc_frag_data
.relax_seen
)
8360 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8364 new_logical_line (file_name
, line
);
8370 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8372 addressT old_address
, old_next_address
, old_size
;
8373 addressT new_address
, new_next_address
, new_size
;
8376 /* All the frags with relax_frag_for_alignment prior to this one in the
8377 section have been done, hopefully eliminating the need for a NOP here.
8378 But, this will put it in if necessary. */
8380 /* Calculate the old address of this fragment and the next fragment. */
8381 old_address
= fragP
->fr_address
- stretch
;
8382 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8383 fragP
->tc_frag_data
.text_expansion
[0]);
8384 old_size
= old_next_address
- old_address
;
8386 /* Calculate the new address of this fragment and the next fragment. */
8387 new_address
= fragP
->fr_address
;
8389 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8390 new_size
= new_next_address
- new_address
;
8392 growth
= new_size
- old_size
;
8394 /* Fix up the text_expansion field and return the new growth. */
8395 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8400 /* Add a NOP instruction. */
8403 relax_frag_add_nop (fragS
*fragP
)
8405 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8406 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8407 assemble_nop (length
, nop_buf
);
8408 fragP
->tc_frag_data
.is_insn
= TRUE
;
8410 if (fragP
->fr_var
< length
)
8412 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8416 fragP
->fr_fix
+= length
;
8417 fragP
->fr_var
-= length
;
8422 static long future_alignment_required (fragS
*, long);
8425 relax_frag_for_align (fragS
*fragP
, long stretch
)
8427 /* Overview of the relaxation procedure for alignment:
8428 We can widen with NOPs or by widening instructions or by filling
8429 bytes after jump instructions. Find the opportune places and widen
8430 them if necessary. */
8435 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8436 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8437 || (fragP
->fr_subtype
== RELAX_SLOTS
8438 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8440 stretch_me
= future_alignment_required (fragP
, stretch
);
8441 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8447 /* We expanded on a previous pass. Can we shrink now? */
8448 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8449 if (shrink
<= stretch
&& stretch
> 0)
8451 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8457 /* Below here, diff > 0. */
8458 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8464 /* Return the address of the next frag that should be aligned.
8466 By "address" we mean the address it _would_ be at if there
8467 is no action taken to align it between here and the target frag.
8468 In other words, if no narrows and no fill nops are used between
8469 here and the frag to align, _even_if_ some of the frags we use
8470 to align targets have already expanded on a previous relaxation
8473 Also, count each frag that may be used to help align the target.
8475 Return 0 if there are no frags left in the chain that need to be
8479 find_address_of_next_align_frag (fragS
**fragPP
,
8483 bfd_boolean
*paddable
)
8485 fragS
*fragP
= *fragPP
;
8486 addressT address
= fragP
->fr_address
;
8488 /* Do not reset the counts to 0. */
8492 /* Limit this to a small search. */
8493 if (*widens
>= (int) xtensa_fetch_width
)
8498 address
+= fragP
->fr_fix
;
8500 if (fragP
->fr_type
== rs_fill
)
8501 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8502 else if (fragP
->fr_type
== rs_machine_dependent
)
8504 switch (fragP
->fr_subtype
)
8506 case RELAX_UNREACHABLE
:
8510 case RELAX_FILL_NOP
:
8512 if (!fragP
->tc_frag_data
.is_no_density
)
8517 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8522 address
+= total_frag_text_expansion (fragP
);;
8526 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8529 case RELAX_ALIGN_NEXT_OPCODE
:
8530 case RELAX_DESIRE_ALIGN
:
8534 case RELAX_MAYBE_UNREACHABLE
:
8535 case RELAX_MAYBE_DESIRE_ALIGN
:
8540 /* Just punt if we don't know the type. */
8547 /* Just punt if we don't know the type. */
8551 fragP
= fragP
->fr_next
;
8559 static long bytes_to_stretch (fragS
*, int, int, int, int);
8562 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8564 fragS
*this_frag
= fragP
;
8568 int narrow_nops
= 0;
8569 bfd_boolean paddable
= FALSE
;
8570 offsetT local_opt_diff
;
8573 int stretch_amount
= 0;
8574 int local_stretch_amount
;
8575 int global_stretch_amount
;
8577 address
= find_address_of_next_align_frag
8578 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8582 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8583 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8585 frag_wane (this_frag
);
8589 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8590 opt_diff
= local_opt_diff
;
8591 assert (opt_diff
>= 0);
8592 assert (max_diff
>= opt_diff
);
8597 fragP
= fragP
->fr_next
;
8599 while (fragP
&& opt_diff
< max_diff
&& address
)
8601 /* We only use these to determine if we can exit early
8602 because there will be plenty of ways to align future
8604 int glob_widens
= 0;
8607 bfd_boolean glob_pad
= 0;
8608 address
= find_address_of_next_align_frag
8609 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8610 /* If there is a padable portion, then skip. */
8611 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8616 offsetT next_m_diff
;
8617 offsetT next_o_diff
;
8619 /* Downrange frags haven't had stretch added to them yet. */
8622 /* The address also includes any text expansion from this
8623 frag in a previous pass, but we don't want that. */
8624 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8626 /* Assume we are going to move at least opt_diff. In
8627 reality, we might not be able to, but assuming that
8628 we will helps catch cases where moving opt_diff pushes
8629 the next target from aligned to unaligned. */
8630 address
+= opt_diff
;
8632 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8634 /* Now cleanup for the adjustments to address. */
8635 next_o_diff
+= opt_diff
;
8636 next_m_diff
+= opt_diff
;
8637 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8638 opt_diff
= next_o_diff
;
8639 if (next_m_diff
< max_diff
)
8640 max_diff
= next_m_diff
;
8641 fragP
= fragP
->fr_next
;
8645 /* If there are enough wideners in between, do it. */
8648 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8650 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8655 local_stretch_amount
8656 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8657 num_widens
, local_opt_diff
);
8658 global_stretch_amount
8659 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8660 num_widens
, opt_diff
);
8661 /* If the condition below is true, then the frag couldn't
8662 stretch the correct amount for the global case, so we just
8663 optimize locally. We'll rely on the subsequent frags to get
8664 the correct alignment in the global case. */
8665 if (global_stretch_amount
< local_stretch_amount
)
8666 stretch_amount
= local_stretch_amount
;
8668 stretch_amount
= global_stretch_amount
;
8670 if (this_frag
->fr_subtype
== RELAX_SLOTS
8671 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8672 assert (stretch_amount
<= 1);
8673 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8675 if (this_frag
->tc_frag_data
.is_no_density
)
8676 assert (stretch_amount
== 3 || stretch_amount
== 0);
8678 assert (stretch_amount
<= 3);
8681 return stretch_amount
;
8685 /* The idea: widen everything you can to get a target or loop aligned,
8686 then start using NOPs.
8688 When we must have a NOP, here is a table of how we decide
8689 (so you don't have to fight through the control flow below):
8691 wide_nops = the number of wide NOPs available for aligning
8692 narrow_nops = the number of narrow NOPs available for aligning
8693 (a subset of wide_nops)
8694 widens = the number of narrow instructions that should be widened
8701 b 0 1 1 (case 3a makes this case unnecessary)
8704 c 0 1 2 (case 4a makes this case unnecessary)
8707 c 0 2 1 (case 5b makes this case unnecessary)
8710 c 0 1 4 (case 6b makes this case unnecessary)
8711 d 1 1 1 (case 6a makes this case unnecessary)
8712 e 0 2 2 (case 6a makes this case unnecessary)
8713 f 0 3 0 (case 6a makes this case unnecessary)
8716 c 1 1 2 (case 7b makes this case unnecessary)
8717 d 0 1 5 (case 7a makes this case unnecessary)
8718 e 0 2 3 (case 7b makes this case unnecessary)
8719 f 0 3 1 (case 7b makes this case unnecessary)
8720 g 1 2 1 (case 7b makes this case unnecessary)
8724 bytes_to_stretch (fragS
*this_frag
,
8730 int bytes_short
= desired_diff
- num_widens
;
8732 assert (desired_diff
>= 0 && desired_diff
< 8);
8733 if (desired_diff
== 0)
8736 assert (wide_nops
> 0 || num_widens
> 0);
8738 /* Always prefer widening to NOP-filling. */
8739 if (bytes_short
< 0)
8741 /* There are enough RELAX_NARROW frags after this one
8742 to align the target without widening this frag in any way. */
8746 if (bytes_short
== 0)
8748 /* Widen every narrow between here and the align target
8749 and the align target will be properly aligned. */
8750 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8756 /* From here we will need at least one NOP to get an alignment.
8757 However, we may not be able to align at all, in which case,
8759 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8761 switch (desired_diff
)
8766 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8767 return 2; /* case 2 */
8773 return 3; /* case 3a */
8775 if (num_widens
>= 1 && wide_nops
== 1)
8776 return 3; /* case 4a */
8777 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8778 return 2; /* case 4b */
8781 if (num_widens
>= 2 && wide_nops
== 1)
8782 return 3; /* case 5a */
8783 /* We will need two nops. Are there enough nops
8784 between here and the align target? */
8785 if (wide_nops
< 2 || narrow_nops
== 0)
8787 /* Are there other nops closer that can serve instead? */
8788 if (wide_nops
> 2 && narrow_nops
> 1)
8790 /* Take the density one first, because there might not be
8791 another density one available. */
8792 if (!this_frag
->tc_frag_data
.is_no_density
)
8793 return 2; /* case 5b narrow */
8795 return 3; /* case 5b wide */
8799 return 3; /* case 6a */
8800 else if (num_widens
>= 3 && wide_nops
== 1)
8801 return 3; /* case 6b */
8804 if (wide_nops
== 1 && num_widens
>= 4)
8805 return 3; /* case 7a */
8806 else if (wide_nops
== 2 && num_widens
>= 1)
8807 return 3; /* case 7b */
8815 /* We will need a NOP no matter what, but should we widen
8816 this instruction to help?
8818 This is a RELAX_NARROW frag. */
8819 switch (desired_diff
)
8828 if (wide_nops
>= 1 && num_widens
== 1)
8829 return 1; /* case 4a */
8832 if (wide_nops
>= 1 && num_widens
== 2)
8833 return 1; /* case 5a */
8837 return 0; /* case 6a */
8838 else if (wide_nops
>= 1 && num_widens
== 3)
8839 return 1; /* case 6b */
8842 if (wide_nops
>= 1 && num_widens
== 4)
8843 return 1; /* case 7a */
8844 else if (wide_nops
>= 2 && num_widens
== 1)
8845 return 1; /* case 7b */
8858 relax_frag_immed (segT segP
,
8865 bfd_boolean estimate_only
)
8869 bfd_boolean negatable_branch
= FALSE
;
8870 bfd_boolean branch_jmp_to_next
= FALSE
;
8871 bfd_boolean wide_insn
= FALSE
;
8872 xtensa_isa isa
= xtensa_default_isa
;
8874 offsetT frag_offset
;
8877 int num_text_bytes
, num_literal_bytes
;
8878 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8880 assert (fragP
->fr_opcode
!= NULL
);
8882 xg_clear_vinsn (&cur_vinsn
);
8883 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
8884 if (cur_vinsn
.num_slots
> 1)
8887 tinsn
= cur_vinsn
.slots
[slot
];
8888 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8890 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
8893 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8894 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8896 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8898 old_size
= xtensa_format_length (isa
, fmt
);
8900 /* Special case: replace a branch to the next instruction with a NOP.
8901 This is required to work around a hardware bug in T1040.0 and also
8902 serves as an optimization. */
8904 if (branch_jmp_to_next
8905 && ((old_size
== 2) || (old_size
== 3))
8906 && !next_frag_is_loop_target (fragP
))
8909 /* Here is the fun stuff: Get the immediate field from this
8910 instruction. If it fits, we are done. If not, find the next
8911 instruction sequence that fits. */
8913 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8914 istack_init (&istack
);
8915 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8916 min_steps
, stretch
);
8917 if (num_steps
< min_steps
)
8919 as_fatal (_("internal error: relaxation failed"));
8923 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8925 as_fatal (_("internal error: relaxation requires too many steps"));
8929 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8931 /* Figure out the number of bytes needed. */
8933 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8935 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8937 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8939 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8942 num_text_bytes
+= old_size
;
8943 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8944 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8946 total_text_diff
= num_text_bytes
- old_size
;
8947 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8949 /* It MUST get larger. If not, we could get an infinite loop. */
8950 assert (num_text_bytes
>= 0);
8951 assert (literal_diff
>= 0);
8952 assert (total_text_diff
>= 0);
8954 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8955 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8956 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8957 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8959 /* Find the associated expandable literal for this. */
8960 if (literal_diff
!= 0)
8962 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8965 assert (literal_diff
== 4);
8966 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8968 /* We expect that the literal section state has NOT been
8970 assert (lit_fragP
->fr_type
== rs_machine_dependent
8971 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8972 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8974 /* We need to mark this section for another iteration
8980 if (negatable_branch
&& istack
.ninsn
> 1)
8981 update_next_frag_state (fragP
);
8983 return this_text_diff
;
8987 /* md_convert_frag Hook and Helper Functions. */
8989 static void convert_frag_align_next_opcode (fragS
*);
8990 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
8991 static void convert_frag_fill_nop (fragS
*);
8992 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
8995 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
8997 static xtensa_insnbuf vbuf
= NULL
;
8998 xtensa_isa isa
= xtensa_default_isa
;
9005 as_where (&file_name
, &line
);
9006 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9008 switch (fragp
->fr_subtype
)
9010 case RELAX_ALIGN_NEXT_OPCODE
:
9011 /* Always convert. */
9012 convert_frag_align_next_opcode (fragp
);
9015 case RELAX_DESIRE_ALIGN
:
9016 /* Do nothing. If not aligned already, too bad. */
9020 case RELAX_LITERAL_FINAL
:
9025 vbuf
= xtensa_insnbuf_alloc (isa
);
9027 xtensa_insnbuf_from_chars
9028 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9029 fmt
= xtensa_format_decode (isa
, vbuf
);
9030 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9032 for (slot
= 0; slot
< num_slots
; slot
++)
9034 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9037 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9041 case RELAX_IMMED_STEP1
:
9042 case RELAX_IMMED_STEP2
:
9043 /* Place the immediate. */
9046 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9051 /* This is OK because some slots could have
9052 relaxations and others have none. */
9058 case RELAX_UNREACHABLE
:
9059 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9060 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9061 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9065 case RELAX_MAYBE_UNREACHABLE
:
9066 case RELAX_MAYBE_DESIRE_ALIGN
:
9070 case RELAX_FILL_NOP
:
9071 convert_frag_fill_nop (fragp
);
9074 case RELAX_LITERAL_NR
:
9075 if (use_literal_section
)
9077 /* This should have been handled during relaxation. When
9078 relaxing a code segment, literals sometimes need to be
9079 added to the corresponding literal segment. If that
9080 literal segment has already been relaxed, then we end up
9081 in this situation. Marking the literal segments as data
9082 would make this happen less often (since GAS always relaxes
9083 code before data), but we could still get into trouble if
9084 there are instructions in a segment that is not marked as
9085 containing code. Until we can implement a better solution,
9086 cheat and adjust the addresses of all the following frags.
9087 This could break subsequent alignments, but the linker's
9088 literal coalescing will do that anyway. */
9091 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9092 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9093 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9096 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9100 as_bad (_("invalid relaxation fragment result"));
9105 new_logical_line (file_name
, line
);
9110 convert_frag_align_next_opcode (fragS
*fragp
)
9112 char *nop_buf
; /* Location for Writing. */
9113 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9114 addressT aligned_address
;
9118 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9120 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9121 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9122 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9124 for (nop
= 0; nop
< nop_count
; nop
++)
9127 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9129 assemble_nop (nop_size
, nop_buf
);
9130 nop_buf
+= nop_size
;
9133 fragp
->fr_fix
+= fill_size
;
9134 fragp
->fr_var
-= fill_size
;
9139 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9141 TInsn tinsn
, single_target
;
9142 int size
, old_size
, diff
;
9143 offsetT frag_offset
;
9146 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9148 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9150 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9151 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9152 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9157 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9159 /* No conversion. */
9164 assert (fragP
->fr_opcode
!= NULL
);
9166 /* Frags in this relaxation state should only contain
9167 single instruction bundles. */
9168 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9170 /* Just convert it to a wide form.... */
9172 old_size
= xg_get_single_size (tinsn
.opcode
);
9174 tinsn_init (&single_target
);
9175 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9177 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9179 as_bad (_("unable to widen instruction"));
9183 size
= xg_get_single_size (single_target
.opcode
);
9184 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9187 diff
= size
- old_size
;
9189 assert (diff
<= fragP
->fr_var
);
9190 fragP
->fr_var
-= diff
;
9191 fragP
->fr_fix
+= diff
;
9199 convert_frag_fill_nop (fragS
*fragP
)
9201 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9202 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9203 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9204 - fragP
->fr_address
- fragP
->fr_fix
));
9207 /* No conversion. */
9211 assemble_nop (size
, loc
);
9212 fragP
->tc_frag_data
.is_insn
= TRUE
;
9213 fragP
->fr_var
-= size
;
9214 fragP
->fr_fix
+= size
;
9219 static fixS
*fix_new_exp_in_seg
9220 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9221 bfd_reloc_code_real_type
);
9222 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9225 convert_frag_immed (segT segP
,
9231 char *immed_instr
= fragP
->fr_opcode
;
9233 bfd_boolean expanded
= FALSE
;
9234 bfd_boolean branch_jmp_to_next
= FALSE
;
9235 char *fr_opcode
= fragP
->fr_opcode
;
9236 xtensa_isa isa
= xtensa_default_isa
;
9237 bfd_boolean wide_insn
= FALSE
;
9239 bfd_boolean is_loop
;
9241 assert (fr_opcode
!= NULL
);
9243 xg_clear_vinsn (&cur_vinsn
);
9245 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9246 if (cur_vinsn
.num_slots
> 1)
9249 orig_tinsn
= cur_vinsn
.slots
[slot
];
9250 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9252 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9254 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9255 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9257 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9259 /* Conversion just inserts a NOP and marks the fix as completed. */
9260 bytes
= xtensa_format_length (isa
, fmt
);
9263 cur_vinsn
.slots
[slot
].opcode
=
9264 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9265 cur_vinsn
.slots
[slot
].ntok
= 0;
9269 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9270 assert (bytes
== 2 || bytes
== 3);
9271 build_nop (&cur_vinsn
.slots
[0], bytes
);
9272 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9274 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9275 xtensa_insnbuf_to_chars
9276 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9281 /* Here is the fun stuff: Get the immediate field from this
9282 instruction. If it fits, we're done. If not, find the next
9283 instruction sequence that fits. */
9287 symbolS
*lit_sym
= NULL
;
9289 int target_offset
= 0;
9292 symbolS
*gen_label
= NULL
;
9293 offsetT frag_offset
;
9294 bfd_boolean first
= TRUE
;
9295 bfd_boolean last_is_jump
;
9297 /* It does not fit. Find something that does and
9298 convert immediately. */
9299 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9300 istack_init (&istack
);
9301 xg_assembly_relax (&istack
, &orig_tinsn
,
9302 segP
, fragP
, frag_offset
, min_steps
, 0);
9304 old_size
= xtensa_format_length (isa
, fmt
);
9306 /* Assemble this right inline. */
9308 /* First, create the mapping from a label name to the REAL label. */
9310 for (i
= 0; i
< istack
.ninsn
; i
++)
9312 TInsn
*tinsn
= &istack
.insn
[i
];
9315 switch (tinsn
->insn_type
)
9318 if (lit_sym
!= NULL
)
9319 as_bad (_("multiple literals in expansion"));
9320 /* First find the appropriate space in the literal pool. */
9321 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9322 if (lit_frag
== NULL
)
9323 as_bad (_("no registered fragment for literal"));
9324 if (tinsn
->ntok
!= 1)
9325 as_bad (_("number of literal tokens != 1"));
9327 /* Set the literal symbol and add a fixup. */
9328 lit_sym
= lit_frag
->fr_symbol
;
9332 if (align_targets
&& !is_loop
)
9334 fragS
*unreach
= fragP
->fr_next
;
9335 while (!(unreach
->fr_type
== rs_machine_dependent
9336 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9337 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9339 unreach
= unreach
->fr_next
;
9342 assert (unreach
->fr_type
== rs_machine_dependent
9343 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9344 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9346 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9348 assert (gen_label
== NULL
);
9349 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9350 fr_opcode
- fragP
->fr_literal
9351 + target_offset
, fragP
);
9355 if (first
&& wide_insn
)
9357 target_offset
+= xtensa_format_length (isa
, fmt
);
9359 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9360 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9363 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9370 last_is_jump
= FALSE
;
9371 for (i
= 0; i
< istack
.ninsn
; i
++)
9373 TInsn
*tinsn
= &istack
.insn
[i
];
9377 bfd_reloc_code_real_type reloc_type
;
9379 switch (tinsn
->insn_type
)
9382 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9383 /* Already checked. */
9384 assert (lit_frag
!= NULL
);
9385 assert (lit_sym
!= NULL
);
9386 assert (tinsn
->ntok
== 1);
9388 target_seg
= S_GET_SEGMENT (lit_sym
);
9389 assert (target_seg
);
9390 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
);
9391 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9392 &tinsn
->tok
[0], FALSE
, reloc_type
);
9399 xg_resolve_labels (tinsn
, gen_label
);
9400 xg_resolve_literals (tinsn
, lit_sym
);
9401 if (wide_insn
&& first
)
9404 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9406 cur_vinsn
.slots
[slot
] = *tinsn
;
9410 cur_vinsn
.slots
[slot
].opcode
=
9411 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9412 cur_vinsn
.slots
[slot
].ntok
= 0;
9414 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9415 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9416 (unsigned char *) immed_instr
, 0);
9417 fragP
->tc_frag_data
.is_insn
= TRUE
;
9418 size
= xtensa_format_length (isa
, fmt
);
9419 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9422 (tinsn
, immed_instr
+ size
, fragP
,
9423 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9424 size
+= xg_get_single_size (tinsn
->opcode
);
9429 size
= xg_get_single_size (tinsn
->opcode
);
9430 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9431 immed_instr
- fragP
->fr_literal
, TRUE
);
9433 immed_instr
+= size
;
9439 diff
= total_size
- old_size
;
9443 assert (diff
<= fragP
->fr_var
);
9444 fragP
->fr_var
-= diff
;
9445 fragP
->fr_fix
+= diff
;
9448 /* Check for undefined immediates in LOOP instructions. */
9452 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9453 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9455 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9458 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9459 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9461 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9466 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9467 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9469 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9471 /* Add an expansion note on the expanded instruction. */
9472 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9473 &orig_tinsn
.tok
[0], TRUE
,
9474 BFD_RELOC_XTENSA_ASM_EXPAND
);
9479 /* Add a new fix expression into the desired segment. We have to
9480 switch to that segment to do this. */
9483 fix_new_exp_in_seg (segT new_seg
,
9490 bfd_reloc_code_real_type r_type
)
9494 subsegT subseg
= now_subseg
;
9496 assert (new_seg
!= 0);
9497 subseg_set (new_seg
, new_subseg
);
9499 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9500 subseg_set (seg
, subseg
);
9505 /* Relax a loop instruction so that it can span loop >256 bytes.
9511 addi as, as, lo8 (label-.L1)
9512 addmi as, as, mid8 (label-.L1)
9523 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9528 unsigned long target
;
9529 static xtensa_insnbuf insnbuf
= NULL
;
9530 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9531 xtensa_isa isa
= xtensa_default_isa
;
9532 addressT loop_offset
;
9533 addressT addi_offset
= 9;
9534 addressT addmi_offset
= 12;
9539 insnbuf
= xtensa_insnbuf_alloc (isa
);
9541 /* Get the loop offset. */
9542 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9544 /* Validate that there really is a LOOP at the loop_offset. Because
9545 loops are not bundleable, we can assume that the instruction will be
9547 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9548 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9550 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9551 addi_offset
+= loop_offset
;
9552 addmi_offset
+= loop_offset
;
9554 assert (tinsn
->ntok
== 2);
9555 if (tinsn
->tok
[1].X_op
== O_constant
)
9556 target
= tinsn
->tok
[1].X_add_number
;
9557 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9559 /* Find the fragment. */
9560 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9561 assert (S_GET_SEGMENT (sym
) == segP
9562 || S_GET_SEGMENT (sym
) == absolute_section
);
9563 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9567 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9571 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9572 loop_length_hi
= loop_length
& ~0x0ff;
9573 loop_length_lo
= loop_length
& 0x0ff;
9574 if (loop_length_lo
>= 128)
9576 loop_length_lo
-= 256;
9577 loop_length_hi
+= 256;
9580 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9581 32512. If the loop is larger than that, then we just fail. */
9582 if (loop_length_hi
> 32512)
9583 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9584 _("loop too long for LOOP instruction"));
9586 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9587 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9589 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9590 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9592 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9593 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9595 fragP
->tc_frag_data
.is_insn
= TRUE
;
9596 xtensa_insnbuf_to_chars
9597 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9599 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9600 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9601 xtensa_insnbuf_to_chars
9602 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9604 /* Walk through all of the frags from here to the loop end
9605 and mark them as no_transform to keep them from being modified
9606 by the linker. If we ever have a relocation for the
9607 addi/addmi of the difference of two symbols we can remove this. */
9610 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9611 next_fragP
= next_fragP
->fr_next
)
9613 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9614 if (next_fragP
->tc_frag_data
.is_loop_target
)
9616 if (target_count
== 2)
9622 /* A map that keeps information on a per-subsegment basis. This is
9623 maintained during initial assembly, but is invalid once the
9624 subsegments are smashed together. I.E., it cannot be used during
9627 typedef struct subseg_map_struct
9635 float total_freq
; /* fall-through + branch target frequency */
9636 float target_freq
; /* branch target frequency alone */
9638 struct subseg_map_struct
*next
;
9642 static subseg_map
*sseg_map
= NULL
;
9645 get_subseg_info (segT seg
, subsegT subseg
)
9647 subseg_map
*subseg_e
;
9649 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9651 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9659 add_subseg_info (segT seg
, subsegT subseg
)
9661 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9662 memset (subseg_e
, 0, sizeof (subseg_map
));
9663 subseg_e
->seg
= seg
;
9664 subseg_e
->subseg
= subseg
;
9665 subseg_e
->flags
= 0;
9666 /* Start off considering every branch target very important. */
9667 subseg_e
->target_freq
= 1.0;
9668 subseg_e
->total_freq
= 1.0;
9669 subseg_e
->next
= sseg_map
;
9670 sseg_map
= subseg_e
;
9676 get_last_insn_flags (segT seg
, subsegT subseg
)
9678 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9680 return subseg_e
->flags
;
9686 set_last_insn_flags (segT seg
,
9691 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9693 subseg_e
= add_subseg_info (seg
, subseg
);
9695 subseg_e
->flags
|= fl
;
9697 subseg_e
->flags
&= ~fl
;
9702 get_subseg_total_freq (segT seg
, subsegT subseg
)
9704 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9706 return subseg_e
->total_freq
;
9712 get_subseg_target_freq (segT seg
, subsegT subseg
)
9714 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9716 return subseg_e
->target_freq
;
9722 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9724 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9726 subseg_e
= add_subseg_info (seg
, subseg
);
9727 subseg_e
->total_freq
= total_f
;
9728 subseg_e
->target_freq
= target_f
;
9732 /* Segment Lists and emit_state Stuff. */
9735 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9740 segT literal_section
= head
->seg
;
9742 /* Move the literal section to the front of the section list. */
9743 assert (literal_section
);
9744 if (literal_section
!= stdoutput
->sections
)
9746 bfd_section_list_remove (stdoutput
, literal_section
);
9747 bfd_section_list_prepend (stdoutput
, literal_section
);
9754 static void mark_literal_frags (seg_list
*);
9757 xtensa_move_literals (void)
9760 frchainS
*frchain_from
, *frchain_to
;
9761 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9762 fragS
**frag_splice
;
9765 fixS
*fix
, *next_fix
, **fix_splice
;
9768 mark_literal_frags (literal_head
->next
);
9770 if (use_literal_section
)
9773 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
9775 /* Keep the literals for .init and .fini in separate sections. */
9776 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
9777 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
9780 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9781 search_frag
= frchain_from
->frch_root
;
9782 literal_pool
= NULL
;
9784 frag_splice
= &(frchain_from
->frch_root
);
9786 while (!search_frag
->tc_frag_data
.literal_frag
)
9788 assert (search_frag
->fr_fix
== 0
9789 || search_frag
->fr_type
== rs_align
);
9790 search_frag
= search_frag
->fr_next
;
9793 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9794 == RELAX_LITERAL_POOL_BEGIN
);
9795 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9797 /* Make sure that all the frags in this series are closed, and
9798 that there is at least one left over of zero-size. This
9799 prevents us from making a segment with an frchain without any
9801 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9802 xtensa_set_frag_assembly_state (frag_now
);
9803 last_frag
= frag_now
;
9804 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9805 xtensa_set_frag_assembly_state (frag_now
);
9807 while (search_frag
!= frag_now
)
9809 next_frag
= search_frag
->fr_next
;
9811 /* First, move the frag out of the literal section and
9812 to the appropriate place. */
9813 if (search_frag
->tc_frag_data
.literal_frag
)
9815 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9816 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9817 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
9818 assert (frchain_to
);
9820 insert_after
= literal_pool
;
9822 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9823 insert_after
= insert_after
->fr_next
;
9825 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
9827 *frag_splice
= next_frag
;
9828 search_frag
->fr_next
= insert_after
->fr_next
;
9829 insert_after
->fr_next
= search_frag
;
9830 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9832 /* Now move any fixups associated with this frag to the
9834 fix
= frchain_from
->fix_root
;
9835 fix_splice
= &(frchain_from
->fix_root
);
9838 next_fix
= fix
->fx_next
;
9839 if (fix
->fx_frag
== search_frag
)
9841 *fix_splice
= next_fix
;
9842 fix
->fx_next
= frchain_to
->fix_root
;
9843 frchain_to
->fix_root
= fix
;
9844 if (frchain_to
->fix_tail
== NULL
)
9845 frchain_to
->fix_tail
= fix
;
9848 fix_splice
= &(fix
->fx_next
);
9851 search_frag
= next_frag
;
9854 if (frchain_from
->fix_root
!= NULL
)
9856 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9857 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9859 assert (frchain_from
->fix_root
== NULL
);
9861 frchain_from
->fix_tail
= NULL
;
9862 xtensa_restore_emit_state (&state
);
9865 /* Now fix up the SEGMENT value for all the literal symbols. */
9866 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9868 symbolS
*lit_sym
= lit
->sym
;
9869 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9871 S_SET_SEGMENT (lit_sym
, dest_seg
);
9876 /* Walk over all the frags for segments in a list and mark them as
9877 containing literals. As clunky as this is, we can't rely on frag_var
9878 and frag_variant to get called in all situations. */
9881 mark_literal_frags (seg_list
*segment
)
9883 frchainS
*frchain_from
;
9888 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9889 search_frag
= frchain_from
->frch_root
;
9892 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9893 search_frag
= search_frag
->fr_next
;
9895 segment
= segment
->next
;
9901 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9903 /* Move all of the sections in the section list to come
9904 after "after" in the gnu segment list. */
9909 segT literal_section
= head
->seg
;
9911 /* Move the literal section after "after". */
9912 assert (literal_section
);
9913 if (literal_section
!= after
)
9915 bfd_section_list_remove (stdoutput
, literal_section
);
9916 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
9924 /* Push all the literal segments to the end of the gnu list. */
9927 xtensa_reorder_segments (void)
9934 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9940 /* Now that we have the last section, push all the literal
9941 sections to the end. */
9942 xtensa_reorder_seg_list (literal_head
, last_sec
);
9944 /* Now perform the final error check. */
9945 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
9947 assert (new_count
== old_count
);
9951 /* Change the emit state (seg, subseg, and frag related stuff) to the
9952 correct location. Return a emit_state which can be passed to
9953 xtensa_restore_emit_state to return to current fragment. */
9956 xtensa_switch_to_literal_fragment (emit_state
*result
)
9958 if (directive_state
[directive_absolute_literals
])
9960 segT lit4_seg
= cache_literal_section (TRUE
);
9961 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
9964 xtensa_switch_to_non_abs_literal_fragment (result
);
9966 /* Do a 4-byte align here. */
9967 frag_align (2, 0, 0);
9968 record_alignment (now_seg
, 2);
9973 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
9975 static bfd_boolean recursive
= FALSE
;
9976 fragS
*pool_location
= get_literal_pool_location (now_seg
);
9978 bfd_boolean is_init
=
9979 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
9980 bfd_boolean is_fini
=
9981 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
9983 if (pool_location
== NULL
9984 && !use_literal_section
9986 && !is_init
&& ! is_fini
)
9988 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
9990 /* When we mark a literal pool location, we want to put a frag in
9991 the literal pool that points to it. But to do that, we want to
9992 switch_to_literal_fragment. But literal sections don't have
9993 literal pools, so their location is always null, so we would
9994 recurse forever. This is kind of hacky, but it works. */
9997 xtensa_mark_literal_pool_location ();
10001 lit_seg
= cache_literal_section (FALSE
);
10002 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10004 if (!use_literal_section
10005 && !is_init
&& !is_fini
10006 && get_literal_pool_location (now_seg
) != pool_location
)
10008 /* Close whatever frag is there. */
10009 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10010 xtensa_set_frag_assembly_state (frag_now
);
10011 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10012 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10013 xtensa_set_frag_assembly_state (frag_now
);
10018 /* Call this function before emitting data into the literal section.
10019 This is a helper function for xtensa_switch_to_literal_fragment.
10020 This is similar to a .section new_now_seg subseg. */
10023 xtensa_switch_section_emit_state (emit_state
*state
,
10025 subsegT new_now_subseg
)
10027 state
->name
= now_seg
->name
;
10028 state
->now_seg
= now_seg
;
10029 state
->now_subseg
= now_subseg
;
10030 state
->generating_literals
= generating_literals
;
10031 generating_literals
++;
10032 subseg_set (new_now_seg
, new_now_subseg
);
10036 /* Use to restore the emitting into the normal place. */
10039 xtensa_restore_emit_state (emit_state
*state
)
10041 generating_literals
= state
->generating_literals
;
10042 subseg_set (state
->now_seg
, state
->now_subseg
);
10046 /* Predicate function used to look up a section in a particular group. */
10049 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10051 const char *gname
= inf
;
10052 const char *group_name
= elf_group_name (sec
);
10054 return (group_name
== gname
10055 || (group_name
!= NULL
10057 && strcmp (group_name
, gname
) == 0));
10061 /* Get the literal section to be used for the current text section.
10062 The result may be cached in the default_lit_sections structure. */
10065 cache_literal_section (bfd_boolean use_abs_literals
)
10067 const char *text_name
, *group_name
= 0;
10068 char *base_name
, *name
, *suffix
;
10070 segT seg
, current_section
;
10071 int current_subsec
;
10072 bfd_boolean linkonce
= FALSE
;
10074 /* Save the current section/subsection. */
10075 current_section
= now_seg
;
10076 current_subsec
= now_subseg
;
10078 /* Clear the cached values if they are no longer valid. */
10079 if (now_seg
!= default_lit_sections
.current_text_seg
)
10081 default_lit_sections
.current_text_seg
= now_seg
;
10082 default_lit_sections
.lit_seg
= NULL
;
10083 default_lit_sections
.lit4_seg
= NULL
;
10086 /* Check if the literal section is already cached. */
10087 if (use_abs_literals
)
10088 pcached
= &default_lit_sections
.lit4_seg
;
10090 pcached
= &default_lit_sections
.lit_seg
;
10095 text_name
= default_lit_sections
.lit_prefix
;
10096 if (! text_name
|| ! *text_name
)
10098 text_name
= segment_name (current_section
);
10099 group_name
= elf_group_name (current_section
);
10100 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10103 base_name
= use_abs_literals
? ".lit4" : ".literal";
10106 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10107 sprintf (name
, "%s.%s", base_name
, group_name
);
10109 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10111 suffix
= strchr (text_name
+ linkonce_len
, '.');
10113 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10114 + (suffix
? strlen (suffix
) : 0));
10115 strcpy (name
, ".gnu.linkonce");
10116 strcat (name
, base_name
);
10118 strcat (name
, suffix
);
10123 /* If the section name ends with ".text", then replace that suffix
10124 instead of appending an additional suffix. */
10125 size_t len
= strlen (text_name
);
10126 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10129 name
= xmalloc (len
+ strlen (base_name
) + 1);
10130 strcpy (name
, text_name
);
10131 strcpy (name
+ len
, base_name
);
10134 /* Canonicalize section names to allow renaming literal sections.
10135 The group name, if any, came from the current text section and
10136 has already been canonicalized. */
10137 name
= tc_canonicalize_symbol_name (name
);
10139 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10140 (void *) group_name
);
10145 seg
= subseg_force_new (name
, 0);
10147 if (! use_abs_literals
)
10149 /* Add the newly created literal segment to the list. */
10150 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10152 n
->next
= literal_head
->next
;
10153 literal_head
->next
= n
;
10156 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10157 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10158 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10160 elf_group_name (seg
) = group_name
;
10162 bfd_set_section_flags (stdoutput
, seg
, flags
);
10163 bfd_set_section_alignment (stdoutput
, seg
, 2);
10167 subseg_set (current_section
, current_subsec
);
10172 /* Property Tables Stuff. */
10174 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10175 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10176 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10178 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10179 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10181 static bfd_boolean
get_frag_is_literal (const fragS
*);
10182 static void xtensa_create_property_segments
10183 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10184 static void xtensa_create_xproperty_segments
10185 (frag_flags_fn
, const char *, xt_section_type
);
10186 static segment_info_type
*retrieve_segment_info (segT
);
10187 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10188 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10189 static void add_xt_block_frags
10190 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10191 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10192 static void xtensa_frag_flags_init (frag_flags
*);
10193 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10194 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10195 static void add_xt_prop_frags
10196 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10198 /* Set up property tables after relaxation. */
10201 xtensa_post_relax_hook (void)
10203 xtensa_move_seg_list_to_beginning (literal_head
);
10205 xtensa_find_unmarked_state_frags ();
10206 xtensa_mark_frags_for_org ();
10208 xtensa_create_property_segments (get_frag_is_literal
,
10210 XTENSA_LIT_SEC_NAME
,
10212 xtensa_create_xproperty_segments (get_frag_property_flags
,
10213 XTENSA_PROP_SEC_NAME
,
10216 if (warn_unaligned_branch_targets
)
10217 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10218 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10222 /* This function is only meaningful after xtensa_move_literals. */
10225 get_frag_is_literal (const fragS
*fragP
)
10227 assert (fragP
!= NULL
);
10228 return fragP
->tc_frag_data
.is_literal
;
10233 xtensa_create_property_segments (frag_predicate property_function
,
10234 frag_predicate end_property_function
,
10235 const char *section_name_base
,
10236 xt_section_type sec_type
)
10240 /* Walk over all of the current segments.
10241 Walk over each fragment
10242 For each non-empty fragment,
10243 Build a property record (append where possible). */
10245 for (seclist
= &stdoutput
->sections
;
10246 seclist
&& *seclist
;
10247 seclist
= &(*seclist
)->next
)
10249 segT sec
= *seclist
;
10252 flags
= bfd_get_section_flags (stdoutput
, sec
);
10253 if (flags
& SEC_DEBUGGING
)
10255 if (!(flags
& SEC_ALLOC
))
10258 if (section_has_property (sec
, property_function
))
10261 xtensa_get_property_section (sec
, section_name_base
);
10262 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10263 xtensa_block_info
**xt_blocks
=
10264 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10265 /* Walk over all of the frchains here and add new sections. */
10266 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10267 end_property_function
);
10271 /* Now we fill them out.... */
10273 for (seclist
= &stdoutput
->sections
;
10274 seclist
&& *seclist
;
10275 seclist
= &(*seclist
)->next
)
10277 segment_info_type
*seginfo
;
10278 xtensa_block_info
*block
;
10279 segT sec
= *seclist
;
10281 seginfo
= seg_info (sec
);
10282 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10286 xtensa_block_info
*cur_block
;
10287 /* This is a section with some data. */
10289 bfd_size_type rec_size
;
10291 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10294 rec_size
= num_recs
* 8;
10295 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10297 /* In order to make this work with the assembler, we have to
10298 build some frags and then build the "fixups" for it. It
10299 would be easier to just set the contents then set the
10304 /* Allocate a fragment and leak it. */
10306 bfd_size_type frag_size
;
10308 frchainS
*frchainP
;
10312 frag_size
= sizeof (fragS
) + rec_size
;
10313 fragP
= (fragS
*) xmalloc (frag_size
);
10315 memset (fragP
, 0, frag_size
);
10316 fragP
->fr_address
= 0;
10317 fragP
->fr_next
= NULL
;
10318 fragP
->fr_fix
= rec_size
;
10320 fragP
->fr_type
= rs_fill
;
10321 /* The rest are zeros. */
10323 frchainP
= seginfo
->frchainP
;
10324 frchainP
->frch_root
= fragP
;
10325 frchainP
->frch_last
= fragP
;
10327 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10328 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10330 seginfo
->fix_root
= fixes
;
10331 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10333 frag_data
= &fragP
->fr_literal
[0];
10334 for (i
= 0; i
< num_recs
; i
++)
10336 fixS
*fix
= &fixes
[i
];
10337 assert (cur_block
);
10339 /* Write the fixup. */
10340 if (i
!= num_recs
- 1)
10341 fix
->fx_next
= &fixes
[i
+ 1];
10343 fix
->fx_next
= NULL
;
10346 fix
->fx_frag
= fragP
;
10347 fix
->fx_where
= i
* 8;
10348 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10349 fix
->fx_offset
= cur_block
->offset
;
10350 fix
->fx_r_type
= BFD_RELOC_32
;
10351 fix
->fx_file
= "Internal Assembly";
10354 /* Write the length. */
10355 md_number_to_chars (&frag_data
[4 + 8 * i
],
10356 cur_block
->size
, 4);
10357 cur_block
= cur_block
->next
;
10366 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10367 const char *section_name_base
,
10368 xt_section_type sec_type
)
10372 /* Walk over all of the current segments.
10373 Walk over each fragment.
10374 For each fragment that has instructions,
10375 build an instruction record (append where possible). */
10377 for (seclist
= &stdoutput
->sections
;
10378 seclist
&& *seclist
;
10379 seclist
= &(*seclist
)->next
)
10381 segT sec
= *seclist
;
10384 flags
= bfd_get_section_flags (stdoutput
, sec
);
10385 if ((flags
& SEC_DEBUGGING
)
10386 || !(flags
& SEC_ALLOC
)
10387 || (flags
& SEC_MERGE
))
10390 if (section_has_xproperty (sec
, flag_fn
))
10393 xtensa_get_property_section (sec
, section_name_base
);
10394 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10395 xtensa_block_info
**xt_blocks
=
10396 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10397 /* Walk over all of the frchains here and add new sections. */
10398 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10402 /* Now we fill them out.... */
10404 for (seclist
= &stdoutput
->sections
;
10405 seclist
&& *seclist
;
10406 seclist
= &(*seclist
)->next
)
10408 segment_info_type
*seginfo
;
10409 xtensa_block_info
*block
;
10410 segT sec
= *seclist
;
10412 seginfo
= seg_info (sec
);
10413 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10417 xtensa_block_info
*cur_block
;
10418 /* This is a section with some data. */
10420 bfd_size_type rec_size
;
10422 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10425 rec_size
= num_recs
* (8 + 4);
10426 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10428 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10430 /* In order to make this work with the assembler, we have to build
10431 some frags then build the "fixups" for it. It would be easier to
10432 just set the contents then set the arlents. */
10436 /* Allocate a fragment and (unfortunately) leak it. */
10438 bfd_size_type frag_size
;
10440 frchainS
*frchainP
;
10444 frag_size
= sizeof (fragS
) + rec_size
;
10445 fragP
= (fragS
*) xmalloc (frag_size
);
10447 memset (fragP
, 0, frag_size
);
10448 fragP
->fr_address
= 0;
10449 fragP
->fr_next
= NULL
;
10450 fragP
->fr_fix
= rec_size
;
10452 fragP
->fr_type
= rs_fill
;
10453 /* The rest are zeros. */
10455 frchainP
= seginfo
->frchainP
;
10456 frchainP
->frch_root
= fragP
;
10457 frchainP
->frch_last
= fragP
;
10459 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10460 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10462 seginfo
->fix_root
= fixes
;
10463 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10465 frag_data
= &fragP
->fr_literal
[0];
10466 for (i
= 0; i
< num_recs
; i
++)
10468 fixS
*fix
= &fixes
[i
];
10469 assert (cur_block
);
10471 /* Write the fixup. */
10472 if (i
!= num_recs
- 1)
10473 fix
->fx_next
= &fixes
[i
+ 1];
10475 fix
->fx_next
= NULL
;
10478 fix
->fx_frag
= fragP
;
10479 fix
->fx_where
= i
* (8 + 4);
10480 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10481 fix
->fx_offset
= cur_block
->offset
;
10482 fix
->fx_r_type
= BFD_RELOC_32
;
10483 fix
->fx_file
= "Internal Assembly";
10486 /* Write the length. */
10487 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10488 cur_block
->size
, 4);
10489 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10490 frag_flags_to_number (&cur_block
->flags
),
10492 cur_block
= cur_block
->next
;
10500 static segment_info_type
*
10501 retrieve_segment_info (segT seg
)
10503 segment_info_type
*seginfo
;
10504 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10507 frchainS
*frchainP
;
10509 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10510 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10511 seginfo
->fix_root
= NULL
;
10512 seginfo
->fix_tail
= NULL
;
10513 seginfo
->bfd_section
= seg
;
10515 /* We will not be dealing with these, only our special ones. */
10516 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10518 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10519 frchainP
->frch_root
= NULL
;
10520 frchainP
->frch_last
= NULL
;
10521 frchainP
->frch_next
= NULL
;
10522 frchainP
->frch_subseg
= 0;
10523 frchainP
->fix_root
= NULL
;
10524 frchainP
->fix_tail
= NULL
;
10525 /* Do not init the objstack. */
10526 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10527 /* frchainP->frch_frag_now = fragP; */
10528 frchainP
->frch_frag_now
= NULL
;
10530 seginfo
->frchainP
= frchainP
;
10538 section_has_property (segT sec
, frag_predicate property_function
)
10540 segment_info_type
*seginfo
= seg_info (sec
);
10543 if (seginfo
&& seginfo
->frchainP
)
10545 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10547 if (property_function (fragP
)
10548 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10557 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10559 segment_info_type
*seginfo
= seg_info (sec
);
10562 if (seginfo
&& seginfo
->frchainP
)
10564 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10566 frag_flags prop_flags
;
10567 property_function (fragP
, &prop_flags
);
10568 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10576 /* Two types of block sections exist right now: literal and insns. */
10579 add_xt_block_frags (segT sec
,
10581 xtensa_block_info
**xt_block
,
10582 frag_predicate property_function
,
10583 frag_predicate end_property_function
)
10585 segment_info_type
*seg_info
;
10586 segment_info_type
*xt_seg_info
;
10587 bfd_vma seg_offset
;
10590 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10591 seg_info
= retrieve_segment_info (sec
);
10593 /* Build it if needed. */
10594 while (*xt_block
!= NULL
)
10595 xt_block
= &(*xt_block
)->next
;
10596 /* We are either at NULL at the beginning or at the end. */
10598 /* Walk through the frags. */
10601 if (seg_info
->frchainP
)
10603 for (fragP
= seg_info
->frchainP
->frch_root
;
10605 fragP
= fragP
->fr_next
)
10607 if (property_function (fragP
)
10608 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10610 if (*xt_block
!= NULL
)
10612 if ((*xt_block
)->offset
+ (*xt_block
)->size
10613 == fragP
->fr_address
)
10614 (*xt_block
)->size
+= fragP
->fr_fix
;
10616 xt_block
= &((*xt_block
)->next
);
10618 if (*xt_block
== NULL
)
10620 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10621 xmalloc (sizeof (xtensa_block_info
));
10622 new_block
->sec
= sec
;
10623 new_block
->offset
= fragP
->fr_address
;
10624 new_block
->size
= fragP
->fr_fix
;
10625 new_block
->next
= NULL
;
10626 xtensa_frag_flags_init (&new_block
->flags
);
10627 *xt_block
= new_block
;
10629 if (end_property_function
10630 && end_property_function (fragP
))
10632 xt_block
= &((*xt_block
)->next
);
10640 /* Break the encapsulation of add_xt_prop_frags here. */
10643 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10645 if (prop_flags
->is_literal
10646 || prop_flags
->is_insn
10647 || prop_flags
->is_data
10648 || prop_flags
->is_unreachable
)
10655 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10657 memset (prop_flags
, 0, sizeof (frag_flags
));
10662 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10664 xtensa_frag_flags_init (prop_flags
);
10665 if (fragP
->tc_frag_data
.is_literal
)
10666 prop_flags
->is_literal
= TRUE
;
10667 if (fragP
->tc_frag_data
.is_specific_opcode
10668 || fragP
->tc_frag_data
.is_no_transform
)
10669 prop_flags
->is_no_transform
= TRUE
;
10670 if (fragP
->tc_frag_data
.is_unreachable
)
10671 prop_flags
->is_unreachable
= TRUE
;
10672 else if (fragP
->tc_frag_data
.is_insn
)
10674 prop_flags
->is_insn
= TRUE
;
10675 if (fragP
->tc_frag_data
.is_loop_target
)
10676 prop_flags
->insn
.is_loop_target
= TRUE
;
10677 if (fragP
->tc_frag_data
.is_branch_target
)
10678 prop_flags
->insn
.is_branch_target
= TRUE
;
10679 if (fragP
->tc_frag_data
.is_no_density
)
10680 prop_flags
->insn
.is_no_density
= TRUE
;
10681 if (fragP
->tc_frag_data
.use_absolute_literals
)
10682 prop_flags
->insn
.is_abslit
= TRUE
;
10684 if (fragP
->tc_frag_data
.is_align
)
10686 prop_flags
->is_align
= TRUE
;
10687 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10688 if (xtensa_frag_flags_is_empty (prop_flags
))
10689 prop_flags
->is_data
= TRUE
;
10695 frag_flags_to_number (const frag_flags
*prop_flags
)
10698 if (prop_flags
->is_literal
)
10699 num
|= XTENSA_PROP_LITERAL
;
10700 if (prop_flags
->is_insn
)
10701 num
|= XTENSA_PROP_INSN
;
10702 if (prop_flags
->is_data
)
10703 num
|= XTENSA_PROP_DATA
;
10704 if (prop_flags
->is_unreachable
)
10705 num
|= XTENSA_PROP_UNREACHABLE
;
10706 if (prop_flags
->insn
.is_loop_target
)
10707 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10708 if (prop_flags
->insn
.is_branch_target
)
10710 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10711 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10714 if (prop_flags
->insn
.is_no_density
)
10715 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10716 if (prop_flags
->is_no_transform
)
10717 num
|= XTENSA_PROP_NO_TRANSFORM
;
10718 if (prop_flags
->insn
.is_no_reorder
)
10719 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10720 if (prop_flags
->insn
.is_abslit
)
10721 num
|= XTENSA_PROP_INSN_ABSLIT
;
10723 if (prop_flags
->is_align
)
10725 num
|= XTENSA_PROP_ALIGN
;
10726 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10734 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10735 const frag_flags
*prop_flags_2
)
10737 /* Cannot combine with an end marker. */
10739 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10741 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10743 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10746 if (prop_flags_1
->is_insn
)
10748 /* Properties of the beginning of the frag. */
10749 if (prop_flags_2
->insn
.is_loop_target
)
10751 if (prop_flags_2
->insn
.is_branch_target
)
10753 if (prop_flags_1
->insn
.is_no_density
!=
10754 prop_flags_2
->insn
.is_no_density
)
10756 if (prop_flags_1
->is_no_transform
!=
10757 prop_flags_2
->is_no_transform
)
10759 if (prop_flags_1
->insn
.is_no_reorder
!=
10760 prop_flags_2
->insn
.is_no_reorder
)
10762 if (prop_flags_1
->insn
.is_abslit
!=
10763 prop_flags_2
->insn
.is_abslit
)
10767 if (prop_flags_1
->is_align
)
10775 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10778 unsigned align_bits
;
10780 if (!xt_block
->flags
.is_align
)
10781 return xt_block
->size
;
10783 end_addr
= xt_block
->offset
+ xt_block
->size
;
10784 align_bits
= xt_block
->flags
.alignment
;
10785 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10786 return end_addr
- xt_block
->offset
;
10791 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10792 const xtensa_block_info
*xt_block_2
)
10794 if (xt_block
->sec
!= xt_block_2
->sec
)
10796 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10797 != xt_block_2
->offset
)
10800 if (xt_block_2
->size
== 0
10801 && (!xt_block_2
->flags
.is_unreachable
10802 || xt_block
->flags
.is_unreachable
))
10804 if (xt_block_2
->flags
.is_align
10805 && xt_block
->flags
.is_align
)
10807 /* Nothing needed. */
10808 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10813 if (xt_block_2
->flags
.is_align
)
10815 /* Push alignment to previous entry. */
10816 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10817 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10822 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10823 &xt_block_2
->flags
))
10826 xt_block
->size
+= xt_block_2
->size
;
10828 if (xt_block_2
->flags
.is_align
)
10830 xt_block
->flags
.is_align
= TRUE
;
10831 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10839 add_xt_prop_frags (segT sec
,
10841 xtensa_block_info
**xt_block
,
10842 frag_flags_fn property_function
)
10844 segment_info_type
*seg_info
;
10845 segment_info_type
*xt_seg_info
;
10846 bfd_vma seg_offset
;
10849 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10850 seg_info
= retrieve_segment_info (sec
);
10851 /* Build it if needed. */
10852 while (*xt_block
!= NULL
)
10854 xt_block
= &(*xt_block
)->next
;
10856 /* We are either at NULL at the beginning or at the end. */
10858 /* Walk through the frags. */
10861 if (seg_info
->frchainP
)
10863 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10864 fragP
= fragP
->fr_next
)
10866 xtensa_block_info tmp_block
;
10867 tmp_block
.sec
= sec
;
10868 tmp_block
.offset
= fragP
->fr_address
;
10869 tmp_block
.size
= fragP
->fr_fix
;
10870 tmp_block
.next
= NULL
;
10871 property_function (fragP
, &tmp_block
.flags
);
10873 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10874 /* && fragP->fr_fix != 0) */
10876 if ((*xt_block
) == NULL
10877 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10879 xtensa_block_info
*new_block
;
10880 if ((*xt_block
) != NULL
)
10881 xt_block
= &(*xt_block
)->next
;
10882 new_block
= (xtensa_block_info
*)
10883 xmalloc (sizeof (xtensa_block_info
));
10884 *new_block
= tmp_block
;
10885 *xt_block
= new_block
;
10893 /* op_placement_info_table */
10895 /* op_placement_info makes it easier to determine which
10896 ops can go in which slots. */
10899 init_op_placement_info_table (void)
10901 xtensa_isa isa
= xtensa_default_isa
;
10902 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10903 xtensa_opcode opcode
;
10906 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10908 op_placement_table
= (op_placement_info_table
)
10909 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10910 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10912 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10914 op_placement_info
*opi
= &op_placement_table
[opcode
];
10915 /* FIXME: Make tinsn allocation dynamic. */
10916 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10917 as_fatal (_("too many operands in instruction"));
10918 opi
->narrowest
= XTENSA_UNDEFINED
;
10919 opi
->narrowest_size
= 0x7F;
10920 opi
->narrowest_slot
= 0;
10922 opi
->num_formats
= 0;
10924 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10926 opi
->slots
[fmt
] = 0;
10927 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10929 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10931 int fmt_length
= xtensa_format_length (isa
, fmt
);
10933 set_bit (fmt
, opi
->formats
);
10934 set_bit (slot
, opi
->slots
[fmt
]);
10935 if (fmt_length
< opi
->narrowest_size
10936 || (fmt_length
== opi
->narrowest_size
10937 && (xtensa_format_num_slots (isa
, fmt
)
10938 < xtensa_format_num_slots (isa
,
10941 opi
->narrowest
= fmt
;
10942 opi
->narrowest_size
= fmt_length
;
10943 opi
->narrowest_slot
= slot
;
10948 opi
->num_formats
++;
10951 xtensa_insnbuf_free (isa
, ibuf
);
10956 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
10958 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
10962 /* If the opcode is available in a single slot format, return its size. */
10965 xg_get_single_size (xtensa_opcode opcode
)
10967 return op_placement_table
[opcode
].narrowest_size
;
10971 static xtensa_format
10972 xg_get_single_format (xtensa_opcode opcode
)
10974 return op_placement_table
[opcode
].narrowest
;
10979 xg_get_single_slot (xtensa_opcode opcode
)
10981 return op_placement_table
[opcode
].narrowest_slot
;
10985 /* Instruction Stack Functions (from "xtensa-istack.h"). */
10988 istack_init (IStack
*stack
)
10990 memset (stack
, 0, sizeof (IStack
));
10996 istack_empty (IStack
*stack
)
10998 return (stack
->ninsn
== 0);
11003 istack_full (IStack
*stack
)
11005 return (stack
->ninsn
== MAX_ISTACK
);
11009 /* Return a pointer to the top IStack entry.
11010 It is an error to call this if istack_empty () is TRUE. */
11013 istack_top (IStack
*stack
)
11015 int rec
= stack
->ninsn
- 1;
11016 assert (!istack_empty (stack
));
11017 return &stack
->insn
[rec
];
11021 /* Add a new TInsn to an IStack.
11022 It is an error to call this if istack_full () is TRUE. */
11025 istack_push (IStack
*stack
, TInsn
*insn
)
11027 int rec
= stack
->ninsn
;
11028 assert (!istack_full (stack
));
11029 stack
->insn
[rec
] = *insn
;
11034 /* Clear space for the next TInsn on the IStack and return a pointer
11035 to it. It is an error to call this if istack_full () is TRUE. */
11038 istack_push_space (IStack
*stack
)
11040 int rec
= stack
->ninsn
;
11042 assert (!istack_full (stack
));
11043 insn
= &stack
->insn
[rec
];
11050 /* Remove the last pushed instruction. It is an error to call this if
11051 istack_empty () returns TRUE. */
11054 istack_pop (IStack
*stack
)
11056 int rec
= stack
->ninsn
- 1;
11057 assert (!istack_empty (stack
));
11059 tinsn_init (&stack
->insn
[rec
]);
11063 /* TInsn functions. */
11066 tinsn_init (TInsn
*dst
)
11068 memset (dst
, 0, sizeof (TInsn
));
11072 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11075 tinsn_has_symbolic_operands (const TInsn
*insn
)
11078 int n
= insn
->ntok
;
11080 assert (insn
->insn_type
== ITYPE_INSN
);
11082 for (i
= 0; i
< n
; ++i
)
11084 switch (insn
->tok
[i
].X_op
)
11098 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11100 xtensa_isa isa
= xtensa_default_isa
;
11102 int n
= insn
->ntok
;
11104 assert (insn
->insn_type
== ITYPE_INSN
);
11106 for (i
= 0; i
< n
; ++i
)
11108 switch (insn
->tok
[i
].X_op
)
11116 /* Errors for these types are caught later. */
11121 /* Symbolic immediates are only allowed on the last immediate
11122 operand. At this time, CONST16 is the only opcode where we
11123 support non-PC-relative relocations. */
11124 if (i
!= get_relaxable_immed (insn
->opcode
)
11125 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11126 && insn
->opcode
!= xtensa_const16_opcode
))
11128 as_bad (_("invalid symbolic operand"));
11137 /* For assembly code with complex expressions (e.g. subtraction),
11138 we have to build them in the literal pool so that
11139 their results are calculated correctly after relaxation.
11140 The relaxation only handles expressions that
11141 boil down to SYMBOL + OFFSET. */
11144 tinsn_has_complex_operands (const TInsn
*insn
)
11147 int n
= insn
->ntok
;
11148 assert (insn
->insn_type
== ITYPE_INSN
);
11149 for (i
= 0; i
< n
; ++i
)
11151 switch (insn
->tok
[i
].X_op
)
11167 /* Encode a TInsn opcode and its constant operands into slotbuf.
11168 Return TRUE if there is a symbol in the immediate field. This
11169 function assumes that:
11170 1) The number of operands are correct.
11171 2) The insn_type is ITYPE_INSN.
11172 3) The opcode can be encoded in the specified format and slot.
11173 4) Operands are either O_constant or O_symbol, and all constants fit. */
11176 tinsn_to_slotbuf (xtensa_format fmt
,
11179 xtensa_insnbuf slotbuf
)
11181 xtensa_isa isa
= xtensa_default_isa
;
11182 xtensa_opcode opcode
= tinsn
->opcode
;
11183 bfd_boolean has_fixup
= FALSE
;
11184 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11187 assert (tinsn
->insn_type
== ITYPE_INSN
);
11188 if (noperands
!= tinsn
->ntok
)
11189 as_fatal (_("operand number mismatch"));
11191 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11193 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11194 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11198 for (i
= 0; i
< noperands
; i
++)
11200 expressionS
*expr
= &tinsn
->tok
[i
];
11206 switch (expr
->X_op
)
11209 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11211 /* The register number has already been checked in
11212 expression_maybe_register, so we don't need to check here. */
11213 opnd_value
= expr
->X_add_number
;
11214 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11215 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11218 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11222 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11224 as_where (&file_name
, &line
);
11225 /* It is a constant and we called this function
11226 then we have to try to fit it. */
11227 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11228 expr
->X_add_number
, file_name
, line
);
11241 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11242 into a multi-slot instruction, fill the other slots with NOPs.
11243 Return TRUE if there is a symbol in the immediate field. See also the
11244 assumptions listed for tinsn_to_slotbuf. */
11247 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11249 static xtensa_insnbuf slotbuf
= 0;
11250 static vliw_insn vinsn
;
11251 xtensa_isa isa
= xtensa_default_isa
;
11252 bfd_boolean has_fixup
= FALSE
;
11257 slotbuf
= xtensa_insnbuf_alloc (isa
);
11258 xg_init_vinsn (&vinsn
);
11261 xg_clear_vinsn (&vinsn
);
11263 bundle_tinsn (tinsn
, &vinsn
);
11265 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11267 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11269 /* Only one slot may have a fix-up because the rest contains NOPs. */
11271 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11272 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11279 /* Check the instruction arguments. Return TRUE on failure. */
11282 tinsn_check_arguments (const TInsn
*insn
)
11284 xtensa_isa isa
= xtensa_default_isa
;
11285 xtensa_opcode opcode
= insn
->opcode
;
11287 if (opcode
== XTENSA_UNDEFINED
)
11289 as_bad (_("invalid opcode"));
11293 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11295 as_bad (_("too few operands"));
11299 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11301 as_bad (_("too many operands"));
11308 /* Load an instruction from its encoded form. */
11311 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11315 xg_init_vinsn (&vinsn
);
11316 vinsn_from_chars (&vinsn
, f
);
11318 *tinsn
= vinsn
.slots
[slot
];
11319 xg_free_vinsn (&vinsn
);
11324 tinsn_from_insnbuf (TInsn
*tinsn
,
11325 xtensa_insnbuf slotbuf
,
11330 xtensa_isa isa
= xtensa_default_isa
;
11332 /* Find the immed. */
11333 tinsn_init (tinsn
);
11334 tinsn
->insn_type
= ITYPE_INSN
;
11335 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11336 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11337 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11338 for (i
= 0; i
< tinsn
->ntok
; i
++)
11340 set_expr_const (&tinsn
->tok
[i
],
11341 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11342 tinsn
->opcode
, i
));
11347 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11350 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11352 xtensa_opcode opcode
= tinsn
->opcode
;
11355 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11357 opnum
= get_relaxable_immed (opcode
);
11358 assert (opnum
>= 0);
11359 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11360 fragP
->tc_frag_data
.slot_symbols
[slot
],
11361 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11367 get_num_stack_text_bytes (IStack
*istack
)
11370 int text_bytes
= 0;
11372 for (i
= 0; i
< istack
->ninsn
; i
++)
11374 TInsn
*tinsn
= &istack
->insn
[i
];
11375 if (tinsn
->insn_type
== ITYPE_INSN
)
11376 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11383 get_num_stack_literal_bytes (IStack
*istack
)
11388 for (i
= 0; i
< istack
->ninsn
; i
++)
11390 TInsn
*tinsn
= &istack
->insn
[i
];
11391 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11398 /* vliw_insn functions. */
11401 xg_init_vinsn (vliw_insn
*v
)
11404 xtensa_isa isa
= xtensa_default_isa
;
11406 xg_clear_vinsn (v
);
11408 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11409 if (v
->insnbuf
== NULL
)
11410 as_fatal (_("out of memory"));
11412 for (i
= 0; i
< MAX_SLOTS
; i
++)
11414 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11415 if (v
->slotbuf
[i
] == NULL
)
11416 as_fatal (_("out of memory"));
11422 xg_clear_vinsn (vliw_insn
*v
)
11426 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11428 v
->format
= XTENSA_UNDEFINED
;
11430 v
->inside_bundle
= FALSE
;
11432 if (xt_saved_debug_type
!= DEBUG_NONE
)
11433 debug_type
= xt_saved_debug_type
;
11435 for (i
= 0; i
< MAX_SLOTS
; i
++)
11436 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11441 vinsn_has_specific_opcodes (vliw_insn
*v
)
11445 for (i
= 0; i
< v
->num_slots
; i
++)
11447 if (v
->slots
[i
].is_specific_opcode
)
11455 xg_free_vinsn (vliw_insn
*v
)
11458 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11459 for (i
= 0; i
< MAX_SLOTS
; i
++)
11460 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11464 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11465 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11468 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11471 bfd_boolean record_fixup
)
11473 xtensa_isa isa
= xtensa_default_isa
;
11474 xtensa_format fmt
= vinsn
->format
;
11475 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11477 bfd_boolean has_fixup
= FALSE
;
11479 xtensa_format_encode (isa
, fmt
, insnbuf
);
11481 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11483 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11484 bfd_boolean tinsn_has_fixup
=
11485 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11486 vinsn
->slotbuf
[slot
]);
11488 xtensa_format_set_slot (isa
, fmt
, slot
,
11489 insnbuf
, vinsn
->slotbuf
[slot
]);
11490 if (tinsn_has_fixup
)
11493 xtensa_opcode opcode
= tinsn
->opcode
;
11494 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11497 for (i
= 0; i
< noperands
; i
++)
11499 expressionS
* expr
= &tinsn
->tok
[i
];
11500 switch (expr
->X_op
)
11505 if (get_relaxable_immed (opcode
) == i
)
11507 /* Add a fix record for the instruction, except if this
11508 function is being called prior to relaxation, i.e.,
11509 if record_fixup is false, and the instruction might
11510 be relaxed later. */
11512 || tinsn
->is_specific_opcode
11513 || !xg_is_relaxable_insn (tinsn
, 0))
11515 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11516 frag_offset
- fragP
->fr_literal
);
11520 if (expr
->X_op
!= O_symbol
)
11521 as_bad (_("invalid operand"));
11522 tinsn
->symbol
= expr
->X_add_symbol
;
11523 tinsn
->offset
= expr
->X_add_number
;
11527 as_bad (_("symbolic operand not allowed"));
11535 as_bad (_("expression too complex"));
11547 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11549 static xtensa_insnbuf insnbuf
= NULL
;
11550 static xtensa_insnbuf slotbuf
= NULL
;
11553 xtensa_isa isa
= xtensa_default_isa
;
11557 insnbuf
= xtensa_insnbuf_alloc (isa
);
11558 slotbuf
= xtensa_insnbuf_alloc (isa
);
11561 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11562 fmt
= xtensa_format_decode (isa
, insnbuf
);
11563 if (fmt
== XTENSA_UNDEFINED
)
11564 as_fatal (_("cannot decode instruction format"));
11565 vinsn
->format
= fmt
;
11566 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11568 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11570 TInsn
*tinsn
= &vinsn
->slots
[i
];
11571 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11572 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11577 /* Expression utilities. */
11579 /* Return TRUE if the expression is an integer constant. */
11582 expr_is_const (const expressionS
*s
)
11584 return (s
->X_op
== O_constant
);
11588 /* Get the expression constant.
11589 Calling this is illegal if expr_is_const () returns TRUE. */
11592 get_expr_const (const expressionS
*s
)
11594 assert (expr_is_const (s
));
11595 return s
->X_add_number
;
11599 /* Set the expression to a constant value. */
11602 set_expr_const (expressionS
*s
, offsetT val
)
11604 s
->X_op
= O_constant
;
11605 s
->X_add_number
= val
;
11606 s
->X_add_symbol
= NULL
;
11607 s
->X_op_symbol
= NULL
;
11612 expr_is_register (const expressionS
*s
)
11614 return (s
->X_op
== O_register
);
11618 /* Get the expression constant.
11619 Calling this is illegal if expr_is_const () returns TRUE. */
11622 get_expr_register (const expressionS
*s
)
11624 assert (expr_is_register (s
));
11625 return s
->X_add_number
;
11629 /* Set the expression to a symbol + constant offset. */
11632 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11634 s
->X_op
= O_symbol
;
11635 s
->X_add_symbol
= sym
;
11636 s
->X_op_symbol
= NULL
; /* unused */
11637 s
->X_add_number
= offset
;
11641 /* Return TRUE if the two expressions are equal. */
11644 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11646 if (s1
->X_op
!= s2
->X_op
)
11648 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11650 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11652 if (s1
->X_add_number
!= s2
->X_add_number
)
11659 copy_expr (expressionS
*dst
, const expressionS
*src
)
11661 memcpy (dst
, src
, sizeof (expressionS
));
11665 /* Support for the "--rename-section" option. */
11667 struct rename_section_struct
11671 struct rename_section_struct
*next
;
11674 static struct rename_section_struct
*section_rename
;
11677 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11678 entries to the section_rename list. Note: Specifying multiple
11679 renamings separated by colons is not documented and is retained only
11680 for backward compatibility. */
11683 build_section_rename (const char *arg
)
11685 struct rename_section_struct
*r
;
11686 char *this_arg
= NULL
;
11687 char *next_arg
= NULL
;
11689 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11691 char *old_name
, *new_name
;
11695 next_arg
= strchr (this_arg
, ':');
11703 old_name
= this_arg
;
11704 new_name
= strchr (this_arg
, '=');
11706 if (*old_name
== '\0')
11708 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11711 if (!new_name
|| new_name
[1] == '\0')
11713 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11720 /* Check for invalid section renaming. */
11721 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11723 if (strcmp (r
->old_name
, old_name
) == 0)
11724 as_bad (_("section %s renamed multiple times"), old_name
);
11725 if (strcmp (r
->new_name
, new_name
) == 0)
11726 as_bad (_("multiple sections remapped to output section %s"),
11731 r
= (struct rename_section_struct
*)
11732 xmalloc (sizeof (struct rename_section_struct
));
11733 r
->old_name
= xstrdup (old_name
);
11734 r
->new_name
= xstrdup (new_name
);
11735 r
->next
= section_rename
;
11736 section_rename
= r
;
11742 xtensa_section_rename (char *name
)
11744 struct rename_section_struct
*r
= section_rename
;
11746 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11748 if (strcmp (r
->old_name
, name
) == 0)
11749 return r
->new_name
;