1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2017 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
32 #include "elf/xtensa.h"
34 /* Provide default values for new configuration settings. */
40 #define uint32 unsigned int
43 #define int32 signed int
48 Naming conventions (used somewhat inconsistently):
49 The xtensa_ functions are exported
50 The xg_ functions are internal
52 We also have a couple of different extensibility mechanisms.
53 1) The idiom replacement:
54 This is used when a line is first parsed to
55 replace an instruction pattern with another instruction
56 It is currently limited to replacements of instructions
57 with constant operands.
58 2) The xtensa-relax.c mechanism that has stronger instruction
59 replacement patterns. When an instruction's immediate field
60 does not fit the next instruction sequence is attempted.
61 In addition, "narrow" opcodes are supported this way. */
64 /* Define characters with special meanings to GAS. */
65 const char comment_chars
[] = "#";
66 const char line_comment_chars
[] = "#";
67 const char line_separator_chars
[] = ";";
68 const char EXP_CHARS
[] = "eE";
69 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
72 /* Flags to indicate whether the hardware supports the density and
73 absolute literals options. */
75 bfd_boolean density_supported
;
76 bfd_boolean absolute_literals_supported
;
78 static vliw_insn cur_vinsn
;
80 unsigned xtensa_num_pipe_stages
;
81 unsigned xtensa_fetch_width
;
83 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
85 /* Some functions are only valid in the front end. This variable
86 allows us to assert that we haven't crossed over into the
88 static bfd_boolean past_xtensa_end
= FALSE
;
90 /* Flags for properties of the last instruction in a segment. */
91 #define FLAG_IS_A0_WRITER 0x1
92 #define FLAG_IS_BAD_LOOPEND 0x2
95 /* We define a special segment names ".literal" to place literals
96 into. The .fini and .init sections are special because they
97 contain code that is moved together by the linker. We give them
98 their own special .fini.literal and .init.literal sections. */
100 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
101 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
102 #define INIT_SECTION_NAME xtensa_section_rename (".init")
103 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. If lit_prefix is set, it is
108 used to determine the literal section names; otherwise, the literal
109 sections are determined based on the current text section. The
110 lit_seg and lit4_seg fields cache these literal sections, with the
111 current_text_seg field used a tag to indicate whether the cached
114 typedef struct lit_state_struct
117 segT current_text_seg
;
122 static lit_state default_lit_sections
;
125 /* We keep a list of literal segments. The seg_list type is the node
126 for this list. The literal_head pointer is the head of the list,
127 with the literal_head_h dummy node at the start. */
129 typedef struct seg_list_struct
131 struct seg_list_struct
*next
;
135 static seg_list literal_head_h
;
136 static seg_list
*literal_head
= &literal_head_h
;
139 /* Lists of symbols. We keep a list of symbols that label the current
140 instruction, so that we can adjust the symbols when inserting alignment
141 for various instructions. We also keep a list of all the symbols on
142 literals, so that we can fix up those symbols when the literals are
143 later moved into the text sections. */
145 typedef struct sym_list_struct
147 struct sym_list_struct
*next
;
151 static sym_list
*insn_labels
= NULL
;
152 static sym_list
*free_insn_labels
= NULL
;
153 static sym_list
*saved_insn_labels
= NULL
;
155 static sym_list
*literal_syms
;
158 /* Flags to determine whether to prefer const16 or l32r
159 if both options are available. */
160 int prefer_const16
= 0;
163 /* Global flag to indicate when we are emitting literals. */
164 int generating_literals
= 0;
166 /* The following PROPERTY table definitions are copied from
167 <elf/xtensa.h> and must be kept in sync with the code there. */
169 /* Flags in the property tables to specify whether blocks of memory
170 are literals, instructions, data, or unreachable. For
171 instructions, blocks that begin loop targets and branch targets are
172 designated. Blocks that do not allow density, instruction
173 reordering or transformation are also specified. Finally, for
174 branch targets, branch target alignment priority is included.
175 Alignment of the next block is specified in the current block
176 and the size of the current block does not include any fill required
177 to align to the next block. */
179 #define XTENSA_PROP_LITERAL 0x00000001
180 #define XTENSA_PROP_INSN 0x00000002
181 #define XTENSA_PROP_DATA 0x00000004
182 #define XTENSA_PROP_UNREACHABLE 0x00000008
183 /* Instruction only properties at beginning of code. */
184 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
185 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
186 /* Instruction only properties about code. */
187 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
188 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
189 /* Historically, NO_TRANSFORM was a property of instructions,
190 but it should apply to literals under certain circumstances. */
191 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
193 /* Branch target alignment information. This transmits information
194 to the linker optimization about the priority of aligning a
195 particular block for branch target alignment: None, low priority,
196 high priority, or required. These only need to be checked in
197 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
200 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
201 case XTENSA_PROP_BT_ALIGN_NONE:
202 case XTENSA_PROP_BT_ALIGN_LOW:
203 case XTENSA_PROP_BT_ALIGN_HIGH:
204 case XTENSA_PROP_BT_ALIGN_REQUIRE:
206 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
208 /* No branch target alignment. */
209 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
210 /* Low priority branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
212 /* High priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
214 /* Required branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
217 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
218 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
219 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
222 /* Alignment is specified in the block BEFORE the one that needs
223 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
224 get the required alignment specified as a power of 2. Use
225 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
226 alignment. Be careful of side effects since the SET will evaluate
227 flags twice. Also, note that the SIZE of a block in the property
228 table does not include the alignment size, so the alignment fill
229 must be calculated to determine if two blocks are contiguous.
230 TEXT_ALIGN is not currently implemented but is a placeholder for a
231 possible future implementation. */
233 #define XTENSA_PROP_ALIGN 0x00000800
235 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
237 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
238 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
239 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
241 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
244 /* Structure for saving instruction and alignment per-fragment data
245 that will be written to the object file. This structure is
246 equivalent to the actual data that will be written out to the file
247 but is easier to use. We provide a conversion to file flags
248 in frag_flags_to_number. */
250 typedef struct frag_flags_struct frag_flags
;
252 struct frag_flags_struct
254 /* is_literal should only be used after xtensa_move_literals.
255 If you need to check if you are generating a literal fragment,
256 then use the generating_literals global. */
258 unsigned is_literal
: 1;
259 unsigned is_insn
: 1;
260 unsigned is_data
: 1;
261 unsigned is_unreachable
: 1;
263 /* is_specific_opcode implies no_transform. */
264 unsigned is_no_transform
: 1;
268 unsigned is_loop_target
: 1;
269 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
270 unsigned bt_align_priority
: 2;
272 unsigned is_no_density
: 1;
273 /* no_longcalls flag does not need to be placed in the object file. */
275 unsigned is_no_reorder
: 1;
277 /* Uses absolute literal addressing for l32r. */
278 unsigned is_abslit
: 1;
280 unsigned is_align
: 1;
281 unsigned alignment
: 5;
285 /* Structure for saving information about a block of property data
286 for frags that have the same flags. */
287 struct xtensa_block_info_struct
293 struct xtensa_block_info_struct
*next
;
297 /* Structure for saving the current state before emitting literals. */
298 typedef struct emit_state_struct
303 int generating_literals
;
307 /* Opcode placement information */
309 typedef unsigned long long bitfield
;
310 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
311 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
312 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
314 #define MAX_FORMATS 32
316 typedef struct op_placement_info_struct
319 /* A number describing how restrictive the issue is for this
320 opcode. For example, an opcode that fits lots of different
321 formats has a high freedom, as does an opcode that fits
322 only one format but many slots in that format. The most
323 restrictive is the opcode that fits only one slot in one
326 xtensa_format narrowest
;
330 /* formats is a bitfield with the Nth bit set
331 if the opcode fits in the Nth xtensa_format. */
334 /* slots[N]'s Mth bit is set if the op fits in the
335 Mth slot of the Nth xtensa_format. */
336 bitfield slots
[MAX_FORMATS
];
338 /* A count of the number of slots in a given format
339 an op can fit (i.e., the bitcount of the slot field above). */
340 char slots_in_format
[MAX_FORMATS
];
342 } op_placement_info
, *op_placement_info_table
;
344 op_placement_info_table op_placement_table
;
347 /* Extra expression types. */
349 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
350 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
351 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
352 #define O_pcrel O_md4 /* value is a PC-relative offset */
353 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
354 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
355 #define O_tlscall O_md7 /* TLS_CALL relocation */
356 #define O_tpoff O_md8 /* TPOFF relocation */
357 #define O_dtpoff O_md9 /* DTPOFF relocation */
359 struct suffix_reloc_map
363 bfd_reloc_code_real_type reloc
;
367 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
369 static struct suffix_reloc_map suffix_relocs
[] =
371 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
372 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
373 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
374 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
375 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
376 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
377 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
378 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
379 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
393 directive_literal_prefix
,
395 directive_absolute_literals
,
396 directive_last_directive
402 bfd_boolean can_be_negated
;
405 const directive_infoS directive_info
[] =
408 { "literal", FALSE
},
410 { "transform", TRUE
},
411 { "freeregs", FALSE
},
412 { "longcalls", TRUE
},
413 { "literal_prefix", FALSE
},
414 { "schedule", TRUE
},
415 { "absolute-literals", TRUE
}
418 bfd_boolean directive_state
[] =
423 TRUE
, /* transform */
424 FALSE
, /* freeregs */
425 FALSE
, /* longcalls */
426 FALSE
, /* literal_prefix */
427 FALSE
, /* schedule */
428 FALSE
/* absolute_literals */
431 /* A circular list of all potential and actual literal pool locations
435 struct litpool_frag
*next
;
436 struct litpool_frag
*prev
;
439 short priority
; /* 1, 2, or 3 -- 1 is highest */
440 short original_priority
;
443 /* Map a segment to its litpool_frag list. */
446 struct litpool_seg
*next
;
448 struct litpool_frag frag_list
;
449 int frag_count
; /* since last litpool location */
452 static struct litpool_seg litpool_seg_list
;
455 /* Directive functions. */
457 static void xtensa_begin_directive (int);
458 static void xtensa_end_directive (int);
459 static void xtensa_literal_prefix (void);
460 static void xtensa_literal_position (int);
461 static void xtensa_literal_pseudo (int);
462 static void xtensa_frequency_pseudo (int);
463 static void xtensa_elf_cons (int);
464 static void xtensa_leb128 (int);
466 /* Parsing and Idiom Translation. */
468 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
470 /* Various Other Internal Functions. */
472 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
473 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
474 static void xtensa_mark_literal_pool_location (void);
475 static addressT
get_expanded_loop_offset (xtensa_opcode
);
476 static fragS
*get_literal_pool_location (segT
);
477 static void set_literal_pool_location (segT
, fragS
*);
478 static void xtensa_set_frag_assembly_state (fragS
*);
479 static void finish_vinsn (vliw_insn
*);
480 static bfd_boolean
emit_single_op (TInsn
*);
481 static int total_frag_text_expansion (fragS
*);
482 static bfd_boolean use_trampolines
= TRUE
;
483 static void xtensa_check_frag_count (void);
484 static void xtensa_create_trampoline_frag (bfd_boolean
);
485 static void xtensa_maybe_create_trampoline_frag (void);
486 struct trampoline_frag
;
487 static int init_trampoline_frag (struct trampoline_frag
*);
488 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
489 static bfd_boolean auto_litpools
= FALSE
;
490 static int auto_litpool_limit
= 10000;
492 /* Alignment Functions. */
494 static int get_text_align_power (unsigned);
495 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
496 static int branch_align_power (segT
);
498 /* Helpers for xtensa_relax_frag(). */
500 static long relax_frag_add_nop (fragS
*);
502 /* Accessors for additional per-subsegment information. */
504 static unsigned get_last_insn_flags (segT
, subsegT
);
505 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
506 static float get_subseg_total_freq (segT
, subsegT
);
507 static float get_subseg_target_freq (segT
, subsegT
);
508 static void set_subseg_freq (segT
, subsegT
, float, float);
510 /* Segment list functions. */
512 static void xtensa_move_literals (void);
513 static void xtensa_reorder_segments (void);
514 static void xtensa_switch_to_literal_fragment (emit_state
*);
515 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
516 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
517 static void xtensa_restore_emit_state (emit_state
*);
518 static segT
cache_literal_section (bfd_boolean
);
520 /* op_placement_info functions. */
522 static void init_op_placement_info_table (void);
523 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
524 static int xg_get_single_size (xtensa_opcode
);
525 static xtensa_format
xg_get_single_format (xtensa_opcode
);
526 static int xg_get_single_slot (xtensa_opcode
);
528 /* TInsn and IStack functions. */
530 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
531 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
532 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
533 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
534 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
535 static void tinsn_from_chars (TInsn
*, char *, int);
536 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
537 static int get_num_stack_text_bytes (IStack
*);
538 static int get_num_stack_literal_bytes (IStack
*);
539 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
541 /* vliw_insn functions. */
543 static void xg_init_vinsn (vliw_insn
*);
544 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
545 static void xg_clear_vinsn (vliw_insn
*);
546 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
547 static void xg_free_vinsn (vliw_insn
*);
548 static bfd_boolean vinsn_to_insnbuf
549 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
550 static void vinsn_from_chars (vliw_insn
*, char *);
552 /* Expression Utilities. */
554 bfd_boolean
expr_is_const (const expressionS
*);
555 offsetT
get_expr_const (const expressionS
*);
556 void set_expr_const (expressionS
*, offsetT
);
557 bfd_boolean
expr_is_register (const expressionS
*);
558 offsetT
get_expr_register (const expressionS
*);
559 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
560 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
561 static void copy_expr (expressionS
*, const expressionS
*);
563 /* Section renaming. */
565 static void build_section_rename (const char *);
568 /* ISA imported from bfd. */
569 extern xtensa_isa xtensa_default_isa
;
571 extern int target_big_endian
;
573 static xtensa_opcode xtensa_addi_opcode
;
574 static xtensa_opcode xtensa_addmi_opcode
;
575 static xtensa_opcode xtensa_call0_opcode
;
576 static xtensa_opcode xtensa_call4_opcode
;
577 static xtensa_opcode xtensa_call8_opcode
;
578 static xtensa_opcode xtensa_call12_opcode
;
579 static xtensa_opcode xtensa_callx0_opcode
;
580 static xtensa_opcode xtensa_callx4_opcode
;
581 static xtensa_opcode xtensa_callx8_opcode
;
582 static xtensa_opcode xtensa_callx12_opcode
;
583 static xtensa_opcode xtensa_const16_opcode
;
584 static xtensa_opcode xtensa_entry_opcode
;
585 static xtensa_opcode xtensa_extui_opcode
;
586 static xtensa_opcode xtensa_movi_opcode
;
587 static xtensa_opcode xtensa_movi_n_opcode
;
588 static xtensa_opcode xtensa_isync_opcode
;
589 static xtensa_opcode xtensa_j_opcode
;
590 static xtensa_opcode xtensa_jx_opcode
;
591 static xtensa_opcode xtensa_l32r_opcode
;
592 static xtensa_opcode xtensa_loop_opcode
;
593 static xtensa_opcode xtensa_loopnez_opcode
;
594 static xtensa_opcode xtensa_loopgtz_opcode
;
595 static xtensa_opcode xtensa_nop_opcode
;
596 static xtensa_opcode xtensa_nop_n_opcode
;
597 static xtensa_opcode xtensa_or_opcode
;
598 static xtensa_opcode xtensa_ret_opcode
;
599 static xtensa_opcode xtensa_ret_n_opcode
;
600 static xtensa_opcode xtensa_retw_opcode
;
601 static xtensa_opcode xtensa_retw_n_opcode
;
602 static xtensa_opcode xtensa_rsr_lcount_opcode
;
603 static xtensa_opcode xtensa_waiti_opcode
;
604 static int config_max_slots
= 0;
607 /* Command-line Options. */
609 bfd_boolean use_literal_section
= TRUE
;
610 enum flix_level produce_flix
= FLIX_ALL
;
611 static bfd_boolean align_targets
= TRUE
;
612 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
613 static bfd_boolean has_a0_b_retw
= FALSE
;
614 static bfd_boolean workaround_a0_b_retw
= FALSE
;
615 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
616 static bfd_boolean workaround_short_loop
= FALSE
;
617 static bfd_boolean maybe_has_short_loop
= FALSE
;
618 static bfd_boolean workaround_close_loop_end
= FALSE
;
619 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
620 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
622 /* When workaround_short_loops is TRUE, all loops with early exits must
623 have at least 3 instructions. workaround_all_short_loops is a modifier
624 to the workaround_short_loop flag. In addition to the
625 workaround_short_loop actions, all straightline loopgtz and loopnez
626 must have at least 3 instructions. */
628 static bfd_boolean workaround_all_short_loops
= FALSE
;
632 xtensa_setup_hw_workarounds (int earliest
, int latest
)
634 if (earliest
> latest
)
635 as_fatal (_("illegal range of target hardware versions"));
637 /* Enable all workarounds for pre-T1050.0 hardware. */
638 if (earliest
< 105000 || latest
< 105000)
640 workaround_a0_b_retw
|= TRUE
;
641 workaround_b_j_loop_end
|= TRUE
;
642 workaround_short_loop
|= TRUE
;
643 workaround_close_loop_end
|= TRUE
;
644 workaround_all_short_loops
|= TRUE
;
645 enforce_three_byte_loop_align
= TRUE
;
652 option_density
= OPTION_MD_BASE
,
656 option_no_generate_flix
,
663 option_no_link_relax
,
671 option_text_section_literals
,
672 option_no_text_section_literals
,
674 option_absolute_literals
,
675 option_no_absolute_literals
,
677 option_align_targets
,
678 option_no_align_targets
,
680 option_warn_unaligned_targets
,
685 option_workaround_a0_b_retw
,
686 option_no_workaround_a0_b_retw
,
688 option_workaround_b_j_loop_end
,
689 option_no_workaround_b_j_loop_end
,
691 option_workaround_short_loop
,
692 option_no_workaround_short_loop
,
694 option_workaround_all_short_loops
,
695 option_no_workaround_all_short_loops
,
697 option_workaround_close_loop_end
,
698 option_no_workaround_close_loop_end
,
700 option_no_workarounds
,
702 option_rename_section_name
,
705 option_prefer_const16
,
707 option_target_hardware
,
710 option_no_trampolines
,
712 option_auto_litpools
,
713 option_no_auto_litpools
,
714 option_auto_litpool_limit
,
717 const char *md_shortopts
= "";
719 struct option md_longopts
[] =
721 { "density", no_argument
, NULL
, option_density
},
722 { "no-density", no_argument
, NULL
, option_no_density
},
724 { "flix", no_argument
, NULL
, option_flix
},
725 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
726 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
728 /* Both "relax" and "generics" are deprecated and treated as equivalent
729 to the "transform" option. */
730 { "relax", no_argument
, NULL
, option_relax
},
731 { "no-relax", no_argument
, NULL
, option_no_relax
},
732 { "generics", no_argument
, NULL
, option_generics
},
733 { "no-generics", no_argument
, NULL
, option_no_generics
},
735 { "transform", no_argument
, NULL
, option_transform
},
736 { "no-transform", no_argument
, NULL
, option_no_transform
},
737 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
738 { "no-text-section-literals", no_argument
, NULL
,
739 option_no_text_section_literals
},
740 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
741 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
742 /* This option was changed from -align-target to -target-align
743 because it conflicted with the "-al" option. */
744 { "target-align", no_argument
, NULL
, option_align_targets
},
745 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
746 { "warn-unaligned-targets", no_argument
, NULL
,
747 option_warn_unaligned_targets
},
748 { "longcalls", no_argument
, NULL
, option_longcalls
},
749 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
751 { "no-workaround-a0-b-retw", no_argument
, NULL
,
752 option_no_workaround_a0_b_retw
},
753 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
755 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
756 option_no_workaround_b_j_loop_end
},
757 { "workaround-b-j-loop-end", no_argument
, NULL
,
758 option_workaround_b_j_loop_end
},
760 { "no-workaround-short-loops", no_argument
, NULL
,
761 option_no_workaround_short_loop
},
762 { "workaround-short-loops", no_argument
, NULL
,
763 option_workaround_short_loop
},
765 { "no-workaround-all-short-loops", no_argument
, NULL
,
766 option_no_workaround_all_short_loops
},
767 { "workaround-all-short-loop", no_argument
, NULL
,
768 option_workaround_all_short_loops
},
770 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
771 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
773 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
775 { "no-workaround-close-loop-end", no_argument
, NULL
,
776 option_no_workaround_close_loop_end
},
777 { "workaround-close-loop-end", no_argument
, NULL
,
778 option_workaround_close_loop_end
},
780 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
782 { "link-relax", no_argument
, NULL
, option_link_relax
},
783 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
785 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
787 { "trampolines", no_argument
, NULL
, option_trampolines
},
788 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
790 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
791 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
792 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
794 { NULL
, no_argument
, NULL
, 0 }
797 size_t md_longopts_size
= sizeof md_longopts
;
801 md_parse_option (int c
, const char *arg
)
806 as_warn (_("--density option is ignored"));
808 case option_no_density
:
809 as_warn (_("--no-density option is ignored"));
811 case option_link_relax
:
814 case option_no_link_relax
:
818 produce_flix
= FLIX_ALL
;
820 case option_no_generate_flix
:
821 produce_flix
= FLIX_NO_GENERATE
;
824 produce_flix
= FLIX_NONE
;
826 case option_generics
:
827 as_warn (_("--generics is deprecated; use --transform instead"));
828 return md_parse_option (option_transform
, arg
);
829 case option_no_generics
:
830 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
831 return md_parse_option (option_no_transform
, arg
);
833 as_warn (_("--relax is deprecated; use --transform instead"));
834 return md_parse_option (option_transform
, arg
);
835 case option_no_relax
:
836 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
837 return md_parse_option (option_no_transform
, arg
);
838 case option_longcalls
:
839 directive_state
[directive_longcalls
] = TRUE
;
841 case option_no_longcalls
:
842 directive_state
[directive_longcalls
] = FALSE
;
844 case option_text_section_literals
:
845 use_literal_section
= FALSE
;
847 case option_no_text_section_literals
:
848 use_literal_section
= TRUE
;
850 case option_absolute_literals
:
851 if (!absolute_literals_supported
)
853 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
856 directive_state
[directive_absolute_literals
] = TRUE
;
858 case option_no_absolute_literals
:
859 directive_state
[directive_absolute_literals
] = FALSE
;
862 case option_workaround_a0_b_retw
:
863 workaround_a0_b_retw
= TRUE
;
865 case option_no_workaround_a0_b_retw
:
866 workaround_a0_b_retw
= FALSE
;
868 case option_workaround_b_j_loop_end
:
869 workaround_b_j_loop_end
= TRUE
;
871 case option_no_workaround_b_j_loop_end
:
872 workaround_b_j_loop_end
= FALSE
;
875 case option_workaround_short_loop
:
876 workaround_short_loop
= TRUE
;
878 case option_no_workaround_short_loop
:
879 workaround_short_loop
= FALSE
;
882 case option_workaround_all_short_loops
:
883 workaround_all_short_loops
= TRUE
;
885 case option_no_workaround_all_short_loops
:
886 workaround_all_short_loops
= FALSE
;
889 case option_workaround_close_loop_end
:
890 workaround_close_loop_end
= TRUE
;
892 case option_no_workaround_close_loop_end
:
893 workaround_close_loop_end
= FALSE
;
896 case option_no_workarounds
:
897 workaround_a0_b_retw
= FALSE
;
898 workaround_b_j_loop_end
= FALSE
;
899 workaround_short_loop
= FALSE
;
900 workaround_all_short_loops
= FALSE
;
901 workaround_close_loop_end
= FALSE
;
904 case option_align_targets
:
905 align_targets
= TRUE
;
907 case option_no_align_targets
:
908 align_targets
= FALSE
;
911 case option_warn_unaligned_targets
:
912 warn_unaligned_branch_targets
= TRUE
;
915 case option_rename_section_name
:
916 build_section_rename (arg
);
920 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
921 should be emitted or not. FIXME: Not implemented. */
924 case option_prefer_l32r
:
926 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
930 case option_prefer_const16
:
932 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
936 case option_target_hardware
:
938 int earliest
, latest
= 0;
940 if (*arg
== 0 || *arg
== '-')
941 as_fatal (_("invalid target hardware version"));
943 earliest
= strtol (arg
, &end
, 0);
947 else if (*end
== '-')
950 as_fatal (_("invalid target hardware version"));
951 latest
= strtol (end
, &end
, 0);
954 as_fatal (_("invalid target hardware version"));
956 xtensa_setup_hw_workarounds (earliest
, latest
);
960 case option_transform
:
961 /* This option has no affect other than to use the defaults,
962 which are already set. */
965 case option_no_transform
:
966 /* This option turns off all transformations of any kind.
967 However, because we want to preserve the state of other
968 directives, we only change its own field. Thus, before
969 you perform any transformation, always check if transform
970 is available. If you use the functions we provide for this
971 purpose, you will be ok. */
972 directive_state
[directive_transform
] = FALSE
;
975 case option_trampolines
:
976 use_trampolines
= TRUE
;
979 case option_no_trampolines
:
980 use_trampolines
= FALSE
;
983 case option_auto_litpools
:
984 auto_litpools
= TRUE
;
985 use_literal_section
= FALSE
;
988 case option_no_auto_litpools
:
989 auto_litpools
= FALSE
;
990 auto_litpool_limit
= -1;
993 case option_auto_litpool_limit
:
997 if (auto_litpool_limit
< 0)
998 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
999 if (*arg
== 0 || *arg
== '-')
1000 as_fatal (_("invalid auto-litpool-limit argument"));
1001 value
= strtol (arg
, &end
, 10);
1003 as_fatal (_("invalid auto-litpool-limit argument"));
1004 if (value
< 100 || value
> 10000)
1005 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1006 auto_litpool_limit
= value
;
1007 auto_litpools
= TRUE
;
1008 use_literal_section
= FALSE
;
1019 md_show_usage (FILE *stream
)
1023 --[no-]text-section-literals\n\
1024 [Do not] put literals in the text section\n\
1025 --[no-]absolute-literals\n\
1026 [Do not] default to use non-PC-relative literals\n\
1027 --[no-]target-align [Do not] try to align branch targets\n\
1028 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1029 --[no-]transform [Do not] transform instructions\n\
1030 --flix both allow hand-written and generate flix bundles\n\
1031 --no-generate-flix allow hand-written but do not generate\n\
1033 --no-allow-flix neither allow hand-written nor generate\n\
1035 --rename-section old=new Rename section 'old' to 'new'\n\
1036 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1037 when jumps do not reach their targets\n\
1038 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1039 --auto-litpool-limit=<value>\n\
1040 (range 100-10000) Maximum number of blocks of\n\
1041 instructions to emit between literal pool\n\
1042 locations; implies --auto-litpools flag\n", stream
);
1046 /* Functions related to the list of current label symbols. */
1049 xtensa_add_insn_label (symbolS
*sym
)
1053 if (!free_insn_labels
)
1054 l
= XNEW (sym_list
);
1057 l
= free_insn_labels
;
1058 free_insn_labels
= l
->next
;
1062 l
->next
= insn_labels
;
1068 xtensa_clear_insn_labels (void)
1072 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1080 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1084 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1086 symbolS
*lit_sym
= lit
->sym
;
1087 S_SET_VALUE (lit_sym
, new_offset
);
1088 symbol_set_frag (lit_sym
, new_frag
);
1093 /* Directive data and functions. */
1095 typedef struct state_stackS_struct
1097 directiveE directive
;
1098 bfd_boolean negated
;
1099 bfd_boolean old_state
;
1103 struct state_stackS_struct
*prev
;
1106 state_stackS
*directive_state_stack
;
1108 const pseudo_typeS md_pseudo_table
[] =
1110 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1111 { "literal_position", xtensa_literal_position
, 0 },
1112 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1113 { "long", xtensa_elf_cons
, 4 },
1114 { "word", xtensa_elf_cons
, 4 },
1115 { "4byte", xtensa_elf_cons
, 4 },
1116 { "short", xtensa_elf_cons
, 2 },
1117 { "2byte", xtensa_elf_cons
, 2 },
1118 { "sleb128", xtensa_leb128
, 1},
1119 { "uleb128", xtensa_leb128
, 0},
1120 { "begin", xtensa_begin_directive
, 0 },
1121 { "end", xtensa_end_directive
, 0 },
1122 { "literal", xtensa_literal_pseudo
, 0 },
1123 { "frequency", xtensa_frequency_pseudo
, 0 },
1129 use_transform (void)
1131 /* After md_end, you should be checking frag by frag, rather
1132 than state directives. */
1133 gas_assert (!past_xtensa_end
);
1134 return directive_state
[directive_transform
];
1139 do_align_targets (void)
1141 /* Do not use this function after md_end; just look at align_targets
1142 instead. There is no target-align directive, so alignment is either
1143 enabled for all frags or not done at all. */
1144 gas_assert (!past_xtensa_end
);
1145 return align_targets
&& use_transform ();
1150 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1154 state_stackS
*stack
= XNEW (state_stackS
);
1156 file
= as_where (&line
);
1158 stack
->directive
= directive
;
1159 stack
->negated
= negated
;
1160 stack
->old_state
= directive_state
[directive
];
1163 stack
->datum
= datum
;
1164 stack
->prev
= directive_state_stack
;
1165 directive_state_stack
= stack
;
1167 directive_state
[directive
] = !negated
;
1172 directive_pop (directiveE
*directive
,
1173 bfd_boolean
*negated
,
1178 state_stackS
*top
= directive_state_stack
;
1180 if (!directive_state_stack
)
1182 as_bad (_("unmatched .end directive"));
1183 *directive
= directive_none
;
1187 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1188 *directive
= top
->directive
;
1189 *negated
= top
->negated
;
1192 *datum
= top
->datum
;
1193 directive_state_stack
= top
->prev
;
1199 directive_balance (void)
1201 while (directive_state_stack
)
1203 directiveE directive
;
1204 bfd_boolean negated
;
1209 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1210 as_warn_where ((char *) file
, line
,
1211 _(".begin directive with no matching .end directive"));
1217 inside_directive (directiveE dir
)
1219 state_stackS
*top
= directive_state_stack
;
1221 while (top
&& top
->directive
!= dir
)
1224 return (top
!= NULL
);
1229 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1233 const char *directive_string
;
1235 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1240 input_line_pointer
+= 3;
1243 len
= strspn (input_line_pointer
,
1244 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1246 /* This code is a hack to make .begin [no-][generics|relax] exactly
1247 equivalent to .begin [no-]transform. We should remove it when
1248 we stop accepting those options. */
1250 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1252 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1253 directive_string
= "transform";
1255 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1257 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1258 directive_string
= "transform";
1261 directive_string
= input_line_pointer
;
1263 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1265 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1267 input_line_pointer
+= len
;
1268 *directive
= (directiveE
) i
;
1269 if (*negated
&& !directive_info
[i
].can_be_negated
)
1270 as_bad (_("directive %s cannot be negated"),
1271 directive_info
[i
].name
);
1276 as_bad (_("unknown directive"));
1277 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1282 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1284 directiveE directive
;
1285 bfd_boolean negated
;
1289 get_directive (&directive
, &negated
);
1290 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1292 discard_rest_of_line ();
1296 if (cur_vinsn
.inside_bundle
)
1297 as_bad (_("directives are not valid inside bundles"));
1301 case directive_literal
:
1302 if (!inside_directive (directive_literal
))
1304 /* Previous labels go with whatever follows this directive, not with
1305 the literal, so save them now. */
1306 saved_insn_labels
= insn_labels
;
1309 as_warn (_(".begin literal is deprecated; use .literal instead"));
1310 state
= XNEW (emit_state
);
1311 xtensa_switch_to_literal_fragment (state
);
1312 directive_push (directive_literal
, negated
, state
);
1315 case directive_literal_prefix
:
1316 /* Have to flush pending output because a movi relaxed to an l32r
1317 might produce a literal. */
1318 md_flush_pending_output ();
1319 /* Check to see if the current fragment is a literal
1320 fragment. If it is, then this operation is not allowed. */
1321 if (generating_literals
)
1323 as_bad (_("cannot set literal_prefix inside literal fragment"));
1327 /* Allocate the literal state for this section and push
1328 onto the directive stack. */
1329 ls
= XNEW (lit_state
);
1332 *ls
= default_lit_sections
;
1333 directive_push (directive_literal_prefix
, negated
, ls
);
1335 /* Process the new prefix. */
1336 xtensa_literal_prefix ();
1339 case directive_freeregs
:
1340 /* This information is currently unused, but we'll accept the statement
1341 and just discard the rest of the line. This won't check the syntax,
1342 but it will accept every correct freeregs directive. */
1343 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1344 directive_push (directive_freeregs
, negated
, 0);
1347 case directive_schedule
:
1348 md_flush_pending_output ();
1349 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1350 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1351 directive_push (directive_schedule
, negated
, 0);
1352 xtensa_set_frag_assembly_state (frag_now
);
1355 case directive_density
:
1356 as_warn (_(".begin [no-]density is ignored"));
1359 case directive_absolute_literals
:
1360 md_flush_pending_output ();
1361 if (!absolute_literals_supported
&& !negated
)
1363 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1366 xtensa_set_frag_assembly_state (frag_now
);
1367 directive_push (directive
, negated
, 0);
1371 md_flush_pending_output ();
1372 xtensa_set_frag_assembly_state (frag_now
);
1373 directive_push (directive
, negated
, 0);
1377 demand_empty_rest_of_line ();
1382 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1384 directiveE begin_directive
, end_directive
;
1385 bfd_boolean begin_negated
, end_negated
;
1389 emit_state
**state_ptr
;
1392 if (cur_vinsn
.inside_bundle
)
1393 as_bad (_("directives are not valid inside bundles"));
1395 get_directive (&end_directive
, &end_negated
);
1397 md_flush_pending_output ();
1399 switch ((int) end_directive
)
1401 case XTENSA_UNDEFINED
:
1402 discard_rest_of_line ();
1405 case (int) directive_density
:
1406 as_warn (_(".end [no-]density is ignored"));
1407 demand_empty_rest_of_line ();
1410 case (int) directive_absolute_literals
:
1411 if (!absolute_literals_supported
&& !end_negated
)
1413 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1414 demand_empty_rest_of_line ();
1423 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1424 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1425 (const void **) state_ptr
);
1427 if (begin_directive
!= directive_none
)
1429 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1431 as_bad (_("does not match begin %s%s at %s:%d"),
1432 begin_negated
? "no-" : "",
1433 directive_info
[begin_directive
].name
, file
, line
);
1437 switch (end_directive
)
1439 case directive_literal
:
1440 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1441 xtensa_restore_emit_state (state
);
1442 xtensa_set_frag_assembly_state (frag_now
);
1444 if (!inside_directive (directive_literal
))
1446 /* Restore the list of current labels. */
1447 xtensa_clear_insn_labels ();
1448 insn_labels
= saved_insn_labels
;
1452 case directive_literal_prefix
:
1453 /* Restore the default collection sections from saved state. */
1454 s
= (lit_state
*) state
;
1456 default_lit_sections
= *s
;
1458 /* Free the state storage. */
1459 free (s
->lit_prefix
);
1463 case directive_schedule
:
1464 case directive_freeregs
:
1468 xtensa_set_frag_assembly_state (frag_now
);
1474 demand_empty_rest_of_line ();
1478 /* Place an aligned literal fragment at the current location. */
1481 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1483 md_flush_pending_output ();
1485 if (inside_directive (directive_literal
))
1486 as_warn (_(".literal_position inside literal directive; ignoring"));
1487 xtensa_mark_literal_pool_location ();
1489 demand_empty_rest_of_line ();
1490 xtensa_clear_insn_labels ();
1494 /* Support .literal label, expr, ... */
1497 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1500 char *p
, *base_name
;
1504 if (inside_directive (directive_literal
))
1506 as_bad (_(".literal not allowed inside .begin literal region"));
1507 ignore_rest_of_line ();
1511 md_flush_pending_output ();
1513 /* Previous labels go with whatever follows this directive, not with
1514 the literal, so save them now. */
1515 saved_insn_labels
= insn_labels
;
1518 /* If we are using text-section literals, then this is the right value... */
1521 base_name
= input_line_pointer
;
1523 xtensa_switch_to_literal_fragment (&state
);
1525 /* ...but if we aren't using text-section-literals, then we
1526 need to put them in the section we just switched to. */
1527 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1530 /* FIXME, despite the previous comments, dest_seg is unused... */
1533 /* All literals are aligned to four-byte boundaries. */
1534 frag_align (2, 0, 0);
1535 record_alignment (now_seg
, 2);
1537 c
= get_symbol_name (&base_name
);
1538 /* Just after name is now '\0'. */
1539 p
= input_line_pointer
;
1541 SKIP_WHITESPACE_AFTER_NAME ();
1543 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1545 as_bad (_("expected comma or colon after symbol name; "
1546 "rest of line ignored"));
1547 ignore_rest_of_line ();
1548 xtensa_restore_emit_state (&state
);
1556 input_line_pointer
++; /* skip ',' or ':' */
1558 xtensa_elf_cons (4);
1560 xtensa_restore_emit_state (&state
);
1562 /* Restore the list of current labels. */
1563 xtensa_clear_insn_labels ();
1564 insn_labels
= saved_insn_labels
;
1569 xtensa_literal_prefix (void)
1574 /* Parse the new prefix from the input_line_pointer. */
1576 len
= strspn (input_line_pointer
,
1577 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1578 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1580 /* Get a null-terminated copy of the name. */
1581 name
= xmemdup0 (input_line_pointer
, len
);
1583 /* Skip the name in the input line. */
1584 input_line_pointer
+= len
;
1586 default_lit_sections
.lit_prefix
= name
;
1588 /* Clear cached literal sections, since the prefix has changed. */
1589 default_lit_sections
.lit_seg
= NULL
;
1590 default_lit_sections
.lit4_seg
= NULL
;
1594 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1597 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1599 float fall_through_f
, target_f
;
1601 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1602 if (fall_through_f
< 0)
1604 as_bad (_("fall through frequency must be greater than 0"));
1605 ignore_rest_of_line ();
1609 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1612 as_bad (_("branch target frequency must be greater than 0"));
1613 ignore_rest_of_line ();
1617 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1619 demand_empty_rest_of_line ();
1623 /* Like normal .long/.short/.word, except support @plt, etc.
1624 Clobbers input_line_pointer, checks end-of-line. */
1627 xtensa_elf_cons (int nbytes
)
1630 bfd_reloc_code_real_type reloc
;
1632 md_flush_pending_output ();
1634 if (cur_vinsn
.inside_bundle
)
1635 as_bad (_("directives are not valid inside bundles"));
1637 if (is_it_end_of_statement ())
1639 demand_empty_rest_of_line ();
1646 if (exp
.X_op
== O_symbol
1647 && *input_line_pointer
== '@'
1648 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1651 reloc_howto_type
*reloc_howto
=
1652 bfd_reloc_type_lookup (stdoutput
, reloc
);
1654 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1655 as_bad (_("unsupported relocation"));
1656 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1657 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1658 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1659 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1660 as_bad (_("opcode-specific %s relocation used outside "
1661 "an instruction"), reloc_howto
->name
);
1662 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1663 as_bad (_("%s relocations do not fit in %d bytes"),
1664 reloc_howto
->name
, nbytes
);
1665 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1666 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1667 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1668 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1671 char *p
= frag_more ((int) nbytes
);
1672 xtensa_set_frag_assembly_state (frag_now
);
1673 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1674 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1679 xtensa_set_frag_assembly_state (frag_now
);
1680 emit_expr (&exp
, (unsigned int) nbytes
);
1683 while (*input_line_pointer
++ == ',');
1685 input_line_pointer
--; /* Put terminator back into stream. */
1686 demand_empty_rest_of_line ();
1689 static bfd_boolean is_leb128_expr
;
1692 xtensa_leb128 (int sign
)
1694 is_leb128_expr
= TRUE
;
1696 is_leb128_expr
= FALSE
;
1700 /* Parsing and Idiom Translation. */
1702 /* Parse @plt, etc. and return the desired relocation. */
1703 static bfd_reloc_code_real_type
1704 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1714 return BFD_RELOC_NONE
;
1716 for (ch
= *str
, str2
= ident
;
1717 (str2
< ident
+ sizeof (ident
) - 1
1718 && (ISALNUM (ch
) || ch
== '@'));
1721 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1728 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1729 if (ch
== suffix_relocs
[i
].suffix
[0]
1730 && len
== suffix_relocs
[i
].length
1731 && memcmp (ident
, suffix_relocs
[i
].suffix
, suffix_relocs
[i
].length
) == 0)
1733 /* Now check for "identifier@suffix+constant". */
1734 if (*str
== '-' || *str
== '+')
1736 char *orig_line
= input_line_pointer
;
1737 expressionS new_exp
;
1739 input_line_pointer
= str
;
1740 expression (&new_exp
);
1741 if (new_exp
.X_op
== O_constant
)
1743 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1744 str
= input_line_pointer
;
1747 if (&input_line_pointer
!= str_p
)
1748 input_line_pointer
= orig_line
;
1752 return suffix_relocs
[i
].reloc
;
1755 return BFD_RELOC_UNUSED
;
1759 /* Find the matching operator type. */
1761 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1763 operatorT
operator = O_illegal
;
1766 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1768 if (suffix_relocs
[i
].reloc
== reloc
)
1770 operator = suffix_relocs
[i
].operator;
1774 gas_assert (operator != O_illegal
);
1779 /* Find the matching reloc type. */
1780 static bfd_reloc_code_real_type
1781 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1784 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1786 for (i
= 0; i
< ARRAY_SIZE (suffix_relocs
); i
++)
1788 if (suffix_relocs
[i
].operator == operator)
1790 reloc
= suffix_relocs
[i
].reloc
;
1797 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1798 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1799 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1800 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1803 if (reloc
== BFD_RELOC_UNUSED
)
1804 return BFD_RELOC_32
;
1811 expression_end (const char *name
)
1834 #define ERROR_REG_NUM ((unsigned) -1)
1837 tc_get_register (const char *prefix
)
1840 const char *next_expr
;
1841 const char *old_line_pointer
;
1844 old_line_pointer
= input_line_pointer
;
1846 if (*input_line_pointer
== '$')
1847 ++input_line_pointer
;
1849 /* Accept "sp" as a synonym for "a1". */
1850 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1851 && expression_end (input_line_pointer
+ 2))
1853 input_line_pointer
+= 2;
1854 return 1; /* AR[1] */
1857 while (*input_line_pointer
++ == *prefix
++)
1859 --input_line_pointer
;
1864 as_bad (_("bad register name: %s"), old_line_pointer
);
1865 return ERROR_REG_NUM
;
1868 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1870 as_bad (_("bad register number: %s"), input_line_pointer
);
1871 return ERROR_REG_NUM
;
1876 while (ISDIGIT ((int) *input_line_pointer
))
1877 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1879 if (!(next_expr
= expression_end (input_line_pointer
)))
1881 as_bad (_("bad register name: %s"), old_line_pointer
);
1882 return ERROR_REG_NUM
;
1885 input_line_pointer
= (char *) next_expr
;
1892 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1894 xtensa_isa isa
= xtensa_default_isa
;
1896 /* Check if this is an immediate operand. */
1897 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1899 bfd_reloc_code_real_type reloc
;
1900 segT t
= expression (tok
);
1902 if (t
== absolute_section
1903 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1905 gas_assert (tok
->X_op
== O_constant
);
1906 tok
->X_op
= O_symbol
;
1907 tok
->X_add_symbol
= &abs_symbol
;
1910 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1911 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1916 case BFD_RELOC_LO16
:
1917 if (tok
->X_op
== O_constant
)
1919 tok
->X_add_number
&= 0xffff;
1923 case BFD_RELOC_HI16
:
1924 if (tok
->X_op
== O_constant
)
1926 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1930 case BFD_RELOC_UNUSED
:
1931 as_bad (_("unsupported relocation"));
1933 case BFD_RELOC_32_PCREL
:
1934 as_bad (_("pcrel relocation not allowed in an instruction"));
1939 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1944 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1945 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1947 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1950 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1951 as_bad (_("register number out of range"));
1954 tok
->X_op
= O_register
;
1955 tok
->X_add_symbol
= 0;
1956 tok
->X_add_number
= reg
;
1961 /* Split up the arguments for an opcode or pseudo-op. */
1964 tokenize_arguments (char **args
, char *str
)
1966 char *old_input_line_pointer
;
1967 bfd_boolean saw_comma
= FALSE
;
1968 bfd_boolean saw_arg
= FALSE
;
1969 bfd_boolean saw_colon
= FALSE
;
1971 char *arg_end
, *arg
;
1974 /* Save and restore input_line_pointer around this function. */
1975 old_input_line_pointer
= input_line_pointer
;
1976 input_line_pointer
= str
;
1978 while (*input_line_pointer
)
1981 switch (*input_line_pointer
)
1988 input_line_pointer
++;
1989 if (saw_comma
|| saw_colon
|| !saw_arg
)
1995 input_line_pointer
++;
1996 if (saw_comma
|| saw_colon
|| !saw_arg
)
2002 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2005 arg_end
= input_line_pointer
+ 1;
2006 while (!expression_end (arg_end
))
2009 arg_len
= arg_end
- input_line_pointer
;
2010 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2011 args
[num_args
] = arg
;
2015 strncpy (arg
, input_line_pointer
, arg_len
);
2016 arg
[arg_len
] = '\0';
2018 input_line_pointer
= arg_end
;
2028 if (saw_comma
|| saw_colon
)
2030 input_line_pointer
= old_input_line_pointer
;
2035 as_bad (_("extra comma"));
2037 as_bad (_("extra colon"));
2039 as_bad (_("missing argument"));
2041 as_bad (_("missing comma or colon"));
2042 input_line_pointer
= old_input_line_pointer
;
2047 /* Parse the arguments to an opcode. Return TRUE on error. */
2050 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2052 expressionS
*tok
, *last_tok
;
2053 xtensa_opcode opcode
= insn
->opcode
;
2054 bfd_boolean had_error
= TRUE
;
2055 xtensa_isa isa
= xtensa_default_isa
;
2056 int n
, num_regs
= 0;
2057 int opcode_operand_count
;
2058 int opnd_cnt
, last_opnd_cnt
;
2059 unsigned int next_reg
= 0;
2060 char *old_input_line_pointer
;
2062 if (insn
->insn_type
== ITYPE_LITERAL
)
2063 opcode_operand_count
= 1;
2065 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2068 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2070 /* Save and restore input_line_pointer around this function. */
2071 old_input_line_pointer
= input_line_pointer
;
2077 /* Skip invisible operands. */
2078 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2084 for (n
= 0; n
< num_args
; n
++)
2086 input_line_pointer
= arg_strings
[n
];
2087 if (*input_line_pointer
== ':')
2089 xtensa_regfile opnd_rf
;
2090 input_line_pointer
++;
2093 gas_assert (opnd_cnt
> 0);
2095 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2097 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2098 as_warn (_("incorrect register number, ignoring"));
2103 if (opnd_cnt
>= opcode_operand_count
)
2105 as_warn (_("too many arguments"));
2108 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2110 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2111 next_reg
= tok
->X_add_number
+ 1;
2113 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2115 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2117 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2118 /* minus 1 because we are seeing one right now */
2124 last_opnd_cnt
= opnd_cnt
;
2125 demand_empty_rest_of_line ();
2132 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2136 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2139 insn
->ntok
= tok
- insn
->tok
;
2143 input_line_pointer
= old_input_line_pointer
;
2149 get_invisible_operands (TInsn
*insn
)
2151 xtensa_isa isa
= xtensa_default_isa
;
2152 static xtensa_insnbuf slotbuf
= NULL
;
2154 xtensa_opcode opc
= insn
->opcode
;
2155 int slot
, opnd
, fmt_found
;
2159 slotbuf
= xtensa_insnbuf_alloc (isa
);
2161 /* Find format/slot where this can be encoded. */
2164 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2166 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2168 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2174 if (fmt_found
) break;
2179 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2183 /* First encode all the visible operands
2184 (to deal with shared field operands). */
2185 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2187 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2188 && (insn
->tok
[opnd
].X_op
== O_register
2189 || insn
->tok
[opnd
].X_op
== O_constant
))
2191 val
= insn
->tok
[opnd
].X_add_number
;
2192 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2193 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2197 /* Then pull out the values for the invisible ones. */
2198 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2200 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2202 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2203 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2204 insn
->tok
[opnd
].X_add_number
= val
;
2205 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2206 insn
->tok
[opnd
].X_op
= O_register
;
2208 insn
->tok
[opnd
].X_op
= O_constant
;
2217 xg_reverse_shift_count (char **cnt_argp
)
2219 char *cnt_arg
, *new_arg
;
2220 cnt_arg
= *cnt_argp
;
2222 /* replace the argument with "31-(argument)" */
2223 new_arg
= concat ("31-(", cnt_arg
, ")", (char *) NULL
);
2226 *cnt_argp
= new_arg
;
2230 /* If "arg" is a constant expression, return non-zero with the value
2234 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2237 char *save_ptr
= input_line_pointer
;
2239 input_line_pointer
= arg
;
2241 input_line_pointer
= save_ptr
;
2243 if (exp
.X_op
== O_constant
)
2245 *valp
= exp
.X_add_number
;
2254 xg_replace_opname (char **popname
, const char *newop
)
2257 *popname
= xstrdup (newop
);
2262 xg_check_num_args (int *pnum_args
,
2267 int num_args
= *pnum_args
;
2269 if (num_args
< expected_num
)
2271 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2272 num_args
, opname
, expected_num
);
2276 if (num_args
> expected_num
)
2278 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2279 num_args
, opname
, expected_num
);
2280 while (num_args
-- > expected_num
)
2282 free (arg_strings
[num_args
]);
2283 arg_strings
[num_args
] = 0;
2285 *pnum_args
= expected_num
;
2293 /* If the register is not specified as part of the opcode,
2294 then get it from the operand and move it to the opcode. */
2297 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2299 xtensa_isa isa
= xtensa_default_isa
;
2301 char *opname
, *new_opname
;
2302 const char *sr_name
;
2303 int is_user
, is_write
;
2308 is_user
= (opname
[1] == 'u');
2309 is_write
= (opname
[0] == 'w');
2311 /* Opname == [rw]ur or [rwx]sr... */
2313 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2316 /* Check if the argument is a symbolic register name. */
2317 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2318 /* Handle WSR to "INTSET" as a special case. */
2319 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2320 && !strcasecmp (arg_strings
[1], "intset"))
2321 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2322 if (sr
== XTENSA_UNDEFINED
2323 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2325 /* Maybe it's a register number.... */
2327 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2329 as_bad (_("invalid register '%s' for '%s' instruction"),
2330 arg_strings
[1], opname
);
2333 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2334 if (sr
== XTENSA_UNDEFINED
)
2336 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2337 (long) val
, opname
);
2342 /* Remove the last argument, which is now part of the opcode. */
2343 free (arg_strings
[1]);
2347 /* Translate the opcode. */
2348 sr_name
= xtensa_sysreg_name (isa
, sr
);
2349 /* Another special case for "WSR.INTSET".... */
2350 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2352 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2354 *popname
= new_opname
;
2361 xtensa_translate_old_userreg_ops (char **popname
)
2363 xtensa_isa isa
= xtensa_default_isa
;
2365 char *opname
, *new_opname
;
2366 const char *sr_name
;
2367 bfd_boolean has_underbar
= FALSE
;
2370 if (opname
[0] == '_')
2372 has_underbar
= TRUE
;
2376 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2377 if (sr
!= XTENSA_UNDEFINED
)
2379 /* The new default name ("nnn") is different from the old default
2380 name ("URnnn"). The old default is handled below, and we don't
2381 want to recognize [RW]nnn, so do nothing if the name is the (new)
2383 static char namebuf
[10];
2384 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2385 if (strcmp (namebuf
, opname
+ 1) == 0)
2393 /* Only continue if the reg name is "URnnn". */
2394 if (opname
[1] != 'u' || opname
[2] != 'r')
2396 val
= strtoul (opname
+ 3, &end
, 10);
2400 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2401 if (sr
== XTENSA_UNDEFINED
)
2403 as_bad (_("invalid register number (%ld) for '%s'"),
2404 (long) val
, opname
);
2409 /* Translate the opcode. */
2410 sr_name
= xtensa_sysreg_name (isa
, sr
);
2411 new_opname
= XNEWVEC (char, strlen (sr_name
) + 6);
2412 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2413 opname
[0], sr_name
);
2415 *popname
= new_opname
;
2422 xtensa_translate_zero_immed (const char *old_op
,
2432 gas_assert (opname
[0] != '_');
2434 if (strcmp (opname
, old_op
) != 0)
2437 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2439 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2441 xg_replace_opname (popname
, new_op
);
2442 free (arg_strings
[1]);
2443 arg_strings
[1] = arg_strings
[2];
2452 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2453 Returns non-zero if an error was found. */
2456 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2458 char *opname
= *popname
;
2459 bfd_boolean has_underbar
= FALSE
;
2463 has_underbar
= TRUE
;
2467 if (strcmp (opname
, "mov") == 0)
2469 if (use_transform () && !has_underbar
&& density_supported
)
2470 xg_replace_opname (popname
, "mov.n");
2473 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2475 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2476 arg_strings
[2] = xstrdup (arg_strings
[1]);
2482 if (strcmp (opname
, "bbsi.l") == 0)
2484 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2486 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2487 if (target_big_endian
)
2488 xg_reverse_shift_count (&arg_strings
[1]);
2492 if (strcmp (opname
, "bbci.l") == 0)
2494 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2496 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2497 if (target_big_endian
)
2498 xg_reverse_shift_count (&arg_strings
[1]);
2502 /* Don't do anything special with NOPs inside FLIX instructions. They
2503 are handled elsewhere. Real NOP instructions are always available
2504 in configurations with FLIX, so this should never be an issue but
2505 check for it anyway. */
2506 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2507 && strcmp (opname
, "nop") == 0)
2509 if (use_transform () && !has_underbar
&& density_supported
)
2510 xg_replace_opname (popname
, "nop.n");
2513 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2515 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2516 arg_strings
[0] = xstrdup ("a1");
2517 arg_strings
[1] = xstrdup ("a1");
2518 arg_strings
[2] = xstrdup ("a1");
2524 /* Recognize [RW]UR and [RWX]SR. */
2525 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2526 && (opname
[1] == 'u' || opname
[1] == 's'))
2527 || (opname
[0] == 'x' && opname
[1] == 's'))
2529 && opname
[3] == '\0')
2530 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2532 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2533 [RW]<name> if <name> is the non-default name of a user register. */
2534 if ((opname
[0] == 'r' || opname
[0] == 'w')
2535 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2536 return xtensa_translate_old_userreg_ops (popname
);
2538 /* Relax branches that don't allow comparisons against an immediate value
2539 of zero to the corresponding branches with implicit zero immediates. */
2540 if (!has_underbar
&& use_transform ())
2542 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2543 pnum_args
, arg_strings
))
2546 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2547 pnum_args
, arg_strings
))
2550 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2551 pnum_args
, arg_strings
))
2554 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2555 pnum_args
, arg_strings
))
2563 /* Functions for dealing with the Xtensa ISA. */
2565 /* Currently the assembler only allows us to use a single target per
2566 fragment. Because of this, only one operand for a given
2567 instruction may be symbolic. If there is a PC-relative operand,
2568 the last one is chosen. Otherwise, the result is the number of the
2569 last immediate operand, and if there are none of those, we fail and
2573 get_relaxable_immed (xtensa_opcode opcode
)
2575 int last_immed
= -1;
2578 if (opcode
== XTENSA_UNDEFINED
)
2581 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2582 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2584 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2586 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2588 if (last_immed
== -1
2589 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2596 static xtensa_opcode
2597 get_opcode_from_buf (const char *buf
, int slot
)
2599 static xtensa_insnbuf insnbuf
= NULL
;
2600 static xtensa_insnbuf slotbuf
= NULL
;
2601 xtensa_isa isa
= xtensa_default_isa
;
2606 insnbuf
= xtensa_insnbuf_alloc (isa
);
2607 slotbuf
= xtensa_insnbuf_alloc (isa
);
2610 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2611 fmt
= xtensa_format_decode (isa
, insnbuf
);
2612 if (fmt
== XTENSA_UNDEFINED
)
2613 return XTENSA_UNDEFINED
;
2615 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2616 return XTENSA_UNDEFINED
;
2618 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2619 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2623 #ifdef TENSILICA_DEBUG
2625 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2628 xtensa_print_insn_table (void)
2630 int num_opcodes
, num_operands
;
2631 xtensa_opcode opcode
;
2632 xtensa_isa isa
= xtensa_default_isa
;
2634 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2635 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2638 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2639 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2640 for (opn
= 0; opn
< num_operands
; opn
++)
2642 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2644 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2646 xtensa_regfile opnd_rf
=
2647 xtensa_operand_regfile (isa
, opcode
, opn
);
2648 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2650 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2651 fputs ("[lLr] ", stderr
);
2653 fputs ("i ", stderr
);
2655 fprintf (stderr
, "\n");
2661 print_vliw_insn (xtensa_insnbuf vbuf
)
2663 xtensa_isa isa
= xtensa_default_isa
;
2664 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2665 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2668 fprintf (stderr
, "format = %d\n", f
);
2670 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2672 xtensa_opcode opcode
;
2676 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2677 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2678 opname
= xtensa_opcode_name (isa
, opcode
);
2680 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2681 fprintf (stderr
, " operands = ");
2683 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2687 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2689 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2690 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2691 fprintf (stderr
, "%d ", val
);
2693 fprintf (stderr
, "\n");
2695 xtensa_insnbuf_free (isa
, sbuf
);
2698 #endif /* TENSILICA_DEBUG */
2702 is_direct_call_opcode (xtensa_opcode opcode
)
2704 xtensa_isa isa
= xtensa_default_isa
;
2705 int n
, num_operands
;
2707 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2710 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2711 for (n
= 0; n
< num_operands
; n
++)
2713 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2714 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2721 /* Convert from BFD relocation type code to slot and operand number.
2722 Returns non-zero on failure. */
2725 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2727 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2728 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2730 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2733 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2734 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2736 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2746 /* Convert from slot number to BFD relocation type code for the
2747 standard PC-relative relocations. Return BFD_RELOC_NONE on
2750 static bfd_reloc_code_real_type
2751 encode_reloc (int slot
)
2753 if (slot
< 0 || slot
> 14)
2754 return BFD_RELOC_NONE
;
2756 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2760 /* Convert from slot numbers to BFD relocation type code for the
2761 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2763 static bfd_reloc_code_real_type
2764 encode_alt_reloc (int slot
)
2766 if (slot
< 0 || slot
> 14)
2767 return BFD_RELOC_NONE
;
2769 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2774 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2777 xtensa_opcode opcode
,
2783 uint32 valbuf
= value
;
2785 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2787 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2789 as_bad_where ((char *) file
, line
,
2790 _("operand %d of '%s' has out of range value '%u'"),
2792 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2795 as_bad_where ((char *) file
, line
,
2796 _("operand %d of '%s' has invalid value '%u'"),
2798 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2803 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2809 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2812 xtensa_opcode opcode
,
2816 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2817 fmt
, slot
, slotbuf
, &val
);
2818 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2823 /* Checks for rules from xtensa-relax tables. */
2825 /* The routine xg_instruction_matches_option_term must return TRUE
2826 when a given option term is true. The meaning of all of the option
2827 terms is given interpretation by this function. */
2830 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2832 if (strcmp (option
->option_name
, "realnop") == 0
2833 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2835 /* These conditions were evaluated statically when building the
2836 relaxation table. There's no need to reevaluate them now. */
2839 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2840 return insn
->extra_arg
.X_op
== O_register
;
2843 as_fatal (_("internal error: unknown option name '%s'"),
2844 option
->option_name
);
2850 xg_instruction_matches_or_options (TInsn
*insn
,
2851 const ReqOrOptionList
*or_option
)
2853 const ReqOrOption
*option
;
2854 /* Must match each of the AND terms. */
2855 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2857 if (xg_instruction_matches_option_term (insn
, option
))
2865 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2867 const ReqOption
*req_options
;
2868 /* Must match each of the AND terms. */
2869 for (req_options
= options
;
2870 req_options
!= NULL
;
2871 req_options
= req_options
->next
)
2873 /* Must match one of the OR clauses. */
2874 if (!xg_instruction_matches_or_options (insn
,
2875 req_options
->or_option_terms
))
2882 /* Return the transition rule that matches or NULL if none matches. */
2885 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2887 PreconditionList
*condition_l
;
2889 if (rule
->opcode
!= insn
->opcode
)
2892 for (condition_l
= rule
->conditions
;
2893 condition_l
!= NULL
;
2894 condition_l
= condition_l
->next
)
2898 Precondition
*cond
= condition_l
->precond
;
2903 /* The expression must be the constant. */
2904 gas_assert (cond
->op_num
< insn
->ntok
);
2905 exp1
= &insn
->tok
[cond
->op_num
];
2906 if (expr_is_const (exp1
))
2911 if (get_expr_const (exp1
) != cond
->op_data
)
2915 if (get_expr_const (exp1
) == cond
->op_data
)
2922 else if (expr_is_register (exp1
))
2927 if (get_expr_register (exp1
) != cond
->op_data
)
2931 if (get_expr_register (exp1
) == cond
->op_data
)
2943 gas_assert (cond
->op_num
< insn
->ntok
);
2944 gas_assert (cond
->op_data
< insn
->ntok
);
2945 exp1
= &insn
->tok
[cond
->op_num
];
2946 exp2
= &insn
->tok
[cond
->op_data
];
2951 if (!expr_is_equal (exp1
, exp2
))
2955 if (expr_is_equal (exp1
, exp2
))
2967 if (!xg_instruction_matches_options (insn
, rule
->options
))
2975 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2977 bfd_boolean a_greater
= FALSE
;
2978 bfd_boolean b_greater
= FALSE
;
2980 ReqOptionList
*l_a
= a
->options
;
2981 ReqOptionList
*l_b
= b
->options
;
2983 /* We only care if they both are the same except for
2984 a const16 vs. an l32r. */
2986 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2988 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2989 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2990 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2992 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2994 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2996 /* This is the case we care about. */
2997 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2998 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3005 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3006 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3016 l_or_a
= l_or_a
->next
;
3017 l_or_b
= l_or_b
->next
;
3019 if (l_or_a
|| l_or_b
)
3028 /* Incomparable if the substitution was used differently in two cases. */
3029 if (a_greater
&& b_greater
)
3041 static TransitionRule
*
3042 xg_instruction_match (TInsn
*insn
)
3044 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3046 gas_assert (insn
->opcode
< table
->num_opcodes
);
3048 /* Walk through all of the possible transitions. */
3049 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3051 TransitionRule
*rule
= l
->rule
;
3052 if (xg_instruction_matches_rule (insn
, rule
))
3059 /* Various Other Internal Functions. */
3062 is_unique_insn_expansion (TransitionRule
*r
)
3064 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3066 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3072 /* Check if there is exactly one relaxation for INSN that converts it to
3073 another instruction of equal or larger size. If so, and if TARG is
3074 non-null, go ahead and generate the relaxed instruction into TARG. If
3075 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3076 instruction, i.e., ignore relaxations that convert to an instruction of
3077 equal size. In some contexts where this function is used, only
3078 a single widening is allowed and the NARROW_ONLY argument is used to
3079 exclude cases like ADDI being "widened" to an ADDMI, which may
3080 later be relaxed to an ADDMI/ADDI pair. */
3083 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3085 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3087 TransitionRule
*match
= 0;
3089 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3090 gas_assert (insn
->opcode
< table
->num_opcodes
);
3092 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3094 TransitionRule
*rule
= l
->rule
;
3096 if (xg_instruction_matches_rule (insn
, rule
)
3097 && is_unique_insn_expansion (rule
)
3098 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3099 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3110 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3115 /* Return the maximum number of bytes this opcode can expand to. */
3118 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3120 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3122 int max_size
= xg_get_single_size (opcode
);
3124 gas_assert (opcode
< table
->num_opcodes
);
3126 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3128 TransitionRule
*rule
= l
->rule
;
3129 BuildInstr
*build_list
;
3134 build_list
= rule
->to_instr
;
3135 if (is_unique_insn_expansion (rule
))
3137 gas_assert (build_list
->typ
== INSTR_INSTR
);
3138 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3141 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3143 switch (build_list
->typ
)
3146 this_size
+= xg_get_single_size (build_list
->opcode
);
3148 case INSTR_LITERAL_DEF
:
3149 case INSTR_LABEL_DEF
:
3154 if (this_size
> max_size
)
3155 max_size
= this_size
;
3161 /* Return the maximum number of literal bytes this opcode can generate. */
3164 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3166 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3170 gas_assert (opcode
< table
->num_opcodes
);
3172 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3174 TransitionRule
*rule
= l
->rule
;
3175 BuildInstr
*build_list
;
3180 build_list
= rule
->to_instr
;
3181 if (is_unique_insn_expansion (rule
))
3183 gas_assert (build_list
->typ
== INSTR_INSTR
);
3184 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3187 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3189 switch (build_list
->typ
)
3191 case INSTR_LITERAL_DEF
:
3192 /* Hard-coded 4-byte literal. */
3196 case INSTR_LABEL_DEF
:
3201 if (this_size
> max_size
)
3202 max_size
= this_size
;
3209 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3211 int steps_taken
= 0;
3212 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3215 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3216 gas_assert (insn
->opcode
< table
->num_opcodes
);
3218 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3220 TransitionRule
*rule
= l
->rule
;
3222 if (xg_instruction_matches_rule (insn
, rule
))
3224 if (steps_taken
== lateral_steps
)
3234 get_special_literal_symbol (void)
3236 static symbolS
*sym
= NULL
;
3239 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3245 get_special_label_symbol (void)
3247 static symbolS
*sym
= NULL
;
3250 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3256 xg_valid_literal_expression (const expressionS
*exp
)
3278 /* This will check to see if the value can be converted into the
3279 operand type. It will return TRUE if it does not fit. */
3282 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3284 uint32 valbuf
= value
;
3285 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3291 /* Assumes: All immeds are constants. Check that all constants fit
3292 into their immeds; return FALSE if not. */
3295 xg_immeds_fit (const TInsn
*insn
)
3297 xtensa_isa isa
= xtensa_default_isa
;
3301 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3302 for (i
= 0; i
< n
; ++i
)
3304 const expressionS
*exp
= &insn
->tok
[i
];
3306 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3313 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3318 /* The symbol should have a fixup associated with it. */
3327 /* This should only be called after we have an initial
3328 estimate of the addresses. */
3331 xg_symbolic_immeds_fit (const TInsn
*insn
,
3337 xtensa_isa isa
= xtensa_default_isa
;
3345 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3347 for (i
= 0; i
< n
; ++i
)
3349 const expressionS
*exp
= &insn
->tok
[i
];
3351 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3358 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3364 /* Check for the worst case. */
3365 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3370 /* We only allow symbols for PC-relative references.
3371 If pc_frag == 0, then we don't have frag locations yet. */
3373 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3376 /* If it is a weak symbol or a symbol in a different section,
3377 it cannot be known to fit at assembly time. */
3378 if (S_IS_WEAK (exp
->X_add_symbol
)
3379 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3381 /* For a direct call with --no-longcalls, be optimistic and
3382 assume it will be in range. If the symbol is weak and
3383 undefined, it may remain undefined at link-time, in which
3384 case it will have a zero value and almost certainly be out
3385 of range for a direct call; thus, relax for undefined weak
3386 symbols even if longcalls is not enabled. */
3387 if (is_direct_call_opcode (insn
->opcode
)
3388 && ! pc_frag
->tc_frag_data
.use_longcalls
3389 && (! S_IS_WEAK (exp
->X_add_symbol
)
3390 || S_IS_DEFINED (exp
->X_add_symbol
)))
3396 symbolP
= exp
->X_add_symbol
;
3397 sym_frag
= symbol_get_frag (symbolP
);
3398 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3399 pc
= pc_frag
->fr_address
+ pc_offset
;
3401 /* If frag has yet to be reached on this pass, assume it
3402 will move by STRETCH just as we did. If this is not so,
3403 it will be because some frag between grows, and that will
3404 force another pass. Beware zero-length frags. There
3405 should be a faster way to do this. */
3408 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3409 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3414 new_offset
= target
;
3415 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3416 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3421 /* The symbol should have a fixup associated with it. */
3430 /* Return TRUE on success. */
3433 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3439 targ
->debug_line
= insn
->debug_line
;
3440 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3445 targ
->opcode
= bi
->opcode
;
3446 targ
->insn_type
= ITYPE_INSN
;
3447 targ
->is_specific_opcode
= FALSE
;
3449 for (; op
!= NULL
; op
= op
->next
)
3451 int op_num
= op
->op_num
;
3452 int op_data
= op
->op_data
;
3454 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3456 if (targ
->ntok
<= op_num
)
3457 targ
->ntok
= op_num
+ 1;
3462 set_expr_const (&targ
->tok
[op_num
], op_data
);
3465 gas_assert (op_data
< insn
->ntok
);
3466 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3469 if (insn
->extra_arg
.X_op
!= O_register
)
3471 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3474 sym
= get_special_literal_symbol ();
3475 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3476 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3477 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3478 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3481 sym
= get_special_label_symbol ();
3482 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3484 case OP_OPERAND_HI16U
:
3485 case OP_OPERAND_LOW16U
:
3486 gas_assert (op_data
< insn
->ntok
);
3487 if (expr_is_const (&insn
->tok
[op_data
]))
3490 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3491 val
= xg_apply_userdef_op_fn (op
->typ
,
3494 targ
->tok
[op_num
].X_add_number
= val
;
3498 /* For const16 we can create relocations for these. */
3499 if (targ
->opcode
== XTENSA_UNDEFINED
3500 || (targ
->opcode
!= xtensa_const16_opcode
))
3502 gas_assert (op_data
< insn
->ntok
);
3503 /* Need to build a O_lo16 or O_hi16. */
3504 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3505 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3507 if (op
->typ
== OP_OPERAND_HI16U
)
3508 targ
->tok
[op_num
].X_op
= O_hi16
;
3509 else if (op
->typ
== OP_OPERAND_LOW16U
)
3510 targ
->tok
[op_num
].X_op
= O_lo16
;
3517 /* currently handles:
3520 OP_OPERAND_F32MINUS */
3521 if (xg_has_userdef_op_fn (op
->typ
))
3523 gas_assert (op_data
< insn
->ntok
);
3524 if (expr_is_const (&insn
->tok
[op_data
]))
3527 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3528 val
= xg_apply_userdef_op_fn (op
->typ
,
3531 targ
->tok
[op_num
].X_add_number
= val
;
3534 return FALSE
; /* We cannot use a relocation for this. */
3543 case INSTR_LITERAL_DEF
:
3545 targ
->opcode
= XTENSA_UNDEFINED
;
3546 targ
->insn_type
= ITYPE_LITERAL
;
3547 targ
->is_specific_opcode
= FALSE
;
3548 for (; op
!= NULL
; op
= op
->next
)
3550 int op_num
= op
->op_num
;
3551 int op_data
= op
->op_data
;
3552 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3554 if (targ
->ntok
<= op_num
)
3555 targ
->ntok
= op_num
+ 1;
3560 gas_assert (op_data
< insn
->ntok
);
3561 /* We can only pass resolvable literals through. */
3562 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3564 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3576 case INSTR_LABEL_DEF
:
3578 targ
->opcode
= XTENSA_UNDEFINED
;
3579 targ
->insn_type
= ITYPE_LABEL
;
3580 targ
->is_specific_opcode
= FALSE
;
3581 /* Literal with no ops is a label? */
3582 gas_assert (op
== NULL
);
3593 /* Return TRUE on success. */
3596 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3598 for (; bi
!= NULL
; bi
= bi
->next
)
3600 TInsn
*next_insn
= istack_push_space (istack
);
3602 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3609 /* Return TRUE on valid expansion. */
3612 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3614 int stack_size
= istack
->ninsn
;
3615 int steps_taken
= 0;
3616 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3619 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3620 gas_assert (insn
->opcode
< table
->num_opcodes
);
3622 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3624 TransitionRule
*rule
= l
->rule
;
3626 if (xg_instruction_matches_rule (insn
, rule
))
3628 if (lateral_steps
== steps_taken
)
3632 /* This is it. Expand the rule to the stack. */
3633 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3636 /* Check to see if it fits. */
3637 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3639 TInsn
*tinsn
= &istack
->insn
[i
];
3641 if (tinsn
->insn_type
== ITYPE_INSN
3642 && !tinsn_has_symbolic_operands (tinsn
)
3643 && !xg_immeds_fit (tinsn
))
3645 istack
->ninsn
= stack_size
;
3658 /* Relax the assembly instruction at least "min_steps".
3659 Return the number of steps taken.
3661 For relaxation to correctly terminate, every relaxation chain must
3662 terminate in one of two ways:
3664 1. If the chain from one instruction to the next consists entirely of
3665 single instructions, then the chain *must* handle all possible
3666 immediates without failing. It must not ever fail because an
3667 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3668 chain is one example. L32R loads 32 bits, and there cannot be an
3669 immediate larger than 32 bits, so it satisfies this condition.
3670 Single instruction relaxation chains are as defined by
3671 xg_is_single_relaxable_instruction.
3673 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3674 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3676 Strictly speaking, in most cases you can violate condition 1 and be OK
3677 -- in particular when the last two instructions have the same single
3678 size. But nevertheless, you should guarantee the above two conditions.
3680 We could fix this so that single-instruction expansions correctly
3681 terminate when they can't handle the range, but the error messages are
3682 worse, and it actually turns out that in every case but one (18-bit wide
3683 branches), you need a multi-instruction expansion to get the full range
3684 anyway. And because 18-bit branches are handled identically to 15-bit
3685 branches, there isn't any point in changing it. */
3688 xg_assembly_relax (IStack
*istack
,
3691 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3692 offsetT pc_offset
, /* offset in fragment */
3693 int min_steps
, /* minimum conversion steps */
3694 long stretch
) /* number of bytes stretched so far */
3696 int steps_taken
= 0;
3698 /* Some of its immeds don't fit. Try to build a relaxed version.
3699 This may go through a couple of stages of single instruction
3700 transformations before we get there. */
3702 TInsn single_target
;
3704 int lateral_steps
= 0;
3705 int istack_size
= istack
->ninsn
;
3707 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3708 && steps_taken
>= min_steps
)
3710 istack_push (istack
, insn
);
3713 current_insn
= *insn
;
3715 /* Walk through all of the single instruction expansions. */
3716 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3719 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3722 if (steps_taken
>= min_steps
)
3724 istack_push (istack
, &single_target
);
3728 current_insn
= single_target
;
3731 /* Now check for a multi-instruction expansion. */
3732 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3734 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3737 if (steps_taken
>= min_steps
)
3739 istack_push (istack
, ¤t_insn
);
3744 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3746 if (steps_taken
>= min_steps
)
3750 istack
->ninsn
= istack_size
;
3753 /* It's not going to work -- use the original. */
3754 istack_push (istack
, insn
);
3760 xg_finish_frag (char *last_insn
,
3761 enum xtensa_relax_statesE frag_state
,
3762 enum xtensa_relax_statesE slot0_state
,
3764 bfd_boolean is_insn
)
3766 /* Finish off this fragment so that it has at LEAST the desired
3767 max_growth. If it doesn't fit in this fragment, close this one
3768 and start a new one. In either case, return a pointer to the
3769 beginning of the growth area. */
3773 frag_grow (max_growth
);
3774 old_frag
= frag_now
;
3776 frag_now
->fr_opcode
= last_insn
;
3778 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3780 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3781 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3783 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3784 xtensa_set_frag_assembly_state (frag_now
);
3786 /* Just to make sure that we did not split it up. */
3787 gas_assert (old_frag
->fr_next
== frag_now
);
3791 /* Return TRUE if the target frag is one of the next non-empty frags. */
3794 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3799 for (; fragP
; fragP
= fragP
->fr_next
)
3801 if (fragP
== target
)
3803 if (fragP
->fr_fix
!= 0)
3805 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3807 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3808 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3810 if (fragP
->fr_type
== rs_space
)
3818 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3820 xtensa_isa isa
= xtensa_default_isa
;
3822 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3827 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3828 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3831 for (i
= 0; i
< num_ops
; i
++)
3833 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3839 if (target_op
== -1)
3842 if (insn
->ntok
<= target_op
)
3845 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3848 sym
= insn
->tok
[target_op
].X_add_symbol
;
3852 if (insn
->tok
[target_op
].X_add_number
!= 0)
3855 target_frag
= symbol_get_frag (sym
);
3856 if (target_frag
== NULL
)
3859 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3860 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3868 xg_add_branch_and_loop_targets (TInsn
*insn
)
3870 xtensa_isa isa
= xtensa_default_isa
;
3871 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3873 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3876 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3877 && insn
->tok
[i
].X_op
== O_symbol
)
3878 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3882 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3883 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3887 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3889 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3890 && insn
->tok
[i
].X_op
== O_symbol
)
3892 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3893 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3894 if (S_IS_DEFINED (sym
))
3895 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3902 /* Return FALSE if no error. */
3905 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3910 switch (instr_spec
->typ
)
3913 new_insn
->insn_type
= ITYPE_INSN
;
3914 new_insn
->opcode
= instr_spec
->opcode
;
3916 case INSTR_LITERAL_DEF
:
3917 new_insn
->insn_type
= ITYPE_LITERAL
;
3918 new_insn
->opcode
= XTENSA_UNDEFINED
;
3920 case INSTR_LABEL_DEF
:
3923 new_insn
->is_specific_opcode
= FALSE
;
3924 new_insn
->debug_line
= old_insn
->debug_line
;
3925 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3927 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3930 const expressionS
*src_exp
;
3936 /* The expression must be the constant. */
3937 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3938 exp
= &new_insn
->tok
[b_op
->op_num
];
3939 set_expr_const (exp
, b_op
->op_data
);
3943 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3944 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3945 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3946 exp
= &new_insn
->tok
[b_op
->op_num
];
3947 copy_expr (exp
, src_exp
);
3952 as_bad (_("can't handle generation of literal/labels yet"));
3956 as_bad (_("can't handle undefined OP TYPE"));
3961 new_insn
->ntok
= num_ops
;
3966 /* Return TRUE if it was simplified. */
3969 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3971 TransitionRule
*rule
;
3972 BuildInstr
*insn_spec
;
3974 if (old_insn
->is_specific_opcode
|| !density_supported
)
3977 rule
= xg_instruction_match (old_insn
);
3981 insn_spec
= rule
->to_instr
;
3982 /* There should only be one. */
3983 gas_assert (insn_spec
!= NULL
);
3984 gas_assert (insn_spec
->next
== NULL
);
3985 if (insn_spec
->next
!= NULL
)
3988 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3994 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3995 l32i.n. (2) Check the number of operands. (3) Place the instruction
3996 tokens into the stack or relax it and place multiple
3997 instructions/literals onto the stack. Return FALSE if no error. */
4000 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4004 bfd_boolean do_expand
;
4006 tinsn_init (&new_insn
);
4008 /* Narrow it if we can. xg_simplify_insn now does all the
4009 appropriate checking (e.g., for the density option). */
4010 if (xg_simplify_insn (orig_insn
, &new_insn
))
4011 orig_insn
= &new_insn
;
4013 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4015 if (orig_insn
->ntok
< noperands
)
4017 as_bad (_("found %d operands for '%s': Expected %d"),
4019 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4023 if (orig_insn
->ntok
> noperands
)
4024 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
4026 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4029 /* If there are not enough operands, we will assert above. If there
4030 are too many, just cut out the extras here. */
4031 orig_insn
->ntok
= noperands
;
4033 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4036 /* Special case for extui opcode which has constraints not handled
4037 by the ordinary operand encoding checks. The number of operands
4038 and related syntax issues have already been checked. */
4039 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4041 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4042 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4043 if (shiftimm
+ maskimm
> 32)
4045 as_bad (_("immediate operands sum to greater than 32"));
4050 /* If the instruction will definitely need to be relaxed, it is better
4051 to expand it now for better scheduling. Decide whether to expand
4053 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4055 /* Calls should be expanded to longcalls only in the backend relaxation
4056 so that the assembly scheduler will keep the L32R/CALLX instructions
4058 if (is_direct_call_opcode (orig_insn
->opcode
))
4061 if (tinsn_has_symbolic_operands (orig_insn
))
4063 /* The values of symbolic operands are not known yet, so only expand
4064 now if an operand is "complex" (e.g., difference of symbols) and
4065 will have to be stored as a literal regardless of the value. */
4066 if (!tinsn_has_complex_operands (orig_insn
))
4069 else if (xg_immeds_fit (orig_insn
))
4073 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4075 istack_push (istack
, orig_insn
);
4081 /* Return TRUE if the section flags are marked linkonce
4082 or the name is .gnu.linkonce.*. */
4084 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4087 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4089 flagword flags
, link_once_flags
;
4091 flags
= bfd_get_section_flags (abfd
, sec
);
4092 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4094 /* Flags might not be set yet. */
4095 if (!link_once_flags
4096 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4097 link_once_flags
= SEC_LINK_ONCE
;
4099 return (link_once_flags
!= 0);
4104 xtensa_add_literal_sym (symbolS
*sym
)
4108 l
= XNEW (sym_list
);
4110 l
->next
= literal_syms
;
4116 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4118 static int lit_num
= 0;
4119 static char name
[256];
4122 sprintf (name
, ".L_lit_sym%d", lit_num
);
4124 /* Create a local symbol. If it is in a linkonce section, we have to
4125 be careful to make sure that if it is used in a relocation that the
4126 symbol will be in the output file. */
4127 if (get_is_linkonce_section (stdoutput
, sec
))
4129 symbolP
= symbol_new (name
, sec
, 0, frag
);
4130 S_CLEAR_EXTERNAL (symbolP
);
4131 /* symbolP->local = 1; */
4134 symbolP
= symbol_new (name
, sec
, 0, frag
);
4136 xtensa_add_literal_sym (symbolP
);
4143 /* Currently all literals that are generated here are 32-bit L32R targets. */
4146 xg_assemble_literal (/* const */ TInsn
*insn
)
4149 symbolS
*lit_sym
= NULL
;
4150 bfd_reloc_code_real_type reloc
;
4151 bfd_boolean pcrel
= FALSE
;
4154 /* size = 4 for L32R. It could easily be larger when we move to
4155 larger constants. Add a parameter later. */
4156 offsetT litsize
= 4;
4157 offsetT litalign
= 2; /* 2^2 = 4 */
4158 expressionS saved_loc
;
4159 expressionS
* emit_val
;
4161 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4163 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4164 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4166 xtensa_switch_to_literal_fragment (&state
);
4168 emit_val
= &insn
->tok
[0];
4169 if (emit_val
->X_op
== O_big
)
4171 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4174 /* This happens when someone writes a "movi a2, big_number". */
4175 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4176 _("invalid immediate"));
4177 xtensa_restore_emit_state (&state
);
4182 /* Force a 4-byte align here. Note that this opens a new frag, so all
4183 literals done with this function have a frag to themselves. That's
4184 important for the way text section literals work. */
4185 frag_align (litalign
, 0, 0);
4186 record_alignment (now_seg
, litalign
);
4188 switch (emit_val
->X_op
)
4198 p
= frag_more (litsize
);
4199 xtensa_set_frag_assembly_state (frag_now
);
4200 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4201 if (emit_val
->X_add_symbol
)
4202 emit_val
->X_op
= O_symbol
;
4204 emit_val
->X_op
= O_constant
;
4205 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4206 litsize
, emit_val
, pcrel
, reloc
);
4210 emit_expr (emit_val
, litsize
);
4214 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4215 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4216 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4217 lit_sym
= frag_now
->fr_symbol
;
4220 xtensa_restore_emit_state (&state
);
4226 xg_assemble_literal_space (/* const */ int size
, int slot
)
4229 /* We might have to do something about this alignment. It only
4230 takes effect if something is placed here. */
4231 offsetT litalign
= 2; /* 2^2 = 4 */
4232 fragS
*lit_saved_frag
;
4234 gas_assert (size
% 4 == 0);
4236 xtensa_switch_to_literal_fragment (&state
);
4238 /* Force a 4-byte align here. */
4239 frag_align (litalign
, 0, 0);
4240 record_alignment (now_seg
, litalign
);
4244 lit_saved_frag
= frag_now
;
4245 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4246 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4247 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4250 xtensa_restore_emit_state (&state
);
4251 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4255 /* Put in a fixup record based on the opcode.
4256 Return TRUE on success. */
4259 xg_add_opcode_fix (TInsn
*tinsn
,
4267 xtensa_opcode opcode
= tinsn
->opcode
;
4268 bfd_reloc_code_real_type reloc
;
4269 reloc_howto_type
*howto
;
4273 reloc
= BFD_RELOC_NONE
;
4275 /* First try the special cases for "alternate" relocs. */
4276 if (opcode
== xtensa_l32r_opcode
)
4278 if (fragP
->tc_frag_data
.use_absolute_literals
)
4279 reloc
= encode_alt_reloc (slot
);
4281 else if (opcode
== xtensa_const16_opcode
)
4283 if (exp
->X_op
== O_lo16
)
4285 reloc
= encode_reloc (slot
);
4286 exp
->X_op
= O_symbol
;
4288 else if (exp
->X_op
== O_hi16
)
4290 reloc
= encode_alt_reloc (slot
);
4291 exp
->X_op
= O_symbol
;
4295 if (opnum
!= get_relaxable_immed (opcode
))
4297 as_bad (_("invalid relocation for operand %i of '%s'"),
4298 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4302 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4303 into the symbol table where the generic portions of the assembler
4304 won't know what to do with them. */
4305 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4307 as_bad (_("invalid expression for operand %i of '%s'"),
4308 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4312 /* Next try the generic relocs. */
4313 if (reloc
== BFD_RELOC_NONE
)
4314 reloc
= encode_reloc (slot
);
4315 if (reloc
== BFD_RELOC_NONE
)
4317 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4321 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4324 as_bad (_("undefined symbol for opcode \"%s\""),
4325 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4329 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4330 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4331 howto
->pc_relative
, reloc
);
4332 the_fix
->fx_no_overflow
= 1;
4333 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4334 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4335 the_fix
->tc_fix_data
.slot
= slot
;
4342 xg_emit_insn_to_buf (TInsn
*tinsn
,
4346 bfd_boolean build_fix
)
4348 static xtensa_insnbuf insnbuf
= NULL
;
4349 bfd_boolean has_symbolic_immed
= FALSE
;
4350 bfd_boolean ok
= TRUE
;
4353 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4355 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4356 if (has_symbolic_immed
&& build_fix
)
4359 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4360 int slot
= xg_get_single_slot (tinsn
->opcode
);
4361 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4362 expressionS
*exp
= &tinsn
->tok
[opnum
];
4364 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4367 fragP
->tc_frag_data
.is_insn
= TRUE
;
4368 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4369 (unsigned char *) buf
, 0);
4375 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4377 symbolS
*sym
= get_special_literal_symbol ();
4381 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4382 for (i
= 0; i
< insn
->ntok
; i
++)
4383 if (insn
->tok
[i
].X_add_symbol
== sym
)
4384 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4390 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4392 symbolS
*sym
= get_special_label_symbol ();
4394 for (i
= 0; i
< insn
->ntok
; i
++)
4395 if (insn
->tok
[i
].X_add_symbol
== sym
)
4396 insn
->tok
[i
].X_add_symbol
= label_sym
;
4401 /* Return TRUE if the instruction can write to the specified
4402 integer register. */
4405 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4409 xtensa_isa isa
= xtensa_default_isa
;
4411 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4413 for (i
= 0; i
< num_ops
; i
++)
4416 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4417 if ((inout
== 'o' || inout
== 'm')
4418 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4420 xtensa_regfile opnd_rf
=
4421 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4422 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4424 if ((insn
->tok
[i
].X_op
== O_register
)
4425 && (insn
->tok
[i
].X_add_number
== regnum
))
4435 is_bad_loopend_opcode (const TInsn
*tinsn
)
4437 xtensa_opcode opcode
= tinsn
->opcode
;
4439 if (opcode
== XTENSA_UNDEFINED
)
4442 if (opcode
== xtensa_call0_opcode
4443 || opcode
== xtensa_callx0_opcode
4444 || opcode
== xtensa_call4_opcode
4445 || opcode
== xtensa_callx4_opcode
4446 || opcode
== xtensa_call8_opcode
4447 || opcode
== xtensa_callx8_opcode
4448 || opcode
== xtensa_call12_opcode
4449 || opcode
== xtensa_callx12_opcode
4450 || opcode
== xtensa_isync_opcode
4451 || opcode
== xtensa_ret_opcode
4452 || opcode
== xtensa_ret_n_opcode
4453 || opcode
== xtensa_retw_opcode
4454 || opcode
== xtensa_retw_n_opcode
4455 || opcode
== xtensa_waiti_opcode
4456 || opcode
== xtensa_rsr_lcount_opcode
)
4463 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4464 This allows the debugger to add unaligned labels.
4465 Also, the assembler generates stabs labels that need
4466 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4469 is_unaligned_label (symbolS
*sym
)
4471 const char *name
= S_GET_NAME (sym
);
4472 static size_t fake_size
= 0;
4476 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4479 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4481 fake_size
= strlen (FAKE_LABEL_NAME
);
4484 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4485 && (name
[fake_size
] == 'F'
4486 || name
[fake_size
] == 'L'
4487 || (name
[fake_size
] == 'e'
4488 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4496 next_non_empty_frag (const fragS
*fragP
)
4498 fragS
*next_fragP
= fragP
->fr_next
;
4500 /* Sometimes an empty will end up here due storage allocation issues.
4501 So we have to skip until we find something legit. */
4502 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4503 next_fragP
= next_fragP
->fr_next
;
4505 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4513 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4515 xtensa_opcode out_opcode
;
4516 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4518 if (next_fragP
== NULL
)
4521 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4522 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4524 *opcode
= out_opcode
;
4532 frag_format_size (const fragS
*fragP
)
4534 static xtensa_insnbuf insnbuf
= NULL
;
4535 xtensa_isa isa
= xtensa_default_isa
;
4540 insnbuf
= xtensa_insnbuf_alloc (isa
);
4543 return XTENSA_UNDEFINED
;
4545 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4546 (unsigned char *) fragP
->fr_literal
, 0);
4548 fmt
= xtensa_format_decode (isa
, insnbuf
);
4549 if (fmt
== XTENSA_UNDEFINED
)
4550 return XTENSA_UNDEFINED
;
4551 fmt_size
= xtensa_format_length (isa
, fmt
);
4553 /* If the next format won't be changing due to relaxation, just
4554 return the length of the first format. */
4555 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4558 /* If during relaxation we have to pull an instruction out of a
4559 multi-slot instruction, we will return the more conservative
4560 number. This works because alignment on bigger instructions
4561 is more restrictive than alignment on smaller instructions.
4562 This is more conservative than we would like, but it happens
4565 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4568 /* If we aren't doing one of our own relaxations or it isn't
4569 slot-based, then the insn size won't change. */
4570 if (fragP
->fr_type
!= rs_machine_dependent
)
4572 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4575 /* If an instruction is about to grow, return the longer size. */
4576 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4577 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4578 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4580 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4581 instruction in the relaxed version is of length 3. (The case
4582 where we have to pull the instruction out of a FLIX bundle
4583 is handled conservatively above.) However, frags with opcodes
4584 that are expanding to wide branches end up having formats that
4585 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4586 we can't tell directly what format the relaxer picked. This
4587 is a wart in the design of the relaxer that should someday be
4588 fixed, but would require major changes, or at least should
4589 be accompanied by major changes to make use of that data.
4591 In any event, we can tell that we are expanding from a single-slot
4592 format to a wider one with the logic below. */
4595 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4597 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4599 if (relaxed_size
== xtensa_format_length (isa
, i
))
4600 return relaxed_size
;
4606 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4607 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4614 next_frag_format_size (const fragS
*fragP
)
4616 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4617 return frag_format_size (next_fragP
);
4621 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4622 required two-byte instructions to be treated as three-byte instructions
4623 for loop instruction alignment. This restriction was removed beginning
4624 with Xtensa LX. Now the only requirement on loop instruction alignment
4625 is that the first instruction of the loop must appear at an address that
4626 does not cross a fetch boundary. */
4629 get_loop_align_size (int insn_size
)
4631 if (insn_size
== XTENSA_UNDEFINED
)
4632 return xtensa_fetch_width
;
4634 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4641 /* If the next legit fragment is an end-of-loop marker,
4642 switch its state so it will instantiate a NOP. */
4645 update_next_frag_state (fragS
*fragP
)
4647 fragS
*next_fragP
= fragP
->fr_next
;
4648 fragS
*new_target
= NULL
;
4652 /* We are guaranteed there will be one of these... */
4653 while (!(next_fragP
->fr_type
== rs_machine_dependent
4654 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4655 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4656 next_fragP
= next_fragP
->fr_next
;
4658 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4659 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4660 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4662 /* ...and one of these. */
4663 new_target
= next_fragP
->fr_next
;
4664 while (!(new_target
->fr_type
== rs_machine_dependent
4665 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4666 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4667 new_target
= new_target
->fr_next
;
4669 gas_assert (new_target
->fr_type
== rs_machine_dependent
4670 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4671 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4674 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4676 if (next_fragP
->fr_type
== rs_machine_dependent
4677 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4679 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4683 next_fragP
= next_fragP
->fr_next
;
4689 next_frag_is_branch_target (const fragS
*fragP
)
4691 /* Sometimes an empty will end up here due to storage allocation issues,
4692 so we have to skip until we find something legit. */
4693 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4695 if (fragP
->tc_frag_data
.is_branch_target
)
4697 if (fragP
->fr_fix
!= 0)
4705 next_frag_is_loop_target (const fragS
*fragP
)
4707 /* Sometimes an empty will end up here due storage allocation issues.
4708 So we have to skip until we find something legit. */
4709 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4711 if (fragP
->tc_frag_data
.is_loop_target
)
4713 if (fragP
->fr_fix
!= 0)
4720 /* As specified in the relaxation table, when a loop instruction is
4721 relaxed, there are 24 bytes between the loop instruction itself and
4722 the first instruction in the loop. */
4724 #define RELAXED_LOOP_INSN_BYTES 24
4727 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4729 const fragS
*next_fragp
= fragp
->fr_next
;
4730 xtensa_opcode next_opcode
;
4732 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4735 /* Sometimes an empty will end up here due to storage allocation issues,
4736 so we have to skip until we find something legit. */
4737 while (next_fragp
->fr_fix
== 0)
4738 next_fragp
= next_fragp
->fr_next
;
4740 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4743 /* There is some implicit knowledge encoded in here.
4744 The LOOP instructions that are NOT RELAX_IMMED have
4745 been relaxed. Note that we can assume that the LOOP
4746 instruction is in slot 0 because loops aren't bundleable. */
4747 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4748 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4754 /* Mark a location where we can later insert literal frags. Update
4755 the section's literal_pool_loc, so subsequent literals can be
4756 placed nearest to their use. */
4759 xtensa_mark_literal_pool_location (void)
4761 /* Any labels pointing to the current location need
4762 to be adjusted to after the literal pool. */
4764 fragS
*pool_location
;
4766 if (use_literal_section
)
4769 /* We stash info in these frags so we can later move the literal's
4770 fixes into this frchain's fix list. */
4771 pool_location
= frag_now
;
4772 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4773 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4774 /* Just record this frag. */
4775 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4776 frag_variant (rs_machine_dependent
, 0, 0,
4777 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4778 xtensa_set_frag_assembly_state (frag_now
);
4779 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4780 frag_variant (rs_machine_dependent
, 0, 0,
4781 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4782 xtensa_set_frag_assembly_state (frag_now
);
4784 /* Now put a frag into the literal pool that points to this location. */
4785 set_literal_pool_location (now_seg
, pool_location
);
4786 xtensa_switch_to_non_abs_literal_fragment (&s
);
4787 frag_align (2, 0, 0);
4788 record_alignment (now_seg
, 2);
4790 /* Close whatever frag is there. */
4791 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4792 xtensa_set_frag_assembly_state (frag_now
);
4793 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4794 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4795 xtensa_restore_emit_state (&s
);
4796 xtensa_set_frag_assembly_state (frag_now
);
4800 /* Build a nop of the correct size into tinsn. */
4803 build_nop (TInsn
*tinsn
, int size
)
4809 tinsn
->opcode
= xtensa_nop_n_opcode
;
4811 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4812 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4816 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4818 tinsn
->opcode
= xtensa_or_opcode
;
4819 set_expr_const (&tinsn
->tok
[0], 1);
4820 set_expr_const (&tinsn
->tok
[1], 1);
4821 set_expr_const (&tinsn
->tok
[2], 1);
4825 tinsn
->opcode
= xtensa_nop_opcode
;
4827 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4832 /* Assemble a NOP of the requested size in the buffer. User must have
4833 allocated "buf" with at least "size" bytes. */
4836 assemble_nop (int size
, char *buf
)
4838 static xtensa_insnbuf insnbuf
= NULL
;
4841 build_nop (&tinsn
, size
);
4844 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4846 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4847 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4848 (unsigned char *) buf
, 0);
4852 /* Return the number of bytes for the offset of the expanded loop
4853 instruction. This should be incorporated into the relaxation
4854 specification but is hard-coded here. This is used to auto-align
4855 the loop instruction. It is invalid to call this function if the
4856 configuration does not have loops or if the opcode is not a loop
4860 get_expanded_loop_offset (xtensa_opcode opcode
)
4862 /* This is the OFFSET of the loop instruction in the expanded loop.
4863 This MUST correspond directly to the specification of the loop
4864 expansion. It will be validated on fragment conversion. */
4865 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4866 if (opcode
== xtensa_loop_opcode
)
4868 if (opcode
== xtensa_loopnez_opcode
)
4870 if (opcode
== xtensa_loopgtz_opcode
)
4872 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4878 get_literal_pool_location (segT seg
)
4880 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4881 struct litpool_frag
*lpf
;
4882 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4886 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4887 { /* Skip "candidates" for now. */
4888 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4892 /* Must convert a lower-priority pool. */
4893 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4895 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4898 /* Still no match -- try for a low priority pool. */
4899 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4901 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4905 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4910 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4912 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4916 /* Set frag assembly state should be called when a new frag is
4917 opened and after a frag has been closed. */
4920 xtensa_set_frag_assembly_state (fragS
*fragP
)
4922 if (!density_supported
)
4923 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4925 /* This function is called from subsegs_finish, which is called
4926 after xtensa_end, so we can't use "use_transform" or
4927 "use_schedule" here. */
4928 if (!directive_state
[directive_transform
])
4929 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4930 if (directive_state
[directive_longcalls
])
4931 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4932 fragP
->tc_frag_data
.use_absolute_literals
=
4933 directive_state
[directive_absolute_literals
];
4934 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4939 relaxable_section (asection
*sec
)
4941 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4942 && strcmp (sec
->name
, ".eh_frame") != 0);
4947 xtensa_mark_frags_for_org (void)
4951 /* Walk over each fragment of all of the current segments. If we find
4952 a .org frag in any of the segments, mark all frags prior to it as
4953 "no transform", which will prevent linker optimizations from messing
4954 up the .org distance. This should be done after
4955 xtensa_find_unmarked_state_frags, because we don't want to worry here
4956 about that function trashing the data we save here. */
4958 for (seclist
= &stdoutput
->sections
;
4959 seclist
&& *seclist
;
4960 seclist
= &(*seclist
)->next
)
4962 segT sec
= *seclist
;
4963 segment_info_type
*seginfo
;
4966 flags
= bfd_get_section_flags (stdoutput
, sec
);
4967 if (flags
& SEC_DEBUGGING
)
4969 if (!(flags
& SEC_ALLOC
))
4972 seginfo
= seg_info (sec
);
4973 if (seginfo
&& seginfo
->frchainP
)
4975 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4976 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4977 fragP
= fragP
->fr_next
)
4979 /* cvt_frag_to_fill has changed the fr_type of org frags to
4980 rs_fill, so use the value as cached in rs_subtype here. */
4981 if (fragP
->fr_subtype
== RELAX_ORG
)
4983 while (last_fragP
!= fragP
->fr_next
)
4985 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4986 last_fragP
= last_fragP
->fr_next
;
4996 xtensa_find_unmarked_state_frags (void)
5000 /* Walk over each fragment of all of the current segments. For each
5001 unmarked fragment, mark it with the same info as the previous
5003 for (seclist
= &stdoutput
->sections
;
5004 seclist
&& *seclist
;
5005 seclist
= &(*seclist
)->next
)
5007 segT sec
= *seclist
;
5008 segment_info_type
*seginfo
;
5011 flags
= bfd_get_section_flags (stdoutput
, sec
);
5012 if (flags
& SEC_DEBUGGING
)
5014 if (!(flags
& SEC_ALLOC
))
5017 seginfo
= seg_info (sec
);
5018 if (seginfo
&& seginfo
->frchainP
)
5020 fragS
*last_fragP
= 0;
5021 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5022 fragP
= fragP
->fr_next
)
5024 if (fragP
->fr_fix
!= 0
5025 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5027 if (last_fragP
== 0)
5029 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5030 _("assembly state not set for first frag in section %s"),
5035 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5036 fragP
->tc_frag_data
.is_no_density
=
5037 last_fragP
->tc_frag_data
.is_no_density
;
5038 fragP
->tc_frag_data
.is_no_transform
=
5039 last_fragP
->tc_frag_data
.is_no_transform
;
5040 fragP
->tc_frag_data
.use_longcalls
=
5041 last_fragP
->tc_frag_data
.use_longcalls
;
5042 fragP
->tc_frag_data
.use_absolute_literals
=
5043 last_fragP
->tc_frag_data
.use_absolute_literals
;
5046 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5055 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5057 void *unused ATTRIBUTE_UNUSED
)
5059 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5060 segment_info_type
*seginfo
= seg_info (sec
);
5061 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5063 if (flags
& SEC_CODE
)
5065 xtensa_isa isa
= xtensa_default_isa
;
5066 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5067 while (frag
!= NULL
)
5069 if (frag
->tc_frag_data
.is_branch_target
)
5072 addressT branch_align
, frag_addr
;
5075 xtensa_insnbuf_from_chars
5076 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5077 fmt
= xtensa_format_decode (isa
, insnbuf
);
5078 op_size
= xtensa_format_length (isa
, fmt
);
5079 branch_align
= 1 << branch_align_power (sec
);
5080 frag_addr
= frag
->fr_address
% branch_align
;
5081 if (frag_addr
+ op_size
> branch_align
)
5082 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5083 _("unaligned branch target: %d bytes at 0x%lx"),
5084 op_size
, (long) frag
->fr_address
);
5086 frag
= frag
->fr_next
;
5088 xtensa_insnbuf_free (isa
, insnbuf
);
5094 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5096 void *unused ATTRIBUTE_UNUSED
)
5098 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5099 segment_info_type
*seginfo
= seg_info (sec
);
5100 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5101 xtensa_isa isa
= xtensa_default_isa
;
5103 if (flags
& SEC_CODE
)
5105 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5106 while (frag
!= NULL
)
5108 if (frag
->tc_frag_data
.is_first_loop_insn
)
5114 if (frag
->fr_fix
== 0)
5115 frag
= next_non_empty_frag (frag
);
5119 xtensa_insnbuf_from_chars
5120 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5121 fmt
= xtensa_format_decode (isa
, insnbuf
);
5122 op_size
= xtensa_format_length (isa
, fmt
);
5123 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5125 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5126 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5127 _("unaligned loop: %d bytes at 0x%lx"),
5128 op_size
, (long) frag
->fr_address
);
5131 frag
= frag
->fr_next
;
5133 xtensa_insnbuf_free (isa
, insnbuf
);
5139 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5141 xtensa_isa isa
= xtensa_default_isa
;
5142 static xtensa_insnbuf insnbuf
= NULL
;
5143 static xtensa_insnbuf slotbuf
= NULL
;
5146 bfd_boolean alt_reloc
;
5147 xtensa_opcode opcode
;
5148 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5150 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5152 as_fatal (_("unexpected fix"));
5156 insnbuf
= xtensa_insnbuf_alloc (isa
);
5157 slotbuf
= xtensa_insnbuf_alloc (isa
);
5160 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5161 fmt
= xtensa_format_decode (isa
, insnbuf
);
5162 if (fmt
== XTENSA_UNDEFINED
)
5163 as_fatal (_("undecodable fix"));
5164 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5165 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5166 if (opcode
== XTENSA_UNDEFINED
)
5167 as_fatal (_("undecodable fix"));
5169 /* CONST16 immediates are not PC-relative, despite the fact that we
5170 reuse the normal PC-relative operand relocations for the low part
5171 of a CONST16 operand. */
5172 if (opcode
== xtensa_const16_opcode
)
5175 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5176 get_relaxable_immed (opcode
), val
,
5177 fixP
->fx_file
, fixP
->fx_line
);
5179 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5180 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5186 /* External Functions and Other GAS Hooks. */
5189 xtensa_target_format (void)
5191 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5196 xtensa_file_arch_init (bfd
*abfd
)
5198 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5203 md_number_to_chars (char *buf
, valueT val
, int n
)
5205 if (target_big_endian
)
5206 number_to_chars_bigendian (buf
, val
, n
);
5208 number_to_chars_littleendian (buf
, val
, n
);
5212 xg_init_global_config (void)
5214 target_big_endian
= XCHAL_HAVE_BE
;
5216 density_supported
= XCHAL_HAVE_DENSITY
;
5217 absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
5218 xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
5220 directive_state
[directive_density
] = XCHAL_HAVE_DENSITY
;
5221 directive_state
[directive_absolute_literals
] = XSHAL_USE_ABSOLUTE_LITERALS
;
5225 xtensa_init (int argc ATTRIBUTE_UNUSED
, char **argv ATTRIBUTE_UNUSED
)
5227 xg_init_global_config ();
5230 /* This function is called once, at assembler startup time. It should
5231 set up all the tables, etc. that the MD part of the assembler will
5237 segT current_section
= now_seg
;
5238 int current_subsec
= now_subseg
;
5242 xtensa_default_isa
= xtensa_isa_init (0, 0);
5243 isa
= xtensa_default_isa
;
5247 /* Set up the literal sections. */
5248 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5250 subseg_set (current_section
, current_subsec
);
5252 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5253 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5254 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5255 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5256 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5257 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5258 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5259 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5260 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5261 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5262 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5263 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5264 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5265 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5266 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5267 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5268 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5269 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5270 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5271 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5272 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5273 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5274 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5275 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5276 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5277 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5278 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5279 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5280 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5281 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5282 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5284 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5286 int format_slots
= xtensa_format_num_slots (isa
, i
);
5287 if (format_slots
> config_max_slots
)
5288 config_max_slots
= format_slots
;
5291 xg_init_vinsn (&cur_vinsn
);
5293 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5295 init_op_placement_info_table ();
5297 /* Set up the assembly state. */
5298 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5299 xtensa_set_frag_assembly_state (frag_now
);
5303 /* TC_INIT_FIX_DATA hook */
5306 xtensa_init_fix_data (fixS
*x
)
5308 x
->tc_fix_data
.slot
= 0;
5309 x
->tc_fix_data
.X_add_symbol
= NULL
;
5310 x
->tc_fix_data
.X_add_number
= 0;
5314 /* tc_frob_label hook */
5317 xtensa_frob_label (symbolS
*sym
)
5321 if (cur_vinsn
.inside_bundle
)
5323 as_bad (_("labels are not valid inside bundles"));
5327 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5329 /* Since the label was already attached to a frag associated with the
5330 previous basic block, it now needs to be reset to the current frag. */
5331 symbol_set_frag (sym
, frag_now
);
5332 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5334 if (generating_literals
)
5335 xtensa_add_literal_sym (sym
);
5337 xtensa_add_insn_label (sym
);
5339 if (symbol_get_tc (sym
)->is_loop_target
)
5341 if ((get_last_insn_flags (now_seg
, now_subseg
)
5342 & FLAG_IS_BAD_LOOPEND
) != 0)
5343 as_bad (_("invalid last instruction for a zero-overhead loop"));
5345 xtensa_set_frag_assembly_state (frag_now
);
5346 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5347 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5349 xtensa_set_frag_assembly_state (frag_now
);
5350 xtensa_move_labels (frag_now
, 0);
5353 /* No target aligning in the absolute section. */
5354 if (now_seg
!= absolute_section
5355 && !is_unaligned_label (sym
)
5356 && !generating_literals
)
5358 xtensa_set_frag_assembly_state (frag_now
);
5360 if (do_align_targets ())
5361 frag_var (rs_machine_dependent
, 0, (int) freq
,
5362 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5363 frag_now
->fr_offset
, NULL
);
5365 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5366 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5367 xtensa_set_frag_assembly_state (frag_now
);
5368 xtensa_move_labels (frag_now
, 0);
5371 /* We need to mark the following properties even if we aren't aligning. */
5373 /* If the label is already known to be a branch target, i.e., a
5374 forward branch, mark the frag accordingly. Backward branches
5375 are handled by xg_add_branch_and_loop_targets. */
5376 if (symbol_get_tc (sym
)->is_branch_target
)
5377 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5379 /* Loops only go forward, so they can be identified here. */
5380 if (symbol_get_tc (sym
)->is_loop_target
)
5381 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5383 dwarf2_emit_label (sym
);
5387 /* tc_unrecognized_line hook */
5390 xtensa_unrecognized_line (int ch
)
5395 if (cur_vinsn
.inside_bundle
== 0)
5397 /* PR8110: Cannot emit line number info inside a FLIX bundle
5398 when using --gstabs. Temporarily disable debug info. */
5399 generate_lineno_debug ();
5400 if (debug_type
== DEBUG_STABS
)
5402 xt_saved_debug_type
= debug_type
;
5403 debug_type
= DEBUG_NONE
;
5406 cur_vinsn
.inside_bundle
= 1;
5410 as_bad (_("extra opening brace"));
5416 if (cur_vinsn
.inside_bundle
)
5417 finish_vinsn (&cur_vinsn
);
5420 as_bad (_("extra closing brace"));
5425 as_bad (_("syntax error"));
5432 /* md_flush_pending_output hook */
5435 xtensa_flush_pending_output (void)
5437 /* This line fixes a bug where automatically generated gstabs info
5438 separates a function label from its entry instruction, ending up
5439 with the literal position between the function label and the entry
5440 instruction and crashing code. It only happens with --gstabs and
5441 --text-section-literals, and when several other obscure relaxation
5442 conditions are met. */
5443 if (outputting_stabs_line_debug
)
5446 if (cur_vinsn
.inside_bundle
)
5447 as_bad (_("missing closing brace"));
5449 /* If there is a non-zero instruction fragment, close it. */
5450 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5452 frag_wane (frag_now
);
5454 xtensa_set_frag_assembly_state (frag_now
);
5456 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5458 xtensa_clear_insn_labels ();
5462 /* We had an error while parsing an instruction. The string might look
5463 like this: "insn arg1, arg2 }". If so, we need to see the closing
5464 brace and reset some fields. Otherwise, the vinsn never gets closed
5465 and the num_slots field will grow past the end of the array of slots,
5466 and bad things happen. */
5469 error_reset_cur_vinsn (void)
5471 if (cur_vinsn
.inside_bundle
)
5473 if (*input_line_pointer
== '}'
5474 || *(input_line_pointer
- 1) == '}'
5475 || *(input_line_pointer
- 2) == '}')
5476 xg_clear_vinsn (&cur_vinsn
);
5482 md_assemble (char *str
)
5484 xtensa_isa isa
= xtensa_default_isa
;
5487 bfd_boolean has_underbar
= FALSE
;
5488 char *arg_strings
[MAX_INSN_ARGS
];
5490 TInsn orig_insn
; /* Original instruction from the input. */
5492 tinsn_init (&orig_insn
);
5494 /* Split off the opcode. */
5495 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5496 opname
= xstrndup (str
, opnamelen
);
5498 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5501 as_bad (_("syntax error"));
5505 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5508 /* Check for an underbar prefix. */
5511 has_underbar
= TRUE
;
5515 orig_insn
.insn_type
= ITYPE_INSN
;
5517 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5518 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5520 /* Special case: Check for "CALLXn.TLS" pseudo op. If found, grab its
5521 extra argument and set the opcode to "CALLXn". */
5522 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5523 && strncasecmp (opname
, "callx", 5) == 0)
5525 unsigned long window_size
;
5528 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5529 if (suffix
!= opname
+ 5
5530 && (window_size
== 0
5533 || window_size
== 12)
5534 && strcasecmp (suffix
, ".tls") == 0)
5536 switch (window_size
)
5538 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5539 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5540 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5541 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5545 as_bad (_("wrong number of operands for '%s'"), opname
);
5548 bfd_reloc_code_real_type reloc
;
5549 char *old_input_line_pointer
;
5550 expressionS
*tok
= &orig_insn
.extra_arg
;
5552 old_input_line_pointer
= input_line_pointer
;
5553 input_line_pointer
= arg_strings
[num_args
- 1];
5556 if (tok
->X_op
== O_symbol
5557 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5558 == BFD_RELOC_XTENSA_TLS_CALL
))
5559 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5561 as_bad (_("bad relocation expression for '%s'"), opname
);
5563 input_line_pointer
= old_input_line_pointer
;
5569 /* Special case: Check for "j.l" pseudo op. */
5570 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5571 && strncasecmp (opname
, "j.l", 3) == 0)
5574 as_bad (_("wrong number of operands for '%s'"), opname
);
5577 char *old_input_line_pointer
;
5578 expressionS
*tok
= &orig_insn
.extra_arg
;
5580 old_input_line_pointer
= input_line_pointer
;
5581 input_line_pointer
= arg_strings
[num_args
- 1];
5583 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5584 input_line_pointer
= old_input_line_pointer
;
5587 orig_insn
.opcode
= xtensa_j_opcode
;
5591 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5593 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5594 if (fmt
== XTENSA_UNDEFINED
)
5596 as_bad (_("unknown opcode or format name '%s'"), opname
);
5597 error_reset_cur_vinsn ();
5600 if (!cur_vinsn
.inside_bundle
)
5602 as_bad (_("format names only valid inside bundles"));
5603 error_reset_cur_vinsn ();
5606 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5607 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5609 cur_vinsn
.format
= fmt
;
5610 free (has_underbar
? opname
- 1 : opname
);
5611 error_reset_cur_vinsn ();
5615 /* Parse the arguments. */
5616 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5618 as_bad (_("syntax error"));
5619 error_reset_cur_vinsn ();
5623 /* Free the opcode and argument strings, now that they've been parsed. */
5624 free (has_underbar
? opname
- 1 : opname
);
5626 while (num_args
-- > 0)
5627 free (arg_strings
[num_args
]);
5629 /* Get expressions for invisible operands. */
5630 if (get_invisible_operands (&orig_insn
))
5632 error_reset_cur_vinsn ();
5636 /* Check for the right number and type of arguments. */
5637 if (tinsn_check_arguments (&orig_insn
))
5639 error_reset_cur_vinsn ();
5643 /* Record the line number for each TInsn, because a FLIX bundle may be
5644 spread across multiple input lines and individual instructions may be
5645 moved around in some cases. */
5646 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5647 dwarf2_where (&orig_insn
.debug_line
);
5648 dwarf2_consume_line_info ();
5650 xg_add_branch_and_loop_targets (&orig_insn
);
5652 /* Check that immediate value for ENTRY is >= 16. */
5653 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5655 expressionS
*exp
= &orig_insn
.tok
[2];
5656 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5657 as_warn (_("entry instruction with stack decrement < 16"));
5661 assemble_tokens (opcode, tok, ntok);
5662 expand the tokens from the orig_insn into the
5663 stack of instructions that will not expand
5664 unless required at relaxation time. */
5666 if (!cur_vinsn
.inside_bundle
)
5667 emit_single_op (&orig_insn
);
5668 else /* We are inside a bundle. */
5670 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5671 cur_vinsn
.num_slots
++;
5672 if (*input_line_pointer
== '}'
5673 || *(input_line_pointer
- 1) == '}'
5674 || *(input_line_pointer
- 2) == '}')
5675 finish_vinsn (&cur_vinsn
);
5678 /* We've just emitted a new instruction so clear the list of labels. */
5679 xtensa_clear_insn_labels ();
5681 xtensa_check_frag_count ();
5685 /* HANDLE_ALIGN hook */
5687 /* For a .align directive, we mark the previous block with the alignment
5688 information. This will be placed in the object file in the
5689 property section corresponding to this section. */
5692 xtensa_handle_align (fragS
*fragP
)
5695 && ! fragP
->tc_frag_data
.is_literal
5696 && (fragP
->fr_type
== rs_align
5697 || fragP
->fr_type
== rs_align_code
)
5698 && fragP
->fr_offset
> 0
5699 && now_seg
!= bss_section
)
5701 fragP
->tc_frag_data
.is_align
= TRUE
;
5702 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5705 if (fragP
->fr_type
== rs_align_test
)
5708 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5710 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5711 _("unaligned entry instruction"));
5714 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5715 fragP
->fr_subtype
= RELAX_ORG
;
5719 /* TC_FRAG_INIT hook */
5722 xtensa_frag_init (fragS
*frag
)
5724 xtensa_set_frag_assembly_state (frag
);
5729 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5735 /* Round up a section size to the appropriate boundary. */
5738 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5740 return size
; /* Byte alignment is fine. */
5745 md_pcrel_from (fixS
*fixP
)
5748 static xtensa_insnbuf insnbuf
= NULL
;
5749 static xtensa_insnbuf slotbuf
= NULL
;
5752 xtensa_opcode opcode
;
5755 xtensa_isa isa
= xtensa_default_isa
;
5756 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5757 bfd_boolean alt_reloc
;
5759 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5762 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5767 insnbuf
= xtensa_insnbuf_alloc (isa
);
5768 slotbuf
= xtensa_insnbuf_alloc (isa
);
5771 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5772 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5773 fmt
= xtensa_format_decode (isa
, insnbuf
);
5775 if (fmt
== XTENSA_UNDEFINED
)
5776 as_fatal (_("bad instruction format"));
5778 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5779 as_fatal (_("invalid relocation"));
5781 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5782 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5784 /* Check for "alternate" relocations (operand not specified). None
5785 of the current uses for these are really PC-relative. */
5786 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5788 if (opcode
!= xtensa_l32r_opcode
5789 && opcode
!= xtensa_const16_opcode
)
5790 as_fatal (_("invalid relocation for '%s' instruction"),
5791 xtensa_opcode_name (isa
, opcode
));
5795 opnum
= get_relaxable_immed (opcode
);
5797 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5798 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5800 as_bad_where (fixP
->fx_file
,
5802 _("invalid relocation for operand %d of '%s'"),
5803 opnum
, xtensa_opcode_name (isa
, opcode
));
5806 return 0 - opnd_value
;
5810 /* TC_FORCE_RELOCATION hook */
5813 xtensa_force_relocation (fixS
*fix
)
5815 switch (fix
->fx_r_type
)
5817 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5818 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5819 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5820 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5821 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5822 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5823 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5824 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5825 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5826 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5827 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5828 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5829 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5830 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5831 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5832 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5838 if (linkrelax
&& fix
->fx_addsy
5839 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5842 return generic_force_reloc (fix
);
5846 /* TC_VALIDATE_FIX_SUB hook */
5849 xtensa_validate_fix_sub (fixS
*fix
)
5851 segT add_symbol_segment
, sub_symbol_segment
;
5853 /* The difference of two symbols should be resolved by the assembler when
5854 linkrelax is not set. If the linker may relax the section containing
5855 the symbols, then an Xtensa DIFF relocation must be generated so that
5856 the linker knows to adjust the difference value. */
5857 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5860 /* Make sure both symbols are in the same segment, and that segment is
5861 "normal" and relaxable. If the segment is not "normal", then the
5862 fix is not valid. If the segment is not "relaxable", then the fix
5863 should have been handled earlier. */
5864 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5865 if (! SEG_NORMAL (add_symbol_segment
) ||
5866 ! relaxable_section (add_symbol_segment
))
5868 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5869 return (sub_symbol_segment
== add_symbol_segment
);
5873 /* NO_PSEUDO_DOT hook */
5875 /* This function has nothing to do with pseudo dots, but this is the
5876 nearest macro to where the check needs to take place. FIXME: This
5880 xtensa_check_inside_bundle (void)
5882 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5883 as_bad (_("directives are not valid inside bundles"));
5885 /* This function must always return FALSE because it is called via a
5886 macro that has nothing to do with bundling. */
5891 /* md_elf_section_change_hook */
5894 xtensa_elf_section_change_hook (void)
5896 /* Set up the assembly state. */
5897 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5898 xtensa_set_frag_assembly_state (frag_now
);
5902 /* tc_fix_adjustable hook */
5905 xtensa_fix_adjustable (fixS
*fixP
)
5907 /* We need the symbol name for the VTABLE entries. */
5908 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5909 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5916 /* tc_symbol_new_hook */
5918 symbolS
*expr_symbols
= NULL
;
5921 xtensa_symbol_new_hook (symbolS
*sym
)
5923 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5925 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5932 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5934 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5937 /* Subtracted symbols are only allowed for a few relocation types, and
5938 unless linkrelax is enabled, they should not make it to this point. */
5939 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5940 || fixP
->fx_r_type
== BFD_RELOC_16
5941 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5944 switch (fixP
->fx_r_type
)
5946 case BFD_RELOC_32_PCREL
:
5952 switch (fixP
->fx_r_type
)
5955 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5956 fixP
->fx_signed
= 0;
5959 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5960 fixP
->fx_signed
= 0;
5963 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5964 fixP
->fx_signed
= 0;
5970 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5971 - S_GET_VALUE (fixP
->fx_subsy
));
5973 /* The difference value gets written out, and the DIFF reloc
5974 identifies the address of the subtracted symbol (i.e., the one
5975 with the lowest address). */
5977 fixP
->fx_offset
-= val
;
5978 fixP
->fx_subsy
= NULL
;
5980 else if (! fixP
->fx_addsy
)
5987 case BFD_RELOC_XTENSA_PLT
:
5988 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5989 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5992 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5993 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5994 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5995 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5996 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5997 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5998 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6001 case BFD_RELOC_XTENSA_SLOT0_OP
:
6002 case BFD_RELOC_XTENSA_SLOT1_OP
:
6003 case BFD_RELOC_XTENSA_SLOT2_OP
:
6004 case BFD_RELOC_XTENSA_SLOT3_OP
:
6005 case BFD_RELOC_XTENSA_SLOT4_OP
:
6006 case BFD_RELOC_XTENSA_SLOT5_OP
:
6007 case BFD_RELOC_XTENSA_SLOT6_OP
:
6008 case BFD_RELOC_XTENSA_SLOT7_OP
:
6009 case BFD_RELOC_XTENSA_SLOT8_OP
:
6010 case BFD_RELOC_XTENSA_SLOT9_OP
:
6011 case BFD_RELOC_XTENSA_SLOT10_OP
:
6012 case BFD_RELOC_XTENSA_SLOT11_OP
:
6013 case BFD_RELOC_XTENSA_SLOT12_OP
:
6014 case BFD_RELOC_XTENSA_SLOT13_OP
:
6015 case BFD_RELOC_XTENSA_SLOT14_OP
:
6018 /* Write the tentative value of a PC-relative relocation to a
6019 local symbol into the instruction. The value will be ignored
6020 by the linker, and it makes the object file disassembly
6021 readable when all branch targets are encoded in relocations. */
6023 gas_assert (fixP
->fx_addsy
);
6024 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6025 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6027 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6028 - md_pcrel_from (fixP
));
6029 (void) xg_apply_fix_value (fixP
, val
);
6032 else if (! fixP
->fx_addsy
)
6035 if (xg_apply_fix_value (fixP
, val
))
6040 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6041 case BFD_RELOC_XTENSA_TLS_FUNC
:
6042 case BFD_RELOC_XTENSA_TLS_ARG
:
6043 case BFD_RELOC_XTENSA_TLS_CALL
:
6044 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6045 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6046 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6047 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6048 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6049 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6050 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6051 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6052 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6053 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6054 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6055 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6056 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6057 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6058 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6059 /* These all need to be resolved at link-time. Do nothing now. */
6062 case BFD_RELOC_VTABLE_INHERIT
:
6063 case BFD_RELOC_VTABLE_ENTRY
:
6068 as_bad (_("unhandled local relocation fix %s"),
6069 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6075 md_atof (int type
, char *litP
, int *sizeP
)
6077 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6082 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6084 return total_frag_text_expansion (fragP
);
6088 /* Translate internal representation of relocation info to BFD target
6092 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6096 reloc
= XNEW (arelent
);
6097 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6098 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6099 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6101 /* Make sure none of our internal relocations make it this far.
6102 They'd better have been fully resolved by this point. */
6103 gas_assert ((int) fixp
->fx_r_type
> 0);
6105 reloc
->addend
= fixp
->fx_offset
;
6107 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6108 if (reloc
->howto
== NULL
)
6110 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6111 _("cannot represent `%s' relocation in object file"),
6112 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6113 free (reloc
->sym_ptr_ptr
);
6118 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6119 as_fatal (_("internal error; cannot generate `%s' relocation"),
6120 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6126 /* Checks for resource conflicts between instructions. */
6128 /* The func unit stuff could be implemented as bit-vectors rather
6129 than the iterative approach here. If it ends up being too
6130 slow, we will switch it. */
6133 new_resource_table (void *data
,
6136 unit_num_copies_func uncf
,
6137 opcode_num_units_func onuf
,
6138 opcode_funcUnit_use_unit_func ouuf
,
6139 opcode_funcUnit_use_stage_func ousf
)
6142 resource_table
*rt
= XNEW (resource_table
);
6144 rt
->cycles
= cycles
;
6145 rt
->allocated_cycles
= cycles
;
6147 rt
->unit_num_copies
= uncf
;
6148 rt
->opcode_num_units
= onuf
;
6149 rt
->opcode_unit_use
= ouuf
;
6150 rt
->opcode_unit_stage
= ousf
;
6152 rt
->units
= XCNEWVEC (unsigned char *, cycles
);
6153 for (i
= 0; i
< cycles
; i
++)
6154 rt
->units
[i
] = XCNEWVEC (unsigned char, nu
);
6161 clear_resource_table (resource_table
*rt
)
6164 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6165 for (j
= 0; j
< rt
->num_units
; j
++)
6166 rt
->units
[i
][j
] = 0;
6170 /* We never shrink it, just fake it into thinking so. */
6173 resize_resource_table (resource_table
*rt
, int cycles
)
6177 rt
->cycles
= cycles
;
6178 if (cycles
<= rt
->allocated_cycles
)
6181 old_cycles
= rt
->allocated_cycles
;
6182 rt
->allocated_cycles
= cycles
;
6184 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6185 for (i
= 0; i
< old_cycles
; i
++)
6186 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6187 for (i
= old_cycles
; i
< cycles
; i
++)
6188 rt
->units
[i
] = XCNEWVEC (unsigned char, rt
->num_units
);
6193 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6196 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6198 for (i
= 0; i
< uses
; i
++)
6200 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6201 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6202 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6203 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6204 if (copies_in_use
>= copies
)
6212 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6215 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6217 for (i
= 0; i
< uses
; i
++)
6219 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6220 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6221 /* Note that this allows resources to be oversubscribed. That's
6222 essential to the way the optional scheduler works.
6223 resources_available reports when a resource is over-subscribed,
6224 so it's easy to tell. */
6225 rt
->units
[stage
+ cycle
][unit
]++;
6231 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6234 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6236 for (i
= 0; i
< uses
; i
++)
6238 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6239 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6240 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6241 rt
->units
[stage
+ cycle
][unit
]--;
6246 /* Wrapper functions make parameterized resource reservation
6250 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6252 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6258 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6260 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6265 /* Note that this function does not check issue constraints, but
6266 solely whether the hardware is available to execute the given
6267 instructions together. It also doesn't check if the tinsns
6268 write the same state, or access the same tieports. That is
6269 checked by check_t1_t2_reads_and_writes. */
6272 resources_conflict (vliw_insn
*vinsn
)
6275 static resource_table
*rt
= NULL
;
6277 /* This is the most common case by far. Optimize it. */
6278 if (vinsn
->num_slots
== 1)
6283 xtensa_isa isa
= xtensa_default_isa
;
6284 rt
= new_resource_table
6285 (isa
, xtensa_num_pipe_stages
,
6286 xtensa_isa_num_funcUnits (isa
),
6287 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6288 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6289 opcode_funcUnit_use_unit
,
6290 opcode_funcUnit_use_stage
);
6293 clear_resource_table (rt
);
6295 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6297 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6299 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6306 /* finish_vinsn, emit_single_op and helper functions. */
6308 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6309 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6310 static void xg_assemble_vliw_tokens (vliw_insn
*);
6313 /* We have reached the end of a bundle; emit into the frag. */
6316 finish_vinsn (vliw_insn
*vinsn
)
6321 if (find_vinsn_conflicts (vinsn
))
6323 xg_clear_vinsn (vinsn
);
6327 /* First, find a format that works. */
6328 if (vinsn
->format
== XTENSA_UNDEFINED
)
6329 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6331 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6332 && produce_flix
== FLIX_NONE
)
6334 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6335 xg_clear_vinsn (vinsn
);
6339 if (vinsn
->format
== XTENSA_UNDEFINED
)
6341 as_bad (_("couldn't find a valid instruction format"));
6342 fprintf (stderr
, _(" ops were: "));
6343 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6344 fprintf (stderr
, _(" %s;"),
6345 xtensa_opcode_name (xtensa_default_isa
,
6346 vinsn
->slots
[i
].opcode
));
6347 fprintf (stderr
, _("\n"));
6348 xg_clear_vinsn (vinsn
);
6352 if (vinsn
->num_slots
6353 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6355 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6356 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6357 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6359 xg_clear_vinsn (vinsn
);
6363 if (resources_conflict (vinsn
))
6365 as_bad (_("illegal resource usage in bundle"));
6366 fprintf (stderr
, " ops were: ");
6367 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6368 fprintf (stderr
, " %s;",
6369 xtensa_opcode_name (xtensa_default_isa
,
6370 vinsn
->slots
[i
].opcode
));
6371 fprintf (stderr
, "\n");
6372 xg_clear_vinsn (vinsn
);
6376 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6378 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6380 symbolS
*lit_sym
= NULL
;
6382 bfd_boolean e
= FALSE
;
6383 bfd_boolean saved_density
= density_supported
;
6385 /* We don't want to narrow ops inside multi-slot bundles. */
6386 if (vinsn
->num_slots
> 1)
6387 density_supported
= FALSE
;
6389 istack_init (&slotstack
);
6390 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6392 vinsn
->slots
[i
].opcode
=
6393 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6395 vinsn
->slots
[i
].ntok
= 0;
6398 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6404 density_supported
= saved_density
;
6408 xg_clear_vinsn (vinsn
);
6412 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6414 TInsn
*insn
= &slotstack
.insn
[j
];
6415 if (insn
->insn_type
== ITYPE_LITERAL
)
6417 gas_assert (lit_sym
== NULL
);
6418 lit_sym
= xg_assemble_literal (insn
);
6422 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6424 xg_resolve_literals (insn
, lit_sym
);
6425 if (j
!= slotstack
.ninsn
- 1)
6426 emit_single_op (insn
);
6430 if (vinsn
->num_slots
> 1)
6432 if (opcode_fits_format_slot
6433 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6436 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6440 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6441 if (vinsn
->format
== XTENSA_UNDEFINED
)
6442 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6444 vinsn
->slots
[i
].opcode
6445 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6448 vinsn
->slots
[i
].ntok
= 0;
6453 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6454 vinsn
->format
= XTENSA_UNDEFINED
;
6459 /* Now check resource conflicts on the modified bundle. */
6460 if (resources_conflict (vinsn
))
6462 as_bad (_("illegal resource usage in bundle"));
6463 fprintf (stderr
, " ops were: ");
6464 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6465 fprintf (stderr
, " %s;",
6466 xtensa_opcode_name (xtensa_default_isa
,
6467 vinsn
->slots
[i
].opcode
));
6468 fprintf (stderr
, "\n");
6469 xg_clear_vinsn (vinsn
);
6473 /* First, find a format that works. */
6474 if (vinsn
->format
== XTENSA_UNDEFINED
)
6475 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6477 xg_assemble_vliw_tokens (vinsn
);
6479 xg_clear_vinsn (vinsn
);
6481 xtensa_check_frag_count ();
6485 /* Given an vliw instruction, what conflicts are there in register
6486 usage and in writes to states and queues?
6488 This function does two things:
6489 1. Reports an error when a vinsn contains illegal combinations
6490 of writes to registers states or queues.
6491 2. Marks individual tinsns as not relaxable if the combination
6492 contains antidependencies.
6494 Job 2 handles things like swap semantics in instructions that need
6495 to be relaxed. For example,
6499 normally would be relaxed to
6504 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6506 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6508 then we can't relax it into
6511 { add a0, a1, a0 ; add a2, a0, a4 ; }
6513 because the value of a0 is trashed before the second add can read it. */
6515 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6518 find_vinsn_conflicts (vliw_insn
*vinsn
)
6522 xtensa_isa isa
= xtensa_default_isa
;
6524 gas_assert (!past_xtensa_end
);
6526 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6528 TInsn
*op1
= &vinsn
->slots
[i
];
6529 if (op1
->is_specific_opcode
)
6530 op1
->keep_wide
= TRUE
;
6532 op1
->keep_wide
= FALSE
;
6535 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6537 TInsn
*op1
= &vinsn
->slots
[i
];
6539 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6542 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6546 TInsn
*op2
= &vinsn
->slots
[j
];
6547 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6548 switch (conflict_type
)
6551 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6552 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6553 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6556 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6557 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6558 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6561 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6562 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6563 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6566 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6567 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6568 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6571 /* Everything is OK. */
6574 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6575 || conflict_type
== 'a');
6582 as_bad (_("multiple branches or jumps in the same bundle"));
6590 /* Check how the state used by t1 and t2 relate.
6593 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6594 case B: no relationship between what is read and written (both could
6595 read the same reg though)
6596 case C: t1 writes a register t2 writes (a register conflict within a
6598 case D: t1 writes a state that t2 also writes
6599 case E: t1 writes a tie queue that t2 also writes
6600 case F: two volatile queue accesses
6604 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6606 xtensa_isa isa
= xtensa_default_isa
;
6607 xtensa_regfile t1_regfile
, t2_regfile
;
6609 int t1_base_reg
, t1_last_reg
;
6610 int t2_base_reg
, t2_last_reg
;
6611 char t1_inout
, t2_inout
;
6613 char conflict
= 'b';
6618 bfd_boolean t1_volatile
= FALSE
;
6619 bfd_boolean t2_volatile
= FALSE
;
6621 /* Check registers. */
6622 for (j
= 0; j
< t2
->ntok
; j
++)
6624 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6627 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6628 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6629 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6631 for (i
= 0; i
< t1
->ntok
; i
++)
6633 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6636 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6638 if (t1_regfile
!= t2_regfile
)
6641 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6642 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6644 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6645 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6647 if (t1_inout
== 'm' || t1_inout
== 'o'
6648 || t2_inout
== 'm' || t2_inout
== 'o')
6655 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6656 t1_last_reg
= (t1_base_reg
6657 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6659 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6661 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6663 if (t1_reg
!= t2_reg
)
6666 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6672 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6678 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6686 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6687 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6688 for (j
= 0; j
< t2_states
; j
++)
6690 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6691 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6692 for (i
= 0; i
< t1_states
; i
++)
6694 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6695 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6696 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6699 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6705 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6711 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6716 /* Check tieports. */
6717 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6718 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6719 for (j
= 0; j
< t2_interfaces
; j
++)
6721 xtensa_interface t2_int
6722 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6723 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6725 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6726 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6729 for (i
= 0; i
< t1_interfaces
; i
++)
6731 xtensa_interface t1_int
6732 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6733 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6735 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6736 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6739 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6742 if (t1_int
!= t2_int
)
6745 if (t2_inout
== 'i' && t1_inout
== 'o')
6751 if (t1_inout
== 'i' && t2_inout
== 'o')
6757 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6766 static xtensa_format
6767 xg_find_narrowest_format (vliw_insn
*vinsn
)
6769 /* Right now we assume that the ops within the vinsn are properly
6770 ordered for the slots that the programmer wanted them in. In
6771 other words, we don't rearrange the ops in hopes of finding a
6772 better format. The scheduler handles that. */
6774 xtensa_isa isa
= xtensa_default_isa
;
6775 xtensa_format format
;
6776 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6778 if (vinsn
->num_slots
== 1)
6779 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6781 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6784 xg_copy_vinsn (&v_copy
, vinsn
);
6785 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6789 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6791 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6793 v_copy
.slots
[slot
].opcode
=
6794 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6795 v_copy
.slots
[slot
].ntok
= 0;
6798 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6801 else if (v_copy
.num_slots
> 1)
6804 /* Try the widened version. */
6805 if (!v_copy
.slots
[slot
].keep_wide
6806 && !v_copy
.slots
[slot
].is_specific_opcode
6807 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6809 && opcode_fits_format_slot (widened
.opcode
,
6812 v_copy
.slots
[slot
] = widened
;
6817 if (fit
== v_copy
.num_slots
)
6819 xg_copy_vinsn (vinsn
, &v_copy
);
6820 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6821 vinsn
->format
= format
;
6827 if (format
== xtensa_isa_num_formats (isa
))
6828 return XTENSA_UNDEFINED
;
6834 /* Return the additional space needed in a frag
6835 for possible relaxations of any ops in a VLIW insn.
6836 Also fill out the relaxations that might be required of
6837 each tinsn in the vinsn. */
6840 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6842 bfd_boolean finish_frag
= FALSE
;
6843 int extra_space
= 0;
6846 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6848 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6849 if (!tinsn_has_symbolic_operands (tinsn
))
6851 /* A narrow instruction could be widened later to help
6852 alignment issues. */
6853 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6854 && !tinsn
->is_specific_opcode
6855 && vinsn
->num_slots
== 1)
6857 /* Difference in bytes between narrow and wide insns... */
6859 tinsn
->subtype
= RELAX_NARROW
;
6864 if (workaround_b_j_loop_end
6865 && tinsn
->opcode
== xtensa_jx_opcode
6866 && use_transform ())
6868 /* Add 2 of these. */
6869 extra_space
+= 3; /* for the nop size */
6870 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6873 /* Need to assemble it with space for the relocation. */
6874 if (xg_is_relaxable_insn (tinsn
, 0)
6875 && !tinsn
->is_specific_opcode
)
6877 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6878 int max_literal_size
=
6879 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6881 tinsn
->literal_space
= max_literal_size
;
6883 tinsn
->subtype
= RELAX_IMMED
;
6884 extra_space
+= max_size
;
6888 /* A fix record will be added for this instruction prior
6889 to relaxation, so make it end the frag. */
6894 *pfinish_frag
= finish_frag
;
6900 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6902 xtensa_isa isa
= xtensa_default_isa
;
6903 int slot
, chosen_slot
;
6905 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6906 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6907 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6909 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6910 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6912 if (slot
== chosen_slot
)
6913 vinsn
->slots
[slot
] = *tinsn
;
6916 vinsn
->slots
[slot
].opcode
=
6917 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6918 vinsn
->slots
[slot
].ntok
= 0;
6919 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6926 emit_single_op (TInsn
*orig_insn
)
6929 IStack istack
; /* put instructions into here */
6930 symbolS
*lit_sym
= NULL
;
6931 symbolS
*label_sym
= NULL
;
6933 istack_init (&istack
);
6935 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6936 Because the scheduling and bundling characteristics of movi and
6937 l32r or const16 are so different, we can do much better if we relax
6938 it prior to scheduling and bundling, rather than after. */
6939 if ((orig_insn
->opcode
== xtensa_movi_opcode
6940 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6941 && !cur_vinsn
.inside_bundle
6942 && (orig_insn
->tok
[1].X_op
== O_symbol
6943 || orig_insn
->tok
[1].X_op
== O_pltrel
6944 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6945 || orig_insn
->tok
[1].X_op
== O_tlsarg
6946 || orig_insn
->tok
[1].X_op
== O_tpoff
6947 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6948 && !orig_insn
->is_specific_opcode
&& use_transform ())
6949 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6951 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6954 for (i
= 0; i
< istack
.ninsn
; i
++)
6956 TInsn
*insn
= &istack
.insn
[i
];
6957 switch (insn
->insn_type
)
6960 gas_assert (lit_sym
== NULL
);
6961 lit_sym
= xg_assemble_literal (insn
);
6965 static int relaxed_sym_idx
= 0;
6966 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
6967 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6969 gas_assert (label_sym
== NULL
);
6970 label_sym
= symbol_find_or_make (label
);
6971 gas_assert (label_sym
);
6979 xg_resolve_literals (insn
, lit_sym
);
6981 xg_resolve_labels (insn
, label_sym
);
6983 bundle_tinsn (insn
, &v
);
6998 total_frag_text_expansion (fragS
*fragP
)
7001 int total_expansion
= 0;
7003 for (slot
= 0; slot
< config_max_slots
; slot
++)
7004 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7006 return total_expansion
;
7010 /* Emit a vliw instruction to the current fragment. */
7013 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7015 bfd_boolean finish_frag
;
7016 bfd_boolean is_jump
= FALSE
;
7017 bfd_boolean is_branch
= FALSE
;
7018 xtensa_isa isa
= xtensa_default_isa
;
7023 struct dwarf2_line_info debug_line
;
7024 bfd_boolean loc_directive_seen
= FALSE
;
7027 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7029 if (generating_literals
)
7031 static int reported
= 0;
7033 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7034 _("cannot assemble into a literal fragment"));
7041 if (frag_now_fix () != 0
7042 && (! frag_now
->tc_frag_data
.is_insn
7043 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7044 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7045 || (directive_state
[directive_longcalls
]
7046 != frag_now
->tc_frag_data
.use_longcalls
)
7047 || (directive_state
[directive_absolute_literals
]
7048 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7050 frag_wane (frag_now
);
7052 xtensa_set_frag_assembly_state (frag_now
);
7055 if (workaround_a0_b_retw
7056 && vinsn
->num_slots
== 1
7057 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7058 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7059 && use_transform ())
7061 has_a0_b_retw
= TRUE
;
7063 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7064 After the first assembly pass we will check all of them and
7065 add a nop if needed. */
7066 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7067 frag_var (rs_machine_dependent
, 4, 4,
7068 RELAX_ADD_NOP_IF_A0_B_RETW
,
7069 frag_now
->fr_symbol
,
7070 frag_now
->fr_offset
,
7072 xtensa_set_frag_assembly_state (frag_now
);
7073 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7074 frag_var (rs_machine_dependent
, 4, 4,
7075 RELAX_ADD_NOP_IF_A0_B_RETW
,
7076 frag_now
->fr_symbol
,
7077 frag_now
->fr_offset
,
7079 xtensa_set_frag_assembly_state (frag_now
);
7082 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7084 tinsn
= &vinsn
->slots
[slot
];
7086 /* See if the instruction implies an aligned section. */
7087 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7088 record_alignment (now_seg
, 2);
7090 /* Determine the best line number for debug info. */
7091 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7092 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7093 || tinsn
->debug_line
.line
< debug_line
.line
7094 || tinsn
->debug_line
.column
< debug_line
.column
))
7095 debug_line
= tinsn
->debug_line
;
7096 if (tinsn
->loc_directive_seen
)
7097 loc_directive_seen
= TRUE
;
7100 /* Special cases for instructions that force an alignment... */
7101 /* None of these opcodes are bundle-able. */
7102 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7106 /* Remember the symbol that marks the end of the loop in the frag
7107 that marks the start of the loop. This way we can easily find
7108 the end of the loop at the beginning, without adding special code
7109 to mark the loop instructions themselves. */
7110 symbolS
*target_sym
= NULL
;
7111 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7112 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7114 xtensa_set_frag_assembly_state (frag_now
);
7115 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7117 max_fill
= get_text_align_max_fill_size
7118 (get_text_align_power (xtensa_fetch_width
),
7119 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7121 if (use_transform ())
7122 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7123 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7125 frag_var (rs_machine_dependent
, 0, 0,
7126 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7127 xtensa_set_frag_assembly_state (frag_now
);
7130 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7131 && !vinsn
->slots
[0].is_specific_opcode
)
7133 xtensa_mark_literal_pool_location ();
7134 xtensa_move_labels (frag_now
, 0);
7135 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7138 if (vinsn
->num_slots
== 1)
7140 if (workaround_a0_b_retw
&& use_transform ())
7141 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7142 is_register_writer (&vinsn
->slots
[0], "a", 0));
7144 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7145 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7148 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7150 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7152 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7154 /* vinsn_to_insnbuf will produce the error. */
7155 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7157 f
= frag_more (insn_size
+ extra_space
);
7158 xtensa_set_frag_assembly_state (frag_now
);
7159 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7162 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7163 if (vinsn
->format
== XTENSA_UNDEFINED
)
7166 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7168 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7169 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7172 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7174 tinsn
= &vinsn
->slots
[slot
];
7175 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7176 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7177 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7178 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7179 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7181 frag_now
->tc_frag_data
.literal_frags
[slot
] =
7182 tinsn
->tok
[1].X_add_symbol
->sy_frag
;
7184 if (tinsn
->literal_space
!= 0)
7185 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7186 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7188 if (tinsn
->subtype
== RELAX_NARROW
)
7189 gas_assert (vinsn
->num_slots
== 1);
7190 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7192 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7195 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7196 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7200 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7201 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7205 frag_variant (rs_machine_dependent
,
7206 extra_space
, extra_space
, RELAX_SLOTS
,
7207 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7208 xtensa_set_frag_assembly_state (frag_now
);
7211 /* Special cases for loops:
7212 close_loop_end should be inserted AFTER short_loop.
7213 Make sure that CLOSE loops are processed BEFORE short_loops
7214 when converting them. */
7216 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7217 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7218 && !vinsn
->slots
[0].is_specific_opcode
)
7220 if (workaround_short_loop
&& use_transform ())
7222 maybe_has_short_loop
= TRUE
;
7223 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7224 frag_var (rs_machine_dependent
, 4, 4,
7225 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7226 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7227 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7228 frag_var (rs_machine_dependent
, 4, 4,
7229 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7230 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7233 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7234 loop at least 12 bytes away from another loop's end. */
7235 if (workaround_close_loop_end
&& use_transform ())
7237 maybe_has_close_loop_end
= TRUE
;
7238 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7239 frag_var (rs_machine_dependent
, 12, 12,
7240 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7241 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7245 if (use_transform ())
7249 gas_assert (finish_frag
);
7250 frag_var (rs_machine_dependent
,
7251 xtensa_fetch_width
, xtensa_fetch_width
,
7253 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7254 xtensa_set_frag_assembly_state (frag_now
);
7255 xtensa_maybe_create_trampoline_frag ();
7256 /* Always create one here. */
7257 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7259 else if (is_branch
&& do_align_targets ())
7261 gas_assert (finish_frag
);
7262 frag_var (rs_machine_dependent
,
7263 xtensa_fetch_width
, xtensa_fetch_width
,
7264 RELAX_MAYBE_UNREACHABLE
,
7265 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7266 xtensa_set_frag_assembly_state (frag_now
);
7267 frag_var (rs_machine_dependent
,
7269 RELAX_MAYBE_DESIRE_ALIGN
,
7270 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7271 xtensa_set_frag_assembly_state (frag_now
);
7275 /* Now, if the original opcode was a call... */
7276 if (do_align_targets ()
7277 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7279 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7280 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7281 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7282 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7283 xtensa_set_frag_assembly_state (frag_now
);
7286 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7288 frag_wane (frag_now
);
7290 xtensa_set_frag_assembly_state (frag_now
);
7295 /* xtensa_end and helper functions. */
7297 static void xtensa_cleanup_align_frags (void);
7298 static void xtensa_fix_target_frags (void);
7299 static void xtensa_mark_narrow_branches (void);
7300 static void xtensa_mark_zcl_first_insns (void);
7301 static void xtensa_mark_difference_of_two_symbols (void);
7302 static void xtensa_fix_a0_b_retw_frags (void);
7303 static void xtensa_fix_b_j_loop_end_frags (void);
7304 static void xtensa_fix_close_loop_end_frags (void);
7305 static void xtensa_fix_short_loop_frags (void);
7306 static void xtensa_sanity_check (void);
7307 static void xtensa_add_config_info (void);
7312 directive_balance ();
7313 xtensa_flush_pending_output ();
7315 past_xtensa_end
= TRUE
;
7317 xtensa_move_literals ();
7319 xtensa_reorder_segments ();
7320 xtensa_cleanup_align_frags ();
7321 xtensa_fix_target_frags ();
7322 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7323 xtensa_fix_a0_b_retw_frags ();
7324 if (workaround_b_j_loop_end
)
7325 xtensa_fix_b_j_loop_end_frags ();
7327 /* "close_loop_end" should be processed BEFORE "short_loop". */
7328 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7329 xtensa_fix_close_loop_end_frags ();
7331 if (workaround_short_loop
&& maybe_has_short_loop
)
7332 xtensa_fix_short_loop_frags ();
7334 xtensa_mark_narrow_branches ();
7335 xtensa_mark_zcl_first_insns ();
7337 xtensa_sanity_check ();
7339 xtensa_add_config_info ();
7341 xtensa_check_frag_count ();
7345 struct trampoline_frag
7347 struct trampoline_frag
*next
;
7348 bfd_boolean needs_jump_around
;
7353 struct trampoline_seg
7355 struct trampoline_seg
*next
;
7357 struct trampoline_frag trampoline_list
;
7360 static struct trampoline_seg trampoline_seg_list
;
7361 #define J_RANGE (128 * 1024)
7363 static int unreachable_count
= 0;
7367 xtensa_maybe_create_trampoline_frag (void)
7369 if (!use_trampolines
)
7372 /* We create an area for possible trampolines every 10 unreachable frags.
7373 These are preferred over the ones not preceded by an unreachable frag,
7374 because we don't have to jump around them. This function is called after
7375 each RELAX_UNREACHABLE frag is created. */
7377 if (++unreachable_count
> 10)
7379 xtensa_create_trampoline_frag (FALSE
);
7380 clear_frag_count ();
7381 unreachable_count
= 0;
7386 xtensa_check_frag_count (void)
7388 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7391 /* We create an area for possible trampolines every 8000 frags or so. This
7392 is an estimate based on the max range of a "j" insn (+/-128K) divided
7393 by a typical frag byte count (16), minus a few for safety. This function
7394 is called after each source line is processed. */
7396 if (get_frag_count () > 8000)
7398 xtensa_create_trampoline_frag (TRUE
);
7399 clear_frag_count ();
7400 unreachable_count
= 0;
7403 /* We create an area for a possible literal pool every N (default 5000)
7405 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7408 static xtensa_insnbuf trampoline_buf
= NULL
;
7409 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7411 static xtensa_insnbuf litpool_buf
= NULL
;
7412 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7414 #define TRAMPOLINE_FRAG_SIZE 3000
7417 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7419 /* Emit a frag where we can place intermediate jump instructions,
7420 in case we need to jump farther than 128K bytes.
7421 Each jump instruction takes three bytes.
7422 We allocate enough for 1000 trampolines in each frag.
7423 If that's not enough, oh well. */
7425 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7426 struct trampoline_frag
*tf
;
7429 int size
= TRAMPOLINE_FRAG_SIZE
;
7431 for ( ; ts
; ts
= ts
->next
)
7433 if (ts
->seg
== now_seg
)
7439 ts
= XCNEW(struct trampoline_seg
);
7440 ts
->next
= trampoline_seg_list
.next
;
7441 trampoline_seg_list
.next
= ts
;
7445 frag_wane (frag_now
);
7447 xtensa_set_frag_assembly_state (frag_now
);
7448 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7449 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7450 if (trampoline_buf
== NULL
)
7452 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7453 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7455 tf
= XNEW (struct trampoline_frag
);
7456 tf
->next
= ts
->trampoline_list
.next
;
7457 ts
->trampoline_list
.next
= tf
;
7458 tf
->needs_jump_around
= needs_jump_around
;
7464 static struct trampoline_seg
*
7465 find_trampoline_seg (asection
*seg
)
7467 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7469 for ( ; ts
; ts
= ts
->next
)
7479 void dump_trampolines (void);
7482 dump_trampolines (void)
7484 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7486 for ( ; ts
; ts
= ts
->next
)
7488 asection
*seg
= ts
->seg
;
7492 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7493 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7494 for ( ; tf
; tf
= tf
->next
)
7496 if (tf
->fragP
== NULL
)
7498 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7499 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7500 tf
->needs_jump_around
? "T" : "F");
7505 static void dump_litpools (void) __attribute__ ((unused
));
7508 dump_litpools (void)
7510 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7511 struct litpool_frag
*lpf
;
7513 for ( ; lps
; lps
= lps
->next
)
7515 printf("litpool seg %s\n", lps
->seg
->name
);
7516 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7518 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7520 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7522 if (litfrag
->fr_fix
== 4)
7524 litfrag
= litfrag
->fr_next
;
7526 printf(" %ld <%d:%d> (%d) [%d]: ",
7527 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7528 lpf
->fragP
->fr_line
, count
);
7529 //dump_frag(lpf->fragP);
7535 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7536 bfd_boolean only_if_needed
)
7538 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7540 struct litpool_frag
*lpf
;
7541 bfd_boolean needed
= FALSE
;
7543 if (use_literal_section
|| !auto_litpools
)
7546 for ( ; lps
; lps
= lps
->next
)
7548 if (lps
->seg
== now_seg
)
7554 lps
= XCNEW (struct litpool_seg
);
7555 lps
->next
= litpool_seg_list
.next
;
7556 litpool_seg_list
.next
= lps
;
7558 lps
->frag_list
.next
= &lps
->frag_list
;
7559 lps
->frag_list
.prev
= &lps
->frag_list
;
7560 /* Put candidate literal pool at the beginning of every section,
7561 so that even when section starts with literal load there's a
7562 literal pool available. */
7563 lps
->frag_count
= auto_litpool_limit
;
7572 if (past_xtensa_end
|| !use_transform() ||
7573 frag_now
->tc_frag_data
.is_no_transform
)
7577 if (auto_litpool_limit
<= 0)
7579 /* Don't create a litpool based only on frag count. */
7582 else if (lps
->frag_count
> auto_litpool_limit
)
7599 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7600 /* Create a potential site for a literal pool. */
7601 frag_wane (frag_now
);
7603 xtensa_set_frag_assembly_state (frag_now
);
7605 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7606 fragP
->tc_frag_data
.literal_frag
= fragP
;
7607 frag_var (rs_machine_dependent
, size
, size
,
7609 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7610 RELAX_LITERAL_POOL_BEGIN
,
7612 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7613 frag_variant (rs_machine_dependent
, 0, 0,
7614 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7615 xtensa_set_frag_assembly_state (frag_now
);
7619 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7620 just record it here. */
7624 lpf
= XNEW (struct litpool_frag
);
7625 /* Insert at tail of circular list. */
7627 lps
->frag_list
.prev
->next
= lpf
;
7628 lpf
->next
= &lps
->frag_list
;
7629 lpf
->prev
= lps
->frag_list
.prev
;
7630 lps
->frag_list
.prev
= lpf
;
7632 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7633 lpf
->original_priority
= lpf
->priority
;
7635 lps
->frag_count
= 0;
7639 xtensa_cleanup_align_frags (void)
7644 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7645 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7648 /* Walk over all of the fragments in a subsection. */
7649 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7651 if ((fragP
->fr_type
== rs_align
7652 || fragP
->fr_type
== rs_align_code
7653 || (fragP
->fr_type
== rs_machine_dependent
7654 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7655 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7656 && fragP
->fr_fix
== 0)
7658 fragS
*next
= fragP
->fr_next
;
7661 && next
->fr_fix
== 0
7662 && next
->fr_type
== rs_machine_dependent
7663 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7666 next
= next
->fr_next
;
7669 /* If we don't widen branch targets, then they
7670 will be easier to align. */
7671 if (fragP
->tc_frag_data
.is_branch_target
7672 && fragP
->fr_opcode
== fragP
->fr_literal
7673 && fragP
->fr_type
== rs_machine_dependent
7674 && fragP
->fr_subtype
== RELAX_SLOTS
7675 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7677 if (fragP
->fr_type
== rs_machine_dependent
7678 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7679 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7685 /* Re-process all of the fragments looking to convert all of the
7686 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7687 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7688 Otherwise, convert to a .fill 0. */
7691 xtensa_fix_target_frags (void)
7696 /* When this routine is called, all of the subsections are still intact
7697 so we walk over subsections instead of sections. */
7698 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7699 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7703 /* Walk over all of the fragments in a subsection. */
7704 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7706 if (fragP
->fr_type
== rs_machine_dependent
7707 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7709 if (next_frag_is_branch_target (fragP
))
7710 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7719 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7722 xtensa_mark_narrow_branches (void)
7727 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7728 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7731 /* Walk over all of the fragments in a subsection. */
7732 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7734 if (fragP
->fr_type
== rs_machine_dependent
7735 && fragP
->fr_subtype
== RELAX_SLOTS
7736 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7740 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7741 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7743 if (vinsn
.num_slots
== 1
7744 && xtensa_opcode_is_branch (xtensa_default_isa
,
7745 vinsn
.slots
[0].opcode
) == 1
7746 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7747 && is_narrow_branch_guaranteed_in_range (fragP
,
7750 fragP
->fr_subtype
= RELAX_SLOTS
;
7751 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7752 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7760 /* A branch is typically widened only when its target is out of
7761 range. However, we would like to widen them to align a subsequent
7762 branch target when possible.
7764 Because the branch relaxation code is so convoluted, the optimal solution
7765 (combining the two cases) is difficult to get right in all circumstances.
7766 We therefore go with an "almost as good" solution, where we only
7767 use for alignment narrow branches that definitely will not expand to a
7768 jump and a branch. These functions find and mark these cases. */
7770 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7771 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7772 We start counting beginning with the frag after the 2-byte branch, so the
7773 maximum offset is (4 - 2) + 63 = 65. */
7774 #define MAX_IMMED6 65
7776 static offsetT
unrelaxed_frag_max_size (fragS
*);
7779 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7781 const expressionS
*exp
= &tinsn
->tok
[1];
7782 symbolS
*symbolP
= exp
->X_add_symbol
;
7783 offsetT max_distance
= exp
->X_add_number
;
7786 if (exp
->X_op
!= O_symbol
)
7789 target_frag
= symbol_get_frag (symbolP
);
7791 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7792 if (is_branch_jmp_to_next (tinsn
, fragP
))
7795 /* The branch doesn't branch over it's own frag,
7796 but over the subsequent ones. */
7797 fragP
= fragP
->fr_next
;
7798 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7800 max_distance
+= unrelaxed_frag_max_size (fragP
);
7801 fragP
= fragP
->fr_next
;
7803 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7810 xtensa_mark_zcl_first_insns (void)
7815 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7816 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7819 /* Walk over all of the fragments in a subsection. */
7820 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7822 if (fragP
->fr_type
== rs_machine_dependent
7823 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7824 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7826 /* Find the loop frag. */
7827 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7828 /* Find the first insn frag. */
7829 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7831 /* Handle a corner case that comes up in hardware
7832 diagnostics. The original assembly looks like this:
7835 <empty_frag>--not found by next_non_empty_frag
7838 Depending on the start address, the assembler may or
7839 may not change it to look something like this:
7842 nop--frag isn't empty anymore
7845 So set up to check the alignment of the nop if it
7847 while (loop_frag
!= targ_frag
)
7849 if (loop_frag
->fr_type
== rs_machine_dependent
7850 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7851 || loop_frag
->fr_subtype
7852 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7853 targ_frag
= loop_frag
;
7855 loop_frag
= loop_frag
->fr_next
;
7858 /* Of course, sometimes (mostly for toy test cases) a
7859 zero-cost loop instruction is the last in a section. */
7862 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7863 /* Do not widen a frag that is the first instruction of a
7864 zero-cost loop. It makes that loop harder to align. */
7865 if (targ_frag
->fr_type
== rs_machine_dependent
7866 && targ_frag
->fr_subtype
== RELAX_SLOTS
7867 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7870 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7871 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7874 frag_wane (targ_frag
);
7875 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7879 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7887 /* When a difference-of-symbols expression is encoded as a uleb128 or
7888 sleb128 value, the linker is unable to adjust that value to account for
7889 link-time relaxation. Mark all the code between such symbols so that
7890 its size cannot be changed by linker relaxation. */
7893 xtensa_mark_difference_of_two_symbols (void)
7897 for (expr_sym
= expr_symbols
; expr_sym
;
7898 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7900 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7902 if (exp
->X_op
== O_subtract
)
7904 symbolS
*left
= exp
->X_add_symbol
;
7905 symbolS
*right
= exp
->X_op_symbol
;
7907 /* Difference of two symbols not in the same section
7908 are handled with relocations in the linker. */
7909 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7915 if (symbol_get_frag (left
)->fr_address
7916 <= symbol_get_frag (right
)->fr_address
)
7918 start
= symbol_get_frag (left
);
7919 end
= symbol_get_frag (right
);
7923 start
= symbol_get_frag (right
);
7924 end
= symbol_get_frag (left
);
7927 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7928 walk
= start
->tc_frag_data
.no_transform_end
;
7933 walk
->tc_frag_data
.is_no_transform
= 1;
7934 walk
= walk
->fr_next
;
7936 while (walk
&& walk
->fr_address
< end
->fr_address
);
7938 start
->tc_frag_data
.no_transform_end
= walk
;
7945 /* Re-process all of the fragments looking to convert all of the
7946 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7947 conditional branch or a retw/retw.n, convert this frag to one that
7948 will generate a NOP. In any case close it off with a .fill 0. */
7950 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7953 xtensa_fix_a0_b_retw_frags (void)
7958 /* When this routine is called, all of the subsections are still intact
7959 so we walk over subsections instead of sections. */
7960 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7961 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7965 /* Walk over all of the fragments in a subsection. */
7966 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7968 if (fragP
->fr_type
== rs_machine_dependent
7969 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7971 if (next_instrs_are_b_retw (fragP
))
7973 if (fragP
->tc_frag_data
.is_no_transform
)
7974 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7976 relax_frag_add_nop (fragP
);
7986 next_instrs_are_b_retw (fragS
*fragP
)
7988 xtensa_opcode opcode
;
7990 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7991 static xtensa_insnbuf insnbuf
= NULL
;
7992 static xtensa_insnbuf slotbuf
= NULL
;
7993 xtensa_isa isa
= xtensa_default_isa
;
7996 bfd_boolean branch_seen
= FALSE
;
8000 insnbuf
= xtensa_insnbuf_alloc (isa
);
8001 slotbuf
= xtensa_insnbuf_alloc (isa
);
8004 if (next_fragP
== NULL
)
8007 /* Check for the conditional branch. */
8008 xtensa_insnbuf_from_chars
8009 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8010 fmt
= xtensa_format_decode (isa
, insnbuf
);
8011 if (fmt
== XTENSA_UNDEFINED
)
8014 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8016 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8017 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8019 branch_seen
= (branch_seen
8020 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8026 offset
+= xtensa_format_length (isa
, fmt
);
8027 if (offset
== next_fragP
->fr_fix
)
8029 next_fragP
= next_non_empty_frag (next_fragP
);
8033 if (next_fragP
== NULL
)
8036 /* Check for the retw/retw.n. */
8037 xtensa_insnbuf_from_chars
8038 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8039 fmt
= xtensa_format_decode (isa
, insnbuf
);
8041 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8042 have no problems. */
8043 if (fmt
== XTENSA_UNDEFINED
8044 || xtensa_format_num_slots (isa
, fmt
) != 1)
8047 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8048 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8050 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8057 /* Re-process all of the fragments looking to convert all of the
8058 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8059 loop end label, convert this frag to one that will generate a NOP.
8060 In any case close it off with a .fill 0. */
8062 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8065 xtensa_fix_b_j_loop_end_frags (void)
8070 /* When this routine is called, all of the subsections are still intact
8071 so we walk over subsections instead of sections. */
8072 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8073 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8077 /* Walk over all of the fragments in a subsection. */
8078 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8080 if (fragP
->fr_type
== rs_machine_dependent
8081 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8083 if (next_instr_is_loop_end (fragP
))
8085 if (fragP
->tc_frag_data
.is_no_transform
)
8086 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8088 relax_frag_add_nop (fragP
);
8098 next_instr_is_loop_end (fragS
*fragP
)
8100 const fragS
*next_fragP
;
8102 if (next_frag_is_loop_target (fragP
))
8105 next_fragP
= next_non_empty_frag (fragP
);
8106 if (next_fragP
== NULL
)
8109 if (!next_frag_is_loop_target (next_fragP
))
8112 /* If the size is >= 3 then there is more than one instruction here.
8113 The hardware bug will not fire. */
8114 if (next_fragP
->fr_fix
> 3)
8121 /* Re-process all of the fragments looking to convert all of the
8122 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8123 not MY loop's loop end within 12 bytes, add enough nops here to
8124 make it at least 12 bytes away. In any case close it off with a
8127 static offsetT min_bytes_to_other_loop_end
8128 (fragS
*, fragS
*, offsetT
);
8131 xtensa_fix_close_loop_end_frags (void)
8136 /* When this routine is called, all of the subsections are still intact
8137 so we walk over subsections instead of sections. */
8138 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8139 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8143 fragS
*current_target
= NULL
;
8145 /* Walk over all of the fragments in a subsection. */
8146 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8148 if (fragP
->fr_type
== rs_machine_dependent
8149 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8150 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8151 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8154 && fragP
->fr_type
== rs_machine_dependent
8155 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8158 int bytes_added
= 0;
8160 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8161 /* Max out at 12. */
8162 min_bytes
= min_bytes_to_other_loop_end
8163 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8165 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8167 if (fragP
->tc_frag_data
.is_no_transform
)
8168 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8171 while (min_bytes
+ bytes_added
8172 < REQUIRED_LOOP_DIVIDING_BYTES
)
8176 if (fragP
->fr_var
< length
)
8177 as_fatal (_("fr_var %lu < length %d"),
8178 (long) fragP
->fr_var
, length
);
8181 assemble_nop (length
,
8182 fragP
->fr_literal
+ fragP
->fr_fix
);
8183 fragP
->fr_fix
+= length
;
8184 fragP
->fr_var
-= length
;
8186 bytes_added
+= length
;
8192 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8193 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8199 static offsetT
unrelaxed_frag_min_size (fragS
*);
8202 min_bytes_to_other_loop_end (fragS
*fragP
,
8203 fragS
*current_target
,
8207 fragS
*current_fragP
;
8209 for (current_fragP
= fragP
;
8211 current_fragP
= current_fragP
->fr_next
)
8213 if (current_fragP
->tc_frag_data
.is_loop_target
8214 && current_fragP
!= current_target
)
8217 offset
+= unrelaxed_frag_min_size (current_fragP
);
8219 if (offset
>= max_size
)
8227 unrelaxed_frag_min_size (fragS
*fragP
)
8229 offsetT size
= fragP
->fr_fix
;
8231 /* Add fill size. */
8232 if (fragP
->fr_type
== rs_fill
)
8233 size
+= fragP
->fr_offset
;
8240 unrelaxed_frag_max_size (fragS
*fragP
)
8242 offsetT size
= fragP
->fr_fix
;
8243 switch (fragP
->fr_type
)
8246 /* Empty frags created by the obstack allocation scheme
8247 end up with type 0. */
8252 size
+= fragP
->fr_offset
;
8260 /* No further adjustments needed. */
8262 case rs_machine_dependent
:
8263 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8264 size
+= fragP
->fr_var
;
8267 /* We had darn well better know how big it is. */
8276 /* Re-process all of the fragments looking to convert all
8277 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8280 1) the instruction size count to the loop end label
8281 is too short (<= 2 instructions),
8282 2) loop has a jump or branch in it
8285 1) workaround_all_short_loops is TRUE
8286 2) The generating loop was a 'loopgtz' or 'loopnez'
8287 3) the instruction size count to the loop end label is too short
8289 then convert this frag (and maybe the next one) to generate a NOP.
8290 In any case close it off with a .fill 0. */
8292 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8293 static bfd_boolean
branch_before_loop_end (fragS
*);
8296 xtensa_fix_short_loop_frags (void)
8301 /* When this routine is called, all of the subsections are still intact
8302 so we walk over subsections instead of sections. */
8303 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8304 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8307 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8309 /* Walk over all of the fragments in a subsection. */
8310 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8312 if (fragP
->fr_type
== rs_machine_dependent
8313 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8314 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8317 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8318 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8319 current_opcode
= t_insn
.opcode
;
8320 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8321 current_opcode
) == 1);
8324 if (fragP
->fr_type
== rs_machine_dependent
8325 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8327 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8328 && (branch_before_loop_end (fragP
->fr_next
)
8329 || (workaround_all_short_loops
8330 && current_opcode
!= XTENSA_UNDEFINED
8331 && current_opcode
!= xtensa_loop_opcode
)))
8333 if (fragP
->tc_frag_data
.is_no_transform
)
8334 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8336 relax_frag_add_nop (fragP
);
8345 static int unrelaxed_frag_min_insn_count (fragS
*);
8348 count_insns_to_loop_end (fragS
*base_fragP
,
8349 bfd_boolean count_relax_add
,
8352 fragS
*fragP
= NULL
;
8357 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8359 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8360 if (insn_count
>= max_count
)
8363 if (count_relax_add
)
8365 if (fragP
->fr_type
== rs_machine_dependent
8366 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8368 /* In order to add the appropriate number of
8369 NOPs, we count an instruction for downstream
8372 if (insn_count
>= max_count
)
8382 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8384 xtensa_isa isa
= xtensa_default_isa
;
8385 static xtensa_insnbuf insnbuf
= NULL
;
8389 if (!fragP
->tc_frag_data
.is_insn
)
8393 insnbuf
= xtensa_insnbuf_alloc (isa
);
8395 /* Decode the fixed instructions. */
8396 while (offset
< fragP
->fr_fix
)
8400 xtensa_insnbuf_from_chars
8401 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8402 fmt
= xtensa_format_decode (isa
, insnbuf
);
8404 if (fmt
== XTENSA_UNDEFINED
)
8406 as_fatal (_("undecodable instruction in instruction frag"));
8409 offset
+= xtensa_format_length (isa
, fmt
);
8417 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8420 branch_before_loop_end (fragS
*base_fragP
)
8424 for (fragP
= base_fragP
;
8425 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8426 fragP
= fragP
->fr_next
)
8428 if (unrelaxed_frag_has_b_j (fragP
))
8436 unrelaxed_frag_has_b_j (fragS
*fragP
)
8438 static xtensa_insnbuf insnbuf
= NULL
;
8439 xtensa_isa isa
= xtensa_default_isa
;
8442 if (!fragP
->tc_frag_data
.is_insn
)
8446 insnbuf
= xtensa_insnbuf_alloc (isa
);
8448 /* Decode the fixed instructions. */
8449 while (offset
< fragP
->fr_fix
)
8454 xtensa_insnbuf_from_chars
8455 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8456 fmt
= xtensa_format_decode (isa
, insnbuf
);
8457 if (fmt
== XTENSA_UNDEFINED
)
8460 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8462 xtensa_opcode opcode
=
8463 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8464 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8465 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8468 offset
+= xtensa_format_length (isa
, fmt
);
8474 /* Checks to be made after initial assembly but before relaxation. */
8476 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8477 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8480 xtensa_sanity_check (void)
8482 const char *file_name
;
8487 file_name
= as_where (&line
);
8488 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8489 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8493 /* Walk over all of the fragments in a subsection. */
8494 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8496 if (fragP
->fr_type
== rs_machine_dependent
8497 && fragP
->fr_subtype
== RELAX_SLOTS
8498 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8500 static xtensa_insnbuf insnbuf
= NULL
;
8503 if (fragP
->fr_opcode
!= NULL
)
8506 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8507 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8508 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8510 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8511 t_insn
.opcode
) == 1)
8513 if (is_empty_loop (&t_insn
, fragP
))
8515 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8516 as_bad (_("invalid empty loop"));
8518 if (!is_local_forward_loop (&t_insn
, fragP
))
8520 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8521 as_bad (_("loop target does not follow "
8522 "loop instruction in section"));
8529 new_logical_line (file_name
, line
);
8533 #define LOOP_IMMED_OPN 1
8535 /* Return TRUE if the loop target is the next non-zero fragment. */
8538 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8540 const expressionS
*exp
;
8544 if (insn
->insn_type
!= ITYPE_INSN
)
8547 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8550 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8553 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8555 if (exp
->X_op
!= O_symbol
)
8558 symbolP
= exp
->X_add_symbol
;
8562 if (symbol_get_frag (symbolP
) == NULL
)
8565 if (S_GET_VALUE (symbolP
) != 0)
8568 /* Walk through the zero-size fragments from this one. If we find
8569 the target fragment, then this is a zero-size loop. */
8571 for (next_fragP
= fragP
->fr_next
;
8573 next_fragP
= next_fragP
->fr_next
)
8575 if (next_fragP
== symbol_get_frag (symbolP
))
8577 if (next_fragP
->fr_fix
!= 0)
8585 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8587 const expressionS
*exp
;
8591 if (insn
->insn_type
!= ITYPE_INSN
)
8594 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8597 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8600 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8602 if (exp
->X_op
!= O_symbol
)
8605 symbolP
= exp
->X_add_symbol
;
8609 if (symbol_get_frag (symbolP
) == NULL
)
8612 /* Walk through fragments until we find the target.
8613 If we do not find the target, then this is an invalid loop. */
8615 for (next_fragP
= fragP
->fr_next
;
8617 next_fragP
= next_fragP
->fr_next
)
8619 if (next_fragP
== symbol_get_frag (symbolP
))
8627 #define XTINFO_NAME "Xtensa_Info"
8628 #define XTINFO_NAMESZ 12
8629 #define XTINFO_TYPE 1
8632 xtensa_add_config_info (void)
8638 info_sec
= subseg_new (".xtensa.info", 0);
8639 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8641 data
= XNEWVEC (char, 100);
8642 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8643 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8644 sz
= strlen (data
) + 1;
8646 /* Add enough null terminators to pad to a word boundary. */
8649 while ((sz
& 3) != 0);
8651 /* Follow the standard note section layout:
8652 First write the length of the name string. */
8654 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8656 /* Next comes the length of the "descriptor", i.e., the actual data. */
8658 md_number_to_chars (p
, (valueT
) sz
, 4);
8660 /* Write the note type. */
8662 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8664 /* Write the name field. */
8665 p
= frag_more (XTINFO_NAMESZ
);
8666 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8668 /* Finally, write the descriptor. */
8670 memcpy (p
, data
, sz
);
8676 /* Alignment Functions. */
8679 get_text_align_power (unsigned target_size
)
8681 if (target_size
<= 4)
8684 if (target_size
<= 8)
8687 if (target_size
<= 16)
8690 if (target_size
<= 32)
8693 if (target_size
<= 64)
8696 if (target_size
<= 128)
8699 if (target_size
<= 256)
8702 if (target_size
<= 512)
8705 if (target_size
<= 1024)
8714 get_text_align_max_fill_size (int align_pow
,
8715 bfd_boolean use_nops
,
8716 bfd_boolean use_no_density
)
8719 return (1 << align_pow
);
8721 return 3 * (1 << align_pow
);
8723 return 1 + (1 << align_pow
);
8727 /* Calculate the minimum bytes of fill needed at "address" to align a
8728 target instruction of size "target_size" so that it does not cross a
8729 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8730 the fill can be an arbitrary number of bytes. Otherwise, the space must
8731 be filled by NOP instructions. */
8734 get_text_align_fill_size (addressT address
,
8737 bfd_boolean use_nops
,
8738 bfd_boolean use_no_density
)
8740 addressT alignment
, fill
, fill_limit
, fill_step
;
8741 bfd_boolean skip_one
= FALSE
;
8743 alignment
= (1 << align_pow
);
8744 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8748 fill_limit
= alignment
;
8751 else if (!use_no_density
)
8753 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8754 fill_limit
= alignment
* 2;
8760 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8761 fill_limit
= alignment
* 3;
8765 /* Try all fill sizes until finding one that works. */
8766 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8768 if (skip_one
&& fill
== 1)
8770 if ((address
+ fill
) >> align_pow
8771 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8780 branch_align_power (segT sec
)
8782 /* If the Xtensa processor has a fetch width of X, and
8783 the section is aligned to at least that boundary, then a branch
8784 target need only fit within that aligned block of memory to avoid
8785 a stall. Otherwise, try to fit branch targets within 4-byte
8786 aligned blocks (which may be insufficient, e.g., if the section
8787 has no alignment, but it's good enough). */
8788 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8789 int sec_align
= get_recorded_alignment (sec
);
8791 if (sec_align
>= fetch_align
)
8798 /* This will assert if it is not possible. */
8801 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8807 gas_assert (fill_size
% 3 == 0);
8808 return (fill_size
/ 3);
8811 gas_assert (fill_size
!= 1); /* Bad argument. */
8813 while (fill_size
> 1)
8816 if (fill_size
== 2 || fill_size
== 4)
8818 fill_size
-= insn_size
;
8821 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8827 get_text_align_nth_nop_size (offsetT fill_size
,
8829 bfd_boolean use_no_density
)
8836 gas_assert (fill_size
!= 1); /* Bad argument. */
8838 while (fill_size
> 1)
8841 if (fill_size
== 2 || fill_size
== 4)
8843 fill_size
-= insn_size
;
8853 /* For the given fragment, find the appropriate address
8854 for it to begin at if we are using NOPs to align it. */
8857 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8859 /* The rule is: get next fragment's FIRST instruction. Find
8860 the smallest number of bytes that need to be added to
8861 ensure that the next fragment's FIRST instruction will fit
8864 E.G., 2 bytes : 0, 1, 2 mod 4
8867 If the FIRST instruction MIGHT be relaxed,
8868 assume that it will become a 3-byte instruction.
8870 Note again here that LOOP instructions are not bundleable,
8871 and this relaxation only applies to LOOP opcodes. */
8874 int first_insn_size
;
8876 addressT pre_opcode_bytes
;
8879 xtensa_opcode opcode
;
8880 bfd_boolean is_loop
;
8882 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8883 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8885 /* Find the loop frag. */
8886 first_insn
= next_non_empty_frag (fragP
);
8887 /* Now find the first insn frag. */
8888 first_insn
= next_non_empty_frag (first_insn
);
8890 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8891 gas_assert (is_loop
);
8892 loop_insn_size
= xg_get_single_size (opcode
);
8894 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8895 pre_opcode_bytes
+= loop_insn_size
;
8897 /* For loops, the alignment depends on the size of the
8898 instruction following the loop, not the LOOP instruction. */
8900 if (first_insn
== NULL
)
8901 first_insn_size
= xtensa_fetch_width
;
8903 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8905 /* If it was 8, then we'll need a larger alignment for the section. */
8906 align_power
= get_text_align_power (first_insn_size
);
8907 record_alignment (now_seg
, align_power
);
8909 fill_size
= get_text_align_fill_size
8910 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8911 fragP
->tc_frag_data
.is_no_density
);
8913 return address
+ fill_size
;
8917 /* 3 mechanisms for relaxing an alignment:
8919 Align to a power of 2.
8920 Align so the next fragment's instruction does not cross a word boundary.
8921 Align the current instruction so that if the next instruction
8922 were 3 bytes, it would not cross a word boundary.
8926 zeros - This is easy; always insert zeros.
8927 nops - 3-byte and 2-byte instructions
8931 >=5 : 3-byte instruction + fn (n-3)
8932 widening - widen previous instructions. */
8935 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8937 addressT target_address
, loop_insn_offset
;
8939 xtensa_opcode loop_opcode
;
8940 bfd_boolean is_loop
;
8943 offsetT branch_align
;
8946 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8947 switch (fragP
->fr_subtype
)
8949 case RELAX_DESIRE_ALIGN
:
8950 target_size
= next_frag_format_size (fragP
);
8951 if (target_size
== XTENSA_UNDEFINED
)
8953 align_power
= branch_align_power (now_seg
);
8954 branch_align
= 1 << align_power
;
8955 /* Don't count on the section alignment being as large as the target. */
8956 if (target_size
> branch_align
)
8957 target_size
= branch_align
;
8958 opt_diff
= get_text_align_fill_size (address
, align_power
,
8959 target_size
, FALSE
, FALSE
);
8961 *max_diff
= (opt_diff
+ branch_align
8962 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8963 gas_assert (*max_diff
>= opt_diff
);
8966 case RELAX_ALIGN_NEXT_OPCODE
:
8967 /* The next non-empty frag after this one holds the LOOP instruction
8968 that needs to be aligned. The required alignment depends on the
8969 size of the next non-empty frag after the loop frag, i.e., the
8970 first instruction in the loop. */
8971 loop_frag
= next_non_empty_frag (fragP
);
8972 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8973 loop_insn_offset
= 0;
8974 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8975 gas_assert (is_loop
);
8977 /* If the loop has been expanded then the LOOP instruction
8978 could be at an offset from this fragment. */
8979 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8980 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8982 /* In an ideal world, which is what we are shooting for here,
8983 we wouldn't need to use any NOPs immediately prior to the
8984 LOOP instruction. If this approach fails, relax_frag_loop_align
8985 will call get_noop_aligned_address. */
8987 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8988 align_power
= get_text_align_power (target_size
);
8989 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8990 target_size
, FALSE
, FALSE
);
8992 *max_diff
= xtensa_fetch_width
8993 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8994 - target_size
+ opt_diff
;
8995 gas_assert (*max_diff
>= opt_diff
);
9006 /* md_relax_frag Hook and Helper Functions. */
9008 static long relax_frag_loop_align (fragS
*, long);
9009 static long relax_frag_for_align (fragS
*, long);
9010 static long relax_frag_immed
9011 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9013 typedef struct cached_fixup cached_fixupS
;
9022 typedef struct fixup_cache fixup_cacheS
;
9025 cached_fixupS
*fixups
;
9033 static int fixup_order (const void *a
, const void *b
)
9035 const cached_fixupS
*pa
= a
;
9036 const cached_fixupS
*pb
= b
;
9038 if (pa
->addr
== pb
->addr
)
9040 if (pa
->target
== pb
->target
)
9042 if (pa
->fixP
->fx_r_type
== pb
->fixP
->fx_r_type
)
9044 return pa
->fixP
->fx_r_type
< pb
->fixP
->fx_r_type
? -1 : 1;
9046 return pa
->target
- pb
->target
;
9048 return pa
->addr
- pb
->addr
;
9051 static bfd_boolean
xtensa_make_cached_fixup (cached_fixupS
*o
, fixS
*fixP
)
9053 xtensa_isa isa
= xtensa_default_isa
;
9054 int addr
= fixP
->fx_frag
->fr_address
;
9057 symbolS
*s
= fixP
->fx_addsy
;
9060 xtensa_opcode opcode
;
9062 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9063 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9065 target
= S_GET_VALUE (s
);
9066 delta
= target
- addr
;
9068 if (abs(delta
) < J_RANGE
/ 2)
9071 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9072 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9074 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9075 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9076 slot
= fixP
->tc_fix_data
.slot
;
9077 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9078 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9079 if (opcode
!= xtensa_j_opcode
)
9090 static void xtensa_realloc_fixup_cache (fixup_cacheS
*cache
, unsigned add
)
9092 if (cache
->n_fixups
+ add
> cache
->n_max
)
9094 cache
->n_max
= (cache
->n_fixups
+ add
) * 2;
9095 cache
->fixups
= XRESIZEVEC (cached_fixupS
, cache
->fixups
, cache
->n_max
);
9099 static void xtensa_cache_relaxable_fixups (fixup_cacheS
*cache
,
9100 segment_info_type
*seginfo
)
9104 cache
->n_fixups
= 0;
9106 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
9108 xtensa_realloc_fixup_cache (cache
, 1);
9110 if (xtensa_make_cached_fixup (cache
->fixups
+ cache
->n_fixups
, fixP
))
9113 qsort (cache
->fixups
, cache
->n_fixups
, sizeof (*cache
->fixups
), fixup_order
);
9116 static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS
*cache
,
9120 unsigned b
= cache
->n_fixups
;
9124 unsigned c
= (a
+ b
) / 2;
9126 if (cache
->fixups
[c
].addr
< addr
)
9134 static void xtensa_delete_cached_fixup (fixup_cacheS
*cache
, unsigned i
)
9136 memmove (cache
->fixups
+ i
, cache
->fixups
+ i
+ 1,
9137 (cache
->n_fixups
- i
- 1) * sizeof (*cache
->fixups
));
9141 static bfd_boolean
xtensa_add_cached_fixup (fixup_cacheS
*cache
, fixS
*fixP
)
9146 if (!xtensa_make_cached_fixup (&o
, fixP
))
9148 xtensa_realloc_fixup_cache (cache
, 1);
9149 i
= xtensa_find_first_cached_fixup (cache
, o
.addr
);
9150 if (i
< cache
->n_fixups
)
9153 memmove (cache
->fixups
+ i
+ 1, cache
->fixups
+ i
,
9154 (cache
->n_fixups
- i
) * sizeof (*cache
->fixups
));
9156 cache
->fixups
[i
] = o
;
9161 /* Return the number of bytes added to this fragment, given that the
9162 input has been stretched already by "stretch". */
9165 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9167 xtensa_isa isa
= xtensa_default_isa
;
9168 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9169 long new_stretch
= 0;
9170 const char *file_name
;
9173 static xtensa_insnbuf vbuf
= NULL
;
9174 int slot
, num_slots
;
9177 file_name
= as_where (&line
);
9178 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9180 fragP
->tc_frag_data
.unreported_expansion
= 0;
9182 switch (fragP
->fr_subtype
)
9184 case RELAX_ALIGN_NEXT_OPCODE
:
9185 /* Always convert. */
9186 if (fragP
->tc_frag_data
.relax_seen
)
9187 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9190 case RELAX_LOOP_END
:
9194 case RELAX_LOOP_END_ADD_NOP
:
9195 /* Add a NOP and switch to .fill 0. */
9196 new_stretch
= relax_frag_add_nop (fragP
);
9200 case RELAX_DESIRE_ALIGN
:
9201 /* Do nothing. The narrowing before this frag will either align
9206 case RELAX_LITERAL_FINAL
:
9209 case RELAX_LITERAL_NR
:
9211 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9212 gas_assert (unreported
== lit_size
);
9213 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9214 fragP
->fr_var
-= lit_size
;
9215 fragP
->fr_fix
+= lit_size
;
9221 vbuf
= xtensa_insnbuf_alloc (isa
);
9223 xtensa_insnbuf_from_chars
9224 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9225 fmt
= xtensa_format_decode (isa
, vbuf
);
9226 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9228 for (slot
= 0; slot
< num_slots
; slot
++)
9230 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9233 if (fragP
->tc_frag_data
.relax_seen
)
9234 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9238 case RELAX_IMMED_STEP1
:
9239 case RELAX_IMMED_STEP2
:
9240 case RELAX_IMMED_STEP3
:
9241 /* Place the immediate. */
9242 new_stretch
+= relax_frag_immed
9243 (now_seg
, fragP
, stretch
,
9244 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9245 fmt
, slot
, stretched_p
, FALSE
);
9249 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9255 case RELAX_LITERAL_POOL_BEGIN
:
9256 if (fragP
->fr_var
!= 0)
9258 /* We have a converted "candidate" literal pool;
9259 assemble a jump around it. */
9261 if (!litpool_slotbuf
)
9263 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9264 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9267 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9268 fragP
->tc_frag_data
.is_insn
= TRUE
;
9270 insn
.insn_type
= ITYPE_INSN
;
9271 insn
.opcode
= xtensa_j_opcode
;
9273 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9275 fmt
= xg_get_single_format (xtensa_j_opcode
);
9276 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9277 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9278 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9279 (unsigned char *)fragP
->fr_literal
+
9284 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9285 BFD_RELOC_XTENSA_SLOT0_OP
);
9289 case RELAX_LITERAL_POOL_END
:
9290 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9291 case RELAX_MAYBE_UNREACHABLE
:
9292 case RELAX_MAYBE_DESIRE_ALIGN
:
9293 /* No relaxation required. */
9296 case RELAX_FILL_NOP
:
9297 case RELAX_UNREACHABLE
:
9298 if (fragP
->tc_frag_data
.relax_seen
)
9299 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9302 case RELAX_TRAMPOLINE
:
9303 if (fragP
->tc_frag_data
.relax_seen
)
9305 static fixup_cacheS fixup_cache
;
9306 segment_info_type
*seginfo
= seg_info (now_seg
);
9307 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9308 int searchaddr
= trampaddr
< J_RANGE
? 0 : trampaddr
- J_RANGE
;
9311 if (now_seg
!= fixup_cache
.seg
||
9312 fragP
== fixup_cache
.first_frag
||
9313 fixup_cache
.first_frag
== NULL
)
9315 xtensa_cache_relaxable_fixups (&fixup_cache
, seginfo
);
9316 fixup_cache
.seg
= now_seg
;
9317 fixup_cache
.first_frag
= fragP
;
9320 /* Scan for jumps that will not reach. */
9321 for (i
= xtensa_find_first_cached_fixup (&fixup_cache
, searchaddr
);
9322 i
< fixup_cache
.n_fixups
; ++i
)
9325 fixS
*fixP
= fixup_cache
.fixups
[i
].fixP
;
9326 int target
= fixup_cache
.fixups
[i
].target
;
9327 int addr
= fixup_cache
.fixups
[i
].addr
;
9328 int delta
= fixup_cache
.fixups
[i
].delta
+ stretch
;
9330 trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9332 if (addr
+ J_RANGE
< trampaddr
)
9334 if (addr
> trampaddr
+ J_RANGE
)
9336 if (abs (delta
) < J_RANGE
)
9339 slot
= fixP
->tc_fix_data
.slot
;
9341 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
9342 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
9343 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9344 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9345 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9346 int lower
= (target
< addr
) ? target
: addr
;
9347 int upper
= (target
> addr
) ? target
: addr
;
9348 int midpoint
= lower
+ (upper
- lower
) / 2;
9350 if ((upper
- lower
) > 2 * J_RANGE
)
9352 /* One trampoline won't suffice; we need multiple jumps.
9353 Jump to the trampoline that's farthest, but still in
9354 range relative to the original "j" instruction. */
9355 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9357 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9358 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
9363 if (this_addr
- addr
< J_RANGE
)
9368 /* Backward jump. */
9369 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9376 struct trampoline_frag
*best_tf
= NULL
;
9379 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9381 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9382 int this_delta
= abs (this_addr
- midpoint
);
9384 if (!best_tf
|| this_delta
< best_delta
)
9387 best_delta
= this_delta
;
9392 if (tf
->fragP
== fragP
)
9394 if (abs (addr
- trampaddr
) < J_RANGE
)
9395 { /* The trampoline is in range of original; fix it! */
9400 fragS
*fP
; /* The out-of-range jump. */
9402 new_stretch
+= init_trampoline_frag (tf
);
9403 offset
= fragP
->fr_fix
; /* Where to assemble the j insn. */
9404 lsym
= fragP
->fr_symbol
;
9406 /* Assemble a jump to the target label here. */
9408 insn
.insn_type
= ITYPE_INSN
;
9409 insn
.opcode
= xtensa_j_opcode
;
9411 set_expr_symbol_offset (&insn
.tok
[0], lsym
, offset
);
9412 fmt
= xg_get_single_format (xtensa_j_opcode
);
9413 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9414 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9415 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fragP
->fr_literal
+ offset
, 3);
9418 /* Add a fix-up for the original j insn. */
9419 newfixP
= fix_new (fP
, fixP
->fx_where
, fixP
->fx_size
, lsym
, fragP
->fr_fix
- 3, TRUE
, fixP
->fx_r_type
);
9420 newfixP
->fx_no_overflow
= 1;
9421 newfixP
->tc_fix_data
.X_add_symbol
= lsym
;
9422 newfixP
->tc_fix_data
.X_add_number
= offset
;
9423 newfixP
->tc_fix_data
.slot
= slot
;
9425 xtensa_delete_cached_fixup (&fixup_cache
, i
);
9426 xtensa_add_cached_fixup (&fixup_cache
, newfixP
);
9428 /* Move the fix-up from the original j insn to this one. */
9429 fixP
->fx_frag
= fragP
;
9430 fixP
->fx_where
= fragP
->fr_fix
- 3;
9432 fixP
->tc_fix_data
.slot
= 0;
9433 fixP
->fx_r_type
= BFD_RELOC_XTENSA_SLOT0_OP
;
9435 xtensa_add_cached_fixup (&fixup_cache
, fixP
);
9437 /* re-do current fixup */
9440 /* Adjust the jump around this trampoline (if present). */
9441 if (tf
->fixP
!= NULL
)
9443 tf
->fixP
->fx_offset
+= 3;
9446 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9447 /* Do we have room for more? */
9448 if (fragP
->fr_var
< 3)
9449 { /* No, convert to fill. */
9451 fragP
->fr_subtype
= 0;
9452 /* Remove from the trampoline_list. */
9453 prev
->next
= tf
->next
;
9454 if (fragP
== fixup_cache
.first_frag
)
9455 fixup_cache
.first_frag
= NULL
;
9466 as_bad (_("bad relaxation state"));
9469 /* Tell gas we need another relaxation pass. */
9470 if (! fragP
->tc_frag_data
.relax_seen
)
9472 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9476 new_logical_line (file_name
, line
);
9482 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9484 addressT old_address
, old_next_address
, old_size
;
9485 addressT new_address
, new_next_address
, new_size
;
9488 /* All the frags with relax_frag_for_alignment prior to this one in the
9489 section have been done, hopefully eliminating the need for a NOP here.
9490 But, this will put it in if necessary. */
9492 /* Calculate the old address of this fragment and the next fragment. */
9493 old_address
= fragP
->fr_address
- stretch
;
9494 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9495 fragP
->tc_frag_data
.text_expansion
[0]);
9496 old_size
= old_next_address
- old_address
;
9498 /* Calculate the new address of this fragment and the next fragment. */
9499 new_address
= fragP
->fr_address
;
9501 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9502 new_size
= new_next_address
- new_address
;
9504 growth
= new_size
- old_size
;
9506 /* Fix up the text_expansion field and return the new growth. */
9507 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9512 /* Add a NOP instruction. */
9515 relax_frag_add_nop (fragS
*fragP
)
9517 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9518 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9519 assemble_nop (length
, nop_buf
);
9520 fragP
->tc_frag_data
.is_insn
= TRUE
;
9522 if (fragP
->fr_var
< length
)
9524 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9528 fragP
->fr_fix
+= length
;
9529 fragP
->fr_var
-= length
;
9534 static long future_alignment_required (fragS
*, long);
9537 relax_frag_for_align (fragS
*fragP
, long stretch
)
9539 /* Overview of the relaxation procedure for alignment:
9540 We can widen with NOPs or by widening instructions or by filling
9541 bytes after jump instructions. Find the opportune places and widen
9542 them if necessary. */
9547 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9548 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9549 || (fragP
->fr_subtype
== RELAX_SLOTS
9550 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9552 stretch_me
= future_alignment_required (fragP
, stretch
);
9553 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9559 /* We expanded on a previous pass. Can we shrink now? */
9560 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9561 if (shrink
<= stretch
&& stretch
> 0)
9563 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9569 /* Below here, diff > 0. */
9570 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9576 /* Return the address of the next frag that should be aligned.
9578 By "address" we mean the address it _would_ be at if there
9579 is no action taken to align it between here and the target frag.
9580 In other words, if no narrows and no fill nops are used between
9581 here and the frag to align, _even_if_ some of the frags we use
9582 to align targets have already expanded on a previous relaxation
9585 Also, count each frag that may be used to help align the target.
9587 Return 0 if there are no frags left in the chain that need to be
9591 find_address_of_next_align_frag (fragS
**fragPP
,
9595 bfd_boolean
*paddable
)
9597 fragS
*fragP
= *fragPP
;
9598 addressT address
= fragP
->fr_address
;
9600 /* Do not reset the counts to 0. */
9604 /* Limit this to a small search. */
9605 if (*widens
>= (int) xtensa_fetch_width
)
9610 address
+= fragP
->fr_fix
;
9612 if (fragP
->fr_type
== rs_fill
)
9613 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9614 else if (fragP
->fr_type
== rs_machine_dependent
)
9616 switch (fragP
->fr_subtype
)
9618 case RELAX_UNREACHABLE
:
9622 case RELAX_FILL_NOP
:
9624 if (!fragP
->tc_frag_data
.is_no_density
)
9629 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9634 address
+= total_frag_text_expansion (fragP
);
9638 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9641 case RELAX_ALIGN_NEXT_OPCODE
:
9642 case RELAX_DESIRE_ALIGN
:
9646 case RELAX_MAYBE_UNREACHABLE
:
9647 case RELAX_MAYBE_DESIRE_ALIGN
:
9652 /* Just punt if we don't know the type. */
9659 /* Just punt if we don't know the type. */
9663 fragP
= fragP
->fr_next
;
9671 static long bytes_to_stretch (fragS
*, int, int, int, int);
9674 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9676 fragS
*this_frag
= fragP
;
9680 int narrow_nops
= 0;
9681 bfd_boolean paddable
= FALSE
;
9682 offsetT local_opt_diff
;
9685 int stretch_amount
= 0;
9686 int local_stretch_amount
;
9687 int global_stretch_amount
;
9689 address
= find_address_of_next_align_frag
9690 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9694 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9695 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9697 frag_wane (this_frag
);
9701 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9702 opt_diff
= local_opt_diff
;
9703 gas_assert (opt_diff
>= 0);
9704 gas_assert (max_diff
>= opt_diff
);
9709 fragP
= fragP
->fr_next
;
9711 while (fragP
&& opt_diff
< max_diff
&& address
)
9713 /* We only use these to determine if we can exit early
9714 because there will be plenty of ways to align future
9716 int glob_widens
= 0;
9719 bfd_boolean glob_pad
= 0;
9720 address
= find_address_of_next_align_frag
9721 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9722 /* If there is a padable portion, then skip. */
9723 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9728 offsetT next_m_diff
;
9729 offsetT next_o_diff
;
9731 /* Downrange frags haven't had stretch added to them yet. */
9734 /* The address also includes any text expansion from this
9735 frag in a previous pass, but we don't want that. */
9736 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9738 /* Assume we are going to move at least opt_diff. In
9739 reality, we might not be able to, but assuming that
9740 we will helps catch cases where moving opt_diff pushes
9741 the next target from aligned to unaligned. */
9742 address
+= opt_diff
;
9744 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9746 /* Now cleanup for the adjustments to address. */
9747 next_o_diff
+= opt_diff
;
9748 next_m_diff
+= opt_diff
;
9749 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9750 opt_diff
= next_o_diff
;
9751 if (next_m_diff
< max_diff
)
9752 max_diff
= next_m_diff
;
9753 fragP
= fragP
->fr_next
;
9757 /* If there are enough wideners in between, do it. */
9760 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9762 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9767 local_stretch_amount
9768 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9769 num_widens
, local_opt_diff
);
9770 global_stretch_amount
9771 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9772 num_widens
, opt_diff
);
9773 /* If the condition below is true, then the frag couldn't
9774 stretch the correct amount for the global case, so we just
9775 optimize locally. We'll rely on the subsequent frags to get
9776 the correct alignment in the global case. */
9777 if (global_stretch_amount
< local_stretch_amount
)
9778 stretch_amount
= local_stretch_amount
;
9780 stretch_amount
= global_stretch_amount
;
9782 if (this_frag
->fr_subtype
== RELAX_SLOTS
9783 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9784 gas_assert (stretch_amount
<= 1);
9785 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9787 if (this_frag
->tc_frag_data
.is_no_density
)
9788 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9790 gas_assert (stretch_amount
<= 3);
9793 return stretch_amount
;
9797 /* The idea: widen everything you can to get a target or loop aligned,
9798 then start using NOPs.
9800 wide_nops = the number of wide NOPs available for aligning
9801 narrow_nops = the number of narrow NOPs available for aligning
9802 (a subset of wide_nops)
9803 widens = the number of narrow instructions that should be widened
9808 bytes_to_stretch (fragS
*this_frag
,
9817 int bytes_short
= desired_diff
- num_widens
;
9819 gas_assert (desired_diff
>= 0
9820 && desired_diff
< (signed) xtensa_fetch_width
);
9821 if (desired_diff
== 0)
9824 gas_assert (wide_nops
> 0 || num_widens
> 0);
9826 /* Always prefer widening to NOP-filling. */
9827 if (bytes_short
< 0)
9829 /* There are enough RELAX_NARROW frags after this one
9830 to align the target without widening this frag in any way. */
9834 if (bytes_short
== 0)
9836 /* Widen every narrow between here and the align target
9837 and the align target will be properly aligned. */
9838 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9844 /* From here we will need at least one NOP to get an alignment.
9845 However, we may not be able to align at all, in which case,
9847 nops_needed
= desired_diff
/ 3;
9849 /* If there aren't enough nops, don't widen. */
9850 if (nops_needed
> wide_nops
)
9853 /* First try it with all wide nops. */
9854 nop_bytes
= nops_needed
* 3;
9855 extra_bytes
= desired_diff
- nop_bytes
;
9857 if (nop_bytes
+ num_widens
>= desired_diff
)
9859 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9861 else if (num_widens
== extra_bytes
)
9866 /* Add a narrow nop. */
9870 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9873 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9875 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9876 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9877 else if (num_widens
== extra_bytes
)
9882 /* Replace a wide nop with a narrow nop--we can get here if
9883 extra_bytes was negative in the previous conditional. */
9884 if (narrow_nops
== 1)
9888 if (nop_bytes
+ num_widens
>= desired_diff
)
9890 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9891 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9892 else if (num_widens
== extra_bytes
)
9897 /* If we can't satisfy any of the above cases, then we can't align
9898 using padding or fill nops. */
9903 static struct trampoline_frag
*
9904 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9906 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9907 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9908 struct trampoline_frag
*best_tf
= NULL
;
9911 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9912 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9913 offsetT addr
= fragP
->fr_address
;
9914 offsetT lower
= (addr
< target
) ? addr
: target
;
9915 offsetT upper
= (addr
> target
) ? addr
: target
;
9916 int delta
= upper
- lower
;
9917 offsetT midpoint
= lower
+ delta
/ 2;
9918 int this_delta
= -1;
9921 if (delta
> 2 * J_RANGE
)
9923 /* One trampoline won't do; we need multiple.
9924 Choose the farthest trampoline that's still in range of the original
9925 and let a later pass finish the job. */
9926 for ( ; tf
; tf
= tf
->next
)
9928 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9930 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9934 if (this_addr
- addr
< J_RANGE
)
9939 /* Backward jump. */
9940 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9944 if (abs (addr
- this_addr
) < J_RANGE
)
9949 for ( ; tf
; tf
= tf
->next
)
9951 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9952 this_delta
= abs (this_addr
- midpoint
);
9953 if (unreachable_only
&& tf
->needs_jump_around
)
9955 if (!best_tf
|| this_delta
< best_delta
)
9958 best_delta
= this_delta
;
9959 best_addr
= this_addr
;
9964 best_delta
< J_RANGE
&&
9965 abs(best_addr
- lower
) < J_RANGE
&&
9966 abs(best_addr
- upper
) < J_RANGE
)
9969 return NULL
; /* No suitable trampoline found. */
9973 static struct trampoline_frag
*
9974 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9976 struct trampoline_frag
*tf
= NULL
;
9978 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9981 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
9988 check_and_update_trampolines (void)
9990 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9991 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9992 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9994 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9996 if (tf
->fragP
->fr_var
< 3)
9998 frag_wane (tf
->fragP
);
9999 prev
->next
= tf
->next
;
10007 init_trampoline_frag (struct trampoline_frag
*trampP
)
10009 fragS
*fp
= trampP
->fragP
;
10012 if (fp
->fr_fix
== 0)
10015 char label
[10 + 2 * sizeof(fp
)];
10016 sprintf (label
, ".L0_TR_%p", fp
);
10018 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10019 fp
->fr_symbol
= lsym
;
10020 if (trampP
->needs_jump_around
)
10022 /* Add a jump around this block of jumps, in case
10023 control flows into this block. */
10027 xtensa_isa isa
= xtensa_default_isa
;
10029 fp
->tc_frag_data
.is_insn
= 1;
10030 /* Assemble a jump insn. */
10031 tinsn_init (&insn
);
10032 insn
.insn_type
= ITYPE_INSN
;
10033 insn
.opcode
= xtensa_j_opcode
;
10035 set_expr_symbol_offset (&insn
.tok
[0], lsym
, 3);
10036 fmt
= xg_get_single_format (xtensa_j_opcode
);
10037 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10038 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10039 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fp
->fr_literal
, 3);
10043 fixP
= fix_new (fp
, 0, 3, lsym
, 3, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10044 trampP
->fixP
= fixP
;
10052 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
10054 fragS
*tramp
= trampP
->fragP
;
10056 int offset
= tramp
->fr_fix
; /* Where to assemble the j insn. */
10062 xtensa_isa isa
= xtensa_default_isa
;
10066 for (i
= 0; i
< MAX_SLOTS
; ++i
)
10067 if (origfrag
->tc_frag_data
.slot_symbols
[i
])
10069 gas_assert (slot
== -1);
10073 gas_assert (slot
>= 0 && slot
< MAX_SLOTS
);
10075 lsym
= tramp
->fr_symbol
;
10076 /* Assemble a jump to the target label in the trampoline frag. */
10077 tsym
= origfrag
->tc_frag_data
.slot_symbols
[slot
];
10078 toffset
= origfrag
-> tc_frag_data
.slot_offsets
[slot
];
10079 tinsn_init (&insn
);
10080 insn
.insn_type
= ITYPE_INSN
;
10081 insn
.opcode
= xtensa_j_opcode
;
10083 set_expr_symbol_offset (&insn
.tok
[0], tsym
, toffset
);
10084 fmt
= xg_get_single_format (xtensa_j_opcode
);
10085 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10086 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10087 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)tramp
->fr_literal
+ offset
, 3);
10088 tramp
->fr_fix
+= 3;
10089 tramp
->fr_var
-= 3;
10091 /* add a fix-up for the trampoline jump. */
10092 fixP
= fix_new (tramp
, tramp
->fr_fix
- 3, 3, tsym
, toffset
, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10093 /* Modify the jump at the start of this trampoline to point past the newly-added jump. */
10094 fixP
= trampP
->fixP
;
10096 fixP
->fx_offset
+= 3;
10097 /* Modify the original j to point here. */
10098 origfrag
->tc_frag_data
.slot_symbols
[slot
] = lsym
;
10099 origfrag
->tc_frag_data
.slot_offsets
[slot
] = tramp
->fr_fix
- 3;
10100 /* If trampoline is full, remove it from the list. */
10101 check_and_update_trampolines ();
10108 relax_frag_immed (segT segP
,
10115 bfd_boolean estimate_only
)
10119 bfd_boolean negatable_branch
= FALSE
;
10120 bfd_boolean branch_jmp_to_next
= FALSE
;
10121 bfd_boolean from_wide_insn
= FALSE
;
10122 xtensa_isa isa
= xtensa_default_isa
;
10124 offsetT frag_offset
;
10126 int num_text_bytes
, num_literal_bytes
;
10127 int literal_diff
, total_text_diff
, this_text_diff
;
10129 gas_assert (fragP
->fr_opcode
!= NULL
);
10131 xg_clear_vinsn (&cur_vinsn
);
10132 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10133 if (cur_vinsn
.num_slots
> 1)
10134 from_wide_insn
= TRUE
;
10136 tinsn
= cur_vinsn
.slots
[slot
];
10137 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10139 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10142 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10143 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10145 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10147 old_size
= xtensa_format_length (isa
, fmt
);
10149 /* Special case: replace a branch to the next instruction with a NOP.
10150 This is required to work around a hardware bug in T1040.0 and also
10151 serves as an optimization. */
10153 if (branch_jmp_to_next
10154 && ((old_size
== 2) || (old_size
== 3))
10155 && !next_frag_is_loop_target (fragP
))
10158 /* Here is the fun stuff: Get the immediate field from this
10159 instruction. If it fits, we are done. If not, find the next
10160 instruction sequence that fits. */
10162 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10163 istack_init (&istack
);
10164 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10165 min_steps
, stretch
);
10166 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10168 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10170 /* Figure out the number of bytes needed. */
10171 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10173 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10174 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10176 if (from_wide_insn
)
10179 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10182 num_text_bytes
+= old_size
;
10183 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10184 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10187 /* The first instruction in the relaxed sequence will go after
10188 the current wide instruction, and thus its symbolic immediates
10191 istack_init (&istack
);
10192 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10193 frag_offset
+ old_size
,
10194 min_steps
, stretch
+ old_size
);
10195 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10197 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10198 = (int) RELAX_IMMED
+ num_steps
;
10200 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10202 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10204 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10208 total_text_diff
= num_text_bytes
- old_size
;
10209 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10211 /* It MUST get larger. If not, we could get an infinite loop. */
10212 gas_assert (num_text_bytes
>= 0);
10213 gas_assert (literal_diff
>= 0);
10214 gas_assert (total_text_diff
>= 0);
10216 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10217 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10218 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10219 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10221 /* Find the associated expandable literal for this. */
10222 if (literal_diff
!= 0)
10224 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10227 gas_assert (literal_diff
== 4);
10228 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10230 /* We expect that the literal section state has NOT been
10232 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10233 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10234 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10236 /* We need to mark this section for another iteration
10242 if (negatable_branch
&& istack
.ninsn
> 1)
10243 update_next_frag_state (fragP
);
10245 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10246 if (istack
.ninsn
> 2 &&
10247 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10248 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10249 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10251 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10253 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
10255 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
10259 this_text_diff
+= init_trampoline_frag (tf
);
10260 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
10264 /* If target symbol is undefined, assume it will reach once linked. */
10265 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10267 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10269 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10270 _("jump target out of range; no usable trampoline found"));
10276 return this_text_diff
;
10280 /* md_convert_frag Hook and Helper Functions. */
10282 static void convert_frag_align_next_opcode (fragS
*);
10283 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10284 static void convert_frag_fill_nop (fragS
*);
10285 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10288 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10290 static xtensa_insnbuf vbuf
= NULL
;
10291 xtensa_isa isa
= xtensa_default_isa
;
10295 const char *file_name
;
10298 file_name
= as_where (&line
);
10299 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10301 switch (fragp
->fr_subtype
)
10303 case RELAX_ALIGN_NEXT_OPCODE
:
10304 /* Always convert. */
10305 convert_frag_align_next_opcode (fragp
);
10308 case RELAX_DESIRE_ALIGN
:
10309 /* Do nothing. If not aligned already, too bad. */
10312 case RELAX_LITERAL
:
10313 case RELAX_LITERAL_FINAL
:
10318 vbuf
= xtensa_insnbuf_alloc (isa
);
10320 xtensa_insnbuf_from_chars
10321 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10322 fmt
= xtensa_format_decode (isa
, vbuf
);
10323 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10325 for (slot
= 0; slot
< num_slots
; slot
++)
10327 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10330 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10334 case RELAX_IMMED_STEP1
:
10335 case RELAX_IMMED_STEP2
:
10336 case RELAX_IMMED_STEP3
:
10337 /* Place the immediate. */
10340 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10345 /* This is OK because some slots could have
10346 relaxations and others have none. */
10352 case RELAX_UNREACHABLE
:
10353 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10354 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10355 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10359 case RELAX_MAYBE_UNREACHABLE
:
10360 case RELAX_MAYBE_DESIRE_ALIGN
:
10364 case RELAX_FILL_NOP
:
10365 convert_frag_fill_nop (fragp
);
10368 case RELAX_LITERAL_NR
:
10369 if (use_literal_section
)
10371 /* This should have been handled during relaxation. When
10372 relaxing a code segment, literals sometimes need to be
10373 added to the corresponding literal segment. If that
10374 literal segment has already been relaxed, then we end up
10375 in this situation. Marking the literal segments as data
10376 would make this happen less often (since GAS always relaxes
10377 code before data), but we could still get into trouble if
10378 there are instructions in a segment that is not marked as
10379 containing code. Until we can implement a better solution,
10380 cheat and adjust the addresses of all the following frags.
10381 This could break subsequent alignments, but the linker's
10382 literal coalescing will do that anyway. */
10385 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10386 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10387 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10388 fragp
->fr_var
-= 4;
10389 fragp
->fr_fix
+= 4;
10390 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10391 f
->fr_address
+= 4;
10394 as_bad (_("invalid relaxation fragment result"));
10397 case RELAX_TRAMPOLINE
:
10402 new_logical_line (file_name
, line
);
10407 convert_frag_align_next_opcode (fragS
*fragp
)
10409 char *nop_buf
; /* Location for Writing. */
10410 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10411 addressT aligned_address
;
10413 int nop
, nop_count
;
10415 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10417 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10418 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10419 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10421 for (nop
= 0; nop
< nop_count
; nop
++)
10424 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10426 assemble_nop (nop_size
, nop_buf
);
10427 nop_buf
+= nop_size
;
10430 fragp
->fr_fix
+= fill_size
;
10431 fragp
->fr_var
-= fill_size
;
10436 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10438 TInsn tinsn
, single_target
;
10439 int size
, old_size
, diff
;
10440 offsetT frag_offset
;
10442 gas_assert (slot
== 0);
10443 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10445 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10447 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10448 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10449 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10454 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10456 /* No conversion. */
10461 gas_assert (fragP
->fr_opcode
!= NULL
);
10463 /* Frags in this relaxation state should only contain
10464 single instruction bundles. */
10465 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10467 /* Just convert it to a wide form.... */
10469 old_size
= xg_get_single_size (tinsn
.opcode
);
10471 tinsn_init (&single_target
);
10472 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10474 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10476 as_bad (_("unable to widen instruction"));
10480 size
= xg_get_single_size (single_target
.opcode
);
10481 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10482 frag_offset
, TRUE
);
10484 diff
= size
- old_size
;
10485 gas_assert (diff
>= 0);
10486 gas_assert (diff
<= fragP
->fr_var
);
10487 fragP
->fr_var
-= diff
;
10488 fragP
->fr_fix
+= diff
;
10496 convert_frag_fill_nop (fragS
*fragP
)
10498 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10499 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10500 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10501 - fragP
->fr_address
- fragP
->fr_fix
));
10504 /* No conversion. */
10508 assemble_nop (size
, loc
);
10509 fragP
->tc_frag_data
.is_insn
= TRUE
;
10510 fragP
->fr_var
-= size
;
10511 fragP
->fr_fix
+= size
;
10516 static fixS
*fix_new_exp_in_seg
10517 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10518 bfd_reloc_code_real_type
);
10519 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10522 convert_frag_immed (segT segP
,
10528 char *immed_instr
= fragP
->fr_opcode
;
10530 bfd_boolean expanded
= FALSE
;
10531 bfd_boolean branch_jmp_to_next
= FALSE
;
10532 char *fr_opcode
= fragP
->fr_opcode
;
10533 xtensa_isa isa
= xtensa_default_isa
;
10534 bfd_boolean from_wide_insn
= FALSE
;
10536 bfd_boolean is_loop
;
10538 gas_assert (fr_opcode
!= NULL
);
10540 xg_clear_vinsn (&cur_vinsn
);
10542 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10543 if (cur_vinsn
.num_slots
> 1)
10544 from_wide_insn
= TRUE
;
10546 orig_tinsn
= cur_vinsn
.slots
[slot
];
10547 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10549 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10551 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10552 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10554 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10556 /* Conversion just inserts a NOP and marks the fix as completed. */
10557 bytes
= xtensa_format_length (isa
, fmt
);
10560 cur_vinsn
.slots
[slot
].opcode
=
10561 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10562 cur_vinsn
.slots
[slot
].ntok
= 0;
10566 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10567 gas_assert (bytes
== 2 || bytes
== 3);
10568 build_nop (&cur_vinsn
.slots
[0], bytes
);
10569 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10571 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10572 xtensa_insnbuf_to_chars
10573 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10578 /* Here is the fun stuff: Get the immediate field from this
10579 instruction. If it fits, we're done. If not, find the next
10580 instruction sequence that fits. */
10584 symbolS
*lit_sym
= NULL
;
10585 int total_size
= 0;
10586 int target_offset
= 0;
10589 symbolS
*gen_label
= NULL
;
10590 offsetT frag_offset
;
10591 bfd_boolean first
= TRUE
;
10593 /* It does not fit. Find something that does and
10594 convert immediately. */
10595 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10596 istack_init (&istack
);
10597 xg_assembly_relax (&istack
, &orig_tinsn
,
10598 segP
, fragP
, frag_offset
, min_steps
, 0);
10600 old_size
= xtensa_format_length (isa
, fmt
);
10602 /* Assemble this right inline. */
10604 /* First, create the mapping from a label name to the REAL label. */
10606 for (i
= 0; i
< istack
.ninsn
; i
++)
10608 TInsn
*tinsn
= &istack
.insn
[i
];
10611 switch (tinsn
->insn_type
)
10613 case ITYPE_LITERAL
:
10614 if (lit_sym
!= NULL
)
10615 as_bad (_("multiple literals in expansion"));
10616 /* First find the appropriate space in the literal pool. */
10617 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10618 if (lit_frag
== NULL
)
10619 as_bad (_("no registered fragment for literal"));
10620 if (tinsn
->ntok
!= 1)
10621 as_bad (_("number of literal tokens != 1"));
10623 /* Set the literal symbol and add a fixup. */
10624 lit_sym
= lit_frag
->fr_symbol
;
10628 if (align_targets
&& !is_loop
)
10630 fragS
*unreach
= fragP
->fr_next
;
10631 while (!(unreach
->fr_type
== rs_machine_dependent
10632 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10633 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10635 unreach
= unreach
->fr_next
;
10638 gas_assert (unreach
->fr_type
== rs_machine_dependent
10639 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10640 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10642 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10644 gas_assert (gen_label
== NULL
);
10645 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10646 fr_opcode
- fragP
->fr_literal
10647 + target_offset
, fragP
);
10651 if (first
&& from_wide_insn
)
10653 target_offset
+= xtensa_format_length (isa
, fmt
);
10655 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10656 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10659 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10666 for (i
= 0; i
< istack
.ninsn
; i
++)
10668 TInsn
*tinsn
= &istack
.insn
[i
];
10672 bfd_reloc_code_real_type reloc_type
;
10674 switch (tinsn
->insn_type
)
10676 case ITYPE_LITERAL
:
10677 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10678 /* Already checked. */
10679 gas_assert (lit_frag
!= NULL
);
10680 gas_assert (lit_sym
!= NULL
);
10681 gas_assert (tinsn
->ntok
== 1);
10683 target_seg
= S_GET_SEGMENT (lit_sym
);
10684 gas_assert (target_seg
);
10685 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10686 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10687 &tinsn
->tok
[0], FALSE
, reloc_type
);
10694 xg_resolve_labels (tinsn
, gen_label
);
10695 xg_resolve_literals (tinsn
, lit_sym
);
10696 if (from_wide_insn
&& first
)
10699 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10701 cur_vinsn
.slots
[slot
] = *tinsn
;
10705 cur_vinsn
.slots
[slot
].opcode
=
10706 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10707 cur_vinsn
.slots
[slot
].ntok
= 0;
10709 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10710 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10711 (unsigned char *) immed_instr
, 0);
10712 fragP
->tc_frag_data
.is_insn
= TRUE
;
10713 size
= xtensa_format_length (isa
, fmt
);
10714 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10716 xg_emit_insn_to_buf
10717 (tinsn
, immed_instr
+ size
, fragP
,
10718 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10719 size
+= xg_get_single_size (tinsn
->opcode
);
10724 size
= xg_get_single_size (tinsn
->opcode
);
10725 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10726 immed_instr
- fragP
->fr_literal
, TRUE
);
10728 immed_instr
+= size
;
10729 total_size
+= size
;
10734 diff
= total_size
- old_size
;
10735 gas_assert (diff
>= 0);
10738 gas_assert (diff
<= fragP
->fr_var
);
10739 fragP
->fr_var
-= diff
;
10740 fragP
->fr_fix
+= diff
;
10743 /* Check for undefined immediates in LOOP instructions. */
10747 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10748 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10750 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10753 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10754 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10756 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10761 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10762 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10764 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10766 /* Add an expansion note on the expanded instruction. */
10767 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10768 &orig_tinsn
.tok
[0], TRUE
,
10769 BFD_RELOC_XTENSA_ASM_EXPAND
);
10774 /* Add a new fix expression into the desired segment. We have to
10775 switch to that segment to do this. */
10778 fix_new_exp_in_seg (segT new_seg
,
10779 subsegT new_subseg
,
10785 bfd_reloc_code_real_type r_type
)
10788 segT seg
= now_seg
;
10789 subsegT subseg
= now_subseg
;
10791 gas_assert (new_seg
!= 0);
10792 subseg_set (new_seg
, new_subseg
);
10794 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10795 subseg_set (seg
, subseg
);
10800 /* Relax a loop instruction so that it can span loop >256 bytes.
10806 addi as, as, lo8 (label-.L1)
10807 addmi as, as, mid8 (label-.L1)
10818 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10823 unsigned long target
;
10824 static xtensa_insnbuf insnbuf
= NULL
;
10825 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10826 xtensa_isa isa
= xtensa_default_isa
;
10827 addressT loop_offset
;
10828 addressT addi_offset
= 9;
10829 addressT addmi_offset
= 12;
10834 insnbuf
= xtensa_insnbuf_alloc (isa
);
10836 /* Get the loop offset. */
10837 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10839 /* Validate that there really is a LOOP at the loop_offset. Because
10840 loops are not bundleable, we can assume that the instruction will be
10842 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10843 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10845 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10846 addi_offset
+= loop_offset
;
10847 addmi_offset
+= loop_offset
;
10849 gas_assert (tinsn
->ntok
== 2);
10850 if (tinsn
->tok
[1].X_op
== O_constant
)
10851 target
= tinsn
->tok
[1].X_add_number
;
10852 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10854 /* Find the fragment. */
10855 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10856 gas_assert (S_GET_SEGMENT (sym
) == segP
10857 || S_GET_SEGMENT (sym
) == absolute_section
);
10858 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10862 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10866 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10867 loop_length_hi
= loop_length
& ~0x0ff;
10868 loop_length_lo
= loop_length
& 0x0ff;
10869 if (loop_length_lo
>= 128)
10871 loop_length_lo
-= 256;
10872 loop_length_hi
+= 256;
10875 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10876 32512. If the loop is larger than that, then we just fail. */
10877 if (loop_length_hi
> 32512)
10878 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10879 _("loop too long for LOOP instruction"));
10881 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10882 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10884 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10885 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10887 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10888 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10890 fragP
->tc_frag_data
.is_insn
= TRUE
;
10891 xtensa_insnbuf_to_chars
10892 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10894 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10895 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10896 xtensa_insnbuf_to_chars
10897 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10899 /* Walk through all of the frags from here to the loop end
10900 and mark them as no_transform to keep them from being modified
10901 by the linker. If we ever have a relocation for the
10902 addi/addmi of the difference of two symbols we can remove this. */
10905 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10906 next_fragP
= next_fragP
->fr_next
)
10908 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10909 if (next_fragP
->tc_frag_data
.is_loop_target
)
10911 if (target_count
== 2)
10917 /* A map that keeps information on a per-subsegment basis. This is
10918 maintained during initial assembly, but is invalid once the
10919 subsegments are smashed together. I.E., it cannot be used during
10922 typedef struct subseg_map_struct
10930 float total_freq
; /* fall-through + branch target frequency */
10931 float target_freq
; /* branch target frequency alone */
10933 struct subseg_map_struct
*next
;
10937 static subseg_map
*sseg_map
= NULL
;
10939 static subseg_map
*
10940 get_subseg_info (segT seg
, subsegT subseg
)
10942 subseg_map
*subseg_e
;
10944 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10946 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10953 static subseg_map
*
10954 add_subseg_info (segT seg
, subsegT subseg
)
10956 subseg_map
*subseg_e
= XNEW (subseg_map
);
10957 memset (subseg_e
, 0, sizeof (subseg_map
));
10958 subseg_e
->seg
= seg
;
10959 subseg_e
->subseg
= subseg
;
10960 subseg_e
->flags
= 0;
10961 /* Start off considering every branch target very important. */
10962 subseg_e
->target_freq
= 1.0;
10963 subseg_e
->total_freq
= 1.0;
10964 subseg_e
->next
= sseg_map
;
10965 sseg_map
= subseg_e
;
10971 get_last_insn_flags (segT seg
, subsegT subseg
)
10973 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10975 return subseg_e
->flags
;
10981 set_last_insn_flags (segT seg
,
10986 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10988 subseg_e
= add_subseg_info (seg
, subseg
);
10990 subseg_e
->flags
|= fl
;
10992 subseg_e
->flags
&= ~fl
;
10997 get_subseg_total_freq (segT seg
, subsegT subseg
)
10999 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11001 return subseg_e
->total_freq
;
11007 get_subseg_target_freq (segT seg
, subsegT subseg
)
11009 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11011 return subseg_e
->target_freq
;
11017 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11019 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11021 subseg_e
= add_subseg_info (seg
, subseg
);
11022 subseg_e
->total_freq
= total_f
;
11023 subseg_e
->target_freq
= target_f
;
11027 /* Segment Lists and emit_state Stuff. */
11030 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11035 segT literal_section
= head
->seg
;
11037 /* Move the literal section to the front of the section list. */
11038 gas_assert (literal_section
);
11039 if (literal_section
!= stdoutput
->sections
)
11041 bfd_section_list_remove (stdoutput
, literal_section
);
11042 bfd_section_list_prepend (stdoutput
, literal_section
);
11049 static void mark_literal_frags (seg_list
*);
11052 xg_promote_candidate_litpool (struct litpool_seg
*lps
,
11053 struct litpool_frag
*lp
)
11058 char label
[10 + 2 * sizeof (fragS
*)];
11060 poolbeg
= lp
->fragP
;
11062 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11063 poolend
= poolbeg
->fr_next
;
11064 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11065 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11066 /* Create a local symbol pointing to the
11067 end of the pool. */
11068 sprintf (label
, ".L0_LT_%p", poolbeg
);
11069 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11071 poolbeg
->fr_symbol
= lsym
;
11072 /* Rest is done in xtensa_relax_frag. */
11076 xtensa_move_literals (void)
11079 frchainS
*frchain_from
, *frchain_to
;
11080 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11081 fragS
**frag_splice
;
11084 fixS
*fix
, *next_fix
, **fix_splice
;
11086 struct litpool_seg
*lps
;
11087 const char *init_name
= INIT_SECTION_NAME
;
11088 const char *fini_name
= FINI_SECTION_NAME
;
11089 int init_name_len
= strlen(init_name
);
11090 int fini_name_len
= strlen(fini_name
);
11092 mark_literal_frags (literal_head
->next
);
11094 if (use_literal_section
)
11097 /* Assign addresses (rough estimates) to the potential literal pool locations
11098 and create new ones if the gaps are too large. */
11100 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11102 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11103 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11106 for ( ; frchP
; frchP
= frchP
->frch_next
)
11109 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11111 if (lpf
&& fragP
== lpf
->fragP
)
11113 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11114 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11115 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11116 /* Found a litpool location. */
11120 if (fragP
->fr_type
== rs_machine_dependent
&&
11121 fragP
->fr_subtype
== RELAX_SLOTS
)
11124 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11126 if (fragP
->tc_frag_data
.literal_frags
[slot
])
11128 /* L32R; point its literal to the nearest litpool
11129 preferring non-"candidate" positions to avoid
11130 the jump-around. */
11131 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11132 struct litpool_frag
*lp
= lpf
->prev
;
11137 while (lp
->fragP
->fr_subtype
==
11138 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11141 if (lp
->fragP
== NULL
)
11143 /* End of list; have to bite the bullet.
11144 Take the nearest. */
11148 /* Does it (conservatively) reach? */
11149 if (addr
- lp
->addr
<= 128 * 1024)
11151 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
11153 /* Found a good one. */
11156 else if (lp
->prev
->fragP
&&
11157 addr
- lp
->prev
->addr
> 128 * 1024)
11159 /* This is still a "candidate" but the next one
11160 will be too far away, so revert to the nearest
11161 one, convert it and add the jump around. */
11168 /* Convert candidate and add the jump around. */
11169 if (lp
->fragP
->fr_subtype
==
11170 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11171 xg_promote_candidate_litpool (lps
, lp
);
11173 if (! litfrag
->tc_frag_data
.literal_frag
)
11175 /* Take earliest use of this literal to avoid
11177 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11182 addr
+= fragP
->fr_fix
;
11183 if (fragP
->fr_type
== rs_fill
)
11184 addr
+= fragP
->fr_offset
;
11189 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11191 const char *seg_name
= segment_name (segment
->seg
);
11193 /* Keep the literals for .init and .fini in separate sections. */
11194 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11195 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11196 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11197 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11200 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11201 search_frag
= frchain_from
->frch_root
;
11202 literal_pool
= NULL
;
11204 frag_splice
= &(frchain_from
->frch_root
);
11206 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11208 gas_assert (search_frag
->fr_fix
== 0
11209 || search_frag
->fr_type
== rs_align
);
11210 search_frag
= search_frag
->fr_next
;
11215 search_frag
= frchain_from
->frch_root
;
11216 as_bad_where (search_frag
->fr_file
, search_frag
->fr_line
,
11217 _("literal pool location required for text-section-literals; specify with .literal_position"));
11221 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11222 == RELAX_LITERAL_POOL_BEGIN
);
11223 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11225 /* Make sure that all the frags in this series are closed, and
11226 that there is at least one left over of zero-size. This
11227 prevents us from making a segment with an frchain without any
11229 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11230 xtensa_set_frag_assembly_state (frag_now
);
11231 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11232 xtensa_set_frag_assembly_state (frag_now
);
11234 while (search_frag
!= frag_now
)
11236 next_frag
= search_frag
->fr_next
;
11237 if (search_frag
->tc_frag_data
.literal_frag
)
11239 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11240 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11241 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11242 gas_assert (frchain_to
);
11245 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11247 /* Skip empty fill frags. */
11248 *frag_splice
= next_frag
;
11249 search_frag
= next_frag
;
11253 if (search_frag
->fr_type
== rs_align
)
11255 /* Skip alignment frags, because the pool as a whole will be
11256 aligned if used, and we don't want to force alignment if the
11258 *frag_splice
= next_frag
;
11259 search_frag
= next_frag
;
11263 /* First, move the frag out of the literal section and
11264 to the appropriate place. */
11266 /* Insert an alignment frag at start of pool. */
11267 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11268 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11270 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11271 emit_state prev_state
;
11274 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11275 prev_frag
= frag_now
;
11276 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11277 align_frag
= frag_now
;
11278 frag_align (2, 0, 0);
11279 /* Splice it into the right place. */
11280 prev_frag
->fr_next
= align_frag
->fr_next
;
11281 align_frag
->fr_next
= literal_pool
->fr_next
;
11282 literal_pool
->fr_next
= align_frag
;
11283 /* Insert after this one. */
11284 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11285 xtensa_restore_emit_state (&prev_state
);
11287 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11288 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11289 /* Skip align frag. */
11290 if (insert_after
->fr_next
->fr_type
== rs_align
)
11292 insert_after
= insert_after
->fr_next
;
11295 *frag_splice
= next_frag
;
11296 search_frag
->fr_next
= insert_after
->fr_next
;
11297 insert_after
->fr_next
= search_frag
;
11298 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11299 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11301 /* Now move any fixups associated with this frag to the
11303 fix
= frchain_from
->fix_root
;
11304 fix_splice
= &(frchain_from
->fix_root
);
11307 next_fix
= fix
->fx_next
;
11308 if (fix
->fx_frag
== search_frag
)
11310 *fix_splice
= next_fix
;
11311 fix
->fx_next
= frchain_to
->fix_root
;
11312 frchain_to
->fix_root
= fix
;
11313 if (frchain_to
->fix_tail
== NULL
)
11314 frchain_to
->fix_tail
= fix
;
11317 fix_splice
= &(fix
->fx_next
);
11320 search_frag
= next_frag
;
11323 if (frchain_from
->fix_root
!= NULL
)
11325 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11326 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11328 gas_assert (frchain_from
->fix_root
== NULL
);
11330 frchain_from
->fix_tail
= NULL
;
11331 xtensa_restore_emit_state (&state
);
11334 /* Now fix up the SEGMENT value for all the literal symbols. */
11335 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11337 symbolS
*lit_sym
= lit
->sym
;
11338 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11340 S_SET_SEGMENT (lit_sym
, dseg
);
11345 /* Walk over all the frags for segments in a list and mark them as
11346 containing literals. As clunky as this is, we can't rely on frag_var
11347 and frag_variant to get called in all situations. */
11350 mark_literal_frags (seg_list
*segment
)
11352 frchainS
*frchain_from
;
11353 fragS
*search_frag
;
11357 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11358 search_frag
= frchain_from
->frch_root
;
11359 while (search_frag
)
11361 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11362 search_frag
= search_frag
->fr_next
;
11364 segment
= segment
->next
;
11370 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11372 /* Move all of the sections in the section list to come
11373 after "after" in the gnu segment list. */
11378 segT literal_section
= head
->seg
;
11380 /* Move the literal section after "after". */
11381 gas_assert (literal_section
);
11382 if (literal_section
!= after
)
11384 bfd_section_list_remove (stdoutput
, literal_section
);
11385 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11393 /* Push all the literal segments to the end of the gnu list. */
11396 xtensa_reorder_segments (void)
11403 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11409 /* Now that we have the last section, push all the literal
11410 sections to the end. */
11411 xtensa_reorder_seg_list (literal_head
, last_sec
);
11413 /* Now perform the final error check. */
11414 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11416 gas_assert (new_count
== old_count
);
11420 /* Change the emit state (seg, subseg, and frag related stuff) to the
11421 correct location. Return a emit_state which can be passed to
11422 xtensa_restore_emit_state to return to current fragment. */
11425 xtensa_switch_to_literal_fragment (emit_state
*result
)
11427 if (directive_state
[directive_absolute_literals
])
11429 segT lit4_seg
= cache_literal_section (TRUE
);
11430 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11433 xtensa_switch_to_non_abs_literal_fragment (result
);
11435 /* Do a 4-byte align here. */
11436 frag_align (2, 0, 0);
11437 record_alignment (now_seg
, 2);
11442 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11444 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11446 bfd_boolean is_init
=
11447 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
11448 bfd_boolean is_fini
=
11449 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
11451 if (pool_location
== NULL
11452 && !use_literal_section
11453 && !is_init
&& ! is_fini
)
11455 if (!auto_litpools
)
11457 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11459 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
11460 pool_location
= get_literal_pool_location (now_seg
);
11463 lit_seg
= cache_literal_section (FALSE
);
11464 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11466 if (!use_literal_section
11467 && !is_init
&& !is_fini
11468 && get_literal_pool_location (now_seg
) != pool_location
)
11470 /* Close whatever frag is there. */
11471 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11472 xtensa_set_frag_assembly_state (frag_now
);
11473 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11474 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11475 xtensa_set_frag_assembly_state (frag_now
);
11480 /* Call this function before emitting data into the literal section.
11481 This is a helper function for xtensa_switch_to_literal_fragment.
11482 This is similar to a .section new_now_seg subseg. */
11485 xtensa_switch_section_emit_state (emit_state
*state
,
11487 subsegT new_now_subseg
)
11489 state
->name
= now_seg
->name
;
11490 state
->now_seg
= now_seg
;
11491 state
->now_subseg
= now_subseg
;
11492 state
->generating_literals
= generating_literals
;
11493 generating_literals
++;
11494 subseg_set (new_now_seg
, new_now_subseg
);
11498 /* Use to restore the emitting into the normal place. */
11501 xtensa_restore_emit_state (emit_state
*state
)
11503 generating_literals
= state
->generating_literals
;
11504 subseg_set (state
->now_seg
, state
->now_subseg
);
11508 /* Predicate function used to look up a section in a particular group. */
11511 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11513 const char *gname
= inf
;
11514 const char *group_name
= elf_group_name (sec
);
11516 return (group_name
== gname
11517 || (group_name
!= NULL
11519 && strcmp (group_name
, gname
) == 0));
11523 /* Get the literal section to be used for the current text section.
11524 The result may be cached in the default_lit_sections structure. */
11527 cache_literal_section (bfd_boolean use_abs_literals
)
11529 const char *text_name
, *group_name
= 0;
11530 const char *base_name
, *suffix
;
11533 segT seg
, current_section
;
11534 int current_subsec
;
11535 bfd_boolean linkonce
= FALSE
;
11537 /* Save the current section/subsection. */
11538 current_section
= now_seg
;
11539 current_subsec
= now_subseg
;
11541 /* Clear the cached values if they are no longer valid. */
11542 if (now_seg
!= default_lit_sections
.current_text_seg
)
11544 default_lit_sections
.current_text_seg
= now_seg
;
11545 default_lit_sections
.lit_seg
= NULL
;
11546 default_lit_sections
.lit4_seg
= NULL
;
11549 /* Check if the literal section is already cached. */
11550 if (use_abs_literals
)
11551 pcached
= &default_lit_sections
.lit4_seg
;
11553 pcached
= &default_lit_sections
.lit_seg
;
11558 text_name
= default_lit_sections
.lit_prefix
;
11559 if (! text_name
|| ! *text_name
)
11561 text_name
= segment_name (current_section
);
11562 group_name
= elf_group_name (current_section
);
11563 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11566 base_name
= use_abs_literals
? ".lit4" : ".literal";
11569 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11571 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11573 suffix
= strchr (text_name
+ linkonce_len
, '.');
11575 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11581 /* If the section name begins or ends with ".text", then replace
11582 that portion instead of appending an additional suffix. */
11583 size_t len
= strlen (text_name
);
11585 && (strcmp (text_name
+ len
- 5, ".text") == 0
11586 || strncmp (text_name
, ".text", 5) == 0))
11589 name
= XNEWVEC (char, len
+ strlen (base_name
) + 1);
11590 if (strncmp (text_name
, ".text", 5) == 0)
11592 strcpy (name
, base_name
);
11593 strcat (name
, text_name
+ 5);
11597 strcpy (name
, text_name
);
11598 strcpy (name
+ len
, base_name
);
11602 /* Canonicalize section names to allow renaming literal sections.
11603 The group name, if any, came from the current text section and
11604 has already been canonicalized. */
11605 name
= tc_canonicalize_symbol_name (name
);
11607 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11608 (void *) group_name
);
11613 seg
= subseg_force_new (name
, 0);
11615 if (! use_abs_literals
)
11617 /* Add the newly created literal segment to the list. */
11618 seg_list
*n
= XNEW (seg_list
);
11620 n
->next
= literal_head
->next
;
11621 literal_head
->next
= n
;
11624 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11625 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11626 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11628 elf_group_name (seg
) = group_name
;
11630 bfd_set_section_flags (stdoutput
, seg
, flags
);
11631 bfd_set_section_alignment (stdoutput
, seg
, 2);
11635 subseg_set (current_section
, current_subsec
);
11640 /* Property Tables Stuff. */
11642 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11643 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11644 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11646 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11647 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11649 static bfd_boolean
get_frag_is_literal (const fragS
*);
11650 static void xtensa_create_property_segments
11651 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11652 static void xtensa_create_xproperty_segments
11653 (frag_flags_fn
, const char *, xt_section_type
);
11654 static bfd_boolean
exclude_section_from_property_tables (segT
);
11655 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11656 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11657 static void add_xt_block_frags
11658 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11659 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11660 static void xtensa_frag_flags_init (frag_flags
*);
11661 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11662 static flagword
frag_flags_to_number (const frag_flags
*);
11663 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11665 /* Set up property tables after relaxation. */
11668 xtensa_post_relax_hook (void)
11670 xtensa_move_seg_list_to_beginning (literal_head
);
11672 xtensa_find_unmarked_state_frags ();
11673 xtensa_mark_frags_for_org ();
11674 xtensa_mark_difference_of_two_symbols ();
11676 xtensa_create_property_segments (get_frag_is_literal
,
11678 XTENSA_LIT_SEC_NAME
,
11680 xtensa_create_xproperty_segments (get_frag_property_flags
,
11681 XTENSA_PROP_SEC_NAME
,
11684 if (warn_unaligned_branch_targets
)
11685 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11686 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11690 /* This function is only meaningful after xtensa_move_literals. */
11693 get_frag_is_literal (const fragS
*fragP
)
11695 gas_assert (fragP
!= NULL
);
11696 return fragP
->tc_frag_data
.is_literal
;
11701 xtensa_create_property_segments (frag_predicate property_function
,
11702 frag_predicate end_property_function
,
11703 const char *section_name_base
,
11704 xt_section_type sec_type
)
11708 /* Walk over all of the current segments.
11709 Walk over each fragment
11710 For each non-empty fragment,
11711 Build a property record (append where possible). */
11713 for (seclist
= &stdoutput
->sections
;
11714 seclist
&& *seclist
;
11715 seclist
= &(*seclist
)->next
)
11717 segT sec
= *seclist
;
11719 if (exclude_section_from_property_tables (sec
))
11722 if (section_has_property (sec
, property_function
))
11724 segment_info_type
*xt_seg_info
;
11725 xtensa_block_info
**xt_blocks
;
11726 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11728 prop_sec
->output_section
= prop_sec
;
11729 subseg_set (prop_sec
, 0);
11730 xt_seg_info
= seg_info (prop_sec
);
11731 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11733 /* Walk over all of the frchains here and add new sections. */
11734 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11735 end_property_function
);
11739 /* Now we fill them out.... */
11741 for (seclist
= &stdoutput
->sections
;
11742 seclist
&& *seclist
;
11743 seclist
= &(*seclist
)->next
)
11745 segment_info_type
*seginfo
;
11746 xtensa_block_info
*block
;
11747 segT sec
= *seclist
;
11749 seginfo
= seg_info (sec
);
11750 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11754 xtensa_block_info
*cur_block
;
11756 bfd_size_type rec_size
;
11758 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11761 rec_size
= num_recs
* 8;
11762 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11769 subseg_set (sec
, 0);
11770 frag_data
= frag_more (rec_size
);
11772 for (i
= 0; i
< num_recs
; i
++)
11776 /* Write the fixup. */
11777 gas_assert (cur_block
);
11778 fix
= fix_new (frag_now
, i
* 8, 4,
11779 section_symbol (cur_block
->sec
),
11781 FALSE
, BFD_RELOC_32
);
11782 fix
->fx_file
= "<internal>";
11785 /* Write the length. */
11786 md_number_to_chars (&frag_data
[4 + i
* 8],
11787 cur_block
->size
, 4);
11788 cur_block
= cur_block
->next
;
11790 frag_wane (frag_now
);
11792 frag_wane (frag_now
);
11800 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11801 const char *section_name_base
,
11802 xt_section_type sec_type
)
11806 /* Walk over all of the current segments.
11807 Walk over each fragment.
11808 For each fragment that has instructions,
11809 build an instruction record (append where possible). */
11811 for (seclist
= &stdoutput
->sections
;
11812 seclist
&& *seclist
;
11813 seclist
= &(*seclist
)->next
)
11815 segT sec
= *seclist
;
11817 if (exclude_section_from_property_tables (sec
))
11820 if (section_has_xproperty (sec
, flag_fn
))
11822 segment_info_type
*xt_seg_info
;
11823 xtensa_block_info
**xt_blocks
;
11824 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11826 prop_sec
->output_section
= prop_sec
;
11827 subseg_set (prop_sec
, 0);
11828 xt_seg_info
= seg_info (prop_sec
);
11829 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11831 /* Walk over all of the frchains here and add new sections. */
11832 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11836 /* Now we fill them out.... */
11838 for (seclist
= &stdoutput
->sections
;
11839 seclist
&& *seclist
;
11840 seclist
= &(*seclist
)->next
)
11842 segment_info_type
*seginfo
;
11843 xtensa_block_info
*block
;
11844 segT sec
= *seclist
;
11846 seginfo
= seg_info (sec
);
11847 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11851 xtensa_block_info
*cur_block
;
11853 bfd_size_type rec_size
;
11855 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11858 rec_size
= num_recs
* (8 + 4);
11859 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11860 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11867 subseg_set (sec
, 0);
11868 frag_data
= frag_more (rec_size
);
11870 for (i
= 0; i
< num_recs
; i
++)
11874 /* Write the fixup. */
11875 gas_assert (cur_block
);
11876 fix
= fix_new (frag_now
, i
* 12, 4,
11877 section_symbol (cur_block
->sec
),
11879 FALSE
, BFD_RELOC_32
);
11880 fix
->fx_file
= "<internal>";
11883 /* Write the length. */
11884 md_number_to_chars (&frag_data
[4 + i
* 12],
11885 cur_block
->size
, 4);
11886 md_number_to_chars (&frag_data
[8 + i
* 12],
11887 frag_flags_to_number (&cur_block
->flags
),
11888 sizeof (flagword
));
11889 cur_block
= cur_block
->next
;
11891 frag_wane (frag_now
);
11893 frag_wane (frag_now
);
11901 exclude_section_from_property_tables (segT sec
)
11903 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11905 /* Sections that don't contribute to the memory footprint are excluded. */
11906 if ((flags
& SEC_DEBUGGING
)
11907 || !(flags
& SEC_ALLOC
)
11908 || (flags
& SEC_MERGE
))
11911 /* Linker cie and fde optimizations mess up property entries for
11912 eh_frame sections, but there is nothing inside them relevant to
11913 property tables anyway. */
11914 if (strcmp (sec
->name
, ".eh_frame") == 0)
11922 section_has_property (segT sec
, frag_predicate property_function
)
11924 segment_info_type
*seginfo
= seg_info (sec
);
11927 if (seginfo
&& seginfo
->frchainP
)
11929 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11931 if (property_function (fragP
)
11932 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11941 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11943 segment_info_type
*seginfo
= seg_info (sec
);
11946 if (seginfo
&& seginfo
->frchainP
)
11948 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11950 frag_flags prop_flags
;
11951 property_function (fragP
, &prop_flags
);
11952 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11960 /* Two types of block sections exist right now: literal and insns. */
11963 add_xt_block_frags (segT sec
,
11964 xtensa_block_info
**xt_block
,
11965 frag_predicate property_function
,
11966 frag_predicate end_property_function
)
11970 /* Build it if needed. */
11971 while (*xt_block
!= NULL
)
11972 xt_block
= &(*xt_block
)->next
;
11973 /* We are either at NULL at the beginning or at the end. */
11975 /* Walk through the frags. */
11976 if (seg_info (sec
)->frchainP
)
11978 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11980 fragP
= fragP
->fr_next
)
11982 if (property_function (fragP
)
11983 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11985 if (*xt_block
!= NULL
)
11987 if ((*xt_block
)->offset
+ (*xt_block
)->size
11988 == fragP
->fr_address
)
11989 (*xt_block
)->size
+= fragP
->fr_fix
;
11991 xt_block
= &((*xt_block
)->next
);
11993 if (*xt_block
== NULL
)
11995 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
11996 new_block
->sec
= sec
;
11997 new_block
->offset
= fragP
->fr_address
;
11998 new_block
->size
= fragP
->fr_fix
;
11999 new_block
->next
= NULL
;
12000 xtensa_frag_flags_init (&new_block
->flags
);
12001 *xt_block
= new_block
;
12003 if (end_property_function
12004 && end_property_function (fragP
))
12006 xt_block
= &((*xt_block
)->next
);
12014 /* Break the encapsulation of add_xt_prop_frags here. */
12017 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
12019 if (prop_flags
->is_literal
12020 || prop_flags
->is_insn
12021 || prop_flags
->is_data
12022 || prop_flags
->is_unreachable
)
12029 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12031 memset (prop_flags
, 0, sizeof (frag_flags
));
12036 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12038 xtensa_frag_flags_init (prop_flags
);
12039 if (fragP
->tc_frag_data
.is_literal
)
12040 prop_flags
->is_literal
= TRUE
;
12041 if (fragP
->tc_frag_data
.is_specific_opcode
12042 || fragP
->tc_frag_data
.is_no_transform
)
12044 prop_flags
->is_no_transform
= TRUE
;
12045 if (xtensa_frag_flags_is_empty (prop_flags
))
12046 prop_flags
->is_data
= TRUE
;
12048 if (fragP
->tc_frag_data
.is_unreachable
)
12049 prop_flags
->is_unreachable
= TRUE
;
12050 else if (fragP
->tc_frag_data
.is_insn
)
12052 prop_flags
->is_insn
= TRUE
;
12053 if (fragP
->tc_frag_data
.is_loop_target
)
12054 prop_flags
->insn
.is_loop_target
= TRUE
;
12055 if (fragP
->tc_frag_data
.is_branch_target
)
12056 prop_flags
->insn
.is_branch_target
= TRUE
;
12057 if (fragP
->tc_frag_data
.is_no_density
)
12058 prop_flags
->insn
.is_no_density
= TRUE
;
12059 if (fragP
->tc_frag_data
.use_absolute_literals
)
12060 prop_flags
->insn
.is_abslit
= TRUE
;
12062 if (fragP
->tc_frag_data
.is_align
)
12064 prop_flags
->is_align
= TRUE
;
12065 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12066 if (xtensa_frag_flags_is_empty (prop_flags
))
12067 prop_flags
->is_data
= TRUE
;
12073 frag_flags_to_number (const frag_flags
*prop_flags
)
12076 if (prop_flags
->is_literal
)
12077 num
|= XTENSA_PROP_LITERAL
;
12078 if (prop_flags
->is_insn
)
12079 num
|= XTENSA_PROP_INSN
;
12080 if (prop_flags
->is_data
)
12081 num
|= XTENSA_PROP_DATA
;
12082 if (prop_flags
->is_unreachable
)
12083 num
|= XTENSA_PROP_UNREACHABLE
;
12084 if (prop_flags
->insn
.is_loop_target
)
12085 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12086 if (prop_flags
->insn
.is_branch_target
)
12088 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12089 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12092 if (prop_flags
->insn
.is_no_density
)
12093 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12094 if (prop_flags
->is_no_transform
)
12095 num
|= XTENSA_PROP_NO_TRANSFORM
;
12096 if (prop_flags
->insn
.is_no_reorder
)
12097 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12098 if (prop_flags
->insn
.is_abslit
)
12099 num
|= XTENSA_PROP_INSN_ABSLIT
;
12101 if (prop_flags
->is_align
)
12103 num
|= XTENSA_PROP_ALIGN
;
12104 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12112 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12113 const frag_flags
*prop_flags_2
)
12115 /* Cannot combine with an end marker. */
12117 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12119 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12121 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12124 if (prop_flags_1
->is_insn
)
12126 /* Properties of the beginning of the frag. */
12127 if (prop_flags_2
->insn
.is_loop_target
)
12129 if (prop_flags_2
->insn
.is_branch_target
)
12131 if (prop_flags_1
->insn
.is_no_density
!=
12132 prop_flags_2
->insn
.is_no_density
)
12134 if (prop_flags_1
->is_no_transform
!=
12135 prop_flags_2
->is_no_transform
)
12137 if (prop_flags_1
->insn
.is_no_reorder
!=
12138 prop_flags_2
->insn
.is_no_reorder
)
12140 if (prop_flags_1
->insn
.is_abslit
!=
12141 prop_flags_2
->insn
.is_abslit
)
12145 if (prop_flags_1
->is_align
)
12153 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12156 unsigned align_bits
;
12158 if (!xt_block
->flags
.is_align
)
12159 return xt_block
->size
;
12161 end_addr
= xt_block
->offset
+ xt_block
->size
;
12162 align_bits
= xt_block
->flags
.alignment
;
12163 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12164 return end_addr
- xt_block
->offset
;
12169 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12170 const xtensa_block_info
*xt_block_2
)
12172 if (xt_block
->sec
!= xt_block_2
->sec
)
12174 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12175 != xt_block_2
->offset
)
12178 if (xt_block_2
->size
== 0
12179 && (!xt_block_2
->flags
.is_unreachable
12180 || xt_block
->flags
.is_unreachable
))
12182 if (xt_block_2
->flags
.is_align
12183 && xt_block
->flags
.is_align
)
12185 /* Nothing needed. */
12186 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12191 if (xt_block_2
->flags
.is_align
)
12193 /* Push alignment to previous entry. */
12194 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12195 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12200 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12201 &xt_block_2
->flags
))
12204 xt_block
->size
+= xt_block_2
->size
;
12206 if (xt_block_2
->flags
.is_align
)
12208 xt_block
->flags
.is_align
= TRUE
;
12209 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12217 add_xt_prop_frags (segT sec
,
12218 xtensa_block_info
**xt_block
,
12219 frag_flags_fn property_function
)
12223 /* Build it if needed. */
12224 while (*xt_block
!= NULL
)
12226 xt_block
= &(*xt_block
)->next
;
12228 /* We are either at NULL at the beginning or at the end. */
12230 /* Walk through the frags. */
12231 if (seg_info (sec
)->frchainP
)
12233 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12234 fragP
= fragP
->fr_next
)
12236 xtensa_block_info tmp_block
;
12237 tmp_block
.sec
= sec
;
12238 tmp_block
.offset
= fragP
->fr_address
;
12239 tmp_block
.size
= fragP
->fr_fix
;
12240 tmp_block
.next
= NULL
;
12241 property_function (fragP
, &tmp_block
.flags
);
12243 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12244 /* && fragP->fr_fix != 0) */
12246 if ((*xt_block
) == NULL
12247 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12249 xtensa_block_info
*new_block
;
12250 if ((*xt_block
) != NULL
)
12251 xt_block
= &(*xt_block
)->next
;
12252 new_block
= XNEW (xtensa_block_info
);
12253 *new_block
= tmp_block
;
12254 *xt_block
= new_block
;
12262 /* op_placement_info_table */
12264 /* op_placement_info makes it easier to determine which
12265 ops can go in which slots. */
12268 init_op_placement_info_table (void)
12270 xtensa_isa isa
= xtensa_default_isa
;
12271 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12272 xtensa_opcode opcode
;
12275 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12277 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12278 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12280 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12282 op_placement_info
*opi
= &op_placement_table
[opcode
];
12283 /* FIXME: Make tinsn allocation dynamic. */
12284 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12285 as_fatal (_("too many operands in instruction"));
12286 opi
->narrowest
= XTENSA_UNDEFINED
;
12287 opi
->narrowest_size
= 0x7F;
12288 opi
->narrowest_slot
= 0;
12290 opi
->num_formats
= 0;
12292 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12294 opi
->slots
[fmt
] = 0;
12295 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12297 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12299 int fmt_length
= xtensa_format_length (isa
, fmt
);
12301 set_bit (fmt
, opi
->formats
);
12302 set_bit (slot
, opi
->slots
[fmt
]);
12303 if (fmt_length
< opi
->narrowest_size
12304 || (fmt_length
== opi
->narrowest_size
12305 && (xtensa_format_num_slots (isa
, fmt
)
12306 < xtensa_format_num_slots (isa
,
12309 opi
->narrowest
= fmt
;
12310 opi
->narrowest_size
= fmt_length
;
12311 opi
->narrowest_slot
= slot
;
12316 opi
->num_formats
++;
12319 xtensa_insnbuf_free (isa
, ibuf
);
12324 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12326 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12330 /* If the opcode is available in a single slot format, return its size. */
12333 xg_get_single_size (xtensa_opcode opcode
)
12335 return op_placement_table
[opcode
].narrowest_size
;
12339 static xtensa_format
12340 xg_get_single_format (xtensa_opcode opcode
)
12342 return op_placement_table
[opcode
].narrowest
;
12347 xg_get_single_slot (xtensa_opcode opcode
)
12349 return op_placement_table
[opcode
].narrowest_slot
;
12353 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12356 istack_init (IStack
*stack
)
12363 istack_empty (IStack
*stack
)
12365 return (stack
->ninsn
== 0);
12370 istack_full (IStack
*stack
)
12372 return (stack
->ninsn
== MAX_ISTACK
);
12376 /* Return a pointer to the top IStack entry.
12377 It is an error to call this if istack_empty () is TRUE. */
12380 istack_top (IStack
*stack
)
12382 int rec
= stack
->ninsn
- 1;
12383 gas_assert (!istack_empty (stack
));
12384 return &stack
->insn
[rec
];
12388 /* Add a new TInsn to an IStack.
12389 It is an error to call this if istack_full () is TRUE. */
12392 istack_push (IStack
*stack
, TInsn
*insn
)
12394 int rec
= stack
->ninsn
;
12395 gas_assert (!istack_full (stack
));
12396 stack
->insn
[rec
] = *insn
;
12401 /* Clear space for the next TInsn on the IStack and return a pointer
12402 to it. It is an error to call this if istack_full () is TRUE. */
12405 istack_push_space (IStack
*stack
)
12407 int rec
= stack
->ninsn
;
12409 gas_assert (!istack_full (stack
));
12410 insn
= &stack
->insn
[rec
];
12417 /* Remove the last pushed instruction. It is an error to call this if
12418 istack_empty () returns TRUE. */
12421 istack_pop (IStack
*stack
)
12423 int rec
= stack
->ninsn
- 1;
12424 gas_assert (!istack_empty (stack
));
12426 tinsn_init (&stack
->insn
[rec
]);
12430 /* TInsn functions. */
12433 tinsn_init (TInsn
*dst
)
12435 memset (dst
, 0, sizeof (TInsn
));
12439 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12442 tinsn_has_symbolic_operands (const TInsn
*insn
)
12445 int n
= insn
->ntok
;
12447 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12449 for (i
= 0; i
< n
; ++i
)
12451 switch (insn
->tok
[i
].X_op
)
12465 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12467 xtensa_isa isa
= xtensa_default_isa
;
12469 int n
= insn
->ntok
;
12471 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12473 for (i
= 0; i
< n
; ++i
)
12475 switch (insn
->tok
[i
].X_op
)
12483 /* Errors for these types are caught later. */
12488 /* Symbolic immediates are only allowed on the last immediate
12489 operand. At this time, CONST16 is the only opcode where we
12490 support non-PC-relative relocations. */
12491 if (i
!= get_relaxable_immed (insn
->opcode
)
12492 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12493 && insn
->opcode
!= xtensa_const16_opcode
))
12495 as_bad (_("invalid symbolic operand"));
12504 /* For assembly code with complex expressions (e.g. subtraction),
12505 we have to build them in the literal pool so that
12506 their results are calculated correctly after relaxation.
12507 The relaxation only handles expressions that
12508 boil down to SYMBOL + OFFSET. */
12511 tinsn_has_complex_operands (const TInsn
*insn
)
12514 int n
= insn
->ntok
;
12515 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12516 for (i
= 0; i
< n
; ++i
)
12518 switch (insn
->tok
[i
].X_op
)
12534 /* Encode a TInsn opcode and its constant operands into slotbuf.
12535 Return TRUE if there is a symbol in the immediate field. This
12536 function assumes that:
12537 1) The number of operands are correct.
12538 2) The insn_type is ITYPE_INSN.
12539 3) The opcode can be encoded in the specified format and slot.
12540 4) Operands are either O_constant or O_symbol, and all constants fit. */
12543 tinsn_to_slotbuf (xtensa_format fmt
,
12546 xtensa_insnbuf slotbuf
)
12548 xtensa_isa isa
= xtensa_default_isa
;
12549 xtensa_opcode opcode
= tinsn
->opcode
;
12550 bfd_boolean has_fixup
= FALSE
;
12551 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12554 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12555 if (noperands
!= tinsn
->ntok
)
12556 as_fatal (_("operand number mismatch"));
12558 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12560 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12561 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12565 for (i
= 0; i
< noperands
; i
++)
12567 expressionS
*exp
= &tinsn
->tok
[i
];
12570 const char *file_name
;
12576 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12578 /* The register number has already been checked in
12579 expression_maybe_register, so we don't need to check here. */
12580 opnd_value
= exp
->X_add_number
;
12581 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12582 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12585 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12589 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12591 file_name
= as_where (&line
);
12592 /* It is a constant and we called this function
12593 then we have to try to fit it. */
12594 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12595 exp
->X_add_number
, file_name
, line
);
12608 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12609 into a multi-slot instruction, fill the other slots with NOPs.
12610 Return TRUE if there is a symbol in the immediate field. See also the
12611 assumptions listed for tinsn_to_slotbuf. */
12614 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12616 static xtensa_insnbuf slotbuf
= 0;
12617 static vliw_insn vinsn
;
12618 xtensa_isa isa
= xtensa_default_isa
;
12619 bfd_boolean has_fixup
= FALSE
;
12624 slotbuf
= xtensa_insnbuf_alloc (isa
);
12625 xg_init_vinsn (&vinsn
);
12628 xg_clear_vinsn (&vinsn
);
12630 bundle_tinsn (tinsn
, &vinsn
);
12632 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12634 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12636 /* Only one slot may have a fix-up because the rest contains NOPs. */
12638 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12639 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12646 /* Check the instruction arguments. Return TRUE on failure. */
12649 tinsn_check_arguments (const TInsn
*insn
)
12651 xtensa_isa isa
= xtensa_default_isa
;
12652 xtensa_opcode opcode
= insn
->opcode
;
12653 xtensa_regfile t1_regfile
, t2_regfile
;
12654 int t1_reg
, t2_reg
;
12655 int t1_base_reg
, t1_last_reg
;
12656 int t2_base_reg
, t2_last_reg
;
12657 char t1_inout
, t2_inout
;
12660 if (opcode
== XTENSA_UNDEFINED
)
12662 as_bad (_("invalid opcode"));
12666 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12668 as_bad (_("too few operands"));
12672 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12674 as_bad (_("too many operands"));
12678 /* Check registers. */
12679 for (j
= 0; j
< insn
->ntok
; j
++)
12681 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12684 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12685 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12687 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12689 for (i
= 0; i
< insn
->ntok
; i
++)
12694 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12697 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12699 if (t1_regfile
!= t2_regfile
)
12702 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12703 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12705 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12706 t1_last_reg
= (t1_base_reg
12707 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12709 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12711 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12713 if (t1_reg
!= t2_reg
)
12716 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12718 as_bad (_("multiple writes to the same register"));
12729 /* Load an instruction from its encoded form. */
12732 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12736 xg_init_vinsn (&vinsn
);
12737 vinsn_from_chars (&vinsn
, f
);
12739 *tinsn
= vinsn
.slots
[slot
];
12740 xg_free_vinsn (&vinsn
);
12745 tinsn_from_insnbuf (TInsn
*tinsn
,
12746 xtensa_insnbuf slotbuf
,
12751 xtensa_isa isa
= xtensa_default_isa
;
12753 /* Find the immed. */
12754 tinsn_init (tinsn
);
12755 tinsn
->insn_type
= ITYPE_INSN
;
12756 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12757 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12758 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12759 for (i
= 0; i
< tinsn
->ntok
; i
++)
12761 set_expr_const (&tinsn
->tok
[i
],
12762 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12763 tinsn
->opcode
, i
));
12768 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12771 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12773 xtensa_opcode opcode
= tinsn
->opcode
;
12776 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12778 opnum
= get_relaxable_immed (opcode
);
12779 gas_assert (opnum
>= 0);
12780 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12781 fragP
->tc_frag_data
.slot_symbols
[slot
],
12782 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12784 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12789 get_num_stack_text_bytes (IStack
*istack
)
12792 int text_bytes
= 0;
12794 for (i
= 0; i
< istack
->ninsn
; i
++)
12796 TInsn
*tinsn
= &istack
->insn
[i
];
12797 if (tinsn
->insn_type
== ITYPE_INSN
)
12798 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12805 get_num_stack_literal_bytes (IStack
*istack
)
12810 for (i
= 0; i
< istack
->ninsn
; i
++)
12812 TInsn
*tinsn
= &istack
->insn
[i
];
12813 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12820 /* vliw_insn functions. */
12823 xg_init_vinsn (vliw_insn
*v
)
12826 xtensa_isa isa
= xtensa_default_isa
;
12828 xg_clear_vinsn (v
);
12830 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12831 if (v
->insnbuf
== NULL
)
12832 as_fatal (_("out of memory"));
12834 for (i
= 0; i
< config_max_slots
; i
++)
12836 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12837 if (v
->slotbuf
[i
] == NULL
)
12838 as_fatal (_("out of memory"));
12844 xg_clear_vinsn (vliw_insn
*v
)
12848 memset (v
, 0, offsetof (vliw_insn
, slots
)
12849 + sizeof(TInsn
) * config_max_slots
);
12851 v
->format
= XTENSA_UNDEFINED
;
12853 v
->inside_bundle
= FALSE
;
12855 if (xt_saved_debug_type
!= DEBUG_NONE
)
12856 debug_type
= xt_saved_debug_type
;
12858 for (i
= 0; i
< config_max_slots
; i
++)
12859 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12864 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12867 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12868 dst
->insnbuf
= src
->insnbuf
;
12869 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12874 vinsn_has_specific_opcodes (vliw_insn
*v
)
12878 for (i
= 0; i
< v
->num_slots
; i
++)
12880 if (v
->slots
[i
].is_specific_opcode
)
12888 xg_free_vinsn (vliw_insn
*v
)
12891 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12892 for (i
= 0; i
< config_max_slots
; i
++)
12893 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12897 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12898 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12901 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12904 bfd_boolean record_fixup
)
12906 xtensa_isa isa
= xtensa_default_isa
;
12907 xtensa_format fmt
= vinsn
->format
;
12908 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12910 bfd_boolean has_fixup
= FALSE
;
12912 xtensa_format_encode (isa
, fmt
, insnbuf
);
12914 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12916 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12917 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12918 bfd_boolean tinsn_has_fixup
=
12919 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12920 vinsn
->slotbuf
[slot
]);
12922 xtensa_format_set_slot (isa
, fmt
, slot
,
12923 insnbuf
, vinsn
->slotbuf
[slot
]);
12924 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12926 if (vinsn
->num_slots
!= 1)
12927 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12928 else if (record_fixup
)
12929 /* Instructions that generate TLS relocations should always be
12930 relaxed in the front-end. If "record_fixup" is set, then this
12931 function is being called during back-end relaxation, so flag
12932 the unexpected behavior as an error. */
12933 as_bad (_("unexpected TLS relocation"));
12935 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12936 xtensa_format_length (isa
, fmt
),
12937 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12938 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12940 if (tinsn_has_fixup
)
12943 xtensa_opcode opcode
= tinsn
->opcode
;
12944 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12947 for (i
= 0; i
< noperands
; i
++)
12949 expressionS
* exp
= &tinsn
->tok
[i
];
12955 if (get_relaxable_immed (opcode
) == i
)
12957 /* Add a fix record for the instruction, except if this
12958 function is being called prior to relaxation, i.e.,
12959 if record_fixup is false, and the instruction might
12960 be relaxed later. */
12962 || tinsn
->is_specific_opcode
12963 || !xg_is_relaxable_insn (tinsn
, 0))
12965 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12966 frag_offset
- fragP
->fr_literal
);
12970 if (exp
->X_op
!= O_symbol
)
12971 as_bad (_("invalid operand"));
12972 tinsn
->symbol
= exp
->X_add_symbol
;
12973 tinsn
->offset
= exp
->X_add_number
;
12977 as_bad (_("symbolic operand not allowed"));
12985 as_bad (_("expression too complex"));
12997 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
12999 static xtensa_insnbuf insnbuf
= NULL
;
13000 static xtensa_insnbuf slotbuf
= NULL
;
13003 xtensa_isa isa
= xtensa_default_isa
;
13007 insnbuf
= xtensa_insnbuf_alloc (isa
);
13008 slotbuf
= xtensa_insnbuf_alloc (isa
);
13011 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
13012 fmt
= xtensa_format_decode (isa
, insnbuf
);
13013 if (fmt
== XTENSA_UNDEFINED
)
13014 as_fatal (_("cannot decode instruction format"));
13015 vinsn
->format
= fmt
;
13016 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
13018 for (i
= 0; i
< vinsn
->num_slots
; i
++)
13020 TInsn
*tinsn
= &vinsn
->slots
[i
];
13021 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13022 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13027 /* Expression utilities. */
13029 /* Return TRUE if the expression is an integer constant. */
13032 expr_is_const (const expressionS
*s
)
13034 return (s
->X_op
== O_constant
);
13038 /* Get the expression constant.
13039 Calling this is illegal if expr_is_const () returns TRUE. */
13042 get_expr_const (const expressionS
*s
)
13044 gas_assert (expr_is_const (s
));
13045 return s
->X_add_number
;
13049 /* Set the expression to a constant value. */
13052 set_expr_const (expressionS
*s
, offsetT val
)
13054 s
->X_op
= O_constant
;
13055 s
->X_add_number
= val
;
13056 s
->X_add_symbol
= NULL
;
13057 s
->X_op_symbol
= NULL
;
13062 expr_is_register (const expressionS
*s
)
13064 return (s
->X_op
== O_register
);
13068 /* Get the expression constant.
13069 Calling this is illegal if expr_is_const () returns TRUE. */
13072 get_expr_register (const expressionS
*s
)
13074 gas_assert (expr_is_register (s
));
13075 return s
->X_add_number
;
13079 /* Set the expression to a symbol + constant offset. */
13082 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13084 s
->X_op
= O_symbol
;
13085 s
->X_add_symbol
= sym
;
13086 s
->X_op_symbol
= NULL
; /* unused */
13087 s
->X_add_number
= offset
;
13091 /* Return TRUE if the two expressions are equal. */
13094 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13096 if (s1
->X_op
!= s2
->X_op
)
13098 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13100 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13102 if (s1
->X_add_number
!= s2
->X_add_number
)
13109 copy_expr (expressionS
*dst
, const expressionS
*src
)
13111 memcpy (dst
, src
, sizeof (expressionS
));
13115 /* Support for the "--rename-section" option. */
13117 struct rename_section_struct
13119 const char *old_name
;
13121 struct rename_section_struct
*next
;
13124 static struct rename_section_struct
*section_rename
;
13127 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13128 entries to the section_rename list. Note: Specifying multiple
13129 renamings separated by colons is not documented and is retained only
13130 for backward compatibility. */
13133 build_section_rename (const char *arg
)
13135 struct rename_section_struct
*r
;
13136 char *this_arg
= NULL
;
13137 char *next_arg
= NULL
;
13139 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13141 char *old_name
, *new_name
;
13145 next_arg
= strchr (this_arg
, ':');
13153 old_name
= this_arg
;
13154 new_name
= strchr (this_arg
, '=');
13156 if (*old_name
== '\0')
13158 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13161 if (!new_name
|| new_name
[1] == '\0')
13163 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13170 /* Check for invalid section renaming. */
13171 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13173 if (strcmp (r
->old_name
, old_name
) == 0)
13174 as_bad (_("section %s renamed multiple times"), old_name
);
13175 if (strcmp (r
->new_name
, new_name
) == 0)
13176 as_bad (_("multiple sections remapped to output section %s"),
13181 r
= XNEW (struct rename_section_struct
);
13182 r
->old_name
= xstrdup (old_name
);
13183 r
->new_name
= xstrdup (new_name
);
13184 r
->next
= section_rename
;
13185 section_rename
= r
;
13191 xtensa_section_rename (const char *name
)
13193 struct rename_section_struct
*r
= section_rename
;
13195 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13197 if (strcmp (r
->old_name
, name
) == 0)
13198 return r
->new_name
;
13201 return (char *) name
;