1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
19 MA 02111-1307, USA. */
25 #include "safe-ctype.h"
26 #include "tc-xtensa.h"
29 #include "xtensa-relax.h"
30 #include "xtensa-istack.h"
31 #include "dwarf2dbg.h"
32 #include "struc-symbol.h"
33 #include "xtensa-config.h"
36 #define uint32 unsigned int
39 #define int32 signed int
44 Naming conventions (used somewhat inconsistently):
45 The xtensa_ functions are exported
46 The xg_ functions are internal
48 We also have a couple of different extensibility mechanisms.
49 1) The idiom replacement:
50 This is used when a line is first parsed to
51 replace an instruction pattern with another instruction
52 It is currently limited to replacements of instructions
53 with constant operands.
54 2) The xtensa-relax.c mechanism that has stronger instruction
55 replacement patterns. When an instruction's immediate field
56 does not fit the next instruction sequence is attempted.
57 In addition, "narrow" opcodes are supported this way. */
60 /* Define characters with special meanings to GAS. */
61 const char comment_chars
[] = "#";
62 const char line_comment_chars
[] = "#";
63 const char line_separator_chars
[] = ";";
64 const char EXP_CHARS
[] = "eE";
65 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
68 /* Flags to indicate whether the hardware supports the density and
69 absolute literals options. */
71 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
72 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
74 /* Maximum width we would pad an unreachable frag to get alignment. */
75 #define UNREACHABLE_MAX_WIDTH 8
77 static vliw_insn cur_vinsn
;
79 size_t xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
81 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
83 /* Some functions are only valid in the front end. This variable
84 allows us to assert that we haven't crossed over into the
86 static bfd_boolean past_xtensa_end
= FALSE
;
88 /* Flags for properties of the last instruction in a segment. */
89 #define FLAG_IS_A0_WRITER 0x1
90 #define FLAG_IS_BAD_LOOPEND 0x2
93 /* We define a special segment names ".literal" to place literals
94 into. The .fini and .init sections are special because they
95 contain code that is moved together by the linker. We give them
96 their own special .fini.literal and .init.literal sections. */
98 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
99 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
100 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal")
103 #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal")
106 /* This type is used for the directive_stack to keep track of the
107 state of the literal collection pools. */
109 typedef struct lit_state_struct
111 const char *lit_seg_name
;
112 const char *lit4_seg_name
;
113 const char *init_lit_seg_name
;
114 const char *fini_lit_seg_name
;
121 static lit_state default_lit_sections
;
124 /* We keep lists of literal segments. The seg_list type is the node
125 for such a list. The *_literal_head locals are the heads of the
126 various lists. All of these lists have a dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
136 static seg_list init_literal_head_h
;
137 static seg_list
*init_literal_head
= &init_literal_head_h
;
138 static seg_list fini_literal_head_h
;
139 static seg_list
*fini_literal_head
= &fini_literal_head_h
;
142 /* Lists of symbols. We keep a list of symbols that label the current
143 instruction, so that we can adjust the symbols when inserting alignment
144 for various instructions. We also keep a list of all the symbols on
145 literals, so that we can fix up those symbols when the literals are
146 later moved into the text sections. */
148 typedef struct sym_list_struct
150 struct sym_list_struct
*next
;
154 static sym_list
*insn_labels
= NULL
;
155 static sym_list
*free_insn_labels
= NULL
;
156 static sym_list
*saved_insn_labels
= NULL
;
158 static sym_list
*literal_syms
;
161 /* Flags to determine whether to prefer const16 or l32r
162 if both options are available. */
163 int prefer_const16
= 0;
166 /* Global flag to indicate when we are emitting literals. */
167 int generating_literals
= 0;
169 /* The following PROPERTY table definitions are copied from
170 <elf/xtensa.h> and must be kept in sync with the code there. */
172 /* Flags in the property tables to specify whether blocks of memory
173 are literals, instructions, data, or unreachable. For
174 instructions, blocks that begin loop targets and branch targets are
175 designated. Blocks that do not allow density, instruction
176 reordering or transformation are also specified. Finally, for
177 branch targets, branch target alignment priority is included.
178 Alignment of the next block is specified in the current block
179 and the size of the current block does not include any fill required
180 to align to the next block. */
182 #define XTENSA_PROP_LITERAL 0x00000001
183 #define XTENSA_PROP_INSN 0x00000002
184 #define XTENSA_PROP_DATA 0x00000004
185 #define XTENSA_PROP_UNREACHABLE 0x00000008
186 /* Instruction only properties at beginning of code. */
187 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
188 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
189 /* Instruction only properties about code. */
190 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
191 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
192 #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100
194 /* Branch target alignment information. This transmits information
195 to the linker optimization about the priority of aligning a
196 particular block for branch target alignment: None, low priority,
197 high priority, or required. These only need to be checked in
198 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
201 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
202 case XTENSA_PROP_BT_ALIGN_NONE:
203 case XTENSA_PROP_BT_ALIGN_LOW:
204 case XTENSA_PROP_BT_ALIGN_HIGH:
205 case XTENSA_PROP_BT_ALIGN_REQUIRE:
207 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
209 /* No branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
211 /* Low priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
213 /* High priority branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
215 /* Required branch target alignment. */
216 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
218 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
219 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
220 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
221 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
222 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
225 /* Alignment is specified in the block BEFORE the one that needs
226 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
227 get the required alignment specified as a power of 2. Use
228 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
229 alignment. Be careful of side effects since the SET will evaluate
230 flags twice. Also, note that the SIZE of a block in the property
231 table does not include the alignment size, so the alignment fill
232 must be calculated to determine if two blocks are contiguous.
233 TEXT_ALIGN is not currently implemented but is a placeholder for a
234 possible future implementation. */
236 #define XTENSA_PROP_ALIGN 0x00000800
238 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
240 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
241 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
242 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
243 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
244 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
246 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
249 /* Structure for saving instruction and alignment per-fragment data
250 that will be written to the object file. This structure is
251 equivalent to the actual data that will be written out to the file
252 but is easier to use. We provide a conversion to file flags
253 in frag_flags_to_number. */
255 typedef struct frag_flags_struct frag_flags
;
257 struct frag_flags_struct
259 /* is_literal should only be used after xtensa_move_literals.
260 If you need to check if you are generating a literal fragment,
261 then use the generating_literals global. */
263 unsigned is_literal
: 1;
264 unsigned is_insn
: 1;
265 unsigned is_data
: 1;
266 unsigned is_unreachable
: 1;
270 unsigned is_loop_target
: 1;
271 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
272 unsigned bt_align_priority
: 2;
274 unsigned is_no_density
: 1;
275 /* no_longcalls flag does not need to be placed in the object file. */
276 /* is_specific_opcode implies no_transform. */
277 unsigned is_no_transform
: 1;
279 unsigned is_no_reorder
: 1;
281 /* Uses absolute literal addressing for l32r. */
282 unsigned is_abslit
: 1;
284 unsigned is_align
: 1;
285 unsigned alignment
: 5;
289 /* Structure for saving information about a block of property data
290 for frags that have the same flags. */
291 struct xtensa_block_info_struct
297 struct xtensa_block_info_struct
*next
;
301 /* Structure for saving the current state before emitting literals. */
302 typedef struct emit_state_struct
307 int generating_literals
;
311 /* Opcode placement information */
313 typedef unsigned long long bitfield
;
314 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
315 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
316 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
318 #define MAX_FORMATS 32
320 typedef struct op_placement_info_struct
323 /* A number describing how restrictive the issue is for this
324 opcode. For example, an opcode that fits lots of different
325 formats has a high freedom, as does an opcode that fits
326 only one format but many slots in that format. The most
327 restrictive is the opcode that fits only one slot in one
330 /* The single format (i.e., if the op can live in a bundle by itself),
331 narrowest format, and widest format the op can be bundled in
333 xtensa_format single
;
334 xtensa_format narrowest
;
335 xtensa_format widest
;
340 /* formats is a bitfield with the Nth bit set
341 if the opcode fits in the Nth xtensa_format. */
344 /* slots[N]'s Mth bit is set if the op fits in the
345 Mth slot of the Nth xtensa_format. */
346 bitfield slots
[MAX_FORMATS
];
348 /* A count of the number of slots in a given format
349 an op can fit (i.e., the bitcount of the slot field above). */
350 char slots_in_format
[MAX_FORMATS
];
352 } op_placement_info
, *op_placement_info_table
;
354 op_placement_info_table op_placement_table
;
357 /* Extra expression types. */
359 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
360 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
361 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
374 directive_literal_prefix
,
376 directive_absolute_literals
,
377 directive_last_directive
383 bfd_boolean can_be_negated
;
386 const directive_infoS directive_info
[] =
389 { "literal", FALSE
},
391 { "transform", TRUE
},
392 { "freeregs", FALSE
},
393 { "longcalls", TRUE
},
394 { "literal_prefix", FALSE
},
395 { "schedule", TRUE
},
396 { "absolute-literals", TRUE
}
399 bfd_boolean directive_state
[] =
403 #if !XCHAL_HAVE_DENSITY
408 TRUE
, /* transform */
409 FALSE
, /* freeregs */
410 FALSE
, /* longcalls */
411 FALSE
, /* literal_prefix */
413 #if XSHAL_USE_ABSOLUTE_LITERALS
414 TRUE
/* absolute_literals */
416 FALSE
/* absolute_literals */
421 /* Directive functions. */
423 static void xtensa_begin_directive (int);
424 static void xtensa_end_directive (int);
425 static void xtensa_dwarf2_directive_loc (int);
426 static void xtensa_literal_prefix (char const *, int);
427 static void xtensa_literal_position (int);
428 static void xtensa_literal_pseudo (int);
429 static void xtensa_frequency_pseudo (int);
430 static void xtensa_elf_cons (int);
432 /* Parsing and Idiom Translation. */
434 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
436 /* Various Other Internal Functions. */
438 static void xtensa_mark_literal_pool_location (void);
439 static addressT
get_expanded_loop_offset (xtensa_opcode
);
440 static fragS
*get_literal_pool_location (segT
);
441 static void set_literal_pool_location (segT
, fragS
*);
442 static void xtensa_set_frag_assembly_state (fragS
*);
443 static void finish_vinsn (vliw_insn
*);
444 static bfd_boolean
emit_single_op (TInsn
*);
445 static int total_frag_text_expansion (fragS
*);
447 /* Alignment Functions. */
449 static size_t get_text_align_power (int);
450 static addressT
get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
452 /* Helpers for xtensa_relax_frag(). */
454 static long relax_frag_add_nop (fragS
*);
456 /* Accessors for additional per-subsegment information. */
458 static unsigned get_last_insn_flags (segT
, subsegT
);
459 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
460 static float get_subseg_total_freq (segT
, subsegT
);
461 static float get_subseg_target_freq (segT
, subsegT
);
462 static void set_subseg_freq (segT
, subsegT
, float, float);
464 /* Segment list functions. */
466 static void xtensa_move_literals (void);
467 static void xtensa_reorder_segments (void);
468 static void xtensa_switch_to_literal_fragment (emit_state
*);
469 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
470 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
471 static void xtensa_restore_emit_state (emit_state
*);
472 static void cache_literal_section
473 (seg_list
*, const char *, segT
*, bfd_boolean
);
475 /* Import from elf32-xtensa.c in BFD library. */
477 extern char *xtensa_get_property_section_name (asection
*, const char *);
479 /* op_placement_info functions. */
481 static void init_op_placement_info_table (void);
482 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
483 static int xg_get_single_size (xtensa_opcode
);
484 static xtensa_format
xg_get_single_format (xtensa_opcode
);
486 /* TInsn and IStack functions. */
488 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
489 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
490 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
491 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
492 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
493 static void tinsn_from_chars (TInsn
*, char *, int);
494 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
495 static int get_num_stack_text_bytes (IStack
*);
496 static int get_num_stack_literal_bytes (IStack
*);
498 /* vliw_insn functions. */
500 static void xg_init_vinsn (vliw_insn
*);
501 static void xg_clear_vinsn (vliw_insn
*);
502 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
503 static void xg_free_vinsn (vliw_insn
*);
504 static bfd_boolean vinsn_to_insnbuf
505 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
506 static void vinsn_from_chars (vliw_insn
*, char *);
508 /* Expression Utilities. */
510 bfd_boolean
expr_is_const (const expressionS
*);
511 offsetT
get_expr_const (const expressionS
*);
512 void set_expr_const (expressionS
*, offsetT
);
513 bfd_boolean
expr_is_register (const expressionS
*);
514 offsetT
get_expr_register (const expressionS
*);
515 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
516 static void set_expr_symbol_offset_diff
517 (expressionS
*, symbolS
*, symbolS
*, offsetT
);
518 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
519 static void copy_expr (expressionS
*, const expressionS
*);
521 /* Section renaming. */
523 static void build_section_rename (const char *);
526 /* ISA imported from bfd. */
527 extern xtensa_isa xtensa_default_isa
;
529 extern int target_big_endian
;
531 static xtensa_opcode xtensa_addi_opcode
;
532 static xtensa_opcode xtensa_addmi_opcode
;
533 static xtensa_opcode xtensa_call0_opcode
;
534 static xtensa_opcode xtensa_call4_opcode
;
535 static xtensa_opcode xtensa_call8_opcode
;
536 static xtensa_opcode xtensa_call12_opcode
;
537 static xtensa_opcode xtensa_callx0_opcode
;
538 static xtensa_opcode xtensa_callx4_opcode
;
539 static xtensa_opcode xtensa_callx8_opcode
;
540 static xtensa_opcode xtensa_callx12_opcode
;
541 static xtensa_opcode xtensa_const16_opcode
;
542 static xtensa_opcode xtensa_entry_opcode
;
543 static xtensa_opcode xtensa_movi_opcode
;
544 static xtensa_opcode xtensa_movi_n_opcode
;
545 static xtensa_opcode xtensa_isync_opcode
;
546 static xtensa_opcode xtensa_jx_opcode
;
547 static xtensa_opcode xtensa_l32r_opcode
;
548 static xtensa_opcode xtensa_loop_opcode
;
549 static xtensa_opcode xtensa_loopnez_opcode
;
550 static xtensa_opcode xtensa_loopgtz_opcode
;
551 static xtensa_opcode xtensa_nop_opcode
;
552 static xtensa_opcode xtensa_nop_n_opcode
;
553 static xtensa_opcode xtensa_or_opcode
;
554 static xtensa_opcode xtensa_ret_opcode
;
555 static xtensa_opcode xtensa_ret_n_opcode
;
556 static xtensa_opcode xtensa_retw_opcode
;
557 static xtensa_opcode xtensa_retw_n_opcode
;
558 static xtensa_opcode xtensa_rsr_lcount_opcode
;
559 static xtensa_opcode xtensa_waiti_opcode
;
562 /* Command-line Options. */
564 bfd_boolean use_literal_section
= TRUE
;
565 static bfd_boolean align_targets
= TRUE
;
566 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
567 static bfd_boolean has_a0_b_retw
= FALSE
;
568 static bfd_boolean workaround_a0_b_retw
= FALSE
;
569 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
570 static bfd_boolean workaround_short_loop
= FALSE
;
571 static bfd_boolean maybe_has_short_loop
= FALSE
;
572 static bfd_boolean workaround_close_loop_end
= FALSE
;
573 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
575 /* When workaround_short_loops is TRUE, all loops with early exits must
576 have at least 3 instructions. workaround_all_short_loops is a modifier
577 to the workaround_short_loop flag. In addition to the
578 workaround_short_loop actions, all straightline loopgtz and loopnez
579 must have at least 3 instructions. */
581 static bfd_boolean workaround_all_short_loops
= FALSE
;
585 xtensa_setup_hw_workarounds (int earliest
, int latest
)
587 if (earliest
> latest
)
588 as_fatal (_("illegal range of target hardware versions"));
590 /* Enable all workarounds for pre-T1050.0 hardware. */
591 if (earliest
< 105000 || latest
< 105000)
593 workaround_a0_b_retw
|= TRUE
;
594 workaround_b_j_loop_end
|= TRUE
;
595 workaround_short_loop
|= TRUE
;
596 workaround_close_loop_end
|= TRUE
;
597 workaround_all_short_loops
|= TRUE
;
604 option_density
= OPTION_MD_BASE
,
611 option_no_link_relax
,
619 option_text_section_literals
,
620 option_no_text_section_literals
,
622 option_absolute_literals
,
623 option_no_absolute_literals
,
625 option_align_targets
,
626 option_no_align_targets
,
628 option_warn_unaligned_targets
,
633 option_workaround_a0_b_retw
,
634 option_no_workaround_a0_b_retw
,
636 option_workaround_b_j_loop_end
,
637 option_no_workaround_b_j_loop_end
,
639 option_workaround_short_loop
,
640 option_no_workaround_short_loop
,
642 option_workaround_all_short_loops
,
643 option_no_workaround_all_short_loops
,
645 option_workaround_close_loop_end
,
646 option_no_workaround_close_loop_end
,
648 option_no_workarounds
,
650 option_rename_section_name
,
653 option_prefer_const16
,
655 option_target_hardware
658 const char *md_shortopts
= "";
660 struct option md_longopts
[] =
662 { "density", no_argument
, NULL
, option_density
},
663 { "no-density", no_argument
, NULL
, option_no_density
},
665 /* Both "relax" and "generics" are deprecated and treated as equivalent
666 to the "transform" option. */
667 { "relax", no_argument
, NULL
, option_relax
},
668 { "no-relax", no_argument
, NULL
, option_no_relax
},
669 { "generics", no_argument
, NULL
, option_generics
},
670 { "no-generics", no_argument
, NULL
, option_no_generics
},
672 { "transform", no_argument
, NULL
, option_transform
},
673 { "no-transform", no_argument
, NULL
, option_no_transform
},
674 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
675 { "no-text-section-literals", no_argument
, NULL
,
676 option_no_text_section_literals
},
677 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
678 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
679 /* This option was changed from -align-target to -target-align
680 because it conflicted with the "-al" option. */
681 { "target-align", no_argument
, NULL
, option_align_targets
},
682 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
683 { "warn-unaligned-targets", no_argument
, NULL
,
684 option_warn_unaligned_targets
},
685 { "longcalls", no_argument
, NULL
, option_longcalls
},
686 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
688 { "no-workaround-a0-b-retw", no_argument
, NULL
,
689 option_no_workaround_a0_b_retw
},
690 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
692 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
693 option_no_workaround_b_j_loop_end
},
694 { "workaround-b-j-loop-end", no_argument
, NULL
,
695 option_workaround_b_j_loop_end
},
697 { "no-workaround-short-loops", no_argument
, NULL
,
698 option_no_workaround_short_loop
},
699 { "workaround-short-loops", no_argument
, NULL
,
700 option_workaround_short_loop
},
702 { "no-workaround-all-short-loops", no_argument
, NULL
,
703 option_no_workaround_all_short_loops
},
704 { "workaround-all-short-loop", no_argument
, NULL
,
705 option_workaround_all_short_loops
},
707 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
708 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
710 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
712 { "no-workaround-close-loop-end", no_argument
, NULL
,
713 option_no_workaround_close_loop_end
},
714 { "workaround-close-loop-end", no_argument
, NULL
,
715 option_workaround_close_loop_end
},
717 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
719 { "link-relax", no_argument
, NULL
, option_link_relax
},
720 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
722 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
724 { NULL
, no_argument
, NULL
, 0 }
727 size_t md_longopts_size
= sizeof md_longopts
;
731 md_parse_option (int c
, char *arg
)
736 as_warn (_("--density option is ignored"));
738 case option_no_density
:
739 as_warn (_("--no-density option is ignored"));
741 case option_link_relax
:
744 case option_no_link_relax
:
747 case option_generics
:
748 as_warn (_("--generics is deprecated; use --transform instead"));
749 return md_parse_option (option_transform
, arg
);
750 case option_no_generics
:
751 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
752 return md_parse_option (option_no_transform
, arg
);
754 as_warn (_("--relax is deprecated; use --transform instead"));
755 return md_parse_option (option_transform
, arg
);
756 case option_no_relax
:
757 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
758 return md_parse_option (option_no_transform
, arg
);
759 case option_longcalls
:
760 directive_state
[directive_longcalls
] = TRUE
;
762 case option_no_longcalls
:
763 directive_state
[directive_longcalls
] = FALSE
;
765 case option_text_section_literals
:
766 use_literal_section
= FALSE
;
768 case option_no_text_section_literals
:
769 use_literal_section
= TRUE
;
771 case option_absolute_literals
:
772 if (!absolute_literals_supported
)
774 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
777 directive_state
[directive_absolute_literals
] = TRUE
;
779 case option_no_absolute_literals
:
780 directive_state
[directive_absolute_literals
] = FALSE
;
783 case option_workaround_a0_b_retw
:
784 workaround_a0_b_retw
= TRUE
;
786 case option_no_workaround_a0_b_retw
:
787 workaround_a0_b_retw
= FALSE
;
789 case option_workaround_b_j_loop_end
:
790 workaround_b_j_loop_end
= TRUE
;
792 case option_no_workaround_b_j_loop_end
:
793 workaround_b_j_loop_end
= FALSE
;
796 case option_workaround_short_loop
:
797 workaround_short_loop
= TRUE
;
799 case option_no_workaround_short_loop
:
800 workaround_short_loop
= FALSE
;
803 case option_workaround_all_short_loops
:
804 workaround_all_short_loops
= TRUE
;
806 case option_no_workaround_all_short_loops
:
807 workaround_all_short_loops
= FALSE
;
810 case option_workaround_close_loop_end
:
811 workaround_close_loop_end
= TRUE
;
813 case option_no_workaround_close_loop_end
:
814 workaround_close_loop_end
= FALSE
;
817 case option_no_workarounds
:
818 workaround_a0_b_retw
= FALSE
;
819 workaround_b_j_loop_end
= FALSE
;
820 workaround_short_loop
= FALSE
;
821 workaround_all_short_loops
= FALSE
;
822 workaround_close_loop_end
= FALSE
;
825 case option_align_targets
:
826 align_targets
= TRUE
;
828 case option_no_align_targets
:
829 align_targets
= FALSE
;
832 case option_warn_unaligned_targets
:
833 warn_unaligned_branch_targets
= TRUE
;
836 case option_rename_section_name
:
837 build_section_rename (arg
);
841 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
842 should be emitted or not. FIXME: Not implemented. */
845 case option_prefer_l32r
:
847 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
851 case option_prefer_const16
:
853 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
857 case option_target_hardware
:
859 int earliest
, latest
= 0;
860 if (*arg
== 0 || *arg
== '-')
861 as_fatal (_("invalid target hardware version"));
863 earliest
= strtol (arg
, &arg
, 0);
867 else if (*arg
== '-')
870 as_fatal (_("invalid target hardware version"));
871 latest
= strtol (arg
, &arg
, 0);
874 as_fatal (_("invalid target hardware version"));
876 xtensa_setup_hw_workarounds (earliest
, latest
);
880 case option_transform
:
881 /* This option has no affect other than to use the defaults,
882 which are already set. */
885 case option_no_transform
:
886 /* This option turns off all transformations of any kind.
887 However, because we want to preserve the state of other
888 directives, we only change its own field. Thus, before
889 you perform any transformation, always check if transform
890 is available. If you use the functions we provide for this
891 purpose, you will be ok. */
892 directive_state
[directive_transform
] = FALSE
;
902 md_show_usage (FILE *stream
)
906 --[no-]text-section-literals\n\
907 [Do not] put literals in the text section\n\
908 --[no-]absolute-literals\n\
909 [Do not] default to use non-PC-relative literals\n\
910 --[no-]target-align [Do not] try to align branch targets\n\
911 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
912 --[no-]transform [Do not] transform instructions\n\
913 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
917 /* Functions related to the list of current label symbols. */
920 xtensa_add_insn_label (symbolS
*sym
)
924 if (!free_insn_labels
)
925 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
928 l
= free_insn_labels
;
929 free_insn_labels
= l
->next
;
933 l
->next
= insn_labels
;
939 xtensa_clear_insn_labels (void)
943 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
950 /* The "loops_ok" argument is provided to allow ignoring labels that
951 define loop ends. This fixes a bug where the NOPs to align a
952 loop opcode were included in a previous zero-cost loop:
971 This argument is used to prevent moving the NOP to before the
972 loop-end label, which is what you want in this special case. */
975 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
, bfd_boolean loops_ok
)
979 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
981 symbolS
*lit_sym
= lit
->sym
;
982 if (loops_ok
|| ! symbol_get_tc (lit_sym
)->is_loop_target
)
984 S_SET_VALUE (lit_sym
, new_offset
);
985 symbol_set_frag (lit_sym
, new_frag
);
991 /* Directive data and functions. */
993 typedef struct state_stackS_struct
995 directiveE directive
;
997 bfd_boolean old_state
;
1001 struct state_stackS_struct
*prev
;
1004 state_stackS
*directive_state_stack
;
1006 const pseudo_typeS md_pseudo_table
[] =
1008 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1009 { "literal_position", xtensa_literal_position
, 0 },
1010 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1011 { "long", xtensa_elf_cons
, 4 },
1012 { "word", xtensa_elf_cons
, 4 },
1013 { "short", xtensa_elf_cons
, 2 },
1014 { "begin", xtensa_begin_directive
, 0 },
1015 { "end", xtensa_end_directive
, 0 },
1016 { "loc", xtensa_dwarf2_directive_loc
, 0 },
1017 { "literal", xtensa_literal_pseudo
, 0 },
1018 { "frequency", xtensa_frequency_pseudo
, 0 },
1024 use_transform (void)
1026 /* After md_end, you should be checking frag by frag, rather
1027 than state directives. */
1028 assert (!past_xtensa_end
);
1029 return directive_state
[directive_transform
];
1034 do_align_targets (void)
1036 /* Do not use this function after md_end; just look at align_targets
1037 instead. There is no target-align directive, so alignment is either
1038 enabled for all frags or not done at all. */
1039 assert (!past_xtensa_end
);
1040 return align_targets
&& use_transform ();
1045 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1049 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1051 as_where (&file
, &line
);
1053 stack
->directive
= directive
;
1054 stack
->negated
= negated
;
1055 stack
->old_state
= directive_state
[directive
];
1058 stack
->datum
= datum
;
1059 stack
->prev
= directive_state_stack
;
1060 directive_state_stack
= stack
;
1062 directive_state
[directive
] = !negated
;
1067 directive_pop (directiveE
*directive
,
1068 bfd_boolean
*negated
,
1073 state_stackS
*top
= directive_state_stack
;
1075 if (!directive_state_stack
)
1077 as_bad (_("unmatched end directive"));
1078 *directive
= directive_none
;
1082 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1083 *directive
= top
->directive
;
1084 *negated
= top
->negated
;
1087 *datum
= top
->datum
;
1088 directive_state_stack
= top
->prev
;
1094 directive_balance (void)
1096 while (directive_state_stack
)
1098 directiveE directive
;
1099 bfd_boolean negated
;
1104 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1105 as_warn_where ((char *) file
, line
,
1106 _(".begin directive with no matching .end directive"));
1112 inside_directive (directiveE dir
)
1114 state_stackS
*top
= directive_state_stack
;
1116 while (top
&& top
->directive
!= dir
)
1119 return (top
!= NULL
);
1124 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1128 char *directive_string
;
1130 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1135 input_line_pointer
+= 3;
1138 len
= strspn (input_line_pointer
,
1139 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1141 /* This code is a hack to make .begin [no-][generics|relax] exactly
1142 equivalent to .begin [no-]transform. We should remove it when
1143 we stop accepting those options. */
1145 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1147 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1148 directive_string
= "transform";
1150 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1152 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1153 directive_string
= "transform";
1156 directive_string
= input_line_pointer
;
1158 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1160 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1162 input_line_pointer
+= len
;
1163 *directive
= (directiveE
) i
;
1164 if (*negated
&& !directive_info
[i
].can_be_negated
)
1165 as_bad (_("directive %s cannot be negated"),
1166 directive_info
[i
].name
);
1171 as_bad (_("unknown directive"));
1172 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1177 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1179 directiveE directive
;
1180 bfd_boolean negated
;
1185 get_directive (&directive
, &negated
);
1186 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1188 discard_rest_of_line ();
1192 if (cur_vinsn
.inside_bundle
)
1193 as_bad (_("directives are not valid inside bundles"));
1197 case directive_literal
:
1198 if (!inside_directive (directive_literal
))
1200 /* Previous labels go with whatever follows this directive, not with
1201 the literal, so save them now. */
1202 saved_insn_labels
= insn_labels
;
1205 as_warn (_(".begin literal is deprecated; use .literal instead"));
1206 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1207 xtensa_switch_to_literal_fragment (state
);
1208 directive_push (directive_literal
, negated
, state
);
1211 case directive_literal_prefix
:
1212 /* Have to flush pending output because a movi relaxed to an l32r
1213 might produce a literal. */
1214 md_flush_pending_output ();
1215 /* Check to see if the current fragment is a literal
1216 fragment. If it is, then this operation is not allowed. */
1217 if (generating_literals
)
1219 as_bad (_("cannot set literal_prefix inside literal fragment"));
1223 /* Allocate the literal state for this section and push
1224 onto the directive stack. */
1225 ls
= xmalloc (sizeof (lit_state
));
1228 *ls
= default_lit_sections
;
1230 directive_push (directive_literal_prefix
, negated
, ls
);
1232 /* Parse the new prefix from the input_line_pointer. */
1234 len
= strspn (input_line_pointer
,
1235 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1236 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1238 /* Process the new prefix. */
1239 xtensa_literal_prefix (input_line_pointer
, len
);
1241 /* Skip the name in the input line. */
1242 input_line_pointer
+= len
;
1245 case directive_freeregs
:
1246 /* This information is currently unused, but we'll accept the statement
1247 and just discard the rest of the line. This won't check the syntax,
1248 but it will accept every correct freeregs directive. */
1249 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1250 directive_push (directive_freeregs
, negated
, 0);
1253 case directive_schedule
:
1254 md_flush_pending_output ();
1255 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1256 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1257 directive_push (directive_schedule
, negated
, 0);
1258 xtensa_set_frag_assembly_state (frag_now
);
1261 case directive_density
:
1262 as_warn (_(".begin [no-]density is ignored"));
1265 case directive_absolute_literals
:
1266 md_flush_pending_output ();
1267 if (!absolute_literals_supported
&& !negated
)
1269 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1272 xtensa_set_frag_assembly_state (frag_now
);
1273 directive_push (directive
, negated
, 0);
1277 md_flush_pending_output ();
1278 xtensa_set_frag_assembly_state (frag_now
);
1279 directive_push (directive
, negated
, 0);
1283 demand_empty_rest_of_line ();
1288 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1290 directiveE begin_directive
, end_directive
;
1291 bfd_boolean begin_negated
, end_negated
;
1295 emit_state
**state_ptr
;
1298 if (cur_vinsn
.inside_bundle
)
1299 as_bad (_("directives are not valid inside bundles"));
1301 get_directive (&end_directive
, &end_negated
);
1303 md_flush_pending_output ();
1305 switch (end_directive
)
1307 case (directiveE
) XTENSA_UNDEFINED
:
1308 discard_rest_of_line ();
1311 case directive_density
:
1312 as_warn (_(".end [no-]density is ignored"));
1313 demand_empty_rest_of_line ();
1316 case directive_absolute_literals
:
1317 if (!absolute_literals_supported
&& !end_negated
)
1319 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1320 demand_empty_rest_of_line ();
1329 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1330 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1331 (const void **) state_ptr
);
1333 if (begin_directive
!= directive_none
)
1335 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1337 as_bad (_("does not match begin %s%s at %s:%d"),
1338 begin_negated
? "no-" : "",
1339 directive_info
[begin_directive
].name
, file
, line
);
1343 switch (end_directive
)
1345 case directive_literal
:
1346 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1347 xtensa_restore_emit_state (state
);
1348 xtensa_set_frag_assembly_state (frag_now
);
1350 if (!inside_directive (directive_literal
))
1352 /* Restore the list of current labels. */
1353 xtensa_clear_insn_labels ();
1354 insn_labels
= saved_insn_labels
;
1358 case directive_literal_prefix
:
1359 /* Restore the default collection sections from saved state. */
1360 s
= (lit_state
*) state
;
1363 if (use_literal_section
)
1364 default_lit_sections
= *s
;
1366 /* free the state storage */
1370 case directive_schedule
:
1371 case directive_freeregs
:
1375 xtensa_set_frag_assembly_state (frag_now
);
1381 demand_empty_rest_of_line ();
1385 /* Wrap dwarf2 functions so that we correctly support the .loc directive. */
1387 static bfd_boolean xtensa_loc_directive_seen
= FALSE
;
1390 xtensa_dwarf2_directive_loc (int x
)
1392 xtensa_loc_directive_seen
= TRUE
;
1393 dwarf2_directive_loc (x
);
1398 xtensa_dwarf2_emit_insn (int size
, struct dwarf2_line_info
*loc
)
1400 if (debug_type
!= DEBUG_DWARF2
&& ! xtensa_loc_directive_seen
)
1402 xtensa_loc_directive_seen
= FALSE
;
1403 dwarf2_gen_line_info (frag_now_fix () - size
, loc
);
1407 /* Place an aligned literal fragment at the current location. */
1410 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1412 md_flush_pending_output ();
1414 if (inside_directive (directive_literal
))
1415 as_warn (_(".literal_position inside literal directive; ignoring"));
1416 xtensa_mark_literal_pool_location ();
1418 demand_empty_rest_of_line ();
1419 xtensa_clear_insn_labels ();
1423 /* Support .literal label, expr, ... */
1426 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1429 char *p
, *base_name
;
1433 if (inside_directive (directive_literal
))
1435 as_bad (_(".literal not allowed inside .begin literal region"));
1436 ignore_rest_of_line ();
1440 md_flush_pending_output ();
1442 /* Previous labels go with whatever follows this directive, not with
1443 the literal, so save them now. */
1444 saved_insn_labels
= insn_labels
;
1447 /* If we are using text-section literals, then this is the right value... */
1450 base_name
= input_line_pointer
;
1452 xtensa_switch_to_literal_fragment (&state
);
1454 /* ...but if we aren't using text-section-literals, then we
1455 need to put them in the section we just switched to. */
1456 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1459 /* All literals are aligned to four-byte boundaries. */
1460 frag_align (2, 0, 0);
1461 record_alignment (now_seg
, 2);
1463 c
= get_symbol_end ();
1464 /* Just after name is now '\0'. */
1465 p
= input_line_pointer
;
1469 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1471 as_bad (_("expected comma or colon after symbol name; "
1472 "rest of line ignored"));
1473 ignore_rest_of_line ();
1474 xtensa_restore_emit_state (&state
);
1482 input_line_pointer
++; /* skip ',' or ':' */
1484 xtensa_elf_cons (4);
1486 xtensa_restore_emit_state (&state
);
1488 /* Restore the list of current labels. */
1489 xtensa_clear_insn_labels ();
1490 insn_labels
= saved_insn_labels
;
1495 xtensa_literal_prefix (char const *start
, int len
)
1497 char *name
, *linkonce_suffix
;
1498 char *newname
, *newname4
;
1499 size_t linkonce_len
;
1501 /* Get a null-terminated copy of the name. */
1502 name
= xmalloc (len
+ 1);
1505 strncpy (name
, start
, len
);
1508 /* Allocate the sections (interesting note: the memory pointing to
1509 the name is actually used for the name by the new section). */
1511 newname
= xmalloc (len
+ strlen (".literal") + 1);
1512 newname4
= xmalloc (len
+ strlen (".lit4") + 1);
1514 linkonce_len
= sizeof (".gnu.linkonce.") - 1;
1515 if (strncmp (name
, ".gnu.linkonce.", linkonce_len
) == 0
1516 && (linkonce_suffix
= strchr (name
+ linkonce_len
, '.')) != 0)
1518 strcpy (newname
, ".gnu.linkonce.literal");
1519 strcpy (newname4
, ".gnu.linkonce.lit4");
1521 strcat (newname
, linkonce_suffix
);
1522 strcat (newname4
, linkonce_suffix
);
1526 int suffix_pos
= len
;
1528 /* If the section name ends with ".text", then replace that suffix
1529 instead of appending an additional suffix. */
1530 if (len
>= 5 && strcmp (name
+ len
- 5, ".text") == 0)
1533 strcpy (newname
, name
);
1534 strcpy (newname4
, name
);
1536 strcpy (newname
+ suffix_pos
, ".literal");
1537 strcpy (newname4
+ suffix_pos
, ".lit4");
1540 /* Note that cache_literal_section does not create a segment if
1541 it already exists. */
1542 default_lit_sections
.lit_seg
= NULL
;
1543 default_lit_sections
.lit4_seg
= NULL
;
1545 /* Canonicalizing section names allows renaming literal
1546 sections to occur correctly. */
1547 default_lit_sections
.lit_seg_name
= tc_canonicalize_symbol_name (newname
);
1548 default_lit_sections
.lit4_seg_name
= tc_canonicalize_symbol_name (newname4
);
1554 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1557 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1559 float fall_through_f
, target_f
;
1561 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1562 if (fall_through_f
< 0)
1564 as_bad (_("fall through frequency must be greater than 0"));
1565 ignore_rest_of_line ();
1569 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1572 as_bad (_("branch target frequency must be greater than 0"));
1573 ignore_rest_of_line ();
1577 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1579 demand_empty_rest_of_line ();
1583 /* Like normal .long/.short/.word, except support @plt, etc.
1584 Clobbers input_line_pointer, checks end-of-line. */
1587 xtensa_elf_cons (int nbytes
)
1590 bfd_reloc_code_real_type reloc
;
1592 md_flush_pending_output ();
1594 if (cur_vinsn
.inside_bundle
)
1595 as_bad (_("directives are not valid inside bundles"));
1597 if (is_it_end_of_statement ())
1599 demand_empty_rest_of_line ();
1606 if (exp
.X_op
== O_symbol
1607 && *input_line_pointer
== '@'
1608 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1611 reloc_howto_type
*reloc_howto
=
1612 bfd_reloc_type_lookup (stdoutput
, reloc
);
1614 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1615 as_bad (_("unsupported relocation"));
1616 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1617 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1618 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1619 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1620 as_bad (_("opcode-specific %s relocation used outside "
1621 "an instruction"), reloc_howto
->name
);
1622 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1623 as_bad (_("%s relocations do not fit in %d bytes"),
1624 reloc_howto
->name
, nbytes
);
1627 char *p
= frag_more ((int) nbytes
);
1628 xtensa_set_frag_assembly_state (frag_now
);
1629 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1630 nbytes
, &exp
, 0, reloc
);
1634 emit_expr (&exp
, (unsigned int) nbytes
);
1636 while (*input_line_pointer
++ == ',');
1638 input_line_pointer
--; /* Put terminator back into stream. */
1639 demand_empty_rest_of_line ();
1643 /* Parsing and Idiom Translation. */
1645 /* Parse @plt, etc. and return the desired relocation. */
1646 static bfd_reloc_code_real_type
1647 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1653 bfd_reloc_code_real_type reloc
;
1661 struct map_bfd
*ptr
;
1663 #define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
1665 static struct map_bfd mapping
[] =
1667 MAP ("l", BFD_RELOC_LO16
),
1668 MAP ("h", BFD_RELOC_HI16
),
1669 MAP ("plt", BFD_RELOC_XTENSA_PLT
),
1670 { (char *) 0, 0, BFD_RELOC_UNUSED
}
1674 return BFD_RELOC_NONE
;
1676 for (ch
= *str
, str2
= ident
;
1677 (str2
< ident
+ sizeof (ident
) - 1
1678 && (ISALNUM (ch
) || ch
== '@'));
1681 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1688 for (ptr
= &mapping
[0]; ptr
->length
> 0; ptr
++)
1689 if (ch
== ptr
->string
[0]
1690 && len
== ptr
->length
1691 && memcmp (ident
, ptr
->string
, ptr
->length
) == 0)
1693 /* Now check for "identifier@suffix+constant". */
1694 if (*str
== '-' || *str
== '+')
1696 char *orig_line
= input_line_pointer
;
1697 expressionS new_exp
;
1699 input_line_pointer
= str
;
1700 expression (&new_exp
);
1701 if (new_exp
.X_op
== O_constant
)
1703 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1704 str
= input_line_pointer
;
1707 if (&input_line_pointer
!= str_p
)
1708 input_line_pointer
= orig_line
;
1715 return BFD_RELOC_UNUSED
;
1720 expression_end (const char *name
)
1743 #define ERROR_REG_NUM ((unsigned) -1)
1746 tc_get_register (const char *prefix
)
1749 const char *next_expr
;
1750 const char *old_line_pointer
;
1753 old_line_pointer
= input_line_pointer
;
1755 if (*input_line_pointer
== '$')
1756 ++input_line_pointer
;
1758 /* Accept "sp" as a synonym for "a1". */
1759 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1760 && expression_end (input_line_pointer
+ 2))
1762 input_line_pointer
+= 2;
1763 return 1; /* AR[1] */
1766 while (*input_line_pointer
++ == *prefix
++)
1768 --input_line_pointer
;
1773 as_bad (_("bad register name: %s"), old_line_pointer
);
1774 return ERROR_REG_NUM
;
1777 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1779 as_bad (_("bad register number: %s"), input_line_pointer
);
1780 return ERROR_REG_NUM
;
1785 while (ISDIGIT ((int) *input_line_pointer
))
1786 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1788 if (!(next_expr
= expression_end (input_line_pointer
)))
1790 as_bad (_("bad register name: %s"), old_line_pointer
);
1791 return ERROR_REG_NUM
;
1794 input_line_pointer
= (char *) next_expr
;
1801 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1803 xtensa_isa isa
= xtensa_default_isa
;
1805 /* Check if this is an immediate operand. */
1806 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1808 bfd_reloc_code_real_type reloc
;
1809 segT t
= expression (tok
);
1810 if (t
== absolute_section
1811 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1813 assert (tok
->X_op
== O_constant
);
1814 tok
->X_op
= O_symbol
;
1815 tok
->X_add_symbol
= &abs_symbol
;
1818 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1819 && (reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1820 && (reloc
!= BFD_RELOC_NONE
))
1825 case BFD_RELOC_UNUSED
:
1826 as_bad (_("unsupported relocation"));
1829 case BFD_RELOC_XTENSA_PLT
:
1830 tok
->X_op
= O_pltrel
;
1833 case BFD_RELOC_LO16
:
1834 if (tok
->X_op
== O_constant
)
1835 tok
->X_add_number
&= 0xffff;
1840 case BFD_RELOC_HI16
:
1841 if (tok
->X_op
== O_constant
)
1842 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1851 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1852 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1854 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1857 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1858 as_bad (_("register number out of range"));
1861 tok
->X_op
= O_register
;
1862 tok
->X_add_symbol
= 0;
1863 tok
->X_add_number
= reg
;
1868 /* Split up the arguments for an opcode or pseudo-op. */
1871 tokenize_arguments (char **args
, char *str
)
1873 char *old_input_line_pointer
;
1874 bfd_boolean saw_comma
= FALSE
;
1875 bfd_boolean saw_arg
= FALSE
;
1876 bfd_boolean saw_colon
= FALSE
;
1878 char *arg_end
, *arg
;
1881 /* Save and restore input_line_pointer around this function. */
1882 old_input_line_pointer
= input_line_pointer
;
1883 input_line_pointer
= str
;
1885 while (*input_line_pointer
)
1888 switch (*input_line_pointer
)
1895 input_line_pointer
++;
1896 if (saw_comma
|| saw_colon
|| !saw_arg
)
1902 input_line_pointer
++;
1903 if (saw_comma
|| saw_colon
|| !saw_arg
)
1909 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1912 arg_end
= input_line_pointer
+ 1;
1913 while (!expression_end (arg_end
))
1916 arg_len
= arg_end
- input_line_pointer
;
1917 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1918 args
[num_args
] = arg
;
1922 strncpy (arg
, input_line_pointer
, arg_len
);
1923 arg
[arg_len
] = '\0';
1925 input_line_pointer
= arg_end
;
1935 if (saw_comma
|| saw_colon
)
1937 input_line_pointer
= old_input_line_pointer
;
1942 as_bad (_("extra comma"));
1944 as_bad (_("extra colon"));
1946 as_bad (_("missing argument"));
1948 as_bad (_("missing comma or colon"));
1949 input_line_pointer
= old_input_line_pointer
;
1954 /* Parse the arguments to an opcode. Return TRUE on error. */
1957 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1959 expressionS
*tok
, *last_tok
;
1960 xtensa_opcode opcode
= insn
->opcode
;
1961 bfd_boolean had_error
= TRUE
;
1962 xtensa_isa isa
= xtensa_default_isa
;
1963 int n
, num_regs
= 0;
1964 int opcode_operand_count
;
1965 int opnd_cnt
, last_opnd_cnt
;
1966 unsigned int next_reg
= 0;
1967 char *old_input_line_pointer
;
1969 if (insn
->insn_type
== ITYPE_LITERAL
)
1970 opcode_operand_count
= 1;
1972 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1975 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1977 /* Save and restore input_line_pointer around this function. */
1978 old_input_line_pointer
= input_line_pointer
;
1984 /* Skip invisible operands. */
1985 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1991 for (n
= 0; n
< num_args
; n
++)
1993 input_line_pointer
= arg_strings
[n
];
1994 if (*input_line_pointer
== ':')
1996 xtensa_regfile opnd_rf
;
1997 input_line_pointer
++;
2000 assert (opnd_cnt
> 0);
2002 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2004 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2005 as_warn (_("incorrect register number, ignoring"));
2010 if (opnd_cnt
>= opcode_operand_count
)
2012 as_warn (_("too many arguments"));
2015 assert (opnd_cnt
< MAX_INSN_ARGS
);
2017 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2018 next_reg
= tok
->X_add_number
+ 1;
2020 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2022 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2024 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2025 /* minus 1 because we are seeing one right now */
2031 last_opnd_cnt
= opnd_cnt
;
2038 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2042 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2045 insn
->ntok
= tok
- insn
->tok
;
2049 input_line_pointer
= old_input_line_pointer
;
2055 get_invisible_operands (TInsn
*insn
)
2057 xtensa_isa isa
= xtensa_default_isa
;
2058 static xtensa_insnbuf slotbuf
= NULL
;
2060 xtensa_opcode opc
= insn
->opcode
;
2061 int slot
, opnd
, fmt_found
;
2065 slotbuf
= xtensa_insnbuf_alloc (isa
);
2067 /* Find format/slot where this can be encoded. */
2070 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2072 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2074 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2080 if (fmt_found
) break;
2085 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2089 /* First encode all the visible operands
2090 (to deal with shared field operands). */
2091 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2093 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2094 && (insn
->tok
[opnd
].X_op
== O_register
2095 || insn
->tok
[opnd
].X_op
== O_constant
))
2097 val
= insn
->tok
[opnd
].X_add_number
;
2098 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2099 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2103 /* Then pull out the values for the invisible ones. */
2104 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2106 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2108 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2109 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2110 insn
->tok
[opnd
].X_add_number
= val
;
2111 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2112 insn
->tok
[opnd
].X_op
= O_register
;
2114 insn
->tok
[opnd
].X_op
= O_constant
;
2123 xg_reverse_shift_count (char **cnt_argp
)
2125 char *cnt_arg
, *new_arg
;
2126 cnt_arg
= *cnt_argp
;
2128 /* replace the argument with "31-(argument)" */
2129 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2130 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2133 *cnt_argp
= new_arg
;
2137 /* If "arg" is a constant expression, return non-zero with the value
2141 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2144 char *save_ptr
= input_line_pointer
;
2146 input_line_pointer
= arg
;
2148 input_line_pointer
= save_ptr
;
2150 if (exp
.X_op
== O_constant
)
2152 *valp
= exp
.X_add_number
;
2161 xg_replace_opname (char **popname
, char *newop
)
2164 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2165 strcpy (*popname
, newop
);
2170 xg_check_num_args (int *pnum_args
,
2175 int num_args
= *pnum_args
;
2177 if (num_args
< expected_num
)
2179 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2180 num_args
, opname
, expected_num
);
2184 if (num_args
> expected_num
)
2186 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2187 num_args
, opname
, expected_num
);
2188 while (num_args
-- > expected_num
)
2190 free (arg_strings
[num_args
]);
2191 arg_strings
[num_args
] = 0;
2193 *pnum_args
= expected_num
;
2201 /* If the register is not specified as part of the opcode,
2202 then get it from the operand and move it to the opcode. */
2205 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2207 xtensa_isa isa
= xtensa_default_isa
;
2209 char *opname
, *new_opname
;
2210 const char *sr_name
;
2211 int is_user
, is_write
;
2212 bfd_boolean has_underbar
= FALSE
;
2217 has_underbar
= TRUE
;
2220 is_user
= (opname
[1] == 'u');
2221 is_write
= (opname
[0] == 'w');
2223 /* Opname == [rw]ur or [rwx]sr... */
2225 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2228 /* Check if the argument is a symbolic register name. */
2229 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2230 /* Handle WSR to "INTSET" as a special case. */
2231 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2232 && !strcasecmp (arg_strings
[1], "intset"))
2233 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2234 if (sr
== XTENSA_UNDEFINED
2235 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2237 /* Maybe it's a register number.... */
2239 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2241 as_bad (_("invalid register '%s' for '%s' instruction"),
2242 arg_strings
[1], opname
);
2245 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2246 if (sr
== XTENSA_UNDEFINED
)
2248 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2254 /* Remove the last argument, which is now part of the opcode. */
2255 free (arg_strings
[1]);
2259 /* Translate the opcode. */
2260 sr_name
= xtensa_sysreg_name (isa
, sr
);
2261 /* Another special case for "WSR.INTSET".... */
2262 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2264 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2265 sprintf (new_opname
, "%s%s.%s", (has_underbar
? "_" : ""),
2268 *popname
= new_opname
;
2275 xtensa_translate_old_userreg_ops (char **popname
)
2277 xtensa_isa isa
= xtensa_default_isa
;
2279 char *opname
, *new_opname
;
2280 const char *sr_name
;
2281 bfd_boolean has_underbar
= FALSE
;
2284 if (opname
[0] == '_')
2286 has_underbar
= TRUE
;
2290 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2291 if (sr
!= XTENSA_UNDEFINED
)
2293 /* The new default name ("nnn") is different from the old default
2294 name ("URnnn"). The old default is handled below, and we don't
2295 want to recognize [RW]nnn, so do nothing if the name is the (new)
2297 static char namebuf
[10];
2298 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2299 if (strcmp (namebuf
, opname
+ 1) == 0)
2307 /* Only continue if the reg name is "URnnn". */
2308 if (opname
[1] != 'u' || opname
[2] != 'r')
2310 val
= strtoul (opname
+ 3, &end
, 10);
2314 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2315 if (sr
== XTENSA_UNDEFINED
)
2317 as_bad (_("invalid register number (%ld) for '%s'"),
2323 /* Translate the opcode. */
2324 sr_name
= xtensa_sysreg_name (isa
, sr
);
2325 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2326 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2327 opname
[0], sr_name
);
2329 *popname
= new_opname
;
2336 xtensa_translate_zero_immed (char *old_op
,
2346 assert (opname
[0] != '_');
2348 if (strcmp (opname
, old_op
) != 0)
2351 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2353 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2355 xg_replace_opname (popname
, new_op
);
2356 free (arg_strings
[1]);
2357 arg_strings
[1] = arg_strings
[2];
2366 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2367 Returns non-zero if an error was found. */
2370 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2372 char *opname
= *popname
;
2373 bfd_boolean has_underbar
= FALSE
;
2375 if (cur_vinsn
.inside_bundle
)
2380 has_underbar
= TRUE
;
2384 if (strcmp (opname
, "mov") == 0)
2386 if (use_transform () && !has_underbar
&& density_supported
)
2387 xg_replace_opname (popname
, "mov.n");
2390 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2392 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2393 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2394 strcpy (arg_strings
[2], arg_strings
[1]);
2400 if (strcmp (opname
, "bbsi.l") == 0)
2402 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2404 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2405 if (target_big_endian
)
2406 xg_reverse_shift_count (&arg_strings
[1]);
2410 if (strcmp (opname
, "bbci.l") == 0)
2412 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2414 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2415 if (target_big_endian
)
2416 xg_reverse_shift_count (&arg_strings
[1]);
2420 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
2421 && strcmp (opname
, "nop") == 0)
2423 if (use_transform () && !has_underbar
&& density_supported
)
2424 xg_replace_opname (popname
, "nop.n");
2427 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2429 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2430 arg_strings
[0] = (char *) xmalloc (3);
2431 arg_strings
[1] = (char *) xmalloc (3);
2432 arg_strings
[2] = (char *) xmalloc (3);
2433 strcpy (arg_strings
[0], "a1");
2434 strcpy (arg_strings
[1], "a1");
2435 strcpy (arg_strings
[2], "a1");
2441 /* Recognize [RW]UR and [RWX]SR. */
2442 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2443 && (opname
[1] == 'u' || opname
[1] == 's'))
2444 || (opname
[0] == 'x' && opname
[1] == 's'))
2446 && opname
[3] == '\0')
2447 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2449 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2450 [RW]<name> if <name> is the non-default name of a user register. */
2451 if ((opname
[0] == 'r' || opname
[0] == 'w')
2452 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2453 return xtensa_translate_old_userreg_ops (popname
);
2455 /* Relax branches that don't allow comparisons against an immediate value
2456 of zero to the corresponding branches with implicit zero immediates. */
2457 if (!has_underbar
&& use_transform ())
2459 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2460 pnum_args
, arg_strings
))
2463 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2464 pnum_args
, arg_strings
))
2467 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2468 pnum_args
, arg_strings
))
2471 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2472 pnum_args
, arg_strings
))
2480 /* Functions for dealing with the Xtensa ISA. */
2482 /* Currently the assembler only allows us to use a single target per
2483 fragment. Because of this, only one operand for a given
2484 instruction may be symbolic. If there is a PC-relative operand,
2485 the last one is chosen. Otherwise, the result is the number of the
2486 last immediate operand, and if there are none of those, we fail and
2490 get_relaxable_immed (xtensa_opcode opcode
)
2492 int last_immed
= -1;
2495 if (opcode
== XTENSA_UNDEFINED
)
2498 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2499 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2501 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2503 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2505 if (last_immed
== -1
2506 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2513 static xtensa_opcode
2514 get_opcode_from_buf (const char *buf
, int slot
)
2516 static xtensa_insnbuf insnbuf
= NULL
;
2517 static xtensa_insnbuf slotbuf
= NULL
;
2518 xtensa_isa isa
= xtensa_default_isa
;
2523 insnbuf
= xtensa_insnbuf_alloc (isa
);
2524 slotbuf
= xtensa_insnbuf_alloc (isa
);
2527 xtensa_insnbuf_from_chars (isa
, insnbuf
, buf
, 0);
2528 fmt
= xtensa_format_decode (isa
, insnbuf
);
2529 if (fmt
== XTENSA_UNDEFINED
)
2530 return XTENSA_UNDEFINED
;
2532 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2533 return XTENSA_UNDEFINED
;
2535 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2536 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2540 #ifdef TENSILICA_DEBUG
2542 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2545 xtensa_print_insn_table (void)
2547 int num_opcodes
, num_operands
;
2548 xtensa_opcode opcode
;
2549 xtensa_isa isa
= xtensa_default_isa
;
2551 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2552 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2555 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2556 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2557 for (opn
= 0; opn
< num_operands
; opn
++)
2559 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2561 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2563 xtensa_regfile opnd_rf
=
2564 xtensa_operand_regfile (isa
, opcode
, opn
);
2565 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2567 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2568 fputs ("[lLr] ", stderr
);
2570 fputs ("i ", stderr
);
2572 fprintf (stderr
, "\n");
2578 print_vliw_insn (xtensa_insnbuf vbuf
)
2580 xtensa_isa isa
= xtensa_default_isa
;
2581 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2582 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2585 fprintf (stderr
, "format = %d\n", f
);
2587 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2589 xtensa_opcode opcode
;
2593 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2594 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2595 opname
= xtensa_opcode_name (isa
, opcode
);
2597 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2598 fprintf (stderr
, " operands = ");
2600 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2604 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2606 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2607 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2608 fprintf (stderr
, "%d ", val
);
2610 fprintf (stderr
, "\n");
2612 xtensa_insnbuf_free (isa
, sbuf
);
2615 #endif /* TENSILICA_DEBUG */
2619 is_direct_call_opcode (xtensa_opcode opcode
)
2621 xtensa_isa isa
= xtensa_default_isa
;
2622 int n
, num_operands
;
2624 if (xtensa_opcode_is_call (isa
, opcode
) == 0)
2627 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2628 for (n
= 0; n
< num_operands
; n
++)
2630 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2631 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2638 /* Convert from BFD relocation type code to slot and operand number.
2639 Returns non-zero on failure. */
2642 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2644 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2645 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2647 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2650 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2651 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2653 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2663 /* Convert from slot number to BFD relocation type code for the
2664 standard PC-relative relocations. Return BFD_RELOC_NONE on
2667 static bfd_reloc_code_real_type
2668 encode_reloc (int slot
)
2670 if (slot
< 0 || slot
> 14)
2671 return BFD_RELOC_NONE
;
2673 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2677 /* Convert from slot numbers to BFD relocation type code for the
2678 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2680 static bfd_reloc_code_real_type
2681 encode_alt_reloc (int slot
)
2683 if (slot
< 0 || slot
> 14)
2684 return BFD_RELOC_NONE
;
2686 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2691 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2694 xtensa_opcode opcode
,
2700 uint32 valbuf
= value
;
2702 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2704 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2706 as_bad_where ((char *) file
, line
,
2707 _("operand %u is out of range for '%s'"), value
,
2708 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2710 as_bad_where ((char *) file
, line
,
2711 _("operand %u is invalid for '%s'"), value
,
2712 xtensa_opcode_name (xtensa_default_isa
, opcode
));
2716 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2722 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2725 xtensa_opcode opcode
,
2729 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2730 fmt
, slot
, slotbuf
, &val
);
2731 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2736 /* Checks for rules from xtensa-relax tables. */
2738 /* The routine xg_instruction_matches_option_term must return TRUE
2739 when a given option term is true. The meaning of all of the option
2740 terms is given interpretation by this function. This is needed when
2741 an option depends on the state of a directive, but there are no such
2742 options in use right now. */
2745 xg_instruction_matches_option_term (TInsn
*insn ATTRIBUTE_UNUSED
,
2746 const ReqOrOption
*option
)
2748 if (strcmp (option
->option_name
, "realnop") == 0
2749 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2751 /* These conditions were evaluated statically when building the
2752 relaxation table. There's no need to reevaluate them now. */
2757 as_fatal (_("internal error: unknown option name '%s'"),
2758 option
->option_name
);
2764 xg_instruction_matches_or_options (TInsn
*insn
,
2765 const ReqOrOptionList
*or_option
)
2767 const ReqOrOption
*option
;
2768 /* Must match each of the AND terms. */
2769 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2771 if (xg_instruction_matches_option_term (insn
, option
))
2779 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2781 const ReqOption
*req_options
;
2782 /* Must match each of the AND terms. */
2783 for (req_options
= options
;
2784 req_options
!= NULL
;
2785 req_options
= req_options
->next
)
2787 /* Must match one of the OR clauses. */
2788 if (!xg_instruction_matches_or_options (insn
,
2789 req_options
->or_option_terms
))
2796 /* Return the transition rule that matches or NULL if none matches. */
2799 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2801 PreconditionList
*condition_l
;
2803 if (rule
->opcode
!= insn
->opcode
)
2806 for (condition_l
= rule
->conditions
;
2807 condition_l
!= NULL
;
2808 condition_l
= condition_l
->next
)
2812 Precondition
*cond
= condition_l
->precond
;
2817 /* The expression must be the constant. */
2818 assert (cond
->op_num
< insn
->ntok
);
2819 exp1
= &insn
->tok
[cond
->op_num
];
2820 if (expr_is_const (exp1
))
2825 if (get_expr_const (exp1
) != cond
->op_data
)
2829 if (get_expr_const (exp1
) == cond
->op_data
)
2836 else if (expr_is_register (exp1
))
2841 if (get_expr_register (exp1
) != cond
->op_data
)
2845 if (get_expr_register (exp1
) == cond
->op_data
)
2857 assert (cond
->op_num
< insn
->ntok
);
2858 assert (cond
->op_data
< insn
->ntok
);
2859 exp1
= &insn
->tok
[cond
->op_num
];
2860 exp2
= &insn
->tok
[cond
->op_data
];
2865 if (!expr_is_equal (exp1
, exp2
))
2869 if (expr_is_equal (exp1
, exp2
))
2881 if (!xg_instruction_matches_options (insn
, rule
->options
))
2889 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2891 bfd_boolean a_greater
= FALSE
;
2892 bfd_boolean b_greater
= FALSE
;
2894 ReqOptionList
*l_a
= a
->options
;
2895 ReqOptionList
*l_b
= b
->options
;
2897 /* We only care if they both are the same except for
2898 a const16 vs. an l32r. */
2900 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2902 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2903 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2904 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2906 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2908 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2910 /* This is the case we care about. */
2911 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2912 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2919 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2920 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2930 l_or_a
= l_or_a
->next
;
2931 l_or_b
= l_or_b
->next
;
2933 if (l_or_a
|| l_or_b
)
2942 /* Incomparable if the substitution was used differently in two cases. */
2943 if (a_greater
&& b_greater
)
2955 static TransitionRule
*
2956 xg_instruction_match (TInsn
*insn
)
2958 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2960 assert (insn
->opcode
< table
->num_opcodes
);
2962 /* Walk through all of the possible transitions. */
2963 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2965 TransitionRule
*rule
= l
->rule
;
2966 if (xg_instruction_matches_rule (insn
, rule
))
2973 /* Various Other Internal Functions. */
2976 is_unique_insn_expansion (TransitionRule
*r
)
2978 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2980 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2987 xg_get_build_instr_size (BuildInstr
*insn
)
2989 assert (insn
->typ
== INSTR_INSTR
);
2990 return xg_get_single_size (insn
->opcode
);
2995 xg_is_narrow_insn (TInsn
*insn
)
2997 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3000 assert (insn
->insn_type
== ITYPE_INSN
);
3001 assert (insn
->opcode
< table
->num_opcodes
);
3003 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3005 TransitionRule
*rule
= l
->rule
;
3007 if (xg_instruction_matches_rule (insn
, rule
)
3008 && is_unique_insn_expansion (rule
))
3010 /* It only generates one instruction... */
3011 assert (insn
->insn_type
== ITYPE_INSN
);
3012 /* ...and it is a larger instruction. */
3013 if (xg_get_single_size (insn
->opcode
)
3014 < xg_get_build_instr_size (rule
->to_instr
))
3022 return (num_match
== 1);
3027 xg_is_single_relaxable_insn (TInsn
*insn
)
3029 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3032 assert (insn
->insn_type
== ITYPE_INSN
);
3033 assert (insn
->opcode
< table
->num_opcodes
);
3035 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3037 TransitionRule
*rule
= l
->rule
;
3039 if (xg_instruction_matches_rule (insn
, rule
)
3040 && is_unique_insn_expansion (rule
))
3042 /* It only generates one instruction... */
3043 assert (insn
->insn_type
== ITYPE_INSN
);
3044 /* ... and it is a larger instruction. */
3045 if (xg_get_single_size (insn
->opcode
)
3046 <= xg_get_build_instr_size (rule
->to_instr
))
3054 return (num_match
== 1);
3058 /* Return the maximum number of bytes this opcode can expand to. */
3061 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3063 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3065 int max_size
= xg_get_single_size (opcode
);
3067 assert (opcode
< table
->num_opcodes
);
3069 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3071 TransitionRule
*rule
= l
->rule
;
3072 BuildInstr
*build_list
;
3077 build_list
= rule
->to_instr
;
3078 if (is_unique_insn_expansion (rule
))
3080 assert (build_list
->typ
== INSTR_INSTR
);
3081 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3084 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3086 switch (build_list
->typ
)
3089 this_size
+= xg_get_single_size (build_list
->opcode
);
3091 case INSTR_LITERAL_DEF
:
3092 case INSTR_LABEL_DEF
:
3097 if (this_size
> max_size
)
3098 max_size
= this_size
;
3104 /* Return the maximum number of literal bytes this opcode can generate. */
3107 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3109 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3113 assert (opcode
< table
->num_opcodes
);
3115 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3117 TransitionRule
*rule
= l
->rule
;
3118 BuildInstr
*build_list
;
3123 build_list
= rule
->to_instr
;
3124 if (is_unique_insn_expansion (rule
))
3126 assert (build_list
->typ
== INSTR_INSTR
);
3127 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3130 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3132 switch (build_list
->typ
)
3134 case INSTR_LITERAL_DEF
:
3135 /* Hard-coded 4-byte literal. */
3139 case INSTR_LABEL_DEF
:
3144 if (this_size
> max_size
)
3145 max_size
= this_size
;
3152 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3154 int steps_taken
= 0;
3155 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3158 assert (insn
->insn_type
== ITYPE_INSN
);
3159 assert (insn
->opcode
< table
->num_opcodes
);
3161 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3163 TransitionRule
*rule
= l
->rule
;
3165 if (xg_instruction_matches_rule (insn
, rule
))
3167 if (steps_taken
== lateral_steps
)
3177 get_special_literal_symbol (void)
3179 static symbolS
*sym
= NULL
;
3182 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3188 get_special_label_symbol (void)
3190 static symbolS
*sym
= NULL
;
3193 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3199 xg_valid_literal_expression (const expressionS
*exp
)
3216 /* This will check to see if the value can be converted into the
3217 operand type. It will return TRUE if it does not fit. */
3220 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3222 uint32 valbuf
= value
;
3223 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3229 /* Assumes: All immeds are constants. Check that all constants fit
3230 into their immeds; return FALSE if not. */
3233 xg_immeds_fit (const TInsn
*insn
)
3235 xtensa_isa isa
= xtensa_default_isa
;
3239 assert (insn
->insn_type
== ITYPE_INSN
);
3240 for (i
= 0; i
< n
; ++i
)
3242 const expressionS
*expr
= &insn
->tok
[i
];
3243 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3250 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3255 /* The symbol should have a fixup associated with it. */
3264 /* This should only be called after we have an initial
3265 estimate of the addresses. */
3268 xg_symbolic_immeds_fit (const TInsn
*insn
,
3274 xtensa_isa isa
= xtensa_default_isa
;
3282 assert (insn
->insn_type
== ITYPE_INSN
);
3284 for (i
= 0; i
< n
; ++i
)
3286 const expressionS
*expr
= &insn
->tok
[i
];
3287 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3294 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3300 /* Check for the worst case. */
3301 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3306 /* We only allow symbols for PC-relative references.
3307 If pc_frag == 0, then we don't have frag locations yet. */
3309 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3312 /* If it is a weak symbol, then assume it won't reach. */
3313 if (S_IS_WEAK (expr
->X_add_symbol
))
3316 if (is_direct_call_opcode (insn
->opcode
)
3317 && ! pc_frag
->tc_frag_data
.use_longcalls
)
3319 /* If callee is undefined or in a different segment, be
3320 optimistic and assume it will be in range. */
3321 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3325 /* Only references within a segment can be known to fit in the
3326 operands at assembly time. */
3327 if (S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3330 symbolP
= expr
->X_add_symbol
;
3331 sym_frag
= symbol_get_frag (symbolP
);
3332 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3333 pc
= pc_frag
->fr_address
+ pc_offset
;
3335 /* If frag has yet to be reached on this pass, assume it
3336 will move by STRETCH just as we did. If this is not so,
3337 it will be because some frag between grows, and that will
3338 force another pass. Beware zero-length frags. There
3339 should be a faster way to do this. */
3342 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3343 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3348 new_offset
= target
;
3349 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3350 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3355 /* The symbol should have a fixup associated with it. */
3364 /* Return TRUE on success. */
3367 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3372 memset (targ
, 0, sizeof (TInsn
));
3373 targ
->loc
= insn
->loc
;
3378 targ
->opcode
= bi
->opcode
;
3379 targ
->insn_type
= ITYPE_INSN
;
3380 targ
->is_specific_opcode
= FALSE
;
3382 for (; op
!= NULL
; op
= op
->next
)
3384 int op_num
= op
->op_num
;
3385 int op_data
= op
->op_data
;
3387 assert (op
->op_num
< MAX_INSN_ARGS
);
3389 if (targ
->ntok
<= op_num
)
3390 targ
->ntok
= op_num
+ 1;
3395 set_expr_const (&targ
->tok
[op_num
], op_data
);
3398 assert (op_data
< insn
->ntok
);
3399 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3402 sym
= get_special_literal_symbol ();
3403 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3406 sym
= get_special_label_symbol ();
3407 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3409 case OP_OPERAND_HI16U
:
3410 case OP_OPERAND_LOW16U
:
3411 assert (op_data
< insn
->ntok
);
3412 if (expr_is_const (&insn
->tok
[op_data
]))
3415 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3416 val
= xg_apply_userdef_op_fn (op
->typ
,
3419 targ
->tok
[op_num
].X_add_number
= val
;
3423 /* For const16 we can create relocations for these. */
3424 if (targ
->opcode
== XTENSA_UNDEFINED
3425 || (targ
->opcode
!= xtensa_const16_opcode
))
3427 assert (op_data
< insn
->ntok
);
3428 /* Need to build a O_lo16 or O_hi16. */
3429 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3430 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3432 if (op
->typ
== OP_OPERAND_HI16U
)
3433 targ
->tok
[op_num
].X_op
= O_hi16
;
3434 else if (op
->typ
== OP_OPERAND_LOW16U
)
3435 targ
->tok
[op_num
].X_op
= O_lo16
;
3442 /* currently handles:
3445 OP_OPERAND_F32MINUS */
3446 if (xg_has_userdef_op_fn (op
->typ
))
3448 assert (op_data
< insn
->ntok
);
3449 if (expr_is_const (&insn
->tok
[op_data
]))
3452 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3453 val
= xg_apply_userdef_op_fn (op
->typ
,
3456 targ
->tok
[op_num
].X_add_number
= val
;
3459 return FALSE
; /* We cannot use a relocation for this. */
3468 case INSTR_LITERAL_DEF
:
3470 targ
->opcode
= XTENSA_UNDEFINED
;
3471 targ
->insn_type
= ITYPE_LITERAL
;
3472 targ
->is_specific_opcode
= FALSE
;
3473 for (; op
!= NULL
; op
= op
->next
)
3475 int op_num
= op
->op_num
;
3476 int op_data
= op
->op_data
;
3477 assert (op
->op_num
< MAX_INSN_ARGS
);
3479 if (targ
->ntok
<= op_num
)
3480 targ
->ntok
= op_num
+ 1;
3485 assert (op_data
< insn
->ntok
);
3486 /* We can only pass resolvable literals through. */
3487 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3489 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3501 case INSTR_LABEL_DEF
:
3503 targ
->opcode
= XTENSA_UNDEFINED
;
3504 targ
->insn_type
= ITYPE_LABEL
;
3505 targ
->is_specific_opcode
= FALSE
;
3506 /* Literal with no ops is a label? */
3507 assert (op
== NULL
);
3518 /* Return TRUE on success. */
3521 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3523 for (; bi
!= NULL
; bi
= bi
->next
)
3525 TInsn
*next_insn
= istack_push_space (istack
);
3527 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3534 /* Return TRUE on valid expansion. */
3537 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3539 int stack_size
= istack
->ninsn
;
3540 int steps_taken
= 0;
3541 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3544 assert (insn
->insn_type
== ITYPE_INSN
);
3545 assert (insn
->opcode
< table
->num_opcodes
);
3547 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3549 TransitionRule
*rule
= l
->rule
;
3551 if (xg_instruction_matches_rule (insn
, rule
))
3553 if (lateral_steps
== steps_taken
)
3557 /* This is it. Expand the rule to the stack. */
3558 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3561 /* Check to see if it fits. */
3562 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3564 TInsn
*insn
= &istack
->insn
[i
];
3566 if (insn
->insn_type
== ITYPE_INSN
3567 && !tinsn_has_symbolic_operands (insn
)
3568 && !xg_immeds_fit (insn
))
3570 istack
->ninsn
= stack_size
;
3584 xg_expand_narrow (TInsn
*targ
, TInsn
*insn
)
3586 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3589 assert (insn
->insn_type
== ITYPE_INSN
);
3590 assert (insn
->opcode
< table
->num_opcodes
);
3592 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3594 TransitionRule
*rule
= l
->rule
;
3595 if (xg_instruction_matches_rule (insn
, rule
)
3596 && is_unique_insn_expansion (rule
))
3598 /* Is it a larger instruction? */
3599 if (xg_get_single_size (insn
->opcode
)
3600 <= xg_get_build_instr_size (rule
->to_instr
))
3602 xg_build_to_insn (targ
, insn
, rule
->to_instr
);
3611 /* Relax the assembly instruction at least "min_steps".
3612 Return the number of steps taken. */
3615 xg_assembly_relax (IStack
*istack
,
3618 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3619 offsetT pc_offset
, /* offset in fragment */
3620 int min_steps
, /* minimum conversion steps */
3621 long stretch
) /* number of bytes stretched so far */
3623 int steps_taken
= 0;
3625 /* assert (has no symbolic operands)
3626 Some of its immeds don't fit.
3627 Try to build a relaxed version.
3628 This may go through a couple of stages
3629 of single instruction transformations before
3632 TInsn single_target
;
3634 int lateral_steps
= 0;
3635 int istack_size
= istack
->ninsn
;
3637 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3638 && steps_taken
>= min_steps
)
3640 istack_push (istack
, insn
);
3643 current_insn
= *insn
;
3645 /* Walk through all of the single instruction expansions. */
3646 while (xg_is_single_relaxable_insn (¤t_insn
))
3648 int error_val
= xg_expand_narrow (&single_target
, ¤t_insn
);
3650 assert (!error_val
);
3652 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3656 if (steps_taken
>= min_steps
)
3658 istack_push (istack
, &single_target
);
3662 current_insn
= single_target
;
3665 /* Now check for a multi-instruction expansion. */
3666 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3668 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3671 if (steps_taken
>= min_steps
)
3673 istack_push (istack
, ¤t_insn
);
3678 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3680 if (steps_taken
>= min_steps
)
3684 istack
->ninsn
= istack_size
;
3687 /* It's not going to work -- use the original. */
3688 istack_push (istack
, insn
);
3694 xg_force_frag_space (int size
)
3696 /* This may have the side effect of creating a new fragment for the
3697 space to go into. I just do not like the name of the "frag"
3704 xg_finish_frag (char *last_insn
,
3705 enum xtensa_relax_statesE frag_state
,
3706 enum xtensa_relax_statesE slot0_state
,
3708 bfd_boolean is_insn
)
3710 /* Finish off this fragment so that it has at LEAST the desired
3711 max_growth. If it doesn't fit in this fragment, close this one
3712 and start a new one. In either case, return a pointer to the
3713 beginning of the growth area. */
3717 xg_force_frag_space (max_growth
);
3719 old_frag
= frag_now
;
3721 frag_now
->fr_opcode
= last_insn
;
3723 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3725 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3726 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3728 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3729 xtensa_set_frag_assembly_state (frag_now
);
3731 /* Just to make sure that we did not split it up. */
3732 assert (old_frag
->fr_next
== frag_now
);
3736 /* Return TRUE if the target frag is one of the next non-empty frags. */
3739 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3744 for (; fragP
; fragP
= fragP
->fr_next
)
3746 if (fragP
== target
)
3748 if (fragP
->fr_fix
!= 0)
3750 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3752 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3753 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3755 if (fragP
->fr_type
== rs_space
)
3763 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3765 xtensa_isa isa
= xtensa_default_isa
;
3767 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3772 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 0
3773 && xtensa_opcode_is_jump (isa
, insn
->opcode
) == 0)
3776 for (i
= 0; i
< num_ops
; i
++)
3778 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3784 if (target_op
== -1)
3787 if (insn
->ntok
<= target_op
)
3790 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3793 sym
= insn
->tok
[target_op
].X_add_symbol
;
3797 if (insn
->tok
[target_op
].X_add_number
!= 0)
3800 target_frag
= symbol_get_frag (sym
);
3801 if (target_frag
== NULL
)
3804 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3805 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3813 xg_add_branch_and_loop_targets (TInsn
*insn
)
3815 xtensa_isa isa
= xtensa_default_isa
;
3816 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3818 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3821 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3822 && insn
->tok
[i
].X_op
== O_symbol
)
3823 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3827 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3828 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3832 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3834 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3835 && insn
->tok
[i
].X_op
== O_symbol
)
3837 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3838 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3839 if (S_IS_DEFINED (sym
))
3840 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3847 /* Return FALSE if no error. */
3850 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3855 switch (instr_spec
->typ
)
3858 new_insn
->insn_type
= ITYPE_INSN
;
3859 new_insn
->opcode
= instr_spec
->opcode
;
3860 new_insn
->is_specific_opcode
= FALSE
;
3861 new_insn
->loc
= old_insn
->loc
;
3863 case INSTR_LITERAL_DEF
:
3864 new_insn
->insn_type
= ITYPE_LITERAL
;
3865 new_insn
->opcode
= XTENSA_UNDEFINED
;
3866 new_insn
->is_specific_opcode
= FALSE
;
3867 new_insn
->loc
= old_insn
->loc
;
3869 case INSTR_LABEL_DEF
:
3870 as_bad (_("INSTR_LABEL_DEF not supported yet"));
3874 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3877 const expressionS
*src_exp
;
3883 /* The expression must be the constant. */
3884 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3885 exp
= &new_insn
->tok
[b_op
->op_num
];
3886 set_expr_const (exp
, b_op
->op_data
);
3890 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3891 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3892 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3893 exp
= &new_insn
->tok
[b_op
->op_num
];
3894 copy_expr (exp
, src_exp
);
3899 as_bad (_("can't handle generation of literal/labels yet"));
3903 as_bad (_("can't handle undefined OP TYPE"));
3908 new_insn
->ntok
= num_ops
;
3913 /* Return TRUE if it was simplified. */
3916 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3918 TransitionRule
*rule
;
3919 BuildInstr
*insn_spec
;
3921 if (old_insn
->is_specific_opcode
|| !density_supported
)
3924 rule
= xg_instruction_match (old_insn
);
3928 insn_spec
= rule
->to_instr
;
3929 /* There should only be one. */
3930 assert (insn_spec
!= NULL
);
3931 assert (insn_spec
->next
== NULL
);
3932 if (insn_spec
->next
!= NULL
)
3935 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3941 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3942 l32i.n. (2) Check the number of operands. (3) Place the instruction
3943 tokens into the stack or relax it and place multiple
3944 instructions/literals onto the stack. Return FALSE if no error. */
3947 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3951 bfd_boolean do_expand
;
3953 memset (&new_insn
, 0, sizeof (TInsn
));
3955 /* Narrow it if we can. xg_simplify_insn now does all the
3956 appropriate checking (e.g., for the density option). */
3957 if (xg_simplify_insn (orig_insn
, &new_insn
))
3958 orig_insn
= &new_insn
;
3960 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3962 if (orig_insn
->ntok
< noperands
)
3964 as_bad (_("found %d operands for '%s': Expected %d"),
3966 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3970 if (orig_insn
->ntok
> noperands
)
3971 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3973 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3976 /* If there are not enough operands, we will assert above. If there
3977 are too many, just cut out the extras here. */
3978 orig_insn
->ntok
= noperands
;
3980 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3983 /* If the instruction will definitely need to be relaxed, it is better
3984 to expand it now for better scheduling. Decide whether to expand
3986 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3988 /* Calls should be expanded to longcalls only in the backend relaxation
3989 so that the assembly scheduler will keep the L32R/CALLX instructions
3991 if (is_direct_call_opcode (orig_insn
->opcode
))
3994 if (tinsn_has_symbolic_operands (orig_insn
))
3996 /* The values of symbolic operands are not known yet, so only expand
3997 now if an operand is "complex" (e.g., difference of symbols) and
3998 will have to be stored as a literal regardless of the value. */
3999 if (!tinsn_has_complex_operands (orig_insn
))
4002 else if (xg_immeds_fit (orig_insn
))
4006 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4008 istack_push (istack
, orig_insn
);
4014 /* Return TRUE if the section flags are marked linkonce
4015 or the name is .gnu.linkonce*. */
4018 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4020 flagword flags
, link_once_flags
;
4022 flags
= bfd_get_section_flags (abfd
, sec
);
4023 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4025 /* Flags might not be set yet. */
4026 if (!link_once_flags
)
4028 static size_t len
= sizeof ".gnu.linkonce.t.";
4030 if (strncmp (segment_name (sec
), ".gnu.linkonce.t.", len
- 1) == 0)
4031 link_once_flags
= SEC_LINK_ONCE
;
4033 return (link_once_flags
!= 0);
4038 xtensa_add_literal_sym (symbolS
*sym
)
4042 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4044 l
->next
= literal_syms
;
4050 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4052 static int lit_num
= 0;
4053 static char name
[256];
4056 sprintf (name
, ".L_lit_sym%d", lit_num
);
4058 /* Create a local symbol. If it is in a linkonce section, we have to
4059 be careful to make sure that if it is used in a relocation that the
4060 symbol will be in the output file. */
4061 if (get_is_linkonce_section (stdoutput
, sec
))
4063 symbolP
= symbol_new (name
, sec
, 0, frag
);
4064 S_CLEAR_EXTERNAL (symbolP
);
4065 /* symbolP->local = 1; */
4068 symbolP
= symbol_new (name
, sec
, 0, frag
);
4070 xtensa_add_literal_sym (symbolP
);
4072 frag
->tc_frag_data
.is_literal
= TRUE
;
4078 /* Currently all literals that are generated here are 32-bit L32R targets. */
4081 xg_assemble_literal (/* const */ TInsn
*insn
)
4084 symbolS
*lit_sym
= NULL
;
4086 /* size = 4 for L32R. It could easily be larger when we move to
4087 larger constants. Add a parameter later. */
4088 offsetT litsize
= 4;
4089 offsetT litalign
= 2; /* 2^2 = 4 */
4090 expressionS saved_loc
;
4091 expressionS
* emit_val
;
4093 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4095 assert (insn
->insn_type
== ITYPE_LITERAL
);
4096 assert (insn
->ntok
== 1); /* must be only one token here */
4098 xtensa_switch_to_literal_fragment (&state
);
4100 emit_val
= &insn
->tok
[0];
4101 if (emit_val
->X_op
== O_big
)
4103 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4106 /* This happens when someone writes a "movi a2, big_number". */
4107 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4108 _("invalid immediate"));
4109 xtensa_restore_emit_state (&state
);
4114 /* Force a 4-byte align here. Note that this opens a new frag, so all
4115 literals done with this function have a frag to themselves. That's
4116 important for the way text section literals work. */
4117 frag_align (litalign
, 0, 0);
4118 record_alignment (now_seg
, litalign
);
4120 if (emit_val
->X_op
== O_pltrel
)
4122 char *p
= frag_more (litsize
);
4123 xtensa_set_frag_assembly_state (frag_now
);
4124 if (emit_val
->X_add_symbol
)
4125 emit_val
->X_op
= O_symbol
;
4127 emit_val
->X_op
= O_constant
;
4128 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4129 litsize
, emit_val
, 0, BFD_RELOC_XTENSA_PLT
);
4132 emit_expr (emit_val
, litsize
);
4134 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4135 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4136 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4137 lit_sym
= frag_now
->fr_symbol
;
4138 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4141 xtensa_restore_emit_state (&state
);
4147 xg_assemble_literal_space (/* const */ int size
, int slot
)
4150 /* We might have to do something about this alignment. It only
4151 takes effect if something is placed here. */
4152 offsetT litalign
= 2; /* 2^2 = 4 */
4153 fragS
*lit_saved_frag
;
4155 assert (size
% 4 == 0);
4157 xtensa_switch_to_literal_fragment (&state
);
4159 /* Force a 4-byte align here. */
4160 frag_align (litalign
, 0, 0);
4161 record_alignment (now_seg
, litalign
);
4163 xg_force_frag_space (size
);
4165 lit_saved_frag
= frag_now
;
4166 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4167 frag_now
->tc_frag_data
.is_literal
= TRUE
;
4168 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4169 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4172 xtensa_restore_emit_state (&state
);
4173 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4177 /* Put in a fixup record based on the opcode.
4178 Return TRUE on success. */
4181 xg_add_opcode_fix (TInsn
*tinsn
,
4189 xtensa_opcode opcode
= tinsn
->opcode
;
4190 bfd_reloc_code_real_type reloc
;
4191 reloc_howto_type
*howto
;
4195 reloc
= BFD_RELOC_NONE
;
4197 /* First try the special cases for "alternate" relocs. */
4198 if (opcode
== xtensa_l32r_opcode
)
4200 if (fragP
->tc_frag_data
.use_absolute_literals
)
4201 reloc
= encode_alt_reloc (slot
);
4203 else if (opcode
== xtensa_const16_opcode
)
4205 if (expr
->X_op
== O_lo16
)
4207 reloc
= encode_reloc (slot
);
4208 expr
->X_op
= O_symbol
;
4210 else if (expr
->X_op
== O_hi16
)
4212 reloc
= encode_alt_reloc (slot
);
4213 expr
->X_op
= O_symbol
;
4217 if (opnum
!= get_relaxable_immed (opcode
))
4219 as_bad (_("invalid relocation for operand %i of '%s'"),
4220 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4224 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4225 into the symbol table where the generic portions of the assembler
4226 won't know what to do with them. */
4227 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4229 as_bad (_("invalid expression for operand %i of '%s'"),
4230 opnum
, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4234 /* Next try the generic relocs. */
4235 if (reloc
== BFD_RELOC_NONE
)
4236 reloc
= encode_reloc (slot
);
4237 if (reloc
== BFD_RELOC_NONE
)
4239 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4243 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4246 as_bad (_("undefined symbol for opcode \"%s\""),
4247 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4251 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4252 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4253 howto
->pc_relative
, reloc
);
4254 the_fix
->fx_no_overflow
= 1;
4256 if (expr
->X_add_symbol
4257 && (S_IS_EXTERNAL (expr
->X_add_symbol
)
4258 || S_IS_WEAK (expr
->X_add_symbol
)))
4259 the_fix
->fx_plt
= TRUE
;
4261 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4262 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4263 the_fix
->tc_fix_data
.slot
= slot
;
4270 xg_emit_insn_to_buf (TInsn
*tinsn
,
4275 bfd_boolean build_fix
)
4277 static xtensa_insnbuf insnbuf
= NULL
;
4278 bfd_boolean has_symbolic_immed
= FALSE
;
4279 bfd_boolean ok
= TRUE
;
4281 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4283 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4284 if (has_symbolic_immed
&& build_fix
)
4287 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4288 expressionS
*exp
= &tinsn
->tok
[opnum
];
4290 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, 0, exp
, fragP
, offset
))
4293 fragP
->tc_frag_data
.is_insn
= TRUE
;
4294 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4300 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4302 symbolS
*sym
= get_special_literal_symbol ();
4306 assert (insn
->insn_type
== ITYPE_INSN
);
4307 for (i
= 0; i
< insn
->ntok
; i
++)
4308 if (insn
->tok
[i
].X_add_symbol
== sym
)
4309 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4315 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4317 symbolS
*sym
= get_special_label_symbol ();
4319 /* assert (!insn->is_literal); */
4320 for (i
= 0; i
< insn
->ntok
; i
++)
4321 if (insn
->tok
[i
].X_add_symbol
== sym
)
4322 insn
->tok
[i
].X_add_symbol
= label_sym
;
4327 /* Return TRUE if the instruction can write to the specified
4328 integer register. */
4331 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4335 xtensa_isa isa
= xtensa_default_isa
;
4337 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4339 for (i
= 0; i
< num_ops
; i
++)
4342 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4343 if ((inout
== 'o' || inout
== 'm')
4344 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4346 xtensa_regfile opnd_rf
=
4347 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4348 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4350 if ((insn
->tok
[i
].X_op
== O_register
)
4351 && (insn
->tok
[i
].X_add_number
== regnum
))
4361 is_bad_loopend_opcode (const TInsn
*tinsn
)
4363 xtensa_opcode opcode
= tinsn
->opcode
;
4365 if (opcode
== XTENSA_UNDEFINED
)
4368 if (opcode
== xtensa_call0_opcode
4369 || opcode
== xtensa_callx0_opcode
4370 || opcode
== xtensa_call4_opcode
4371 || opcode
== xtensa_callx4_opcode
4372 || opcode
== xtensa_call8_opcode
4373 || opcode
== xtensa_callx8_opcode
4374 || opcode
== xtensa_call12_opcode
4375 || opcode
== xtensa_callx12_opcode
4376 || opcode
== xtensa_isync_opcode
4377 || opcode
== xtensa_ret_opcode
4378 || opcode
== xtensa_ret_n_opcode
4379 || opcode
== xtensa_retw_opcode
4380 || opcode
== xtensa_retw_n_opcode
4381 || opcode
== xtensa_waiti_opcode
4382 || opcode
== xtensa_rsr_lcount_opcode
)
4389 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4390 This allows the debugger to add unaligned labels.
4391 Also, the assembler generates stabs labels that need
4392 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4395 is_unaligned_label (symbolS
*sym
)
4397 const char *name
= S_GET_NAME (sym
);
4398 static size_t fake_size
= 0;
4402 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4405 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4407 fake_size
= strlen (FAKE_LABEL_NAME
);
4410 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4411 && (name
[fake_size
] == 'F'
4412 || name
[fake_size
] == 'L'
4413 || (name
[fake_size
] == 'e'
4414 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4422 next_non_empty_frag (const fragS
*fragP
)
4424 fragS
*next_fragP
= fragP
->fr_next
;
4426 /* Sometimes an empty will end up here due storage allocation issues.
4427 So we have to skip until we find something legit. */
4428 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4429 next_fragP
= next_fragP
->fr_next
;
4431 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4439 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4441 xtensa_opcode out_opcode
;
4442 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4444 if (next_fragP
== NULL
)
4447 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4448 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4450 *opcode
= out_opcode
;
4458 frag_format_size (const fragS
*fragP
)
4460 static xtensa_insnbuf insnbuf
= NULL
;
4461 xtensa_isa isa
= xtensa_default_isa
;
4466 insnbuf
= xtensa_insnbuf_alloc (isa
);
4469 return XTENSA_UNDEFINED
;
4471 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
, 0);
4473 fmt
= xtensa_format_decode (isa
, insnbuf
);
4474 if (fmt
== XTENSA_UNDEFINED
)
4475 return XTENSA_UNDEFINED
;
4476 fmt_size
= xtensa_format_length (isa
, fmt
);
4478 /* If the next format won't be changing due to relaxation, just
4479 return the length of the first format. */
4480 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4483 /* If during relaxation we have to pull an instruction out of a
4484 multi-slot instruction, we will return the more conservative
4485 number. This works because alignment on bigger instructions
4486 is more restrictive than alignment on smaller instructions.
4487 This is more conservative than we would like, but it happens
4490 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4493 /* If we aren't doing one of our own relaxations or it isn't
4494 slot-based, then the insn size won't change. */
4495 if (fragP
->fr_type
!= rs_machine_dependent
)
4497 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4500 /* If an instruction is about to grow, return the longer size. */
4501 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4502 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
)
4505 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4506 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4513 next_frag_format_size (const fragS
*fragP
)
4515 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4516 return frag_format_size (next_fragP
);
4520 /* If the next legit fragment is an end-of-loop marker,
4521 switch its state so it will instantiate a NOP. */
4524 update_next_frag_state (fragS
*fragP
)
4526 fragS
*next_fragP
= fragP
->fr_next
;
4527 fragS
*new_target
= NULL
;
4531 /* We are guaranteed there will be one of these... */
4532 while (!(next_fragP
->fr_type
== rs_machine_dependent
4533 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4534 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4535 next_fragP
= next_fragP
->fr_next
;
4537 assert (next_fragP
->fr_type
== rs_machine_dependent
4538 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4539 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4541 /* ...and one of these. */
4542 new_target
= next_fragP
->fr_next
;
4543 while (!(new_target
->fr_type
== rs_machine_dependent
4544 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4545 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4546 new_target
= new_target
->fr_next
;
4548 assert (new_target
->fr_type
== rs_machine_dependent
4549 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4550 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4553 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4555 if (next_fragP
->fr_type
== rs_machine_dependent
4556 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4558 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4562 next_fragP
= next_fragP
->fr_next
;
4568 next_frag_is_branch_target (const fragS
*fragP
)
4570 /* Sometimes an empty will end up here due to storage allocation issues,
4571 so we have to skip until we find something legit. */
4572 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4574 if (fragP
->tc_frag_data
.is_branch_target
)
4576 if (fragP
->fr_fix
!= 0)
4584 next_frag_is_loop_target (const fragS
*fragP
)
4586 /* Sometimes an empty will end up here due storage allocation issues.
4587 So we have to skip until we find something legit. */
4588 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4590 if (fragP
->tc_frag_data
.is_loop_target
)
4592 if (fragP
->fr_fix
!= 0)
4600 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4602 const fragS
*next_fragp
= fragp
->fr_next
;
4603 xtensa_opcode next_opcode
;
4605 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4608 /* Sometimes an empty will end up here due to storage allocation issues,
4609 so we have to skip until we find something legit. */
4610 while (next_fragp
->fr_fix
== 0)
4611 next_fragp
= next_fragp
->fr_next
;
4613 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4616 /* There is some implicit knowledge encoded in here.
4617 The LOOP instructions that are NOT RELAX_IMMED have
4618 been relaxed. Note that we can assume that the LOOP
4619 instruction is in slot 0 because loops aren't bundleable. */
4620 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4621 return get_expanded_loop_offset (next_opcode
);
4627 /* Mark a location where we can later insert literal frags. Update
4628 the section's literal_pool_loc, so subsequent literals can be
4629 placed nearest to their use. */
4632 xtensa_mark_literal_pool_location (void)
4634 /* Any labels pointing to the current location need
4635 to be adjusted to after the literal pool. */
4637 fragS
*pool_location
;
4639 if (use_literal_section
&& !directive_state
[directive_absolute_literals
])
4642 frag_align (2, 0, 0);
4643 record_alignment (now_seg
, 2);
4645 /* We stash info in the fr_var of these frags
4646 so we can later move the literal's fixes into this
4647 frchain's fix list. We can use fr_var because fr_var's
4648 interpretation depends solely on the fr_type and subtype. */
4649 pool_location
= frag_now
;
4650 frag_variant (rs_machine_dependent
, 0, (int) frchain_now
,
4651 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4652 xtensa_set_frag_assembly_state (frag_now
);
4653 frag_variant (rs_machine_dependent
, 0, (int) now_seg
,
4654 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4655 xtensa_set_frag_assembly_state (frag_now
);
4657 /* Now put a frag into the literal pool that points to this location. */
4658 set_literal_pool_location (now_seg
, pool_location
);
4659 xtensa_switch_to_non_abs_literal_fragment (&s
);
4660 frag_align (2, 0, 0);
4661 record_alignment (now_seg
, 2);
4663 /* Close whatever frag is there. */
4664 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4665 xtensa_set_frag_assembly_state (frag_now
);
4666 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4667 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4668 xtensa_restore_emit_state (&s
);
4669 xtensa_set_frag_assembly_state (frag_now
);
4673 /* Build a nop of the correct size into tinsn. */
4676 build_nop (TInsn
*tinsn
, int size
)
4682 tinsn
->opcode
= xtensa_nop_n_opcode
;
4684 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4685 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4689 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4691 tinsn
->opcode
= xtensa_or_opcode
;
4692 set_expr_const (&tinsn
->tok
[0], 1);
4693 set_expr_const (&tinsn
->tok
[1], 1);
4694 set_expr_const (&tinsn
->tok
[2], 1);
4698 tinsn
->opcode
= xtensa_nop_opcode
;
4700 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4705 /* Assemble a NOP of the requested size in the buffer. User must have
4706 allocated "buf" with at least "size" bytes. */
4709 assemble_nop (size_t size
, char *buf
)
4711 static xtensa_insnbuf insnbuf
= NULL
;
4714 build_nop (&tinsn
, size
);
4717 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4719 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4720 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
, buf
, 0);
4724 /* Return the number of bytes for the offset of the expanded loop
4725 instruction. This should be incorporated into the relaxation
4726 specification but is hard-coded here. This is used to auto-align
4727 the loop instruction. It is invalid to call this function if the
4728 configuration does not have loops or if the opcode is not a loop
4732 get_expanded_loop_offset (xtensa_opcode opcode
)
4734 /* This is the OFFSET of the loop instruction in the expanded loop.
4735 This MUST correspond directly to the specification of the loop
4736 expansion. It will be validated on fragment conversion. */
4737 assert (opcode
!= XTENSA_UNDEFINED
);
4738 if (opcode
== xtensa_loop_opcode
)
4740 if (opcode
== xtensa_loopnez_opcode
)
4742 if (opcode
== xtensa_loopgtz_opcode
)
4744 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4750 get_literal_pool_location (segT seg
)
4752 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4757 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4759 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4763 /* Set frag assembly state should be called when a new frag is
4764 opened and after a frag has been closed. */
4767 xtensa_set_frag_assembly_state (fragS
*fragP
)
4769 if (!density_supported
)
4770 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4772 /* This function is called from subsegs_finish, which is called
4773 after xtensa_end, so we can't use "use_transform" or
4774 "use_schedule" here. */
4775 if (!directive_state
[directive_transform
])
4776 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4777 if (directive_state
[directive_longcalls
])
4778 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4779 fragP
->tc_frag_data
.use_absolute_literals
=
4780 directive_state
[directive_absolute_literals
];
4781 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4786 relaxable_section (asection
*sec
)
4788 return (sec
->flags
& SEC_DEBUGGING
) == 0;
4793 xtensa_find_unmarked_state_frags (void)
4797 /* Walk over each fragment of all of the current segments. For each
4798 unmarked fragment, mark it with the same info as the previous
4800 for (seclist
= &stdoutput
->sections
;
4801 seclist
&& *seclist
;
4802 seclist
= &(*seclist
)->next
)
4804 segT sec
= *seclist
;
4805 segment_info_type
*seginfo
;
4808 flags
= bfd_get_section_flags (stdoutput
, sec
);
4809 if (flags
& SEC_DEBUGGING
)
4811 if (!(flags
& SEC_ALLOC
))
4814 seginfo
= seg_info (sec
);
4815 if (seginfo
&& seginfo
->frchainP
)
4817 fragS
*last_fragP
= 0;
4818 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4819 fragP
= fragP
->fr_next
)
4821 if (fragP
->fr_fix
!= 0
4822 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4824 if (last_fragP
== 0)
4826 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4827 _("assembly state not set for first frag in section %s"),
4832 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4833 fragP
->tc_frag_data
.is_no_density
=
4834 last_fragP
->tc_frag_data
.is_no_density
;
4835 fragP
->tc_frag_data
.is_no_transform
=
4836 last_fragP
->tc_frag_data
.is_no_transform
;
4837 fragP
->tc_frag_data
.use_longcalls
=
4838 last_fragP
->tc_frag_data
.use_longcalls
;
4839 fragP
->tc_frag_data
.use_absolute_literals
=
4840 last_fragP
->tc_frag_data
.use_absolute_literals
;
4843 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4852 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4854 void *unused ATTRIBUTE_UNUSED
)
4856 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4857 segment_info_type
*seginfo
= seg_info (sec
);
4858 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4860 if (flags
& SEC_CODE
)
4862 xtensa_isa isa
= xtensa_default_isa
;
4863 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4864 while (frag
!= NULL
)
4866 if (frag
->tc_frag_data
.is_branch_target
)
4872 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4873 fmt
= xtensa_format_decode (isa
, insnbuf
);
4874 op_size
= xtensa_format_length (isa
, fmt
);
4875 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4876 if (frag_addr
+ op_size
> (int) xtensa_fetch_width
)
4877 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4878 _("unaligned branch target: %d bytes at 0x%lx"),
4879 op_size
, frag
->fr_address
);
4881 frag
= frag
->fr_next
;
4883 xtensa_insnbuf_free (isa
, insnbuf
);
4889 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4891 void *unused ATTRIBUTE_UNUSED
)
4893 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4894 segment_info_type
*seginfo
= seg_info (sec
);
4895 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4896 xtensa_isa isa
= xtensa_default_isa
;
4898 if (flags
& SEC_CODE
)
4900 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4901 while (frag
!= NULL
)
4903 if (frag
->tc_frag_data
.is_first_loop_insn
)
4909 xtensa_insnbuf_from_chars (isa
, insnbuf
, frag
->fr_literal
, 0);
4910 fmt
= xtensa_format_decode (isa
, insnbuf
);
4911 op_size
= xtensa_format_length (isa
, fmt
);
4912 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4914 if (frag_addr
+ op_size
> (signed) xtensa_fetch_width
)
4915 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4916 _("unaligned loop: %d bytes at 0x%lx"),
4917 op_size
, frag
->fr_address
);
4919 frag
= frag
->fr_next
;
4921 xtensa_insnbuf_free (isa
, insnbuf
);
4927 xg_apply_fix_value (fixS
*fixP
, valueT val
)
4929 xtensa_isa isa
= xtensa_default_isa
;
4930 static xtensa_insnbuf insnbuf
= NULL
;
4931 static xtensa_insnbuf slotbuf
= NULL
;
4934 bfd_boolean alt_reloc
;
4935 xtensa_opcode opcode
;
4936 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4938 (void) decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
);
4940 as_fatal (_("unexpected fix"));
4944 insnbuf
= xtensa_insnbuf_alloc (isa
);
4945 slotbuf
= xtensa_insnbuf_alloc (isa
);
4948 xtensa_insnbuf_from_chars (isa
, insnbuf
, fixpos
, 0);
4949 fmt
= xtensa_format_decode (isa
, insnbuf
);
4950 if (fmt
== XTENSA_UNDEFINED
)
4951 as_fatal (_("undecodable fix"));
4952 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4953 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
4954 if (opcode
== XTENSA_UNDEFINED
)
4955 as_fatal (_("undecodable fix"));
4957 /* CONST16 immediates are not PC-relative, despite the fact that we
4958 reuse the normal PC-relative operand relocations for the low part
4959 of a CONST16 operand. */
4960 if (opcode
== xtensa_const16_opcode
)
4963 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
4964 get_relaxable_immed (opcode
), val
,
4965 fixP
->fx_file
, fixP
->fx_line
);
4967 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
4968 xtensa_insnbuf_to_chars (isa
, insnbuf
, fixpos
, 0);
4974 /* External Functions and Other GAS Hooks. */
4977 xtensa_target_format (void)
4979 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
4984 xtensa_file_arch_init (bfd
*abfd
)
4986 bfd_set_private_flags (abfd
, 0x100 | 0x200);
4991 md_number_to_chars (char *buf
, valueT val
, int n
)
4993 if (target_big_endian
)
4994 number_to_chars_bigendian (buf
, val
, n
);
4996 number_to_chars_littleendian (buf
, val
, n
);
5000 /* This function is called once, at assembler startup time. It should
5001 set up all the tables, etc. that the MD part of the assembler will
5007 segT current_section
= now_seg
;
5008 int current_subsec
= now_subseg
;
5011 xtensa_default_isa
= xtensa_isa_init (0, 0);
5012 isa
= xtensa_default_isa
;
5016 /* Set up the .literal, .fini.literal and .init.literal sections. */
5017 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5018 default_lit_sections
.init_lit_seg_name
= INIT_LITERAL_SECTION_NAME
;
5019 default_lit_sections
.fini_lit_seg_name
= FINI_LITERAL_SECTION_NAME
;
5020 default_lit_sections
.lit_seg_name
= LITERAL_SECTION_NAME
;
5021 default_lit_sections
.lit4_seg_name
= LIT4_SECTION_NAME
;
5023 subseg_set (current_section
, current_subsec
);
5025 xg_init_vinsn (&cur_vinsn
);
5027 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5028 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5029 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5030 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5031 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5032 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5033 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5034 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5035 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5036 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5037 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5038 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5039 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5040 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5041 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5042 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5043 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5044 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5045 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5046 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5047 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5048 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5049 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5050 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5051 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5052 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5053 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5054 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5055 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5057 init_op_placement_info_table ();
5059 /* Set up the assembly state. */
5060 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5061 xtensa_set_frag_assembly_state (frag_now
);
5065 /* TC_INIT_FIX_DATA hook */
5068 xtensa_init_fix_data (fixS
*x
)
5070 x
->tc_fix_data
.slot
= 0;
5071 x
->tc_fix_data
.X_add_symbol
= NULL
;
5072 x
->tc_fix_data
.X_add_number
= 0;
5076 /* tc_frob_label hook */
5079 xtensa_frob_label (symbolS
*sym
)
5081 float freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5083 /* Since the label was already attached to a frag associated with the
5084 previous basic block, it now needs to be reset to the current frag. */
5085 symbol_set_frag (sym
, frag_now
);
5086 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5088 if (generating_literals
)
5089 xtensa_add_literal_sym (sym
);
5091 xtensa_add_insn_label (sym
);
5093 if (symbol_get_tc (sym
)->is_loop_target
)
5095 if ((get_last_insn_flags (now_seg
, now_subseg
)
5096 & FLAG_IS_BAD_LOOPEND
) != 0)
5097 as_bad (_("invalid last instruction for a zero-overhead loop"));
5099 xtensa_set_frag_assembly_state (frag_now
);
5100 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5101 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5103 xtensa_set_frag_assembly_state (frag_now
);
5104 xtensa_move_labels (frag_now
, 0, TRUE
);
5107 /* No target aligning in the absolute section. */
5108 if (now_seg
!= absolute_section
5109 && do_align_targets ()
5110 && !is_unaligned_label (sym
)
5111 && !generating_literals
)
5113 xtensa_set_frag_assembly_state (frag_now
);
5115 frag_var (rs_machine_dependent
,
5117 RELAX_DESIRE_ALIGN_IF_TARGET
,
5118 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5119 xtensa_set_frag_assembly_state (frag_now
);
5120 xtensa_move_labels (frag_now
, 0, TRUE
);
5123 /* We need to mark the following properties even if we aren't aligning. */
5125 /* If the label is already known to be a branch target, i.e., a
5126 forward branch, mark the frag accordingly. Backward branches
5127 are handled by xg_add_branch_and_loop_targets. */
5128 if (symbol_get_tc (sym
)->is_branch_target
)
5129 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5131 /* Loops only go forward, so they can be identified here. */
5132 if (symbol_get_tc (sym
)->is_loop_target
)
5133 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5137 /* tc_unrecognized_line hook */
5140 xtensa_unrecognized_line (int ch
)
5145 if (cur_vinsn
.inside_bundle
== 0)
5147 /* PR8110: Cannot emit line number info inside a FLIX bundle
5148 when using --gstabs. Temporarily disable debug info. */
5149 generate_lineno_debug ();
5150 if (debug_type
== DEBUG_STABS
)
5152 xt_saved_debug_type
= debug_type
;
5153 debug_type
= DEBUG_NONE
;
5156 cur_vinsn
.inside_bundle
= 1;
5160 as_bad (_("extra opening brace"));
5166 if (cur_vinsn
.inside_bundle
)
5167 finish_vinsn (&cur_vinsn
);
5170 as_bad (_("extra closing brace"));
5175 as_bad (_("syntax error"));
5182 /* md_flush_pending_output hook */
5185 xtensa_flush_pending_output (void)
5187 if (cur_vinsn
.inside_bundle
)
5188 as_bad (_("missing closing brace"));
5190 /* If there is a non-zero instruction fragment, close it. */
5191 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5193 frag_wane (frag_now
);
5195 xtensa_set_frag_assembly_state (frag_now
);
5197 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5199 xtensa_clear_insn_labels ();
5203 /* We had an error while parsing an instruction. The string might look
5204 like this: "insn arg1, arg2 }". If so, we need to see the closing
5205 brace and reset some fields. Otherwise, the vinsn never gets closed
5206 and the num_slots field will grow past the end of the array of slots,
5207 and bad things happen. */
5210 error_reset_cur_vinsn (void)
5212 if (cur_vinsn
.inside_bundle
)
5214 if (*input_line_pointer
== '}'
5215 || *(input_line_pointer
- 1) == '}'
5216 || *(input_line_pointer
- 2) == '}')
5217 xg_clear_vinsn (&cur_vinsn
);
5223 md_assemble (char *str
)
5225 xtensa_isa isa
= xtensa_default_isa
;
5228 bfd_boolean has_underbar
= FALSE
;
5229 char *arg_strings
[MAX_INSN_ARGS
];
5231 TInsn orig_insn
; /* Original instruction from the input. */
5233 tinsn_init (&orig_insn
);
5235 /* Split off the opcode. */
5236 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5237 opname
= xmalloc (opnamelen
+ 1);
5238 memcpy (opname
, str
, opnamelen
);
5239 opname
[opnamelen
] = '\0';
5241 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5244 as_bad (_("syntax error"));
5248 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5251 /* Check for an underbar prefix. */
5254 has_underbar
= TRUE
;
5258 orig_insn
.insn_type
= ITYPE_INSN
;
5260 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5262 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5263 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5265 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5266 if (fmt
== XTENSA_UNDEFINED
)
5268 as_bad (_("unknown opcode or format name '%s'"), opname
);
5269 error_reset_cur_vinsn ();
5272 if (!cur_vinsn
.inside_bundle
)
5274 as_bad (_("format names only valid inside bundles"));
5275 error_reset_cur_vinsn ();
5278 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5279 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5281 cur_vinsn
.format
= fmt
;
5282 free (has_underbar
? opname
- 1 : opname
);
5283 error_reset_cur_vinsn ();
5287 /* Parse the arguments. */
5288 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5290 as_bad (_("syntax error"));
5291 error_reset_cur_vinsn ();
5295 /* Free the opcode and argument strings, now that they've been parsed. */
5296 free (has_underbar
? opname
- 1 : opname
);
5298 while (num_args
-- > 0)
5299 free (arg_strings
[num_args
]);
5301 /* Get expressions for invisible operands. */
5302 if (get_invisible_operands (&orig_insn
))
5304 error_reset_cur_vinsn ();
5308 /* Check for the right number and type of arguments. */
5309 if (tinsn_check_arguments (&orig_insn
))
5311 error_reset_cur_vinsn ();
5315 dwarf2_where (&orig_insn
.loc
);
5317 xg_add_branch_and_loop_targets (&orig_insn
);
5319 /* Special-case for "entry" instruction. */
5320 if (orig_insn
.opcode
== xtensa_entry_opcode
)
5322 /* Check that the third opcode (#2) is >= 16. */
5323 if (orig_insn
.ntok
>= 3)
5325 expressionS
*exp
= &orig_insn
.tok
[2];
5329 if (exp
->X_add_number
< 16)
5330 as_warn (_("entry instruction with stack decrement < 16"));
5334 as_warn (_("entry instruction with non-constant decrement"));
5340 assemble_tokens (opcode, tok, ntok);
5341 expand the tokens from the orig_insn into the
5342 stack of instructions that will not expand
5343 unless required at relaxation time. */
5345 if (!cur_vinsn
.inside_bundle
)
5346 emit_single_op (&orig_insn
);
5347 else /* We are inside a bundle. */
5349 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5350 cur_vinsn
.num_slots
++;
5351 if (*input_line_pointer
== '}'
5352 || *(input_line_pointer
- 1) == '}'
5353 || *(input_line_pointer
- 2) == '}')
5354 finish_vinsn (&cur_vinsn
);
5357 /* We've just emitted a new instruction so clear the list of labels. */
5358 xtensa_clear_insn_labels ();
5362 /* HANDLE_ALIGN hook */
5364 /* For a .align directive, we mark the previous block with the alignment
5365 information. This will be placed in the object file in the
5366 property section corresponding to this section. */
5369 xtensa_handle_align (fragS
*fragP
)
5372 && ! fragP
->tc_frag_data
.is_literal
5373 && (fragP
->fr_type
== rs_align
5374 || fragP
->fr_type
== rs_align_code
)
5375 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5376 && fragP
->fr_offset
> 0
5377 && now_seg
!= bss_section
)
5379 fragP
->tc_frag_data
.is_align
= TRUE
;
5380 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5383 if (fragP
->fr_type
== rs_align_test
)
5386 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5388 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5389 _("unaligned entry instruction"));
5394 /* TC_FRAG_INIT hook */
5397 xtensa_frag_init (fragS
*frag
)
5399 xtensa_set_frag_assembly_state (frag
);
5404 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5410 /* Round up a section size to the appropriate boundary. */
5413 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5415 return size
; /* Byte alignment is fine. */
5420 md_pcrel_from (fixS
*fixP
)
5423 static xtensa_insnbuf insnbuf
= NULL
;
5424 static xtensa_insnbuf slotbuf
= NULL
;
5427 xtensa_opcode opcode
;
5430 xtensa_isa isa
= xtensa_default_isa
;
5431 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5432 bfd_boolean alt_reloc
;
5434 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5439 insnbuf
= xtensa_insnbuf_alloc (isa
);
5440 slotbuf
= xtensa_insnbuf_alloc (isa
);
5443 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5444 xtensa_insnbuf_from_chars (isa
, insnbuf
, insn_p
, 0);
5445 fmt
= xtensa_format_decode (isa
, insnbuf
);
5447 if (fmt
== XTENSA_UNDEFINED
)
5448 as_fatal (_("bad instruction format"));
5450 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5451 as_fatal (_("invalid relocation"));
5453 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5454 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5456 /* Check for "alternate" relocations (operand not specified). None
5457 of the current uses for these are really PC-relative. */
5458 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5460 if (opcode
!= xtensa_l32r_opcode
5461 && opcode
!= xtensa_const16_opcode
)
5462 as_fatal (_("invalid relocation for '%s' instruction"),
5463 xtensa_opcode_name (isa
, opcode
));
5467 opnum
= get_relaxable_immed (opcode
);
5469 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5470 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5472 as_bad_where (fixP
->fx_file
,
5474 _("invalid relocation for operand %d of '%s'"),
5475 opnum
, xtensa_opcode_name (isa
, opcode
));
5478 return 0 - opnd_value
;
5482 /* TC_FORCE_RELOCATION hook */
5485 xtensa_force_relocation (fixS
*fix
)
5487 switch (fix
->fx_r_type
)
5489 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5490 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5491 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5492 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5493 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5494 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5495 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5496 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5497 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5498 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5499 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5500 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5501 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5502 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5503 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5504 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5510 if (linkrelax
&& fix
->fx_addsy
5511 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5514 return generic_force_reloc (fix
);
5518 /* TC_VALIDATE_FIX_SUB hook */
5521 xtensa_validate_fix_sub (fixS
*fix
)
5523 segT add_symbol_segment
, sub_symbol_segment
;
5525 /* The difference of two symbols should be resolved by the assembler when
5526 linkrelax is not set. If the linker may relax the section containing
5527 the symbols, then an Xtensa DIFF relocation must be generated so that
5528 the linker knows to adjust the difference value. */
5529 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5532 /* Make sure both symbols are in the same segment, and that segment is
5533 "normal" and relaxable. If the segment is not "normal", then the
5534 fix is not valid. If the segment is not "relaxable", then the fix
5535 should have been handled earlier. */
5536 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5537 if (! SEG_NORMAL (add_symbol_segment
) ||
5538 ! relaxable_section (add_symbol_segment
))
5540 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5541 return (sub_symbol_segment
== add_symbol_segment
);
5545 /* NO_PSEUDO_DOT hook */
5547 /* This function has nothing to do with pseudo dots, but this is the
5548 nearest macro to where the check needs to take place. FIXME: This
5552 xtensa_check_inside_bundle (void)
5554 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5555 as_bad (_("directives are not valid inside bundles"));
5557 /* This function must always return FALSE because it is called via a
5558 macro that has nothing to do with bundling. */
5563 /* md_elf_section_change_hook */
5566 xtensa_elf_section_change_hook (void)
5568 /* Set up the assembly state. */
5569 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5570 xtensa_set_frag_assembly_state (frag_now
);
5574 /* tc_fix_adjustable hook */
5577 xtensa_fix_adjustable (fixS
*fixP
)
5579 /* An offset is not allowed in combination with the difference of two
5580 symbols, but that cannot be easily detected after a local symbol
5581 has been adjusted to a (section+offset) form. Return 0 so that such
5582 an fix will not be adjusted. */
5583 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5584 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5587 /* We need the symbol name for the VTABLE entries. */
5588 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5589 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5597 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg
)
5599 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5602 switch (fixP
->fx_r_type
)
5607 if (linkrelax
&& fixP
->fx_subsy
)
5609 switch (fixP
->fx_r_type
)
5612 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5615 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5618 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5624 /* An offset is only allowed when it results from adjusting a
5625 local symbol into a section-relative offset. If the offset
5626 came from the original expression, tc_fix_adjustable will have
5627 prevented the fix from being converted to a section-relative
5628 form so that we can flag the error here. */
5629 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5631 _("cannot represent subtraction with an offset"));
5633 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5634 - S_GET_VALUE (fixP
->fx_subsy
));
5636 /* The difference value gets written out, and the DIFF reloc
5637 identifies the address of the subtracted symbol (i.e., the one
5638 with the lowest address). */
5640 fixP
->fx_offset
-= val
;
5641 fixP
->fx_subsy
= NULL
;
5643 else if (! fixP
->fx_addsy
)
5650 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5651 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5654 case BFD_RELOC_XTENSA_SLOT0_OP
:
5655 case BFD_RELOC_XTENSA_SLOT1_OP
:
5656 case BFD_RELOC_XTENSA_SLOT2_OP
:
5657 case BFD_RELOC_XTENSA_SLOT3_OP
:
5658 case BFD_RELOC_XTENSA_SLOT4_OP
:
5659 case BFD_RELOC_XTENSA_SLOT5_OP
:
5660 case BFD_RELOC_XTENSA_SLOT6_OP
:
5661 case BFD_RELOC_XTENSA_SLOT7_OP
:
5662 case BFD_RELOC_XTENSA_SLOT8_OP
:
5663 case BFD_RELOC_XTENSA_SLOT9_OP
:
5664 case BFD_RELOC_XTENSA_SLOT10_OP
:
5665 case BFD_RELOC_XTENSA_SLOT11_OP
:
5666 case BFD_RELOC_XTENSA_SLOT12_OP
:
5667 case BFD_RELOC_XTENSA_SLOT13_OP
:
5668 case BFD_RELOC_XTENSA_SLOT14_OP
:
5671 /* Write the tentative value of a PC-relative relocation to a
5672 local symbol into the instruction. The value will be ignored
5673 by the linker, and it makes the object file disassembly
5674 readable when all branch targets are encoded in relocations. */
5676 assert (fixP
->fx_addsy
);
5677 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
&& !fixP
->fx_plt
5678 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5680 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5681 - md_pcrel_from (fixP
));
5682 (void) xg_apply_fix_value (fixP
, val
);
5685 else if (! fixP
->fx_addsy
)
5688 if (xg_apply_fix_value (fixP
, val
))
5693 case BFD_RELOC_XTENSA_PLT
:
5694 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5695 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5696 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5697 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5698 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5699 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5700 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5701 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5702 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5703 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5704 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5705 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5706 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5707 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5708 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5709 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5710 /* These all need to be resolved at link-time. Do nothing now. */
5713 case BFD_RELOC_VTABLE_INHERIT
:
5714 case BFD_RELOC_VTABLE_ENTRY
:
5719 as_bad (_("unhandled local relocation fix %s"),
5720 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5726 md_atof (int type
, char *litP
, int *sizeP
)
5729 LITTLENUM_TYPE words
[4];
5745 return "bad call to md_atof";
5748 t
= atof_ieee (input_line_pointer
, type
, words
);
5750 input_line_pointer
= t
;
5754 for (i
= prec
- 1; i
>= 0; i
--)
5757 if (target_big_endian
)
5758 idx
= (prec
- 1 - i
);
5760 md_number_to_chars (litP
, (valueT
) words
[idx
], 2);
5769 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5771 return total_frag_text_expansion (fragP
);
5775 /* Translate internal representation of relocation info to BFD target
5779 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5783 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5784 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5785 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5786 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5788 /* Make sure none of our internal relocations make it this far.
5789 They'd better have been fully resolved by this point. */
5790 assert ((int) fixp
->fx_r_type
> 0);
5792 reloc
->addend
= fixp
->fx_offset
;
5794 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5795 if (reloc
->howto
== NULL
)
5797 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5798 _("cannot represent `%s' relocation in object file"),
5799 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5800 free (reloc
->sym_ptr_ptr
);
5805 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5806 as_fatal (_("internal error? cannot generate `%s' relocation"),
5807 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5813 /* Checks for resource conflicts between instructions. */
5815 /* The func unit stuff could be implemented as bit-vectors rather
5816 than the iterative approach here. If it ends up being too
5817 slow, we will switch it. */
5820 new_resource_table (void *data
,
5823 unit_num_copies_func uncf
,
5824 opcode_num_units_func onuf
,
5825 opcode_funcUnit_use_unit_func ouuf
,
5826 opcode_funcUnit_use_stage_func ousf
)
5829 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5831 rt
->cycles
= cycles
;
5832 rt
->allocated_cycles
= cycles
;
5834 rt
->unit_num_copies
= uncf
;
5835 rt
->opcode_num_units
= onuf
;
5836 rt
->opcode_unit_use
= ouuf
;
5837 rt
->opcode_unit_stage
= ousf
;
5839 rt
->units
= (char **) xcalloc (cycles
, sizeof (char *));
5840 for (i
= 0; i
< cycles
; i
++)
5841 rt
->units
[i
] = (char *) xcalloc (nu
, sizeof (char));
5848 clear_resource_table (resource_table
*rt
)
5851 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
5852 for (j
= 0; j
< rt
->num_units
; j
++)
5853 rt
->units
[i
][j
] = 0;
5857 /* We never shrink it, just fake it into thinking so. */
5860 resize_resource_table (resource_table
*rt
, int cycles
)
5864 rt
->cycles
= cycles
;
5865 if (cycles
<= rt
->allocated_cycles
)
5868 old_cycles
= rt
->allocated_cycles
;
5869 rt
->allocated_cycles
= cycles
;
5871 rt
->units
= xrealloc (rt
->units
, sizeof (char *) * rt
->allocated_cycles
);
5872 for (i
= 0; i
< old_cycles
; i
++)
5873 rt
->units
[i
] = xrealloc (rt
->units
[i
], sizeof (char) * rt
->num_units
);
5874 for (i
= old_cycles
; i
< cycles
; i
++)
5875 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (char));
5880 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5883 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5885 for (i
= 0; i
< uses
; i
++)
5887 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5888 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5889 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
5890 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
5891 if (copies_in_use
>= copies
)
5899 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5902 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5904 for (i
= 0; i
< uses
; i
++)
5906 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5907 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5908 /* Note that this allows resources to be oversubscribed. That's
5909 essential to the way the optional scheduler works.
5910 resources_available reports when a resource is over-subscribed,
5911 so it's easy to tell. */
5912 rt
->units
[stage
+ cycle
][unit
]++;
5918 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
5921 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
5923 for (i
= 0; i
< uses
; i
++)
5925 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
5926 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
5927 rt
->units
[stage
+ cycle
][unit
]--;
5928 assert (rt
->units
[stage
+ cycle
][unit
] >= 0);
5933 /* Wrapper functions make parameterized resource reservation
5937 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
5939 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5945 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
5947 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
5952 /* Note that this function does not check issue constraints, but
5953 solely whether the hardware is available to execute the given
5954 instructions together. It also doesn't check if the tinsns
5955 write the same state, or access the same tieports. That is
5956 checked by check_t1_t2_reads_and_writes. */
5959 resources_conflict (vliw_insn
*vinsn
)
5962 static resource_table
*rt
= NULL
;
5964 /* This is the most common case by far. Optimize it. */
5965 if (vinsn
->num_slots
== 1)
5970 xtensa_isa isa
= xtensa_default_isa
;
5971 rt
= new_resource_table
5972 (isa
, xtensa_isa_num_pipe_stages (isa
),
5973 xtensa_isa_num_funcUnits (isa
),
5974 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
5975 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
5976 opcode_funcUnit_use_unit
,
5977 opcode_funcUnit_use_stage
);
5980 clear_resource_table (rt
);
5982 for (i
= 0; i
< vinsn
->num_slots
; i
++)
5984 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
5986 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
5993 /* finish_vinsn, emit_single_op and helper functions. */
5995 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
5996 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
5997 static void bundle_single_op (TInsn
*);
5998 static void xg_assemble_vliw_tokens (vliw_insn
*);
6001 /* We have reached the end of a bundle; emit into the frag. */
6004 finish_vinsn (vliw_insn
*vinsn
)
6011 if (find_vinsn_conflicts (vinsn
))
6013 xg_clear_vinsn (vinsn
);
6017 /* First, find a format that works. */
6018 if (vinsn
->format
== XTENSA_UNDEFINED
)
6019 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6021 if (vinsn
->format
== XTENSA_UNDEFINED
)
6023 as_where (&file_name
, &line
);
6024 as_bad_where (file_name
, line
,
6025 _("couldn't find a valid instruction format"));
6026 fprintf (stderr
, _(" ops were: "));
6027 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6028 fprintf (stderr
, _(" %s;"),
6029 xtensa_opcode_name (xtensa_default_isa
,
6030 vinsn
->slots
[i
].opcode
));
6031 fprintf (stderr
, _("\n"));
6032 xg_clear_vinsn (vinsn
);
6036 if (vinsn
->num_slots
6037 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6039 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6040 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6041 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6043 xg_clear_vinsn (vinsn
);
6047 if (resources_conflict (vinsn
))
6049 as_where (&file_name
, &line
);
6050 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6051 fprintf (stderr
, " ops were: ");
6052 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6053 fprintf (stderr
, " %s;",
6054 xtensa_opcode_name (xtensa_default_isa
,
6055 vinsn
->slots
[i
].opcode
));
6056 fprintf (stderr
, "\n");
6057 xg_clear_vinsn (vinsn
);
6061 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6063 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6065 symbolS
*lit_sym
= NULL
;
6067 bfd_boolean e
= FALSE
;
6068 bfd_boolean saved_density
= density_supported
;
6070 /* We don't want to narrow ops inside multi-slot bundles. */
6071 if (vinsn
->num_slots
> 1)
6072 density_supported
= FALSE
;
6074 istack_init (&slotstack
);
6075 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6077 vinsn
->slots
[i
].opcode
=
6078 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6080 vinsn
->slots
[i
].ntok
= 0;
6083 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6089 density_supported
= saved_density
;
6093 xg_clear_vinsn (vinsn
);
6097 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6099 TInsn
*insn
= &slotstack
.insn
[j
];
6100 if (insn
->insn_type
== ITYPE_LITERAL
)
6102 assert (lit_sym
== NULL
);
6103 lit_sym
= xg_assemble_literal (insn
);
6107 assert (insn
->insn_type
== ITYPE_INSN
);
6109 xg_resolve_literals (insn
, lit_sym
);
6110 if (j
!= slotstack
.ninsn
- 1)
6111 emit_single_op (insn
);
6115 if (vinsn
->num_slots
> 1)
6117 if (opcode_fits_format_slot
6118 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6121 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6125 bundle_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6126 if (vinsn
->format
== XTENSA_UNDEFINED
)
6127 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6129 vinsn
->slots
[i
].opcode
6130 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6133 vinsn
->slots
[i
].ntok
= 0;
6138 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6139 vinsn
->format
= XTENSA_UNDEFINED
;
6144 /* Now check resource conflicts on the modified bundle. */
6145 if (resources_conflict (vinsn
))
6147 as_where (&file_name
, &line
);
6148 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6149 fprintf (stderr
, " ops were: ");
6150 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6151 fprintf (stderr
, " %s;",
6152 xtensa_opcode_name (xtensa_default_isa
,
6153 vinsn
->slots
[i
].opcode
));
6154 fprintf (stderr
, "\n");
6155 xg_clear_vinsn (vinsn
);
6159 /* First, find a format that works. */
6160 if (vinsn
->format
== XTENSA_UNDEFINED
)
6161 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6163 xg_assemble_vliw_tokens (vinsn
);
6165 xg_clear_vinsn (vinsn
);
6169 /* Given an vliw instruction, what conflicts are there in register
6170 usage and in writes to states and queues?
6172 This function does two things:
6173 1. Reports an error when a vinsn contains illegal combinations
6174 of writes to registers states or queues.
6175 2. Marks individual tinsns as not relaxable if the combination
6176 contains antidependencies.
6178 Job 2 handles things like swap semantics in instructions that need
6179 to be relaxed. For example,
6183 normally would be relaxed to
6188 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6190 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6192 then we can't relax it into
6195 { add a0, a1, a0 ; add a2, a0, a4 ; }
6197 because the value of a0 is trashed before the second add can read it. */
6199 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6202 find_vinsn_conflicts (vliw_insn
*vinsn
)
6206 xtensa_isa isa
= xtensa_default_isa
;
6208 assert (!past_xtensa_end
);
6210 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6212 TInsn
*op1
= &vinsn
->slots
[i
];
6213 if (op1
->is_specific_opcode
)
6214 op1
->keep_wide
= TRUE
;
6216 op1
->keep_wide
= FALSE
;
6219 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6221 TInsn
*op1
= &vinsn
->slots
[i
];
6223 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6226 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6230 TInsn
*op2
= &vinsn
->slots
[j
];
6231 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6232 switch (conflict_type
)
6235 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6236 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6237 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6240 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6241 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6242 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6245 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"),
6246 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6247 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6250 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"),
6251 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6252 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6255 /* Everything is OK. */
6258 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6259 || conflict_type
== 'a');
6266 as_bad (_("multiple branches or jumps in the same bundle"));
6274 /* Check how the state used by t1 and t2 relate.
6277 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6278 case B: no relationship between what is read and written (both could
6279 read the same reg though)
6280 case C: t1 writes a register t2 writes (a register conflict within a
6282 case D: t1 writes a state that t2 also writes
6283 case E: t1 writes a tie queue that t2 also writes
6284 case F: two volatile queue accesses
6288 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6290 xtensa_isa isa
= xtensa_default_isa
;
6291 xtensa_regfile t1_regfile
, t2_regfile
;
6293 int t1_base_reg
, t1_last_reg
;
6294 int t2_base_reg
, t2_last_reg
;
6295 char t1_inout
, t2_inout
;
6297 char conflict
= 'b';
6302 bfd_boolean t1_volatile
= FALSE
;
6303 bfd_boolean t2_volatile
= FALSE
;
6305 /* Check registers. */
6306 for (j
= 0; j
< t2
->ntok
; j
++)
6308 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6311 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6312 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6313 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6315 for (i
= 0; i
< t1
->ntok
; i
++)
6317 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6320 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6322 if (t1_regfile
!= t2_regfile
)
6325 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6326 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6328 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6329 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6331 if (t1_inout
== 'm' || t1_inout
== 'o'
6332 || t2_inout
== 'm' || t2_inout
== 'o')
6339 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6340 t1_last_reg
= (t1_base_reg
6341 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6343 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6345 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6347 if (t1_reg
!= t2_reg
)
6350 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6356 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6362 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6370 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6371 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6372 for (j
= 0; j
< t2_states
; j
++)
6374 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6375 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6376 for (i
= 0; i
< t1_states
; i
++)
6378 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6379 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6383 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6389 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6395 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6400 /* Check tieports. */
6401 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6402 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6403 for (j
= 0; j
< t2_interfaces
; j
++)
6405 xtensa_interface t2_int
6406 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6407 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6409 t2_inout
= xtensa_interface_inout (isa
, j
);
6410 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6413 for (i
= 0; i
< t1_interfaces
; i
++)
6415 xtensa_interface t1_int
6416 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6417 int t1_class
= xtensa_interface_class_id (isa
, t2_int
);
6419 t1_inout
= xtensa_interface_inout (isa
, i
);
6420 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6423 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6426 if (t1_int
!= t2_int
)
6429 if (t2_inout
== 'i' && t1_inout
== 'o')
6435 if (t1_inout
== 'i' && t2_inout
== 'o')
6441 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6450 static xtensa_format
6451 xg_find_narrowest_format (vliw_insn
*vinsn
)
6453 /* Right now we assume that the ops within the vinsn are properly
6454 ordered for the slots that the programmer wanted them in. In
6455 other words, we don't rearrange the ops in hopes of finding a
6456 better format. The scheduler handles that. */
6458 xtensa_isa isa
= xtensa_default_isa
;
6459 xtensa_format format
;
6460 vliw_insn v_copy
= *vinsn
;
6461 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6463 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6466 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6470 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6472 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6474 v_copy
.slots
[slot
].opcode
=
6475 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6476 v_copy
.slots
[slot
].ntok
= 0;
6479 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6482 else if (v_copy
.num_slots
> 1)
6485 /* Try the widened version. */
6486 if (!v_copy
.slots
[slot
].keep_wide
6487 && !v_copy
.slots
[slot
].is_specific_opcode
6488 && xg_is_narrow_insn (&v_copy
.slots
[slot
])
6489 && !xg_expand_narrow (&widened
, &v_copy
.slots
[slot
])
6490 && opcode_fits_format_slot (widened
.opcode
,
6493 /* The xg_is_narrow clause requires some explanation:
6495 addi can be "widened" to an addmi, which is then
6496 expanded to an addmi/addi pair if the immediate
6497 requires it, but here we must have a single widen
6500 xg_is_narrow tells us that addi isn't really
6501 narrow. The widen_spec_list says that there are
6504 v_copy
.slots
[slot
] = widened
;
6509 if (fit
== v_copy
.num_slots
)
6512 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6513 vinsn
->format
= format
;
6519 if (format
== xtensa_isa_num_formats (isa
))
6520 return XTENSA_UNDEFINED
;
6526 /* Return the additional space needed in a frag
6527 for possible relaxations of any ops in a VLIW insn.
6528 Also fill out the relaxations that might be required of
6529 each tinsn in the vinsn. */
6532 relaxation_requirements (vliw_insn
*vinsn
)
6534 int extra_space
= 0;
6537 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6539 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6540 if (!tinsn_has_symbolic_operands (tinsn
))
6542 /* A narrow instruction could be widened later to help
6543 alignment issues. */
6544 if (xg_is_narrow_insn (tinsn
)
6545 && !tinsn
->is_specific_opcode
6546 && vinsn
->num_slots
== 1)
6548 /* Difference in bytes between narrow and wide insns... */
6550 tinsn
->subtype
= RELAX_NARROW
;
6551 tinsn
->record_fix
= TRUE
;
6556 tinsn
->record_fix
= FALSE
;
6557 /* No extra_space needed. */
6562 if (workaround_b_j_loop_end
6563 && tinsn
->opcode
== xtensa_jx_opcode
6564 && use_transform ())
6566 /* Add 2 of these. */
6567 extra_space
+= 3; /* for the nop size */
6568 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6571 /* Need to assemble it with space for the relocation. */
6572 if (xg_is_relaxable_insn (tinsn
, 0)
6573 && !tinsn
->is_specific_opcode
)
6575 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6576 int max_literal_size
=
6577 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6579 tinsn
->literal_space
= max_literal_size
;
6581 tinsn
->subtype
= RELAX_IMMED
;
6582 tinsn
->record_fix
= FALSE
;
6583 extra_space
+= max_size
;
6587 tinsn
->record_fix
= TRUE
;
6588 /* No extra space needed. */
6597 bundle_single_op (TInsn
*orig_insn
)
6599 xtensa_isa isa
= xtensa_default_isa
;
6604 v
.format
= op_placement_table
[orig_insn
->opcode
].narrowest
;
6605 assert (v
.format
!= XTENSA_UNDEFINED
);
6606 v
.num_slots
= xtensa_format_num_slots (isa
, v
.format
);
6609 !opcode_fits_format_slot (orig_insn
->opcode
, v
.format
, slot
);
6612 v
.slots
[slot
].opcode
=
6613 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6614 v
.slots
[slot
].ntok
= 0;
6615 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6618 v
.slots
[slot
] = *orig_insn
;
6621 for ( ; slot
< v
.num_slots
; slot
++)
6623 v
.slots
[slot
].opcode
=
6624 xtensa_format_slot_nop_opcode (isa
, v
.format
, slot
);
6625 v
.slots
[slot
].ntok
= 0;
6626 v
.slots
[slot
].insn_type
= ITYPE_INSN
;
6635 emit_single_op (TInsn
*orig_insn
)
6638 IStack istack
; /* put instructions into here */
6639 symbolS
*lit_sym
= NULL
;
6640 symbolS
*label_sym
= NULL
;
6642 istack_init (&istack
);
6644 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6645 Because the scheduling and bundling characteristics of movi and
6646 l32r or const16 are so different, we can do much better if we relax
6647 it prior to scheduling and bundling, rather than after. */
6648 if ((orig_insn
->opcode
== xtensa_movi_opcode
6649 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6650 && !cur_vinsn
.inside_bundle
6651 && (orig_insn
->tok
[1].X_op
== O_symbol
6652 || orig_insn
->tok
[1].X_op
== O_pltrel
))
6653 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6655 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6658 for (i
= 0; i
< istack
.ninsn
; i
++)
6660 TInsn
*insn
= &istack
.insn
[i
];
6661 switch (insn
->insn_type
)
6664 assert (lit_sym
== NULL
);
6665 lit_sym
= xg_assemble_literal (insn
);
6669 static int relaxed_sym_idx
= 0;
6670 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6671 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6673 assert (label_sym
== NULL
);
6674 label_sym
= symbol_find_or_make (label
);
6681 xg_resolve_literals (insn
, lit_sym
);
6683 xg_resolve_labels (insn
, label_sym
);
6684 bundle_single_op (insn
);
6696 total_frag_text_expansion (fragS
*fragP
)
6699 int total_expansion
= 0;
6701 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6702 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6704 return total_expansion
;
6708 /* Emit a vliw instruction to the current fragment. */
6711 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6713 bfd_boolean finish_frag
= FALSE
;
6714 bfd_boolean is_jump
= FALSE
;
6715 bfd_boolean is_branch
= FALSE
;
6716 xtensa_isa isa
= xtensa_default_isa
;
6722 struct dwarf2_line_info best_loc
;
6724 best_loc
.line
= INT_MAX
;
6726 if (generating_literals
)
6728 static int reported
= 0;
6730 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6731 _("cannot assemble into a literal fragment"));
6738 if (frag_now_fix () != 0
6739 && (! frag_now
->tc_frag_data
.is_insn
6740 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6741 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6742 || (directive_state
[directive_longcalls
]
6743 != frag_now
->tc_frag_data
.use_longcalls
)
6744 || (directive_state
[directive_absolute_literals
]
6745 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6747 frag_wane (frag_now
);
6749 xtensa_set_frag_assembly_state (frag_now
);
6752 if (workaround_a0_b_retw
6753 && vinsn
->num_slots
== 1
6754 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6755 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6756 && use_transform ())
6758 has_a0_b_retw
= TRUE
;
6760 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6761 After the first assembly pass we will check all of them and
6762 add a nop if needed. */
6763 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6764 frag_var (rs_machine_dependent
, 4, 4,
6765 RELAX_ADD_NOP_IF_A0_B_RETW
,
6766 frag_now
->fr_symbol
,
6767 frag_now
->fr_offset
,
6769 xtensa_set_frag_assembly_state (frag_now
);
6770 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6771 frag_var (rs_machine_dependent
, 4, 4,
6772 RELAX_ADD_NOP_IF_A0_B_RETW
,
6773 frag_now
->fr_symbol
,
6774 frag_now
->fr_offset
,
6776 xtensa_set_frag_assembly_state (frag_now
);
6779 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6781 /* See if the instruction implies an aligned section. */
6782 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[i
].opcode
) == 1)
6783 record_alignment (now_seg
, 2);
6785 /* Also determine the best line number for debug info. */
6786 best_loc
= vinsn
->slots
[i
].loc
.line
< best_loc
.line
6787 ? vinsn
->slots
[i
].loc
: best_loc
;
6790 /* Special cases for instructions that force an alignment... */
6791 /* None of these opcodes are bundle-able. */
6792 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6796 xtensa_set_frag_assembly_state (frag_now
);
6797 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6799 max_fill
= get_text_align_max_fill_size
6800 (get_text_align_power (xtensa_fetch_width
),
6801 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6803 if (use_transform ())
6804 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6805 RELAX_ALIGN_NEXT_OPCODE
,
6806 frag_now
->fr_symbol
,
6807 frag_now
->fr_offset
,
6810 frag_var (rs_machine_dependent
, 0, 0,
6811 RELAX_CHECK_ALIGN_NEXT_OPCODE
, 0, 0, NULL
);
6812 xtensa_set_frag_assembly_state (frag_now
);
6814 xtensa_move_labels (frag_now
, 0, FALSE
);
6817 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6818 && !vinsn
->slots
[0].is_specific_opcode
)
6820 xtensa_mark_literal_pool_location ();
6821 xtensa_move_labels (frag_now
, 0, TRUE
);
6822 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6825 if (vinsn
->num_slots
== 1)
6827 if (workaround_a0_b_retw
&& use_transform ())
6828 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6829 is_register_writer (&vinsn
->slots
[0], "a", 0));
6831 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6832 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6835 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6837 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6839 extra_space
= relaxation_requirements (vinsn
);
6841 /* vinsn_to_insnbuf will produce the error. */
6842 if (vinsn
->format
!= XTENSA_UNDEFINED
)
6844 f
= (char *) frag_more (insn_size
+ extra_space
);
6845 xtensa_set_frag_assembly_state (frag_now
);
6846 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6849 vinsn_to_insnbuf (vinsn
, f
, frag_now
, TRUE
);
6850 if (vinsn
->format
== XTENSA_UNDEFINED
)
6853 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, f
, 0);
6855 xtensa_dwarf2_emit_insn (insn_size
- extra_space
, &best_loc
);
6857 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6859 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6860 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
6861 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
6862 frag_now
->tc_frag_data
.slot_sub_symbols
[slot
] = tinsn
->sub_symbol
;
6863 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
6864 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
6865 if (tinsn
->literal_space
!= 0)
6866 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
6868 if (tinsn
->subtype
== RELAX_NARROW
)
6869 assert (vinsn
->num_slots
== 1);
6870 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
6872 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
6875 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->record_fix
6876 || tinsn
->offset
|| tinsn
->literal_frag
|| is_jump
|| is_branch
)
6880 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6881 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
6885 frag_variant (rs_machine_dependent
,
6886 extra_space
, extra_space
, RELAX_SLOTS
,
6887 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
6888 xtensa_set_frag_assembly_state (frag_now
);
6891 /* Special cases for loops:
6892 close_loop_end should be inserted AFTER short_loop.
6893 Make sure that CLOSE loops are processed BEFORE short_loops
6894 when converting them. */
6896 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
6897 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
)
6898 && !vinsn
->slots
[0].is_specific_opcode
)
6900 if (workaround_short_loop
&& use_transform ())
6902 maybe_has_short_loop
= TRUE
;
6903 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6904 frag_var (rs_machine_dependent
, 4, 4,
6905 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6906 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6907 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6908 frag_var (rs_machine_dependent
, 4, 4,
6909 RELAX_ADD_NOP_IF_SHORT_LOOP
,
6910 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6913 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
6914 loop at least 12 bytes away from another loop's end. */
6915 if (workaround_close_loop_end
&& use_transform ())
6917 maybe_has_close_loop_end
= TRUE
;
6918 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6919 frag_var (rs_machine_dependent
, 12, 12,
6920 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
6921 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6925 if (use_transform ())
6929 assert (finish_frag
);
6930 frag_var (rs_machine_dependent
,
6931 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6933 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6934 xtensa_set_frag_assembly_state (frag_now
);
6936 else if (is_branch
&& do_align_targets ())
6938 assert (finish_frag
);
6939 frag_var (rs_machine_dependent
,
6940 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
6941 RELAX_MAYBE_UNREACHABLE
,
6942 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6943 xtensa_set_frag_assembly_state (frag_now
);
6944 frag_var (rs_machine_dependent
,
6946 RELAX_MAYBE_DESIRE_ALIGN
,
6947 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6948 xtensa_set_frag_assembly_state (frag_now
);
6952 /* Now, if the original opcode was a call... */
6953 if (do_align_targets ()
6954 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
6956 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
6957 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6958 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
6959 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
6960 xtensa_set_frag_assembly_state (frag_now
);
6963 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6965 frag_wane (frag_now
);
6967 xtensa_set_frag_assembly_state (frag_now
);
6972 /* xtensa_end and helper functions. */
6974 static void xtensa_cleanup_align_frags (void);
6975 static void xtensa_fix_target_frags (void);
6976 static void xtensa_mark_narrow_branches (void);
6977 static void xtensa_mark_zcl_first_insns (void);
6978 static void xtensa_fix_a0_b_retw_frags (void);
6979 static void xtensa_fix_b_j_loop_end_frags (void);
6980 static void xtensa_fix_close_loop_end_frags (void);
6981 static void xtensa_fix_short_loop_frags (void);
6982 static void xtensa_sanity_check (void);
6987 directive_balance ();
6988 xtensa_flush_pending_output ();
6990 past_xtensa_end
= TRUE
;
6992 xtensa_move_literals ();
6994 xtensa_reorder_segments ();
6995 xtensa_cleanup_align_frags ();
6996 xtensa_fix_target_frags ();
6997 if (workaround_a0_b_retw
&& has_a0_b_retw
)
6998 xtensa_fix_a0_b_retw_frags ();
6999 if (workaround_b_j_loop_end
)
7000 xtensa_fix_b_j_loop_end_frags ();
7002 /* "close_loop_end" should be processed BEFORE "short_loop". */
7003 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7004 xtensa_fix_close_loop_end_frags ();
7006 if (workaround_short_loop
&& maybe_has_short_loop
)
7007 xtensa_fix_short_loop_frags ();
7008 xtensa_mark_narrow_branches ();
7009 xtensa_mark_zcl_first_insns ();
7011 xtensa_sanity_check ();
7016 xtensa_cleanup_align_frags (void)
7020 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7023 /* Walk over all of the fragments in a subsection. */
7024 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7026 if ((fragP
->fr_type
== rs_align
7027 || fragP
->fr_type
== rs_align_code
7028 || (fragP
->fr_type
== rs_machine_dependent
7029 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7030 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7031 && fragP
->fr_fix
== 0)
7033 fragS
*next
= fragP
->fr_next
;
7036 && next
->fr_fix
== 0
7037 && next
->fr_type
== rs_machine_dependent
7038 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7041 next
= next
->fr_next
;
7044 /* If we don't widen branch targets, then they
7045 will be easier to align. */
7046 if (fragP
->tc_frag_data
.is_branch_target
7047 && fragP
->fr_opcode
== fragP
->fr_literal
7048 && fragP
->fr_type
== rs_machine_dependent
7049 && fragP
->fr_subtype
== RELAX_SLOTS
7050 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7052 if (fragP
->fr_type
== rs_machine_dependent
7053 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7054 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7060 /* Re-process all of the fragments looking to convert all of the
7061 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7062 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7063 Otherwise, convert to a .fill 0. */
7066 xtensa_fix_target_frags (void)
7070 /* When this routine is called, all of the subsections are still intact
7071 so we walk over subsections instead of sections. */
7072 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7076 /* Walk over all of the fragments in a subsection. */
7077 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7079 if (fragP
->fr_type
== rs_machine_dependent
7080 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7082 if (next_frag_is_branch_target (fragP
))
7083 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7092 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7095 xtensa_mark_narrow_branches (void)
7099 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7102 /* Walk over all of the fragments in a subsection. */
7103 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7105 if (fragP
->fr_type
== rs_machine_dependent
7106 && fragP
->fr_subtype
== RELAX_SLOTS
7107 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7110 const expressionS
*expr
;
7113 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7114 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7116 expr
= &vinsn
.slots
[0].tok
[1];
7117 symbolP
= expr
->X_add_symbol
;
7119 if (vinsn
.num_slots
== 1
7120 && xtensa_opcode_is_branch (xtensa_default_isa
,
7121 vinsn
.slots
[0].opcode
)
7122 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7123 && is_narrow_branch_guaranteed_in_range (fragP
,
7126 fragP
->fr_subtype
= RELAX_SLOTS
;
7127 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7135 /* A branch is typically widened only when its target is out of
7136 range. However, we would like to widen them to align a subsequent
7137 branch target when possible.
7139 Because the branch relaxation code is so convoluted, the optimal solution
7140 (combining the two cases) is difficult to get right in all circumstances.
7141 We therefore go with an "almost as good" solution, where we only
7142 use for alignment narrow branches that definitely will not expand to a
7143 jump and a branch. These functions find and mark these cases. */
7145 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7146 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7147 We start counting beginning with the frag after the 2-byte branch, so the
7148 maximum offset is (4 - 2) + 63 = 65. */
7149 #define MAX_IMMED6 65
7151 static size_t unrelaxed_frag_max_size (fragS
*);
7154 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7156 const expressionS
*expr
= &tinsn
->tok
[1];
7157 symbolS
*symbolP
= expr
->X_add_symbol
;
7158 fragS
*target_frag
= symbol_get_frag (symbolP
);
7159 size_t max_distance
= expr
->X_add_number
;
7160 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7161 if (is_branch_jmp_to_next (tinsn
, fragP
))
7164 /* The branch doesn't branch over it's own frag,
7165 but over the subsequent ones. */
7166 fragP
= fragP
->fr_next
;
7167 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7169 max_distance
+= unrelaxed_frag_max_size (fragP
);
7170 fragP
= fragP
->fr_next
;
7172 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7179 xtensa_mark_zcl_first_insns (void)
7183 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7186 /* Walk over all of the fragments in a subsection. */
7187 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7189 if (fragP
->fr_type
== rs_machine_dependent
7190 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7191 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7193 /* Find the loop frag. */
7194 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7195 /* Find the first insn frag. */
7196 targ_frag
= next_non_empty_frag (targ_frag
);
7198 /* Of course, sometimes (mostly for toy test cases) a
7199 zero-cost loop instruction is the last in a section. */
7202 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7203 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7212 /* Re-process all of the fragments looking to convert all of the
7213 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7214 conditional branch or a retw/retw.n, convert this frag to one that
7215 will generate a NOP. In any case close it off with a .fill 0. */
7217 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7220 xtensa_fix_a0_b_retw_frags (void)
7224 /* When this routine is called, all of the subsections are still intact
7225 so we walk over subsections instead of sections. */
7226 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7230 /* Walk over all of the fragments in a subsection. */
7231 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7233 if (fragP
->fr_type
== rs_machine_dependent
7234 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7236 if (next_instrs_are_b_retw (fragP
))
7238 if (fragP
->tc_frag_data
.is_no_transform
)
7239 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7241 relax_frag_add_nop (fragP
);
7251 next_instrs_are_b_retw (fragS
*fragP
)
7253 xtensa_opcode opcode
;
7255 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7256 static xtensa_insnbuf insnbuf
= NULL
;
7257 static xtensa_insnbuf slotbuf
= NULL
;
7258 xtensa_isa isa
= xtensa_default_isa
;
7261 bfd_boolean branch_seen
= FALSE
;
7265 insnbuf
= xtensa_insnbuf_alloc (isa
);
7266 slotbuf
= xtensa_insnbuf_alloc (isa
);
7269 if (next_fragP
== NULL
)
7272 /* Check for the conditional branch. */
7273 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7274 fmt
= xtensa_format_decode (isa
, insnbuf
);
7275 if (fmt
== XTENSA_UNDEFINED
)
7278 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7280 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7281 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7283 branch_seen
= (branch_seen
7284 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7290 offset
+= xtensa_format_length (isa
, fmt
);
7291 if (offset
== next_fragP
->fr_fix
)
7293 next_fragP
= next_non_empty_frag (next_fragP
);
7297 if (next_fragP
== NULL
)
7300 /* Check for the retw/retw.n. */
7301 xtensa_insnbuf_from_chars (isa
, insnbuf
, &next_fragP
->fr_literal
[offset
], 0);
7302 fmt
= xtensa_format_decode (isa
, insnbuf
);
7304 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7305 have no problems. */
7306 if (fmt
== XTENSA_UNDEFINED
7307 || xtensa_format_num_slots (isa
, fmt
) != 1)
7310 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7311 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7313 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7320 /* Re-process all of the fragments looking to convert all of the
7321 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7322 loop end label, convert this frag to one that will generate a NOP.
7323 In any case close it off with a .fill 0. */
7325 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7328 xtensa_fix_b_j_loop_end_frags (void)
7332 /* When this routine is called, all of the subsections are still intact
7333 so we walk over subsections instead of sections. */
7334 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7338 /* Walk over all of the fragments in a subsection. */
7339 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7341 if (fragP
->fr_type
== rs_machine_dependent
7342 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7344 if (next_instr_is_loop_end (fragP
))
7346 if (fragP
->tc_frag_data
.is_no_transform
)
7347 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7349 relax_frag_add_nop (fragP
);
7359 next_instr_is_loop_end (fragS
*fragP
)
7361 const fragS
*next_fragP
;
7363 if (next_frag_is_loop_target (fragP
))
7366 next_fragP
= next_non_empty_frag (fragP
);
7367 if (next_fragP
== NULL
)
7370 if (!next_frag_is_loop_target (next_fragP
))
7373 /* If the size is >= 3 then there is more than one instruction here.
7374 The hardware bug will not fire. */
7375 if (next_fragP
->fr_fix
> 3)
7382 /* Re-process all of the fragments looking to convert all of the
7383 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7384 not MY loop's loop end within 12 bytes, add enough nops here to
7385 make it at least 12 bytes away. In any case close it off with a
7388 static size_t min_bytes_to_other_loop_end (fragS
*, fragS
*, offsetT
, size_t);
7391 xtensa_fix_close_loop_end_frags (void)
7395 /* When this routine is called, all of the subsections are still intact
7396 so we walk over subsections instead of sections. */
7397 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7401 fragS
*current_target
= NULL
;
7402 offsetT current_offset
= 0;
7404 /* Walk over all of the fragments in a subsection. */
7405 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7407 if (fragP
->fr_type
== rs_machine_dependent
7408 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7409 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7410 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7413 /* Read it. If the instruction is a loop, get the target. */
7415 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7416 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7417 t_insn
.opcode
) == 1)
7419 /* Get the current fragment target. */
7420 if (fragP
->tc_frag_data
.slot_symbols
[0])
7422 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7423 current_target
= symbol_get_frag (sym
);
7424 current_offset
= fragP
->fr_offset
;
7430 && fragP
->fr_type
== rs_machine_dependent
7431 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7434 size_t bytes_added
= 0;
7436 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7437 /* Max out at 12. */
7438 min_bytes
= min_bytes_to_other_loop_end
7439 (fragP
->fr_next
, current_target
, current_offset
,
7440 REQUIRED_LOOP_DIVIDING_BYTES
);
7442 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7444 if (fragP
->tc_frag_data
.is_no_transform
)
7445 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7448 while (min_bytes
+ bytes_added
7449 < REQUIRED_LOOP_DIVIDING_BYTES
)
7453 if (fragP
->fr_var
< length
)
7454 as_fatal (_("fr_var %lu < length %d"),
7455 fragP
->fr_var
, length
);
7458 assemble_nop (length
,
7459 fragP
->fr_literal
+ fragP
->fr_fix
);
7460 fragP
->fr_fix
+= length
;
7461 fragP
->fr_var
-= length
;
7463 bytes_added
+= length
;
7469 assert (fragP
->fr_type
!= rs_machine_dependent
7470 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7476 static size_t unrelaxed_frag_min_size (fragS
*);
7479 min_bytes_to_other_loop_end (fragS
*fragP
,
7480 fragS
*current_target
,
7481 offsetT current_offset
,
7485 fragS
*current_fragP
;
7487 for (current_fragP
= fragP
;
7489 current_fragP
= current_fragP
->fr_next
)
7491 if (current_fragP
->tc_frag_data
.is_loop_target
7492 && current_fragP
!= current_target
)
7493 return offset
+ current_offset
;
7495 offset
+= unrelaxed_frag_min_size (current_fragP
);
7497 if (offset
+ current_offset
>= max_size
)
7505 unrelaxed_frag_min_size (fragS
*fragP
)
7507 size_t size
= fragP
->fr_fix
;
7510 if (fragP
->fr_type
== rs_fill
)
7511 size
+= fragP
->fr_offset
;
7518 unrelaxed_frag_max_size (fragS
*fragP
)
7520 size_t size
= fragP
->fr_fix
;
7521 switch (fragP
->fr_type
)
7524 /* Empty frags created by the obstack allocation scheme
7525 end up with type 0. */
7530 size
+= fragP
->fr_offset
;
7538 /* No further adjustments needed. */
7540 case rs_machine_dependent
:
7541 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7542 size
+= fragP
->fr_var
;
7545 /* We had darn well better know how big it is. */
7554 /* Re-process all of the fragments looking to convert all
7555 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7558 1) the instruction size count to the loop end label
7559 is too short (<= 2 instructions),
7560 2) loop has a jump or branch in it
7563 1) workaround_all_short_loops is TRUE
7564 2) The generating loop was a 'loopgtz' or 'loopnez'
7565 3) the instruction size count to the loop end label is too short
7567 then convert this frag (and maybe the next one) to generate a NOP.
7568 In any case close it off with a .fill 0. */
7570 static size_t count_insns_to_loop_end (fragS
*, bfd_boolean
, size_t);
7571 static bfd_boolean
branch_before_loop_end (fragS
*);
7574 xtensa_fix_short_loop_frags (void)
7578 /* When this routine is called, all of the subsections are still intact
7579 so we walk over subsections instead of sections. */
7580 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7583 fragS
*current_target
= NULL
;
7584 offsetT current_offset
= 0;
7585 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7587 /* Walk over all of the fragments in a subsection. */
7588 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7590 /* Check on the current loop. */
7591 if (fragP
->fr_type
== rs_machine_dependent
7592 && ((fragP
->fr_subtype
== RELAX_IMMED
)
7593 || ((fragP
->fr_subtype
== RELAX_SLOTS
)
7594 && (fragP
->tc_frag_data
.slot_subtypes
[0]
7599 /* Read it. If the instruction is a loop, get the target. */
7600 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7601 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7602 t_insn
.opcode
) == 1)
7604 /* Get the current fragment target. */
7605 if (fragP
->tc_frag_data
.slot_symbols
[0])
7607 symbolS
*sym
= fragP
->tc_frag_data
.slot_symbols
[0];
7608 current_target
= symbol_get_frag (sym
);
7609 current_offset
= fragP
->fr_offset
;
7610 current_opcode
= t_insn
.opcode
;
7615 if (fragP
->fr_type
== rs_machine_dependent
7616 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7619 count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3);
7621 && (branch_before_loop_end (fragP
->fr_next
)
7622 || (workaround_all_short_loops
7623 && current_opcode
!= XTENSA_UNDEFINED
7624 && current_opcode
!= xtensa_loop_opcode
)))
7626 if (fragP
->tc_frag_data
.is_no_transform
)
7627 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7629 relax_frag_add_nop (fragP
);
7638 static size_t unrelaxed_frag_min_insn_count (fragS
*);
7641 count_insns_to_loop_end (fragS
*base_fragP
,
7642 bfd_boolean count_relax_add
,
7645 fragS
*fragP
= NULL
;
7646 size_t insn_count
= 0;
7650 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7652 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7653 if (insn_count
>= max_count
)
7656 if (count_relax_add
)
7658 if (fragP
->fr_type
== rs_machine_dependent
7659 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7661 /* In order to add the appropriate number of
7662 NOPs, we count an instruction for downstream
7665 if (insn_count
>= max_count
)
7675 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7677 xtensa_isa isa
= xtensa_default_isa
;
7678 static xtensa_insnbuf insnbuf
= NULL
;
7679 size_t insn_count
= 0;
7682 if (!fragP
->tc_frag_data
.is_insn
)
7686 insnbuf
= xtensa_insnbuf_alloc (isa
);
7688 /* Decode the fixed instructions. */
7689 while (offset
< fragP
->fr_fix
)
7693 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7694 fmt
= xtensa_format_decode (isa
, insnbuf
);
7696 if (fmt
== XTENSA_UNDEFINED
)
7698 as_fatal (_("undecodable instruction in instruction frag"));
7701 offset
+= xtensa_format_length (isa
, fmt
);
7709 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7712 branch_before_loop_end (fragS
*base_fragP
)
7716 for (fragP
= base_fragP
;
7717 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7718 fragP
= fragP
->fr_next
)
7720 if (unrelaxed_frag_has_b_j (fragP
))
7728 unrelaxed_frag_has_b_j (fragS
*fragP
)
7730 static xtensa_insnbuf insnbuf
= NULL
;
7731 xtensa_isa isa
= xtensa_default_isa
;
7734 if (!fragP
->tc_frag_data
.is_insn
)
7738 insnbuf
= xtensa_insnbuf_alloc (isa
);
7740 /* Decode the fixed instructions. */
7741 while (offset
< fragP
->fr_fix
)
7746 xtensa_insnbuf_from_chars (isa
, insnbuf
, fragP
->fr_literal
+ offset
, 0);
7747 fmt
= xtensa_format_decode (isa
, insnbuf
);
7748 if (fmt
== XTENSA_UNDEFINED
)
7751 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7753 xtensa_opcode opcode
=
7754 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7755 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7756 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7759 offset
+= xtensa_format_length (isa
, fmt
);
7765 /* Checks to be made after initial assembly but before relaxation. */
7767 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7768 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7771 xtensa_sanity_check (void)
7778 as_where (&file_name
, &line
);
7779 for (frchP
= frchain_root
; frchP
; frchP
= frchP
->frch_next
)
7783 /* Walk over all of the fragments in a subsection. */
7784 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7786 /* Currently we only check for empty loops here. */
7787 if (fragP
->fr_type
== rs_machine_dependent
7788 && fragP
->fr_subtype
== RELAX_IMMED
)
7790 static xtensa_insnbuf insnbuf
= NULL
;
7793 if (fragP
->fr_opcode
!= NULL
)
7796 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7797 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
7798 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
7800 if (xtensa_opcode_is_loop (xtensa_default_isa
,
7801 t_insn
.opcode
) == 1)
7803 if (is_empty_loop (&t_insn
, fragP
))
7805 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7806 as_bad (_("invalid empty loop"));
7808 if (!is_local_forward_loop (&t_insn
, fragP
))
7810 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
7811 as_bad (_("loop target does not follow "
7812 "loop instruction in section"));
7819 new_logical_line (file_name
, line
);
7823 #define LOOP_IMMED_OPN 1
7825 /* Return TRUE if the loop target is the next non-zero fragment. */
7828 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
7830 const expressionS
*expr
;
7834 if (insn
->insn_type
!= ITYPE_INSN
)
7837 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
7840 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7843 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7845 if (expr
->X_op
!= O_symbol
)
7848 symbolP
= expr
->X_add_symbol
;
7852 if (symbol_get_frag (symbolP
) == NULL
)
7855 if (S_GET_VALUE (symbolP
) != 0)
7858 /* Walk through the zero-size fragments from this one. If we find
7859 the target fragment, then this is a zero-size loop. */
7861 for (next_fragP
= fragP
->fr_next
;
7863 next_fragP
= next_fragP
->fr_next
)
7865 if (next_fragP
== symbol_get_frag (symbolP
))
7867 if (next_fragP
->fr_fix
!= 0)
7875 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
7877 const expressionS
*expr
;
7881 if (insn
->insn_type
!= ITYPE_INSN
)
7884 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) == 0)
7887 if (insn
->ntok
<= LOOP_IMMED_OPN
)
7890 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
7892 if (expr
->X_op
!= O_symbol
)
7895 symbolP
= expr
->X_add_symbol
;
7899 if (symbol_get_frag (symbolP
) == NULL
)
7902 /* Walk through fragments until we find the target.
7903 If we do not find the target, then this is an invalid loop. */
7905 for (next_fragP
= fragP
->fr_next
;
7907 next_fragP
= next_fragP
->fr_next
)
7909 if (next_fragP
== symbol_get_frag (symbolP
))
7917 /* Alignment Functions. */
7920 get_text_align_power (int target_size
)
7923 for (i
= 0; i
< sizeof (size_t); i
++)
7925 if (target_size
<= (1 << i
))
7934 get_text_align_max_fill_size (int align_pow
,
7935 bfd_boolean use_nops
,
7936 bfd_boolean use_no_density
)
7939 return (1 << align_pow
);
7941 return 3 * (1 << align_pow
);
7943 return 1 + (1 << align_pow
);
7947 /* get_text_align_fill_size ()
7951 target_size = size of next instruction
7952 align_pow = get_text_align_power (target_size).
7956 address = current address + loop instruction size;
7957 target_size = 3 (for 2 or 3 byte target)
7958 = 4 (for 4 byte target)
7959 = 8 (for 8 byte target)
7960 align_pow = get_text_align_power (target_size);
7962 use_no_density = set appropriately
7964 address = current address + loop instruction size;
7966 align_pow = get_text_align_power (target_size);
7968 use_no_density = 0. */
7971 get_text_align_fill_size (addressT address
,
7974 bfd_boolean use_nops
,
7975 bfd_boolean use_no_density
)
7979 align_pow: log2 (required alignment).
7981 target_size: alignment must allow the new_address and
7982 new_address+target_size-1.
7984 use_nops: if TRUE, then we can only use 2- or 3-byte nops.
7986 use_no_density: if use_nops and use_no_density, we can only use
7989 Usually the align_pow is the power of 2 that is greater than
7990 or equal to the target_size. This handles the 2-byte, 3-byte
7991 and 8-byte instructions.
7995 (1) aligning an instruction properly, but without using NOPs.
7996 E.G.: a 3-byte instruction can go on any address where address mod 4
7997 is zero or one. The aligner uses this case to find the optimal
7998 number of fill bytes for relax_frag_for_align.
8000 (2) aligning an instruction properly, but where we might need to use
8001 extra NOPs. E.G.: when the aligner couldn't find enough widenings
8002 or similar to get the optimal location. */
8004 size_t alignment
= (1 << align_pow
);
8006 assert (target_size
!= 0);
8010 unsigned fill_bytes
;
8011 for (fill_bytes
= 0; fill_bytes
< alignment
; fill_bytes
++)
8013 addressT end_address
= address
+ target_size
- 1 + fill_bytes
;
8014 addressT start_address
= address
+ fill_bytes
;
8015 if ((end_address
>> align_pow
) == (start_address
>> align_pow
))
8021 /* This is the slightly harder case. */
8022 assert ((int) alignment
>= target_size
);
8023 assert (target_size
> 0);
8024 if (!use_no_density
)
8027 for (i
= 0; i
< alignment
* 2; i
++)
8031 if ((address
+ i
) >> align_pow
8032 == (address
+ i
+ target_size
- 1) >> align_pow
)
8040 /* Can only fill multiples of 3. */
8041 for (i
= 0; i
<= alignment
* 3; i
+= 3)
8043 if ((address
+ i
) >> align_pow
8044 == (address
+ i
+ target_size
- 1) >> align_pow
)
8053 /* This will assert if it is not possible. */
8056 get_text_align_nop_count (size_t fill_size
, bfd_boolean use_no_density
)
8061 assert (fill_size
% 3 == 0);
8062 return (fill_size
/ 3);
8065 assert (fill_size
!= 1); /* Bad argument. */
8067 while (fill_size
> 1)
8069 size_t insn_size
= 3;
8070 if (fill_size
== 2 || fill_size
== 4)
8072 fill_size
-= insn_size
;
8075 assert (fill_size
!= 1); /* Bad algorithm. */
8081 get_text_align_nth_nop_size (size_t fill_size
,
8083 bfd_boolean use_no_density
)
8087 assert (get_text_align_nop_count (fill_size
, use_no_density
) > n
);
8092 while (fill_size
> 1)
8094 size_t insn_size
= 3;
8095 if (fill_size
== 2 || fill_size
== 4)
8097 fill_size
-= insn_size
;
8107 /* For the given fragment, find the appropriate address
8108 for it to begin at if we are using NOPs to align it. */
8111 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8113 /* The rule is: get next fragment's FIRST instruction. Find
8114 the smallest number of bytes that need to be added to
8115 ensure that the next fragment's FIRST instruction will fit
8118 E.G., 2 bytes : 0, 1, 2 mod 4
8121 If the FIRST instruction MIGHT be relaxed,
8122 assume that it will become a 3-byte instruction.
8124 Note again here that LOOP instructions are not bundleable,
8125 and this relaxation only applies to LOOP opcodes. */
8127 size_t fill_size
= 0;
8128 int first_insn_size
;
8130 addressT pre_opcode_bytes
;
8133 xtensa_opcode opcode
;
8134 bfd_boolean is_loop
;
8136 assert (fragP
->fr_type
== rs_machine_dependent
);
8137 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8139 /* Find the loop frag. */
8140 first_insn
= next_non_empty_frag (fragP
);
8141 /* Now find the first insn frag. */
8142 first_insn
= next_non_empty_frag (first_insn
);
8144 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8146 loop_insn_size
= xg_get_single_size (opcode
);
8148 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8149 pre_opcode_bytes
+= loop_insn_size
;
8151 /* For loops, the alignment depends on the size of the
8152 instruction following the loop, not the LOOP instruction. */
8154 if (first_insn
== NULL
)
8157 assert (first_insn
->tc_frag_data
.is_first_loop_insn
);
8159 first_insn_size
= frag_format_size (first_insn
);
8161 if (first_insn_size
== 2 || first_insn_size
== XTENSA_UNDEFINED
)
8162 first_insn_size
= 3; /* ISA specifies this */
8164 /* If it was 8, then we'll need a larger alignment for the section. */
8165 alignment
= get_text_align_power (first_insn_size
);
8167 /* Is now_seg valid? */
8168 record_alignment (now_seg
, alignment
);
8170 fill_size
= get_text_align_fill_size
8171 (address
+ pre_opcode_bytes
,
8172 get_text_align_power (first_insn_size
),
8173 first_insn_size
, TRUE
, fragP
->tc_frag_data
.is_no_density
);
8175 return address
+ fill_size
;
8179 /* 3 mechanisms for relaxing an alignment:
8181 Align to a power of 2.
8182 Align so the next fragment's instruction does not cross a word boundary.
8183 Align the current instruction so that if the next instruction
8184 were 3 bytes, it would not cross a word boundary.
8188 zeros - This is easy; always insert zeros.
8189 nops - 3-byte and 2-byte instructions
8193 >=5 : 3-byte instruction + fn (n-3)
8194 widening - widen previous instructions. */
8197 get_aligned_diff (fragS
*fragP
, addressT address
, addressT
*max_diff
)
8199 addressT target_address
, loop_insn_offset
;
8201 xtensa_opcode loop_opcode
;
8202 bfd_boolean is_loop
;
8203 int text_align_power
;
8206 assert (fragP
->fr_type
== rs_machine_dependent
);
8207 switch (fragP
->fr_subtype
)
8209 case RELAX_DESIRE_ALIGN
:
8210 target_size
= next_frag_format_size (fragP
);
8211 if (target_size
== XTENSA_UNDEFINED
)
8213 text_align_power
= get_text_align_power (xtensa_fetch_width
);
8214 opt_diff
= get_text_align_fill_size (address
, text_align_power
,
8215 target_size
, FALSE
, FALSE
);
8217 *max_diff
= opt_diff
+ xtensa_fetch_width
8218 - (target_size
+ ((address
+ opt_diff
) % xtensa_fetch_width
));
8219 assert (*max_diff
>= opt_diff
);
8222 case RELAX_ALIGN_NEXT_OPCODE
:
8223 target_size
= next_frag_format_size (fragP
);
8224 loop_insn_offset
= 0;
8225 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8228 /* If the loop has been expanded then the LOOP instruction
8229 could be at an offset from this fragment. */
8230 if (next_non_empty_frag(fragP
)->tc_frag_data
.slot_subtypes
[0]
8232 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8234 if (target_size
== 2)
8235 target_size
= 3; /* ISA specifies this */
8237 /* In an ideal world, which is what we are shooting for here,
8238 we wouldn't need to use any NOPs immediately prior to the
8239 LOOP instruction. If this approach fails, relax_frag_loop_align
8240 will call get_noop_aligned_address. */
8242 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8243 text_align_power
= get_text_align_power (target_size
),
8244 opt_diff
= get_text_align_fill_size (target_address
, text_align_power
,
8245 target_size
, FALSE
, FALSE
);
8247 *max_diff
= xtensa_fetch_width
8248 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8249 - target_size
+ opt_diff
;
8250 assert (*max_diff
>= opt_diff
);
8261 /* md_relax_frag Hook and Helper Functions. */
8263 static long relax_frag_loop_align (fragS
*, long);
8264 static long relax_frag_for_align (fragS
*, long);
8265 static long relax_frag_immed
8266 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8269 /* Return the number of bytes added to this fragment, given that the
8270 input has been stretched already by "stretch". */
8273 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8275 xtensa_isa isa
= xtensa_default_isa
;
8276 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8277 long new_stretch
= 0;
8280 static xtensa_insnbuf vbuf
= NULL
;
8281 int slot
, num_slots
;
8284 as_where (&file_name
, &line
);
8285 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8287 fragP
->tc_frag_data
.unreported_expansion
= 0;
8289 switch (fragP
->fr_subtype
)
8291 case RELAX_ALIGN_NEXT_OPCODE
:
8292 /* Always convert. */
8293 if (fragP
->tc_frag_data
.relax_seen
)
8294 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8297 case RELAX_LOOP_END
:
8301 case RELAX_LOOP_END_ADD_NOP
:
8302 /* Add a NOP and switch to .fill 0. */
8303 new_stretch
= relax_frag_add_nop (fragP
);
8307 case RELAX_DESIRE_ALIGN
:
8308 /* Do nothing. The narrowing before this frag will either align
8313 case RELAX_LITERAL_FINAL
:
8316 case RELAX_LITERAL_NR
:
8318 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8319 assert (unreported
== lit_size
);
8320 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8321 fragP
->fr_var
-= lit_size
;
8322 fragP
->fr_fix
+= lit_size
;
8328 vbuf
= xtensa_insnbuf_alloc (isa
);
8330 xtensa_insnbuf_from_chars (isa
, vbuf
, fragP
->fr_opcode
, 0);
8331 fmt
= xtensa_format_decode (isa
, vbuf
);
8332 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8334 for (slot
= 0; slot
< num_slots
; slot
++)
8336 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8339 if (fragP
->tc_frag_data
.relax_seen
)
8340 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8344 case RELAX_IMMED_STEP1
:
8345 case RELAX_IMMED_STEP2
:
8346 /* Place the immediate. */
8347 new_stretch
+= relax_frag_immed
8348 (now_seg
, fragP
, stretch
,
8349 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8350 fmt
, slot
, stretched_p
, FALSE
);
8354 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8360 case RELAX_LITERAL_POOL_BEGIN
:
8361 case RELAX_LITERAL_POOL_END
:
8362 case RELAX_MAYBE_UNREACHABLE
:
8363 case RELAX_MAYBE_DESIRE_ALIGN
:
8364 /* No relaxation required. */
8367 case RELAX_FILL_NOP
:
8368 case RELAX_UNREACHABLE
:
8369 if (fragP
->tc_frag_data
.relax_seen
)
8370 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8374 as_bad (_("bad relaxation state"));
8377 /* Tell gas we need another relaxation pass. */
8378 if (! fragP
->tc_frag_data
.relax_seen
)
8380 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8384 new_logical_line (file_name
, line
);
8390 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8392 addressT old_address
, old_next_address
, old_size
;
8393 addressT new_address
, new_next_address
, new_size
;
8396 /* All the frags with relax_frag_for_alignment prior to this one in the
8397 section have been done, hopefully eliminating the need for a NOP here.
8398 But, this will put it in if necessary. */
8400 /* Calculate the old address of this fragment and the next fragment. */
8401 old_address
= fragP
->fr_address
- stretch
;
8402 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8403 fragP
->tc_frag_data
.text_expansion
[0]);
8404 old_size
= old_next_address
- old_address
;
8406 /* Calculate the new address of this fragment and the next fragment. */
8407 new_address
= fragP
->fr_address
;
8409 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8410 new_size
= new_next_address
- new_address
;
8412 growth
= new_size
- old_size
;
8414 /* Fix up the text_expansion field and return the new growth. */
8415 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8420 /* Add a NOP instruction. */
8423 relax_frag_add_nop (fragS
*fragP
)
8425 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8426 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8427 assemble_nop (length
, nop_buf
);
8428 fragP
->tc_frag_data
.is_insn
= TRUE
;
8430 if (fragP
->fr_var
< length
)
8432 as_fatal (_("fr_var (%ld) < length (%d)"), fragP
->fr_var
, length
);
8436 fragP
->fr_fix
+= length
;
8437 fragP
->fr_var
-= length
;
8442 static long future_alignment_required (fragS
*, long);
8445 relax_frag_for_align (fragS
*fragP
, long stretch
)
8447 /* Overview of the relaxation procedure for alignment:
8448 We can widen with NOPs or by widening instructions or by filling
8449 bytes after jump instructions. Find the opportune places and widen
8450 them if necessary. */
8455 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8456 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8457 || (fragP
->fr_subtype
== RELAX_SLOTS
8458 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8460 stretch_me
= future_alignment_required (fragP
, stretch
);
8461 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8467 /* We expanded on a previous pass. Can we shrink now? */
8468 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8469 if (shrink
<= stretch
&& stretch
> 0)
8471 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8477 /* Below here, diff > 0. */
8478 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8484 /* Return the address of the next frag that should be aligned.
8486 By "address" we mean the address it _would_ be at if there
8487 is no action taken to align it between here and the target frag.
8488 In other words, if no narrows and no fill nops are used between
8489 here and the frag to align, _even_if_ some of the frags we use
8490 to align targets have already expanded on a previous relaxation
8493 Also, count each frag that may be used to help align the target.
8495 Return 0 if there are no frags left in the chain that need to be
8499 find_address_of_next_align_frag (fragS
**fragPP
,
8503 bfd_boolean
*paddable
)
8505 fragS
*fragP
= *fragPP
;
8506 addressT address
= fragP
->fr_address
;
8508 /* Do not reset the counts to 0. */
8512 /* Limit this to a small search. */
8518 address
+= fragP
->fr_fix
;
8520 if (fragP
->fr_type
== rs_fill
)
8521 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8522 else if (fragP
->fr_type
== rs_machine_dependent
)
8524 switch (fragP
->fr_subtype
)
8526 case RELAX_UNREACHABLE
:
8530 case RELAX_FILL_NOP
:
8532 if (!fragP
->tc_frag_data
.is_no_density
)
8537 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8542 address
+= total_frag_text_expansion (fragP
);;
8546 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8549 case RELAX_ALIGN_NEXT_OPCODE
:
8550 case RELAX_DESIRE_ALIGN
:
8554 case RELAX_MAYBE_UNREACHABLE
:
8555 case RELAX_MAYBE_DESIRE_ALIGN
:
8560 /* Just punt if we don't know the type. */
8567 /* Just punt if we don't know the type. */
8571 fragP
= fragP
->fr_next
;
8579 static long bytes_to_stretch (fragS
*, int, int, int, int);
8581 /* Undefine LOOKAHEAD_ALIGNER to get the older behavior.
8582 I'll leave this in until I am more confident this works. */
8584 #define LOOKAHEAD_ALIGNER 1
8587 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8589 fragS
*this_frag
= fragP
;
8593 int narrow_nops
= 0;
8594 bfd_boolean paddable
= FALSE
;
8595 offsetT local_opt_diff
;
8598 int stretch_amount
= 0;
8599 int local_stretch_amount
;
8600 int global_stretch_amount
;
8602 address
= find_address_of_next_align_frag
8603 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8607 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8608 opt_diff
= local_opt_diff
;
8609 assert (opt_diff
>= 0);
8610 assert (max_diff
>= opt_diff
);
8613 #ifdef LOOKAHEAD_ALIGNER
8615 fragP
= fragP
->fr_next
;
8617 while (fragP
&& opt_diff
< max_diff
&& address
)
8619 /* We only use these to determine if we can exit early
8620 because there will be plenty of ways to align future
8622 unsigned int glob_widens
= 0;
8625 bfd_boolean glob_pad
= 0;
8626 address
= find_address_of_next_align_frag
8627 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8628 /* If there is a padable portion, then skip. */
8629 if (glob_pad
|| (glob_widens
>= xtensa_fetch_width
))
8634 offsetT next_m_diff
;
8635 offsetT next_o_diff
;
8637 /* Downrange frags haven't had stretch added to them yet. */
8640 /* The address also includes any text expansion from this
8641 frag in a previous pass, but we don't want that. */
8642 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8644 /* Assume we are going to move at least opt_diff. In
8645 reality, we might not be able to, but assuming that
8646 we will helps catch cases where moving opt_diff pushes
8647 the next target from aligned to unaligned. */
8648 address
+= opt_diff
;
8650 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8652 /* Now cleanup for the adjustments to address. */
8653 next_o_diff
+= opt_diff
;
8654 next_m_diff
+= opt_diff
;
8655 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8656 opt_diff
= next_o_diff
;
8657 if (next_m_diff
< max_diff
)
8658 max_diff
= next_m_diff
;
8659 fragP
= fragP
->fr_next
;
8662 #endif /* LOOKAHEAD_ALIGNER */
8663 /* If there are enough wideners in between, do it. */
8666 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8668 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8673 local_stretch_amount
8674 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8675 num_widens
, local_opt_diff
);
8676 #ifdef LOOKAHEAD_ALIGNER
8677 global_stretch_amount
8678 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8679 num_widens
, opt_diff
);
8680 /* If the condition below is true, then the frag couldn't
8681 stretch the correct amount for the global case, so we just
8682 optimize locally. We'll rely on the subsequent frags to get
8683 the correct alignment in the global case. */
8684 if (global_stretch_amount
< local_stretch_amount
)
8685 stretch_amount
= local_stretch_amount
;
8687 stretch_amount
= global_stretch_amount
;
8688 #else /* ! LOOKAHEAD_ALIGNER */
8689 stretch_amount
= local_stretch_amount
;
8690 #endif /* ! LOOKAHEAD_ALIGNER */
8691 if (this_frag
->fr_subtype
== RELAX_SLOTS
8692 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8693 assert (stretch_amount
<= 1);
8694 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8696 if (this_frag
->tc_frag_data
.is_no_density
)
8697 assert (stretch_amount
== 3 || stretch_amount
== 0);
8699 assert (stretch_amount
<= 3);
8702 return stretch_amount
;
8706 /* The idea: widen everything you can to get a target or loop aligned,
8707 then start using NOPs.
8709 When we must have a NOP, here is a table of how we decide
8710 (so you don't have to fight through the control flow below):
8712 wide_nops = the number of wide NOPs available for aligning
8713 narrow_nops = the number of narrow NOPs available for aligning
8714 (a subset of wide_nops)
8715 widens = the number of narrow instructions that should be widened
8722 b 0 1 1 (case 3a makes this case unnecessary)
8725 c 0 1 2 (case 4a makes this case unnecessary)
8728 c 0 2 1 (case 5b makes this case unnecessary)
8731 c 0 1 4 (case 6b makes this case unneccesary)
8732 d 1 1 1 (case 6a makes this case unnecessary)
8733 e 0 2 2 (case 6a makes this case unnecessary)
8734 f 0 3 0 (case 6a makes this case unnecessary)
8737 c 1 1 2 (case 7b makes this case unnecessary)
8738 d 0 1 5 (case 7a makes this case unnecessary)
8739 e 0 2 3 (case 7b makes this case unnecessary)
8740 f 0 3 1 (case 7b makes this case unnecessary)
8741 g 1 2 1 (case 7b makes this case unnecessary)
8745 bytes_to_stretch (fragS
*this_frag
,
8751 int bytes_short
= desired_diff
- num_widens
;
8753 assert (desired_diff
>= 0 && desired_diff
< 8);
8754 if (desired_diff
== 0)
8757 assert (wide_nops
> 0 || num_widens
> 0);
8759 /* Always prefer widening to NOP-filling. */
8760 if (bytes_short
< 0)
8762 /* There are enough RELAX_NARROW frags after this one
8763 to align the target without widening this frag in any way. */
8767 if (bytes_short
== 0)
8769 /* Widen every narrow between here and the align target
8770 and the align target will be properly aligned. */
8771 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8777 /* From here we will need at least one NOP to get an alignment.
8778 However, we may not be able to align at all, in which case,
8780 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8782 switch (desired_diff
)
8787 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
8788 return 2; /* case 2 */
8794 return 3; /* case 3a */
8796 if (num_widens
>= 1 && wide_nops
== 1)
8797 return 3; /* case 4a */
8798 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
8799 return 2; /* case 4b */
8802 if (num_widens
>= 2 && wide_nops
== 1)
8803 return 3; /* case 5a */
8804 /* We will need two nops. Are there enough nops
8805 between here and the align target? */
8806 if (wide_nops
< 2 || narrow_nops
== 0)
8808 /* Are there other nops closer that can serve instead? */
8809 if (wide_nops
> 2 && narrow_nops
> 1)
8811 /* Take the density one first, because there might not be
8812 another density one available. */
8813 if (!this_frag
->tc_frag_data
.is_no_density
)
8814 return 2; /* case 5b narrow */
8816 return 3; /* case 5b wide */
8820 return 3; /* case 6a */
8821 else if (num_widens
>= 3 && wide_nops
== 1)
8822 return 3; /* case 6b */
8825 if (wide_nops
== 1 && num_widens
>= 4)
8826 return 3; /* case 7a */
8827 else if (wide_nops
== 2 && num_widens
>= 1)
8828 return 3; /* case 7b */
8836 /* We will need a NOP no matter what, but should we widen
8837 this instruction to help?
8839 This is a RELAX_FRAG_NARROW frag. */
8840 switch (desired_diff
)
8849 if (wide_nops
>= 1 && num_widens
== 1)
8850 return 1; /* case 4a */
8853 if (wide_nops
>= 1 && num_widens
== 2)
8854 return 1; /* case 5a */
8858 return 0; /* case 6a */
8859 else if (wide_nops
>= 1 && num_widens
== 3)
8860 return 1; /* case 6b */
8863 if (wide_nops
>= 1 && num_widens
== 4)
8864 return 1; /* case 7a */
8865 else if (wide_nops
>= 2 && num_widens
== 1)
8866 return 1; /* case 7b */
8879 relax_frag_immed (segT segP
,
8886 bfd_boolean estimate_only
)
8889 vliw_insn orig_vinsn
;
8891 bfd_boolean negatable_branch
= FALSE
;
8892 bfd_boolean branch_jmp_to_next
= FALSE
;
8893 bfd_boolean wide_insn
= FALSE
;
8894 xtensa_isa isa
= xtensa_default_isa
;
8896 offsetT frag_offset
;
8899 int num_text_bytes
, num_literal_bytes
;
8900 int literal_diff
, total_text_diff
, this_text_diff
, first
;
8902 assert (fragP
->fr_opcode
!= NULL
);
8904 xg_init_vinsn (&orig_vinsn
);
8905 vinsn_from_chars (&orig_vinsn
, fragP
->fr_opcode
);
8906 if (xtensa_format_num_slots (isa
, fmt
) > 1)
8909 tinsn
= orig_vinsn
.slots
[slot
];
8910 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
8912 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
))
8915 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
8916 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
8918 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
8920 old_size
= xtensa_format_length (isa
, fmt
);
8922 /* Special case: replace a branch to the next instruction with a NOP.
8923 This is required to work around a hardware bug in T1040.0 and also
8924 serves as an optimization. */
8926 if (branch_jmp_to_next
8927 && ((old_size
== 2) || (old_size
== 3))
8928 && !next_frag_is_loop_target (fragP
))
8931 /* Here is the fun stuff: Get the immediate field from this
8932 instruction. If it fits, we are done. If not, find the next
8933 instruction sequence that fits. */
8935 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
8936 istack_init (&istack
);
8937 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
8938 min_steps
, stretch
);
8939 if (num_steps
< min_steps
)
8941 as_fatal (_("internal error: relaxation failed"));
8945 if (num_steps
> RELAX_IMMED_MAXSTEPS
)
8947 as_fatal (_("internal error: relaxation requires too many steps"));
8951 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
8953 /* Figure out the number of bytes needed. */
8955 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
8957 num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
8959 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
8961 num_text_bytes
= get_num_stack_text_bytes (&istack
);
8964 num_text_bytes
+= old_size
;
8965 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
8966 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
8968 total_text_diff
= num_text_bytes
- old_size
;
8969 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
8971 /* It MUST get larger. If not, we could get an infinite loop. */
8972 assert (num_text_bytes
>= 0);
8973 assert (literal_diff
>= 0);
8974 assert (total_text_diff
>= 0);
8976 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
8977 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
8978 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
8979 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
8981 /* Find the associated expandable literal for this. */
8982 if (literal_diff
!= 0)
8984 lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
8987 assert (literal_diff
== 4);
8988 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
8990 /* We expect that the literal section state has NOT been
8992 assert (lit_fragP
->fr_type
== rs_machine_dependent
8993 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
8994 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
8996 /* We need to mark this section for another iteration
9002 if (negatable_branch
&& istack
.ninsn
> 1)
9003 update_next_frag_state (fragP
);
9005 return this_text_diff
;
9009 /* md_convert_frag Hook and Helper Functions. */
9011 static void convert_frag_align_next_opcode (fragS
*);
9012 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9013 static void convert_frag_fill_nop (fragS
*);
9014 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9017 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9019 static xtensa_insnbuf vbuf
= NULL
;
9020 xtensa_isa isa
= xtensa_default_isa
;
9027 as_where (&file_name
, &line
);
9028 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9030 switch (fragp
->fr_subtype
)
9032 case RELAX_ALIGN_NEXT_OPCODE
:
9033 /* Always convert. */
9034 convert_frag_align_next_opcode (fragp
);
9037 case RELAX_DESIRE_ALIGN
:
9038 /* Do nothing. If not aligned already, too bad. */
9042 case RELAX_LITERAL_FINAL
:
9047 vbuf
= xtensa_insnbuf_alloc (isa
);
9049 xtensa_insnbuf_from_chars (isa
, vbuf
, fragp
->fr_opcode
, 0);
9050 fmt
= xtensa_format_decode (isa
, vbuf
);
9051 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9053 for (slot
= 0; slot
< num_slots
; slot
++)
9055 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9058 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9062 case RELAX_IMMED_STEP1
:
9063 case RELAX_IMMED_STEP2
:
9064 /* Place the immediate. */
9067 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9072 /* This is OK because some slots could have
9073 relaxations and others have none. */
9079 case RELAX_UNREACHABLE
:
9080 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9081 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9082 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9086 case RELAX_MAYBE_UNREACHABLE
:
9087 case RELAX_MAYBE_DESIRE_ALIGN
:
9091 case RELAX_FILL_NOP
:
9092 convert_frag_fill_nop (fragp
);
9095 case RELAX_LITERAL_NR
:
9096 if (use_literal_section
)
9098 /* This should have been handled during relaxation. When
9099 relaxing a code segment, literals sometimes need to be
9100 added to the corresponding literal segment. If that
9101 literal segment has already been relaxed, then we end up
9102 in this situation. Marking the literal segments as data
9103 would make this happen less often (since GAS always relaxes
9104 code before data), but we could still get into trouble if
9105 there are instructions in a segment that is not marked as
9106 containing code. Until we can implement a better solution,
9107 cheat and adjust the addresses of all the following frags.
9108 This could break subsequent alignments, but the linker's
9109 literal coalescing will do that anyway. */
9112 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9113 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9114 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9117 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9121 as_bad (_("invalid relaxation fragment result"));
9126 new_logical_line (file_name
, line
);
9131 convert_frag_align_next_opcode (fragS
*fragp
)
9133 char *nop_buf
; /* Location for Writing. */
9136 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9137 addressT aligned_address
;
9138 size_t fill_size
, nop_count
;
9140 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9142 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9143 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9144 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9146 for (i
= 0; i
< nop_count
; i
++)
9149 nop_size
= get_text_align_nth_nop_size (fill_size
, i
, use_no_density
);
9151 assemble_nop (nop_size
, nop_buf
);
9152 nop_buf
+= nop_size
;
9155 fragp
->fr_fix
+= fill_size
;
9156 fragp
->fr_var
-= fill_size
;
9161 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9163 TInsn tinsn
, single_target
;
9164 xtensa_format single_fmt
;
9165 int size
, old_size
, diff
, error_val
;
9166 offsetT frag_offset
;
9169 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9171 if (xtensa_opcode_is_branch (xtensa_default_isa
, tinsn
.opcode
) == 1)
9173 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9174 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9175 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9180 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9182 /* No conversion. */
9187 assert (fragP
->fr_opcode
!= NULL
);
9189 /* Frags in this relaxation state should only contain
9190 single instruction bundles. */
9191 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9193 /* Just convert it to a wide form.... */
9195 old_size
= xg_get_single_size (tinsn
.opcode
);
9197 tinsn_init (&single_target
);
9198 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9200 error_val
= xg_expand_narrow (&single_target
, &tinsn
);
9203 as_bad (_("unable to widen instruction"));
9207 size
= xg_get_single_size (single_target
.opcode
);
9208 single_fmt
= xg_get_single_format (single_target
.opcode
);
9210 xg_emit_insn_to_buf (&single_target
, single_fmt
, fragP
->fr_opcode
,
9211 fragP
, frag_offset
, TRUE
);
9213 diff
= size
- old_size
;
9215 assert (diff
<= fragP
->fr_var
);
9216 fragP
->fr_var
-= diff
;
9217 fragP
->fr_fix
+= diff
;
9225 convert_frag_fill_nop (fragS
*fragP
)
9227 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9228 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9229 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9230 - fragP
->fr_address
- fragP
->fr_fix
));
9233 /* No conversion. */
9237 assemble_nop (size
, loc
);
9238 fragP
->tc_frag_data
.is_insn
= TRUE
;
9239 fragP
->fr_var
-= size
;
9240 fragP
->fr_fix
+= size
;
9245 static fixS
*fix_new_exp_in_seg
9246 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9247 bfd_reloc_code_real_type
);
9248 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9251 convert_frag_immed (segT segP
,
9257 char *immed_instr
= fragP
->fr_opcode
;
9259 bfd_boolean expanded
= FALSE
;
9260 bfd_boolean branch_jmp_to_next
= FALSE
;
9261 char *fr_opcode
= fragP
->fr_opcode
;
9262 vliw_insn orig_vinsn
;
9263 xtensa_isa isa
= xtensa_default_isa
;
9264 bfd_boolean wide_insn
= FALSE
;
9266 bfd_boolean is_loop
;
9268 assert (fr_opcode
!= NULL
);
9270 xg_init_vinsn (&orig_vinsn
);
9272 vinsn_from_chars (&orig_vinsn
, fr_opcode
);
9273 if (xtensa_format_num_slots (isa
, fmt
) > 1)
9276 orig_tinsn
= orig_vinsn
.slots
[slot
];
9277 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9279 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9281 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9282 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9284 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9286 /* Conversion just inserts a NOP and marks the fix as completed. */
9287 bytes
= xtensa_format_length (isa
, fmt
);
9290 orig_vinsn
.slots
[slot
].opcode
=
9291 xtensa_format_slot_nop_opcode (isa
, orig_vinsn
.format
, slot
);
9292 orig_vinsn
.slots
[slot
].ntok
= 0;
9296 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9297 assert (bytes
== 2 || bytes
== 3);
9298 build_nop (&orig_vinsn
.slots
[0], bytes
);
9299 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9301 vinsn_to_insnbuf (&orig_vinsn
, fr_opcode
, frag_now
, FALSE
);
9302 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
, fr_opcode
, 0);
9307 /* Here is the fun stuff: Get the immediate field from this
9308 instruction. If it fits, we're done. If not, find the next
9309 instruction sequence that fits. */
9313 symbolS
*lit_sym
= NULL
;
9315 int target_offset
= 0;
9318 symbolS
*gen_label
= NULL
;
9319 offsetT frag_offset
;
9320 bfd_boolean first
= TRUE
;
9321 bfd_boolean last_is_jump
;
9323 /* It does not fit. Find something that does and
9324 convert immediately. */
9325 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9326 istack_init (&istack
);
9327 xg_assembly_relax (&istack
, &orig_tinsn
,
9328 segP
, fragP
, frag_offset
, min_steps
, 0);
9330 old_size
= xtensa_format_length (isa
, fmt
);
9332 /* Assemble this right inline. */
9334 /* First, create the mapping from a label name to the REAL label. */
9336 for (i
= 0; i
< istack
.ninsn
; i
++)
9338 TInsn
*tinsn
= &istack
.insn
[i
];
9341 switch (tinsn
->insn_type
)
9344 if (lit_sym
!= NULL
)
9345 as_bad (_("multiple literals in expansion"));
9346 /* First find the appropriate space in the literal pool. */
9347 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9348 if (lit_frag
== NULL
)
9349 as_bad (_("no registered fragment for literal"));
9350 if (tinsn
->ntok
!= 1)
9351 as_bad (_("number of literal tokens != 1"));
9353 /* Set the literal symbol and add a fixup. */
9354 lit_sym
= lit_frag
->fr_symbol
;
9358 if (align_targets
&& !is_loop
)
9360 fragS
*unreach
= fragP
->fr_next
;
9361 while (!(unreach
->fr_type
== rs_machine_dependent
9362 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9363 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9365 unreach
= unreach
->fr_next
;
9368 assert (unreach
->fr_type
== rs_machine_dependent
9369 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9370 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9372 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9374 assert (gen_label
== NULL
);
9375 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9376 fr_opcode
- fragP
->fr_literal
9377 + target_offset
, fragP
);
9381 if (first
&& wide_insn
)
9383 target_offset
+= xtensa_format_length (isa
, fmt
);
9385 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9386 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9389 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9396 last_is_jump
= FALSE
;
9397 for (i
= 0; i
< istack
.ninsn
; i
++)
9399 TInsn
*tinsn
= &istack
.insn
[i
];
9403 bfd_reloc_code_real_type reloc_type
;
9405 switch (tinsn
->insn_type
)
9408 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9409 /* Already checked. */
9410 assert (lit_frag
!= NULL
);
9411 assert (lit_sym
!= NULL
);
9412 assert (tinsn
->ntok
== 1);
9414 target_seg
= S_GET_SEGMENT (lit_sym
);
9415 assert (target_seg
);
9416 if (tinsn
->tok
[0].X_op
== O_pltrel
)
9417 reloc_type
= BFD_RELOC_XTENSA_PLT
;
9419 reloc_type
= BFD_RELOC_32
;
9420 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9421 &tinsn
->tok
[0], FALSE
, reloc_type
);
9428 xg_resolve_labels (tinsn
, gen_label
);
9429 xg_resolve_literals (tinsn
, lit_sym
);
9430 if (wide_insn
&& first
)
9433 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9435 tinsn
->record_fix
= TRUE
;
9436 orig_vinsn
.slots
[slot
] = *tinsn
;
9440 orig_vinsn
.slots
[slot
].opcode
=
9441 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9442 orig_vinsn
.slots
[slot
].ntok
= 0;
9443 orig_vinsn
.slots
[slot
].record_fix
= FALSE
;
9445 vinsn_to_insnbuf (&orig_vinsn
, immed_instr
, fragP
, TRUE
);
9446 xtensa_insnbuf_to_chars (isa
, orig_vinsn
.insnbuf
,
9448 fragP
->tc_frag_data
.is_insn
= TRUE
;
9449 size
= xtensa_format_length (isa
, fmt
);
9450 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9452 xtensa_format single_fmt
=
9453 xg_get_single_format (tinsn
->opcode
);
9456 (tinsn
, single_fmt
, immed_instr
+ size
, fragP
,
9457 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9458 size
+= xg_get_single_size (tinsn
->opcode
);
9463 xtensa_format single_format
;
9464 size
= xg_get_single_size (tinsn
->opcode
);
9465 single_format
= xg_get_single_format (tinsn
->opcode
);
9466 xg_emit_insn_to_buf (tinsn
, single_format
, immed_instr
,
9468 immed_instr
- fragP
->fr_literal
, TRUE
);
9470 immed_instr
+= size
;
9476 diff
= total_size
- old_size
;
9480 assert (diff
<= fragP
->fr_var
);
9481 fragP
->fr_var
-= diff
;
9482 fragP
->fr_fix
+= diff
;
9486 xg_free_vinsn (&orig_vinsn
);
9488 /* Check for undefined immediates in LOOP instructions. */
9492 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9493 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9495 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9498 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9499 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9501 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9506 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9507 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9509 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9511 /* Add an expansion note on the expanded instruction. */
9512 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9513 &orig_tinsn
.tok
[0], TRUE
,
9514 BFD_RELOC_XTENSA_ASM_EXPAND
);
9519 /* Add a new fix expression into the desired segment. We have to
9520 switch to that segment to do this. */
9523 fix_new_exp_in_seg (segT new_seg
,
9530 bfd_reloc_code_real_type r_type
)
9534 subsegT subseg
= now_subseg
;
9536 assert (new_seg
!= 0);
9537 subseg_set (new_seg
, new_subseg
);
9539 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9540 subseg_set (seg
, subseg
);
9545 /* Relax a loop instruction so that it can span loop >256 bytes.
9551 addi as, as, lo8 (label-.L1)
9552 addmi as, as, mid8 (label-.L1)
9563 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9568 unsigned long target
;
9569 static xtensa_insnbuf insnbuf
= NULL
;
9570 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9571 xtensa_isa isa
= xtensa_default_isa
;
9572 addressT loop_offset
;
9573 addressT addi_offset
= 9;
9574 addressT addmi_offset
= 12;
9576 size_t target_count
;
9579 insnbuf
= xtensa_insnbuf_alloc (isa
);
9581 /* Get the loop offset. */
9582 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9584 /* Validate that there really is a LOOP at the loop_offset. Because
9585 loops are not bundleable, we can assume that the instruction will be
9587 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9588 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9590 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9591 addi_offset
+= loop_offset
;
9592 addmi_offset
+= loop_offset
;
9594 assert (tinsn
->ntok
== 2);
9595 if (tinsn
->tok
[1].X_op
== O_constant
)
9596 target
= tinsn
->tok
[1].X_add_number
;
9597 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9599 /* Find the fragment. */
9600 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9601 assert (S_GET_SEGMENT (sym
) == segP
9602 || S_GET_SEGMENT (sym
) == absolute_section
);
9603 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9607 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9612 know (symbolP
->sy_frag
);
9613 know (!(S_GET_SEGMENT (symbolP
) == absolute_section
)
9614 || symbol_get_frag (symbolP
) == &zero_address_frag
);
9616 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9617 loop_length_hi
= loop_length
& ~0x0ff;
9618 loop_length_lo
= loop_length
& 0x0ff;
9619 if (loop_length_lo
>= 128)
9621 loop_length_lo
-= 256;
9622 loop_length_hi
+= 256;
9625 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9626 32512. If the loop is larger than that, then we just fail. */
9627 if (loop_length_hi
> 32512)
9628 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9629 _("loop too long for LOOP instruction"));
9631 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9632 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9634 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9635 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9637 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9638 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9640 fragP
->tc_frag_data
.is_insn
= TRUE
;
9641 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addi_offset
, 0);
9643 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9644 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9645 xtensa_insnbuf_to_chars (isa
, insnbuf
, fragP
->fr_opcode
+ addmi_offset
, 0);
9647 /* Walk through all of the frags from here to the loop end
9648 and mark them as no_transform to keep them from being modified
9649 by the linker. If we ever have a relocation for the
9650 addi/addmi of the difference of two symbols we can remove this. */
9653 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9654 next_fragP
= next_fragP
->fr_next
)
9656 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9657 if (next_fragP
->tc_frag_data
.is_loop_target
)
9659 if (target_count
== 2)
9665 /* A map that keeps information on a per-subsegment basis. This is
9666 maintained during initial assembly, but is invalid once the
9667 subsegments are smashed together. I.E., it cannot be used during
9670 typedef struct subseg_map_struct
9678 float total_freq
; /* fall-through + branch target frequency */
9679 float target_freq
; /* branch target frequency alone */
9681 struct subseg_map_struct
*next
;
9685 static subseg_map
*sseg_map
= NULL
;
9688 get_subseg_info (segT seg
, subsegT subseg
)
9690 subseg_map
*subseg_e
;
9692 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9694 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9702 add_subseg_info (segT seg
, subsegT subseg
)
9704 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9705 memset (subseg_e
, 0, sizeof (subseg_map
));
9706 subseg_e
->seg
= seg
;
9707 subseg_e
->subseg
= subseg
;
9708 subseg_e
->flags
= 0;
9709 /* Start off considering every branch target very important. */
9710 subseg_e
->target_freq
= 1.0;
9711 subseg_e
->total_freq
= 1.0;
9712 subseg_e
->next
= sseg_map
;
9713 sseg_map
= subseg_e
;
9719 get_last_insn_flags (segT seg
, subsegT subseg
)
9721 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9723 return subseg_e
->flags
;
9729 set_last_insn_flags (segT seg
,
9734 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9736 subseg_e
= add_subseg_info (seg
, subseg
);
9738 subseg_e
->flags
|= fl
;
9740 subseg_e
->flags
&= ~fl
;
9745 get_subseg_total_freq (segT seg
, subsegT subseg
)
9747 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9749 return subseg_e
->total_freq
;
9755 get_subseg_target_freq (segT seg
, subsegT subseg
)
9757 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9759 return subseg_e
->target_freq
;
9765 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9767 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9769 subseg_e
= add_subseg_info (seg
, subseg
);
9770 subseg_e
->total_freq
= total_f
;
9771 subseg_e
->target_freq
= target_f
;
9775 /* Segment Lists and emit_state Stuff. */
9777 /* Remove the segment from the global sections list. */
9780 xtensa_remove_section (segT sec
)
9782 /* Handle brain-dead bfd_section_list_remove macro, which
9783 expect the address of the prior section's "next" field, not
9784 just the address of the section to remove. */
9786 segT
*ps_next_ptr
= &stdoutput
->sections
;
9787 while (*ps_next_ptr
!= sec
&& *ps_next_ptr
!= NULL
)
9788 ps_next_ptr
= &(*ps_next_ptr
)->next
;
9790 assert (*ps_next_ptr
!= NULL
);
9792 bfd_section_list_remove (stdoutput
, ps_next_ptr
);
9797 xtensa_insert_section (segT after_sec
, segT sec
)
9799 segT
*after_sec_next
;
9800 if (after_sec
== NULL
)
9801 after_sec_next
= &stdoutput
->sections
;
9803 after_sec_next
= &after_sec
->next
;
9805 bfd_section_list_insert (stdoutput
, after_sec_next
, sec
);
9810 xtensa_move_seg_list_to_beginning (seg_list
*head
)
9815 segT literal_section
= head
->seg
;
9817 /* Move the literal section to the front of the section list. */
9818 assert (literal_section
);
9819 xtensa_remove_section (literal_section
);
9820 xtensa_insert_section (NULL
, literal_section
);
9827 static void mark_literal_frags (seg_list
*);
9830 xtensa_move_literals (void)
9833 frchainS
*frchain_from
, *frchain_to
;
9834 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
9835 fragS
**frag_splice
;
9838 fixS
*fix
, *next_fix
, **fix_splice
;
9841 mark_literal_frags (literal_head
->next
);
9842 mark_literal_frags (init_literal_head
->next
);
9843 mark_literal_frags (fini_literal_head
->next
);
9845 if (use_literal_section
)
9848 segment
= literal_head
->next
;
9851 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9852 search_frag
= frchain_from
->frch_root
;
9853 literal_pool
= NULL
;
9855 frag_splice
= &(frchain_from
->frch_root
);
9857 while (!search_frag
->tc_frag_data
.literal_frag
)
9859 assert (search_frag
->fr_fix
== 0
9860 || search_frag
->fr_type
== rs_align
);
9861 search_frag
= search_frag
->fr_next
;
9864 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
9865 == RELAX_LITERAL_POOL_BEGIN
);
9866 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
9868 /* Make sure that all the frags in this series are closed, and
9869 that there is at least one left over of zero-size. This
9870 prevents us from making a segment with an frchain without any
9872 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9873 xtensa_set_frag_assembly_state (frag_now
);
9874 last_frag
= frag_now
;
9875 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
9876 xtensa_set_frag_assembly_state (frag_now
);
9878 while (search_frag
!= frag_now
)
9880 next_frag
= search_frag
->fr_next
;
9882 /* First, move the frag out of the literal section and
9883 to the appropriate place. */
9884 if (search_frag
->tc_frag_data
.literal_frag
)
9886 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
9887 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
9888 /* Note that we set this fr_var to be a fix
9889 chain when we created the literal pool location
9890 as RELAX_LITERAL_POOL_BEGIN. */
9891 frchain_to
= (frchainS
*) literal_pool
->fr_var
;
9893 insert_after
= literal_pool
;
9895 while (insert_after
->fr_next
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
9896 insert_after
= insert_after
->fr_next
;
9898 dest_seg
= (segT
) insert_after
->fr_next
->fr_var
;
9900 *frag_splice
= next_frag
;
9901 search_frag
->fr_next
= insert_after
->fr_next
;
9902 insert_after
->fr_next
= search_frag
;
9903 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
9905 /* Now move any fixups associated with this frag to the
9907 fix
= frchain_from
->fix_root
;
9908 fix_splice
= &(frchain_from
->fix_root
);
9911 next_fix
= fix
->fx_next
;
9912 if (fix
->fx_frag
== search_frag
)
9914 *fix_splice
= next_fix
;
9915 fix
->fx_next
= frchain_to
->fix_root
;
9916 frchain_to
->fix_root
= fix
;
9917 if (frchain_to
->fix_tail
== NULL
)
9918 frchain_to
->fix_tail
= fix
;
9921 fix_splice
= &(fix
->fx_next
);
9924 search_frag
= next_frag
;
9927 if (frchain_from
->fix_root
!= NULL
)
9929 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9930 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
9932 assert (frchain_from
->fix_root
== NULL
);
9934 frchain_from
->fix_tail
= NULL
;
9935 xtensa_restore_emit_state (&state
);
9936 segment
= segment
->next
;
9939 /* Now fix up the SEGMENT value for all the literal symbols. */
9940 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
9942 symbolS
*lit_sym
= lit
->sym
;
9943 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
9945 S_SET_SEGMENT (lit_sym
, dest_seg
);
9950 /* Walk over all the frags for segments in a list and mark them as
9951 containing literals. As clunky as this is, we can't rely on frag_var
9952 and frag_variant to get called in all situations. */
9955 mark_literal_frags (seg_list
*segment
)
9957 frchainS
*frchain_from
;
9962 frchain_from
= seg_info (segment
->seg
)->frchainP
;
9963 search_frag
= frchain_from
->frch_root
;
9966 search_frag
->tc_frag_data
.is_literal
= TRUE
;
9967 search_frag
= search_frag
->fr_next
;
9969 segment
= segment
->next
;
9975 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
9977 /* Move all of the sections in the section list to come
9978 after "after" in the gnu segment list. */
9983 segT literal_section
= head
->seg
;
9985 /* Move the literal section after "after". */
9986 assert (literal_section
);
9987 if (literal_section
!= after
)
9989 xtensa_remove_section (literal_section
);
9990 xtensa_insert_section (after
, literal_section
);
9998 /* Push all the literal segments to the end of the gnu list. */
10001 xtensa_reorder_segments (void)
10008 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10014 /* Now that we have the last section, push all the literal
10015 sections to the end. */
10016 xtensa_reorder_seg_list (literal_head
, last_sec
);
10017 xtensa_reorder_seg_list (init_literal_head
, last_sec
);
10018 xtensa_reorder_seg_list (fini_literal_head
, last_sec
);
10020 /* Now perform the final error check. */
10021 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10023 assert (new_count
== old_count
);
10027 /* Change the emit state (seg, subseg, and frag related stuff) to the
10028 correct location. Return a emit_state which can be passed to
10029 xtensa_restore_emit_state to return to current fragment. */
10032 xtensa_switch_to_literal_fragment (emit_state
*result
)
10034 if (directive_state
[directive_absolute_literals
])
10036 cache_literal_section (0, default_lit_sections
.lit4_seg_name
,
10037 &default_lit_sections
.lit4_seg
, FALSE
);
10038 xtensa_switch_section_emit_state (result
,
10039 default_lit_sections
.lit4_seg
, 0);
10042 xtensa_switch_to_non_abs_literal_fragment (result
);
10044 /* Do a 4-byte align here. */
10045 frag_align (2, 0, 0);
10046 record_alignment (now_seg
, 2);
10051 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10053 /* When we mark a literal pool location, we want to put a frag in
10054 the literal pool that points to it. But to do that, we want to
10055 switch_to_literal_fragment. But literal sections don't have
10056 literal pools, so their location is always null, so we would
10057 recurse forever. This is kind of hacky, but it works. */
10059 static bfd_boolean recursive
= FALSE
;
10060 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10061 bfd_boolean is_init
=
10062 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10064 bfd_boolean is_fini
=
10065 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10067 if (pool_location
== NULL
10068 && !use_literal_section
10070 && !is_init
&& ! is_fini
)
10072 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10074 xtensa_mark_literal_pool_location ();
10078 /* Special case: If we are in the ".fini" or ".init" section, then
10079 we will ALWAYS be generating to the ".fini.literal" and
10080 ".init.literal" sections. */
10084 cache_literal_section (init_literal_head
,
10085 default_lit_sections
.init_lit_seg_name
,
10086 &default_lit_sections
.init_lit_seg
, TRUE
);
10087 xtensa_switch_section_emit_state (result
,
10088 default_lit_sections
.init_lit_seg
, 0);
10092 cache_literal_section (fini_literal_head
,
10093 default_lit_sections
.fini_lit_seg_name
,
10094 &default_lit_sections
.fini_lit_seg
, TRUE
);
10095 xtensa_switch_section_emit_state (result
,
10096 default_lit_sections
.fini_lit_seg
, 0);
10100 cache_literal_section (literal_head
,
10101 default_lit_sections
.lit_seg_name
,
10102 &default_lit_sections
.lit_seg
, TRUE
);
10103 xtensa_switch_section_emit_state (result
,
10104 default_lit_sections
.lit_seg
, 0);
10107 if (!use_literal_section
10108 && !is_init
&& !is_fini
10109 && get_literal_pool_location (now_seg
) != pool_location
)
10111 /* Close whatever frag is there. */
10112 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10113 xtensa_set_frag_assembly_state (frag_now
);
10114 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10115 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10116 xtensa_set_frag_assembly_state (frag_now
);
10121 /* Call this function before emitting data into the literal section.
10122 This is a helper function for xtensa_switch_to_literal_fragment.
10123 This is similar to a .section new_now_seg subseg. */
10126 xtensa_switch_section_emit_state (emit_state
*state
,
10128 subsegT new_now_subseg
)
10130 state
->name
= now_seg
->name
;
10131 state
->now_seg
= now_seg
;
10132 state
->now_subseg
= now_subseg
;
10133 state
->generating_literals
= generating_literals
;
10134 generating_literals
++;
10135 subseg_set (new_now_seg
, new_now_subseg
);
10139 /* Use to restore the emitting into the normal place. */
10142 xtensa_restore_emit_state (emit_state
*state
)
10144 generating_literals
= state
->generating_literals
;
10145 subseg_set (state
->now_seg
, state
->now_subseg
);
10149 /* Get a segment of a given name. If the segment is already
10150 present, return it; otherwise, create a new one. */
10153 cache_literal_section (seg_list
*head
,
10156 bfd_boolean is_code
)
10158 segT current_section
= now_seg
;
10159 int current_subsec
= now_subseg
;
10165 /* Check if the named section exists. */
10166 for (seg
= stdoutput
->sections
; seg
; seg
= seg
->next
)
10168 if (!strcmp (segment_name (seg
), name
))
10174 /* Create a new literal section. */
10175 seg
= subseg_new (name
, (subsegT
) 0);
10178 /* Add the newly created literal segment to the specified list. */
10179 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10181 n
->next
= head
->next
;
10184 bfd_set_section_flags (stdoutput
, seg
, SEC_HAS_CONTENTS
|
10185 SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10186 | (is_code
? SEC_CODE
: SEC_DATA
));
10187 bfd_set_section_alignment (stdoutput
, seg
, 2);
10191 subseg_set (current_section
, current_subsec
);
10195 /* Property Tables Stuff. */
10197 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10198 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10199 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10201 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10202 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10204 static bfd_boolean
get_frag_is_literal (const fragS
*);
10205 static void xtensa_create_property_segments
10206 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10207 static void xtensa_create_xproperty_segments
10208 (frag_flags_fn
, const char *, xt_section_type
);
10209 static segment_info_type
*retrieve_segment_info (segT
);
10210 static segT
retrieve_xtensa_section (char *);
10211 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10212 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10213 static void add_xt_block_frags
10214 (segT
, segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10215 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10216 static void xtensa_frag_flags_init (frag_flags
*);
10217 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10218 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10219 static void add_xt_prop_frags
10220 (segT
, segT
, xtensa_block_info
**, frag_flags_fn
);
10222 /* Set up property tables after relaxation. */
10225 xtensa_post_relax_hook (void)
10227 xtensa_move_seg_list_to_beginning (literal_head
);
10228 xtensa_move_seg_list_to_beginning (init_literal_head
);
10229 xtensa_move_seg_list_to_beginning (fini_literal_head
);
10231 xtensa_find_unmarked_state_frags ();
10233 if (use_literal_section
)
10234 xtensa_create_property_segments (get_frag_is_literal
,
10236 XTENSA_LIT_SEC_NAME
,
10238 xtensa_create_xproperty_segments (get_frag_property_flags
,
10239 XTENSA_PROP_SEC_NAME
,
10242 if (warn_unaligned_branch_targets
)
10243 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10244 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10248 /* This function is only meaningful after xtensa_move_literals. */
10251 get_frag_is_literal (const fragS
*fragP
)
10253 assert (fragP
!= NULL
);
10254 return fragP
->tc_frag_data
.is_literal
;
10259 xtensa_create_property_segments (frag_predicate property_function
,
10260 frag_predicate end_property_function
,
10261 const char *section_name_base
,
10262 xt_section_type sec_type
)
10266 /* Walk over all of the current segments.
10267 Walk over each fragment
10268 For each non-empty fragment,
10269 Build a property record (append where possible). */
10271 for (seclist
= &stdoutput
->sections
;
10272 seclist
&& *seclist
;
10273 seclist
= &(*seclist
)->next
)
10275 segT sec
= *seclist
;
10278 flags
= bfd_get_section_flags (stdoutput
, sec
);
10279 if (flags
& SEC_DEBUGGING
)
10281 if (!(flags
& SEC_ALLOC
))
10284 if (section_has_property (sec
, property_function
))
10286 char *property_section_name
=
10287 xtensa_get_property_section_name (sec
, section_name_base
);
10288 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10289 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10290 xtensa_block_info
**xt_blocks
=
10291 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10292 /* Walk over all of the frchains here and add new sections. */
10293 add_xt_block_frags (sec
, insn_sec
, xt_blocks
, property_function
,
10294 end_property_function
);
10298 /* Now we fill them out.... */
10300 for (seclist
= &stdoutput
->sections
;
10301 seclist
&& *seclist
;
10302 seclist
= &(*seclist
)->next
)
10304 segment_info_type
*seginfo
;
10305 xtensa_block_info
*block
;
10306 segT sec
= *seclist
;
10308 seginfo
= seg_info (sec
);
10309 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10313 xtensa_block_info
*cur_block
;
10314 /* This is a section with some data. */
10318 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10321 rec_size
= num_recs
* 8;
10322 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10324 /* In order to make this work with the assembler, we have to
10325 build some frags and then build the "fixups" for it. It
10326 would be easier to just set the contents then set the
10331 /* Allocate a fragment and leak it. */
10335 frchainS
*frchainP
;
10339 frag_size
= sizeof (fragS
) + rec_size
;
10340 fragP
= (fragS
*) xmalloc (frag_size
);
10342 memset (fragP
, 0, frag_size
);
10343 fragP
->fr_address
= 0;
10344 fragP
->fr_next
= NULL
;
10345 fragP
->fr_fix
= rec_size
;
10347 fragP
->fr_type
= rs_fill
;
10348 /* The rest are zeros. */
10350 frchainP
= seginfo
->frchainP
;
10351 frchainP
->frch_root
= fragP
;
10352 frchainP
->frch_last
= fragP
;
10354 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10355 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10357 seginfo
->fix_root
= fixes
;
10358 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10360 frag_data
= &fragP
->fr_literal
[0];
10361 for (i
= 0; i
< num_recs
; i
++)
10363 fixS
*fix
= &fixes
[i
];
10364 assert (cur_block
);
10366 /* Write the fixup. */
10367 if (i
!= num_recs
- 1)
10368 fix
->fx_next
= &fixes
[i
+ 1];
10370 fix
->fx_next
= NULL
;
10373 fix
->fx_frag
= fragP
;
10374 fix
->fx_where
= i
* 8;
10375 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10376 fix
->fx_offset
= cur_block
->offset
;
10377 fix
->fx_r_type
= BFD_RELOC_32
;
10378 fix
->fx_file
= "Internal Assembly";
10381 /* Write the length. */
10382 md_number_to_chars (&frag_data
[4 + 8 * i
],
10383 cur_block
->size
, 4);
10384 cur_block
= cur_block
->next
;
10393 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10394 const char *section_name_base
,
10395 xt_section_type sec_type
)
10399 /* Walk over all of the current segments.
10400 Walk over each fragment.
10401 For each fragment that has instructions,
10402 build an instruction record (append where possible). */
10404 for (seclist
= &stdoutput
->sections
;
10405 seclist
&& *seclist
;
10406 seclist
= &(*seclist
)->next
)
10408 segT sec
= *seclist
;
10411 flags
= bfd_get_section_flags (stdoutput
, sec
);
10412 if (flags
& SEC_DEBUGGING
)
10414 if (!(flags
& SEC_ALLOC
))
10417 if (section_has_xproperty (sec
, flag_fn
))
10419 char *property_section_name
=
10420 xtensa_get_property_section_name (sec
, section_name_base
);
10421 segT insn_sec
= retrieve_xtensa_section (property_section_name
);
10422 segment_info_type
*xt_seg_info
= retrieve_segment_info (insn_sec
);
10423 xtensa_block_info
**xt_blocks
=
10424 &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10425 /* Walk over all of the frchains here and add new sections. */
10426 add_xt_prop_frags (sec
, insn_sec
, xt_blocks
, flag_fn
);
10430 /* Now we fill them out.... */
10432 for (seclist
= &stdoutput
->sections
;
10433 seclist
&& *seclist
;
10434 seclist
= &(*seclist
)->next
)
10436 segment_info_type
*seginfo
;
10437 xtensa_block_info
*block
;
10438 segT sec
= *seclist
;
10440 seginfo
= seg_info (sec
);
10441 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10445 xtensa_block_info
*cur_block
;
10446 /* This is a section with some data. */
10450 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10453 rec_size
= num_recs
* (8 + 4);
10454 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10456 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10458 /* In order to make this work with the assembler, we have to build
10459 some frags then build the "fixups" for it. It would be easier to
10460 just set the contents then set the arlents. */
10464 /* Allocate a fragment and (unfortunately) leak it. */
10468 frchainS
*frchainP
;
10472 frag_size
= sizeof (fragS
) + rec_size
;
10473 fragP
= (fragS
*) xmalloc (frag_size
);
10475 memset (fragP
, 0, frag_size
);
10476 fragP
->fr_address
= 0;
10477 fragP
->fr_next
= NULL
;
10478 fragP
->fr_fix
= rec_size
;
10480 fragP
->fr_type
= rs_fill
;
10481 /* The rest are zeros. */
10483 frchainP
= seginfo
->frchainP
;
10484 frchainP
->frch_root
= fragP
;
10485 frchainP
->frch_last
= fragP
;
10487 fixes
= (fixS
*) xmalloc (sizeof (fixS
) * num_recs
);
10488 memset (fixes
, 0, sizeof (fixS
) * num_recs
);
10490 seginfo
->fix_root
= fixes
;
10491 seginfo
->fix_tail
= &fixes
[num_recs
- 1];
10493 frag_data
= &fragP
->fr_literal
[0];
10494 for (i
= 0; i
< num_recs
; i
++)
10496 fixS
*fix
= &fixes
[i
];
10497 assert (cur_block
);
10499 /* Write the fixup. */
10500 if (i
!= num_recs
- 1)
10501 fix
->fx_next
= &fixes
[i
+ 1];
10503 fix
->fx_next
= NULL
;
10506 fix
->fx_frag
= fragP
;
10507 fix
->fx_where
= i
* (8 + 4);
10508 fix
->fx_addsy
= section_symbol (cur_block
->sec
);
10509 fix
->fx_offset
= cur_block
->offset
;
10510 fix
->fx_r_type
= BFD_RELOC_32
;
10511 fix
->fx_file
= "Internal Assembly";
10514 /* Write the length. */
10515 md_number_to_chars (&frag_data
[4 + (8+4) * i
],
10516 cur_block
->size
, 4);
10517 md_number_to_chars (&frag_data
[8 + (8+4) * i
],
10518 frag_flags_to_number (&cur_block
->flags
),
10520 cur_block
= cur_block
->next
;
10528 static segment_info_type
*
10529 retrieve_segment_info (segT seg
)
10531 segment_info_type
*seginfo
;
10532 seginfo
= (segment_info_type
*) bfd_get_section_userdata (stdoutput
, seg
);
10535 frchainS
*frchainP
;
10537 seginfo
= (segment_info_type
*) xmalloc (sizeof (*seginfo
));
10538 memset ((void *) seginfo
, 0, sizeof (*seginfo
));
10539 seginfo
->fix_root
= NULL
;
10540 seginfo
->fix_tail
= NULL
;
10541 seginfo
->bfd_section
= seg
;
10543 /* We will not be dealing with these, only our special ones. */
10544 bfd_set_section_userdata (stdoutput
, seg
, (void *) seginfo
);
10546 frchainP
= (frchainS
*) xmalloc (sizeof (frchainS
));
10547 frchainP
->frch_root
= NULL
;
10548 frchainP
->frch_last
= NULL
;
10549 frchainP
->frch_next
= NULL
;
10550 frchainP
->frch_seg
= seg
;
10551 frchainP
->frch_subseg
= 0;
10552 frchainP
->fix_root
= NULL
;
10553 frchainP
->fix_tail
= NULL
;
10554 /* Do not init the objstack. */
10555 /* obstack_begin (&frchainP->frch_obstack, chunksize); */
10556 /* frchainP->frch_frag_now = fragP; */
10557 frchainP
->frch_frag_now
= NULL
;
10559 seginfo
->frchainP
= frchainP
;
10567 retrieve_xtensa_section (char *sec_name
)
10569 bfd
*abfd
= stdoutput
;
10570 flagword flags
, out_flags
, link_once_flags
;
10573 flags
= bfd_get_section_flags (abfd
, now_seg
);
10574 link_once_flags
= (flags
& SEC_LINK_ONCE
);
10575 if (link_once_flags
)
10576 link_once_flags
|= (flags
& SEC_LINK_DUPLICATES
);
10577 out_flags
= (SEC_RELOC
| SEC_HAS_CONTENTS
| SEC_READONLY
| link_once_flags
);
10579 s
= bfd_make_section_old_way (abfd
, sec_name
);
10581 as_bad (_("could not create section %s"), sec_name
);
10582 if (!bfd_set_section_flags (abfd
, s
, out_flags
))
10583 as_bad (_("invalid flag combination on section %s"), sec_name
);
10590 section_has_property (segT sec
, frag_predicate property_function
)
10592 segment_info_type
*seginfo
= seg_info (sec
);
10595 if (seginfo
&& seginfo
->frchainP
)
10597 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10599 if (property_function (fragP
)
10600 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10609 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10611 segment_info_type
*seginfo
= seg_info (sec
);
10614 if (seginfo
&& seginfo
->frchainP
)
10616 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10618 frag_flags prop_flags
;
10619 property_function (fragP
, &prop_flags
);
10620 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10628 /* Two types of block sections exist right now: literal and insns. */
10631 add_xt_block_frags (segT sec
,
10633 xtensa_block_info
**xt_block
,
10634 frag_predicate property_function
,
10635 frag_predicate end_property_function
)
10637 segment_info_type
*seg_info
;
10638 segment_info_type
*xt_seg_info
;
10639 bfd_vma seg_offset
;
10642 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10643 seg_info
= retrieve_segment_info (sec
);
10645 /* Build it if needed. */
10646 while (*xt_block
!= NULL
)
10647 xt_block
= &(*xt_block
)->next
;
10648 /* We are either at NULL at the beginning or at the end. */
10650 /* Walk through the frags. */
10653 if (seg_info
->frchainP
)
10655 for (fragP
= seg_info
->frchainP
->frch_root
;
10657 fragP
= fragP
->fr_next
)
10659 if (property_function (fragP
)
10660 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10662 if (*xt_block
!= NULL
)
10664 if ((*xt_block
)->offset
+ (*xt_block
)->size
10665 == fragP
->fr_address
)
10666 (*xt_block
)->size
+= fragP
->fr_fix
;
10668 xt_block
= &((*xt_block
)->next
);
10670 if (*xt_block
== NULL
)
10672 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10673 xmalloc (sizeof (xtensa_block_info
));
10674 new_block
->sec
= sec
;
10675 new_block
->offset
= fragP
->fr_address
;
10676 new_block
->size
= fragP
->fr_fix
;
10677 new_block
->next
= NULL
;
10678 xtensa_frag_flags_init (&new_block
->flags
);
10679 *xt_block
= new_block
;
10681 if (end_property_function
10682 && end_property_function (fragP
))
10684 xt_block
= &((*xt_block
)->next
);
10692 /* Break the encapsulation of add_xt_prop_frags here. */
10695 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10697 if (prop_flags
->is_literal
10698 || prop_flags
->is_insn
10699 || prop_flags
->is_data
10700 || prop_flags
->is_unreachable
)
10707 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10709 memset (prop_flags
, 0, sizeof (frag_flags
));
10714 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10716 xtensa_frag_flags_init (prop_flags
);
10717 if (fragP
->tc_frag_data
.is_literal
)
10718 prop_flags
->is_literal
= TRUE
;
10719 if (fragP
->tc_frag_data
.is_unreachable
)
10720 prop_flags
->is_unreachable
= TRUE
;
10721 else if (fragP
->tc_frag_data
.is_insn
)
10723 prop_flags
->is_insn
= TRUE
;
10724 if (fragP
->tc_frag_data
.is_loop_target
)
10725 prop_flags
->insn
.is_loop_target
= TRUE
;
10726 if (fragP
->tc_frag_data
.is_branch_target
)
10727 prop_flags
->insn
.is_branch_target
= TRUE
;
10728 if (fragP
->tc_frag_data
.is_specific_opcode
10729 || fragP
->tc_frag_data
.is_no_transform
)
10730 prop_flags
->insn
.is_no_transform
= TRUE
;
10731 if (fragP
->tc_frag_data
.is_no_density
)
10732 prop_flags
->insn
.is_no_density
= TRUE
;
10733 if (fragP
->tc_frag_data
.use_absolute_literals
)
10734 prop_flags
->insn
.is_abslit
= TRUE
;
10736 if (fragP
->tc_frag_data
.is_align
)
10738 prop_flags
->is_align
= TRUE
;
10739 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10740 if (xtensa_frag_flags_is_empty (prop_flags
))
10741 prop_flags
->is_data
= TRUE
;
10747 frag_flags_to_number (const frag_flags
*prop_flags
)
10750 if (prop_flags
->is_literal
)
10751 num
|= XTENSA_PROP_LITERAL
;
10752 if (prop_flags
->is_insn
)
10753 num
|= XTENSA_PROP_INSN
;
10754 if (prop_flags
->is_data
)
10755 num
|= XTENSA_PROP_DATA
;
10756 if (prop_flags
->is_unreachable
)
10757 num
|= XTENSA_PROP_UNREACHABLE
;
10758 if (prop_flags
->insn
.is_loop_target
)
10759 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10760 if (prop_flags
->insn
.is_branch_target
)
10762 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10763 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10766 if (prop_flags
->insn
.is_no_density
)
10767 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10768 if (prop_flags
->insn
.is_no_transform
)
10769 num
|= XTENSA_PROP_INSN_NO_TRANSFORM
;
10770 if (prop_flags
->insn
.is_no_reorder
)
10771 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10772 if (prop_flags
->insn
.is_abslit
)
10773 num
|= XTENSA_PROP_INSN_ABSLIT
;
10775 if (prop_flags
->is_align
)
10777 num
|= XTENSA_PROP_ALIGN
;
10778 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10786 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10787 const frag_flags
*prop_flags_2
)
10789 /* Cannot combine with an end marker. */
10791 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10793 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10795 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10798 if (prop_flags_1
->is_insn
)
10800 /* Properties of the beginning of the frag. */
10801 if (prop_flags_2
->insn
.is_loop_target
)
10803 if (prop_flags_2
->insn
.is_branch_target
)
10805 if (prop_flags_1
->insn
.is_no_density
!=
10806 prop_flags_2
->insn
.is_no_density
)
10808 if (prop_flags_1
->insn
.is_no_transform
!=
10809 prop_flags_2
->insn
.is_no_transform
)
10811 if (prop_flags_1
->insn
.is_no_reorder
!=
10812 prop_flags_2
->insn
.is_no_reorder
)
10814 if (prop_flags_1
->insn
.is_abslit
!=
10815 prop_flags_2
->insn
.is_abslit
)
10819 if (prop_flags_1
->is_align
)
10827 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10832 if (!xt_block
->flags
.is_align
)
10833 return xt_block
->size
;
10835 end_addr
= xt_block
->offset
+ xt_block
->size
;
10836 align_bits
= xt_block
->flags
.alignment
;
10837 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10838 return end_addr
- xt_block
->offset
;
10843 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10844 const xtensa_block_info
*xt_block_2
)
10846 if (xt_block
->sec
!= xt_block_2
->sec
)
10848 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10849 != xt_block_2
->offset
)
10852 if (xt_block_2
->size
== 0
10853 && (!xt_block_2
->flags
.is_unreachable
10854 || xt_block
->flags
.is_unreachable
))
10856 if (xt_block_2
->flags
.is_align
10857 && xt_block
->flags
.is_align
)
10859 /* Nothing needed. */
10860 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10865 if (xt_block_2
->flags
.is_align
)
10867 /* Push alignment to previous entry. */
10868 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10869 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10874 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
10875 &xt_block_2
->flags
))
10878 xt_block
->size
+= xt_block_2
->size
;
10880 if (xt_block_2
->flags
.is_align
)
10882 xt_block
->flags
.is_align
= TRUE
;
10883 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
10891 add_xt_prop_frags (segT sec
,
10893 xtensa_block_info
**xt_block
,
10894 frag_flags_fn property_function
)
10896 segment_info_type
*seg_info
;
10897 segment_info_type
*xt_seg_info
;
10898 bfd_vma seg_offset
;
10901 xt_seg_info
= retrieve_segment_info (xt_block_sec
);
10902 seg_info
= retrieve_segment_info (sec
);
10903 /* Build it if needed. */
10904 while (*xt_block
!= NULL
)
10906 xt_block
= &(*xt_block
)->next
;
10908 /* We are either at NULL at the beginning or at the end. */
10910 /* Walk through the frags. */
10913 if (seg_info
->frchainP
)
10915 for (fragP
= seg_info
->frchainP
->frch_root
; fragP
;
10916 fragP
= fragP
->fr_next
)
10918 xtensa_block_info tmp_block
;
10919 tmp_block
.sec
= sec
;
10920 tmp_block
.offset
= fragP
->fr_address
;
10921 tmp_block
.size
= fragP
->fr_fix
;
10922 tmp_block
.next
= NULL
;
10923 property_function (fragP
, &tmp_block
.flags
);
10925 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
10926 /* && fragP->fr_fix != 0) */
10928 if ((*xt_block
) == NULL
10929 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
10931 xtensa_block_info
*new_block
;
10932 if ((*xt_block
) != NULL
)
10933 xt_block
= &(*xt_block
)->next
;
10934 new_block
= (xtensa_block_info
*)
10935 xmalloc (sizeof (xtensa_block_info
));
10936 *new_block
= tmp_block
;
10937 *xt_block
= new_block
;
10945 /* op_placement_info_table */
10947 /* op_placement_info makes it easier to determine which
10948 ops can go in which slots. */
10951 init_op_placement_info_table (void)
10953 xtensa_isa isa
= xtensa_default_isa
;
10954 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
10955 xtensa_opcode opcode
;
10958 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
10960 op_placement_table
= (op_placement_info_table
)
10961 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
10962 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
10964 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
10966 op_placement_info
*opi
= &op_placement_table
[opcode
];
10967 /* FIXME: Make tinsn allocation dynamic. */
10968 if (xtensa_opcode_num_operands (isa
, opcode
) >= MAX_INSN_ARGS
)
10969 as_fatal (_("too many operands in instruction"));
10970 opi
->single
= XTENSA_UNDEFINED
;
10971 opi
->single_size
= 0;
10972 opi
->widest
= XTENSA_UNDEFINED
;
10973 opi
->widest_size
= 0;
10974 opi
->narrowest
= XTENSA_UNDEFINED
;
10975 opi
->narrowest_size
= 0x7F;
10977 opi
->num_formats
= 0;
10979 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
10981 opi
->slots
[fmt
] = 0;
10982 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
10984 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
10986 int fmt_length
= xtensa_format_length (isa
, fmt
);
10988 set_bit (fmt
, opi
->formats
);
10989 set_bit (slot
, opi
->slots
[fmt
]);
10990 /* opi->slot_count[fmt]++; */
10991 if (fmt_length
< opi
->narrowest_size
)
10993 opi
->narrowest
= fmt
;
10994 opi
->narrowest_size
= fmt_length
;
10996 if (fmt_length
> opi
->widest_size
)
10999 opi
->widest_size
= fmt_length
;
11001 if (xtensa_format_num_slots (isa
, fmt
) == 1)
11003 if (opi
->single_size
== 0
11004 || fmt_length
< opi
->single_size
)
11007 opi
->single_size
= fmt_length
;
11013 opi
->num_formats
++;
11016 xtensa_insnbuf_free (isa
, ibuf
);
11021 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11023 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11027 /* If the opcode is available in a single slot format, return its size. */
11030 xg_get_single_size (xtensa_opcode opcode
)
11032 assert (op_placement_table
[opcode
].single
!= XTENSA_UNDEFINED
);
11033 return op_placement_table
[opcode
].single_size
;
11037 static xtensa_format
11038 xg_get_single_format (xtensa_opcode opcode
)
11040 return op_placement_table
[opcode
].single
;
11044 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11047 istack_init (IStack
*stack
)
11049 memset (stack
, 0, sizeof (IStack
));
11055 istack_empty (IStack
*stack
)
11057 return (stack
->ninsn
== 0);
11062 istack_full (IStack
*stack
)
11064 return (stack
->ninsn
== MAX_ISTACK
);
11068 /* Return a pointer to the top IStack entry.
11069 It is an error to call this if istack_empty () is TRUE. */
11072 istack_top (IStack
*stack
)
11074 int rec
= stack
->ninsn
- 1;
11075 assert (!istack_empty (stack
));
11076 return &stack
->insn
[rec
];
11080 /* Add a new TInsn to an IStack.
11081 It is an error to call this if istack_full () is TRUE. */
11084 istack_push (IStack
*stack
, TInsn
*insn
)
11086 int rec
= stack
->ninsn
;
11087 assert (!istack_full (stack
));
11088 stack
->insn
[rec
] = *insn
;
11093 /* Clear space for the next TInsn on the IStack and return a pointer
11094 to it. It is an error to call this if istack_full () is TRUE. */
11097 istack_push_space (IStack
*stack
)
11099 int rec
= stack
->ninsn
;
11101 assert (!istack_full (stack
));
11102 insn
= &stack
->insn
[rec
];
11103 memset (insn
, 0, sizeof (TInsn
));
11109 /* Remove the last pushed instruction. It is an error to call this if
11110 istack_empty () returns TRUE. */
11113 istack_pop (IStack
*stack
)
11115 int rec
= stack
->ninsn
- 1;
11116 assert (!istack_empty (stack
));
11118 memset (&stack
->insn
[rec
], 0, sizeof (TInsn
));
11122 /* TInsn functions. */
11125 tinsn_init (TInsn
*dst
)
11127 memset (dst
, 0, sizeof (TInsn
));
11131 /* Get the ``num''th token of the TInsn.
11132 It is illegal to call this if num > insn->ntoks. */
11135 tinsn_get_tok (TInsn
*insn
, int num
)
11137 assert (num
< insn
->ntok
);
11138 return &insn
->tok
[num
];
11142 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11145 tinsn_has_symbolic_operands (const TInsn
*insn
)
11148 int n
= insn
->ntok
;
11150 assert (insn
->insn_type
== ITYPE_INSN
);
11152 for (i
= 0; i
< n
; ++i
)
11154 switch (insn
->tok
[i
].X_op
)
11168 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11170 xtensa_isa isa
= xtensa_default_isa
;
11172 int n
= insn
->ntok
;
11174 assert (insn
->insn_type
== ITYPE_INSN
);
11176 for (i
= 0; i
< n
; ++i
)
11178 switch (insn
->tok
[i
].X_op
)
11186 /* Errors for these types are caught later. */
11191 /* Symbolic immediates are only allowed on the last immediate
11192 operand. At this time, CONST16 is the only opcode where we
11193 support non-PC-relative relocations. (It isn't necessary
11194 to complain about non-PC-relative relocations here, but
11195 otherwise, no error is reported until the relocations are
11196 generated, and the assembler won't get that far if there
11197 are any other errors. It's nice to see all the problems
11199 if (i
!= get_relaxable_immed (insn
->opcode
)
11200 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11201 && insn
->opcode
!= xtensa_const16_opcode
))
11203 as_bad (_("invalid symbolic operand %d on '%s'"),
11204 i
, xtensa_opcode_name (isa
, insn
->opcode
));
11213 /* For assembly code with complex expressions (e.g. subtraction),
11214 we have to build them in the literal pool so that
11215 their results are calculated correctly after relaxation.
11216 The relaxation only handles expressions that
11217 boil down to SYMBOL + OFFSET. */
11220 tinsn_has_complex_operands (const TInsn
*insn
)
11223 int n
= insn
->ntok
;
11224 assert (insn
->insn_type
== ITYPE_INSN
);
11225 for (i
= 0; i
< n
; ++i
)
11227 switch (insn
->tok
[i
].X_op
)
11243 /* Convert the constant operands in the tinsn to insnbuf.
11244 Return TRUE if there is a symbol in the immediate field.
11246 Before this is called,
11247 1) the number of operands are correct
11248 2) the tinsn is a ITYPE_INSN
11249 3) ONLY the relaxable_ is built
11250 4) All operands are O_constant, O_symbol. All constants fit
11251 The return value tells whether there are any remaining O_symbols. */
11254 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11256 static xtensa_insnbuf slotbuf
= 0;
11257 xtensa_isa isa
= xtensa_default_isa
;
11258 xtensa_opcode opcode
= tinsn
->opcode
;
11259 xtensa_format fmt
= xg_get_single_format (opcode
);
11260 bfd_boolean has_fixup
= FALSE
;
11261 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11268 slotbuf
= xtensa_insnbuf_alloc (isa
);
11270 assert (tinsn
->insn_type
== ITYPE_INSN
);
11271 if (noperands
!= tinsn
->ntok
)
11272 as_fatal (_("operand number mismatch"));
11274 if (xtensa_opcode_encode (isa
, fmt
, 0, slotbuf
, opcode
))
11275 as_fatal (_("cannot encode opcode"));
11277 for (i
= 0; i
< noperands
; ++i
)
11279 expressionS
*expr
= &tinsn
->tok
[i
];
11280 switch (expr
->X_op
)
11283 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11285 /* The register number has already been checked in
11286 expression_maybe_register, so we don't need to check here. */
11287 opnd_value
= expr
->X_add_number
;
11288 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11289 xtensa_operand_set_field (isa
, opcode
, i
, fmt
, 0,
11290 slotbuf
, opnd_value
);
11294 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11296 as_where (&file_name
, &line
);
11297 /* It is a constant and we called this function,
11298 then we have to try to fit it. */
11299 xtensa_insnbuf_set_operand (slotbuf
, fmt
, 0, opcode
, i
,
11300 expr
->X_add_number
, file_name
, line
);
11309 xtensa_format_encode (isa
, fmt
, insnbuf
);
11310 xtensa_format_set_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
11316 /* Convert the constant operands in the tinsn to slotbuf.
11317 Return TRUE if there is a symbol in the immediate field.
11318 (Eventually this should replace tinsn_to_insnbuf.) */
11320 /* Before this is called,
11321 1) the number of operands are correct
11322 2) the tinsn is a ITYPE_INSN
11323 3) ONLY the relaxable_ is built
11324 4) All operands are
11325 O_constant, O_symbol
11328 The return value tells whether there are any remaining O_symbols. */
11331 tinsn_to_slotbuf (xtensa_format fmt
,
11334 xtensa_insnbuf slotbuf
)
11336 xtensa_isa isa
= xtensa_default_isa
;
11337 xtensa_opcode opcode
= tinsn
->opcode
;
11338 bfd_boolean has_fixup
= FALSE
;
11339 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11342 *((int *) &slotbuf
[0]) = 0;
11343 *((int *) &slotbuf
[1]) = 0;
11344 assert (tinsn
->insn_type
== ITYPE_INSN
);
11345 if (noperands
!= tinsn
->ntok
)
11346 as_fatal (_("operand number mismatch"));
11348 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11350 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11351 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11355 for (i
= 0; i
< noperands
; i
++)
11357 expressionS
*expr
= &tinsn
->tok
[i
];
11362 switch (expr
->X_op
)
11365 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11367 /* The register number has already been checked in
11368 expression_maybe_register, so we don't need to check here. */
11369 opnd_value
= expr
->X_add_number
;
11370 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11371 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11374 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11378 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11380 as_where (&file_name
, &line
);
11381 /* It is a constant and we called this function
11382 then we have to try to fit it. */
11383 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11384 expr
->X_add_number
, file_name
, line
);
11397 /* Check the instruction arguments. Return TRUE on failure. */
11400 tinsn_check_arguments (const TInsn
*insn
)
11402 xtensa_isa isa
= xtensa_default_isa
;
11403 xtensa_opcode opcode
= insn
->opcode
;
11405 if (opcode
== XTENSA_UNDEFINED
)
11407 as_bad (_("invalid opcode"));
11411 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11413 as_bad (_("too few operands"));
11417 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11419 as_bad (_("too many operands"));
11426 /* Load an instruction from its encoded form. */
11429 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11433 xg_init_vinsn (&vinsn
);
11434 vinsn_from_chars (&vinsn
, f
);
11436 *tinsn
= vinsn
.slots
[slot
];
11437 xg_free_vinsn (&vinsn
);
11442 tinsn_from_insnbuf (TInsn
*tinsn
,
11443 xtensa_insnbuf slotbuf
,
11448 xtensa_isa isa
= xtensa_default_isa
;
11450 /* Find the immed. */
11451 tinsn_init (tinsn
);
11452 tinsn
->insn_type
= ITYPE_INSN
;
11453 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11454 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11455 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11456 for (i
= 0; i
< tinsn
->ntok
; i
++)
11458 set_expr_const (&tinsn
->tok
[i
],
11459 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11460 tinsn
->opcode
, i
));
11465 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11468 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11470 xtensa_opcode opcode
= tinsn
->opcode
;
11473 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11475 opnum
= get_relaxable_immed (opcode
);
11476 assert (opnum
>= 0);
11477 if (fragP
->tc_frag_data
.slot_sub_symbols
[slot
])
11479 set_expr_symbol_offset_diff
11480 (&tinsn
->tok
[opnum
],
11481 fragP
->tc_frag_data
.slot_symbols
[slot
],
11482 fragP
->tc_frag_data
.slot_sub_symbols
[slot
],
11483 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11487 set_expr_symbol_offset
11488 (&tinsn
->tok
[opnum
],
11489 fragP
->tc_frag_data
.slot_symbols
[slot
],
11490 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11497 get_num_stack_text_bytes (IStack
*istack
)
11500 int text_bytes
= 0;
11502 for (i
= 0; i
< istack
->ninsn
; i
++)
11504 TInsn
*tinsn
= &istack
->insn
[i
];
11505 if (tinsn
->insn_type
== ITYPE_INSN
)
11506 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11513 get_num_stack_literal_bytes (IStack
*istack
)
11518 for (i
= 0; i
< istack
->ninsn
; i
++)
11520 TInsn
*tinsn
= &istack
->insn
[i
];
11521 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11528 /* vliw_insn functions. */
11531 xg_init_vinsn (vliw_insn
*v
)
11534 xtensa_isa isa
= xtensa_default_isa
;
11536 xg_clear_vinsn (v
);
11538 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11539 if (v
->insnbuf
== NULL
)
11540 as_fatal (_("out of memory"));
11542 for (i
= 0; i
< MAX_SLOTS
; i
++)
11544 tinsn_init (&v
->slots
[i
]);
11545 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11546 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11547 if (v
->slotbuf
[i
] == NULL
)
11548 as_fatal (_("out of memory"));
11554 xg_clear_vinsn (vliw_insn
*v
)
11557 v
->format
= XTENSA_UNDEFINED
;
11559 v
->inside_bundle
= FALSE
;
11561 if (xt_saved_debug_type
!= DEBUG_NONE
)
11562 debug_type
= xt_saved_debug_type
;
11564 for (i
= 0; i
< MAX_SLOTS
; i
++)
11566 memset (&v
->slots
[i
], 0, sizeof (TInsn
));
11567 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11573 vinsn_has_specific_opcodes (vliw_insn
*v
)
11577 for (i
= 0; i
< v
->num_slots
; i
++)
11579 if (v
->slots
[i
].is_specific_opcode
)
11587 xg_free_vinsn (vliw_insn
*v
)
11590 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11591 for (i
= 0; i
< MAX_SLOTS
; i
++)
11592 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11596 /* Before this is called, we should have
11597 filled out the following fields:
11599 1) the number of operands for each opcode are correct
11600 2) the tinsn in the slots are ITYPE_INSN
11601 3) ONLY the relaxable_ is built
11602 4) All operands are
11603 O_constant, O_symbol
11606 The return value tells whether there are any remaining O_symbols. */
11609 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11612 bfd_boolean record_fixup
)
11614 xtensa_isa isa
= xtensa_default_isa
;
11615 xtensa_format fmt
= vinsn
->format
;
11616 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11618 bfd_boolean has_fixup
= FALSE
;
11620 xtensa_format_encode (isa
, fmt
, insnbuf
);
11622 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11624 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11625 bfd_boolean tinsn_has_fixup
=
11626 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11627 vinsn
->slotbuf
[slot
]);
11629 xtensa_format_set_slot (isa
, fmt
, slot
,
11630 insnbuf
, vinsn
->slotbuf
[slot
]);
11631 /* tinsn_has_fixup tracks if there is a fixup at all.
11632 record_fixup controls globally. I.E., we use this
11633 function from several places, some of which are after
11634 fixups have already been recorded. Finally,
11635 tinsn->record_fixup controls based on the individual ops,
11636 which may or may not need it based on the relaxation
11638 if (tinsn_has_fixup
&& record_fixup
)
11641 xtensa_opcode opcode
= tinsn
->opcode
;
11642 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11645 for (i
= 0; i
< noperands
; i
++)
11647 expressionS
* expr
= &tinsn
->tok
[i
];
11648 switch (expr
->X_op
)
11653 if (get_relaxable_immed (opcode
) == i
)
11655 if (tinsn
->record_fix
|| expr
->X_op
!= O_symbol
)
11657 if (!xg_add_opcode_fix
11658 (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11659 frag_offset
- fragP
->fr_literal
))
11660 as_bad (_("instruction with constant operands does not fit"));
11664 tinsn
->symbol
= expr
->X_add_symbol
;
11665 tinsn
->offset
= expr
->X_add_number
;
11669 as_bad (_("invalid operand %d on '%s'"),
11670 i
, xtensa_opcode_name (isa
, opcode
));
11678 if (get_relaxable_immed (opcode
) == i
)
11680 if (tinsn
->record_fix
)
11681 as_bad (_("invalid subtract operand"));
11684 tinsn
->symbol
= expr
->X_add_symbol
;
11685 tinsn
->sub_symbol
= expr
->X_op_symbol
;
11686 tinsn
->offset
= expr
->X_add_number
;
11690 as_bad (_("invalid operand %d on '%s'"),
11691 i
, xtensa_opcode_name (isa
, opcode
));
11695 as_bad (_("invalid expression for operand %d on '%s'"),
11696 i
, xtensa_opcode_name (isa
, opcode
));
11708 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11710 static xtensa_insnbuf insnbuf
= NULL
;
11711 static xtensa_insnbuf slotbuf
= NULL
;
11714 xtensa_isa isa
= xtensa_default_isa
;
11718 insnbuf
= xtensa_insnbuf_alloc (isa
);
11719 slotbuf
= xtensa_insnbuf_alloc (isa
);
11722 xtensa_insnbuf_from_chars (isa
, insnbuf
, f
, 0);
11723 fmt
= xtensa_format_decode (isa
, insnbuf
);
11724 if (fmt
== XTENSA_UNDEFINED
)
11725 as_fatal (_("cannot decode instruction format"));
11726 vinsn
->format
= fmt
;
11727 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11729 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11731 TInsn
*tinsn
= &vinsn
->slots
[i
];
11732 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11733 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11738 /* Expression utilities. */
11740 /* Return TRUE if the expression is an integer constant. */
11743 expr_is_const (const expressionS
*s
)
11745 return (s
->X_op
== O_constant
);
11749 /* Get the expression constant.
11750 Calling this is illegal if expr_is_const () returns TRUE. */
11753 get_expr_const (const expressionS
*s
)
11755 assert (expr_is_const (s
));
11756 return s
->X_add_number
;
11760 /* Set the expression to a constant value. */
11763 set_expr_const (expressionS
*s
, offsetT val
)
11765 s
->X_op
= O_constant
;
11766 s
->X_add_number
= val
;
11767 s
->X_add_symbol
= NULL
;
11768 s
->X_op_symbol
= NULL
;
11773 expr_is_register (const expressionS
*s
)
11775 return (s
->X_op
== O_register
);
11779 /* Get the expression constant.
11780 Calling this is illegal if expr_is_const () returns TRUE. */
11783 get_expr_register (const expressionS
*s
)
11785 assert (expr_is_register (s
));
11786 return s
->X_add_number
;
11790 /* Set the expression to a symbol + constant offset. */
11793 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11795 s
->X_op
= O_symbol
;
11796 s
->X_add_symbol
= sym
;
11797 s
->X_op_symbol
= NULL
; /* unused */
11798 s
->X_add_number
= offset
;
11802 /* Set the expression to symbol - minus_sym + offset. */
11805 set_expr_symbol_offset_diff (expressionS
*s
,
11807 symbolS
*minus_sym
,
11810 s
->X_op
= O_subtract
;
11811 s
->X_add_symbol
= sym
;
11812 s
->X_op_symbol
= minus_sym
; /* unused */
11813 s
->X_add_number
= offset
;
11817 /* Return TRUE if the two expressions are equal. */
11820 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11822 if (s1
->X_op
!= s2
->X_op
)
11824 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11826 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11828 if (s1
->X_add_number
!= s2
->X_add_number
)
11835 copy_expr (expressionS
*dst
, const expressionS
*src
)
11837 memcpy (dst
, src
, sizeof (expressionS
));
11841 /* Support for the "--rename-section" option. */
11843 struct rename_section_struct
11847 struct rename_section_struct
*next
;
11850 static struct rename_section_struct
*section_rename
;
11853 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11854 entries to the section_rename list. Note: Specifying multiple
11855 renamings separated by colons is not documented and is retained only
11856 for backward compatibility. */
11859 build_section_rename (const char *arg
)
11861 struct rename_section_struct
*r
;
11862 char *this_arg
= NULL
;
11863 char *next_arg
= NULL
;
11865 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11867 char *old_name
, *new_name
;
11871 next_arg
= strchr (this_arg
, ':');
11879 old_name
= this_arg
;
11880 new_name
= strchr (this_arg
, '=');
11882 if (*old_name
== '\0')
11884 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11887 if (!new_name
|| new_name
[1] == '\0')
11889 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11896 /* Check for invalid section renaming. */
11897 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11899 if (strcmp (r
->old_name
, old_name
) == 0)
11900 as_bad (_("section %s renamed multiple times"), old_name
);
11901 if (strcmp (r
->new_name
, new_name
) == 0)
11902 as_bad (_("multiple sections remapped to output section %s"),
11907 r
= (struct rename_section_struct
*)
11908 xmalloc (sizeof (struct rename_section_struct
));
11909 r
->old_name
= xstrdup (old_name
);
11910 r
->new_name
= xstrdup (new_name
);
11911 r
->next
= section_rename
;
11912 section_rename
= r
;
11918 xtensa_section_rename (char *name
)
11920 struct rename_section_struct
*r
= section_rename
;
11922 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11924 if (strcmp (r
->old_name
, name
) == 0)
11925 return r
->new_name
;