1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 /* Maximum width we would pad an unreachable frag to get alignment. */
78 #define UNREACHABLE_MAX_WIDTH 8
80 static vliw_insn cur_vinsn
;
82 unsigned xtensa_num_pipe_stages
;
83 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
85 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
87 /* Some functions are only valid in the front end. This variable
88 allows us to assert that we haven't crossed over into the
90 static bfd_boolean past_xtensa_end
= FALSE
;
92 /* Flags for properties of the last instruction in a segment. */
93 #define FLAG_IS_A0_WRITER 0x1
94 #define FLAG_IS_BAD_LOOPEND 0x2
97 /* We define a special segment names ".literal" to place literals
98 into. The .fini and .init sections are special because they
99 contain code that is moved together by the linker. We give them
100 their own special .fini.literal and .init.literal sections. */
102 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
103 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
104 #define INIT_SECTION_NAME xtensa_section_rename (".init")
105 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
108 /* This type is used for the directive_stack to keep track of the
109 state of the literal collection pools. If lit_prefix is set, it is
110 used to determine the literal section names; otherwise, the literal
111 sections are determined based on the current text section. The
112 lit_seg and lit4_seg fields cache these literal sections, with the
113 current_text_seg field used a tag to indicate whether the cached
116 typedef struct lit_state_struct
119 segT current_text_seg
;
124 static lit_state default_lit_sections
;
127 /* We keep a list of literal segments. The seg_list type is the node
128 for this list. The literal_head pointer is the head of the list,
129 with the literal_head_h dummy node at the start. */
131 typedef struct seg_list_struct
133 struct seg_list_struct
*next
;
137 static seg_list literal_head_h
;
138 static seg_list
*literal_head
= &literal_head_h
;
141 /* Lists of symbols. We keep a list of symbols that label the current
142 instruction, so that we can adjust the symbols when inserting alignment
143 for various instructions. We also keep a list of all the symbols on
144 literals, so that we can fix up those symbols when the literals are
145 later moved into the text sections. */
147 typedef struct sym_list_struct
149 struct sym_list_struct
*next
;
153 static sym_list
*insn_labels
= NULL
;
154 static sym_list
*free_insn_labels
= NULL
;
155 static sym_list
*saved_insn_labels
= NULL
;
157 static sym_list
*literal_syms
;
160 /* Flags to determine whether to prefer const16 or l32r
161 if both options are available. */
162 int prefer_const16
= 0;
165 /* Global flag to indicate when we are emitting literals. */
166 int generating_literals
= 0;
168 /* The following PROPERTY table definitions are copied from
169 <elf/xtensa.h> and must be kept in sync with the code there. */
171 /* Flags in the property tables to specify whether blocks of memory
172 are literals, instructions, data, or unreachable. For
173 instructions, blocks that begin loop targets and branch targets are
174 designated. Blocks that do not allow density, instruction
175 reordering or transformation are also specified. Finally, for
176 branch targets, branch target alignment priority is included.
177 Alignment of the next block is specified in the current block
178 and the size of the current block does not include any fill required
179 to align to the next block. */
181 #define XTENSA_PROP_LITERAL 0x00000001
182 #define XTENSA_PROP_INSN 0x00000002
183 #define XTENSA_PROP_DATA 0x00000004
184 #define XTENSA_PROP_UNREACHABLE 0x00000008
185 /* Instruction only properties at beginning of code. */
186 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
187 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
188 /* Instruction only properties about code. */
189 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
190 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
191 /* Historically, NO_TRANSFORM was a property of instructions,
192 but it should apply to literals under certain circumstances. */
193 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
195 /* Branch target alignment information. This transmits information
196 to the linker optimization about the priority of aligning a
197 particular block for branch target alignment: None, low priority,
198 high priority, or required. These only need to be checked in
199 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
202 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
203 case XTENSA_PROP_BT_ALIGN_NONE:
204 case XTENSA_PROP_BT_ALIGN_LOW:
205 case XTENSA_PROP_BT_ALIGN_HIGH:
206 case XTENSA_PROP_BT_ALIGN_REQUIRE:
208 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
210 /* No branch target alignment. */
211 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
212 /* Low priority branch target alignment. */
213 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
214 /* High priority branch target alignment. */
215 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
216 /* Required branch target alignment. */
217 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
219 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
220 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
221 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
222 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
223 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
226 /* Alignment is specified in the block BEFORE the one that needs
227 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
228 get the required alignment specified as a power of 2. Use
229 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
230 alignment. Be careful of side effects since the SET will evaluate
231 flags twice. Also, note that the SIZE of a block in the property
232 table does not include the alignment size, so the alignment fill
233 must be calculated to determine if two blocks are contiguous.
234 TEXT_ALIGN is not currently implemented but is a placeholder for a
235 possible future implementation. */
237 #define XTENSA_PROP_ALIGN 0x00000800
239 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
241 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
242 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
243 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
244 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
245 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
247 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
250 /* Structure for saving instruction and alignment per-fragment data
251 that will be written to the object file. This structure is
252 equivalent to the actual data that will be written out to the file
253 but is easier to use. We provide a conversion to file flags
254 in frag_flags_to_number. */
256 typedef struct frag_flags_struct frag_flags
;
258 struct frag_flags_struct
260 /* is_literal should only be used after xtensa_move_literals.
261 If you need to check if you are generating a literal fragment,
262 then use the generating_literals global. */
264 unsigned is_literal
: 1;
265 unsigned is_insn
: 1;
266 unsigned is_data
: 1;
267 unsigned is_unreachable
: 1;
269 /* is_specific_opcode implies no_transform. */
270 unsigned is_no_transform
: 1;
274 unsigned is_loop_target
: 1;
275 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
276 unsigned bt_align_priority
: 2;
278 unsigned is_no_density
: 1;
279 /* no_longcalls flag does not need to be placed in the object file. */
281 unsigned is_no_reorder
: 1;
283 /* Uses absolute literal addressing for l32r. */
284 unsigned is_abslit
: 1;
286 unsigned is_align
: 1;
287 unsigned alignment
: 5;
291 /* Structure for saving information about a block of property data
292 for frags that have the same flags. */
293 struct xtensa_block_info_struct
299 struct xtensa_block_info_struct
*next
;
303 /* Structure for saving the current state before emitting literals. */
304 typedef struct emit_state_struct
309 int generating_literals
;
313 /* Opcode placement information */
315 typedef unsigned long long bitfield
;
316 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
317 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
318 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
320 #define MAX_FORMATS 32
322 typedef struct op_placement_info_struct
325 /* A number describing how restrictive the issue is for this
326 opcode. For example, an opcode that fits lots of different
327 formats has a high freedom, as does an opcode that fits
328 only one format but many slots in that format. The most
329 restrictive is the opcode that fits only one slot in one
332 xtensa_format narrowest
;
336 /* formats is a bitfield with the Nth bit set
337 if the opcode fits in the Nth xtensa_format. */
340 /* slots[N]'s Mth bit is set if the op fits in the
341 Mth slot of the Nth xtensa_format. */
342 bitfield slots
[MAX_FORMATS
];
344 /* A count of the number of slots in a given format
345 an op can fit (i.e., the bitcount of the slot field above). */
346 char slots_in_format
[MAX_FORMATS
];
348 } op_placement_info
, *op_placement_info_table
;
350 op_placement_info_table op_placement_table
;
353 /* Extra expression types. */
355 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
356 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
357 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
358 #define O_pcrel O_md4 /* value is a PC-relative offset */
359 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
360 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
361 #define O_tlscall O_md7 /* TLS_CALL relocation */
362 #define O_tpoff O_md8 /* TPOFF relocation */
363 #define O_dtpoff O_md9 /* DTPOFF relocation */
365 struct suffix_reloc_map
369 bfd_reloc_code_real_type reloc
;
370 unsigned char operator;
373 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
375 static struct suffix_reloc_map suffix_relocs
[] =
377 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
378 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
379 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
380 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
381 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
382 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
383 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
384 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
385 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
386 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
400 directive_literal_prefix
,
402 directive_absolute_literals
,
403 directive_last_directive
409 bfd_boolean can_be_negated
;
412 const directive_infoS directive_info
[] =
415 { "literal", FALSE
},
417 { "transform", TRUE
},
418 { "freeregs", FALSE
},
419 { "longcalls", TRUE
},
420 { "literal_prefix", FALSE
},
421 { "schedule", TRUE
},
422 { "absolute-literals", TRUE
}
425 bfd_boolean directive_state
[] =
429 #if !XCHAL_HAVE_DENSITY
434 TRUE
, /* transform */
435 FALSE
, /* freeregs */
436 FALSE
, /* longcalls */
437 FALSE
, /* literal_prefix */
438 FALSE
, /* schedule */
439 #if XSHAL_USE_ABSOLUTE_LITERALS
440 TRUE
/* absolute_literals */
442 FALSE
/* absolute_literals */
447 /* Directive functions. */
449 static void xtensa_begin_directive (int);
450 static void xtensa_end_directive (int);
451 static void xtensa_literal_prefix (void);
452 static void xtensa_literal_position (int);
453 static void xtensa_literal_pseudo (int);
454 static void xtensa_frequency_pseudo (int);
455 static void xtensa_elf_cons (int);
456 static void xtensa_leb128 (int);
458 /* Parsing and Idiom Translation. */
460 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
462 /* Various Other Internal Functions. */
464 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
465 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
466 static void xtensa_mark_literal_pool_location (void);
467 static addressT
get_expanded_loop_offset (xtensa_opcode
);
468 static fragS
*get_literal_pool_location (segT
);
469 static void set_literal_pool_location (segT
, fragS
*);
470 static void xtensa_set_frag_assembly_state (fragS
*);
471 static void finish_vinsn (vliw_insn
*);
472 static bfd_boolean
emit_single_op (TInsn
*);
473 static int total_frag_text_expansion (fragS
*);
475 /* Alignment Functions. */
477 static int get_text_align_power (unsigned);
478 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
479 static int branch_align_power (segT
);
481 /* Helpers for xtensa_relax_frag(). */
483 static long relax_frag_add_nop (fragS
*);
485 /* Accessors for additional per-subsegment information. */
487 static unsigned get_last_insn_flags (segT
, subsegT
);
488 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
489 static float get_subseg_total_freq (segT
, subsegT
);
490 static float get_subseg_target_freq (segT
, subsegT
);
491 static void set_subseg_freq (segT
, subsegT
, float, float);
493 /* Segment list functions. */
495 static void xtensa_move_literals (void);
496 static void xtensa_reorder_segments (void);
497 static void xtensa_switch_to_literal_fragment (emit_state
*);
498 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
499 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
500 static void xtensa_restore_emit_state (emit_state
*);
501 static segT
cache_literal_section (bfd_boolean
);
503 /* Import from elf32-xtensa.c in BFD library. */
505 extern asection
*xtensa_make_property_section (asection
*, const char *);
507 /* op_placement_info functions. */
509 static void init_op_placement_info_table (void);
510 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
511 static int xg_get_single_size (xtensa_opcode
);
512 static xtensa_format
xg_get_single_format (xtensa_opcode
);
513 static int xg_get_single_slot (xtensa_opcode
);
515 /* TInsn and IStack functions. */
517 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
518 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
519 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
520 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
521 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
522 static void tinsn_from_chars (TInsn
*, char *, int);
523 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
524 static int get_num_stack_text_bytes (IStack
*);
525 static int get_num_stack_literal_bytes (IStack
*);
527 /* vliw_insn functions. */
529 static void xg_init_vinsn (vliw_insn
*);
530 static void xg_clear_vinsn (vliw_insn
*);
531 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
532 static void xg_free_vinsn (vliw_insn
*);
533 static bfd_boolean vinsn_to_insnbuf
534 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
535 static void vinsn_from_chars (vliw_insn
*, char *);
537 /* Expression Utilities. */
539 bfd_boolean
expr_is_const (const expressionS
*);
540 offsetT
get_expr_const (const expressionS
*);
541 void set_expr_const (expressionS
*, offsetT
);
542 bfd_boolean
expr_is_register (const expressionS
*);
543 offsetT
get_expr_register (const expressionS
*);
544 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
545 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
546 static void copy_expr (expressionS
*, const expressionS
*);
548 /* Section renaming. */
550 static void build_section_rename (const char *);
553 /* ISA imported from bfd. */
554 extern xtensa_isa xtensa_default_isa
;
556 extern int target_big_endian
;
558 static xtensa_opcode xtensa_addi_opcode
;
559 static xtensa_opcode xtensa_addmi_opcode
;
560 static xtensa_opcode xtensa_call0_opcode
;
561 static xtensa_opcode xtensa_call4_opcode
;
562 static xtensa_opcode xtensa_call8_opcode
;
563 static xtensa_opcode xtensa_call12_opcode
;
564 static xtensa_opcode xtensa_callx0_opcode
;
565 static xtensa_opcode xtensa_callx4_opcode
;
566 static xtensa_opcode xtensa_callx8_opcode
;
567 static xtensa_opcode xtensa_callx12_opcode
;
568 static xtensa_opcode xtensa_const16_opcode
;
569 static xtensa_opcode xtensa_entry_opcode
;
570 static xtensa_opcode xtensa_extui_opcode
;
571 static xtensa_opcode xtensa_movi_opcode
;
572 static xtensa_opcode xtensa_movi_n_opcode
;
573 static xtensa_opcode xtensa_isync_opcode
;
574 static xtensa_opcode xtensa_j_opcode
;
575 static xtensa_opcode xtensa_jx_opcode
;
576 static xtensa_opcode xtensa_l32r_opcode
;
577 static xtensa_opcode xtensa_loop_opcode
;
578 static xtensa_opcode xtensa_loopnez_opcode
;
579 static xtensa_opcode xtensa_loopgtz_opcode
;
580 static xtensa_opcode xtensa_nop_opcode
;
581 static xtensa_opcode xtensa_nop_n_opcode
;
582 static xtensa_opcode xtensa_or_opcode
;
583 static xtensa_opcode xtensa_ret_opcode
;
584 static xtensa_opcode xtensa_ret_n_opcode
;
585 static xtensa_opcode xtensa_retw_opcode
;
586 static xtensa_opcode xtensa_retw_n_opcode
;
587 static xtensa_opcode xtensa_rsr_lcount_opcode
;
588 static xtensa_opcode xtensa_waiti_opcode
;
591 /* Command-line Options. */
593 bfd_boolean use_literal_section
= TRUE
;
594 static bfd_boolean align_targets
= TRUE
;
595 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
596 static bfd_boolean has_a0_b_retw
= FALSE
;
597 static bfd_boolean workaround_a0_b_retw
= FALSE
;
598 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
599 static bfd_boolean workaround_short_loop
= FALSE
;
600 static bfd_boolean maybe_has_short_loop
= FALSE
;
601 static bfd_boolean workaround_close_loop_end
= FALSE
;
602 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
603 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
605 /* When workaround_short_loops is TRUE, all loops with early exits must
606 have at least 3 instructions. workaround_all_short_loops is a modifier
607 to the workaround_short_loop flag. In addition to the
608 workaround_short_loop actions, all straightline loopgtz and loopnez
609 must have at least 3 instructions. */
611 static bfd_boolean workaround_all_short_loops
= FALSE
;
615 xtensa_setup_hw_workarounds (int earliest
, int latest
)
617 if (earliest
> latest
)
618 as_fatal (_("illegal range of target hardware versions"));
620 /* Enable all workarounds for pre-T1050.0 hardware. */
621 if (earliest
< 105000 || latest
< 105000)
623 workaround_a0_b_retw
|= TRUE
;
624 workaround_b_j_loop_end
|= TRUE
;
625 workaround_short_loop
|= TRUE
;
626 workaround_close_loop_end
|= TRUE
;
627 workaround_all_short_loops
|= TRUE
;
628 enforce_three_byte_loop_align
= TRUE
;
635 option_density
= OPTION_MD_BASE
,
642 option_no_link_relax
,
650 option_text_section_literals
,
651 option_no_text_section_literals
,
653 option_absolute_literals
,
654 option_no_absolute_literals
,
656 option_align_targets
,
657 option_no_align_targets
,
659 option_warn_unaligned_targets
,
664 option_workaround_a0_b_retw
,
665 option_no_workaround_a0_b_retw
,
667 option_workaround_b_j_loop_end
,
668 option_no_workaround_b_j_loop_end
,
670 option_workaround_short_loop
,
671 option_no_workaround_short_loop
,
673 option_workaround_all_short_loops
,
674 option_no_workaround_all_short_loops
,
676 option_workaround_close_loop_end
,
677 option_no_workaround_close_loop_end
,
679 option_no_workarounds
,
681 option_rename_section_name
,
684 option_prefer_const16
,
686 option_target_hardware
689 const char *md_shortopts
= "";
691 struct option md_longopts
[] =
693 { "density", no_argument
, NULL
, option_density
},
694 { "no-density", no_argument
, NULL
, option_no_density
},
696 /* Both "relax" and "generics" are deprecated and treated as equivalent
697 to the "transform" option. */
698 { "relax", no_argument
, NULL
, option_relax
},
699 { "no-relax", no_argument
, NULL
, option_no_relax
},
700 { "generics", no_argument
, NULL
, option_generics
},
701 { "no-generics", no_argument
, NULL
, option_no_generics
},
703 { "transform", no_argument
, NULL
, option_transform
},
704 { "no-transform", no_argument
, NULL
, option_no_transform
},
705 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
706 { "no-text-section-literals", no_argument
, NULL
,
707 option_no_text_section_literals
},
708 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
709 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
710 /* This option was changed from -align-target to -target-align
711 because it conflicted with the "-al" option. */
712 { "target-align", no_argument
, NULL
, option_align_targets
},
713 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
714 { "warn-unaligned-targets", no_argument
, NULL
,
715 option_warn_unaligned_targets
},
716 { "longcalls", no_argument
, NULL
, option_longcalls
},
717 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
719 { "no-workaround-a0-b-retw", no_argument
, NULL
,
720 option_no_workaround_a0_b_retw
},
721 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
723 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
724 option_no_workaround_b_j_loop_end
},
725 { "workaround-b-j-loop-end", no_argument
, NULL
,
726 option_workaround_b_j_loop_end
},
728 { "no-workaround-short-loops", no_argument
, NULL
,
729 option_no_workaround_short_loop
},
730 { "workaround-short-loops", no_argument
, NULL
,
731 option_workaround_short_loop
},
733 { "no-workaround-all-short-loops", no_argument
, NULL
,
734 option_no_workaround_all_short_loops
},
735 { "workaround-all-short-loop", no_argument
, NULL
,
736 option_workaround_all_short_loops
},
738 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
739 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
741 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
743 { "no-workaround-close-loop-end", no_argument
, NULL
,
744 option_no_workaround_close_loop_end
},
745 { "workaround-close-loop-end", no_argument
, NULL
,
746 option_workaround_close_loop_end
},
748 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
750 { "link-relax", no_argument
, NULL
, option_link_relax
},
751 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
753 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
755 { NULL
, no_argument
, NULL
, 0 }
758 size_t md_longopts_size
= sizeof md_longopts
;
762 md_parse_option (int c
, char *arg
)
767 as_warn (_("--density option is ignored"));
769 case option_no_density
:
770 as_warn (_("--no-density option is ignored"));
772 case option_link_relax
:
775 case option_no_link_relax
:
778 case option_generics
:
779 as_warn (_("--generics is deprecated; use --transform instead"));
780 return md_parse_option (option_transform
, arg
);
781 case option_no_generics
:
782 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
783 return md_parse_option (option_no_transform
, arg
);
785 as_warn (_("--relax is deprecated; use --transform instead"));
786 return md_parse_option (option_transform
, arg
);
787 case option_no_relax
:
788 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
789 return md_parse_option (option_no_transform
, arg
);
790 case option_longcalls
:
791 directive_state
[directive_longcalls
] = TRUE
;
793 case option_no_longcalls
:
794 directive_state
[directive_longcalls
] = FALSE
;
796 case option_text_section_literals
:
797 use_literal_section
= FALSE
;
799 case option_no_text_section_literals
:
800 use_literal_section
= TRUE
;
802 case option_absolute_literals
:
803 if (!absolute_literals_supported
)
805 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
808 directive_state
[directive_absolute_literals
] = TRUE
;
810 case option_no_absolute_literals
:
811 directive_state
[directive_absolute_literals
] = FALSE
;
814 case option_workaround_a0_b_retw
:
815 workaround_a0_b_retw
= TRUE
;
817 case option_no_workaround_a0_b_retw
:
818 workaround_a0_b_retw
= FALSE
;
820 case option_workaround_b_j_loop_end
:
821 workaround_b_j_loop_end
= TRUE
;
823 case option_no_workaround_b_j_loop_end
:
824 workaround_b_j_loop_end
= FALSE
;
827 case option_workaround_short_loop
:
828 workaround_short_loop
= TRUE
;
830 case option_no_workaround_short_loop
:
831 workaround_short_loop
= FALSE
;
834 case option_workaround_all_short_loops
:
835 workaround_all_short_loops
= TRUE
;
837 case option_no_workaround_all_short_loops
:
838 workaround_all_short_loops
= FALSE
;
841 case option_workaround_close_loop_end
:
842 workaround_close_loop_end
= TRUE
;
844 case option_no_workaround_close_loop_end
:
845 workaround_close_loop_end
= FALSE
;
848 case option_no_workarounds
:
849 workaround_a0_b_retw
= FALSE
;
850 workaround_b_j_loop_end
= FALSE
;
851 workaround_short_loop
= FALSE
;
852 workaround_all_short_loops
= FALSE
;
853 workaround_close_loop_end
= FALSE
;
856 case option_align_targets
:
857 align_targets
= TRUE
;
859 case option_no_align_targets
:
860 align_targets
= FALSE
;
863 case option_warn_unaligned_targets
:
864 warn_unaligned_branch_targets
= TRUE
;
867 case option_rename_section_name
:
868 build_section_rename (arg
);
872 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
873 should be emitted or not. FIXME: Not implemented. */
876 case option_prefer_l32r
:
878 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
882 case option_prefer_const16
:
884 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
888 case option_target_hardware
:
890 int earliest
, latest
= 0;
891 if (*arg
== 0 || *arg
== '-')
892 as_fatal (_("invalid target hardware version"));
894 earliest
= strtol (arg
, &arg
, 0);
898 else if (*arg
== '-')
901 as_fatal (_("invalid target hardware version"));
902 latest
= strtol (arg
, &arg
, 0);
905 as_fatal (_("invalid target hardware version"));
907 xtensa_setup_hw_workarounds (earliest
, latest
);
911 case option_transform
:
912 /* This option has no affect other than to use the defaults,
913 which are already set. */
916 case option_no_transform
:
917 /* This option turns off all transformations of any kind.
918 However, because we want to preserve the state of other
919 directives, we only change its own field. Thus, before
920 you perform any transformation, always check if transform
921 is available. If you use the functions we provide for this
922 purpose, you will be ok. */
923 directive_state
[directive_transform
] = FALSE
;
933 md_show_usage (FILE *stream
)
937 --[no-]text-section-literals\n\
938 [Do not] put literals in the text section\n\
939 --[no-]absolute-literals\n\
940 [Do not] default to use non-PC-relative literals\n\
941 --[no-]target-align [Do not] try to align branch targets\n\
942 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
943 --[no-]transform [Do not] transform instructions\n\
944 --rename-section old=new Rename section 'old' to 'new'\n", stream
);
948 /* Functions related to the list of current label symbols. */
951 xtensa_add_insn_label (symbolS
*sym
)
955 if (!free_insn_labels
)
956 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
959 l
= free_insn_labels
;
960 free_insn_labels
= l
->next
;
964 l
->next
= insn_labels
;
970 xtensa_clear_insn_labels (void)
974 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
982 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
986 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
988 symbolS
*lit_sym
= lit
->sym
;
989 S_SET_VALUE (lit_sym
, new_offset
);
990 symbol_set_frag (lit_sym
, new_frag
);
995 /* Directive data and functions. */
997 typedef struct state_stackS_struct
999 directiveE directive
;
1000 bfd_boolean negated
;
1001 bfd_boolean old_state
;
1005 struct state_stackS_struct
*prev
;
1008 state_stackS
*directive_state_stack
;
1010 const pseudo_typeS md_pseudo_table
[] =
1012 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1013 { "literal_position", xtensa_literal_position
, 0 },
1014 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1015 { "long", xtensa_elf_cons
, 4 },
1016 { "word", xtensa_elf_cons
, 4 },
1017 { "4byte", xtensa_elf_cons
, 4 },
1018 { "short", xtensa_elf_cons
, 2 },
1019 { "2byte", xtensa_elf_cons
, 2 },
1020 { "sleb128", xtensa_leb128
, 1},
1021 { "uleb128", xtensa_leb128
, 0},
1022 { "begin", xtensa_begin_directive
, 0 },
1023 { "end", xtensa_end_directive
, 0 },
1024 { "literal", xtensa_literal_pseudo
, 0 },
1025 { "frequency", xtensa_frequency_pseudo
, 0 },
1031 use_transform (void)
1033 /* After md_end, you should be checking frag by frag, rather
1034 than state directives. */
1035 assert (!past_xtensa_end
);
1036 return directive_state
[directive_transform
];
1041 do_align_targets (void)
1043 /* Do not use this function after md_end; just look at align_targets
1044 instead. There is no target-align directive, so alignment is either
1045 enabled for all frags or not done at all. */
1046 assert (!past_xtensa_end
);
1047 return align_targets
&& use_transform ();
1052 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1056 state_stackS
*stack
= (state_stackS
*) xmalloc (sizeof (state_stackS
));
1058 as_where (&file
, &line
);
1060 stack
->directive
= directive
;
1061 stack
->negated
= negated
;
1062 stack
->old_state
= directive_state
[directive
];
1065 stack
->datum
= datum
;
1066 stack
->prev
= directive_state_stack
;
1067 directive_state_stack
= stack
;
1069 directive_state
[directive
] = !negated
;
1074 directive_pop (directiveE
*directive
,
1075 bfd_boolean
*negated
,
1080 state_stackS
*top
= directive_state_stack
;
1082 if (!directive_state_stack
)
1084 as_bad (_("unmatched end directive"));
1085 *directive
= directive_none
;
1089 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1090 *directive
= top
->directive
;
1091 *negated
= top
->negated
;
1094 *datum
= top
->datum
;
1095 directive_state_stack
= top
->prev
;
1101 directive_balance (void)
1103 while (directive_state_stack
)
1105 directiveE directive
;
1106 bfd_boolean negated
;
1111 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1112 as_warn_where ((char *) file
, line
,
1113 _(".begin directive with no matching .end directive"));
1119 inside_directive (directiveE dir
)
1121 state_stackS
*top
= directive_state_stack
;
1123 while (top
&& top
->directive
!= dir
)
1126 return (top
!= NULL
);
1131 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1135 char *directive_string
;
1137 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1142 input_line_pointer
+= 3;
1145 len
= strspn (input_line_pointer
,
1146 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1148 /* This code is a hack to make .begin [no-][generics|relax] exactly
1149 equivalent to .begin [no-]transform. We should remove it when
1150 we stop accepting those options. */
1152 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1154 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1155 directive_string
= "transform";
1157 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1159 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1160 directive_string
= "transform";
1163 directive_string
= input_line_pointer
;
1165 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1167 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1169 input_line_pointer
+= len
;
1170 *directive
= (directiveE
) i
;
1171 if (*negated
&& !directive_info
[i
].can_be_negated
)
1172 as_bad (_("directive %s cannot be negated"),
1173 directive_info
[i
].name
);
1178 as_bad (_("unknown directive"));
1179 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1184 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1186 directiveE directive
;
1187 bfd_boolean negated
;
1191 get_directive (&directive
, &negated
);
1192 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1194 discard_rest_of_line ();
1198 if (cur_vinsn
.inside_bundle
)
1199 as_bad (_("directives are not valid inside bundles"));
1203 case directive_literal
:
1204 if (!inside_directive (directive_literal
))
1206 /* Previous labels go with whatever follows this directive, not with
1207 the literal, so save them now. */
1208 saved_insn_labels
= insn_labels
;
1211 as_warn (_(".begin literal is deprecated; use .literal instead"));
1212 state
= (emit_state
*) xmalloc (sizeof (emit_state
));
1213 xtensa_switch_to_literal_fragment (state
);
1214 directive_push (directive_literal
, negated
, state
);
1217 case directive_literal_prefix
:
1218 /* Have to flush pending output because a movi relaxed to an l32r
1219 might produce a literal. */
1220 md_flush_pending_output ();
1221 /* Check to see if the current fragment is a literal
1222 fragment. If it is, then this operation is not allowed. */
1223 if (generating_literals
)
1225 as_bad (_("cannot set literal_prefix inside literal fragment"));
1229 /* Allocate the literal state for this section and push
1230 onto the directive stack. */
1231 ls
= xmalloc (sizeof (lit_state
));
1234 *ls
= default_lit_sections
;
1235 directive_push (directive_literal_prefix
, negated
, ls
);
1237 /* Process the new prefix. */
1238 xtensa_literal_prefix ();
1241 case directive_freeregs
:
1242 /* This information is currently unused, but we'll accept the statement
1243 and just discard the rest of the line. This won't check the syntax,
1244 but it will accept every correct freeregs directive. */
1245 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1246 directive_push (directive_freeregs
, negated
, 0);
1249 case directive_schedule
:
1250 md_flush_pending_output ();
1251 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1252 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1253 directive_push (directive_schedule
, negated
, 0);
1254 xtensa_set_frag_assembly_state (frag_now
);
1257 case directive_density
:
1258 as_warn (_(".begin [no-]density is ignored"));
1261 case directive_absolute_literals
:
1262 md_flush_pending_output ();
1263 if (!absolute_literals_supported
&& !negated
)
1265 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1268 xtensa_set_frag_assembly_state (frag_now
);
1269 directive_push (directive
, negated
, 0);
1273 md_flush_pending_output ();
1274 xtensa_set_frag_assembly_state (frag_now
);
1275 directive_push (directive
, negated
, 0);
1279 demand_empty_rest_of_line ();
1284 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1286 directiveE begin_directive
, end_directive
;
1287 bfd_boolean begin_negated
, end_negated
;
1291 emit_state
**state_ptr
;
1294 if (cur_vinsn
.inside_bundle
)
1295 as_bad (_("directives are not valid inside bundles"));
1297 get_directive (&end_directive
, &end_negated
);
1299 md_flush_pending_output ();
1301 switch (end_directive
)
1303 case (directiveE
) XTENSA_UNDEFINED
:
1304 discard_rest_of_line ();
1307 case directive_density
:
1308 as_warn (_(".end [no-]density is ignored"));
1309 demand_empty_rest_of_line ();
1312 case directive_absolute_literals
:
1313 if (!absolute_literals_supported
&& !end_negated
)
1315 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1316 demand_empty_rest_of_line ();
1325 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1326 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1327 (const void **) state_ptr
);
1329 if (begin_directive
!= directive_none
)
1331 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1333 as_bad (_("does not match begin %s%s at %s:%d"),
1334 begin_negated
? "no-" : "",
1335 directive_info
[begin_directive
].name
, file
, line
);
1339 switch (end_directive
)
1341 case directive_literal
:
1342 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1343 xtensa_restore_emit_state (state
);
1344 xtensa_set_frag_assembly_state (frag_now
);
1346 if (!inside_directive (directive_literal
))
1348 /* Restore the list of current labels. */
1349 xtensa_clear_insn_labels ();
1350 insn_labels
= saved_insn_labels
;
1354 case directive_literal_prefix
:
1355 /* Restore the default collection sections from saved state. */
1356 s
= (lit_state
*) state
;
1358 default_lit_sections
= *s
;
1360 /* Free the state storage. */
1361 free (s
->lit_prefix
);
1365 case directive_schedule
:
1366 case directive_freeregs
:
1370 xtensa_set_frag_assembly_state (frag_now
);
1376 demand_empty_rest_of_line ();
1380 /* Place an aligned literal fragment at the current location. */
1383 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1385 md_flush_pending_output ();
1387 if (inside_directive (directive_literal
))
1388 as_warn (_(".literal_position inside literal directive; ignoring"));
1389 xtensa_mark_literal_pool_location ();
1391 demand_empty_rest_of_line ();
1392 xtensa_clear_insn_labels ();
1396 /* Support .literal label, expr, ... */
1399 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1402 char *p
, *base_name
;
1406 if (inside_directive (directive_literal
))
1408 as_bad (_(".literal not allowed inside .begin literal region"));
1409 ignore_rest_of_line ();
1413 md_flush_pending_output ();
1415 /* Previous labels go with whatever follows this directive, not with
1416 the literal, so save them now. */
1417 saved_insn_labels
= insn_labels
;
1420 /* If we are using text-section literals, then this is the right value... */
1423 base_name
= input_line_pointer
;
1425 xtensa_switch_to_literal_fragment (&state
);
1427 /* ...but if we aren't using text-section-literals, then we
1428 need to put them in the section we just switched to. */
1429 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1432 /* All literals are aligned to four-byte boundaries. */
1433 frag_align (2, 0, 0);
1434 record_alignment (now_seg
, 2);
1436 c
= get_symbol_end ();
1437 /* Just after name is now '\0'. */
1438 p
= input_line_pointer
;
1442 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1444 as_bad (_("expected comma or colon after symbol name; "
1445 "rest of line ignored"));
1446 ignore_rest_of_line ();
1447 xtensa_restore_emit_state (&state
);
1455 input_line_pointer
++; /* skip ',' or ':' */
1457 xtensa_elf_cons (4);
1459 xtensa_restore_emit_state (&state
);
1461 /* Restore the list of current labels. */
1462 xtensa_clear_insn_labels ();
1463 insn_labels
= saved_insn_labels
;
1468 xtensa_literal_prefix (void)
1473 /* Parse the new prefix from the input_line_pointer. */
1475 len
= strspn (input_line_pointer
,
1476 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1477 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1479 /* Get a null-terminated copy of the name. */
1480 name
= xmalloc (len
+ 1);
1482 strncpy (name
, input_line_pointer
, len
);
1485 /* Skip the name in the input line. */
1486 input_line_pointer
+= len
;
1488 default_lit_sections
.lit_prefix
= name
;
1490 /* Clear cached literal sections, since the prefix has changed. */
1491 default_lit_sections
.lit_seg
= NULL
;
1492 default_lit_sections
.lit4_seg
= NULL
;
1496 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1499 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1501 float fall_through_f
, target_f
;
1503 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1504 if (fall_through_f
< 0)
1506 as_bad (_("fall through frequency must be greater than 0"));
1507 ignore_rest_of_line ();
1511 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1514 as_bad (_("branch target frequency must be greater than 0"));
1515 ignore_rest_of_line ();
1519 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1521 demand_empty_rest_of_line ();
1525 /* Like normal .long/.short/.word, except support @plt, etc.
1526 Clobbers input_line_pointer, checks end-of-line. */
1529 xtensa_elf_cons (int nbytes
)
1532 bfd_reloc_code_real_type reloc
;
1534 md_flush_pending_output ();
1536 if (cur_vinsn
.inside_bundle
)
1537 as_bad (_("directives are not valid inside bundles"));
1539 if (is_it_end_of_statement ())
1541 demand_empty_rest_of_line ();
1548 if (exp
.X_op
== O_symbol
1549 && *input_line_pointer
== '@'
1550 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1553 reloc_howto_type
*reloc_howto
=
1554 bfd_reloc_type_lookup (stdoutput
, reloc
);
1556 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1557 as_bad (_("unsupported relocation"));
1558 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1559 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1560 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1561 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1562 as_bad (_("opcode-specific %s relocation used outside "
1563 "an instruction"), reloc_howto
->name
);
1564 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1565 as_bad (_("%s relocations do not fit in %d bytes"),
1566 reloc_howto
->name
, nbytes
);
1567 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1568 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1569 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1570 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1573 char *p
= frag_more ((int) nbytes
);
1574 xtensa_set_frag_assembly_state (frag_now
);
1575 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1576 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1581 xtensa_set_frag_assembly_state (frag_now
);
1582 emit_expr (&exp
, (unsigned int) nbytes
);
1585 while (*input_line_pointer
++ == ',');
1587 input_line_pointer
--; /* Put terminator back into stream. */
1588 demand_empty_rest_of_line ();
1591 static bfd_boolean is_leb128_expr
;
1594 xtensa_leb128 (int sign
)
1596 is_leb128_expr
= TRUE
;
1598 is_leb128_expr
= FALSE
;
1602 /* Parsing and Idiom Translation. */
1604 /* Parse @plt, etc. and return the desired relocation. */
1605 static bfd_reloc_code_real_type
1606 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1613 struct suffix_reloc_map
*ptr
;
1616 return BFD_RELOC_NONE
;
1618 for (ch
= *str
, str2
= ident
;
1619 (str2
< ident
+ sizeof (ident
) - 1
1620 && (ISALNUM (ch
) || ch
== '@'));
1623 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1630 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1631 if (ch
== ptr
->suffix
[0]
1632 && len
== ptr
->length
1633 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1635 /* Now check for "identifier@suffix+constant". */
1636 if (*str
== '-' || *str
== '+')
1638 char *orig_line
= input_line_pointer
;
1639 expressionS new_exp
;
1641 input_line_pointer
= str
;
1642 expression (&new_exp
);
1643 if (new_exp
.X_op
== O_constant
)
1645 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1646 str
= input_line_pointer
;
1649 if (&input_line_pointer
!= str_p
)
1650 input_line_pointer
= orig_line
;
1657 return BFD_RELOC_UNUSED
;
1661 /* Find the matching operator type. */
1662 static unsigned char
1663 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1665 struct suffix_reloc_map
*sfx
;
1666 unsigned char operator = (unsigned char) -1;
1668 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1670 if (sfx
->reloc
== reloc
)
1672 operator = sfx
->operator;
1676 assert (operator != (unsigned char) -1);
1681 /* Find the matching reloc type. */
1682 static bfd_reloc_code_real_type
1683 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1685 struct suffix_reloc_map
*sfx
;
1686 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1688 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1690 if (sfx
->operator == operator)
1699 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1700 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1701 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1702 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1705 if (reloc
== BFD_RELOC_UNUSED
)
1706 return BFD_RELOC_32
;
1713 expression_end (const char *name
)
1736 #define ERROR_REG_NUM ((unsigned) -1)
1739 tc_get_register (const char *prefix
)
1742 const char *next_expr
;
1743 const char *old_line_pointer
;
1746 old_line_pointer
= input_line_pointer
;
1748 if (*input_line_pointer
== '$')
1749 ++input_line_pointer
;
1751 /* Accept "sp" as a synonym for "a1". */
1752 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1753 && expression_end (input_line_pointer
+ 2))
1755 input_line_pointer
+= 2;
1756 return 1; /* AR[1] */
1759 while (*input_line_pointer
++ == *prefix
++)
1761 --input_line_pointer
;
1766 as_bad (_("bad register name: %s"), old_line_pointer
);
1767 return ERROR_REG_NUM
;
1770 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1772 as_bad (_("bad register number: %s"), input_line_pointer
);
1773 return ERROR_REG_NUM
;
1778 while (ISDIGIT ((int) *input_line_pointer
))
1779 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1781 if (!(next_expr
= expression_end (input_line_pointer
)))
1783 as_bad (_("bad register name: %s"), old_line_pointer
);
1784 return ERROR_REG_NUM
;
1787 input_line_pointer
= (char *) next_expr
;
1794 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1796 xtensa_isa isa
= xtensa_default_isa
;
1798 /* Check if this is an immediate operand. */
1799 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1801 bfd_reloc_code_real_type reloc
;
1802 segT t
= expression (tok
);
1803 if (t
== absolute_section
1804 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1806 assert (tok
->X_op
== O_constant
);
1807 tok
->X_op
= O_symbol
;
1808 tok
->X_add_symbol
= &abs_symbol
;
1811 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1812 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1817 case BFD_RELOC_LO16
:
1818 if (tok
->X_op
== O_constant
)
1820 tok
->X_add_number
&= 0xffff;
1824 case BFD_RELOC_HI16
:
1825 if (tok
->X_op
== O_constant
)
1827 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1831 case BFD_RELOC_UNUSED
:
1832 as_bad (_("unsupported relocation"));
1834 case BFD_RELOC_32_PCREL
:
1835 as_bad (_("pcrel relocation not allowed in an instruction"));
1840 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1845 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1846 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1848 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1851 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1852 as_bad (_("register number out of range"));
1855 tok
->X_op
= O_register
;
1856 tok
->X_add_symbol
= 0;
1857 tok
->X_add_number
= reg
;
1862 /* Split up the arguments for an opcode or pseudo-op. */
1865 tokenize_arguments (char **args
, char *str
)
1867 char *old_input_line_pointer
;
1868 bfd_boolean saw_comma
= FALSE
;
1869 bfd_boolean saw_arg
= FALSE
;
1870 bfd_boolean saw_colon
= FALSE
;
1872 char *arg_end
, *arg
;
1875 /* Save and restore input_line_pointer around this function. */
1876 old_input_line_pointer
= input_line_pointer
;
1877 input_line_pointer
= str
;
1879 while (*input_line_pointer
)
1882 switch (*input_line_pointer
)
1889 input_line_pointer
++;
1890 if (saw_comma
|| saw_colon
|| !saw_arg
)
1896 input_line_pointer
++;
1897 if (saw_comma
|| saw_colon
|| !saw_arg
)
1903 if (!saw_comma
&& !saw_colon
&& saw_arg
)
1906 arg_end
= input_line_pointer
+ 1;
1907 while (!expression_end (arg_end
))
1910 arg_len
= arg_end
- input_line_pointer
;
1911 arg
= (char *) xmalloc ((saw_colon
? 1 : 0) + arg_len
+ 1);
1912 args
[num_args
] = arg
;
1916 strncpy (arg
, input_line_pointer
, arg_len
);
1917 arg
[arg_len
] = '\0';
1919 input_line_pointer
= arg_end
;
1929 if (saw_comma
|| saw_colon
)
1931 input_line_pointer
= old_input_line_pointer
;
1936 as_bad (_("extra comma"));
1938 as_bad (_("extra colon"));
1940 as_bad (_("missing argument"));
1942 as_bad (_("missing comma or colon"));
1943 input_line_pointer
= old_input_line_pointer
;
1948 /* Parse the arguments to an opcode. Return TRUE on error. */
1951 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
1953 expressionS
*tok
, *last_tok
;
1954 xtensa_opcode opcode
= insn
->opcode
;
1955 bfd_boolean had_error
= TRUE
;
1956 xtensa_isa isa
= xtensa_default_isa
;
1957 int n
, num_regs
= 0;
1958 int opcode_operand_count
;
1959 int opnd_cnt
, last_opnd_cnt
;
1960 unsigned int next_reg
= 0;
1961 char *old_input_line_pointer
;
1963 if (insn
->insn_type
== ITYPE_LITERAL
)
1964 opcode_operand_count
= 1;
1966 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
1969 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
1971 /* Save and restore input_line_pointer around this function. */
1972 old_input_line_pointer
= input_line_pointer
;
1978 /* Skip invisible operands. */
1979 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
1985 for (n
= 0; n
< num_args
; n
++)
1987 input_line_pointer
= arg_strings
[n
];
1988 if (*input_line_pointer
== ':')
1990 xtensa_regfile opnd_rf
;
1991 input_line_pointer
++;
1994 assert (opnd_cnt
> 0);
1996 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
1998 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
1999 as_warn (_("incorrect register number, ignoring"));
2004 if (opnd_cnt
>= opcode_operand_count
)
2006 as_warn (_("too many arguments"));
2009 assert (opnd_cnt
< MAX_INSN_ARGS
);
2011 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2012 next_reg
= tok
->X_add_number
+ 1;
2014 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2016 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2018 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2019 /* minus 1 because we are seeing one right now */
2025 last_opnd_cnt
= opnd_cnt
;
2032 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2036 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2039 insn
->ntok
= tok
- insn
->tok
;
2043 input_line_pointer
= old_input_line_pointer
;
2049 get_invisible_operands (TInsn
*insn
)
2051 xtensa_isa isa
= xtensa_default_isa
;
2052 static xtensa_insnbuf slotbuf
= NULL
;
2054 xtensa_opcode opc
= insn
->opcode
;
2055 int slot
, opnd
, fmt_found
;
2059 slotbuf
= xtensa_insnbuf_alloc (isa
);
2061 /* Find format/slot where this can be encoded. */
2064 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2066 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2068 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2074 if (fmt_found
) break;
2079 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2083 /* First encode all the visible operands
2084 (to deal with shared field operands). */
2085 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2087 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2088 && (insn
->tok
[opnd
].X_op
== O_register
2089 || insn
->tok
[opnd
].X_op
== O_constant
))
2091 val
= insn
->tok
[opnd
].X_add_number
;
2092 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2093 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2097 /* Then pull out the values for the invisible ones. */
2098 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2100 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2102 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2103 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2104 insn
->tok
[opnd
].X_add_number
= val
;
2105 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2106 insn
->tok
[opnd
].X_op
= O_register
;
2108 insn
->tok
[opnd
].X_op
= O_constant
;
2117 xg_reverse_shift_count (char **cnt_argp
)
2119 char *cnt_arg
, *new_arg
;
2120 cnt_arg
= *cnt_argp
;
2122 /* replace the argument with "31-(argument)" */
2123 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2124 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2127 *cnt_argp
= new_arg
;
2131 /* If "arg" is a constant expression, return non-zero with the value
2135 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2138 char *save_ptr
= input_line_pointer
;
2140 input_line_pointer
= arg
;
2142 input_line_pointer
= save_ptr
;
2144 if (exp
.X_op
== O_constant
)
2146 *valp
= exp
.X_add_number
;
2155 xg_replace_opname (char **popname
, char *newop
)
2158 *popname
= (char *) xmalloc (strlen (newop
) + 1);
2159 strcpy (*popname
, newop
);
2164 xg_check_num_args (int *pnum_args
,
2169 int num_args
= *pnum_args
;
2171 if (num_args
< expected_num
)
2173 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2174 num_args
, opname
, expected_num
);
2178 if (num_args
> expected_num
)
2180 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2181 num_args
, opname
, expected_num
);
2182 while (num_args
-- > expected_num
)
2184 free (arg_strings
[num_args
]);
2185 arg_strings
[num_args
] = 0;
2187 *pnum_args
= expected_num
;
2195 /* If the register is not specified as part of the opcode,
2196 then get it from the operand and move it to the opcode. */
2199 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2201 xtensa_isa isa
= xtensa_default_isa
;
2203 char *opname
, *new_opname
;
2204 const char *sr_name
;
2205 int is_user
, is_write
;
2210 is_user
= (opname
[1] == 'u');
2211 is_write
= (opname
[0] == 'w');
2213 /* Opname == [rw]ur or [rwx]sr... */
2215 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2218 /* Check if the argument is a symbolic register name. */
2219 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2220 /* Handle WSR to "INTSET" as a special case. */
2221 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2222 && !strcasecmp (arg_strings
[1], "intset"))
2223 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2224 if (sr
== XTENSA_UNDEFINED
2225 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2227 /* Maybe it's a register number.... */
2229 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2231 as_bad (_("invalid register '%s' for '%s' instruction"),
2232 arg_strings
[1], opname
);
2235 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2236 if (sr
== XTENSA_UNDEFINED
)
2238 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2239 (long) val
, opname
);
2244 /* Remove the last argument, which is now part of the opcode. */
2245 free (arg_strings
[1]);
2249 /* Translate the opcode. */
2250 sr_name
= xtensa_sysreg_name (isa
, sr
);
2251 /* Another special case for "WSR.INTSET".... */
2252 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2254 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2255 sprintf (new_opname
, "%s.%s", *popname
, sr_name
);
2257 *popname
= new_opname
;
2264 xtensa_translate_old_userreg_ops (char **popname
)
2266 xtensa_isa isa
= xtensa_default_isa
;
2268 char *opname
, *new_opname
;
2269 const char *sr_name
;
2270 bfd_boolean has_underbar
= FALSE
;
2273 if (opname
[0] == '_')
2275 has_underbar
= TRUE
;
2279 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2280 if (sr
!= XTENSA_UNDEFINED
)
2282 /* The new default name ("nnn") is different from the old default
2283 name ("URnnn"). The old default is handled below, and we don't
2284 want to recognize [RW]nnn, so do nothing if the name is the (new)
2286 static char namebuf
[10];
2287 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2288 if (strcmp (namebuf
, opname
+ 1) == 0)
2296 /* Only continue if the reg name is "URnnn". */
2297 if (opname
[1] != 'u' || opname
[2] != 'r')
2299 val
= strtoul (opname
+ 3, &end
, 10);
2303 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2304 if (sr
== XTENSA_UNDEFINED
)
2306 as_bad (_("invalid register number (%ld) for '%s'"),
2307 (long) val
, opname
);
2312 /* Translate the opcode. */
2313 sr_name
= xtensa_sysreg_name (isa
, sr
);
2314 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2315 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2316 opname
[0], sr_name
);
2318 *popname
= new_opname
;
2325 xtensa_translate_zero_immed (char *old_op
,
2335 assert (opname
[0] != '_');
2337 if (strcmp (opname
, old_op
) != 0)
2340 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2342 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2344 xg_replace_opname (popname
, new_op
);
2345 free (arg_strings
[1]);
2346 arg_strings
[1] = arg_strings
[2];
2355 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2356 Returns non-zero if an error was found. */
2359 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2361 char *opname
= *popname
;
2362 bfd_boolean has_underbar
= FALSE
;
2366 has_underbar
= TRUE
;
2370 if (strcmp (opname
, "mov") == 0)
2372 if (use_transform () && !has_underbar
&& density_supported
)
2373 xg_replace_opname (popname
, "mov.n");
2376 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2378 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2379 arg_strings
[2] = (char *) xmalloc (strlen (arg_strings
[1]) + 1);
2380 strcpy (arg_strings
[2], arg_strings
[1]);
2386 if (strcmp (opname
, "bbsi.l") == 0)
2388 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2390 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2391 if (target_big_endian
)
2392 xg_reverse_shift_count (&arg_strings
[1]);
2396 if (strcmp (opname
, "bbci.l") == 0)
2398 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2400 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2401 if (target_big_endian
)
2402 xg_reverse_shift_count (&arg_strings
[1]);
2406 /* Don't do anything special with NOPs inside FLIX instructions. They
2407 are handled elsewhere. Real NOP instructions are always available
2408 in configurations with FLIX, so this should never be an issue but
2409 check for it anyway. */
2410 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2411 && strcmp (opname
, "nop") == 0)
2413 if (use_transform () && !has_underbar
&& density_supported
)
2414 xg_replace_opname (popname
, "nop.n");
2417 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2419 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2420 arg_strings
[0] = (char *) xmalloc (3);
2421 arg_strings
[1] = (char *) xmalloc (3);
2422 arg_strings
[2] = (char *) xmalloc (3);
2423 strcpy (arg_strings
[0], "a1");
2424 strcpy (arg_strings
[1], "a1");
2425 strcpy (arg_strings
[2], "a1");
2431 /* Recognize [RW]UR and [RWX]SR. */
2432 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2433 && (opname
[1] == 'u' || opname
[1] == 's'))
2434 || (opname
[0] == 'x' && opname
[1] == 's'))
2436 && opname
[3] == '\0')
2437 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2439 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2440 [RW]<name> if <name> is the non-default name of a user register. */
2441 if ((opname
[0] == 'r' || opname
[0] == 'w')
2442 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2443 return xtensa_translate_old_userreg_ops (popname
);
2445 /* Relax branches that don't allow comparisons against an immediate value
2446 of zero to the corresponding branches with implicit zero immediates. */
2447 if (!has_underbar
&& use_transform ())
2449 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2450 pnum_args
, arg_strings
))
2453 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2454 pnum_args
, arg_strings
))
2457 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2458 pnum_args
, arg_strings
))
2461 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2462 pnum_args
, arg_strings
))
2470 /* Functions for dealing with the Xtensa ISA. */
2472 /* Currently the assembler only allows us to use a single target per
2473 fragment. Because of this, only one operand for a given
2474 instruction may be symbolic. If there is a PC-relative operand,
2475 the last one is chosen. Otherwise, the result is the number of the
2476 last immediate operand, and if there are none of those, we fail and
2480 get_relaxable_immed (xtensa_opcode opcode
)
2482 int last_immed
= -1;
2485 if (opcode
== XTENSA_UNDEFINED
)
2488 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2489 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2491 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2493 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2495 if (last_immed
== -1
2496 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2503 static xtensa_opcode
2504 get_opcode_from_buf (const char *buf
, int slot
)
2506 static xtensa_insnbuf insnbuf
= NULL
;
2507 static xtensa_insnbuf slotbuf
= NULL
;
2508 xtensa_isa isa
= xtensa_default_isa
;
2513 insnbuf
= xtensa_insnbuf_alloc (isa
);
2514 slotbuf
= xtensa_insnbuf_alloc (isa
);
2517 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2518 fmt
= xtensa_format_decode (isa
, insnbuf
);
2519 if (fmt
== XTENSA_UNDEFINED
)
2520 return XTENSA_UNDEFINED
;
2522 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2523 return XTENSA_UNDEFINED
;
2525 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2526 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2530 #ifdef TENSILICA_DEBUG
2532 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2535 xtensa_print_insn_table (void)
2537 int num_opcodes
, num_operands
;
2538 xtensa_opcode opcode
;
2539 xtensa_isa isa
= xtensa_default_isa
;
2541 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2542 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2545 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2546 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2547 for (opn
= 0; opn
< num_operands
; opn
++)
2549 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2551 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2553 xtensa_regfile opnd_rf
=
2554 xtensa_operand_regfile (isa
, opcode
, opn
);
2555 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2557 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2558 fputs ("[lLr] ", stderr
);
2560 fputs ("i ", stderr
);
2562 fprintf (stderr
, "\n");
2568 print_vliw_insn (xtensa_insnbuf vbuf
)
2570 xtensa_isa isa
= xtensa_default_isa
;
2571 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2572 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2575 fprintf (stderr
, "format = %d\n", f
);
2577 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2579 xtensa_opcode opcode
;
2583 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2584 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2585 opname
= xtensa_opcode_name (isa
, opcode
);
2587 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2588 fprintf (stderr
, " operands = ");
2590 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2594 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2596 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2597 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2598 fprintf (stderr
, "%d ", val
);
2600 fprintf (stderr
, "\n");
2602 xtensa_insnbuf_free (isa
, sbuf
);
2605 #endif /* TENSILICA_DEBUG */
2609 is_direct_call_opcode (xtensa_opcode opcode
)
2611 xtensa_isa isa
= xtensa_default_isa
;
2612 int n
, num_operands
;
2614 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2617 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2618 for (n
= 0; n
< num_operands
; n
++)
2620 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2621 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2628 /* Convert from BFD relocation type code to slot and operand number.
2629 Returns non-zero on failure. */
2632 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2634 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2635 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2637 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2640 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2641 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2643 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2653 /* Convert from slot number to BFD relocation type code for the
2654 standard PC-relative relocations. Return BFD_RELOC_NONE on
2657 static bfd_reloc_code_real_type
2658 encode_reloc (int slot
)
2660 if (slot
< 0 || slot
> 14)
2661 return BFD_RELOC_NONE
;
2663 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2667 /* Convert from slot numbers to BFD relocation type code for the
2668 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2670 static bfd_reloc_code_real_type
2671 encode_alt_reloc (int slot
)
2673 if (slot
< 0 || slot
> 14)
2674 return BFD_RELOC_NONE
;
2676 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2681 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2684 xtensa_opcode opcode
,
2690 uint32 valbuf
= value
;
2692 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2694 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2696 as_bad_where ((char *) file
, line
,
2697 _("operand %d of '%s' has out of range value '%u'"),
2699 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2702 as_bad_where ((char *) file
, line
,
2703 _("operand %d of '%s' has invalid value '%u'"),
2705 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2710 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2716 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2719 xtensa_opcode opcode
,
2723 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2724 fmt
, slot
, slotbuf
, &val
);
2725 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2730 /* Checks for rules from xtensa-relax tables. */
2732 /* The routine xg_instruction_matches_option_term must return TRUE
2733 when a given option term is true. The meaning of all of the option
2734 terms is given interpretation by this function. */
2737 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2739 if (strcmp (option
->option_name
, "realnop") == 0
2740 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2742 /* These conditions were evaluated statically when building the
2743 relaxation table. There's no need to reevaluate them now. */
2746 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2747 return insn
->extra_arg
.X_op
== O_register
;
2750 as_fatal (_("internal error: unknown option name '%s'"),
2751 option
->option_name
);
2757 xg_instruction_matches_or_options (TInsn
*insn
,
2758 const ReqOrOptionList
*or_option
)
2760 const ReqOrOption
*option
;
2761 /* Must match each of the AND terms. */
2762 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2764 if (xg_instruction_matches_option_term (insn
, option
))
2772 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2774 const ReqOption
*req_options
;
2775 /* Must match each of the AND terms. */
2776 for (req_options
= options
;
2777 req_options
!= NULL
;
2778 req_options
= req_options
->next
)
2780 /* Must match one of the OR clauses. */
2781 if (!xg_instruction_matches_or_options (insn
,
2782 req_options
->or_option_terms
))
2789 /* Return the transition rule that matches or NULL if none matches. */
2792 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2794 PreconditionList
*condition_l
;
2796 if (rule
->opcode
!= insn
->opcode
)
2799 for (condition_l
= rule
->conditions
;
2800 condition_l
!= NULL
;
2801 condition_l
= condition_l
->next
)
2805 Precondition
*cond
= condition_l
->precond
;
2810 /* The expression must be the constant. */
2811 assert (cond
->op_num
< insn
->ntok
);
2812 exp1
= &insn
->tok
[cond
->op_num
];
2813 if (expr_is_const (exp1
))
2818 if (get_expr_const (exp1
) != cond
->op_data
)
2822 if (get_expr_const (exp1
) == cond
->op_data
)
2829 else if (expr_is_register (exp1
))
2834 if (get_expr_register (exp1
) != cond
->op_data
)
2838 if (get_expr_register (exp1
) == cond
->op_data
)
2850 assert (cond
->op_num
< insn
->ntok
);
2851 assert (cond
->op_data
< insn
->ntok
);
2852 exp1
= &insn
->tok
[cond
->op_num
];
2853 exp2
= &insn
->tok
[cond
->op_data
];
2858 if (!expr_is_equal (exp1
, exp2
))
2862 if (expr_is_equal (exp1
, exp2
))
2874 if (!xg_instruction_matches_options (insn
, rule
->options
))
2882 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2884 bfd_boolean a_greater
= FALSE
;
2885 bfd_boolean b_greater
= FALSE
;
2887 ReqOptionList
*l_a
= a
->options
;
2888 ReqOptionList
*l_b
= b
->options
;
2890 /* We only care if they both are the same except for
2891 a const16 vs. an l32r. */
2893 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2895 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
2896 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
2897 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
2899 if (l_or_a
->is_true
!= l_or_b
->is_true
)
2901 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
2903 /* This is the case we care about. */
2904 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
2905 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
2912 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
2913 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
2923 l_or_a
= l_or_a
->next
;
2924 l_or_b
= l_or_b
->next
;
2926 if (l_or_a
|| l_or_b
)
2935 /* Incomparable if the substitution was used differently in two cases. */
2936 if (a_greater
&& b_greater
)
2948 static TransitionRule
*
2949 xg_instruction_match (TInsn
*insn
)
2951 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
2953 assert (insn
->opcode
< table
->num_opcodes
);
2955 /* Walk through all of the possible transitions. */
2956 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
2958 TransitionRule
*rule
= l
->rule
;
2959 if (xg_instruction_matches_rule (insn
, rule
))
2966 /* Various Other Internal Functions. */
2969 is_unique_insn_expansion (TransitionRule
*r
)
2971 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
2973 if (r
->to_instr
->typ
!= INSTR_INSTR
)
2979 /* Check if there is exactly one relaxation for INSN that converts it to
2980 another instruction of equal or larger size. If so, and if TARG is
2981 non-null, go ahead and generate the relaxed instruction into TARG. If
2982 NARROW_ONLY is true, then only consider relaxations that widen a narrow
2983 instruction, i.e., ignore relaxations that convert to an instruction of
2984 equal size. In some contexts where this function is used, only
2985 a single widening is allowed and the NARROW_ONLY argument is used to
2986 exclude cases like ADDI being "widened" to an ADDMI, which may
2987 later be relaxed to an ADDMI/ADDI pair. */
2990 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
2992 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
2994 TransitionRule
*match
= 0;
2996 assert (insn
->insn_type
== ITYPE_INSN
);
2997 assert (insn
->opcode
< table
->num_opcodes
);
2999 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3001 TransitionRule
*rule
= l
->rule
;
3003 if (xg_instruction_matches_rule (insn
, rule
)
3004 && is_unique_insn_expansion (rule
)
3005 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3006 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3017 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3022 /* Return the maximum number of bytes this opcode can expand to. */
3025 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3027 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3029 int max_size
= xg_get_single_size (opcode
);
3031 assert (opcode
< table
->num_opcodes
);
3033 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3035 TransitionRule
*rule
= l
->rule
;
3036 BuildInstr
*build_list
;
3041 build_list
= rule
->to_instr
;
3042 if (is_unique_insn_expansion (rule
))
3044 assert (build_list
->typ
== INSTR_INSTR
);
3045 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3048 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3050 switch (build_list
->typ
)
3053 this_size
+= xg_get_single_size (build_list
->opcode
);
3055 case INSTR_LITERAL_DEF
:
3056 case INSTR_LABEL_DEF
:
3061 if (this_size
> max_size
)
3062 max_size
= this_size
;
3068 /* Return the maximum number of literal bytes this opcode can generate. */
3071 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3073 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3077 assert (opcode
< table
->num_opcodes
);
3079 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3081 TransitionRule
*rule
= l
->rule
;
3082 BuildInstr
*build_list
;
3087 build_list
= rule
->to_instr
;
3088 if (is_unique_insn_expansion (rule
))
3090 assert (build_list
->typ
== INSTR_INSTR
);
3091 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3094 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3096 switch (build_list
->typ
)
3098 case INSTR_LITERAL_DEF
:
3099 /* Hard-coded 4-byte literal. */
3103 case INSTR_LABEL_DEF
:
3108 if (this_size
> max_size
)
3109 max_size
= this_size
;
3116 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3118 int steps_taken
= 0;
3119 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3122 assert (insn
->insn_type
== ITYPE_INSN
);
3123 assert (insn
->opcode
< table
->num_opcodes
);
3125 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3127 TransitionRule
*rule
= l
->rule
;
3129 if (xg_instruction_matches_rule (insn
, rule
))
3131 if (steps_taken
== lateral_steps
)
3141 get_special_literal_symbol (void)
3143 static symbolS
*sym
= NULL
;
3146 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3152 get_special_label_symbol (void)
3154 static symbolS
*sym
= NULL
;
3157 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3163 xg_valid_literal_expression (const expressionS
*exp
)
3185 /* This will check to see if the value can be converted into the
3186 operand type. It will return TRUE if it does not fit. */
3189 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3191 uint32 valbuf
= value
;
3192 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3198 /* Assumes: All immeds are constants. Check that all constants fit
3199 into their immeds; return FALSE if not. */
3202 xg_immeds_fit (const TInsn
*insn
)
3204 xtensa_isa isa
= xtensa_default_isa
;
3208 assert (insn
->insn_type
== ITYPE_INSN
);
3209 for (i
= 0; i
< n
; ++i
)
3211 const expressionS
*expr
= &insn
->tok
[i
];
3212 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3219 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3224 /* The symbol should have a fixup associated with it. */
3233 /* This should only be called after we have an initial
3234 estimate of the addresses. */
3237 xg_symbolic_immeds_fit (const TInsn
*insn
,
3243 xtensa_isa isa
= xtensa_default_isa
;
3251 assert (insn
->insn_type
== ITYPE_INSN
);
3253 for (i
= 0; i
< n
; ++i
)
3255 const expressionS
*expr
= &insn
->tok
[i
];
3256 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3263 if (xg_check_operand (expr
->X_add_number
, insn
->opcode
, i
))
3269 /* Check for the worst case. */
3270 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3275 /* We only allow symbols for PC-relative references.
3276 If pc_frag == 0, then we don't have frag locations yet. */
3278 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3281 /* If it is a weak symbol or a symbol in a different section,
3282 it cannot be known to fit at assembly time. */
3283 if (S_IS_WEAK (expr
->X_add_symbol
)
3284 || S_GET_SEGMENT (expr
->X_add_symbol
) != pc_seg
)
3286 /* For a direct call with --no-longcalls, be optimistic and
3287 assume it will be in range. If the symbol is weak and
3288 undefined, it may remain undefined at link-time, in which
3289 case it will have a zero value and almost certainly be out
3290 of range for a direct call; thus, relax for undefined weak
3291 symbols even if longcalls is not enabled. */
3292 if (is_direct_call_opcode (insn
->opcode
)
3293 && ! pc_frag
->tc_frag_data
.use_longcalls
3294 && (! S_IS_WEAK (expr
->X_add_symbol
)
3295 || S_IS_DEFINED (expr
->X_add_symbol
)))
3301 symbolP
= expr
->X_add_symbol
;
3302 sym_frag
= symbol_get_frag (symbolP
);
3303 target
= S_GET_VALUE (symbolP
) + expr
->X_add_number
;
3304 pc
= pc_frag
->fr_address
+ pc_offset
;
3306 /* If frag has yet to be reached on this pass, assume it
3307 will move by STRETCH just as we did. If this is not so,
3308 it will be because some frag between grows, and that will
3309 force another pass. Beware zero-length frags. There
3310 should be a faster way to do this. */
3313 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3314 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3319 new_offset
= target
;
3320 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3321 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3326 /* The symbol should have a fixup associated with it. */
3335 /* Return TRUE on success. */
3338 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3344 targ
->debug_line
= insn
->debug_line
;
3345 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3350 targ
->opcode
= bi
->opcode
;
3351 targ
->insn_type
= ITYPE_INSN
;
3352 targ
->is_specific_opcode
= FALSE
;
3354 for (; op
!= NULL
; op
= op
->next
)
3356 int op_num
= op
->op_num
;
3357 int op_data
= op
->op_data
;
3359 assert (op
->op_num
< MAX_INSN_ARGS
);
3361 if (targ
->ntok
<= op_num
)
3362 targ
->ntok
= op_num
+ 1;
3367 set_expr_const (&targ
->tok
[op_num
], op_data
);
3370 assert (op_data
< insn
->ntok
);
3371 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3374 if (insn
->extra_arg
.X_op
!= O_register
)
3376 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3379 sym
= get_special_literal_symbol ();
3380 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3381 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3382 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3383 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3386 sym
= get_special_label_symbol ();
3387 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3389 case OP_OPERAND_HI16U
:
3390 case OP_OPERAND_LOW16U
:
3391 assert (op_data
< insn
->ntok
);
3392 if (expr_is_const (&insn
->tok
[op_data
]))
3395 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3396 val
= xg_apply_userdef_op_fn (op
->typ
,
3399 targ
->tok
[op_num
].X_add_number
= val
;
3403 /* For const16 we can create relocations for these. */
3404 if (targ
->opcode
== XTENSA_UNDEFINED
3405 || (targ
->opcode
!= xtensa_const16_opcode
))
3407 assert (op_data
< insn
->ntok
);
3408 /* Need to build a O_lo16 or O_hi16. */
3409 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3410 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3412 if (op
->typ
== OP_OPERAND_HI16U
)
3413 targ
->tok
[op_num
].X_op
= O_hi16
;
3414 else if (op
->typ
== OP_OPERAND_LOW16U
)
3415 targ
->tok
[op_num
].X_op
= O_lo16
;
3422 /* currently handles:
3425 OP_OPERAND_F32MINUS */
3426 if (xg_has_userdef_op_fn (op
->typ
))
3428 assert (op_data
< insn
->ntok
);
3429 if (expr_is_const (&insn
->tok
[op_data
]))
3432 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3433 val
= xg_apply_userdef_op_fn (op
->typ
,
3436 targ
->tok
[op_num
].X_add_number
= val
;
3439 return FALSE
; /* We cannot use a relocation for this. */
3448 case INSTR_LITERAL_DEF
:
3450 targ
->opcode
= XTENSA_UNDEFINED
;
3451 targ
->insn_type
= ITYPE_LITERAL
;
3452 targ
->is_specific_opcode
= FALSE
;
3453 for (; op
!= NULL
; op
= op
->next
)
3455 int op_num
= op
->op_num
;
3456 int op_data
= op
->op_data
;
3457 assert (op
->op_num
< MAX_INSN_ARGS
);
3459 if (targ
->ntok
<= op_num
)
3460 targ
->ntok
= op_num
+ 1;
3465 assert (op_data
< insn
->ntok
);
3466 /* We can only pass resolvable literals through. */
3467 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3469 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3481 case INSTR_LABEL_DEF
:
3483 targ
->opcode
= XTENSA_UNDEFINED
;
3484 targ
->insn_type
= ITYPE_LABEL
;
3485 targ
->is_specific_opcode
= FALSE
;
3486 /* Literal with no ops is a label? */
3487 assert (op
== NULL
);
3498 /* Return TRUE on success. */
3501 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3503 for (; bi
!= NULL
; bi
= bi
->next
)
3505 TInsn
*next_insn
= istack_push_space (istack
);
3507 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3514 /* Return TRUE on valid expansion. */
3517 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3519 int stack_size
= istack
->ninsn
;
3520 int steps_taken
= 0;
3521 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3524 assert (insn
->insn_type
== ITYPE_INSN
);
3525 assert (insn
->opcode
< table
->num_opcodes
);
3527 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3529 TransitionRule
*rule
= l
->rule
;
3531 if (xg_instruction_matches_rule (insn
, rule
))
3533 if (lateral_steps
== steps_taken
)
3537 /* This is it. Expand the rule to the stack. */
3538 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3541 /* Check to see if it fits. */
3542 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3544 TInsn
*insn
= &istack
->insn
[i
];
3546 if (insn
->insn_type
== ITYPE_INSN
3547 && !tinsn_has_symbolic_operands (insn
)
3548 && !xg_immeds_fit (insn
))
3550 istack
->ninsn
= stack_size
;
3563 /* Relax the assembly instruction at least "min_steps".
3564 Return the number of steps taken.
3566 For relaxation to correctly terminate, every relaxation chain must
3567 terminate in one of two ways:
3569 1. If the chain from one instruction to the next consists entirely of
3570 single instructions, then the chain *must* handle all possible
3571 immediates without failing. It must not ever fail because an
3572 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3573 chain is one example. L32R loads 32 bits, and there cannot be an
3574 immediate larger than 32 bits, so it satisfies this condition.
3575 Single instruction relaxation chains are as defined by
3576 xg_is_single_relaxable_instruction.
3578 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3579 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3581 Strictly speaking, in most cases you can violate condition 1 and be OK
3582 -- in particular when the last two instructions have the same single
3583 size. But nevertheless, you should guarantee the above two conditions.
3585 We could fix this so that single-instruction expansions correctly
3586 terminate when they can't handle the range, but the error messages are
3587 worse, and it actually turns out that in every case but one (18-bit wide
3588 branches), you need a multi-instruction expansion to get the full range
3589 anyway. And because 18-bit branches are handled identically to 15-bit
3590 branches, there isn't any point in changing it. */
3593 xg_assembly_relax (IStack
*istack
,
3596 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3597 offsetT pc_offset
, /* offset in fragment */
3598 int min_steps
, /* minimum conversion steps */
3599 long stretch
) /* number of bytes stretched so far */
3601 int steps_taken
= 0;
3603 /* Some of its immeds don't fit. Try to build a relaxed version.
3604 This may go through a couple of stages of single instruction
3605 transformations before we get there. */
3607 TInsn single_target
;
3609 int lateral_steps
= 0;
3610 int istack_size
= istack
->ninsn
;
3612 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3613 && steps_taken
>= min_steps
)
3615 istack_push (istack
, insn
);
3618 current_insn
= *insn
;
3620 /* Walk through all of the single instruction expansions. */
3621 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3624 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3627 if (steps_taken
>= min_steps
)
3629 istack_push (istack
, &single_target
);
3633 current_insn
= single_target
;
3636 /* Now check for a multi-instruction expansion. */
3637 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3639 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3642 if (steps_taken
>= min_steps
)
3644 istack_push (istack
, ¤t_insn
);
3649 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3651 if (steps_taken
>= min_steps
)
3655 istack
->ninsn
= istack_size
;
3658 /* It's not going to work -- use the original. */
3659 istack_push (istack
, insn
);
3665 xg_finish_frag (char *last_insn
,
3666 enum xtensa_relax_statesE frag_state
,
3667 enum xtensa_relax_statesE slot0_state
,
3669 bfd_boolean is_insn
)
3671 /* Finish off this fragment so that it has at LEAST the desired
3672 max_growth. If it doesn't fit in this fragment, close this one
3673 and start a new one. In either case, return a pointer to the
3674 beginning of the growth area. */
3678 frag_grow (max_growth
);
3679 old_frag
= frag_now
;
3681 frag_now
->fr_opcode
= last_insn
;
3683 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3685 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3686 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3688 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3689 xtensa_set_frag_assembly_state (frag_now
);
3691 /* Just to make sure that we did not split it up. */
3692 assert (old_frag
->fr_next
== frag_now
);
3696 /* Return TRUE if the target frag is one of the next non-empty frags. */
3699 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3704 for (; fragP
; fragP
= fragP
->fr_next
)
3706 if (fragP
== target
)
3708 if (fragP
->fr_fix
!= 0)
3710 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3712 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3713 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3715 if (fragP
->fr_type
== rs_space
)
3723 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3725 xtensa_isa isa
= xtensa_default_isa
;
3727 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3732 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3733 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3736 for (i
= 0; i
< num_ops
; i
++)
3738 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3744 if (target_op
== -1)
3747 if (insn
->ntok
<= target_op
)
3750 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3753 sym
= insn
->tok
[target_op
].X_add_symbol
;
3757 if (insn
->tok
[target_op
].X_add_number
!= 0)
3760 target_frag
= symbol_get_frag (sym
);
3761 if (target_frag
== NULL
)
3764 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3765 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3773 xg_add_branch_and_loop_targets (TInsn
*insn
)
3775 xtensa_isa isa
= xtensa_default_isa
;
3776 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3778 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3781 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3782 && insn
->tok
[i
].X_op
== O_symbol
)
3783 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3787 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3788 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3792 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3794 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3795 && insn
->tok
[i
].X_op
== O_symbol
)
3797 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3798 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3799 if (S_IS_DEFINED (sym
))
3800 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3807 /* Return FALSE if no error. */
3810 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3815 switch (instr_spec
->typ
)
3818 new_insn
->insn_type
= ITYPE_INSN
;
3819 new_insn
->opcode
= instr_spec
->opcode
;
3821 case INSTR_LITERAL_DEF
:
3822 new_insn
->insn_type
= ITYPE_LITERAL
;
3823 new_insn
->opcode
= XTENSA_UNDEFINED
;
3825 case INSTR_LABEL_DEF
:
3828 new_insn
->is_specific_opcode
= FALSE
;
3829 new_insn
->debug_line
= old_insn
->debug_line
;
3830 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3832 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3835 const expressionS
*src_exp
;
3841 /* The expression must be the constant. */
3842 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3843 exp
= &new_insn
->tok
[b_op
->op_num
];
3844 set_expr_const (exp
, b_op
->op_data
);
3848 assert (b_op
->op_num
< MAX_INSN_ARGS
);
3849 assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3850 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3851 exp
= &new_insn
->tok
[b_op
->op_num
];
3852 copy_expr (exp
, src_exp
);
3857 as_bad (_("can't handle generation of literal/labels yet"));
3861 as_bad (_("can't handle undefined OP TYPE"));
3866 new_insn
->ntok
= num_ops
;
3871 /* Return TRUE if it was simplified. */
3874 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3876 TransitionRule
*rule
;
3877 BuildInstr
*insn_spec
;
3879 if (old_insn
->is_specific_opcode
|| !density_supported
)
3882 rule
= xg_instruction_match (old_insn
);
3886 insn_spec
= rule
->to_instr
;
3887 /* There should only be one. */
3888 assert (insn_spec
!= NULL
);
3889 assert (insn_spec
->next
== NULL
);
3890 if (insn_spec
->next
!= NULL
)
3893 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
3899 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
3900 l32i.n. (2) Check the number of operands. (3) Place the instruction
3901 tokens into the stack or relax it and place multiple
3902 instructions/literals onto the stack. Return FALSE if no error. */
3905 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
3909 bfd_boolean do_expand
;
3911 tinsn_init (&new_insn
);
3913 /* Narrow it if we can. xg_simplify_insn now does all the
3914 appropriate checking (e.g., for the density option). */
3915 if (xg_simplify_insn (orig_insn
, &new_insn
))
3916 orig_insn
= &new_insn
;
3918 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
3920 if (orig_insn
->ntok
< noperands
)
3922 as_bad (_("found %d operands for '%s': Expected %d"),
3924 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3928 if (orig_insn
->ntok
> noperands
)
3929 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
3931 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
3934 /* If there are not enough operands, we will assert above. If there
3935 are too many, just cut out the extras here. */
3936 orig_insn
->ntok
= noperands
;
3938 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
3941 /* Special case for extui opcode which has constraints not handled
3942 by the ordinary operand encoding checks. The number of operands
3943 and related syntax issues have already been checked. */
3944 if (orig_insn
->opcode
== xtensa_extui_opcode
)
3946 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
3947 int maskimm
= orig_insn
->tok
[3].X_add_number
;
3948 if (shiftimm
+ maskimm
> 32)
3950 as_bad (_("immediate operands sum to greater than 32"));
3955 /* If the instruction will definitely need to be relaxed, it is better
3956 to expand it now for better scheduling. Decide whether to expand
3958 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
3960 /* Calls should be expanded to longcalls only in the backend relaxation
3961 so that the assembly scheduler will keep the L32R/CALLX instructions
3963 if (is_direct_call_opcode (orig_insn
->opcode
))
3966 if (tinsn_has_symbolic_operands (orig_insn
))
3968 /* The values of symbolic operands are not known yet, so only expand
3969 now if an operand is "complex" (e.g., difference of symbols) and
3970 will have to be stored as a literal regardless of the value. */
3971 if (!tinsn_has_complex_operands (orig_insn
))
3974 else if (xg_immeds_fit (orig_insn
))
3978 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
3980 istack_push (istack
, orig_insn
);
3986 /* Return TRUE if the section flags are marked linkonce
3987 or the name is .gnu.linkonce.*. */
3989 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
3992 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
3994 flagword flags
, link_once_flags
;
3996 flags
= bfd_get_section_flags (abfd
, sec
);
3997 link_once_flags
= (flags
& SEC_LINK_ONCE
);
3999 /* Flags might not be set yet. */
4000 if (!link_once_flags
4001 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4002 link_once_flags
= SEC_LINK_ONCE
;
4004 return (link_once_flags
!= 0);
4009 xtensa_add_literal_sym (symbolS
*sym
)
4013 l
= (sym_list
*) xmalloc (sizeof (sym_list
));
4015 l
->next
= literal_syms
;
4021 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4023 static int lit_num
= 0;
4024 static char name
[256];
4027 sprintf (name
, ".L_lit_sym%d", lit_num
);
4029 /* Create a local symbol. If it is in a linkonce section, we have to
4030 be careful to make sure that if it is used in a relocation that the
4031 symbol will be in the output file. */
4032 if (get_is_linkonce_section (stdoutput
, sec
))
4034 symbolP
= symbol_new (name
, sec
, 0, frag
);
4035 S_CLEAR_EXTERNAL (symbolP
);
4036 /* symbolP->local = 1; */
4039 symbolP
= symbol_new (name
, sec
, 0, frag
);
4041 xtensa_add_literal_sym (symbolP
);
4048 /* Currently all literals that are generated here are 32-bit L32R targets. */
4051 xg_assemble_literal (/* const */ TInsn
*insn
)
4054 symbolS
*lit_sym
= NULL
;
4055 bfd_reloc_code_real_type reloc
;
4056 bfd_boolean pcrel
= FALSE
;
4059 /* size = 4 for L32R. It could easily be larger when we move to
4060 larger constants. Add a parameter later. */
4061 offsetT litsize
= 4;
4062 offsetT litalign
= 2; /* 2^2 = 4 */
4063 expressionS saved_loc
;
4064 expressionS
* emit_val
;
4066 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4068 assert (insn
->insn_type
== ITYPE_LITERAL
);
4069 assert (insn
->ntok
== 1); /* must be only one token here */
4071 xtensa_switch_to_literal_fragment (&state
);
4073 emit_val
= &insn
->tok
[0];
4074 if (emit_val
->X_op
== O_big
)
4076 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4079 /* This happens when someone writes a "movi a2, big_number". */
4080 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4081 _("invalid immediate"));
4082 xtensa_restore_emit_state (&state
);
4087 /* Force a 4-byte align here. Note that this opens a new frag, so all
4088 literals done with this function have a frag to themselves. That's
4089 important for the way text section literals work. */
4090 frag_align (litalign
, 0, 0);
4091 record_alignment (now_seg
, litalign
);
4093 switch (emit_val
->X_op
)
4103 p
= frag_more (litsize
);
4104 xtensa_set_frag_assembly_state (frag_now
);
4105 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4106 if (emit_val
->X_add_symbol
)
4107 emit_val
->X_op
= O_symbol
;
4109 emit_val
->X_op
= O_constant
;
4110 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4111 litsize
, emit_val
, pcrel
, reloc
);
4115 emit_expr (emit_val
, litsize
);
4119 assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4120 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4121 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4122 lit_sym
= frag_now
->fr_symbol
;
4125 xtensa_restore_emit_state (&state
);
4131 xg_assemble_literal_space (/* const */ int size
, int slot
)
4134 /* We might have to do something about this alignment. It only
4135 takes effect if something is placed here. */
4136 offsetT litalign
= 2; /* 2^2 = 4 */
4137 fragS
*lit_saved_frag
;
4139 assert (size
% 4 == 0);
4141 xtensa_switch_to_literal_fragment (&state
);
4143 /* Force a 4-byte align here. */
4144 frag_align (litalign
, 0, 0);
4145 record_alignment (now_seg
, litalign
);
4149 lit_saved_frag
= frag_now
;
4150 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4151 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4152 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4155 xtensa_restore_emit_state (&state
);
4156 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4160 /* Put in a fixup record based on the opcode.
4161 Return TRUE on success. */
4164 xg_add_opcode_fix (TInsn
*tinsn
,
4172 xtensa_opcode opcode
= tinsn
->opcode
;
4173 bfd_reloc_code_real_type reloc
;
4174 reloc_howto_type
*howto
;
4178 reloc
= BFD_RELOC_NONE
;
4180 /* First try the special cases for "alternate" relocs. */
4181 if (opcode
== xtensa_l32r_opcode
)
4183 if (fragP
->tc_frag_data
.use_absolute_literals
)
4184 reloc
= encode_alt_reloc (slot
);
4186 else if (opcode
== xtensa_const16_opcode
)
4188 if (expr
->X_op
== O_lo16
)
4190 reloc
= encode_reloc (slot
);
4191 expr
->X_op
= O_symbol
;
4193 else if (expr
->X_op
== O_hi16
)
4195 reloc
= encode_alt_reloc (slot
);
4196 expr
->X_op
= O_symbol
;
4200 if (opnum
!= get_relaxable_immed (opcode
))
4202 as_bad (_("invalid relocation for operand %i of '%s'"),
4203 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4207 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4208 into the symbol table where the generic portions of the assembler
4209 won't know what to do with them. */
4210 if (expr
->X_op
== O_lo16
|| expr
->X_op
== O_hi16
)
4212 as_bad (_("invalid expression for operand %i of '%s'"),
4213 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4217 /* Next try the generic relocs. */
4218 if (reloc
== BFD_RELOC_NONE
)
4219 reloc
= encode_reloc (slot
);
4220 if (reloc
== BFD_RELOC_NONE
)
4222 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4226 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4229 as_bad (_("undefined symbol for opcode \"%s\""),
4230 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4234 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4235 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, expr
,
4236 howto
->pc_relative
, reloc
);
4237 the_fix
->fx_no_overflow
= 1;
4238 the_fix
->tc_fix_data
.X_add_symbol
= expr
->X_add_symbol
;
4239 the_fix
->tc_fix_data
.X_add_number
= expr
->X_add_number
;
4240 the_fix
->tc_fix_data
.slot
= slot
;
4247 xg_emit_insn_to_buf (TInsn
*tinsn
,
4251 bfd_boolean build_fix
)
4253 static xtensa_insnbuf insnbuf
= NULL
;
4254 bfd_boolean has_symbolic_immed
= FALSE
;
4255 bfd_boolean ok
= TRUE
;
4258 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4260 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4261 if (has_symbolic_immed
&& build_fix
)
4264 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4265 int slot
= xg_get_single_slot (tinsn
->opcode
);
4266 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4267 expressionS
*exp
= &tinsn
->tok
[opnum
];
4269 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4272 fragP
->tc_frag_data
.is_insn
= TRUE
;
4273 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4274 (unsigned char *) buf
, 0);
4280 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4282 symbolS
*sym
= get_special_literal_symbol ();
4286 assert (insn
->insn_type
== ITYPE_INSN
);
4287 for (i
= 0; i
< insn
->ntok
; i
++)
4288 if (insn
->tok
[i
].X_add_symbol
== sym
)
4289 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4295 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4297 symbolS
*sym
= get_special_label_symbol ();
4299 for (i
= 0; i
< insn
->ntok
; i
++)
4300 if (insn
->tok
[i
].X_add_symbol
== sym
)
4301 insn
->tok
[i
].X_add_symbol
= label_sym
;
4306 /* Return TRUE if the instruction can write to the specified
4307 integer register. */
4310 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4314 xtensa_isa isa
= xtensa_default_isa
;
4316 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4318 for (i
= 0; i
< num_ops
; i
++)
4321 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4322 if ((inout
== 'o' || inout
== 'm')
4323 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4325 xtensa_regfile opnd_rf
=
4326 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4327 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4329 if ((insn
->tok
[i
].X_op
== O_register
)
4330 && (insn
->tok
[i
].X_add_number
== regnum
))
4340 is_bad_loopend_opcode (const TInsn
*tinsn
)
4342 xtensa_opcode opcode
= tinsn
->opcode
;
4344 if (opcode
== XTENSA_UNDEFINED
)
4347 if (opcode
== xtensa_call0_opcode
4348 || opcode
== xtensa_callx0_opcode
4349 || opcode
== xtensa_call4_opcode
4350 || opcode
== xtensa_callx4_opcode
4351 || opcode
== xtensa_call8_opcode
4352 || opcode
== xtensa_callx8_opcode
4353 || opcode
== xtensa_call12_opcode
4354 || opcode
== xtensa_callx12_opcode
4355 || opcode
== xtensa_isync_opcode
4356 || opcode
== xtensa_ret_opcode
4357 || opcode
== xtensa_ret_n_opcode
4358 || opcode
== xtensa_retw_opcode
4359 || opcode
== xtensa_retw_n_opcode
4360 || opcode
== xtensa_waiti_opcode
4361 || opcode
== xtensa_rsr_lcount_opcode
)
4368 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4369 This allows the debugger to add unaligned labels.
4370 Also, the assembler generates stabs labels that need
4371 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4374 is_unaligned_label (symbolS
*sym
)
4376 const char *name
= S_GET_NAME (sym
);
4377 static size_t fake_size
= 0;
4381 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4384 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4386 fake_size
= strlen (FAKE_LABEL_NAME
);
4389 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4390 && (name
[fake_size
] == 'F'
4391 || name
[fake_size
] == 'L'
4392 || (name
[fake_size
] == 'e'
4393 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4401 next_non_empty_frag (const fragS
*fragP
)
4403 fragS
*next_fragP
= fragP
->fr_next
;
4405 /* Sometimes an empty will end up here due storage allocation issues.
4406 So we have to skip until we find something legit. */
4407 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4408 next_fragP
= next_fragP
->fr_next
;
4410 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4418 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4420 xtensa_opcode out_opcode
;
4421 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4423 if (next_fragP
== NULL
)
4426 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4427 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4429 *opcode
= out_opcode
;
4437 frag_format_size (const fragS
*fragP
)
4439 static xtensa_insnbuf insnbuf
= NULL
;
4440 xtensa_isa isa
= xtensa_default_isa
;
4445 insnbuf
= xtensa_insnbuf_alloc (isa
);
4448 return XTENSA_UNDEFINED
;
4450 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4451 (unsigned char *) fragP
->fr_literal
, 0);
4453 fmt
= xtensa_format_decode (isa
, insnbuf
);
4454 if (fmt
== XTENSA_UNDEFINED
)
4455 return XTENSA_UNDEFINED
;
4456 fmt_size
= xtensa_format_length (isa
, fmt
);
4458 /* If the next format won't be changing due to relaxation, just
4459 return the length of the first format. */
4460 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4463 /* If during relaxation we have to pull an instruction out of a
4464 multi-slot instruction, we will return the more conservative
4465 number. This works because alignment on bigger instructions
4466 is more restrictive than alignment on smaller instructions.
4467 This is more conservative than we would like, but it happens
4470 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4473 /* If we aren't doing one of our own relaxations or it isn't
4474 slot-based, then the insn size won't change. */
4475 if (fragP
->fr_type
!= rs_machine_dependent
)
4477 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4480 /* If an instruction is about to grow, return the longer size. */
4481 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4482 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4483 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4485 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4486 instruction in the relaxed version is of length 3. (The case
4487 where we have to pull the instruction out of a FLIX bundle
4488 is handled conservatively above.) However, frags with opcodes
4489 that are expanding to wide branches end up having formats that
4490 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4491 we can't tell directly what format the relaxer picked. This
4492 is a wart in the design of the relaxer that should someday be
4493 fixed, but would require major changes, or at least should
4494 be accompanied by major changes to make use of that data.
4496 In any event, we can tell that we are expanding from a single-slot
4497 three-byte format to a wider one with the logic below. */
4499 if (fmt_size
<= 3 && fragP
->tc_frag_data
.text_expansion
[0] != 3)
4500 return 3 + fragP
->tc_frag_data
.text_expansion
[0];
4505 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4506 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4513 next_frag_format_size (const fragS
*fragP
)
4515 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4516 return frag_format_size (next_fragP
);
4520 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4521 required two-byte instructions to be treated as three-byte instructions
4522 for loop instruction alignment. This restriction was removed beginning
4523 with Xtensa LX. Now the only requirement on loop instruction alignment
4524 is that the first instruction of the loop must appear at an address that
4525 does not cross a fetch boundary. */
4528 get_loop_align_size (int insn_size
)
4530 if (insn_size
== XTENSA_UNDEFINED
)
4531 return xtensa_fetch_width
;
4533 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4540 /* If the next legit fragment is an end-of-loop marker,
4541 switch its state so it will instantiate a NOP. */
4544 update_next_frag_state (fragS
*fragP
)
4546 fragS
*next_fragP
= fragP
->fr_next
;
4547 fragS
*new_target
= NULL
;
4551 /* We are guaranteed there will be one of these... */
4552 while (!(next_fragP
->fr_type
== rs_machine_dependent
4553 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4554 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4555 next_fragP
= next_fragP
->fr_next
;
4557 assert (next_fragP
->fr_type
== rs_machine_dependent
4558 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4559 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4561 /* ...and one of these. */
4562 new_target
= next_fragP
->fr_next
;
4563 while (!(new_target
->fr_type
== rs_machine_dependent
4564 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4565 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4566 new_target
= new_target
->fr_next
;
4568 assert (new_target
->fr_type
== rs_machine_dependent
4569 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4570 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4573 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4575 if (next_fragP
->fr_type
== rs_machine_dependent
4576 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4578 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4582 next_fragP
= next_fragP
->fr_next
;
4588 next_frag_is_branch_target (const fragS
*fragP
)
4590 /* Sometimes an empty will end up here due to storage allocation issues,
4591 so we have to skip until we find something legit. */
4592 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4594 if (fragP
->tc_frag_data
.is_branch_target
)
4596 if (fragP
->fr_fix
!= 0)
4604 next_frag_is_loop_target (const fragS
*fragP
)
4606 /* Sometimes an empty will end up here due storage allocation issues.
4607 So we have to skip until we find something legit. */
4608 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4610 if (fragP
->tc_frag_data
.is_loop_target
)
4612 if (fragP
->fr_fix
!= 0)
4620 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4622 const fragS
*next_fragp
= fragp
->fr_next
;
4623 xtensa_opcode next_opcode
;
4625 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4628 /* Sometimes an empty will end up here due to storage allocation issues,
4629 so we have to skip until we find something legit. */
4630 while (next_fragp
->fr_fix
== 0)
4631 next_fragp
= next_fragp
->fr_next
;
4633 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4636 /* There is some implicit knowledge encoded in here.
4637 The LOOP instructions that are NOT RELAX_IMMED have
4638 been relaxed. Note that we can assume that the LOOP
4639 instruction is in slot 0 because loops aren't bundleable. */
4640 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4641 return get_expanded_loop_offset (next_opcode
);
4647 /* Mark a location where we can later insert literal frags. Update
4648 the section's literal_pool_loc, so subsequent literals can be
4649 placed nearest to their use. */
4652 xtensa_mark_literal_pool_location (void)
4654 /* Any labels pointing to the current location need
4655 to be adjusted to after the literal pool. */
4657 fragS
*pool_location
;
4659 if (use_literal_section
)
4662 /* We stash info in these frags so we can later move the literal's
4663 fixes into this frchain's fix list. */
4664 pool_location
= frag_now
;
4665 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4666 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4667 frag_variant (rs_machine_dependent
, 0, 0,
4668 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4669 xtensa_set_frag_assembly_state (frag_now
);
4670 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4671 frag_variant (rs_machine_dependent
, 0, 0,
4672 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4673 xtensa_set_frag_assembly_state (frag_now
);
4675 /* Now put a frag into the literal pool that points to this location. */
4676 set_literal_pool_location (now_seg
, pool_location
);
4677 xtensa_switch_to_non_abs_literal_fragment (&s
);
4678 frag_align (2, 0, 0);
4679 record_alignment (now_seg
, 2);
4681 /* Close whatever frag is there. */
4682 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4683 xtensa_set_frag_assembly_state (frag_now
);
4684 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4685 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4686 xtensa_restore_emit_state (&s
);
4687 xtensa_set_frag_assembly_state (frag_now
);
4691 /* Build a nop of the correct size into tinsn. */
4694 build_nop (TInsn
*tinsn
, int size
)
4700 tinsn
->opcode
= xtensa_nop_n_opcode
;
4702 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4703 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4707 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4709 tinsn
->opcode
= xtensa_or_opcode
;
4710 set_expr_const (&tinsn
->tok
[0], 1);
4711 set_expr_const (&tinsn
->tok
[1], 1);
4712 set_expr_const (&tinsn
->tok
[2], 1);
4716 tinsn
->opcode
= xtensa_nop_opcode
;
4718 assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4723 /* Assemble a NOP of the requested size in the buffer. User must have
4724 allocated "buf" with at least "size" bytes. */
4727 assemble_nop (int size
, char *buf
)
4729 static xtensa_insnbuf insnbuf
= NULL
;
4732 build_nop (&tinsn
, size
);
4735 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4737 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4738 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4739 (unsigned char *) buf
, 0);
4743 /* Return the number of bytes for the offset of the expanded loop
4744 instruction. This should be incorporated into the relaxation
4745 specification but is hard-coded here. This is used to auto-align
4746 the loop instruction. It is invalid to call this function if the
4747 configuration does not have loops or if the opcode is not a loop
4751 get_expanded_loop_offset (xtensa_opcode opcode
)
4753 /* This is the OFFSET of the loop instruction in the expanded loop.
4754 This MUST correspond directly to the specification of the loop
4755 expansion. It will be validated on fragment conversion. */
4756 assert (opcode
!= XTENSA_UNDEFINED
);
4757 if (opcode
== xtensa_loop_opcode
)
4759 if (opcode
== xtensa_loopnez_opcode
)
4761 if (opcode
== xtensa_loopgtz_opcode
)
4763 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4769 get_literal_pool_location (segT seg
)
4771 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4776 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4778 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4782 /* Set frag assembly state should be called when a new frag is
4783 opened and after a frag has been closed. */
4786 xtensa_set_frag_assembly_state (fragS
*fragP
)
4788 if (!density_supported
)
4789 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4791 /* This function is called from subsegs_finish, which is called
4792 after xtensa_end, so we can't use "use_transform" or
4793 "use_schedule" here. */
4794 if (!directive_state
[directive_transform
])
4795 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4796 if (directive_state
[directive_longcalls
])
4797 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4798 fragP
->tc_frag_data
.use_absolute_literals
=
4799 directive_state
[directive_absolute_literals
];
4800 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4805 relaxable_section (asection
*sec
)
4807 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4808 && strcmp (sec
->name
, ".eh_frame") != 0);
4813 xtensa_mark_frags_for_org (void)
4817 /* Walk over each fragment of all of the current segments. If we find
4818 a .org frag in any of the segments, mark all frags prior to it as
4819 "no transform", which will prevent linker optimizations from messing
4820 up the .org distance. This should be done after
4821 xtensa_find_unmarked_state_frags, because we don't want to worry here
4822 about that function trashing the data we save here. */
4824 for (seclist
= &stdoutput
->sections
;
4825 seclist
&& *seclist
;
4826 seclist
= &(*seclist
)->next
)
4828 segT sec
= *seclist
;
4829 segment_info_type
*seginfo
;
4832 flags
= bfd_get_section_flags (stdoutput
, sec
);
4833 if (flags
& SEC_DEBUGGING
)
4835 if (!(flags
& SEC_ALLOC
))
4838 seginfo
= seg_info (sec
);
4839 if (seginfo
&& seginfo
->frchainP
)
4841 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4842 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4843 fragP
= fragP
->fr_next
)
4845 /* cvt_frag_to_fill has changed the fr_type of org frags to
4846 rs_fill, so use the value as cached in rs_subtype here. */
4847 if (fragP
->fr_subtype
== RELAX_ORG
)
4849 while (last_fragP
!= fragP
->fr_next
)
4851 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4852 last_fragP
= last_fragP
->fr_next
;
4862 xtensa_find_unmarked_state_frags (void)
4866 /* Walk over each fragment of all of the current segments. For each
4867 unmarked fragment, mark it with the same info as the previous
4869 for (seclist
= &stdoutput
->sections
;
4870 seclist
&& *seclist
;
4871 seclist
= &(*seclist
)->next
)
4873 segT sec
= *seclist
;
4874 segment_info_type
*seginfo
;
4877 flags
= bfd_get_section_flags (stdoutput
, sec
);
4878 if (flags
& SEC_DEBUGGING
)
4880 if (!(flags
& SEC_ALLOC
))
4883 seginfo
= seg_info (sec
);
4884 if (seginfo
&& seginfo
->frchainP
)
4886 fragS
*last_fragP
= 0;
4887 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4888 fragP
= fragP
->fr_next
)
4890 if (fragP
->fr_fix
!= 0
4891 && !fragP
->tc_frag_data
.is_assembly_state_set
)
4893 if (last_fragP
== 0)
4895 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
4896 _("assembly state not set for first frag in section %s"),
4901 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4902 fragP
->tc_frag_data
.is_no_density
=
4903 last_fragP
->tc_frag_data
.is_no_density
;
4904 fragP
->tc_frag_data
.is_no_transform
=
4905 last_fragP
->tc_frag_data
.is_no_transform
;
4906 fragP
->tc_frag_data
.use_longcalls
=
4907 last_fragP
->tc_frag_data
.use_longcalls
;
4908 fragP
->tc_frag_data
.use_absolute_literals
=
4909 last_fragP
->tc_frag_data
.use_absolute_literals
;
4912 if (fragP
->tc_frag_data
.is_assembly_state_set
)
4921 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
4923 void *unused ATTRIBUTE_UNUSED
)
4925 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4926 segment_info_type
*seginfo
= seg_info (sec
);
4927 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4929 if (flags
& SEC_CODE
)
4931 xtensa_isa isa
= xtensa_default_isa
;
4932 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4933 while (frag
!= NULL
)
4935 if (frag
->tc_frag_data
.is_branch_target
)
4938 addressT branch_align
, frag_addr
;
4941 xtensa_insnbuf_from_chars
4942 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4943 fmt
= xtensa_format_decode (isa
, insnbuf
);
4944 op_size
= xtensa_format_length (isa
, fmt
);
4945 branch_align
= 1 << branch_align_power (sec
);
4946 frag_addr
= frag
->fr_address
% branch_align
;
4947 if (frag_addr
+ op_size
> branch_align
)
4948 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4949 _("unaligned branch target: %d bytes at 0x%lx"),
4950 op_size
, (long) frag
->fr_address
);
4952 frag
= frag
->fr_next
;
4954 xtensa_insnbuf_free (isa
, insnbuf
);
4960 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
4962 void *unused ATTRIBUTE_UNUSED
)
4964 flagword flags
= bfd_get_section_flags (abfd
, sec
);
4965 segment_info_type
*seginfo
= seg_info (sec
);
4966 fragS
*frag
= seginfo
->frchainP
->frch_root
;
4967 xtensa_isa isa
= xtensa_default_isa
;
4969 if (flags
& SEC_CODE
)
4971 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
4972 while (frag
!= NULL
)
4974 if (frag
->tc_frag_data
.is_first_loop_insn
)
4980 xtensa_insnbuf_from_chars
4981 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
4982 fmt
= xtensa_format_decode (isa
, insnbuf
);
4983 op_size
= xtensa_format_length (isa
, fmt
);
4984 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
4986 if (frag_addr
+ op_size
> xtensa_fetch_width
)
4987 as_warn_where (frag
->fr_file
, frag
->fr_line
,
4988 _("unaligned loop: %d bytes at 0x%lx"),
4989 op_size
, (long) frag
->fr_address
);
4991 frag
= frag
->fr_next
;
4993 xtensa_insnbuf_free (isa
, insnbuf
);
4999 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5001 xtensa_isa isa
= xtensa_default_isa
;
5002 static xtensa_insnbuf insnbuf
= NULL
;
5003 static xtensa_insnbuf slotbuf
= NULL
;
5006 bfd_boolean alt_reloc
;
5007 xtensa_opcode opcode
;
5008 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5010 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5012 as_fatal (_("unexpected fix"));
5016 insnbuf
= xtensa_insnbuf_alloc (isa
);
5017 slotbuf
= xtensa_insnbuf_alloc (isa
);
5020 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5021 fmt
= xtensa_format_decode (isa
, insnbuf
);
5022 if (fmt
== XTENSA_UNDEFINED
)
5023 as_fatal (_("undecodable fix"));
5024 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5025 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5026 if (opcode
== XTENSA_UNDEFINED
)
5027 as_fatal (_("undecodable fix"));
5029 /* CONST16 immediates are not PC-relative, despite the fact that we
5030 reuse the normal PC-relative operand relocations for the low part
5031 of a CONST16 operand. */
5032 if (opcode
== xtensa_const16_opcode
)
5035 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5036 get_relaxable_immed (opcode
), val
,
5037 fixP
->fx_file
, fixP
->fx_line
);
5039 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5040 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5046 /* External Functions and Other GAS Hooks. */
5049 xtensa_target_format (void)
5051 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5056 xtensa_file_arch_init (bfd
*abfd
)
5058 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5063 md_number_to_chars (char *buf
, valueT val
, int n
)
5065 if (target_big_endian
)
5066 number_to_chars_bigendian (buf
, val
, n
);
5068 number_to_chars_littleendian (buf
, val
, n
);
5072 /* This function is called once, at assembler startup time. It should
5073 set up all the tables, etc. that the MD part of the assembler will
5079 segT current_section
= now_seg
;
5080 int current_subsec
= now_subseg
;
5083 xtensa_default_isa
= xtensa_isa_init (0, 0);
5084 isa
= xtensa_default_isa
;
5088 /* Set up the literal sections. */
5089 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5091 subseg_set (current_section
, current_subsec
);
5093 xg_init_vinsn (&cur_vinsn
);
5095 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5096 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5097 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5098 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5099 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5100 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5101 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5102 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5103 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5104 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5105 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5106 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5107 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5108 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5109 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5110 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5111 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5112 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5113 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5114 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5115 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5116 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5117 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5118 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5119 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5120 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5121 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5122 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5123 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5124 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5125 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5127 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5129 init_op_placement_info_table ();
5131 /* Set up the assembly state. */
5132 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5133 xtensa_set_frag_assembly_state (frag_now
);
5137 /* TC_INIT_FIX_DATA hook */
5140 xtensa_init_fix_data (fixS
*x
)
5142 x
->tc_fix_data
.slot
= 0;
5143 x
->tc_fix_data
.X_add_symbol
= NULL
;
5144 x
->tc_fix_data
.X_add_number
= 0;
5148 /* tc_frob_label hook */
5151 xtensa_frob_label (symbolS
*sym
)
5155 if (cur_vinsn
.inside_bundle
)
5157 as_bad (_("labels are not valid inside bundles"));
5161 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5163 /* Since the label was already attached to a frag associated with the
5164 previous basic block, it now needs to be reset to the current frag. */
5165 symbol_set_frag (sym
, frag_now
);
5166 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5168 if (generating_literals
)
5169 xtensa_add_literal_sym (sym
);
5171 xtensa_add_insn_label (sym
);
5173 if (symbol_get_tc (sym
)->is_loop_target
)
5175 if ((get_last_insn_flags (now_seg
, now_subseg
)
5176 & FLAG_IS_BAD_LOOPEND
) != 0)
5177 as_bad (_("invalid last instruction for a zero-overhead loop"));
5179 xtensa_set_frag_assembly_state (frag_now
);
5180 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5181 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5183 xtensa_set_frag_assembly_state (frag_now
);
5184 xtensa_move_labels (frag_now
, 0);
5187 /* No target aligning in the absolute section. */
5188 if (now_seg
!= absolute_section
5189 && do_align_targets ()
5190 && !is_unaligned_label (sym
)
5191 && !generating_literals
)
5193 xtensa_set_frag_assembly_state (frag_now
);
5195 frag_var (rs_machine_dependent
,
5197 RELAX_DESIRE_ALIGN_IF_TARGET
,
5198 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5199 xtensa_set_frag_assembly_state (frag_now
);
5200 xtensa_move_labels (frag_now
, 0);
5203 /* We need to mark the following properties even if we aren't aligning. */
5205 /* If the label is already known to be a branch target, i.e., a
5206 forward branch, mark the frag accordingly. Backward branches
5207 are handled by xg_add_branch_and_loop_targets. */
5208 if (symbol_get_tc (sym
)->is_branch_target
)
5209 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5211 /* Loops only go forward, so they can be identified here. */
5212 if (symbol_get_tc (sym
)->is_loop_target
)
5213 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5215 dwarf2_emit_label (sym
);
5219 /* tc_unrecognized_line hook */
5222 xtensa_unrecognized_line (int ch
)
5227 if (cur_vinsn
.inside_bundle
== 0)
5229 /* PR8110: Cannot emit line number info inside a FLIX bundle
5230 when using --gstabs. Temporarily disable debug info. */
5231 generate_lineno_debug ();
5232 if (debug_type
== DEBUG_STABS
)
5234 xt_saved_debug_type
= debug_type
;
5235 debug_type
= DEBUG_NONE
;
5238 cur_vinsn
.inside_bundle
= 1;
5242 as_bad (_("extra opening brace"));
5248 if (cur_vinsn
.inside_bundle
)
5249 finish_vinsn (&cur_vinsn
);
5252 as_bad (_("extra closing brace"));
5257 as_bad (_("syntax error"));
5264 /* md_flush_pending_output hook */
5267 xtensa_flush_pending_output (void)
5269 /* This line fixes a bug where automatically generated gstabs info
5270 separates a function label from its entry instruction, ending up
5271 with the literal position between the function label and the entry
5272 instruction and crashing code. It only happens with --gstabs and
5273 --text-section-literals, and when several other obscure relaxation
5274 conditions are met. */
5275 if (outputting_stabs_line_debug
)
5278 if (cur_vinsn
.inside_bundle
)
5279 as_bad (_("missing closing brace"));
5281 /* If there is a non-zero instruction fragment, close it. */
5282 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5284 frag_wane (frag_now
);
5286 xtensa_set_frag_assembly_state (frag_now
);
5288 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5290 xtensa_clear_insn_labels ();
5294 /* We had an error while parsing an instruction. The string might look
5295 like this: "insn arg1, arg2 }". If so, we need to see the closing
5296 brace and reset some fields. Otherwise, the vinsn never gets closed
5297 and the num_slots field will grow past the end of the array of slots,
5298 and bad things happen. */
5301 error_reset_cur_vinsn (void)
5303 if (cur_vinsn
.inside_bundle
)
5305 if (*input_line_pointer
== '}'
5306 || *(input_line_pointer
- 1) == '}'
5307 || *(input_line_pointer
- 2) == '}')
5308 xg_clear_vinsn (&cur_vinsn
);
5314 md_assemble (char *str
)
5316 xtensa_isa isa
= xtensa_default_isa
;
5319 bfd_boolean has_underbar
= FALSE
;
5320 char *arg_strings
[MAX_INSN_ARGS
];
5322 TInsn orig_insn
; /* Original instruction from the input. */
5324 tinsn_init (&orig_insn
);
5326 /* Split off the opcode. */
5327 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5328 opname
= xmalloc (opnamelen
+ 1);
5329 memcpy (opname
, str
, opnamelen
);
5330 opname
[opnamelen
] = '\0';
5332 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5335 as_bad (_("syntax error"));
5339 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5342 /* Check for an underbar prefix. */
5345 has_underbar
= TRUE
;
5349 orig_insn
.insn_type
= ITYPE_INSN
;
5351 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5352 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5354 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5355 extra argument and set the opcode to "CALLXn". */
5356 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5357 && strncasecmp (opname
, "callx", 5) == 0)
5359 unsigned long window_size
;
5362 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5363 if (suffix
!= opname
+ 5
5364 && (window_size
== 0
5367 || window_size
== 12)
5368 && strcasecmp (suffix
, ".tls") == 0)
5370 switch (window_size
)
5372 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5373 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5374 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5375 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5379 as_bad (_("wrong number of operands for '%s'"), opname
);
5382 bfd_reloc_code_real_type reloc
;
5383 char *old_input_line_pointer
;
5384 expressionS
*tok
= &orig_insn
.extra_arg
;
5387 old_input_line_pointer
= input_line_pointer
;
5388 input_line_pointer
= arg_strings
[num_args
- 1];
5390 t
= expression (tok
);
5391 if (tok
->X_op
== O_symbol
5392 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5393 == BFD_RELOC_XTENSA_TLS_CALL
))
5394 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5396 as_bad (_("bad relocation expression for '%s'"), opname
);
5398 input_line_pointer
= old_input_line_pointer
;
5404 /* Special case: Check for "j.l" psuedo op. */
5405 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5406 && strncasecmp (opname
, "j.l", 3) == 0)
5409 as_bad (_("wrong number of operands for '%s'"), opname
);
5412 char *old_input_line_pointer
;
5413 expressionS
*tok
= &orig_insn
.extra_arg
;
5415 old_input_line_pointer
= input_line_pointer
;
5416 input_line_pointer
= arg_strings
[num_args
- 1];
5418 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5419 input_line_pointer
= old_input_line_pointer
;
5422 orig_insn
.opcode
= xtensa_j_opcode
;
5426 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5428 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5429 if (fmt
== XTENSA_UNDEFINED
)
5431 as_bad (_("unknown opcode or format name '%s'"), opname
);
5432 error_reset_cur_vinsn ();
5435 if (!cur_vinsn
.inside_bundle
)
5437 as_bad (_("format names only valid inside bundles"));
5438 error_reset_cur_vinsn ();
5441 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5442 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5444 cur_vinsn
.format
= fmt
;
5445 free (has_underbar
? opname
- 1 : opname
);
5446 error_reset_cur_vinsn ();
5450 /* Parse the arguments. */
5451 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5453 as_bad (_("syntax error"));
5454 error_reset_cur_vinsn ();
5458 /* Free the opcode and argument strings, now that they've been parsed. */
5459 free (has_underbar
? opname
- 1 : opname
);
5461 while (num_args
-- > 0)
5462 free (arg_strings
[num_args
]);
5464 /* Get expressions for invisible operands. */
5465 if (get_invisible_operands (&orig_insn
))
5467 error_reset_cur_vinsn ();
5471 /* Check for the right number and type of arguments. */
5472 if (tinsn_check_arguments (&orig_insn
))
5474 error_reset_cur_vinsn ();
5478 /* Record the line number for each TInsn, because a FLIX bundle may be
5479 spread across multiple input lines and individual instructions may be
5480 moved around in some cases. */
5481 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5482 dwarf2_where (&orig_insn
.debug_line
);
5483 dwarf2_consume_line_info ();
5485 xg_add_branch_and_loop_targets (&orig_insn
);
5487 /* Check that immediate value for ENTRY is >= 16. */
5488 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5490 expressionS
*exp
= &orig_insn
.tok
[2];
5491 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5492 as_warn (_("entry instruction with stack decrement < 16"));
5496 assemble_tokens (opcode, tok, ntok);
5497 expand the tokens from the orig_insn into the
5498 stack of instructions that will not expand
5499 unless required at relaxation time. */
5501 if (!cur_vinsn
.inside_bundle
)
5502 emit_single_op (&orig_insn
);
5503 else /* We are inside a bundle. */
5505 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5506 cur_vinsn
.num_slots
++;
5507 if (*input_line_pointer
== '}'
5508 || *(input_line_pointer
- 1) == '}'
5509 || *(input_line_pointer
- 2) == '}')
5510 finish_vinsn (&cur_vinsn
);
5513 /* We've just emitted a new instruction so clear the list of labels. */
5514 xtensa_clear_insn_labels ();
5518 /* HANDLE_ALIGN hook */
5520 /* For a .align directive, we mark the previous block with the alignment
5521 information. This will be placed in the object file in the
5522 property section corresponding to this section. */
5525 xtensa_handle_align (fragS
*fragP
)
5528 && ! fragP
->tc_frag_data
.is_literal
5529 && (fragP
->fr_type
== rs_align
5530 || fragP
->fr_type
== rs_align_code
)
5531 && fragP
->fr_address
+ fragP
->fr_fix
> 0
5532 && fragP
->fr_offset
> 0
5533 && now_seg
!= bss_section
)
5535 fragP
->tc_frag_data
.is_align
= TRUE
;
5536 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5539 if (fragP
->fr_type
== rs_align_test
)
5542 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5544 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5545 _("unaligned entry instruction"));
5548 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5549 fragP
->fr_subtype
= RELAX_ORG
;
5553 /* TC_FRAG_INIT hook */
5556 xtensa_frag_init (fragS
*frag
)
5558 xtensa_set_frag_assembly_state (frag
);
5563 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5569 /* Round up a section size to the appropriate boundary. */
5572 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5574 return size
; /* Byte alignment is fine. */
5579 md_pcrel_from (fixS
*fixP
)
5582 static xtensa_insnbuf insnbuf
= NULL
;
5583 static xtensa_insnbuf slotbuf
= NULL
;
5586 xtensa_opcode opcode
;
5589 xtensa_isa isa
= xtensa_default_isa
;
5590 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5591 bfd_boolean alt_reloc
;
5593 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5596 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5601 insnbuf
= xtensa_insnbuf_alloc (isa
);
5602 slotbuf
= xtensa_insnbuf_alloc (isa
);
5605 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5606 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5607 fmt
= xtensa_format_decode (isa
, insnbuf
);
5609 if (fmt
== XTENSA_UNDEFINED
)
5610 as_fatal (_("bad instruction format"));
5612 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5613 as_fatal (_("invalid relocation"));
5615 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5616 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5618 /* Check for "alternate" relocations (operand not specified). None
5619 of the current uses for these are really PC-relative. */
5620 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5622 if (opcode
!= xtensa_l32r_opcode
5623 && opcode
!= xtensa_const16_opcode
)
5624 as_fatal (_("invalid relocation for '%s' instruction"),
5625 xtensa_opcode_name (isa
, opcode
));
5629 opnum
= get_relaxable_immed (opcode
);
5631 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5632 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5634 as_bad_where (fixP
->fx_file
,
5636 _("invalid relocation for operand %d of '%s'"),
5637 opnum
, xtensa_opcode_name (isa
, opcode
));
5640 return 0 - opnd_value
;
5644 /* TC_FORCE_RELOCATION hook */
5647 xtensa_force_relocation (fixS
*fix
)
5649 switch (fix
->fx_r_type
)
5651 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5652 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5653 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5654 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5655 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5656 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5657 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5658 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5659 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5660 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5661 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5662 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5663 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5664 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5665 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5666 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5672 if (linkrelax
&& fix
->fx_addsy
5673 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5676 return generic_force_reloc (fix
);
5680 /* TC_VALIDATE_FIX_SUB hook */
5683 xtensa_validate_fix_sub (fixS
*fix
)
5685 segT add_symbol_segment
, sub_symbol_segment
;
5687 /* The difference of two symbols should be resolved by the assembler when
5688 linkrelax is not set. If the linker may relax the section containing
5689 the symbols, then an Xtensa DIFF relocation must be generated so that
5690 the linker knows to adjust the difference value. */
5691 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5694 /* Make sure both symbols are in the same segment, and that segment is
5695 "normal" and relaxable. If the segment is not "normal", then the
5696 fix is not valid. If the segment is not "relaxable", then the fix
5697 should have been handled earlier. */
5698 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5699 if (! SEG_NORMAL (add_symbol_segment
) ||
5700 ! relaxable_section (add_symbol_segment
))
5702 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5703 return (sub_symbol_segment
== add_symbol_segment
);
5707 /* NO_PSEUDO_DOT hook */
5709 /* This function has nothing to do with pseudo dots, but this is the
5710 nearest macro to where the check needs to take place. FIXME: This
5714 xtensa_check_inside_bundle (void)
5716 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5717 as_bad (_("directives are not valid inside bundles"));
5719 /* This function must always return FALSE because it is called via a
5720 macro that has nothing to do with bundling. */
5725 /* md_elf_section_change_hook */
5728 xtensa_elf_section_change_hook (void)
5730 /* Set up the assembly state. */
5731 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5732 xtensa_set_frag_assembly_state (frag_now
);
5736 /* tc_fix_adjustable hook */
5739 xtensa_fix_adjustable (fixS
*fixP
)
5741 /* An offset is not allowed in combination with the difference of two
5742 symbols, but that cannot be easily detected after a local symbol
5743 has been adjusted to a (section+offset) form. Return 0 so that such
5744 an fix will not be adjusted. */
5745 if (fixP
->fx_subsy
&& fixP
->fx_addsy
&& fixP
->fx_offset
5746 && relaxable_section (S_GET_SEGMENT (fixP
->fx_subsy
)))
5749 /* We need the symbol name for the VTABLE entries. */
5750 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5751 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5758 /* tc_symbol_new_hook */
5760 symbolS
*expr_symbols
= NULL
;
5763 xtensa_symbol_new_hook (symbolS
*sym
)
5765 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5767 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5774 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5776 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5779 /* Subtracted symbols are only allowed for a few relocation types, and
5780 unless linkrelax is enabled, they should not make it to this point. */
5781 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5782 || fixP
->fx_r_type
== BFD_RELOC_16
5783 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5786 switch (fixP
->fx_r_type
)
5788 case BFD_RELOC_32_PCREL
:
5794 switch (fixP
->fx_r_type
)
5797 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5800 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5803 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5809 /* An offset is only allowed when it results from adjusting a
5810 local symbol into a section-relative offset. If the offset
5811 came from the original expression, tc_fix_adjustable will have
5812 prevented the fix from being converted to a section-relative
5813 form so that we can flag the error here. */
5814 if (fixP
->fx_offset
!= 0 && !symbol_section_p (fixP
->fx_addsy
))
5815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5816 _("cannot represent subtraction with an offset"));
5818 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5819 - S_GET_VALUE (fixP
->fx_subsy
));
5821 /* The difference value gets written out, and the DIFF reloc
5822 identifies the address of the subtracted symbol (i.e., the one
5823 with the lowest address). */
5825 fixP
->fx_offset
-= val
;
5826 fixP
->fx_subsy
= NULL
;
5828 else if (! fixP
->fx_addsy
)
5835 case BFD_RELOC_XTENSA_PLT
:
5836 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5837 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5840 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5841 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5842 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5843 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5844 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5845 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
5846 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5849 case BFD_RELOC_XTENSA_SLOT0_OP
:
5850 case BFD_RELOC_XTENSA_SLOT1_OP
:
5851 case BFD_RELOC_XTENSA_SLOT2_OP
:
5852 case BFD_RELOC_XTENSA_SLOT3_OP
:
5853 case BFD_RELOC_XTENSA_SLOT4_OP
:
5854 case BFD_RELOC_XTENSA_SLOT5_OP
:
5855 case BFD_RELOC_XTENSA_SLOT6_OP
:
5856 case BFD_RELOC_XTENSA_SLOT7_OP
:
5857 case BFD_RELOC_XTENSA_SLOT8_OP
:
5858 case BFD_RELOC_XTENSA_SLOT9_OP
:
5859 case BFD_RELOC_XTENSA_SLOT10_OP
:
5860 case BFD_RELOC_XTENSA_SLOT11_OP
:
5861 case BFD_RELOC_XTENSA_SLOT12_OP
:
5862 case BFD_RELOC_XTENSA_SLOT13_OP
:
5863 case BFD_RELOC_XTENSA_SLOT14_OP
:
5866 /* Write the tentative value of a PC-relative relocation to a
5867 local symbol into the instruction. The value will be ignored
5868 by the linker, and it makes the object file disassembly
5869 readable when all branch targets are encoded in relocations. */
5871 assert (fixP
->fx_addsy
);
5872 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
5873 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
5875 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5876 - md_pcrel_from (fixP
));
5877 (void) xg_apply_fix_value (fixP
, val
);
5880 else if (! fixP
->fx_addsy
)
5883 if (xg_apply_fix_value (fixP
, val
))
5888 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5889 case BFD_RELOC_XTENSA_TLS_FUNC
:
5890 case BFD_RELOC_XTENSA_TLS_ARG
:
5891 case BFD_RELOC_XTENSA_TLS_CALL
:
5892 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5893 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5894 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5895 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5896 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5897 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5898 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5899 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5900 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5901 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5902 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5903 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5904 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5905 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5906 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5907 /* These all need to be resolved at link-time. Do nothing now. */
5910 case BFD_RELOC_VTABLE_INHERIT
:
5911 case BFD_RELOC_VTABLE_ENTRY
:
5916 as_bad (_("unhandled local relocation fix %s"),
5917 bfd_get_reloc_code_name (fixP
->fx_r_type
));
5923 md_atof (int type
, char *litP
, int *sizeP
)
5925 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
5930 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
5932 return total_frag_text_expansion (fragP
);
5936 /* Translate internal representation of relocation info to BFD target
5940 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
5944 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
5945 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
5946 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
5947 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5949 /* Make sure none of our internal relocations make it this far.
5950 They'd better have been fully resolved by this point. */
5951 assert ((int) fixp
->fx_r_type
> 0);
5953 reloc
->addend
= fixp
->fx_offset
;
5955 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5956 if (reloc
->howto
== NULL
)
5958 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5959 _("cannot represent `%s' relocation in object file"),
5960 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5961 free (reloc
->sym_ptr_ptr
);
5966 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
5967 as_fatal (_("internal error; cannot generate `%s' relocation"),
5968 bfd_get_reloc_code_name (fixp
->fx_r_type
));
5974 /* Checks for resource conflicts between instructions. */
5976 /* The func unit stuff could be implemented as bit-vectors rather
5977 than the iterative approach here. If it ends up being too
5978 slow, we will switch it. */
5981 new_resource_table (void *data
,
5984 unit_num_copies_func uncf
,
5985 opcode_num_units_func onuf
,
5986 opcode_funcUnit_use_unit_func ouuf
,
5987 opcode_funcUnit_use_stage_func ousf
)
5990 resource_table
*rt
= (resource_table
*) xmalloc (sizeof (resource_table
));
5992 rt
->cycles
= cycles
;
5993 rt
->allocated_cycles
= cycles
;
5995 rt
->unit_num_copies
= uncf
;
5996 rt
->opcode_num_units
= onuf
;
5997 rt
->opcode_unit_use
= ouuf
;
5998 rt
->opcode_unit_stage
= ousf
;
6000 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6001 for (i
= 0; i
< cycles
; i
++)
6002 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6009 clear_resource_table (resource_table
*rt
)
6012 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6013 for (j
= 0; j
< rt
->num_units
; j
++)
6014 rt
->units
[i
][j
] = 0;
6018 /* We never shrink it, just fake it into thinking so. */
6021 resize_resource_table (resource_table
*rt
, int cycles
)
6025 rt
->cycles
= cycles
;
6026 if (cycles
<= rt
->allocated_cycles
)
6029 old_cycles
= rt
->allocated_cycles
;
6030 rt
->allocated_cycles
= cycles
;
6032 rt
->units
= xrealloc (rt
->units
,
6033 rt
->allocated_cycles
* sizeof (unsigned char *));
6034 for (i
= 0; i
< old_cycles
; i
++)
6035 rt
->units
[i
] = xrealloc (rt
->units
[i
],
6036 rt
->num_units
* sizeof (unsigned char));
6037 for (i
= old_cycles
; i
< cycles
; i
++)
6038 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6043 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6046 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6048 for (i
= 0; i
< uses
; i
++)
6050 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6051 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6052 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6053 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6054 if (copies_in_use
>= copies
)
6062 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6065 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6067 for (i
= 0; i
< uses
; i
++)
6069 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6070 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6071 /* Note that this allows resources to be oversubscribed. That's
6072 essential to the way the optional scheduler works.
6073 resources_available reports when a resource is over-subscribed,
6074 so it's easy to tell. */
6075 rt
->units
[stage
+ cycle
][unit
]++;
6081 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6084 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6086 for (i
= 0; i
< uses
; i
++)
6088 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6089 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6090 assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6091 rt
->units
[stage
+ cycle
][unit
]--;
6096 /* Wrapper functions make parameterized resource reservation
6100 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6102 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6108 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6110 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6115 /* Note that this function does not check issue constraints, but
6116 solely whether the hardware is available to execute the given
6117 instructions together. It also doesn't check if the tinsns
6118 write the same state, or access the same tieports. That is
6119 checked by check_t1_t2_reads_and_writes. */
6122 resources_conflict (vliw_insn
*vinsn
)
6125 static resource_table
*rt
= NULL
;
6127 /* This is the most common case by far. Optimize it. */
6128 if (vinsn
->num_slots
== 1)
6133 xtensa_isa isa
= xtensa_default_isa
;
6134 rt
= new_resource_table
6135 (isa
, xtensa_num_pipe_stages
,
6136 xtensa_isa_num_funcUnits (isa
),
6137 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6138 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6139 opcode_funcUnit_use_unit
,
6140 opcode_funcUnit_use_stage
);
6143 clear_resource_table (rt
);
6145 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6147 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6149 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6156 /* finish_vinsn, emit_single_op and helper functions. */
6158 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6159 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6160 static void xg_assemble_vliw_tokens (vliw_insn
*);
6163 /* We have reached the end of a bundle; emit into the frag. */
6166 finish_vinsn (vliw_insn
*vinsn
)
6173 if (find_vinsn_conflicts (vinsn
))
6175 xg_clear_vinsn (vinsn
);
6179 /* First, find a format that works. */
6180 if (vinsn
->format
== XTENSA_UNDEFINED
)
6181 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6183 if (vinsn
->format
== XTENSA_UNDEFINED
)
6185 as_where (&file_name
, &line
);
6186 as_bad_where (file_name
, line
,
6187 _("couldn't find a valid instruction format"));
6188 fprintf (stderr
, _(" ops were: "));
6189 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6190 fprintf (stderr
, _(" %s;"),
6191 xtensa_opcode_name (xtensa_default_isa
,
6192 vinsn
->slots
[i
].opcode
));
6193 fprintf (stderr
, _("\n"));
6194 xg_clear_vinsn (vinsn
);
6198 if (vinsn
->num_slots
6199 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6201 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6202 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6203 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6205 xg_clear_vinsn (vinsn
);
6209 if (resources_conflict (vinsn
))
6211 as_where (&file_name
, &line
);
6212 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6213 fprintf (stderr
, " ops were: ");
6214 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6215 fprintf (stderr
, " %s;",
6216 xtensa_opcode_name (xtensa_default_isa
,
6217 vinsn
->slots
[i
].opcode
));
6218 fprintf (stderr
, "\n");
6219 xg_clear_vinsn (vinsn
);
6223 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6225 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6227 symbolS
*lit_sym
= NULL
;
6229 bfd_boolean e
= FALSE
;
6230 bfd_boolean saved_density
= density_supported
;
6232 /* We don't want to narrow ops inside multi-slot bundles. */
6233 if (vinsn
->num_slots
> 1)
6234 density_supported
= FALSE
;
6236 istack_init (&slotstack
);
6237 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6239 vinsn
->slots
[i
].opcode
=
6240 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6242 vinsn
->slots
[i
].ntok
= 0;
6245 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6251 density_supported
= saved_density
;
6255 xg_clear_vinsn (vinsn
);
6259 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6261 TInsn
*insn
= &slotstack
.insn
[j
];
6262 if (insn
->insn_type
== ITYPE_LITERAL
)
6264 assert (lit_sym
== NULL
);
6265 lit_sym
= xg_assemble_literal (insn
);
6269 assert (insn
->insn_type
== ITYPE_INSN
);
6271 xg_resolve_literals (insn
, lit_sym
);
6272 if (j
!= slotstack
.ninsn
- 1)
6273 emit_single_op (insn
);
6277 if (vinsn
->num_slots
> 1)
6279 if (opcode_fits_format_slot
6280 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6283 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6287 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6288 if (vinsn
->format
== XTENSA_UNDEFINED
)
6289 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6291 vinsn
->slots
[i
].opcode
6292 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6295 vinsn
->slots
[i
].ntok
= 0;
6300 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6301 vinsn
->format
= XTENSA_UNDEFINED
;
6306 /* Now check resource conflicts on the modified bundle. */
6307 if (resources_conflict (vinsn
))
6309 as_where (&file_name
, &line
);
6310 as_bad_where (file_name
, line
, _("illegal resource usage in bundle"));
6311 fprintf (stderr
, " ops were: ");
6312 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6313 fprintf (stderr
, " %s;",
6314 xtensa_opcode_name (xtensa_default_isa
,
6315 vinsn
->slots
[i
].opcode
));
6316 fprintf (stderr
, "\n");
6317 xg_clear_vinsn (vinsn
);
6321 /* First, find a format that works. */
6322 if (vinsn
->format
== XTENSA_UNDEFINED
)
6323 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6325 xg_assemble_vliw_tokens (vinsn
);
6327 xg_clear_vinsn (vinsn
);
6331 /* Given an vliw instruction, what conflicts are there in register
6332 usage and in writes to states and queues?
6334 This function does two things:
6335 1. Reports an error when a vinsn contains illegal combinations
6336 of writes to registers states or queues.
6337 2. Marks individual tinsns as not relaxable if the combination
6338 contains antidependencies.
6340 Job 2 handles things like swap semantics in instructions that need
6341 to be relaxed. For example,
6345 normally would be relaxed to
6350 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6352 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6354 then we can't relax it into
6357 { add a0, a1, a0 ; add a2, a0, a4 ; }
6359 because the value of a0 is trashed before the second add can read it. */
6361 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6364 find_vinsn_conflicts (vliw_insn
*vinsn
)
6368 xtensa_isa isa
= xtensa_default_isa
;
6370 assert (!past_xtensa_end
);
6372 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6374 TInsn
*op1
= &vinsn
->slots
[i
];
6375 if (op1
->is_specific_opcode
)
6376 op1
->keep_wide
= TRUE
;
6378 op1
->keep_wide
= FALSE
;
6381 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6383 TInsn
*op1
= &vinsn
->slots
[i
];
6385 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6388 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6392 TInsn
*op2
= &vinsn
->slots
[j
];
6393 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6394 switch (conflict_type
)
6397 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6398 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6399 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6402 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6403 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6404 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6407 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6408 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6409 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6412 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6413 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6414 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6417 /* Everything is OK. */
6420 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6421 || conflict_type
== 'a');
6428 as_bad (_("multiple branches or jumps in the same bundle"));
6436 /* Check how the state used by t1 and t2 relate.
6439 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6440 case B: no relationship between what is read and written (both could
6441 read the same reg though)
6442 case C: t1 writes a register t2 writes (a register conflict within a
6444 case D: t1 writes a state that t2 also writes
6445 case E: t1 writes a tie queue that t2 also writes
6446 case F: two volatile queue accesses
6450 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6452 xtensa_isa isa
= xtensa_default_isa
;
6453 xtensa_regfile t1_regfile
, t2_regfile
;
6455 int t1_base_reg
, t1_last_reg
;
6456 int t2_base_reg
, t2_last_reg
;
6457 char t1_inout
, t2_inout
;
6459 char conflict
= 'b';
6464 bfd_boolean t1_volatile
= FALSE
;
6465 bfd_boolean t2_volatile
= FALSE
;
6467 /* Check registers. */
6468 for (j
= 0; j
< t2
->ntok
; j
++)
6470 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6473 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6474 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6475 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6477 for (i
= 0; i
< t1
->ntok
; i
++)
6479 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6482 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6484 if (t1_regfile
!= t2_regfile
)
6487 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6488 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6490 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6491 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6493 if (t1_inout
== 'm' || t1_inout
== 'o'
6494 || t2_inout
== 'm' || t2_inout
== 'o')
6501 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6502 t1_last_reg
= (t1_base_reg
6503 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6505 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6507 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6509 if (t1_reg
!= t2_reg
)
6512 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6518 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6524 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6532 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6533 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6534 for (j
= 0; j
< t2_states
; j
++)
6536 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6537 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6538 for (i
= 0; i
< t1_states
; i
++)
6540 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6541 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6545 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6551 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6557 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6562 /* Check tieports. */
6563 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6564 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6565 for (j
= 0; j
< t2_interfaces
; j
++)
6567 xtensa_interface t2_int
6568 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6569 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6571 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6572 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6575 for (i
= 0; i
< t1_interfaces
; i
++)
6577 xtensa_interface t1_int
6578 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6579 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6581 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6582 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6585 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6588 if (t1_int
!= t2_int
)
6591 if (t2_inout
== 'i' && t1_inout
== 'o')
6597 if (t1_inout
== 'i' && t2_inout
== 'o')
6603 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6612 static xtensa_format
6613 xg_find_narrowest_format (vliw_insn
*vinsn
)
6615 /* Right now we assume that the ops within the vinsn are properly
6616 ordered for the slots that the programmer wanted them in. In
6617 other words, we don't rearrange the ops in hopes of finding a
6618 better format. The scheduler handles that. */
6620 xtensa_isa isa
= xtensa_default_isa
;
6621 xtensa_format format
;
6622 vliw_insn v_copy
= *vinsn
;
6623 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6625 if (vinsn
->num_slots
== 1)
6626 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6628 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6631 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6635 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6637 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6639 v_copy
.slots
[slot
].opcode
=
6640 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6641 v_copy
.slots
[slot
].ntok
= 0;
6644 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6647 else if (v_copy
.num_slots
> 1)
6650 /* Try the widened version. */
6651 if (!v_copy
.slots
[slot
].keep_wide
6652 && !v_copy
.slots
[slot
].is_specific_opcode
6653 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6655 && opcode_fits_format_slot (widened
.opcode
,
6658 v_copy
.slots
[slot
] = widened
;
6663 if (fit
== v_copy
.num_slots
)
6666 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6667 vinsn
->format
= format
;
6673 if (format
== xtensa_isa_num_formats (isa
))
6674 return XTENSA_UNDEFINED
;
6680 /* Return the additional space needed in a frag
6681 for possible relaxations of any ops in a VLIW insn.
6682 Also fill out the relaxations that might be required of
6683 each tinsn in the vinsn. */
6686 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6688 bfd_boolean finish_frag
= FALSE
;
6689 int extra_space
= 0;
6692 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6694 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6695 if (!tinsn_has_symbolic_operands (tinsn
))
6697 /* A narrow instruction could be widened later to help
6698 alignment issues. */
6699 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6700 && !tinsn
->is_specific_opcode
6701 && vinsn
->num_slots
== 1)
6703 /* Difference in bytes between narrow and wide insns... */
6705 tinsn
->subtype
= RELAX_NARROW
;
6710 if (workaround_b_j_loop_end
6711 && tinsn
->opcode
== xtensa_jx_opcode
6712 && use_transform ())
6714 /* Add 2 of these. */
6715 extra_space
+= 3; /* for the nop size */
6716 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6719 /* Need to assemble it with space for the relocation. */
6720 if (xg_is_relaxable_insn (tinsn
, 0)
6721 && !tinsn
->is_specific_opcode
)
6723 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6724 int max_literal_size
=
6725 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6727 tinsn
->literal_space
= max_literal_size
;
6729 tinsn
->subtype
= RELAX_IMMED
;
6730 extra_space
+= max_size
;
6734 /* A fix record will be added for this instruction prior
6735 to relaxation, so make it end the frag. */
6740 *pfinish_frag
= finish_frag
;
6746 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6748 xtensa_isa isa
= xtensa_default_isa
;
6749 int slot
, chosen_slot
;
6751 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6752 assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6753 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6755 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6756 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6758 if (slot
== chosen_slot
)
6759 vinsn
->slots
[slot
] = *tinsn
;
6762 vinsn
->slots
[slot
].opcode
=
6763 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6764 vinsn
->slots
[slot
].ntok
= 0;
6765 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6772 emit_single_op (TInsn
*orig_insn
)
6775 IStack istack
; /* put instructions into here */
6776 symbolS
*lit_sym
= NULL
;
6777 symbolS
*label_sym
= NULL
;
6779 istack_init (&istack
);
6781 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6782 Because the scheduling and bundling characteristics of movi and
6783 l32r or const16 are so different, we can do much better if we relax
6784 it prior to scheduling and bundling, rather than after. */
6785 if ((orig_insn
->opcode
== xtensa_movi_opcode
6786 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6787 && !cur_vinsn
.inside_bundle
6788 && (orig_insn
->tok
[1].X_op
== O_symbol
6789 || orig_insn
->tok
[1].X_op
== O_pltrel
6790 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6791 || orig_insn
->tok
[1].X_op
== O_tlsarg
6792 || orig_insn
->tok
[1].X_op
== O_tpoff
6793 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6794 && !orig_insn
->is_specific_opcode
&& use_transform ())
6795 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6797 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6800 for (i
= 0; i
< istack
.ninsn
; i
++)
6802 TInsn
*insn
= &istack
.insn
[i
];
6803 switch (insn
->insn_type
)
6806 assert (lit_sym
== NULL
);
6807 lit_sym
= xg_assemble_literal (insn
);
6811 static int relaxed_sym_idx
= 0;
6812 char *label
= xmalloc (strlen (FAKE_LABEL_NAME
) + 12);
6813 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6815 assert (label_sym
== NULL
);
6816 label_sym
= symbol_find_or_make (label
);
6825 xg_resolve_literals (insn
, lit_sym
);
6827 xg_resolve_labels (insn
, label_sym
);
6829 bundle_tinsn (insn
, &v
);
6844 total_frag_text_expansion (fragS
*fragP
)
6847 int total_expansion
= 0;
6849 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
6850 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
6852 return total_expansion
;
6856 /* Emit a vliw instruction to the current fragment. */
6859 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
6861 bfd_boolean finish_frag
;
6862 bfd_boolean is_jump
= FALSE
;
6863 bfd_boolean is_branch
= FALSE
;
6864 xtensa_isa isa
= xtensa_default_isa
;
6869 struct dwarf2_line_info debug_line
;
6870 bfd_boolean loc_directive_seen
= FALSE
;
6873 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
6875 if (generating_literals
)
6877 static int reported
= 0;
6879 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
6880 _("cannot assemble into a literal fragment"));
6887 if (frag_now_fix () != 0
6888 && (! frag_now
->tc_frag_data
.is_insn
6889 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
6890 || !use_transform () != frag_now
->tc_frag_data
.is_no_transform
6891 || (directive_state
[directive_longcalls
]
6892 != frag_now
->tc_frag_data
.use_longcalls
)
6893 || (directive_state
[directive_absolute_literals
]
6894 != frag_now
->tc_frag_data
.use_absolute_literals
)))
6896 frag_wane (frag_now
);
6898 xtensa_set_frag_assembly_state (frag_now
);
6901 if (workaround_a0_b_retw
6902 && vinsn
->num_slots
== 1
6903 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
6904 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
6905 && use_transform ())
6907 has_a0_b_retw
= TRUE
;
6909 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
6910 After the first assembly pass we will check all of them and
6911 add a nop if needed. */
6912 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6913 frag_var (rs_machine_dependent
, 4, 4,
6914 RELAX_ADD_NOP_IF_A0_B_RETW
,
6915 frag_now
->fr_symbol
,
6916 frag_now
->fr_offset
,
6918 xtensa_set_frag_assembly_state (frag_now
);
6919 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6920 frag_var (rs_machine_dependent
, 4, 4,
6921 RELAX_ADD_NOP_IF_A0_B_RETW
,
6922 frag_now
->fr_symbol
,
6923 frag_now
->fr_offset
,
6925 xtensa_set_frag_assembly_state (frag_now
);
6928 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6930 tinsn
= &vinsn
->slots
[slot
];
6932 /* See if the instruction implies an aligned section. */
6933 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
6934 record_alignment (now_seg
, 2);
6936 /* Determine the best line number for debug info. */
6937 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
6938 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
6939 || tinsn
->debug_line
.line
< debug_line
.line
6940 || tinsn
->debug_line
.column
< debug_line
.column
))
6941 debug_line
= tinsn
->debug_line
;
6942 if (tinsn
->loc_directive_seen
)
6943 loc_directive_seen
= TRUE
;
6946 /* Special cases for instructions that force an alignment... */
6947 /* None of these opcodes are bundle-able. */
6948 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
6952 /* Remember the symbol that marks the end of the loop in the frag
6953 that marks the start of the loop. This way we can easily find
6954 the end of the loop at the beginning, without adding special code
6955 to mark the loop instructions themselves. */
6956 symbolS
*target_sym
= NULL
;
6957 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
6958 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
6960 xtensa_set_frag_assembly_state (frag_now
);
6961 frag_now
->tc_frag_data
.is_insn
= TRUE
;
6963 max_fill
= get_text_align_max_fill_size
6964 (get_text_align_power (xtensa_fetch_width
),
6965 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
6967 if (use_transform ())
6968 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
6969 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6971 frag_var (rs_machine_dependent
, 0, 0,
6972 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
6973 xtensa_set_frag_assembly_state (frag_now
);
6976 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
6977 && !vinsn
->slots
[0].is_specific_opcode
)
6979 xtensa_mark_literal_pool_location ();
6980 xtensa_move_labels (frag_now
, 0);
6981 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
6984 if (vinsn
->num_slots
== 1)
6986 if (workaround_a0_b_retw
&& use_transform ())
6987 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
6988 is_register_writer (&vinsn
->slots
[0], "a", 0));
6990 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
6991 is_bad_loopend_opcode (&vinsn
->slots
[0]));
6994 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
6996 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
6998 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7000 /* vinsn_to_insnbuf will produce the error. */
7001 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7003 f
= frag_more (insn_size
+ extra_space
);
7004 xtensa_set_frag_assembly_state (frag_now
);
7005 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7008 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7009 if (vinsn
->format
== XTENSA_UNDEFINED
)
7012 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7014 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7015 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7018 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7020 tinsn
= &vinsn
->slots
[slot
];
7021 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7022 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7023 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7024 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7025 if (tinsn
->literal_space
!= 0)
7026 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7027 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7029 if (tinsn
->subtype
== RELAX_NARROW
)
7030 assert (vinsn
->num_slots
== 1);
7031 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7033 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7036 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7037 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7041 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7042 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7046 frag_variant (rs_machine_dependent
,
7047 extra_space
, extra_space
, RELAX_SLOTS
,
7048 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7049 xtensa_set_frag_assembly_state (frag_now
);
7052 /* Special cases for loops:
7053 close_loop_end should be inserted AFTER short_loop.
7054 Make sure that CLOSE loops are processed BEFORE short_loops
7055 when converting them. */
7057 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7058 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7059 && !vinsn
->slots
[0].is_specific_opcode
)
7061 if (workaround_short_loop
&& use_transform ())
7063 maybe_has_short_loop
= TRUE
;
7064 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7065 frag_var (rs_machine_dependent
, 4, 4,
7066 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7067 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7068 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7069 frag_var (rs_machine_dependent
, 4, 4,
7070 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7071 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7074 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7075 loop at least 12 bytes away from another loop's end. */
7076 if (workaround_close_loop_end
&& use_transform ())
7078 maybe_has_close_loop_end
= TRUE
;
7079 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7080 frag_var (rs_machine_dependent
, 12, 12,
7081 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7082 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7086 if (use_transform ())
7090 assert (finish_frag
);
7091 frag_var (rs_machine_dependent
,
7092 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7094 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7095 xtensa_set_frag_assembly_state (frag_now
);
7097 else if (is_branch
&& do_align_targets ())
7099 assert (finish_frag
);
7100 frag_var (rs_machine_dependent
,
7101 UNREACHABLE_MAX_WIDTH
, UNREACHABLE_MAX_WIDTH
,
7102 RELAX_MAYBE_UNREACHABLE
,
7103 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7104 xtensa_set_frag_assembly_state (frag_now
);
7105 frag_var (rs_machine_dependent
,
7107 RELAX_MAYBE_DESIRE_ALIGN
,
7108 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7109 xtensa_set_frag_assembly_state (frag_now
);
7113 /* Now, if the original opcode was a call... */
7114 if (do_align_targets ()
7115 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7117 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7118 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7119 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7120 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7121 xtensa_set_frag_assembly_state (frag_now
);
7124 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7126 frag_wane (frag_now
);
7128 xtensa_set_frag_assembly_state (frag_now
);
7133 /* xtensa_end and helper functions. */
7135 static void xtensa_cleanup_align_frags (void);
7136 static void xtensa_fix_target_frags (void);
7137 static void xtensa_mark_narrow_branches (void);
7138 static void xtensa_mark_zcl_first_insns (void);
7139 static void xtensa_mark_difference_of_two_symbols (void);
7140 static void xtensa_fix_a0_b_retw_frags (void);
7141 static void xtensa_fix_b_j_loop_end_frags (void);
7142 static void xtensa_fix_close_loop_end_frags (void);
7143 static void xtensa_fix_short_loop_frags (void);
7144 static void xtensa_sanity_check (void);
7145 static void xtensa_add_config_info (void);
7150 directive_balance ();
7151 xtensa_flush_pending_output ();
7153 past_xtensa_end
= TRUE
;
7155 xtensa_move_literals ();
7157 xtensa_reorder_segments ();
7158 xtensa_cleanup_align_frags ();
7159 xtensa_fix_target_frags ();
7160 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7161 xtensa_fix_a0_b_retw_frags ();
7162 if (workaround_b_j_loop_end
)
7163 xtensa_fix_b_j_loop_end_frags ();
7165 /* "close_loop_end" should be processed BEFORE "short_loop". */
7166 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7167 xtensa_fix_close_loop_end_frags ();
7169 if (workaround_short_loop
&& maybe_has_short_loop
)
7170 xtensa_fix_short_loop_frags ();
7172 xtensa_mark_narrow_branches ();
7173 xtensa_mark_zcl_first_insns ();
7175 xtensa_sanity_check ();
7177 xtensa_add_config_info ();
7182 xtensa_cleanup_align_frags (void)
7187 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7188 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7191 /* Walk over all of the fragments in a subsection. */
7192 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7194 if ((fragP
->fr_type
== rs_align
7195 || fragP
->fr_type
== rs_align_code
7196 || (fragP
->fr_type
== rs_machine_dependent
7197 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7198 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7199 && fragP
->fr_fix
== 0)
7201 fragS
*next
= fragP
->fr_next
;
7204 && next
->fr_fix
== 0
7205 && next
->fr_type
== rs_machine_dependent
7206 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7209 next
= next
->fr_next
;
7212 /* If we don't widen branch targets, then they
7213 will be easier to align. */
7214 if (fragP
->tc_frag_data
.is_branch_target
7215 && fragP
->fr_opcode
== fragP
->fr_literal
7216 && fragP
->fr_type
== rs_machine_dependent
7217 && fragP
->fr_subtype
== RELAX_SLOTS
7218 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7220 if (fragP
->fr_type
== rs_machine_dependent
7221 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7222 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7228 /* Re-process all of the fragments looking to convert all of the
7229 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7230 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7231 Otherwise, convert to a .fill 0. */
7234 xtensa_fix_target_frags (void)
7239 /* When this routine is called, all of the subsections are still intact
7240 so we walk over subsections instead of sections. */
7241 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7242 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7246 /* Walk over all of the fragments in a subsection. */
7247 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7249 if (fragP
->fr_type
== rs_machine_dependent
7250 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7252 if (next_frag_is_branch_target (fragP
))
7253 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7262 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7265 xtensa_mark_narrow_branches (void)
7270 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7271 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7274 /* Walk over all of the fragments in a subsection. */
7275 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7277 if (fragP
->fr_type
== rs_machine_dependent
7278 && fragP
->fr_subtype
== RELAX_SLOTS
7279 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7283 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7284 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7286 if (vinsn
.num_slots
== 1
7287 && xtensa_opcode_is_branch (xtensa_default_isa
,
7288 vinsn
.slots
[0].opcode
) == 1
7289 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7290 && is_narrow_branch_guaranteed_in_range (fragP
,
7293 fragP
->fr_subtype
= RELAX_SLOTS
;
7294 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7295 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7303 /* A branch is typically widened only when its target is out of
7304 range. However, we would like to widen them to align a subsequent
7305 branch target when possible.
7307 Because the branch relaxation code is so convoluted, the optimal solution
7308 (combining the two cases) is difficult to get right in all circumstances.
7309 We therefore go with an "almost as good" solution, where we only
7310 use for alignment narrow branches that definitely will not expand to a
7311 jump and a branch. These functions find and mark these cases. */
7313 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7314 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7315 We start counting beginning with the frag after the 2-byte branch, so the
7316 maximum offset is (4 - 2) + 63 = 65. */
7317 #define MAX_IMMED6 65
7319 static offsetT
unrelaxed_frag_max_size (fragS
*);
7322 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7324 const expressionS
*expr
= &tinsn
->tok
[1];
7325 symbolS
*symbolP
= expr
->X_add_symbol
;
7326 offsetT max_distance
= expr
->X_add_number
;
7329 if (expr
->X_op
!= O_symbol
)
7332 target_frag
= symbol_get_frag (symbolP
);
7334 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7335 if (is_branch_jmp_to_next (tinsn
, fragP
))
7338 /* The branch doesn't branch over it's own frag,
7339 but over the subsequent ones. */
7340 fragP
= fragP
->fr_next
;
7341 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7343 max_distance
+= unrelaxed_frag_max_size (fragP
);
7344 fragP
= fragP
->fr_next
;
7346 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7353 xtensa_mark_zcl_first_insns (void)
7358 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7359 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7362 /* Walk over all of the fragments in a subsection. */
7363 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7365 if (fragP
->fr_type
== rs_machine_dependent
7366 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7367 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7369 /* Find the loop frag. */
7370 fragS
*targ_frag
= next_non_empty_frag (fragP
);
7371 /* Find the first insn frag. */
7372 targ_frag
= next_non_empty_frag (targ_frag
);
7374 /* Of course, sometimes (mostly for toy test cases) a
7375 zero-cost loop instruction is the last in a section. */
7378 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7379 /* Do not widen a frag that is the first instruction of a
7380 zero-cost loop. It makes that loop harder to align. */
7381 if (targ_frag
->fr_type
== rs_machine_dependent
7382 && targ_frag
->fr_subtype
== RELAX_SLOTS
7383 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7386 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7387 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7390 frag_wane (targ_frag
);
7391 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7395 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7403 /* When a difference-of-symbols expression is encoded as a uleb128 or
7404 sleb128 value, the linker is unable to adjust that value to account for
7405 link-time relaxation. Mark all the code between such symbols so that
7406 its size cannot be changed by linker relaxation. */
7409 xtensa_mark_difference_of_two_symbols (void)
7413 for (expr_sym
= expr_symbols
; expr_sym
;
7414 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7416 expressionS
*expr
= symbol_get_value_expression (expr_sym
);
7418 if (expr
->X_op
== O_subtract
)
7420 symbolS
*left
= expr
->X_add_symbol
;
7421 symbolS
*right
= expr
->X_op_symbol
;
7423 /* Difference of two symbols not in the same section
7424 are handled with relocations in the linker. */
7425 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7430 if (symbol_get_frag (left
)->fr_address
7431 <= symbol_get_frag (right
)->fr_address
)
7433 start
= symbol_get_frag (left
);
7434 end
= symbol_get_frag (right
);
7438 start
= symbol_get_frag (right
);
7439 end
= symbol_get_frag (left
);
7443 start
->tc_frag_data
.is_no_transform
= 1;
7444 start
= start
->fr_next
;
7446 while (start
&& start
->fr_address
< end
->fr_address
);
7453 /* Re-process all of the fragments looking to convert all of the
7454 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7455 conditional branch or a retw/retw.n, convert this frag to one that
7456 will generate a NOP. In any case close it off with a .fill 0. */
7458 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7461 xtensa_fix_a0_b_retw_frags (void)
7466 /* When this routine is called, all of the subsections are still intact
7467 so we walk over subsections instead of sections. */
7468 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7469 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7473 /* Walk over all of the fragments in a subsection. */
7474 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7476 if (fragP
->fr_type
== rs_machine_dependent
7477 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7479 if (next_instrs_are_b_retw (fragP
))
7481 if (fragP
->tc_frag_data
.is_no_transform
)
7482 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7484 relax_frag_add_nop (fragP
);
7494 next_instrs_are_b_retw (fragS
*fragP
)
7496 xtensa_opcode opcode
;
7498 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7499 static xtensa_insnbuf insnbuf
= NULL
;
7500 static xtensa_insnbuf slotbuf
= NULL
;
7501 xtensa_isa isa
= xtensa_default_isa
;
7504 bfd_boolean branch_seen
= FALSE
;
7508 insnbuf
= xtensa_insnbuf_alloc (isa
);
7509 slotbuf
= xtensa_insnbuf_alloc (isa
);
7512 if (next_fragP
== NULL
)
7515 /* Check for the conditional branch. */
7516 xtensa_insnbuf_from_chars
7517 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7518 fmt
= xtensa_format_decode (isa
, insnbuf
);
7519 if (fmt
== XTENSA_UNDEFINED
)
7522 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7524 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
7525 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
7527 branch_seen
= (branch_seen
7528 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
7534 offset
+= xtensa_format_length (isa
, fmt
);
7535 if (offset
== next_fragP
->fr_fix
)
7537 next_fragP
= next_non_empty_frag (next_fragP
);
7541 if (next_fragP
== NULL
)
7544 /* Check for the retw/retw.n. */
7545 xtensa_insnbuf_from_chars
7546 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
7547 fmt
= xtensa_format_decode (isa
, insnbuf
);
7549 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
7550 have no problems. */
7551 if (fmt
== XTENSA_UNDEFINED
7552 || xtensa_format_num_slots (isa
, fmt
) != 1)
7555 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
7556 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
7558 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
7565 /* Re-process all of the fragments looking to convert all of the
7566 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
7567 loop end label, convert this frag to one that will generate a NOP.
7568 In any case close it off with a .fill 0. */
7570 static bfd_boolean
next_instr_is_loop_end (fragS
*);
7573 xtensa_fix_b_j_loop_end_frags (void)
7578 /* When this routine is called, all of the subsections are still intact
7579 so we walk over subsections instead of sections. */
7580 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7581 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7585 /* Walk over all of the fragments in a subsection. */
7586 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7588 if (fragP
->fr_type
== rs_machine_dependent
7589 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
7591 if (next_instr_is_loop_end (fragP
))
7593 if (fragP
->tc_frag_data
.is_no_transform
)
7594 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
7596 relax_frag_add_nop (fragP
);
7606 next_instr_is_loop_end (fragS
*fragP
)
7608 const fragS
*next_fragP
;
7610 if (next_frag_is_loop_target (fragP
))
7613 next_fragP
= next_non_empty_frag (fragP
);
7614 if (next_fragP
== NULL
)
7617 if (!next_frag_is_loop_target (next_fragP
))
7620 /* If the size is >= 3 then there is more than one instruction here.
7621 The hardware bug will not fire. */
7622 if (next_fragP
->fr_fix
> 3)
7629 /* Re-process all of the fragments looking to convert all of the
7630 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
7631 not MY loop's loop end within 12 bytes, add enough nops here to
7632 make it at least 12 bytes away. In any case close it off with a
7635 static offsetT min_bytes_to_other_loop_end
7636 (fragS
*, fragS
*, offsetT
);
7639 xtensa_fix_close_loop_end_frags (void)
7644 /* When this routine is called, all of the subsections are still intact
7645 so we walk over subsections instead of sections. */
7646 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7647 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7651 fragS
*current_target
= NULL
;
7653 /* Walk over all of the fragments in a subsection. */
7654 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7656 if (fragP
->fr_type
== rs_machine_dependent
7657 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7658 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7659 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7662 && fragP
->fr_type
== rs_machine_dependent
7663 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
7666 int bytes_added
= 0;
7668 #define REQUIRED_LOOP_DIVIDING_BYTES 12
7669 /* Max out at 12. */
7670 min_bytes
= min_bytes_to_other_loop_end
7671 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
7673 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
7675 if (fragP
->tc_frag_data
.is_no_transform
)
7676 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
7679 while (min_bytes
+ bytes_added
7680 < REQUIRED_LOOP_DIVIDING_BYTES
)
7684 if (fragP
->fr_var
< length
)
7685 as_fatal (_("fr_var %lu < length %d"),
7686 (long) fragP
->fr_var
, length
);
7689 assemble_nop (length
,
7690 fragP
->fr_literal
+ fragP
->fr_fix
);
7691 fragP
->fr_fix
+= length
;
7692 fragP
->fr_var
-= length
;
7694 bytes_added
+= length
;
7700 assert (fragP
->fr_type
!= rs_machine_dependent
7701 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
7707 static offsetT
unrelaxed_frag_min_size (fragS
*);
7710 min_bytes_to_other_loop_end (fragS
*fragP
,
7711 fragS
*current_target
,
7715 fragS
*current_fragP
;
7717 for (current_fragP
= fragP
;
7719 current_fragP
= current_fragP
->fr_next
)
7721 if (current_fragP
->tc_frag_data
.is_loop_target
7722 && current_fragP
!= current_target
)
7725 offset
+= unrelaxed_frag_min_size (current_fragP
);
7727 if (offset
>= max_size
)
7735 unrelaxed_frag_min_size (fragS
*fragP
)
7737 offsetT size
= fragP
->fr_fix
;
7739 /* Add fill size. */
7740 if (fragP
->fr_type
== rs_fill
)
7741 size
+= fragP
->fr_offset
;
7748 unrelaxed_frag_max_size (fragS
*fragP
)
7750 offsetT size
= fragP
->fr_fix
;
7751 switch (fragP
->fr_type
)
7754 /* Empty frags created by the obstack allocation scheme
7755 end up with type 0. */
7760 size
+= fragP
->fr_offset
;
7768 /* No further adjustments needed. */
7770 case rs_machine_dependent
:
7771 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
7772 size
+= fragP
->fr_var
;
7775 /* We had darn well better know how big it is. */
7784 /* Re-process all of the fragments looking to convert all
7785 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
7788 1) the instruction size count to the loop end label
7789 is too short (<= 2 instructions),
7790 2) loop has a jump or branch in it
7793 1) workaround_all_short_loops is TRUE
7794 2) The generating loop was a 'loopgtz' or 'loopnez'
7795 3) the instruction size count to the loop end label is too short
7797 then convert this frag (and maybe the next one) to generate a NOP.
7798 In any case close it off with a .fill 0. */
7800 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
7801 static bfd_boolean
branch_before_loop_end (fragS
*);
7804 xtensa_fix_short_loop_frags (void)
7809 /* When this routine is called, all of the subsections are still intact
7810 so we walk over subsections instead of sections. */
7811 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7812 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7815 fragS
*current_target
= NULL
;
7816 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
7818 /* Walk over all of the fragments in a subsection. */
7819 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7821 if (fragP
->fr_type
== rs_machine_dependent
7822 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
7823 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
7826 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7827 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
7828 current_target
= symbol_get_frag (fragP
->fr_symbol
);
7829 current_opcode
= t_insn
.opcode
;
7830 assert (xtensa_opcode_is_loop (xtensa_default_isa
,
7831 current_opcode
) == 1);
7834 if (fragP
->fr_type
== rs_machine_dependent
7835 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7837 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
7838 && (branch_before_loop_end (fragP
->fr_next
)
7839 || (workaround_all_short_loops
7840 && current_opcode
!= XTENSA_UNDEFINED
7841 && current_opcode
!= xtensa_loop_opcode
)))
7843 if (fragP
->tc_frag_data
.is_no_transform
)
7844 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
7846 relax_frag_add_nop (fragP
);
7855 static int unrelaxed_frag_min_insn_count (fragS
*);
7858 count_insns_to_loop_end (fragS
*base_fragP
,
7859 bfd_boolean count_relax_add
,
7862 fragS
*fragP
= NULL
;
7867 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
7869 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
7870 if (insn_count
>= max_count
)
7873 if (count_relax_add
)
7875 if (fragP
->fr_type
== rs_machine_dependent
7876 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
7878 /* In order to add the appropriate number of
7879 NOPs, we count an instruction for downstream
7882 if (insn_count
>= max_count
)
7892 unrelaxed_frag_min_insn_count (fragS
*fragP
)
7894 xtensa_isa isa
= xtensa_default_isa
;
7895 static xtensa_insnbuf insnbuf
= NULL
;
7899 if (!fragP
->tc_frag_data
.is_insn
)
7903 insnbuf
= xtensa_insnbuf_alloc (isa
);
7905 /* Decode the fixed instructions. */
7906 while (offset
< fragP
->fr_fix
)
7910 xtensa_insnbuf_from_chars
7911 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7912 fmt
= xtensa_format_decode (isa
, insnbuf
);
7914 if (fmt
== XTENSA_UNDEFINED
)
7916 as_fatal (_("undecodable instruction in instruction frag"));
7919 offset
+= xtensa_format_length (isa
, fmt
);
7927 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
7930 branch_before_loop_end (fragS
*base_fragP
)
7934 for (fragP
= base_fragP
;
7935 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
7936 fragP
= fragP
->fr_next
)
7938 if (unrelaxed_frag_has_b_j (fragP
))
7946 unrelaxed_frag_has_b_j (fragS
*fragP
)
7948 static xtensa_insnbuf insnbuf
= NULL
;
7949 xtensa_isa isa
= xtensa_default_isa
;
7952 if (!fragP
->tc_frag_data
.is_insn
)
7956 insnbuf
= xtensa_insnbuf_alloc (isa
);
7958 /* Decode the fixed instructions. */
7959 while (offset
< fragP
->fr_fix
)
7964 xtensa_insnbuf_from_chars
7965 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
7966 fmt
= xtensa_format_decode (isa
, insnbuf
);
7967 if (fmt
== XTENSA_UNDEFINED
)
7970 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
7972 xtensa_opcode opcode
=
7973 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
7974 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
7975 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
7978 offset
+= xtensa_format_length (isa
, fmt
);
7984 /* Checks to be made after initial assembly but before relaxation. */
7986 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
7987 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
7990 xtensa_sanity_check (void)
7997 as_where (&file_name
, &line
);
7998 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7999 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8003 /* Walk over all of the fragments in a subsection. */
8004 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8006 if (fragP
->fr_type
== rs_machine_dependent
8007 && fragP
->fr_subtype
== RELAX_SLOTS
8008 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8010 static xtensa_insnbuf insnbuf
= NULL
;
8013 if (fragP
->fr_opcode
!= NULL
)
8016 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8017 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8018 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8020 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8021 t_insn
.opcode
) == 1)
8023 if (is_empty_loop (&t_insn
, fragP
))
8025 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8026 as_bad (_("invalid empty loop"));
8028 if (!is_local_forward_loop (&t_insn
, fragP
))
8030 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8031 as_bad (_("loop target does not follow "
8032 "loop instruction in section"));
8039 new_logical_line (file_name
, line
);
8043 #define LOOP_IMMED_OPN 1
8045 /* Return TRUE if the loop target is the next non-zero fragment. */
8048 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8050 const expressionS
*expr
;
8054 if (insn
->insn_type
!= ITYPE_INSN
)
8057 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8060 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8063 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8065 if (expr
->X_op
!= O_symbol
)
8068 symbolP
= expr
->X_add_symbol
;
8072 if (symbol_get_frag (symbolP
) == NULL
)
8075 if (S_GET_VALUE (symbolP
) != 0)
8078 /* Walk through the zero-size fragments from this one. If we find
8079 the target fragment, then this is a zero-size loop. */
8081 for (next_fragP
= fragP
->fr_next
;
8083 next_fragP
= next_fragP
->fr_next
)
8085 if (next_fragP
== symbol_get_frag (symbolP
))
8087 if (next_fragP
->fr_fix
!= 0)
8095 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8097 const expressionS
*expr
;
8101 if (insn
->insn_type
!= ITYPE_INSN
)
8104 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8107 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8110 expr
= &insn
->tok
[LOOP_IMMED_OPN
];
8112 if (expr
->X_op
!= O_symbol
)
8115 symbolP
= expr
->X_add_symbol
;
8119 if (symbol_get_frag (symbolP
) == NULL
)
8122 /* Walk through fragments until we find the target.
8123 If we do not find the target, then this is an invalid loop. */
8125 for (next_fragP
= fragP
->fr_next
;
8127 next_fragP
= next_fragP
->fr_next
)
8129 if (next_fragP
== symbol_get_frag (symbolP
))
8137 #define XTINFO_NAME "Xtensa_Info"
8138 #define XTINFO_NAMESZ 12
8139 #define XTINFO_TYPE 1
8142 xtensa_add_config_info (void)
8148 info_sec
= subseg_new (".xtensa.info", 0);
8149 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8151 data
= xmalloc (100);
8152 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8153 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8154 sz
= strlen (data
) + 1;
8156 /* Add enough null terminators to pad to a word boundary. */
8159 while ((sz
& 3) != 0);
8161 /* Follow the standard note section layout:
8162 First write the length of the name string. */
8164 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8166 /* Next comes the length of the "descriptor", i.e., the actual data. */
8168 md_number_to_chars (p
, (valueT
) sz
, 4);
8170 /* Write the note type. */
8172 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8174 /* Write the name field. */
8175 p
= frag_more (XTINFO_NAMESZ
);
8176 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8178 /* Finally, write the descriptor. */
8180 memcpy (p
, data
, sz
);
8186 /* Alignment Functions. */
8189 get_text_align_power (unsigned target_size
)
8191 if (target_size
<= 4)
8193 assert (target_size
== 8);
8199 get_text_align_max_fill_size (int align_pow
,
8200 bfd_boolean use_nops
,
8201 bfd_boolean use_no_density
)
8204 return (1 << align_pow
);
8206 return 3 * (1 << align_pow
);
8208 return 1 + (1 << align_pow
);
8212 /* Calculate the minimum bytes of fill needed at "address" to align a
8213 target instruction of size "target_size" so that it does not cross a
8214 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8215 the fill can be an arbitrary number of bytes. Otherwise, the space must
8216 be filled by NOP instructions. */
8219 get_text_align_fill_size (addressT address
,
8222 bfd_boolean use_nops
,
8223 bfd_boolean use_no_density
)
8225 addressT alignment
, fill
, fill_limit
, fill_step
;
8226 bfd_boolean skip_one
= FALSE
;
8228 alignment
= (1 << align_pow
);
8229 assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8233 fill_limit
= alignment
;
8236 else if (!use_no_density
)
8238 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8239 fill_limit
= alignment
* 2;
8245 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8246 fill_limit
= alignment
* 3;
8250 /* Try all fill sizes until finding one that works. */
8251 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8253 if (skip_one
&& fill
== 1)
8255 if ((address
+ fill
) >> align_pow
8256 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8265 branch_align_power (segT sec
)
8267 /* If the Xtensa processor has a fetch width of 8 bytes, and the section
8268 is aligned to at least an 8-byte boundary, then a branch target need
8269 only fit within an 8-byte aligned block of memory to avoid a stall.
8270 Otherwise, try to fit branch targets within 4-byte aligned blocks
8271 (which may be insufficient, e.g., if the section has no alignment, but
8272 it's good enough). */
8273 if (xtensa_fetch_width
== 8)
8275 if (get_recorded_alignment (sec
) >= 3)
8279 assert (xtensa_fetch_width
== 4);
8285 /* This will assert if it is not possible. */
8288 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8294 assert (fill_size
% 3 == 0);
8295 return (fill_size
/ 3);
8298 assert (fill_size
!= 1); /* Bad argument. */
8300 while (fill_size
> 1)
8303 if (fill_size
== 2 || fill_size
== 4)
8305 fill_size
-= insn_size
;
8308 assert (fill_size
!= 1); /* Bad algorithm. */
8314 get_text_align_nth_nop_size (offsetT fill_size
,
8316 bfd_boolean use_no_density
)
8323 assert (fill_size
!= 1); /* Bad argument. */
8325 while (fill_size
> 1)
8328 if (fill_size
== 2 || fill_size
== 4)
8330 fill_size
-= insn_size
;
8340 /* For the given fragment, find the appropriate address
8341 for it to begin at if we are using NOPs to align it. */
8344 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8346 /* The rule is: get next fragment's FIRST instruction. Find
8347 the smallest number of bytes that need to be added to
8348 ensure that the next fragment's FIRST instruction will fit
8351 E.G., 2 bytes : 0, 1, 2 mod 4
8354 If the FIRST instruction MIGHT be relaxed,
8355 assume that it will become a 3-byte instruction.
8357 Note again here that LOOP instructions are not bundleable,
8358 and this relaxation only applies to LOOP opcodes. */
8361 int first_insn_size
;
8363 addressT pre_opcode_bytes
;
8366 xtensa_opcode opcode
;
8367 bfd_boolean is_loop
;
8369 assert (fragP
->fr_type
== rs_machine_dependent
);
8370 assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8372 /* Find the loop frag. */
8373 first_insn
= next_non_empty_frag (fragP
);
8374 /* Now find the first insn frag. */
8375 first_insn
= next_non_empty_frag (first_insn
);
8377 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8379 loop_insn_size
= xg_get_single_size (opcode
);
8381 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8382 pre_opcode_bytes
+= loop_insn_size
;
8384 /* For loops, the alignment depends on the size of the
8385 instruction following the loop, not the LOOP instruction. */
8387 if (first_insn
== NULL
)
8388 first_insn_size
= xtensa_fetch_width
;
8390 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8392 /* If it was 8, then we'll need a larger alignment for the section. */
8393 align_power
= get_text_align_power (first_insn_size
);
8394 record_alignment (now_seg
, align_power
);
8396 fill_size
= get_text_align_fill_size
8397 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8398 fragP
->tc_frag_data
.is_no_density
);
8400 return address
+ fill_size
;
8404 /* 3 mechanisms for relaxing an alignment:
8406 Align to a power of 2.
8407 Align so the next fragment's instruction does not cross a word boundary.
8408 Align the current instruction so that if the next instruction
8409 were 3 bytes, it would not cross a word boundary.
8413 zeros - This is easy; always insert zeros.
8414 nops - 3-byte and 2-byte instructions
8418 >=5 : 3-byte instruction + fn (n-3)
8419 widening - widen previous instructions. */
8422 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8424 addressT target_address
, loop_insn_offset
;
8426 xtensa_opcode loop_opcode
;
8427 bfd_boolean is_loop
;
8430 offsetT branch_align
;
8433 assert (fragP
->fr_type
== rs_machine_dependent
);
8434 switch (fragP
->fr_subtype
)
8436 case RELAX_DESIRE_ALIGN
:
8437 target_size
= next_frag_format_size (fragP
);
8438 if (target_size
== XTENSA_UNDEFINED
)
8440 align_power
= branch_align_power (now_seg
);
8441 branch_align
= 1 << align_power
;
8442 /* Don't count on the section alignment being as large as the target. */
8443 if (target_size
> branch_align
)
8444 target_size
= branch_align
;
8445 opt_diff
= get_text_align_fill_size (address
, align_power
,
8446 target_size
, FALSE
, FALSE
);
8448 *max_diff
= (opt_diff
+ branch_align
8449 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8450 assert (*max_diff
>= opt_diff
);
8453 case RELAX_ALIGN_NEXT_OPCODE
:
8454 /* The next non-empty frag after this one holds the LOOP instruction
8455 that needs to be aligned. The required alignment depends on the
8456 size of the next non-empty frag after the loop frag, i.e., the
8457 first instruction in the loop. */
8458 loop_frag
= next_non_empty_frag (fragP
);
8459 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8460 loop_insn_offset
= 0;
8461 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8464 /* If the loop has been expanded then the LOOP instruction
8465 could be at an offset from this fragment. */
8466 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8467 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8469 /* In an ideal world, which is what we are shooting for here,
8470 we wouldn't need to use any NOPs immediately prior to the
8471 LOOP instruction. If this approach fails, relax_frag_loop_align
8472 will call get_noop_aligned_address. */
8474 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8475 align_power
= get_text_align_power (target_size
);
8476 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8477 target_size
, FALSE
, FALSE
);
8479 *max_diff
= xtensa_fetch_width
8480 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8481 - target_size
+ opt_diff
;
8482 assert (*max_diff
>= opt_diff
);
8493 /* md_relax_frag Hook and Helper Functions. */
8495 static long relax_frag_loop_align (fragS
*, long);
8496 static long relax_frag_for_align (fragS
*, long);
8497 static long relax_frag_immed
8498 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
8501 /* Return the number of bytes added to this fragment, given that the
8502 input has been stretched already by "stretch". */
8505 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
8507 xtensa_isa isa
= xtensa_default_isa
;
8508 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
8509 long new_stretch
= 0;
8513 static xtensa_insnbuf vbuf
= NULL
;
8514 int slot
, num_slots
;
8517 as_where (&file_name
, &line
);
8518 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8520 fragP
->tc_frag_data
.unreported_expansion
= 0;
8522 switch (fragP
->fr_subtype
)
8524 case RELAX_ALIGN_NEXT_OPCODE
:
8525 /* Always convert. */
8526 if (fragP
->tc_frag_data
.relax_seen
)
8527 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
8530 case RELAX_LOOP_END
:
8534 case RELAX_LOOP_END_ADD_NOP
:
8535 /* Add a NOP and switch to .fill 0. */
8536 new_stretch
= relax_frag_add_nop (fragP
);
8540 case RELAX_DESIRE_ALIGN
:
8541 /* Do nothing. The narrowing before this frag will either align
8546 case RELAX_LITERAL_FINAL
:
8549 case RELAX_LITERAL_NR
:
8551 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
8552 assert (unreported
== lit_size
);
8553 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
8554 fragP
->fr_var
-= lit_size
;
8555 fragP
->fr_fix
+= lit_size
;
8561 vbuf
= xtensa_insnbuf_alloc (isa
);
8563 xtensa_insnbuf_from_chars
8564 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
8565 fmt
= xtensa_format_decode (isa
, vbuf
);
8566 num_slots
= xtensa_format_num_slots (isa
, fmt
);
8568 for (slot
= 0; slot
< num_slots
; slot
++)
8570 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
8573 if (fragP
->tc_frag_data
.relax_seen
)
8574 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8578 case RELAX_IMMED_STEP1
:
8579 case RELAX_IMMED_STEP2
:
8580 case RELAX_IMMED_STEP3
:
8581 /* Place the immediate. */
8582 new_stretch
+= relax_frag_immed
8583 (now_seg
, fragP
, stretch
,
8584 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
8585 fmt
, slot
, stretched_p
, FALSE
);
8589 /* This is OK; see the note in xg_assemble_vliw_tokens. */
8595 case RELAX_LITERAL_POOL_BEGIN
:
8596 case RELAX_LITERAL_POOL_END
:
8597 case RELAX_MAYBE_UNREACHABLE
:
8598 case RELAX_MAYBE_DESIRE_ALIGN
:
8599 /* No relaxation required. */
8602 case RELAX_FILL_NOP
:
8603 case RELAX_UNREACHABLE
:
8604 if (fragP
->tc_frag_data
.relax_seen
)
8605 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
8609 as_bad (_("bad relaxation state"));
8612 /* Tell gas we need another relaxation pass. */
8613 if (! fragP
->tc_frag_data
.relax_seen
)
8615 fragP
->tc_frag_data
.relax_seen
= TRUE
;
8619 new_logical_line (file_name
, line
);
8625 relax_frag_loop_align (fragS
*fragP
, long stretch
)
8627 addressT old_address
, old_next_address
, old_size
;
8628 addressT new_address
, new_next_address
, new_size
;
8631 /* All the frags with relax_frag_for_alignment prior to this one in the
8632 section have been done, hopefully eliminating the need for a NOP here.
8633 But, this will put it in if necessary. */
8635 /* Calculate the old address of this fragment and the next fragment. */
8636 old_address
= fragP
->fr_address
- stretch
;
8637 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
8638 fragP
->tc_frag_data
.text_expansion
[0]);
8639 old_size
= old_next_address
- old_address
;
8641 /* Calculate the new address of this fragment and the next fragment. */
8642 new_address
= fragP
->fr_address
;
8644 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
8645 new_size
= new_next_address
- new_address
;
8647 growth
= new_size
- old_size
;
8649 /* Fix up the text_expansion field and return the new growth. */
8650 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
8655 /* Add a NOP instruction. */
8658 relax_frag_add_nop (fragS
*fragP
)
8660 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
8661 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
8662 assemble_nop (length
, nop_buf
);
8663 fragP
->tc_frag_data
.is_insn
= TRUE
;
8665 if (fragP
->fr_var
< length
)
8667 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
8671 fragP
->fr_fix
+= length
;
8672 fragP
->fr_var
-= length
;
8677 static long future_alignment_required (fragS
*, long);
8680 relax_frag_for_align (fragS
*fragP
, long stretch
)
8682 /* Overview of the relaxation procedure for alignment:
8683 We can widen with NOPs or by widening instructions or by filling
8684 bytes after jump instructions. Find the opportune places and widen
8685 them if necessary. */
8690 assert (fragP
->fr_subtype
== RELAX_FILL_NOP
8691 || fragP
->fr_subtype
== RELAX_UNREACHABLE
8692 || (fragP
->fr_subtype
== RELAX_SLOTS
8693 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
8695 stretch_me
= future_alignment_required (fragP
, stretch
);
8696 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
8702 /* We expanded on a previous pass. Can we shrink now? */
8703 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
8704 if (shrink
<= stretch
&& stretch
> 0)
8706 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8712 /* Below here, diff > 0. */
8713 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
8719 /* Return the address of the next frag that should be aligned.
8721 By "address" we mean the address it _would_ be at if there
8722 is no action taken to align it between here and the target frag.
8723 In other words, if no narrows and no fill nops are used between
8724 here and the frag to align, _even_if_ some of the frags we use
8725 to align targets have already expanded on a previous relaxation
8728 Also, count each frag that may be used to help align the target.
8730 Return 0 if there are no frags left in the chain that need to be
8734 find_address_of_next_align_frag (fragS
**fragPP
,
8738 bfd_boolean
*paddable
)
8740 fragS
*fragP
= *fragPP
;
8741 addressT address
= fragP
->fr_address
;
8743 /* Do not reset the counts to 0. */
8747 /* Limit this to a small search. */
8748 if (*widens
>= (int) xtensa_fetch_width
)
8753 address
+= fragP
->fr_fix
;
8755 if (fragP
->fr_type
== rs_fill
)
8756 address
+= fragP
->fr_offset
* fragP
->fr_var
;
8757 else if (fragP
->fr_type
== rs_machine_dependent
)
8759 switch (fragP
->fr_subtype
)
8761 case RELAX_UNREACHABLE
:
8765 case RELAX_FILL_NOP
:
8767 if (!fragP
->tc_frag_data
.is_no_density
)
8772 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8777 address
+= total_frag_text_expansion (fragP
);;
8781 address
+= fragP
->tc_frag_data
.text_expansion
[0];
8784 case RELAX_ALIGN_NEXT_OPCODE
:
8785 case RELAX_DESIRE_ALIGN
:
8789 case RELAX_MAYBE_UNREACHABLE
:
8790 case RELAX_MAYBE_DESIRE_ALIGN
:
8795 /* Just punt if we don't know the type. */
8802 /* Just punt if we don't know the type. */
8806 fragP
= fragP
->fr_next
;
8814 static long bytes_to_stretch (fragS
*, int, int, int, int);
8817 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
8819 fragS
*this_frag
= fragP
;
8823 int narrow_nops
= 0;
8824 bfd_boolean paddable
= FALSE
;
8825 offsetT local_opt_diff
;
8828 int stretch_amount
= 0;
8829 int local_stretch_amount
;
8830 int global_stretch_amount
;
8832 address
= find_address_of_next_align_frag
8833 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
8837 if (this_frag
->tc_frag_data
.is_aligning_branch
)
8838 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
8840 frag_wane (this_frag
);
8844 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
8845 opt_diff
= local_opt_diff
;
8846 assert (opt_diff
>= 0);
8847 assert (max_diff
>= opt_diff
);
8852 fragP
= fragP
->fr_next
;
8854 while (fragP
&& opt_diff
< max_diff
&& address
)
8856 /* We only use these to determine if we can exit early
8857 because there will be plenty of ways to align future
8859 int glob_widens
= 0;
8862 bfd_boolean glob_pad
= 0;
8863 address
= find_address_of_next_align_frag
8864 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
8865 /* If there is a padable portion, then skip. */
8866 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
8871 offsetT next_m_diff
;
8872 offsetT next_o_diff
;
8874 /* Downrange frags haven't had stretch added to them yet. */
8877 /* The address also includes any text expansion from this
8878 frag in a previous pass, but we don't want that. */
8879 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
8881 /* Assume we are going to move at least opt_diff. In
8882 reality, we might not be able to, but assuming that
8883 we will helps catch cases where moving opt_diff pushes
8884 the next target from aligned to unaligned. */
8885 address
+= opt_diff
;
8887 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
8889 /* Now cleanup for the adjustments to address. */
8890 next_o_diff
+= opt_diff
;
8891 next_m_diff
+= opt_diff
;
8892 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
8893 opt_diff
= next_o_diff
;
8894 if (next_m_diff
< max_diff
)
8895 max_diff
= next_m_diff
;
8896 fragP
= fragP
->fr_next
;
8900 /* If there are enough wideners in between, do it. */
8903 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
8905 assert (opt_diff
<= UNREACHABLE_MAX_WIDTH
);
8910 local_stretch_amount
8911 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8912 num_widens
, local_opt_diff
);
8913 global_stretch_amount
8914 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
8915 num_widens
, opt_diff
);
8916 /* If the condition below is true, then the frag couldn't
8917 stretch the correct amount for the global case, so we just
8918 optimize locally. We'll rely on the subsequent frags to get
8919 the correct alignment in the global case. */
8920 if (global_stretch_amount
< local_stretch_amount
)
8921 stretch_amount
= local_stretch_amount
;
8923 stretch_amount
= global_stretch_amount
;
8925 if (this_frag
->fr_subtype
== RELAX_SLOTS
8926 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
8927 assert (stretch_amount
<= 1);
8928 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
8930 if (this_frag
->tc_frag_data
.is_no_density
)
8931 assert (stretch_amount
== 3 || stretch_amount
== 0);
8933 assert (stretch_amount
<= 3);
8936 return stretch_amount
;
8940 /* The idea: widen everything you can to get a target or loop aligned,
8941 then start using NOPs.
8943 When we must have a NOP, here is a table of how we decide
8944 (so you don't have to fight through the control flow below):
8946 wide_nops = the number of wide NOPs available for aligning
8947 narrow_nops = the number of narrow NOPs available for aligning
8948 (a subset of wide_nops)
8949 widens = the number of narrow instructions that should be widened
8956 b 0 1 1 (case 3a makes this case unnecessary)
8959 c 0 1 2 (case 4a makes this case unnecessary)
8962 c 0 2 1 (case 5b makes this case unnecessary)
8965 c 0 1 4 (case 6b makes this case unnecessary)
8966 d 1 1 1 (case 6a makes this case unnecessary)
8967 e 0 2 2 (case 6a makes this case unnecessary)
8968 f 0 3 0 (case 6a makes this case unnecessary)
8971 c 1 1 2 (case 7b makes this case unnecessary)
8972 d 0 1 5 (case 7a makes this case unnecessary)
8973 e 0 2 3 (case 7b makes this case unnecessary)
8974 f 0 3 1 (case 7b makes this case unnecessary)
8975 g 1 2 1 (case 7b makes this case unnecessary)
8979 bytes_to_stretch (fragS
*this_frag
,
8985 int bytes_short
= desired_diff
- num_widens
;
8987 assert (desired_diff
>= 0 && desired_diff
< 8);
8988 if (desired_diff
== 0)
8991 assert (wide_nops
> 0 || num_widens
> 0);
8993 /* Always prefer widening to NOP-filling. */
8994 if (bytes_short
< 0)
8996 /* There are enough RELAX_NARROW frags after this one
8997 to align the target without widening this frag in any way. */
9001 if (bytes_short
== 0)
9003 /* Widen every narrow between here and the align target
9004 and the align target will be properly aligned. */
9005 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9011 /* From here we will need at least one NOP to get an alignment.
9012 However, we may not be able to align at all, in which case,
9014 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9016 switch (desired_diff
)
9021 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 1)
9022 return 2; /* case 2 */
9028 return 3; /* case 3a */
9030 if (num_widens
>= 1 && wide_nops
== 1)
9031 return 3; /* case 4a */
9032 if (!this_frag
->tc_frag_data
.is_no_density
&& narrow_nops
== 2)
9033 return 2; /* case 4b */
9036 if (num_widens
>= 2 && wide_nops
== 1)
9037 return 3; /* case 5a */
9038 /* We will need two nops. Are there enough nops
9039 between here and the align target? */
9040 if (wide_nops
< 2 || narrow_nops
== 0)
9042 /* Are there other nops closer that can serve instead? */
9043 if (wide_nops
> 2 && narrow_nops
> 1)
9045 /* Take the density one first, because there might not be
9046 another density one available. */
9047 if (!this_frag
->tc_frag_data
.is_no_density
)
9048 return 2; /* case 5b narrow */
9050 return 3; /* case 5b wide */
9054 return 3; /* case 6a */
9055 else if (num_widens
>= 3 && wide_nops
== 1)
9056 return 3; /* case 6b */
9059 if (wide_nops
== 1 && num_widens
>= 4)
9060 return 3; /* case 7a */
9061 else if (wide_nops
== 2 && num_widens
>= 1)
9062 return 3; /* case 7b */
9070 /* We will need a NOP no matter what, but should we widen
9071 this instruction to help?
9073 This is a RELAX_NARROW frag. */
9074 switch (desired_diff
)
9083 if (wide_nops
>= 1 && num_widens
== 1)
9084 return 1; /* case 4a */
9087 if (wide_nops
>= 1 && num_widens
== 2)
9088 return 1; /* case 5a */
9092 return 0; /* case 6a */
9093 else if (wide_nops
>= 1 && num_widens
== 3)
9094 return 1; /* case 6b */
9097 if (wide_nops
>= 1 && num_widens
== 4)
9098 return 1; /* case 7a */
9099 else if (wide_nops
>= 2 && num_widens
== 1)
9100 return 1; /* case 7b */
9113 relax_frag_immed (segT segP
,
9120 bfd_boolean estimate_only
)
9124 bfd_boolean negatable_branch
= FALSE
;
9125 bfd_boolean branch_jmp_to_next
= FALSE
;
9126 bfd_boolean from_wide_insn
= FALSE
;
9127 xtensa_isa isa
= xtensa_default_isa
;
9129 offsetT frag_offset
;
9131 int num_text_bytes
, num_literal_bytes
;
9132 int literal_diff
, total_text_diff
, this_text_diff
;
9134 assert (fragP
->fr_opcode
!= NULL
);
9136 xg_clear_vinsn (&cur_vinsn
);
9137 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
9138 if (cur_vinsn
.num_slots
> 1)
9139 from_wide_insn
= TRUE
;
9141 tinsn
= cur_vinsn
.slots
[slot
];
9142 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
9144 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
9147 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9148 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
9150 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
9152 old_size
= xtensa_format_length (isa
, fmt
);
9154 /* Special case: replace a branch to the next instruction with a NOP.
9155 This is required to work around a hardware bug in T1040.0 and also
9156 serves as an optimization. */
9158 if (branch_jmp_to_next
9159 && ((old_size
== 2) || (old_size
== 3))
9160 && !next_frag_is_loop_target (fragP
))
9163 /* Here is the fun stuff: Get the immediate field from this
9164 instruction. If it fits, we are done. If not, find the next
9165 instruction sequence that fits. */
9167 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9168 istack_init (&istack
);
9169 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
9170 min_steps
, stretch
);
9171 assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9173 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
9175 /* Figure out the number of bytes needed. */
9176 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9178 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9179 num_text_bytes
= get_num_stack_text_bytes (&istack
);
9184 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
9187 num_text_bytes
+= old_size
;
9188 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
9189 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
9192 /* The first instruction in the relaxed sequence will go after
9193 the current wide instruction, and thus its symbolic immediates
9196 istack_init (&istack
);
9197 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
9198 frag_offset
+ old_size
,
9199 min_steps
, stretch
+ old_size
);
9200 assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
9202 fragP
->tc_frag_data
.slot_subtypes
[slot
]
9203 = (int) RELAX_IMMED
+ num_steps
;
9205 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
9207 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
9209 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
9213 total_text_diff
= num_text_bytes
- old_size
;
9214 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
9216 /* It MUST get larger. If not, we could get an infinite loop. */
9217 assert (num_text_bytes
>= 0);
9218 assert (literal_diff
>= 0);
9219 assert (total_text_diff
>= 0);
9221 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
9222 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
9223 assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
9224 assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
9226 /* Find the associated expandable literal for this. */
9227 if (literal_diff
!= 0)
9229 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
9232 assert (literal_diff
== 4);
9233 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
9235 /* We expect that the literal section state has NOT been
9237 assert (lit_fragP
->fr_type
== rs_machine_dependent
9238 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
9239 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
9241 /* We need to mark this section for another iteration
9247 if (negatable_branch
&& istack
.ninsn
> 1)
9248 update_next_frag_state (fragP
);
9250 return this_text_diff
;
9254 /* md_convert_frag Hook and Helper Functions. */
9256 static void convert_frag_align_next_opcode (fragS
*);
9257 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
9258 static void convert_frag_fill_nop (fragS
*);
9259 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
9262 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
9264 static xtensa_insnbuf vbuf
= NULL
;
9265 xtensa_isa isa
= xtensa_default_isa
;
9272 as_where (&file_name
, &line
);
9273 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
9275 switch (fragp
->fr_subtype
)
9277 case RELAX_ALIGN_NEXT_OPCODE
:
9278 /* Always convert. */
9279 convert_frag_align_next_opcode (fragp
);
9282 case RELAX_DESIRE_ALIGN
:
9283 /* Do nothing. If not aligned already, too bad. */
9287 case RELAX_LITERAL_FINAL
:
9292 vbuf
= xtensa_insnbuf_alloc (isa
);
9294 xtensa_insnbuf_from_chars
9295 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
9296 fmt
= xtensa_format_decode (isa
, vbuf
);
9297 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9299 for (slot
= 0; slot
< num_slots
; slot
++)
9301 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
9304 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
9308 case RELAX_IMMED_STEP1
:
9309 case RELAX_IMMED_STEP2
:
9310 case RELAX_IMMED_STEP3
:
9311 /* Place the immediate. */
9314 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9319 /* This is OK because some slots could have
9320 relaxations and others have none. */
9326 case RELAX_UNREACHABLE
:
9327 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
9328 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
9329 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
9333 case RELAX_MAYBE_UNREACHABLE
:
9334 case RELAX_MAYBE_DESIRE_ALIGN
:
9338 case RELAX_FILL_NOP
:
9339 convert_frag_fill_nop (fragp
);
9342 case RELAX_LITERAL_NR
:
9343 if (use_literal_section
)
9345 /* This should have been handled during relaxation. When
9346 relaxing a code segment, literals sometimes need to be
9347 added to the corresponding literal segment. If that
9348 literal segment has already been relaxed, then we end up
9349 in this situation. Marking the literal segments as data
9350 would make this happen less often (since GAS always relaxes
9351 code before data), but we could still get into trouble if
9352 there are instructions in a segment that is not marked as
9353 containing code. Until we can implement a better solution,
9354 cheat and adjust the addresses of all the following frags.
9355 This could break subsequent alignments, but the linker's
9356 literal coalescing will do that anyway. */
9359 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
9360 assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
9361 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
9364 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
9368 as_bad (_("invalid relaxation fragment result"));
9373 new_logical_line (file_name
, line
);
9378 convert_frag_align_next_opcode (fragS
*fragp
)
9380 char *nop_buf
; /* Location for Writing. */
9381 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
9382 addressT aligned_address
;
9386 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
9388 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
9389 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
9390 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
9392 for (nop
= 0; nop
< nop_count
; nop
++)
9395 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
9397 assemble_nop (nop_size
, nop_buf
);
9398 nop_buf
+= nop_size
;
9401 fragp
->fr_fix
+= fill_size
;
9402 fragp
->fr_var
-= fill_size
;
9407 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
9409 TInsn tinsn
, single_target
;
9410 int size
, old_size
, diff
;
9411 offsetT frag_offset
;
9414 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
9416 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
9418 assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
9419 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
9420 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
9425 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
9427 /* No conversion. */
9432 assert (fragP
->fr_opcode
!= NULL
);
9434 /* Frags in this relaxation state should only contain
9435 single instruction bundles. */
9436 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
9438 /* Just convert it to a wide form.... */
9440 old_size
= xg_get_single_size (tinsn
.opcode
);
9442 tinsn_init (&single_target
);
9443 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
9445 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
9447 as_bad (_("unable to widen instruction"));
9451 size
= xg_get_single_size (single_target
.opcode
);
9452 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
9455 diff
= size
- old_size
;
9457 assert (diff
<= fragP
->fr_var
);
9458 fragP
->fr_var
-= diff
;
9459 fragP
->fr_fix
+= diff
;
9467 convert_frag_fill_nop (fragS
*fragP
)
9469 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
9470 int size
= fragP
->tc_frag_data
.text_expansion
[0];
9471 assert ((unsigned) size
== (fragP
->fr_next
->fr_address
9472 - fragP
->fr_address
- fragP
->fr_fix
));
9475 /* No conversion. */
9479 assemble_nop (size
, loc
);
9480 fragP
->tc_frag_data
.is_insn
= TRUE
;
9481 fragP
->fr_var
-= size
;
9482 fragP
->fr_fix
+= size
;
9487 static fixS
*fix_new_exp_in_seg
9488 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
9489 bfd_reloc_code_real_type
);
9490 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
9493 convert_frag_immed (segT segP
,
9499 char *immed_instr
= fragP
->fr_opcode
;
9501 bfd_boolean expanded
= FALSE
;
9502 bfd_boolean branch_jmp_to_next
= FALSE
;
9503 char *fr_opcode
= fragP
->fr_opcode
;
9504 xtensa_isa isa
= xtensa_default_isa
;
9505 bfd_boolean from_wide_insn
= FALSE
;
9507 bfd_boolean is_loop
;
9509 assert (fr_opcode
!= NULL
);
9511 xg_clear_vinsn (&cur_vinsn
);
9513 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
9514 if (cur_vinsn
.num_slots
> 1)
9515 from_wide_insn
= TRUE
;
9517 orig_tinsn
= cur_vinsn
.slots
[slot
];
9518 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
9520 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
9522 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
9523 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
9525 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
9527 /* Conversion just inserts a NOP and marks the fix as completed. */
9528 bytes
= xtensa_format_length (isa
, fmt
);
9531 cur_vinsn
.slots
[slot
].opcode
=
9532 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
9533 cur_vinsn
.slots
[slot
].ntok
= 0;
9537 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
9538 assert (bytes
== 2 || bytes
== 3);
9539 build_nop (&cur_vinsn
.slots
[0], bytes
);
9540 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
9542 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
9543 xtensa_insnbuf_to_chars
9544 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
9549 /* Here is the fun stuff: Get the immediate field from this
9550 instruction. If it fits, we're done. If not, find the next
9551 instruction sequence that fits. */
9555 symbolS
*lit_sym
= NULL
;
9557 int target_offset
= 0;
9560 symbolS
*gen_label
= NULL
;
9561 offsetT frag_offset
;
9562 bfd_boolean first
= TRUE
;
9563 bfd_boolean last_is_jump
;
9565 /* It does not fit. Find something that does and
9566 convert immediately. */
9567 frag_offset
= fr_opcode
- fragP
->fr_literal
;
9568 istack_init (&istack
);
9569 xg_assembly_relax (&istack
, &orig_tinsn
,
9570 segP
, fragP
, frag_offset
, min_steps
, 0);
9572 old_size
= xtensa_format_length (isa
, fmt
);
9574 /* Assemble this right inline. */
9576 /* First, create the mapping from a label name to the REAL label. */
9578 for (i
= 0; i
< istack
.ninsn
; i
++)
9580 TInsn
*tinsn
= &istack
.insn
[i
];
9583 switch (tinsn
->insn_type
)
9586 if (lit_sym
!= NULL
)
9587 as_bad (_("multiple literals in expansion"));
9588 /* First find the appropriate space in the literal pool. */
9589 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9590 if (lit_frag
== NULL
)
9591 as_bad (_("no registered fragment for literal"));
9592 if (tinsn
->ntok
!= 1)
9593 as_bad (_("number of literal tokens != 1"));
9595 /* Set the literal symbol and add a fixup. */
9596 lit_sym
= lit_frag
->fr_symbol
;
9600 if (align_targets
&& !is_loop
)
9602 fragS
*unreach
= fragP
->fr_next
;
9603 while (!(unreach
->fr_type
== rs_machine_dependent
9604 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9605 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
9607 unreach
= unreach
->fr_next
;
9610 assert (unreach
->fr_type
== rs_machine_dependent
9611 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
9612 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
9614 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
9616 assert (gen_label
== NULL
);
9617 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
9618 fr_opcode
- fragP
->fr_literal
9619 + target_offset
, fragP
);
9623 if (first
&& from_wide_insn
)
9625 target_offset
+= xtensa_format_length (isa
, fmt
);
9627 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9628 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9631 target_offset
+= xg_get_single_size (tinsn
->opcode
);
9638 last_is_jump
= FALSE
;
9639 for (i
= 0; i
< istack
.ninsn
; i
++)
9641 TInsn
*tinsn
= &istack
.insn
[i
];
9645 bfd_reloc_code_real_type reloc_type
;
9647 switch (tinsn
->insn_type
)
9650 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
9651 /* Already checked. */
9652 assert (lit_frag
!= NULL
);
9653 assert (lit_sym
!= NULL
);
9654 assert (tinsn
->ntok
== 1);
9656 target_seg
= S_GET_SEGMENT (lit_sym
);
9657 assert (target_seg
);
9658 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
9659 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
9660 &tinsn
->tok
[0], FALSE
, reloc_type
);
9667 xg_resolve_labels (tinsn
, gen_label
);
9668 xg_resolve_literals (tinsn
, lit_sym
);
9669 if (from_wide_insn
&& first
)
9672 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9674 cur_vinsn
.slots
[slot
] = *tinsn
;
9678 cur_vinsn
.slots
[slot
].opcode
=
9679 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
9680 cur_vinsn
.slots
[slot
].ntok
= 0;
9682 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
9683 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
9684 (unsigned char *) immed_instr
, 0);
9685 fragP
->tc_frag_data
.is_insn
= TRUE
;
9686 size
= xtensa_format_length (isa
, fmt
);
9687 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
9690 (tinsn
, immed_instr
+ size
, fragP
,
9691 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
9692 size
+= xg_get_single_size (tinsn
->opcode
);
9697 size
= xg_get_single_size (tinsn
->opcode
);
9698 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
9699 immed_instr
- fragP
->fr_literal
, TRUE
);
9701 immed_instr
+= size
;
9707 diff
= total_size
- old_size
;
9711 assert (diff
<= fragP
->fr_var
);
9712 fragP
->fr_var
-= diff
;
9713 fragP
->fr_fix
+= diff
;
9716 /* Check for undefined immediates in LOOP instructions. */
9720 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
9721 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9723 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9726 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
9727 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
9729 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
9734 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
9735 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
9737 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
9739 /* Add an expansion note on the expanded instruction. */
9740 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
9741 &orig_tinsn
.tok
[0], TRUE
,
9742 BFD_RELOC_XTENSA_ASM_EXPAND
);
9747 /* Add a new fix expression into the desired segment. We have to
9748 switch to that segment to do this. */
9751 fix_new_exp_in_seg (segT new_seg
,
9758 bfd_reloc_code_real_type r_type
)
9762 subsegT subseg
= now_subseg
;
9764 assert (new_seg
!= 0);
9765 subseg_set (new_seg
, new_subseg
);
9767 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
9768 subseg_set (seg
, subseg
);
9773 /* Relax a loop instruction so that it can span loop >256 bytes.
9779 addi as, as, lo8 (label-.L1)
9780 addmi as, as, mid8 (label-.L1)
9791 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
9796 unsigned long target
;
9797 static xtensa_insnbuf insnbuf
= NULL
;
9798 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
9799 xtensa_isa isa
= xtensa_default_isa
;
9800 addressT loop_offset
;
9801 addressT addi_offset
= 9;
9802 addressT addmi_offset
= 12;
9807 insnbuf
= xtensa_insnbuf_alloc (isa
);
9809 /* Get the loop offset. */
9810 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
9812 /* Validate that there really is a LOOP at the loop_offset. Because
9813 loops are not bundleable, we can assume that the instruction will be
9815 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
9816 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
9818 assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
9819 addi_offset
+= loop_offset
;
9820 addmi_offset
+= loop_offset
;
9822 assert (tinsn
->ntok
== 2);
9823 if (tinsn
->tok
[1].X_op
== O_constant
)
9824 target
= tinsn
->tok
[1].X_add_number
;
9825 else if (tinsn
->tok
[1].X_op
== O_symbol
)
9827 /* Find the fragment. */
9828 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
9829 assert (S_GET_SEGMENT (sym
) == segP
9830 || S_GET_SEGMENT (sym
) == absolute_section
);
9831 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
9835 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
9839 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
9840 loop_length_hi
= loop_length
& ~0x0ff;
9841 loop_length_lo
= loop_length
& 0x0ff;
9842 if (loop_length_lo
>= 128)
9844 loop_length_lo
-= 256;
9845 loop_length_hi
+= 256;
9848 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
9849 32512. If the loop is larger than that, then we just fail. */
9850 if (loop_length_hi
> 32512)
9851 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9852 _("loop too long for LOOP instruction"));
9854 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
9855 assert (addi_insn
.opcode
== xtensa_addi_opcode
);
9857 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
9858 assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
9860 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
9861 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
9863 fragP
->tc_frag_data
.is_insn
= TRUE
;
9864 xtensa_insnbuf_to_chars
9865 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
9867 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
9868 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
9869 xtensa_insnbuf_to_chars
9870 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
9872 /* Walk through all of the frags from here to the loop end
9873 and mark them as no_transform to keep them from being modified
9874 by the linker. If we ever have a relocation for the
9875 addi/addmi of the difference of two symbols we can remove this. */
9878 for (next_fragP
= fragP
; next_fragP
!= NULL
;
9879 next_fragP
= next_fragP
->fr_next
)
9881 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
9882 if (next_fragP
->tc_frag_data
.is_loop_target
)
9884 if (target_count
== 2)
9890 /* A map that keeps information on a per-subsegment basis. This is
9891 maintained during initial assembly, but is invalid once the
9892 subsegments are smashed together. I.E., it cannot be used during
9895 typedef struct subseg_map_struct
9903 float total_freq
; /* fall-through + branch target frequency */
9904 float target_freq
; /* branch target frequency alone */
9906 struct subseg_map_struct
*next
;
9910 static subseg_map
*sseg_map
= NULL
;
9913 get_subseg_info (segT seg
, subsegT subseg
)
9915 subseg_map
*subseg_e
;
9917 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
9919 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
9927 add_subseg_info (segT seg
, subsegT subseg
)
9929 subseg_map
*subseg_e
= (subseg_map
*) xmalloc (sizeof (subseg_map
));
9930 memset (subseg_e
, 0, sizeof (subseg_map
));
9931 subseg_e
->seg
= seg
;
9932 subseg_e
->subseg
= subseg
;
9933 subseg_e
->flags
= 0;
9934 /* Start off considering every branch target very important. */
9935 subseg_e
->target_freq
= 1.0;
9936 subseg_e
->total_freq
= 1.0;
9937 subseg_e
->next
= sseg_map
;
9938 sseg_map
= subseg_e
;
9944 get_last_insn_flags (segT seg
, subsegT subseg
)
9946 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9948 return subseg_e
->flags
;
9954 set_last_insn_flags (segT seg
,
9959 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9961 subseg_e
= add_subseg_info (seg
, subseg
);
9963 subseg_e
->flags
|= fl
;
9965 subseg_e
->flags
&= ~fl
;
9970 get_subseg_total_freq (segT seg
, subsegT subseg
)
9972 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9974 return subseg_e
->total_freq
;
9980 get_subseg_target_freq (segT seg
, subsegT subseg
)
9982 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9984 return subseg_e
->target_freq
;
9990 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
9992 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
9994 subseg_e
= add_subseg_info (seg
, subseg
);
9995 subseg_e
->total_freq
= total_f
;
9996 subseg_e
->target_freq
= target_f
;
10000 /* Segment Lists and emit_state Stuff. */
10003 xtensa_move_seg_list_to_beginning (seg_list
*head
)
10008 segT literal_section
= head
->seg
;
10010 /* Move the literal section to the front of the section list. */
10011 assert (literal_section
);
10012 if (literal_section
!= stdoutput
->sections
)
10014 bfd_section_list_remove (stdoutput
, literal_section
);
10015 bfd_section_list_prepend (stdoutput
, literal_section
);
10022 static void mark_literal_frags (seg_list
*);
10025 xtensa_move_literals (void)
10028 frchainS
*frchain_from
, *frchain_to
;
10029 fragS
*search_frag
, *next_frag
, *last_frag
, *literal_pool
, *insert_after
;
10030 fragS
**frag_splice
;
10033 fixS
*fix
, *next_fix
, **fix_splice
;
10036 mark_literal_frags (literal_head
->next
);
10038 if (use_literal_section
)
10041 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
10043 /* Keep the literals for .init and .fini in separate sections. */
10044 if (!strcmp (segment_name (segment
->seg
), INIT_SECTION_NAME
)
10045 || !strcmp (segment_name (segment
->seg
), FINI_SECTION_NAME
))
10048 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10049 search_frag
= frchain_from
->frch_root
;
10050 literal_pool
= NULL
;
10052 frag_splice
= &(frchain_from
->frch_root
);
10054 while (!search_frag
->tc_frag_data
.literal_frag
)
10056 assert (search_frag
->fr_fix
== 0
10057 || search_frag
->fr_type
== rs_align
);
10058 search_frag
= search_frag
->fr_next
;
10061 assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
10062 == RELAX_LITERAL_POOL_BEGIN
);
10063 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
10065 /* Make sure that all the frags in this series are closed, and
10066 that there is at least one left over of zero-size. This
10067 prevents us from making a segment with an frchain without any
10069 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10070 xtensa_set_frag_assembly_state (frag_now
);
10071 last_frag
= frag_now
;
10072 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10073 xtensa_set_frag_assembly_state (frag_now
);
10075 while (search_frag
!= frag_now
)
10077 next_frag
= search_frag
->fr_next
;
10079 /* First, move the frag out of the literal section and
10080 to the appropriate place. */
10081 if (search_frag
->tc_frag_data
.literal_frag
)
10083 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
10084 assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
10085 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
10086 assert (frchain_to
);
10088 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
10089 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
10091 *frag_splice
= next_frag
;
10092 search_frag
->fr_next
= insert_after
->fr_next
;
10093 insert_after
->fr_next
= search_frag
;
10094 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
10095 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
10097 /* Now move any fixups associated with this frag to the
10099 fix
= frchain_from
->fix_root
;
10100 fix_splice
= &(frchain_from
->fix_root
);
10103 next_fix
= fix
->fx_next
;
10104 if (fix
->fx_frag
== search_frag
)
10106 *fix_splice
= next_fix
;
10107 fix
->fx_next
= frchain_to
->fix_root
;
10108 frchain_to
->fix_root
= fix
;
10109 if (frchain_to
->fix_tail
== NULL
)
10110 frchain_to
->fix_tail
= fix
;
10113 fix_splice
= &(fix
->fx_next
);
10116 search_frag
= next_frag
;
10119 if (frchain_from
->fix_root
!= NULL
)
10121 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10122 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
10124 assert (frchain_from
->fix_root
== NULL
);
10126 frchain_from
->fix_tail
= NULL
;
10127 xtensa_restore_emit_state (&state
);
10130 /* Now fix up the SEGMENT value for all the literal symbols. */
10131 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
10133 symbolS
*lit_sym
= lit
->sym
;
10134 segT dest_seg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
10136 S_SET_SEGMENT (lit_sym
, dest_seg
);
10141 /* Walk over all the frags for segments in a list and mark them as
10142 containing literals. As clunky as this is, we can't rely on frag_var
10143 and frag_variant to get called in all situations. */
10146 mark_literal_frags (seg_list
*segment
)
10148 frchainS
*frchain_from
;
10149 fragS
*search_frag
;
10153 frchain_from
= seg_info (segment
->seg
)->frchainP
;
10154 search_frag
= frchain_from
->frch_root
;
10155 while (search_frag
)
10157 search_frag
->tc_frag_data
.is_literal
= TRUE
;
10158 search_frag
= search_frag
->fr_next
;
10160 segment
= segment
->next
;
10166 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
10168 /* Move all of the sections in the section list to come
10169 after "after" in the gnu segment list. */
10174 segT literal_section
= head
->seg
;
10176 /* Move the literal section after "after". */
10177 assert (literal_section
);
10178 if (literal_section
!= after
)
10180 bfd_section_list_remove (stdoutput
, literal_section
);
10181 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
10189 /* Push all the literal segments to the end of the gnu list. */
10192 xtensa_reorder_segments (void)
10199 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10205 /* Now that we have the last section, push all the literal
10206 sections to the end. */
10207 xtensa_reorder_seg_list (literal_head
, last_sec
);
10209 /* Now perform the final error check. */
10210 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
10212 assert (new_count
== old_count
);
10216 /* Change the emit state (seg, subseg, and frag related stuff) to the
10217 correct location. Return a emit_state which can be passed to
10218 xtensa_restore_emit_state to return to current fragment. */
10221 xtensa_switch_to_literal_fragment (emit_state
*result
)
10223 if (directive_state
[directive_absolute_literals
])
10225 segT lit4_seg
= cache_literal_section (TRUE
);
10226 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
10229 xtensa_switch_to_non_abs_literal_fragment (result
);
10231 /* Do a 4-byte align here. */
10232 frag_align (2, 0, 0);
10233 record_alignment (now_seg
, 2);
10238 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
10240 static bfd_boolean recursive
= FALSE
;
10241 fragS
*pool_location
= get_literal_pool_location (now_seg
);
10243 bfd_boolean is_init
=
10244 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
10245 bfd_boolean is_fini
=
10246 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
10248 if (pool_location
== NULL
10249 && !use_literal_section
10251 && !is_init
&& ! is_fini
)
10253 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
10255 /* When we mark a literal pool location, we want to put a frag in
10256 the literal pool that points to it. But to do that, we want to
10257 switch_to_literal_fragment. But literal sections don't have
10258 literal pools, so their location is always null, so we would
10259 recurse forever. This is kind of hacky, but it works. */
10262 xtensa_mark_literal_pool_location ();
10266 lit_seg
= cache_literal_section (FALSE
);
10267 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
10269 if (!use_literal_section
10270 && !is_init
&& !is_fini
10271 && get_literal_pool_location (now_seg
) != pool_location
)
10273 /* Close whatever frag is there. */
10274 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10275 xtensa_set_frag_assembly_state (frag_now
);
10276 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
10277 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
10278 xtensa_set_frag_assembly_state (frag_now
);
10283 /* Call this function before emitting data into the literal section.
10284 This is a helper function for xtensa_switch_to_literal_fragment.
10285 This is similar to a .section new_now_seg subseg. */
10288 xtensa_switch_section_emit_state (emit_state
*state
,
10290 subsegT new_now_subseg
)
10292 state
->name
= now_seg
->name
;
10293 state
->now_seg
= now_seg
;
10294 state
->now_subseg
= now_subseg
;
10295 state
->generating_literals
= generating_literals
;
10296 generating_literals
++;
10297 subseg_set (new_now_seg
, new_now_subseg
);
10301 /* Use to restore the emitting into the normal place. */
10304 xtensa_restore_emit_state (emit_state
*state
)
10306 generating_literals
= state
->generating_literals
;
10307 subseg_set (state
->now_seg
, state
->now_subseg
);
10311 /* Predicate function used to look up a section in a particular group. */
10314 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
10316 const char *gname
= inf
;
10317 const char *group_name
= elf_group_name (sec
);
10319 return (group_name
== gname
10320 || (group_name
!= NULL
10322 && strcmp (group_name
, gname
) == 0));
10326 /* Get the literal section to be used for the current text section.
10327 The result may be cached in the default_lit_sections structure. */
10330 cache_literal_section (bfd_boolean use_abs_literals
)
10332 const char *text_name
, *group_name
= 0;
10333 char *base_name
, *name
, *suffix
;
10335 segT seg
, current_section
;
10336 int current_subsec
;
10337 bfd_boolean linkonce
= FALSE
;
10339 /* Save the current section/subsection. */
10340 current_section
= now_seg
;
10341 current_subsec
= now_subseg
;
10343 /* Clear the cached values if they are no longer valid. */
10344 if (now_seg
!= default_lit_sections
.current_text_seg
)
10346 default_lit_sections
.current_text_seg
= now_seg
;
10347 default_lit_sections
.lit_seg
= NULL
;
10348 default_lit_sections
.lit4_seg
= NULL
;
10351 /* Check if the literal section is already cached. */
10352 if (use_abs_literals
)
10353 pcached
= &default_lit_sections
.lit4_seg
;
10355 pcached
= &default_lit_sections
.lit_seg
;
10360 text_name
= default_lit_sections
.lit_prefix
;
10361 if (! text_name
|| ! *text_name
)
10363 text_name
= segment_name (current_section
);
10364 group_name
= elf_group_name (current_section
);
10365 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
10368 base_name
= use_abs_literals
? ".lit4" : ".literal";
10371 name
= xmalloc (strlen (base_name
) + strlen (group_name
) + 2);
10372 sprintf (name
, "%s.%s", base_name
, group_name
);
10374 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
10376 suffix
= strchr (text_name
+ linkonce_len
, '.');
10378 name
= xmalloc (linkonce_len
+ strlen (base_name
) + 1
10379 + (suffix
? strlen (suffix
) : 0));
10380 strcpy (name
, ".gnu.linkonce");
10381 strcat (name
, base_name
);
10383 strcat (name
, suffix
);
10388 /* If the section name ends with ".text", then replace that suffix
10389 instead of appending an additional suffix. */
10390 size_t len
= strlen (text_name
);
10391 if (len
>= 5 && strcmp (text_name
+ len
- 5, ".text") == 0)
10394 name
= xmalloc (len
+ strlen (base_name
) + 1);
10395 strcpy (name
, text_name
);
10396 strcpy (name
+ len
, base_name
);
10399 /* Canonicalize section names to allow renaming literal sections.
10400 The group name, if any, came from the current text section and
10401 has already been canonicalized. */
10402 name
= tc_canonicalize_symbol_name (name
);
10404 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
10405 (void *) group_name
);
10410 seg
= subseg_force_new (name
, 0);
10412 if (! use_abs_literals
)
10414 /* Add the newly created literal segment to the list. */
10415 seg_list
*n
= (seg_list
*) xmalloc (sizeof (seg_list
));
10417 n
->next
= literal_head
->next
;
10418 literal_head
->next
= n
;
10421 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
10422 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
10423 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
10425 elf_group_name (seg
) = group_name
;
10427 bfd_set_section_flags (stdoutput
, seg
, flags
);
10428 bfd_set_section_alignment (stdoutput
, seg
, 2);
10432 subseg_set (current_section
, current_subsec
);
10437 /* Property Tables Stuff. */
10439 #define XTENSA_INSN_SEC_NAME ".xt.insn"
10440 #define XTENSA_LIT_SEC_NAME ".xt.lit"
10441 #define XTENSA_PROP_SEC_NAME ".xt.prop"
10443 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
10444 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
10446 static bfd_boolean
get_frag_is_literal (const fragS
*);
10447 static void xtensa_create_property_segments
10448 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
10449 static void xtensa_create_xproperty_segments
10450 (frag_flags_fn
, const char *, xt_section_type
);
10451 static bfd_boolean
exclude_section_from_property_tables (segT
);
10452 static bfd_boolean
section_has_property (segT
, frag_predicate
);
10453 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
10454 static void add_xt_block_frags
10455 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
10456 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
10457 static void xtensa_frag_flags_init (frag_flags
*);
10458 static void get_frag_property_flags (const fragS
*, frag_flags
*);
10459 static bfd_vma
frag_flags_to_number (const frag_flags
*);
10460 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
10462 /* Set up property tables after relaxation. */
10465 xtensa_post_relax_hook (void)
10467 xtensa_move_seg_list_to_beginning (literal_head
);
10469 xtensa_find_unmarked_state_frags ();
10470 xtensa_mark_frags_for_org ();
10471 xtensa_mark_difference_of_two_symbols ();
10473 xtensa_create_property_segments (get_frag_is_literal
,
10475 XTENSA_LIT_SEC_NAME
,
10477 xtensa_create_xproperty_segments (get_frag_property_flags
,
10478 XTENSA_PROP_SEC_NAME
,
10481 if (warn_unaligned_branch_targets
)
10482 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
10483 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
10487 /* This function is only meaningful after xtensa_move_literals. */
10490 get_frag_is_literal (const fragS
*fragP
)
10492 assert (fragP
!= NULL
);
10493 return fragP
->tc_frag_data
.is_literal
;
10498 xtensa_create_property_segments (frag_predicate property_function
,
10499 frag_predicate end_property_function
,
10500 const char *section_name_base
,
10501 xt_section_type sec_type
)
10505 /* Walk over all of the current segments.
10506 Walk over each fragment
10507 For each non-empty fragment,
10508 Build a property record (append where possible). */
10510 for (seclist
= &stdoutput
->sections
;
10511 seclist
&& *seclist
;
10512 seclist
= &(*seclist
)->next
)
10514 segT sec
= *seclist
;
10516 if (exclude_section_from_property_tables (sec
))
10519 if (section_has_property (sec
, property_function
))
10521 segment_info_type
*xt_seg_info
;
10522 xtensa_block_info
**xt_blocks
;
10523 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10525 prop_sec
->output_section
= prop_sec
;
10526 subseg_set (prop_sec
, 0);
10527 xt_seg_info
= seg_info (prop_sec
);
10528 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10530 /* Walk over all of the frchains here and add new sections. */
10531 add_xt_block_frags (sec
, xt_blocks
, property_function
,
10532 end_property_function
);
10536 /* Now we fill them out.... */
10538 for (seclist
= &stdoutput
->sections
;
10539 seclist
&& *seclist
;
10540 seclist
= &(*seclist
)->next
)
10542 segment_info_type
*seginfo
;
10543 xtensa_block_info
*block
;
10544 segT sec
= *seclist
;
10546 seginfo
= seg_info (sec
);
10547 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10551 xtensa_block_info
*cur_block
;
10553 bfd_size_type rec_size
;
10555 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10558 rec_size
= num_recs
* 8;
10559 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10566 subseg_set (sec
, 0);
10567 frag_data
= frag_more (rec_size
);
10569 for (i
= 0; i
< num_recs
; i
++)
10573 /* Write the fixup. */
10574 assert (cur_block
);
10575 fix
= fix_new (frag_now
, i
* 8, 4,
10576 section_symbol (cur_block
->sec
),
10578 FALSE
, BFD_RELOC_32
);
10579 fix
->fx_file
= "<internal>";
10582 /* Write the length. */
10583 md_number_to_chars (&frag_data
[4 + i
* 8],
10584 cur_block
->size
, 4);
10585 cur_block
= cur_block
->next
;
10587 frag_wane (frag_now
);
10589 frag_wane (frag_now
);
10597 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
10598 const char *section_name_base
,
10599 xt_section_type sec_type
)
10603 /* Walk over all of the current segments.
10604 Walk over each fragment.
10605 For each fragment that has instructions,
10606 build an instruction record (append where possible). */
10608 for (seclist
= &stdoutput
->sections
;
10609 seclist
&& *seclist
;
10610 seclist
= &(*seclist
)->next
)
10612 segT sec
= *seclist
;
10614 if (exclude_section_from_property_tables (sec
))
10617 if (section_has_xproperty (sec
, flag_fn
))
10619 segment_info_type
*xt_seg_info
;
10620 xtensa_block_info
**xt_blocks
;
10621 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
10623 prop_sec
->output_section
= prop_sec
;
10624 subseg_set (prop_sec
, 0);
10625 xt_seg_info
= seg_info (prop_sec
);
10626 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
10628 /* Walk over all of the frchains here and add new sections. */
10629 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
10633 /* Now we fill them out.... */
10635 for (seclist
= &stdoutput
->sections
;
10636 seclist
&& *seclist
;
10637 seclist
= &(*seclist
)->next
)
10639 segment_info_type
*seginfo
;
10640 xtensa_block_info
*block
;
10641 segT sec
= *seclist
;
10643 seginfo
= seg_info (sec
);
10644 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
10648 xtensa_block_info
*cur_block
;
10650 bfd_size_type rec_size
;
10652 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
10655 rec_size
= num_recs
* (8 + 4);
10656 bfd_set_section_size (stdoutput
, sec
, rec_size
);
10657 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
10664 subseg_set (sec
, 0);
10665 frag_data
= frag_more (rec_size
);
10667 for (i
= 0; i
< num_recs
; i
++)
10671 /* Write the fixup. */
10672 assert (cur_block
);
10673 fix
= fix_new (frag_now
, i
* 12, 4,
10674 section_symbol (cur_block
->sec
),
10676 FALSE
, BFD_RELOC_32
);
10677 fix
->fx_file
= "<internal>";
10680 /* Write the length. */
10681 md_number_to_chars (&frag_data
[4 + i
* 12],
10682 cur_block
->size
, 4);
10683 md_number_to_chars (&frag_data
[8 + i
* 12],
10684 frag_flags_to_number (&cur_block
->flags
),
10686 cur_block
= cur_block
->next
;
10688 frag_wane (frag_now
);
10690 frag_wane (frag_now
);
10698 exclude_section_from_property_tables (segT sec
)
10700 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
10702 /* Sections that don't contribute to the memory footprint are excluded. */
10703 if ((flags
& SEC_DEBUGGING
)
10704 || !(flags
& SEC_ALLOC
)
10705 || (flags
& SEC_MERGE
))
10708 /* Linker cie and fde optimizations mess up property entries for
10709 eh_frame sections, but there is nothing inside them relevant to
10710 property tables anyway. */
10711 if (strcmp (sec
->name
, ".eh_frame") == 0)
10719 section_has_property (segT sec
, frag_predicate property_function
)
10721 segment_info_type
*seginfo
= seg_info (sec
);
10724 if (seginfo
&& seginfo
->frchainP
)
10726 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10728 if (property_function (fragP
)
10729 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10738 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
10740 segment_info_type
*seginfo
= seg_info (sec
);
10743 if (seginfo
&& seginfo
->frchainP
)
10745 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
10747 frag_flags prop_flags
;
10748 property_function (fragP
, &prop_flags
);
10749 if (!xtensa_frag_flags_is_empty (&prop_flags
))
10757 /* Two types of block sections exist right now: literal and insns. */
10760 add_xt_block_frags (segT sec
,
10761 xtensa_block_info
**xt_block
,
10762 frag_predicate property_function
,
10763 frag_predicate end_property_function
)
10765 bfd_vma seg_offset
;
10768 /* Build it if needed. */
10769 while (*xt_block
!= NULL
)
10770 xt_block
= &(*xt_block
)->next
;
10771 /* We are either at NULL at the beginning or at the end. */
10773 /* Walk through the frags. */
10776 if (seg_info (sec
)->frchainP
)
10778 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
10780 fragP
= fragP
->fr_next
)
10782 if (property_function (fragP
)
10783 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
10785 if (*xt_block
!= NULL
)
10787 if ((*xt_block
)->offset
+ (*xt_block
)->size
10788 == fragP
->fr_address
)
10789 (*xt_block
)->size
+= fragP
->fr_fix
;
10791 xt_block
= &((*xt_block
)->next
);
10793 if (*xt_block
== NULL
)
10795 xtensa_block_info
*new_block
= (xtensa_block_info
*)
10796 xmalloc (sizeof (xtensa_block_info
));
10797 new_block
->sec
= sec
;
10798 new_block
->offset
= fragP
->fr_address
;
10799 new_block
->size
= fragP
->fr_fix
;
10800 new_block
->next
= NULL
;
10801 xtensa_frag_flags_init (&new_block
->flags
);
10802 *xt_block
= new_block
;
10804 if (end_property_function
10805 && end_property_function (fragP
))
10807 xt_block
= &((*xt_block
)->next
);
10815 /* Break the encapsulation of add_xt_prop_frags here. */
10818 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
10820 if (prop_flags
->is_literal
10821 || prop_flags
->is_insn
10822 || prop_flags
->is_data
10823 || prop_flags
->is_unreachable
)
10830 xtensa_frag_flags_init (frag_flags
*prop_flags
)
10832 memset (prop_flags
, 0, sizeof (frag_flags
));
10837 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
10839 xtensa_frag_flags_init (prop_flags
);
10840 if (fragP
->tc_frag_data
.is_literal
)
10841 prop_flags
->is_literal
= TRUE
;
10842 if (fragP
->tc_frag_data
.is_specific_opcode
10843 || fragP
->tc_frag_data
.is_no_transform
)
10845 prop_flags
->is_no_transform
= TRUE
;
10846 if (xtensa_frag_flags_is_empty (prop_flags
))
10847 prop_flags
->is_data
= TRUE
;
10849 if (fragP
->tc_frag_data
.is_unreachable
)
10850 prop_flags
->is_unreachable
= TRUE
;
10851 else if (fragP
->tc_frag_data
.is_insn
)
10853 prop_flags
->is_insn
= TRUE
;
10854 if (fragP
->tc_frag_data
.is_loop_target
)
10855 prop_flags
->insn
.is_loop_target
= TRUE
;
10856 if (fragP
->tc_frag_data
.is_branch_target
)
10857 prop_flags
->insn
.is_branch_target
= TRUE
;
10858 if (fragP
->tc_frag_data
.is_no_density
)
10859 prop_flags
->insn
.is_no_density
= TRUE
;
10860 if (fragP
->tc_frag_data
.use_absolute_literals
)
10861 prop_flags
->insn
.is_abslit
= TRUE
;
10863 if (fragP
->tc_frag_data
.is_align
)
10865 prop_flags
->is_align
= TRUE
;
10866 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
10867 if (xtensa_frag_flags_is_empty (prop_flags
))
10868 prop_flags
->is_data
= TRUE
;
10874 frag_flags_to_number (const frag_flags
*prop_flags
)
10877 if (prop_flags
->is_literal
)
10878 num
|= XTENSA_PROP_LITERAL
;
10879 if (prop_flags
->is_insn
)
10880 num
|= XTENSA_PROP_INSN
;
10881 if (prop_flags
->is_data
)
10882 num
|= XTENSA_PROP_DATA
;
10883 if (prop_flags
->is_unreachable
)
10884 num
|= XTENSA_PROP_UNREACHABLE
;
10885 if (prop_flags
->insn
.is_loop_target
)
10886 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
10887 if (prop_flags
->insn
.is_branch_target
)
10889 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
10890 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
10893 if (prop_flags
->insn
.is_no_density
)
10894 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
10895 if (prop_flags
->is_no_transform
)
10896 num
|= XTENSA_PROP_NO_TRANSFORM
;
10897 if (prop_flags
->insn
.is_no_reorder
)
10898 num
|= XTENSA_PROP_INSN_NO_REORDER
;
10899 if (prop_flags
->insn
.is_abslit
)
10900 num
|= XTENSA_PROP_INSN_ABSLIT
;
10902 if (prop_flags
->is_align
)
10904 num
|= XTENSA_PROP_ALIGN
;
10905 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
10913 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
10914 const frag_flags
*prop_flags_2
)
10916 /* Cannot combine with an end marker. */
10918 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
10920 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
10922 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
10925 if (prop_flags_1
->is_insn
)
10927 /* Properties of the beginning of the frag. */
10928 if (prop_flags_2
->insn
.is_loop_target
)
10930 if (prop_flags_2
->insn
.is_branch_target
)
10932 if (prop_flags_1
->insn
.is_no_density
!=
10933 prop_flags_2
->insn
.is_no_density
)
10935 if (prop_flags_1
->is_no_transform
!=
10936 prop_flags_2
->is_no_transform
)
10938 if (prop_flags_1
->insn
.is_no_reorder
!=
10939 prop_flags_2
->insn
.is_no_reorder
)
10941 if (prop_flags_1
->insn
.is_abslit
!=
10942 prop_flags_2
->insn
.is_abslit
)
10946 if (prop_flags_1
->is_align
)
10954 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
10957 unsigned align_bits
;
10959 if (!xt_block
->flags
.is_align
)
10960 return xt_block
->size
;
10962 end_addr
= xt_block
->offset
+ xt_block
->size
;
10963 align_bits
= xt_block
->flags
.alignment
;
10964 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
10965 return end_addr
- xt_block
->offset
;
10970 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
10971 const xtensa_block_info
*xt_block_2
)
10973 if (xt_block
->sec
!= xt_block_2
->sec
)
10975 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
10976 != xt_block_2
->offset
)
10979 if (xt_block_2
->size
== 0
10980 && (!xt_block_2
->flags
.is_unreachable
10981 || xt_block
->flags
.is_unreachable
))
10983 if (xt_block_2
->flags
.is_align
10984 && xt_block
->flags
.is_align
)
10986 /* Nothing needed. */
10987 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
10992 if (xt_block_2
->flags
.is_align
)
10994 /* Push alignment to previous entry. */
10995 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
10996 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11001 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
11002 &xt_block_2
->flags
))
11005 xt_block
->size
+= xt_block_2
->size
;
11007 if (xt_block_2
->flags
.is_align
)
11009 xt_block
->flags
.is_align
= TRUE
;
11010 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
11018 add_xt_prop_frags (segT sec
,
11019 xtensa_block_info
**xt_block
,
11020 frag_flags_fn property_function
)
11022 bfd_vma seg_offset
;
11025 /* Build it if needed. */
11026 while (*xt_block
!= NULL
)
11028 xt_block
= &(*xt_block
)->next
;
11030 /* We are either at NULL at the beginning or at the end. */
11032 /* Walk through the frags. */
11035 if (seg_info (sec
)->frchainP
)
11037 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
11038 fragP
= fragP
->fr_next
)
11040 xtensa_block_info tmp_block
;
11041 tmp_block
.sec
= sec
;
11042 tmp_block
.offset
= fragP
->fr_address
;
11043 tmp_block
.size
= fragP
->fr_fix
;
11044 tmp_block
.next
= NULL
;
11045 property_function (fragP
, &tmp_block
.flags
);
11047 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
11048 /* && fragP->fr_fix != 0) */
11050 if ((*xt_block
) == NULL
11051 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
11053 xtensa_block_info
*new_block
;
11054 if ((*xt_block
) != NULL
)
11055 xt_block
= &(*xt_block
)->next
;
11056 new_block
= (xtensa_block_info
*)
11057 xmalloc (sizeof (xtensa_block_info
));
11058 *new_block
= tmp_block
;
11059 *xt_block
= new_block
;
11067 /* op_placement_info_table */
11069 /* op_placement_info makes it easier to determine which
11070 ops can go in which slots. */
11073 init_op_placement_info_table (void)
11075 xtensa_isa isa
= xtensa_default_isa
;
11076 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
11077 xtensa_opcode opcode
;
11080 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
11082 op_placement_table
= (op_placement_info_table
)
11083 xmalloc (sizeof (op_placement_info
) * num_opcodes
);
11084 assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
11086 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
11088 op_placement_info
*opi
= &op_placement_table
[opcode
];
11089 /* FIXME: Make tinsn allocation dynamic. */
11090 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
11091 as_fatal (_("too many operands in instruction"));
11092 opi
->narrowest
= XTENSA_UNDEFINED
;
11093 opi
->narrowest_size
= 0x7F;
11094 opi
->narrowest_slot
= 0;
11096 opi
->num_formats
= 0;
11098 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
11100 opi
->slots
[fmt
] = 0;
11101 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
11103 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
11105 int fmt_length
= xtensa_format_length (isa
, fmt
);
11107 set_bit (fmt
, opi
->formats
);
11108 set_bit (slot
, opi
->slots
[fmt
]);
11109 if (fmt_length
< opi
->narrowest_size
11110 || (fmt_length
== opi
->narrowest_size
11111 && (xtensa_format_num_slots (isa
, fmt
)
11112 < xtensa_format_num_slots (isa
,
11115 opi
->narrowest
= fmt
;
11116 opi
->narrowest_size
= fmt_length
;
11117 opi
->narrowest_slot
= slot
;
11122 opi
->num_formats
++;
11125 xtensa_insnbuf_free (isa
, ibuf
);
11130 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
11132 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
11136 /* If the opcode is available in a single slot format, return its size. */
11139 xg_get_single_size (xtensa_opcode opcode
)
11141 return op_placement_table
[opcode
].narrowest_size
;
11145 static xtensa_format
11146 xg_get_single_format (xtensa_opcode opcode
)
11148 return op_placement_table
[opcode
].narrowest
;
11153 xg_get_single_slot (xtensa_opcode opcode
)
11155 return op_placement_table
[opcode
].narrowest_slot
;
11159 /* Instruction Stack Functions (from "xtensa-istack.h"). */
11162 istack_init (IStack
*stack
)
11164 memset (stack
, 0, sizeof (IStack
));
11170 istack_empty (IStack
*stack
)
11172 return (stack
->ninsn
== 0);
11177 istack_full (IStack
*stack
)
11179 return (stack
->ninsn
== MAX_ISTACK
);
11183 /* Return a pointer to the top IStack entry.
11184 It is an error to call this if istack_empty () is TRUE. */
11187 istack_top (IStack
*stack
)
11189 int rec
= stack
->ninsn
- 1;
11190 assert (!istack_empty (stack
));
11191 return &stack
->insn
[rec
];
11195 /* Add a new TInsn to an IStack.
11196 It is an error to call this if istack_full () is TRUE. */
11199 istack_push (IStack
*stack
, TInsn
*insn
)
11201 int rec
= stack
->ninsn
;
11202 assert (!istack_full (stack
));
11203 stack
->insn
[rec
] = *insn
;
11208 /* Clear space for the next TInsn on the IStack and return a pointer
11209 to it. It is an error to call this if istack_full () is TRUE. */
11212 istack_push_space (IStack
*stack
)
11214 int rec
= stack
->ninsn
;
11216 assert (!istack_full (stack
));
11217 insn
= &stack
->insn
[rec
];
11224 /* Remove the last pushed instruction. It is an error to call this if
11225 istack_empty () returns TRUE. */
11228 istack_pop (IStack
*stack
)
11230 int rec
= stack
->ninsn
- 1;
11231 assert (!istack_empty (stack
));
11233 tinsn_init (&stack
->insn
[rec
]);
11237 /* TInsn functions. */
11240 tinsn_init (TInsn
*dst
)
11242 memset (dst
, 0, sizeof (TInsn
));
11246 /* Return TRUE if ANY of the operands in the insn are symbolic. */
11249 tinsn_has_symbolic_operands (const TInsn
*insn
)
11252 int n
= insn
->ntok
;
11254 assert (insn
->insn_type
== ITYPE_INSN
);
11256 for (i
= 0; i
< n
; ++i
)
11258 switch (insn
->tok
[i
].X_op
)
11272 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
11274 xtensa_isa isa
= xtensa_default_isa
;
11276 int n
= insn
->ntok
;
11278 assert (insn
->insn_type
== ITYPE_INSN
);
11280 for (i
= 0; i
< n
; ++i
)
11282 switch (insn
->tok
[i
].X_op
)
11290 /* Errors for these types are caught later. */
11295 /* Symbolic immediates are only allowed on the last immediate
11296 operand. At this time, CONST16 is the only opcode where we
11297 support non-PC-relative relocations. */
11298 if (i
!= get_relaxable_immed (insn
->opcode
)
11299 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
11300 && insn
->opcode
!= xtensa_const16_opcode
))
11302 as_bad (_("invalid symbolic operand"));
11311 /* For assembly code with complex expressions (e.g. subtraction),
11312 we have to build them in the literal pool so that
11313 their results are calculated correctly after relaxation.
11314 The relaxation only handles expressions that
11315 boil down to SYMBOL + OFFSET. */
11318 tinsn_has_complex_operands (const TInsn
*insn
)
11321 int n
= insn
->ntok
;
11322 assert (insn
->insn_type
== ITYPE_INSN
);
11323 for (i
= 0; i
< n
; ++i
)
11325 switch (insn
->tok
[i
].X_op
)
11341 /* Encode a TInsn opcode and its constant operands into slotbuf.
11342 Return TRUE if there is a symbol in the immediate field. This
11343 function assumes that:
11344 1) The number of operands are correct.
11345 2) The insn_type is ITYPE_INSN.
11346 3) The opcode can be encoded in the specified format and slot.
11347 4) Operands are either O_constant or O_symbol, and all constants fit. */
11350 tinsn_to_slotbuf (xtensa_format fmt
,
11353 xtensa_insnbuf slotbuf
)
11355 xtensa_isa isa
= xtensa_default_isa
;
11356 xtensa_opcode opcode
= tinsn
->opcode
;
11357 bfd_boolean has_fixup
= FALSE
;
11358 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11361 assert (tinsn
->insn_type
== ITYPE_INSN
);
11362 if (noperands
!= tinsn
->ntok
)
11363 as_fatal (_("operand number mismatch"));
11365 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
11367 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
11368 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
11372 for (i
= 0; i
< noperands
; i
++)
11374 expressionS
*expr
= &tinsn
->tok
[i
];
11380 switch (expr
->X_op
)
11383 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11385 /* The register number has already been checked in
11386 expression_maybe_register, so we don't need to check here. */
11387 opnd_value
= expr
->X_add_number
;
11388 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
11389 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
11392 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
11396 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
11398 as_where (&file_name
, &line
);
11399 /* It is a constant and we called this function
11400 then we have to try to fit it. */
11401 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
11402 expr
->X_add_number
, file_name
, line
);
11415 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
11416 into a multi-slot instruction, fill the other slots with NOPs.
11417 Return TRUE if there is a symbol in the immediate field. See also the
11418 assumptions listed for tinsn_to_slotbuf. */
11421 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
11423 static xtensa_insnbuf slotbuf
= 0;
11424 static vliw_insn vinsn
;
11425 xtensa_isa isa
= xtensa_default_isa
;
11426 bfd_boolean has_fixup
= FALSE
;
11431 slotbuf
= xtensa_insnbuf_alloc (isa
);
11432 xg_init_vinsn (&vinsn
);
11435 xg_clear_vinsn (&vinsn
);
11437 bundle_tinsn (tinsn
, &vinsn
);
11439 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
11441 for (i
= 0; i
< vinsn
.num_slots
; i
++)
11443 /* Only one slot may have a fix-up because the rest contains NOPs. */
11445 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
11446 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
11453 /* Check the instruction arguments. Return TRUE on failure. */
11456 tinsn_check_arguments (const TInsn
*insn
)
11458 xtensa_isa isa
= xtensa_default_isa
;
11459 xtensa_opcode opcode
= insn
->opcode
;
11461 if (opcode
== XTENSA_UNDEFINED
)
11463 as_bad (_("invalid opcode"));
11467 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
11469 as_bad (_("too few operands"));
11473 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
11475 as_bad (_("too many operands"));
11482 /* Load an instruction from its encoded form. */
11485 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
11489 xg_init_vinsn (&vinsn
);
11490 vinsn_from_chars (&vinsn
, f
);
11492 *tinsn
= vinsn
.slots
[slot
];
11493 xg_free_vinsn (&vinsn
);
11498 tinsn_from_insnbuf (TInsn
*tinsn
,
11499 xtensa_insnbuf slotbuf
,
11504 xtensa_isa isa
= xtensa_default_isa
;
11506 /* Find the immed. */
11507 tinsn_init (tinsn
);
11508 tinsn
->insn_type
= ITYPE_INSN
;
11509 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
11510 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
11511 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
11512 for (i
= 0; i
< tinsn
->ntok
; i
++)
11514 set_expr_const (&tinsn
->tok
[i
],
11515 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
11516 tinsn
->opcode
, i
));
11521 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
11524 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
11526 xtensa_opcode opcode
= tinsn
->opcode
;
11529 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
11531 opnum
= get_relaxable_immed (opcode
);
11532 assert (opnum
>= 0);
11533 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
11534 fragP
->tc_frag_data
.slot_symbols
[slot
],
11535 fragP
->tc_frag_data
.slot_offsets
[slot
]);
11537 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
11542 get_num_stack_text_bytes (IStack
*istack
)
11545 int text_bytes
= 0;
11547 for (i
= 0; i
< istack
->ninsn
; i
++)
11549 TInsn
*tinsn
= &istack
->insn
[i
];
11550 if (tinsn
->insn_type
== ITYPE_INSN
)
11551 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
11558 get_num_stack_literal_bytes (IStack
*istack
)
11563 for (i
= 0; i
< istack
->ninsn
; i
++)
11565 TInsn
*tinsn
= &istack
->insn
[i
];
11566 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
11573 /* vliw_insn functions. */
11576 xg_init_vinsn (vliw_insn
*v
)
11579 xtensa_isa isa
= xtensa_default_isa
;
11581 xg_clear_vinsn (v
);
11583 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
11584 if (v
->insnbuf
== NULL
)
11585 as_fatal (_("out of memory"));
11587 for (i
= 0; i
< MAX_SLOTS
; i
++)
11589 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
11590 if (v
->slotbuf
[i
] == NULL
)
11591 as_fatal (_("out of memory"));
11597 xg_clear_vinsn (vliw_insn
*v
)
11601 memset (v
, 0, offsetof (vliw_insn
, insnbuf
));
11603 v
->format
= XTENSA_UNDEFINED
;
11605 v
->inside_bundle
= FALSE
;
11607 if (xt_saved_debug_type
!= DEBUG_NONE
)
11608 debug_type
= xt_saved_debug_type
;
11610 for (i
= 0; i
< MAX_SLOTS
; i
++)
11611 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
11616 vinsn_has_specific_opcodes (vliw_insn
*v
)
11620 for (i
= 0; i
< v
->num_slots
; i
++)
11622 if (v
->slots
[i
].is_specific_opcode
)
11630 xg_free_vinsn (vliw_insn
*v
)
11633 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
11634 for (i
= 0; i
< MAX_SLOTS
; i
++)
11635 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
11639 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
11640 operands. See also the assumptions listed for tinsn_to_slotbuf. */
11643 vinsn_to_insnbuf (vliw_insn
*vinsn
,
11646 bfd_boolean record_fixup
)
11648 xtensa_isa isa
= xtensa_default_isa
;
11649 xtensa_format fmt
= vinsn
->format
;
11650 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
11652 bfd_boolean has_fixup
= FALSE
;
11654 xtensa_format_encode (isa
, fmt
, insnbuf
);
11656 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
11658 TInsn
*tinsn
= &vinsn
->slots
[slot
];
11659 expressionS
*extra_arg
= &tinsn
->extra_arg
;
11660 bfd_boolean tinsn_has_fixup
=
11661 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
11662 vinsn
->slotbuf
[slot
]);
11664 xtensa_format_set_slot (isa
, fmt
, slot
,
11665 insnbuf
, vinsn
->slotbuf
[slot
]);
11666 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
11668 if (vinsn
->num_slots
!= 1)
11669 as_bad (_("TLS relocation not allowed in FLIX bundle"));
11670 else if (record_fixup
)
11671 /* Instructions that generate TLS relocations should always be
11672 relaxed in the front-end. If "record_fixup" is set, then this
11673 function is being called during back-end relaxation, so flag
11674 the unexpected behavior as an error. */
11675 as_bad (_("unexpected TLS relocation"));
11677 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
11678 xtensa_format_length (isa
, fmt
),
11679 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
11680 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
11682 if (tinsn_has_fixup
)
11685 xtensa_opcode opcode
= tinsn
->opcode
;
11686 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
11689 for (i
= 0; i
< noperands
; i
++)
11691 expressionS
* expr
= &tinsn
->tok
[i
];
11692 switch (expr
->X_op
)
11697 if (get_relaxable_immed (opcode
) == i
)
11699 /* Add a fix record for the instruction, except if this
11700 function is being called prior to relaxation, i.e.,
11701 if record_fixup is false, and the instruction might
11702 be relaxed later. */
11704 || tinsn
->is_specific_opcode
11705 || !xg_is_relaxable_insn (tinsn
, 0))
11707 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, expr
, fragP
,
11708 frag_offset
- fragP
->fr_literal
);
11712 if (expr
->X_op
!= O_symbol
)
11713 as_bad (_("invalid operand"));
11714 tinsn
->symbol
= expr
->X_add_symbol
;
11715 tinsn
->offset
= expr
->X_add_number
;
11719 as_bad (_("symbolic operand not allowed"));
11727 as_bad (_("expression too complex"));
11739 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
11741 static xtensa_insnbuf insnbuf
= NULL
;
11742 static xtensa_insnbuf slotbuf
= NULL
;
11745 xtensa_isa isa
= xtensa_default_isa
;
11749 insnbuf
= xtensa_insnbuf_alloc (isa
);
11750 slotbuf
= xtensa_insnbuf_alloc (isa
);
11753 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
11754 fmt
= xtensa_format_decode (isa
, insnbuf
);
11755 if (fmt
== XTENSA_UNDEFINED
)
11756 as_fatal (_("cannot decode instruction format"));
11757 vinsn
->format
= fmt
;
11758 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
11760 for (i
= 0; i
< vinsn
->num_slots
; i
++)
11762 TInsn
*tinsn
= &vinsn
->slots
[i
];
11763 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
11764 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
11769 /* Expression utilities. */
11771 /* Return TRUE if the expression is an integer constant. */
11774 expr_is_const (const expressionS
*s
)
11776 return (s
->X_op
== O_constant
);
11780 /* Get the expression constant.
11781 Calling this is illegal if expr_is_const () returns TRUE. */
11784 get_expr_const (const expressionS
*s
)
11786 assert (expr_is_const (s
));
11787 return s
->X_add_number
;
11791 /* Set the expression to a constant value. */
11794 set_expr_const (expressionS
*s
, offsetT val
)
11796 s
->X_op
= O_constant
;
11797 s
->X_add_number
= val
;
11798 s
->X_add_symbol
= NULL
;
11799 s
->X_op_symbol
= NULL
;
11804 expr_is_register (const expressionS
*s
)
11806 return (s
->X_op
== O_register
);
11810 /* Get the expression constant.
11811 Calling this is illegal if expr_is_const () returns TRUE. */
11814 get_expr_register (const expressionS
*s
)
11816 assert (expr_is_register (s
));
11817 return s
->X_add_number
;
11821 /* Set the expression to a symbol + constant offset. */
11824 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
11826 s
->X_op
= O_symbol
;
11827 s
->X_add_symbol
= sym
;
11828 s
->X_op_symbol
= NULL
; /* unused */
11829 s
->X_add_number
= offset
;
11833 /* Return TRUE if the two expressions are equal. */
11836 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
11838 if (s1
->X_op
!= s2
->X_op
)
11840 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
11842 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
11844 if (s1
->X_add_number
!= s2
->X_add_number
)
11851 copy_expr (expressionS
*dst
, const expressionS
*src
)
11853 memcpy (dst
, src
, sizeof (expressionS
));
11857 /* Support for the "--rename-section" option. */
11859 struct rename_section_struct
11863 struct rename_section_struct
*next
;
11866 static struct rename_section_struct
*section_rename
;
11869 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
11870 entries to the section_rename list. Note: Specifying multiple
11871 renamings separated by colons is not documented and is retained only
11872 for backward compatibility. */
11875 build_section_rename (const char *arg
)
11877 struct rename_section_struct
*r
;
11878 char *this_arg
= NULL
;
11879 char *next_arg
= NULL
;
11881 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
11883 char *old_name
, *new_name
;
11887 next_arg
= strchr (this_arg
, ':');
11895 old_name
= this_arg
;
11896 new_name
= strchr (this_arg
, '=');
11898 if (*old_name
== '\0')
11900 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
11903 if (!new_name
|| new_name
[1] == '\0')
11905 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
11912 /* Check for invalid section renaming. */
11913 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11915 if (strcmp (r
->old_name
, old_name
) == 0)
11916 as_bad (_("section %s renamed multiple times"), old_name
);
11917 if (strcmp (r
->new_name
, new_name
) == 0)
11918 as_bad (_("multiple sections remapped to output section %s"),
11923 r
= (struct rename_section_struct
*)
11924 xmalloc (sizeof (struct rename_section_struct
));
11925 r
->old_name
= xstrdup (old_name
);
11926 r
->new_name
= xstrdup (new_name
);
11927 r
->next
= section_rename
;
11928 section_rename
= r
;
11934 xtensa_section_rename (char *name
)
11936 struct rename_section_struct
*r
= section_rename
;
11938 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
11940 if (strcmp (r
->old_name
, name
) == 0)
11941 return r
->new_name
;