1 /* tc-xtensa.c -- Assemble Xtensa instructions.
2 Copyright (C) 2003-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 #include "safe-ctype.h"
25 #include "tc-xtensa.h"
27 #include "xtensa-relax.h"
28 #include "dwarf2dbg.h"
29 #include "xtensa-istack.h"
30 #include "struc-symbol.h"
31 #include "xtensa-config.h"
33 /* Provide default values for new configuration settings. */
39 #define uint32 unsigned int
42 #define int32 signed int
47 Naming conventions (used somewhat inconsistently):
48 The xtensa_ functions are exported
49 The xg_ functions are internal
51 We also have a couple of different extensibility mechanisms.
52 1) The idiom replacement:
53 This is used when a line is first parsed to
54 replace an instruction pattern with another instruction
55 It is currently limited to replacements of instructions
56 with constant operands.
57 2) The xtensa-relax.c mechanism that has stronger instruction
58 replacement patterns. When an instruction's immediate field
59 does not fit the next instruction sequence is attempted.
60 In addition, "narrow" opcodes are supported this way. */
63 /* Define characters with special meanings to GAS. */
64 const char comment_chars
[] = "#";
65 const char line_comment_chars
[] = "#";
66 const char line_separator_chars
[] = ";";
67 const char EXP_CHARS
[] = "eE";
68 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
71 /* Flags to indicate whether the hardware supports the density and
72 absolute literals options. */
74 bfd_boolean density_supported
= XCHAL_HAVE_DENSITY
;
75 bfd_boolean absolute_literals_supported
= XSHAL_USE_ABSOLUTE_LITERALS
;
77 static vliw_insn cur_vinsn
;
79 unsigned xtensa_num_pipe_stages
;
80 unsigned xtensa_fetch_width
= XCHAL_INST_FETCH_WIDTH
;
82 static enum debug_info_type xt_saved_debug_type
= DEBUG_NONE
;
84 /* Some functions are only valid in the front end. This variable
85 allows us to assert that we haven't crossed over into the
87 static bfd_boolean past_xtensa_end
= FALSE
;
89 /* Flags for properties of the last instruction in a segment. */
90 #define FLAG_IS_A0_WRITER 0x1
91 #define FLAG_IS_BAD_LOOPEND 0x2
94 /* We define a special segment names ".literal" to place literals
95 into. The .fini and .init sections are special because they
96 contain code that is moved together by the linker. We give them
97 their own special .fini.literal and .init.literal sections. */
99 #define LITERAL_SECTION_NAME xtensa_section_rename (".literal")
100 #define LIT4_SECTION_NAME xtensa_section_rename (".lit4")
101 #define INIT_SECTION_NAME xtensa_section_rename (".init")
102 #define FINI_SECTION_NAME xtensa_section_rename (".fini")
105 /* This type is used for the directive_stack to keep track of the
106 state of the literal collection pools. If lit_prefix is set, it is
107 used to determine the literal section names; otherwise, the literal
108 sections are determined based on the current text section. The
109 lit_seg and lit4_seg fields cache these literal sections, with the
110 current_text_seg field used a tag to indicate whether the cached
113 typedef struct lit_state_struct
116 segT current_text_seg
;
121 static lit_state default_lit_sections
;
124 /* We keep a list of literal segments. The seg_list type is the node
125 for this list. The literal_head pointer is the head of the list,
126 with the literal_head_h dummy node at the start. */
128 typedef struct seg_list_struct
130 struct seg_list_struct
*next
;
134 static seg_list literal_head_h
;
135 static seg_list
*literal_head
= &literal_head_h
;
138 /* Lists of symbols. We keep a list of symbols that label the current
139 instruction, so that we can adjust the symbols when inserting alignment
140 for various instructions. We also keep a list of all the symbols on
141 literals, so that we can fix up those symbols when the literals are
142 later moved into the text sections. */
144 typedef struct sym_list_struct
146 struct sym_list_struct
*next
;
150 static sym_list
*insn_labels
= NULL
;
151 static sym_list
*free_insn_labels
= NULL
;
152 static sym_list
*saved_insn_labels
= NULL
;
154 static sym_list
*literal_syms
;
157 /* Flags to determine whether to prefer const16 or l32r
158 if both options are available. */
159 int prefer_const16
= 0;
162 /* Global flag to indicate when we are emitting literals. */
163 int generating_literals
= 0;
165 /* The following PROPERTY table definitions are copied from
166 <elf/xtensa.h> and must be kept in sync with the code there. */
168 /* Flags in the property tables to specify whether blocks of memory
169 are literals, instructions, data, or unreachable. For
170 instructions, blocks that begin loop targets and branch targets are
171 designated. Blocks that do not allow density, instruction
172 reordering or transformation are also specified. Finally, for
173 branch targets, branch target alignment priority is included.
174 Alignment of the next block is specified in the current block
175 and the size of the current block does not include any fill required
176 to align to the next block. */
178 #define XTENSA_PROP_LITERAL 0x00000001
179 #define XTENSA_PROP_INSN 0x00000002
180 #define XTENSA_PROP_DATA 0x00000004
181 #define XTENSA_PROP_UNREACHABLE 0x00000008
182 /* Instruction only properties at beginning of code. */
183 #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010
184 #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020
185 /* Instruction only properties about code. */
186 #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040
187 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080
188 /* Historically, NO_TRANSFORM was a property of instructions,
189 but it should apply to literals under certain circumstances. */
190 #define XTENSA_PROP_NO_TRANSFORM 0x00000100
192 /* Branch target alignment information. This transmits information
193 to the linker optimization about the priority of aligning a
194 particular block for branch target alignment: None, low priority,
195 high priority, or required. These only need to be checked in
196 instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
199 switch (GET_XTENSA_PROP_BT_ALIGN (flags))
200 case XTENSA_PROP_BT_ALIGN_NONE:
201 case XTENSA_PROP_BT_ALIGN_LOW:
202 case XTENSA_PROP_BT_ALIGN_HIGH:
203 case XTENSA_PROP_BT_ALIGN_REQUIRE:
205 #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600
207 /* No branch target alignment. */
208 #define XTENSA_PROP_BT_ALIGN_NONE 0x0
209 /* Low priority branch target alignment. */
210 #define XTENSA_PROP_BT_ALIGN_LOW 0x1
211 /* High priority branch target alignment. */
212 #define XTENSA_PROP_BT_ALIGN_HIGH 0x2
213 /* Required branch target alignment. */
214 #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3
216 #define GET_XTENSA_PROP_BT_ALIGN(flag) \
217 (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
218 #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
219 (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
220 (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
223 /* Alignment is specified in the block BEFORE the one that needs
224 alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to
225 get the required alignment specified as a power of 2. Use
226 SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
227 alignment. Be careful of side effects since the SET will evaluate
228 flags twice. Also, note that the SIZE of a block in the property
229 table does not include the alignment size, so the alignment fill
230 must be calculated to determine if two blocks are contiguous.
231 TEXT_ALIGN is not currently implemented but is a placeholder for a
232 possible future implementation. */
234 #define XTENSA_PROP_ALIGN 0x00000800
236 #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000
238 #define GET_XTENSA_PROP_ALIGNMENT(flag) \
239 (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
240 #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
241 (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
242 (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
244 #define XTENSA_PROP_INSN_ABSLIT 0x00020000
247 /* Structure for saving instruction and alignment per-fragment data
248 that will be written to the object file. This structure is
249 equivalent to the actual data that will be written out to the file
250 but is easier to use. We provide a conversion to file flags
251 in frag_flags_to_number. */
253 typedef struct frag_flags_struct frag_flags
;
255 struct frag_flags_struct
257 /* is_literal should only be used after xtensa_move_literals.
258 If you need to check if you are generating a literal fragment,
259 then use the generating_literals global. */
261 unsigned is_literal
: 1;
262 unsigned is_insn
: 1;
263 unsigned is_data
: 1;
264 unsigned is_unreachable
: 1;
266 /* is_specific_opcode implies no_transform. */
267 unsigned is_no_transform
: 1;
271 unsigned is_loop_target
: 1;
272 unsigned is_branch_target
: 1; /* Branch targets have a priority. */
273 unsigned bt_align_priority
: 2;
275 unsigned is_no_density
: 1;
276 /* no_longcalls flag does not need to be placed in the object file. */
278 unsigned is_no_reorder
: 1;
280 /* Uses absolute literal addressing for l32r. */
281 unsigned is_abslit
: 1;
283 unsigned is_align
: 1;
284 unsigned alignment
: 5;
288 /* Structure for saving information about a block of property data
289 for frags that have the same flags. */
290 struct xtensa_block_info_struct
296 struct xtensa_block_info_struct
*next
;
300 /* Structure for saving the current state before emitting literals. */
301 typedef struct emit_state_struct
306 int generating_literals
;
310 /* Opcode placement information */
312 typedef unsigned long long bitfield
;
313 #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit)))
314 #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit)))
315 #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit)))
317 #define MAX_FORMATS 32
319 typedef struct op_placement_info_struct
322 /* A number describing how restrictive the issue is for this
323 opcode. For example, an opcode that fits lots of different
324 formats has a high freedom, as does an opcode that fits
325 only one format but many slots in that format. The most
326 restrictive is the opcode that fits only one slot in one
329 xtensa_format narrowest
;
333 /* formats is a bitfield with the Nth bit set
334 if the opcode fits in the Nth xtensa_format. */
337 /* slots[N]'s Mth bit is set if the op fits in the
338 Mth slot of the Nth xtensa_format. */
339 bitfield slots
[MAX_FORMATS
];
341 /* A count of the number of slots in a given format
342 an op can fit (i.e., the bitcount of the slot field above). */
343 char slots_in_format
[MAX_FORMATS
];
345 } op_placement_info
, *op_placement_info_table
;
347 op_placement_info_table op_placement_table
;
350 /* Extra expression types. */
352 #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */
353 #define O_hi16 O_md2 /* use high 16 bits of symbolic value */
354 #define O_lo16 O_md3 /* use low 16 bits of symbolic value */
355 #define O_pcrel O_md4 /* value is a PC-relative offset */
356 #define O_tlsfunc O_md5 /* TLS_FUNC/TLSDESC_FN relocation */
357 #define O_tlsarg O_md6 /* TLS_ARG/TLSDESC_ARG relocation */
358 #define O_tlscall O_md7 /* TLS_CALL relocation */
359 #define O_tpoff O_md8 /* TPOFF relocation */
360 #define O_dtpoff O_md9 /* DTPOFF relocation */
362 struct suffix_reloc_map
366 bfd_reloc_code_real_type reloc
;
367 unsigned char operator;
370 #define SUFFIX_MAP(str, reloc, op) { str, sizeof (str) - 1, reloc, op }
372 static struct suffix_reloc_map suffix_relocs
[] =
374 SUFFIX_MAP ("l", BFD_RELOC_LO16
, O_lo16
),
375 SUFFIX_MAP ("h", BFD_RELOC_HI16
, O_hi16
),
376 SUFFIX_MAP ("plt", BFD_RELOC_XTENSA_PLT
, O_pltrel
),
377 SUFFIX_MAP ("pcrel", BFD_RELOC_32_PCREL
, O_pcrel
),
378 SUFFIX_MAP ("tlsfunc", BFD_RELOC_XTENSA_TLS_FUNC
, O_tlsfunc
),
379 SUFFIX_MAP ("tlsarg", BFD_RELOC_XTENSA_TLS_ARG
, O_tlsarg
),
380 SUFFIX_MAP ("tlscall", BFD_RELOC_XTENSA_TLS_CALL
, O_tlscall
),
381 SUFFIX_MAP ("tpoff", BFD_RELOC_XTENSA_TLS_TPOFF
, O_tpoff
),
382 SUFFIX_MAP ("dtpoff", BFD_RELOC_XTENSA_TLS_DTPOFF
, O_dtpoff
),
383 { (char *) 0, 0, BFD_RELOC_UNUSED
, 0 }
397 directive_literal_prefix
,
399 directive_absolute_literals
,
400 directive_last_directive
406 bfd_boolean can_be_negated
;
409 const directive_infoS directive_info
[] =
412 { "literal", FALSE
},
414 { "transform", TRUE
},
415 { "freeregs", FALSE
},
416 { "longcalls", TRUE
},
417 { "literal_prefix", FALSE
},
418 { "schedule", TRUE
},
419 { "absolute-literals", TRUE
}
422 bfd_boolean directive_state
[] =
426 #if !XCHAL_HAVE_DENSITY
431 TRUE
, /* transform */
432 FALSE
, /* freeregs */
433 FALSE
, /* longcalls */
434 FALSE
, /* literal_prefix */
435 FALSE
, /* schedule */
436 #if XSHAL_USE_ABSOLUTE_LITERALS
437 TRUE
/* absolute_literals */
439 FALSE
/* absolute_literals */
443 /* A circular list of all potential and actual literal pool locations
447 struct litpool_frag
*next
;
448 struct litpool_frag
*prev
;
451 short priority
; /* 1, 2, or 3 -- 1 is highest */
452 short original_priority
;
455 /* Map a segment to its litpool_frag list. */
458 struct litpool_seg
*next
;
460 struct litpool_frag frag_list
;
461 int frag_count
; /* since last litpool location */
464 static struct litpool_seg litpool_seg_list
;
467 /* Directive functions. */
469 static void xtensa_begin_directive (int);
470 static void xtensa_end_directive (int);
471 static void xtensa_literal_prefix (void);
472 static void xtensa_literal_position (int);
473 static void xtensa_literal_pseudo (int);
474 static void xtensa_frequency_pseudo (int);
475 static void xtensa_elf_cons (int);
476 static void xtensa_leb128 (int);
478 /* Parsing and Idiom Translation. */
480 static bfd_reloc_code_real_type
xtensa_elf_suffix (char **, expressionS
*);
482 /* Various Other Internal Functions. */
484 extern bfd_boolean
xg_is_single_relaxable_insn (TInsn
*, TInsn
*, bfd_boolean
);
485 static bfd_boolean
xg_build_to_insn (TInsn
*, TInsn
*, BuildInstr
*);
486 static void xtensa_mark_literal_pool_location (void);
487 static addressT
get_expanded_loop_offset (xtensa_opcode
);
488 static fragS
*get_literal_pool_location (segT
);
489 static void set_literal_pool_location (segT
, fragS
*);
490 static void xtensa_set_frag_assembly_state (fragS
*);
491 static void finish_vinsn (vliw_insn
*);
492 static bfd_boolean
emit_single_op (TInsn
*);
493 static int total_frag_text_expansion (fragS
*);
494 static bfd_boolean use_trampolines
= TRUE
;
495 static void xtensa_check_frag_count (void);
496 static void xtensa_create_trampoline_frag (bfd_boolean
);
497 static void xtensa_maybe_create_trampoline_frag (void);
498 struct trampoline_frag
;
499 static int init_trampoline_frag (struct trampoline_frag
*);
500 static void xtensa_maybe_create_literal_pool_frag (bfd_boolean
, bfd_boolean
);
501 static bfd_boolean auto_litpools
= FALSE
;
502 static int auto_litpool_limit
= 10000;
504 /* Alignment Functions. */
506 static int get_text_align_power (unsigned);
507 static int get_text_align_max_fill_size (int, bfd_boolean
, bfd_boolean
);
508 static int branch_align_power (segT
);
510 /* Helpers for xtensa_relax_frag(). */
512 static long relax_frag_add_nop (fragS
*);
514 /* Accessors for additional per-subsegment information. */
516 static unsigned get_last_insn_flags (segT
, subsegT
);
517 static void set_last_insn_flags (segT
, subsegT
, unsigned, bfd_boolean
);
518 static float get_subseg_total_freq (segT
, subsegT
);
519 static float get_subseg_target_freq (segT
, subsegT
);
520 static void set_subseg_freq (segT
, subsegT
, float, float);
522 /* Segment list functions. */
524 static void xtensa_move_literals (void);
525 static void xtensa_reorder_segments (void);
526 static void xtensa_switch_to_literal_fragment (emit_state
*);
527 static void xtensa_switch_to_non_abs_literal_fragment (emit_state
*);
528 static void xtensa_switch_section_emit_state (emit_state
*, segT
, subsegT
);
529 static void xtensa_restore_emit_state (emit_state
*);
530 static segT
cache_literal_section (bfd_boolean
);
532 /* Import from elf32-xtensa.c in BFD library. */
534 extern asection
*xtensa_make_property_section (asection
*, const char *);
536 /* op_placement_info functions. */
538 static void init_op_placement_info_table (void);
539 extern bfd_boolean
opcode_fits_format_slot (xtensa_opcode
, xtensa_format
, int);
540 static int xg_get_single_size (xtensa_opcode
);
541 static xtensa_format
xg_get_single_format (xtensa_opcode
);
542 static int xg_get_single_slot (xtensa_opcode
);
544 /* TInsn and IStack functions. */
546 static bfd_boolean
tinsn_has_symbolic_operands (const TInsn
*);
547 static bfd_boolean
tinsn_has_invalid_symbolic_operands (const TInsn
*);
548 static bfd_boolean
tinsn_has_complex_operands (const TInsn
*);
549 static bfd_boolean
tinsn_to_insnbuf (TInsn
*, xtensa_insnbuf
);
550 static bfd_boolean
tinsn_check_arguments (const TInsn
*);
551 static void tinsn_from_chars (TInsn
*, char *, int);
552 static void tinsn_immed_from_frag (TInsn
*, fragS
*, int);
553 static int get_num_stack_text_bytes (IStack
*);
554 static int get_num_stack_literal_bytes (IStack
*);
555 static bfd_boolean
tinsn_to_slotbuf (xtensa_format
, int, TInsn
*, xtensa_insnbuf
);
557 /* vliw_insn functions. */
559 static void xg_init_vinsn (vliw_insn
*);
560 static void xg_copy_vinsn (vliw_insn
*, vliw_insn
*);
561 static void xg_clear_vinsn (vliw_insn
*);
562 static bfd_boolean
vinsn_has_specific_opcodes (vliw_insn
*);
563 static void xg_free_vinsn (vliw_insn
*);
564 static bfd_boolean vinsn_to_insnbuf
565 (vliw_insn
*, char *, fragS
*, bfd_boolean
);
566 static void vinsn_from_chars (vliw_insn
*, char *);
568 /* Expression Utilities. */
570 bfd_boolean
expr_is_const (const expressionS
*);
571 offsetT
get_expr_const (const expressionS
*);
572 void set_expr_const (expressionS
*, offsetT
);
573 bfd_boolean
expr_is_register (const expressionS
*);
574 offsetT
get_expr_register (const expressionS
*);
575 void set_expr_symbol_offset (expressionS
*, symbolS
*, offsetT
);
576 bfd_boolean
expr_is_equal (expressionS
*, expressionS
*);
577 static void copy_expr (expressionS
*, const expressionS
*);
579 /* Section renaming. */
581 static void build_section_rename (const char *);
584 /* ISA imported from bfd. */
585 extern xtensa_isa xtensa_default_isa
;
587 extern int target_big_endian
;
589 static xtensa_opcode xtensa_addi_opcode
;
590 static xtensa_opcode xtensa_addmi_opcode
;
591 static xtensa_opcode xtensa_call0_opcode
;
592 static xtensa_opcode xtensa_call4_opcode
;
593 static xtensa_opcode xtensa_call8_opcode
;
594 static xtensa_opcode xtensa_call12_opcode
;
595 static xtensa_opcode xtensa_callx0_opcode
;
596 static xtensa_opcode xtensa_callx4_opcode
;
597 static xtensa_opcode xtensa_callx8_opcode
;
598 static xtensa_opcode xtensa_callx12_opcode
;
599 static xtensa_opcode xtensa_const16_opcode
;
600 static xtensa_opcode xtensa_entry_opcode
;
601 static xtensa_opcode xtensa_extui_opcode
;
602 static xtensa_opcode xtensa_movi_opcode
;
603 static xtensa_opcode xtensa_movi_n_opcode
;
604 static xtensa_opcode xtensa_isync_opcode
;
605 static xtensa_opcode xtensa_j_opcode
;
606 static xtensa_opcode xtensa_jx_opcode
;
607 static xtensa_opcode xtensa_l32r_opcode
;
608 static xtensa_opcode xtensa_loop_opcode
;
609 static xtensa_opcode xtensa_loopnez_opcode
;
610 static xtensa_opcode xtensa_loopgtz_opcode
;
611 static xtensa_opcode xtensa_nop_opcode
;
612 static xtensa_opcode xtensa_nop_n_opcode
;
613 static xtensa_opcode xtensa_or_opcode
;
614 static xtensa_opcode xtensa_ret_opcode
;
615 static xtensa_opcode xtensa_ret_n_opcode
;
616 static xtensa_opcode xtensa_retw_opcode
;
617 static xtensa_opcode xtensa_retw_n_opcode
;
618 static xtensa_opcode xtensa_rsr_lcount_opcode
;
619 static xtensa_opcode xtensa_waiti_opcode
;
620 static int config_max_slots
= 0;
623 /* Command-line Options. */
625 bfd_boolean use_literal_section
= TRUE
;
626 enum flix_level produce_flix
= FLIX_ALL
;
627 static bfd_boolean align_targets
= TRUE
;
628 static bfd_boolean warn_unaligned_branch_targets
= FALSE
;
629 static bfd_boolean has_a0_b_retw
= FALSE
;
630 static bfd_boolean workaround_a0_b_retw
= FALSE
;
631 static bfd_boolean workaround_b_j_loop_end
= FALSE
;
632 static bfd_boolean workaround_short_loop
= FALSE
;
633 static bfd_boolean maybe_has_short_loop
= FALSE
;
634 static bfd_boolean workaround_close_loop_end
= FALSE
;
635 static bfd_boolean maybe_has_close_loop_end
= FALSE
;
636 static bfd_boolean enforce_three_byte_loop_align
= FALSE
;
638 /* When workaround_short_loops is TRUE, all loops with early exits must
639 have at least 3 instructions. workaround_all_short_loops is a modifier
640 to the workaround_short_loop flag. In addition to the
641 workaround_short_loop actions, all straightline loopgtz and loopnez
642 must have at least 3 instructions. */
644 static bfd_boolean workaround_all_short_loops
= FALSE
;
648 xtensa_setup_hw_workarounds (int earliest
, int latest
)
650 if (earliest
> latest
)
651 as_fatal (_("illegal range of target hardware versions"));
653 /* Enable all workarounds for pre-T1050.0 hardware. */
654 if (earliest
< 105000 || latest
< 105000)
656 workaround_a0_b_retw
|= TRUE
;
657 workaround_b_j_loop_end
|= TRUE
;
658 workaround_short_loop
|= TRUE
;
659 workaround_close_loop_end
|= TRUE
;
660 workaround_all_short_loops
|= TRUE
;
661 enforce_three_byte_loop_align
= TRUE
;
668 option_density
= OPTION_MD_BASE
,
672 option_no_generate_flix
,
679 option_no_link_relax
,
687 option_text_section_literals
,
688 option_no_text_section_literals
,
690 option_absolute_literals
,
691 option_no_absolute_literals
,
693 option_align_targets
,
694 option_no_align_targets
,
696 option_warn_unaligned_targets
,
701 option_workaround_a0_b_retw
,
702 option_no_workaround_a0_b_retw
,
704 option_workaround_b_j_loop_end
,
705 option_no_workaround_b_j_loop_end
,
707 option_workaround_short_loop
,
708 option_no_workaround_short_loop
,
710 option_workaround_all_short_loops
,
711 option_no_workaround_all_short_loops
,
713 option_workaround_close_loop_end
,
714 option_no_workaround_close_loop_end
,
716 option_no_workarounds
,
718 option_rename_section_name
,
721 option_prefer_const16
,
723 option_target_hardware
,
726 option_no_trampolines
,
728 option_auto_litpools
,
729 option_no_auto_litpools
,
730 option_auto_litpool_limit
,
733 const char *md_shortopts
= "";
735 struct option md_longopts
[] =
737 { "density", no_argument
, NULL
, option_density
},
738 { "no-density", no_argument
, NULL
, option_no_density
},
740 { "flix", no_argument
, NULL
, option_flix
},
741 { "no-generate-flix", no_argument
, NULL
, option_no_generate_flix
},
742 { "no-allow-flix", no_argument
, NULL
, option_no_flix
},
744 /* Both "relax" and "generics" are deprecated and treated as equivalent
745 to the "transform" option. */
746 { "relax", no_argument
, NULL
, option_relax
},
747 { "no-relax", no_argument
, NULL
, option_no_relax
},
748 { "generics", no_argument
, NULL
, option_generics
},
749 { "no-generics", no_argument
, NULL
, option_no_generics
},
751 { "transform", no_argument
, NULL
, option_transform
},
752 { "no-transform", no_argument
, NULL
, option_no_transform
},
753 { "text-section-literals", no_argument
, NULL
, option_text_section_literals
},
754 { "no-text-section-literals", no_argument
, NULL
,
755 option_no_text_section_literals
},
756 { "absolute-literals", no_argument
, NULL
, option_absolute_literals
},
757 { "no-absolute-literals", no_argument
, NULL
, option_no_absolute_literals
},
758 /* This option was changed from -align-target to -target-align
759 because it conflicted with the "-al" option. */
760 { "target-align", no_argument
, NULL
, option_align_targets
},
761 { "no-target-align", no_argument
, NULL
, option_no_align_targets
},
762 { "warn-unaligned-targets", no_argument
, NULL
,
763 option_warn_unaligned_targets
},
764 { "longcalls", no_argument
, NULL
, option_longcalls
},
765 { "no-longcalls", no_argument
, NULL
, option_no_longcalls
},
767 { "no-workaround-a0-b-retw", no_argument
, NULL
,
768 option_no_workaround_a0_b_retw
},
769 { "workaround-a0-b-retw", no_argument
, NULL
, option_workaround_a0_b_retw
},
771 { "no-workaround-b-j-loop-end", no_argument
, NULL
,
772 option_no_workaround_b_j_loop_end
},
773 { "workaround-b-j-loop-end", no_argument
, NULL
,
774 option_workaround_b_j_loop_end
},
776 { "no-workaround-short-loops", no_argument
, NULL
,
777 option_no_workaround_short_loop
},
778 { "workaround-short-loops", no_argument
, NULL
,
779 option_workaround_short_loop
},
781 { "no-workaround-all-short-loops", no_argument
, NULL
,
782 option_no_workaround_all_short_loops
},
783 { "workaround-all-short-loop", no_argument
, NULL
,
784 option_workaround_all_short_loops
},
786 { "prefer-l32r", no_argument
, NULL
, option_prefer_l32r
},
787 { "prefer-const16", no_argument
, NULL
, option_prefer_const16
},
789 { "no-workarounds", no_argument
, NULL
, option_no_workarounds
},
791 { "no-workaround-close-loop-end", no_argument
, NULL
,
792 option_no_workaround_close_loop_end
},
793 { "workaround-close-loop-end", no_argument
, NULL
,
794 option_workaround_close_loop_end
},
796 { "rename-section", required_argument
, NULL
, option_rename_section_name
},
798 { "link-relax", no_argument
, NULL
, option_link_relax
},
799 { "no-link-relax", no_argument
, NULL
, option_no_link_relax
},
801 { "target-hardware", required_argument
, NULL
, option_target_hardware
},
803 { "trampolines", no_argument
, NULL
, option_trampolines
},
804 { "no-trampolines", no_argument
, NULL
, option_no_trampolines
},
806 { "auto-litpools", no_argument
, NULL
, option_auto_litpools
},
807 { "no-auto-litpools", no_argument
, NULL
, option_no_auto_litpools
},
808 { "auto-litpool-limit", required_argument
, NULL
, option_auto_litpool_limit
},
810 { NULL
, no_argument
, NULL
, 0 }
813 size_t md_longopts_size
= sizeof md_longopts
;
817 md_parse_option (int c
, const char *arg
)
822 as_warn (_("--density option is ignored"));
824 case option_no_density
:
825 as_warn (_("--no-density option is ignored"));
827 case option_link_relax
:
830 case option_no_link_relax
:
834 produce_flix
= FLIX_ALL
;
836 case option_no_generate_flix
:
837 produce_flix
= FLIX_NO_GENERATE
;
840 produce_flix
= FLIX_NONE
;
842 case option_generics
:
843 as_warn (_("--generics is deprecated; use --transform instead"));
844 return md_parse_option (option_transform
, arg
);
845 case option_no_generics
:
846 as_warn (_("--no-generics is deprecated; use --no-transform instead"));
847 return md_parse_option (option_no_transform
, arg
);
849 as_warn (_("--relax is deprecated; use --transform instead"));
850 return md_parse_option (option_transform
, arg
);
851 case option_no_relax
:
852 as_warn (_("--no-relax is deprecated; use --no-transform instead"));
853 return md_parse_option (option_no_transform
, arg
);
854 case option_longcalls
:
855 directive_state
[directive_longcalls
] = TRUE
;
857 case option_no_longcalls
:
858 directive_state
[directive_longcalls
] = FALSE
;
860 case option_text_section_literals
:
861 use_literal_section
= FALSE
;
863 case option_no_text_section_literals
:
864 use_literal_section
= TRUE
;
866 case option_absolute_literals
:
867 if (!absolute_literals_supported
)
869 as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
872 directive_state
[directive_absolute_literals
] = TRUE
;
874 case option_no_absolute_literals
:
875 directive_state
[directive_absolute_literals
] = FALSE
;
878 case option_workaround_a0_b_retw
:
879 workaround_a0_b_retw
= TRUE
;
881 case option_no_workaround_a0_b_retw
:
882 workaround_a0_b_retw
= FALSE
;
884 case option_workaround_b_j_loop_end
:
885 workaround_b_j_loop_end
= TRUE
;
887 case option_no_workaround_b_j_loop_end
:
888 workaround_b_j_loop_end
= FALSE
;
891 case option_workaround_short_loop
:
892 workaround_short_loop
= TRUE
;
894 case option_no_workaround_short_loop
:
895 workaround_short_loop
= FALSE
;
898 case option_workaround_all_short_loops
:
899 workaround_all_short_loops
= TRUE
;
901 case option_no_workaround_all_short_loops
:
902 workaround_all_short_loops
= FALSE
;
905 case option_workaround_close_loop_end
:
906 workaround_close_loop_end
= TRUE
;
908 case option_no_workaround_close_loop_end
:
909 workaround_close_loop_end
= FALSE
;
912 case option_no_workarounds
:
913 workaround_a0_b_retw
= FALSE
;
914 workaround_b_j_loop_end
= FALSE
;
915 workaround_short_loop
= FALSE
;
916 workaround_all_short_loops
= FALSE
;
917 workaround_close_loop_end
= FALSE
;
920 case option_align_targets
:
921 align_targets
= TRUE
;
923 case option_no_align_targets
:
924 align_targets
= FALSE
;
927 case option_warn_unaligned_targets
:
928 warn_unaligned_branch_targets
= TRUE
;
931 case option_rename_section_name
:
932 build_section_rename (arg
);
936 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
937 should be emitted or not. FIXME: Not implemented. */
940 case option_prefer_l32r
:
942 as_fatal (_("prefer-l32r conflicts with prefer-const16"));
946 case option_prefer_const16
:
948 as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
952 case option_target_hardware
:
954 int earliest
, latest
= 0;
956 if (*arg
== 0 || *arg
== '-')
957 as_fatal (_("invalid target hardware version"));
959 earliest
= strtol (arg
, &end
, 0);
963 else if (*end
== '-')
966 as_fatal (_("invalid target hardware version"));
967 latest
= strtol (end
, &end
, 0);
970 as_fatal (_("invalid target hardware version"));
972 xtensa_setup_hw_workarounds (earliest
, latest
);
976 case option_transform
:
977 /* This option has no affect other than to use the defaults,
978 which are already set. */
981 case option_no_transform
:
982 /* This option turns off all transformations of any kind.
983 However, because we want to preserve the state of other
984 directives, we only change its own field. Thus, before
985 you perform any transformation, always check if transform
986 is available. If you use the functions we provide for this
987 purpose, you will be ok. */
988 directive_state
[directive_transform
] = FALSE
;
991 case option_trampolines
:
992 use_trampolines
= TRUE
;
995 case option_no_trampolines
:
996 use_trampolines
= FALSE
;
999 case option_auto_litpools
:
1000 auto_litpools
= TRUE
;
1001 use_literal_section
= FALSE
;
1004 case option_no_auto_litpools
:
1005 auto_litpools
= FALSE
;
1006 auto_litpool_limit
= -1;
1009 case option_auto_litpool_limit
:
1013 if (auto_litpool_limit
< 0)
1014 as_fatal (_("no-auto-litpools is incompatible with auto-litpool-limit"));
1015 if (*arg
== 0 || *arg
== '-')
1016 as_fatal (_("invalid auto-litpool-limit argument"));
1017 value
= strtol (arg
, &end
, 10);
1019 as_fatal (_("invalid auto-litpool-limit argument"));
1020 if (value
< 100 || value
> 10000)
1021 as_fatal (_("invalid auto-litpool-limit argument (range is 100-10000)"));
1022 auto_litpool_limit
= value
;
1023 auto_litpools
= TRUE
;
1024 use_literal_section
= FALSE
;
1035 md_show_usage (FILE *stream
)
1039 --[no-]text-section-literals\n\
1040 [Do not] put literals in the text section\n\
1041 --[no-]absolute-literals\n\
1042 [Do not] default to use non-PC-relative literals\n\
1043 --[no-]target-align [Do not] try to align branch targets\n\
1044 --[no-]longcalls [Do not] emit 32-bit call sequences\n\
1045 --[no-]transform [Do not] transform instructions\n\
1046 --flix both allow hand-written and generate flix bundles\n\
1047 --no-generate-flix allow hand-written but do not generate\n\
1049 --no-allow-flix neither allow hand-written nor generate\n\
1051 --rename-section old=new Rename section 'old' to 'new'\n\
1052 --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\
1053 when jumps do not reach their targets\n\
1054 --[no-]auto-litpools [Do not] automatically create literal pools\n\
1055 --auto-litpool-limit=<value>\n\
1056 (range 100-10000) Maximum number of blocks of\n\
1057 instructions to emit between literal pool\n\
1058 locations; implies --auto-litpools flag\n", stream
);
1062 /* Functions related to the list of current label symbols. */
1065 xtensa_add_insn_label (symbolS
*sym
)
1069 if (!free_insn_labels
)
1070 l
= XNEW (sym_list
);
1073 l
= free_insn_labels
;
1074 free_insn_labels
= l
->next
;
1078 l
->next
= insn_labels
;
1084 xtensa_clear_insn_labels (void)
1088 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1096 xtensa_move_labels (fragS
*new_frag
, valueT new_offset
)
1100 for (lit
= insn_labels
; lit
; lit
= lit
->next
)
1102 symbolS
*lit_sym
= lit
->sym
;
1103 S_SET_VALUE (lit_sym
, new_offset
);
1104 symbol_set_frag (lit_sym
, new_frag
);
1109 /* Directive data and functions. */
1111 typedef struct state_stackS_struct
1113 directiveE directive
;
1114 bfd_boolean negated
;
1115 bfd_boolean old_state
;
1119 struct state_stackS_struct
*prev
;
1122 state_stackS
*directive_state_stack
;
1124 const pseudo_typeS md_pseudo_table
[] =
1126 { "align", s_align_bytes
, 0 }, /* Defaulting is invalid (0). */
1127 { "literal_position", xtensa_literal_position
, 0 },
1128 { "frame", s_ignore
, 0 }, /* Formerly used for STABS debugging. */
1129 { "long", xtensa_elf_cons
, 4 },
1130 { "word", xtensa_elf_cons
, 4 },
1131 { "4byte", xtensa_elf_cons
, 4 },
1132 { "short", xtensa_elf_cons
, 2 },
1133 { "2byte", xtensa_elf_cons
, 2 },
1134 { "sleb128", xtensa_leb128
, 1},
1135 { "uleb128", xtensa_leb128
, 0},
1136 { "begin", xtensa_begin_directive
, 0 },
1137 { "end", xtensa_end_directive
, 0 },
1138 { "literal", xtensa_literal_pseudo
, 0 },
1139 { "frequency", xtensa_frequency_pseudo
, 0 },
1145 use_transform (void)
1147 /* After md_end, you should be checking frag by frag, rather
1148 than state directives. */
1149 gas_assert (!past_xtensa_end
);
1150 return directive_state
[directive_transform
];
1155 do_align_targets (void)
1157 /* Do not use this function after md_end; just look at align_targets
1158 instead. There is no target-align directive, so alignment is either
1159 enabled for all frags or not done at all. */
1160 gas_assert (!past_xtensa_end
);
1161 return align_targets
&& use_transform ();
1166 directive_push (directiveE directive
, bfd_boolean negated
, const void *datum
)
1170 state_stackS
*stack
= XNEW (state_stackS
);
1172 file
= as_where (&line
);
1174 stack
->directive
= directive
;
1175 stack
->negated
= negated
;
1176 stack
->old_state
= directive_state
[directive
];
1179 stack
->datum
= datum
;
1180 stack
->prev
= directive_state_stack
;
1181 directive_state_stack
= stack
;
1183 directive_state
[directive
] = !negated
;
1188 directive_pop (directiveE
*directive
,
1189 bfd_boolean
*negated
,
1194 state_stackS
*top
= directive_state_stack
;
1196 if (!directive_state_stack
)
1198 as_bad (_("unmatched end directive"));
1199 *directive
= directive_none
;
1203 directive_state
[directive_state_stack
->directive
] = top
->old_state
;
1204 *directive
= top
->directive
;
1205 *negated
= top
->negated
;
1208 *datum
= top
->datum
;
1209 directive_state_stack
= top
->prev
;
1215 directive_balance (void)
1217 while (directive_state_stack
)
1219 directiveE directive
;
1220 bfd_boolean negated
;
1225 directive_pop (&directive
, &negated
, &file
, &line
, &datum
);
1226 as_warn_where ((char *) file
, line
,
1227 _(".begin directive with no matching .end directive"));
1233 inside_directive (directiveE dir
)
1235 state_stackS
*top
= directive_state_stack
;
1237 while (top
&& top
->directive
!= dir
)
1240 return (top
!= NULL
);
1245 get_directive (directiveE
*directive
, bfd_boolean
*negated
)
1249 const char *directive_string
;
1251 if (strncmp (input_line_pointer
, "no-", 3) != 0)
1256 input_line_pointer
+= 3;
1259 len
= strspn (input_line_pointer
,
1260 "abcdefghijklmnopqrstuvwxyz_-/0123456789.");
1262 /* This code is a hack to make .begin [no-][generics|relax] exactly
1263 equivalent to .begin [no-]transform. We should remove it when
1264 we stop accepting those options. */
1266 if (strncmp (input_line_pointer
, "generics", strlen ("generics")) == 0)
1268 as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
1269 directive_string
= "transform";
1271 else if (strncmp (input_line_pointer
, "relax", strlen ("relax")) == 0)
1273 as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
1274 directive_string
= "transform";
1277 directive_string
= input_line_pointer
;
1279 for (i
= 0; i
< sizeof (directive_info
) / sizeof (*directive_info
); ++i
)
1281 if (strncmp (directive_string
, directive_info
[i
].name
, len
) == 0)
1283 input_line_pointer
+= len
;
1284 *directive
= (directiveE
) i
;
1285 if (*negated
&& !directive_info
[i
].can_be_negated
)
1286 as_bad (_("directive %s cannot be negated"),
1287 directive_info
[i
].name
);
1292 as_bad (_("unknown directive"));
1293 *directive
= (directiveE
) XTENSA_UNDEFINED
;
1298 xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED
)
1300 directiveE directive
;
1301 bfd_boolean negated
;
1305 get_directive (&directive
, &negated
);
1306 if (directive
== (directiveE
) XTENSA_UNDEFINED
)
1308 discard_rest_of_line ();
1312 if (cur_vinsn
.inside_bundle
)
1313 as_bad (_("directives are not valid inside bundles"));
1317 case directive_literal
:
1318 if (!inside_directive (directive_literal
))
1320 /* Previous labels go with whatever follows this directive, not with
1321 the literal, so save them now. */
1322 saved_insn_labels
= insn_labels
;
1325 as_warn (_(".begin literal is deprecated; use .literal instead"));
1326 state
= XNEW (emit_state
);
1327 xtensa_switch_to_literal_fragment (state
);
1328 directive_push (directive_literal
, negated
, state
);
1331 case directive_literal_prefix
:
1332 /* Have to flush pending output because a movi relaxed to an l32r
1333 might produce a literal. */
1334 md_flush_pending_output ();
1335 /* Check to see if the current fragment is a literal
1336 fragment. If it is, then this operation is not allowed. */
1337 if (generating_literals
)
1339 as_bad (_("cannot set literal_prefix inside literal fragment"));
1343 /* Allocate the literal state for this section and push
1344 onto the directive stack. */
1345 ls
= XNEW (lit_state
);
1348 *ls
= default_lit_sections
;
1349 directive_push (directive_literal_prefix
, negated
, ls
);
1351 /* Process the new prefix. */
1352 xtensa_literal_prefix ();
1355 case directive_freeregs
:
1356 /* This information is currently unused, but we'll accept the statement
1357 and just discard the rest of the line. This won't check the syntax,
1358 but it will accept every correct freeregs directive. */
1359 input_line_pointer
+= strcspn (input_line_pointer
, "\n");
1360 directive_push (directive_freeregs
, negated
, 0);
1363 case directive_schedule
:
1364 md_flush_pending_output ();
1365 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
1366 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
1367 directive_push (directive_schedule
, negated
, 0);
1368 xtensa_set_frag_assembly_state (frag_now
);
1371 case directive_density
:
1372 as_warn (_(".begin [no-]density is ignored"));
1375 case directive_absolute_literals
:
1376 md_flush_pending_output ();
1377 if (!absolute_literals_supported
&& !negated
)
1379 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1382 xtensa_set_frag_assembly_state (frag_now
);
1383 directive_push (directive
, negated
, 0);
1387 md_flush_pending_output ();
1388 xtensa_set_frag_assembly_state (frag_now
);
1389 directive_push (directive
, negated
, 0);
1393 demand_empty_rest_of_line ();
1398 xtensa_end_directive (int ignore ATTRIBUTE_UNUSED
)
1400 directiveE begin_directive
, end_directive
;
1401 bfd_boolean begin_negated
, end_negated
;
1405 emit_state
**state_ptr
;
1408 if (cur_vinsn
.inside_bundle
)
1409 as_bad (_("directives are not valid inside bundles"));
1411 get_directive (&end_directive
, &end_negated
);
1413 md_flush_pending_output ();
1415 switch ((int) end_directive
)
1417 case XTENSA_UNDEFINED
:
1418 discard_rest_of_line ();
1421 case (int) directive_density
:
1422 as_warn (_(".end [no-]density is ignored"));
1423 demand_empty_rest_of_line ();
1426 case (int) directive_absolute_literals
:
1427 if (!absolute_literals_supported
&& !end_negated
)
1429 as_warn (_("Xtensa absolute literals option not supported; ignored"));
1430 demand_empty_rest_of_line ();
1439 state_ptr
= &state
; /* use state_ptr to avoid type-punning warning */
1440 directive_pop (&begin_directive
, &begin_negated
, &file
, &line
,
1441 (const void **) state_ptr
);
1443 if (begin_directive
!= directive_none
)
1445 if (begin_directive
!= end_directive
|| begin_negated
!= end_negated
)
1447 as_bad (_("does not match begin %s%s at %s:%d"),
1448 begin_negated
? "no-" : "",
1449 directive_info
[begin_directive
].name
, file
, line
);
1453 switch (end_directive
)
1455 case directive_literal
:
1456 frag_var (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
1457 xtensa_restore_emit_state (state
);
1458 xtensa_set_frag_assembly_state (frag_now
);
1460 if (!inside_directive (directive_literal
))
1462 /* Restore the list of current labels. */
1463 xtensa_clear_insn_labels ();
1464 insn_labels
= saved_insn_labels
;
1468 case directive_literal_prefix
:
1469 /* Restore the default collection sections from saved state. */
1470 s
= (lit_state
*) state
;
1472 default_lit_sections
= *s
;
1474 /* Free the state storage. */
1475 free (s
->lit_prefix
);
1479 case directive_schedule
:
1480 case directive_freeregs
:
1484 xtensa_set_frag_assembly_state (frag_now
);
1490 demand_empty_rest_of_line ();
1494 /* Place an aligned literal fragment at the current location. */
1497 xtensa_literal_position (int ignore ATTRIBUTE_UNUSED
)
1499 md_flush_pending_output ();
1501 if (inside_directive (directive_literal
))
1502 as_warn (_(".literal_position inside literal directive; ignoring"));
1503 xtensa_mark_literal_pool_location ();
1505 demand_empty_rest_of_line ();
1506 xtensa_clear_insn_labels ();
1510 /* Support .literal label, expr, ... */
1513 xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED
)
1516 char *p
, *base_name
;
1520 if (inside_directive (directive_literal
))
1522 as_bad (_(".literal not allowed inside .begin literal region"));
1523 ignore_rest_of_line ();
1527 md_flush_pending_output ();
1529 /* Previous labels go with whatever follows this directive, not with
1530 the literal, so save them now. */
1531 saved_insn_labels
= insn_labels
;
1534 /* If we are using text-section literals, then this is the right value... */
1537 base_name
= input_line_pointer
;
1539 xtensa_switch_to_literal_fragment (&state
);
1541 /* ...but if we aren't using text-section-literals, then we
1542 need to put them in the section we just switched to. */
1543 if (use_literal_section
|| directive_state
[directive_absolute_literals
])
1546 /* FIXME, despite the previous comments, dest_seg is unused... */
1549 /* All literals are aligned to four-byte boundaries. */
1550 frag_align (2, 0, 0);
1551 record_alignment (now_seg
, 2);
1553 c
= get_symbol_name (&base_name
);
1554 /* Just after name is now '\0'. */
1555 p
= input_line_pointer
;
1557 SKIP_WHITESPACE_AFTER_NAME ();
1559 if (*input_line_pointer
!= ',' && *input_line_pointer
!= ':')
1561 as_bad (_("expected comma or colon after symbol name; "
1562 "rest of line ignored"));
1563 ignore_rest_of_line ();
1564 xtensa_restore_emit_state (&state
);
1572 input_line_pointer
++; /* skip ',' or ':' */
1574 xtensa_elf_cons (4);
1576 xtensa_restore_emit_state (&state
);
1578 /* Restore the list of current labels. */
1579 xtensa_clear_insn_labels ();
1580 insn_labels
= saved_insn_labels
;
1585 xtensa_literal_prefix (void)
1590 /* Parse the new prefix from the input_line_pointer. */
1592 len
= strspn (input_line_pointer
,
1593 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
1594 "abcdefghijklmnopqrstuvwxyz_/0123456789.$");
1596 /* Get a null-terminated copy of the name. */
1597 name
= xmalloc (len
+ 1);
1599 strncpy (name
, input_line_pointer
, len
);
1602 /* Skip the name in the input line. */
1603 input_line_pointer
+= len
;
1605 default_lit_sections
.lit_prefix
= name
;
1607 /* Clear cached literal sections, since the prefix has changed. */
1608 default_lit_sections
.lit_seg
= NULL
;
1609 default_lit_sections
.lit4_seg
= NULL
;
1613 /* Support ".frequency branch_target_frequency fall_through_frequency". */
1616 xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED
)
1618 float fall_through_f
, target_f
;
1620 fall_through_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1621 if (fall_through_f
< 0)
1623 as_bad (_("fall through frequency must be greater than 0"));
1624 ignore_rest_of_line ();
1628 target_f
= (float) strtod (input_line_pointer
, &input_line_pointer
);
1631 as_bad (_("branch target frequency must be greater than 0"));
1632 ignore_rest_of_line ();
1636 set_subseg_freq (now_seg
, now_subseg
, target_f
+ fall_through_f
, target_f
);
1638 demand_empty_rest_of_line ();
1642 /* Like normal .long/.short/.word, except support @plt, etc.
1643 Clobbers input_line_pointer, checks end-of-line. */
1646 xtensa_elf_cons (int nbytes
)
1649 bfd_reloc_code_real_type reloc
;
1651 md_flush_pending_output ();
1653 if (cur_vinsn
.inside_bundle
)
1654 as_bad (_("directives are not valid inside bundles"));
1656 if (is_it_end_of_statement ())
1658 demand_empty_rest_of_line ();
1665 if (exp
.X_op
== O_symbol
1666 && *input_line_pointer
== '@'
1667 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, &exp
))
1670 reloc_howto_type
*reloc_howto
=
1671 bfd_reloc_type_lookup (stdoutput
, reloc
);
1673 if (reloc
== BFD_RELOC_UNUSED
|| !reloc_howto
)
1674 as_bad (_("unsupported relocation"));
1675 else if ((reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
1676 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
1677 || (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
1678 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
))
1679 as_bad (_("opcode-specific %s relocation used outside "
1680 "an instruction"), reloc_howto
->name
);
1681 else if (nbytes
!= (int) bfd_get_reloc_size (reloc_howto
))
1682 as_bad (_("%s relocations do not fit in %d bytes"),
1683 reloc_howto
->name
, nbytes
);
1684 else if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
1685 || reloc
== BFD_RELOC_XTENSA_TLS_ARG
1686 || reloc
== BFD_RELOC_XTENSA_TLS_CALL
)
1687 as_bad (_("invalid use of %s relocation"), reloc_howto
->name
);
1690 char *p
= frag_more ((int) nbytes
);
1691 xtensa_set_frag_assembly_state (frag_now
);
1692 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
1693 nbytes
, &exp
, reloc_howto
->pc_relative
, reloc
);
1698 xtensa_set_frag_assembly_state (frag_now
);
1699 emit_expr (&exp
, (unsigned int) nbytes
);
1702 while (*input_line_pointer
++ == ',');
1704 input_line_pointer
--; /* Put terminator back into stream. */
1705 demand_empty_rest_of_line ();
1708 static bfd_boolean is_leb128_expr
;
1711 xtensa_leb128 (int sign
)
1713 is_leb128_expr
= TRUE
;
1715 is_leb128_expr
= FALSE
;
1719 /* Parsing and Idiom Translation. */
1721 /* Parse @plt, etc. and return the desired relocation. */
1722 static bfd_reloc_code_real_type
1723 xtensa_elf_suffix (char **str_p
, expressionS
*exp_p
)
1730 struct suffix_reloc_map
*ptr
;
1733 return BFD_RELOC_NONE
;
1735 for (ch
= *str
, str2
= ident
;
1736 (str2
< ident
+ sizeof (ident
) - 1
1737 && (ISALNUM (ch
) || ch
== '@'));
1740 *str2
++ = (ISLOWER (ch
)) ? ch
: TOLOWER (ch
);
1747 for (ptr
= &suffix_relocs
[0]; ptr
->length
> 0; ptr
++)
1748 if (ch
== ptr
->suffix
[0]
1749 && len
== ptr
->length
1750 && memcmp (ident
, ptr
->suffix
, ptr
->length
) == 0)
1752 /* Now check for "identifier@suffix+constant". */
1753 if (*str
== '-' || *str
== '+')
1755 char *orig_line
= input_line_pointer
;
1756 expressionS new_exp
;
1758 input_line_pointer
= str
;
1759 expression (&new_exp
);
1760 if (new_exp
.X_op
== O_constant
)
1762 exp_p
->X_add_number
+= new_exp
.X_add_number
;
1763 str
= input_line_pointer
;
1766 if (&input_line_pointer
!= str_p
)
1767 input_line_pointer
= orig_line
;
1774 return BFD_RELOC_UNUSED
;
1778 /* Find the matching operator type. */
1779 static unsigned char
1780 map_suffix_reloc_to_operator (bfd_reloc_code_real_type reloc
)
1782 struct suffix_reloc_map
*sfx
;
1783 unsigned char operator = (unsigned char) -1;
1785 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1787 if (sfx
->reloc
== reloc
)
1789 operator = sfx
->operator;
1793 gas_assert (operator != (unsigned char) -1);
1798 /* Find the matching reloc type. */
1799 static bfd_reloc_code_real_type
1800 map_operator_to_reloc (unsigned char operator, bfd_boolean is_literal
)
1802 struct suffix_reloc_map
*sfx
;
1803 bfd_reloc_code_real_type reloc
= BFD_RELOC_UNUSED
;
1805 for (sfx
= &suffix_relocs
[0]; sfx
->suffix
; sfx
++)
1807 if (sfx
->operator == operator)
1816 if (reloc
== BFD_RELOC_XTENSA_TLS_FUNC
)
1817 return BFD_RELOC_XTENSA_TLSDESC_FN
;
1818 else if (reloc
== BFD_RELOC_XTENSA_TLS_ARG
)
1819 return BFD_RELOC_XTENSA_TLSDESC_ARG
;
1822 if (reloc
== BFD_RELOC_UNUSED
)
1823 return BFD_RELOC_32
;
1830 expression_end (const char *name
)
1853 #define ERROR_REG_NUM ((unsigned) -1)
1856 tc_get_register (const char *prefix
)
1859 const char *next_expr
;
1860 const char *old_line_pointer
;
1863 old_line_pointer
= input_line_pointer
;
1865 if (*input_line_pointer
== '$')
1866 ++input_line_pointer
;
1868 /* Accept "sp" as a synonym for "a1". */
1869 if (input_line_pointer
[0] == 's' && input_line_pointer
[1] == 'p'
1870 && expression_end (input_line_pointer
+ 2))
1872 input_line_pointer
+= 2;
1873 return 1; /* AR[1] */
1876 while (*input_line_pointer
++ == *prefix
++)
1878 --input_line_pointer
;
1883 as_bad (_("bad register name: %s"), old_line_pointer
);
1884 return ERROR_REG_NUM
;
1887 if (!ISDIGIT ((unsigned char) *input_line_pointer
))
1889 as_bad (_("bad register number: %s"), input_line_pointer
);
1890 return ERROR_REG_NUM
;
1895 while (ISDIGIT ((int) *input_line_pointer
))
1896 reg
= reg
* 10 + *input_line_pointer
++ - '0';
1898 if (!(next_expr
= expression_end (input_line_pointer
)))
1900 as_bad (_("bad register name: %s"), old_line_pointer
);
1901 return ERROR_REG_NUM
;
1904 input_line_pointer
= (char *) next_expr
;
1911 expression_maybe_register (xtensa_opcode opc
, int opnd
, expressionS
*tok
)
1913 xtensa_isa isa
= xtensa_default_isa
;
1915 /* Check if this is an immediate operand. */
1916 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 0)
1918 bfd_reloc_code_real_type reloc
;
1919 segT t
= expression (tok
);
1921 if (t
== absolute_section
1922 && xtensa_operand_is_PCrelative (isa
, opc
, opnd
) == 1)
1924 gas_assert (tok
->X_op
== O_constant
);
1925 tok
->X_op
= O_symbol
;
1926 tok
->X_add_symbol
= &abs_symbol
;
1929 if ((tok
->X_op
== O_constant
|| tok
->X_op
== O_symbol
)
1930 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
1935 case BFD_RELOC_LO16
:
1936 if (tok
->X_op
== O_constant
)
1938 tok
->X_add_number
&= 0xffff;
1942 case BFD_RELOC_HI16
:
1943 if (tok
->X_op
== O_constant
)
1945 tok
->X_add_number
= ((unsigned) tok
->X_add_number
) >> 16;
1949 case BFD_RELOC_UNUSED
:
1950 as_bad (_("unsupported relocation"));
1952 case BFD_RELOC_32_PCREL
:
1953 as_bad (_("pcrel relocation not allowed in an instruction"));
1958 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
1963 xtensa_regfile opnd_rf
= xtensa_operand_regfile (isa
, opc
, opnd
);
1964 unsigned reg
= tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
));
1966 if (reg
!= ERROR_REG_NUM
) /* Already errored */
1969 if (xtensa_operand_encode (isa
, opc
, opnd
, &buf
))
1970 as_bad (_("register number out of range"));
1973 tok
->X_op
= O_register
;
1974 tok
->X_add_symbol
= 0;
1975 tok
->X_add_number
= reg
;
1980 /* Split up the arguments for an opcode or pseudo-op. */
1983 tokenize_arguments (char **args
, char *str
)
1985 char *old_input_line_pointer
;
1986 bfd_boolean saw_comma
= FALSE
;
1987 bfd_boolean saw_arg
= FALSE
;
1988 bfd_boolean saw_colon
= FALSE
;
1990 char *arg_end
, *arg
;
1993 /* Save and restore input_line_pointer around this function. */
1994 old_input_line_pointer
= input_line_pointer
;
1995 input_line_pointer
= str
;
1997 while (*input_line_pointer
)
2000 switch (*input_line_pointer
)
2007 input_line_pointer
++;
2008 if (saw_comma
|| saw_colon
|| !saw_arg
)
2014 input_line_pointer
++;
2015 if (saw_comma
|| saw_colon
|| !saw_arg
)
2021 if (!saw_comma
&& !saw_colon
&& saw_arg
)
2024 arg_end
= input_line_pointer
+ 1;
2025 while (!expression_end (arg_end
))
2028 arg_len
= arg_end
- input_line_pointer
;
2029 arg
= XNEWVEC (char, (saw_colon
? 1 : 0) + arg_len
+ 1);
2030 args
[num_args
] = arg
;
2034 strncpy (arg
, input_line_pointer
, arg_len
);
2035 arg
[arg_len
] = '\0';
2037 input_line_pointer
= arg_end
;
2047 if (saw_comma
|| saw_colon
)
2049 input_line_pointer
= old_input_line_pointer
;
2054 as_bad (_("extra comma"));
2056 as_bad (_("extra colon"));
2058 as_bad (_("missing argument"));
2060 as_bad (_("missing comma or colon"));
2061 input_line_pointer
= old_input_line_pointer
;
2066 /* Parse the arguments to an opcode. Return TRUE on error. */
2069 parse_arguments (TInsn
*insn
, int num_args
, char **arg_strings
)
2071 expressionS
*tok
, *last_tok
;
2072 xtensa_opcode opcode
= insn
->opcode
;
2073 bfd_boolean had_error
= TRUE
;
2074 xtensa_isa isa
= xtensa_default_isa
;
2075 int n
, num_regs
= 0;
2076 int opcode_operand_count
;
2077 int opnd_cnt
, last_opnd_cnt
;
2078 unsigned int next_reg
= 0;
2079 char *old_input_line_pointer
;
2081 if (insn
->insn_type
== ITYPE_LITERAL
)
2082 opcode_operand_count
= 1;
2084 opcode_operand_count
= xtensa_opcode_num_operands (isa
, opcode
);
2087 memset (tok
, 0, sizeof (*tok
) * MAX_INSN_ARGS
);
2089 /* Save and restore input_line_pointer around this function. */
2090 old_input_line_pointer
= input_line_pointer
;
2096 /* Skip invisible operands. */
2097 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0)
2103 for (n
= 0; n
< num_args
; n
++)
2105 input_line_pointer
= arg_strings
[n
];
2106 if (*input_line_pointer
== ':')
2108 xtensa_regfile opnd_rf
;
2109 input_line_pointer
++;
2112 gas_assert (opnd_cnt
> 0);
2114 opnd_rf
= xtensa_operand_regfile (isa
, opcode
, last_opnd_cnt
);
2116 != tc_get_register (xtensa_regfile_shortname (isa
, opnd_rf
)))
2117 as_warn (_("incorrect register number, ignoring"));
2122 if (opnd_cnt
>= opcode_operand_count
)
2124 as_warn (_("too many arguments"));
2127 gas_assert (opnd_cnt
< MAX_INSN_ARGS
);
2129 expression_maybe_register (opcode
, opnd_cnt
, tok
);
2130 next_reg
= tok
->X_add_number
+ 1;
2132 if (tok
->X_op
== O_illegal
|| tok
->X_op
== O_absent
)
2134 if (xtensa_operand_is_register (isa
, opcode
, opnd_cnt
) == 1)
2136 num_regs
= xtensa_operand_num_regs (isa
, opcode
, opnd_cnt
) - 1;
2137 /* minus 1 because we are seeing one right now */
2143 last_opnd_cnt
= opnd_cnt
;
2144 demand_empty_rest_of_line ();
2151 while (xtensa_operand_is_visible (isa
, opcode
, opnd_cnt
) == 0);
2155 if (num_regs
> 0 && ((int) next_reg
!= last_tok
->X_add_number
+ 1))
2158 insn
->ntok
= tok
- insn
->tok
;
2162 input_line_pointer
= old_input_line_pointer
;
2168 get_invisible_operands (TInsn
*insn
)
2170 xtensa_isa isa
= xtensa_default_isa
;
2171 static xtensa_insnbuf slotbuf
= NULL
;
2173 xtensa_opcode opc
= insn
->opcode
;
2174 int slot
, opnd
, fmt_found
;
2178 slotbuf
= xtensa_insnbuf_alloc (isa
);
2180 /* Find format/slot where this can be encoded. */
2183 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
2185 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
2187 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opc
) == 0)
2193 if (fmt_found
) break;
2198 as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa
, opc
));
2202 /* First encode all the visible operands
2203 (to deal with shared field operands). */
2204 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2206 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 1
2207 && (insn
->tok
[opnd
].X_op
== O_register
2208 || insn
->tok
[opnd
].X_op
== O_constant
))
2210 val
= insn
->tok
[opnd
].X_add_number
;
2211 xtensa_operand_encode (isa
, opc
, opnd
, &val
);
2212 xtensa_operand_set_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, val
);
2216 /* Then pull out the values for the invisible ones. */
2217 for (opnd
= 0; opnd
< insn
->ntok
; opnd
++)
2219 if (xtensa_operand_is_visible (isa
, opc
, opnd
) == 0)
2221 xtensa_operand_get_field (isa
, opc
, opnd
, fmt
, slot
, slotbuf
, &val
);
2222 xtensa_operand_decode (isa
, opc
, opnd
, &val
);
2223 insn
->tok
[opnd
].X_add_number
= val
;
2224 if (xtensa_operand_is_register (isa
, opc
, opnd
) == 1)
2225 insn
->tok
[opnd
].X_op
= O_register
;
2227 insn
->tok
[opnd
].X_op
= O_constant
;
2236 xg_reverse_shift_count (char **cnt_argp
)
2238 char *cnt_arg
, *new_arg
;
2239 cnt_arg
= *cnt_argp
;
2241 /* replace the argument with "31-(argument)" */
2242 new_arg
= (char *) xmalloc (strlen (cnt_arg
) + 6);
2243 sprintf (new_arg
, "31-(%s)", cnt_arg
);
2246 *cnt_argp
= new_arg
;
2250 /* If "arg" is a constant expression, return non-zero with the value
2254 xg_arg_is_constant (char *arg
, offsetT
*valp
)
2257 char *save_ptr
= input_line_pointer
;
2259 input_line_pointer
= arg
;
2261 input_line_pointer
= save_ptr
;
2263 if (exp
.X_op
== O_constant
)
2265 *valp
= exp
.X_add_number
;
2274 xg_replace_opname (char **popname
, const char *newop
)
2277 *popname
= xstrdup (newop
);
2282 xg_check_num_args (int *pnum_args
,
2287 int num_args
= *pnum_args
;
2289 if (num_args
< expected_num
)
2291 as_bad (_("not enough operands (%d) for '%s'; expected %d"),
2292 num_args
, opname
, expected_num
);
2296 if (num_args
> expected_num
)
2298 as_warn (_("too many operands (%d) for '%s'; expected %d"),
2299 num_args
, opname
, expected_num
);
2300 while (num_args
-- > expected_num
)
2302 free (arg_strings
[num_args
]);
2303 arg_strings
[num_args
] = 0;
2305 *pnum_args
= expected_num
;
2313 /* If the register is not specified as part of the opcode,
2314 then get it from the operand and move it to the opcode. */
2317 xg_translate_sysreg_op (char **popname
, int *pnum_args
, char **arg_strings
)
2319 xtensa_isa isa
= xtensa_default_isa
;
2321 char *opname
, *new_opname
;
2322 const char *sr_name
;
2323 int is_user
, is_write
;
2328 is_user
= (opname
[1] == 'u');
2329 is_write
= (opname
[0] == 'w');
2331 /* Opname == [rw]ur or [rwx]sr... */
2333 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2336 /* Check if the argument is a symbolic register name. */
2337 sr
= xtensa_sysreg_lookup_name (isa
, arg_strings
[1]);
2338 /* Handle WSR to "INTSET" as a special case. */
2339 if (sr
== XTENSA_UNDEFINED
&& is_write
&& !is_user
2340 && !strcasecmp (arg_strings
[1], "intset"))
2341 sr
= xtensa_sysreg_lookup_name (isa
, "interrupt");
2342 if (sr
== XTENSA_UNDEFINED
2343 || (xtensa_sysreg_is_user (isa
, sr
) == 1) != is_user
)
2345 /* Maybe it's a register number.... */
2347 if (!xg_arg_is_constant (arg_strings
[1], &val
))
2349 as_bad (_("invalid register '%s' for '%s' instruction"),
2350 arg_strings
[1], opname
);
2353 sr
= xtensa_sysreg_lookup (isa
, val
, is_user
);
2354 if (sr
== XTENSA_UNDEFINED
)
2356 as_bad (_("invalid register number (%ld) for '%s' instruction"),
2357 (long) val
, opname
);
2362 /* Remove the last argument, which is now part of the opcode. */
2363 free (arg_strings
[1]);
2367 /* Translate the opcode. */
2368 sr_name
= xtensa_sysreg_name (isa
, sr
);
2369 /* Another special case for "WSR.INTSET".... */
2370 if (is_write
&& !is_user
&& !strcasecmp ("interrupt", sr_name
))
2372 new_opname
= concat (*popname
, ".", sr_name
, (char *) NULL
);
2374 *popname
= new_opname
;
2381 xtensa_translate_old_userreg_ops (char **popname
)
2383 xtensa_isa isa
= xtensa_default_isa
;
2385 char *opname
, *new_opname
;
2386 const char *sr_name
;
2387 bfd_boolean has_underbar
= FALSE
;
2390 if (opname
[0] == '_')
2392 has_underbar
= TRUE
;
2396 sr
= xtensa_sysreg_lookup_name (isa
, opname
+ 1);
2397 if (sr
!= XTENSA_UNDEFINED
)
2399 /* The new default name ("nnn") is different from the old default
2400 name ("URnnn"). The old default is handled below, and we don't
2401 want to recognize [RW]nnn, so do nothing if the name is the (new)
2403 static char namebuf
[10];
2404 sprintf (namebuf
, "%d", xtensa_sysreg_number (isa
, sr
));
2405 if (strcmp (namebuf
, opname
+ 1) == 0)
2413 /* Only continue if the reg name is "URnnn". */
2414 if (opname
[1] != 'u' || opname
[2] != 'r')
2416 val
= strtoul (opname
+ 3, &end
, 10);
2420 sr
= xtensa_sysreg_lookup (isa
, val
, 1);
2421 if (sr
== XTENSA_UNDEFINED
)
2423 as_bad (_("invalid register number (%ld) for '%s'"),
2424 (long) val
, opname
);
2429 /* Translate the opcode. */
2430 sr_name
= xtensa_sysreg_name (isa
, sr
);
2431 new_opname
= (char *) xmalloc (strlen (sr_name
) + 6);
2432 sprintf (new_opname
, "%s%cur.%s", (has_underbar
? "_" : ""),
2433 opname
[0], sr_name
);
2435 *popname
= new_opname
;
2442 xtensa_translate_zero_immed (const char *old_op
,
2452 gas_assert (opname
[0] != '_');
2454 if (strcmp (opname
, old_op
) != 0)
2457 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2459 if (xg_arg_is_constant (arg_strings
[1], &val
) && val
== 0)
2461 xg_replace_opname (popname
, new_op
);
2462 free (arg_strings
[1]);
2463 arg_strings
[1] = arg_strings
[2];
2472 /* If the instruction is an idiom (i.e., a built-in macro), translate it.
2473 Returns non-zero if an error was found. */
2476 xg_translate_idioms (char **popname
, int *pnum_args
, char **arg_strings
)
2478 char *opname
= *popname
;
2479 bfd_boolean has_underbar
= FALSE
;
2483 has_underbar
= TRUE
;
2487 if (strcmp (opname
, "mov") == 0)
2489 if (use_transform () && !has_underbar
&& density_supported
)
2490 xg_replace_opname (popname
, "mov.n");
2493 if (xg_check_num_args (pnum_args
, 2, opname
, arg_strings
))
2495 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2496 arg_strings
[2] = xstrdup (arg_strings
[1]);
2502 if (strcmp (opname
, "bbsi.l") == 0)
2504 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2506 xg_replace_opname (popname
, (has_underbar
? "_bbsi" : "bbsi"));
2507 if (target_big_endian
)
2508 xg_reverse_shift_count (&arg_strings
[1]);
2512 if (strcmp (opname
, "bbci.l") == 0)
2514 if (xg_check_num_args (pnum_args
, 3, opname
, arg_strings
))
2516 xg_replace_opname (popname
, (has_underbar
? "_bbci" : "bbci"));
2517 if (target_big_endian
)
2518 xg_reverse_shift_count (&arg_strings
[1]);
2522 /* Don't do anything special with NOPs inside FLIX instructions. They
2523 are handled elsewhere. Real NOP instructions are always available
2524 in configurations with FLIX, so this should never be an issue but
2525 check for it anyway. */
2526 if (!cur_vinsn
.inside_bundle
&& xtensa_nop_opcode
== XTENSA_UNDEFINED
2527 && strcmp (opname
, "nop") == 0)
2529 if (use_transform () && !has_underbar
&& density_supported
)
2530 xg_replace_opname (popname
, "nop.n");
2533 if (xg_check_num_args (pnum_args
, 0, opname
, arg_strings
))
2535 xg_replace_opname (popname
, (has_underbar
? "_or" : "or"));
2536 arg_strings
[0] = xstrdup ("a1");
2537 arg_strings
[1] = xstrdup ("a1");
2538 arg_strings
[2] = xstrdup ("a1");
2544 /* Recognize [RW]UR and [RWX]SR. */
2545 if ((((opname
[0] == 'r' || opname
[0] == 'w')
2546 && (opname
[1] == 'u' || opname
[1] == 's'))
2547 || (opname
[0] == 'x' && opname
[1] == 's'))
2549 && opname
[3] == '\0')
2550 return xg_translate_sysreg_op (popname
, pnum_args
, arg_strings
);
2552 /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
2553 [RW]<name> if <name> is the non-default name of a user register. */
2554 if ((opname
[0] == 'r' || opname
[0] == 'w')
2555 && xtensa_opcode_lookup (xtensa_default_isa
, opname
) == XTENSA_UNDEFINED
)
2556 return xtensa_translate_old_userreg_ops (popname
);
2558 /* Relax branches that don't allow comparisons against an immediate value
2559 of zero to the corresponding branches with implicit zero immediates. */
2560 if (!has_underbar
&& use_transform ())
2562 if (xtensa_translate_zero_immed ("bnei", "bnez", popname
,
2563 pnum_args
, arg_strings
))
2566 if (xtensa_translate_zero_immed ("beqi", "beqz", popname
,
2567 pnum_args
, arg_strings
))
2570 if (xtensa_translate_zero_immed ("bgei", "bgez", popname
,
2571 pnum_args
, arg_strings
))
2574 if (xtensa_translate_zero_immed ("blti", "bltz", popname
,
2575 pnum_args
, arg_strings
))
2583 /* Functions for dealing with the Xtensa ISA. */
2585 /* Currently the assembler only allows us to use a single target per
2586 fragment. Because of this, only one operand for a given
2587 instruction may be symbolic. If there is a PC-relative operand,
2588 the last one is chosen. Otherwise, the result is the number of the
2589 last immediate operand, and if there are none of those, we fail and
2593 get_relaxable_immed (xtensa_opcode opcode
)
2595 int last_immed
= -1;
2598 if (opcode
== XTENSA_UNDEFINED
)
2601 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
, opcode
);
2602 for (opi
= noperands
- 1; opi
>= 0; opi
--)
2604 if (xtensa_operand_is_visible (xtensa_default_isa
, opcode
, opi
) == 0)
2606 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, opi
) == 1)
2608 if (last_immed
== -1
2609 && xtensa_operand_is_register (xtensa_default_isa
, opcode
, opi
) == 0)
2616 static xtensa_opcode
2617 get_opcode_from_buf (const char *buf
, int slot
)
2619 static xtensa_insnbuf insnbuf
= NULL
;
2620 static xtensa_insnbuf slotbuf
= NULL
;
2621 xtensa_isa isa
= xtensa_default_isa
;
2626 insnbuf
= xtensa_insnbuf_alloc (isa
);
2627 slotbuf
= xtensa_insnbuf_alloc (isa
);
2630 xtensa_insnbuf_from_chars (isa
, insnbuf
, (const unsigned char *) buf
, 0);
2631 fmt
= xtensa_format_decode (isa
, insnbuf
);
2632 if (fmt
== XTENSA_UNDEFINED
)
2633 return XTENSA_UNDEFINED
;
2635 if (slot
>= xtensa_format_num_slots (isa
, fmt
))
2636 return XTENSA_UNDEFINED
;
2638 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
2639 return xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
2643 #ifdef TENSILICA_DEBUG
2645 /* For debugging, print out the mapping of opcode numbers to opcodes. */
2648 xtensa_print_insn_table (void)
2650 int num_opcodes
, num_operands
;
2651 xtensa_opcode opcode
;
2652 xtensa_isa isa
= xtensa_default_isa
;
2654 num_opcodes
= xtensa_isa_num_opcodes (xtensa_default_isa
);
2655 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
2658 fprintf (stderr
, "%d: %s: ", opcode
, xtensa_opcode_name (isa
, opcode
));
2659 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2660 for (opn
= 0; opn
< num_operands
; opn
++)
2662 if (xtensa_operand_is_visible (isa
, opcode
, opn
) == 0)
2664 if (xtensa_operand_is_register (isa
, opcode
, opn
) == 1)
2666 xtensa_regfile opnd_rf
=
2667 xtensa_operand_regfile (isa
, opcode
, opn
);
2668 fprintf (stderr
, "%s ", xtensa_regfile_shortname (isa
, opnd_rf
));
2670 else if (xtensa_operand_is_PCrelative (isa
, opcode
, opn
) == 1)
2671 fputs ("[lLr] ", stderr
);
2673 fputs ("i ", stderr
);
2675 fprintf (stderr
, "\n");
2681 print_vliw_insn (xtensa_insnbuf vbuf
)
2683 xtensa_isa isa
= xtensa_default_isa
;
2684 xtensa_format f
= xtensa_format_decode (isa
, vbuf
);
2685 xtensa_insnbuf sbuf
= xtensa_insnbuf_alloc (isa
);
2688 fprintf (stderr
, "format = %d\n", f
);
2690 for (op
= 0; op
< xtensa_format_num_slots (isa
, f
); op
++)
2692 xtensa_opcode opcode
;
2696 xtensa_format_get_slot (isa
, f
, op
, vbuf
, sbuf
);
2697 opcode
= xtensa_opcode_decode (isa
, f
, op
, sbuf
);
2698 opname
= xtensa_opcode_name (isa
, opcode
);
2700 fprintf (stderr
, "op in slot %i is %s;\n", op
, opname
);
2701 fprintf (stderr
, " operands = ");
2703 operands
< xtensa_opcode_num_operands (isa
, opcode
);
2707 if (xtensa_operand_is_visible (isa
, opcode
, operands
) == 0)
2709 xtensa_operand_get_field (isa
, opcode
, operands
, f
, op
, sbuf
, &val
);
2710 xtensa_operand_decode (isa
, opcode
, operands
, &val
);
2711 fprintf (stderr
, "%d ", val
);
2713 fprintf (stderr
, "\n");
2715 xtensa_insnbuf_free (isa
, sbuf
);
2718 #endif /* TENSILICA_DEBUG */
2722 is_direct_call_opcode (xtensa_opcode opcode
)
2724 xtensa_isa isa
= xtensa_default_isa
;
2725 int n
, num_operands
;
2727 if (xtensa_opcode_is_call (isa
, opcode
) != 1)
2730 num_operands
= xtensa_opcode_num_operands (isa
, opcode
);
2731 for (n
= 0; n
< num_operands
; n
++)
2733 if (xtensa_operand_is_register (isa
, opcode
, n
) == 0
2734 && xtensa_operand_is_PCrelative (isa
, opcode
, n
) == 1)
2741 /* Convert from BFD relocation type code to slot and operand number.
2742 Returns non-zero on failure. */
2745 decode_reloc (bfd_reloc_code_real_type reloc
, int *slot
, bfd_boolean
*is_alt
)
2747 if (reloc
>= BFD_RELOC_XTENSA_SLOT0_OP
2748 && reloc
<= BFD_RELOC_XTENSA_SLOT14_OP
)
2750 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_OP
;
2753 else if (reloc
>= BFD_RELOC_XTENSA_SLOT0_ALT
2754 && reloc
<= BFD_RELOC_XTENSA_SLOT14_ALT
)
2756 *slot
= reloc
- BFD_RELOC_XTENSA_SLOT0_ALT
;
2766 /* Convert from slot number to BFD relocation type code for the
2767 standard PC-relative relocations. Return BFD_RELOC_NONE on
2770 static bfd_reloc_code_real_type
2771 encode_reloc (int slot
)
2773 if (slot
< 0 || slot
> 14)
2774 return BFD_RELOC_NONE
;
2776 return BFD_RELOC_XTENSA_SLOT0_OP
+ slot
;
2780 /* Convert from slot numbers to BFD relocation type code for the
2781 "alternate" relocations. Return BFD_RELOC_NONE on failure. */
2783 static bfd_reloc_code_real_type
2784 encode_alt_reloc (int slot
)
2786 if (slot
< 0 || slot
> 14)
2787 return BFD_RELOC_NONE
;
2789 return BFD_RELOC_XTENSA_SLOT0_ALT
+ slot
;
2794 xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf
,
2797 xtensa_opcode opcode
,
2803 uint32 valbuf
= value
;
2805 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
2807 if (xtensa_operand_is_PCrelative (xtensa_default_isa
, opcode
, operand
)
2809 as_bad_where ((char *) file
, line
,
2810 _("operand %d of '%s' has out of range value '%u'"),
2812 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2815 as_bad_where ((char *) file
, line
,
2816 _("operand %d of '%s' has invalid value '%u'"),
2818 xtensa_opcode_name (xtensa_default_isa
, opcode
),
2823 xtensa_operand_set_field (xtensa_default_isa
, opcode
, operand
, fmt
, slot
,
2829 xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf
,
2832 xtensa_opcode opcode
,
2836 (void) xtensa_operand_get_field (xtensa_default_isa
, opcode
, opnum
,
2837 fmt
, slot
, slotbuf
, &val
);
2838 (void) xtensa_operand_decode (xtensa_default_isa
, opcode
, opnum
, &val
);
2843 /* Checks for rules from xtensa-relax tables. */
2845 /* The routine xg_instruction_matches_option_term must return TRUE
2846 when a given option term is true. The meaning of all of the option
2847 terms is given interpretation by this function. */
2850 xg_instruction_matches_option_term (TInsn
*insn
, const ReqOrOption
*option
)
2852 if (strcmp (option
->option_name
, "realnop") == 0
2853 || strncmp (option
->option_name
, "IsaUse", 6) == 0)
2855 /* These conditions were evaluated statically when building the
2856 relaxation table. There's no need to reevaluate them now. */
2859 else if (strcmp (option
->option_name
, "FREEREG") == 0)
2860 return insn
->extra_arg
.X_op
== O_register
;
2863 as_fatal (_("internal error: unknown option name '%s'"),
2864 option
->option_name
);
2870 xg_instruction_matches_or_options (TInsn
*insn
,
2871 const ReqOrOptionList
*or_option
)
2873 const ReqOrOption
*option
;
2874 /* Must match each of the AND terms. */
2875 for (option
= or_option
; option
!= NULL
; option
= option
->next
)
2877 if (xg_instruction_matches_option_term (insn
, option
))
2885 xg_instruction_matches_options (TInsn
*insn
, const ReqOptionList
*options
)
2887 const ReqOption
*req_options
;
2888 /* Must match each of the AND terms. */
2889 for (req_options
= options
;
2890 req_options
!= NULL
;
2891 req_options
= req_options
->next
)
2893 /* Must match one of the OR clauses. */
2894 if (!xg_instruction_matches_or_options (insn
,
2895 req_options
->or_option_terms
))
2902 /* Return the transition rule that matches or NULL if none matches. */
2905 xg_instruction_matches_rule (TInsn
*insn
, TransitionRule
*rule
)
2907 PreconditionList
*condition_l
;
2909 if (rule
->opcode
!= insn
->opcode
)
2912 for (condition_l
= rule
->conditions
;
2913 condition_l
!= NULL
;
2914 condition_l
= condition_l
->next
)
2918 Precondition
*cond
= condition_l
->precond
;
2923 /* The expression must be the constant. */
2924 gas_assert (cond
->op_num
< insn
->ntok
);
2925 exp1
= &insn
->tok
[cond
->op_num
];
2926 if (expr_is_const (exp1
))
2931 if (get_expr_const (exp1
) != cond
->op_data
)
2935 if (get_expr_const (exp1
) == cond
->op_data
)
2942 else if (expr_is_register (exp1
))
2947 if (get_expr_register (exp1
) != cond
->op_data
)
2951 if (get_expr_register (exp1
) == cond
->op_data
)
2963 gas_assert (cond
->op_num
< insn
->ntok
);
2964 gas_assert (cond
->op_data
< insn
->ntok
);
2965 exp1
= &insn
->tok
[cond
->op_num
];
2966 exp2
= &insn
->tok
[cond
->op_data
];
2971 if (!expr_is_equal (exp1
, exp2
))
2975 if (expr_is_equal (exp1
, exp2
))
2987 if (!xg_instruction_matches_options (insn
, rule
->options
))
2995 transition_rule_cmp (const TransitionRule
*a
, const TransitionRule
*b
)
2997 bfd_boolean a_greater
= FALSE
;
2998 bfd_boolean b_greater
= FALSE
;
3000 ReqOptionList
*l_a
= a
->options
;
3001 ReqOptionList
*l_b
= b
->options
;
3003 /* We only care if they both are the same except for
3004 a const16 vs. an l32r. */
3006 while (l_a
&& l_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3008 ReqOrOptionList
*l_or_a
= l_a
->or_option_terms
;
3009 ReqOrOptionList
*l_or_b
= l_b
->or_option_terms
;
3010 while (l_or_a
&& l_or_b
&& ((l_a
->next
== NULL
) == (l_b
->next
== NULL
)))
3012 if (l_or_a
->is_true
!= l_or_b
->is_true
)
3014 if (strcmp (l_or_a
->option_name
, l_or_b
->option_name
) != 0)
3016 /* This is the case we care about. */
3017 if (strcmp (l_or_a
->option_name
, "IsaUseConst16") == 0
3018 && strcmp (l_or_b
->option_name
, "IsaUseL32R") == 0)
3025 else if (strcmp (l_or_a
->option_name
, "IsaUseL32R") == 0
3026 && strcmp (l_or_b
->option_name
, "IsaUseConst16") == 0)
3036 l_or_a
= l_or_a
->next
;
3037 l_or_b
= l_or_b
->next
;
3039 if (l_or_a
|| l_or_b
)
3048 /* Incomparable if the substitution was used differently in two cases. */
3049 if (a_greater
&& b_greater
)
3061 static TransitionRule
*
3062 xg_instruction_match (TInsn
*insn
)
3064 TransitionTable
*table
= xg_build_simplify_table (&transition_rule_cmp
);
3066 gas_assert (insn
->opcode
< table
->num_opcodes
);
3068 /* Walk through all of the possible transitions. */
3069 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3071 TransitionRule
*rule
= l
->rule
;
3072 if (xg_instruction_matches_rule (insn
, rule
))
3079 /* Various Other Internal Functions. */
3082 is_unique_insn_expansion (TransitionRule
*r
)
3084 if (!r
->to_instr
|| r
->to_instr
->next
!= NULL
)
3086 if (r
->to_instr
->typ
!= INSTR_INSTR
)
3092 /* Check if there is exactly one relaxation for INSN that converts it to
3093 another instruction of equal or larger size. If so, and if TARG is
3094 non-null, go ahead and generate the relaxed instruction into TARG. If
3095 NARROW_ONLY is true, then only consider relaxations that widen a narrow
3096 instruction, i.e., ignore relaxations that convert to an instruction of
3097 equal size. In some contexts where this function is used, only
3098 a single widening is allowed and the NARROW_ONLY argument is used to
3099 exclude cases like ADDI being "widened" to an ADDMI, which may
3100 later be relaxed to an ADDMI/ADDI pair. */
3103 xg_is_single_relaxable_insn (TInsn
*insn
, TInsn
*targ
, bfd_boolean narrow_only
)
3105 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3107 TransitionRule
*match
= 0;
3109 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3110 gas_assert (insn
->opcode
< table
->num_opcodes
);
3112 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3114 TransitionRule
*rule
= l
->rule
;
3116 if (xg_instruction_matches_rule (insn
, rule
)
3117 && is_unique_insn_expansion (rule
)
3118 && (xg_get_single_size (insn
->opcode
) + (narrow_only
? 1 : 0)
3119 <= xg_get_single_size (rule
->to_instr
->opcode
)))
3130 xg_build_to_insn (targ
, insn
, match
->to_instr
);
3135 /* Return the maximum number of bytes this opcode can expand to. */
3138 xg_get_max_insn_widen_size (xtensa_opcode opcode
)
3140 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3142 int max_size
= xg_get_single_size (opcode
);
3144 gas_assert (opcode
< table
->num_opcodes
);
3146 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3148 TransitionRule
*rule
= l
->rule
;
3149 BuildInstr
*build_list
;
3154 build_list
= rule
->to_instr
;
3155 if (is_unique_insn_expansion (rule
))
3157 gas_assert (build_list
->typ
== INSTR_INSTR
);
3158 this_size
= xg_get_max_insn_widen_size (build_list
->opcode
);
3161 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3163 switch (build_list
->typ
)
3166 this_size
+= xg_get_single_size (build_list
->opcode
);
3168 case INSTR_LITERAL_DEF
:
3169 case INSTR_LABEL_DEF
:
3174 if (this_size
> max_size
)
3175 max_size
= this_size
;
3181 /* Return the maximum number of literal bytes this opcode can generate. */
3184 xg_get_max_insn_widen_literal_size (xtensa_opcode opcode
)
3186 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3190 gas_assert (opcode
< table
->num_opcodes
);
3192 for (l
= table
->table
[opcode
]; l
!= NULL
; l
= l
->next
)
3194 TransitionRule
*rule
= l
->rule
;
3195 BuildInstr
*build_list
;
3200 build_list
= rule
->to_instr
;
3201 if (is_unique_insn_expansion (rule
))
3203 gas_assert (build_list
->typ
== INSTR_INSTR
);
3204 this_size
= xg_get_max_insn_widen_literal_size (build_list
->opcode
);
3207 for (; build_list
!= NULL
; build_list
= build_list
->next
)
3209 switch (build_list
->typ
)
3211 case INSTR_LITERAL_DEF
:
3212 /* Hard-coded 4-byte literal. */
3216 case INSTR_LABEL_DEF
:
3221 if (this_size
> max_size
)
3222 max_size
= this_size
;
3229 xg_is_relaxable_insn (TInsn
*insn
, int lateral_steps
)
3231 int steps_taken
= 0;
3232 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3235 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3236 gas_assert (insn
->opcode
< table
->num_opcodes
);
3238 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3240 TransitionRule
*rule
= l
->rule
;
3242 if (xg_instruction_matches_rule (insn
, rule
))
3244 if (steps_taken
== lateral_steps
)
3254 get_special_literal_symbol (void)
3256 static symbolS
*sym
= NULL
;
3259 sym
= symbol_find_or_make ("SPECIAL_LITERAL0\001");
3265 get_special_label_symbol (void)
3267 static symbolS
*sym
= NULL
;
3270 sym
= symbol_find_or_make ("SPECIAL_LABEL0\001");
3276 xg_valid_literal_expression (const expressionS
*exp
)
3298 /* This will check to see if the value can be converted into the
3299 operand type. It will return TRUE if it does not fit. */
3302 xg_check_operand (int32 value
, xtensa_opcode opcode
, int operand
)
3304 uint32 valbuf
= value
;
3305 if (xtensa_operand_encode (xtensa_default_isa
, opcode
, operand
, &valbuf
))
3311 /* Assumes: All immeds are constants. Check that all constants fit
3312 into their immeds; return FALSE if not. */
3315 xg_immeds_fit (const TInsn
*insn
)
3317 xtensa_isa isa
= xtensa_default_isa
;
3321 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3322 for (i
= 0; i
< n
; ++i
)
3324 const expressionS
*exp
= &insn
->tok
[i
];
3326 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3333 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3338 /* The symbol should have a fixup associated with it. */
3347 /* This should only be called after we have an initial
3348 estimate of the addresses. */
3351 xg_symbolic_immeds_fit (const TInsn
*insn
,
3357 xtensa_isa isa
= xtensa_default_isa
;
3365 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3367 for (i
= 0; i
< n
; ++i
)
3369 const expressionS
*exp
= &insn
->tok
[i
];
3371 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
3378 if (xg_check_operand (exp
->X_add_number
, insn
->opcode
, i
))
3384 /* Check for the worst case. */
3385 if (xg_check_operand (0xffff, insn
->opcode
, i
))
3390 /* We only allow symbols for PC-relative references.
3391 If pc_frag == 0, then we don't have frag locations yet. */
3393 || xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 0)
3396 /* If it is a weak symbol or a symbol in a different section,
3397 it cannot be known to fit at assembly time. */
3398 if (S_IS_WEAK (exp
->X_add_symbol
)
3399 || S_GET_SEGMENT (exp
->X_add_symbol
) != pc_seg
)
3401 /* For a direct call with --no-longcalls, be optimistic and
3402 assume it will be in range. If the symbol is weak and
3403 undefined, it may remain undefined at link-time, in which
3404 case it will have a zero value and almost certainly be out
3405 of range for a direct call; thus, relax for undefined weak
3406 symbols even if longcalls is not enabled. */
3407 if (is_direct_call_opcode (insn
->opcode
)
3408 && ! pc_frag
->tc_frag_data
.use_longcalls
3409 && (! S_IS_WEAK (exp
->X_add_symbol
)
3410 || S_IS_DEFINED (exp
->X_add_symbol
)))
3416 symbolP
= exp
->X_add_symbol
;
3417 sym_frag
= symbol_get_frag (symbolP
);
3418 target
= S_GET_VALUE (symbolP
) + exp
->X_add_number
;
3419 pc
= pc_frag
->fr_address
+ pc_offset
;
3421 /* If frag has yet to be reached on this pass, assume it
3422 will move by STRETCH just as we did. If this is not so,
3423 it will be because some frag between grows, and that will
3424 force another pass. Beware zero-length frags. There
3425 should be a faster way to do this. */
3428 && sym_frag
->relax_marker
!= pc_frag
->relax_marker
3429 && S_GET_SEGMENT (symbolP
) == pc_seg
)
3434 new_offset
= target
;
3435 xtensa_operand_do_reloc (isa
, insn
->opcode
, i
, &new_offset
, pc
);
3436 if (xg_check_operand (new_offset
, insn
->opcode
, i
))
3441 /* The symbol should have a fixup associated with it. */
3450 /* Return TRUE on success. */
3453 xg_build_to_insn (TInsn
*targ
, TInsn
*insn
, BuildInstr
*bi
)
3459 targ
->debug_line
= insn
->debug_line
;
3460 targ
->loc_directive_seen
= insn
->loc_directive_seen
;
3465 targ
->opcode
= bi
->opcode
;
3466 targ
->insn_type
= ITYPE_INSN
;
3467 targ
->is_specific_opcode
= FALSE
;
3469 for (; op
!= NULL
; op
= op
->next
)
3471 int op_num
= op
->op_num
;
3472 int op_data
= op
->op_data
;
3474 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3476 if (targ
->ntok
<= op_num
)
3477 targ
->ntok
= op_num
+ 1;
3482 set_expr_const (&targ
->tok
[op_num
], op_data
);
3485 gas_assert (op_data
< insn
->ntok
);
3486 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3489 if (insn
->extra_arg
.X_op
!= O_register
)
3491 copy_expr (&targ
->tok
[op_num
], &insn
->extra_arg
);
3494 sym
= get_special_literal_symbol ();
3495 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3496 if (insn
->tok
[op_data
].X_op
== O_tlsfunc
3497 || insn
->tok
[op_data
].X_op
== O_tlsarg
)
3498 copy_expr (&targ
->extra_arg
, &insn
->tok
[op_data
]);
3501 sym
= get_special_label_symbol ();
3502 set_expr_symbol_offset (&targ
->tok
[op_num
], sym
, 0);
3504 case OP_OPERAND_HI16U
:
3505 case OP_OPERAND_LOW16U
:
3506 gas_assert (op_data
< insn
->ntok
);
3507 if (expr_is_const (&insn
->tok
[op_data
]))
3510 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3511 val
= xg_apply_userdef_op_fn (op
->typ
,
3514 targ
->tok
[op_num
].X_add_number
= val
;
3518 /* For const16 we can create relocations for these. */
3519 if (targ
->opcode
== XTENSA_UNDEFINED
3520 || (targ
->opcode
!= xtensa_const16_opcode
))
3522 gas_assert (op_data
< insn
->ntok
);
3523 /* Need to build a O_lo16 or O_hi16. */
3524 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3525 if (targ
->tok
[op_num
].X_op
== O_symbol
)
3527 if (op
->typ
== OP_OPERAND_HI16U
)
3528 targ
->tok
[op_num
].X_op
= O_hi16
;
3529 else if (op
->typ
== OP_OPERAND_LOW16U
)
3530 targ
->tok
[op_num
].X_op
= O_lo16
;
3537 /* currently handles:
3540 OP_OPERAND_F32MINUS */
3541 if (xg_has_userdef_op_fn (op
->typ
))
3543 gas_assert (op_data
< insn
->ntok
);
3544 if (expr_is_const (&insn
->tok
[op_data
]))
3547 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3548 val
= xg_apply_userdef_op_fn (op
->typ
,
3551 targ
->tok
[op_num
].X_add_number
= val
;
3554 return FALSE
; /* We cannot use a relocation for this. */
3563 case INSTR_LITERAL_DEF
:
3565 targ
->opcode
= XTENSA_UNDEFINED
;
3566 targ
->insn_type
= ITYPE_LITERAL
;
3567 targ
->is_specific_opcode
= FALSE
;
3568 for (; op
!= NULL
; op
= op
->next
)
3570 int op_num
= op
->op_num
;
3571 int op_data
= op
->op_data
;
3572 gas_assert (op
->op_num
< MAX_INSN_ARGS
);
3574 if (targ
->ntok
<= op_num
)
3575 targ
->ntok
= op_num
+ 1;
3580 gas_assert (op_data
< insn
->ntok
);
3581 /* We can only pass resolvable literals through. */
3582 if (!xg_valid_literal_expression (&insn
->tok
[op_data
]))
3584 copy_expr (&targ
->tok
[op_num
], &insn
->tok
[op_data
]);
3596 case INSTR_LABEL_DEF
:
3598 targ
->opcode
= XTENSA_UNDEFINED
;
3599 targ
->insn_type
= ITYPE_LABEL
;
3600 targ
->is_specific_opcode
= FALSE
;
3601 /* Literal with no ops is a label? */
3602 gas_assert (op
== NULL
);
3613 /* Return TRUE on success. */
3616 xg_build_to_stack (IStack
*istack
, TInsn
*insn
, BuildInstr
*bi
)
3618 for (; bi
!= NULL
; bi
= bi
->next
)
3620 TInsn
*next_insn
= istack_push_space (istack
);
3622 if (!xg_build_to_insn (next_insn
, insn
, bi
))
3629 /* Return TRUE on valid expansion. */
3632 xg_expand_to_stack (IStack
*istack
, TInsn
*insn
, int lateral_steps
)
3634 int stack_size
= istack
->ninsn
;
3635 int steps_taken
= 0;
3636 TransitionTable
*table
= xg_build_widen_table (&transition_rule_cmp
);
3639 gas_assert (insn
->insn_type
== ITYPE_INSN
);
3640 gas_assert (insn
->opcode
< table
->num_opcodes
);
3642 for (l
= table
->table
[insn
->opcode
]; l
!= NULL
; l
= l
->next
)
3644 TransitionRule
*rule
= l
->rule
;
3646 if (xg_instruction_matches_rule (insn
, rule
))
3648 if (lateral_steps
== steps_taken
)
3652 /* This is it. Expand the rule to the stack. */
3653 if (!xg_build_to_stack (istack
, insn
, rule
->to_instr
))
3656 /* Check to see if it fits. */
3657 for (i
= stack_size
; i
< istack
->ninsn
; i
++)
3659 TInsn
*tinsn
= &istack
->insn
[i
];
3661 if (tinsn
->insn_type
== ITYPE_INSN
3662 && !tinsn_has_symbolic_operands (tinsn
)
3663 && !xg_immeds_fit (tinsn
))
3665 istack
->ninsn
= stack_size
;
3678 /* Relax the assembly instruction at least "min_steps".
3679 Return the number of steps taken.
3681 For relaxation to correctly terminate, every relaxation chain must
3682 terminate in one of two ways:
3684 1. If the chain from one instruction to the next consists entirely of
3685 single instructions, then the chain *must* handle all possible
3686 immediates without failing. It must not ever fail because an
3687 immediate is out of range. The MOVI.N -> MOVI -> L32R relaxation
3688 chain is one example. L32R loads 32 bits, and there cannot be an
3689 immediate larger than 32 bits, so it satisfies this condition.
3690 Single instruction relaxation chains are as defined by
3691 xg_is_single_relaxable_instruction.
3693 2. Otherwise, the chain must end in a multi-instruction expansion: e.g.,
3694 BNEZ.N -> BNEZ -> BNEZ.W15 -> BENZ.N/J
3696 Strictly speaking, in most cases you can violate condition 1 and be OK
3697 -- in particular when the last two instructions have the same single
3698 size. But nevertheless, you should guarantee the above two conditions.
3700 We could fix this so that single-instruction expansions correctly
3701 terminate when they can't handle the range, but the error messages are
3702 worse, and it actually turns out that in every case but one (18-bit wide
3703 branches), you need a multi-instruction expansion to get the full range
3704 anyway. And because 18-bit branches are handled identically to 15-bit
3705 branches, there isn't any point in changing it. */
3708 xg_assembly_relax (IStack
*istack
,
3711 fragS
*pc_frag
, /* if pc_frag == 0, not pc-relative */
3712 offsetT pc_offset
, /* offset in fragment */
3713 int min_steps
, /* minimum conversion steps */
3714 long stretch
) /* number of bytes stretched so far */
3716 int steps_taken
= 0;
3718 /* Some of its immeds don't fit. Try to build a relaxed version.
3719 This may go through a couple of stages of single instruction
3720 transformations before we get there. */
3722 TInsn single_target
;
3724 int lateral_steps
= 0;
3725 int istack_size
= istack
->ninsn
;
3727 if (xg_symbolic_immeds_fit (insn
, pc_seg
, pc_frag
, pc_offset
, stretch
)
3728 && steps_taken
>= min_steps
)
3730 istack_push (istack
, insn
);
3733 current_insn
= *insn
;
3735 /* Walk through all of the single instruction expansions. */
3736 while (xg_is_single_relaxable_insn (¤t_insn
, &single_target
, FALSE
))
3739 if (xg_symbolic_immeds_fit (&single_target
, pc_seg
, pc_frag
, pc_offset
,
3742 if (steps_taken
>= min_steps
)
3744 istack_push (istack
, &single_target
);
3748 current_insn
= single_target
;
3751 /* Now check for a multi-instruction expansion. */
3752 while (xg_is_relaxable_insn (¤t_insn
, lateral_steps
))
3754 if (xg_symbolic_immeds_fit (¤t_insn
, pc_seg
, pc_frag
, pc_offset
,
3757 if (steps_taken
>= min_steps
)
3759 istack_push (istack
, ¤t_insn
);
3764 if (xg_expand_to_stack (istack
, ¤t_insn
, lateral_steps
))
3766 if (steps_taken
>= min_steps
)
3770 istack
->ninsn
= istack_size
;
3773 /* It's not going to work -- use the original. */
3774 istack_push (istack
, insn
);
3780 xg_finish_frag (char *last_insn
,
3781 enum xtensa_relax_statesE frag_state
,
3782 enum xtensa_relax_statesE slot0_state
,
3784 bfd_boolean is_insn
)
3786 /* Finish off this fragment so that it has at LEAST the desired
3787 max_growth. If it doesn't fit in this fragment, close this one
3788 and start a new one. In either case, return a pointer to the
3789 beginning of the growth area. */
3793 frag_grow (max_growth
);
3794 old_frag
= frag_now
;
3796 frag_now
->fr_opcode
= last_insn
;
3798 frag_now
->tc_frag_data
.is_insn
= TRUE
;
3800 frag_var (rs_machine_dependent
, max_growth
, max_growth
,
3801 frag_state
, frag_now
->fr_symbol
, frag_now
->fr_offset
, last_insn
);
3803 old_frag
->tc_frag_data
.slot_subtypes
[0] = slot0_state
;
3804 xtensa_set_frag_assembly_state (frag_now
);
3806 /* Just to make sure that we did not split it up. */
3807 gas_assert (old_frag
->fr_next
== frag_now
);
3811 /* Return TRUE if the target frag is one of the next non-empty frags. */
3814 is_next_frag_target (const fragS
*fragP
, const fragS
*target
)
3819 for (; fragP
; fragP
= fragP
->fr_next
)
3821 if (fragP
== target
)
3823 if (fragP
->fr_fix
!= 0)
3825 if (fragP
->fr_type
== rs_fill
&& fragP
->fr_offset
!= 0)
3827 if ((fragP
->fr_type
== rs_align
|| fragP
->fr_type
== rs_align_code
)
3828 && ((fragP
->fr_address
% (1 << fragP
->fr_offset
)) != 0))
3830 if (fragP
->fr_type
== rs_space
)
3838 is_branch_jmp_to_next (TInsn
*insn
, fragS
*fragP
)
3840 xtensa_isa isa
= xtensa_default_isa
;
3842 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3847 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) != 1
3848 && xtensa_opcode_is_jump (isa
, insn
->opcode
) != 1)
3851 for (i
= 0; i
< num_ops
; i
++)
3853 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1)
3859 if (target_op
== -1)
3862 if (insn
->ntok
<= target_op
)
3865 if (insn
->tok
[target_op
].X_op
!= O_symbol
)
3868 sym
= insn
->tok
[target_op
].X_add_symbol
;
3872 if (insn
->tok
[target_op
].X_add_number
!= 0)
3875 target_frag
= symbol_get_frag (sym
);
3876 if (target_frag
== NULL
)
3879 if (is_next_frag_target (fragP
->fr_next
, target_frag
)
3880 && S_GET_VALUE (sym
) == target_frag
->fr_address
)
3888 xg_add_branch_and_loop_targets (TInsn
*insn
)
3890 xtensa_isa isa
= xtensa_default_isa
;
3891 int num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
3893 if (xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3896 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3897 && insn
->tok
[i
].X_op
== O_symbol
)
3898 symbol_get_tc (insn
->tok
[i
].X_add_symbol
)->is_loop_target
= TRUE
;
3902 if (xtensa_opcode_is_branch (isa
, insn
->opcode
) == 1
3903 || xtensa_opcode_is_loop (isa
, insn
->opcode
) == 1)
3907 for (i
= 0; i
< insn
->ntok
&& i
< num_ops
; i
++)
3909 if (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) == 1
3910 && insn
->tok
[i
].X_op
== O_symbol
)
3912 symbolS
*sym
= insn
->tok
[i
].X_add_symbol
;
3913 symbol_get_tc (sym
)->is_branch_target
= TRUE
;
3914 if (S_IS_DEFINED (sym
))
3915 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
3922 /* Return FALSE if no error. */
3925 xg_build_token_insn (BuildInstr
*instr_spec
, TInsn
*old_insn
, TInsn
*new_insn
)
3930 switch (instr_spec
->typ
)
3933 new_insn
->insn_type
= ITYPE_INSN
;
3934 new_insn
->opcode
= instr_spec
->opcode
;
3936 case INSTR_LITERAL_DEF
:
3937 new_insn
->insn_type
= ITYPE_LITERAL
;
3938 new_insn
->opcode
= XTENSA_UNDEFINED
;
3940 case INSTR_LABEL_DEF
:
3943 new_insn
->is_specific_opcode
= FALSE
;
3944 new_insn
->debug_line
= old_insn
->debug_line
;
3945 new_insn
->loc_directive_seen
= old_insn
->loc_directive_seen
;
3947 for (b_op
= instr_spec
->ops
; b_op
!= NULL
; b_op
= b_op
->next
)
3950 const expressionS
*src_exp
;
3956 /* The expression must be the constant. */
3957 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3958 exp
= &new_insn
->tok
[b_op
->op_num
];
3959 set_expr_const (exp
, b_op
->op_data
);
3963 gas_assert (b_op
->op_num
< MAX_INSN_ARGS
);
3964 gas_assert (b_op
->op_data
< (unsigned) old_insn
->ntok
);
3965 src_exp
= &old_insn
->tok
[b_op
->op_data
];
3966 exp
= &new_insn
->tok
[b_op
->op_num
];
3967 copy_expr (exp
, src_exp
);
3972 as_bad (_("can't handle generation of literal/labels yet"));
3976 as_bad (_("can't handle undefined OP TYPE"));
3981 new_insn
->ntok
= num_ops
;
3986 /* Return TRUE if it was simplified. */
3989 xg_simplify_insn (TInsn
*old_insn
, TInsn
*new_insn
)
3991 TransitionRule
*rule
;
3992 BuildInstr
*insn_spec
;
3994 if (old_insn
->is_specific_opcode
|| !density_supported
)
3997 rule
= xg_instruction_match (old_insn
);
4001 insn_spec
= rule
->to_instr
;
4002 /* There should only be one. */
4003 gas_assert (insn_spec
!= NULL
);
4004 gas_assert (insn_spec
->next
== NULL
);
4005 if (insn_spec
->next
!= NULL
)
4008 xg_build_token_insn (insn_spec
, old_insn
, new_insn
);
4014 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
4015 l32i.n. (2) Check the number of operands. (3) Place the instruction
4016 tokens into the stack or relax it and place multiple
4017 instructions/literals onto the stack. Return FALSE if no error. */
4020 xg_expand_assembly_insn (IStack
*istack
, TInsn
*orig_insn
)
4024 bfd_boolean do_expand
;
4026 tinsn_init (&new_insn
);
4028 /* Narrow it if we can. xg_simplify_insn now does all the
4029 appropriate checking (e.g., for the density option). */
4030 if (xg_simplify_insn (orig_insn
, &new_insn
))
4031 orig_insn
= &new_insn
;
4033 noperands
= xtensa_opcode_num_operands (xtensa_default_isa
,
4035 if (orig_insn
->ntok
< noperands
)
4037 as_bad (_("found %d operands for '%s': Expected %d"),
4039 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4043 if (orig_insn
->ntok
> noperands
)
4044 as_warn (_("found too many (%d) operands for '%s': Expected %d"),
4046 xtensa_opcode_name (xtensa_default_isa
, orig_insn
->opcode
),
4049 /* If there are not enough operands, we will assert above. If there
4050 are too many, just cut out the extras here. */
4051 orig_insn
->ntok
= noperands
;
4053 if (tinsn_has_invalid_symbolic_operands (orig_insn
))
4056 /* Special case for extui opcode which has constraints not handled
4057 by the ordinary operand encoding checks. The number of operands
4058 and related syntax issues have already been checked. */
4059 if (orig_insn
->opcode
== xtensa_extui_opcode
)
4061 int shiftimm
= orig_insn
->tok
[2].X_add_number
;
4062 int maskimm
= orig_insn
->tok
[3].X_add_number
;
4063 if (shiftimm
+ maskimm
> 32)
4065 as_bad (_("immediate operands sum to greater than 32"));
4070 /* If the instruction will definitely need to be relaxed, it is better
4071 to expand it now for better scheduling. Decide whether to expand
4073 do_expand
= (!orig_insn
->is_specific_opcode
&& use_transform ());
4075 /* Calls should be expanded to longcalls only in the backend relaxation
4076 so that the assembly scheduler will keep the L32R/CALLX instructions
4078 if (is_direct_call_opcode (orig_insn
->opcode
))
4081 if (tinsn_has_symbolic_operands (orig_insn
))
4083 /* The values of symbolic operands are not known yet, so only expand
4084 now if an operand is "complex" (e.g., difference of symbols) and
4085 will have to be stored as a literal regardless of the value. */
4086 if (!tinsn_has_complex_operands (orig_insn
))
4089 else if (xg_immeds_fit (orig_insn
))
4093 xg_assembly_relax (istack
, orig_insn
, 0, 0, 0, 0, 0);
4095 istack_push (istack
, orig_insn
);
4101 /* Return TRUE if the section flags are marked linkonce
4102 or the name is .gnu.linkonce.*. */
4104 static int linkonce_len
= sizeof (".gnu.linkonce.") - 1;
4107 get_is_linkonce_section (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
)
4109 flagword flags
, link_once_flags
;
4111 flags
= bfd_get_section_flags (abfd
, sec
);
4112 link_once_flags
= (flags
& SEC_LINK_ONCE
);
4114 /* Flags might not be set yet. */
4115 if (!link_once_flags
4116 && strncmp (segment_name (sec
), ".gnu.linkonce.", linkonce_len
) == 0)
4117 link_once_flags
= SEC_LINK_ONCE
;
4119 return (link_once_flags
!= 0);
4124 xtensa_add_literal_sym (symbolS
*sym
)
4128 l
= XNEW (sym_list
);
4130 l
->next
= literal_syms
;
4136 xtensa_create_literal_symbol (segT sec
, fragS
*frag
)
4138 static int lit_num
= 0;
4139 static char name
[256];
4142 sprintf (name
, ".L_lit_sym%d", lit_num
);
4144 /* Create a local symbol. If it is in a linkonce section, we have to
4145 be careful to make sure that if it is used in a relocation that the
4146 symbol will be in the output file. */
4147 if (get_is_linkonce_section (stdoutput
, sec
))
4149 symbolP
= symbol_new (name
, sec
, 0, frag
);
4150 S_CLEAR_EXTERNAL (symbolP
);
4151 /* symbolP->local = 1; */
4154 symbolP
= symbol_new (name
, sec
, 0, frag
);
4156 xtensa_add_literal_sym (symbolP
);
4163 /* Currently all literals that are generated here are 32-bit L32R targets. */
4166 xg_assemble_literal (/* const */ TInsn
*insn
)
4169 symbolS
*lit_sym
= NULL
;
4170 bfd_reloc_code_real_type reloc
;
4171 bfd_boolean pcrel
= FALSE
;
4174 /* size = 4 for L32R. It could easily be larger when we move to
4175 larger constants. Add a parameter later. */
4176 offsetT litsize
= 4;
4177 offsetT litalign
= 2; /* 2^2 = 4 */
4178 expressionS saved_loc
;
4179 expressionS
* emit_val
;
4181 set_expr_symbol_offset (&saved_loc
, frag_now
->fr_symbol
, frag_now_fix ());
4183 gas_assert (insn
->insn_type
== ITYPE_LITERAL
);
4184 gas_assert (insn
->ntok
== 1); /* must be only one token here */
4186 xtensa_switch_to_literal_fragment (&state
);
4188 emit_val
= &insn
->tok
[0];
4189 if (emit_val
->X_op
== O_big
)
4191 int size
= emit_val
->X_add_number
* CHARS_PER_LITTLENUM
;
4194 /* This happens when someone writes a "movi a2, big_number". */
4195 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
4196 _("invalid immediate"));
4197 xtensa_restore_emit_state (&state
);
4202 /* Force a 4-byte align here. Note that this opens a new frag, so all
4203 literals done with this function have a frag to themselves. That's
4204 important for the way text section literals work. */
4205 frag_align (litalign
, 0, 0);
4206 record_alignment (now_seg
, litalign
);
4208 switch (emit_val
->X_op
)
4218 p
= frag_more (litsize
);
4219 xtensa_set_frag_assembly_state (frag_now
);
4220 reloc
= map_operator_to_reloc (emit_val
->X_op
, TRUE
);
4221 if (emit_val
->X_add_symbol
)
4222 emit_val
->X_op
= O_symbol
;
4224 emit_val
->X_op
= O_constant
;
4225 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
4226 litsize
, emit_val
, pcrel
, reloc
);
4230 emit_expr (emit_val
, litsize
);
4234 gas_assert (frag_now
->tc_frag_data
.literal_frag
== NULL
);
4235 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4236 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4237 lit_sym
= frag_now
->fr_symbol
;
4240 xtensa_restore_emit_state (&state
);
4246 xg_assemble_literal_space (/* const */ int size
, int slot
)
4249 /* We might have to do something about this alignment. It only
4250 takes effect if something is placed here. */
4251 offsetT litalign
= 2; /* 2^2 = 4 */
4252 fragS
*lit_saved_frag
;
4254 gas_assert (size
% 4 == 0);
4256 xtensa_switch_to_literal_fragment (&state
);
4258 /* Force a 4-byte align here. */
4259 frag_align (litalign
, 0, 0);
4260 record_alignment (now_seg
, litalign
);
4264 lit_saved_frag
= frag_now
;
4265 frag_now
->tc_frag_data
.literal_frag
= get_literal_pool_location (now_seg
);
4266 frag_now
->fr_symbol
= xtensa_create_literal_symbol (now_seg
, frag_now
);
4267 xg_finish_frag (0, RELAX_LITERAL
, 0, size
, FALSE
);
4270 xtensa_restore_emit_state (&state
);
4271 frag_now
->tc_frag_data
.literal_frags
[slot
] = lit_saved_frag
;
4275 /* Put in a fixup record based on the opcode.
4276 Return TRUE on success. */
4279 xg_add_opcode_fix (TInsn
*tinsn
,
4287 xtensa_opcode opcode
= tinsn
->opcode
;
4288 bfd_reloc_code_real_type reloc
;
4289 reloc_howto_type
*howto
;
4293 reloc
= BFD_RELOC_NONE
;
4295 /* First try the special cases for "alternate" relocs. */
4296 if (opcode
== xtensa_l32r_opcode
)
4298 if (fragP
->tc_frag_data
.use_absolute_literals
)
4299 reloc
= encode_alt_reloc (slot
);
4301 else if (opcode
== xtensa_const16_opcode
)
4303 if (exp
->X_op
== O_lo16
)
4305 reloc
= encode_reloc (slot
);
4306 exp
->X_op
= O_symbol
;
4308 else if (exp
->X_op
== O_hi16
)
4310 reloc
= encode_alt_reloc (slot
);
4311 exp
->X_op
= O_symbol
;
4315 if (opnum
!= get_relaxable_immed (opcode
))
4317 as_bad (_("invalid relocation for operand %i of '%s'"),
4318 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4322 /* Handle erroneous "@h" and "@l" expressions here before they propagate
4323 into the symbol table where the generic portions of the assembler
4324 won't know what to do with them. */
4325 if (exp
->X_op
== O_lo16
|| exp
->X_op
== O_hi16
)
4327 as_bad (_("invalid expression for operand %i of '%s'"),
4328 opnum
+ 1, xtensa_opcode_name (xtensa_default_isa
, opcode
));
4332 /* Next try the generic relocs. */
4333 if (reloc
== BFD_RELOC_NONE
)
4334 reloc
= encode_reloc (slot
);
4335 if (reloc
== BFD_RELOC_NONE
)
4337 as_bad (_("invalid relocation in instruction slot %i"), slot
);
4341 howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
4344 as_bad (_("undefined symbol for opcode \"%s\""),
4345 xtensa_opcode_name (xtensa_default_isa
, opcode
));
4349 fmt_length
= xtensa_format_length (xtensa_default_isa
, fmt
);
4350 the_fix
= fix_new_exp (fragP
, offset
, fmt_length
, exp
,
4351 howto
->pc_relative
, reloc
);
4352 the_fix
->fx_no_overflow
= 1;
4353 the_fix
->tc_fix_data
.X_add_symbol
= exp
->X_add_symbol
;
4354 the_fix
->tc_fix_data
.X_add_number
= exp
->X_add_number
;
4355 the_fix
->tc_fix_data
.slot
= slot
;
4362 xg_emit_insn_to_buf (TInsn
*tinsn
,
4366 bfd_boolean build_fix
)
4368 static xtensa_insnbuf insnbuf
= NULL
;
4369 bfd_boolean has_symbolic_immed
= FALSE
;
4370 bfd_boolean ok
= TRUE
;
4373 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4375 has_symbolic_immed
= tinsn_to_insnbuf (tinsn
, insnbuf
);
4376 if (has_symbolic_immed
&& build_fix
)
4379 xtensa_format fmt
= xg_get_single_format (tinsn
->opcode
);
4380 int slot
= xg_get_single_slot (tinsn
->opcode
);
4381 int opnum
= get_relaxable_immed (tinsn
->opcode
);
4382 expressionS
*exp
= &tinsn
->tok
[opnum
];
4384 if (!xg_add_opcode_fix (tinsn
, opnum
, fmt
, slot
, exp
, fragP
, offset
))
4387 fragP
->tc_frag_data
.is_insn
= TRUE
;
4388 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4389 (unsigned char *) buf
, 0);
4395 xg_resolve_literals (TInsn
*insn
, symbolS
*lit_sym
)
4397 symbolS
*sym
= get_special_literal_symbol ();
4401 gas_assert (insn
->insn_type
== ITYPE_INSN
);
4402 for (i
= 0; i
< insn
->ntok
; i
++)
4403 if (insn
->tok
[i
].X_add_symbol
== sym
)
4404 insn
->tok
[i
].X_add_symbol
= lit_sym
;
4410 xg_resolve_labels (TInsn
*insn
, symbolS
*label_sym
)
4412 symbolS
*sym
= get_special_label_symbol ();
4414 for (i
= 0; i
< insn
->ntok
; i
++)
4415 if (insn
->tok
[i
].X_add_symbol
== sym
)
4416 insn
->tok
[i
].X_add_symbol
= label_sym
;
4421 /* Return TRUE if the instruction can write to the specified
4422 integer register. */
4425 is_register_writer (const TInsn
*insn
, const char *regset
, int regnum
)
4429 xtensa_isa isa
= xtensa_default_isa
;
4431 num_ops
= xtensa_opcode_num_operands (isa
, insn
->opcode
);
4433 for (i
= 0; i
< num_ops
; i
++)
4436 inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
4437 if ((inout
== 'o' || inout
== 'm')
4438 && xtensa_operand_is_register (isa
, insn
->opcode
, i
) == 1)
4440 xtensa_regfile opnd_rf
=
4441 xtensa_operand_regfile (isa
, insn
->opcode
, i
);
4442 if (!strcmp (xtensa_regfile_shortname (isa
, opnd_rf
), regset
))
4444 if ((insn
->tok
[i
].X_op
== O_register
)
4445 && (insn
->tok
[i
].X_add_number
== regnum
))
4455 is_bad_loopend_opcode (const TInsn
*tinsn
)
4457 xtensa_opcode opcode
= tinsn
->opcode
;
4459 if (opcode
== XTENSA_UNDEFINED
)
4462 if (opcode
== xtensa_call0_opcode
4463 || opcode
== xtensa_callx0_opcode
4464 || opcode
== xtensa_call4_opcode
4465 || opcode
== xtensa_callx4_opcode
4466 || opcode
== xtensa_call8_opcode
4467 || opcode
== xtensa_callx8_opcode
4468 || opcode
== xtensa_call12_opcode
4469 || opcode
== xtensa_callx12_opcode
4470 || opcode
== xtensa_isync_opcode
4471 || opcode
== xtensa_ret_opcode
4472 || opcode
== xtensa_ret_n_opcode
4473 || opcode
== xtensa_retw_opcode
4474 || opcode
== xtensa_retw_n_opcode
4475 || opcode
== xtensa_waiti_opcode
4476 || opcode
== xtensa_rsr_lcount_opcode
)
4483 /* Labels that begin with ".Ln" or ".LM" are unaligned.
4484 This allows the debugger to add unaligned labels.
4485 Also, the assembler generates stabs labels that need
4486 not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */
4489 is_unaligned_label (symbolS
*sym
)
4491 const char *name
= S_GET_NAME (sym
);
4492 static size_t fake_size
= 0;
4496 && name
[1] == 'L' && (name
[2] == 'n' || name
[2] == 'M'))
4499 /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */
4501 fake_size
= strlen (FAKE_LABEL_NAME
);
4504 && strncmp (FAKE_LABEL_NAME
, name
, fake_size
) == 0
4505 && (name
[fake_size
] == 'F'
4506 || name
[fake_size
] == 'L'
4507 || (name
[fake_size
] == 'e'
4508 && strncmp ("endfunc", name
+fake_size
, 7) == 0)))
4516 next_non_empty_frag (const fragS
*fragP
)
4518 fragS
*next_fragP
= fragP
->fr_next
;
4520 /* Sometimes an empty will end up here due storage allocation issues.
4521 So we have to skip until we find something legit. */
4522 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4523 next_fragP
= next_fragP
->fr_next
;
4525 if (next_fragP
== NULL
|| next_fragP
->fr_fix
== 0)
4533 next_frag_opcode_is_loop (const fragS
*fragP
, xtensa_opcode
*opcode
)
4535 xtensa_opcode out_opcode
;
4536 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4538 if (next_fragP
== NULL
)
4541 out_opcode
= get_opcode_from_buf (next_fragP
->fr_literal
, 0);
4542 if (xtensa_opcode_is_loop (xtensa_default_isa
, out_opcode
) == 1)
4544 *opcode
= out_opcode
;
4552 frag_format_size (const fragS
*fragP
)
4554 static xtensa_insnbuf insnbuf
= NULL
;
4555 xtensa_isa isa
= xtensa_default_isa
;
4560 insnbuf
= xtensa_insnbuf_alloc (isa
);
4563 return XTENSA_UNDEFINED
;
4565 xtensa_insnbuf_from_chars (isa
, insnbuf
,
4566 (unsigned char *) fragP
->fr_literal
, 0);
4568 fmt
= xtensa_format_decode (isa
, insnbuf
);
4569 if (fmt
== XTENSA_UNDEFINED
)
4570 return XTENSA_UNDEFINED
;
4571 fmt_size
= xtensa_format_length (isa
, fmt
);
4573 /* If the next format won't be changing due to relaxation, just
4574 return the length of the first format. */
4575 if (fragP
->fr_opcode
!= fragP
->fr_literal
)
4578 /* If during relaxation we have to pull an instruction out of a
4579 multi-slot instruction, we will return the more conservative
4580 number. This works because alignment on bigger instructions
4581 is more restrictive than alignment on smaller instructions.
4582 This is more conservative than we would like, but it happens
4585 if (xtensa_format_num_slots (xtensa_default_isa
, fmt
) > 1)
4588 /* If we aren't doing one of our own relaxations or it isn't
4589 slot-based, then the insn size won't change. */
4590 if (fragP
->fr_type
!= rs_machine_dependent
)
4592 if (fragP
->fr_subtype
!= RELAX_SLOTS
)
4595 /* If an instruction is about to grow, return the longer size. */
4596 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP1
4597 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP2
4598 || fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED_STEP3
)
4600 /* For most frags at RELAX_IMMED_STEPX, with X > 0, the first
4601 instruction in the relaxed version is of length 3. (The case
4602 where we have to pull the instruction out of a FLIX bundle
4603 is handled conservatively above.) However, frags with opcodes
4604 that are expanding to wide branches end up having formats that
4605 are not determinable by the RELAX_IMMED_STEPX enumeration, and
4606 we can't tell directly what format the relaxer picked. This
4607 is a wart in the design of the relaxer that should someday be
4608 fixed, but would require major changes, or at least should
4609 be accompanied by major changes to make use of that data.
4611 In any event, we can tell that we are expanding from a single-slot
4612 format to a wider one with the logic below. */
4615 int relaxed_size
= fmt_size
+ fragP
->tc_frag_data
.text_expansion
[0];
4617 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
4619 if (relaxed_size
== xtensa_format_length (isa
, i
))
4620 return relaxed_size
;
4626 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
4627 return 2 + fragP
->tc_frag_data
.text_expansion
[0];
4634 next_frag_format_size (const fragS
*fragP
)
4636 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
4637 return frag_format_size (next_fragP
);
4641 /* In early Xtensa Processors, for reasons that are unclear, the ISA
4642 required two-byte instructions to be treated as three-byte instructions
4643 for loop instruction alignment. This restriction was removed beginning
4644 with Xtensa LX. Now the only requirement on loop instruction alignment
4645 is that the first instruction of the loop must appear at an address that
4646 does not cross a fetch boundary. */
4649 get_loop_align_size (int insn_size
)
4651 if (insn_size
== XTENSA_UNDEFINED
)
4652 return xtensa_fetch_width
;
4654 if (enforce_three_byte_loop_align
&& insn_size
== 2)
4661 /* If the next legit fragment is an end-of-loop marker,
4662 switch its state so it will instantiate a NOP. */
4665 update_next_frag_state (fragS
*fragP
)
4667 fragS
*next_fragP
= fragP
->fr_next
;
4668 fragS
*new_target
= NULL
;
4672 /* We are guaranteed there will be one of these... */
4673 while (!(next_fragP
->fr_type
== rs_machine_dependent
4674 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4675 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
)))
4676 next_fragP
= next_fragP
->fr_next
;
4678 gas_assert (next_fragP
->fr_type
== rs_machine_dependent
4679 && (next_fragP
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
4680 || next_fragP
->fr_subtype
== RELAX_UNREACHABLE
));
4682 /* ...and one of these. */
4683 new_target
= next_fragP
->fr_next
;
4684 while (!(new_target
->fr_type
== rs_machine_dependent
4685 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4686 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
)))
4687 new_target
= new_target
->fr_next
;
4689 gas_assert (new_target
->fr_type
== rs_machine_dependent
4690 && (new_target
->fr_subtype
== RELAX_MAYBE_DESIRE_ALIGN
4691 || new_target
->fr_subtype
== RELAX_DESIRE_ALIGN
));
4694 while (next_fragP
&& next_fragP
->fr_fix
== 0)
4696 if (next_fragP
->fr_type
== rs_machine_dependent
4697 && next_fragP
->fr_subtype
== RELAX_LOOP_END
)
4699 next_fragP
->fr_subtype
= RELAX_LOOP_END_ADD_NOP
;
4703 next_fragP
= next_fragP
->fr_next
;
4709 next_frag_is_branch_target (const fragS
*fragP
)
4711 /* Sometimes an empty will end up here due to storage allocation issues,
4712 so we have to skip until we find something legit. */
4713 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4715 if (fragP
->tc_frag_data
.is_branch_target
)
4717 if (fragP
->fr_fix
!= 0)
4725 next_frag_is_loop_target (const fragS
*fragP
)
4727 /* Sometimes an empty will end up here due storage allocation issues.
4728 So we have to skip until we find something legit. */
4729 for (fragP
= fragP
->fr_next
; fragP
; fragP
= fragP
->fr_next
)
4731 if (fragP
->tc_frag_data
.is_loop_target
)
4733 if (fragP
->fr_fix
!= 0)
4740 /* As specified in the relaxation table, when a loop instruction is
4741 relaxed, there are 24 bytes between the loop instruction itself and
4742 the first instruction in the loop. */
4744 #define RELAXED_LOOP_INSN_BYTES 24
4747 next_frag_pre_opcode_bytes (const fragS
*fragp
)
4749 const fragS
*next_fragp
= fragp
->fr_next
;
4750 xtensa_opcode next_opcode
;
4752 if (!next_frag_opcode_is_loop (fragp
, &next_opcode
))
4755 /* Sometimes an empty will end up here due to storage allocation issues,
4756 so we have to skip until we find something legit. */
4757 while (next_fragp
->fr_fix
== 0)
4758 next_fragp
= next_fragp
->fr_next
;
4760 if (next_fragp
->fr_type
!= rs_machine_dependent
)
4763 /* There is some implicit knowledge encoded in here.
4764 The LOOP instructions that are NOT RELAX_IMMED have
4765 been relaxed. Note that we can assume that the LOOP
4766 instruction is in slot 0 because loops aren't bundleable. */
4767 if (next_fragp
->tc_frag_data
.slot_subtypes
[0] > RELAX_IMMED
)
4768 return get_expanded_loop_offset (next_opcode
) + RELAXED_LOOP_INSN_BYTES
;
4774 /* Mark a location where we can later insert literal frags. Update
4775 the section's literal_pool_loc, so subsequent literals can be
4776 placed nearest to their use. */
4779 xtensa_mark_literal_pool_location (void)
4781 /* Any labels pointing to the current location need
4782 to be adjusted to after the literal pool. */
4784 fragS
*pool_location
;
4786 if (use_literal_section
)
4789 /* We stash info in these frags so we can later move the literal's
4790 fixes into this frchain's fix list. */
4791 pool_location
= frag_now
;
4792 frag_now
->tc_frag_data
.lit_frchain
= frchain_now
;
4793 frag_now
->tc_frag_data
.literal_frag
= frag_now
;
4794 /* Just record this frag. */
4795 xtensa_maybe_create_literal_pool_frag (FALSE
, FALSE
);
4796 frag_variant (rs_machine_dependent
, 0, 0,
4797 RELAX_LITERAL_POOL_BEGIN
, NULL
, 0, NULL
);
4798 xtensa_set_frag_assembly_state (frag_now
);
4799 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
4800 frag_variant (rs_machine_dependent
, 0, 0,
4801 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
4802 xtensa_set_frag_assembly_state (frag_now
);
4804 /* Now put a frag into the literal pool that points to this location. */
4805 set_literal_pool_location (now_seg
, pool_location
);
4806 xtensa_switch_to_non_abs_literal_fragment (&s
);
4807 frag_align (2, 0, 0);
4808 record_alignment (now_seg
, 2);
4810 /* Close whatever frag is there. */
4811 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4812 xtensa_set_frag_assembly_state (frag_now
);
4813 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
4814 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
4815 xtensa_restore_emit_state (&s
);
4816 xtensa_set_frag_assembly_state (frag_now
);
4820 /* Build a nop of the correct size into tinsn. */
4823 build_nop (TInsn
*tinsn
, int size
)
4829 tinsn
->opcode
= xtensa_nop_n_opcode
;
4831 if (tinsn
->opcode
== XTENSA_UNDEFINED
)
4832 as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
4836 if (xtensa_nop_opcode
== XTENSA_UNDEFINED
)
4838 tinsn
->opcode
= xtensa_or_opcode
;
4839 set_expr_const (&tinsn
->tok
[0], 1);
4840 set_expr_const (&tinsn
->tok
[1], 1);
4841 set_expr_const (&tinsn
->tok
[2], 1);
4845 tinsn
->opcode
= xtensa_nop_opcode
;
4847 gas_assert (tinsn
->opcode
!= XTENSA_UNDEFINED
);
4852 /* Assemble a NOP of the requested size in the buffer. User must have
4853 allocated "buf" with at least "size" bytes. */
4856 assemble_nop (int size
, char *buf
)
4858 static xtensa_insnbuf insnbuf
= NULL
;
4861 build_nop (&tinsn
, size
);
4864 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
4866 tinsn_to_insnbuf (&tinsn
, insnbuf
);
4867 xtensa_insnbuf_to_chars (xtensa_default_isa
, insnbuf
,
4868 (unsigned char *) buf
, 0);
4872 /* Return the number of bytes for the offset of the expanded loop
4873 instruction. This should be incorporated into the relaxation
4874 specification but is hard-coded here. This is used to auto-align
4875 the loop instruction. It is invalid to call this function if the
4876 configuration does not have loops or if the opcode is not a loop
4880 get_expanded_loop_offset (xtensa_opcode opcode
)
4882 /* This is the OFFSET of the loop instruction in the expanded loop.
4883 This MUST correspond directly to the specification of the loop
4884 expansion. It will be validated on fragment conversion. */
4885 gas_assert (opcode
!= XTENSA_UNDEFINED
);
4886 if (opcode
== xtensa_loop_opcode
)
4888 if (opcode
== xtensa_loopnez_opcode
)
4890 if (opcode
== xtensa_loopgtz_opcode
)
4892 as_fatal (_("get_expanded_loop_offset: invalid opcode"));
4898 get_literal_pool_location (segT seg
)
4900 struct litpool_seg
*lps
= litpool_seg_list
.next
;
4901 struct litpool_frag
*lpf
;
4902 for ( ; lps
&& lps
->seg
->id
!= seg
->id
; lps
= lps
->next
)
4906 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4907 { /* Skip "candidates" for now. */
4908 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
&&
4912 /* Must convert a lower-priority pool. */
4913 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4915 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
4918 /* Still no match -- try for a low priority pool. */
4919 for (lpf
= lps
->frag_list
.prev
; lpf
->fragP
; lpf
= lpf
->prev
)
4921 if (lpf
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
4925 return seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
;
4930 set_literal_pool_location (segT seg
, fragS
*literal_pool_loc
)
4932 seg_info (seg
)->tc_segment_info_data
.literal_pool_loc
= literal_pool_loc
;
4936 /* Set frag assembly state should be called when a new frag is
4937 opened and after a frag has been closed. */
4940 xtensa_set_frag_assembly_state (fragS
*fragP
)
4942 if (!density_supported
)
4943 fragP
->tc_frag_data
.is_no_density
= TRUE
;
4945 /* This function is called from subsegs_finish, which is called
4946 after xtensa_end, so we can't use "use_transform" or
4947 "use_schedule" here. */
4948 if (!directive_state
[directive_transform
])
4949 fragP
->tc_frag_data
.is_no_transform
= TRUE
;
4950 if (directive_state
[directive_longcalls
])
4951 fragP
->tc_frag_data
.use_longcalls
= TRUE
;
4952 fragP
->tc_frag_data
.use_absolute_literals
=
4953 directive_state
[directive_absolute_literals
];
4954 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
4959 relaxable_section (asection
*sec
)
4961 return ((sec
->flags
& SEC_DEBUGGING
) == 0
4962 && strcmp (sec
->name
, ".eh_frame") != 0);
4967 xtensa_mark_frags_for_org (void)
4971 /* Walk over each fragment of all of the current segments. If we find
4972 a .org frag in any of the segments, mark all frags prior to it as
4973 "no transform", which will prevent linker optimizations from messing
4974 up the .org distance. This should be done after
4975 xtensa_find_unmarked_state_frags, because we don't want to worry here
4976 about that function trashing the data we save here. */
4978 for (seclist
= &stdoutput
->sections
;
4979 seclist
&& *seclist
;
4980 seclist
= &(*seclist
)->next
)
4982 segT sec
= *seclist
;
4983 segment_info_type
*seginfo
;
4986 flags
= bfd_get_section_flags (stdoutput
, sec
);
4987 if (flags
& SEC_DEBUGGING
)
4989 if (!(flags
& SEC_ALLOC
))
4992 seginfo
= seg_info (sec
);
4993 if (seginfo
&& seginfo
->frchainP
)
4995 fragS
*last_fragP
= seginfo
->frchainP
->frch_root
;
4996 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
4997 fragP
= fragP
->fr_next
)
4999 /* cvt_frag_to_fill has changed the fr_type of org frags to
5000 rs_fill, so use the value as cached in rs_subtype here. */
5001 if (fragP
->fr_subtype
== RELAX_ORG
)
5003 while (last_fragP
!= fragP
->fr_next
)
5005 last_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
5006 last_fragP
= last_fragP
->fr_next
;
5016 xtensa_find_unmarked_state_frags (void)
5020 /* Walk over each fragment of all of the current segments. For each
5021 unmarked fragment, mark it with the same info as the previous
5023 for (seclist
= &stdoutput
->sections
;
5024 seclist
&& *seclist
;
5025 seclist
= &(*seclist
)->next
)
5027 segT sec
= *seclist
;
5028 segment_info_type
*seginfo
;
5031 flags
= bfd_get_section_flags (stdoutput
, sec
);
5032 if (flags
& SEC_DEBUGGING
)
5034 if (!(flags
& SEC_ALLOC
))
5037 seginfo
= seg_info (sec
);
5038 if (seginfo
&& seginfo
->frchainP
)
5040 fragS
*last_fragP
= 0;
5041 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
;
5042 fragP
= fragP
->fr_next
)
5044 if (fragP
->fr_fix
!= 0
5045 && !fragP
->tc_frag_data
.is_assembly_state_set
)
5047 if (last_fragP
== 0)
5049 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
5050 _("assembly state not set for first frag in section %s"),
5055 fragP
->tc_frag_data
.is_assembly_state_set
= TRUE
;
5056 fragP
->tc_frag_data
.is_no_density
=
5057 last_fragP
->tc_frag_data
.is_no_density
;
5058 fragP
->tc_frag_data
.is_no_transform
=
5059 last_fragP
->tc_frag_data
.is_no_transform
;
5060 fragP
->tc_frag_data
.use_longcalls
=
5061 last_fragP
->tc_frag_data
.use_longcalls
;
5062 fragP
->tc_frag_data
.use_absolute_literals
=
5063 last_fragP
->tc_frag_data
.use_absolute_literals
;
5066 if (fragP
->tc_frag_data
.is_assembly_state_set
)
5075 xtensa_find_unaligned_branch_targets (bfd
*abfd ATTRIBUTE_UNUSED
,
5077 void *unused ATTRIBUTE_UNUSED
)
5079 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5080 segment_info_type
*seginfo
= seg_info (sec
);
5081 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5083 if (flags
& SEC_CODE
)
5085 xtensa_isa isa
= xtensa_default_isa
;
5086 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5087 while (frag
!= NULL
)
5089 if (frag
->tc_frag_data
.is_branch_target
)
5092 addressT branch_align
, frag_addr
;
5095 xtensa_insnbuf_from_chars
5096 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5097 fmt
= xtensa_format_decode (isa
, insnbuf
);
5098 op_size
= xtensa_format_length (isa
, fmt
);
5099 branch_align
= 1 << branch_align_power (sec
);
5100 frag_addr
= frag
->fr_address
% branch_align
;
5101 if (frag_addr
+ op_size
> branch_align
)
5102 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5103 _("unaligned branch target: %d bytes at 0x%lx"),
5104 op_size
, (long) frag
->fr_address
);
5106 frag
= frag
->fr_next
;
5108 xtensa_insnbuf_free (isa
, insnbuf
);
5114 xtensa_find_unaligned_loops (bfd
*abfd ATTRIBUTE_UNUSED
,
5116 void *unused ATTRIBUTE_UNUSED
)
5118 flagword flags
= bfd_get_section_flags (abfd
, sec
);
5119 segment_info_type
*seginfo
= seg_info (sec
);
5120 fragS
*frag
= seginfo
->frchainP
->frch_root
;
5121 xtensa_isa isa
= xtensa_default_isa
;
5123 if (flags
& SEC_CODE
)
5125 xtensa_insnbuf insnbuf
= xtensa_insnbuf_alloc (isa
);
5126 while (frag
!= NULL
)
5128 if (frag
->tc_frag_data
.is_first_loop_insn
)
5134 if (frag
->fr_fix
== 0)
5135 frag
= next_non_empty_frag (frag
);
5139 xtensa_insnbuf_from_chars
5140 (isa
, insnbuf
, (unsigned char *) frag
->fr_literal
, 0);
5141 fmt
= xtensa_format_decode (isa
, insnbuf
);
5142 op_size
= xtensa_format_length (isa
, fmt
);
5143 frag_addr
= frag
->fr_address
% xtensa_fetch_width
;
5145 if (frag_addr
+ op_size
> xtensa_fetch_width
)
5146 as_warn_where (frag
->fr_file
, frag
->fr_line
,
5147 _("unaligned loop: %d bytes at 0x%lx"),
5148 op_size
, (long) frag
->fr_address
);
5151 frag
= frag
->fr_next
;
5153 xtensa_insnbuf_free (isa
, insnbuf
);
5159 xg_apply_fix_value (fixS
*fixP
, valueT val
)
5161 xtensa_isa isa
= xtensa_default_isa
;
5162 static xtensa_insnbuf insnbuf
= NULL
;
5163 static xtensa_insnbuf slotbuf
= NULL
;
5166 bfd_boolean alt_reloc
;
5167 xtensa_opcode opcode
;
5168 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5170 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
)
5172 as_fatal (_("unexpected fix"));
5176 insnbuf
= xtensa_insnbuf_alloc (isa
);
5177 slotbuf
= xtensa_insnbuf_alloc (isa
);
5180 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5181 fmt
= xtensa_format_decode (isa
, insnbuf
);
5182 if (fmt
== XTENSA_UNDEFINED
)
5183 as_fatal (_("undecodable fix"));
5184 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5185 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5186 if (opcode
== XTENSA_UNDEFINED
)
5187 as_fatal (_("undecodable fix"));
5189 /* CONST16 immediates are not PC-relative, despite the fact that we
5190 reuse the normal PC-relative operand relocations for the low part
5191 of a CONST16 operand. */
5192 if (opcode
== xtensa_const16_opcode
)
5195 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
,
5196 get_relaxable_immed (opcode
), val
,
5197 fixP
->fx_file
, fixP
->fx_line
);
5199 xtensa_format_set_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5200 xtensa_insnbuf_to_chars (isa
, insnbuf
, (unsigned char *) fixpos
, 0);
5206 /* External Functions and Other GAS Hooks. */
5209 xtensa_target_format (void)
5211 return (target_big_endian
? "elf32-xtensa-be" : "elf32-xtensa-le");
5216 xtensa_file_arch_init (bfd
*abfd
)
5218 bfd_set_private_flags (abfd
, 0x100 | 0x200);
5223 md_number_to_chars (char *buf
, valueT val
, int n
)
5225 if (target_big_endian
)
5226 number_to_chars_bigendian (buf
, val
, n
);
5228 number_to_chars_littleendian (buf
, val
, n
);
5232 /* This function is called once, at assembler startup time. It should
5233 set up all the tables, etc. that the MD part of the assembler will
5239 segT current_section
= now_seg
;
5240 int current_subsec
= now_subseg
;
5244 xtensa_default_isa
= xtensa_isa_init (0, 0);
5245 isa
= xtensa_default_isa
;
5249 /* Set up the literal sections. */
5250 memset (&default_lit_sections
, 0, sizeof (default_lit_sections
));
5252 subseg_set (current_section
, current_subsec
);
5254 xtensa_addi_opcode
= xtensa_opcode_lookup (isa
, "addi");
5255 xtensa_addmi_opcode
= xtensa_opcode_lookup (isa
, "addmi");
5256 xtensa_call0_opcode
= xtensa_opcode_lookup (isa
, "call0");
5257 xtensa_call4_opcode
= xtensa_opcode_lookup (isa
, "call4");
5258 xtensa_call8_opcode
= xtensa_opcode_lookup (isa
, "call8");
5259 xtensa_call12_opcode
= xtensa_opcode_lookup (isa
, "call12");
5260 xtensa_callx0_opcode
= xtensa_opcode_lookup (isa
, "callx0");
5261 xtensa_callx4_opcode
= xtensa_opcode_lookup (isa
, "callx4");
5262 xtensa_callx8_opcode
= xtensa_opcode_lookup (isa
, "callx8");
5263 xtensa_callx12_opcode
= xtensa_opcode_lookup (isa
, "callx12");
5264 xtensa_const16_opcode
= xtensa_opcode_lookup (isa
, "const16");
5265 xtensa_entry_opcode
= xtensa_opcode_lookup (isa
, "entry");
5266 xtensa_extui_opcode
= xtensa_opcode_lookup (isa
, "extui");
5267 xtensa_movi_opcode
= xtensa_opcode_lookup (isa
, "movi");
5268 xtensa_movi_n_opcode
= xtensa_opcode_lookup (isa
, "movi.n");
5269 xtensa_isync_opcode
= xtensa_opcode_lookup (isa
, "isync");
5270 xtensa_j_opcode
= xtensa_opcode_lookup (isa
, "j");
5271 xtensa_jx_opcode
= xtensa_opcode_lookup (isa
, "jx");
5272 xtensa_l32r_opcode
= xtensa_opcode_lookup (isa
, "l32r");
5273 xtensa_loop_opcode
= xtensa_opcode_lookup (isa
, "loop");
5274 xtensa_loopnez_opcode
= xtensa_opcode_lookup (isa
, "loopnez");
5275 xtensa_loopgtz_opcode
= xtensa_opcode_lookup (isa
, "loopgtz");
5276 xtensa_nop_opcode
= xtensa_opcode_lookup (isa
, "nop");
5277 xtensa_nop_n_opcode
= xtensa_opcode_lookup (isa
, "nop.n");
5278 xtensa_or_opcode
= xtensa_opcode_lookup (isa
, "or");
5279 xtensa_ret_opcode
= xtensa_opcode_lookup (isa
, "ret");
5280 xtensa_ret_n_opcode
= xtensa_opcode_lookup (isa
, "ret.n");
5281 xtensa_retw_opcode
= xtensa_opcode_lookup (isa
, "retw");
5282 xtensa_retw_n_opcode
= xtensa_opcode_lookup (isa
, "retw.n");
5283 xtensa_rsr_lcount_opcode
= xtensa_opcode_lookup (isa
, "rsr.lcount");
5284 xtensa_waiti_opcode
= xtensa_opcode_lookup (isa
, "waiti");
5286 for (i
= 0; i
< xtensa_isa_num_formats (isa
); i
++)
5288 int format_slots
= xtensa_format_num_slots (isa
, i
);
5289 if (format_slots
> config_max_slots
)
5290 config_max_slots
= format_slots
;
5293 xg_init_vinsn (&cur_vinsn
);
5295 xtensa_num_pipe_stages
= xtensa_isa_num_pipe_stages (isa
);
5297 init_op_placement_info_table ();
5299 /* Set up the assembly state. */
5300 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5301 xtensa_set_frag_assembly_state (frag_now
);
5305 /* TC_INIT_FIX_DATA hook */
5308 xtensa_init_fix_data (fixS
*x
)
5310 x
->tc_fix_data
.slot
= 0;
5311 x
->tc_fix_data
.X_add_symbol
= NULL
;
5312 x
->tc_fix_data
.X_add_number
= 0;
5316 /* tc_frob_label hook */
5319 xtensa_frob_label (symbolS
*sym
)
5323 if (cur_vinsn
.inside_bundle
)
5325 as_bad (_("labels are not valid inside bundles"));
5329 freq
= get_subseg_target_freq (now_seg
, now_subseg
);
5331 /* Since the label was already attached to a frag associated with the
5332 previous basic block, it now needs to be reset to the current frag. */
5333 symbol_set_frag (sym
, frag_now
);
5334 S_SET_VALUE (sym
, (valueT
) frag_now_fix ());
5336 if (generating_literals
)
5337 xtensa_add_literal_sym (sym
);
5339 xtensa_add_insn_label (sym
);
5341 if (symbol_get_tc (sym
)->is_loop_target
)
5343 if ((get_last_insn_flags (now_seg
, now_subseg
)
5344 & FLAG_IS_BAD_LOOPEND
) != 0)
5345 as_bad (_("invalid last instruction for a zero-overhead loop"));
5347 xtensa_set_frag_assembly_state (frag_now
);
5348 frag_var (rs_machine_dependent
, 4, 4, RELAX_LOOP_END
,
5349 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5351 xtensa_set_frag_assembly_state (frag_now
);
5352 xtensa_move_labels (frag_now
, 0);
5355 /* No target aligning in the absolute section. */
5356 if (now_seg
!= absolute_section
5357 && !is_unaligned_label (sym
)
5358 && !generating_literals
)
5360 xtensa_set_frag_assembly_state (frag_now
);
5362 if (do_align_targets ())
5363 frag_var (rs_machine_dependent
, 0, (int) freq
,
5364 RELAX_DESIRE_ALIGN_IF_TARGET
, frag_now
->fr_symbol
,
5365 frag_now
->fr_offset
, NULL
);
5367 frag_var (rs_fill
, 0, 0, frag_now
->fr_subtype
,
5368 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
5369 xtensa_set_frag_assembly_state (frag_now
);
5370 xtensa_move_labels (frag_now
, 0);
5373 /* We need to mark the following properties even if we aren't aligning. */
5375 /* If the label is already known to be a branch target, i.e., a
5376 forward branch, mark the frag accordingly. Backward branches
5377 are handled by xg_add_branch_and_loop_targets. */
5378 if (symbol_get_tc (sym
)->is_branch_target
)
5379 symbol_get_frag (sym
)->tc_frag_data
.is_branch_target
= TRUE
;
5381 /* Loops only go forward, so they can be identified here. */
5382 if (symbol_get_tc (sym
)->is_loop_target
)
5383 symbol_get_frag (sym
)->tc_frag_data
.is_loop_target
= TRUE
;
5385 dwarf2_emit_label (sym
);
5389 /* tc_unrecognized_line hook */
5392 xtensa_unrecognized_line (int ch
)
5397 if (cur_vinsn
.inside_bundle
== 0)
5399 /* PR8110: Cannot emit line number info inside a FLIX bundle
5400 when using --gstabs. Temporarily disable debug info. */
5401 generate_lineno_debug ();
5402 if (debug_type
== DEBUG_STABS
)
5404 xt_saved_debug_type
= debug_type
;
5405 debug_type
= DEBUG_NONE
;
5408 cur_vinsn
.inside_bundle
= 1;
5412 as_bad (_("extra opening brace"));
5418 if (cur_vinsn
.inside_bundle
)
5419 finish_vinsn (&cur_vinsn
);
5422 as_bad (_("extra closing brace"));
5427 as_bad (_("syntax error"));
5434 /* md_flush_pending_output hook */
5437 xtensa_flush_pending_output (void)
5439 /* This line fixes a bug where automatically generated gstabs info
5440 separates a function label from its entry instruction, ending up
5441 with the literal position between the function label and the entry
5442 instruction and crashing code. It only happens with --gstabs and
5443 --text-section-literals, and when several other obscure relaxation
5444 conditions are met. */
5445 if (outputting_stabs_line_debug
)
5448 if (cur_vinsn
.inside_bundle
)
5449 as_bad (_("missing closing brace"));
5451 /* If there is a non-zero instruction fragment, close it. */
5452 if (frag_now_fix () != 0 && frag_now
->tc_frag_data
.is_insn
)
5454 frag_wane (frag_now
);
5456 xtensa_set_frag_assembly_state (frag_now
);
5458 frag_now
->tc_frag_data
.is_insn
= FALSE
;
5460 xtensa_clear_insn_labels ();
5464 /* We had an error while parsing an instruction. The string might look
5465 like this: "insn arg1, arg2 }". If so, we need to see the closing
5466 brace and reset some fields. Otherwise, the vinsn never gets closed
5467 and the num_slots field will grow past the end of the array of slots,
5468 and bad things happen. */
5471 error_reset_cur_vinsn (void)
5473 if (cur_vinsn
.inside_bundle
)
5475 if (*input_line_pointer
== '}'
5476 || *(input_line_pointer
- 1) == '}'
5477 || *(input_line_pointer
- 2) == '}')
5478 xg_clear_vinsn (&cur_vinsn
);
5484 md_assemble (char *str
)
5486 xtensa_isa isa
= xtensa_default_isa
;
5489 bfd_boolean has_underbar
= FALSE
;
5490 char *arg_strings
[MAX_INSN_ARGS
];
5492 TInsn orig_insn
; /* Original instruction from the input. */
5494 tinsn_init (&orig_insn
);
5496 /* Split off the opcode. */
5497 opnamelen
= strspn (str
, "abcdefghijklmnopqrstuvwxyz_/0123456789.");
5498 opname
= xstrndup (str
, opnamelen
);
5500 num_args
= tokenize_arguments (arg_strings
, str
+ opnamelen
);
5503 as_bad (_("syntax error"));
5507 if (xg_translate_idioms (&opname
, &num_args
, arg_strings
))
5510 /* Check for an underbar prefix. */
5513 has_underbar
= TRUE
;
5517 orig_insn
.insn_type
= ITYPE_INSN
;
5519 orig_insn
.is_specific_opcode
= (has_underbar
|| !use_transform ());
5520 orig_insn
.opcode
= xtensa_opcode_lookup (isa
, opname
);
5522 /* Special case: Check for "CALLXn.TLS" psuedo op. If found, grab its
5523 extra argument and set the opcode to "CALLXn". */
5524 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5525 && strncasecmp (opname
, "callx", 5) == 0)
5527 unsigned long window_size
;
5530 window_size
= strtoul (opname
+ 5, &suffix
, 10);
5531 if (suffix
!= opname
+ 5
5532 && (window_size
== 0
5535 || window_size
== 12)
5536 && strcasecmp (suffix
, ".tls") == 0)
5538 switch (window_size
)
5540 case 0: orig_insn
.opcode
= xtensa_callx0_opcode
; break;
5541 case 4: orig_insn
.opcode
= xtensa_callx4_opcode
; break;
5542 case 8: orig_insn
.opcode
= xtensa_callx8_opcode
; break;
5543 case 12: orig_insn
.opcode
= xtensa_callx12_opcode
; break;
5547 as_bad (_("wrong number of operands for '%s'"), opname
);
5550 bfd_reloc_code_real_type reloc
;
5551 char *old_input_line_pointer
;
5552 expressionS
*tok
= &orig_insn
.extra_arg
;
5554 old_input_line_pointer
= input_line_pointer
;
5555 input_line_pointer
= arg_strings
[num_args
- 1];
5558 if (tok
->X_op
== O_symbol
5559 && ((reloc
= xtensa_elf_suffix (&input_line_pointer
, tok
))
5560 == BFD_RELOC_XTENSA_TLS_CALL
))
5561 tok
->X_op
= map_suffix_reloc_to_operator (reloc
);
5563 as_bad (_("bad relocation expression for '%s'"), opname
);
5565 input_line_pointer
= old_input_line_pointer
;
5571 /* Special case: Check for "j.l" psuedo op. */
5572 if (orig_insn
.opcode
== XTENSA_UNDEFINED
5573 && strncasecmp (opname
, "j.l", 3) == 0)
5576 as_bad (_("wrong number of operands for '%s'"), opname
);
5579 char *old_input_line_pointer
;
5580 expressionS
*tok
= &orig_insn
.extra_arg
;
5582 old_input_line_pointer
= input_line_pointer
;
5583 input_line_pointer
= arg_strings
[num_args
- 1];
5585 expression_maybe_register (xtensa_jx_opcode
, 0, tok
);
5586 input_line_pointer
= old_input_line_pointer
;
5589 orig_insn
.opcode
= xtensa_j_opcode
;
5593 if (orig_insn
.opcode
== XTENSA_UNDEFINED
)
5595 xtensa_format fmt
= xtensa_format_lookup (isa
, opname
);
5596 if (fmt
== XTENSA_UNDEFINED
)
5598 as_bad (_("unknown opcode or format name '%s'"), opname
);
5599 error_reset_cur_vinsn ();
5602 if (!cur_vinsn
.inside_bundle
)
5604 as_bad (_("format names only valid inside bundles"));
5605 error_reset_cur_vinsn ();
5608 if (cur_vinsn
.format
!= XTENSA_UNDEFINED
)
5609 as_warn (_("multiple formats specified for one bundle; using '%s'"),
5611 cur_vinsn
.format
= fmt
;
5612 free (has_underbar
? opname
- 1 : opname
);
5613 error_reset_cur_vinsn ();
5617 /* Parse the arguments. */
5618 if (parse_arguments (&orig_insn
, num_args
, arg_strings
))
5620 as_bad (_("syntax error"));
5621 error_reset_cur_vinsn ();
5625 /* Free the opcode and argument strings, now that they've been parsed. */
5626 free (has_underbar
? opname
- 1 : opname
);
5628 while (num_args
-- > 0)
5629 free (arg_strings
[num_args
]);
5631 /* Get expressions for invisible operands. */
5632 if (get_invisible_operands (&orig_insn
))
5634 error_reset_cur_vinsn ();
5638 /* Check for the right number and type of arguments. */
5639 if (tinsn_check_arguments (&orig_insn
))
5641 error_reset_cur_vinsn ();
5645 /* Record the line number for each TInsn, because a FLIX bundle may be
5646 spread across multiple input lines and individual instructions may be
5647 moved around in some cases. */
5648 orig_insn
.loc_directive_seen
= dwarf2_loc_directive_seen
;
5649 dwarf2_where (&orig_insn
.debug_line
);
5650 dwarf2_consume_line_info ();
5652 xg_add_branch_and_loop_targets (&orig_insn
);
5654 /* Check that immediate value for ENTRY is >= 16. */
5655 if (orig_insn
.opcode
== xtensa_entry_opcode
&& orig_insn
.ntok
>= 3)
5657 expressionS
*exp
= &orig_insn
.tok
[2];
5658 if (exp
->X_op
== O_constant
&& exp
->X_add_number
< 16)
5659 as_warn (_("entry instruction with stack decrement < 16"));
5663 assemble_tokens (opcode, tok, ntok);
5664 expand the tokens from the orig_insn into the
5665 stack of instructions that will not expand
5666 unless required at relaxation time. */
5668 if (!cur_vinsn
.inside_bundle
)
5669 emit_single_op (&orig_insn
);
5670 else /* We are inside a bundle. */
5672 cur_vinsn
.slots
[cur_vinsn
.num_slots
] = orig_insn
;
5673 cur_vinsn
.num_slots
++;
5674 if (*input_line_pointer
== '}'
5675 || *(input_line_pointer
- 1) == '}'
5676 || *(input_line_pointer
- 2) == '}')
5677 finish_vinsn (&cur_vinsn
);
5680 /* We've just emitted a new instruction so clear the list of labels. */
5681 xtensa_clear_insn_labels ();
5683 xtensa_check_frag_count ();
5687 /* HANDLE_ALIGN hook */
5689 /* For a .align directive, we mark the previous block with the alignment
5690 information. This will be placed in the object file in the
5691 property section corresponding to this section. */
5694 xtensa_handle_align (fragS
*fragP
)
5697 && ! fragP
->tc_frag_data
.is_literal
5698 && (fragP
->fr_type
== rs_align
5699 || fragP
->fr_type
== rs_align_code
)
5700 && fragP
->fr_offset
> 0
5701 && now_seg
!= bss_section
)
5703 fragP
->tc_frag_data
.is_align
= TRUE
;
5704 fragP
->tc_frag_data
.alignment
= fragP
->fr_offset
;
5707 if (fragP
->fr_type
== rs_align_test
)
5710 count
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
5712 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5713 _("unaligned entry instruction"));
5716 if (linkrelax
&& fragP
->fr_type
== rs_org
)
5717 fragP
->fr_subtype
= RELAX_ORG
;
5721 /* TC_FRAG_INIT hook */
5724 xtensa_frag_init (fragS
*frag
)
5726 xtensa_set_frag_assembly_state (frag
);
5731 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
5737 /* Round up a section size to the appropriate boundary. */
5740 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
5742 return size
; /* Byte alignment is fine. */
5747 md_pcrel_from (fixS
*fixP
)
5750 static xtensa_insnbuf insnbuf
= NULL
;
5751 static xtensa_insnbuf slotbuf
= NULL
;
5754 xtensa_opcode opcode
;
5757 xtensa_isa isa
= xtensa_default_isa
;
5758 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5759 bfd_boolean alt_reloc
;
5761 if (fixP
->fx_r_type
== BFD_RELOC_XTENSA_ASM_EXPAND
)
5764 if (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
5769 insnbuf
= xtensa_insnbuf_alloc (isa
);
5770 slotbuf
= xtensa_insnbuf_alloc (isa
);
5773 insn_p
= &fixP
->fx_frag
->fr_literal
[fixP
->fx_where
];
5774 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) insn_p
, 0);
5775 fmt
= xtensa_format_decode (isa
, insnbuf
);
5777 if (fmt
== XTENSA_UNDEFINED
)
5778 as_fatal (_("bad instruction format"));
5780 if (decode_reloc (fixP
->fx_r_type
, &slot
, &alt_reloc
) != 0)
5781 as_fatal (_("invalid relocation"));
5783 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
5784 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
5786 /* Check for "alternate" relocations (operand not specified). None
5787 of the current uses for these are really PC-relative. */
5788 if (alt_reloc
|| opcode
== xtensa_const16_opcode
)
5790 if (opcode
!= xtensa_l32r_opcode
5791 && opcode
!= xtensa_const16_opcode
)
5792 as_fatal (_("invalid relocation for '%s' instruction"),
5793 xtensa_opcode_name (isa
, opcode
));
5797 opnum
= get_relaxable_immed (opcode
);
5799 if (xtensa_operand_is_PCrelative (isa
, opcode
, opnum
) != 1
5800 || xtensa_operand_do_reloc (isa
, opcode
, opnum
, &opnd_value
, addr
))
5802 as_bad_where (fixP
->fx_file
,
5804 _("invalid relocation for operand %d of '%s'"),
5805 opnum
, xtensa_opcode_name (isa
, opcode
));
5808 return 0 - opnd_value
;
5812 /* TC_FORCE_RELOCATION hook */
5815 xtensa_force_relocation (fixS
*fix
)
5817 switch (fix
->fx_r_type
)
5819 case BFD_RELOC_XTENSA_ASM_EXPAND
:
5820 case BFD_RELOC_XTENSA_SLOT0_ALT
:
5821 case BFD_RELOC_XTENSA_SLOT1_ALT
:
5822 case BFD_RELOC_XTENSA_SLOT2_ALT
:
5823 case BFD_RELOC_XTENSA_SLOT3_ALT
:
5824 case BFD_RELOC_XTENSA_SLOT4_ALT
:
5825 case BFD_RELOC_XTENSA_SLOT5_ALT
:
5826 case BFD_RELOC_XTENSA_SLOT6_ALT
:
5827 case BFD_RELOC_XTENSA_SLOT7_ALT
:
5828 case BFD_RELOC_XTENSA_SLOT8_ALT
:
5829 case BFD_RELOC_XTENSA_SLOT9_ALT
:
5830 case BFD_RELOC_XTENSA_SLOT10_ALT
:
5831 case BFD_RELOC_XTENSA_SLOT11_ALT
:
5832 case BFD_RELOC_XTENSA_SLOT12_ALT
:
5833 case BFD_RELOC_XTENSA_SLOT13_ALT
:
5834 case BFD_RELOC_XTENSA_SLOT14_ALT
:
5840 if (linkrelax
&& fix
->fx_addsy
5841 && relaxable_section (S_GET_SEGMENT (fix
->fx_addsy
)))
5844 return generic_force_reloc (fix
);
5848 /* TC_VALIDATE_FIX_SUB hook */
5851 xtensa_validate_fix_sub (fixS
*fix
)
5853 segT add_symbol_segment
, sub_symbol_segment
;
5855 /* The difference of two symbols should be resolved by the assembler when
5856 linkrelax is not set. If the linker may relax the section containing
5857 the symbols, then an Xtensa DIFF relocation must be generated so that
5858 the linker knows to adjust the difference value. */
5859 if (!linkrelax
|| fix
->fx_addsy
== NULL
)
5862 /* Make sure both symbols are in the same segment, and that segment is
5863 "normal" and relaxable. If the segment is not "normal", then the
5864 fix is not valid. If the segment is not "relaxable", then the fix
5865 should have been handled earlier. */
5866 add_symbol_segment
= S_GET_SEGMENT (fix
->fx_addsy
);
5867 if (! SEG_NORMAL (add_symbol_segment
) ||
5868 ! relaxable_section (add_symbol_segment
))
5870 sub_symbol_segment
= S_GET_SEGMENT (fix
->fx_subsy
);
5871 return (sub_symbol_segment
== add_symbol_segment
);
5875 /* NO_PSEUDO_DOT hook */
5877 /* This function has nothing to do with pseudo dots, but this is the
5878 nearest macro to where the check needs to take place. FIXME: This
5882 xtensa_check_inside_bundle (void)
5884 if (cur_vinsn
.inside_bundle
&& input_line_pointer
[-1] == '.')
5885 as_bad (_("directives are not valid inside bundles"));
5887 /* This function must always return FALSE because it is called via a
5888 macro that has nothing to do with bundling. */
5893 /* md_elf_section_change_hook */
5896 xtensa_elf_section_change_hook (void)
5898 /* Set up the assembly state. */
5899 if (!frag_now
->tc_frag_data
.is_assembly_state_set
)
5900 xtensa_set_frag_assembly_state (frag_now
);
5904 /* tc_fix_adjustable hook */
5907 xtensa_fix_adjustable (fixS
*fixP
)
5909 /* We need the symbol name for the VTABLE entries. */
5910 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
5911 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
5918 /* tc_symbol_new_hook */
5920 symbolS
*expr_symbols
= NULL
;
5923 xtensa_symbol_new_hook (symbolS
*sym
)
5925 if (is_leb128_expr
&& S_GET_SEGMENT (sym
) == expr_section
)
5927 symbol_get_tc (sym
)->next_expr_symbol
= expr_symbols
;
5934 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg
)
5936 char *const fixpos
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5939 /* Subtracted symbols are only allowed for a few relocation types, and
5940 unless linkrelax is enabled, they should not make it to this point. */
5941 if (fixP
->fx_subsy
&& !(linkrelax
&& (fixP
->fx_r_type
== BFD_RELOC_32
5942 || fixP
->fx_r_type
== BFD_RELOC_16
5943 || fixP
->fx_r_type
== BFD_RELOC_8
)))
5944 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("expression too complex"));
5946 switch (fixP
->fx_r_type
)
5948 case BFD_RELOC_32_PCREL
:
5954 switch (fixP
->fx_r_type
)
5957 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF8
;
5958 fixP
->fx_signed
= 0;
5961 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF16
;
5962 fixP
->fx_signed
= 0;
5965 fixP
->fx_r_type
= BFD_RELOC_XTENSA_DIFF32
;
5966 fixP
->fx_signed
= 0;
5972 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
5973 - S_GET_VALUE (fixP
->fx_subsy
));
5975 /* The difference value gets written out, and the DIFF reloc
5976 identifies the address of the subtracted symbol (i.e., the one
5977 with the lowest address). */
5979 fixP
->fx_offset
-= val
;
5980 fixP
->fx_subsy
= NULL
;
5982 else if (! fixP
->fx_addsy
)
5989 case BFD_RELOC_XTENSA_PLT
:
5990 md_number_to_chars (fixpos
, val
, fixP
->fx_size
);
5991 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
5994 case BFD_RELOC_XTENSA_TLSDESC_FN
:
5995 case BFD_RELOC_XTENSA_TLSDESC_ARG
:
5996 case BFD_RELOC_XTENSA_TLS_TPOFF
:
5997 case BFD_RELOC_XTENSA_TLS_DTPOFF
:
5998 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
5999 md_number_to_chars (fixpos
, 0, fixP
->fx_size
);
6000 fixP
->fx_no_overflow
= 0; /* Use the standard overflow check. */
6003 case BFD_RELOC_XTENSA_SLOT0_OP
:
6004 case BFD_RELOC_XTENSA_SLOT1_OP
:
6005 case BFD_RELOC_XTENSA_SLOT2_OP
:
6006 case BFD_RELOC_XTENSA_SLOT3_OP
:
6007 case BFD_RELOC_XTENSA_SLOT4_OP
:
6008 case BFD_RELOC_XTENSA_SLOT5_OP
:
6009 case BFD_RELOC_XTENSA_SLOT6_OP
:
6010 case BFD_RELOC_XTENSA_SLOT7_OP
:
6011 case BFD_RELOC_XTENSA_SLOT8_OP
:
6012 case BFD_RELOC_XTENSA_SLOT9_OP
:
6013 case BFD_RELOC_XTENSA_SLOT10_OP
:
6014 case BFD_RELOC_XTENSA_SLOT11_OP
:
6015 case BFD_RELOC_XTENSA_SLOT12_OP
:
6016 case BFD_RELOC_XTENSA_SLOT13_OP
:
6017 case BFD_RELOC_XTENSA_SLOT14_OP
:
6020 /* Write the tentative value of a PC-relative relocation to a
6021 local symbol into the instruction. The value will be ignored
6022 by the linker, and it makes the object file disassembly
6023 readable when all branch targets are encoded in relocations. */
6025 gas_assert (fixP
->fx_addsy
);
6026 if (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
6027 && !S_FORCE_RELOC (fixP
->fx_addsy
, 1))
6029 val
= (S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
6030 - md_pcrel_from (fixP
));
6031 (void) xg_apply_fix_value (fixP
, val
);
6034 else if (! fixP
->fx_addsy
)
6037 if (xg_apply_fix_value (fixP
, val
))
6042 case BFD_RELOC_XTENSA_ASM_EXPAND
:
6043 case BFD_RELOC_XTENSA_TLS_FUNC
:
6044 case BFD_RELOC_XTENSA_TLS_ARG
:
6045 case BFD_RELOC_XTENSA_TLS_CALL
:
6046 case BFD_RELOC_XTENSA_SLOT0_ALT
:
6047 case BFD_RELOC_XTENSA_SLOT1_ALT
:
6048 case BFD_RELOC_XTENSA_SLOT2_ALT
:
6049 case BFD_RELOC_XTENSA_SLOT3_ALT
:
6050 case BFD_RELOC_XTENSA_SLOT4_ALT
:
6051 case BFD_RELOC_XTENSA_SLOT5_ALT
:
6052 case BFD_RELOC_XTENSA_SLOT6_ALT
:
6053 case BFD_RELOC_XTENSA_SLOT7_ALT
:
6054 case BFD_RELOC_XTENSA_SLOT8_ALT
:
6055 case BFD_RELOC_XTENSA_SLOT9_ALT
:
6056 case BFD_RELOC_XTENSA_SLOT10_ALT
:
6057 case BFD_RELOC_XTENSA_SLOT11_ALT
:
6058 case BFD_RELOC_XTENSA_SLOT12_ALT
:
6059 case BFD_RELOC_XTENSA_SLOT13_ALT
:
6060 case BFD_RELOC_XTENSA_SLOT14_ALT
:
6061 /* These all need to be resolved at link-time. Do nothing now. */
6064 case BFD_RELOC_VTABLE_INHERIT
:
6065 case BFD_RELOC_VTABLE_ENTRY
:
6070 as_bad (_("unhandled local relocation fix %s"),
6071 bfd_get_reloc_code_name (fixP
->fx_r_type
));
6077 md_atof (int type
, char *litP
, int *sizeP
)
6079 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
6084 md_estimate_size_before_relax (fragS
*fragP
, segT seg ATTRIBUTE_UNUSED
)
6086 return total_frag_text_expansion (fragP
);
6090 /* Translate internal representation of relocation info to BFD target
6094 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
6098 reloc
= XNEW (arelent
);
6099 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
6100 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6101 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6103 /* Make sure none of our internal relocations make it this far.
6104 They'd better have been fully resolved by this point. */
6105 gas_assert ((int) fixp
->fx_r_type
> 0);
6107 reloc
->addend
= fixp
->fx_offset
;
6109 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6110 if (reloc
->howto
== NULL
)
6112 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6113 _("cannot represent `%s' relocation in object file"),
6114 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6115 free (reloc
->sym_ptr_ptr
);
6120 if (!fixp
->fx_pcrel
!= !reloc
->howto
->pc_relative
)
6121 as_fatal (_("internal error; cannot generate `%s' relocation"),
6122 bfd_get_reloc_code_name (fixp
->fx_r_type
));
6128 /* Checks for resource conflicts between instructions. */
6130 /* The func unit stuff could be implemented as bit-vectors rather
6131 than the iterative approach here. If it ends up being too
6132 slow, we will switch it. */
6135 new_resource_table (void *data
,
6138 unit_num_copies_func uncf
,
6139 opcode_num_units_func onuf
,
6140 opcode_funcUnit_use_unit_func ouuf
,
6141 opcode_funcUnit_use_stage_func ousf
)
6144 resource_table
*rt
= XNEW (resource_table
);
6146 rt
->cycles
= cycles
;
6147 rt
->allocated_cycles
= cycles
;
6149 rt
->unit_num_copies
= uncf
;
6150 rt
->opcode_num_units
= onuf
;
6151 rt
->opcode_unit_use
= ouuf
;
6152 rt
->opcode_unit_stage
= ousf
;
6154 rt
->units
= (unsigned char **) xcalloc (cycles
, sizeof (unsigned char *));
6155 for (i
= 0; i
< cycles
; i
++)
6156 rt
->units
[i
] = (unsigned char *) xcalloc (nu
, sizeof (unsigned char));
6163 clear_resource_table (resource_table
*rt
)
6166 for (i
= 0; i
< rt
->allocated_cycles
; i
++)
6167 for (j
= 0; j
< rt
->num_units
; j
++)
6168 rt
->units
[i
][j
] = 0;
6172 /* We never shrink it, just fake it into thinking so. */
6175 resize_resource_table (resource_table
*rt
, int cycles
)
6179 rt
->cycles
= cycles
;
6180 if (cycles
<= rt
->allocated_cycles
)
6183 old_cycles
= rt
->allocated_cycles
;
6184 rt
->allocated_cycles
= cycles
;
6186 rt
->units
= XRESIZEVEC (unsigned char *, rt
->units
, rt
->allocated_cycles
);
6187 for (i
= 0; i
< old_cycles
; i
++)
6188 rt
->units
[i
] = XRESIZEVEC (unsigned char, rt
->units
[i
], rt
->num_units
);
6189 for (i
= old_cycles
; i
< cycles
; i
++)
6190 rt
->units
[i
] = xcalloc (rt
->num_units
, sizeof (unsigned char));
6195 resources_available (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6198 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6200 for (i
= 0; i
< uses
; i
++)
6202 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6203 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6204 int copies_in_use
= rt
->units
[stage
+ cycle
][unit
];
6205 int copies
= (rt
->unit_num_copies
) (rt
->data
, unit
);
6206 if (copies_in_use
>= copies
)
6214 reserve_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6217 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6219 for (i
= 0; i
< uses
; i
++)
6221 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6222 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6223 /* Note that this allows resources to be oversubscribed. That's
6224 essential to the way the optional scheduler works.
6225 resources_available reports when a resource is over-subscribed,
6226 so it's easy to tell. */
6227 rt
->units
[stage
+ cycle
][unit
]++;
6233 release_resources (resource_table
*rt
, xtensa_opcode opcode
, int cycle
)
6236 int uses
= (rt
->opcode_num_units
) (rt
->data
, opcode
);
6238 for (i
= 0; i
< uses
; i
++)
6240 xtensa_funcUnit unit
= (rt
->opcode_unit_use
) (rt
->data
, opcode
, i
);
6241 int stage
= (rt
->opcode_unit_stage
) (rt
->data
, opcode
, i
);
6242 gas_assert (rt
->units
[stage
+ cycle
][unit
] > 0);
6243 rt
->units
[stage
+ cycle
][unit
]--;
6248 /* Wrapper functions make parameterized resource reservation
6252 opcode_funcUnit_use_unit (void *data
, xtensa_opcode opcode
, int idx
)
6254 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6260 opcode_funcUnit_use_stage (void *data
, xtensa_opcode opcode
, int idx
)
6262 xtensa_funcUnit_use
*use
= xtensa_opcode_funcUnit_use (data
, opcode
, idx
);
6267 /* Note that this function does not check issue constraints, but
6268 solely whether the hardware is available to execute the given
6269 instructions together. It also doesn't check if the tinsns
6270 write the same state, or access the same tieports. That is
6271 checked by check_t1_t2_reads_and_writes. */
6274 resources_conflict (vliw_insn
*vinsn
)
6277 static resource_table
*rt
= NULL
;
6279 /* This is the most common case by far. Optimize it. */
6280 if (vinsn
->num_slots
== 1)
6285 xtensa_isa isa
= xtensa_default_isa
;
6286 rt
= new_resource_table
6287 (isa
, xtensa_num_pipe_stages
,
6288 xtensa_isa_num_funcUnits (isa
),
6289 (unit_num_copies_func
) xtensa_funcUnit_num_copies
,
6290 (opcode_num_units_func
) xtensa_opcode_num_funcUnit_uses
,
6291 opcode_funcUnit_use_unit
,
6292 opcode_funcUnit_use_stage
);
6295 clear_resource_table (rt
);
6297 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6299 if (!resources_available (rt
, vinsn
->slots
[i
].opcode
, 0))
6301 reserve_resources (rt
, vinsn
->slots
[i
].opcode
, 0);
6308 /* finish_vinsn, emit_single_op and helper functions. */
6310 static bfd_boolean
find_vinsn_conflicts (vliw_insn
*);
6311 static xtensa_format
xg_find_narrowest_format (vliw_insn
*);
6312 static void xg_assemble_vliw_tokens (vliw_insn
*);
6315 /* We have reached the end of a bundle; emit into the frag. */
6318 finish_vinsn (vliw_insn
*vinsn
)
6323 if (find_vinsn_conflicts (vinsn
))
6325 xg_clear_vinsn (vinsn
);
6329 /* First, find a format that works. */
6330 if (vinsn
->format
== XTENSA_UNDEFINED
)
6331 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6333 if (xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
) > 1
6334 && produce_flix
== FLIX_NONE
)
6336 as_bad (_("The option \"--no-allow-flix\" prohibits multi-slot flix."));
6337 xg_clear_vinsn (vinsn
);
6341 if (vinsn
->format
== XTENSA_UNDEFINED
)
6343 as_bad (_("couldn't find a valid instruction format"));
6344 fprintf (stderr
, _(" ops were: "));
6345 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6346 fprintf (stderr
, _(" %s;"),
6347 xtensa_opcode_name (xtensa_default_isa
,
6348 vinsn
->slots
[i
].opcode
));
6349 fprintf (stderr
, _("\n"));
6350 xg_clear_vinsn (vinsn
);
6354 if (vinsn
->num_slots
6355 != xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
))
6357 as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
6358 xtensa_format_name (xtensa_default_isa
, vinsn
->format
),
6359 xtensa_format_num_slots (xtensa_default_isa
, vinsn
->format
),
6361 xg_clear_vinsn (vinsn
);
6365 if (resources_conflict (vinsn
))
6367 as_bad (_("illegal resource usage in bundle"));
6368 fprintf (stderr
, " ops were: ");
6369 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6370 fprintf (stderr
, " %s;",
6371 xtensa_opcode_name (xtensa_default_isa
,
6372 vinsn
->slots
[i
].opcode
));
6373 fprintf (stderr
, "\n");
6374 xg_clear_vinsn (vinsn
);
6378 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6380 if (vinsn
->slots
[i
].opcode
!= XTENSA_UNDEFINED
)
6382 symbolS
*lit_sym
= NULL
;
6384 bfd_boolean e
= FALSE
;
6385 bfd_boolean saved_density
= density_supported
;
6387 /* We don't want to narrow ops inside multi-slot bundles. */
6388 if (vinsn
->num_slots
> 1)
6389 density_supported
= FALSE
;
6391 istack_init (&slotstack
);
6392 if (vinsn
->slots
[i
].opcode
== xtensa_nop_opcode
)
6394 vinsn
->slots
[i
].opcode
=
6395 xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6397 vinsn
->slots
[i
].ntok
= 0;
6400 if (xg_expand_assembly_insn (&slotstack
, &vinsn
->slots
[i
]))
6406 density_supported
= saved_density
;
6410 xg_clear_vinsn (vinsn
);
6414 for (j
= 0; j
< slotstack
.ninsn
; j
++)
6416 TInsn
*insn
= &slotstack
.insn
[j
];
6417 if (insn
->insn_type
== ITYPE_LITERAL
)
6419 gas_assert (lit_sym
== NULL
);
6420 lit_sym
= xg_assemble_literal (insn
);
6424 gas_assert (insn
->insn_type
== ITYPE_INSN
);
6426 xg_resolve_literals (insn
, lit_sym
);
6427 if (j
!= slotstack
.ninsn
- 1)
6428 emit_single_op (insn
);
6432 if (vinsn
->num_slots
> 1)
6434 if (opcode_fits_format_slot
6435 (slotstack
.insn
[slotstack
.ninsn
- 1].opcode
,
6438 vinsn
->slots
[i
] = slotstack
.insn
[slotstack
.ninsn
- 1];
6442 emit_single_op (&slotstack
.insn
[slotstack
.ninsn
- 1]);
6443 if (vinsn
->format
== XTENSA_UNDEFINED
)
6444 vinsn
->slots
[i
].opcode
= xtensa_nop_opcode
;
6446 vinsn
->slots
[i
].opcode
6447 = xtensa_format_slot_nop_opcode (xtensa_default_isa
,
6450 vinsn
->slots
[i
].ntok
= 0;
6455 vinsn
->slots
[0] = slotstack
.insn
[slotstack
.ninsn
- 1];
6456 vinsn
->format
= XTENSA_UNDEFINED
;
6461 /* Now check resource conflicts on the modified bundle. */
6462 if (resources_conflict (vinsn
))
6464 as_bad (_("illegal resource usage in bundle"));
6465 fprintf (stderr
, " ops were: ");
6466 for (i
= 0; i
< vinsn
->num_slots
; i
++)
6467 fprintf (stderr
, " %s;",
6468 xtensa_opcode_name (xtensa_default_isa
,
6469 vinsn
->slots
[i
].opcode
));
6470 fprintf (stderr
, "\n");
6471 xg_clear_vinsn (vinsn
);
6475 /* First, find a format that works. */
6476 if (vinsn
->format
== XTENSA_UNDEFINED
)
6477 vinsn
->format
= xg_find_narrowest_format (vinsn
);
6479 xg_assemble_vliw_tokens (vinsn
);
6481 xg_clear_vinsn (vinsn
);
6483 xtensa_check_frag_count ();
6487 /* Given an vliw instruction, what conflicts are there in register
6488 usage and in writes to states and queues?
6490 This function does two things:
6491 1. Reports an error when a vinsn contains illegal combinations
6492 of writes to registers states or queues.
6493 2. Marks individual tinsns as not relaxable if the combination
6494 contains antidependencies.
6496 Job 2 handles things like swap semantics in instructions that need
6497 to be relaxed. For example,
6501 normally would be relaxed to
6506 _but_, if the above instruction is bundled with an a0 reader, e.g.,
6508 { addi a0, a1, 10000 ; add a2, a0, a4 ; }
6510 then we can't relax it into
6513 { add a0, a1, a0 ; add a2, a0, a4 ; }
6515 because the value of a0 is trashed before the second add can read it. */
6517 static char check_t1_t2_reads_and_writes (TInsn
*, TInsn
*);
6520 find_vinsn_conflicts (vliw_insn
*vinsn
)
6524 xtensa_isa isa
= xtensa_default_isa
;
6526 gas_assert (!past_xtensa_end
);
6528 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6530 TInsn
*op1
= &vinsn
->slots
[i
];
6531 if (op1
->is_specific_opcode
)
6532 op1
->keep_wide
= TRUE
;
6534 op1
->keep_wide
= FALSE
;
6537 for (i
= 0 ; i
< vinsn
->num_slots
; i
++)
6539 TInsn
*op1
= &vinsn
->slots
[i
];
6541 if (xtensa_opcode_is_branch (isa
, op1
->opcode
) == 1)
6544 for (j
= 0; j
< vinsn
->num_slots
; j
++)
6548 TInsn
*op2
= &vinsn
->slots
[j
];
6549 char conflict_type
= check_t1_t2_reads_and_writes (op1
, op2
);
6550 switch (conflict_type
)
6553 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
6554 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6555 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6558 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
6559 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6560 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6563 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
6564 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6565 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6568 as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
6569 xtensa_opcode_name (isa
, op1
->opcode
), i
,
6570 xtensa_opcode_name (isa
, op2
->opcode
), j
);
6573 /* Everything is OK. */
6576 op2
->is_specific_opcode
= (op2
->is_specific_opcode
6577 || conflict_type
== 'a');
6584 as_bad (_("multiple branches or jumps in the same bundle"));
6592 /* Check how the state used by t1 and t2 relate.
6595 case A: t1 reads a register t2 writes (an antidependency within a bundle)
6596 case B: no relationship between what is read and written (both could
6597 read the same reg though)
6598 case C: t1 writes a register t2 writes (a register conflict within a
6600 case D: t1 writes a state that t2 also writes
6601 case E: t1 writes a tie queue that t2 also writes
6602 case F: two volatile queue accesses
6606 check_t1_t2_reads_and_writes (TInsn
*t1
, TInsn
*t2
)
6608 xtensa_isa isa
= xtensa_default_isa
;
6609 xtensa_regfile t1_regfile
, t2_regfile
;
6611 int t1_base_reg
, t1_last_reg
;
6612 int t2_base_reg
, t2_last_reg
;
6613 char t1_inout
, t2_inout
;
6615 char conflict
= 'b';
6620 bfd_boolean t1_volatile
= FALSE
;
6621 bfd_boolean t2_volatile
= FALSE
;
6623 /* Check registers. */
6624 for (j
= 0; j
< t2
->ntok
; j
++)
6626 if (xtensa_operand_is_register (isa
, t2
->opcode
, j
) != 1)
6629 t2_regfile
= xtensa_operand_regfile (isa
, t2
->opcode
, j
);
6630 t2_base_reg
= t2
->tok
[j
].X_add_number
;
6631 t2_last_reg
= t2_base_reg
+ xtensa_operand_num_regs (isa
, t2
->opcode
, j
);
6633 for (i
= 0; i
< t1
->ntok
; i
++)
6635 if (xtensa_operand_is_register (isa
, t1
->opcode
, i
) != 1)
6638 t1_regfile
= xtensa_operand_regfile (isa
, t1
->opcode
, i
);
6640 if (t1_regfile
!= t2_regfile
)
6643 t1_inout
= xtensa_operand_inout (isa
, t1
->opcode
, i
);
6644 t2_inout
= xtensa_operand_inout (isa
, t2
->opcode
, j
);
6646 if (xtensa_operand_is_known_reg (isa
, t1
->opcode
, i
) == 0
6647 || xtensa_operand_is_known_reg (isa
, t2
->opcode
, j
) == 0)
6649 if (t1_inout
== 'm' || t1_inout
== 'o'
6650 || t2_inout
== 'm' || t2_inout
== 'o')
6657 t1_base_reg
= t1
->tok
[i
].X_add_number
;
6658 t1_last_reg
= (t1_base_reg
6659 + xtensa_operand_num_regs (isa
, t1
->opcode
, i
));
6661 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
6663 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
6665 if (t1_reg
!= t2_reg
)
6668 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6674 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6680 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6688 t1_states
= xtensa_opcode_num_stateOperands (isa
, t1
->opcode
);
6689 t2_states
= xtensa_opcode_num_stateOperands (isa
, t2
->opcode
);
6690 for (j
= 0; j
< t2_states
; j
++)
6692 xtensa_state t2_so
= xtensa_stateOperand_state (isa
, t2
->opcode
, j
);
6693 t2_inout
= xtensa_stateOperand_inout (isa
, t2
->opcode
, j
);
6694 for (i
= 0; i
< t1_states
; i
++)
6696 xtensa_state t1_so
= xtensa_stateOperand_state (isa
, t1
->opcode
, i
);
6697 t1_inout
= xtensa_stateOperand_inout (isa
, t1
->opcode
, i
);
6698 if (t1_so
!= t2_so
|| xtensa_state_is_shared_or (isa
, t1_so
) == 1)
6701 if (t2_inout
== 'i' && (t1_inout
== 'm' || t1_inout
== 'o'))
6707 if (t1_inout
== 'i' && (t2_inout
== 'm' || t2_inout
== 'o'))
6713 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6718 /* Check tieports. */
6719 t1_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t1
->opcode
);
6720 t2_interfaces
= xtensa_opcode_num_interfaceOperands (isa
, t2
->opcode
);
6721 for (j
= 0; j
< t2_interfaces
; j
++)
6723 xtensa_interface t2_int
6724 = xtensa_interfaceOperand_interface (isa
, t2
->opcode
, j
);
6725 int t2_class
= xtensa_interface_class_id (isa
, t2_int
);
6727 t2_inout
= xtensa_interface_inout (isa
, t2_int
);
6728 if (xtensa_interface_has_side_effect (isa
, t2_int
) == 1)
6731 for (i
= 0; i
< t1_interfaces
; i
++)
6733 xtensa_interface t1_int
6734 = xtensa_interfaceOperand_interface (isa
, t1
->opcode
, j
);
6735 int t1_class
= xtensa_interface_class_id (isa
, t1_int
);
6737 t1_inout
= xtensa_interface_inout (isa
, t1_int
);
6738 if (xtensa_interface_has_side_effect (isa
, t1_int
) == 1)
6741 if (t1_volatile
&& t2_volatile
&& (t1_class
== t2_class
))
6744 if (t1_int
!= t2_int
)
6747 if (t2_inout
== 'i' && t1_inout
== 'o')
6753 if (t1_inout
== 'i' && t2_inout
== 'o')
6759 if (t1_inout
!= 'i' && t2_inout
!= 'i')
6768 static xtensa_format
6769 xg_find_narrowest_format (vliw_insn
*vinsn
)
6771 /* Right now we assume that the ops within the vinsn are properly
6772 ordered for the slots that the programmer wanted them in. In
6773 other words, we don't rearrange the ops in hopes of finding a
6774 better format. The scheduler handles that. */
6776 xtensa_isa isa
= xtensa_default_isa
;
6777 xtensa_format format
;
6778 xtensa_opcode nop_opcode
= xtensa_nop_opcode
;
6780 if (vinsn
->num_slots
== 1)
6781 return xg_get_single_format (vinsn
->slots
[0].opcode
);
6783 for (format
= 0; format
< xtensa_isa_num_formats (isa
); format
++)
6786 xg_copy_vinsn (&v_copy
, vinsn
);
6787 if (xtensa_format_num_slots (isa
, format
) == v_copy
.num_slots
)
6791 for (slot
= 0; slot
< v_copy
.num_slots
; slot
++)
6793 if (v_copy
.slots
[slot
].opcode
== nop_opcode
)
6795 v_copy
.slots
[slot
].opcode
=
6796 xtensa_format_slot_nop_opcode (isa
, format
, slot
);
6797 v_copy
.slots
[slot
].ntok
= 0;
6800 if (opcode_fits_format_slot (v_copy
.slots
[slot
].opcode
,
6803 else if (v_copy
.num_slots
> 1)
6806 /* Try the widened version. */
6807 if (!v_copy
.slots
[slot
].keep_wide
6808 && !v_copy
.slots
[slot
].is_specific_opcode
6809 && xg_is_single_relaxable_insn (&v_copy
.slots
[slot
],
6811 && opcode_fits_format_slot (widened
.opcode
,
6814 v_copy
.slots
[slot
] = widened
;
6819 if (fit
== v_copy
.num_slots
)
6821 xg_copy_vinsn (vinsn
, &v_copy
);
6822 xtensa_format_encode (isa
, format
, vinsn
->insnbuf
);
6823 vinsn
->format
= format
;
6829 if (format
== xtensa_isa_num_formats (isa
))
6830 return XTENSA_UNDEFINED
;
6836 /* Return the additional space needed in a frag
6837 for possible relaxations of any ops in a VLIW insn.
6838 Also fill out the relaxations that might be required of
6839 each tinsn in the vinsn. */
6842 relaxation_requirements (vliw_insn
*vinsn
, bfd_boolean
*pfinish_frag
)
6844 bfd_boolean finish_frag
= FALSE
;
6845 int extra_space
= 0;
6848 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6850 TInsn
*tinsn
= &vinsn
->slots
[slot
];
6851 if (!tinsn_has_symbolic_operands (tinsn
))
6853 /* A narrow instruction could be widened later to help
6854 alignment issues. */
6855 if (xg_is_single_relaxable_insn (tinsn
, 0, TRUE
)
6856 && !tinsn
->is_specific_opcode
6857 && vinsn
->num_slots
== 1)
6859 /* Difference in bytes between narrow and wide insns... */
6861 tinsn
->subtype
= RELAX_NARROW
;
6866 if (workaround_b_j_loop_end
6867 && tinsn
->opcode
== xtensa_jx_opcode
6868 && use_transform ())
6870 /* Add 2 of these. */
6871 extra_space
+= 3; /* for the nop size */
6872 tinsn
->subtype
= RELAX_ADD_NOP_IF_PRE_LOOP_END
;
6875 /* Need to assemble it with space for the relocation. */
6876 if (xg_is_relaxable_insn (tinsn
, 0)
6877 && !tinsn
->is_specific_opcode
)
6879 int max_size
= xg_get_max_insn_widen_size (tinsn
->opcode
);
6880 int max_literal_size
=
6881 xg_get_max_insn_widen_literal_size (tinsn
->opcode
);
6883 tinsn
->literal_space
= max_literal_size
;
6885 tinsn
->subtype
= RELAX_IMMED
;
6886 extra_space
+= max_size
;
6890 /* A fix record will be added for this instruction prior
6891 to relaxation, so make it end the frag. */
6896 *pfinish_frag
= finish_frag
;
6902 bundle_tinsn (TInsn
*tinsn
, vliw_insn
*vinsn
)
6904 xtensa_isa isa
= xtensa_default_isa
;
6905 int slot
, chosen_slot
;
6907 vinsn
->format
= xg_get_single_format (tinsn
->opcode
);
6908 gas_assert (vinsn
->format
!= XTENSA_UNDEFINED
);
6909 vinsn
->num_slots
= xtensa_format_num_slots (isa
, vinsn
->format
);
6911 chosen_slot
= xg_get_single_slot (tinsn
->opcode
);
6912 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
6914 if (slot
== chosen_slot
)
6915 vinsn
->slots
[slot
] = *tinsn
;
6918 vinsn
->slots
[slot
].opcode
=
6919 xtensa_format_slot_nop_opcode (isa
, vinsn
->format
, slot
);
6920 vinsn
->slots
[slot
].ntok
= 0;
6921 vinsn
->slots
[slot
].insn_type
= ITYPE_INSN
;
6928 emit_single_op (TInsn
*orig_insn
)
6931 IStack istack
; /* put instructions into here */
6932 symbolS
*lit_sym
= NULL
;
6933 symbolS
*label_sym
= NULL
;
6935 istack_init (&istack
);
6937 /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
6938 Because the scheduling and bundling characteristics of movi and
6939 l32r or const16 are so different, we can do much better if we relax
6940 it prior to scheduling and bundling, rather than after. */
6941 if ((orig_insn
->opcode
== xtensa_movi_opcode
6942 || orig_insn
->opcode
== xtensa_movi_n_opcode
)
6943 && !cur_vinsn
.inside_bundle
6944 && (orig_insn
->tok
[1].X_op
== O_symbol
6945 || orig_insn
->tok
[1].X_op
== O_pltrel
6946 || orig_insn
->tok
[1].X_op
== O_tlsfunc
6947 || orig_insn
->tok
[1].X_op
== O_tlsarg
6948 || orig_insn
->tok
[1].X_op
== O_tpoff
6949 || orig_insn
->tok
[1].X_op
== O_dtpoff
)
6950 && !orig_insn
->is_specific_opcode
&& use_transform ())
6951 xg_assembly_relax (&istack
, orig_insn
, now_seg
, frag_now
, 0, 1, 0);
6953 if (xg_expand_assembly_insn (&istack
, orig_insn
))
6956 for (i
= 0; i
< istack
.ninsn
; i
++)
6958 TInsn
*insn
= &istack
.insn
[i
];
6959 switch (insn
->insn_type
)
6962 gas_assert (lit_sym
== NULL
);
6963 lit_sym
= xg_assemble_literal (insn
);
6967 static int relaxed_sym_idx
= 0;
6968 char *label
= XNEWVEC (char, strlen (FAKE_LABEL_NAME
) + 12);
6969 sprintf (label
, "%s_rl_%x", FAKE_LABEL_NAME
, relaxed_sym_idx
++);
6971 gas_assert (label_sym
== NULL
);
6972 label_sym
= symbol_find_or_make (label
);
6973 gas_assert (label_sym
);
6981 xg_resolve_literals (insn
, lit_sym
);
6983 xg_resolve_labels (insn
, label_sym
);
6985 bundle_tinsn (insn
, &v
);
7000 total_frag_text_expansion (fragS
*fragP
)
7003 int total_expansion
= 0;
7005 for (slot
= 0; slot
< config_max_slots
; slot
++)
7006 total_expansion
+= fragP
->tc_frag_data
.text_expansion
[slot
];
7008 return total_expansion
;
7012 /* Emit a vliw instruction to the current fragment. */
7015 xg_assemble_vliw_tokens (vliw_insn
*vinsn
)
7017 bfd_boolean finish_frag
;
7018 bfd_boolean is_jump
= FALSE
;
7019 bfd_boolean is_branch
= FALSE
;
7020 xtensa_isa isa
= xtensa_default_isa
;
7025 struct dwarf2_line_info debug_line
;
7026 bfd_boolean loc_directive_seen
= FALSE
;
7029 memset (&debug_line
, 0, sizeof (struct dwarf2_line_info
));
7031 if (generating_literals
)
7033 static int reported
= 0;
7035 as_bad_where (frag_now
->fr_file
, frag_now
->fr_line
,
7036 _("cannot assemble into a literal fragment"));
7043 if (frag_now_fix () != 0
7044 && (! frag_now
->tc_frag_data
.is_insn
7045 || (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7046 || (!use_transform ()) != frag_now
->tc_frag_data
.is_no_transform
7047 || (directive_state
[directive_longcalls
]
7048 != frag_now
->tc_frag_data
.use_longcalls
)
7049 || (directive_state
[directive_absolute_literals
]
7050 != frag_now
->tc_frag_data
.use_absolute_literals
)))
7052 frag_wane (frag_now
);
7054 xtensa_set_frag_assembly_state (frag_now
);
7057 if (workaround_a0_b_retw
7058 && vinsn
->num_slots
== 1
7059 && (get_last_insn_flags (now_seg
, now_subseg
) & FLAG_IS_A0_WRITER
) != 0
7060 && xtensa_opcode_is_branch (isa
, vinsn
->slots
[0].opcode
) == 1
7061 && use_transform ())
7063 has_a0_b_retw
= TRUE
;
7065 /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
7066 After the first assembly pass we will check all of them and
7067 add a nop if needed. */
7068 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7069 frag_var (rs_machine_dependent
, 4, 4,
7070 RELAX_ADD_NOP_IF_A0_B_RETW
,
7071 frag_now
->fr_symbol
,
7072 frag_now
->fr_offset
,
7074 xtensa_set_frag_assembly_state (frag_now
);
7075 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7076 frag_var (rs_machine_dependent
, 4, 4,
7077 RELAX_ADD_NOP_IF_A0_B_RETW
,
7078 frag_now
->fr_symbol
,
7079 frag_now
->fr_offset
,
7081 xtensa_set_frag_assembly_state (frag_now
);
7084 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7086 tinsn
= &vinsn
->slots
[slot
];
7088 /* See if the instruction implies an aligned section. */
7089 if (xtensa_opcode_is_loop (isa
, tinsn
->opcode
) == 1)
7090 record_alignment (now_seg
, 2);
7092 /* Determine the best line number for debug info. */
7093 if ((tinsn
->loc_directive_seen
|| !loc_directive_seen
)
7094 && (tinsn
->debug_line
.filenum
!= debug_line
.filenum
7095 || tinsn
->debug_line
.line
< debug_line
.line
7096 || tinsn
->debug_line
.column
< debug_line
.column
))
7097 debug_line
= tinsn
->debug_line
;
7098 if (tinsn
->loc_directive_seen
)
7099 loc_directive_seen
= TRUE
;
7102 /* Special cases for instructions that force an alignment... */
7103 /* None of these opcodes are bundle-able. */
7104 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1)
7108 /* Remember the symbol that marks the end of the loop in the frag
7109 that marks the start of the loop. This way we can easily find
7110 the end of the loop at the beginning, without adding special code
7111 to mark the loop instructions themselves. */
7112 symbolS
*target_sym
= NULL
;
7113 if (vinsn
->slots
[0].tok
[1].X_op
== O_symbol
)
7114 target_sym
= vinsn
->slots
[0].tok
[1].X_add_symbol
;
7116 xtensa_set_frag_assembly_state (frag_now
);
7117 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7119 max_fill
= get_text_align_max_fill_size
7120 (get_text_align_power (xtensa_fetch_width
),
7121 TRUE
, frag_now
->tc_frag_data
.is_no_density
);
7123 if (use_transform ())
7124 frag_var (rs_machine_dependent
, max_fill
, max_fill
,
7125 RELAX_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7127 frag_var (rs_machine_dependent
, 0, 0,
7128 RELAX_CHECK_ALIGN_NEXT_OPCODE
, target_sym
, 0, NULL
);
7129 xtensa_set_frag_assembly_state (frag_now
);
7132 if (vinsn
->slots
[0].opcode
== xtensa_entry_opcode
7133 && !vinsn
->slots
[0].is_specific_opcode
)
7135 xtensa_mark_literal_pool_location ();
7136 xtensa_move_labels (frag_now
, 0);
7137 frag_var (rs_align_test
, 1, 1, 0, NULL
, 2, NULL
);
7140 if (vinsn
->num_slots
== 1)
7142 if (workaround_a0_b_retw
&& use_transform ())
7143 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_A0_WRITER
,
7144 is_register_writer (&vinsn
->slots
[0], "a", 0));
7146 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
,
7147 is_bad_loopend_opcode (&vinsn
->slots
[0]));
7150 set_last_insn_flags (now_seg
, now_subseg
, FLAG_IS_BAD_LOOPEND
, FALSE
);
7152 insn_size
= xtensa_format_length (isa
, vinsn
->format
);
7154 extra_space
= relaxation_requirements (vinsn
, &finish_frag
);
7156 /* vinsn_to_insnbuf will produce the error. */
7157 if (vinsn
->format
!= XTENSA_UNDEFINED
)
7159 f
= frag_more (insn_size
+ extra_space
);
7160 xtensa_set_frag_assembly_state (frag_now
);
7161 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7164 vinsn_to_insnbuf (vinsn
, f
, frag_now
, FALSE
);
7165 if (vinsn
->format
== XTENSA_UNDEFINED
)
7168 xtensa_insnbuf_to_chars (isa
, vinsn
->insnbuf
, (unsigned char *) f
, 0);
7170 if (debug_type
== DEBUG_DWARF2
|| loc_directive_seen
)
7171 dwarf2_gen_line_info (frag_now_fix () - (insn_size
+ extra_space
),
7174 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
7176 tinsn
= &vinsn
->slots
[slot
];
7177 frag_now
->tc_frag_data
.slot_subtypes
[slot
] = tinsn
->subtype
;
7178 frag_now
->tc_frag_data
.slot_symbols
[slot
] = tinsn
->symbol
;
7179 frag_now
->tc_frag_data
.slot_offsets
[slot
] = tinsn
->offset
;
7180 frag_now
->tc_frag_data
.literal_frags
[slot
] = tinsn
->literal_frag
;
7181 if (tinsn
->opcode
== xtensa_l32r_opcode
)
7183 frag_now
->tc_frag_data
.literal_frags
[slot
] =
7184 tinsn
->tok
[1].X_add_symbol
->sy_frag
;
7186 if (tinsn
->literal_space
!= 0)
7187 xg_assemble_literal_space (tinsn
->literal_space
, slot
);
7188 frag_now
->tc_frag_data
.free_reg
[slot
] = tinsn
->extra_arg
;
7190 if (tinsn
->subtype
== RELAX_NARROW
)
7191 gas_assert (vinsn
->num_slots
== 1);
7192 if (xtensa_opcode_is_jump (isa
, tinsn
->opcode
) == 1)
7194 if (xtensa_opcode_is_branch (isa
, tinsn
->opcode
) == 1)
7197 if (tinsn
->subtype
|| tinsn
->symbol
|| tinsn
->offset
7198 || tinsn
->literal_frag
|| is_jump
|| is_branch
)
7202 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7203 frag_now
->tc_frag_data
.is_specific_opcode
= TRUE
;
7207 frag_variant (rs_machine_dependent
,
7208 extra_space
, extra_space
, RELAX_SLOTS
,
7209 frag_now
->fr_symbol
, frag_now
->fr_offset
, f
);
7210 xtensa_set_frag_assembly_state (frag_now
);
7213 /* Special cases for loops:
7214 close_loop_end should be inserted AFTER short_loop.
7215 Make sure that CLOSE loops are processed BEFORE short_loops
7216 when converting them. */
7218 /* "short_loop": Add a NOP if the loop is < 4 bytes. */
7219 if (xtensa_opcode_is_loop (isa
, vinsn
->slots
[0].opcode
) == 1
7220 && !vinsn
->slots
[0].is_specific_opcode
)
7222 if (workaround_short_loop
&& use_transform ())
7224 maybe_has_short_loop
= TRUE
;
7225 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7226 frag_var (rs_machine_dependent
, 4, 4,
7227 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7228 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7229 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7230 frag_var (rs_machine_dependent
, 4, 4,
7231 RELAX_ADD_NOP_IF_SHORT_LOOP
,
7232 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7235 /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
7236 loop at least 12 bytes away from another loop's end. */
7237 if (workaround_close_loop_end
&& use_transform ())
7239 maybe_has_close_loop_end
= TRUE
;
7240 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7241 frag_var (rs_machine_dependent
, 12, 12,
7242 RELAX_ADD_NOP_IF_CLOSE_LOOP_END
,
7243 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7247 if (use_transform ())
7251 gas_assert (finish_frag
);
7252 frag_var (rs_machine_dependent
,
7253 xtensa_fetch_width
, xtensa_fetch_width
,
7255 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7256 xtensa_set_frag_assembly_state (frag_now
);
7257 xtensa_maybe_create_trampoline_frag ();
7258 /* Always create one here. */
7259 xtensa_maybe_create_literal_pool_frag (TRUE
, FALSE
);
7261 else if (is_branch
&& do_align_targets ())
7263 gas_assert (finish_frag
);
7264 frag_var (rs_machine_dependent
,
7265 xtensa_fetch_width
, xtensa_fetch_width
,
7266 RELAX_MAYBE_UNREACHABLE
,
7267 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7268 xtensa_set_frag_assembly_state (frag_now
);
7269 frag_var (rs_machine_dependent
,
7271 RELAX_MAYBE_DESIRE_ALIGN
,
7272 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7273 xtensa_set_frag_assembly_state (frag_now
);
7277 /* Now, if the original opcode was a call... */
7278 if (do_align_targets ()
7279 && xtensa_opcode_is_call (isa
, vinsn
->slots
[0].opcode
) == 1)
7281 float freq
= get_subseg_total_freq (now_seg
, now_subseg
);
7282 frag_now
->tc_frag_data
.is_insn
= TRUE
;
7283 frag_var (rs_machine_dependent
, 4, (int) freq
, RELAX_DESIRE_ALIGN
,
7284 frag_now
->fr_symbol
, frag_now
->fr_offset
, NULL
);
7285 xtensa_set_frag_assembly_state (frag_now
);
7288 if (vinsn_has_specific_opcodes (vinsn
) && use_transform ())
7290 frag_wane (frag_now
);
7292 xtensa_set_frag_assembly_state (frag_now
);
7297 /* xtensa_end and helper functions. */
7299 static void xtensa_cleanup_align_frags (void);
7300 static void xtensa_fix_target_frags (void);
7301 static void xtensa_mark_narrow_branches (void);
7302 static void xtensa_mark_zcl_first_insns (void);
7303 static void xtensa_mark_difference_of_two_symbols (void);
7304 static void xtensa_fix_a0_b_retw_frags (void);
7305 static void xtensa_fix_b_j_loop_end_frags (void);
7306 static void xtensa_fix_close_loop_end_frags (void);
7307 static void xtensa_fix_short_loop_frags (void);
7308 static void xtensa_sanity_check (void);
7309 static void xtensa_add_config_info (void);
7314 directive_balance ();
7315 xtensa_flush_pending_output ();
7317 past_xtensa_end
= TRUE
;
7319 xtensa_move_literals ();
7321 xtensa_reorder_segments ();
7322 xtensa_cleanup_align_frags ();
7323 xtensa_fix_target_frags ();
7324 if (workaround_a0_b_retw
&& has_a0_b_retw
)
7325 xtensa_fix_a0_b_retw_frags ();
7326 if (workaround_b_j_loop_end
)
7327 xtensa_fix_b_j_loop_end_frags ();
7329 /* "close_loop_end" should be processed BEFORE "short_loop". */
7330 if (workaround_close_loop_end
&& maybe_has_close_loop_end
)
7331 xtensa_fix_close_loop_end_frags ();
7333 if (workaround_short_loop
&& maybe_has_short_loop
)
7334 xtensa_fix_short_loop_frags ();
7336 xtensa_mark_narrow_branches ();
7337 xtensa_mark_zcl_first_insns ();
7339 xtensa_sanity_check ();
7341 xtensa_add_config_info ();
7343 xtensa_check_frag_count ();
7347 struct trampoline_frag
7349 struct trampoline_frag
*next
;
7350 bfd_boolean needs_jump_around
;
7355 struct trampoline_seg
7357 struct trampoline_seg
*next
;
7359 struct trampoline_frag trampoline_list
;
7362 static struct trampoline_seg trampoline_seg_list
;
7363 #define J_RANGE (128 * 1024)
7365 static int unreachable_count
= 0;
7369 xtensa_maybe_create_trampoline_frag (void)
7371 if (!use_trampolines
)
7374 /* We create an area for possible trampolines every 10 unreachable frags.
7375 These are preferred over the ones not preceded by an unreachable frag,
7376 because we don't have to jump around them. This function is called after
7377 each RELAX_UNREACHABLE frag is created. */
7379 if (++unreachable_count
> 10)
7381 xtensa_create_trampoline_frag (FALSE
);
7382 clear_frag_count ();
7383 unreachable_count
= 0;
7388 xtensa_check_frag_count (void)
7390 if (!use_trampolines
|| frag_now
->tc_frag_data
.is_no_transform
)
7393 /* We create an area for possible trampolines every 8000 frags or so. This
7394 is an estimate based on the max range of a "j" insn (+/-128K) divided
7395 by a typical frag byte count (16), minus a few for safety. This function
7396 is called after each source line is processed. */
7398 if (get_frag_count () > 8000)
7400 xtensa_create_trampoline_frag (TRUE
);
7401 clear_frag_count ();
7402 unreachable_count
= 0;
7405 /* We create an area for a possible literal pool every N (default 5000)
7407 xtensa_maybe_create_literal_pool_frag (TRUE
, TRUE
);
7410 static xtensa_insnbuf trampoline_buf
= NULL
;
7411 static xtensa_insnbuf trampoline_slotbuf
= NULL
;
7413 static xtensa_insnbuf litpool_buf
= NULL
;
7414 static xtensa_insnbuf litpool_slotbuf
= NULL
;
7416 #define TRAMPOLINE_FRAG_SIZE 3000
7419 xtensa_create_trampoline_frag (bfd_boolean needs_jump_around
)
7421 /* Emit a frag where we can place intermediate jump instructions,
7422 in case we need to jump farther than 128K bytes.
7423 Each jump instruction takes three bytes.
7424 We allocate enough for 1000 trampolines in each frag.
7425 If that's not enough, oh well. */
7427 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7428 struct trampoline_frag
*tf
;
7431 int size
= TRAMPOLINE_FRAG_SIZE
;
7433 for ( ; ts
; ts
= ts
->next
)
7435 if (ts
->seg
== now_seg
)
7441 ts
= (struct trampoline_seg
*)xcalloc(sizeof (struct trampoline_seg
), 1);
7442 ts
->next
= trampoline_seg_list
.next
;
7443 trampoline_seg_list
.next
= ts
;
7447 frag_wane (frag_now
);
7449 xtensa_set_frag_assembly_state (frag_now
);
7450 varP
= frag_var (rs_machine_dependent
, size
, size
, RELAX_TRAMPOLINE
, NULL
, 0, NULL
);
7451 fragP
= (fragS
*)(varP
- SIZEOF_STRUCT_FRAG
);
7452 if (trampoline_buf
== NULL
)
7454 trampoline_buf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7455 trampoline_slotbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
7457 tf
= XNEW (struct trampoline_frag
);
7458 tf
->next
= ts
->trampoline_list
.next
;
7459 ts
->trampoline_list
.next
= tf
;
7460 tf
->needs_jump_around
= needs_jump_around
;
7466 static struct trampoline_seg
*
7467 find_trampoline_seg (asection
*seg
)
7469 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7471 for ( ; ts
; ts
= ts
->next
)
7481 void dump_trampolines (void);
7484 dump_trampolines (void)
7486 struct trampoline_seg
*ts
= trampoline_seg_list
.next
;
7488 for ( ; ts
; ts
= ts
->next
)
7490 asection
*seg
= ts
->seg
;
7494 fprintf(stderr
, "SECTION %s\n", seg
->name
);
7495 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
7496 for ( ; tf
; tf
= tf
->next
)
7498 if (tf
->fragP
== NULL
)
7500 fprintf(stderr
, " 0x%08x: fix=%d, jump_around=%s\n",
7501 (int)tf
->fragP
->fr_address
, (int)tf
->fragP
->fr_fix
,
7502 tf
->needs_jump_around
? "T" : "F");
7507 static void dump_litpools (void) __attribute__ ((unused
));
7510 dump_litpools (void)
7512 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7513 struct litpool_frag
*lpf
;
7515 for ( ; lps
; lps
= lps
->next
)
7517 printf("litpool seg %s\n", lps
->seg
->name
);
7518 for ( lpf
= lps
->frag_list
.next
; lpf
->fragP
; lpf
= lpf
->next
)
7520 fragS
*litfrag
= lpf
->fragP
->fr_next
;
7522 while (litfrag
&& litfrag
->fr_subtype
!= RELAX_LITERAL_POOL_END
)
7524 if (litfrag
->fr_fix
== 4)
7526 litfrag
= litfrag
->fr_next
;
7528 printf(" %ld <%d:%d> (%d) [%d]: ",
7529 lpf
->addr
, lpf
->priority
, lpf
->original_priority
,
7530 lpf
->fragP
->fr_line
, count
);
7531 //dump_frag(lpf->fragP);
7537 xtensa_maybe_create_literal_pool_frag (bfd_boolean create
,
7538 bfd_boolean only_if_needed
)
7540 struct litpool_seg
*lps
= litpool_seg_list
.next
;
7542 struct litpool_frag
*lpf
;
7543 bfd_boolean needed
= FALSE
;
7545 if (use_literal_section
|| !auto_litpools
)
7548 for ( ; lps
; lps
= lps
->next
)
7550 if (lps
->seg
== now_seg
)
7556 lps
= (struct litpool_seg
*)xcalloc (sizeof (struct litpool_seg
), 1);
7557 lps
->next
= litpool_seg_list
.next
;
7558 litpool_seg_list
.next
= lps
;
7560 lps
->frag_list
.next
= &lps
->frag_list
;
7561 lps
->frag_list
.prev
= &lps
->frag_list
;
7570 if (past_xtensa_end
|| !use_transform() ||
7571 frag_now
->tc_frag_data
.is_no_transform
)
7575 if (auto_litpool_limit
<= 0)
7577 /* Don't create a litpool based only on frag count. */
7580 else if (lps
->frag_count
> auto_litpool_limit
)
7597 int size
= (only_if_needed
) ? 3 : 0; /* Space for a "j" insn. */
7598 /* Create a potential site for a literal pool. */
7599 frag_wane (frag_now
);
7601 xtensa_set_frag_assembly_state (frag_now
);
7603 fragP
->tc_frag_data
.lit_frchain
= frchain_now
;
7604 fragP
->tc_frag_data
.literal_frag
= fragP
;
7605 frag_var (rs_machine_dependent
, size
, size
,
7607 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
7608 RELAX_LITERAL_POOL_BEGIN
,
7610 frag_now
->tc_frag_data
.lit_seg
= now_seg
;
7611 frag_variant (rs_machine_dependent
, 0, 0,
7612 RELAX_LITERAL_POOL_END
, NULL
, 0, NULL
);
7613 xtensa_set_frag_assembly_state (frag_now
);
7617 /* RELAX_LITERAL_POOL_BEGIN frag is being created;
7618 just record it here. */
7622 lpf
= XNEW (struct litpool_frag
);
7623 /* Insert at tail of circular list. */
7625 lps
->frag_list
.prev
->next
= lpf
;
7626 lpf
->next
= &lps
->frag_list
;
7627 lpf
->prev
= lps
->frag_list
.prev
;
7628 lps
->frag_list
.prev
= lpf
;
7630 lpf
->priority
= (needed
) ? (only_if_needed
) ? 3 : 2 : 1;
7631 lpf
->original_priority
= lpf
->priority
;
7633 lps
->frag_count
= 0;
7637 xtensa_cleanup_align_frags (void)
7642 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7643 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7646 /* Walk over all of the fragments in a subsection. */
7647 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7649 if ((fragP
->fr_type
== rs_align
7650 || fragP
->fr_type
== rs_align_code
7651 || (fragP
->fr_type
== rs_machine_dependent
7652 && (fragP
->fr_subtype
== RELAX_DESIRE_ALIGN
7653 || fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)))
7654 && fragP
->fr_fix
== 0)
7656 fragS
*next
= fragP
->fr_next
;
7659 && next
->fr_fix
== 0
7660 && next
->fr_type
== rs_machine_dependent
7661 && next
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7664 next
= next
->fr_next
;
7667 /* If we don't widen branch targets, then they
7668 will be easier to align. */
7669 if (fragP
->tc_frag_data
.is_branch_target
7670 && fragP
->fr_opcode
== fragP
->fr_literal
7671 && fragP
->fr_type
== rs_machine_dependent
7672 && fragP
->fr_subtype
== RELAX_SLOTS
7673 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
7675 if (fragP
->fr_type
== rs_machine_dependent
7676 && fragP
->fr_subtype
== RELAX_UNREACHABLE
)
7677 fragP
->tc_frag_data
.is_unreachable
= TRUE
;
7683 /* Re-process all of the fragments looking to convert all of the
7684 RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch
7685 target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
7686 Otherwise, convert to a .fill 0. */
7689 xtensa_fix_target_frags (void)
7694 /* When this routine is called, all of the subsections are still intact
7695 so we walk over subsections instead of sections. */
7696 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7697 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7701 /* Walk over all of the fragments in a subsection. */
7702 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7704 if (fragP
->fr_type
== rs_machine_dependent
7705 && fragP
->fr_subtype
== RELAX_DESIRE_ALIGN_IF_TARGET
)
7707 if (next_frag_is_branch_target (fragP
))
7708 fragP
->fr_subtype
= RELAX_DESIRE_ALIGN
;
7717 static bfd_boolean
is_narrow_branch_guaranteed_in_range (fragS
*, TInsn
*);
7720 xtensa_mark_narrow_branches (void)
7725 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7726 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7729 /* Walk over all of the fragments in a subsection. */
7730 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7732 if (fragP
->fr_type
== rs_machine_dependent
7733 && fragP
->fr_subtype
== RELAX_SLOTS
7734 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
7738 vinsn_from_chars (&vinsn
, fragP
->fr_opcode
);
7739 tinsn_immed_from_frag (&vinsn
.slots
[0], fragP
, 0);
7741 if (vinsn
.num_slots
== 1
7742 && xtensa_opcode_is_branch (xtensa_default_isa
,
7743 vinsn
.slots
[0].opcode
) == 1
7744 && xg_get_single_size (vinsn
.slots
[0].opcode
) == 2
7745 && is_narrow_branch_guaranteed_in_range (fragP
,
7748 fragP
->fr_subtype
= RELAX_SLOTS
;
7749 fragP
->tc_frag_data
.slot_subtypes
[0] = RELAX_NARROW
;
7750 fragP
->tc_frag_data
.is_aligning_branch
= 1;
7758 /* A branch is typically widened only when its target is out of
7759 range. However, we would like to widen them to align a subsequent
7760 branch target when possible.
7762 Because the branch relaxation code is so convoluted, the optimal solution
7763 (combining the two cases) is difficult to get right in all circumstances.
7764 We therefore go with an "almost as good" solution, where we only
7765 use for alignment narrow branches that definitely will not expand to a
7766 jump and a branch. These functions find and mark these cases. */
7768 /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded
7769 as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
7770 We start counting beginning with the frag after the 2-byte branch, so the
7771 maximum offset is (4 - 2) + 63 = 65. */
7772 #define MAX_IMMED6 65
7774 static offsetT
unrelaxed_frag_max_size (fragS
*);
7777 is_narrow_branch_guaranteed_in_range (fragS
*fragP
, TInsn
*tinsn
)
7779 const expressionS
*exp
= &tinsn
->tok
[1];
7780 symbolS
*symbolP
= exp
->X_add_symbol
;
7781 offsetT max_distance
= exp
->X_add_number
;
7784 if (exp
->X_op
!= O_symbol
)
7787 target_frag
= symbol_get_frag (symbolP
);
7789 max_distance
+= (S_GET_VALUE (symbolP
) - target_frag
->fr_address
);
7790 if (is_branch_jmp_to_next (tinsn
, fragP
))
7793 /* The branch doesn't branch over it's own frag,
7794 but over the subsequent ones. */
7795 fragP
= fragP
->fr_next
;
7796 while (fragP
!= NULL
&& fragP
!= target_frag
&& max_distance
<= MAX_IMMED6
)
7798 max_distance
+= unrelaxed_frag_max_size (fragP
);
7799 fragP
= fragP
->fr_next
;
7801 if (max_distance
<= MAX_IMMED6
&& fragP
== target_frag
)
7808 xtensa_mark_zcl_first_insns (void)
7813 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7814 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7817 /* Walk over all of the fragments in a subsection. */
7818 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7820 if (fragP
->fr_type
== rs_machine_dependent
7821 && (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7822 || fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7824 /* Find the loop frag. */
7825 fragS
*loop_frag
= next_non_empty_frag (fragP
);
7826 /* Find the first insn frag. */
7827 fragS
*targ_frag
= next_non_empty_frag (loop_frag
);
7829 /* Handle a corner case that comes up in hardware
7830 diagnostics. The original assembly looks like this:
7833 <empty_frag>--not found by next_non_empty_frag
7836 Depending on the start address, the assembler may or
7837 may not change it to look something like this:
7840 nop--frag isn't empty anymore
7843 So set up to check the alignment of the nop if it
7845 while (loop_frag
!= targ_frag
)
7847 if (loop_frag
->fr_type
== rs_machine_dependent
7848 && (loop_frag
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
7849 || loop_frag
->fr_subtype
7850 == RELAX_CHECK_ALIGN_NEXT_OPCODE
))
7851 targ_frag
= loop_frag
;
7853 loop_frag
= loop_frag
->fr_next
;
7856 /* Of course, sometimes (mostly for toy test cases) a
7857 zero-cost loop instruction is the last in a section. */
7860 targ_frag
->tc_frag_data
.is_first_loop_insn
= TRUE
;
7861 /* Do not widen a frag that is the first instruction of a
7862 zero-cost loop. It makes that loop harder to align. */
7863 if (targ_frag
->fr_type
== rs_machine_dependent
7864 && targ_frag
->fr_subtype
== RELAX_SLOTS
7865 && (targ_frag
->tc_frag_data
.slot_subtypes
[0]
7868 if (targ_frag
->tc_frag_data
.is_aligning_branch
)
7869 targ_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
7872 frag_wane (targ_frag
);
7873 targ_frag
->tc_frag_data
.slot_subtypes
[0] = 0;
7877 if (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)
7885 /* When a difference-of-symbols expression is encoded as a uleb128 or
7886 sleb128 value, the linker is unable to adjust that value to account for
7887 link-time relaxation. Mark all the code between such symbols so that
7888 its size cannot be changed by linker relaxation. */
7891 xtensa_mark_difference_of_two_symbols (void)
7895 for (expr_sym
= expr_symbols
; expr_sym
;
7896 expr_sym
= symbol_get_tc (expr_sym
)->next_expr_symbol
)
7898 expressionS
*exp
= symbol_get_value_expression (expr_sym
);
7900 if (exp
->X_op
== O_subtract
)
7902 symbolS
*left
= exp
->X_add_symbol
;
7903 symbolS
*right
= exp
->X_op_symbol
;
7905 /* Difference of two symbols not in the same section
7906 are handled with relocations in the linker. */
7907 if (S_GET_SEGMENT (left
) == S_GET_SEGMENT (right
))
7913 if (symbol_get_frag (left
)->fr_address
7914 <= symbol_get_frag (right
)->fr_address
)
7916 start
= symbol_get_frag (left
);
7917 end
= symbol_get_frag (right
);
7921 start
= symbol_get_frag (right
);
7922 end
= symbol_get_frag (left
);
7925 if (start
->tc_frag_data
.no_transform_end
!= NULL
)
7926 walk
= start
->tc_frag_data
.no_transform_end
;
7931 walk
->tc_frag_data
.is_no_transform
= 1;
7932 walk
= walk
->fr_next
;
7934 while (walk
&& walk
->fr_address
< end
->fr_address
);
7936 start
->tc_frag_data
.no_transform_end
= walk
;
7943 /* Re-process all of the fragments looking to convert all of the
7944 RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a
7945 conditional branch or a retw/retw.n, convert this frag to one that
7946 will generate a NOP. In any case close it off with a .fill 0. */
7948 static bfd_boolean
next_instrs_are_b_retw (fragS
*);
7951 xtensa_fix_a0_b_retw_frags (void)
7956 /* When this routine is called, all of the subsections are still intact
7957 so we walk over subsections instead of sections. */
7958 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
7959 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
7963 /* Walk over all of the fragments in a subsection. */
7964 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
7966 if (fragP
->fr_type
== rs_machine_dependent
7967 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_A0_B_RETW
)
7969 if (next_instrs_are_b_retw (fragP
))
7971 if (fragP
->tc_frag_data
.is_no_transform
)
7972 as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
7974 relax_frag_add_nop (fragP
);
7984 next_instrs_are_b_retw (fragS
*fragP
)
7986 xtensa_opcode opcode
;
7988 const fragS
*next_fragP
= next_non_empty_frag (fragP
);
7989 static xtensa_insnbuf insnbuf
= NULL
;
7990 static xtensa_insnbuf slotbuf
= NULL
;
7991 xtensa_isa isa
= xtensa_default_isa
;
7994 bfd_boolean branch_seen
= FALSE
;
7998 insnbuf
= xtensa_insnbuf_alloc (isa
);
7999 slotbuf
= xtensa_insnbuf_alloc (isa
);
8002 if (next_fragP
== NULL
)
8005 /* Check for the conditional branch. */
8006 xtensa_insnbuf_from_chars
8007 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8008 fmt
= xtensa_format_decode (isa
, insnbuf
);
8009 if (fmt
== XTENSA_UNDEFINED
)
8012 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8014 xtensa_format_get_slot (isa
, fmt
, slot
, insnbuf
, slotbuf
);
8015 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
8017 branch_seen
= (branch_seen
8018 || xtensa_opcode_is_branch (isa
, opcode
) == 1);
8024 offset
+= xtensa_format_length (isa
, fmt
);
8025 if (offset
== next_fragP
->fr_fix
)
8027 next_fragP
= next_non_empty_frag (next_fragP
);
8031 if (next_fragP
== NULL
)
8034 /* Check for the retw/retw.n. */
8035 xtensa_insnbuf_from_chars
8036 (isa
, insnbuf
, (unsigned char *) &next_fragP
->fr_literal
[offset
], 0);
8037 fmt
= xtensa_format_decode (isa
, insnbuf
);
8039 /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
8040 have no problems. */
8041 if (fmt
== XTENSA_UNDEFINED
8042 || xtensa_format_num_slots (isa
, fmt
) != 1)
8045 xtensa_format_get_slot (isa
, fmt
, 0, insnbuf
, slotbuf
);
8046 opcode
= xtensa_opcode_decode (isa
, fmt
, 0, slotbuf
);
8048 if (opcode
== xtensa_retw_opcode
|| opcode
== xtensa_retw_n_opcode
)
8055 /* Re-process all of the fragments looking to convert all of the
8056 RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a
8057 loop end label, convert this frag to one that will generate a NOP.
8058 In any case close it off with a .fill 0. */
8060 static bfd_boolean
next_instr_is_loop_end (fragS
*);
8063 xtensa_fix_b_j_loop_end_frags (void)
8068 /* When this routine is called, all of the subsections are still intact
8069 so we walk over subsections instead of sections. */
8070 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8071 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8075 /* Walk over all of the fragments in a subsection. */
8076 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8078 if (fragP
->fr_type
== rs_machine_dependent
8079 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_PRE_LOOP_END
)
8081 if (next_instr_is_loop_end (fragP
))
8083 if (fragP
->tc_frag_data
.is_no_transform
)
8084 as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
8086 relax_frag_add_nop (fragP
);
8096 next_instr_is_loop_end (fragS
*fragP
)
8098 const fragS
*next_fragP
;
8100 if (next_frag_is_loop_target (fragP
))
8103 next_fragP
= next_non_empty_frag (fragP
);
8104 if (next_fragP
== NULL
)
8107 if (!next_frag_is_loop_target (next_fragP
))
8110 /* If the size is >= 3 then there is more than one instruction here.
8111 The hardware bug will not fire. */
8112 if (next_fragP
->fr_fix
> 3)
8119 /* Re-process all of the fragments looking to convert all of the
8120 RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is
8121 not MY loop's loop end within 12 bytes, add enough nops here to
8122 make it at least 12 bytes away. In any case close it off with a
8125 static offsetT min_bytes_to_other_loop_end
8126 (fragS
*, fragS
*, offsetT
);
8129 xtensa_fix_close_loop_end_frags (void)
8134 /* When this routine is called, all of the subsections are still intact
8135 so we walk over subsections instead of sections. */
8136 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8137 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8141 fragS
*current_target
= NULL
;
8143 /* Walk over all of the fragments in a subsection. */
8144 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8146 if (fragP
->fr_type
== rs_machine_dependent
8147 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8148 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8149 current_target
= symbol_get_frag (fragP
->fr_symbol
);
8152 && fragP
->fr_type
== rs_machine_dependent
8153 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_CLOSE_LOOP_END
)
8156 int bytes_added
= 0;
8158 #define REQUIRED_LOOP_DIVIDING_BYTES 12
8159 /* Max out at 12. */
8160 min_bytes
= min_bytes_to_other_loop_end
8161 (fragP
->fr_next
, current_target
, REQUIRED_LOOP_DIVIDING_BYTES
);
8163 if (min_bytes
< REQUIRED_LOOP_DIVIDING_BYTES
)
8165 if (fragP
->tc_frag_data
.is_no_transform
)
8166 as_bad (_("loop end too close to another loop end may trigger hardware errata"));
8169 while (min_bytes
+ bytes_added
8170 < REQUIRED_LOOP_DIVIDING_BYTES
)
8174 if (fragP
->fr_var
< length
)
8175 as_fatal (_("fr_var %lu < length %d"),
8176 (long) fragP
->fr_var
, length
);
8179 assemble_nop (length
,
8180 fragP
->fr_literal
+ fragP
->fr_fix
);
8181 fragP
->fr_fix
+= length
;
8182 fragP
->fr_var
-= length
;
8184 bytes_added
+= length
;
8190 gas_assert (fragP
->fr_type
!= rs_machine_dependent
8191 || fragP
->fr_subtype
!= RELAX_ADD_NOP_IF_CLOSE_LOOP_END
);
8197 static offsetT
unrelaxed_frag_min_size (fragS
*);
8200 min_bytes_to_other_loop_end (fragS
*fragP
,
8201 fragS
*current_target
,
8205 fragS
*current_fragP
;
8207 for (current_fragP
= fragP
;
8209 current_fragP
= current_fragP
->fr_next
)
8211 if (current_fragP
->tc_frag_data
.is_loop_target
8212 && current_fragP
!= current_target
)
8215 offset
+= unrelaxed_frag_min_size (current_fragP
);
8217 if (offset
>= max_size
)
8225 unrelaxed_frag_min_size (fragS
*fragP
)
8227 offsetT size
= fragP
->fr_fix
;
8229 /* Add fill size. */
8230 if (fragP
->fr_type
== rs_fill
)
8231 size
+= fragP
->fr_offset
;
8238 unrelaxed_frag_max_size (fragS
*fragP
)
8240 offsetT size
= fragP
->fr_fix
;
8241 switch (fragP
->fr_type
)
8244 /* Empty frags created by the obstack allocation scheme
8245 end up with type 0. */
8250 size
+= fragP
->fr_offset
;
8258 /* No further adjustments needed. */
8260 case rs_machine_dependent
:
8261 if (fragP
->fr_subtype
!= RELAX_DESIRE_ALIGN
)
8262 size
+= fragP
->fr_var
;
8265 /* We had darn well better know how big it is. */
8274 /* Re-process all of the fragments looking to convert all
8275 of the RELAX_ADD_NOP_IF_SHORT_LOOP. If:
8278 1) the instruction size count to the loop end label
8279 is too short (<= 2 instructions),
8280 2) loop has a jump or branch in it
8283 1) workaround_all_short_loops is TRUE
8284 2) The generating loop was a 'loopgtz' or 'loopnez'
8285 3) the instruction size count to the loop end label is too short
8287 then convert this frag (and maybe the next one) to generate a NOP.
8288 In any case close it off with a .fill 0. */
8290 static int count_insns_to_loop_end (fragS
*, bfd_boolean
, int);
8291 static bfd_boolean
branch_before_loop_end (fragS
*);
8294 xtensa_fix_short_loop_frags (void)
8299 /* When this routine is called, all of the subsections are still intact
8300 so we walk over subsections instead of sections. */
8301 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8302 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8305 xtensa_opcode current_opcode
= XTENSA_UNDEFINED
;
8307 /* Walk over all of the fragments in a subsection. */
8308 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8310 if (fragP
->fr_type
== rs_machine_dependent
8311 && ((fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
)
8312 || (fragP
->fr_subtype
== RELAX_CHECK_ALIGN_NEXT_OPCODE
)))
8315 fragS
*loop_frag
= next_non_empty_frag (fragP
);
8316 tinsn_from_chars (&t_insn
, loop_frag
->fr_opcode
, 0);
8317 current_opcode
= t_insn
.opcode
;
8318 gas_assert (xtensa_opcode_is_loop (xtensa_default_isa
,
8319 current_opcode
) == 1);
8322 if (fragP
->fr_type
== rs_machine_dependent
8323 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8325 if (count_insns_to_loop_end (fragP
->fr_next
, TRUE
, 3) < 3
8326 && (branch_before_loop_end (fragP
->fr_next
)
8327 || (workaround_all_short_loops
8328 && current_opcode
!= XTENSA_UNDEFINED
8329 && current_opcode
!= xtensa_loop_opcode
)))
8331 if (fragP
->tc_frag_data
.is_no_transform
)
8332 as_bad (_("loop containing less than three instructions may trigger hardware errata"));
8334 relax_frag_add_nop (fragP
);
8343 static int unrelaxed_frag_min_insn_count (fragS
*);
8346 count_insns_to_loop_end (fragS
*base_fragP
,
8347 bfd_boolean count_relax_add
,
8350 fragS
*fragP
= NULL
;
8355 for (; fragP
&& !fragP
->tc_frag_data
.is_loop_target
; fragP
= fragP
->fr_next
)
8357 insn_count
+= unrelaxed_frag_min_insn_count (fragP
);
8358 if (insn_count
>= max_count
)
8361 if (count_relax_add
)
8363 if (fragP
->fr_type
== rs_machine_dependent
8364 && fragP
->fr_subtype
== RELAX_ADD_NOP_IF_SHORT_LOOP
)
8366 /* In order to add the appropriate number of
8367 NOPs, we count an instruction for downstream
8370 if (insn_count
>= max_count
)
8380 unrelaxed_frag_min_insn_count (fragS
*fragP
)
8382 xtensa_isa isa
= xtensa_default_isa
;
8383 static xtensa_insnbuf insnbuf
= NULL
;
8387 if (!fragP
->tc_frag_data
.is_insn
)
8391 insnbuf
= xtensa_insnbuf_alloc (isa
);
8393 /* Decode the fixed instructions. */
8394 while (offset
< fragP
->fr_fix
)
8398 xtensa_insnbuf_from_chars
8399 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8400 fmt
= xtensa_format_decode (isa
, insnbuf
);
8402 if (fmt
== XTENSA_UNDEFINED
)
8404 as_fatal (_("undecodable instruction in instruction frag"));
8407 offset
+= xtensa_format_length (isa
, fmt
);
8415 static bfd_boolean
unrelaxed_frag_has_b_j (fragS
*);
8418 branch_before_loop_end (fragS
*base_fragP
)
8422 for (fragP
= base_fragP
;
8423 fragP
&& !fragP
->tc_frag_data
.is_loop_target
;
8424 fragP
= fragP
->fr_next
)
8426 if (unrelaxed_frag_has_b_j (fragP
))
8434 unrelaxed_frag_has_b_j (fragS
*fragP
)
8436 static xtensa_insnbuf insnbuf
= NULL
;
8437 xtensa_isa isa
= xtensa_default_isa
;
8440 if (!fragP
->tc_frag_data
.is_insn
)
8444 insnbuf
= xtensa_insnbuf_alloc (isa
);
8446 /* Decode the fixed instructions. */
8447 while (offset
< fragP
->fr_fix
)
8452 xtensa_insnbuf_from_chars
8453 (isa
, insnbuf
, (unsigned char *) fragP
->fr_literal
+ offset
, 0);
8454 fmt
= xtensa_format_decode (isa
, insnbuf
);
8455 if (fmt
== XTENSA_UNDEFINED
)
8458 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
8460 xtensa_opcode opcode
=
8461 get_opcode_from_buf (fragP
->fr_literal
+ offset
, slot
);
8462 if (xtensa_opcode_is_branch (isa
, opcode
) == 1
8463 || xtensa_opcode_is_jump (isa
, opcode
) == 1)
8466 offset
+= xtensa_format_length (isa
, fmt
);
8472 /* Checks to be made after initial assembly but before relaxation. */
8474 static bfd_boolean
is_empty_loop (const TInsn
*, fragS
*);
8475 static bfd_boolean
is_local_forward_loop (const TInsn
*, fragS
*);
8478 xtensa_sanity_check (void)
8480 const char *file_name
;
8485 file_name
= as_where (&line
);
8486 for (s
= stdoutput
->sections
; s
; s
= s
->next
)
8487 for (frchP
= seg_info (s
)->frchainP
; frchP
; frchP
= frchP
->frch_next
)
8491 /* Walk over all of the fragments in a subsection. */
8492 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
8494 if (fragP
->fr_type
== rs_machine_dependent
8495 && fragP
->fr_subtype
== RELAX_SLOTS
8496 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_IMMED
)
8498 static xtensa_insnbuf insnbuf
= NULL
;
8501 if (fragP
->fr_opcode
!= NULL
)
8504 insnbuf
= xtensa_insnbuf_alloc (xtensa_default_isa
);
8505 tinsn_from_chars (&t_insn
, fragP
->fr_opcode
, 0);
8506 tinsn_immed_from_frag (&t_insn
, fragP
, 0);
8508 if (xtensa_opcode_is_loop (xtensa_default_isa
,
8509 t_insn
.opcode
) == 1)
8511 if (is_empty_loop (&t_insn
, fragP
))
8513 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8514 as_bad (_("invalid empty loop"));
8516 if (!is_local_forward_loop (&t_insn
, fragP
))
8518 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
8519 as_bad (_("loop target does not follow "
8520 "loop instruction in section"));
8527 new_logical_line (file_name
, line
);
8531 #define LOOP_IMMED_OPN 1
8533 /* Return TRUE if the loop target is the next non-zero fragment. */
8536 is_empty_loop (const TInsn
*insn
, fragS
*fragP
)
8538 const expressionS
*exp
;
8542 if (insn
->insn_type
!= ITYPE_INSN
)
8545 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8548 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8551 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8553 if (exp
->X_op
!= O_symbol
)
8556 symbolP
= exp
->X_add_symbol
;
8560 if (symbol_get_frag (symbolP
) == NULL
)
8563 if (S_GET_VALUE (symbolP
) != 0)
8566 /* Walk through the zero-size fragments from this one. If we find
8567 the target fragment, then this is a zero-size loop. */
8569 for (next_fragP
= fragP
->fr_next
;
8571 next_fragP
= next_fragP
->fr_next
)
8573 if (next_fragP
== symbol_get_frag (symbolP
))
8575 if (next_fragP
->fr_fix
!= 0)
8583 is_local_forward_loop (const TInsn
*insn
, fragS
*fragP
)
8585 const expressionS
*exp
;
8589 if (insn
->insn_type
!= ITYPE_INSN
)
8592 if (xtensa_opcode_is_loop (xtensa_default_isa
, insn
->opcode
) != 1)
8595 if (insn
->ntok
<= LOOP_IMMED_OPN
)
8598 exp
= &insn
->tok
[LOOP_IMMED_OPN
];
8600 if (exp
->X_op
!= O_symbol
)
8603 symbolP
= exp
->X_add_symbol
;
8607 if (symbol_get_frag (symbolP
) == NULL
)
8610 /* Walk through fragments until we find the target.
8611 If we do not find the target, then this is an invalid loop. */
8613 for (next_fragP
= fragP
->fr_next
;
8615 next_fragP
= next_fragP
->fr_next
)
8617 if (next_fragP
== symbol_get_frag (symbolP
))
8625 #define XTINFO_NAME "Xtensa_Info"
8626 #define XTINFO_NAMESZ 12
8627 #define XTINFO_TYPE 1
8630 xtensa_add_config_info (void)
8636 info_sec
= subseg_new (".xtensa.info", 0);
8637 bfd_set_section_flags (stdoutput
, info_sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
8639 data
= XNEWVEC (char, 100);
8640 sprintf (data
, "USE_ABSOLUTE_LITERALS=%d\nABI=%d\n",
8641 XSHAL_USE_ABSOLUTE_LITERALS
, XSHAL_ABI
);
8642 sz
= strlen (data
) + 1;
8644 /* Add enough null terminators to pad to a word boundary. */
8647 while ((sz
& 3) != 0);
8649 /* Follow the standard note section layout:
8650 First write the length of the name string. */
8652 md_number_to_chars (p
, (valueT
) XTINFO_NAMESZ
, 4);
8654 /* Next comes the length of the "descriptor", i.e., the actual data. */
8656 md_number_to_chars (p
, (valueT
) sz
, 4);
8658 /* Write the note type. */
8660 md_number_to_chars (p
, (valueT
) XTINFO_TYPE
, 4);
8662 /* Write the name field. */
8663 p
= frag_more (XTINFO_NAMESZ
);
8664 memcpy (p
, XTINFO_NAME
, XTINFO_NAMESZ
);
8666 /* Finally, write the descriptor. */
8668 memcpy (p
, data
, sz
);
8674 /* Alignment Functions. */
8677 get_text_align_power (unsigned target_size
)
8679 if (target_size
<= 4)
8682 if (target_size
<= 8)
8685 if (target_size
<= 16)
8688 if (target_size
<= 32)
8691 if (target_size
<= 64)
8694 if (target_size
<= 128)
8697 if (target_size
<= 256)
8700 if (target_size
<= 512)
8703 if (target_size
<= 1024)
8712 get_text_align_max_fill_size (int align_pow
,
8713 bfd_boolean use_nops
,
8714 bfd_boolean use_no_density
)
8717 return (1 << align_pow
);
8719 return 3 * (1 << align_pow
);
8721 return 1 + (1 << align_pow
);
8725 /* Calculate the minimum bytes of fill needed at "address" to align a
8726 target instruction of size "target_size" so that it does not cross a
8727 power-of-two boundary specified by "align_pow". If "use_nops" is FALSE,
8728 the fill can be an arbitrary number of bytes. Otherwise, the space must
8729 be filled by NOP instructions. */
8732 get_text_align_fill_size (addressT address
,
8735 bfd_boolean use_nops
,
8736 bfd_boolean use_no_density
)
8738 addressT alignment
, fill
, fill_limit
, fill_step
;
8739 bfd_boolean skip_one
= FALSE
;
8741 alignment
= (1 << align_pow
);
8742 gas_assert (target_size
> 0 && alignment
>= (addressT
) target_size
);
8746 fill_limit
= alignment
;
8749 else if (!use_no_density
)
8751 /* Combine 2- and 3-byte NOPs to fill anything larger than one. */
8752 fill_limit
= alignment
* 2;
8758 /* Fill with 3-byte NOPs -- can only fill multiples of 3. */
8759 fill_limit
= alignment
* 3;
8763 /* Try all fill sizes until finding one that works. */
8764 for (fill
= 0; fill
< fill_limit
; fill
+= fill_step
)
8766 if (skip_one
&& fill
== 1)
8768 if ((address
+ fill
) >> align_pow
8769 == (address
+ fill
+ target_size
- 1) >> align_pow
)
8778 branch_align_power (segT sec
)
8780 /* If the Xtensa processor has a fetch width of X, and
8781 the section is aligned to at least that boundary, then a branch
8782 target need only fit within that aligned block of memory to avoid
8783 a stall. Otherwise, try to fit branch targets within 4-byte
8784 aligned blocks (which may be insufficient, e.g., if the section
8785 has no alignment, but it's good enough). */
8786 int fetch_align
= get_text_align_power(xtensa_fetch_width
);
8787 int sec_align
= get_recorded_alignment (sec
);
8789 if (sec_align
>= fetch_align
)
8796 /* This will assert if it is not possible. */
8799 get_text_align_nop_count (offsetT fill_size
, bfd_boolean use_no_density
)
8805 gas_assert (fill_size
% 3 == 0);
8806 return (fill_size
/ 3);
8809 gas_assert (fill_size
!= 1); /* Bad argument. */
8811 while (fill_size
> 1)
8814 if (fill_size
== 2 || fill_size
== 4)
8816 fill_size
-= insn_size
;
8819 gas_assert (fill_size
!= 1); /* Bad algorithm. */
8825 get_text_align_nth_nop_size (offsetT fill_size
,
8827 bfd_boolean use_no_density
)
8834 gas_assert (fill_size
!= 1); /* Bad argument. */
8836 while (fill_size
> 1)
8839 if (fill_size
== 2 || fill_size
== 4)
8841 fill_size
-= insn_size
;
8851 /* For the given fragment, find the appropriate address
8852 for it to begin at if we are using NOPs to align it. */
8855 get_noop_aligned_address (fragS
*fragP
, addressT address
)
8857 /* The rule is: get next fragment's FIRST instruction. Find
8858 the smallest number of bytes that need to be added to
8859 ensure that the next fragment's FIRST instruction will fit
8862 E.G., 2 bytes : 0, 1, 2 mod 4
8865 If the FIRST instruction MIGHT be relaxed,
8866 assume that it will become a 3-byte instruction.
8868 Note again here that LOOP instructions are not bundleable,
8869 and this relaxation only applies to LOOP opcodes. */
8872 int first_insn_size
;
8874 addressT pre_opcode_bytes
;
8877 xtensa_opcode opcode
;
8878 bfd_boolean is_loop
;
8880 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8881 gas_assert (fragP
->fr_subtype
== RELAX_ALIGN_NEXT_OPCODE
);
8883 /* Find the loop frag. */
8884 first_insn
= next_non_empty_frag (fragP
);
8885 /* Now find the first insn frag. */
8886 first_insn
= next_non_empty_frag (first_insn
);
8888 is_loop
= next_frag_opcode_is_loop (fragP
, &opcode
);
8889 gas_assert (is_loop
);
8890 loop_insn_size
= xg_get_single_size (opcode
);
8892 pre_opcode_bytes
= next_frag_pre_opcode_bytes (fragP
);
8893 pre_opcode_bytes
+= loop_insn_size
;
8895 /* For loops, the alignment depends on the size of the
8896 instruction following the loop, not the LOOP instruction. */
8898 if (first_insn
== NULL
)
8899 first_insn_size
= xtensa_fetch_width
;
8901 first_insn_size
= get_loop_align_size (frag_format_size (first_insn
));
8903 /* If it was 8, then we'll need a larger alignment for the section. */
8904 align_power
= get_text_align_power (first_insn_size
);
8905 record_alignment (now_seg
, align_power
);
8907 fill_size
= get_text_align_fill_size
8908 (address
+ pre_opcode_bytes
, align_power
, first_insn_size
, TRUE
,
8909 fragP
->tc_frag_data
.is_no_density
);
8911 return address
+ fill_size
;
8915 /* 3 mechanisms for relaxing an alignment:
8917 Align to a power of 2.
8918 Align so the next fragment's instruction does not cross a word boundary.
8919 Align the current instruction so that if the next instruction
8920 were 3 bytes, it would not cross a word boundary.
8924 zeros - This is easy; always insert zeros.
8925 nops - 3-byte and 2-byte instructions
8929 >=5 : 3-byte instruction + fn (n-3)
8930 widening - widen previous instructions. */
8933 get_aligned_diff (fragS
*fragP
, addressT address
, offsetT
*max_diff
)
8935 addressT target_address
, loop_insn_offset
;
8937 xtensa_opcode loop_opcode
;
8938 bfd_boolean is_loop
;
8941 offsetT branch_align
;
8944 gas_assert (fragP
->fr_type
== rs_machine_dependent
);
8945 switch (fragP
->fr_subtype
)
8947 case RELAX_DESIRE_ALIGN
:
8948 target_size
= next_frag_format_size (fragP
);
8949 if (target_size
== XTENSA_UNDEFINED
)
8951 align_power
= branch_align_power (now_seg
);
8952 branch_align
= 1 << align_power
;
8953 /* Don't count on the section alignment being as large as the target. */
8954 if (target_size
> branch_align
)
8955 target_size
= branch_align
;
8956 opt_diff
= get_text_align_fill_size (address
, align_power
,
8957 target_size
, FALSE
, FALSE
);
8959 *max_diff
= (opt_diff
+ branch_align
8960 - (target_size
+ ((address
+ opt_diff
) % branch_align
)));
8961 gas_assert (*max_diff
>= opt_diff
);
8964 case RELAX_ALIGN_NEXT_OPCODE
:
8965 /* The next non-empty frag after this one holds the LOOP instruction
8966 that needs to be aligned. The required alignment depends on the
8967 size of the next non-empty frag after the loop frag, i.e., the
8968 first instruction in the loop. */
8969 loop_frag
= next_non_empty_frag (fragP
);
8970 target_size
= get_loop_align_size (next_frag_format_size (loop_frag
));
8971 loop_insn_offset
= 0;
8972 is_loop
= next_frag_opcode_is_loop (fragP
, &loop_opcode
);
8973 gas_assert (is_loop
);
8975 /* If the loop has been expanded then the LOOP instruction
8976 could be at an offset from this fragment. */
8977 if (loop_frag
->tc_frag_data
.slot_subtypes
[0] != RELAX_IMMED
)
8978 loop_insn_offset
= get_expanded_loop_offset (loop_opcode
);
8980 /* In an ideal world, which is what we are shooting for here,
8981 we wouldn't need to use any NOPs immediately prior to the
8982 LOOP instruction. If this approach fails, relax_frag_loop_align
8983 will call get_noop_aligned_address. */
8985 address
+ loop_insn_offset
+ xg_get_single_size (loop_opcode
);
8986 align_power
= get_text_align_power (target_size
);
8987 opt_diff
= get_text_align_fill_size (target_address
, align_power
,
8988 target_size
, FALSE
, FALSE
);
8990 *max_diff
= xtensa_fetch_width
8991 - ((target_address
+ opt_diff
) % xtensa_fetch_width
)
8992 - target_size
+ opt_diff
;
8993 gas_assert (*max_diff
>= opt_diff
);
9004 /* md_relax_frag Hook and Helper Functions. */
9006 static long relax_frag_loop_align (fragS
*, long);
9007 static long relax_frag_for_align (fragS
*, long);
9008 static long relax_frag_immed
9009 (segT
, fragS
*, long, int, xtensa_format
, int, int *, bfd_boolean
);
9011 typedef struct cached_fixup cached_fixupS
;
9020 typedef struct fixup_cache fixup_cacheS
;
9023 cached_fixupS
*fixups
;
9031 static int fixup_order (const void *a
, const void *b
)
9033 const cached_fixupS
*pa
= a
;
9034 const cached_fixupS
*pb
= b
;
9036 if (pa
->addr
== pb
->addr
)
9038 if (pa
->target
== pb
->target
)
9040 if (pa
->fixP
->fx_r_type
== pb
->fixP
->fx_r_type
)
9042 return pa
->fixP
->fx_r_type
< pb
->fixP
->fx_r_type
? -1 : 1;
9044 return pa
->target
- pb
->target
;
9046 return pa
->addr
- pb
->addr
;
9049 static bfd_boolean
xtensa_make_cached_fixup (cached_fixupS
*o
, fixS
*fixP
)
9051 xtensa_isa isa
= xtensa_default_isa
;
9052 int addr
= fixP
->fx_frag
->fr_address
;
9055 symbolS
*s
= fixP
->fx_addsy
;
9058 xtensa_opcode opcode
;
9060 if (fixP
->fx_r_type
< BFD_RELOC_XTENSA_SLOT0_OP
||
9061 fixP
->fx_r_type
> BFD_RELOC_XTENSA_SLOT14_OP
)
9063 target
= S_GET_VALUE (s
);
9064 delta
= target
- addr
;
9066 if (abs(delta
) < J_RANGE
/ 2)
9069 xtensa_insnbuf_from_chars (isa
, trampoline_buf
,
9070 (unsigned char *) fixP
->fx_frag
->fr_literal
+
9072 fmt
= xtensa_format_decode (isa
, trampoline_buf
);
9073 gas_assert (fmt
!= XTENSA_UNDEFINED
);
9074 slot
= fixP
->tc_fix_data
.slot
;
9075 xtensa_format_get_slot (isa
, fmt
, slot
, trampoline_buf
, trampoline_slotbuf
);
9076 opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, trampoline_slotbuf
);
9077 if (opcode
!= xtensa_j_opcode
)
9088 static void xtensa_realloc_fixup_cache (fixup_cacheS
*cache
, unsigned add
)
9090 if (cache
->n_fixups
+ add
> cache
->n_max
)
9092 cache
->n_max
= (cache
->n_fixups
+ add
) * 2;
9093 cache
->fixups
= XRESIZEVEC (cached_fixupS
, cache
->fixups
, cache
->n_max
);
9097 static void xtensa_cache_relaxable_fixups (fixup_cacheS
*cache
,
9098 segment_info_type
*seginfo
)
9102 cache
->n_fixups
= 0;
9104 for (fixP
= seginfo
->fix_root
; fixP
; fixP
= fixP
->fx_next
)
9106 xtensa_realloc_fixup_cache (cache
, 1);
9108 if (xtensa_make_cached_fixup (cache
->fixups
+ cache
->n_fixups
, fixP
))
9111 qsort (cache
->fixups
, cache
->n_fixups
, sizeof (*cache
->fixups
), fixup_order
);
9114 static unsigned xtensa_find_first_cached_fixup (const fixup_cacheS
*cache
,
9118 unsigned b
= cache
->n_fixups
;
9122 unsigned c
= (a
+ b
) / 2;
9124 if (cache
->fixups
[c
].addr
< addr
)
9132 static void xtensa_delete_cached_fixup (fixup_cacheS
*cache
, unsigned i
)
9134 memmove (cache
->fixups
+ i
, cache
->fixups
+ i
+ 1,
9135 (cache
->n_fixups
- i
- 1) * sizeof (*cache
->fixups
));
9139 static bfd_boolean
xtensa_add_cached_fixup (fixup_cacheS
*cache
, fixS
*fixP
)
9144 if (!xtensa_make_cached_fixup (&o
, fixP
))
9146 xtensa_realloc_fixup_cache (cache
, 1);
9147 i
= xtensa_find_first_cached_fixup (cache
, o
.addr
);
9148 if (i
< cache
->n_fixups
)
9151 memmove (cache
->fixups
+ i
+ 1, cache
->fixups
+ i
,
9152 (cache
->n_fixups
- i
) * sizeof (*cache
->fixups
));
9154 cache
->fixups
[i
] = o
;
9159 /* Return the number of bytes added to this fragment, given that the
9160 input has been stretched already by "stretch". */
9163 xtensa_relax_frag (fragS
*fragP
, long stretch
, int *stretched_p
)
9165 xtensa_isa isa
= xtensa_default_isa
;
9166 int unreported
= fragP
->tc_frag_data
.unreported_expansion
;
9167 long new_stretch
= 0;
9168 const char *file_name
;
9171 static xtensa_insnbuf vbuf
= NULL
;
9172 int slot
, num_slots
;
9175 file_name
= as_where (&line
);
9176 new_logical_line (fragP
->fr_file
, fragP
->fr_line
);
9178 fragP
->tc_frag_data
.unreported_expansion
= 0;
9180 switch (fragP
->fr_subtype
)
9182 case RELAX_ALIGN_NEXT_OPCODE
:
9183 /* Always convert. */
9184 if (fragP
->tc_frag_data
.relax_seen
)
9185 new_stretch
= relax_frag_loop_align (fragP
, stretch
);
9188 case RELAX_LOOP_END
:
9192 case RELAX_LOOP_END_ADD_NOP
:
9193 /* Add a NOP and switch to .fill 0. */
9194 new_stretch
= relax_frag_add_nop (fragP
);
9198 case RELAX_DESIRE_ALIGN
:
9199 /* Do nothing. The narrowing before this frag will either align
9204 case RELAX_LITERAL_FINAL
:
9207 case RELAX_LITERAL_NR
:
9209 fragP
->fr_subtype
= RELAX_LITERAL_FINAL
;
9210 gas_assert (unreported
== lit_size
);
9211 memset (&fragP
->fr_literal
[fragP
->fr_fix
], 0, 4);
9212 fragP
->fr_var
-= lit_size
;
9213 fragP
->fr_fix
+= lit_size
;
9219 vbuf
= xtensa_insnbuf_alloc (isa
);
9221 xtensa_insnbuf_from_chars
9222 (isa
, vbuf
, (unsigned char *) fragP
->fr_opcode
, 0);
9223 fmt
= xtensa_format_decode (isa
, vbuf
);
9224 num_slots
= xtensa_format_num_slots (isa
, fmt
);
9226 for (slot
= 0; slot
< num_slots
; slot
++)
9228 switch (fragP
->tc_frag_data
.slot_subtypes
[slot
])
9231 if (fragP
->tc_frag_data
.relax_seen
)
9232 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9236 case RELAX_IMMED_STEP1
:
9237 case RELAX_IMMED_STEP2
:
9238 case RELAX_IMMED_STEP3
:
9239 /* Place the immediate. */
9240 new_stretch
+= relax_frag_immed
9241 (now_seg
, fragP
, stretch
,
9242 fragP
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
9243 fmt
, slot
, stretched_p
, FALSE
);
9247 /* This is OK; see the note in xg_assemble_vliw_tokens. */
9253 case RELAX_LITERAL_POOL_BEGIN
:
9254 if (fragP
->fr_var
!= 0)
9256 /* We have a converted "candidate" literal pool;
9257 assemble a jump around it. */
9259 if (!litpool_slotbuf
)
9261 litpool_buf
= xtensa_insnbuf_alloc (isa
);
9262 litpool_slotbuf
= xtensa_insnbuf_alloc (isa
);
9265 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9266 fragP
->tc_frag_data
.is_insn
= TRUE
;
9268 insn
.insn_type
= ITYPE_INSN
;
9269 insn
.opcode
= xtensa_j_opcode
;
9271 set_expr_symbol_offset (&insn
.tok
[0], fragP
->fr_symbol
,
9273 fmt
= xg_get_single_format (xtensa_j_opcode
);
9274 tinsn_to_slotbuf (fmt
, 0, &insn
, litpool_slotbuf
);
9275 xtensa_format_set_slot (isa
, fmt
, 0, litpool_buf
, litpool_slotbuf
);
9276 xtensa_insnbuf_to_chars (isa
, litpool_buf
,
9277 (unsigned char *)fragP
->fr_literal
+
9282 fix_new (fragP
, 0, 3, fragP
->fr_symbol
, 0, TRUE
,
9283 BFD_RELOC_XTENSA_SLOT0_OP
);
9287 case RELAX_LITERAL_POOL_END
:
9288 case RELAX_LITERAL_POOL_CANDIDATE_BEGIN
:
9289 case RELAX_MAYBE_UNREACHABLE
:
9290 case RELAX_MAYBE_DESIRE_ALIGN
:
9291 /* No relaxation required. */
9294 case RELAX_FILL_NOP
:
9295 case RELAX_UNREACHABLE
:
9296 if (fragP
->tc_frag_data
.relax_seen
)
9297 new_stretch
+= relax_frag_for_align (fragP
, stretch
);
9300 case RELAX_TRAMPOLINE
:
9301 if (fragP
->tc_frag_data
.relax_seen
)
9303 static fixup_cacheS fixup_cache
;
9304 segment_info_type
*seginfo
= seg_info (now_seg
);
9305 int trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9306 int searchaddr
= trampaddr
< J_RANGE
? 0 : trampaddr
- J_RANGE
;
9309 if (now_seg
!= fixup_cache
.seg
||
9310 fragP
== fixup_cache
.first_frag
||
9311 fixup_cache
.first_frag
== NULL
)
9313 xtensa_cache_relaxable_fixups (&fixup_cache
, seginfo
);
9314 fixup_cache
.seg
= now_seg
;
9315 fixup_cache
.first_frag
= fragP
;
9318 /* Scan for jumps that will not reach. */
9319 for (i
= xtensa_find_first_cached_fixup (&fixup_cache
, searchaddr
);
9320 i
< fixup_cache
.n_fixups
; ++i
)
9323 fixS
*fixP
= fixup_cache
.fixups
[i
].fixP
;
9324 int target
= fixup_cache
.fixups
[i
].target
;
9325 int addr
= fixup_cache
.fixups
[i
].addr
;
9326 int delta
= fixup_cache
.fixups
[i
].delta
+ stretch
;
9328 trampaddr
= fragP
->fr_address
+ fragP
->fr_fix
;
9330 if (addr
+ J_RANGE
< trampaddr
)
9332 if (addr
> trampaddr
+ J_RANGE
)
9334 if (abs (delta
) < J_RANGE
)
9337 slot
= fixP
->tc_fix_data
.slot
;
9339 if (delta
> J_RANGE
|| delta
< -1 * J_RANGE
)
9340 { /* Found an out-of-range jump; scan the list of trampolines for the best match. */
9341 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9342 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9343 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9344 int lower
= (target
< addr
) ? target
: addr
;
9345 int upper
= (target
> addr
) ? target
: addr
;
9346 int midpoint
= lower
+ (upper
- lower
) / 2;
9348 if ((upper
- lower
) > 2 * J_RANGE
)
9350 /* One trampoline won't suffice; we need multiple jumps.
9351 Jump to the trampoline that's farthest, but still in
9352 range relative to the original "j" instruction. */
9353 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9355 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9356 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0 ;
9361 if (this_addr
- addr
< J_RANGE
)
9366 /* Backward jump. */
9367 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9374 struct trampoline_frag
*best_tf
= NULL
;
9377 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9379 int this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9380 int this_delta
= abs (this_addr
- midpoint
);
9382 if (!best_tf
|| this_delta
< best_delta
)
9385 best_delta
= this_delta
;
9390 if (tf
->fragP
== fragP
)
9392 if (abs (addr
- trampaddr
) < J_RANGE
)
9393 { /* The trampoline is in range of original; fix it! */
9398 fragS
*fP
; /* The out-of-range jump. */
9400 new_stretch
+= init_trampoline_frag (tf
);
9401 offset
= fragP
->fr_fix
; /* Where to assemble the j insn. */
9402 lsym
= fragP
->fr_symbol
;
9404 /* Assemble a jump to the target label here. */
9406 insn
.insn_type
= ITYPE_INSN
;
9407 insn
.opcode
= xtensa_j_opcode
;
9409 set_expr_symbol_offset (&insn
.tok
[0], lsym
, offset
);
9410 fmt
= xg_get_single_format (xtensa_j_opcode
);
9411 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
9412 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
9413 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fragP
->fr_literal
+ offset
, 3);
9416 /* Add a fix-up for the original j insn. */
9417 newfixP
= fix_new (fP
, fixP
->fx_where
, fixP
->fx_size
, lsym
, fragP
->fr_fix
- 3, TRUE
, fixP
->fx_r_type
);
9418 newfixP
->fx_no_overflow
= 1;
9419 newfixP
->tc_fix_data
.X_add_symbol
= lsym
;
9420 newfixP
->tc_fix_data
.X_add_number
= offset
;
9421 newfixP
->tc_fix_data
.slot
= slot
;
9423 xtensa_delete_cached_fixup (&fixup_cache
, i
);
9424 xtensa_add_cached_fixup (&fixup_cache
, newfixP
);
9426 /* Move the fix-up from the original j insn to this one. */
9427 fixP
->fx_frag
= fragP
;
9428 fixP
->fx_where
= fragP
->fr_fix
- 3;
9429 fixP
->tc_fix_data
.slot
= 0;
9431 xtensa_add_cached_fixup (&fixup_cache
, fixP
);
9433 /* re-do current fixup */
9436 /* Adjust the jump around this trampoline (if present). */
9437 if (tf
->fixP
!= NULL
)
9439 tf
->fixP
->fx_offset
+= 3;
9442 fragP
->tc_frag_data
.relax_seen
= FALSE
; /* Need another pass. */
9443 /* Do we have room for more? */
9444 if (fragP
->fr_var
< 3)
9445 { /* No, convert to fill. */
9447 fragP
->fr_subtype
= 0;
9448 /* Remove from the trampoline_list. */
9449 prev
->next
= tf
->next
;
9450 if (fragP
== fixup_cache
.first_frag
)
9451 fixup_cache
.first_frag
= NULL
;
9462 as_bad (_("bad relaxation state"));
9465 /* Tell gas we need another relaxation pass. */
9466 if (! fragP
->tc_frag_data
.relax_seen
)
9468 fragP
->tc_frag_data
.relax_seen
= TRUE
;
9472 new_logical_line (file_name
, line
);
9478 relax_frag_loop_align (fragS
*fragP
, long stretch
)
9480 addressT old_address
, old_next_address
, old_size
;
9481 addressT new_address
, new_next_address
, new_size
;
9484 /* All the frags with relax_frag_for_alignment prior to this one in the
9485 section have been done, hopefully eliminating the need for a NOP here.
9486 But, this will put it in if necessary. */
9488 /* Calculate the old address of this fragment and the next fragment. */
9489 old_address
= fragP
->fr_address
- stretch
;
9490 old_next_address
= (fragP
->fr_address
- stretch
+ fragP
->fr_fix
+
9491 fragP
->tc_frag_data
.text_expansion
[0]);
9492 old_size
= old_next_address
- old_address
;
9494 /* Calculate the new address of this fragment and the next fragment. */
9495 new_address
= fragP
->fr_address
;
9497 get_noop_aligned_address (fragP
, fragP
->fr_address
+ fragP
->fr_fix
);
9498 new_size
= new_next_address
- new_address
;
9500 growth
= new_size
- old_size
;
9502 /* Fix up the text_expansion field and return the new growth. */
9503 fragP
->tc_frag_data
.text_expansion
[0] += growth
;
9508 /* Add a NOP instruction. */
9511 relax_frag_add_nop (fragS
*fragP
)
9513 char *nop_buf
= fragP
->fr_literal
+ fragP
->fr_fix
;
9514 int length
= fragP
->tc_frag_data
.is_no_density
? 3 : 2;
9515 assemble_nop (length
, nop_buf
);
9516 fragP
->tc_frag_data
.is_insn
= TRUE
;
9518 if (fragP
->fr_var
< length
)
9520 as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP
->fr_var
, length
);
9524 fragP
->fr_fix
+= length
;
9525 fragP
->fr_var
-= length
;
9530 static long future_alignment_required (fragS
*, long);
9533 relax_frag_for_align (fragS
*fragP
, long stretch
)
9535 /* Overview of the relaxation procedure for alignment:
9536 We can widen with NOPs or by widening instructions or by filling
9537 bytes after jump instructions. Find the opportune places and widen
9538 them if necessary. */
9543 gas_assert (fragP
->fr_subtype
== RELAX_FILL_NOP
9544 || fragP
->fr_subtype
== RELAX_UNREACHABLE
9545 || (fragP
->fr_subtype
== RELAX_SLOTS
9546 && fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
));
9548 stretch_me
= future_alignment_required (fragP
, stretch
);
9549 diff
= stretch_me
- fragP
->tc_frag_data
.text_expansion
[0];
9555 /* We expanded on a previous pass. Can we shrink now? */
9556 long shrink
= fragP
->tc_frag_data
.text_expansion
[0] - stretch_me
;
9557 if (shrink
<= stretch
&& stretch
> 0)
9559 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9565 /* Below here, diff > 0. */
9566 fragP
->tc_frag_data
.text_expansion
[0] = stretch_me
;
9572 /* Return the address of the next frag that should be aligned.
9574 By "address" we mean the address it _would_ be at if there
9575 is no action taken to align it between here and the target frag.
9576 In other words, if no narrows and no fill nops are used between
9577 here and the frag to align, _even_if_ some of the frags we use
9578 to align targets have already expanded on a previous relaxation
9581 Also, count each frag that may be used to help align the target.
9583 Return 0 if there are no frags left in the chain that need to be
9587 find_address_of_next_align_frag (fragS
**fragPP
,
9591 bfd_boolean
*paddable
)
9593 fragS
*fragP
= *fragPP
;
9594 addressT address
= fragP
->fr_address
;
9596 /* Do not reset the counts to 0. */
9600 /* Limit this to a small search. */
9601 if (*widens
>= (int) xtensa_fetch_width
)
9606 address
+= fragP
->fr_fix
;
9608 if (fragP
->fr_type
== rs_fill
)
9609 address
+= fragP
->fr_offset
* fragP
->fr_var
;
9610 else if (fragP
->fr_type
== rs_machine_dependent
)
9612 switch (fragP
->fr_subtype
)
9614 case RELAX_UNREACHABLE
:
9618 case RELAX_FILL_NOP
:
9620 if (!fragP
->tc_frag_data
.is_no_density
)
9625 if (fragP
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9630 address
+= total_frag_text_expansion (fragP
);
9634 address
+= fragP
->tc_frag_data
.text_expansion
[0];
9637 case RELAX_ALIGN_NEXT_OPCODE
:
9638 case RELAX_DESIRE_ALIGN
:
9642 case RELAX_MAYBE_UNREACHABLE
:
9643 case RELAX_MAYBE_DESIRE_ALIGN
:
9648 /* Just punt if we don't know the type. */
9655 /* Just punt if we don't know the type. */
9659 fragP
= fragP
->fr_next
;
9667 static long bytes_to_stretch (fragS
*, int, int, int, int);
9670 future_alignment_required (fragS
*fragP
, long stretch ATTRIBUTE_UNUSED
)
9672 fragS
*this_frag
= fragP
;
9676 int narrow_nops
= 0;
9677 bfd_boolean paddable
= FALSE
;
9678 offsetT local_opt_diff
;
9681 int stretch_amount
= 0;
9682 int local_stretch_amount
;
9683 int global_stretch_amount
;
9685 address
= find_address_of_next_align_frag
9686 (&fragP
, &wide_nops
, &narrow_nops
, &num_widens
, &paddable
);
9690 if (this_frag
->tc_frag_data
.is_aligning_branch
)
9691 this_frag
->tc_frag_data
.slot_subtypes
[0] = RELAX_IMMED
;
9693 frag_wane (this_frag
);
9697 local_opt_diff
= get_aligned_diff (fragP
, address
, &max_diff
);
9698 opt_diff
= local_opt_diff
;
9699 gas_assert (opt_diff
>= 0);
9700 gas_assert (max_diff
>= opt_diff
);
9705 fragP
= fragP
->fr_next
;
9707 while (fragP
&& opt_diff
< max_diff
&& address
)
9709 /* We only use these to determine if we can exit early
9710 because there will be plenty of ways to align future
9712 int glob_widens
= 0;
9715 bfd_boolean glob_pad
= 0;
9716 address
= find_address_of_next_align_frag
9717 (&fragP
, &glob_widens
, &dnn
, &dw
, &glob_pad
);
9718 /* If there is a padable portion, then skip. */
9719 if (glob_pad
|| glob_widens
>= (1 << branch_align_power (now_seg
)))
9724 offsetT next_m_diff
;
9725 offsetT next_o_diff
;
9727 /* Downrange frags haven't had stretch added to them yet. */
9730 /* The address also includes any text expansion from this
9731 frag in a previous pass, but we don't want that. */
9732 address
-= this_frag
->tc_frag_data
.text_expansion
[0];
9734 /* Assume we are going to move at least opt_diff. In
9735 reality, we might not be able to, but assuming that
9736 we will helps catch cases where moving opt_diff pushes
9737 the next target from aligned to unaligned. */
9738 address
+= opt_diff
;
9740 next_o_diff
= get_aligned_diff (fragP
, address
, &next_m_diff
);
9742 /* Now cleanup for the adjustments to address. */
9743 next_o_diff
+= opt_diff
;
9744 next_m_diff
+= opt_diff
;
9745 if (next_o_diff
<= max_diff
&& next_o_diff
> opt_diff
)
9746 opt_diff
= next_o_diff
;
9747 if (next_m_diff
< max_diff
)
9748 max_diff
= next_m_diff
;
9749 fragP
= fragP
->fr_next
;
9753 /* If there are enough wideners in between, do it. */
9756 if (this_frag
->fr_subtype
== RELAX_UNREACHABLE
)
9758 gas_assert (opt_diff
<= (signed) xtensa_fetch_width
);
9763 local_stretch_amount
9764 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9765 num_widens
, local_opt_diff
);
9766 global_stretch_amount
9767 = bytes_to_stretch (this_frag
, wide_nops
, narrow_nops
,
9768 num_widens
, opt_diff
);
9769 /* If the condition below is true, then the frag couldn't
9770 stretch the correct amount for the global case, so we just
9771 optimize locally. We'll rely on the subsequent frags to get
9772 the correct alignment in the global case. */
9773 if (global_stretch_amount
< local_stretch_amount
)
9774 stretch_amount
= local_stretch_amount
;
9776 stretch_amount
= global_stretch_amount
;
9778 if (this_frag
->fr_subtype
== RELAX_SLOTS
9779 && this_frag
->tc_frag_data
.slot_subtypes
[0] == RELAX_NARROW
)
9780 gas_assert (stretch_amount
<= 1);
9781 else if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9783 if (this_frag
->tc_frag_data
.is_no_density
)
9784 gas_assert (stretch_amount
== 3 || stretch_amount
== 0);
9786 gas_assert (stretch_amount
<= 3);
9789 return stretch_amount
;
9793 /* The idea: widen everything you can to get a target or loop aligned,
9794 then start using NOPs.
9796 wide_nops = the number of wide NOPs available for aligning
9797 narrow_nops = the number of narrow NOPs available for aligning
9798 (a subset of wide_nops)
9799 widens = the number of narrow instructions that should be widened
9804 bytes_to_stretch (fragS
*this_frag
,
9813 int bytes_short
= desired_diff
- num_widens
;
9815 gas_assert (desired_diff
>= 0
9816 && desired_diff
< (signed) xtensa_fetch_width
);
9817 if (desired_diff
== 0)
9820 gas_assert (wide_nops
> 0 || num_widens
> 0);
9822 /* Always prefer widening to NOP-filling. */
9823 if (bytes_short
< 0)
9825 /* There are enough RELAX_NARROW frags after this one
9826 to align the target without widening this frag in any way. */
9830 if (bytes_short
== 0)
9832 /* Widen every narrow between here and the align target
9833 and the align target will be properly aligned. */
9834 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9840 /* From here we will need at least one NOP to get an alignment.
9841 However, we may not be able to align at all, in which case,
9843 nops_needed
= desired_diff
/ 3;
9845 /* If there aren't enough nops, don't widen. */
9846 if (nops_needed
> wide_nops
)
9849 /* First try it with all wide nops. */
9850 nop_bytes
= nops_needed
* 3;
9851 extra_bytes
= desired_diff
- nop_bytes
;
9853 if (nop_bytes
+ num_widens
>= desired_diff
)
9855 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9857 else if (num_widens
== extra_bytes
)
9862 /* Add a narrow nop. */
9866 if (narrow_nops
== 0 || nops_needed
> wide_nops
)
9869 if (nop_bytes
+ num_widens
>= desired_diff
&& extra_bytes
>= 0)
9871 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9872 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9873 else if (num_widens
== extra_bytes
)
9878 /* Replace a wide nop with a narrow nop--we can get here if
9879 extra_bytes was negative in the previous conditional. */
9880 if (narrow_nops
== 1)
9884 if (nop_bytes
+ num_widens
>= desired_diff
)
9886 if (this_frag
->fr_subtype
== RELAX_FILL_NOP
)
9887 return !this_frag
->tc_frag_data
.is_no_density
? 2 : 3;
9888 else if (num_widens
== extra_bytes
)
9893 /* If we can't satisfy any of the above cases, then we can't align
9894 using padding or fill nops. */
9899 static struct trampoline_frag
*
9900 search_trampolines (TInsn
*tinsn
, fragS
*fragP
, bfd_boolean unreachable_only
)
9902 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9903 struct trampoline_frag
*tf
= (ts
) ? ts
->trampoline_list
.next
: NULL
;
9904 struct trampoline_frag
*best_tf
= NULL
;
9907 symbolS
*sym
= tinsn
->tok
[0].X_add_symbol
;
9908 offsetT target
= S_GET_VALUE (sym
) + tinsn
->tok
[0].X_add_number
;
9909 offsetT addr
= fragP
->fr_address
;
9910 offsetT lower
= (addr
< target
) ? addr
: target
;
9911 offsetT upper
= (addr
> target
) ? addr
: target
;
9912 int delta
= upper
- lower
;
9913 offsetT midpoint
= lower
+ delta
/ 2;
9914 int this_delta
= -1;
9917 if (delta
> 2 * J_RANGE
)
9919 /* One trampoline won't do; we need multiple.
9920 Choose the farthest trampoline that's still in range of the original
9921 and let a later pass finish the job. */
9922 for ( ; tf
; tf
= tf
->next
)
9924 int next_addr
= (tf
->next
) ? tf
->next
->fragP
->fr_address
+ tf
->next
->fragP
->fr_fix
: 0;
9926 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9930 if (this_addr
- addr
< J_RANGE
)
9935 /* Backward jump. */
9936 if (next_addr
== 0 || addr
- next_addr
> J_RANGE
)
9940 if (abs (addr
- this_addr
) < J_RANGE
)
9945 for ( ; tf
; tf
= tf
->next
)
9947 this_addr
= tf
->fragP
->fr_address
+ tf
->fragP
->fr_fix
;
9948 this_delta
= abs (this_addr
- midpoint
);
9949 if (unreachable_only
&& tf
->needs_jump_around
)
9951 if (!best_tf
|| this_delta
< best_delta
)
9954 best_delta
= this_delta
;
9955 best_addr
= this_addr
;
9960 best_delta
< J_RANGE
&&
9961 abs(best_addr
- lower
) < J_RANGE
&&
9962 abs(best_addr
- upper
) < J_RANGE
)
9965 return NULL
; /* No suitable trampoline found. */
9969 static struct trampoline_frag
*
9970 get_best_trampoline (TInsn
*tinsn
, fragS
*fragP
)
9972 struct trampoline_frag
*tf
= NULL
;
9974 tf
= search_trampolines (tinsn
, fragP
, TRUE
); /* Try unreachable first. */
9977 tf
= search_trampolines (tinsn
, fragP
, FALSE
); /* Try ones needing a jump-around, too. */
9984 check_and_update_trampolines (void)
9986 struct trampoline_seg
*ts
= find_trampoline_seg (now_seg
);
9987 struct trampoline_frag
*tf
= ts
->trampoline_list
.next
;
9988 struct trampoline_frag
*prev
= &ts
->trampoline_list
;
9990 for ( ; tf
; prev
= tf
, tf
= tf
->next
)
9992 if (tf
->fragP
->fr_var
< 3)
9994 frag_wane (tf
->fragP
);
9995 prev
->next
= tf
->next
;
10003 init_trampoline_frag (struct trampoline_frag
*trampP
)
10005 fragS
*fp
= trampP
->fragP
;
10008 if (fp
->fr_fix
== 0)
10011 char label
[10 + 2 * sizeof(fp
)];
10012 sprintf (label
, ".L0_TR_%p", fp
);
10014 lsym
= (symbolS
*)local_symbol_make (label
, now_seg
, 0, fp
);
10015 fp
->fr_symbol
= lsym
;
10016 if (trampP
->needs_jump_around
)
10018 /* Add a jump around this block of jumps, in case
10019 control flows into this block. */
10023 xtensa_isa isa
= xtensa_default_isa
;
10025 fp
->tc_frag_data
.is_insn
= 1;
10026 /* Assemble a jump insn. */
10027 tinsn_init (&insn
);
10028 insn
.insn_type
= ITYPE_INSN
;
10029 insn
.opcode
= xtensa_j_opcode
;
10031 set_expr_symbol_offset (&insn
.tok
[0], lsym
, 3);
10032 fmt
= xg_get_single_format (xtensa_j_opcode
);
10033 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10034 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10035 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)fp
->fr_literal
, 3);
10039 fixP
= fix_new (fp
, 0, 3, lsym
, 3, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10040 trampP
->fixP
= fixP
;
10048 add_jump_to_trampoline (struct trampoline_frag
*trampP
, fragS
*origfrag
)
10050 fragS
*tramp
= trampP
->fragP
;
10052 int offset
= tramp
->fr_fix
; /* Where to assemble the j insn. */
10058 xtensa_isa isa
= xtensa_default_isa
;
10061 lsym
= tramp
->fr_symbol
;
10062 /* Assemble a jump to the target label in the trampoline frag. */
10063 tsym
= origfrag
->tc_frag_data
.slot_symbols
[0];
10064 toffset
= origfrag
-> tc_frag_data
.slot_offsets
[0];
10065 tinsn_init (&insn
);
10066 insn
.insn_type
= ITYPE_INSN
;
10067 insn
.opcode
= xtensa_j_opcode
;
10069 set_expr_symbol_offset (&insn
.tok
[0], tsym
, toffset
);
10070 fmt
= xg_get_single_format (xtensa_j_opcode
);
10071 tinsn_to_slotbuf (fmt
, 0, &insn
, trampoline_slotbuf
);
10072 xtensa_format_set_slot (isa
, fmt
, 0, trampoline_buf
, trampoline_slotbuf
);
10073 xtensa_insnbuf_to_chars (isa
, trampoline_buf
, (unsigned char *)tramp
->fr_literal
+ offset
, 3);
10074 tramp
->fr_fix
+= 3;
10075 tramp
->fr_var
-= 3;
10077 /* add a fix-up for the trampoline jump. */
10078 fixP
= fix_new (tramp
, tramp
->fr_fix
- 3, 3, tsym
, toffset
, TRUE
, BFD_RELOC_XTENSA_SLOT0_OP
);
10079 /* Modify the jump at the start of this trampoline to point past the newly-added jump. */
10080 fixP
= trampP
->fixP
;
10082 fixP
->fx_offset
+= 3;
10083 /* Modify the original j to point here. */
10084 origfrag
->tc_frag_data
.slot_symbols
[0] = lsym
;
10085 origfrag
->tc_frag_data
.slot_offsets
[0] = tramp
->fr_fix
- 3;
10086 /* If trampoline is full, remove it from the list. */
10087 check_and_update_trampolines ();
10094 relax_frag_immed (segT segP
,
10101 bfd_boolean estimate_only
)
10105 bfd_boolean negatable_branch
= FALSE
;
10106 bfd_boolean branch_jmp_to_next
= FALSE
;
10107 bfd_boolean from_wide_insn
= FALSE
;
10108 xtensa_isa isa
= xtensa_default_isa
;
10110 offsetT frag_offset
;
10112 int num_text_bytes
, num_literal_bytes
;
10113 int literal_diff
, total_text_diff
, this_text_diff
;
10115 gas_assert (fragP
->fr_opcode
!= NULL
);
10117 xg_clear_vinsn (&cur_vinsn
);
10118 vinsn_from_chars (&cur_vinsn
, fragP
->fr_opcode
);
10119 if (cur_vinsn
.num_slots
> 1)
10120 from_wide_insn
= TRUE
;
10122 tinsn
= cur_vinsn
.slots
[slot
];
10123 tinsn_immed_from_frag (&tinsn
, fragP
, slot
);
10125 if (estimate_only
&& xtensa_opcode_is_loop (isa
, tinsn
.opcode
) == 1)
10128 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10129 branch_jmp_to_next
= is_branch_jmp_to_next (&tinsn
, fragP
);
10131 negatable_branch
= (xtensa_opcode_is_branch (isa
, tinsn
.opcode
) == 1);
10133 old_size
= xtensa_format_length (isa
, fmt
);
10135 /* Special case: replace a branch to the next instruction with a NOP.
10136 This is required to work around a hardware bug in T1040.0 and also
10137 serves as an optimization. */
10139 if (branch_jmp_to_next
10140 && ((old_size
== 2) || (old_size
== 3))
10141 && !next_frag_is_loop_target (fragP
))
10144 /* Here is the fun stuff: Get the immediate field from this
10145 instruction. If it fits, we are done. If not, find the next
10146 instruction sequence that fits. */
10148 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10149 istack_init (&istack
);
10150 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
, frag_offset
,
10151 min_steps
, stretch
);
10152 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10154 fragP
->tc_frag_data
.slot_subtypes
[slot
] = (int) RELAX_IMMED
+ num_steps
;
10156 /* Figure out the number of bytes needed. */
10157 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10159 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10160 num_text_bytes
= get_num_stack_text_bytes (&istack
);
10162 if (from_wide_insn
)
10165 while (istack
.insn
[first
].opcode
== XTENSA_UNDEFINED
)
10168 num_text_bytes
+= old_size
;
10169 if (opcode_fits_format_slot (istack
.insn
[first
].opcode
, fmt
, slot
))
10170 num_text_bytes
-= xg_get_single_size (istack
.insn
[first
].opcode
);
10173 /* The first instruction in the relaxed sequence will go after
10174 the current wide instruction, and thus its symbolic immediates
10177 istack_init (&istack
);
10178 num_steps
= xg_assembly_relax (&istack
, &tinsn
, segP
, fragP
,
10179 frag_offset
+ old_size
,
10180 min_steps
, stretch
+ old_size
);
10181 gas_assert (num_steps
>= min_steps
&& num_steps
<= RELAX_IMMED_MAXSTEPS
);
10183 fragP
->tc_frag_data
.slot_subtypes
[slot
]
10184 = (int) RELAX_IMMED
+ num_steps
;
10186 num_literal_bytes
= get_num_stack_literal_bytes (&istack
);
10188 = num_literal_bytes
- fragP
->tc_frag_data
.literal_expansion
[slot
];
10190 num_text_bytes
= get_num_stack_text_bytes (&istack
) + old_size
;
10194 total_text_diff
= num_text_bytes
- old_size
;
10195 this_text_diff
= total_text_diff
- fragP
->tc_frag_data
.text_expansion
[slot
];
10197 /* It MUST get larger. If not, we could get an infinite loop. */
10198 gas_assert (num_text_bytes
>= 0);
10199 gas_assert (literal_diff
>= 0);
10200 gas_assert (total_text_diff
>= 0);
10202 fragP
->tc_frag_data
.text_expansion
[slot
] = total_text_diff
;
10203 fragP
->tc_frag_data
.literal_expansion
[slot
] = num_literal_bytes
;
10204 gas_assert (fragP
->tc_frag_data
.text_expansion
[slot
] >= 0);
10205 gas_assert (fragP
->tc_frag_data
.literal_expansion
[slot
] >= 0);
10207 /* Find the associated expandable literal for this. */
10208 if (literal_diff
!= 0)
10210 fragS
*lit_fragP
= fragP
->tc_frag_data
.literal_frags
[slot
];
10213 gas_assert (literal_diff
== 4);
10214 lit_fragP
->tc_frag_data
.unreported_expansion
+= literal_diff
;
10216 /* We expect that the literal section state has NOT been
10218 gas_assert (lit_fragP
->fr_type
== rs_machine_dependent
10219 && lit_fragP
->fr_subtype
== RELAX_LITERAL
);
10220 lit_fragP
->fr_subtype
= RELAX_LITERAL_NR
;
10222 /* We need to mark this section for another iteration
10228 if (negatable_branch
&& istack
.ninsn
> 1)
10229 update_next_frag_state (fragP
);
10231 /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */
10232 if (istack
.ninsn
> 2 &&
10233 istack
.insn
[istack
.ninsn
- 1].insn_type
== ITYPE_LABEL
&&
10234 istack
.insn
[istack
.ninsn
- 2].insn_type
== ITYPE_INSN
&&
10235 istack
.insn
[istack
.ninsn
- 2].opcode
== xtensa_j_opcode
)
10237 TInsn
*jinsn
= &istack
.insn
[istack
.ninsn
- 2];
10239 if (!xg_symbolic_immeds_fit (jinsn
, segP
, fragP
, fragP
->fr_offset
, total_text_diff
))
10241 struct trampoline_frag
*tf
= get_best_trampoline (jinsn
, fragP
);
10245 this_text_diff
+= init_trampoline_frag (tf
);
10246 this_text_diff
+= add_jump_to_trampoline (tf
, fragP
);
10250 /* If target symbol is undefined, assume it will reach once linked. */
10251 expressionS
*exp
= &istack
.insn
[istack
.ninsn
- 2].tok
[0];
10253 if (exp
->X_op
== O_symbol
&& S_IS_DEFINED (exp
->X_add_symbol
))
10255 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10256 _("jump target out of range; no usable trampoline found"));
10262 return this_text_diff
;
10266 /* md_convert_frag Hook and Helper Functions. */
10268 static void convert_frag_align_next_opcode (fragS
*);
10269 static void convert_frag_narrow (segT
, fragS
*, xtensa_format
, int);
10270 static void convert_frag_fill_nop (fragS
*);
10271 static void convert_frag_immed (segT
, fragS
*, int, xtensa_format
, int);
10274 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec
, fragS
*fragp
)
10276 static xtensa_insnbuf vbuf
= NULL
;
10277 xtensa_isa isa
= xtensa_default_isa
;
10281 const char *file_name
;
10284 file_name
= as_where (&line
);
10285 new_logical_line (fragp
->fr_file
, fragp
->fr_line
);
10287 switch (fragp
->fr_subtype
)
10289 case RELAX_ALIGN_NEXT_OPCODE
:
10290 /* Always convert. */
10291 convert_frag_align_next_opcode (fragp
);
10294 case RELAX_DESIRE_ALIGN
:
10295 /* Do nothing. If not aligned already, too bad. */
10298 case RELAX_LITERAL
:
10299 case RELAX_LITERAL_FINAL
:
10304 vbuf
= xtensa_insnbuf_alloc (isa
);
10306 xtensa_insnbuf_from_chars
10307 (isa
, vbuf
, (unsigned char *) fragp
->fr_opcode
, 0);
10308 fmt
= xtensa_format_decode (isa
, vbuf
);
10309 num_slots
= xtensa_format_num_slots (isa
, fmt
);
10311 for (slot
= 0; slot
< num_slots
; slot
++)
10313 switch (fragp
->tc_frag_data
.slot_subtypes
[slot
])
10316 convert_frag_narrow (sec
, fragp
, fmt
, slot
);
10320 case RELAX_IMMED_STEP1
:
10321 case RELAX_IMMED_STEP2
:
10322 case RELAX_IMMED_STEP3
:
10323 /* Place the immediate. */
10326 fragp
->tc_frag_data
.slot_subtypes
[slot
] - RELAX_IMMED
,
10331 /* This is OK because some slots could have
10332 relaxations and others have none. */
10338 case RELAX_UNREACHABLE
:
10339 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, fragp
->fr_var
);
10340 fragp
->fr_fix
+= fragp
->tc_frag_data
.text_expansion
[0];
10341 fragp
->fr_var
-= fragp
->tc_frag_data
.text_expansion
[0];
10345 case RELAX_MAYBE_UNREACHABLE
:
10346 case RELAX_MAYBE_DESIRE_ALIGN
:
10350 case RELAX_FILL_NOP
:
10351 convert_frag_fill_nop (fragp
);
10354 case RELAX_LITERAL_NR
:
10355 if (use_literal_section
)
10357 /* This should have been handled during relaxation. When
10358 relaxing a code segment, literals sometimes need to be
10359 added to the corresponding literal segment. If that
10360 literal segment has already been relaxed, then we end up
10361 in this situation. Marking the literal segments as data
10362 would make this happen less often (since GAS always relaxes
10363 code before data), but we could still get into trouble if
10364 there are instructions in a segment that is not marked as
10365 containing code. Until we can implement a better solution,
10366 cheat and adjust the addresses of all the following frags.
10367 This could break subsequent alignments, but the linker's
10368 literal coalescing will do that anyway. */
10371 fragp
->fr_subtype
= RELAX_LITERAL_FINAL
;
10372 gas_assert (fragp
->tc_frag_data
.unreported_expansion
== 4);
10373 memset (&fragp
->fr_literal
[fragp
->fr_fix
], 0, 4);
10374 fragp
->fr_var
-= 4;
10375 fragp
->fr_fix
+= 4;
10376 for (f
= fragp
->fr_next
; f
; f
= f
->fr_next
)
10377 f
->fr_address
+= 4;
10380 as_bad (_("invalid relaxation fragment result"));
10383 case RELAX_TRAMPOLINE
:
10388 new_logical_line (file_name
, line
);
10393 convert_frag_align_next_opcode (fragS
*fragp
)
10395 char *nop_buf
; /* Location for Writing. */
10396 bfd_boolean use_no_density
= fragp
->tc_frag_data
.is_no_density
;
10397 addressT aligned_address
;
10399 int nop
, nop_count
;
10401 aligned_address
= get_noop_aligned_address (fragp
, fragp
->fr_address
+
10403 fill_size
= aligned_address
- (fragp
->fr_address
+ fragp
->fr_fix
);
10404 nop_count
= get_text_align_nop_count (fill_size
, use_no_density
);
10405 nop_buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
10407 for (nop
= 0; nop
< nop_count
; nop
++)
10410 nop_size
= get_text_align_nth_nop_size (fill_size
, nop
, use_no_density
);
10412 assemble_nop (nop_size
, nop_buf
);
10413 nop_buf
+= nop_size
;
10416 fragp
->fr_fix
+= fill_size
;
10417 fragp
->fr_var
-= fill_size
;
10422 convert_frag_narrow (segT segP
, fragS
*fragP
, xtensa_format fmt
, int slot
)
10424 TInsn tinsn
, single_target
;
10425 int size
, old_size
, diff
;
10426 offsetT frag_offset
;
10428 gas_assert (slot
== 0);
10429 tinsn_from_chars (&tinsn
, fragP
->fr_opcode
, 0);
10431 if (fragP
->tc_frag_data
.is_aligning_branch
== 1)
10433 gas_assert (fragP
->tc_frag_data
.text_expansion
[0] == 1
10434 || fragP
->tc_frag_data
.text_expansion
[0] == 0);
10435 convert_frag_immed (segP
, fragP
, fragP
->tc_frag_data
.text_expansion
[0],
10440 if (fragP
->tc_frag_data
.text_expansion
[0] == 0)
10442 /* No conversion. */
10447 gas_assert (fragP
->fr_opcode
!= NULL
);
10449 /* Frags in this relaxation state should only contain
10450 single instruction bundles. */
10451 tinsn_immed_from_frag (&tinsn
, fragP
, 0);
10453 /* Just convert it to a wide form.... */
10455 old_size
= xg_get_single_size (tinsn
.opcode
);
10457 tinsn_init (&single_target
);
10458 frag_offset
= fragP
->fr_opcode
- fragP
->fr_literal
;
10460 if (! xg_is_single_relaxable_insn (&tinsn
, &single_target
, FALSE
))
10462 as_bad (_("unable to widen instruction"));
10466 size
= xg_get_single_size (single_target
.opcode
);
10467 xg_emit_insn_to_buf (&single_target
, fragP
->fr_opcode
, fragP
,
10468 frag_offset
, TRUE
);
10470 diff
= size
- old_size
;
10471 gas_assert (diff
>= 0);
10472 gas_assert (diff
<= fragP
->fr_var
);
10473 fragP
->fr_var
-= diff
;
10474 fragP
->fr_fix
+= diff
;
10482 convert_frag_fill_nop (fragS
*fragP
)
10484 char *loc
= &fragP
->fr_literal
[fragP
->fr_fix
];
10485 int size
= fragP
->tc_frag_data
.text_expansion
[0];
10486 gas_assert ((unsigned) size
== (fragP
->fr_next
->fr_address
10487 - fragP
->fr_address
- fragP
->fr_fix
));
10490 /* No conversion. */
10494 assemble_nop (size
, loc
);
10495 fragP
->tc_frag_data
.is_insn
= TRUE
;
10496 fragP
->fr_var
-= size
;
10497 fragP
->fr_fix
+= size
;
10502 static fixS
*fix_new_exp_in_seg
10503 (segT
, subsegT
, fragS
*, int, int, expressionS
*, int,
10504 bfd_reloc_code_real_type
);
10505 static void convert_frag_immed_finish_loop (segT
, fragS
*, TInsn
*);
10508 convert_frag_immed (segT segP
,
10514 char *immed_instr
= fragP
->fr_opcode
;
10516 bfd_boolean expanded
= FALSE
;
10517 bfd_boolean branch_jmp_to_next
= FALSE
;
10518 char *fr_opcode
= fragP
->fr_opcode
;
10519 xtensa_isa isa
= xtensa_default_isa
;
10520 bfd_boolean from_wide_insn
= FALSE
;
10522 bfd_boolean is_loop
;
10524 gas_assert (fr_opcode
!= NULL
);
10526 xg_clear_vinsn (&cur_vinsn
);
10528 vinsn_from_chars (&cur_vinsn
, fr_opcode
);
10529 if (cur_vinsn
.num_slots
> 1)
10530 from_wide_insn
= TRUE
;
10532 orig_tinsn
= cur_vinsn
.slots
[slot
];
10533 tinsn_immed_from_frag (&orig_tinsn
, fragP
, slot
);
10535 is_loop
= xtensa_opcode_is_loop (xtensa_default_isa
, orig_tinsn
.opcode
) == 1;
10537 if (workaround_b_j_loop_end
&& ! fragP
->tc_frag_data
.is_no_transform
)
10538 branch_jmp_to_next
= is_branch_jmp_to_next (&orig_tinsn
, fragP
);
10540 if (branch_jmp_to_next
&& !next_frag_is_loop_target (fragP
))
10542 /* Conversion just inserts a NOP and marks the fix as completed. */
10543 bytes
= xtensa_format_length (isa
, fmt
);
10546 cur_vinsn
.slots
[slot
].opcode
=
10547 xtensa_format_slot_nop_opcode (isa
, cur_vinsn
.format
, slot
);
10548 cur_vinsn
.slots
[slot
].ntok
= 0;
10552 bytes
+= fragP
->tc_frag_data
.text_expansion
[0];
10553 gas_assert (bytes
== 2 || bytes
== 3);
10554 build_nop (&cur_vinsn
.slots
[0], bytes
);
10555 fragP
->fr_fix
+= fragP
->tc_frag_data
.text_expansion
[0];
10557 vinsn_to_insnbuf (&cur_vinsn
, fr_opcode
, frag_now
, TRUE
);
10558 xtensa_insnbuf_to_chars
10559 (isa
, cur_vinsn
.insnbuf
, (unsigned char *) fr_opcode
, 0);
10564 /* Here is the fun stuff: Get the immediate field from this
10565 instruction. If it fits, we're done. If not, find the next
10566 instruction sequence that fits. */
10570 symbolS
*lit_sym
= NULL
;
10571 int total_size
= 0;
10572 int target_offset
= 0;
10575 symbolS
*gen_label
= NULL
;
10576 offsetT frag_offset
;
10577 bfd_boolean first
= TRUE
;
10579 /* It does not fit. Find something that does and
10580 convert immediately. */
10581 frag_offset
= fr_opcode
- fragP
->fr_literal
;
10582 istack_init (&istack
);
10583 xg_assembly_relax (&istack
, &orig_tinsn
,
10584 segP
, fragP
, frag_offset
, min_steps
, 0);
10586 old_size
= xtensa_format_length (isa
, fmt
);
10588 /* Assemble this right inline. */
10590 /* First, create the mapping from a label name to the REAL label. */
10592 for (i
= 0; i
< istack
.ninsn
; i
++)
10594 TInsn
*tinsn
= &istack
.insn
[i
];
10597 switch (tinsn
->insn_type
)
10599 case ITYPE_LITERAL
:
10600 if (lit_sym
!= NULL
)
10601 as_bad (_("multiple literals in expansion"));
10602 /* First find the appropriate space in the literal pool. */
10603 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10604 if (lit_frag
== NULL
)
10605 as_bad (_("no registered fragment for literal"));
10606 if (tinsn
->ntok
!= 1)
10607 as_bad (_("number of literal tokens != 1"));
10609 /* Set the literal symbol and add a fixup. */
10610 lit_sym
= lit_frag
->fr_symbol
;
10614 if (align_targets
&& !is_loop
)
10616 fragS
*unreach
= fragP
->fr_next
;
10617 while (!(unreach
->fr_type
== rs_machine_dependent
10618 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10619 || unreach
->fr_subtype
== RELAX_UNREACHABLE
)))
10621 unreach
= unreach
->fr_next
;
10624 gas_assert (unreach
->fr_type
== rs_machine_dependent
10625 && (unreach
->fr_subtype
== RELAX_MAYBE_UNREACHABLE
10626 || unreach
->fr_subtype
== RELAX_UNREACHABLE
));
10628 target_offset
+= unreach
->tc_frag_data
.text_expansion
[0];
10630 gas_assert (gen_label
== NULL
);
10631 gen_label
= symbol_new (FAKE_LABEL_NAME
, now_seg
,
10632 fr_opcode
- fragP
->fr_literal
10633 + target_offset
, fragP
);
10637 if (first
&& from_wide_insn
)
10639 target_offset
+= xtensa_format_length (isa
, fmt
);
10641 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10642 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10645 target_offset
+= xg_get_single_size (tinsn
->opcode
);
10652 for (i
= 0; i
< istack
.ninsn
; i
++)
10654 TInsn
*tinsn
= &istack
.insn
[i
];
10658 bfd_reloc_code_real_type reloc_type
;
10660 switch (tinsn
->insn_type
)
10662 case ITYPE_LITERAL
:
10663 lit_frag
= fragP
->tc_frag_data
.literal_frags
[slot
];
10664 /* Already checked. */
10665 gas_assert (lit_frag
!= NULL
);
10666 gas_assert (lit_sym
!= NULL
);
10667 gas_assert (tinsn
->ntok
== 1);
10669 target_seg
= S_GET_SEGMENT (lit_sym
);
10670 gas_assert (target_seg
);
10671 reloc_type
= map_operator_to_reloc (tinsn
->tok
[0].X_op
, TRUE
);
10672 fix_new_exp_in_seg (target_seg
, 0, lit_frag
, 0, 4,
10673 &tinsn
->tok
[0], FALSE
, reloc_type
);
10680 xg_resolve_labels (tinsn
, gen_label
);
10681 xg_resolve_literals (tinsn
, lit_sym
);
10682 if (from_wide_insn
&& first
)
10685 if (opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10687 cur_vinsn
.slots
[slot
] = *tinsn
;
10691 cur_vinsn
.slots
[slot
].opcode
=
10692 xtensa_format_slot_nop_opcode (isa
, fmt
, slot
);
10693 cur_vinsn
.slots
[slot
].ntok
= 0;
10695 vinsn_to_insnbuf (&cur_vinsn
, immed_instr
, fragP
, TRUE
);
10696 xtensa_insnbuf_to_chars (isa
, cur_vinsn
.insnbuf
,
10697 (unsigned char *) immed_instr
, 0);
10698 fragP
->tc_frag_data
.is_insn
= TRUE
;
10699 size
= xtensa_format_length (isa
, fmt
);
10700 if (!opcode_fits_format_slot (tinsn
->opcode
, fmt
, slot
))
10702 xg_emit_insn_to_buf
10703 (tinsn
, immed_instr
+ size
, fragP
,
10704 immed_instr
- fragP
->fr_literal
+ size
, TRUE
);
10705 size
+= xg_get_single_size (tinsn
->opcode
);
10710 size
= xg_get_single_size (tinsn
->opcode
);
10711 xg_emit_insn_to_buf (tinsn
, immed_instr
, fragP
,
10712 immed_instr
- fragP
->fr_literal
, TRUE
);
10714 immed_instr
+= size
;
10715 total_size
+= size
;
10720 diff
= total_size
- old_size
;
10721 gas_assert (diff
>= 0);
10724 gas_assert (diff
<= fragP
->fr_var
);
10725 fragP
->fr_var
-= diff
;
10726 fragP
->fr_fix
+= diff
;
10729 /* Check for undefined immediates in LOOP instructions. */
10733 sym
= orig_tinsn
.tok
[1].X_add_symbol
;
10734 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10736 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10739 sym
= orig_tinsn
.tok
[1].X_op_symbol
;
10740 if (sym
!= NULL
&& !S_IS_DEFINED (sym
))
10742 as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym
));
10747 if (expanded
&& xtensa_opcode_is_loop (isa
, orig_tinsn
.opcode
) == 1)
10748 convert_frag_immed_finish_loop (segP
, fragP
, &orig_tinsn
);
10750 if (expanded
&& is_direct_call_opcode (orig_tinsn
.opcode
))
10752 /* Add an expansion note on the expanded instruction. */
10753 fix_new_exp_in_seg (now_seg
, 0, fragP
, fr_opcode
- fragP
->fr_literal
, 4,
10754 &orig_tinsn
.tok
[0], TRUE
,
10755 BFD_RELOC_XTENSA_ASM_EXPAND
);
10760 /* Add a new fix expression into the desired segment. We have to
10761 switch to that segment to do this. */
10764 fix_new_exp_in_seg (segT new_seg
,
10765 subsegT new_subseg
,
10771 bfd_reloc_code_real_type r_type
)
10774 segT seg
= now_seg
;
10775 subsegT subseg
= now_subseg
;
10777 gas_assert (new_seg
!= 0);
10778 subseg_set (new_seg
, new_subseg
);
10780 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pcrel
, r_type
);
10781 subseg_set (seg
, subseg
);
10786 /* Relax a loop instruction so that it can span loop >256 bytes.
10792 addi as, as, lo8 (label-.L1)
10793 addmi as, as, mid8 (label-.L1)
10804 convert_frag_immed_finish_loop (segT segP
, fragS
*fragP
, TInsn
*tinsn
)
10809 unsigned long target
;
10810 static xtensa_insnbuf insnbuf
= NULL
;
10811 unsigned int loop_length
, loop_length_hi
, loop_length_lo
;
10812 xtensa_isa isa
= xtensa_default_isa
;
10813 addressT loop_offset
;
10814 addressT addi_offset
= 9;
10815 addressT addmi_offset
= 12;
10820 insnbuf
= xtensa_insnbuf_alloc (isa
);
10822 /* Get the loop offset. */
10823 loop_offset
= get_expanded_loop_offset (tinsn
->opcode
);
10825 /* Validate that there really is a LOOP at the loop_offset. Because
10826 loops are not bundleable, we can assume that the instruction will be
10828 tinsn_from_chars (&loop_insn
, fragP
->fr_opcode
+ loop_offset
, 0);
10829 tinsn_immed_from_frag (&loop_insn
, fragP
, 0);
10831 gas_assert (xtensa_opcode_is_loop (isa
, loop_insn
.opcode
) == 1);
10832 addi_offset
+= loop_offset
;
10833 addmi_offset
+= loop_offset
;
10835 gas_assert (tinsn
->ntok
== 2);
10836 if (tinsn
->tok
[1].X_op
== O_constant
)
10837 target
= tinsn
->tok
[1].X_add_number
;
10838 else if (tinsn
->tok
[1].X_op
== O_symbol
)
10840 /* Find the fragment. */
10841 symbolS
*sym
= tinsn
->tok
[1].X_add_symbol
;
10842 gas_assert (S_GET_SEGMENT (sym
) == segP
10843 || S_GET_SEGMENT (sym
) == absolute_section
);
10844 target
= (S_GET_VALUE (sym
) + tinsn
->tok
[1].X_add_number
);
10848 as_bad (_("invalid expression evaluation type %d"), tinsn
->tok
[1].X_op
);
10852 loop_length
= target
- (fragP
->fr_address
+ fragP
->fr_fix
);
10853 loop_length_hi
= loop_length
& ~0x0ff;
10854 loop_length_lo
= loop_length
& 0x0ff;
10855 if (loop_length_lo
>= 128)
10857 loop_length_lo
-= 256;
10858 loop_length_hi
+= 256;
10861 /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
10862 32512. If the loop is larger than that, then we just fail. */
10863 if (loop_length_hi
> 32512)
10864 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
10865 _("loop too long for LOOP instruction"));
10867 tinsn_from_chars (&addi_insn
, fragP
->fr_opcode
+ addi_offset
, 0);
10868 gas_assert (addi_insn
.opcode
== xtensa_addi_opcode
);
10870 tinsn_from_chars (&addmi_insn
, fragP
->fr_opcode
+ addmi_offset
, 0);
10871 gas_assert (addmi_insn
.opcode
== xtensa_addmi_opcode
);
10873 set_expr_const (&addi_insn
.tok
[2], loop_length_lo
);
10874 tinsn_to_insnbuf (&addi_insn
, insnbuf
);
10876 fragP
->tc_frag_data
.is_insn
= TRUE
;
10877 xtensa_insnbuf_to_chars
10878 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addi_offset
, 0);
10880 set_expr_const (&addmi_insn
.tok
[2], loop_length_hi
);
10881 tinsn_to_insnbuf (&addmi_insn
, insnbuf
);
10882 xtensa_insnbuf_to_chars
10883 (isa
, insnbuf
, (unsigned char *) fragP
->fr_opcode
+ addmi_offset
, 0);
10885 /* Walk through all of the frags from here to the loop end
10886 and mark them as no_transform to keep them from being modified
10887 by the linker. If we ever have a relocation for the
10888 addi/addmi of the difference of two symbols we can remove this. */
10891 for (next_fragP
= fragP
; next_fragP
!= NULL
;
10892 next_fragP
= next_fragP
->fr_next
)
10894 next_fragP
->tc_frag_data
.is_no_transform
= TRUE
;
10895 if (next_fragP
->tc_frag_data
.is_loop_target
)
10897 if (target_count
== 2)
10903 /* A map that keeps information on a per-subsegment basis. This is
10904 maintained during initial assembly, but is invalid once the
10905 subsegments are smashed together. I.E., it cannot be used during
10908 typedef struct subseg_map_struct
10916 float total_freq
; /* fall-through + branch target frequency */
10917 float target_freq
; /* branch target frequency alone */
10919 struct subseg_map_struct
*next
;
10923 static subseg_map
*sseg_map
= NULL
;
10925 static subseg_map
*
10926 get_subseg_info (segT seg
, subsegT subseg
)
10928 subseg_map
*subseg_e
;
10930 for (subseg_e
= sseg_map
; subseg_e
; subseg_e
= subseg_e
->next
)
10932 if (seg
== subseg_e
->seg
&& subseg
== subseg_e
->subseg
)
10939 static subseg_map
*
10940 add_subseg_info (segT seg
, subsegT subseg
)
10942 subseg_map
*subseg_e
= XNEW (subseg_map
);
10943 memset (subseg_e
, 0, sizeof (subseg_map
));
10944 subseg_e
->seg
= seg
;
10945 subseg_e
->subseg
= subseg
;
10946 subseg_e
->flags
= 0;
10947 /* Start off considering every branch target very important. */
10948 subseg_e
->target_freq
= 1.0;
10949 subseg_e
->total_freq
= 1.0;
10950 subseg_e
->next
= sseg_map
;
10951 sseg_map
= subseg_e
;
10957 get_last_insn_flags (segT seg
, subsegT subseg
)
10959 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10961 return subseg_e
->flags
;
10967 set_last_insn_flags (segT seg
,
10972 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10974 subseg_e
= add_subseg_info (seg
, subseg
);
10976 subseg_e
->flags
|= fl
;
10978 subseg_e
->flags
&= ~fl
;
10983 get_subseg_total_freq (segT seg
, subsegT subseg
)
10985 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10987 return subseg_e
->total_freq
;
10993 get_subseg_target_freq (segT seg
, subsegT subseg
)
10995 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
10997 return subseg_e
->target_freq
;
11003 set_subseg_freq (segT seg
, subsegT subseg
, float total_f
, float target_f
)
11005 subseg_map
*subseg_e
= get_subseg_info (seg
, subseg
);
11007 subseg_e
= add_subseg_info (seg
, subseg
);
11008 subseg_e
->total_freq
= total_f
;
11009 subseg_e
->target_freq
= target_f
;
11013 /* Segment Lists and emit_state Stuff. */
11016 xtensa_move_seg_list_to_beginning (seg_list
*head
)
11021 segT literal_section
= head
->seg
;
11023 /* Move the literal section to the front of the section list. */
11024 gas_assert (literal_section
);
11025 if (literal_section
!= stdoutput
->sections
)
11027 bfd_section_list_remove (stdoutput
, literal_section
);
11028 bfd_section_list_prepend (stdoutput
, literal_section
);
11035 static void mark_literal_frags (seg_list
*);
11038 xtensa_move_literals (void)
11041 frchainS
*frchain_from
, *frchain_to
;
11042 fragS
*search_frag
, *next_frag
, *literal_pool
, *insert_after
;
11043 fragS
**frag_splice
;
11046 fixS
*fix
, *next_fix
, **fix_splice
;
11048 struct litpool_seg
*lps
;
11049 const char *init_name
= INIT_SECTION_NAME
;
11050 const char *fini_name
= FINI_SECTION_NAME
;
11051 int init_name_len
= strlen(init_name
);
11052 int fini_name_len
= strlen(fini_name
);
11054 mark_literal_frags (literal_head
->next
);
11056 if (use_literal_section
)
11059 /* Assign addresses (rough estimates) to the potential literal pool locations
11060 and create new ones if the gaps are too large. */
11062 for (lps
= litpool_seg_list
.next
; lps
; lps
= lps
->next
)
11064 frchainS
*frchP
= seg_info (lps
->seg
)->frchainP
;
11065 struct litpool_frag
*lpf
= lps
->frag_list
.next
;
11068 for ( ; frchP
; frchP
= frchP
->frch_next
)
11071 for (fragP
= frchP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11073 if (lpf
&& fragP
== lpf
->fragP
)
11075 gas_assert(fragP
->fr_type
== rs_machine_dependent
&&
11076 (fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
||
11077 fragP
->fr_subtype
== RELAX_LITERAL_POOL_CANDIDATE_BEGIN
));
11078 /* Found a litpool location. */
11082 if (fragP
->fr_type
== rs_machine_dependent
&&
11083 fragP
->fr_subtype
== RELAX_SLOTS
)
11086 for (slot
= 0; slot
< MAX_SLOTS
; slot
++)
11088 if (fragP
->tc_frag_data
.literal_frags
[slot
])
11090 /* L32R; point its literal to the nearest litpool
11091 preferring non-"candidate" positions to avoid
11092 the jump-around. */
11093 fragS
*litfrag
= fragP
->tc_frag_data
.literal_frags
[slot
];
11094 struct litpool_frag
*lp
= lpf
->prev
;
11099 while (lp
->fragP
->fr_subtype
==
11100 RELAX_LITERAL_POOL_CANDIDATE_BEGIN
)
11103 if (lp
->fragP
== NULL
)
11105 /* End of list; have to bite the bullet.
11106 Take the nearest. */
11110 /* Does it (conservatively) reach? */
11111 if (addr
- lp
->addr
<= 128 * 1024)
11113 if (lp
->fragP
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
)
11115 /* Found a good one. */
11118 else if (lp
->prev
->fragP
&&
11119 addr
- lp
->prev
->addr
> 128 * 1024)
11121 /* This is still a "candidate" but the next one
11122 will be too far away, so revert to the nearest
11123 one, convert it and add the jump around. */
11127 char label
[10 + 2 * sizeof (fragS
*)];
11129 poolbeg
= lp
->fragP
;
11131 poolbeg
->fr_subtype
= RELAX_LITERAL_POOL_BEGIN
;
11132 poolend
= poolbeg
->fr_next
;
11133 gas_assert (poolend
->fr_type
== rs_machine_dependent
&&
11134 poolend
->fr_subtype
== RELAX_LITERAL_POOL_END
);
11135 /* Create a local symbol pointing to the
11136 end of the pool. */
11137 sprintf (label
, ".L0_LT_%p", poolbeg
);
11138 lsym
= (symbolS
*)local_symbol_make (label
, lps
->seg
,
11140 poolbeg
->fr_symbol
= lsym
;
11141 /* Rest is done in xtensa_relax_frag. */
11145 if (! litfrag
->tc_frag_data
.literal_frag
)
11147 /* Take earliest use of this literal to avoid
11149 litfrag
->tc_frag_data
.literal_frag
= lp
->fragP
;
11154 addr
+= fragP
->fr_fix
;
11155 if (fragP
->fr_type
== rs_fill
)
11156 addr
+= fragP
->fr_offset
;
11161 for (segment
= literal_head
->next
; segment
; segment
= segment
->next
)
11163 const char *seg_name
= segment_name (segment
->seg
);
11165 /* Keep the literals for .init and .fini in separate sections. */
11166 if ((!memcmp (seg_name
, init_name
, init_name_len
) &&
11167 !strcmp (seg_name
+ init_name_len
, ".literal")) ||
11168 (!memcmp (seg_name
, fini_name
, fini_name_len
) &&
11169 !strcmp (seg_name
+ fini_name_len
, ".literal")))
11172 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11173 search_frag
= frchain_from
->frch_root
;
11174 literal_pool
= NULL
;
11176 frag_splice
= &(frchain_from
->frch_root
);
11178 while (search_frag
&& !search_frag
->tc_frag_data
.literal_frag
)
11180 gas_assert (search_frag
->fr_fix
== 0
11181 || search_frag
->fr_type
== rs_align
);
11182 search_frag
= search_frag
->fr_next
;
11187 search_frag
= frchain_from
->frch_root
;
11188 as_bad_where (search_frag
->fr_file
, search_frag
->fr_line
,
11189 _("literal pool location required for text-section-literals; specify with .literal_position"));
11193 gas_assert (search_frag
->tc_frag_data
.literal_frag
->fr_subtype
11194 == RELAX_LITERAL_POOL_BEGIN
);
11195 xtensa_switch_section_emit_state (&state
, segment
->seg
, 0);
11197 /* Make sure that all the frags in this series are closed, and
11198 that there is at least one left over of zero-size. This
11199 prevents us from making a segment with an frchain without any
11201 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11202 xtensa_set_frag_assembly_state (frag_now
);
11203 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11204 xtensa_set_frag_assembly_state (frag_now
);
11206 while (search_frag
!= frag_now
)
11208 next_frag
= search_frag
->fr_next
;
11209 if (search_frag
->tc_frag_data
.literal_frag
)
11211 literal_pool
= search_frag
->tc_frag_data
.literal_frag
;
11212 gas_assert (literal_pool
->fr_subtype
== RELAX_LITERAL_POOL_BEGIN
);
11213 frchain_to
= literal_pool
->tc_frag_data
.lit_frchain
;
11214 gas_assert (frchain_to
);
11217 if (search_frag
->fr_type
== rs_fill
&& search_frag
->fr_fix
== 0)
11219 /* Skip empty fill frags. */
11220 *frag_splice
= next_frag
;
11221 search_frag
= next_frag
;
11225 if (search_frag
->fr_type
== rs_align
)
11227 /* Skip alignment frags, because the pool as a whole will be
11228 aligned if used, and we don't want to force alignment if the
11230 *frag_splice
= next_frag
;
11231 search_frag
= next_frag
;
11235 /* First, move the frag out of the literal section and
11236 to the appropriate place. */
11238 /* Insert an aligmnent frag at start of pool. */
11239 if (literal_pool
->fr_next
->fr_type
== rs_machine_dependent
&&
11240 literal_pool
->fr_next
->fr_subtype
== RELAX_LITERAL_POOL_END
)
11242 segT pool_seg
= literal_pool
->fr_next
->tc_frag_data
.lit_seg
;
11243 emit_state prev_state
;
11246 xtensa_switch_section_emit_state (&prev_state
, pool_seg
, 0);
11247 prev_frag
= frag_now
;
11248 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11249 align_frag
= frag_now
;
11250 frag_align (2, 0, 0);
11251 /* Splice it into the right place. */
11252 prev_frag
->fr_next
= align_frag
->fr_next
;
11253 align_frag
->fr_next
= literal_pool
->fr_next
;
11254 literal_pool
->fr_next
= align_frag
;
11255 /* Insert after this one. */
11256 literal_pool
->tc_frag_data
.literal_frag
= align_frag
;
11257 xtensa_restore_emit_state (&prev_state
);
11259 insert_after
= literal_pool
->tc_frag_data
.literal_frag
;
11260 dest_seg
= insert_after
->fr_next
->tc_frag_data
.lit_seg
;
11261 /* Skip align frag. */
11262 if (insert_after
->fr_next
->fr_type
== rs_align
)
11264 insert_after
= insert_after
->fr_next
;
11267 *frag_splice
= next_frag
;
11268 search_frag
->fr_next
= insert_after
->fr_next
;
11269 insert_after
->fr_next
= search_frag
;
11270 search_frag
->tc_frag_data
.lit_seg
= dest_seg
;
11271 literal_pool
->tc_frag_data
.literal_frag
= search_frag
;
11273 /* Now move any fixups associated with this frag to the
11275 fix
= frchain_from
->fix_root
;
11276 fix_splice
= &(frchain_from
->fix_root
);
11279 next_fix
= fix
->fx_next
;
11280 if (fix
->fx_frag
== search_frag
)
11282 *fix_splice
= next_fix
;
11283 fix
->fx_next
= frchain_to
->fix_root
;
11284 frchain_to
->fix_root
= fix
;
11285 if (frchain_to
->fix_tail
== NULL
)
11286 frchain_to
->fix_tail
= fix
;
11289 fix_splice
= &(fix
->fx_next
);
11292 search_frag
= next_frag
;
11295 if (frchain_from
->fix_root
!= NULL
)
11297 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11298 as_warn (_("fixes not all moved from %s"), segment
->seg
->name
);
11300 gas_assert (frchain_from
->fix_root
== NULL
);
11302 frchain_from
->fix_tail
= NULL
;
11303 xtensa_restore_emit_state (&state
);
11306 /* Now fix up the SEGMENT value for all the literal symbols. */
11307 for (lit
= literal_syms
; lit
; lit
= lit
->next
)
11309 symbolS
*lit_sym
= lit
->sym
;
11310 segT dseg
= symbol_get_frag (lit_sym
)->tc_frag_data
.lit_seg
;
11312 S_SET_SEGMENT (lit_sym
, dseg
);
11317 /* Walk over all the frags for segments in a list and mark them as
11318 containing literals. As clunky as this is, we can't rely on frag_var
11319 and frag_variant to get called in all situations. */
11322 mark_literal_frags (seg_list
*segment
)
11324 frchainS
*frchain_from
;
11325 fragS
*search_frag
;
11329 frchain_from
= seg_info (segment
->seg
)->frchainP
;
11330 search_frag
= frchain_from
->frch_root
;
11331 while (search_frag
)
11333 search_frag
->tc_frag_data
.is_literal
= TRUE
;
11334 search_frag
= search_frag
->fr_next
;
11336 segment
= segment
->next
;
11342 xtensa_reorder_seg_list (seg_list
*head
, segT after
)
11344 /* Move all of the sections in the section list to come
11345 after "after" in the gnu segment list. */
11350 segT literal_section
= head
->seg
;
11352 /* Move the literal section after "after". */
11353 gas_assert (literal_section
);
11354 if (literal_section
!= after
)
11356 bfd_section_list_remove (stdoutput
, literal_section
);
11357 bfd_section_list_insert_after (stdoutput
, after
, literal_section
);
11365 /* Push all the literal segments to the end of the gnu list. */
11368 xtensa_reorder_segments (void)
11375 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11381 /* Now that we have the last section, push all the literal
11382 sections to the end. */
11383 xtensa_reorder_seg_list (literal_head
, last_sec
);
11385 /* Now perform the final error check. */
11386 for (sec
= stdoutput
->sections
; sec
!= NULL
; sec
= sec
->next
)
11388 gas_assert (new_count
== old_count
);
11392 /* Change the emit state (seg, subseg, and frag related stuff) to the
11393 correct location. Return a emit_state which can be passed to
11394 xtensa_restore_emit_state to return to current fragment. */
11397 xtensa_switch_to_literal_fragment (emit_state
*result
)
11399 if (directive_state
[directive_absolute_literals
])
11401 segT lit4_seg
= cache_literal_section (TRUE
);
11402 xtensa_switch_section_emit_state (result
, lit4_seg
, 0);
11405 xtensa_switch_to_non_abs_literal_fragment (result
);
11407 /* Do a 4-byte align here. */
11408 frag_align (2, 0, 0);
11409 record_alignment (now_seg
, 2);
11414 xtensa_switch_to_non_abs_literal_fragment (emit_state
*result
)
11416 static bfd_boolean recursive
= FALSE
;
11417 fragS
*pool_location
= get_literal_pool_location (now_seg
);
11419 bfd_boolean is_init
=
11420 (now_seg
&& !strcmp (segment_name (now_seg
), INIT_SECTION_NAME
));
11421 bfd_boolean is_fini
=
11422 (now_seg
&& !strcmp (segment_name (now_seg
), FINI_SECTION_NAME
));
11424 if (pool_location
== NULL
11425 && !use_literal_section
11427 && !is_init
&& ! is_fini
)
11429 if (!auto_litpools
)
11431 as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
11434 /* When we mark a literal pool location, we want to put a frag in
11435 the literal pool that points to it. But to do that, we want to
11436 switch_to_literal_fragment. But literal sections don't have
11437 literal pools, so their location is always null, so we would
11438 recurse forever. This is kind of hacky, but it works. */
11441 xtensa_mark_literal_pool_location ();
11445 lit_seg
= cache_literal_section (FALSE
);
11446 xtensa_switch_section_emit_state (result
, lit_seg
, 0);
11448 if (!use_literal_section
11449 && !is_init
&& !is_fini
11450 && get_literal_pool_location (now_seg
) != pool_location
)
11452 /* Close whatever frag is there. */
11453 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11454 xtensa_set_frag_assembly_state (frag_now
);
11455 frag_now
->tc_frag_data
.literal_frag
= pool_location
;
11456 frag_variant (rs_fill
, 0, 0, 0, NULL
, 0, NULL
);
11457 xtensa_set_frag_assembly_state (frag_now
);
11462 /* Call this function before emitting data into the literal section.
11463 This is a helper function for xtensa_switch_to_literal_fragment.
11464 This is similar to a .section new_now_seg subseg. */
11467 xtensa_switch_section_emit_state (emit_state
*state
,
11469 subsegT new_now_subseg
)
11471 state
->name
= now_seg
->name
;
11472 state
->now_seg
= now_seg
;
11473 state
->now_subseg
= now_subseg
;
11474 state
->generating_literals
= generating_literals
;
11475 generating_literals
++;
11476 subseg_set (new_now_seg
, new_now_subseg
);
11480 /* Use to restore the emitting into the normal place. */
11483 xtensa_restore_emit_state (emit_state
*state
)
11485 generating_literals
= state
->generating_literals
;
11486 subseg_set (state
->now_seg
, state
->now_subseg
);
11490 /* Predicate function used to look up a section in a particular group. */
11493 match_section_group (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
, void *inf
)
11495 const char *gname
= inf
;
11496 const char *group_name
= elf_group_name (sec
);
11498 return (group_name
== gname
11499 || (group_name
!= NULL
11501 && strcmp (group_name
, gname
) == 0));
11505 /* Get the literal section to be used for the current text section.
11506 The result may be cached in the default_lit_sections structure. */
11509 cache_literal_section (bfd_boolean use_abs_literals
)
11511 const char *text_name
, *group_name
= 0;
11512 const char *base_name
, *suffix
;
11515 segT seg
, current_section
;
11516 int current_subsec
;
11517 bfd_boolean linkonce
= FALSE
;
11519 /* Save the current section/subsection. */
11520 current_section
= now_seg
;
11521 current_subsec
= now_subseg
;
11523 /* Clear the cached values if they are no longer valid. */
11524 if (now_seg
!= default_lit_sections
.current_text_seg
)
11526 default_lit_sections
.current_text_seg
= now_seg
;
11527 default_lit_sections
.lit_seg
= NULL
;
11528 default_lit_sections
.lit4_seg
= NULL
;
11531 /* Check if the literal section is already cached. */
11532 if (use_abs_literals
)
11533 pcached
= &default_lit_sections
.lit4_seg
;
11535 pcached
= &default_lit_sections
.lit_seg
;
11540 text_name
= default_lit_sections
.lit_prefix
;
11541 if (! text_name
|| ! *text_name
)
11543 text_name
= segment_name (current_section
);
11544 group_name
= elf_group_name (current_section
);
11545 linkonce
= (current_section
->flags
& SEC_LINK_ONCE
) != 0;
11548 base_name
= use_abs_literals
? ".lit4" : ".literal";
11551 name
= concat (base_name
, ".", group_name
, (char *) NULL
);
11553 else if (strncmp (text_name
, ".gnu.linkonce.", linkonce_len
) == 0)
11555 suffix
= strchr (text_name
+ linkonce_len
, '.');
11557 name
= concat (".gnu.linkonce", base_name
, suffix
? suffix
: "",
11563 /* If the section name begins or ends with ".text", then replace
11564 that portion instead of appending an additional suffix. */
11565 size_t len
= strlen (text_name
);
11567 && (strcmp (text_name
+ len
- 5, ".text") == 0
11568 || strncmp (text_name
, ".text", 5) == 0))
11571 name
= xmalloc (len
+ strlen (base_name
) + 1);
11572 if (strncmp (text_name
, ".text", 5) == 0)
11574 strcpy (name
, base_name
);
11575 strcat (name
, text_name
+ 5);
11579 strcpy (name
, text_name
);
11580 strcpy (name
+ len
, base_name
);
11584 /* Canonicalize section names to allow renaming literal sections.
11585 The group name, if any, came from the current text section and
11586 has already been canonicalized. */
11587 name
= tc_canonicalize_symbol_name (name
);
11589 seg
= bfd_get_section_by_name_if (stdoutput
, name
, match_section_group
,
11590 (void *) group_name
);
11595 seg
= subseg_force_new (name
, 0);
11597 if (! use_abs_literals
)
11599 /* Add the newly created literal segment to the list. */
11600 seg_list
*n
= XNEW (seg_list
);
11602 n
->next
= literal_head
->next
;
11603 literal_head
->next
= n
;
11606 flags
= (SEC_HAS_CONTENTS
| SEC_READONLY
| SEC_ALLOC
| SEC_LOAD
11607 | (linkonce
? (SEC_LINK_ONCE
| SEC_LINK_DUPLICATES_DISCARD
) : 0)
11608 | (use_abs_literals
? SEC_DATA
: SEC_CODE
));
11610 elf_group_name (seg
) = group_name
;
11612 bfd_set_section_flags (stdoutput
, seg
, flags
);
11613 bfd_set_section_alignment (stdoutput
, seg
, 2);
11617 subseg_set (current_section
, current_subsec
);
11622 /* Property Tables Stuff. */
11624 #define XTENSA_INSN_SEC_NAME ".xt.insn"
11625 #define XTENSA_LIT_SEC_NAME ".xt.lit"
11626 #define XTENSA_PROP_SEC_NAME ".xt.prop"
11628 typedef bfd_boolean (*frag_predicate
) (const fragS
*);
11629 typedef void (*frag_flags_fn
) (const fragS
*, frag_flags
*);
11631 static bfd_boolean
get_frag_is_literal (const fragS
*);
11632 static void xtensa_create_property_segments
11633 (frag_predicate
, frag_predicate
, const char *, xt_section_type
);
11634 static void xtensa_create_xproperty_segments
11635 (frag_flags_fn
, const char *, xt_section_type
);
11636 static bfd_boolean
exclude_section_from_property_tables (segT
);
11637 static bfd_boolean
section_has_property (segT
, frag_predicate
);
11638 static bfd_boolean
section_has_xproperty (segT
, frag_flags_fn
);
11639 static void add_xt_block_frags
11640 (segT
, xtensa_block_info
**, frag_predicate
, frag_predicate
);
11641 static bfd_boolean
xtensa_frag_flags_is_empty (const frag_flags
*);
11642 static void xtensa_frag_flags_init (frag_flags
*);
11643 static void get_frag_property_flags (const fragS
*, frag_flags
*);
11644 static flagword
frag_flags_to_number (const frag_flags
*);
11645 static void add_xt_prop_frags (segT
, xtensa_block_info
**, frag_flags_fn
);
11647 /* Set up property tables after relaxation. */
11650 xtensa_post_relax_hook (void)
11652 xtensa_move_seg_list_to_beginning (literal_head
);
11654 xtensa_find_unmarked_state_frags ();
11655 xtensa_mark_frags_for_org ();
11656 xtensa_mark_difference_of_two_symbols ();
11658 xtensa_create_property_segments (get_frag_is_literal
,
11660 XTENSA_LIT_SEC_NAME
,
11662 xtensa_create_xproperty_segments (get_frag_property_flags
,
11663 XTENSA_PROP_SEC_NAME
,
11666 if (warn_unaligned_branch_targets
)
11667 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_branch_targets
, 0);
11668 bfd_map_over_sections (stdoutput
, xtensa_find_unaligned_loops
, 0);
11672 /* This function is only meaningful after xtensa_move_literals. */
11675 get_frag_is_literal (const fragS
*fragP
)
11677 gas_assert (fragP
!= NULL
);
11678 return fragP
->tc_frag_data
.is_literal
;
11683 xtensa_create_property_segments (frag_predicate property_function
,
11684 frag_predicate end_property_function
,
11685 const char *section_name_base
,
11686 xt_section_type sec_type
)
11690 /* Walk over all of the current segments.
11691 Walk over each fragment
11692 For each non-empty fragment,
11693 Build a property record (append where possible). */
11695 for (seclist
= &stdoutput
->sections
;
11696 seclist
&& *seclist
;
11697 seclist
= &(*seclist
)->next
)
11699 segT sec
= *seclist
;
11701 if (exclude_section_from_property_tables (sec
))
11704 if (section_has_property (sec
, property_function
))
11706 segment_info_type
*xt_seg_info
;
11707 xtensa_block_info
**xt_blocks
;
11708 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11710 prop_sec
->output_section
= prop_sec
;
11711 subseg_set (prop_sec
, 0);
11712 xt_seg_info
= seg_info (prop_sec
);
11713 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11715 /* Walk over all of the frchains here and add new sections. */
11716 add_xt_block_frags (sec
, xt_blocks
, property_function
,
11717 end_property_function
);
11721 /* Now we fill them out.... */
11723 for (seclist
= &stdoutput
->sections
;
11724 seclist
&& *seclist
;
11725 seclist
= &(*seclist
)->next
)
11727 segment_info_type
*seginfo
;
11728 xtensa_block_info
*block
;
11729 segT sec
= *seclist
;
11731 seginfo
= seg_info (sec
);
11732 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11736 xtensa_block_info
*cur_block
;
11738 bfd_size_type rec_size
;
11740 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11743 rec_size
= num_recs
* 8;
11744 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11751 subseg_set (sec
, 0);
11752 frag_data
= frag_more (rec_size
);
11754 for (i
= 0; i
< num_recs
; i
++)
11758 /* Write the fixup. */
11759 gas_assert (cur_block
);
11760 fix
= fix_new (frag_now
, i
* 8, 4,
11761 section_symbol (cur_block
->sec
),
11763 FALSE
, BFD_RELOC_32
);
11764 fix
->fx_file
= "<internal>";
11767 /* Write the length. */
11768 md_number_to_chars (&frag_data
[4 + i
* 8],
11769 cur_block
->size
, 4);
11770 cur_block
= cur_block
->next
;
11772 frag_wane (frag_now
);
11774 frag_wane (frag_now
);
11782 xtensa_create_xproperty_segments (frag_flags_fn flag_fn
,
11783 const char *section_name_base
,
11784 xt_section_type sec_type
)
11788 /* Walk over all of the current segments.
11789 Walk over each fragment.
11790 For each fragment that has instructions,
11791 build an instruction record (append where possible). */
11793 for (seclist
= &stdoutput
->sections
;
11794 seclist
&& *seclist
;
11795 seclist
= &(*seclist
)->next
)
11797 segT sec
= *seclist
;
11799 if (exclude_section_from_property_tables (sec
))
11802 if (section_has_xproperty (sec
, flag_fn
))
11804 segment_info_type
*xt_seg_info
;
11805 xtensa_block_info
**xt_blocks
;
11806 segT prop_sec
= xtensa_make_property_section (sec
, section_name_base
);
11808 prop_sec
->output_section
= prop_sec
;
11809 subseg_set (prop_sec
, 0);
11810 xt_seg_info
= seg_info (prop_sec
);
11811 xt_blocks
= &xt_seg_info
->tc_segment_info_data
.blocks
[sec_type
];
11813 /* Walk over all of the frchains here and add new sections. */
11814 add_xt_prop_frags (sec
, xt_blocks
, flag_fn
);
11818 /* Now we fill them out.... */
11820 for (seclist
= &stdoutput
->sections
;
11821 seclist
&& *seclist
;
11822 seclist
= &(*seclist
)->next
)
11824 segment_info_type
*seginfo
;
11825 xtensa_block_info
*block
;
11826 segT sec
= *seclist
;
11828 seginfo
= seg_info (sec
);
11829 block
= seginfo
->tc_segment_info_data
.blocks
[sec_type
];
11833 xtensa_block_info
*cur_block
;
11835 bfd_size_type rec_size
;
11837 for (cur_block
= block
; cur_block
; cur_block
= cur_block
->next
)
11840 rec_size
= num_recs
* (8 + 4);
11841 bfd_set_section_size (stdoutput
, sec
, rec_size
);
11842 /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
11849 subseg_set (sec
, 0);
11850 frag_data
= frag_more (rec_size
);
11852 for (i
= 0; i
< num_recs
; i
++)
11856 /* Write the fixup. */
11857 gas_assert (cur_block
);
11858 fix
= fix_new (frag_now
, i
* 12, 4,
11859 section_symbol (cur_block
->sec
),
11861 FALSE
, BFD_RELOC_32
);
11862 fix
->fx_file
= "<internal>";
11865 /* Write the length. */
11866 md_number_to_chars (&frag_data
[4 + i
* 12],
11867 cur_block
->size
, 4);
11868 md_number_to_chars (&frag_data
[8 + i
* 12],
11869 frag_flags_to_number (&cur_block
->flags
),
11870 sizeof (flagword
));
11871 cur_block
= cur_block
->next
;
11873 frag_wane (frag_now
);
11875 frag_wane (frag_now
);
11883 exclude_section_from_property_tables (segT sec
)
11885 flagword flags
= bfd_get_section_flags (stdoutput
, sec
);
11887 /* Sections that don't contribute to the memory footprint are excluded. */
11888 if ((flags
& SEC_DEBUGGING
)
11889 || !(flags
& SEC_ALLOC
)
11890 || (flags
& SEC_MERGE
))
11893 /* Linker cie and fde optimizations mess up property entries for
11894 eh_frame sections, but there is nothing inside them relevant to
11895 property tables anyway. */
11896 if (strcmp (sec
->name
, ".eh_frame") == 0)
11904 section_has_property (segT sec
, frag_predicate property_function
)
11906 segment_info_type
*seginfo
= seg_info (sec
);
11909 if (seginfo
&& seginfo
->frchainP
)
11911 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11913 if (property_function (fragP
)
11914 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11923 section_has_xproperty (segT sec
, frag_flags_fn property_function
)
11925 segment_info_type
*seginfo
= seg_info (sec
);
11928 if (seginfo
&& seginfo
->frchainP
)
11930 for (fragP
= seginfo
->frchainP
->frch_root
; fragP
; fragP
= fragP
->fr_next
)
11932 frag_flags prop_flags
;
11933 property_function (fragP
, &prop_flags
);
11934 if (!xtensa_frag_flags_is_empty (&prop_flags
))
11942 /* Two types of block sections exist right now: literal and insns. */
11945 add_xt_block_frags (segT sec
,
11946 xtensa_block_info
**xt_block
,
11947 frag_predicate property_function
,
11948 frag_predicate end_property_function
)
11952 /* Build it if needed. */
11953 while (*xt_block
!= NULL
)
11954 xt_block
= &(*xt_block
)->next
;
11955 /* We are either at NULL at the beginning or at the end. */
11957 /* Walk through the frags. */
11958 if (seg_info (sec
)->frchainP
)
11960 for (fragP
= seg_info (sec
)->frchainP
->frch_root
;
11962 fragP
= fragP
->fr_next
)
11964 if (property_function (fragP
)
11965 && (fragP
->fr_type
!= rs_fill
|| fragP
->fr_fix
!= 0))
11967 if (*xt_block
!= NULL
)
11969 if ((*xt_block
)->offset
+ (*xt_block
)->size
11970 == fragP
->fr_address
)
11971 (*xt_block
)->size
+= fragP
->fr_fix
;
11973 xt_block
= &((*xt_block
)->next
);
11975 if (*xt_block
== NULL
)
11977 xtensa_block_info
*new_block
= XNEW (xtensa_block_info
);
11978 new_block
->sec
= sec
;
11979 new_block
->offset
= fragP
->fr_address
;
11980 new_block
->size
= fragP
->fr_fix
;
11981 new_block
->next
= NULL
;
11982 xtensa_frag_flags_init (&new_block
->flags
);
11983 *xt_block
= new_block
;
11985 if (end_property_function
11986 && end_property_function (fragP
))
11988 xt_block
= &((*xt_block
)->next
);
11996 /* Break the encapsulation of add_xt_prop_frags here. */
11999 xtensa_frag_flags_is_empty (const frag_flags
*prop_flags
)
12001 if (prop_flags
->is_literal
12002 || prop_flags
->is_insn
12003 || prop_flags
->is_data
12004 || prop_flags
->is_unreachable
)
12011 xtensa_frag_flags_init (frag_flags
*prop_flags
)
12013 memset (prop_flags
, 0, sizeof (frag_flags
));
12018 get_frag_property_flags (const fragS
*fragP
, frag_flags
*prop_flags
)
12020 xtensa_frag_flags_init (prop_flags
);
12021 if (fragP
->tc_frag_data
.is_literal
)
12022 prop_flags
->is_literal
= TRUE
;
12023 if (fragP
->tc_frag_data
.is_specific_opcode
12024 || fragP
->tc_frag_data
.is_no_transform
)
12026 prop_flags
->is_no_transform
= TRUE
;
12027 if (xtensa_frag_flags_is_empty (prop_flags
))
12028 prop_flags
->is_data
= TRUE
;
12030 if (fragP
->tc_frag_data
.is_unreachable
)
12031 prop_flags
->is_unreachable
= TRUE
;
12032 else if (fragP
->tc_frag_data
.is_insn
)
12034 prop_flags
->is_insn
= TRUE
;
12035 if (fragP
->tc_frag_data
.is_loop_target
)
12036 prop_flags
->insn
.is_loop_target
= TRUE
;
12037 if (fragP
->tc_frag_data
.is_branch_target
)
12038 prop_flags
->insn
.is_branch_target
= TRUE
;
12039 if (fragP
->tc_frag_data
.is_no_density
)
12040 prop_flags
->insn
.is_no_density
= TRUE
;
12041 if (fragP
->tc_frag_data
.use_absolute_literals
)
12042 prop_flags
->insn
.is_abslit
= TRUE
;
12044 if (fragP
->tc_frag_data
.is_align
)
12046 prop_flags
->is_align
= TRUE
;
12047 prop_flags
->alignment
= fragP
->tc_frag_data
.alignment
;
12048 if (xtensa_frag_flags_is_empty (prop_flags
))
12049 prop_flags
->is_data
= TRUE
;
12055 frag_flags_to_number (const frag_flags
*prop_flags
)
12058 if (prop_flags
->is_literal
)
12059 num
|= XTENSA_PROP_LITERAL
;
12060 if (prop_flags
->is_insn
)
12061 num
|= XTENSA_PROP_INSN
;
12062 if (prop_flags
->is_data
)
12063 num
|= XTENSA_PROP_DATA
;
12064 if (prop_flags
->is_unreachable
)
12065 num
|= XTENSA_PROP_UNREACHABLE
;
12066 if (prop_flags
->insn
.is_loop_target
)
12067 num
|= XTENSA_PROP_INSN_LOOP_TARGET
;
12068 if (prop_flags
->insn
.is_branch_target
)
12070 num
|= XTENSA_PROP_INSN_BRANCH_TARGET
;
12071 num
= SET_XTENSA_PROP_BT_ALIGN (num
, prop_flags
->insn
.bt_align_priority
);
12074 if (prop_flags
->insn
.is_no_density
)
12075 num
|= XTENSA_PROP_INSN_NO_DENSITY
;
12076 if (prop_flags
->is_no_transform
)
12077 num
|= XTENSA_PROP_NO_TRANSFORM
;
12078 if (prop_flags
->insn
.is_no_reorder
)
12079 num
|= XTENSA_PROP_INSN_NO_REORDER
;
12080 if (prop_flags
->insn
.is_abslit
)
12081 num
|= XTENSA_PROP_INSN_ABSLIT
;
12083 if (prop_flags
->is_align
)
12085 num
|= XTENSA_PROP_ALIGN
;
12086 num
= SET_XTENSA_PROP_ALIGNMENT (num
, prop_flags
->alignment
);
12094 xtensa_frag_flags_combinable (const frag_flags
*prop_flags_1
,
12095 const frag_flags
*prop_flags_2
)
12097 /* Cannot combine with an end marker. */
12099 if (prop_flags_1
->is_literal
!= prop_flags_2
->is_literal
)
12101 if (prop_flags_1
->is_insn
!= prop_flags_2
->is_insn
)
12103 if (prop_flags_1
->is_data
!= prop_flags_2
->is_data
)
12106 if (prop_flags_1
->is_insn
)
12108 /* Properties of the beginning of the frag. */
12109 if (prop_flags_2
->insn
.is_loop_target
)
12111 if (prop_flags_2
->insn
.is_branch_target
)
12113 if (prop_flags_1
->insn
.is_no_density
!=
12114 prop_flags_2
->insn
.is_no_density
)
12116 if (prop_flags_1
->is_no_transform
!=
12117 prop_flags_2
->is_no_transform
)
12119 if (prop_flags_1
->insn
.is_no_reorder
!=
12120 prop_flags_2
->insn
.is_no_reorder
)
12122 if (prop_flags_1
->insn
.is_abslit
!=
12123 prop_flags_2
->insn
.is_abslit
)
12127 if (prop_flags_1
->is_align
)
12135 xt_block_aligned_size (const xtensa_block_info
*xt_block
)
12138 unsigned align_bits
;
12140 if (!xt_block
->flags
.is_align
)
12141 return xt_block
->size
;
12143 end_addr
= xt_block
->offset
+ xt_block
->size
;
12144 align_bits
= xt_block
->flags
.alignment
;
12145 end_addr
= ((end_addr
+ ((1 << align_bits
) -1)) >> align_bits
) << align_bits
;
12146 return end_addr
- xt_block
->offset
;
12151 xtensa_xt_block_combine (xtensa_block_info
*xt_block
,
12152 const xtensa_block_info
*xt_block_2
)
12154 if (xt_block
->sec
!= xt_block_2
->sec
)
12156 if (xt_block
->offset
+ xt_block_aligned_size (xt_block
)
12157 != xt_block_2
->offset
)
12160 if (xt_block_2
->size
== 0
12161 && (!xt_block_2
->flags
.is_unreachable
12162 || xt_block
->flags
.is_unreachable
))
12164 if (xt_block_2
->flags
.is_align
12165 && xt_block
->flags
.is_align
)
12167 /* Nothing needed. */
12168 if (xt_block
->flags
.alignment
>= xt_block_2
->flags
.alignment
)
12173 if (xt_block_2
->flags
.is_align
)
12175 /* Push alignment to previous entry. */
12176 xt_block
->flags
.is_align
= xt_block_2
->flags
.is_align
;
12177 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12182 if (!xtensa_frag_flags_combinable (&xt_block
->flags
,
12183 &xt_block_2
->flags
))
12186 xt_block
->size
+= xt_block_2
->size
;
12188 if (xt_block_2
->flags
.is_align
)
12190 xt_block
->flags
.is_align
= TRUE
;
12191 xt_block
->flags
.alignment
= xt_block_2
->flags
.alignment
;
12199 add_xt_prop_frags (segT sec
,
12200 xtensa_block_info
**xt_block
,
12201 frag_flags_fn property_function
)
12205 /* Build it if needed. */
12206 while (*xt_block
!= NULL
)
12208 xt_block
= &(*xt_block
)->next
;
12210 /* We are either at NULL at the beginning or at the end. */
12212 /* Walk through the frags. */
12213 if (seg_info (sec
)->frchainP
)
12215 for (fragP
= seg_info (sec
)->frchainP
->frch_root
; fragP
;
12216 fragP
= fragP
->fr_next
)
12218 xtensa_block_info tmp_block
;
12219 tmp_block
.sec
= sec
;
12220 tmp_block
.offset
= fragP
->fr_address
;
12221 tmp_block
.size
= fragP
->fr_fix
;
12222 tmp_block
.next
= NULL
;
12223 property_function (fragP
, &tmp_block
.flags
);
12225 if (!xtensa_frag_flags_is_empty (&tmp_block
.flags
))
12226 /* && fragP->fr_fix != 0) */
12228 if ((*xt_block
) == NULL
12229 || !xtensa_xt_block_combine (*xt_block
, &tmp_block
))
12231 xtensa_block_info
*new_block
;
12232 if ((*xt_block
) != NULL
)
12233 xt_block
= &(*xt_block
)->next
;
12234 new_block
= XNEW (xtensa_block_info
);
12235 *new_block
= tmp_block
;
12236 *xt_block
= new_block
;
12244 /* op_placement_info_table */
12246 /* op_placement_info makes it easier to determine which
12247 ops can go in which slots. */
12250 init_op_placement_info_table (void)
12252 xtensa_isa isa
= xtensa_default_isa
;
12253 xtensa_insnbuf ibuf
= xtensa_insnbuf_alloc (isa
);
12254 xtensa_opcode opcode
;
12257 int num_opcodes
= xtensa_isa_num_opcodes (isa
);
12259 op_placement_table
= XNEWVEC (op_placement_info
, num_opcodes
);
12260 gas_assert (xtensa_isa_num_formats (isa
) < MAX_FORMATS
);
12262 for (opcode
= 0; opcode
< num_opcodes
; opcode
++)
12264 op_placement_info
*opi
= &op_placement_table
[opcode
];
12265 /* FIXME: Make tinsn allocation dynamic. */
12266 if (xtensa_opcode_num_operands (isa
, opcode
) > MAX_INSN_ARGS
)
12267 as_fatal (_("too many operands in instruction"));
12268 opi
->narrowest
= XTENSA_UNDEFINED
;
12269 opi
->narrowest_size
= 0x7F;
12270 opi
->narrowest_slot
= 0;
12272 opi
->num_formats
= 0;
12274 for (fmt
= 0; fmt
< xtensa_isa_num_formats (isa
); fmt
++)
12276 opi
->slots
[fmt
] = 0;
12277 for (slot
= 0; slot
< xtensa_format_num_slots (isa
, fmt
); slot
++)
12279 if (xtensa_opcode_encode (isa
, fmt
, slot
, ibuf
, opcode
) == 0)
12281 int fmt_length
= xtensa_format_length (isa
, fmt
);
12283 set_bit (fmt
, opi
->formats
);
12284 set_bit (slot
, opi
->slots
[fmt
]);
12285 if (fmt_length
< opi
->narrowest_size
12286 || (fmt_length
== opi
->narrowest_size
12287 && (xtensa_format_num_slots (isa
, fmt
)
12288 < xtensa_format_num_slots (isa
,
12291 opi
->narrowest
= fmt
;
12292 opi
->narrowest_size
= fmt_length
;
12293 opi
->narrowest_slot
= slot
;
12298 opi
->num_formats
++;
12301 xtensa_insnbuf_free (isa
, ibuf
);
12306 opcode_fits_format_slot (xtensa_opcode opcode
, xtensa_format fmt
, int slot
)
12308 return bit_is_set (slot
, op_placement_table
[opcode
].slots
[fmt
]);
12312 /* If the opcode is available in a single slot format, return its size. */
12315 xg_get_single_size (xtensa_opcode opcode
)
12317 return op_placement_table
[opcode
].narrowest_size
;
12321 static xtensa_format
12322 xg_get_single_format (xtensa_opcode opcode
)
12324 return op_placement_table
[opcode
].narrowest
;
12329 xg_get_single_slot (xtensa_opcode opcode
)
12331 return op_placement_table
[opcode
].narrowest_slot
;
12335 /* Instruction Stack Functions (from "xtensa-istack.h"). */
12338 istack_init (IStack
*stack
)
12345 istack_empty (IStack
*stack
)
12347 return (stack
->ninsn
== 0);
12352 istack_full (IStack
*stack
)
12354 return (stack
->ninsn
== MAX_ISTACK
);
12358 /* Return a pointer to the top IStack entry.
12359 It is an error to call this if istack_empty () is TRUE. */
12362 istack_top (IStack
*stack
)
12364 int rec
= stack
->ninsn
- 1;
12365 gas_assert (!istack_empty (stack
));
12366 return &stack
->insn
[rec
];
12370 /* Add a new TInsn to an IStack.
12371 It is an error to call this if istack_full () is TRUE. */
12374 istack_push (IStack
*stack
, TInsn
*insn
)
12376 int rec
= stack
->ninsn
;
12377 gas_assert (!istack_full (stack
));
12378 stack
->insn
[rec
] = *insn
;
12383 /* Clear space for the next TInsn on the IStack and return a pointer
12384 to it. It is an error to call this if istack_full () is TRUE. */
12387 istack_push_space (IStack
*stack
)
12389 int rec
= stack
->ninsn
;
12391 gas_assert (!istack_full (stack
));
12392 insn
= &stack
->insn
[rec
];
12399 /* Remove the last pushed instruction. It is an error to call this if
12400 istack_empty () returns TRUE. */
12403 istack_pop (IStack
*stack
)
12405 int rec
= stack
->ninsn
- 1;
12406 gas_assert (!istack_empty (stack
));
12408 tinsn_init (&stack
->insn
[rec
]);
12412 /* TInsn functions. */
12415 tinsn_init (TInsn
*dst
)
12417 memset (dst
, 0, sizeof (TInsn
));
12421 /* Return TRUE if ANY of the operands in the insn are symbolic. */
12424 tinsn_has_symbolic_operands (const TInsn
*insn
)
12427 int n
= insn
->ntok
;
12429 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12431 for (i
= 0; i
< n
; ++i
)
12433 switch (insn
->tok
[i
].X_op
)
12447 tinsn_has_invalid_symbolic_operands (const TInsn
*insn
)
12449 xtensa_isa isa
= xtensa_default_isa
;
12451 int n
= insn
->ntok
;
12453 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12455 for (i
= 0; i
< n
; ++i
)
12457 switch (insn
->tok
[i
].X_op
)
12465 /* Errors for these types are caught later. */
12470 /* Symbolic immediates are only allowed on the last immediate
12471 operand. At this time, CONST16 is the only opcode where we
12472 support non-PC-relative relocations. */
12473 if (i
!= get_relaxable_immed (insn
->opcode
)
12474 || (xtensa_operand_is_PCrelative (isa
, insn
->opcode
, i
) != 1
12475 && insn
->opcode
!= xtensa_const16_opcode
))
12477 as_bad (_("invalid symbolic operand"));
12486 /* For assembly code with complex expressions (e.g. subtraction),
12487 we have to build them in the literal pool so that
12488 their results are calculated correctly after relaxation.
12489 The relaxation only handles expressions that
12490 boil down to SYMBOL + OFFSET. */
12493 tinsn_has_complex_operands (const TInsn
*insn
)
12496 int n
= insn
->ntok
;
12497 gas_assert (insn
->insn_type
== ITYPE_INSN
);
12498 for (i
= 0; i
< n
; ++i
)
12500 switch (insn
->tok
[i
].X_op
)
12516 /* Encode a TInsn opcode and its constant operands into slotbuf.
12517 Return TRUE if there is a symbol in the immediate field. This
12518 function assumes that:
12519 1) The number of operands are correct.
12520 2) The insn_type is ITYPE_INSN.
12521 3) The opcode can be encoded in the specified format and slot.
12522 4) Operands are either O_constant or O_symbol, and all constants fit. */
12525 tinsn_to_slotbuf (xtensa_format fmt
,
12528 xtensa_insnbuf slotbuf
)
12530 xtensa_isa isa
= xtensa_default_isa
;
12531 xtensa_opcode opcode
= tinsn
->opcode
;
12532 bfd_boolean has_fixup
= FALSE
;
12533 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12536 gas_assert (tinsn
->insn_type
== ITYPE_INSN
);
12537 if (noperands
!= tinsn
->ntok
)
12538 as_fatal (_("operand number mismatch"));
12540 if (xtensa_opcode_encode (isa
, fmt
, slot
, slotbuf
, opcode
))
12542 as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
12543 xtensa_opcode_name (isa
, opcode
), xtensa_format_name (isa
, fmt
));
12547 for (i
= 0; i
< noperands
; i
++)
12549 expressionS
*exp
= &tinsn
->tok
[i
];
12552 const char *file_name
;
12558 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12560 /* The register number has already been checked in
12561 expression_maybe_register, so we don't need to check here. */
12562 opnd_value
= exp
->X_add_number
;
12563 (void) xtensa_operand_encode (isa
, opcode
, i
, &opnd_value
);
12564 rc
= xtensa_operand_set_field (isa
, opcode
, i
, fmt
, slot
, slotbuf
,
12567 as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa
));
12571 if (xtensa_operand_is_visible (isa
, opcode
, i
) == 0)
12573 file_name
= as_where (&line
);
12574 /* It is a constant and we called this function
12575 then we have to try to fit it. */
12576 xtensa_insnbuf_set_operand (slotbuf
, fmt
, slot
, opcode
, i
,
12577 exp
->X_add_number
, file_name
, line
);
12590 /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded
12591 into a multi-slot instruction, fill the other slots with NOPs.
12592 Return TRUE if there is a symbol in the immediate field. See also the
12593 assumptions listed for tinsn_to_slotbuf. */
12596 tinsn_to_insnbuf (TInsn
*tinsn
, xtensa_insnbuf insnbuf
)
12598 static xtensa_insnbuf slotbuf
= 0;
12599 static vliw_insn vinsn
;
12600 xtensa_isa isa
= xtensa_default_isa
;
12601 bfd_boolean has_fixup
= FALSE
;
12606 slotbuf
= xtensa_insnbuf_alloc (isa
);
12607 xg_init_vinsn (&vinsn
);
12610 xg_clear_vinsn (&vinsn
);
12612 bundle_tinsn (tinsn
, &vinsn
);
12614 xtensa_format_encode (isa
, vinsn
.format
, insnbuf
);
12616 for (i
= 0; i
< vinsn
.num_slots
; i
++)
12618 /* Only one slot may have a fix-up because the rest contains NOPs. */
12620 tinsn_to_slotbuf (vinsn
.format
, i
, &vinsn
.slots
[i
], vinsn
.slotbuf
[i
]);
12621 xtensa_format_set_slot (isa
, vinsn
.format
, i
, insnbuf
, vinsn
.slotbuf
[i
]);
12628 /* Check the instruction arguments. Return TRUE on failure. */
12631 tinsn_check_arguments (const TInsn
*insn
)
12633 xtensa_isa isa
= xtensa_default_isa
;
12634 xtensa_opcode opcode
= insn
->opcode
;
12635 xtensa_regfile t1_regfile
, t2_regfile
;
12636 int t1_reg
, t2_reg
;
12637 int t1_base_reg
, t1_last_reg
;
12638 int t2_base_reg
, t2_last_reg
;
12639 char t1_inout
, t2_inout
;
12642 if (opcode
== XTENSA_UNDEFINED
)
12644 as_bad (_("invalid opcode"));
12648 if (xtensa_opcode_num_operands (isa
, opcode
) > insn
->ntok
)
12650 as_bad (_("too few operands"));
12654 if (xtensa_opcode_num_operands (isa
, opcode
) < insn
->ntok
)
12656 as_bad (_("too many operands"));
12660 /* Check registers. */
12661 for (j
= 0; j
< insn
->ntok
; j
++)
12663 if (xtensa_operand_is_register (isa
, insn
->opcode
, j
) != 1)
12666 t2_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, j
);
12667 t2_base_reg
= insn
->tok
[j
].X_add_number
;
12669 = t2_base_reg
+ xtensa_operand_num_regs (isa
, insn
->opcode
, j
);
12671 for (i
= 0; i
< insn
->ntok
; i
++)
12676 if (xtensa_operand_is_register (isa
, insn
->opcode
, i
) != 1)
12679 t1_regfile
= xtensa_operand_regfile (isa
, insn
->opcode
, i
);
12681 if (t1_regfile
!= t2_regfile
)
12684 t1_inout
= xtensa_operand_inout (isa
, insn
->opcode
, i
);
12685 t2_inout
= xtensa_operand_inout (isa
, insn
->opcode
, j
);
12687 t1_base_reg
= insn
->tok
[i
].X_add_number
;
12688 t1_last_reg
= (t1_base_reg
12689 + xtensa_operand_num_regs (isa
, insn
->opcode
, i
));
12691 for (t1_reg
= t1_base_reg
; t1_reg
< t1_last_reg
; t1_reg
++)
12693 for (t2_reg
= t2_base_reg
; t2_reg
< t2_last_reg
; t2_reg
++)
12695 if (t1_reg
!= t2_reg
)
12698 if (t1_inout
!= 'i' && t2_inout
!= 'i')
12700 as_bad (_("multiple writes to the same register"));
12711 /* Load an instruction from its encoded form. */
12714 tinsn_from_chars (TInsn
*tinsn
, char *f
, int slot
)
12718 xg_init_vinsn (&vinsn
);
12719 vinsn_from_chars (&vinsn
, f
);
12721 *tinsn
= vinsn
.slots
[slot
];
12722 xg_free_vinsn (&vinsn
);
12727 tinsn_from_insnbuf (TInsn
*tinsn
,
12728 xtensa_insnbuf slotbuf
,
12733 xtensa_isa isa
= xtensa_default_isa
;
12735 /* Find the immed. */
12736 tinsn_init (tinsn
);
12737 tinsn
->insn_type
= ITYPE_INSN
;
12738 tinsn
->is_specific_opcode
= FALSE
; /* must not be specific */
12739 tinsn
->opcode
= xtensa_opcode_decode (isa
, fmt
, slot
, slotbuf
);
12740 tinsn
->ntok
= xtensa_opcode_num_operands (isa
, tinsn
->opcode
);
12741 for (i
= 0; i
< tinsn
->ntok
; i
++)
12743 set_expr_const (&tinsn
->tok
[i
],
12744 xtensa_insnbuf_get_operand (slotbuf
, fmt
, slot
,
12745 tinsn
->opcode
, i
));
12750 /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */
12753 tinsn_immed_from_frag (TInsn
*tinsn
, fragS
*fragP
, int slot
)
12755 xtensa_opcode opcode
= tinsn
->opcode
;
12758 if (fragP
->tc_frag_data
.slot_symbols
[slot
])
12760 opnum
= get_relaxable_immed (opcode
);
12761 gas_assert (opnum
>= 0);
12762 set_expr_symbol_offset (&tinsn
->tok
[opnum
],
12763 fragP
->tc_frag_data
.slot_symbols
[slot
],
12764 fragP
->tc_frag_data
.slot_offsets
[slot
]);
12766 tinsn
->extra_arg
= fragP
->tc_frag_data
.free_reg
[slot
];
12771 get_num_stack_text_bytes (IStack
*istack
)
12774 int text_bytes
= 0;
12776 for (i
= 0; i
< istack
->ninsn
; i
++)
12778 TInsn
*tinsn
= &istack
->insn
[i
];
12779 if (tinsn
->insn_type
== ITYPE_INSN
)
12780 text_bytes
+= xg_get_single_size (tinsn
->opcode
);
12787 get_num_stack_literal_bytes (IStack
*istack
)
12792 for (i
= 0; i
< istack
->ninsn
; i
++)
12794 TInsn
*tinsn
= &istack
->insn
[i
];
12795 if (tinsn
->insn_type
== ITYPE_LITERAL
&& tinsn
->ntok
== 1)
12802 /* vliw_insn functions. */
12805 xg_init_vinsn (vliw_insn
*v
)
12808 xtensa_isa isa
= xtensa_default_isa
;
12810 xg_clear_vinsn (v
);
12812 v
->insnbuf
= xtensa_insnbuf_alloc (isa
);
12813 if (v
->insnbuf
== NULL
)
12814 as_fatal (_("out of memory"));
12816 for (i
= 0; i
< config_max_slots
; i
++)
12818 v
->slotbuf
[i
] = xtensa_insnbuf_alloc (isa
);
12819 if (v
->slotbuf
[i
] == NULL
)
12820 as_fatal (_("out of memory"));
12826 xg_clear_vinsn (vliw_insn
*v
)
12830 memset (v
, 0, offsetof (vliw_insn
, slots
)
12831 + sizeof(TInsn
) * config_max_slots
);
12833 v
->format
= XTENSA_UNDEFINED
;
12835 v
->inside_bundle
= FALSE
;
12837 if (xt_saved_debug_type
!= DEBUG_NONE
)
12838 debug_type
= xt_saved_debug_type
;
12840 for (i
= 0; i
< config_max_slots
; i
++)
12841 v
->slots
[i
].opcode
= XTENSA_UNDEFINED
;
12846 xg_copy_vinsn (vliw_insn
*dst
, vliw_insn
*src
)
12849 offsetof(vliw_insn
, slots
) + src
->num_slots
* sizeof(TInsn
));
12850 dst
->insnbuf
= src
->insnbuf
;
12851 memcpy (dst
->slotbuf
, src
->slotbuf
, src
->num_slots
* sizeof(xtensa_insnbuf
));
12856 vinsn_has_specific_opcodes (vliw_insn
*v
)
12860 for (i
= 0; i
< v
->num_slots
; i
++)
12862 if (v
->slots
[i
].is_specific_opcode
)
12870 xg_free_vinsn (vliw_insn
*v
)
12873 xtensa_insnbuf_free (xtensa_default_isa
, v
->insnbuf
);
12874 for (i
= 0; i
< config_max_slots
; i
++)
12875 xtensa_insnbuf_free (xtensa_default_isa
, v
->slotbuf
[i
]);
12879 /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic
12880 operands. See also the assumptions listed for tinsn_to_slotbuf. */
12883 vinsn_to_insnbuf (vliw_insn
*vinsn
,
12886 bfd_boolean record_fixup
)
12888 xtensa_isa isa
= xtensa_default_isa
;
12889 xtensa_format fmt
= vinsn
->format
;
12890 xtensa_insnbuf insnbuf
= vinsn
->insnbuf
;
12892 bfd_boolean has_fixup
= FALSE
;
12894 xtensa_format_encode (isa
, fmt
, insnbuf
);
12896 for (slot
= 0; slot
< vinsn
->num_slots
; slot
++)
12898 TInsn
*tinsn
= &vinsn
->slots
[slot
];
12899 expressionS
*extra_arg
= &tinsn
->extra_arg
;
12900 bfd_boolean tinsn_has_fixup
=
12901 tinsn_to_slotbuf (vinsn
->format
, slot
, tinsn
,
12902 vinsn
->slotbuf
[slot
]);
12904 xtensa_format_set_slot (isa
, fmt
, slot
,
12905 insnbuf
, vinsn
->slotbuf
[slot
]);
12906 if (extra_arg
->X_op
!= O_illegal
&& extra_arg
->X_op
!= O_register
)
12908 if (vinsn
->num_slots
!= 1)
12909 as_bad (_("TLS relocation not allowed in FLIX bundle"));
12910 else if (record_fixup
)
12911 /* Instructions that generate TLS relocations should always be
12912 relaxed in the front-end. If "record_fixup" is set, then this
12913 function is being called during back-end relaxation, so flag
12914 the unexpected behavior as an error. */
12915 as_bad (_("unexpected TLS relocation"));
12917 fix_new (fragP
, frag_offset
- fragP
->fr_literal
,
12918 xtensa_format_length (isa
, fmt
),
12919 extra_arg
->X_add_symbol
, extra_arg
->X_add_number
,
12920 FALSE
, map_operator_to_reloc (extra_arg
->X_op
, FALSE
));
12922 if (tinsn_has_fixup
)
12925 xtensa_opcode opcode
= tinsn
->opcode
;
12926 int noperands
= xtensa_opcode_num_operands (isa
, opcode
);
12929 for (i
= 0; i
< noperands
; i
++)
12931 expressionS
* exp
= &tinsn
->tok
[i
];
12937 if (get_relaxable_immed (opcode
) == i
)
12939 /* Add a fix record for the instruction, except if this
12940 function is being called prior to relaxation, i.e.,
12941 if record_fixup is false, and the instruction might
12942 be relaxed later. */
12944 || tinsn
->is_specific_opcode
12945 || !xg_is_relaxable_insn (tinsn
, 0))
12947 xg_add_opcode_fix (tinsn
, i
, fmt
, slot
, exp
, fragP
,
12948 frag_offset
- fragP
->fr_literal
);
12952 if (exp
->X_op
!= O_symbol
)
12953 as_bad (_("invalid operand"));
12954 tinsn
->symbol
= exp
->X_add_symbol
;
12955 tinsn
->offset
= exp
->X_add_number
;
12959 as_bad (_("symbolic operand not allowed"));
12967 as_bad (_("expression too complex"));
12979 vinsn_from_chars (vliw_insn
*vinsn
, char *f
)
12981 static xtensa_insnbuf insnbuf
= NULL
;
12982 static xtensa_insnbuf slotbuf
= NULL
;
12985 xtensa_isa isa
= xtensa_default_isa
;
12989 insnbuf
= xtensa_insnbuf_alloc (isa
);
12990 slotbuf
= xtensa_insnbuf_alloc (isa
);
12993 xtensa_insnbuf_from_chars (isa
, insnbuf
, (unsigned char *) f
, 0);
12994 fmt
= xtensa_format_decode (isa
, insnbuf
);
12995 if (fmt
== XTENSA_UNDEFINED
)
12996 as_fatal (_("cannot decode instruction format"));
12997 vinsn
->format
= fmt
;
12998 vinsn
->num_slots
= xtensa_format_num_slots (isa
, fmt
);
13000 for (i
= 0; i
< vinsn
->num_slots
; i
++)
13002 TInsn
*tinsn
= &vinsn
->slots
[i
];
13003 xtensa_format_get_slot (isa
, fmt
, i
, insnbuf
, slotbuf
);
13004 tinsn_from_insnbuf (tinsn
, slotbuf
, fmt
, i
);
13009 /* Expression utilities. */
13011 /* Return TRUE if the expression is an integer constant. */
13014 expr_is_const (const expressionS
*s
)
13016 return (s
->X_op
== O_constant
);
13020 /* Get the expression constant.
13021 Calling this is illegal if expr_is_const () returns TRUE. */
13024 get_expr_const (const expressionS
*s
)
13026 gas_assert (expr_is_const (s
));
13027 return s
->X_add_number
;
13031 /* Set the expression to a constant value. */
13034 set_expr_const (expressionS
*s
, offsetT val
)
13036 s
->X_op
= O_constant
;
13037 s
->X_add_number
= val
;
13038 s
->X_add_symbol
= NULL
;
13039 s
->X_op_symbol
= NULL
;
13044 expr_is_register (const expressionS
*s
)
13046 return (s
->X_op
== O_register
);
13050 /* Get the expression constant.
13051 Calling this is illegal if expr_is_const () returns TRUE. */
13054 get_expr_register (const expressionS
*s
)
13056 gas_assert (expr_is_register (s
));
13057 return s
->X_add_number
;
13061 /* Set the expression to a symbol + constant offset. */
13064 set_expr_symbol_offset (expressionS
*s
, symbolS
*sym
, offsetT offset
)
13066 s
->X_op
= O_symbol
;
13067 s
->X_add_symbol
= sym
;
13068 s
->X_op_symbol
= NULL
; /* unused */
13069 s
->X_add_number
= offset
;
13073 /* Return TRUE if the two expressions are equal. */
13076 expr_is_equal (expressionS
*s1
, expressionS
*s2
)
13078 if (s1
->X_op
!= s2
->X_op
)
13080 if (s1
->X_add_symbol
!= s2
->X_add_symbol
)
13082 if (s1
->X_op_symbol
!= s2
->X_op_symbol
)
13084 if (s1
->X_add_number
!= s2
->X_add_number
)
13091 copy_expr (expressionS
*dst
, const expressionS
*src
)
13093 memcpy (dst
, src
, sizeof (expressionS
));
13097 /* Support for the "--rename-section" option. */
13099 struct rename_section_struct
13101 const char *old_name
;
13103 struct rename_section_struct
*next
;
13106 static struct rename_section_struct
*section_rename
;
13109 /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
13110 entries to the section_rename list. Note: Specifying multiple
13111 renamings separated by colons is not documented and is retained only
13112 for backward compatibility. */
13115 build_section_rename (const char *arg
)
13117 struct rename_section_struct
*r
;
13118 char *this_arg
= NULL
;
13119 char *next_arg
= NULL
;
13121 for (this_arg
= xstrdup (arg
); this_arg
!= NULL
; this_arg
= next_arg
)
13123 char *old_name
, *new_name
;
13127 next_arg
= strchr (this_arg
, ':');
13135 old_name
= this_arg
;
13136 new_name
= strchr (this_arg
, '=');
13138 if (*old_name
== '\0')
13140 as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
13143 if (!new_name
|| new_name
[1] == '\0')
13145 as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
13152 /* Check for invalid section renaming. */
13153 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13155 if (strcmp (r
->old_name
, old_name
) == 0)
13156 as_bad (_("section %s renamed multiple times"), old_name
);
13157 if (strcmp (r
->new_name
, new_name
) == 0)
13158 as_bad (_("multiple sections remapped to output section %s"),
13163 r
= XNEW (struct rename_section_struct
);
13164 r
->old_name
= xstrdup (old_name
);
13165 r
->new_name
= xstrdup (new_name
);
13166 r
->next
= section_rename
;
13167 section_rename
= r
;
13173 xtensa_section_rename (const char *name
)
13175 struct rename_section_struct
*r
= section_rename
;
13177 for (r
= section_rename
; r
!= NULL
; r
= r
->next
)
13179 if (strcmp (r
->old_name
, name
) == 0)
13180 return r
->new_name
;
13183 return (char *) name
;